435 files changed, 349532 insertions, 989 deletions

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 3d730a772a2b..fbb76e523658 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -1,14 +1,15 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.35-rc2
-# Tue Jun  8 17:11:49 2010
+# Linux kernel version: 2.6.36.3
+# Mon Jan 24 15:36:52 2011
 #
 CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
 # CONFIG_ARCH_USES_GETTIMEOFFSET is not set
 CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
 CONFIG_HAVE_PROC_CPU=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
@@ -18,10 +19,15 @@ CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_GENERIC_LOCKBREAK=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_ARCH_HAS_DEFAULT_IDLE=y
+CONFIG_ARCH_HAS_CPUFREQ=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_FIQ=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_ARCH_PROVIDES_UDELAY=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 CONFIG_CONSTRUCTORS=y
@@ -32,17 +38,16 @@ CONFIG_CONSTRUCTORS=y
 CONFIG_EXPERIMENTAL=y
 CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_CROSS_COMPILE=""
+CONFIG_CROSS_COMPILE="arm-eabi-"
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_HAVE_KERNEL_GZIP=y
 CONFIG_HAVE_KERNEL_LZMA=y
 CONFIG_HAVE_KERNEL_LZO=y
 CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_BZIP2 is not set
 # CONFIG_KERNEL_LZMA is not set
 # CONFIG_KERNEL_LZO is not set
-CONFIG_SWAP=y
+# CONFIG_SWAP is not set
 # CONFIG_SYSVIPC is not set
 # CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
@@ -54,11 +59,10 @@ CONFIG_SWAP=y
 #
 CONFIG_TREE_RCU=y
 # CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_TINY_RCU is not set
 # CONFIG_RCU_TRACE is not set
 CONFIG_RCU_FANOUT=32
 # CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_RCU_FAST_NO_HZ is not set
+CONFIG_RCU_FAST_NO_HZ=y
 # CONFIG_TREE_RCU_TRACE is not set
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
@@ -88,6 +92,7 @@ CONFIG_RD_GZIP=y
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=10
 CONFIG_EMBEDDED=y
 CONFIG_UID16=y
 # CONFIG_SYSCTL_SYSCALL is not set
@@ -105,6 +110,7 @@ CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_ASHMEM=y
 CONFIG_AIO=y
 CONFIG_HAVE_PERF_EVENTS=y
 CONFIG_PERF_USE_VMALLOC=y
@@ -125,13 +131,13 @@ CONFIG_HAVE_OPROFILE=y
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
 CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
 CONFIG_HAVE_CLK=y
 
 #
 # GCOV-based kernel profiling
 #
 # CONFIG_GCOV_KERNEL is not set
-# CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
@@ -154,8 +160,6 @@ CONFIG_LBDAF=y
 CONFIG_IOSCHED_NOOP=y
 # CONFIG_IOSCHED_DEADLINE is not set
 # CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
 CONFIG_DEFAULT_NOOP=y
 CONFIG_DEFAULT_IOSCHED="noop"
 # CONFIG_INLINE_SPIN_TRYLOCK is not set
@@ -186,7 +190,7 @@ CONFIG_DEFAULT_IOSCHED="noop"
 # CONFIG_INLINE_WRITE_UNLOCK_BH is not set
 # CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
 # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
-# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
 CONFIG_FREEZER=y
 
 #
@@ -216,10 +220,10 @@ CONFIG_MMU=y
 # CONFIG_ARCH_IXP23XX is not set
 # CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_DOVE is not set
 # CONFIG_ARCH_KIRKWOOD is not set
 # CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_LPC32XX is not set
 # CONFIG_ARCH_MV78XX0 is not set
 # CONFIG_ARCH_ORION5X is not set
 # CONFIG_ARCH_MMP is not set
@@ -240,6 +244,7 @@ CONFIG_ARCH_TEGRA=y
 # CONFIG_ARCH_S5P6442 is not set
 # CONFIG_ARCH_S5PC100 is not set
 # CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_S5PV310 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
@@ -258,12 +263,25 @@ CONFIG_ARCH_TEGRA_2x_SOC=y
 # Tegra board type
 #
 CONFIG_MACH_HARMONY=y
+CONFIG_MACH_VENTANA=y
+# CONFIG_MACH_WHISTLER is not set
 # CONFIG_TEGRA_DEBUG_UART_NONE is not set
 # CONFIG_TEGRA_DEBUG_UARTA is not set
 # CONFIG_TEGRA_DEBUG_UARTB is not set
 # CONFIG_TEGRA_DEBUG_UARTC is not set
 CONFIG_TEGRA_DEBUG_UARTD=y
 # CONFIG_TEGRA_DEBUG_UARTE is not set
+CONFIG_TEGRA_SYSTEM_DMA=y
+CONFIG_TEGRA_PWM=y
+CONFIG_TEGRA_FIQ_DEBUGGER=y
+CONFIG_TEGRA_EMC_SCALING_ENABLE=y
+CONFIG_TEGRA_CPU_DVFS=y
+CONFIG_TEGRA_CORE_DVFS=y
+CONFIG_TEGRA_IOVMM_GART=y
+CONFIG_TEGRA_IOVMM=y
+CONFIG_TEGRA_ARB_SEMAPHORE=y
+CONFIG_TEGRA_THERMAL_THROTTLE=y
+# CONFIG_TEGRA_CLOCK_DEBUG_WRITE is not set
 
 #
 # Processor Type
@@ -289,10 +307,10 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_HAS_TLS_REG=y
 CONFIG_OUTER_CACHE=y
 CONFIG_OUTER_CACHE_SYNC=y
 CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
 CONFIG_ARM_L1_CACHE_SHIFT=5
 CONFIG_ARM_DMA_MEM_BUFFERABLE=y
 CONFIG_ARCH_HAS_BARRIERS=y
@@ -300,8 +318,17 @@ CONFIG_CPU_HAS_PMU=y
 # CONFIG_ARM_ERRATA_430973 is not set
 # CONFIG_ARM_ERRATA_458693 is not set
 # CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_ARM_ERRATA_742230=y
+# CONFIG_ARM_ERRATA_742231 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
 CONFIG_ARM_GIC=y
 CONFIG_COMMON_CLKDEV=y
+CONFIG_FIQ_GLUE=y
+CONFIG_FIQ_DEBUGGER=y
+# CONFIG_FIQ_DEBUGGER_NO_SLEEP is not set
+# CONFIG_FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON is not set
+# CONFIG_FIQ_DEBUGGER_CONSOLE is not set
 
 #
 # Bus support
@@ -337,12 +364,12 @@ CONFIG_AEABI=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
 CONFIG_HIGHMEM=y
+# CONFIG_SPARSE_IRQ is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4
 # CONFIG_PHYS_ADDR_T_64BIT is not set
@@ -351,8 +378,11 @@ CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
 # CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_FORCE_MAX_ZONEORDER=11
 CONFIG_ALIGNMENT_TRAP=y
 # CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
 
 #
 # Boot options
@@ -363,11 +393,31 @@ CONFIG_CMDLINE="mem=448M@0M console=ttyS0,115200n8 earlyprintk init=/bin/ash"
 # CONFIG_CMDLINE_FORCE is not set
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
+# CONFIG_AUTO_ZRELADDR is not set
 
 #
 # CPU Power Management
 #
-# CONFIG_CPU_IDLE is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
 
 #
 # Floating point emulation
@@ -395,10 +445,19 @@ CONFIG_PM=y
 # CONFIG_PM_DEBUG is not set
 CONFIG_PM_SLEEP_SMP=y
 CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_NVS=y
 CONFIG_SUSPEND=y
 CONFIG_SUSPEND_FREEZER=y
+CONFIG_HAS_WAKELOCK=y
+CONFIG_HAS_EARLYSUSPEND=y
+CONFIG_WAKELOCK=y
+CONFIG_WAKELOCK_STAT=y
+CONFIG_USER_WAKELOCK=y
+CONFIG_EARLYSUSPEND=y
+# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
+CONFIG_FB_EARLYSUSPEND=y
 # CONFIG_APM_EMULATION is not set
-# CONFIG_PM_RUNTIME is not set
+CONFIG_PM_RUNTIME=y
 CONFIG_PM_OPS=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_NET=y
@@ -461,8 +520,143 @@ CONFIG_IPV6_TUNNEL=y
 CONFIG_IPV6_MULTIPLE_TABLES=y
 # CONFIG_IPV6_SUBTREES is not set
 # CONFIG_IPV6_MROUTE is not set
+CONFIG_ANDROID_PARANOID_NETWORK=y
+CONFIG_NET_ACTIVITY_STATS=y
 # CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_CONNMARK=y
+
+#
+# Xtables targets
+#
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_HL=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_TARGET_TTL is not set
+# CONFIG_IP_NF_RAW is not set
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_NF_CONNTRACK_IPV6 is not set
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
 # CONFIG_RDS is not set
@@ -482,9 +676,62 @@ CONFIG_IPV6_MULTIPLE_TABLES=y
 # CONFIG_WAN_ROUTER is not set
 # CONFIG_PHONET is not set
 # CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+CONFIG_NET_SCH_HTB=y
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+CONFIG_NET_SCH_INGRESS=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+CONFIG_NET_CLS_U32=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+# CONFIG_NET_EMATCH_CMP is not set
+# CONFIG_NET_EMATCH_NBYTE is not set
+CONFIG_NET_EMATCH_U32=y
+# CONFIG_NET_EMATCH_META is not set
+# CONFIG_NET_EMATCH_TEXT is not set
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=y
+CONFIG_NET_ACT_GACT=y
+# CONFIG_GACT_PROB is not set
+CONFIG_NET_ACT_MIRRED=y
+# CONFIG_NET_ACT_IPT is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_SIMP is not set
+# CONFIG_NET_ACT_SKBEDIT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
 # CONFIG_DCB is not set
-CONFIG_RPS=y
+# CONFIG_RPS is not set
 
 #
 # Network testing
@@ -493,12 +740,53 @@ CONFIG_RPS=y
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_ATH3K is not set
+CONFIG_BT_HCIUART_LL=y
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
 # CONFIG_AF_RXRPC is not set
 CONFIG_FIB_RULES=y
-# CONFIG_WIRELESS is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+
+#
+# Some wireless drivers require a rate control algorithm
+#
 # CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_PM=y
+# CONFIG_RFKILL_INPUT is not set
 # CONFIG_NET_9P is not set
 # CONFIG_CAIF is not set
 
@@ -520,7 +808,96 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_DEBUG_DEVRES is not set
 # CONFIG_SYS_HYPERVISOR is not set
 # CONFIG_CONNECTOR is not set
-# CONFIG_MTD is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_NAND_TEGRA=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
@@ -531,19 +908,55 @@ CONFIG_BLK_DEV_LOOP=y
 # DRBD disabled because PROC_FS, INET or CONNECTOR not selected
 #
 # CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_MG_DISK is not set
 CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
 # CONFIG_ANDROID_PMEM is not set
+# CONFIG_ICS932S401 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_KERNEL_DEBUGGER_CORE=y
+# CONFIG_ISL29003 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_SENSORS_AK8975 is not set
+CONFIG_SENSORS_NCT1008=y
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_UID_STAT is not set
+# CONFIG_BMP085 is not set
+# CONFIG_WL127X_RFKILL is not set
+# CONFIG_APANIC is not set
+CONFIG_BCM4329_RFKILL=y
+CONFIG_TEGRA_CRYPTO_DEV=y
 # CONFIG_C2PORT is not set
 
 #
 # EEPROM support
 #
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
 # CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Motion Sensors Support
+#
+# CONFIG_MPU_NONE is not set
+CONFIG_SENSORS_MPU3050=y
+# CONFIG_SENSORS_MPU6000 is not set
+# CONFIG_SENSORS_ACCELEROMETER_NONE is not set
+CONFIG_SENSORS_KXTF9_MPU=y
+# CONFIG_SENSORS_COMPASS_NONE is not set
+CONFIG_SENSORS_AK8975_MPU=y
+CONFIG_SENSORS_PRESSURE_NONE=y
+# CONFIG_SENSORS_MPU_DEBUG is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
@@ -552,29 +965,152 @@ CONFIG_HAVE_IDE=y
 #
 CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
-# CONFIG_MD is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=y
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
 CONFIG_NETDEVICES=y
+# CONFIG_IFB is not set
 CONFIG_DUMMY=y
 # CONFIG_BONDING is not set
 # CONFIG_MACVLAN is not set
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
-# CONFIG_NET_ETHERNET is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
+CONFIG_WLAN=y
+# CONFIG_USB_ZD1201 is not set
+CONFIG_BCM4329=m
+CONFIG_BCM4329_FW_PATH="/system/vendor/firmware/fw_bcm4329.bin"
+CONFIG_BCM4329_NVRAM_PATH="/system/etc/nvram.txt"
+CONFIG_BCM4329_WIFI_CONTROL_FUNC=y
+# CONFIG_BCM4329_DHD_USE_STATIC_BUF is not set
+# CONFIG_BCM4329_HW_OOB is not set
+# CONFIG_BCM4329_OOB_INTR_ONLY is not set
+# CONFIG_BCM4329_GET_CUSTOM_MAC_ENABLE is not set
+# CONFIG_HOSTAP is not set
 
 #
 # Enable WiMAX (Networking options) to see the WiMAX drivers
 #
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_AX8817X is not set
+CONFIG_USB_NET_CDCETHER=y
+# CONFIG_USB_NET_CDC_EEM is not set
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_SMSC75XX is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_GL620A is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+CONFIG_USB_NET_CDC_SUBSET=y
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_ARMLINUX is not set
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
 # CONFIG_WAN is not set
-# CONFIG_PPP is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_MPPE=y
+# CONFIG_PPPOE is not set
+CONFIG_PPPOLAC=y
+CONFIG_PPPOPNS=y
 # CONFIG_SLIP is not set
+CONFIG_SLHC=y
 # CONFIG_NETCONSOLE is not set
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
@@ -584,7 +1120,86 @@ CONFIG_DUMMY=y
 #
 # Input device support
 #
-# CONFIG_INPUT is not set
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+CONFIG_INPUT_KEYRESET=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_TEGRA is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_QT602240 is not set
+CONFIG_TOUCHSCREEN_PANJIT_I2C=y
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_ATMEL_MT_T9=y
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYCHORD is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=y
+CONFIG_INPUT_GPIO=y
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_ALPS_GPIO_SCROLLWHEEL is not set
 
 #
 # Hardware I/O ports
@@ -596,7 +1211,8 @@ CONFIG_DUMMY=y
 # Character devices
 #
 # CONFIG_VT is not set
-# CONFIG_DEVKMEM is not set
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
 # CONFIG_N_GSM is not set
 
@@ -612,6 +1228,9 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 #
 # Non-8250 serial port support
 #
+CONFIG_SERIAL_TEGRA=y
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 # CONFIG_SERIAL_TIMBERDALE is not set
@@ -625,9 +1244,67 @@ CONFIG_UNIX98_PTYS=y
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
+# CONFIG_DCC_TTY is not set
 # CONFIG_RAMOOPS is not set
-# CONFIG_I2C is not set
-# CONFIG_SPI is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+#
+# Multiplexer I2C Chip support
+#
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_SIMTEC is not set
+CONFIG_I2C_TEGRA=y
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_TEGRA=y
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
 
 #
 # PPS support
@@ -636,7 +1313,7 @@ CONFIG_UNIX98_PTYS=y
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
 # CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
+CONFIG_GPIO_SYSFS=y
 
 #
 # Memory mapped GPIO expanders:
@@ -646,6 +1323,13 @@ CONFIG_GPIOLIB=y
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+CONFIG_GPIO_PCA953X=y
+# CONFIG_GPIO_PCA953X_IRQ is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_ADP5588 is not set
 
 #
 # PCI GPIO expanders:
@@ -654,6 +1338,9 @@ CONFIG_GPIOLIB=y
 #
 # SPI GPIO expanders:
 #
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
 
 #
 # AC97 GPIO expanders:
@@ -663,8 +1350,94 @@ CONFIG_GPIOLIB=y
 # MODULbus GPIO expanders:
 #
 # CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+CONFIG_BATTERY_BQ20Z75=y
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
 # CONFIG_THERMAL is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
@@ -673,7 +1446,38 @@ CONFIG_SSB_POSSIBLE=y
 # Sonics Silicon Backplane
 #
 # CONFIG_SSB is not set
-# CONFIG_MFD_SUPPORT is not set
+CONFIG_MFD_SUPPORT=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC35892 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_MAX8907C is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_AB8500_CORE is not set
+CONFIG_MFD_TPS6586X=y
 CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_DEBUG is not set
 CONFIG_REGULATOR_DUMMY=y
@@ -681,11 +1485,99 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
 # CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
 # CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_MEDIA_SUPPORT is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_AD5398 is not set
+CONFIG_REGULATOR_TPS6586X=y
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+CONFIG_IR_CORE=y
+CONFIG_VIDEO_IR=y
+CONFIG_LIRC=y
+# CONFIG_RC_MAP is not set
+# CONFIG_IR_NEC_DECODER is not set
+# CONFIG_IR_RC5_DECODER is not set
+# CONFIG_IR_RC6_DECODER is not set
+# CONFIG_IR_JVC_DECODER is not set
+# CONFIG_IR_SONY_DECODER is not set
+CONFIG_IR_LIRC_CODEC=y
+# CONFIG_IR_IMON is not set
+# CONFIG_IR_MCEUSB is not set
+# CONFIG_IR_STREAMZAP is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=y
+CONFIG_TEGRA_RPC=y
+CONFIG_TEGRA_AVP=y
+CONFIG_TEGRA_CAMERA=y
+CONFIG_VIDEO_OV5650=y
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_I2C_SI4713 is not set
+# CONFIG_RADIO_SI4713 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_RADIO_SAA7706H is not set
+# CONFIG_RADIO_TEF6862 is not set
+# CONFIG_DAB is not set
 
 #
 # Graphics support
 #
+# CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
 CONFIG_VIDEO_OUTPUT_CONTROL=y
 CONFIG_FB=y
@@ -704,37 +1596,531 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SVGALIB is not set
 # CONFIG_FB_MACMODES is not set
 # CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
+CONFIG_FB_MODE_HELPERS=y
 # CONFIG_FB_TILEBLITTING is not set
 
 #
 # Frame buffer hardware drivers
 #
 # CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_TEGRA=y
+# CONFIG_FB_TMIO is not set
 # CONFIG_FB_VIRTUAL is not set
 # CONFIG_FB_METRONOME is not set
 # CONFIG_FB_MB862XX is not set
 # CONFIG_FB_BROADSHEET is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# NVIDIA Tegra Display Driver options
+#
+CONFIG_TEGRA_GRHOST=y
+CONFIG_TEGRA_DC=y
+CONFIG_FB_TEGRA=y
+CONFIG_TEGRA_NVMAP=y
+CONFIG_NVMAP_RECLAIM_UNPINNED_VM=y
+CONFIG_NVMAP_ALLOW_SYSMEM=y
+# CONFIG_NVMAP_HIGHMEM_ONLY is not set
+# CONFIG_NVMAP_CARVEOUT_KILLER is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
 
 #
 # Display device support
 #
 # CONFIG_DISPLAY_SUPPORT is not set
 # CONFIG_LOGO is not set
-# CONFIG_SOUND is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_MMC is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=y
+CONFIG_TEGRA_ALSA=y
+CONFIG_TEGRA_PCM=y
+CONFIG_TEGRA_I2S=y
+CONFIG_TEGRA_IEC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+# CONFIG_SND_SOC_WM8753 is not set
+CONFIG_SND_SOC_WM8903=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX_FF is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CANDO is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EGALAX is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MOSART is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_KONE is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_STANTUM is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_TEGRA_HCD=y
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=y
+# CONFIG_USB_PRINTER is not set
+CONFIG_USB_WDM=y
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+# CONFIG_USB_EZUSB is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_FSL_USB2=y
+CONFIG_USB_FSL_USB2=y
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_MASS_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_ANDROID=y
+# CONFIG_USB_ANDROID_ACM is not set
+CONFIG_USB_ANDROID_ADB=y
+CONFIG_USB_ANDROID_MASS_STORAGE=y
+CONFIG_USB_ANDROID_MTP=y
+# CONFIG_USB_ANDROID_RNDIS is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_USB_TEGRA_OTG=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_EMBEDDED_SDIO=y
+CONFIG_MMC_PARANOID_SD_INIT=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PLTFM is not set
+CONFIG_MMC_SDHCI_TEGRA=y
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
+CONFIG_SWITCH=y
+# CONFIG_SWITCH_GPIO is not set
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_TEGRA is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+CONFIG_RTC_DRV_TPS6586X=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
-# CONFIG_STAGING is not set
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_VIDEO_TM6000 is not set
+# CONFIG_USB_IP_COMMON is not set
+# CONFIG_ECHO is not set
+# CONFIG_RT2870 is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
+CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y
+CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128
+CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16
+CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8
+CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d
+# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+# CONFIG_POHMELFS is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_USB_SERIAL_QUATECH2 is not set
+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+CONFIG_IIO=y
+# CONFIG_IIO_RING_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADIS16220 is not set
+# CONFIG_ADIS16240 is not set
+# CONFIG_KXSD9 is not set
+# CONFIG_LIS3L02DQ is not set
+
+#
+# Analog to digital convertors
+#
+# CONFIG_MAX1363 is not set
+
+#
+# Digital gyroscope sensors
+#
+# CONFIG_ADIS16260 is not set
+
+#
+# Inertial measurement units
+#
+# CONFIG_ADIS16300 is not set
+# CONFIG_ADIS16350 is not set
+# CONFIG_ADIS16400 is not set
+
+#
+# Light sensors
+#
+# CONFIG_SENSORS_TSL2563 is not set
+CONFIG_ISL29018=y
+
+#
+# Magnetometer sensors
+#
+# CONFIG_SENSORS_HMC5843 is not set
+
+#
+# Triggers - standalone
+#
+# CONFIG_ZRAM is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_FB_SM7XX is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_ST_BT is not set
+# CONFIG_ADIS16255 is not set
+# CONFIG_LIRC_STAGING is not set
+# CONFIG_EASYCAP is not set
 
 #
 # File systems
@@ -749,9 +2135,15 @@ CONFIG_EXT3_FS=y
 CONFIG_EXT3_FS_XATTR=y
 CONFIG_EXT3_FS_POSIX_ACL=y
 CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4_FS is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
 CONFIG_JBD=y
 # CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
 CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
@@ -764,12 +2156,12 @@ CONFIG_FS_POSIX_ACL=y
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
 # CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
 # CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
 
 #
 # Caches
@@ -811,6 +2203,8 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_BEFS_FS is not set
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
+# CONFIG_YAFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
 # CONFIG_LOGFS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
@@ -835,8 +2229,25 @@ CONFIG_NETWORK_FILESYSTEMS=y
 #
 # Partition Types
 #
-# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
 CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_CMDLINE_PARTITION is not set
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
 CONFIG_NLS_CODEPAGE_437=y
@@ -893,9 +2304,8 @@ CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 # CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
 CONFIG_DETECT_HUNG_TASK=y
 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
@@ -903,28 +2313,29 @@ CONFIG_SCHED_DEBUG=y
 CONFIG_SCHEDSTATS=y
 CONFIG_TIMER_STATS=y
 # CONFIG_DEBUG_OBJECTS is not set
-CONFIG_DEBUG_SLAB=y
-# CONFIG_DEBUG_SLAB_LEAK is not set
+# CONFIG_DEBUG_SLAB is not set
 # CONFIG_DEBUG_KMEMLEAK is not set
 # CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_MUTEXES is not set
 # CONFIG_DEBUG_LOCK_ALLOC is not set
 # CONFIG_PROVE_LOCKING is not set
 # CONFIG_LOCK_STAT is not set
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
 # CONFIG_DEBUG_KOBJECT is not set
 # CONFIG_DEBUG_HIGHMEM is not set
-CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
 CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
 CONFIG_DEBUG_VM=y
 # CONFIG_DEBUG_WRITECOUNT is not set
 # CONFIG_DEBUG_MEMORY_INIT is not set
 # CONFIG_DEBUG_LIST is not set
-CONFIG_DEBUG_SG=y
+# CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
 # CONFIG_DEBUG_CREDENTIALS is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
@@ -946,13 +2357,10 @@ CONFIG_FTRACE=y
 # CONFIG_PREEMPT_TRACER is not set
 # CONFIG_SCHED_TRACER is not set
 # CONFIG_ENABLE_DEFAULT_TRACERS is not set
-# CONFIG_BOOT_TRACER is not set
 CONFIG_BRANCH_PROFILE_NONE=y
 # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
 # CONFIG_PROFILE_ALL_BRANCHES is not set
 # CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
 # CONFIG_BLK_DEV_IO_TRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
 # CONFIG_ATOMIC64_SELFTEST is not set
@@ -963,9 +2371,7 @@ CONFIG_ARM_UNWIND=y
 # CONFIG_DEBUG_USER is not set
 # CONFIG_DEBUG_ERRORS is not set
 # CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_DEBUG_LL is not set
 # CONFIG_OC_ETM is not set
 
 #
@@ -974,9 +2380,6 @@ CONFIG_EARLY_PRINTK=y
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_DEFAULT_SECURITY_SELINUX is not set
-# CONFIG_DEFAULT_SECURITY_SMACK is not set
-# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
 CONFIG_DEFAULT_SECURITY_DAC=y
 CONFIG_DEFAULT_SECURITY=""
 CONFIG_CRYPTO=y
@@ -993,9 +2396,10 @@ CONFIG_CRYPTO_BLKCIPHER2=y
 CONFIG_CRYPTO_HASH=y
 CONFIG_CRYPTO_HASH2=y
 CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_PCOMP2=y
 CONFIG_CRYPTO_MANAGER=y
 CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_PCRYPT is not set
@@ -1032,7 +2436,7 @@ CONFIG_CRYPTO_HMAC=y
 #
 # Digest
 #
-# CONFIG_CRYPTO_CRC32C is not set
+CONFIG_CRYPTO_CRC32C=y
 # CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
@@ -1079,6 +2483,7 @@ CONFIG_CRYPTO_DEFLATE=y
 #
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_TEGRA_AES=y
 # CONFIG_BINARY_PRINTF is not set
 
 #
@@ -1092,10 +2497,17 @@ CONFIG_CRC16=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
+CONFIG_LIBCRC32C=y
 CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_DECOMPRESS_GZIP=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/tegra_harmony_gnu_linux_defconfig b/arch/arm/configs/tegra_harmony_gnu_linux_defconfig
new file mode 100644
index 000000000000..afec1916bdf0
--- /dev/null
+++ b/arch/arm/configs/tegra_harmony_gnu_linux_defconfig
@@ -0,0 +1,2605 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.36
+# Wed Dec 22 08:57:12 2010
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_LOCKBREAK=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_ARCH_HAS_DEFAULT_IDLE=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_FIQ=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_ARCH_PROVIDES_UDELAY=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+CONFIG_RCU_FAST_NO_HZ=y
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=m
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUPS=y
+# CONFIG_CGROUP_DEBUG is not set
+CONFIG_CGROUP_NS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+#CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+CONFIG_RELAY=y
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+# CONFIG_RD_LZO is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+CONFIG_ARCH_TEGRA=y
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_S5PV310 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
+
+#
+# NVIDIA Tegra options
+#
+CONFIG_ARCH_TEGRA_2x_SOC=y
+
+#
+# Tegra board type
+#
+CONFIG_MACH_HARMONY=y
+# CONFIG_MACH_VENTANA is not set
+CONFIG_MACH_SEABOARD=y
+CONFIG_MACH_KAEN=y
+# CONFIG_TEGRA_DEBUG_UART_NONE is not set
+# CONFIG_TEGRA_DEBUG_UARTA is not set
+# CONFIG_TEGRA_DEBUG_UARTB is not set
+# CONFIG_TEGRA_DEBUG_UARTC is not set
+CONFIG_TEGRA_DEBUG_UARTD=y
+# CONFIG_TEGRA_DEBUG_UARTE is not set
+CONFIG_TEGRA_SYSTEM_DMA=y
+CONFIG_TEGRA_PWM=y
+CONFIG_TEGRA_FIQ_DEBUGGER=y
+
+#
+# NVIDIA NVRM/NVOS options
+#
+CONFIG_TEGRA_NVRM=y
+CONFIG_TEGRA_NVOS=y
+CONFIG_TEGRA_CPU_DVFS=y
+CONFIG_TEGRA_IOVMM_GART=y
+CONFIG_TEGRA_IOVMM=y
+# CONFIG_TEGRA_I2S_AUDIO is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_ARCH_HAS_BARRIERS=y
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_ARM_ERRATA_742230=y
+# CONFIG_ARM_ERRATA_742231 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
+CONFIG_ARM_GIC=y
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SMP=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=2
+CONFIG_HOTPLUG_CPU=y
+CONFIG_LOCAL_TIMERS=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HIGHMEM=y
+CONFIG_HW_PERF_EVENTS=y
+# CONFIG_SPARSE_IRQ is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+CONFIG_CC_STACKPROTECTOR=y
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+CONFIG_ANDROID_PMEM=n
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=448M@0M console=ttyS0,115200n8 earlyprintk init=/bin/ash"
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+# CONFIG_AUTO_ZRELADDR is not set
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_NEON is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_NVS=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_OPS=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+CONFIG_IP_MROUTE=y
+# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+# CONFIG_TCP_CONG_BIC is not set
+CONFIG_TCP_CONG_CUBIC=y
+# CONFIG_TCP_CONG_WESTWOOD is not set
+# CONFIG_TCP_CONG_HTCP is not set
+# CONFIG_TCP_CONG_HSTCP is not set
+# CONFIG_TCP_CONG_HYBLA is not set
+# CONFIG_TCP_CONG_VEGAS is not set
+# CONFIG_TCP_CONG_SCALABLE is not set
+# CONFIG_TCP_CONG_LP is not set
+# CONFIG_TCP_CONG_VENO is not set
+# CONFIG_TCP_CONG_YEAH is not set
+# CONFIG_TCP_CONG_ILLINOIS is not set
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+CONFIG_NETLABEL=y
+CONFIG_NETWORK_SECMARK=y
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+# CONFIG_NETFILTER_ADVANCED is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+
+#
+# Xtables targets
+#
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_SECMARK=y
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+CONFIG_NF_NAT_SIP=y
+CONFIG_IP_NF_MANGLE=y
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_TARGET_LOG=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+# CONFIG_NET_SCH_HTB is not set
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+# CONFIG_NET_SCH_INGRESS is not set
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+# CONFIG_NET_CLS_U32 is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+# CONFIG_NET_EMATCH_CMP is not set
+# CONFIG_NET_EMATCH_NBYTE is not set
+# CONFIG_NET_EMATCH_U32 is not set
+# CONFIG_NET_EMATCH_META is not set
+# CONFIG_NET_EMATCH_TEXT is not set
+CONFIG_NET_CLS_ACT=y
+# CONFIG_NET_ACT_POLICE is not set
+# CONFIG_NET_ACT_GACT is not set
+# CONFIG_NET_ACT_MIRRED is not set
+# CONFIG_NET_ACT_IPT is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_SIMP is not set
+# CONFIG_NET_ACT_SKBEDIT is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+# CONFIG_DNS_RESOLVER is not set
+CONFIG_RPS=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_NET_DROP_MONITOR is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+# CONFIG_BT_RFCOMM_TTY is not set
+CONFIG_BT_BNEP=m
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTSDIO=m
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIVHCI=m
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_ATH3K is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+CONFIG_CFG80211_DEBUGFS=y
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=m
+CONFIG_LIB80211_CRYPT_WEP=m
+CONFIG_LIB80211_CRYPT_CCMP=m
+CONFIG_LIB80211_CRYPT_TKIP=m
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_HAS_RC=y
+# CONFIG_MAC80211_RC_PID is not set
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211_DEBUGFS=y
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_LEDS=y
+# CONFIG_RFKILL_INPUT is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+CONFIG_DEBUG_DEVRES=y
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_NAND_TEGRA is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_XIP=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IWMC3200TOP is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+CONFIG_SCSI_SPI_ATTRS=y
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=y
+CONFIG_DM_BHT=y
+CONFIG_DM_VERITY=y
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+# CONFIG_DM_UEVENT is not set
+CONFIG_NETDEVICES=y
+# CONFIG_IFB is not set
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+CONFIG_WLAN=y
+CONFIG_LIBERTAS_THINFIRM=m
+# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set
+# CONFIG_LIBERTAS_THINFIRM_USB is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+CONFIG_MAC80211_HWSIM=m
+CONFIG_ATH_COMMON=m
+# CONFIG_ATH_DEBUG is not set
+# CONFIG_ATH9K_HTC is not set
+# CONFIG_AR9170_USB is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_HOSTAP=m
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_IWM is not set
+# CONFIG_LIBERTAS is not set
+CONFIG_P54_COMMON=m
+# CONFIG_P54_USB is not set
+# CONFIG_P54_SPI is not set
+CONFIG_P54_LEDS=y
+CONFIG_RT2X00=m
+# CONFIG_RT2500USB is not set
+# CONFIG_RT73USB is not set
+# CONFIG_RT2800USB is not set
+# CONFIG_WL12XX is not set
+# CONFIG_ZD1211RW is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=y
+CONFIG_USB_KAWETH=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_RTL8150=y
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+CONFIG_USB_NET_CDC_EEM=y
+CONFIG_USB_NET_DM9601=y
+CONFIG_USB_NET_SMSC75XX=y
+CONFIG_USB_NET_SMSC95XX=y
+CONFIG_USB_NET_GL620A=y
+CONFIG_USB_NET_NET1080=y
+CONFIG_USB_NET_PLUSB=y
+CONFIG_USB_NET_MCS7830=y
+CONFIG_USB_NET_RNDIS_HOST=y
+CONFIG_USB_NET_CDC_SUBSET=y
+CONFIG_USB_NET_ZAURUS=y
+CONFIG_USB_HSO=y
+CONFIG_USB_NET_INT51X1=y
+CONFIG_USB_IPHETH=y
+CONFIG_USB_SIERRA_NET=y
+CONFIG_WAN=y
+CONFIG_SWITCH=y
+CONFIG_SWITCH_GPIO=y
+
+#
+# CAIF transport drivers
+#
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_SYNC_TTY=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+CONFIG_NETCONSOLE=y
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_KEYBOARD_TEGRA=y
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+CONFIG_MOUSE_GPIO=m
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_QT602240 is not set
+# CONFIG_TOUCHSCREEN_PANJIT_I2C is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
+# CONFIG_INPUT_ADXL34X is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_TEGRA is not set
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+CONFIG_TCG_TPM=m
+CONFIG_TCG_TIS=m
+# CONFIG_TCG_NSC is not set
+# CONFIG_TCG_ATMEL is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=m
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_SIMTEC is not set
+CONFIG_I2C_TEGRA=y
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+CONFIG_I2C_STUB=m
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+CONFIG_SPI_BITBANG=m
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_TEGRA is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=m
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+CONFIG_BATTERY_BQ20Z75=y
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_CHARGER_GPIO=y
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_MFD_SUPPORT=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC35892 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_AB8500_CORE is not set
+CONFIG_MFD_TPS6586X=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_AD5398 is not set
+CONFIG_REGULATOR_TPS6586X=y
+CONFIG_MEDIA_SUPPORT=m
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=m
+CONFIG_VIDEO_V4L2_COMMON=m
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+# CONFIG_VIDEO_V4L1_COMPAT is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=m
+
+#
+# Multimedia drivers
+#
+CONFIG_IR_CORE=m
+CONFIG_VIDEO_IR=m
+CONFIG_LIRC=m
+CONFIG_RC_MAP=m
+CONFIG_IR_NEC_DECODER=m
+CONFIG_IR_RC5_DECODER=m
+CONFIG_IR_RC6_DECODER=m
+CONFIG_IR_JVC_DECODER=m
+CONFIG_IR_SONY_DECODER=m
+CONFIG_IR_LIRC_CODEC=m
+# CONFIG_IR_IMON is not set
+# CONFIG_IR_MCEUSB is not set
+# CONFIG_IR_STREAMZAP is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=m
+CONFIG_MEDIA_TUNER_CUSTOMISE=y
+# CONFIG_MEDIA_TUNER_SIMPLE is not set
+# CONFIG_MEDIA_TUNER_TDA8290 is not set
+# CONFIG_MEDIA_TUNER_TDA827X is not set
+# CONFIG_MEDIA_TUNER_TDA18271 is not set
+# CONFIG_MEDIA_TUNER_TDA9887 is not set
+# CONFIG_MEDIA_TUNER_TEA5761 is not set
+# CONFIG_MEDIA_TUNER_TEA5767 is not set
+# CONFIG_MEDIA_TUNER_MT20XX is not set
+# CONFIG_MEDIA_TUNER_MT2060 is not set
+# CONFIG_MEDIA_TUNER_MT2266 is not set
+# CONFIG_MEDIA_TUNER_MT2131 is not set
+# CONFIG_MEDIA_TUNER_QT1010 is not set
+# CONFIG_MEDIA_TUNER_XC2028 is not set
+# CONFIG_MEDIA_TUNER_XC5000 is not set
+# CONFIG_MEDIA_TUNER_MXL5005S is not set
+# CONFIG_MEDIA_TUNER_MXL5007T is not set
+# CONFIG_MEDIA_TUNER_MC44S803 is not set
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_VIDEO_V4L2=m
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+CONFIG_VIDEO_IR_I2C=m
+
+#
+# Encoders/decoders and other helper chips
+#
+
+#
+# Audio decoders
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TDA9875 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_M52790 is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_AK881X is not set
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+CONFIG_TEGRA_RPC=y
+CONFIG_TEGRA_AVP=y
+CONFIG_TEGRA_CAMERA=y
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=m
+# CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV is not set
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_RADIO_ADAPTERS is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+
+#
+# NVIDIA Tegra Display Driver options
+#
+CONFIG_TEGRA_GRHOST=y
+CONFIG_TEGRA_DC=y
+CONFIG_FB_TEGRA=y
+CONFIG_TEGRA_NVMAP=y
+CONFIG_NVMAP_RECLAIM_UNPINNED_VM=y
+CONFIG_NVMAP_ALLOW_SYSMEM=y
+# CONFIG_NVMAP_HIGHMEM_ONLY is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_JACK=y
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_HRTIMER=m
+CONFIG_SND_SEQ_HRTIMER_DEFAULT=y
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_RAWMIDI_SEQ=m
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=y
+CONFIG_TEGRA_ALSA=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM8903=y
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HIDRAW=y
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX_FF is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+CONFIG_HID_CANDO=y
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EGALAX is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MOSART is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_KONE is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_STANTUM is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+CONFIG_HID_WACOM=m
+# CONFIG_HID_WACOM_POWER_SUPPLY is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_TEGRA_HCD=y
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=y
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+# CONFIG_USB_EZUSB is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+CONFIG_USB_SERIAL_QUALCOMM=m
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+CONFIG_USB_SERIAL_WWAN=y
+CONFIG_USB_SERIAL_OPTION=y
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_USB_TEGRA_OTG is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PLTFM is not set
+CONFIG_MMC_SDHCI_TEGRA=y
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+# CONFIG_LEDS_GPIO is not set
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+CONFIG_LEDS_PWM=y
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGER_TIMER is not set
+# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+# CONFIG_LEDS_TRIGGER_GPIO is not set
+# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+CONFIG_RTC_DRV_TPS6586X=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_TEGRA=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_VIDEO_TM6000 is not set
+# CONFIG_USB_IP_COMMON is not set
+# CONFIG_W35UND is not set
+# CONFIG_PRISM2_USB is not set
+# CONFIG_ECHO is not set
+# CONFIG_OTUS is not set
+CONFIG_BRCM80211=m
+CONFIG_BRCMFMAC=y
+# CONFIG_RT2870 is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_TRANZPORT is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_USB_SERIAL_QUATECH2 is not set
+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+CONFIG_IIO=m
+# CONFIG_IIO_RING_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADIS16220 is not set
+# CONFIG_ADIS16240 is not set
+# CONFIG_KXSD9 is not set
+# CONFIG_LIS3L02DQ is not set
+
+#
+# Analog to digital convertors
+#
+# CONFIG_MAX1363 is not set
+
+#
+# Digital gyroscope sensors
+#
+# CONFIG_ADIS16260 is not set
+
+#
+# Inertial measurement units
+#
+# CONFIG_ADIS16300 is not set
+# CONFIG_ADIS16350 is not set
+# CONFIG_ADIS16400 is not set
+
+#
+# Light sensors
+#
+CONFIG_SENSORS_TSL2563=m
+CONFIG_SENSORS_ISL29018=m
+
+#
+# Magnetometer sensors
+#
+# CONFIG_SENSORS_HMC5843 is not set
+# CONFIG_SENSORS_AK8975 is not set
+
+#
+# Triggers - standalone
+#
+# CONFIG_ZRAM is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_FB_SM7XX is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_ST_BT is not set
+# CONFIG_ADIS16255 is not set
+# CONFIG_LIRC_STAGING is not set
+# CONFIG_EASYCAP is not set
+CONFIG_ATH6K_LEGACY=m
+# CONFIG_AR600x_SD31_XXX is not set
+CONFIG_AR600x_WB31_XXX=y
+# CONFIG_AR600x_SD32_XXX is not set
+# CONFIG_AR600x_CUSTOM_XXX is not set
+# CONFIG_ATH6KL_ENABLE_COEXISTENCE is not set
+# CONFIG_ATH6KL_HCI_BRIDGE is not set
+CONFIG_ATH6KL_CFG80211=y
+# CONFIG_ATH6KL_HTC_RAW_INTERFACE is not set
+# CONFIG_ATH6KL_VIRTUAL_SCATTER_GATHER is not set
+# CONFIG_ATH6KL_SKIP_ABI_VERSION_CHECK is not set
+# CONFIG_ATH6KL_DEBUG is not set
+
+#
+# Chromeos Supplied Third-Party Device Drivers
+#
+CONFIG_GOBI_USBNET=m
+# CONFIG_GOBI_QCSERIAL is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=m
+# CONFIG_CUSE is not set
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=y
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=m
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_TRACING=y
+CONFIG_GENERIC_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+CONFIG_FUNCTION_TRACER=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+CONFIG_KPROBE_EVENT=y
+# CONFIG_FUNCTION_PROFILER is not set
+# CONFIG_FTRACE_STARTUP_TEST is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_STACK_USAGE=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+CONFIG_SECURITY_NETWORK=y
+# CONFIG_SECURITY_NETWORK_XFRM is not set
+CONFIG_SECURITY_PATH=y
+# CONFIG_SECURITY_SELINUX is not set
+# CONFIG_SECURITY_SMACK is not set
+CONFIG_SECURITY_TOMOYO=y
+# CONFIG_SECURITY_APPARMOR is not set
+# CONFIG_IMA is not set
+CONFIG_DEFAULT_SECURITY_TOMOYO=y
+# CONFIG_DEFAULT_SECURITY_DAC is not set
+CONFIG_DEFAULT_SECURITY="tomoyo"
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=m
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/tegra_whistler_android_defconfig b/arch/arm/configs/tegra_whistler_android_defconfig
new file mode 100644
index 000000000000..baeb34e90f00
--- /dev/null
+++ b/arch/arm/configs/tegra_whistler_android_defconfig
@@ -0,0 +1,2481 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.36.3
+# Thu Jan 27 16:46:19 2011
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_LOCKBREAK=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y
+CONFIG_ARCH_HAS_DEFAULT_IDLE=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_FIQ=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_ARCH_PROVIDES_UDELAY=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE="arm-eabi-"
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+# CONFIG_SWAP is not set
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+CONFIG_RCU_FAST_NO_HZ=y
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+# CONFIG_CGROUP_NS is not set
+CONFIG_CGROUP_FREEZER=y
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CPUSETS is not set
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_CGROUP_MEM_RES_CTLR is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+# CONFIG_BLK_CGROUP is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_PANIC_TIMEOUT=10
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_ASHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+CONFIG_ARCH_TEGRA=y
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_S5PV310 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
+
+#
+# NVIDIA Tegra options
+#
+CONFIG_ARCH_TEGRA_2x_SOC=y
+
+#
+# Tegra board type
+#
+# CONFIG_MACH_HARMONY is not set
+# CONFIG_MACH_VENTANA is not set
+CONFIG_MACH_WHISTLER=y
+# CONFIG_TEGRA_DEBUG_UART_NONE is not set
+CONFIG_TEGRA_DEBUG_UARTA=y
+# CONFIG_TEGRA_DEBUG_UARTB is not set
+# CONFIG_TEGRA_DEBUG_UARTC is not set
+# CONFIG_TEGRA_DEBUG_UARTD is not set
+# CONFIG_TEGRA_DEBUG_UARTE is not set
+CONFIG_TEGRA_SYSTEM_DMA=y
+CONFIG_TEGRA_PWM=y
+CONFIG_TEGRA_FIQ_DEBUGGER=y
+# CONFIG_TEGRA_EMC_SCALING_ENABLE is not set
+CONFIG_TEGRA_CPU_DVFS=y
+CONFIG_TEGRA_CORE_DVFS=y
+CONFIG_TEGRA_IOVMM_GART=y
+CONFIG_TEGRA_IOVMM=y
+# CONFIG_TEGRA_THERMAL_THROTTLE is not set
+# CONFIG_TEGRA_CLOCK_DEBUG_WRITE is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_ARCH_HAS_BARRIERS=y
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_ARM_ERRATA_742230=y
+# CONFIG_ARM_ERRATA_742231 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+# CONFIG_ARM_ERRATA_743622 is not set
+CONFIG_ARM_GIC=y
+CONFIG_COMMON_CLKDEV=y
+CONFIG_FIQ_GLUE=y
+CONFIG_FIQ_DEBUGGER=y
+# CONFIG_FIQ_DEBUGGER_NO_SLEEP is not set
+# CONFIG_FIQ_DEBUGGER_WAKEUP_IRQ_ALWAYS_ON is not set
+# CONFIG_FIQ_DEBUGGER_CONSOLE is not set
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SMP=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=2
+CONFIG_HOTPLUG_CPU=y
+CONFIG_LOCAL_TIMERS=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HIGHMEM=y
+# CONFIG_SPARSE_IRQ is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=448M@0M console=ttyS0,115200n8 earlyprintk init=/bin/ash"
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+# CONFIG_AUTO_ZRELADDR is not set
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_NEON is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND_NVS=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_HAS_WAKELOCK=y
+CONFIG_HAS_EARLYSUSPEND=y
+CONFIG_WAKELOCK=y
+CONFIG_WAKELOCK_STAT=y
+CONFIG_USER_WAKELOCK=y
+CONFIG_EARLYSUSPEND=y
+# CONFIG_NO_USER_SPACE_SCREEN_ACCESS_CONTROL is not set
+CONFIG_FB_EARLYSUSPEND=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_OPS=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+CONFIG_INET_ESP=y
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+# CONFIG_IPV6_ROUTE_INFO is not set
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_INET6_XFRM_TUNNEL=y
+CONFIG_INET6_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+# CONFIG_IPV6_SUBTREES is not set
+# CONFIG_IPV6_MROUTE is not set
+CONFIG_ANDROID_PARANOID_NETWORK=y
+CONFIG_NET_ACTIVITY_STATS=y
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_CONNMARK=y
+
+#
+# Xtables targets
+#
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+# CONFIG_NETFILTER_XT_TARGET_IDLETIMER is not set
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_HL=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_ADDRTYPE=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=y
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_NF_NAT_SIP=y
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_TARGET_TTL is not set
+# CONFIG_IP_NF_RAW is not set
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+
+#
+# IPv6: Netfilter Configuration
+#
+# CONFIG_NF_CONNTRACK_IPV6 is not set
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+# CONFIG_NET_SCH_CBQ is not set
+CONFIG_NET_SCH_HTB=y
+# CONFIG_NET_SCH_HFSC is not set
+# CONFIG_NET_SCH_PRIO is not set
+# CONFIG_NET_SCH_MULTIQ is not set
+# CONFIG_NET_SCH_RED is not set
+# CONFIG_NET_SCH_SFQ is not set
+# CONFIG_NET_SCH_TEQL is not set
+# CONFIG_NET_SCH_TBF is not set
+# CONFIG_NET_SCH_GRED is not set
+# CONFIG_NET_SCH_DSMARK is not set
+# CONFIG_NET_SCH_NETEM is not set
+# CONFIG_NET_SCH_DRR is not set
+CONFIG_NET_SCH_INGRESS=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+# CONFIG_NET_CLS_BASIC is not set
+# CONFIG_NET_CLS_TCINDEX is not set
+# CONFIG_NET_CLS_ROUTE4 is not set
+# CONFIG_NET_CLS_FW is not set
+CONFIG_NET_CLS_U32=y
+# CONFIG_CLS_U32_PERF is not set
+# CONFIG_CLS_U32_MARK is not set
+# CONFIG_NET_CLS_RSVP is not set
+# CONFIG_NET_CLS_RSVP6 is not set
+# CONFIG_NET_CLS_FLOW is not set
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+# CONFIG_NET_EMATCH_CMP is not set
+# CONFIG_NET_EMATCH_NBYTE is not set
+CONFIG_NET_EMATCH_U32=y
+# CONFIG_NET_EMATCH_META is not set
+# CONFIG_NET_EMATCH_TEXT is not set
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=y
+CONFIG_NET_ACT_GACT=y
+# CONFIG_GACT_PROB is not set
+CONFIG_NET_ACT_MIRRED=y
+# CONFIG_NET_ACT_IPT is not set
+# CONFIG_NET_ACT_NAT is not set
+# CONFIG_NET_ACT_PEDIT is not set
+# CONFIG_NET_ACT_SIMP is not set
+# CONFIG_NET_ACT_SKBEDIT is not set
+# CONFIG_NET_CLS_IND is not set
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+# CONFIG_RPS is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_ATH3K is not set
+CONFIG_BT_HCIUART_LL=y
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_PRIV=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT_SYSFS=y
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+
+#
+# Some wireless drivers require a rate control algorithm
+#
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=y
+CONFIG_RFKILL_PM=y
+# CONFIG_RFKILL_INPUT is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_NAND_TEGRA=y
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ANDROID_PMEM is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_KERNEL_DEBUGGER_CORE=y
+# CONFIG_ISL29003 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_SENSORS_AK8975 is not set
+# CONFIG_SENSORS_NCT1008 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_UID_STAT is not set
+# CONFIG_BMP085 is not set
+# CONFIG_WL127X_RFKILL is not set
+# CONFIG_APANIC is not set
+CONFIG_BCM4329_RFKILL=y
+# CONFIG_TEGRA_CRYPTO_DEV is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IWMC3200TOP is not set
+
+#
+# Motion Sensors Support
+#
+# CONFIG_SENSORS_MPU3050 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM=y
+# CONFIG_DM_DEBUG is not set
+CONFIG_DM_CRYPT=y
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+# CONFIG_IFB is not set
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_USB_ZD1201 is not set
+CONFIG_BCM4329=m
+CONFIG_BCM4329_FW_PATH="/system/vendor/firmware/fw_bcm4329.bin"
+CONFIG_BCM4329_NVRAM_PATH="/system/etc/nvram.txt"
+CONFIG_BCM4329_WIFI_CONTROL_FUNC=y
+# CONFIG_BCM4329_DHD_USE_STATIC_BUF is not set
+# CONFIG_BCM4329_HW_OOB is not set
+# CONFIG_BCM4329_OOB_INTR_ONLY is not set
+# CONFIG_BCM4329_GET_CUSTOM_MAC_ENABLE is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_WAN is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_MPPE=y
+# CONFIG_PPPOE is not set
+CONFIG_PPPOLAC=y
+CONFIG_PPPOPNS=y
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+CONFIG_INPUT_KEYRESET=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+CONFIG_KEYBOARD_TEGRA=y
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_QT602240 is not set
+# CONFIG_TOUCHSCREEN_PANJIT_I2C is not set
+CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI=y
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MT_T9 is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYCHORD is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=y
+CONFIG_INPUT_GPIO=y
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+CONFIG_INPUT_ADXL34X=y
+CONFIG_INPUT_ADXL34X_I2C=y
+# CONFIG_INPUT_ADXL34X_SPI is not set
+CONFIG_INPUT_ALPS_GPIO_SCROLLWHEEL=y
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_DEVMEM=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_TEGRA=y
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX3107 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_DCC_TTY is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_SIMTEC is not set
+CONFIG_I2C_TEGRA=y
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_TEGRA=y
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PDA_POWER=y
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ20Z75 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_MFD_SUPPORT=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC35892 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8998 is not set
+CONFIG_MFD_MAX8907C=y
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_AB8500_CORE is not set
+CONFIG_MFD_TPS6586X=y
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+CONFIG_REGULATOR_MAX8907C=y
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_AD5398 is not set
+CONFIG_REGULATOR_TPS6586X=y
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+CONFIG_IR_CORE=y
+CONFIG_VIDEO_IR=y
+CONFIG_LIRC=y
+# CONFIG_RC_MAP is not set
+# CONFIG_IR_NEC_DECODER is not set
+# CONFIG_IR_RC5_DECODER is not set
+# CONFIG_IR_RC6_DECODER is not set
+# CONFIG_IR_JVC_DECODER is not set
+# CONFIG_IR_SONY_DECODER is not set
+CONFIG_IR_LIRC_CODEC=y
+# CONFIG_IR_IMON is not set
+# CONFIG_IR_MCEUSB is not set
+# CONFIG_IR_STREAMZAP is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=y
+CONFIG_TEGRA_RPC=y
+CONFIG_TEGRA_AVP=y
+CONFIG_TEGRA_CAMERA=y
+# CONFIG_VIDEO_OV5650 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+# CONFIG_USB_GSPCA is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_I2C_SI4713 is not set
+# CONFIG_RADIO_SI4713 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_RADIO_SAA7706H is not set
+# CONFIG_RADIO_TEF6862 is not set
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+
+#
+# NVIDIA Tegra Display Driver options
+#
+CONFIG_TEGRA_GRHOST=y
+CONFIG_TEGRA_DC=y
+CONFIG_FB_TEGRA=y
+CONFIG_TEGRA_NVMAP=y
+CONFIG_NVMAP_RECLAIM_UNPINNED_VM=y
+CONFIG_NVMAP_ALLOW_SYSMEM=y
+# CONFIG_NVMAP_HIGHMEM_ONLY is not set
+# CONFIG_NVMAP_CARVEOUT_KILLER is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=y
+CONFIG_TEGRA_ALSA=y
+CONFIG_TEGRA_PCM=y
+CONFIG_TEGRA_I2S=y
+CONFIG_TEGRA_IEC=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM8753=y
+# CONFIG_SND_SOC_WM8903 is not set
+# CONFIG_SOUND_PRIME is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX_FF is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CANDO is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EGALAX is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MOSART is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_KONE is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_STANTUM is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+CONFIG_USB_TEGRA_HCD=y
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+# CONFIG_USB_EZUSB is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_FSL_USB2=y
+CONFIG_USB_FSL_USB2=y
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+# CONFIG_USB_ETH is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_MASS_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+CONFIG_USB_ANDROID=y
+# CONFIG_USB_ANDROID_ACM is not set
+CONFIG_USB_ANDROID_ADB=y
+# CONFIG_USB_ANDROID_MASS_STORAGE is not set
+CONFIG_USB_ANDROID_MTP=y
+# CONFIG_USB_ANDROID_RNDIS is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_USB_TEGRA_OTG=y
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_EMBEDDED_SDIO=y
+CONFIG_MMC_PARANOID_SD_INIT=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+CONFIG_MMC_BLOCK_DEFERRED_RESUME=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PLTFM is not set
+CONFIG_MMC_SDHCI_TEGRA=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_SWITCH=y
+# CONFIG_SWITCH_GPIO is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+CONFIG_RTC_INTF_ALARM=y
+CONFIG_RTC_INTF_ALARM_DEV=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_TEGRA is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_TPS6586X is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_VIDEO_TM6000 is not set
+# CONFIG_USB_IP_COMMON is not set
+# CONFIG_ECHO is not set
+# CONFIG_RT2870 is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_RAM_CONSOLE=y
+CONFIG_ANDROID_RAM_CONSOLE_ENABLE_VERBOSE=y
+CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION=y
+CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_DATA_SIZE=128
+CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_ECC_SIZE=16
+CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_SYMBOL_SIZE=8
+CONFIG_ANDROID_RAM_CONSOLE_ERROR_CORRECTION_POLYNOMIAL=0x11d
+# CONFIG_ANDROID_RAM_CONSOLE_EARLY_INIT is not set
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+# CONFIG_POHMELFS is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_USB_SERIAL_QUATECH2 is not set
+# CONFIG_USB_SERIAL_QUATECH_USB2 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+CONFIG_IIO=y
+# CONFIG_IIO_RING_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADIS16220 is not set
+# CONFIG_ADIS16240 is not set
+# CONFIG_KXSD9 is not set
+# CONFIG_LIS3L02DQ is not set
+
+#
+# Analog to digital convertors
+#
+# CONFIG_MAX1363 is not set
+
+#
+# Digital gyroscope sensors
+#
+# CONFIG_ADIS16260 is not set
+
+#
+# Inertial measurement units
+#
+# CONFIG_ADIS16300 is not set
+# CONFIG_ADIS16350 is not set
+# CONFIG_ADIS16400 is not set
+
+#
+# Light sensors
+#
+# CONFIG_SENSORS_TSL2563 is not set
+CONFIG_ISL29018=y
+
+#
+# Magnetometer sensors
+#
+# CONFIG_SENSORS_HMC5843 is not set
+
+#
+# Triggers - standalone
+#
+# CONFIG_ZRAM is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_FB_SM7XX is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_ST_BT is not set
+# CONFIG_ADIS16255 is not set
+# CONFIG_LIRC_STAGING is not set
+# CONFIG_EASYCAP is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_YAFFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+# CONFIG_CMDLINE_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_CPU_NOTIFIER_ERROR_INJECT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_TEGRA_AES is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_ENC8=y
+CONFIG_REED_SOLOMON_DEC8=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 5078dc6c50d8..8c885b6f97f8 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -137,10 +137,10 @@
 #endif
 
 /*
- * This flag is used to indicate that the page pointed to by a pte
- * is dirty and requires cleaning before returning it to the user.
+ * This flag is used to indicate that the page pointed to by a pte is clean
+ * and does not require cleaning before returning it to the user.
  */
-#define PG_dcache_dirty PG_arch_1
+#define PG_dcache_clean PG_arch_1
 
 /*
  *	MM Cache Management
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 73ee18b1a054..ab08cd74e7d3 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -279,9 +279,24 @@ extern struct page *empty_zero_page;
 
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
 
-#define set_pte_at(mm,addr,ptep,pteval) do { \
-	set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \
- } while (0)
+#ifndef CONFIG_SMP
+static inline void __sync_icache_dcache(pte_t pteval)
+{
+}
+#else
+extern void __sync_icache_dcache(pte_t pteval);
+#endif
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+			      pte_t *ptep, pte_t pteval)
+{
+	if (addr >= TASK_SIZE)
+		set_pte_ext(ptep, pteval, 0);
+	else {
+		__sync_icache_dcache(pteval);
+		set_pte_ext(ptep, pteval, PTE_EXT_NG);
+	}
+}
 
 /*
  * The following only work if pte_present() is true.
@@ -293,6 +308,10 @@ extern struct page *empty_zero_page;
 #define pte_young(pte)		(pte_val(pte) & L_PTE_YOUNG)
 #define pte_special(pte)	(0)
 
+#define pte_present_exec_user(pte) \
+	((pte_val(pte) & (L_PTE_PRESENT | L_PTE_EXEC | L_PTE_USER)) == \
+	 (L_PTE_PRESENT | L_PTE_EXEC | L_PTE_USER))
+
 #define PTE_BIT_FUNC(fn,op) \
 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
 
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 33b546ae72d4..12c90ada8f6b 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -560,12 +560,20 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 #endif
 
 /*
- * if PG_dcache_dirty is set for the page, we need to ensure that any
+ * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
- * back to the page.
+ * back to the page. On SMP systems, the cache coherency is handled in the
+ * set_pte_at() function.
  */
+#ifndef CONFIG_SMP
 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 	pte_t *ptep);
+#else
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+				    unsigned long addr, pte_t *ptep)
+{
+}
+#endif
 
 #endif
 
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index e94c092b1560..2bbd98bda7cc 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -29,6 +29,11 @@ config MACH_VENTANA
        help
          Support for NVIDIA Ventana development platform
 
+config MACH_WHISTLER
+       bool "Whistler board"
+       help
+         Support for NVIDIA Whistler development platform
+
 choice
         prompt "Low-level debug console UART"
         default TEGRA_DEBUG_UART_NONE
@@ -73,6 +78,8 @@ config TEGRA_FIQ_DEBUGGER
 	help
 	  Enables the FIQ serial debugger on Tegra"
 
+source "arch/arm/mach-tegra/nv/Kconfig"
+
 endif
 
 config TEGRA_EMC_SCALING_ENABLE
@@ -110,3 +117,8 @@ config TEGRA_THERMAL_THROTTLE
        default y
        help
          Also requires enabling a temperature sensor such as NCT1008.
+
+config TEGRA_CLOCK_DEBUG_WRITE
+	bool "Enable debugfs write access to clock tree"
+	depends on DEBUG_FS
+	default n
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index b2374b94d9ea..df7ad6264abc 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,6 +1,8 @@
 obj-y                                   += common.o
+obj-y                                   += apbio.o
 obj-y                                   += io.o
 obj-y                                   += irq.o legacy_irq.o
+obj-y                                   += syncpt.o
 obj-y                                   += clock.o
 obj-y                                   += dvfs.o
 obj-y                                   += timer.o
@@ -9,11 +11,17 @@ obj-y                                   += pinmux.o
 obj-y                                   += devices.o
 obj-y                                   += delay.o
 obj-y                                   += powergate.o
-obj-y					+= suspend.o
-obj-y					+= fuse.o
-obj-y					+= tegra_i2s_audio.o
-obj-y					+= tegra_spdif_audio.o
-obj-y					+= mc.o
+obj-y                                   += suspend.o
+obj-y                                   += fuse.o
+obj-y                                   += kfuse.o
+ifeq ($(CONFIG_TEGRA_ALSA),y)
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_i2s.o
+else
+obj-y                                   += tegra_i2s_audio.o
+endif
+obj-y                                   += tegra_spdif_audio.o
+obj-y                                   += tegra_das.o
+obj-y                                   += mc.o
 obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
 obj-$(CONFIG_FIQ)                       += fiq.o
 obj-$(CONFIG_TEGRA_FIQ_DEBUGGER)        += tegra_fiq_debugger.o
@@ -24,6 +32,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_dvfs.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_fuse.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += suspend-t2.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_save.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= tegra2_emc.o
@@ -32,13 +41,16 @@ obj-$(CONFIG_CPU_V7)			+= cortex-a9.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)		+= pinmux-t2-tables.o
 obj-$(CONFIG_SMP)                       += localtimer.o
 obj-$(CONFIG_SMP)                       += platsmp.o
+obj-y                                   += headsmp.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += headsmp-t2.o
-obj-$(CONFIG_TEGRA_SYSTEM_DMA)		+= dma.o
+obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
-obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
+obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_TEGRA_IOVMM)               += iovmm.o
 obj-$(CONFIG_TEGRA_IOVMM_GART)          += iovmm-gart.o
 
+obj-y                                   += nv/
+
 obj-${CONFIG_MACH_HARMONY}              += board-harmony.o
 obj-${CONFIG_MACH_HARMONY}              += board-harmony-pinmux.o
 obj-${CONFIG_MACH_HARMONY}              += board-harmony-panel.o
@@ -49,3 +61,15 @@ obj-${CONFIG_MACH_VENTANA}              += board-ventana-pinmux.o
 obj-${CONFIG_MACH_VENTANA}              += board-ventana-sdhci.o
 obj-${CONFIG_MACH_VENTANA}              += board-ventana-power.o
 obj-${CONFIG_MACH_VENTANA}              += board-ventana-panel.o
+obj-${CONFIG_MACH_VENTANA}              += board-ventana-sensors.o
+obj-${CONFIG_MACH_VENTANA}              += board-ventana-kbc.o
+obj-${CONFIG_MACH_VENTANA}              += board-ventana-memory.o
+
+obj-${CONFIG_MACH_WHISTLER}             += board-whistler.o
+obj-${CONFIG_MACH_WHISTLER}             += board-whistler-pinmux.o
+obj-${CONFIG_MACH_WHISTLER}             += board-whistler-sdhci.o
+obj-${CONFIG_MACH_WHISTLER}             += board-whistler-power.o
+obj-${CONFIG_MACH_WHISTLER}             += board-whistler-panel.o
+obj-${CONFIG_MACH_WHISTLER}             += board-whistler-sensors.o
+obj-${CONFIG_MACH_WHISTLER}             += board-whistler-kbc.o
+obj-${CONFIG_MACH_WHISTLER}             += board-whistler-baseband.o
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
new file mode 100644
index 000000000000..d6e08c966e72
--- /dev/null
+++ b/arch/arm/mach-tegra/apbio.c
@@ -0,0 +1,151 @@
+/*
+ * arch/arm/mach-tegra/apbio.c
+ *
+ * Copyright (C) 2010 NVIDIA Corporation.
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+#include <linux/sched.h>
+#include <linux/mutex.h>
+
+#include <mach/dma.h>
+#include <mach/iomap.h>
+
+#include "apbio.h"
+
+static DEFINE_MUTEX(tegra_apb_dma_lock);
+
+#ifdef CONFIG_TEGRA_SYSTEM_DMA
+static struct tegra_dma_channel *tegra_apb_dma;
+static u32 *tegra_apb_bb;
+static dma_addr_t tegra_apb_bb_phys;
+static DECLARE_COMPLETION(tegra_apb_wait);
+
+static void apb_dma_complete(struct tegra_dma_req *req)
+{
+	complete(&tegra_apb_wait);
+}
+
+static inline u32 apb_readl(unsigned long offset)
+{
+	struct tegra_dma_req req;
+	int ret;
+
+	if (!tegra_apb_dma)
+		return readl(IO_TO_VIRT(offset));
+
+	mutex_lock(&tegra_apb_dma_lock);
+	req.complete = apb_dma_complete;
+	req.to_memory = 1;
+	req.dest_addr = tegra_apb_bb_phys;
+	req.dest_bus_width = 32;
+	req.dest_wrap = 1;
+	req.source_addr = offset;
+	req.source_bus_width = 32;
+	req.source_wrap = 4;
+	req.req_sel = 0;
+	req.size = 4;
+
+	INIT_COMPLETION(tegra_apb_wait);
+
+	tegra_dma_enqueue_req(tegra_apb_dma, &req);
+
+	ret = wait_for_completion_timeout(&tegra_apb_wait,
+		msecs_to_jiffies(50));
+
+	if (WARN(ret == 0, "apb read dma timed out"))
+		*(u32 *)tegra_apb_bb = 0;
+
+	mutex_unlock(&tegra_apb_dma_lock);
+	return *((u32 *)tegra_apb_bb);
+}
+
+static inline void apb_writel(u32 value, unsigned long offset)
+{
+	struct tegra_dma_req req;
+	int ret;
+
+	if (!tegra_apb_dma) {
+		writel(value, IO_TO_VIRT(offset));
+		return;
+	}
+
+	mutex_lock(&tegra_apb_dma_lock);
+	*((u32 *)tegra_apb_bb) = value;
+	req.complete = apb_dma_complete;
+	req.to_memory = 0;
+	req.dest_addr = offset;
+	req.dest_wrap = 4;
+	req.dest_bus_width = 32;
+	req.source_addr = tegra_apb_bb_phys;
+	req.source_bus_width = 32;
+	req.source_wrap = 1;
+	req.req_sel = 0;
+	req.size = 4;
+
+	INIT_COMPLETION(tegra_apb_wait);
+
+	tegra_dma_enqueue_req(tegra_apb_dma, &req);
+
+	ret = wait_for_completion_timeout(&tegra_apb_wait,
+		msecs_to_jiffies(50));
+
+	mutex_unlock(&tegra_apb_dma_lock);
+}
+#else
+static inline u32 apb_readl(unsigned long offset)
+{
+	return readl(IO_TO_VIRT(offset));
+}
+
+static inline void apb_writel(u32 value, unsigned long offset)
+{
+	writel(value, IO_TO_VIRT(offset));
+}
+#endif
+
+u32 tegra_apb_readl(unsigned long offset)
+{
+	return apb_readl(offset);
+}
+
+void tegra_apb_writel(u32 value, unsigned long offset)
+{
+	apb_writel(value, offset);
+}
+
+void tegra_init_apb_dma(void)
+{
+#ifdef CONFIG_TEGRA_SYSTEM_DMA
+	tegra_apb_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
+		TEGRA_DMA_SHARED);
+	if (!tegra_apb_dma) {
+		pr_err("%s: can not allocate dma channel\n", __func__);
+		return;
+	}
+
+	tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
+		&tegra_apb_bb_phys, GFP_KERNEL);
+	if (!tegra_apb_bb) {
+		pr_err("%s: can not allocate bounce buffer\n", __func__);
+		tegra_dma_free_channel(tegra_apb_dma);
+		tegra_apb_dma = NULL;
+		return;
+	}
+#endif
+}
diff --git a/arch/arm/mach-tegra/apbio.h b/arch/arm/mach-tegra/apbio.h
new file mode 100644
index 000000000000..a8b8250c891a
--- /dev/null
+++ b/arch/arm/mach-tegra/apbio.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-tegra/apbio.h
+ *
+ * Copyright (C) 2010 NVIDIA Corporation.
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+u32 tegra_apb_readl(unsigned long offset);
+void tegra_apb_writel(u32 value, unsigned long offset);
+void tegra_init_apb_dma(void);
diff --git a/arch/arm/mach-tegra/board-harmony-panel.c b/arch/arm/mach-tegra/board-harmony-panel.c
index 309d72e4b490..8d4e8c7033a4 100644
--- a/arch/arm/mach-tegra/board-harmony-panel.c
+++ b/arch/arm/mach-tegra/board-harmony-panel.c
@@ -1,64 +1,240 @@
 /*
  * arch/arm/mach-tegra/board-harmony-panel.c
  *
- * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2010, NVIDIA Corporation.
  *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
  *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
 #include <linux/resource.h>
-#include <linux/platform_device.h>
 #include <asm/mach-types.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <mach/nvhost.h>
+#include <mach/nvmap.h>
 #include <mach/irqs.h>
 #include <mach/iomap.h>
-#include <mach/tegra_fb.h>
+#include <mach/dc.h>
+#include <mach/fb.h>
 
-/* Framebuffer */
-static struct resource fb_resource[] = {
-	[0] = {
-		.start  = INT_DISPLAY_GENERAL,
-		.end    = INT_DISPLAY_GENERAL,
-		.flags  = IORESOURCE_IRQ,
+#include "devices.h"
+#include "gpio-names.h"
+
+#define harmony_bl_enb		TEGRA_GPIO_PB5
+#define harmony_lvds_shutdown	TEGRA_GPIO_PB2
+#define harmony_en_vdd_pnl	TEGRA_GPIO_PC6
+#define harmony_bl_vdd		TEGRA_GPIO_PW0
+#define harmony_bl_pwm		TEGRA_GPIO_PB4
+
+static int harmony_backlight_init(struct device *dev)
+{
+	int ret;
+
+	ret = gpio_request(harmony_bl_enb, "backlight_enb");
+	if (ret < 0)
+		return ret;
+
+	ret = gpio_direction_output(harmony_bl_enb, 1);
+	if (ret < 0)
+		gpio_free(harmony_bl_enb);
+	else
+		tegra_gpio_enable(harmony_bl_enb);
+
+	return ret;
+};
+
+static void harmony_backlight_exit(struct device *dev)
+{
+	gpio_set_value(harmony_bl_enb, 0);
+	gpio_free(harmony_bl_enb);
+	tegra_gpio_disable(harmony_bl_enb);
+}
+
+static int harmony_backlight_notify(struct device *unused, int brightness)
+{
+	gpio_set_value(harmony_en_vdd_pnl, !!brightness);
+	gpio_set_value(harmony_lvds_shutdown, !!brightness);
+	gpio_set_value(harmony_bl_enb, !!brightness);
+	return brightness;
+}
+
+static struct platform_pwm_backlight_data harmony_backlight_data = {
+	.pwm_id		= 0,
+	.max_brightness	= 255,
+	.dft_brightness	= 224,
+	.pwm_period_ns	= 5000000,
+	.init		= harmony_backlight_init,
+	.exit		= harmony_backlight_exit,
+	.notify		= harmony_backlight_notify,
+};
+
+static struct platform_device harmony_backlight_device = {
+	.name	= "pwm-backlight",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &harmony_backlight_data,
 	},
-	[1] = {
+};
+
+static int harmony_panel_enable(void)
+{
+	gpio_set_value(harmony_lvds_shutdown, 1);
+	return 0;
+}
+
+static int harmony_panel_disable(void)
+{
+	gpio_set_value(harmony_lvds_shutdown, 0);
+	return 0;
+}
+
+static struct resource harmony_disp1_resources[] = {
+	{
+		.name	= "irq",
+		.start	= INT_DISPLAY_GENERAL,
+		.end	= INT_DISPLAY_GENERAL,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "regs",
 		.start	= TEGRA_DISPLAY_BASE,
 		.end	= TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
 		.flags	= IORESOURCE_MEM,
 	},
-	[2] = {
+	{
+		.name	= "fbmem",
 		.start	= 0x1c012000,
-		.end	= 0x1c012000 + 0x500000 - 1,
+		.end	= 0x1c012000 + 0x258000 - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 
-static struct tegra_fb_lcd_data tegra_fb_lcd_platform_data = {
-	.lcd_xres	= 1024,
-	.lcd_yres	= 600,
-	.fb_xres	= 1024,
-	.fb_yres	= 600,
+static struct tegra_dc_mode harmony_panel_modes[] = {
+	{
+		.pclk = 42430000,
+		.h_ref_to_sync = 4,
+		.v_ref_to_sync = 2,
+		.h_sync_width = 136,
+		.v_sync_width = 4,
+		.h_back_porch = 138,
+		.v_back_porch = 21,
+		.h_active = 1024,
+		.v_active = 600,
+		.h_front_porch = 34,
+		.v_front_porch = 4,
+	},
+};
+
+static struct tegra_fb_data harmony_fb_data = {
+	.win		= 0,
+	.xres		= 1024,
+	.yres		= 600,
 	.bits_per_pixel	= 16,
 };
 
-static struct platform_device tegra_fb_device = {
-	.name 		= "tegrafb",
+static struct tegra_dc_out harmony_disp1_out = {
+	.type		= TEGRA_DC_OUT_RGB,
+
+	.align		= TEGRA_DC_ALIGN_MSB,
+	.order		= TEGRA_DC_ORDER_RED_BLUE,
+
+	.modes		= harmony_panel_modes,
+	.n_modes	= ARRAY_SIZE(harmony_panel_modes),
+
+	.enable		= harmony_panel_enable,
+	.disable	= harmony_panel_disable,
+};
+
+static struct tegra_dc_platform_data harmony_disp1_pdata = {
+	.flags		= TEGRA_DC_FLAG_ENABLED,
+	.default_out	= &harmony_disp1_out,
+	.fb		= &harmony_fb_data,
+};
+
+static struct nvhost_device harmony_disp1_device = {
+	.name		= "tegradc",
 	.id		= 0,
-	.resource	= fb_resource,
-	.num_resources 	= ARRAY_SIZE(fb_resource),
+	.resource	= harmony_disp1_resources,
+	.num_resources	= ARRAY_SIZE(harmony_disp1_resources),
 	.dev = {
-		.platform_data = &tegra_fb_lcd_platform_data,
+		.platform_data = &harmony_disp1_pdata,
+	},
+};
+
+static struct nvmap_platform_carveout harmony_carveouts[] = {
+	[0] = {
+		.name		= "iram",
+		.usage_mask	= NVMAP_HEAP_CARVEOUT_IRAM,
+		.base		= TEGRA_IRAM_BASE,
+		.size		= TEGRA_IRAM_SIZE,
+		.buddy_size	= 0, /* no buddy allocation for IRAM */
+	},
+	[1] = {
+		.name		= "generic-0",
+		.usage_mask	= NVMAP_HEAP_CARVEOUT_GENERIC,
+		.base		= 0x18C00000,
+		.size		= SZ_128M - 0xC00000,
+		.buddy_size	= SZ_32K,
 	},
 };
 
-int __init harmony_panel_init(void) {
-	return platform_device_register(&tegra_fb_device);
+static struct nvmap_platform_data harmony_nvmap_data = {
+	.carveouts	= harmony_carveouts,
+	.nr_carveouts	= ARRAY_SIZE(harmony_carveouts),
+};
+
+static struct platform_device harmony_nvmap_device = {
+	.name	= "tegra-nvmap",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &harmony_nvmap_data,
+	},
+};
+
+static struct platform_device *harmony_gfx_devices[] __initdata = {
+	&harmony_nvmap_device,
+	&tegra_grhost_device,
+	&tegra_pwfm0_device,
+	&harmony_backlight_device,
+};
+
+int __init harmony_panel_init(void)
+{
+	int err;
+
+	gpio_request(harmony_en_vdd_pnl, "en_vdd_pnl");
+	gpio_direction_output(harmony_en_vdd_pnl, 1);
+	tegra_gpio_enable(harmony_en_vdd_pnl);
+
+	gpio_request(harmony_bl_vdd, "bl_vdd");
+	gpio_direction_output(harmony_bl_vdd, 1);
+	tegra_gpio_enable(harmony_bl_vdd);
+
+	gpio_request(harmony_lvds_shutdown, "lvds_shdn");
+	gpio_direction_output(harmony_lvds_shutdown, 1);
+	tegra_gpio_enable(harmony_lvds_shutdown);
+
+	err = platform_add_devices(harmony_gfx_devices,
+				   ARRAY_SIZE(harmony_gfx_devices));
+
+	if (!err)
+		err = nvhost_device_register(&harmony_disp1_device);
+
+	return err;
 }
 
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
index 78980e48970f..e5451a1f55dc 100644
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -26,7 +26,7 @@ static __initdata struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
@@ -104,7 +104,7 @@ static __initdata struct tegra_pingroup_config harmony_pinmux[] = {
 	{TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index ee01dd0ae7cd..2fe10590823c 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -23,23 +23,29 @@
 #include <linux/mtd/partitions.h>
 #include <linux/dma-mapping.h>
 #include <linux/pda_power.h>
+#include <linux/i2c.h>
+#include <linux/i2c-tegra.h>
 #include <linux/io.h>
 #include <linux/delay.h>
+#include <linux/tegra_usb.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/setup.h>
 
+#include <mach/audio.h>
+#include <mach/i2s.h>
 #include <mach/iomap.h>
 #include <mach/irqs.h>
 #include <mach/nand.h>
 #include <mach/clk.h>
+#include <mach/usb_phy.h>
+#include <mach/suspend.h>
 
 #include "clock.h"
 #include "board.h"
 #include "board-harmony.h"
-#include "clock.h"
 #include "devices.h"
 
 /* NVidia bootloader tags */
@@ -62,11 +68,26 @@ struct tag_tegra {
 
 static int __init parse_tag_nvidia(const struct tag *tag)
 {
-
 	return 0;
 }
 __tagtable(ATAG_NVIDIA, parse_tag_nvidia);
 
+static struct tegra_utmip_config utmi_phy_config = {
+	.hssync_start_delay = 0,
+	.idle_wait_delay = 17,
+	.elastic_limit = 16,
+	.term_range_adj = 6,
+	.xcvr_setup = 9,
+	.xcvr_lsfslew = 2,
+	.xcvr_lsrslew = 2,
+};
+
+static struct tegra_ehci_platform_data tegra_ehci_pdata = {
+	.phy_config = &utmi_phy_config,
+	.operating_mode = TEGRA_USB_HOST,
+	.power_down_on_bus_suspend = 1,
+};
+
 static struct tegra_nand_chip_parms nand_chip_parms[] = {
 	/* Samsung K5E2G1GACM */
 	[0] = {
@@ -164,21 +185,90 @@ static struct platform_device pda_power_device = {
 	},
 };
 
+static struct tegra_i2c_platform_data harmony_i2c1_platform_data = {
+	.adapter_nr	= 0,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 400000, 0 },
+};
+
+static const struct tegra_pingroup_config i2c2_ddc = {
+	.pingroup	= TEGRA_PINGROUP_DDC,
+	.func		= TEGRA_MUX_I2C2,
+};
+
+static const struct tegra_pingroup_config i2c2_gen2 = {
+	.pingroup	= TEGRA_PINGROUP_PTA,
+	.func		= TEGRA_MUX_I2C2,
+};
+
+static struct tegra_i2c_platform_data harmony_i2c2_platform_data = {
+	.adapter_nr	= 1,
+	.bus_count	= 2,
+	.bus_clk_rate	= { 400000, 100000 },
+	.bus_mux	= { &i2c2_ddc, &i2c2_gen2 },
+	.bus_mux_len	= { 1, 1 },
+};
+
+static struct tegra_i2c_platform_data harmony_i2c3_platform_data = {
+	.adapter_nr	= 3,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 400000, 0 },
+};
+
+static struct tegra_i2c_platform_data harmony_dvc_platform_data = {
+	.adapter_nr	= 4,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 400000, 0 },
+	.is_dvc		= true,
+};
+
+static struct i2c_board_info __initdata harmony_i2c_bus1_board_info[] = {
+	{
+		I2C_BOARD_INFO("wm8903", 0x1a),
+	},
+};
+
+static struct tegra_audio_platform_data tegra_audio_pdata = {
+	.i2s_master	= false,
+	.dsp_master	= false,
+	.dma_on		= true,  /* use dma by default */
+	.i2s_clk_rate	= 240000000,
+	.dap_clk	= "clk_dev1",
+	.audio_sync_clk = "audio_2x",
+	.mode		= I2S_BIT_FORMAT_I2S,
+	.fifo_fmt	= I2S_FIFO_16_LSB,
+	.bit_size	= I2S_BIT_SIZE_16,
+};
+
+static void harmony_i2c_init(void)
+{
+	tegra_i2c_device1.dev.platform_data = &harmony_i2c1_platform_data;
+	tegra_i2c_device2.dev.platform_data = &harmony_i2c2_platform_data;
+	tegra_i2c_device3.dev.platform_data = &harmony_i2c3_platform_data;
+	tegra_i2c_device4.dev.platform_data = &harmony_dvc_platform_data;
+
+	platform_device_register(&tegra_i2c_device1);
+	platform_device_register(&tegra_i2c_device2);
+	platform_device_register(&tegra_i2c_device3);
+	platform_device_register(&tegra_i2c_device4);
+
+	i2c_register_board_info(0, harmony_i2c_bus1_board_info,
+				ARRAY_SIZE(harmony_i2c_bus1_board_info));
+}
+
 static struct platform_device *harmony_devices[] __initdata = {
 	&debug_uart,
 	&pmu_device,
 	&tegra_nand_device,
 	&tegra_udc_device,
 	&pda_power_device,
-	&tegra_i2c_device1,
-	&tegra_i2c_device2,
-	&tegra_i2c_device3,
-	&tegra_i2c_device4,
+	&tegra_ehci3_device,
 	&tegra_spi_device1,
 	&tegra_spi_device2,
 	&tegra_spi_device3,
 	&tegra_spi_device4,
 	&tegra_gart_device,
+	&tegra_i2s_device1,
 };
 
 static void __init tegra_harmony_fixup(struct machine_desc *desc,
@@ -193,22 +283,124 @@ static void __init tegra_harmony_fixup(struct machine_desc *desc,
 
 static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
 	/* name		parent		rate		enabled */
-	{ "uartd",	"pll_p",	216000000,	true },
+	{ "clk_dev1",	NULL,		26000000,	true},
+	{ "clk_m",	NULL,		12000000,	true},
+	{ "3d",		"pll_m",	266400000,	true},
+	{ "2d",		"pll_m",	266400000,	true},
+	{ "vi",		"pll_m",	50000000,	true},
+	{ "vi_sensor",	"pll_m",	111000000,	false},
+	{ "epp",	"pll_m",	266400000,	true},
+	{ "mpe",	"pll_m",	111000000,	false},
+	{ "emc",	"pll_m",	666000000,	true},
+	{ "pll_c",	"clk_m",	600000000,	true},
+	{ "pll_c_out1",	"pll_c",	240000000,	true},
+	{ "vde",	"pll_c",	240000000,	false},
+	{ "pll_p",	"clk_m",	216000000,	true},
+	{ "pll_p_out1",	"pll_p",	28800000,	true},
+	{ "pll_a",	"pll_p_out1",	56448000,	true},
+	{ "pll_a_out0",	"pll_a",	11289600,	true},
+	{ "i2s1",	"pll_a_out0",	11289600,	true},
+	{ "audio",	"pll_a_out0",	11289600,	true},
+	{ "audio_2x",	"audio",	22579200,	false},
+	{ "pll_p_out2",	"pll_p",	48000000,	true},
+	{ "pll_p_out3",	"pll_p",	72000000,	true},
+	{ "i2c1_i2c",	"pll_p_out3",	72000000,	true},
+	{ "i2c2_i2c",	"pll_p_out3",	72000000,	true},
+	{ "i2c3_i2c",	"pll_p_out3",	72000000,	true},
+	{ "dvc_i2c",	"pll_p_out3",	72000000,	true},
+	{ "csi",	"pll_p_out3",	72000000,	false},
+	{ "pll_p_out4",	"pll_p",	108000000,	true},
+	{ "sclk",	"pll_p_out4",	108000000,	true},
+	{ "hclk",	"sclk",		108000000,	true},
+	{ "pclk",	"hclk",		54000000,	true},
+	{ "apbdma",	"hclk",		54000000,	true},
+	{ "spdif_in",	"pll_p",	36000000,	false},
+	{ "csite",	"pll_p",	144000000,	true},
+	{ "uartd",	"pll_p",	216000000,	true},
+	{ "host1x",	"pll_p",	144000000,	true},
+	{ "disp1",	"pll_p",	216000000,	true},
+	{ "pll_d",	"clk_m",	1000000,	false},
+	{ "pll_d_out0",	"pll_d",	500000,		false},
+	{ "dsi",	"pll_d",	1000000,	false},
+	{ "pll_u",	"clk_m",	480000000,	true},
+	{ "clk_d",	"clk_m",	24000000,	true},
+	{ "timer",	"clk_m",	12000000,	true},
+	{ "i2s2",	"clk_m",	11289600,	false},
+	{ "spdif_out",	"clk_m",	12000000,	false},
+	{ "spi",	"clk_m",	12000000,	false},
+	{ "xio",	"clk_m",	12000000,	false},
+	{ "twc",	"clk_m",	12000000,	false},
+	{ "sbc1",	"clk_m",	12000000,	false},
+	{ "sbc2",	"clk_m",	12000000,	false},
+	{ "sbc3",	"clk_m",	12000000,	false},
+	{ "sbc4",	"clk_m",	12000000,	false},
+	{ "ide",	"clk_m",	12000000,	false},
+	{ "ndflash",	"clk_m",	108000000,	true},
+	{ "vfir",	"clk_m",	12000000,	false},
+	{ "sdmmc1",	"clk_m",	48000000,	true},
+	{ "sdmmc2",	"clk_m",	48000000,	true},
+	{ "sdmmc3",	"clk_m",	48000000,	false},
+	{ "sdmmc4",	"clk_m",	48000000,	true},
+	{ "la",		"clk_m",	12000000,	false},
+	{ "owr",	"clk_m",	12000000,	false},
+	{ "nor",	"clk_m",	12000000,	false},
+	{ "mipi",	"clk_m",	12000000,	false},
+	{ "i2c1",	"clk_m",	3000000,	false},
+	{ "i2c2",	"clk_m",	3000000,	false},
+	{ "i2c3",	"clk_m",	3000000,	false},
+	{ "dvc",	"clk_m",	3000000,	false},
+	{ "uarta",	"clk_m",	12000000,	false},
+	{ "uartb",	"clk_m",	12000000,	false},
+	{ "uartc",	"clk_m",	12000000,	false},
+	{ "uarte",	"clk_m",	12000000,	false},
+	{ "cve",	"clk_m",	12000000,	false},
+	{ "tvo",	"clk_m",	12000000,	false},
+	{ "hdmi",	"clk_m",	12000000,	false},
+	{ "tvdac",	"clk_m",	12000000,	false},
+	{ "disp2",	"clk_m",	12000000,	false},
+	{ "usbd",	"clk_m",	12000000,	false},
+	{ "usb2",	"clk_m",	12000000,	false},
+	{ "usb3",	"clk_m",	12000000,	true},
+	{ "isp",	"clk_m",	12000000,	false},
+	{ "csus",	"clk_m",	12000000,	false},
+	{ "pwm",	"clk_32k",	32768,		false},
+	{ "clk_32k",	NULL,		32768,		true},
+	{ "pll_s",	"clk_32k",	32768,		false},
+	{ "rtc",	"clk_32k",	32768,		true},
+	{ "kbc",	"clk_32k",	32768,		true},
 	{ NULL,		NULL,		0,		0},
 };
 
+static struct tegra_suspend_platform_data harmony_suspend = {
+	.cpu_timer = 5000,
+	.cpu_off_timer = 5000,
+	.core_timer = 0x7e7e,
+	.core_off_timer = 0x7f,
+	.separate_req = true,
+	.corereq_high = false,
+	.sysclkreq_high = true,
+	.suspend_mode = TEGRA_SUSPEND_LP0,
+};
+
 static void __init tegra_harmony_init(void)
 {
 	tegra_common_init();
 
+	tegra_init_suspend(&harmony_suspend);
+
 	tegra_clk_init_from_table(harmony_clk_init_table);
 
 	harmony_pinmux_init();
 
+	tegra_ehci3_device.dev.platform_data = &tegra_ehci_pdata;
+
+	tegra_i2s_device1.dev.platform_data = &tegra_audio_pdata;
+
 	platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
 
 	harmony_panel_init();
 	harmony_sdhci_init();
+	harmony_i2c_init();
 }
 
 MACHINE_START(HARMONY, "harmony")
diff --git a/arch/arm/mach-tegra/board-ventana-kbc.c b/arch/arm/mach-tegra/board-ventana-kbc.c
new file mode 100644
index 000000000000..1fb9d68c9ed4
--- /dev/null
+++ b/arch/arm/mach-tegra/board-ventana-kbc.c
@@ -0,0 +1,142 @@
+/*
+ * Copyright (C) 2010 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+/*
+* Warning: Ventana might need some hardware rework to be able to work with
+* kbc-driver. Default Ventana h/w configuration should use GPIO keyboard
+* driver instead
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/device.h>
+
+#include <mach/clk.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/iomap.h>
+#include <mach/io.h>
+#include <mach/kbc.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#define VENTANA_ROW_COUNT	15
+#define VENTANA_COL_COUNT	7
+
+static int plain_kbd_keycode[] = {
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+			KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED, KEY_HOME, KEY_BACK, KEY_MENU,
+			KEY_VOLUMEDOWN, KEY_VOLUMEUP, KEY_RESERVED,
+};
+
+static struct tegra_kbc_wake_key ventana_wake_cfg[] = {
+	[0] = {
+		.row = 14,
+		.col = 1,
+	},
+};
+
+static struct tegra_kbc_platform_data ventana_kbc_platform_data = {
+	.debounce_cnt = 20,
+	.repeat_cnt = 50 * 32,
+	.scan_timeout_cnt = 3000 * 32,
+	.plain_keycode = plain_kbd_keycode,
+	.fn_keycode = NULL,
+	.is_filter_keys = false,
+	.is_wake_on_any_key = false,
+	.wake_key_cnt = 1,
+	.wake_cfg = &ventana_wake_cfg[0],
+};
+
+static struct resource ventana_kbc_resources[] = {
+	[0] = {
+		.start = TEGRA_KBC_BASE,
+		.end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = INT_KBC,
+		.end   = INT_KBC,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device ventana_kbc_device = {
+	.name = "tegra-kbc",
+	.id = -1,
+	.dev = {
+		.platform_data = &ventana_kbc_platform_data,
+	},
+	.resource = ventana_kbc_resources,
+	.num_resources = ARRAY_SIZE(ventana_kbc_resources),
+};
+
+int __init ventana_kbc_init(void)
+{
+	struct tegra_kbc_platform_data *data = &ventana_kbc_platform_data;
+	int i;
+
+	pr_info("KBC: ventana_kbc_init\n");
+
+	/* Setup the pin configuration information. */
+	for (i = 0; i < KBC_MAX_GPIO; i++) {
+		data->pin_cfg[i].num = 0;
+		data->pin_cfg[i].pin_type = kbc_pin_unused;
+	}
+	for (i = 0; i < VENTANA_ROW_COUNT; i++) {
+		data->pin_cfg[i].num = i;
+		data->pin_cfg[i].pin_type = kbc_pin_row;
+	}
+
+	for (i = 0; i < VENTANA_COL_COUNT; i++) {
+		data->pin_cfg[i + VENTANA_ROW_COUNT].num = i;
+		data->pin_cfg[i + VENTANA_ROW_COUNT].pin_type = kbc_pin_col;
+	}
+	platform_device_register(&ventana_kbc_device);
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-ventana-memory.c b/arch/arm/mach-tegra/board-ventana-memory.c
new file mode 100644
index 000000000000..95f51dfb2ce9
--- /dev/null
+++ b/arch/arm/mach-tegra/board-ventana-memory.c
@@ -0,0 +1,508 @@
+/*
+ * Copyright (C) 2010 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "board-ventana.h"
+#include "tegra2_emc.h"
+#include "board.h"
+
+static const struct tegra_emc_table ventana_emc_tables_elpida_300Mhz[] = {
+	{
+		.rate = 50000,   /* SDRAM frequency */
+		.regs = {
+			0x00000003,   /* RC */
+			0x00000007,   /* RFC */
+			0x00000003,   /* RAS */
+			0x00000003,   /* RP */
+			0x00000006,   /* R2W */
+			0x00000004,   /* W2R */
+			0x00000002,   /* R2P */
+			0x00000009,   /* W2P */
+			0x00000003,   /* RD_RCD */
+			0x00000003,   /* WR_RCD */
+			0x00000002,   /* RRD */
+			0x00000002,   /* REXT */
+			0x00000002,   /* WDV */
+			0x00000005,   /* QUSE */
+			0x00000003,   /* QRST */
+			0x00000008,   /* QSAFE */
+			0x0000000b,   /* RDV */
+			0x0000009f,   /* REFRESH */
+			0x00000000,   /* BURST_REFRESH_NUM */
+			0x00000003,   /* PDEX2WR */
+			0x00000003,   /* PDEX2RD */
+			0x00000003,   /* PCHG2PDEN */
+			0x00000008,   /* ACT2PDEN */
+			0x00000001,   /* AR2PDEN */
+			0x0000000a,   /* RW2PDEN */
+			0x00000007,   /* TXSR */
+			0x00000003,   /* TCKE */
+			0x00000008,   /* TFAW */
+			0x00000004,   /* TRPAB */
+			0x00000006,   /* TCLKSTABLE */
+			0x00000002,   /* TCLKSTOP */
+			0x000000d0,   /* TREFBW */
+			0x00000004,   /* QUSE_EXTRA */
+			0x00000000,   /* FBIO_CFG6 */
+			0x00000000,   /* ODT_WRITE */
+			0x00000000,   /* ODT_READ */
+			0x00000082,   /* FBIO_CFG5 */
+			0xa06a04ae,   /* CFG_DIG_DLL */
+			0x0001f000,   /* DLL_XFORM_DQS */
+			0x00000000,   /* DLL_XFORM_QUSE */
+			0x00000000,   /* ZCAL_REF_CNT */
+			0x00000005,   /* ZCAL_WAIT_CNT */
+			0x00000000,   /* AUTO_CAL_INTERVAL */
+			0x00000000,   /* CFG_CLKTRIM_0 */
+			0x00000000,   /* CFG_CLKTRIM_1 */
+			0x00000000,   /* CFG_CLKTRIM_2 */
+		}
+	},
+	{
+		.rate = 75000,   /* SDRAM frequency */
+		.regs = {
+			0x00000005,   /* RC */
+			0x0000000a,   /* RFC */
+			0x00000004,   /* RAS */
+			0x00000003,   /* RP */
+			0x00000006,   /* R2W */
+			0x00000004,   /* W2R */
+			0x00000002,   /* R2P */
+			0x00000009,   /* W2P */
+			0x00000003,   /* RD_RCD */
+			0x00000003,   /* WR_RCD */
+			0x00000002,   /* RRD */
+			0x00000002,   /* REXT */
+			0x00000002,   /* WDV */
+			0x00000005,   /* QUSE */
+			0x00000003,   /* QRST */
+			0x00000008,   /* QSAFE */
+			0x0000000b,   /* RDV */
+			0x000000ff,   /* REFRESH */
+			0x00000000,   /* BURST_REFRESH_NUM */
+			0x00000003,   /* PDEX2WR */
+			0x00000003,   /* PDEX2RD */
+			0x00000003,   /* PCHG2PDEN */
+			0x00000008,   /* ACT2PDEN */
+			0x00000001,   /* AR2PDEN */
+			0x0000000a,   /* RW2PDEN */
+			0x0000000b,   /* TXSR */
+			0x00000003,   /* TCKE */
+			0x00000008,   /* TFAW */
+			0x00000004,   /* TRPAB */
+			0x00000006,   /* TCLKSTABLE */
+			0x00000002,   /* TCLKSTOP */
+			0x00000138,   /* TREFBW */
+			0x00000004,   /* QUSE_EXTRA */
+			0x00000000,   /* FBIO_CFG6 */
+			0x00000000,   /* ODT_WRITE */
+			0x00000000,   /* ODT_READ */
+			0x00000082,   /* FBIO_CFG5 */
+			0xa06a04ae,   /* CFG_DIG_DLL */
+			0x0001f000,   /* DLL_XFORM_DQS */
+			0x00000000,   /* DLL_XFORM_QUSE */
+			0x00000000,   /* ZCAL_REF_CNT */
+			0x00000007,   /* ZCAL_WAIT_CNT */
+			0x00000000,   /* AUTO_CAL_INTERVAL */
+			0x00000000,   /* CFG_CLKTRIM_0 */
+			0x00000000,   /* CFG_CLKTRIM_1 */
+			0x00000000,   /* CFG_CLKTRIM_2 */
+		}
+	},
+	{
+		.rate = 150000,   /* SDRAM frequency */
+		.regs = {
+			0x00000009,   /* RC */
+			0x00000014,   /* RFC */
+			0x00000007,   /* RAS */
+			0x00000004,   /* RP */
+			0x00000006,   /* R2W */
+			0x00000004,   /* W2R */
+			0x00000002,   /* R2P */
+			0x00000009,   /* W2P */
+			0x00000003,   /* RD_RCD */
+			0x00000003,   /* WR_RCD */
+			0x00000002,   /* RRD */
+			0x00000002,   /* REXT */
+			0x00000002,   /* WDV */
+			0x00000005,   /* QUSE */
+			0x00000003,   /* QRST */
+			0x00000008,   /* QSAFE */
+			0x0000000b,   /* RDV */
+			0x0000021f,   /* REFRESH */
+			0x00000000,   /* BURST_REFRESH_NUM */
+			0x00000003,   /* PDEX2WR */
+			0x00000003,   /* PDEX2RD */
+			0x00000004,   /* PCHG2PDEN */
+			0x00000008,   /* ACT2PDEN */
+			0x00000001,   /* AR2PDEN */
+			0x0000000a,   /* RW2PDEN */
+			0x00000015,   /* TXSR */
+			0x00000003,   /* TCKE */
+			0x00000008,   /* TFAW */
+			0x00000004,   /* TRPAB */
+			0x00000006,   /* TCLKSTABLE */
+			0x00000002,   /* TCLKSTOP */
+			0x00000270,   /* TREFBW */
+			0x00000000,   /* QUSE_EXTRA */
+			0x00000001,   /* FBIO_CFG6 */
+			0x00000000,   /* ODT_WRITE */
+			0x00000000,   /* ODT_READ */
+			0x00000082,   /* FBIO_CFG5 */
+			0xA04C04AE,   /* CFG_DIG_DLL */
+			0x007FC010,   /* DLL_XFORM_DQS */
+			0x00000000,   /* DLL_XFORM_QUSE */
+			0x00000000,   /* ZCAL_REF_CNT */
+			0x0000000e,   /* ZCAL_WAIT_CNT */
+			0x00000000,   /* AUTO_CAL_INTERVAL */
+			0x00000000,   /* CFG_CLKTRIM_0 */
+			0x00000000,   /* CFG_CLKTRIM_1 */
+			0x00000000,   /* CFG_CLKTRIM_2 */
+		}
+	},
+	{
+		.rate = 300000,   /* SDRAM frequency */
+		.regs = {
+			0x00000012,   /* RC */
+			0x00000027,   /* RFC */
+			0x0000000D,   /* RAS */
+			0x00000007,   /* RP */
+			0x00000007,   /* R2W */
+			0x00000005,   /* W2R */
+			0x00000003,   /* R2P */
+			0x00000009,   /* W2P */
+			0x00000006,   /* RD_RCD */
+			0x00000006,   /* WR_RCD */
+			0x00000003,   /* RRD */
+			0x00000003,   /* REXT */
+			0x00000002,   /* WDV */
+			0x00000006,   /* QUSE */
+			0x00000003,   /* QRST */
+			0x00000009,   /* QSAFE */
+			0x0000000c,   /* RDV */
+			0x0000045f,   /* REFRESH */
+			0x00000000,   /* BURST_REFRESH_NUM */
+			0x00000004,   /* PDEX2WR */
+			0x00000004,   /* PDEX2RD */
+			0x00000007,   /* PCHG2PDEN */
+			0x00000008,   /* ACT2PDEN */
+			0x00000001,   /* AR2PDEN */
+			0x0000000e,   /* RW2PDEN */
+			0x0000002A,   /* TXSR */
+			0x00000003,   /* TCKE */
+			0x0000000F,   /* TFAW */
+			0x00000008,   /* TRPAB */
+			0x00000005,   /* TCLKSTABLE */
+			0x00000002,   /* TCLKSTOP */
+			0x000004E1,   /* TREFBW */
+			0x00000005,   /* QUSE_EXTRA */
+			0x00000002,   /* FBIO_CFG6 */
+			0x00000000,   /* ODT_WRITE */
+			0x00000000,   /* ODT_READ */
+			0x00000282,   /* FBIO_CFG5 */
+			0xE03C048B,   /* CFG_DIG_DLL */
+			0x007FC010,   /* DLL_XFORM_DQS */
+			0x00000000,   /* DLL_XFORM_QUSE */
+			0x00000000,   /* ZCAL_REF_CNT */
+			0x0000001B,   /* ZCAL_WAIT_CNT */
+			0x00000000,   /* AUTO_CAL_INTERVAL */
+			0x00000000,   /* CFG_CLKTRIM_0 */
+			0x00000000,   /* CFG_CLKTRIM_1 */
+			0x00000000,   /* CFG_CLKTRIM_2 */
+		}
+	}
+};
+
+static const struct tegra_emc_table ventana_emc_tables_elpida_400Mhz[] = {
+	{
+		.rate = 23750,   /* SDRAM frquency */
+		.regs = {
+			0x00000002,   /* RC */
+			0x00000006,   /* RFC */
+			0x00000003,   /* RAS */
+			0x00000003,   /* RP */
+			0x00000006,   /* R2W */
+			0x00000004,   /* W2R */
+			0x00000002,   /* R2P */
+			0x0000000b,   /* W2P */
+			0x00000003,   /* RD_RCD */
+			0x00000003,   /* WR_RCD */
+			0x00000002,   /* RRD */
+			0x00000002,   /* REXT */
+			0x00000003,   /* WDV */
+			0x00000005,   /* QUSE */
+			0x00000004,   /* QRST */
+			0x00000008,   /* QSAFE */
+			0x0000000c,   /* RDV */
+			0x00000047,   /* REFRESH */
+			0x00000000,   /* BURST_REFRESH_NUM */
+			0x00000003,   /* PDEX2WR */
+			0x00000003,   /* PDEX2RD */
+			0x00000003,   /* PCHG2PDEN */
+			0x00000008,   /* ACT2PDEN */
+			0x00000001,   /* AR2PDEN */
+			0x0000000b,   /* RW2PDEN */
+			0x00000004,   /* TXSR */
+			0x00000003,   /* TCKE */
+			0x00000008,   /* TFAW */
+			0x00000004,   /* TRPAB */
+			0x00000008,   /* TCLKSTABLE */
+			0x00000002,   /* TCLKSTOP */
+			0x00000060,   /* TREFBW */
+			0x00000004,   /* QUSE_EXTRA */
+			0x00000003,   /* FBIO_CFG6 */
+			0x00000000,   /* ODT_WRITE */
+			0x00000000,   /* ODT_READ */
+			0x00000082,   /* FBIO_CFG5 */
+			0xa0ae04ae,   /* CFG_DIG_DLL */
+			0x0001f800,   /* DLL_XFORM_DQS */
+			0x00000000,   /* DLL_XFORM_QUSE */
+			0x00000000,   /* ZCAL_REF_CNT */
+			0x00000003,   /* ZCAL_WAIT_CNT */
+			0x00000000,   /* AUTO_CAL_INTERVAL */
+			0x00000000,   /* CFG_CLKTRIM_0 */
+			0x00000000,   /* CFG_CLKTRIM_1 */
+			0x00000000,   /* CFG_CLKTRIM_2 */
+		}
+	},
+	{
+		.rate = 63333,   /* SDRAM frquency */
+		.regs = {
+			0x00000004,   /* RC */
+			0x00000009,   /* RFC */
+			0x00000003,   /* RAS */
+			0x00000003,   /* RP */
+			0x00000006,   /* R2W */
+			0x00000004,   /* W2R */
+			0x00000002,   /* R2P */
+			0x0000000b,   /* W2P */
+			0x00000003,   /* RD_RCD */
+			0x00000003,   /* WR_RCD */
+			0x00000002,   /* RRD */
+			0x00000002,   /* REXT */
+			0x00000003,   /* WDV */
+			0x00000006,   /* QUSE */
+			0x00000004,   /* QRST */
+			0x00000008,   /* QSAFE */
+			0x0000000c,   /* RDV */
+			0x000000c4,   /* REFRESH */
+			0x00000000,   /* BURST_REFRESH_NUM */
+			0x00000003,   /* PDEX2WR */
+			0x00000003,   /* PDEX2RD */
+			0x00000003,   /* PCHG2PDEN */
+			0x00000008,   /* ACT2PDEN */
+			0x00000001,   /* AR2PDEN */
+			0x0000000b,   /* RW2PDEN */
+			0x00000009,   /* TXSR */
+			0x00000003,   /* TCKE */
+			0x00000008,   /* TFAW */
+			0x00000004,   /* TRPAB */
+			0x00000008,   /* TCLKSTABLE */
+			0x00000002,   /* TCLKSTOP */
+			0x00000107,   /* TREFBW */
+			0x00000005,   /* QUSE_EXTRA */
+			0x00000000,   /* FBIO_CFG6 */
+			0x00000000,   /* ODT_WRITE */
+			0x00000000,   /* ODT_READ */
+			0x00000082,   /* FBIO_CFG5 */
+			0xa0ae04ae,   /* CFG_DIG_DLL */
+			0x0001f800,   /* DLL_XFORM_DQS */
+			0x00000000,   /* DLL_XFORM_QUSE */
+			0x00000000,   /* ZCAL_REF_CNT */
+			0x00000006,   /* ZCAL_WAIT_CNT */
+			0x00000000,   /* AUTO_CAL_INTERVAL */
+			0x00000000,   /* CFG_CLKTRIM_0 */
+			0x00000000,   /* CFG_CLKTRIM_1 */
+			0x00000000,   /* CFG_CLKTRIM_2 */
+		}
+	},
+	{
+		.rate = 95000,   /* SDRAM frquency */
+		.regs = {
+			0x00000006,   /* RC */
+			0x0000000d,   /* RFC */
+			0x00000004,   /* RAS */
+			0x00000003,   /* RP */
+			0x00000006,   /* R2W */
+			0x00000004,   /* W2R */
+			0x00000002,   /* R2P */
+			0x0000000b,   /* W2P */
+			0x00000003,   /* RD_RCD */
+			0x00000003,   /* WR_RCD */
+			0x00000002,   /* RRD */
+			0x00000002,   /* REXT */
+			0x00000003,   /* WDV */
+			0x00000006,   /* QUSE */
+			0x00000004,   /* QRST */
+			0x00000008,   /* QSAFE */
+			0x0000000c,   /* RDV */
+			0x0000013f,   /* REFRESH */
+			0x00000000,   /* BURST_REFRESH_NUM */
+			0x00000003,   /* PDEX2WR */
+			0x00000003,   /* PDEX2RD */
+			0x00000003,   /* PCHG2PDEN */
+			0x00000008,   /* ACT2PDEN */
+			0x00000001,   /* AR2PDEN */
+			0x0000000b,   /* RW2PDEN */
+			0x0000000e,   /* TXSR */
+			0x00000003,   /* TCKE */
+			0x00000008,   /* TFAW */
+			0x00000004,   /* TRPAB */
+			0x00000008,   /* TCLKSTABLE */
+			0x00000002,   /* TCLKSTOP */
+			0x0000018c,   /* TREFBW */
+			0x00000005,   /* QUSE_EXTRA */
+			0x00000001,   /* FBIO_CFG6 */
+			0x00000000,   /* ODT_WRITE */
+			0x00000000,   /* ODT_READ */
+			0x00000082,   /* FBIO_CFG5 */
+			0xa0ae04ae,   /* CFG_DIG_DLL */
+			0x0001f000,   /* DLL_XFORM_DQS */
+			0x00000000,   /* DLL_XFORM_QUSE */
+			0x00000000,   /* ZCAL_REF_CNT */
+			0x00000009,   /* ZCAL_WAIT_CNT */
+			0x00000000,   /* AUTO_CAL_INTERVAL */
+			0x00000000,   /* CFG_CLKTRIM_0 */
+			0x00000000,   /* CFG_CLKTRIM_1 */
+			0x00000000,   /* CFG_CLKTRIM_2 */
+		}
+	},
+	{
+		.rate = 190000,   /* SDRAM frquency */
+		.regs = {
+			0x0000000c,   /* RC */
+			0x00000019,   /* RFC */
+			0x00000008,   /* RAS */
+			0x00000004,   /* RP */
+			0x00000007,   /* R2W */
+			0x00000004,   /* W2R */
+			0x00000002,   /* R2P */
+			0x0000000b,   /* W2P */
+			0x00000004,   /* RD_RCD */
+			0x00000004,   /* WR_RCD */
+			0x00000002,   /* RRD */
+			0x00000003,   /* REXT */
+			0x00000003,   /* WDV */
+			0x00000006,   /* QUSE */
+			0x00000004,   /* QRST */
+			0x00000009,   /* QSAFE */
+			0x0000000d,   /* RDV */
+			0x000002bf,   /* REFRESH */
+			0x00000000,   /* BURST_REFRESH_NUM */
+			0x00000003,   /* PDEX2WR */
+			0x00000003,   /* PDEX2RD */
+			0x00000004,   /* PCHG2PDEN */
+			0x00000008,   /* ACT2PDEN */
+			0x00000001,   /* AR2PDEN */
+			0x0000000c,   /* RW2PDEN */
+			0x0000001b,   /* TXSR */
+			0x00000003,   /* TCKE */
+			0x0000000a,   /* TFAW */
+			0x00000004,   /* TRPAB */
+			0x00000008,   /* TCLKSTABLE */
+			0x00000002,   /* TCLKSTOP */
+			0x00000317,   /* TREFBW */
+			0x00000005,   /* QUSE_EXTRA */
+			0x00000002,   /* FBIO_CFG6 */
+			0x00000000,   /* ODT_WRITE */
+			0x00000000,   /* ODT_READ */
+			0x00000082,   /* FBIO_CFG5 */
+			0xa06204ae,   /* CFG_DIG_DLL */
+			0x007f7010,   /* DLL_XFORM_DQS */
+			0x00000000,   /* DLL_XFORM_QUSE */
+			0x00000000,   /* ZCAL_REF_CNT */
+			0x00000012,   /* ZCAL_WAIT_CNT */
+			0x00000000,   /* AUTO_CAL_INTERVAL */
+			0x00000000,   /* CFG_CLKTRIM_0 */
+			0x00000000,   /* CFG_CLKTRIM_1 */
+			0x00000000,   /* CFG_CLKTRIM_2 */
+		}
+	},
+	{
+		.rate = 380000,   /* SDRAM frquency */
+		.regs = {
+			0x00000017,   /* RC */
+			0x00000032,   /* RFC */
+			0x00000010,   /* RAS */
+			0x00000007,   /* RP */
+			0x00000008,   /* R2W */
+			0x00000005,   /* W2R */
+			0x00000003,   /* R2P */
+			0x0000000b,   /* W2P */
+			0x00000007,   /* RD_RCD */
+			0x00000007,   /* WR_RCD */
+			0x00000004,   /* RRD */
+			0x00000003,   /* REXT */
+			0x00000003,   /* WDV */
+			0x00000007,   /* QUSE */
+			0x00000004,   /* QRST */
+			0x0000000a,   /* QSAFE */
+			0x0000000e,   /* RDV */
+			0x0000059f,   /* REFRESH */
+			0x00000000,   /* BURST_REFRESH_NUM */
+			0x00000004,   /* PDEX2WR */
+			0x00000004,   /* PDEX2RD */
+			0x00000007,   /* PCHG2PDEN */
+			0x00000008,   /* ACT2PDEN */
+			0x00000001,   /* AR2PDEN */
+			0x00000011,   /* RW2PDEN */
+			0x00000036,   /* TXSR */
+			0x00000003,   /* TCKE */
+			0x00000013,   /* TFAW */
+			0x00000008,   /* TRPAB */
+			0x00000007,   /* TCLKSTABLE */
+			0x00000002,   /* TCLKSTOP */
+			0x0000062d,   /* TREFBW */
+			0x00000006,   /* QUSE_EXTRA */
+			0x00000003,   /* FBIO_CFG6 */
+			0x00000000,   /* ODT_WRITE */
+			0x00000000,   /* ODT_READ */
+			0x00000282,   /* FBIO_CFG5 */
+			0xe044048b,   /* CFG_DIG_DLL */
+			0x007fb010,   /* DLL_XFORM_DQS */
+			0x00000000,   /* DLL_XFORM_QUSE */
+			0x00000000,   /* ZCAL_REF_CNT */
+			0x00000023,   /* ZCAL_WAIT_CNT */
+			0x00000000,   /* AUTO_CAL_INTERVAL */
+			0x00000000,   /* CFG_CLKTRIM_0 */
+			0x00000000,   /* CFG_CLKTRIM_1 */
+			0x00000000,   /* CFG_CLKTRIM_2 */
+		}
+	}
+};
+
+#define TEGRA25_SKU		0x0B00
+
+int ventana_emc_init(void)
+{
+	struct board_info BoardInfo;
+
+	tegra_get_board_info(&BoardInfo);
+	if (BoardInfo.sku == TEGRA25_SKU) {
+		pr_info("%s: Elpida 400 Mhz memory found\n", __func__);
+		tegra_init_emc(ventana_emc_tables_elpida_400Mhz,
+			ARRAY_SIZE(ventana_emc_tables_elpida_400Mhz));
+	} else {
+		pr_info("%s: Elpida 333 Mhz memory found\n", __func__);
+		tegra_init_emc(ventana_emc_tables_elpida_300Mhz,
+			ARRAY_SIZE(ventana_emc_tables_elpida_300Mhz));
+	}
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-ventana-panel.c b/arch/arm/mach-tegra/board-ventana-panel.c
index f3e75e25bf6b..9c0637ed2886 100644
--- a/arch/arm/mach-tegra/board-ventana-panel.c
+++ b/arch/arm/mach-tegra/board-ventana-panel.c
@@ -24,6 +24,7 @@
 #include <linux/resource.h>
 #include <asm/mach-types.h>
 #include <linux/platform_device.h>
+#include <linux/earlysuspend.h>
 #include <linux/pwm_backlight.h>
 #include <mach/nvhost.h>
 #include <mach/nvmap.h>
@@ -34,12 +35,18 @@
 
 #include "devices.h"
 #include "gpio-names.h"
+#include "board.h"
 
+#define ventana_pnl_pwr_enb	TEGRA_GPIO_PC6
 #define ventana_bl_enb		TEGRA_GPIO_PD4
 #define ventana_lvds_shutdown	TEGRA_GPIO_PB2
 #define ventana_hdmi_hpd	TEGRA_GPIO_PN7
 #define ventana_hdmi_enb	TEGRA_GPIO_PV5
 
+static struct regulator *ventana_hdmi_reg = NULL;
+static struct regulator *ventana_hdmi_pll = NULL;
+
+
 static int ventana_backlight_init(struct device *dev) {
 	int ret;
 
@@ -88,17 +95,7 @@ static struct platform_device ventana_backlight_device = {
 
 static int ventana_panel_enable(void)
 {
-	static struct regulator *reg = NULL;
-
-	if (reg == NULL) {
-		reg = regulator_get(NULL, "avdd_lvds");
-		if (WARN_ON(IS_ERR(reg)))
-			pr_err("%s: couldn't get regulator avdd_lvds: %ld\n",
-			       __func__, PTR_ERR(reg));
-		else
-			regulator_enable(reg);
-	}
-
+	gpio_set_value(ventana_pnl_pwr_enb, 1);
 	gpio_set_value(ventana_lvds_shutdown, 1);
 	return 0;
 }
@@ -106,18 +103,42 @@ static int ventana_panel_enable(void)
 static int ventana_panel_disable(void)
 {
 	gpio_set_value(ventana_lvds_shutdown, 0);
+	gpio_set_value(ventana_pnl_pwr_enb, 0);
 	return 0;
 }
 
 static int ventana_hdmi_enable(void)
 {
 	gpio_set_value(ventana_hdmi_enb, 1);
+	if (!ventana_hdmi_reg) {
+		ventana_hdmi_reg = regulator_get(NULL, "avdd_hdmi"); /* LD07 */
+		if (IS_ERR_OR_NULL(ventana_hdmi_reg)) {
+			pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
+			ventana_hdmi_reg = NULL;
+			return PTR_ERR(ventana_hdmi_reg);
+		}
+	}
+	regulator_enable(ventana_hdmi_reg);
+
+	if (!ventana_hdmi_pll) {
+		ventana_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll"); /* LD08 */
+		if (IS_ERR_OR_NULL(ventana_hdmi_pll)) {
+			pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
+			ventana_hdmi_pll = NULL;
+			regulator_disable(ventana_hdmi_reg);
+			ventana_hdmi_reg = NULL;
+			return PTR_ERR(ventana_hdmi_pll);
+		}
+	}
+	regulator_enable(ventana_hdmi_pll);
 	return 0;
 }
 
 static int ventana_hdmi_disable(void)
 {
 	gpio_set_value(ventana_hdmi_enb, 0);
+	regulator_disable(ventana_hdmi_reg);
+	regulator_disable(ventana_hdmi_pll);
 	return 0;
 }
 
@@ -136,8 +157,6 @@ static struct resource ventana_disp1_resources[] = {
 	},
 	{
 		.name	= "fbmem",
-		.start	= 0x18012000,
-		.end	= 0x18414000 - 1, /* enough for 1080P 16bpp */
 		.flags	= IORESOURCE_MEM,
 	},
 };
@@ -158,8 +177,6 @@ static struct resource ventana_disp2_resources[] = {
 	{
 		.name	= "fbmem",
 		.flags	= IORESOURCE_MEM,
-		.start	= 0x18414000,
-		.end	= 0x18BFD000 - 1,
 	},
 	{
 		.name	= "hdmi_regs",
@@ -194,8 +211,8 @@ static struct tegra_fb_data ventana_fb_data = {
 
 static struct tegra_fb_data ventana_hdmi_fb_data = {
 	.win		= 0,
-	.xres		= 1280,
-	.yres		= 720,
+	.xres		= 1366,
+	.yres		= 768,
 	.bits_per_pixel	= 16,
 };
 
@@ -233,7 +250,7 @@ static struct tegra_dc_platform_data ventana_disp1_pdata = {
 };
 
 static struct tegra_dc_platform_data ventana_disp2_pdata = {
-	.flags		= TEGRA_DC_FLAG_ENABLED,
+	.flags		= 0,
 	.default_out	= &ventana_disp2_out,
 	.fb		= &ventana_hdmi_fb_data,
 };
@@ -269,8 +286,6 @@ static struct nvmap_platform_carveout ventana_carveouts[] = {
 	[1] = {
 		.name		= "generic-0",
 		.usage_mask	= NVMAP_HEAP_CARVEOUT_GENERIC,
-		.base		= 0x18C00000,
-		.size		= SZ_128M - 0xC00000,
 		.buddy_size	= SZ_32K,
 	},
 };
@@ -295,25 +310,70 @@ static struct platform_device *ventana_gfx_devices[] __initdata = {
 	&ventana_backlight_device,
 };
 
+#ifdef CONFIG_HAS_EARLYSUSPEND
+/* put early_suspend/late_resume handlers here for the display in order
+ * to keep the code out of the display driver, keeping it closer to upstream
+ */
+struct early_suspend ventana_panel_early_suspender;
+
+static void ventana_panel_early_suspend(struct early_suspend *h)
+{
+	if (num_registered_fb > 0)
+		fb_blank(registered_fb[0], FB_BLANK_POWERDOWN);
+}
+
+static void ventana_panel_late_resume(struct early_suspend *h)
+{
+	if (num_registered_fb > 0)
+		fb_blank(registered_fb[0], FB_BLANK_UNBLANK);
+}
+#endif
+
 int __init ventana_panel_init(void)
 {
 	int err;
+	struct resource *res;
+
+	gpio_request(ventana_pnl_pwr_enb, "pnl_pwr_enb");
+	gpio_direction_output(ventana_pnl_pwr_enb, 1);
+	tegra_gpio_enable(ventana_pnl_pwr_enb);
 
 	gpio_request(ventana_lvds_shutdown, "lvds_shdn");
 	gpio_direction_output(ventana_lvds_shutdown, 1);
 	tegra_gpio_enable(ventana_lvds_shutdown);
 
-	gpio_request(ventana_hdmi_enb, "hdmi_5v_en");
-	gpio_direction_output(ventana_hdmi_enb, 0);
 	tegra_gpio_enable(ventana_hdmi_enb);
+	gpio_request(ventana_hdmi_enb, "hdmi_5v_en");
+	gpio_direction_output(ventana_hdmi_enb, 1);
 
+	tegra_gpio_enable(ventana_hdmi_hpd);
 	gpio_request(ventana_hdmi_hpd, "hdmi_hpd");
 	gpio_direction_input(ventana_hdmi_hpd);
-	tegra_gpio_enable(ventana_hdmi_hpd);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	ventana_panel_early_suspender.suspend = ventana_panel_early_suspend;
+	ventana_panel_early_suspender.resume = ventana_panel_late_resume;
+	ventana_panel_early_suspender.level = EARLY_SUSPEND_LEVEL_DISABLE_FB;
+	register_early_suspend(&ventana_panel_early_suspender);
+#endif
+
+	ventana_carveouts[1].base = tegra_carveout_start;
+	ventana_carveouts[1].size = tegra_carveout_size;
 
 	err = platform_add_devices(ventana_gfx_devices,
 				   ARRAY_SIZE(ventana_gfx_devices));
 
+
+	res = nvhost_get_resource_byname(&ventana_disp1_device,
+		IORESOURCE_MEM, "fbmem");
+	res->start = tegra_fb_start;
+	res->end = tegra_fb_start + tegra_fb_size - 1;
+
+	res = nvhost_get_resource_byname(&ventana_disp2_device,
+		IORESOURCE_MEM, "fbmem");
+	res->start = tegra_fb2_start;
+	res->end = tegra_fb2_start + tegra_fb2_size - 1;
+
 	if (!err)
 		err = nvhost_device_register(&ventana_disp1_device);
 
diff --git a/arch/arm/mach-tegra/board-ventana-pinmux.c b/arch/arm/mach-tegra/board-ventana-pinmux.c
index e85034ccda50..a0f99448ca4b 100644
--- a/arch/arm/mach-tegra/board-ventana-pinmux.c
+++ b/arch/arm/mach-tegra/board-ventana-pinmux.c
@@ -48,17 +48,17 @@ static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
 	{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DDC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_DTA,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_DTB,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_DTC,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_DTD,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_DTE,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DTE,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
@@ -67,15 +67,15 @@ static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
 	{TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
-	{TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_LCSN,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
@@ -110,7 +110,7 @@ static __initdata struct tegra_pingroup_config ventana_pinmux[] = {
 	{TEGRA_PINGROUP_LPW1,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_LPW2,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
-	{TEGRA_PINGROUP_LSC1,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSC1,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
 	{TEGRA_PINGROUP_LSCK,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_LSDA,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
 	{TEGRA_PINGROUP_LSDI,  TEGRA_MUX_RSVD4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
diff --git a/arch/arm/mach-tegra/board-ventana-power.c b/arch/arm/mach-tegra/board-ventana-power.c
index fe1af074ab9e..696e43d32074 100644..100755
--- a/arch/arm/mach-tegra/board-ventana-power.c
+++ b/arch/arm/mach-tegra/board-ventana-power.c
@@ -29,13 +29,25 @@
 #include <mach/irqs.h>
 
 #include "gpio-names.h"
+#include "fuse.h"
 #include "power.h"
 #include "wakeups-t2.h"
 #include "board.h"
+#include "board-ventana.h"
 
 #define PMC_CTRL		0x0
 #define PMC_CTRL_INTR_LOW	(1 << 17)
 
+#define CHARGING_DISABLE	TEGRA_GPIO_PR6
+
+int __init ventana_charge_init(void)
+{
+	gpio_request(CHARGING_DISABLE, "chg_disable");
+	gpio_direction_output(CHARGING_DISABLE, 0);
+	tegra_gpio_enable(CHARGING_DISABLE);
+	return 0;
+}
+
 static struct regulator_consumer_supply tps658621_sm0_supply[] = {
 	REGULATOR_SUPPLY("vdd_core", NULL),
 };
@@ -53,22 +65,24 @@ static struct regulator_consumer_supply tps658621_ldo1_supply[] = {
 };
 static struct regulator_consumer_supply tps658621_ldo2_supply[] = {
 	REGULATOR_SUPPLY("vdd_rtc", NULL),
+	REGULATOR_SUPPLY("vdd_aon", NULL),
 };
 static struct regulator_consumer_supply tps658621_ldo3_supply[] = {
 	REGULATOR_SUPPLY("avdd_usb", NULL),
 	REGULATOR_SUPPLY("avdd_usb_pll", NULL),
-	REGULATOR_SUPPLY("avdd_lvds", NULL),
 };
 static struct regulator_consumer_supply tps658621_ldo4_supply[] = {
 	REGULATOR_SUPPLY("avdd_osc", NULL),
 	REGULATOR_SUPPLY("vddio_sys", "panjit_touch"),
 };
 static struct regulator_consumer_supply tps658621_ldo5_supply[] = {
-	REGULATOR_SUPPLY("vcore_mmc", "sdhci-tegra.1"),
-	REGULATOR_SUPPLY("vcore_mmc", "sdhci-tegra.3"),
+	REGULATOR_SUPPLY("disabled_vmmc", "sdhci-tegra.0"),
+	REGULATOR_SUPPLY("disabled_vmmc", "sdhci-tegra.1"),
+	REGULATOR_SUPPLY("disabled_vmmc", "sdhci-tegra.2"),
+	REGULATOR_SUPPLY("disabled_vmmc", "sdhci-tegra.3"),
 };
 static struct regulator_consumer_supply tps658621_ldo6_supply[] = {
-	REGULATOR_SUPPLY("vddio_vi", NULL),
+	REGULATOR_SUPPLY("vcsi", "tegra_camera"),
 };
 static struct regulator_consumer_supply tps658621_ldo7_supply[] = {
 	REGULATOR_SUPPLY("avdd_hdmi", NULL),
@@ -107,13 +121,18 @@ static struct regulator_init_data ldo2_data = REGULATOR_INIT(ldo2, 725, 1500);
 static struct regulator_init_data ldo3_data = REGULATOR_INIT(ldo3, 1250, 3300);
 static struct regulator_init_data ldo4_data = REGULATOR_INIT(ldo4, 1700, 2475);
 static struct regulator_init_data ldo5_data = REGULATOR_INIT(ldo5, 1250, 3300);
-static struct regulator_init_data ldo6_data = REGULATOR_INIT(ldo6, 1250, 3300);
+static struct regulator_init_data ldo6_data = REGULATOR_INIT(ldo6, 1250, 1800);
 static struct regulator_init_data ldo7_data = REGULATOR_INIT(ldo7, 1250, 3300);
 static struct regulator_init_data ldo8_data = REGULATOR_INIT(ldo8, 1250, 3300);
 static struct regulator_init_data ldo9_data = REGULATOR_INIT(ldo9, 1250, 3300);
 
 static struct tps6586x_rtc_platform_data rtc_data = {
 	.irq = TEGRA_NR_IRQS + TPS6586X_INT_RTC_ALM1,
+	.start = {
+		.year = 2009,
+		.month = 1,
+		.day = 1,
+	}
 };
 
 #define TPS_REG(_id, _data)			\
@@ -160,24 +179,35 @@ static struct i2c_board_info __initdata ventana_regulators[] = {
 };
 
 static struct tegra_suspend_platform_data ventana_suspend_data = {
+	/*
+	 * Check power on time and crystal oscillator start time
+	 * for appropriate settings.
+	 */
 	.cpu_timer	= 2000,
-	.cpu_off_timer	= 0,
-	.suspend_mode	= TEGRA_SUSPEND_LP1,
+	.cpu_off_timer	= 100,
+	.suspend_mode	= TEGRA_SUSPEND_LP0,
 	.core_timer	= 0x7e7e,
-	.core_off_timer = 0,
+	.core_off_timer = 0xf,
 	.separate_req	= true,
 	.corereq_high	= false,
 	.sysclkreq_high	= true,
-	.wake_enb	= TEGRA_WAKE_GPIO_PV2,
+	.wake_enb	= TEGRA_WAKE_GPIO_PV2 | TEGRA_WAKE_GPIO_PY6,
 	.wake_high	= 0,
-	.wake_low	= TEGRA_WAKE_GPIO_PV2,
+	.wake_low	= TEGRA_WAKE_GPIO_PV2 | TEGRA_WAKE_GPIO_PY6,
 	.wake_any	= 0,
 };
 
 int __init ventana_regulator_init(void)
 {
 	void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+	void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
 	u32 pmc_ctrl;
+	u32 minor;
+
+	minor = (readl(chip_id) >> 16) & 0xf;
+	/* A03 (but not A03p) chips do not support LP0 */
+	if (minor == 3 && !(tegra_spare_fuse(18) || tegra_spare_fuse(19)))
+		ventana_suspend_data.suspend_mode = TEGRA_SUSPEND_LP1;
 
 	/* configure the power management controller to trigger PMU
 	 * interrupts when low */
@@ -185,5 +215,29 @@ int __init ventana_regulator_init(void)
 	writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
 	i2c_register_board_info(4, ventana_regulators, 1);
 	tegra_init_suspend(&ventana_suspend_data);
+
 	return 0;
 }
+
+static int __init ventana_pcie_init(void)
+{
+	int ret;
+
+	ret = gpio_request(TPS6586X_GPIO_BASE, "pcie_vdd");
+	if (ret < 0)
+		goto fail;
+
+	ret = gpio_direction_output(TPS6586X_GPIO_BASE, 1);
+	if (ret < 0)
+		goto fail;
+
+	gpio_export(TPS6586X_GPIO_BASE, false);
+	return 0;
+
+fail:
+	pr_err("%s: gpio_request failed #%d\n", __func__, TPS6586X_GPIO_BASE);
+	gpio_free(TPS6586X_GPIO_BASE);
+	return ret;
+}
+
+late_initcall(ventana_pcie_init);
diff --git a/arch/arm/mach-tegra/board-ventana-sdhci.c b/arch/arm/mach-tegra/board-ventana-sdhci.c
index 13ab48b1c7a1..9eb7a71306e1 100644..100755
--- a/arch/arm/mach-tegra/board-ventana-sdhci.c
+++ b/arch/arm/mach-tegra/board-ventana-sdhci.c
@@ -16,8 +16,12 @@
 
 #include <linux/resource.h>
 #include <linux/platform_device.h>
+#include <linux/wlan_plat.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mmc/host.h>
 
 #include <asm/mach-types.h>
 #include <mach/irqs.h>
@@ -27,6 +31,32 @@
 #include "gpio-names.h"
 #include "board.h"
 
+#define VENTANA_WLAN_PWR	TEGRA_GPIO_PK5
+#define VENTANA_WLAN_RST	TEGRA_GPIO_PK6
+
+static void (*wifi_status_cb)(int card_present, void *dev_id);
+static void *wifi_status_cb_devid;
+static int ventana_wifi_status_register(void (*callback)(int , void *), void *);
+static struct clk *wifi_32k_clk;
+
+static int ventana_wifi_reset(int on);
+static int ventana_wifi_power(int on);
+static int ventana_wifi_set_carddetect(int val);
+
+static struct wifi_platform_data ventana_wifi_control = {
+	.set_power      = ventana_wifi_power,
+	.set_reset      = ventana_wifi_reset,
+	.set_carddetect = ventana_wifi_set_carddetect,
+};
+
+static struct platform_device ventana_wifi_device = {
+	.name           = "bcm4329_wlan",
+	.id             = 1,
+	.dev            = {
+		.platform_data = &ventana_wifi_control,
+	},
+};
+
 static struct resource sdhci_resource0[] = {
 	[0] = {
 		.start  = INT_SDMMC1,
@@ -66,9 +96,23 @@ static struct resource sdhci_resource3[] = {
 	},
 };
 
+
 static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
 	.clk_id = NULL,
-	.force_hs = 1,
+	.force_hs = 0,
+	.register_status_notify	= ventana_wifi_status_register,
+	.cccr   = {
+		.sdio_vsn       = 2,
+		.multi_block    = 1,
+		.low_speed      = 0,
+		.wide_bus       = 0,
+		.high_power     = 1,
+		.high_speed     = 1,
+	},
+	.cis  = {
+		.vendor         = 0x02d0,
+		.device         = 0x4329,
+	},
 	.cd_gpio = -1,
 	.wp_gpio = -1,
 	.power_gpio = -1,
@@ -120,6 +164,74 @@ static struct platform_device tegra_sdhci_device3 = {
 	},
 };
 
+static int ventana_wifi_status_register(
+		void (*callback)(int card_present, void *dev_id),
+		void *dev_id)
+{
+	if (wifi_status_cb)
+		return -EAGAIN;
+	wifi_status_cb = callback;
+	wifi_status_cb_devid = dev_id;
+	return 0;
+}
+
+static int ventana_wifi_set_carddetect(int val)
+{
+	pr_debug("%s: %d\n", __func__, val);
+	if (wifi_status_cb)
+		wifi_status_cb(val, wifi_status_cb_devid);
+	else
+		pr_warning("%s: Nobody to notify\n", __func__);
+	return 0;
+}
+
+static int ventana_wifi_power(int on)
+{
+	pr_debug("%s: %d\n", __func__, on);
+
+	gpio_set_value(VENTANA_WLAN_PWR, on);
+	mdelay(100);
+	gpio_set_value(VENTANA_WLAN_RST, on);
+	mdelay(200);
+
+	if (on)
+		clk_enable(wifi_32k_clk);
+	else
+		clk_disable(wifi_32k_clk);
+
+	return 0;
+}
+
+static int ventana_wifi_reset(int on)
+{
+	pr_debug("%s: do nothing\n", __func__);
+	return 0;
+}
+
+static int __init ventana_wifi_init(void)
+{
+	wifi_32k_clk = clk_get_sys(NULL, "blink");
+	if (IS_ERR(wifi_32k_clk)) {
+		pr_err("%s: unable to get blink clock\n", __func__);
+		return PTR_ERR(wifi_32k_clk);
+	}
+
+	gpio_request(VENTANA_WLAN_PWR, "wlan_power");
+	gpio_request(VENTANA_WLAN_RST, "wlan_rst");
+
+	tegra_gpio_enable(VENTANA_WLAN_PWR);
+	tegra_gpio_enable(VENTANA_WLAN_RST);
+
+	gpio_direction_output(VENTANA_WLAN_PWR, 0);
+	gpio_direction_output(VENTANA_WLAN_RST, 0);
+
+	platform_device_register(&ventana_wifi_device);
+
+	device_init_wakeup(&ventana_wifi_device.dev, 1);
+	device_set_wakeup_enable(&ventana_wifi_device.dev, 0);
+
+	return 0;
+}
 int __init ventana_sdhci_init(void)
 {
 	gpio_request(tegra_sdhci_platform_data2.power_gpio, "sdhci2_power");
@@ -140,5 +252,6 @@ int __init ventana_sdhci_init(void)
 	platform_device_register(&tegra_sdhci_device2);
 	platform_device_register(&tegra_sdhci_device0);
 
+	ventana_wifi_init();
 	return 0;
 }
diff --git a/arch/arm/mach-tegra/board-ventana-sensors.c b/arch/arm/mach-tegra/board-ventana-sensors.c
new file mode 100644
index 000000000000..a819a2320ba8
--- /dev/null
+++ b/arch/arm/mach-tegra/board-ventana-sensors.c
@@ -0,0 +1,334 @@
+/*
+ * arch/arm/mach-tegra/board-ventana-sensors.c
+ *
+ * Copyright (c) 2010, NVIDIA, All Rights Reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/i2c.h>
+#include <linux/akm8975.h>
+#include <linux/mpu.h>
+#include <linux/i2c/pca954x.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/nct1008.h>
+
+#include <mach/gpio.h>
+
+#include <media/ov5650.h>
+#include <generated/mach-types.h>
+
+#include "gpio-names.h"
+#include "board.h"
+#include "board-ventana.h"
+
+#define ISL29018_IRQ_GPIO	TEGRA_GPIO_PZ2
+#define AKM8975_IRQ_GPIO	TEGRA_GPIO_PN5
+#define CAMERA_POWER_GPIO	TEGRA_GPIO_PV4
+#define CAMERA_CSI_MUX_SEL_GPIO	TEGRA_GPIO_PBB4
+#define AC_PRESENT_GPIO		TEGRA_GPIO_PV3
+#define NCT1008_THERM2_GPIO	TEGRA_GPIO_PN6
+
+extern void tegra_throttling_enable(bool enable);
+
+static int ventana_camera_init(void)
+{
+	tegra_gpio_enable(CAMERA_POWER_GPIO);
+	gpio_request(CAMERA_POWER_GPIO, "camera_power_en");
+	gpio_direction_output(CAMERA_POWER_GPIO, 1);
+	gpio_export(CAMERA_POWER_GPIO, false);
+
+	tegra_gpio_enable(CAMERA_CSI_MUX_SEL_GPIO);
+	gpio_request(CAMERA_CSI_MUX_SEL_GPIO, "camera_csi_sel");
+	gpio_direction_output(CAMERA_CSI_MUX_SEL_GPIO, 0);
+	gpio_export(CAMERA_CSI_MUX_SEL_GPIO, false);
+
+	return 0;
+}
+
+static int ventana_ov5650_power_on(void)
+{
+	return 0;
+}
+
+static int ventana_ov5650_power_off(void)
+{
+	return 0;
+}
+
+struct ov5650_platform_data ventana_ov5650_data = {
+	.power_on = ventana_ov5650_power_on,
+	.power_off = ventana_ov5650_power_off,
+};
+
+static void ventana_isl29018_init(void)
+{
+	tegra_gpio_enable(ISL29018_IRQ_GPIO);
+	gpio_request(ISL29018_IRQ_GPIO, "isl29018");
+	gpio_direction_input(ISL29018_IRQ_GPIO);
+}
+
+#ifdef CONFIG_SENSORS_AK8975
+static void ventana_akm8975_init(void)
+{
+	tegra_gpio_enable(AKM8975_IRQ_GPIO);
+	gpio_request(AKM8975_IRQ_GPIO, "akm8975");
+	gpio_direction_input(AKM8975_IRQ_GPIO);
+}
+#endif
+
+static void ventana_bq20z75_init(void)
+{
+	tegra_gpio_enable(AC_PRESENT_GPIO);
+	gpio_request(AC_PRESENT_GPIO, "ac_present");
+	gpio_direction_input(AC_PRESENT_GPIO);
+}
+
+static void ventana_nct1008_init(void)
+{
+	tegra_gpio_enable(NCT1008_THERM2_GPIO);
+	gpio_request(NCT1008_THERM2_GPIO, "temp_alert");
+	gpio_direction_input(NCT1008_THERM2_GPIO);
+}
+
+static struct nct1008_platform_data ventana_nct1008_pdata = {
+	.supported_hwrev = true,
+	.ext_range = false,
+	.conv_rate = 0x08,
+	.offset = 0,
+	.hysteresis = 0,
+	.shutdown_ext_limit = 115,
+	.shutdown_local_limit = 120,
+	.throttling_ext_limit = 90,
+	.alarm_fn = tegra_throttling_enable,
+};
+
+static const struct i2c_board_info ventana_i2c0_board_info[] = {
+	{
+		I2C_BOARD_INFO("isl29018", 0x44),
+		.irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PZ2),
+	},
+};
+
+static const struct i2c_board_info ventana_i2c2_board_info[] = {
+	{
+		I2C_BOARD_INFO("bq20z75-battery", 0x0B),
+		.irq = TEGRA_GPIO_TO_IRQ(AC_PRESENT_GPIO),
+	},
+};
+
+static struct pca953x_platform_data ventana_tca6416_data = {
+	.gpio_base      = TEGRA_NR_GPIOS + 4, /* 4 gpios are already requested by tps6586x */
+};
+
+static struct pca954x_platform_mode ventana_pca9546_modes[] = {
+	{ .adap_id = 6, }, /* REAR CAM1 */
+	{ .adap_id = 7, }, /* REAR CAM2 */
+	{ .adap_id = 8, }, /* FRONT CAM3 */
+};
+
+static struct pca954x_platform_data ventana_pca9546_data = {
+	.modes	  = ventana_pca9546_modes,
+	.num_modes      = ARRAY_SIZE(ventana_pca9546_modes),
+};
+
+static const struct i2c_board_info ventana_i2c3_board_info_tca6416[] = {
+	{
+		I2C_BOARD_INFO("tca6416", 0x20),
+		.platform_data = &ventana_tca6416_data,
+	},
+};
+
+static const struct i2c_board_info ventana_i2c3_board_info_pca9546[] = {
+	{
+		I2C_BOARD_INFO("pca9546", 0x70),
+		.platform_data = &ventana_pca9546_data,
+	},
+};
+
+static struct i2c_board_info ventana_i2c4_board_info[] = {
+	{
+		I2C_BOARD_INFO("nct1008", 0x4C),
+		.irq = TEGRA_GPIO_TO_IRQ(NCT1008_THERM2_GPIO),
+		.platform_data = &ventana_nct1008_pdata,
+	},
+
+#ifdef CONFIG_SENSORS_AK8975
+	{
+		I2C_BOARD_INFO("akm8975", 0x0C),
+		.irq = TEGRA_GPIO_TO_IRQ(AKM8975_IRQ_GPIO),
+	},
+#endif
+};
+
+static struct i2c_board_info ventana_i2c7_board_info[] = {
+	{
+		I2C_BOARD_INFO("ov5650", 0x36),
+		.platform_data = &ventana_ov5650_data,
+	},
+};
+
+#ifdef CONFIG_SENSORS_MPU3050
+#define SENSOR_MPU_NAME "mpu3050"
+static struct mpu3050_platform_data mpu3050_data = {
+	.int_config  = 0x10,
+	.orientation = { 0, -1, 0, -1, 0, 0, 0, 0, -1 },  /* Orientation matrix for MPU on ventana */
+	.level_shifter = 0,
+	.accel = {
+#ifdef CONFIG_SENSORS_KXTF9_MPU
+	.get_slave_descr = get_accel_slave_descr,
+#else
+	.get_slave_descr = NULL,
+#endif
+	.adapt_num   = 0,
+	.bus         = EXT_SLAVE_BUS_SECONDARY,
+	.address     = 0x0F,
+	.orientation = { 0, -1, 0, -1, 0, 0, 0, 0, -1 },  /* Orientation matrix for Kionix on ventana */
+	},
+
+	.compass = {
+#ifdef CONFIG_SENSORS_AK8975_MPU
+	.get_slave_descr = get_compass_slave_descr,
+#else
+	.get_slave_descr = NULL,
+#endif
+	.adapt_num   = 4,            /* bus number 4 on ventana */
+	.bus         = EXT_SLAVE_BUS_PRIMARY,
+	.address     = 0x0C,
+	.orientation = { 1, 0, 0, 0, -1, 0, 0, 0, -1 },  /* Orientation matrix for AKM on ventana */
+	},
+};
+
+static struct i2c_board_info __initdata mpu3050_i2c0_boardinfo[] = {
+	{
+		I2C_BOARD_INFO(SENSOR_MPU_NAME, 0x68),
+		.irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PZ4),
+		.platform_data = &mpu3050_data,
+	},
+};
+
+static void ventana_mpuirq_init(void)
+{
+	pr_info("*** MPU START *** ventana_mpuirq_init...\n");
+	tegra_gpio_enable(TEGRA_GPIO_PZ4);
+	gpio_request(TEGRA_GPIO_PZ4, SENSOR_MPU_NAME);
+	gpio_direction_input(TEGRA_GPIO_PZ4);
+	pr_info("*** MPU END *** ventana_mpuirq_init...\n");
+}
+#endif
+
+int __init ventana_sensors_init(void)
+{
+	struct board_info BoardInfo;
+
+	ventana_isl29018_init();
+#ifdef CONFIG_SENSORS_AK8975
+	ventana_akm8975_init();
+#endif
+#ifdef CONFIG_SENSORS_MPU3050
+	ventana_mpuirq_init();
+#endif
+	ventana_camera_init();
+	ventana_nct1008_init();
+
+	i2c_register_board_info(0, ventana_i2c0_board_info,
+		ARRAY_SIZE(ventana_i2c0_board_info));
+
+	tegra_get_board_info(&BoardInfo);
+
+	/*
+	 * battery driver is supported on FAB.D boards and above only,
+	 * since they have the necessary hardware rework
+	 */
+	if (BoardInfo.sku > 0) {
+		ventana_bq20z75_init();
+		i2c_register_board_info(2, ventana_i2c2_board_info,
+			ARRAY_SIZE(ventana_i2c2_board_info));
+	}
+
+	i2c_register_board_info(4, ventana_i2c4_board_info,
+		ARRAY_SIZE(ventana_i2c4_board_info));
+
+	i2c_register_board_info(7, ventana_i2c7_board_info,
+		ARRAY_SIZE(ventana_i2c7_board_info));
+
+#ifdef CONFIG_SENSORS_MPU3050
+	i2c_register_board_info(0, mpu3050_i2c0_boardinfo,
+		ARRAY_SIZE(mpu3050_i2c0_boardinfo));
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_VIDEO_OV5650
+
+struct ov5650_gpios {
+	const char *name;
+	int gpio;
+	int enabled;
+};
+
+#define OV5650_GPIO(_name, _gpio, _enabled)		\
+	{						\
+		.name = _name,				\
+		.gpio = _gpio,				\
+		.enabled = _enabled,			\
+	}
+
+static struct ov5650_gpios ov5650_gpio_keys[] = {
+	[0] = OV5650_GPIO("en_avdd_csi", AVDD_DSI_CSI_ENB_GPIO, 1),
+	[1] = OV5650_GPIO("cam2_pwdn", CAM2_PWR_DN_GPIO, 0),
+	[2] = OV5650_GPIO("cam2_rst_lo", CAM2_RST_L_GPIO, 1),
+	[3] = OV5650_GPIO("cam2_af_pwdn_lo", CAM2_AF_PWR_DN_L_GPIO, 0),
+	[4] = OV5650_GPIO("cam2_ldo_shdn_lo", CAM2_LDO_SHUTDN_L_GPIO, 1),
+	[5] = OV5650_GPIO("cam2_i2c_mux_rst_lo", CAM2_I2C_MUX_RST_GPIO, 1),
+};
+
+int __init ventana_ov5650_late_init(void)
+{
+	int ret;
+	int i;
+
+	if (!machine_is_ventana())
+		return 0;
+
+	i2c_new_device(i2c_get_adapter(3), ventana_i2c3_board_info_tca6416);
+
+	for (i = 0; i < ARRAY_SIZE(ov5650_gpio_keys); i++) {
+		ret = gpio_request(ov5650_gpio_keys[i].gpio,
+			ov5650_gpio_keys[i].name);
+		if (ret < 0) {
+			pr_err("%s: gpio_request failed for gpio #%d\n",
+				__func__, i);
+			goto fail;
+		}
+		gpio_direction_output(ov5650_gpio_keys[i].gpio,
+			ov5650_gpio_keys[i].enabled);
+		gpio_export(ov5650_gpio_keys[i].gpio, false);
+	}
+
+	i2c_new_device(i2c_get_adapter(3), ventana_i2c3_board_info_pca9546);
+
+	return 0;
+
+fail:
+	while (i--)
+		gpio_free(ov5650_gpio_keys[i].gpio);
+	return ret;
+}
+
+late_initcall(ventana_ov5650_late_init);
+
+#endif /* CONFIG_VIDEO_OV5650 */
diff --git a/arch/arm/mach-tegra/board-ventana.c b/arch/arm/mach-tegra/board-ventana.c
index 6302118a335b..61d3008b3e3b 100644
--- a/arch/arm/mach-tegra/board-ventana.c
+++ b/arch/arm/mach-tegra/board-ventana.c
@@ -26,14 +26,24 @@
 #include <linux/clk.h>
 #include <linux/serial_8250.h>
 #include <linux/i2c.h>
-#include <linux/i2c/panjit_ts.h>
 #include <linux/dma-mapping.h>
 #include <linux/delay.h>
 #include <linux/i2c-tegra.h>
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/tegra_usb.h>
 #include <linux/usb/android_composite.h>
+#include <linux/mfd/tps6586x.h>
+#include <linux/memblock.h>
+
+#ifdef CONFIG_TOUCHSCREEN_PANJIT_I2C
+#include <linux/i2c/panjit_ts.h>
+#endif
+
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MT_T9
+#include <linux/i2c/atmel_maxtouch.h>
+#endif
 
 #include <mach/clk.h>
 #include <mach/iomap.h>
@@ -41,9 +51,13 @@
 #include <mach/pinmux.h>
 #include <mach/iomap.h>
 #include <mach/io.h>
-
+#include <mach/i2s.h>
+#include <mach/spdif.h>
+#include <mach/audio.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <mach/usb_phy.h>
+#include <mach/tegra_das.h>
 
 #include "board.h"
 #include "clock.h"
@@ -51,13 +65,29 @@
 #include "devices.h"
 #include "gpio-names.h"
 #include "fuse.h"
+#include "wakeups-t2.h"
+
+static struct usb_mass_storage_platform_data tegra_usb_fsg_platform = {
+	.vendor = "NVIDIA",
+	.product = "Tegra 2",
+	.nluns = 1,
+};
+
+static struct platform_device tegra_usb_fsg_device = {
+	.name = "usb_mass_storage",
+	.id = -1,
+	.dev = {
+		.platform_data = &tegra_usb_fsg_platform,
+	},
+};
 
 static struct plat_serial8250_port debug_uart_platform_data[] = {
 	{
 		.membase	= IO_ADDRESS(TEGRA_UARTD_BASE),
 		.mapbase	= TEGRA_UARTD_BASE,
 		.irq		= INT_UARTD,
-		.flags		= UPF_BOOT_AUTOCONF,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
+		.type           = PORT_TEGRA,
 		.iotype		= UPIO_MEM,
 		.regshift	= 2,
 		.uartclk	= 216000000,
@@ -74,16 +104,92 @@ static struct platform_device debug_uart = {
 	},
 };
 
+static struct tegra_audio_platform_data tegra_spdif_pdata = {
+	.dma_on = true,  /* use dma by default */
+	.i2s_clk_rate = 5644800,
+	.mode = SPDIF_BIT_MODE_MODE16BIT,
+	.fifo_fmt = 0,
+};
+
+static struct tegra_utmip_config utmi_phy_config[] = {
+	[0] = {
+			.hssync_start_delay = 0,
+			.idle_wait_delay = 17,
+			.elastic_limit = 16,
+			.term_range_adj = 6,
+			.xcvr_setup = 15,
+			.xcvr_lsfslew = 2,
+			.xcvr_lsrslew = 2,
+	},
+	[1] = {
+			.hssync_start_delay = 0,
+			.idle_wait_delay = 17,
+			.elastic_limit = 16,
+			.term_range_adj = 6,
+			.xcvr_setup = 8,
+			.xcvr_lsfslew = 2,
+			.xcvr_lsrslew = 2,
+	},
+};
+
+static struct tegra_ulpi_config ulpi_phy_config = {
+	.reset_gpio = TEGRA_GPIO_PG2,
+	.clk = "clk_dev2",
+};
+
+#ifdef CONFIG_BCM4329_RFKILL
+
+static struct resource ventana_bcm4329_rfkill_resources[] = {
+	{
+		.name   = "bcm4329_nshutdown_gpio",
+		.start  = TEGRA_GPIO_PU0,
+		.end    = TEGRA_GPIO_PU0,
+		.flags  = IORESOURCE_IO,
+	},
+};
+
+static struct platform_device ventana_bcm4329_rfkill_device = {
+	.name = "bcm4329_rfkill",
+	.id             = -1,
+	.num_resources  = ARRAY_SIZE(ventana_bcm4329_rfkill_resources),
+	.resource       = ventana_bcm4329_rfkill_resources,
+};
+
+static noinline void __init ventana_bt_rfkill(void)
+{
+	/*Add Clock Resource*/
+	clk_add_alias("bcm4329_32k_clk", ventana_bcm4329_rfkill_device.name, \
+				"blink", NULL);
+
+	platform_device_register(&ventana_bcm4329_rfkill_device);
+
+	return;
+}
+#else
+static inline void ventana_bt_rfkill(void) { }
+#endif
+
 static __initdata struct tegra_clk_init_table ventana_clk_init_table[] = {
 	/* name		parent		rate		enabled */
 	{ "uartd",	"pll_p",	216000000,	true},
-	{ "pll_m",	"clk_m",	600000000,	true},
+	{ "uartc",	"pll_m",	600000000,	false},
+	{ "blink",	"clk_32k",	32768,		false},
+	{ "pll_p_out4",	"pll_p",	24000000,	true },
 	{ "pwm",	"clk_32k",	32768,		false},
+	{ "pll_a",	NULL,		11289600,	true},
+	{ "pll_a_out0",	NULL,		11289600,	true},
+	{ "i2s1",	"pll_a_out0",	11289600,	true},
+	{ "i2s2",	"pll_a_out0",	11289600,	true},
+	{ "audio",	"pll_a_out0",	11289600,	true},
+	{ "audio_2x",	"audio",	22579200,	true},
+	{ "spdif_out",	"pll_a_out0",	5644800,	false},
+	{ "kbc",	"clk_32k",	32768,		true},
 	{ NULL,		NULL,		0,		0},
 };
 
-static char *usb_functions[] = { "mtp" };
-static char *usb_functions_adb[] = { "mtp", "adb" };
+static char *usb_functions[] = { "mtp", "usb_mass_storage" };
+static char *usb_functions_adb[] = { "mtp", "adb", "usb_mass_storage" };
+
 
 static struct android_usb_product usb_products[] = {
 	{
@@ -119,6 +225,23 @@ static struct platform_device androidusb_device = {
 	},
 };
 
+static struct i2c_board_info __initdata ventana_i2c_bus1_board_info[] = {
+	{
+		I2C_BOARD_INFO("wm8903", 0x1a),
+	},
+};
+
+static struct tegra_ulpi_config ventana_ehci2_ulpi_phy_config = {
+	.reset_gpio = TEGRA_GPIO_PV1,
+	.clk = "clk_dev2",
+};
+
+static struct tegra_ehci_platform_data ventana_ehci2_ulpi_platform_data = {
+	.operating_mode = TEGRA_USB_HOST,
+	.power_down_on_bus_suspend = 0,
+	.phy_config = &ventana_ehci2_ulpi_phy_config,
+};
+
 static struct tegra_i2c_platform_data ventana_i2c1_platform_data = {
 	.adapter_nr	= 0,
 	.bus_count	= 1,
@@ -138,7 +261,7 @@ static const struct tegra_pingroup_config i2c2_gen2 = {
 static struct tegra_i2c_platform_data ventana_i2c2_platform_data = {
 	.adapter_nr	= 1,
 	.bus_count	= 2,
-	.bus_clk_rate	= { 400000, 100000 },
+	.bus_clk_rate	= { 400000, 10000 },
 	.bus_mux	= { &i2c2_ddc, &i2c2_gen2 },
 	.bus_mux_len	= { 1, 1 },
 };
@@ -156,6 +279,107 @@ static struct tegra_i2c_platform_data ventana_dvc_platform_data = {
 	.is_dvc		= true,
 };
 
+static struct tegra_audio_platform_data tegra_audio_pdata[] = {
+	/* For I2S1 */
+	[0] = {
+		.i2s_master	= true,
+		.dma_on		= true,  /* use dma by default */
+		.i2s_master_clk = 44100,
+		.i2s_clk_rate	= 240000000,
+		.dap_clk	= "clk_dev1",
+		.audio_sync_clk = "audio_2x",
+		.mode		= I2S_BIT_FORMAT_I2S,
+		.fifo_fmt	= I2S_FIFO_PACKED,
+		.bit_size	= I2S_BIT_SIZE_16,
+		.i2s_bus_width = 32,
+		.dsp_bus_width = 16,
+	},
+	/* For I2S2 */
+	[1] = {
+		.i2s_master	= true,
+		.dma_on		= true,  /* use dma by default */
+		.i2s_master_clk = 8000,
+		.dsp_master_clk = 8000,
+		.i2s_clk_rate	= 2000000,
+		.dap_clk	= "clk_dev1",
+		.audio_sync_clk = "audio_2x",
+		.mode		= I2S_BIT_FORMAT_DSP,
+		.fifo_fmt	= I2S_FIFO_16_LSB,
+		.bit_size	= I2S_BIT_SIZE_16,
+		.i2s_bus_width = 32,
+		.dsp_bus_width = 16,
+	}
+};
+
+static struct tegra_das_platform_data tegra_das_pdata = {
+	.tegra_dap_port_info_table = {
+		[0] = {
+			.dac_port = tegra_das_port_none,
+			.codec_type = tegra_audio_codec_type_none,
+			.device_property = {
+				.num_channels = 0,
+				.bits_per_sample = 0,
+				.rate = 0,
+				.dac_dap_data_comm_format = 0,
+			},
+		},
+		/* I2S1 <--> DAC1 <--> DAP1 <--> Hifi Codec */
+		[1] = {
+			.dac_port = tegra_das_port_i2s1,
+			.codec_type = tegra_audio_codec_type_hifi,
+			.device_property = {
+				.num_channels = 2,
+				.bits_per_sample = 16,
+				.rate = 44100,
+				.dac_dap_data_comm_format = dac_dap_data_format_i2s,
+			},
+		},
+		[2] = {
+			.dac_port = tegra_das_port_none,
+			.codec_type = tegra_audio_codec_type_none,
+			.device_property = {
+				.num_channels = 0,
+				.bits_per_sample = 0,
+				.rate = 0,
+				.dac_dap_data_comm_format = 0,
+			},
+		},
+		[3] = {
+			.dac_port = tegra_das_port_none,
+			.codec_type = tegra_audio_codec_type_none,
+			.device_property = {
+				.num_channels = 0,
+				.bits_per_sample = 0,
+				.rate = 0,
+				.dac_dap_data_comm_format = 0,
+			},
+		},
+		[4] = {
+			.dac_port = tegra_das_port_none,
+			.codec_type = tegra_audio_codec_type_none,
+			.device_property = {
+				.num_channels = 0,
+				.bits_per_sample = 0,
+				.rate = 0,
+				.dac_dap_data_comm_format = 0,
+			},
+		},
+	},
+
+	.tegra_das_con_table = {
+		[0] = {
+			.con_id = tegra_das_port_con_id_hifi,
+			.num_entries = 4,
+			.con_line = {
+				[0] = {tegra_das_port_i2s1, tegra_das_port_dap1, true},
+				[1] = {tegra_das_port_dap1, tegra_das_port_i2s1, false},
+				[2] = {tegra_das_port_i2s2, tegra_das_port_dap4, true},
+				[3] = {tegra_das_port_dap4, tegra_das_port_i2s2, false},
+			},
+		},
+	}
+};
+
 static void ventana_i2c_init(void)
 {
 	tegra_i2c_device1.dev.platform_data = &ventana_i2c1_platform_data;
@@ -163,12 +387,16 @@ static void ventana_i2c_init(void)
 	tegra_i2c_device3.dev.platform_data = &ventana_i2c3_platform_data;
 	tegra_i2c_device4.dev.platform_data = &ventana_dvc_platform_data;
 
-	platform_device_register(&tegra_i2c_device4);
-	platform_device_register(&tegra_i2c_device3);
-	platform_device_register(&tegra_i2c_device2);
+	i2c_register_board_info(0, ventana_i2c_bus1_board_info, 1);
+
 	platform_device_register(&tegra_i2c_device1);
+	platform_device_register(&tegra_i2c_device2);
+	platform_device_register(&tegra_i2c_device3);
+	platform_device_register(&tegra_i2c_device4);
 }
 
+
+#ifdef CONFIG_KEYBOARD_GPIO
 #define GPIO_KEY(_id, _gpio, _iswake)		\
 	{					\
 		.code = _id,			\
@@ -181,17 +409,29 @@ static void ventana_i2c_init(void)
 	}
 
 static struct gpio_keys_button ventana_keys[] = {
-	[0] = GPIO_KEY(KEY_MENU, PQ3, 0),
+	[0] = GPIO_KEY(KEY_FIND, PQ3, 0),
 	[1] = GPIO_KEY(KEY_HOME, PQ1, 0),
 	[2] = GPIO_KEY(KEY_BACK, PQ2, 0),
 	[3] = GPIO_KEY(KEY_VOLUMEUP, PQ5, 0),
 	[4] = GPIO_KEY(KEY_VOLUMEDOWN, PQ4, 0),
 	[5] = GPIO_KEY(KEY_POWER, PV2, 1),
+	[6] = GPIO_KEY(KEY_MENU, PC7, 0),
 };
 
+#define PMC_WAKE_STATUS 0x14
+
+static int ventana_wakeup_key(void)
+{
+	unsigned long status =
+		readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_WAKE_STATUS);
+
+	return status & TEGRA_WAKE_GPIO_PV2 ? KEY_POWER : KEY_RESERVED;
+}
+
 static struct gpio_keys_platform_data ventana_keys_platform_data = {
 	.buttons	= ventana_keys,
 	.nbuttons	= ARRAY_SIZE(ventana_keys),
+	.wakeup_key	= ventana_wakeup_key,
 };
 
 static struct platform_device ventana_keys_device = {
@@ -202,38 +442,58 @@ static struct platform_device ventana_keys_device = {
 	},
 };
 
+static void ventana_keys_init(void)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ventana_keys); i++)
+		tegra_gpio_enable(ventana_keys[i].gpio);
+}
+#endif
+
+static struct platform_device tegra_camera = {
+	.name = "tegra_camera",
+	.id = -1,
+};
+
 static struct platform_device *ventana_devices[] __initdata = {
-	&tegra_otg_device,
+	&tegra_usb_fsg_device,
 	&androidusb_device,
 	&debug_uart,
+	&tegra_uartb_device,
+	&tegra_uartc_device,
 	&pmu_device,
 	&tegra_udc_device,
+	&tegra_ehci2_device,
 	&tegra_gart_device,
 	&tegra_aes_device,
+#ifdef CONFIG_KEYBOARD_GPIO
 	&ventana_keys_device,
+#endif
+	&tegra_wdt_device,
+	&tegra_i2s_device1,
+	&tegra_i2s_device2,
+	&tegra_spdif_device,
+	&tegra_avp_device,
+	&tegra_camera,
+	&tegra_das_device,
 };
 
-static void ventana_keys_init(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(ventana_keys); i++)
-		tegra_gpio_enable(ventana_keys[i].gpio);
-}
 
+#ifdef CONFIG_TOUCHSCREEN_PANJIT_I2C
 static struct panjit_i2c_ts_platform_data panjit_data = {
 	.gpio_reset = TEGRA_GPIO_PQ7,
 };
 
 static const struct i2c_board_info ventana_i2c_bus1_touch_info[] = {
 	{
-		I2C_BOARD_INFO("panjit_touch", 0x3),
-		.irq		= TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PV6),
-		.platform_data	= &panjit_data,
-	},
+	 I2C_BOARD_INFO("panjit_touch", 0x3),
+	 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PV6),
+	 .platform_data = &panjit_data,
+	 },
 };
 
-static int __init ventana_touch_init(void)
+static int __init ventana_touch_init_panjit(void)
 {
 	tegra_gpio_enable(TEGRA_GPIO_PV6);
 
@@ -242,25 +502,237 @@ static int __init ventana_touch_init(void)
 
 	return 0;
 }
+#endif
+
+#ifdef CONFIG_TOUCHSCREEN_ATMEL_MT_T9
+/* Atmel MaxTouch touchscreen              Driver data */
+/*-----------------------------------------------------*/
+/*
+ * Reads the CHANGELINE state; interrupt is valid if the changeline
+ * is low.
+ */
+static u8 read_chg(void)
+{
+	return gpio_get_value(TEGRA_GPIO_PV6);
+}
+
+static u8 valid_interrupt(void)
+{
+	return !read_chg();
+}
+
+static struct mxt_platform_data Atmel_mxt_info = {
+	/* Maximum number of simultaneous touches to report. */
+	.numtouch = 10,
+	// TODO: no need for any hw-specific things at init/exit?
+	.init_platform_hw = NULL,
+	.exit_platform_hw = NULL,
+	.max_x = 1366,
+	.max_y = 768,
+	.valid_interrupt = &valid_interrupt,
+	.read_chg = &read_chg,
+};
+
+static struct i2c_board_info __initdata i2c_info[] = {
+	{
+	 I2C_BOARD_INFO("maXTouch", MXT_I2C_ADDRESS),
+	 .irq = TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PV6),
+	 .platform_data = &Atmel_mxt_info,
+	 },
+};
+
+static int __init ventana_touch_init_atmel(void)
+{
+	tegra_gpio_enable(TEGRA_GPIO_PV6);
+	tegra_gpio_enable(TEGRA_GPIO_PQ7);
+
+	gpio_set_value(TEGRA_GPIO_PQ7, 0);
+	msleep(1);
+	gpio_set_value(TEGRA_GPIO_PQ7, 1);
+	msleep(100);
+
+	i2c_register_board_info(0, i2c_info, 1);
+
+	return 0;
+}
+#endif
+
+static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
+	[0] = {
+			.phy_config = &utmi_phy_config[0],
+			.operating_mode = TEGRA_USB_HOST,
+			.power_down_on_bus_suspend = 0,
+	},
+	[1] = {
+			.phy_config = &ulpi_phy_config,
+			.operating_mode = TEGRA_USB_HOST,
+			.power_down_on_bus_suspend = 1,
+	},
+	[2] = {
+			.phy_config = &utmi_phy_config[1],
+			.operating_mode = TEGRA_USB_HOST,
+			.power_down_on_bus_suspend = 0,
+	},
+};
+
+static struct platform_device *tegra_usb_otg_host_register(void)
+{
+	struct platform_device *pdev;
+	void *platform_data;
+	int val;
+
+	pdev = platform_device_alloc(tegra_ehci1_device.name, tegra_ehci1_device.id);
+	if (!pdev)
+		return NULL;
+
+	val = platform_device_add_resources(pdev, tegra_ehci1_device.resource,
+		tegra_ehci1_device.num_resources);
+	if (val)
+		goto error;
+
+	pdev->dev.dma_mask =  tegra_ehci1_device.dev.dma_mask;
+	pdev->dev.coherent_dma_mask = tegra_ehci1_device.dev.coherent_dma_mask;
+
+	platform_data = kmalloc(sizeof(struct tegra_ehci_platform_data), GFP_KERNEL);
+	if (!platform_data)
+		goto error;
+
+	memcpy(platform_data, &tegra_ehci_pdata[0],
+				sizeof(struct tegra_ehci_platform_data));
+	pdev->dev.platform_data = platform_data;
+
+	val = platform_device_add(pdev);
+	if (val)
+		goto error_add;
+
+	return pdev;
+
+error_add:
+	kfree(platform_data);
+error:
+	pr_err("%s: failed to add the host contoller device\n", __func__);
+	platform_device_put(pdev);
+	return NULL;
+}
+
+static void tegra_usb_otg_host_unregister(struct platform_device *pdev)
+{
+	kfree(pdev->dev.platform_data);
+	platform_device_unregister(pdev);
+}
+
+static struct tegra_otg_platform_data tegra_otg_pdata = {
+	.host_register = &tegra_usb_otg_host_register,
+	.host_unregister = &tegra_usb_otg_host_unregister,
+};
+
+static void ventana_usb_init(void)
+{
+	tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
+	platform_device_register(&tegra_otg_device);
+
+	tegra_ehci3_device.dev.platform_data=&tegra_ehci_pdata[2];
+	platform_device_register(&tegra_ehci3_device);
+}
+
+static int __init ventana_gps_init(void)
+{
+	struct clk *clk32 = clk_get_sys(NULL, "blink");
+	if (!IS_ERR(clk32)) {
+		clk_set_rate(clk32,clk32->parent->rate);
+		clk_enable(clk32);
+	}
+
+	tegra_gpio_enable(TEGRA_GPIO_PZ3);
+	return 0;
+}
+
+static void ventana_power_off(void)
+{
+	int ret;
+
+	ret = tps6586x_power_off();
+	if (ret)
+		pr_err("ventana: failed to power off\n");
+
+	while(1);
+}
+
+static void __init ventana_power_off_init(void)
+{
+	pm_power_off = ventana_power_off;
+}
 
 static void __init tegra_ventana_init(void)
 {
 	char serial[20];
+#if defined(CONFIG_TOUCHSCREEN_PANJIT_I2C) || \
+	defined(CONFIG_TOUCHSCREEN_ATMEL_MT_T9)
+	struct board_info BoardInfo;
+#endif
 
 	tegra_common_init();
 	tegra_clk_init_from_table(ventana_clk_init_table);
 	ventana_pinmux_init();
-
+	ventana_i2c_init();
 	snprintf(serial, sizeof(serial), "%llx", tegra_chip_uid());
 	andusb_plat.serial_number = kstrdup(serial, GFP_KERNEL);
+	tegra_i2s_device1.dev.platform_data = &tegra_audio_pdata[0];
+	tegra_i2s_device2.dev.platform_data = &tegra_audio_pdata[1];
+	tegra_spdif_device.dev.platform_data = &tegra_spdif_pdata;
+	tegra_das_device.dev.platform_data = &tegra_das_pdata;
+	tegra_ehci2_device.dev.platform_data
+		= &ventana_ehci2_ulpi_platform_data;
 	platform_add_devices(ventana_devices, ARRAY_SIZE(ventana_devices));
 
 	ventana_sdhci_init();
-	ventana_i2c_init();
+	ventana_charge_init();
 	ventana_regulator_init();
-	ventana_touch_init();
+
+#if defined(CONFIG_TOUCHSCREEN_PANJIT_I2C) || \
+	defined(CONFIG_TOUCHSCREEN_ATMEL_MT_T9)
+
+	tegra_get_board_info(&BoardInfo);
+
+	/* boards with sku > 0 have atmel touch panels */
+	if (BoardInfo.sku) {
+		pr_info("Initializing Atmel touch driver\n");
+		ventana_touch_init_atmel();
+	} else {
+		pr_info("Initializing Panjit touch driver\n");
+		ventana_touch_init_panjit();
+	}
+#endif
+
+#ifdef CONFIG_KEYBOARD_GPIO
 	ventana_keys_init();
+#endif
+#ifdef CONFIG_KEYBOARD_TEGRA
+	ventana_kbc_init();
+#endif
+
+	ventana_usb_init();
+	ventana_gps_init();
 	ventana_panel_init();
+	ventana_sensors_init();
+	ventana_bt_rfkill();
+	ventana_power_off_init();
+	ventana_emc_init();
+}
+
+int __init tegra_ventana_protected_aperture_init(void)
+{
+	tegra_protected_aperture_init(tegra_grhost_aperture);
+	return 0;
+}
+late_initcall(tegra_ventana_protected_aperture_init);
+
+void __init tegra_ventana_reserve(void)
+{
+	if (memblock_reserve(0x0, 4096) < 0)
+		pr_warn("Cannot reserve first 4K of memory for safety\n");
+
+	tegra_reserve(SZ_256M, SZ_8M, SZ_16M);
 }
 
 MACHINE_START(VENTANA, "ventana")
@@ -270,5 +742,6 @@ MACHINE_START(VENTANA, "ventana")
 	.init_irq       = tegra_init_irq,
 	.init_machine   = tegra_ventana_init,
 	.map_io         = tegra_map_common_io,
+	.reserve        = tegra_ventana_reserve,
 	.timer          = &tegra_timer,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-ventana.h b/arch/arm/mach-tegra/board-ventana.h
index 39703583249d..2c929c435935 100644
--- a/arch/arm/mach-tegra/board-ventana.h
+++ b/arch/arm/mach-tegra/board-ventana.h
@@ -17,9 +17,27 @@
 #ifndef _MACH_TEGRA_BOARD_VENTANA_H
 #define _MACH_TEGRA_BOARD_VENTANA_H
 
+int ventana_charge_init(void);
 int ventana_regulator_init(void);
 int ventana_sdhci_init(void);
 int ventana_pinmux_init(void);
 int ventana_panel_init(void);
+int ventana_sensors_init(void);
+int ventana_kbc_init(void);
+int ventana_emc_init(void);
+
+/* external gpios */
+
+/* TPS6586X gpios */
+#define TPS6586X_GPIO_BASE	TEGRA_NR_GPIOS
+#define AVDD_DSI_CSI_ENB_GPIO	TPS6586X_GPIO_BASE + 1 /* gpio2 */
+
+/* TCA6416 gpios */
+#define TCA6416_GPIO_BASE	TEGRA_NR_GPIOS + 4
+#define CAM2_PWR_DN_GPIO	TCA6416_GPIO_BASE + 4 /* gpio4 */
+#define CAM2_RST_L_GPIO		TCA6416_GPIO_BASE + 5 /* gpio5 */
+#define CAM2_AF_PWR_DN_L_GPIO	TCA6416_GPIO_BASE + 6 /* gpio6 */
+#define CAM2_LDO_SHUTDN_L_GPIO	TCA6416_GPIO_BASE + 7 /* gpio7 */
+#define CAM2_I2C_MUX_RST_GPIO	TCA6416_GPIO_BASE + 15 /* gpio15 */
 
 #endif
diff --git a/arch/arm/mach-tegra/board-whistler-baseband.c b/arch/arm/mach-tegra/board-whistler-baseband.c
new file mode 100755
index 000000000000..c91089c01558
--- /dev/null
+++ b/arch/arm/mach-tegra/board-whistler-baseband.c
@@ -0,0 +1,243 @@
+/*
+ * arch/arm/mach-tegra/board-whistler-baseband.c
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/resource.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/err.h>
+#include <linux/tegra_usb.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/pinmux.h>
+#include <mach/usb_phy.h>
+
+#include "devices.h"
+#include "gpio-names.h"
+
+#define MODEM_PWR_ON	TEGRA_GPIO_PV1
+#define MODEM_RESET	TEGRA_GPIO_PV0
+
+/* Rainbow1 and 570 */
+#define AWR		TEGRA_GPIO_PZ0
+#define CWR		TEGRA_GPIO_PY6
+#define SPI_INT		TEGRA_GPIO_PO6
+#define SPI_SLAVE_SEL	TEGRA_GPIO_PV2
+
+/* PH450 */
+#define AP2MDM_ACK2	TEGRA_GPIO_PU2
+#define MDM2AP_ACK2	TEGRA_GPIO_PV2
+
+static int rainbow_570_reset(void);
+static int rainbow_570_handshake(void);
+static int ph450_reset(void);
+static int ph450_handshake(void);
+
+static __initdata struct tegra_pingroup_config whistler_null_ulpi_pinmux[] = {
+	{TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP,
+	 TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP,
+	 TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL,
+	 TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD4, TEGRA_PUPD_NORMAL,
+	 TEGRA_TRI_NORMAL},
+};
+
+static struct tegra_ulpi_trimmer e951_trimmer = { 10, 1, 1, 1 };
+
+static struct tegra_ulpi_config ehci2_null_ulpi_phy_config = {
+	.inf_type = TEGRA_USB_NULL_ULPI,
+	.trimmer = &e951_trimmer,
+	.preinit = rainbow_570_reset,
+	.postinit = rainbow_570_handshake,
+};
+
+static struct tegra_ehci_platform_data ehci2_null_ulpi_platform_data = {
+	.operating_mode = TEGRA_USB_HOST,
+	.power_down_on_bus_suspend = 0,
+	.phy_config = &ehci2_null_ulpi_phy_config,
+};
+
+static int __init tegra_null_ulpi_init(void)
+{
+	tegra_ehci2_device.dev.platform_data = &ehci2_null_ulpi_platform_data;
+	platform_device_register(&tegra_ehci2_device);
+	return 0;
+}
+
+static int __init rainbow_570_init(void)
+{
+	int ret;
+
+	ret = gpio_request(MODEM_PWR_ON, "mdm_power");
+	if (ret)
+		return ret;
+
+	ret = gpio_request(MODEM_RESET, "mdm_reset");
+	if (ret) {
+		gpio_free(MODEM_PWR_ON);
+		return ret;
+	}
+	ret = gpio_request(AWR, "mdm_awr");
+	if (ret) {
+		gpio_free(MODEM_PWR_ON);
+		gpio_free(MODEM_RESET);
+		return ret;
+	}
+	ret = gpio_request(CWR, "mdm_cwr");
+	if (ret) {
+		gpio_free(MODEM_PWR_ON);
+		gpio_free(MODEM_RESET);
+		gpio_free(AWR);
+		return ret;
+	}
+
+	tegra_gpio_enable(MODEM_PWR_ON);
+	tegra_gpio_enable(MODEM_RESET);
+	tegra_gpio_enable(AWR);
+	tegra_gpio_enable(CWR);
+
+	gpio_direction_output(MODEM_PWR_ON, 0);
+	gpio_direction_output(MODEM_RESET, 0);
+	gpio_direction_output(AWR, 0);
+	gpio_direction_input(CWR);
+
+	return 0;
+}
+
+static int rainbow_570_reset(void)
+{
+	gpio_set_value(AWR, 0);
+	gpio_set_value(MODEM_PWR_ON, 0);
+	gpio_set_value(MODEM_RESET, 0);
+	mdelay(300);
+	gpio_set_value(MODEM_RESET, 1);
+	mdelay(300);
+
+	/* pulse modem power on for 1200 ms */
+	gpio_set_value(MODEM_PWR_ON, 1);
+	mdelay(1200);
+	gpio_set_value(MODEM_PWR_ON, 0);
+	mdelay(100);
+
+	return 0;
+}
+
+static int rainbow_570_handshake(void)
+{
+	/* set AWR high */
+	gpio_set_value(AWR, 1);
+
+	/* wait for CWR high if modem firmware requires */
+
+	return 0;
+}
+
+static int __init ph450_init(void)
+{
+	int ret;
+
+	ret = gpio_request(MODEM_PWR_ON, "mdm_power");
+	if (ret)
+		return ret;
+
+	ret = gpio_request(MODEM_RESET, "mdm_reset");
+	if (ret) {
+		gpio_free(MODEM_PWR_ON);
+		return ret;
+	}
+	ret = gpio_request(AP2MDM_ACK2, "ap2mdm_ack2");
+	if (ret) {
+		gpio_free(MODEM_PWR_ON);
+		gpio_free(MODEM_RESET);
+		return ret;
+	}
+	ret = gpio_request(MDM2AP_ACK2, "mdm2ap_ack2");
+	if (ret) {
+		gpio_free(MODEM_PWR_ON);
+		gpio_free(MODEM_RESET);
+		gpio_free(AP2MDM_ACK2);
+		return ret;
+	}
+
+	/* enable pull-up for MDM2AP_ACK2 */
+	tegra_pinmux_set_pullupdown(TEGRA_PINGROUP_UAC, TEGRA_PUPD_PULL_UP);
+
+	tegra_gpio_enable(MODEM_PWR_ON);
+	tegra_gpio_enable(MODEM_RESET);
+	tegra_gpio_enable(AP2MDM_ACK2);
+	tegra_gpio_enable(MDM2AP_ACK2);
+
+	gpio_direction_output(MODEM_PWR_ON, 0);
+	gpio_direction_output(MODEM_RESET, 0);
+	gpio_direction_output(AP2MDM_ACK2, 1);
+	gpio_direction_input(MDM2AP_ACK2);
+
+	return 0;
+}
+
+static int ph450_reset(void)
+{
+	gpio_set_value(AP2MDM_ACK2, 1);
+	gpio_set_value(MODEM_PWR_ON, 0);
+	gpio_set_value(MODEM_RESET, 0);
+	mdelay(200);
+	gpio_set_value(MODEM_RESET, 1);
+
+	return 0;
+}
+
+static int ph450_handshake(void)
+{
+	while (1) {
+		/* wait for MDM2AP_ACK2 low */
+		int val = gpio_get_value(MDM2AP_ACK2);
+		if (!val) {
+			printk("MDM2AP_ACK2 detected\n");
+			break;
+		} else {
+			printk(".");
+			mdelay(100);
+		}
+	}
+
+	/* set AP2MDM_ACK2 low */
+	gpio_set_value(AP2MDM_ACK2, 0);
+	return 0;
+}
+
+int __init whistler_baseband_init(void)
+{
+	int ret;
+
+	tegra_pinmux_config_table(whistler_null_ulpi_pinmux,
+				  ARRAY_SIZE(whistler_null_ulpi_pinmux));
+
+	ret = rainbow_570_init();
+	if (ret) {
+		pr_err("modem init failed\n");
+		return ret;
+	}
+
+	tegra_null_ulpi_init();
+
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-whistler-kbc.c b/arch/arm/mach-tegra/board-whistler-kbc.c
new file mode 100644
index 000000000000..ca62d8570115
--- /dev/null
+++ b/arch/arm/mach-tegra/board-whistler-kbc.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (C) 2010 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/device.h>
+
+#include <mach/clk.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/iomap.h>
+#include <mach/io.h>
+#include <mach/kbc.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+/*
+* Scrollwheel is connected to KBC pins but has it's own
+* driver using those pins as gpio.
+* In case of using scrollwheel  Row3 and Col3/4/5
+* should NOT be configured as KBC
+*/
+#ifdef CONFIG_INPUT_ALPS_GPIO_SCROLLWHEEL
+#define WHISTLER_ROW_COUNT	2
+#define WHISTLER_COL_COUNT	2
+#else
+#define WHISTLER_ROW_COUNT	4
+#define WHISTLER_COL_COUNT	2
+#endif
+
+#ifdef CONFIG_INPUT_ALPS_GPIO_SCROLLWHEEL
+static int plain_kbd_keycode[] = {
+	KEY_POWER, KEY_RESERVED,
+	KEY_HOME,  KEY_BACK,
+};
+#else
+static int plain_kbd_keycode[] = {
+	KEY_POWER,      KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_HOME,       KEY_BACK,     KEY_RESERVED, KEY_RESERVED,
+	KEY_RESERVED,   KEY_RESERVED, KEY_RESERVED, KEY_RESERVED,
+	KEY_VOLUMEDOWN, KEY_VOLUMEUP, KEY_RESERVED, KEY_RESERVED,
+};
+#endif
+static struct tegra_kbc_wake_key whistler_wake_cfg[] = {
+	[0] = {
+		.row = 0,
+		.col = 0,
+	},
+};
+
+static struct tegra_kbc_platform_data whistler_kbc_platform_data = {
+	.debounce_cnt = 20,
+	.repeat_cnt = 50 * 32,
+	.scan_timeout_cnt = 3000 * 32,
+	.plain_keycode = plain_kbd_keycode,
+	.fn_keycode = NULL,
+	.is_filter_keys = false,
+	.is_wake_on_any_key = false,
+	.wake_key_cnt = 1,
+	.wake_cfg = &whistler_wake_cfg[0],
+};
+
+static struct resource whistler_kbc_resources[] = {
+	[0] = {
+		.start = TEGRA_KBC_BASE,
+		.end   = TEGRA_KBC_BASE + TEGRA_KBC_SIZE - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = INT_KBC,
+		.end   = INT_KBC,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device whistler_kbc_device = {
+	.name = "tegra-kbc",
+	.id = -1,
+	.dev = {
+		.platform_data = &whistler_kbc_platform_data,
+	},
+	.resource = whistler_kbc_resources,
+	.num_resources = ARRAY_SIZE(whistler_kbc_resources),
+};
+
+int __init whistler_kbc_init(void)
+{
+	struct tegra_kbc_platform_data *data = &whistler_kbc_platform_data;
+	int i;
+
+	pr_info("KBC: whistler_kbc_init\n");
+
+	/* Setup the pin configuration information. */
+	for (i = 0; i < KBC_MAX_GPIO; i++) {
+		data->pin_cfg[i].num = 0;
+		data->pin_cfg[i].pin_type = kbc_pin_unused;
+	}
+
+	for (i = 0; i < WHISTLER_ROW_COUNT; i++) {
+		data->pin_cfg[i].num = i;
+		data->pin_cfg[i].pin_type = kbc_pin_row;
+	}
+	for (i = 0; i < WHISTLER_COL_COUNT; i++) {
+		data->pin_cfg[i + WHISTLER_ROW_COUNT].num = i;
+		data->pin_cfg[i + WHISTLER_ROW_COUNT].pin_type = kbc_pin_col;
+	}
+
+	platform_device_register(&whistler_kbc_device);
+	return 0;
+}
+
+
+
diff --git a/arch/arm/mach-tegra/board-whistler-panel.c b/arch/arm/mach-tegra/board-whistler-panel.c
new file mode 100644
index 000000000000..72fa6207eda5
--- /dev/null
+++ b/arch/arm/mach-tegra/board-whistler-panel.c
@@ -0,0 +1,344 @@
+/*
+ * arch/arm/mach-tegra/board-whistler-panel.c
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/resource.h>
+#include <asm/mach-types.h>
+#include <linux/platform_device.h>
+#include <linux/pwm_backlight.h>
+#include <mach/nvhost.h>
+#include <mach/nvmap.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/dc.h>
+#include <mach/fb.h>
+
+#include "devices.h"
+#include "gpio-names.h"
+#include "board.h"
+
+#define whistler_bl_enb		TEGRA_GPIO_PW1
+#define whistler_hdmi_hpd	TEGRA_GPIO_PN7
+
+static struct regulator *whistler_hdmi_reg = NULL;
+static struct regulator *whistler_hdmi_pll = NULL;
+
+static int whistler_backlight_init(struct device *dev) {
+	int ret;
+
+	ret = gpio_request(whistler_bl_enb, "backlight_enb");
+	if (ret < 0)
+		return ret;
+
+	ret = gpio_direction_output(whistler_bl_enb, 1);
+	if (ret < 0)
+		gpio_free(whistler_bl_enb);
+	else
+		tegra_gpio_enable(whistler_bl_enb);
+
+	return ret;
+};
+
+static void whistler_backlight_exit(struct device *dev) {
+	gpio_set_value(whistler_bl_enb, 0);
+	gpio_free(whistler_bl_enb);
+	tegra_gpio_disable(whistler_bl_enb);
+}
+
+static int whistler_backlight_notify(struct device *unused, int brightness)
+{
+	gpio_set_value(whistler_bl_enb, !!brightness);
+	return brightness;
+}
+
+static struct platform_pwm_backlight_data whistler_backlight_data = {
+	.pwm_id		= 2,
+	.max_brightness	= 255,
+	.dft_brightness	= 224,
+	.pwm_period_ns	= 5000000,
+	.init		= whistler_backlight_init,
+	.exit		= whistler_backlight_exit,
+	.notify		= whistler_backlight_notify,
+};
+
+static struct platform_device whistler_backlight_device = {
+	.name	= "pwm-backlight",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &whistler_backlight_data,
+	},
+};
+
+static int whistler_hdmi_enable(void)
+{
+	if (!whistler_hdmi_reg) {
+		whistler_hdmi_reg = regulator_get(NULL, "avdd_hdmi"); /* LD011 */
+		if (IS_ERR_OR_NULL(whistler_hdmi_reg)) {
+			pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
+			whistler_hdmi_reg = NULL;
+			return PTR_ERR(whistler_hdmi_reg);
+		}
+	}
+	regulator_enable(whistler_hdmi_reg);
+
+	if (!whistler_hdmi_pll) {
+		whistler_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll"); /* LD06 */
+		if (IS_ERR_OR_NULL(whistler_hdmi_pll)) {
+			pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
+			whistler_hdmi_pll = NULL;
+			regulator_disable(whistler_hdmi_reg);
+			whistler_hdmi_reg = NULL;
+			return PTR_ERR(whistler_hdmi_pll);
+		}
+	}
+	regulator_enable(whistler_hdmi_pll);
+	return 0;
+}
+
+static int whistler_hdmi_disable(void)
+{
+	regulator_disable(whistler_hdmi_reg);
+	regulator_disable(whistler_hdmi_pll);
+	return 0;
+}
+
+static struct resource whistler_disp1_resources[] = {
+	{
+		.name	= "irq",
+		.start	= INT_DISPLAY_GENERAL,
+		.end	= INT_DISPLAY_GENERAL,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "regs",
+		.start	= TEGRA_DISPLAY_BASE,
+		.end	= TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "fbmem",
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct resource whistler_disp2_resources[] = {
+	{
+		.name	= "irq",
+		.start	= INT_DISPLAY_B_GENERAL,
+		.end	= INT_DISPLAY_B_GENERAL,
+		.flags	= IORESOURCE_IRQ,
+	},
+	{
+		.name	= "regs",
+		.start	= TEGRA_DISPLAY2_BASE,
+		.end	= TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "fbmem",
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.name	= "hdmi_regs",
+		.start	= TEGRA_HDMI_BASE,
+		.end	= TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct tegra_dc_mode whistler_panel_modes[] = {
+	{
+		.pclk = 27000000,
+		.h_ref_to_sync = 4,
+		.v_ref_to_sync = 2,
+		.h_sync_width = 10,
+		.v_sync_width = 3,
+		.h_back_porch = 20,
+		.v_back_porch = 3,
+		.h_active = 800,
+		.v_active = 480,
+		.h_front_porch = 70,
+		.v_front_porch = 3,
+	},
+};
+
+static struct tegra_dc_out_pin whistler_dc_out_pins[] = {
+	{
+		.name	= TEGRA_DC_OUT_PIN_H_SYNC,
+		.pol	= TEGRA_DC_OUT_PIN_POL_LOW,
+	},
+	{
+		.name	= TEGRA_DC_OUT_PIN_V_SYNC,
+		.pol	= TEGRA_DC_OUT_PIN_POL_LOW,
+	},
+	{
+		.name	= TEGRA_DC_OUT_PIN_PIXEL_CLOCK,
+		.pol	= TEGRA_DC_OUT_PIN_POL_LOW,
+	},
+};
+
+static struct tegra_dc_out whistler_disp1_out = {
+	.type		= TEGRA_DC_OUT_RGB,
+
+	.align		= TEGRA_DC_ALIGN_MSB,
+	.order		= TEGRA_DC_ORDER_RED_BLUE,
+
+	.modes	 	= whistler_panel_modes,
+	.n_modes 	= ARRAY_SIZE(whistler_panel_modes),
+
+	.out_pins	= whistler_dc_out_pins,
+	.n_out_pins	= ARRAY_SIZE(whistler_dc_out_pins),
+
+};
+
+static struct tegra_dc_out whistler_disp2_out = {
+	.type		= TEGRA_DC_OUT_HDMI,
+	.flags		= TEGRA_DC_OUT_HOTPLUG_HIGH,
+
+	.dcc_bus	= 1,
+	.hotplug_gpio	= whistler_hdmi_hpd,
+
+	.align		= TEGRA_DC_ALIGN_MSB,
+	.order		= TEGRA_DC_ORDER_RED_BLUE,
+
+	.enable		= whistler_hdmi_enable,
+	.disable	= whistler_hdmi_disable,
+};
+
+static struct tegra_fb_data whistler_fb_data = {
+	.win		= 0,
+	.xres		= 800,
+	.yres		= 480,
+	.bits_per_pixel	= 32,
+};
+
+static struct tegra_fb_data whistler_hdmi_fb_data = {
+	.win		= 0,
+	.xres		= 800,
+	.yres		= 480,
+	.bits_per_pixel	= 32,
+};
+
+
+static struct tegra_dc_platform_data whistler_disp1_pdata = {
+	.flags		= TEGRA_DC_FLAG_ENABLED,
+	.default_out	= &whistler_disp1_out,
+	.fb		= &whistler_fb_data,
+};
+
+static struct nvhost_device whistler_disp1_device = {
+	.name		= "tegradc",
+	.id		= 0,
+	.resource	= whistler_disp1_resources,
+	.num_resources	= ARRAY_SIZE(whistler_disp1_resources),
+	.dev = {
+		.platform_data = &whistler_disp1_pdata,
+	},
+};
+
+static struct tegra_dc_platform_data whistler_disp2_pdata = {
+	.flags		= 0,
+	.default_out	= &whistler_disp2_out,
+	.fb		= &whistler_hdmi_fb_data,
+};
+
+static struct nvhost_device whistler_disp2_device = {
+	.name		= "tegradc",
+	.id		= 1,
+	.resource	= whistler_disp2_resources,
+	.num_resources	= ARRAY_SIZE(whistler_disp2_resources),
+	.dev = {
+		.platform_data = &whistler_disp2_pdata,
+	},
+};
+
+static struct nvmap_platform_carveout whistler_carveouts[] = {
+	[0] = {
+		.name		= "iram",
+		.usage_mask	= NVMAP_HEAP_CARVEOUT_IRAM,
+		.base		= TEGRA_IRAM_BASE,
+		.size		= TEGRA_IRAM_SIZE,
+		.buddy_size	= 0, /* no buddy allocation for IRAM */
+	},
+	[1] = {
+		.name		= "generic-0",
+		.usage_mask	= NVMAP_HEAP_CARVEOUT_GENERIC,
+		.base		= 0x18C00000,
+		.size		= SZ_128M - 0xC00000,
+		.buddy_size	= SZ_32K,
+	},
+};
+
+static struct nvmap_platform_data whistler_nvmap_data = {
+	.carveouts	= whistler_carveouts,
+	.nr_carveouts	= ARRAY_SIZE(whistler_carveouts),
+};
+
+static struct platform_device whistler_nvmap_device = {
+	.name	= "tegra-nvmap",
+	.id	= -1,
+	.dev	= {
+		.platform_data = &whistler_nvmap_data,
+	},
+};
+
+static struct platform_device *whistler_gfx_devices[] __initdata = {
+	&whistler_nvmap_device,
+	&tegra_grhost_device,
+	&tegra_pwfm2_device,
+	&whistler_backlight_device,
+};
+
+int __init whistler_panel_init(void)
+{
+	int err;
+	struct resource *res;
+
+	tegra_gpio_enable(whistler_hdmi_hpd);
+	gpio_request(whistler_hdmi_hpd, "hdmi_hpd");
+	gpio_direction_input(whistler_hdmi_hpd);
+
+	whistler_carveouts[1].base = tegra_carveout_start;
+	whistler_carveouts[1].size = tegra_carveout_size;
+
+	err = platform_add_devices(whistler_gfx_devices,
+				   ARRAY_SIZE(whistler_gfx_devices));
+
+	res = nvhost_get_resource_byname(&whistler_disp1_device,
+					 IORESOURCE_MEM, "fbmem");
+	res->start = tegra_fb_start;
+	res->end = tegra_fb_start + tegra_fb_size - 1;
+
+	res = nvhost_get_resource_byname(&whistler_disp2_device,
+					 IORESOURCE_MEM, "fbmem");
+	res->start = tegra_fb2_start;
+	res->end = tegra_fb2_start + tegra_fb2_size - 1;
+
+	if (!err)
+		err = nvhost_device_register(&whistler_disp1_device);
+
+	if (!err)
+		err = nvhost_device_register(&whistler_disp2_device);
+
+	return err;
+}
+
diff --git a/arch/arm/mach-tegra/board-whistler-pinmux.c b/arch/arm/mach-tegra/board-whistler-pinmux.c
new file mode 100644
index 000000000000..d2e1de48b70a
--- /dev/null
+++ b/arch/arm/mach-tegra/board-whistler-pinmux.c
@@ -0,0 +1,166 @@
+/*
+ * arch/arm/mach-tegra/board-whistler-pinmux.c
+ *
+ * Copyright (C) 2010 NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <mach/pinmux.h>
+
+#define DEFAULT_DRIVE(_name)					\
+	{							\
+		.pingroup = TEGRA_DRIVE_PINGROUP_##_name,	\
+		.hsm = TEGRA_HSM_DISABLE,			\
+		.schmitt = TEGRA_SCHMITT_ENABLE,		\
+		.drive = TEGRA_DRIVE_DIV_1,			\
+		.pull_down = TEGRA_PULL_31,			\
+		.pull_up = TEGRA_PULL_31,			\
+		.slew_rising = TEGRA_SLEW_SLOWEST,		\
+		.slew_falling = TEGRA_SLEW_SLOWEST,		\
+	}
+
+
+static __initdata struct tegra_drive_pingroup_config whistler_drive_pinmux[] = {
+	DEFAULT_DRIVE(DBG),
+	DEFAULT_DRIVE(DDC),
+	DEFAULT_DRIVE(VI1),
+	DEFAULT_DRIVE(VI2),
+	DEFAULT_DRIVE(SDIO1),
+};
+
+static __initdata struct tegra_pingroup_config whistler_pinmux[] = {
+	{TEGRA_PINGROUP_ATA,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATB,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATC,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATD,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_OSC,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DTA,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DTB,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DTC,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DTD,   TEGRA_MUX_VI,            TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DTE,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GMA,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GMC,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GMD,   TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GME,   TEGRA_MUX_DAP5,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTB,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCB,  TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCD,  TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LCSN,  TEGRA_MUX_SPI3,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSCK,  TEGRA_MUX_SPI3,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSDA,  TEGRA_MUX_SPI3,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSDI,  TEGRA_MUX_SPI3,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_OWC,   TEGRA_MUX_OWR,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SDB,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_SDIO3,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_SDIO3,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SPIA,  TEGRA_MUX_SPI3,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIB,  TEGRA_MUX_SPI3,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIC,  TEGRA_MUX_SPI3,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI2,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_UAA,   TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_UAB,   TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_UAC,   TEGRA_MUX_OWR,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_UDA,   TEGRA_MUX_SPI1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+};
+
+void __init whistler_pinmux_init(void)
+{
+	tegra_pinmux_config_table(whistler_pinmux, ARRAY_SIZE(whistler_pinmux));
+	tegra_drive_pinmux_config_table(whistler_drive_pinmux,
+					ARRAY_SIZE(whistler_drive_pinmux));
+}
diff --git a/arch/arm/mach-tegra/board-whistler-power.c b/arch/arm/mach-tegra/board-whistler-power.c
new file mode 100644
index 000000000000..51029caac974
--- /dev/null
+++ b/arch/arm/mach-tegra/board-whistler-power.c
@@ -0,0 +1,258 @@
+/*
+ * Copyright (C) 2010 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+#include <linux/i2c.h>
+#include <linux/pda_power.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/max8907c.h>
+#include <linux/regulator/max8907c-regulator.h>
+#include <linux/gpio.h>
+#include <mach/suspend.h>
+#include <linux/io.h>
+
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+
+#include "gpio-names.h"
+#include "fuse.h"
+#include "power.h"
+#include "wakeups-t2.h"
+#include "board.h"
+
+#define PMC_CTRL		0x0
+ #define PMC_CTRL_INTR_LOW	(1 << 17)
+
+static struct regulator_consumer_supply max8907c_SD1_supply[] = {
+	REGULATOR_SUPPLY("vdd_cpu", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_SD2_supply[] = {
+	REGULATOR_SUPPLY("vdd_core", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_SD3_supply[] = {
+	REGULATOR_SUPPLY("vddio_sys", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO1_supply[] = {
+	REGULATOR_SUPPLY("vddio_rx_ddr", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO2_supply[] = {
+	REGULATOR_SUPPLY("avdd_plla", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO3_supply[] = {
+	REGULATOR_SUPPLY("vdd_vcom_1v8b", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO4_supply[] = {
+	REGULATOR_SUPPLY("avdd_usb", NULL),
+	REGULATOR_SUPPLY("avdd_usb_pll", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO5_supply[] = {
+};
+
+static struct regulator_consumer_supply max8907c_LDO6_supply[] = {
+	REGULATOR_SUPPLY("avdd_hdmi_pll", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO7_supply[] = {
+	REGULATOR_SUPPLY("avddio_audio", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO8_supply[] = {
+	REGULATOR_SUPPLY("vdd_vcom_3v0", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO9_supply[] = {
+	REGULATOR_SUPPLY("vdd_cam1", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO10_supply[] = {
+	REGULATOR_SUPPLY("avdd_usb_ic", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO11_supply[] = {
+	REGULATOR_SUPPLY("vddio_pex_clk", NULL),
+	REGULATOR_SUPPLY("avdd_hdmi", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO12_supply[] = {
+	REGULATOR_SUPPLY("vddio_sdio", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO13_supply[] = {
+	REGULATOR_SUPPLY("vdd_vcore_phtn", NULL),
+	REGULATOR_SUPPLY("vdd_vcore_af", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO14_supply[] = {
+	REGULATOR_SUPPLY("avdd_vdac", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO15_supply[] = {
+	REGULATOR_SUPPLY("vdd_vcore_temp", NULL),
+	REGULATOR_SUPPLY("vdd_vcore_hdcp", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO16_supply[] = {
+	REGULATOR_SUPPLY("vdd_vbrtr", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO17_supply[] = {
+	REGULATOR_SUPPLY("vddio_mipi", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO18_supply[] = {
+	REGULATOR_SUPPLY("vcsi", "tegra_camera"),
+};
+
+static struct regulator_consumer_supply max8907c_LDO19_supply[] = {
+	REGULATOR_SUPPLY("vddio_lx", NULL),
+};
+
+static struct regulator_consumer_supply max8907c_LDO20_supply[] = {
+	REGULATOR_SUPPLY("vddio_ddr_1v2", NULL),
+	REGULATOR_SUPPLY("vddio_hsic", NULL),
+};
+
+#define MAX8907C_REGULATOR_DEVICE(_id, _minmv, _maxmv)			\
+static struct regulator_init_data max8907c_##_id##_data = {		\
+	.constraints = {						\
+		.min_uV = (_minmv),					\
+		.max_uV = (_maxmv),					\
+		.valid_modes_mask = (REGULATOR_MODE_NORMAL |		\
+				     REGULATOR_MODE_STANDBY),		\
+		.valid_ops_mask = (REGULATOR_CHANGE_MODE |		\
+				   REGULATOR_CHANGE_STATUS |		\
+				   REGULATOR_CHANGE_VOLTAGE),		\
+	},								\
+	.num_consumer_supplies = ARRAY_SIZE(max8907c_##_id##_supply),	\
+	.consumer_supplies = max8907c_##_id##_supply,			\
+};									\
+static struct platform_device max8907c_##_id##_device = {		\
+	.name	= "max8907c-regulator",					\
+	.id	= MAX8907C_##_id,					\
+	.dev	= {							\
+		.platform_data = &max8907c_##_id##_data,		\
+	},								\
+}
+
+MAX8907C_REGULATOR_DEVICE(SD1, 637500, 1425000);
+MAX8907C_REGULATOR_DEVICE(SD2, 637500, 1425000);
+MAX8907C_REGULATOR_DEVICE(SD3, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO1, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO2, 650000, 2225000);
+MAX8907C_REGULATOR_DEVICE(LDO3, 650000, 2225000);
+MAX8907C_REGULATOR_DEVICE(LDO4, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO5, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO6, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO7, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO8, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO9, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO10, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO11, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO12, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO13, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO14, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO15, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO16, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO17, 650000, 2225000);
+MAX8907C_REGULATOR_DEVICE(LDO18, 650000, 2225000);
+MAX8907C_REGULATOR_DEVICE(LDO19, 750000, 3900000);
+MAX8907C_REGULATOR_DEVICE(LDO20, 750000, 3900000);
+
+static struct platform_device *whistler_max8907c_power_devices[] = {
+	&max8907c_SD1_device,
+	&max8907c_SD2_device,
+	&max8907c_SD3_device,
+	&max8907c_LDO1_device,
+	&max8907c_LDO2_device,
+	&max8907c_LDO3_device,
+	&max8907c_LDO4_device,
+	&max8907c_LDO5_device,
+	&max8907c_LDO6_device,
+	&max8907c_LDO7_device,
+	&max8907c_LDO8_device,
+	&max8907c_LDO9_device,
+	&max8907c_LDO10_device,
+	&max8907c_LDO11_device,
+	&max8907c_LDO12_device,
+	&max8907c_LDO13_device,
+	&max8907c_LDO14_device,
+	&max8907c_LDO15_device,
+	&max8907c_LDO16_device,
+	&max8907c_LDO17_device,
+	&max8907c_LDO18_device,
+	&max8907c_LDO19_device,
+	&max8907c_LDO20_device,
+};
+
+static struct max8907c_platform_data max8907c_pdata = {
+	.num_subdevs = ARRAY_SIZE(whistler_max8907c_power_devices),
+	.subdevs = whistler_max8907c_power_devices,
+};
+
+static struct i2c_board_info __initdata whistler_regulators[] = {
+	{
+		I2C_BOARD_INFO("max8907c", 0x3C),
+		.platform_data	= &max8907c_pdata,
+	},
+};
+
+static struct tegra_suspend_platform_data whistler_suspend_data = {
+	.cpu_timer	= 2000,
+	.cpu_off_timer	= 1000,
+	.suspend_mode	= TEGRA_SUSPEND_LP0,
+	.core_timer	= 0x7e7e,
+	.core_off_timer = 0xf,
+	.separate_req	= true,
+	.corereq_high	= true,
+	.sysclkreq_high	= true,
+	.wake_enb	= TEGRA_WAKE_KBC_EVENT,
+	.wake_high	= 0,
+	.wake_low	= 0,
+	.wake_any	= TEGRA_WAKE_KBC_EVENT,
+};
+
+int __init whistler_regulator_init(void)
+{
+	void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+	void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
+	u32 pmc_ctrl;
+	u32 minor;
+
+	minor = (readl(chip_id) >> 16) & 0xf;
+	/* A03 (but not A03p) chips do not support LP0 */
+	if (minor == 3 && !(tegra_spare_fuse(18) || tegra_spare_fuse(19)))
+		whistler_suspend_data.suspend_mode = TEGRA_SUSPEND_LP1;
+
+	/* configure the power management controller to trigger PMU
+	 * interrupts when low */
+	pmc_ctrl = readl(pmc + PMC_CTRL);
+	writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL);
+
+	i2c_register_board_info(4, whistler_regulators, 1);
+
+	tegra_init_suspend(&whistler_suspend_data);
+
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-whistler-sdhci.c b/arch/arm/mach-tegra/board-whistler-sdhci.c
new file mode 100644
index 000000000000..71b461ff6566
--- /dev/null
+++ b/arch/arm/mach-tegra/board-whistler-sdhci.c
@@ -0,0 +1,269 @@
+/*
+ * arch/arm/mach-tegra/board-harmony-sdhci.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/resource.h>
+#include <linux/platform_device.h>
+#include <linux/wlan_plat.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mmc/host.h>
+
+#include <asm/mach-types.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/sdhci.h>
+
+#include "gpio-names.h"
+#include "board.h"
+
+#define WHISTLER_WLAN_PWR	TEGRA_GPIO_PK5
+#define WHISTLER_WLAN_RST	TEGRA_GPIO_PK6
+
+#define WHISTLER_EXT_SDCARD_DETECT	TEGRA_GPIO_PI5
+
+static void (*wifi_status_cb)(int card_present, void *dev_id);
+static void *wifi_status_cb_devid;
+
+static int whistler_wifi_status_register(
+		void (*sdhcicallback)(int card_present, void *dev_id),
+		void *dev_id)
+{
+	if (wifi_status_cb)
+		return -EAGAIN;
+	wifi_status_cb = sdhcicallback;
+	wifi_status_cb_devid = dev_id;
+	return 0;
+}
+
+static int whistler_wifi_set_carddetect(int val)
+{
+	pr_debug("%s: %d\n", __func__, val);
+	if (wifi_status_cb)
+		wifi_status_cb(val, wifi_status_cb_devid);
+	else
+		pr_warning("%s: Nobody to notify\n", __func__);
+	return 0;
+}
+
+static int whistler_wifi_power(int on)
+{
+	gpio_set_value(WHISTLER_WLAN_PWR, on);
+	mdelay(100);
+	gpio_set_value(WHISTLER_WLAN_RST, on);
+	mdelay(200);
+
+	return 0;
+}
+
+static int whistler_wifi_reset(int on)
+{
+	pr_debug("%s: do nothing\n", __func__);
+	return 0;
+}
+
+
+static struct wifi_platform_data whistler_wifi_control = {
+	.set_power      = whistler_wifi_power,
+	.set_reset      = whistler_wifi_reset,
+	.set_carddetect = whistler_wifi_set_carddetect,
+};
+
+static struct platform_device whistler_wifi_device = {
+	.name           = "bcm4329_wlan",
+	.id             = 1,
+	.dev            = {
+		.platform_data = &whistler_wifi_control,
+	},
+};
+
+
+static struct resource sdhci_resource0[] = {
+	[0] = {
+		.start  = INT_SDMMC1,
+		.end    = INT_SDMMC1,
+		.flags  = IORESOURCE_IRQ,
+	},
+	[1] = {
+		.start	= TEGRA_SDMMC1_BASE,
+		.end	= TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+static struct resource sdhci_resource1[] = {
+	[0] = {
+		.start  = INT_SDMMC2,
+		.end    = INT_SDMMC2,
+		.flags  = IORESOURCE_IRQ,
+	},
+	[1] = {
+		.start	= TEGRA_SDMMC2_BASE,
+		.end	= TEGRA_SDMMC2_BASE + TEGRA_SDMMC2_SIZE-1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+
+static struct resource sdhci_resource2[] = {
+	[0] = {
+		.start  = INT_SDMMC3,
+		.end    = INT_SDMMC3,
+		.flags  = IORESOURCE_IRQ,
+	},
+	[1] = {
+		.start	= TEGRA_SDMMC3_BASE,
+		.end	= TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct resource sdhci_resource3[] = {
+	[0] = {
+		.start  = INT_SDMMC4,
+		.end    = INT_SDMMC4,
+		.flags  = IORESOURCE_IRQ,
+	},
+	[1] = {
+		.start	= TEGRA_SDMMC4_BASE,
+		.end	= TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
+	.clk_id = NULL,
+	.force_hs = 0,
+	.cd_gpio = -1,
+	.wp_gpio = -1,
+	.power_gpio = -1,
+};
+
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data1 = {
+	.clk_id = NULL,
+	.force_hs = 0,
+	.register_status_notify	= whistler_wifi_status_register,
+	.cccr   = {
+		.sdio_vsn       = 2,
+		.multi_block    = 1,
+		.low_speed      = 0,
+		.wide_bus       = 0,
+		.high_power     = 1,
+		.high_speed     = 1,
+	},
+	.cis  = {
+		.vendor         = 0x02d0,
+		.device         = 0x4329,
+	},
+	.cd_gpio = -1,
+	.wp_gpio = -1,
+	.power_gpio = -1,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
+	.clk_id = NULL,
+	.force_hs = 0,
+	.cd_gpio = WHISTLER_EXT_SDCARD_DETECT,
+	.wp_gpio = -1,
+	.power_gpio = -1,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
+	.clk_id = NULL,
+	.force_hs = 0,
+	.cd_gpio = -1,
+	.wp_gpio = -1,
+	.power_gpio = -1,
+};
+
+static struct platform_device tegra_sdhci_device0 = {
+	.name		= "sdhci-tegra",
+	.id		= 0,
+	.resource	= sdhci_resource0,
+	.num_resources	= ARRAY_SIZE(sdhci_resource0),
+	.dev = {
+		.platform_data = &tegra_sdhci_platform_data0,
+	},
+};
+
+static struct platform_device tegra_sdhci_device1 = {
+	.name		= "sdhci-tegra",
+	.id		= 1,
+	.resource	= sdhci_resource1,
+	.num_resources	= ARRAY_SIZE(sdhci_resource1),
+	.dev = {
+		.platform_data = &tegra_sdhci_platform_data1,
+	},
+};
+
+static struct platform_device tegra_sdhci_device2 = {
+	.name		= "sdhci-tegra",
+	.id		= 2,
+	.resource	= sdhci_resource2,
+	.num_resources	= ARRAY_SIZE(sdhci_resource2),
+	.dev = {
+		.platform_data = &tegra_sdhci_platform_data2,
+	},
+};
+
+static struct platform_device tegra_sdhci_device3 = {
+	.name		= "sdhci-tegra",
+	.id		= 3,
+	.resource	= sdhci_resource3,
+	.num_resources	= ARRAY_SIZE(sdhci_resource3),
+	.dev = {
+		.platform_data = &tegra_sdhci_platform_data3,
+	},
+};
+
+static int __init whistler_wifi_init(void)
+{
+	gpio_request(WHISTLER_WLAN_PWR, "wlan_power");
+	gpio_request(WHISTLER_WLAN_RST, "wlan_rst");
+
+	tegra_gpio_enable(WHISTLER_WLAN_PWR);
+	tegra_gpio_enable(WHISTLER_WLAN_RST);
+
+	gpio_direction_output(WHISTLER_WLAN_PWR, 0);
+	gpio_direction_output(WHISTLER_WLAN_RST, 0);
+
+	platform_device_register(&whistler_wifi_device);
+	return 0;
+}
+
+int __init whistler_sdhci_init(void)
+{
+	int ret;
+
+	ret = gpio_request(WHISTLER_EXT_SDCARD_DETECT, "card_detect");
+	if (ret < 0) {
+		tegra_sdhci_platform_data2.cd_gpio = -1;
+		pr_err("card_detect gpio not found\n");
+	}
+	else {
+		tegra_gpio_enable(WHISTLER_EXT_SDCARD_DETECT);
+		gpio_direction_input(WHISTLER_EXT_SDCARD_DETECT);
+	}
+
+	platform_device_register(&tegra_sdhci_device3);
+	platform_device_register(&tegra_sdhci_device2);
+	platform_device_register(&tegra_sdhci_device1);
+	platform_device_register(&tegra_sdhci_device0);
+
+	whistler_wifi_init();
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-whistler-sensors.c b/arch/arm/mach-tegra/board-whistler-sensors.c
new file mode 100644
index 000000000000..a882e437baf9
--- /dev/null
+++ b/arch/arm/mach-tegra/board-whistler-sensors.c
@@ -0,0 +1,169 @@
+/*
+ * arch/arm/mach-tegra/board-whistler-sensors.c
+ *
+ * Copyright (c) 2010, NVIDIA, All Rights Reserved.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#include <linux/i2c.h>
+#include <mach/gpio.h>
+#include <media/ov5650.h>
+#include <linux/regulator/consumer.h>
+#include <linux/err.h>
+#include "gpio-names.h"
+
+#define CAMERA1_PWDN_GPIO		TEGRA_GPIO_PT2
+#define CAMERA1_RESET_GPIO		TEGRA_GPIO_PD2
+#define CAMERA_AF_PD_GPIO		TEGRA_GPIO_PT3
+#define CAMERA_FLASH_EN1_GPIO	TEGRA_GPIO_PBB4
+#define CAMERA_FLASH_EN2_GPIO	TEGRA_GPIO_PA0
+
+#define ADXL34X_IRQ_GPIO		TEGRA_GPIO_PAA1
+#define ISL29018_IRQ_GPIO		TEGRA_GPIO_PK2
+
+static struct regulator *reg_avdd_cam1; /* LDO9 */
+static struct regulator *reg_vdd_af;    /* LDO13 */
+
+static int whistler_camera_init(void)
+{
+	tegra_gpio_enable(CAMERA1_PWDN_GPIO);
+	gpio_request(CAMERA1_PWDN_GPIO, "camera1_powerdown");
+	gpio_direction_output(CAMERA1_PWDN_GPIO, 0);
+
+	tegra_gpio_enable(CAMERA1_RESET_GPIO);
+	gpio_request(CAMERA1_RESET_GPIO, "camera1_reset");
+	gpio_direction_output(CAMERA1_RESET_GPIO, 0);
+
+	tegra_gpio_enable(CAMERA_AF_PD_GPIO);
+	gpio_request(CAMERA_AF_PD_GPIO, "camera_autofocus");
+	gpio_direction_output(CAMERA_AF_PD_GPIO, 0);
+	gpio_export(CAMERA_AF_PD_GPIO, false);
+
+	tegra_gpio_enable(CAMERA_FLASH_EN1_GPIO);
+	gpio_request(CAMERA_FLASH_EN1_GPIO, "camera_flash_en1");
+	gpio_direction_output(CAMERA_FLASH_EN1_GPIO, 0);
+	gpio_export(CAMERA_FLASH_EN1_GPIO, false);
+
+	tegra_gpio_enable(CAMERA_FLASH_EN2_GPIO);
+	gpio_request(CAMERA_FLASH_EN2_GPIO, "camera_flash_en2");
+	gpio_direction_output(CAMERA_FLASH_EN2_GPIO, 0);
+	gpio_export(CAMERA_FLASH_EN2_GPIO, false);
+
+	return 0;
+}
+
+static int whistler_ov5650_power_on(void)
+{
+	gpio_set_value(CAMERA1_PWDN_GPIO, 1);
+	gpio_set_value(CAMERA1_RESET_GPIO, 1);
+	gpio_set_value(CAMERA_AF_PD_GPIO, 1);
+
+	if (!reg_avdd_cam1) {
+		reg_avdd_cam1 = regulator_get(NULL, "vdd_cam1");
+		if (IS_ERR_OR_NULL(reg_avdd_cam1)) {
+			pr_err("whistler_ov5650_power_on: vdd_cam1 failed\n");
+			reg_avdd_cam1 = NULL;
+			return PTR_ERR(reg_avdd_cam1);
+		}
+		regulator_enable(reg_avdd_cam1);
+	}
+
+	if (!reg_vdd_af) {
+		reg_vdd_af = regulator_get(NULL, "vdd_vcore_af");
+		if (IS_ERR_OR_NULL(reg_vdd_af)) {
+			pr_err("whistler_ov5650_power_on: vdd_vcore_af failed\n");
+			reg_vdd_af = NULL;
+			return PTR_ERR(reg_vdd_af);
+		}
+		regulator_enable(reg_vdd_af);
+	}
+
+	return 0;
+}
+
+static int whistler_ov5650_power_off(void)
+{
+	gpio_set_value(CAMERA1_PWDN_GPIO, 0);
+	gpio_set_value(CAMERA1_RESET_GPIO, 0);
+	gpio_set_value(CAMERA_AF_PD_GPIO, 0);
+
+	if (reg_avdd_cam1) {
+		regulator_disable(reg_avdd_cam1);
+		regulator_put(reg_avdd_cam1);
+		reg_avdd_cam1 = NULL;
+	}
+
+	if (reg_vdd_af) {
+		regulator_disable(reg_vdd_af);
+		regulator_put(reg_vdd_af);
+		reg_vdd_af = NULL;
+	}
+	return 0;
+}
+
+struct ov5650_platform_data whistler_ov5650_data = {
+	.power_on = whistler_ov5650_power_on,
+	.power_off = whistler_ov5650_power_off,
+};
+
+static struct i2c_board_info whistler_i2c3_board_info[] = {
+	{
+		I2C_BOARD_INFO("ov5650", 0x36),
+		.platform_data = &whistler_ov5650_data,
+	},
+};
+
+static void whistler_adxl34x_init(void)
+{
+	tegra_gpio_enable(ADXL34X_IRQ_GPIO);
+	gpio_request(ADXL34X_IRQ_GPIO, "adxl34x");
+	gpio_direction_input(ADXL34X_IRQ_GPIO);
+}
+
+static void whistler_isl29018_init(void)
+{
+	tegra_gpio_enable(ISL29018_IRQ_GPIO);
+	gpio_request(ISL29018_IRQ_GPIO, "isl29018");
+	gpio_direction_input(ISL29018_IRQ_GPIO);
+}
+
+static struct i2c_board_info whistler_i2c1_board_info[] = {
+	{
+		I2C_BOARD_INFO("adxl34x", 0x1D),
+		.irq = TEGRA_GPIO_TO_IRQ(ADXL34X_IRQ_GPIO),
+	},
+	{
+		I2C_BOARD_INFO("isl29018", 0x44),
+		.irq = TEGRA_GPIO_TO_IRQ(ISL29018_IRQ_GPIO),
+	},
+};
+
+int __init whistler_sensors_init(void)
+{
+	whistler_camera_init();
+
+	whistler_adxl34x_init();
+
+	whistler_isl29018_init();
+
+	i2c_register_board_info(0, whistler_i2c1_board_info,
+		ARRAY_SIZE(whistler_i2c1_board_info));
+
+	i2c_register_board_info(3, whistler_i2c3_board_info,
+		ARRAY_SIZE(whistler_i2c3_board_info));
+
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/board-whistler.c b/arch/arm/mach-tegra/board-whistler.c
new file mode 100644
index 000000000000..87445a41779e
--- /dev/null
+++ b/arch/arm/mach-tegra/board-whistler.c
@@ -0,0 +1,572 @@
+/*
+ * arch/arm/mach-tegra/board-whistler.c
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/synaptics_i2c_rmi.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/i2c-tegra.h>
+#include <linux/gpio.h>
+#include <linux/gpio_scrollwheel.h>
+#include <linux/input.h>
+#include <linux/tegra_usb.h>
+#include <linux/usb/android_composite.h>
+#include <linux/memblock.h>
+
+#include <mach/clk.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/iomap.h>
+#include <mach/io.h>
+#include <mach/i2s.h>
+#include <mach/audio.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/usb_phy.h>
+#include <mach/tegra_das.h>
+
+#include "board.h"
+#include "clock.h"
+#include "board-whistler.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "fuse.h"
+
+static struct plat_serial8250_port debug_uart_platform_data[] = {
+	{
+		.membase	= IO_ADDRESS(TEGRA_UARTA_BASE),
+		.mapbase	= TEGRA_UARTA_BASE,
+		.irq		= INT_UARTA,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= 216000000,
+	}, {
+		.flags		= 0,
+	}
+};
+
+static struct platform_device debug_uart = {
+	.name = "serial8250",
+	.id = PLAT8250_DEV_PLATFORM,
+	.dev = {
+		.platform_data = debug_uart_platform_data,
+	},
+};
+
+#ifdef CONFIG_BCM4329_RFKILL
+
+static struct resource whistler_bcm4329_rfkill_resources[] = {
+	{
+		.name	= "bcm4329_nshutdown_gpio",
+		.start	= TEGRA_GPIO_PU0,
+		.end	= TEGRA_GPIO_PU0,
+		.flags	= IORESOURCE_IO,
+	},
+};
+
+static struct platform_device whistler_bcm4329_rfkill_device = {
+	.name		= "bcm4329_rfkill",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(whistler_bcm4329_rfkill_resources),
+	.resource	= whistler_bcm4329_rfkill_resources,
+};
+
+static noinline void __init whistler_bt_rfkill(void)
+{
+	platform_device_register(&whistler_bcm4329_rfkill_device);
+	return;
+}
+#else
+static inline void whistler_bt_rfkill(void) { }
+#endif
+
+static struct tegra_utmip_config utmi_phy_config[] = {
+	[0] = {
+			.hssync_start_delay = 0,
+			.idle_wait_delay = 17,
+			.elastic_limit = 16,
+			.term_range_adj = 6,
+			.xcvr_setup = 15,
+			.xcvr_lsfslew = 2,
+			.xcvr_lsrslew = 2,
+		},
+	[1] = {
+			.hssync_start_delay = 0,
+			.idle_wait_delay = 17,
+			.elastic_limit = 16,
+			.term_range_adj = 6,
+			.xcvr_setup = 8,
+			.xcvr_lsfslew = 2,
+			.xcvr_lsrslew = 2,
+		},
+};
+
+static struct tegra_ulpi_config ulpi_phy_config = {
+	.reset_gpio = TEGRA_GPIO_PG2,
+	.clk = "clk_dev2",
+};
+
+static __initdata struct tegra_clk_init_table whistler_clk_init_table[] = {
+	/* name		parent		rate		enabled */
+	{ "uarta",	"pll_p",	216000000,	true},
+	{ "uartc",	"pll_m",	600000000,	false},
+	{ "pwm",	"clk_32k",	32768,		false},
+	{ "kbc",	"clk_32k",	32768,		true},
+	{ "pll_a",	NULL,		11289600,	true},
+	{ "pll_a_out0",	NULL,		11289600,	true},
+	{ "i2s1",	"pll_a_out0",	11289600,	true},
+	{ "i2s2",	"pll_a_out0",	11289600,	true},
+	{ "audio",	"pll_a_out0",	11289600,	true},
+	{ "audio_2x",	"audio",	22579200,	true},
+	{ "sdmmc2",	"pll_p",	25000000,	false},
+	{ NULL,		NULL,		0,		0},
+};
+
+static char *usb_functions[] = { "mtp" };
+static char *usb_functions_adb[] = { "mtp", "adb" };
+
+static struct android_usb_product usb_products[] = {
+	{
+		.product_id     = 0x7102,
+		.num_functions  = ARRAY_SIZE(usb_functions),
+		.functions      = usb_functions,
+	},
+	{
+		.product_id     = 0x7100,
+		.num_functions  = ARRAY_SIZE(usb_functions_adb),
+		.functions      = usb_functions_adb,
+	},
+};
+
+/* standard android USB platform data */
+static struct android_usb_platform_data andusb_plat = {
+	.vendor_id              = 0x0955,
+	.product_id             = 0x7100,
+	.manufacturer_name      = "NVIDIA",
+	.product_name           = "Whistler",
+	.serial_number          = NULL,
+	.num_products = ARRAY_SIZE(usb_products),
+	.products = usb_products,
+	.num_functions = ARRAY_SIZE(usb_functions_adb),
+	.functions = usb_functions_adb,
+};
+
+static struct platform_device androidusb_device = {
+	.name   = "android_usb",
+	.id     = -1,
+	.dev    = {
+		.platform_data  = &andusb_plat,
+	},
+};
+
+static struct tegra_i2c_platform_data whistler_i2c1_platform_data = {
+	.adapter_nr	= 0,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 400000, 0 },
+};
+
+static const struct tegra_pingroup_config i2c2_ddc = {
+	.pingroup	= TEGRA_PINGROUP_DDC,
+	.func		= TEGRA_MUX_I2C2,
+};
+
+static const struct tegra_pingroup_config i2c2_gen2 = {
+	.pingroup	= TEGRA_PINGROUP_PTA,
+	.func		= TEGRA_MUX_I2C2,
+};
+
+static struct tegra_i2c_platform_data whistler_i2c2_platform_data = {
+	.adapter_nr	= 1,
+	.bus_count	= 2,
+	.bus_clk_rate	= { 400000, 100000 },
+	.bus_mux	= { &i2c2_ddc, &i2c2_gen2 },
+	.bus_mux_len	= { 1, 1 },
+};
+
+static struct tegra_i2c_platform_data whistler_i2c3_platform_data = {
+	.adapter_nr	= 3,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 400000, 0 },
+};
+
+static struct tegra_i2c_platform_data whistler_dvc_platform_data = {
+	.adapter_nr	= 4,
+	.bus_count	= 1,
+	.bus_clk_rate	= { 400000, 0 },
+	.is_dvc		= true,
+};
+
+static struct tegra_das_platform_data tegra_das_pdata = {
+	.tegra_dap_port_info_table = {
+		[0] = {
+			.dac_port = tegra_das_port_none,
+			.codec_type = tegra_audio_codec_type_none,
+			.device_property = {
+				.num_channels = 0,
+				.bits_per_sample = 0,
+				.rate = 0,
+				.dac_dap_data_comm_format = 0,
+			},
+		},
+		/* I2S1 <--> DAC1 <--> DAP1 <--> Hifi Codec */
+		[1] = {
+			.dac_port = tegra_das_port_i2s1,
+			.codec_type = tegra_audio_codec_type_hifi,
+			.device_property = {
+				.num_channels = 2,
+				.bits_per_sample = 16,
+				.rate = 44100,
+				.dac_dap_data_comm_format = dac_dap_data_format_i2s,
+			},
+		},
+		[2] = {
+			.dac_port = tegra_das_port_none,
+			.codec_type = tegra_audio_codec_type_none,
+			.device_property = {
+				.num_channels = 0,
+				.bits_per_sample = 0,
+				.rate = 0,
+				.dac_dap_data_comm_format = 0,
+			},
+		},
+		[3] = {
+			.dac_port = tegra_das_port_none,
+			.codec_type = tegra_audio_codec_type_none,
+			.device_property = {
+				.num_channels = 0,
+				.bits_per_sample = 0,
+				.rate = 0,
+				.dac_dap_data_comm_format = 0,
+			},
+		},
+		[4] = {
+			.dac_port = tegra_das_port_none,
+			.codec_type = tegra_audio_codec_type_none,
+			.device_property = {
+				.num_channels = 0,
+				.bits_per_sample = 0,
+				.rate = 0,
+				.dac_dap_data_comm_format = 0,
+			},
+		},
+	},
+
+	.tegra_das_con_table = {
+		[0] = {
+			.con_id = tegra_das_port_con_id_hifi,
+			.num_entries = 2,
+			.con_line = {
+				[0] = {tegra_das_port_i2s1, tegra_das_port_dap1, true},
+				[1] = {tegra_das_port_dap1, tegra_das_port_i2s1, false},
+			},
+		},
+	}
+};
+
+static void whistler_i2c_init(void)
+{
+	tegra_i2c_device1.dev.platform_data = &whistler_i2c1_platform_data;
+	tegra_i2c_device2.dev.platform_data = &whistler_i2c2_platform_data;
+	tegra_i2c_device3.dev.platform_data = &whistler_i2c3_platform_data;
+	tegra_i2c_device4.dev.platform_data = &whistler_dvc_platform_data;
+
+	platform_device_register(&tegra_i2c_device4);
+	platform_device_register(&tegra_i2c_device3);
+	platform_device_register(&tegra_i2c_device2);
+	platform_device_register(&tegra_i2c_device1);
+}
+
+
+static struct tegra_audio_platform_data tegra_audio_pdata[] = {
+	/* For I2S1 */
+	[0] = {
+		.i2s_master	= true,
+		.dsp_master	= false,
+		.dma_on		= true,  /* use dma by default */
+		.i2s_master_clk = 44100,
+		.dsp_master_clk = 8000,
+		.i2s_clk_rate	= 240000000,
+		.dap_clk	= "clk_dev1",
+		.audio_sync_clk = "audio_2x",
+		.mode		= I2S_BIT_FORMAT_I2S,
+		.fifo_fmt	= I2S_FIFO_PACKED,
+		.bit_size	= I2S_BIT_SIZE_16,
+		.i2s_bus_width = 32,
+		.dsp_bus_width = 16,
+	},
+	/* For I2S2 */
+	[1] = {
+		.i2s_master	= false,
+		.dsp_master	= true,
+		.dma_on		= true,  /* use dma by default */
+		.i2s_master_clk = 44100,
+		.dsp_master_clk = 8000,
+		.i2s_clk_rate	= 240000000,
+		.dap_clk	= "clk_dev1",
+		.audio_sync_clk = "audio_2x",
+		.mode		= I2S_BIT_FORMAT_DSP,
+		.fifo_fmt	= I2S_FIFO_16_LSB,
+		.bit_size	= I2S_BIT_SIZE_16,
+		.i2s_bus_width = 32,
+		.dsp_bus_width = 16,
+	}
+};
+
+
+#define GPIO_SCROLL(_pinaction, _gpio, _desc)	\
+{	\
+	.pinaction = GPIO_SCROLLWHEEL_PIN_##_pinaction, \
+	.gpio = TEGRA_GPIO_##_gpio,	\
+	.desc = _desc,	\
+	.active_low = 1,	\
+	.debounce_interval = 2,	\
+}
+
+static struct gpio_scrollwheel_button scroll_keys[] = {
+	[0] = GPIO_SCROLL(ONOFF, PR3, "sw_onoff"),
+	[1] = GPIO_SCROLL(PRESS, PQ5, "sw_press"),
+	[2] = GPIO_SCROLL(ROT1, PQ3, "sw_rot1"),
+	[3] = GPIO_SCROLL(ROT2, PQ4, "sw_rot2"),
+};
+
+static struct gpio_scrollwheel_platform_data whistler_scroll_platform_data = {
+	.buttons = scroll_keys,
+	.nbuttons = ARRAY_SIZE(scroll_keys),
+};
+
+static struct platform_device whistler_scroll_device = {
+	.name	= "alps-gpio-scrollwheel",
+	.id	= 0,
+	.dev	= {
+		.platform_data	= &whistler_scroll_platform_data,
+	},
+};
+
+static struct platform_device tegra_camera = {
+	.name = "tegra_camera",
+	.id = -1,
+};
+
+static struct platform_device *whistler_devices[] __initdata = {
+	&androidusb_device,
+	&debug_uart,
+	&tegra_uartb_device,
+	&tegra_uartc_device,
+	&pmu_device,
+	&tegra_udc_device,
+	&tegra_gart_device,
+	&tegra_wdt_device,
+	&tegra_avp_device,
+	&whistler_scroll_device,
+	&tegra_camera,
+	&tegra_i2s_device1,
+	&tegra_i2s_device2,
+	&tegra_das_device,
+};
+
+static struct synaptics_i2c_rmi_platform_data synaptics_pdata= {
+	.flags			= SYNAPTICS_FLIP_X | SYNAPTICS_FLIP_Y | SYNAPTICS_SWAP_XY,
+	.irqflags		= IRQF_TRIGGER_LOW,
+};
+
+static const struct i2c_board_info whistler_i2c_touch_info[] = {
+	{
+		I2C_BOARD_INFO("synaptics-rmi-ts", 0x20),
+		.irq		= TEGRA_GPIO_TO_IRQ(TEGRA_GPIO_PC6),
+		.platform_data	= &synaptics_pdata,
+	},
+};
+
+static int __init whistler_touch_init(void)
+{
+	i2c_register_board_info(0, whistler_i2c_touch_info, 1);
+
+	return 0;
+}
+
+static int __init whistler_scroll_init(void)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(scroll_keys); i++)
+		tegra_gpio_enable(scroll_keys[i].gpio);
+
+	return 0;
+}
+
+
+static struct tegra_ehci_platform_data tegra_ehci_pdata[] = {
+	[0] = {
+			.phy_config = &utmi_phy_config[0],
+			.operating_mode = TEGRA_USB_HOST,
+			.power_down_on_bus_suspend = 0,
+		},
+	[1] = {
+			.phy_config = &ulpi_phy_config,
+			.operating_mode = TEGRA_USB_HOST,
+			.power_down_on_bus_suspend = 1,
+		},
+	[2] = {
+			.phy_config = &utmi_phy_config[1],
+			.operating_mode = TEGRA_USB_HOST,
+			.power_down_on_bus_suspend = 0,
+	},
+};
+
+static struct platform_device *tegra_usb_otg_host_register(void)
+{
+	struct platform_device *pdev;
+	void *platform_data;
+	int val;
+
+	pdev = platform_device_alloc(tegra_ehci1_device.name,
+			tegra_ehci1_device.id);
+	if (!pdev)
+		return NULL;
+
+	val = platform_device_add_resources(pdev, tegra_ehci1_device.resource,
+		tegra_ehci1_device.num_resources);
+	if (val)
+		goto error;
+
+	pdev->dev.dma_mask =  tegra_ehci1_device.dev.dma_mask;
+	pdev->dev.coherent_dma_mask = tegra_ehci1_device.dev.coherent_dma_mask;
+
+	platform_data = kmalloc(sizeof(struct tegra_ehci_platform_data),
+				GFP_KERNEL);
+	if (!platform_data)
+		goto error;
+
+	memcpy(platform_data, &tegra_ehci_pdata[0],
+				sizeof(struct tegra_ehci_platform_data));
+	pdev->dev.platform_data = platform_data;
+
+	val = platform_device_add(pdev);
+	if (val)
+		goto error_add;
+
+	return pdev;
+
+error_add:
+	kfree(platform_data);
+error:
+	pr_err("%s: failed to add the host contoller device\n", __func__);
+	platform_device_put(pdev);
+	return NULL;
+}
+
+static void tegra_usb_otg_host_unregister(struct platform_device *pdev)
+{
+	kfree(pdev->dev.platform_data);
+	platform_device_unregister(pdev);
+}
+
+static struct tegra_otg_platform_data tegra_otg_pdata = {
+	.host_register = &tegra_usb_otg_host_register,
+	.host_unregister = &tegra_usb_otg_host_unregister,
+};
+
+static void whistler_usb_init(void)
+{
+	tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
+	platform_device_register(&tegra_otg_device);
+
+	tegra_ehci3_device.dev.platform_data=&tegra_ehci_pdata[2];
+	platform_device_register(&tegra_ehci3_device);
+}
+
+static int __init whistler_gps_init(void)
+{
+	tegra_gpio_enable(TEGRA_GPIO_PU4);
+	return 0;
+}
+
+static const struct i2c_board_info whistler_codec_info[] = {
+	{
+		I2C_BOARD_INFO("wm8753", 0x1a),
+	},
+};
+
+static void whistler_codec_init(void)
+{
+	i2c_register_board_info(4, whistler_codec_info, 1);
+}
+static void __init tegra_whistler_init(void)
+{
+	char serial[20];
+
+	tegra_common_init();
+	tegra_clk_init_from_table(whistler_clk_init_table);
+	whistler_pinmux_init();
+	whistler_i2c_init();
+	snprintf(serial, sizeof(serial), "%llx", tegra_chip_uid());
+	andusb_plat.serial_number = kstrdup(serial, GFP_KERNEL);
+	tegra_i2s_device1.dev.platform_data = &tegra_audio_pdata[0];
+	tegra_i2s_device2.dev.platform_data = &tegra_audio_pdata[1];
+	platform_add_devices(whistler_devices, ARRAY_SIZE(whistler_devices));
+
+	tegra_das_device.dev.platform_data = &tegra_das_pdata;
+
+	whistler_sdhci_init();
+	whistler_regulator_init();
+	whistler_panel_init();
+	whistler_sensors_init();
+	whistler_touch_init();
+	whistler_kbc_init();
+	whistler_bt_rfkill();
+	whistler_gps_init();
+	whistler_usb_init();
+	whistler_scroll_init();
+	whistler_codec_init();
+}
+
+int __init tegra_whistler_protected_aperture_init(void)
+{
+	tegra_protected_aperture_init(tegra_grhost_aperture);
+	return 0;
+}
+
+void __init tegra_whistler_reserve(void)
+{
+	if (memblock_reserve(0x0, 4096) < 0)
+		pr_warn("Cannot reserve first 4K of memory for safety\n");
+
+	tegra_reserve(SZ_128M, SZ_8M, SZ_16M);
+}
+
+MACHINE_START(WHISTLER, "whistler")
+	.boot_params    = 0x00000100,
+	.phys_io        = IO_APB_PHYS,
+	.io_pg_offst    = ((IO_APB_VIRT) >> 18) & 0xfffc,
+	.init_irq       = tegra_init_irq,
+	.init_machine   = tegra_whistler_init,
+	.map_io         = tegra_map_common_io,
+	.reserve        = tegra_whistler_reserve,
+	.timer          = &tegra_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-whistler.h b/arch/arm/mach-tegra/board-whistler.h
new file mode 100755
index 000000000000..f24f882c8a43
--- /dev/null
+++ b/arch/arm/mach-tegra/board-whistler.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-tegra/board-whistler.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MACH_TEGRA_BOARD_WHISTLER_H
+#define _MACH_TEGRA_BOARD_WHISTLER_H
+
+int whistler_regulator_init(void);
+int whistler_sdhci_init(void);
+int whistler_pinmux_init(void);
+int whistler_panel_init(void);
+int whistler_kbc_init(void);
+int whistler_sensors_init(void);
+int whistler_baseband_init(void);
+
+#endif
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 04f1538b1a37..8a25cf664e8d 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -47,4 +47,22 @@ extern unsigned long tegra_lp0_vec_size;
 extern unsigned long tegra_grhost_aperture;
 
 extern struct sys_timer tegra_timer;
+
+enum board_fab {
+	BOARD_FAB_A = 0,
+	BOARD_FAB_B,
+	BOARD_FAB_C,
+	BOARD_FAB_D,
+};
+
+struct board_info {
+	u16 board_id;
+	u16 sku;
+	u8  fab;
+	u8  major_revision;
+	u8  minor_revision;
+};
+
+void tegra_get_board_info(struct board_info *);
+
 #endif
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index e97cc2532aef..2ee342f35e2d 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -25,6 +25,7 @@
 #include <linux/module.h>
 #include <linux/seq_file.h>
 #include <linux/slab.h>
+#include <linux/uaccess.h>
 
 #include <asm/clkdev.h>
 
@@ -794,6 +795,88 @@ static const struct file_operations possible_parents_fops = {
 	.release	= single_release,
 };
 
+static int parent_show(struct seq_file *s, void *data)
+{
+	struct clk *c = s->private;
+	struct clk *p = clk_get_parent(c);
+
+	seq_printf(s, "%s\n", p ? p->name : "clk_root");
+	return 0;
+}
+
+static int parent_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, parent_show, inode->i_private);
+}
+
+static int rate_get(void *data, u64 *val)
+{
+	struct clk *c = (struct clk *)data;
+	*val = (u64)clk_get_rate(c);
+	return 0;
+}
+
+#ifdef CONFIG_TEGRA_CLOCK_DEBUG_WRITE
+
+static const mode_t parent_rate_mode =  S_IRUGO | S_IWUGO;
+
+static ssize_t parent_write(struct file *file,
+	const char __user *userbuf, size_t count, loff_t *ppos)
+{
+	struct seq_file *s = file->private_data;
+	struct clk *c = s->private;
+	struct clk *p = NULL;
+	char buf[32];
+
+	if (sizeof(buf) <= count)
+		return -EINVAL;
+
+	if (copy_from_user(buf, userbuf, count))
+		return -EFAULT;
+
+	/* terminate buffer and trim - white spaces may be appended
+	 *  at the end when invoked from shell command line */
+	buf[count]='\0';
+	strim(buf);
+
+	p = tegra_get_clock_by_name(buf);
+	if (!p)
+		return -EINVAL;
+
+	clk_set_parent(c, p);
+	return count;
+}
+
+static const struct file_operations parent_fops = {
+	.open		= parent_open,
+	.read		= seq_read,
+	.write		= parent_write,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int rate_set(void *data, u64 val)
+{
+	struct clk *c = (struct clk *)data;
+	clk_set_rate(c, (unsigned long)val);
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n");
+
+#else
+
+static const mode_t parent_rate_mode =  S_IRUGO;
+
+static const struct file_operations parent_fops = {
+	.open		= parent_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, NULL, "%llu\n");
+#endif
+
 static int clk_debugfs_register_one(struct clk *c)
 {
 	struct dentry *d, *child, *child_tmp;
@@ -807,11 +890,21 @@ static int clk_debugfs_register_one(struct clk *c)
 	if (!d)
 		goto err_out;
 
-	d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+	d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
 	if (!d)
 		goto err_out;
 
-	d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+	d = debugfs_create_u32("max", S_IRUGO, c->dent, (u32 *)&c->max_rate);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_file(
+		"parent", parent_rate_mode, c->dent, c, &parent_fops);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_file(
+		"rate", parent_rate_mode, c->dent, c, &rate_fops);
 	if (!d)
 		goto err_out;
 
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index f3319d30e29c..9337f6afc4c9 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -42,6 +42,8 @@
 #define PLLU			(1 << 14)
 #define ENABLE_ON_INIT		(1 << 28)
 
+#define MAX_SAME_LIMIT_SKU_IDS	16
+
 struct clk;
 
 struct clk_mux_sel {
@@ -152,6 +154,12 @@ struct tegra_clk_init_table {
 	bool enabled;
 };
 
+struct tegra_sku_rate_limit {
+	const char *clk_name;
+	unsigned long max_rate;
+	int sku_ids[MAX_SAME_LIMIT_SKU_IDS];
+};
+
 void tegra2_init_clocks(void);
 void tegra2_periph_reset_deassert(struct clk *c);
 void tegra2_periph_reset_assert(struct clk *c);
@@ -164,4 +172,15 @@ void clk_set_cansleep(struct clk *c);
 unsigned long clk_get_rate_locked(struct clk *c);
 void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
 
+#ifdef CONFIG_CPU_FREQ
+struct cpufreq_frequency_table;
+
+struct tegra_cpufreq_table_data {
+	struct cpufreq_frequency_table *freq_table;
+	int throttle_lowest_index;
+	int throttle_highest_index;
+};
+struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void);
+#endif
+
 #endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index a4b72dca2303..3baccca70ed6 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -33,6 +33,7 @@
 #include <mach/powergate.h>
 #include <mach/system.h>
 
+#include "apbio.h"
 #include "board.h"
 #include "clock.h"
 #include "fuse.h"
@@ -51,12 +52,21 @@ unsigned long tegra_lp0_vec_start;
 unsigned long tegra_lp0_vec_size;
 unsigned long tegra_grhost_aperture;
 
+static struct board_info tegra_board_info = {
+	.board_id = -1,
+	.sku = -1,
+	.fab = -1,
+	.major_revision = -1,
+	.minor_revision = -1,
+};
+
 void (*tegra_reset)(char mode, const char *cmd);
 
 static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
 	/* set up clocks that should always be on */
 	/* name		parent		rate		enabled */
 	{ "clk_m",	NULL,		0,		true },
+	{ "pll_m",	"clk_m",	600000000,	true },
 	{ "pll_p",	"clk_m",	216000000,	true },
 	{ "pll_p_out1",	"pll_p",	28800000,	true },
 	{ "pll_p_out2",	"pll_p",	48000000,	true },
@@ -70,6 +80,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
 	{ "emc",	NULL,		0,		true },
 	{ "csite",	NULL,		0,		true },
 	{ "timer", 	NULL,		0,		true },
+	{ "kfuse",	NULL,		0,		true },
 	{ "rtc",	NULL,		0,		true },
 
 	/* set frequencies of some device clocks */
@@ -140,7 +151,7 @@ void __init tegra_common_init(void)
 	tegra_init_power();
 	tegra_init_cache();
 	tegra_dma_init();
-	tegra_init_fuse_dma();
+	tegra_init_apb_dma();
 }
 
 static int __init tegra_bootloader_fb_arg(char *options)
@@ -170,6 +181,56 @@ static int __init tegra_lp0_vec_arg(char *options)
 }
 early_param("lp0_vec", tegra_lp0_vec_arg);
 
+static int __init tegra_board_info_parse(char *info)
+{
+	char *p;
+	int pos = 0;
+	struct board_info *bi = &tegra_board_info;
+
+	while (info && *info) {
+		if ((p = strchr(info, ':')))
+			*p++ = '\0';
+
+		if (strlen(info) > 0) {
+			switch(pos) {
+			case 0:
+				bi->board_id = simple_strtol(info, NULL, 16);
+				break;
+			case 1:
+				bi->sku = simple_strtol(info, NULL, 16);
+				break;
+			case 2:
+				bi->fab = simple_strtol(info, NULL, 16);
+				break;
+			case 3:
+				bi->major_revision = simple_strtol(info, NULL, 16);
+				break;
+			case 4:
+				bi->minor_revision = simple_strtol(info, NULL, 16);
+				break;
+			default:
+				break;
+			}
+		}
+
+		info = p;
+		pos++;
+	}
+
+	pr_info("board info: Id:%d%2d SKU:%d Fab:%d Rev:%c MinRev:%d\n",
+			bi->board_id >> 8 & 0xFF, bi->board_id & 0xFF,
+			bi->sku, bi->fab, bi->major_revision, bi->minor_revision);
+
+	return 1;
+}
+
+__setup("board_info=", tegra_board_info_parse);
+
+void tegra_get_board_info(struct board_info *bi)
+{
+	memcpy(bi, &tegra_board_info, sizeof(*bi));
+}
+
 /*
  * Tegra has a protected aperture that prevents access by most non-CPU
  * memory masters to addresses above the aperture value.  Enabling it
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index 3b8a6b56783e..21dedf62d14e 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -37,21 +37,9 @@
 #include <mach/hardware.h>
 #include <mach/clk.h>
 
-/*
- * Frequency table index must be sequential starting at 0 and frequencies
- * must be ascending.
- */
-static struct cpufreq_frequency_table freq_table[] = {
-	{ 0, 216000 },
-	{ 1, 312000 },
-	{ 2, 456000 },
-	{ 3, 608000 },
-	{ 4, 760000 },
-	{ 5, 816000 },
-	{ 6, 912000 },
-	{ 7, 1000000 },
-	{ 8, CPUFREQ_TABLE_END },
-};
+#include "clock.h"
+
+static struct cpufreq_frequency_table *freq_table;
 
 #define NUM_CPUS	2
 
@@ -68,11 +56,11 @@ static unsigned long tegra_cpu_highest_speed(void);
 
 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
 /* CPU frequency is gradually lowered when throttling is enabled */
-#define THROTTLE_LOWEST_INDEX	2 /* 456000 */
-#define THROTTLE_HIGHEST_INDEX	6 /* 912000 */
 #define THROTTLE_DELAY		msecs_to_jiffies(2000)
 
 static bool is_throttling;
+static int throttle_lowest_index;
+static int throttle_highest_index;
 static int throttle_index;
 static int throttle_next_index;
 static struct delayed_work throttle_work;
@@ -91,7 +79,7 @@ static void tegra_throttle_work_func(struct work_struct *work)
 	if (freq_table[throttle_index].frequency < current_freq)
 		tegra_update_cpu_speed(freq_table[throttle_index].frequency);
 
-	if (throttle_index > THROTTLE_LOWEST_INDEX) {
+	if (throttle_index > throttle_lowest_index) {
 		throttle_next_index = throttle_index - 1;
 		queue_delayed_work(workqueue, &throttle_work, THROTTLE_DELAY);
 	}
@@ -112,14 +100,14 @@ void tegra_throttling_enable(bool enable)
 
 		is_throttling = true;
 
-		for (throttle_index = THROTTLE_HIGHEST_INDEX;
-		     throttle_index >= THROTTLE_LOWEST_INDEX;
+		for (throttle_index = throttle_highest_index;
+		     throttle_index >= throttle_lowest_index;
 		     throttle_index--)
 			if (freq_table[throttle_index].frequency
 			    < current_freq)
 				break;
 
-		throttle_index = max(throttle_index, THROTTLE_LOWEST_INDEX);
+		throttle_index = max(throttle_index, throttle_lowest_index);
 		throttle_next_index = throttle_index;
 		queue_delayed_work(workqueue, &throttle_work, 0);
 	} else if (!enable && is_throttling) {
@@ -381,6 +369,10 @@ static struct cpufreq_driver tegra_cpufreq_driver = {
 
 static int __init tegra_cpufreq_init(void)
 {
+	struct tegra_cpufreq_table_data *table_data =
+		tegra_cpufreq_table_get();
+	BUG_ON(!table_data);
+
 #ifdef CONFIG_TEGRA_THERMAL_THROTTLE
 	/*
 	 * High-priority, others flags default: not bound to a specific
@@ -392,7 +384,11 @@ static int __init tegra_cpufreq_init(void)
 	if (!workqueue)
 		return -ENOMEM;
 	INIT_DELAYED_WORK(&throttle_work, tegra_throttle_work_func);
+
+	throttle_lowest_index = table_data->throttle_lowest_index;
+	throttle_highest_index = table_data->throttle_highest_index;
 #endif
+	freq_table = table_data->freq_table;
 	return cpufreq_register_driver(&tegra_cpufreq_driver);
 }
 
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index dac6bbbf0e2c..1bee4e58683b 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -518,6 +518,21 @@ struct platform_device tegra_spdif_device = {
 	.num_resources	= ARRAY_SIZE(spdif_resource),
 };
 
+static struct resource das_resource[] = {
+	[0] = {
+		.start	= TEGRA_APB_MISC_BASE,
+		.end	= TEGRA_APB_MISC_BASE + TEGRA_APB_MISC_SIZE - 1,
+		.flags	= IORESOURCE_MEM
+	}
+};
+
+struct platform_device tegra_das_device = {
+	.name		= "tegra_das",
+	.id		= -1,
+	.resource	= das_resource,
+	.num_resources	= ARRAY_SIZE(das_resource),
+};
+
 static struct resource tegra_gart_resources[] = {
 	[0] = {
 		.name	= "mc",
diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h
index 1c547257a34f..ca5934965a11 100644
--- a/arch/arm/mach-tegra/devices.h
+++ b/arch/arm/mach-tegra/devices.h
@@ -60,5 +60,6 @@ extern struct platform_device tegra_grhost_device;
 extern struct platform_device tegra_spdif_device;
 extern struct platform_device tegra_avp_device;
 extern struct platform_device tegra_aes_device;
+extern struct platform_device tegra_das_device;
 
 #endif
diff --git a/arch/arm/mach-tegra/dma.c b/arch/arm/mach-tegra/dma.c
index db94fcf58399..b054764aa214 100644
--- a/arch/arm/mach-tegra/dma.c
+++ b/arch/arm/mach-tegra/dma.c
@@ -477,7 +477,30 @@ static void tegra_dma_update_hw(struct tegra_dma_channel *ch,
 	u32 csr;
 
 	csr = CSR_IE_EOC | CSR_FLOW;
-	ahb_seq = AHB_SEQ_INTR_ENB | AHB_SEQ_BURST_1;
+	ahb_seq = AHB_SEQ_INTR_ENB;
+
+	switch(req->req_sel) {
+	case TEGRA_DMA_REQ_SEL_SL2B1:
+	case TEGRA_DMA_REQ_SEL_SL2B2:
+	case TEGRA_DMA_REQ_SEL_SL2B3:
+	case TEGRA_DMA_REQ_SEL_SL2B4:
+	case TEGRA_DMA_REQ_SEL_SPI:
+		/* For spi/slink the burst size based on transfer size
+		 * i.e. if multiple of 32 bytes then busrt is
+		 * 8 word else if multiple of 16 bytes then burst is
+		 * 4 word else burst size is 1 word */
+		if (req->size & 0xF)
+			ahb_seq |= AHB_SEQ_BURST_1;
+		else if ((req->size >> 4) & 0x1)
+			ahb_seq |= AHB_SEQ_BURST_4;
+		else
+			ahb_seq |= AHB_SEQ_BURST_8;
+		break;
+	default:
+		ahb_seq |= AHB_SEQ_BURST_1;
+		break;
+	}
+
 	apb_seq = 0;
 
 	csr |= req->req_sel << CSR_REQ_SEL_SHIFT;
diff --git a/arch/arm/mach-tegra/dvfs.h b/arch/arm/mach-tegra/dvfs.h
index 68622b899c59..a785a2edc530 100644
--- a/arch/arm/mach-tegra/dvfs.h
+++ b/arch/arm/mach-tegra/dvfs.h
@@ -61,7 +61,8 @@ struct dvfs_rail {
 struct dvfs {
 	/* Used only by tegra2_clock.c */
 	const char *clk_name;
-	int cpu_process_id;
+	int speedo_id;
+	int process_id;
 
 	/* Must be initialized before tegra_dvfs_init */
 	int freqs_mult;
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index fcb6d05495fb..1aa393c18323 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -19,30 +19,17 @@
 
 #include <linux/kernel.h>
 #include <linux/io.h>
-#include <linux/dma-mapping.h>
-#include <linux/spinlock.h>
-#include <linux/completion.h>
-#include <linux/sched.h>
-#include <linux/mutex.h>
 
-#include <mach/dma.h>
 #include <mach/iomap.h>
 
 #include "fuse.h"
+#include "apbio.h"
 
 #define FUSE_UID_LOW		0x108
 #define FUSE_UID_HIGH		0x10c
 #define FUSE_SKU_INFO		0x110
 #define FUSE_SPARE_BIT		0x200
 
-static DEFINE_MUTEX(tegra_fuse_dma_lock);
-
-#ifdef CONFIG_TEGRA_SYSTEM_DMA
-static struct tegra_dma_channel *tegra_fuse_dma;
-static u32 *tegra_fuse_bb;
-static dma_addr_t tegra_fuse_bb_phys;
-static DECLARE_COMPLETION(tegra_fuse_wait);
-
 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
 	[TEGRA_REVISION_UNKNOWN] = "unknown",
 	[TEGRA_REVISION_A02] = "A02",
@@ -50,102 +37,19 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
 	[TEGRA_REVISION_A03p] = "A03 prime",
 };
 
-static void fuse_dma_complete(struct tegra_dma_req *req)
-{
-	complete(&tegra_fuse_wait);
-}
-
-static inline u32 fuse_readl(unsigned long offset)
-{
-	struct tegra_dma_req req;
-	int ret;
-
-	if (!tegra_fuse_dma)
-		return readl(IO_TO_VIRT(TEGRA_FUSE_BASE + offset));
-
-	mutex_lock(&tegra_fuse_dma_lock);
-	req.complete = fuse_dma_complete;
-	req.to_memory = 1;
-	req.dest_addr = tegra_fuse_bb_phys;
-	req.dest_bus_width = 32;
-	req.dest_wrap = 1;
-	req.source_addr = TEGRA_FUSE_BASE + offset;
-	req.source_bus_width = 32;
-	req.source_wrap = 4;
-	req.req_sel = 0;
-	req.size = 4;
-
-	INIT_COMPLETION(tegra_fuse_wait);
-
-	tegra_dma_enqueue_req(tegra_fuse_dma, &req);
-
-	ret = wait_for_completion_timeout(&tegra_fuse_wait,
-		msecs_to_jiffies(50));
-
-	if (WARN(ret == 0, "fuse read dma timed out"))
-		*(u32 *)tegra_fuse_bb = 0;
-
-	mutex_unlock(&tegra_fuse_dma_lock);
-	return *((u32 *)tegra_fuse_bb);
-}
-
-static inline void fuse_writel(u32 value, unsigned long offset)
-{
-	struct tegra_dma_req req;
-	int ret;
-
-	if (!tegra_fuse_dma) {
-		writel(value, IO_TO_VIRT(TEGRA_FUSE_BASE + offset));
-		return;
-	}
-
-	mutex_lock(&tegra_fuse_dma_lock);
-	*((u32 *)tegra_fuse_bb) = value;
-	req.complete = fuse_dma_complete;
-	req.to_memory = 0;
-	req.dest_addr = TEGRA_FUSE_BASE + offset;
-	req.dest_wrap = 4;
-	req.dest_bus_width = 32;
-	req.source_addr = tegra_fuse_bb_phys;
-	req.source_bus_width = 32;
-	req.source_wrap = 1;
-	req.req_sel = 0;
-	req.size = 4;
-
-	INIT_COMPLETION(tegra_fuse_wait);
-
-	tegra_dma_enqueue_req(tegra_fuse_dma, &req);
-
-	ret = wait_for_completion_timeout(&tegra_fuse_wait,
-		msecs_to_jiffies(50));
-
-	mutex_unlock(&tegra_fuse_dma_lock);
-}
-#else
-static inline u32 fuse_readl(unsigned long offset)
-{
-	return readl(IO_TO_VIRT(TEGRA_FUSE_BASE + offset));
-}
-
-static inline void fuse_writel(u32 value, unsigned long offset)
-{
-	writel(value, IO_TO_VIRT(TEGRA_FUSE_BASE + offset));
-}
-#endif
-
 u32 tegra_fuse_readl(unsigned long offset)
 {
-	return fuse_readl(offset);
+	return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
 }
 
 void tegra_fuse_writel(u32 value, unsigned long offset)
 {
-	fuse_writel(value, offset);
+	tegra_apb_writel(value, TEGRA_FUSE_BASE + offset);
 }
 
 static inline bool get_spare_fuse(int bit)
 {
-	return fuse_readl(FUSE_SPARE_BIT + bit * 4);
+	return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
 }
 
 void tegra_init_fuse(void)
@@ -153,6 +57,7 @@ void tegra_init_fuse(void)
 	u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
 	reg |= 1 << 28;
 	writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+	tegra_init_speedo_data();
 
 	pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
 		tegra_revision_name[tegra_get_revision()],
@@ -160,60 +65,29 @@ void tegra_init_fuse(void)
 		tegra_core_process_id());
 }
 
-void tegra_init_fuse_dma(void)
-{
-#ifdef CONFIG_TEGRA_SYSTEM_DMA
-	tegra_fuse_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
-		TEGRA_DMA_SHARED);
-	if (!tegra_fuse_dma) {
-		pr_err("%s: can not allocate dma channel\n", __func__);
-		return;
-	}
-
-	tegra_fuse_bb = dma_alloc_coherent(NULL, sizeof(u32),
-		&tegra_fuse_bb_phys, GFP_KERNEL);
-	if (!tegra_fuse_bb) {
-		pr_err("%s: can not allocate bounce buffer\n", __func__);
-		tegra_dma_free_channel(tegra_fuse_dma);
-		tegra_fuse_dma = NULL;
-		return;
-	}
-#endif
-}
-
 unsigned long long tegra_chip_uid(void)
 {
 	unsigned long long lo, hi;
 
-	lo = fuse_readl(FUSE_UID_LOW);
-	hi = fuse_readl(FUSE_UID_HIGH);
+	lo = tegra_fuse_readl(FUSE_UID_LOW);
+	hi = tegra_fuse_readl(FUSE_UID_HIGH);
 	return (hi << 32ull) | lo;
 }
 
+unsigned int tegra_spare_fuse(int bit)
+{
+	BUG_ON(bit < 0 || bit > 61);
+	return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
+}
+
 int tegra_sku_id(void)
 {
 	int sku_id;
-	u32 reg = fuse_readl(FUSE_SKU_INFO);
+	u32 reg = tegra_fuse_readl(FUSE_SKU_INFO);
 	sku_id = reg & 0xFF;
 	return sku_id;
 }
 
-int tegra_cpu_process_id(void)
-{
-	int cpu_process_id;
-	u32 reg = fuse_readl(FUSE_SPARE_BIT);
-	cpu_process_id = (reg >> 6) & 3;
-	return cpu_process_id;
-}
-
-int tegra_core_process_id(void)
-{
-	int core_process_id;
-	u32 reg = fuse_readl(FUSE_SPARE_BIT);
-	core_process_id = (reg >> 12) & 3;
-	return core_process_id;
-}
-
 enum tegra_revision tegra_get_revision(void)
 {
 	void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h
index 8a9042635f2b..d38474376469 100644
--- a/arch/arm/mach-tegra/fuse.h
+++ b/arch/arm/mach-tegra/fuse.h
@@ -26,11 +26,13 @@ enum tegra_revision {
 };
 
 unsigned long long tegra_chip_uid(void);
+unsigned int tegra_spare_fuse(int bit);
 int tegra_sku_id(void);
 int tegra_cpu_process_id(void);
 int tegra_core_process_id(void);
+int tegra_soc_speedo_id(void);
 void tegra_init_fuse(void);
-void tegra_init_fuse_dma(void);
+void tegra_init_speedo_data(void);
 u32 tegra_fuse_readl(unsigned long offset);
 void tegra_fuse_writel(u32 value, unsigned long offset);
 enum tegra_revision tegra_get_revision(void);
diff --git a/arch/arm/mach-tegra/headsmp-t2.S b/arch/arm/mach-tegra/headsmp-t2.S
index 9da0ed68e63d..b71ff090918d 100644
--- a/arch/arm/mach-tegra/headsmp-t2.S
+++ b/arch/arm/mach-tegra/headsmp-t2.S
@@ -1,7 +1,7 @@
 /*
- * arch/arm/mach-tegra/headsmp.S
+ * arch/arm/mach-tegra/headsmp-t2.S
  *
- * SMP initialization routines for Tegra SoCs
+ * SMP initialization routines for Tegra2 SoCs
  *
  * Copyright (c) 2009-2010, NVIDIA Corporation.
  *
@@ -37,9 +37,7 @@
 
 #define PMC_DPD_SAMPLE	0x20
 #define PMC_DPD_ENABLE	0x24
-#define PMC_SCRATCH1	0x54
 #define PMC_SCRATCH39	0x138
-#define RST_DEVICES_U	0xc
 
 #define CLK_RESET_PLLX_BASE     0xe0
 #define CLK_RESET_PLLX_MISC     0xe4
@@ -50,28 +48,6 @@
 
 /*        .section ".cpuinit.text", "ax"*/
 
-.macro	poke_ev, val, tmp
-	mov32	\tmp, (TEGRA_EXCEPTION_VECTORS_BASE + 0x100)
-	str	\val, [\tmp]
-.endm
-
-#ifdef CONFIG_SMP
-/*
- *	tegra_secondary_startup
- *
- *	 Initial secondary processor boot vector; jumps to kernel's
- *	 secondary_startup routine
- */
-ENTRY(tegra_secondary_startup)
-	msr	cpsr_fsxc, #0xd3
-	bl	__invalidate_cpu_state
-	cpu_id	r0
-	enable_coresite r1
-	poke_ev	r0, r1
-	b	secondary_startup
-ENDPROC(tegra_secondary_startup)
-#endif
-
 /*
  *	__restart_plls
  *
@@ -108,30 +84,8 @@ __restart_plls:
 	/* FIXME: need to record actual power transition here */
 	mov	r0, #0
 	b	__cortex_a9_l2x0_restart
-ENDPROC(__restart_pllx)
-/*
- *	__enable_coresite_access
- *
- *	  Takes the coresite debug interface out of reset, enables
- *	  access to all CPUs. Called with MMU disabled.
- */
-	.align L1_CACHE_SHIFT
-__enable_coresite_access:
-	mov32	r0, (TEGRA_CLK_RESET_BASE + RST_DEVICES_U)
-	mov32	r2, (TEGRA_TMRUS_BASE)
+ENDPROC(__restart_plls)
 
-	/* assert reset for 2usec */
-	ldr	r1, [r0]
-	orr	r1, #(1<<9)
-	str	r1, [r0]
-	wait_for_us r3, r2, r4
-	add	r3, r3, #2
-	bic	r1, r1, #(1<<9)
-	wait_until r3, r2, r4
-	str	r1, [r0]
-	enable_coresite r3
-	bx	lr
-ENDPROC(__enable_coresite_access)
 /*
  *	tegra_lp2_startup
  *
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
new file mode 100644
index 000000000000..25f78071666e
--- /dev/null
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -0,0 +1,83 @@
+/*
+ * arch/arm/mach-tegra/headsmp.S
+ *
+ * SMP initialization routines for Tegra SoCs
+ *
+ * Copyright (c) 2009-2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+#include <asm/assembler.h>
+#include <asm/cache.h>
+
+#include <mach/iomap.h>
+#include <mach/io.h>
+
+#include "power-macros.S"
+
+#define RST_DEVICES_U	0xc
+
+/*        .section ".cpuinit.text", "ax"*/
+
+.macro	poke_ev, val, tmp
+	mov32	\tmp, (TEGRA_EXCEPTION_VECTORS_BASE + 0x100)
+	str	\val, [\tmp]
+.endm
+
+/*
+ *	tegra_secondary_startup
+ *
+ *	 Initial secondary processor boot vector; jumps to kernel's
+ *	 secondary_startup routine
+ */
+ENTRY(tegra_secondary_startup)
+	msr	cpsr_fsxc, #0xd3
+	bl	__invalidate_cpu_state
+	cpu_id	r0
+	enable_coresite r1
+	poke_ev	r0, r1
+	b	secondary_startup
+ENDPROC(tegra_secondary_startup)
+
+/*
+ *	__enable_coresite_access
+ *
+ *	  Called only on CPU0 to take the CoreSight debug interface out of
+ *	  reset. Called with MMU disabled.
+ */
+	.align L1_CACHE_SHIFT
+ENTRY(__enable_coresite_access)
+	mov32	r0, (TEGRA_CLK_RESET_BASE + RST_DEVICES_U)
+	mov32	r2, (TEGRA_TMRUS_BASE)
+
+	/* assert reset for 2usec */
+	ldr	r1, [r0]
+#ifndef CONFIG_TEGRA_FPGA_PLATFORM
+	orr	r1, #(1<<9)
+	str	r1, [r0]
+#endif
+	wait_for_us r3, r2, r4
+	add	r3, r3, #2
+	bic	r1, r1, #(1<<9)
+	wait_until r3, r2, r4
+	str	r1, [r0]
+	/* Enable CoreSight */
+	enable_coresite r3
+	bx	lr
+ENDPROC(__enable_coresite_access)
diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h
index f5a64cba61ae..1dc9c556d6fa 100644
--- a/arch/arm/mach-tegra/include/mach/dc.h
+++ b/arch/arm/mach-tegra/include/mach/dc.h
@@ -37,6 +37,7 @@ struct tegra_dc_mode {
 	int	v_active;
 	int	h_front_porch;
 	int	v_front_porch;
+	int	stereo_mode;
 	u32	flags;
 };
 
@@ -48,6 +49,29 @@ enum {
 	TEGRA_DC_OUT_HDMI,
 };
 
+struct tegra_dc_out_pin {
+	int     name;
+	int     pol;
+};
+
+enum {
+	TEGRA_DC_OUT_PIN_DATA_ENABLE,
+	TEGRA_DC_OUT_PIN_H_SYNC,
+	TEGRA_DC_OUT_PIN_V_SYNC,
+	TEGRA_DC_OUT_PIN_PIXEL_CLOCK,
+};
+
+enum {
+	TEGRA_DC_OUT_PIN_POL_LOW,
+	TEGRA_DC_OUT_PIN_POL_HIGH,
+};
+
+enum {
+	TEGRA_DC_DISABLE_DITHER = 1,
+	TEGRA_DC_ORDERED_DITHER,
+	TEGRA_DC_ERRDIFF_DITHER,
+};
+
 struct tegra_dc_out {
 	int			type;
 	unsigned		flags;
@@ -62,6 +86,7 @@ struct tegra_dc_out {
 	unsigned		order;
 	unsigned		align;
 	unsigned		depth;
+	unsigned		dither;
 
 	unsigned		height; /* mm */
 	unsigned		width; /* mm */
@@ -69,13 +94,21 @@ struct tegra_dc_out {
 	struct tegra_dc_mode	*modes;
 	int			n_modes;
 
+	struct tegra_dc_out_pin	*out_pins;
+	unsigned		n_out_pins;
+
 	int	(*enable)(void);
+	int	(*postpoweron)(void);
 	int	(*disable)(void);
 };
 
-#define TEGRA_DC_OUT_HOTPLUG_HIGH	(0 << 1)
-#define TEGRA_DC_OUT_HOTPLUG_LOW	(1 << 1)
-#define TEGRA_DC_OUT_HOTPLUG_MASK	(1 << 1)
+/* bits for tegra_dc_out.flags */
+#define TEGRA_DC_OUT_HOTPLUG_HIGH		(0 << 1)
+#define TEGRA_DC_OUT_HOTPLUG_LOW		(1 << 1)
+#define TEGRA_DC_OUT_HOTPLUG_MASK		(1 << 1)
+#define TEGRA_DC_OUT_NVHDCP_POLICY_ALWAYS_ON	(0 << 2)
+#define TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND	(1 << 2)
+#define TEGRA_DC_OUT_NVHDCP_POLICY_MASK		(1 << 2)
 
 #define TEGRA_DC_ALIGN_MSB		0
 #define TEGRA_DC_ALIGN_LSB		1
@@ -118,6 +151,7 @@ struct tegra_dc_win {
 #define TEGRA_WIN_FLAG_ENABLED		(1 << 0)
 #define TEGRA_WIN_FLAG_BLEND_PREMULT	(1 << 1)
 #define TEGRA_WIN_FLAG_BLEND_COVERAGE	(1 << 2)
+#define TEGRA_WIN_FLAG_TILED		(1 << 3)
 
 #define TEGRA_WIN_BLEND_FLAGS_MASK \
 	(TEGRA_WIN_FLAG_BLEND_PREMULT | TEGRA_WIN_FLAG_BLEND_COVERAGE)
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index e7fe2788e92d..e77176e7c87e 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -113,6 +113,9 @@
 #define TEGRA_APB_DMA_CH0_BASE		0x6000B000
 #define TEGRA_APB_DMA_CH0_SIZE		32
 
+#define TEGRA_AVP_CACHE_BASE		0x6000C000
+#define TEGRA_AVP_CACHE_SIZE		4
+
 #define TEGRA_AHB_GIZMO_BASE		0x6000C004
 #define TEGRA_AHB_GIZMO_SIZE		0x10C
 
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
new file mode 100644
index 000000000000..4725c9815d0b
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/kbc.h
@@ -0,0 +1,77 @@
+/*
+ * arch/arm/mach-tegra/include/mach/kbc.h
+ *
+ * Platform definitions for tegra-kbc keyboard input driver
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef ASMARM_ARCH_TEGRA_KBC_H
+#define ASMARM_ARCH_TEGRA_KBC_H
+
+#include <linux/types.h>
+
+#define KBC_MAX_ROW		16
+#define KBC_MAX_COL		8
+#define KBC_MAX_GPIO		(KBC_MAX_ROW + KBC_MAX_COL)
+#define KBC_MAX_KPRESS_EVENT	8
+#define KBC_MAX_KEY		(KBC_MAX_ROW * KBC_MAX_COL)
+
+enum {
+	kbc_pin_unused = 0,
+	kbc_pin_row,
+	kbc_pin_col,
+};
+
+struct tegra_kbc_wake_key {
+	u8 row:4;
+	u8 col:4;
+};
+
+struct tegra_kbc_pin_cfg {
+	int pin_type;
+	unsigned char num;
+};
+/**
+ * struct tegra_kbc_platform_data - Tegra kbc specific platform data for kbc
+ *                                  driver.
+ * @debounce_cnt: Debaunce count in terms of clock ticks of 32KHz
+ * @repeat_cnt: The time to start next scan after completing the current scan
+ *              in terms of clock ticks of 32KHz clock
+ * @scan_timeout_cnt: Number of clock count (32KHz) to keep scanning of keys
+ *              after any key is pressed.
+ * @plain_keycode: The key code array for keys in normal mode.
+ * @fn_keycode:  The key code array for keys with function key pressed.
+ * @is_filter_keys: Tells whether filter algorithms applied or not.
+ * @kbc_pin_type: The type of kbc pin whether unused or column or row.
+ * @is_wake_on_any_key: System whouls wakeup on any key or the key list from
+ *                      wake_cfg.
+ * @wake_key_cnt: Number of key count in wakeup list.
+ */
+struct tegra_kbc_platform_data {
+	unsigned int debounce_cnt;
+	unsigned int repeat_cnt;
+	unsigned int scan_timeout_cnt;
+	int *plain_keycode;
+	int *fn_keycode;
+	bool is_filter_keys;
+	struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
+	bool is_wake_on_any_key;
+	struct tegra_kbc_wake_key *wake_cfg;
+	int wake_key_cnt;
+};
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/kfuse.h b/arch/arm/mach-tegra/include/mach/kfuse.h
new file mode 100644
index 000000000000..cfe85cc86ff2
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/kfuse.h
@@ -0,0 +1,20 @@
+/*
+ * arch/arm/mach-tegra/kfuse.h
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* there are 144 32-bit values in total */
+#define KFUSE_DATA_SZ (144 * 4)
+
+int tegra_kfuse_read(void *dest, size_t len);
diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h
index 4ebc3e055ed1..7c225b1d4d63 100644
--- a/arch/arm/mach-tegra/include/mach/memory.h
+++ b/arch/arm/mach-tegra/include/mach/memory.h
@@ -27,5 +27,7 @@
 #define NET_IP_ALIGN	0
 #define NET_SKB_PAD	L1_CACHE_BYTES
 
+#define CONSISTENT_DMA_SIZE	(14 * SZ_1M)
+
 #endif
 
diff --git a/arch/arm/mach-tegra/include/mach/nvhost.h b/arch/arm/mach-tegra/include/mach/nvhost.h
index c72666ae0d37..fc0336a42b50 100644
--- a/arch/arm/mach-tegra/include/mach/nvhost.h
+++ b/arch/arm/mach-tegra/include/mach/nvhost.h
@@ -114,8 +114,10 @@ struct nvhost_set_nvmap_fd_args {
 	_IOR(NVHOST_IOCTL_MAGIC, 4, struct nvhost_get_param_args)
 #define NVHOST_IOCTL_CHANNEL_SET_NVMAP_FD	\
 	_IOW(NVHOST_IOCTL_MAGIC, 5, struct nvhost_set_nvmap_fd_args)
+#define NVHOST_IOCTL_CHANNEL_NULL_KICKOFF	\
+	_IOR(NVHOST_IOCTL_MAGIC, 6, struct nvhost_get_param_args)
 #define NVHOST_IOCTL_CHANNEL_LAST		\
-	_IOC_NR(NVHOST_IOCTL_CHANNEL_SET_NVMAP_FD)
+	_IOC_NR(NVHOST_IOCTL_CHANNEL_NULL_KICKOFF)
 #define NVHOST_IOCTL_CHANNEL_MAX_ARG_SIZE sizeof(struct nvhost_get_param_args)
 
 struct nvhost_ctrl_syncpt_read_args {
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h
index 34e2686fca45..ca4fc14038d2 100644
--- a/arch/arm/mach-tegra/include/mach/sdhci.h
+++ b/arch/arm/mach-tegra/include/mach/sdhci.h
@@ -18,6 +18,7 @@
 #define __ASM_ARM_ARCH_TEGRA_SDHCI_H
 
 #include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
 
 struct tegra_sdhci_platform_data {
 	const char *clk_id;
@@ -28,6 +29,16 @@ struct tegra_sdhci_platform_data {
 
 	void (*board_probe)(int id, struct mmc_host *);
 	void (*board_remove)(int id, struct mmc_host *);
+
+	/* embedded sdio data */
+	struct sdio_cis cis;
+	struct sdio_cccr cccr;
+	struct sdio_embedded_func *funcs;
+	int num_funcs;
+
+	/* card detect callback registration function */
+	int (*register_status_notify)(void (*callback)(int card_present,
+				void *dev_id), void *dev_id);
 };
 
 #endif
diff --git a/arch/arm/mach-tegra/include/mach/spi.h b/arch/arm/mach-tegra/include/mach/spi.h
new file mode 100644
index 000000000000..171e4007b4bc
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/spi.h
@@ -0,0 +1,42 @@
+/*
+ * arch/arm/mach-tegra/include/mach/spi.h
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_SPI_H
+#define __MACH_TEGRA_SPI_H
+
+#include <linux/types.h>
+#include <linux/spi/spi.h>
+
+typedef int	(*callback)(void *client_data);
+
+/**
+ * register_spi_slave_callback - registers notification callback provided by
+ * the client.
+ * This callback indicate that the controller is all set to receive/transfer
+ * data.
+ * @spi: struct spi_device - refer to linux/spi/spi.h
+ * @func: Callback function
+ * @client_data: Data to be passed in callback
+ * Context: can not sleep
+ */
+int spi_tegra_register_callback(struct spi_device *spi, callback func,
+	void *client_data);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h
index 70c95ac93355..d7e807bb564f 100644
--- a/arch/arm/mach-tegra/include/mach/system.h
+++ b/arch/arm/mach-tegra/include/mach/system.h
@@ -32,11 +32,11 @@ static inline void arch_idle(void)
 
 static inline void tegra_assert_system_reset(void)
 {
-	void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
+	void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0x00);
 	u32 reg;
 
 	reg = readl(reset);
-	reg |= 0x04;
+	reg |= 0x10;
 	writel(reg, reset);
 }
 
diff --git a/arch/arm/mach-tegra/include/mach/tegra2_i2s.h b/arch/arm/mach-tegra/include/mach/tegra2_i2s.h
new file mode 100644
index 000000000000..46846c1ef834
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra2_i2s.h
@@ -0,0 +1,307 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra2_i2s.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Iliyan Malchev <malchev@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __ARCH_ARM_MACH_TEGRA_I2S_H
+#define __ARCH_ARM_MACH_TEGRA_I2S_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+
+/* Offsets from TEGRA_I2S1_BASE and TEGRA_I2S2_BASE */
+
+#define I2S_I2S_CTRL_0			0
+#define I2S_I2S_STATUS_0		4
+#define I2S_I2S_TIMING_0		8
+#define I2S_I2S_FIFO_SCR_0		0x0c
+#define I2S_I2S_PCM_CTRL_0		0x10
+#define I2S_I2S_NW_CTRL_0		0x14
+#define I2S_I2S_TDM_CTRL_0		0x20
+#define I2S_I2S_TDM_TX_RX_CTRL_0	0x24
+#define I2S_I2S_FIFO1_0			0x40
+#define I2S_I2S_FIFO2_0			0x80
+
+/*
+ * I2S_I2S_CTRL_0
+ */
+
+#define I2S_I2S_CTRL_FIFO2_TX_ENABLE		(1<<30)
+#define I2S_I2S_CTRL_FIFO1_ENABLE		(1<<29)
+#define I2S_I2S_CTRL_FIFO2_ENABLE		(1<<28)
+#define I2S_I2S_CTRL_FIFO1_RX_ENABLE		(1<<27)
+#define I2S_I2S_CTRL_FIFO_LPBK_ENABLE		(1<<26)
+#define I2S_I2S_CTRL_MASTER_ENABLE		(1<<25)
+#define I2S_I2S_CTRL_L_R_CTRL			(1<<24)  /* 0 = Left low/Right high */
+
+#define I2S_BIT_FORMAT_I2S 0
+#define I2S_BIT_FORMAT_RJM 1
+#define I2S_BIT_FORMAT_LJM 2
+#define I2S_BIT_FORMAT_DSP 3
+#define I2S_BIT_FORMAT_SHIFT 10
+
+#define I2S_I2S_CTRL_BIT_FORMAT_MASK		(3<<10)
+#define I2S_I2S_CTRL_BIT_FORMAT_I2S		(I2S_BIT_FORMAT_I2S<<10)
+#define I2S_I2S_CTRL_BIT_FORMAT_RJM		(I2S_BIT_FORMAT_RJM<<10)
+#define I2S_I2S_CTRL_BIT_FORMAT_LJM		(I2S_BIT_FORMAT_LJM<<10)
+#define I2S_I2S_CTRL_BIT_FORMAT_DSP		(I2S_BIT_FORMAT_DSP<<10)
+
+#define I2S_BIT_SIZE_16 0
+#define I2S_BIT_SIZE_20 1
+#define I2S_BIT_SIZE_24 2
+#define I2S_BIT_SIZE_32 3
+#define I2S_BIT_SIZE_SHIFT 8
+
+#define I2S_I2S_CTRL_BIT_SIZE_MASK		(3 << I2S_BIT_SIZE_SHIFT)
+#define I2S_I2S_CTRL_BIT_SIZE_16		(I2S_BIT_SIZE_16 << I2S_BIT_SIZE_SHIFT)
+#define I2S_I2S_CTRL_BIT_SIZE_20		(I2S_BIT_SIZE_20 << I2S_BIT_SIZE_SHIFT)
+#define I2S_I2S_CTRL_BIT_SIZE_24		(I2S_BIT_SIZE_24 << I2S_BIT_SIZE_SHIFT)
+#define I2S_I2S_CTRL_BIT_SIZE_32		(I2S_BIT_SIZE_32 << I2S_BIT_SIZE_SHIFT)
+
+#define I2S_FIFO_16_LSB 0
+#define I2S_FIFO_20_LSB 1
+#define I2S_FIFO_24_LSB 2
+#define I2S_FIFO_32     3
+#define I2S_FIFO_PACKED 7
+#define I2S_FIFO_SHIFT  4
+
+#define I2S_I2S_CTRL_FIFO_FORMAT_MASK		(7<<4)
+#define I2S_I2S_CTRL_FIFO_FORMAT_16_LSB		(I2S_FIFO_16_LSB << I2S_FIFO_SHIFT)
+#define I2S_I2S_CTRL_FIFO_FORMAT_20_LSB		(I2S_FIFO_20_LSB << I2S_FIFO_SHIFT)
+#define I2S_I2S_CTRL_FIFO_FORMAT_24_LSB		(I2S_FIFO_24_LSB << I2S_FIFO_SHIFT)
+#define I2S_I2S_CTRL_FIFO_FORMAT_32		(I2S_FIFO_32 << I2S_FIFO_SHIFT)
+#define I2S_I2S_CTRL_FIFO_FORMAT_PACKED		(I2S_FIFO_PACKED << I2S_FIFO_SHIFT)
+
+// Left/Right Control Polarity. 0= Left channel when LRCK is low, Right channel  when LRCK is high, 1= vice versa
+#define I2S_LRCK_LEFT_LOW   0
+#define I2S_LRCK_RIGHT_LOW  1
+#define I2S_LRCK_SHIFT      24
+
+
+#define I2S_I2S_CTRL_LRCK_MASK              (1<<I2S_LRCK_SHIFT)
+#define I2S_I2S_CTRL_LRCK_L_LOW             (I2S_LRCK_LEFT_LOW << I2S_LRCK_SHIFT)
+#define I2S_I2S_CTRL_LRCK_R_LOW             (I2S_LRCK_RIGHT_LOW << I2S_LRCK_SHIFT)
+
+
+#define I2S_I2S_IE_FIFO1_ERR			(1<<3)
+#define I2S_I2S_IE_FIFO2_ERR			(1<<2)
+#define I2S_I2S_QE_FIFO1			(1<<1)
+#define I2S_I2S_QE_FIFO2			(1<<0)
+
+/*
+ * I2S_I2S_STATUS_0
+ */
+
+#define I2S_I2S_STATUS_FIFO1_RDY		(1<<31)
+#define I2S_I2S_STATUS_FIFO2_RDY		(1<<30)
+#define I2S_I2S_STATUS_FIFO1_BSY		(1<<29)
+#define I2S_I2S_STATUS_FIFO2_BSY		(1<<28)
+#define I2S_I2S_STATUS_FIFO1_ERR		(1<<3)
+#define I2S_I2S_STATUS_FIFO2_ERR		(1<<2)
+#define I2S_I2S_STATUS_QS_FIFO1			(1<<1)
+#define I2S_I2S_STATUS_QS_FIFO2			(1<<0)
+
+/*
+ * I2S_I2S_TIMING_0
+ */
+
+#define I2S_I2S_TIMING_NON_SYM_ENABLE		(1<<12)
+#define I2S_I2S_TIMING_CHANNEL_BIT_COUNT_MASK	0x7ff
+#define I2S_I2S_TIMING_CHANNEL_BIT_COUNT	(1<<0)
+
+/*
+ * I2S_I2S_FIFO_SCR_0
+ */
+
+#define I2S_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK  0x3f
+#define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT 24
+#define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT 16
+
+#define I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_MASK	(0x3f<<24)
+#define I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_MASK	(0x3f<<16)
+
+#define I2S_I2S_FIFO_SCR_FIFO2_CLR			(1<<12)
+#define I2S_I2S_FIFO_SCR_FIFO1_CLR			(1<<8)
+
+#define I2S_FIFO_ATN_LVL_ONE_SLOT	0
+#define I2S_FIFO_ATN_LVL_FOUR_SLOTS	1
+#define I2S_FIFO_ATN_LVL_EIGHT_SLOTS	2
+#define I2S_FIFO_ATN_LVL_TWELVE_SLOTS	3
+#define I2S_FIFO2_ATN_LVL_SHIFT		4
+#define I2S_FIFO1_ATN_LVL_SHIFT		0
+
+#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK		(3 << I2S_FIFO2_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_ONE_SLOT		(I2S_FIFO_ATN_LVL_ONE_SLOT     << I2S_FIFO2_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_FOUR_SLOTS	(I2S_FIFO_ATN_LVL_FOUR_SLOTS   << I2S_FIFO2_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_EIGHT_SLOTS	(I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << I2S_FIFO2_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_TWELVE_SLOTS	(I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO2_ATN_LVL_SHIFT)
+
+#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK		(3 << I2S_FIFO1_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_ONE_SLOT		(I2S_FIFO_ATN_LVL_ONE_SLOT     << I2S_FIFO1_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_FOUR_SLOTS	(I2S_FIFO_ATN_LVL_FOUR_SLOTS   << I2S_FIFO1_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_EIGHT_SLOTS	(I2S_FIFO_ATN_LVL_EIGHT_SLOTS  << I2S_FIFO1_ATN_LVL_SHIFT)
+#define I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_TWELVE_SLOTS	(I2S_FIFO_ATN_LVL_TWELVE_SLOTS << I2S_FIFO1_ATN_LVL_SHIFT)
+
+/*
+ * I2S_I2S_PCM_CTRL_0
+ */
+#define I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ		0
+#define I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ 		1
+#define I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ		2
+#define I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ			3
+#define I2S_PCM_TRM_EDGE_CTRL_SHIFT			9
+
+#define I2S_I2S_PCM_TRM_EDGE_CTRL_MASK			\
+		(3 << I2S_PCM_TRM_EDGE_CTRL_SHIFT)
+#define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ		\
+		(I2S_PCM_TRM_EDGE_POS_EDGE_NO_HIGHZ	\
+		<< I2S_PCM_TRM_EDGE_CTRL_SHIFT)
+#define I2S_I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ		\
+		(I2S_PCM_TRM_EDGE_POS_EDGE_HIGHZ	\
+		<< I2S_PCM_TRM_EDGE_CTRL_SHIFT)
+#define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ		\
+		(I2S_PCM_TRM_EDGE_NEG_EDGE_NO_HIGHZ	\
+		<< I2S_PCM_TRM_EDGE_CTRL_SHIFT)
+#define I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ		\
+		(I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ	\
+		<< I2S_PCM_TRM_EDGE_CTRL_SHIFT)
+
+#define I2S_PCM_TRM_MASK_BITS_ZERO			0
+#define I2S_PCM_TRM_MASK_BITS_ONE			1
+#define I2S_PCM_TRM_MASK_BITS_TWO			2
+#define I2S_PCM_TRM_MASK_BITS_THREE			3
+#define I2S_PCM_TRM_MASK_BITS_FOUR			4
+#define I2S_PCM_TRM_MASK_BITS_FIVE			5
+#define I2S_PCM_TRM_MASK_BITS_SIX			6
+#define I2S_PCM_TRM_MASK_BITS_SEVEN			7
+#define I2S_PCM_TRM_MASK_BITS_SHIFT			6
+
+#define I2S_I2S_PCM_TRM_MASK_BITS_MASK			\
+		(7 << I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_ZERO			\
+		(I2S_PCM_TRM_MASK_BITS_ZERO		\
+		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_ONE			\
+		(I2S_PCM_TRM_MASK_BITS_ONE		\
+		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_TWO			\
+		(I2S_PCM_TRM_MASK_BITS_TWO		\
+		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_THREE			\
+		(I2S_PCM_TRM_MASK_BITS_THREE		\
+		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_FOUR			\
+		(I2S_PCM_TRM_MASK_BITS_FOUR		\
+		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_FIVE			\
+		(I2S_PCM_TRM_MASK_BITS_FIVE		\
+		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_SIX			\
+		(I2S_PCM_TRM_MASK_BITS_SIX		\
+		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_TRM_MASK_BITS_SEVEN			\
+		(I2S_PCM_TRM_MASK_BITS_SEVEN		\
+		<< I2S_PCM_TRM_MASK_BITS_SHIFT)
+
+#define I2S_I2S_PCM_CTRL_FSYNC_PCM_CTRL			(1<<5)
+#define I2S_I2S_PCM_CTRL_TRM_MODE			(1<<4)
+
+#define I2S_PCM_RCV_MASK_BITS_ZERO			0
+#define I2S_PCM_RCV_MASK_BITS_ONE			1
+#define I2S_PCM_RCV_MASK_BITS_TWO			2
+#define I2S_PCM_RCV_MASK_BITS_THREE			3
+#define I2S_PCM_RCV_MASK_BITS_FOUR			4
+#define I2S_PCM_RCV_MASK_BITS_FIVE			5
+#define I2S_PCM_RCV_MASK_BITS_SIX			6
+#define I2S_PCM_RCV_MASK_BITS_SEVEN			7
+#define I2S_PCM_RCV_MASK_BITS_SHIFT			1
+
+#define I2S_I2S_PCM_RCV_MASK_BITS_MASK			\
+		(7 << I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_ZERO			\
+		(I2S_PCM_RCV_MASK_BITS_ZERO		\
+		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_ONE			\
+		(I2S_PCM_RCV_MASK_BITS_ONE		\
+		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_TWO			\
+		(I2S_PCM_RCV_MASK_BITS_TWO		\
+		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_THREE			\
+		(I2S_PCM_RCV_MASK_BITS_THREE		\
+		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_FOUR			\
+		(I2S_PCM_RCV_MASK_BITS_FOUR		\
+		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_FIVE			\
+		(I2S_PCM_RCV_MASK_BITS_FIVE		\
+		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_SIX			\
+		(I2S_PCM_RCV_MASK_BITS_SIX		\
+		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
+#define I2S_I2S_PCM_RCV_MASK_BITS_SEVEN			\
+		(I2S_PCM_RCV_MASK_BITS_SEVEN		\
+		<< I2S_PCM_RCV_MASK_BITS_SHIFT)
+
+#define I2S_I2S_PCM_CTRL_RCV_MODE			(1<<0)
+
+struct i2s_runtime_data {
+	int i2s_ctrl_0;
+	int i2s_status_0;
+	int i2s_timing_0;
+	int i2s__fifo_scr_0;
+	int i2s_fifo1_0;
+	int i2s_fifo2_0;
+};
+
+/*
+ * API
+ */
+
+void i2s_dump_registers(int ifc);
+void i2s_get_all_regs(int ifc, struct i2s_runtime_data* ird);
+void i2s_set_all_regs(int ifc, struct i2s_runtime_data* ird);
+int i2s_set_channel_bit_count(int ifc, int sampling, int bitclk);
+void i2s_set_fifo_mode(int ifc, int fifo, int tx);
+void i2s_set_loopback(int ifc, int on);
+int i2s_fifo_set_attention_level(int ifc, int fifo, unsigned level);
+void i2s_fifo_enable(int ifc, int fifo, int on);
+void i2s_fifo_clear(int ifc, int fifo);
+void i2s_set_master(int ifc, int master);
+int i2s_set_bit_format(int ifc, unsigned format);
+int i2s_set_bit_size(int ifc, unsigned bit_size);
+int i2s_set_fifo_format(int ifc, unsigned fmt);
+void i2s_set_left_right_control_polarity(int ifc, int high_low);
+int i2s_set_pcm_edge_mode(int ifc, unsigned edge_mode);
+int i2s_set_pcm_mask_bits(int ifc, unsigned mask_bits, int tx);
+void i2s_set_pcm_fsync_width(int ifc, int fsync_long);
+void i2s_enable_pcm_mode(int ifc, int enable);
+void i2s_set_fifo_irq_on_err(int ifc, int fifo, int on);
+void i2s_set_fifo_irq_on_qe(int ifc, int fifo, int on);
+void i2s_enable_fifos(int ifc, int on);
+void i2s_fifo_write(int ifc, int fifo, u32 data);
+u32 i2s_fifo_read(int ifc, int fifo);
+u32 i2s_get_status(int ifc);
+u32 i2s_get_control(int ifc);
+void i2s_ack_status(int ifc);
+u32 i2s_get_fifo_scr(int ifc);
+u32 i2s_get_fifo_full_empty_count(int ifc, int fifo);
+phys_addr_t i2s_get_fifo_phy_base(int ifc, int fifo);
+struct clk *i2s_get_clock_by_name(const char *name);
+
+#endif /* __ARCH_ARM_MACH_TEGRA_I2S_H */
diff --git a/arch/arm/mach-tegra/include/mach/tegra_das.h b/arch/arm/mach-tegra/include/mach/tegra_das.h
new file mode 100644
index 000000000000..e3e29b044f8d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_das.h
@@ -0,0 +1,231 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_das.h
+ *
+ * Declarations of Tegra Digital Audio Switch (das)
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __MACH_TEGRA_DAS_H
+#define __MACH_TEGRA_DAS_H
+
+#include <linux/kernel.h>
+
+/*
+                            -----------------
+                            |               |
+                            |               |<----> DAP1
+                DAC1 <----> |    Digital    |
+    ---------               |               |<----> DAP2
+    |       |               |     Audio     |
+    | Tegra |   DAC2 <----> |               |<----> DAP3
+    |  SoC  |               |    Switch     |
+    |       |               |               |<----> DAP4
+    ---------               |     (DAS)     |
+                DAC3 <----> |               |<----> DAP5
+                            |               |
+                            |               |
+                            -----------------
+
+*/
+
+#define APB_MISC_DAS_DAP_CTRL_SEL_0			(0xc00)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1			(0xc04)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2			(0xc08)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3			(0xc0c)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4			(0xc10)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0		(0xc40)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1		(0xc44)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2		(0xc48)
+
+#define DAP_MS_SEL_SHIFT		(31)
+#define DAP_MS_SEL_DEFAULT_MASK		(0x1)
+#define DAP_SDATA1_TX_RX_SHIFT		(30)
+#define DAP_SDATA1_TX_RX_DEFAULT_MASK	(0x1)
+#define DAP_SDATA2_RX_TX_SHIFT		(29)
+#define DAP_SDATA2_RX_TX_DEFAULT_MASK	(0x1)
+#define DAP_CTRL_SEL_SHIFT		(0)
+#define DAP_CTRL_SEL_DEFAULT_MASK	(0x1f)
+
+#define DAC_SDATA2_SEL_SHIFT		(28)
+#define DAC_SDATA2_SEL_DEFAULT_MASK	(0xf)
+#define DAC_SDATA1_SEL_SHIFT		(24)
+#define DAC_SDATA1_SEL_DEFAULT_MASK	(0xf)
+#define DAC_CLK_SEL_SHIFT		(0)
+#define DAC_CLK_SEL_DEFAULT_MASK	(0xf)
+
+
+#define DAP_CTRL_SEL_DAC1		(0)
+#define DAP_CTRL_SEL_DAC2		(1)
+#define DAP_CTRL_SEL_DAC3		(2)
+#define DAP_CTRL_SEL_DAP1		(16)
+#define DAP_CTRL_SEL_DAP2		(17)
+#define DAP_CTRL_SEL_DAP3		(18)
+#define DAP_CTRL_SEL_DAP4		(19)
+#define DAP_CTRL_SEL_DAP5		(20)
+
+#define MAX_CONNECTIONLINES 8
+
+typedef enum tegra_das_port_t {
+	tegra_das_port_none = 0,
+	tegra_das_port_dap1,
+	tegra_das_port_dap2,
+	tegra_das_port_dap3,
+	tegra_das_port_dap4,
+	tegra_das_port_dap5,
+	tegra_das_port_i2s1,
+	tegra_das_port_i2s2,
+	tegra_das_port_ac97
+} tegra_das_port;
+
+#define MAX_DAP_PORTS	(tegra_das_port_dap5 + 1)
+
+/* defines possible hardware connected to DAP */
+enum tegra_audio_codec_type {
+	tegra_audio_codec_type_none = 0,
+	tegra_audio_codec_type_hifi,
+	tegra_audio_codec_type_voice,
+	tegra_audio_codec_type_bluetooth,
+	tegra_audio_codec_type_baseband,
+	tegra_audio_codec_type_fm_radio,
+};
+
+/* index for possible connection based on the use case */
+enum tegra_das_port_con_id {
+	tegra_das_port_con_id_none = 0,
+	tegra_das_port_con_id_hifi,
+	tegra_das_port_con_id_voice,
+	tegra_das_port_con_id_analog_radio,
+	tegra_das_port_con_id_digital_radio,
+	tegra_das_port_con_id_bt_codec,
+	tegra_das_port_con_id_voicecall_no_bt,
+	tegra_das_port_con_id_voicecall_no_bt_record,
+	tegra_das_port_con_id_voicecall_with_bt,
+	tegra_das_port_con_id_voicecall_with_bt_record,
+
+	tegra_das_port_con_id_max
+};
+
+/* possible list of input/output devices */
+#define audio_dev_none			(0x0)
+#define audio_dev_all			(0xffffffff)
+
+/* Inputs */
+#define audio_dev_builtin_mic		(0x1)
+#define audio_dev_mic			(0x2)
+#define audio_dev_lineIn		(0x4)
+
+/* Outputs */
+#define audio_dev_speaker		(0x100)
+#define audio_dev_earpiece		(0x200)
+#define audio_dev_lineout		(0x400)
+#define audio_dev_headphone		(0x800)
+#define audio_dev_bt_a2dp		(0x1000)
+
+/* Both */
+#define audio_dev_aux			(0x10000)
+#define audio_dev_headset		(0x20000)
+#define audio_dev_radio			(0x40000)
+#define audio_dev_bt_sco		(0x80000)
+
+/* data format supported */
+enum dac_dap_data_format {
+	dac_dap_data_format_i2s = 0x1,
+	dac_dap_data_format_rjm,
+	dac_dap_data_format_ljm,
+	dac_dap_data_format_dsp,
+	dac_dap_data_format_pcm,
+	dac_dap_data_format_nw,
+	dac_dap_data_format_tdm,
+};
+
+struct audio_dev_property {
+	unsigned int num_channels;
+	unsigned int bits_per_sample;
+	unsigned int rate;
+	enum dac_dap_data_format  dac_dap_data_comm_format;
+};
+
+/*
+ * structure which contains dap endpoint
+ * dac_port contains dac port for particular dap and
+ * codec_type contains possible codec which can be connected to dap port
+ */
+struct tegra_dap_property {
+	tegra_das_port dac_port;
+	enum  tegra_audio_codec_type codec_type;
+	struct audio_dev_property device_property;
+};
+
+struct tegra_das_con_line {
+	tegra_das_port src;
+	tegra_das_port dest;
+	bool src_master;
+};
+
+struct tegra_das_con {
+	enum tegra_das_port_con_id con_id;
+	unsigned int num_entries;
+	struct tegra_das_con_line con_line[MAX_CONNECTIONLINES];
+};
+
+struct tegra_das_platform_data {
+	void *driver_data;
+	const char *dap_clk;
+	const struct tegra_dap_property tegra_dap_port_info_table[MAX_DAP_PORTS];
+	const struct tegra_das_con tegra_das_con_table[MAX_DAP_PORTS];
+};
+
+struct tegra_das_mux_select {
+	tegra_das_port port_type;
+	u32 reg_offset;
+	u32 mux_mask;
+	u32 mux_shift;
+	u32 sdata1_mask;
+	u32 sdata1_shift;
+	u32 sdata2_mask;
+	u32 sdata2_shift;
+	u32 ms_mode_mask;
+	u32 ms_mode_shift;
+	u32 mux_value;
+};
+
+
+int tegra_das_open(void);
+
+int tegra_das_close(void);
+
+/*
+ * Function to make connections between dac and dap.
+ * con_id specifies the enum depending on the required port connections
+ * enable, if true do connections else disconnect
+ */
+int tegra_das_set_connection(enum tegra_das_port_con_id new_con_id);
+
+/*
+ * Function to get current port connection for das
+ */
+int tegra_das_get_connection(void);
+
+/*
+ * Function to set power state on das's dap port
+ * if is_normal is true then power mode is normal else tristated
+ */
+int tegra_das_power_mode(bool is_normal);
+
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/usb_phy.h b/arch/arm/mach-tegra/include/mach/usb_phy.h
index cc42e7b044b4..8cb7eb457ff3 100644
--- a/arch/arm/mach-tegra/include/mach/usb_phy.h
+++ b/arch/arm/mach-tegra/include/mach/usb_phy.h
@@ -32,9 +32,25 @@ struct tegra_utmip_config {
 	u8 xcvr_lsrslew;
 };
 
+enum tegra_ulpi_inf_type {
+        TEGRA_USB_LINK_ULPI = 0,
+        TEGRA_USB_NULL_ULPI,
+};
+
+struct tegra_ulpi_trimmer {
+	u8 shadow_clk_delay;	/* 0 ~ 31 */
+	u8 clock_out_delay;	/* 0 ~ 31 */
+	u8 data_trimmer;	/* 0 ~ 7 */
+	u8 stpdirnxt_trimmer;	/* 0 ~ 7 */
+};
+
 struct tegra_ulpi_config {
+	enum tegra_ulpi_inf_type inf_type;
 	int reset_gpio;
 	const char *clk;
+	const struct tegra_ulpi_trimmer *trimmer;
+	int (*preinit)(void);
+	int (*postinit)(void);
 };
 
 enum tegra_usb_phy_port_speed {
diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
index fd6aa65b2dc6..db488e890b9e 100644
--- a/arch/arm/mach-tegra/include/mach/vmalloc.h
+++ b/arch/arm/mach-tegra/include/mach/vmalloc.h
@@ -23,6 +23,6 @@
 
 #include <asm/sizes.h>
 
-#define VMALLOC_END        0xFE000000UL
+#define VMALLOC_END        0xF8000000UL
 
 #endif
diff --git a/arch/arm/mach-tegra/kfuse.c b/arch/arm/mach-tegra/kfuse.c
new file mode 100644
index 000000000000..b2439f5a4ae2
--- /dev/null
+++ b/arch/arm/mach-tegra/kfuse.c
@@ -0,0 +1,83 @@
+/*
+ * arch/arm/mach-tegra/kfuse.c
+ *
+ * Copyright (C) 2010-2011 NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* The kfuse block stores downstream and upstream HDCP keys for use by HDMI
+ * module.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/string.h>
+
+#include <mach/iomap.h>
+#include <mach/kfuse.h>
+
+#include "apbio.h"
+
+/* register definition */
+#define KFUSE_STATE					0x80
+#define  KFUSE_STATE_DONE		(1u << 16)
+#define  KFUSE_STATE_CRCPASS		(1u << 17)
+#define KFUSE_KEYADDR					0x88
+#define  KFUSE_KEYADDR_AUTOINC		(1u << 16)
+#define KFUSE_KEYS					0x8c
+
+static inline u32 tegra_kfuse_readl(unsigned long offset)
+{
+	return tegra_apb_readl(TEGRA_KFUSE_BASE + offset);
+}
+
+static inline void tegra_kfuse_writel(u32 value, unsigned long offset)
+{
+	tegra_apb_writel(value, TEGRA_KFUSE_BASE + offset);
+}
+
+static void wait_for_done(void)
+{
+	u32 reg;
+
+	do {
+		reg = tegra_kfuse_readl(KFUSE_STATE);
+	} while ((reg & KFUSE_STATE_DONE) == 0);
+}
+
+/* read up to KFUSE_DATA_SZ bytes into dest.
+ * always starts at the first kfuse.
+ */
+int tegra_kfuse_read(void *dest, size_t len)
+{
+	u32 v;
+	unsigned cnt;
+
+	if (len > KFUSE_DATA_SZ)
+		return -EINVAL;
+
+	tegra_kfuse_writel(KFUSE_KEYADDR_AUTOINC, KFUSE_KEYADDR);
+	wait_for_done();
+
+	if ((tegra_kfuse_readl(KFUSE_STATE) & KFUSE_STATE_CRCPASS) == 0) {
+		pr_err("kfuse: crc failed\n");
+		return -EIO;
+	}
+
+	for (cnt = 0; cnt < len; cnt += 4) {
+		v = tegra_kfuse_readl(KFUSE_KEYS);
+		memcpy(dest + cnt, &v, sizeof v);
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-tegra/nv/Kconfig b/arch/arm/mach-tegra/nv/Kconfig
new file mode 100644
index 000000000000..5601cbae2139
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/Kconfig
@@ -0,0 +1,16 @@
+comment "NVIDIA NVRM/NVOS options"
+
+
+config TEGRA_NVRM
+	bool "Enable NVRM stub driver"
+	default n
+	help
+		Enable NVRM stub driver
+
+
+config TEGRA_NVOS
+	bool "Enable NVOS driver"
+	default n
+	help
+		Enable NVOS driver
+
diff --git a/arch/arm/mach-tegra/nv/Makefile b/arch/arm/mach-tegra/nv/Makefile
new file mode 100644
index 000000000000..7fb51c48192f
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/Makefile
@@ -0,0 +1,19 @@
+
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+ccflags-y += -Iarch/arm/mach-tegra/nv/include
+
+
+obj-$(CONFIG_TEGRA_NVRM)	+= nvrm_user.o
+obj-$(CONFIG_TEGRA_NVRM)	+= nvrpc_user.o
+obj-$(CONFIG_TEGRA_NVRM)	+= nvrm/
+obj-$(CONFIG_TEGRA_NVRM)	+= nvreftrack/
+
+obj-$(CONFIG_TEGRA_NVOS)	+= nvos_user.o
+obj-$(CONFIG_TEGRA_NVOS)	+= nvos/
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arahb_arbc.h b/arch/arm/mach-tegra/nv/include/ap15/arahb_arbc.h
new file mode 100644
index 000000000000..42229b51247b
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arahb_arbc.h
@@ -0,0 +1,2417 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAHB_ARBC_H_INC_
+#define ___ARAHB_ARBC_H_INC_
+
+// Register AHB_ARBITRATION_DISABLE_0  
+#define AHB_ARBITRATION_DISABLE_0                       _MK_ADDR_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_WORD_COUNT                    0x1
+#define AHB_ARBITRATION_DISABLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_RESET_MASK                    _MK_MASK_CONST(0x800937f7)
+#define AHB_ARBITRATION_DISABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_READ_MASK                     _MK_MASK_CONST(0x800937f7)
+#define AHB_ARBITRATION_DISABLE_0_WRITE_MASK                    _MK_MASK_CONST(0x800937f7)
+//  1 = disable bus parking.
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SHIFT                    _MK_SHIFT_CONST(31)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_RANGE                    31:31
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable SDIO2 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_FIELD                   (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDIO2_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_RANGE                   19:19
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_WOFFSET                 0x0
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_ENABLE                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO2_DISABLE                 _MK_ENUM_CONST(1)
+
+//  1 = disable BSEA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SHIFT                    _MK_SHIFT_CONST(16)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_BSEA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_RANGE                    16:16
+#define AHB_ARBITRATION_DISABLE_0_BSEA_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable BSEV from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_BSEV_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_RANGE                    13:13
+#define AHB_ARBITRATION_DISABLE_0_BSEV_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable HSMMC1 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_SHIFT                  _MK_SHIFT_CONST(12)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_HSMMC1_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_RANGE                  12:12
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_HSMMC1_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable NAND from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_NAND_SHIFT                    _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_DISABLE_0_NAND_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_NAND_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_NAND_RANGE                    10:10
+#define AHB_ARBITRATION_DISABLE_0_NAND_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_NAND_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_NAND_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable SDIO1 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_SHIFT                   _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_FIELD                   (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDIO1_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_RANGE                   9:9
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_WOFFSET                 0x0
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_ENABLE                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDIO1_DISABLE                 _MK_ENUM_CONST(1)
+
+//  1 = disable XIO from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_XIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_DISABLE_0_XIO_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_XIO_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_XIO_RANGE                     8:8
+#define AHB_ARBITRATION_DISABLE_0_XIO_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_XIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_XIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable APB-DMA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SHIFT                  _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_APBDMA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_RANGE                  7:7
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable USB from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_USB_SHIFT                     _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_DISABLE_0_USB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_USB_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_USB_RANGE                     6:6
+#define AHB_ARBITRATION_DISABLE_0_USB_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_USB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_USB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_USB_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable AHB-DMA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SHIFT                  _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_AHBDMA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_RANGE                  5:5
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable EIDE from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SHIFT                    _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_EIDE_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_RANGE                    4:4
+#define AHB_ARBITRATION_DISABLE_0_EIDE_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable VCP from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_VCP_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_DISABLE_0_VCP_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_VCP_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_VCP_RANGE                     2:2
+#define AHB_ARBITRATION_DISABLE_0_VCP_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_VCP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_VCP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable COP from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_COP_SHIFT                     _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_DISABLE_0_COP_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_COP_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_COP_RANGE                     1:1
+#define AHB_ARBITRATION_DISABLE_0_COP_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_COP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_COP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_COP_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable CPU from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_CPU_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_CPU_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_CPU_RANGE                     0:0
+#define AHB_ARBITRATION_DISABLE_0_CPU_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_CPU_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_CPU_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_DISABLE                   _MK_ENUM_CONST(1)
+
+
+// Register AHB_ARBITRATION_PRIORITY_CTRL_0  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//
+//  The AHB arbiter implements a 2-level priority scheme.  In the 1st level, arbitration is determined between
+//  the high and low priority group according to the priority weight; the higher the weight, the higher the
+//  winning rate of the high priority group.  In the 2nd level, within each of the high/low priority group, 
+//  arbitration is determined in a round-robin fashion.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////
+#define AHB_ARBITRATION_PRIORITY_CTRL_0                 _MK_ADDR_CONST(0x4)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_WORD_COUNT                      0x1
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// AHB priority weight count. This 3-bit field is  use to control 
+// the amount of attention (weight) giving to the high priority 
+// group before switching to the low priority group.
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SHIFT                       _MK_SHIFT_CONST(29)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_FIELD                       (_MK_MASK_CONST(0x7) << AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SHIFT)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_RANGE                       31:29
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_WOFFSET                     0x0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = low priority
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_FIELD                       (_MK_MASK_CONST(0x1fffffff) << AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SHIFT)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_RANGE                       28:0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_WOFFSET                     0x0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1fffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_USR_PROTECT_0  
+#define AHB_ARBITRATION_USR_PROTECT_0                   _MK_ADDR_CONST(0x8)
+#define AHB_ARBITRATION_USR_PROTECT_0_WORD_COUNT                        0x1
+#define AHB_ARBITRATION_USR_PROTECT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_RESET_MASK                        _MK_MASK_CONST(0x1ff)
+#define AHB_ARBITRATION_USR_PROTECT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_READ_MASK                         _MK_MASK_CONST(0x1ff)
+#define AHB_ARBITRATION_USR_PROTECT_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Abort on USR mode access to Cache memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SHIFT                       _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_RANGE                       8:8
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to internal ROM memory  space
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_ROM_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_RANGE                 7:7
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to APB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SHIFT                 _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_APB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_RANGE                 6:6
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to AHB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SHIFT                 _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_AHB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_RANGE                 5:5
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to PPSB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SHIFT                        _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_FIELD                        (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_RANGE                        4:4
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_WOFFSET                      0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_ABT_DIS                      _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_ABT_EN                       _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMd memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_RANGE                       3:3
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMc memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SHIFT                       _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_RANGE                       2:2
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMb memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_RANGE                       1:1
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMa memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_RANGE                       0:0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_ABT_EN                      _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_AHB_MEM_0  
+#define AHB_GIZMO_AHB_MEM_0                     _MK_ADDR_CONST(0xc)
+#define AHB_GIZMO_AHB_MEM_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_AHB_MEM_0_RESET_VAL                   _MK_MASK_CONST(0x200c1)
+#define AHB_GIZMO_AHB_MEM_0_RESET_MASK                  _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_AHB_MEM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_READ_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_AHB_MEM_0_WRITE_MASK                  _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit counter use to indicate 
+// the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SHIFT                   _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_FIELD                   (_MK_MASK_CONST(0xff) << AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_RANGE                   31:24
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately 
+// 1 = start the AHB write request immediately as soon as the device 
+// has put one write data in hte AHB gizmos queue. 0 = start the AHB 
+// write request only when all the  write data has transferred from 
+// the device to the AHB gizmos queue.
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_RANGE                     18:18
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Maximum 
+// allowed AHB burst size. 
+// 00 = single transfer. 
+// 01 = burst-of-4. 
+// 10 = burst-of-8 
+// 11 = burst-of-16.
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SHIFT                     _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_RANGE                     17:16
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                  _MK_ENUM_CONST(1)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                  _MK_ENUM_CONST(2)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                 _MK_ENUM_CONST(3)
+
+// AHB slave gizmo (memory controller)-Dont split AHB write transaction 1 = dont 
+// split AHB write transaction  ever. 0 (and enable_split=1) = allow AHB write 
+// transaction to be split.
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SHIFT                     _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_RANGE                     7:7
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DISABLE                   _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Accept AHB write request 
+// always. 1= always accept AHB write request without checking 
+// whether there is room in the queue to store the write data.Bypass 
+// Memory Controller AHB slave gizmo write queue. 0 = accept AHB 
+// write request only when theres  enough room in the queue to store 
+// all the write data. Memory controller AHB  slave gizmos write queue 
+// is used in this case.
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                  _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_RANGE                  6:6
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration. 1 = allow AHB master re-arbitration as 
+// soon as the device returns one read data into the gizmos queue. 0 = allow AHB master 
+// re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SHIFT                  _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_RANGE                  2:2
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_ENABLE                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Foce all AHB transaction to single 
+// data request transaction 1 = force to single data transaction always.  
+// 0 = dont force to single data transaction.
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SHIFT                   _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_RANGE                   1:1
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Enable splitting AHB transaction. 
+// 1 = enable 0 = disable.
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_RANGE                  0:0
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_APB_DMA_0  
+#define AHB_GIZMO_APB_DMA_0                     _MK_ADDR_CONST(0x10)
+#define AHB_GIZMO_APB_DMA_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_APB_DMA_0_RESET_VAL                   _MK_MASK_CONST(0xa0000)
+#define AHB_GIZMO_APB_DMA_0_RESET_MASK                  _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_APB_DMA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_READ_MASK                   _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_APB_DMA_0_WRITE_MASK                  _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate 
+// the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SHIFT                   _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_FIELD                   (_MK_MASK_CONST(0xff) << AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_RANGE                   31:24
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_WOFFSET                 0x0
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all 
+// requested read data to be in the AHB gizmos queue before returning 
+// the data back to the IP. 0 = transfer each read data from the AHB 
+// to the IP  immediately.
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SHIFT                       _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_APB_DMA_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_RANGE                       19:19
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_WOFFSET                     0x0
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_NO_WAIT                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_WAIT                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  
+// 1 = start the AHB write request immediately as soon as the device has 
+// put one write data in the AHB gizmos queue. 0 = start the AHB write 
+// request only when all the  write data has transferred from the device 
+// to the AHB gizmos queue.
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_APB_DMA_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_RANGE                     18:18
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SHIFT                     _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_RANGE                     17:16
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_WOFFSET                   0x0
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                  _MK_ENUM_CONST(1)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                  _MK_ENUM_CONST(2)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                 _MK_ENUM_CONST(3)
+
+
+// Reserved address 20 [0x14] 
+
+// Register AHB_GIZMO_IDE_0  
+#define AHB_GIZMO_IDE_0                 _MK_ADDR_CONST(0x18)
+#define AHB_GIZMO_IDE_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_IDE_0_RESET_VAL                       _MK_MASK_CONST(0x200bf)
+#define AHB_GIZMO_IDE_0_RESET_MASK                      _MK_MASK_CONST(0xff0f00ff)
+#define AHB_GIZMO_IDE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_READ_MASK                       _MK_MASK_CONST(0xff0f00ff)
+#define AHB_GIZMO_IDE_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f00ff)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk 
+// count between requests from  this AHB master.
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_IDE_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data 
+// to be in the AHB gizmos queue before returning the data back to the IP. 0 = transfer 
+// each read data from the AHB to the IP  immediately.
+#define AHB_GIZMO_IDE_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_IDE_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_IDE_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_IDE_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_IDE_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the 
+// AHB write request immediately as soon as the device has put one write data in the 
+// AHB gizmos queue. 0 = start the AHB write request only when all the  write data 
+// has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_IDE_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction 
+// ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept 
+// AHB write request without checking whether there is room in the queue 
+// to store the write data. 0 = accept AHB write request only when theres  
+// enough room in the queue to store all the write data.
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo  Maximum allowed IP 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.
+// 11 = burst-of-16.
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_FIELD                  (_MK_MASK_CONST(0x3) << AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_RANGE                  5:4
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_WOFFSET                        0x0
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DEFAULT                        _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                       _MK_ENUM_CONST(1)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                       _MK_ENUM_CONST(2)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                      _MK_ENUM_CONST(3)
+
+// AHB slave gizmo  Start write request to device immediately.  1 = start write request on the device side as soon 
+// as the AHB master puts data into the gizmos queue. 0 = start the device write request only when the  AHB master 
+// has placed all write data into the gizmos queue.
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon 
+// as the device returns one read data into the gizmos queue.0 = allow AHB master re-arbitration 
+// only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always. 
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable, 0 = disable.
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_USB_0  
+#define AHB_GIZMO_USB_0                 _MK_ADDR_CONST(0x1c)
+#define AHB_GIZMO_USB_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_USB_0_RESET_VAL                       _MK_MASK_CONST(0x20083)
+#define AHB_GIZMO_USB_0_RESET_MASK                      _MK_MASK_CONST(0xff0f00cf)
+#define AHB_GIZMO_USB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_READ_MASK                       _MK_MASK_CONST(0xff0f00cf)
+#define AHB_GIZMO_USB_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f00cf)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_USB_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in 
+// the AHB gizmos queue before returning the data back to the IP. 0 = transfer each read data 
+// from the AHB to the IP  immediately.
+#define AHB_GIZMO_USB_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_USB_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_USB_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_USB_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_USB_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device has put one write data in the AHB gizmos 
+// queue. 0 = start the AHB write request only when all the  write data has transferred 
+// from the device to the AHB gizmos queue.
+#define AHB_GIZMO_USB_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_USB_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_USB_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction 
+// ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept 
+// AHB write request without checking whether there is room in the queue 
+// to store the write data. 0 = accept AHB write request only when theres  
+// enough room in the queue to store all the write data.
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo  Start write request to device immediately.  1 = start write request on 
+// the device side as soon as the AHB master puts data into the gizmos queue. 0 = start the 
+// device write request only when the  AHB master has placed all write data into the gizmos 
+// queue.
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DISABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_ENABLE                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon 
+// as the device returns one read data into the gizmos queue. 0 = allow AHB master 
+// re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always. 
+// 0 = dont force to single data transaction.
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_AHB_XBAR_BRIDGE_0  
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0                     _MK_ADDR_CONST(0x20)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_RESET_VAL                   _MK_MASK_CONST(0x8d)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 
+// 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SHIFT                     _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_RANGE                     7:7
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DISABLE                   _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write 
+// request without checking whether there is room in the queue to store the write 
+// data. 0 = accept AHB write request only when theres  enough room in the queue 
+// to store all the write data.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                  _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_RANGE                  6:6
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Maximum allowed IP burst 
+// size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_RANGE                      5:4
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Start write request to device immediately.  1 = start write request on the 
+// device side as soon as the AHB master puts data into the gizmos queue.  0 = start the device 
+// write request only when the  AHB master has placed all write data into the gizmos queue.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_RANGE                     3:3
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as 
+// the device returns one read data into the gizmos queue.  0 = allow AHB master re-arbitration 
+// only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SHIFT                  _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_RANGE                  2:2
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_ENABLE                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always.  
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SHIFT                   _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_RANGE                   1:1
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable 0 = disable
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_RANGE                  0:0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_CPU_AHB_BRIDGE_0  
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0                      _MK_ADDR_CONST(0x24)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RESET_VAL                    _MK_MASK_CONST(0x60000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RESET_MASK                   _MK_MASK_CONST(0xf0000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_READ_MASK                    _MK_MASK_CONST(0xf0000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_WRITE_MASK                   _MK_MASK_CONST(0xf0000)
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in the 
+// AHB gizmos queue before returning the data back to the IP.  0 = transfer each read data from 
+// the AHB to the IP  immediately.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SHIFT                        _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_RANGE                        19:19
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_WOFFSET                      0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_NO_WAIT                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_WAIT                 _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB write 
+// request immediately as soon as the device  has put one write data in the AHB gizmos queue.  
+// 0 = start the AHB write request only when all the  write data has transferred from the 
+// device to the AHB gizmos queue.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed AHB 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_COP_AHB_BRIDGE_0  
+#define AHB_GIZMO_COP_AHB_BRIDGE_0                      _MK_ADDR_CONST(0x28)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RESET_VAL                    _MK_MASK_CONST(0x60000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RESET_MASK                   _MK_MASK_CONST(0xf0000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_READ_MASK                    _MK_MASK_CONST(0xf0000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_WRITE_MASK                   _MK_MASK_CONST(0xf0000)
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in the 
+// AHB gizmos queue before returning the data back to the IP.  0 = transfer each read data from 
+// the AHB to the IP  immediately.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SHIFT                        _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_RANGE                        19:19
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_WOFFSET                      0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_NO_WAIT                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_WAIT                 _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB write 
+// request immediately as soon as the device  has put one write data in the AHB gizmos queue.  
+// 0 = start the AHB write request only when all the  write data has transferred from the 
+// device to the AHB gizmos queue.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed AHB 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_XBAR_APB_CTLR_0  
+#define AHB_GIZMO_XBAR_APB_CTLR_0                       _MK_ADDR_CONST(0x2c)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_WORD_COUNT                    0x1
+#define AHB_GIZMO_XBAR_APB_CTLR_0_RESET_VAL                     _MK_MASK_CONST(0x8)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_RESET_MASK                    _MK_MASK_CONST(0x38)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_READ_MASK                     _MK_MASK_CONST(0x38)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_WRITE_MASK                    _MK_MASK_CONST(0x38)
+// AHB slave gizmo - Maximum allowed IP 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_RANGE                        5:4
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Start write request to device immediately.  1 = start write request on 
+// the device side as soon as the AHB master puts data into the gizmos queue.  0 = start 
+// the device write request only when the  AHB master has placed all write data into the 
+// gizmos queue.
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DISABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Register AHB_GIZMO_NAND_0  
+#define AHB_GIZMO_NAND_0                        _MK_ADDR_CONST(0x3c)
+#define AHB_GIZMO_NAND_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_NAND_0_RESET_VAL                      _MK_MASK_CONST(0xa0000)
+#define AHB_GIZMO_NAND_0_RESET_MASK                     _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_NAND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_READ_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_NAND_0_WRITE_MASK                     _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_NAND_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_NAND_0_RD_DATA_SHIFT                  _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_NAND_0_RD_DATA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_NAND_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_NAND_0_RD_DATA_RANGE                  19:19
+#define AHB_GIZMO_NAND_0_RD_DATA_WOFFSET                        0x0
+#define AHB_GIZMO_NAND_0_RD_DATA_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_RD_DATA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_RD_DATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_RD_DATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_RD_DATA_NO_WAIT                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_RD_DATA_WAIT                   _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_NAND_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_NAND_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Reserved address 64 [0x40] 
+
+// Register AHB_GIZMO_HSMMC1_0  
+#define AHB_GIZMO_HSMMC1_0                      _MK_ADDR_CONST(0x44)
+#define AHB_GIZMO_HSMMC1_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_HSMMC1_0_RESET_VAL                    _MK_MASK_CONST(0x40000)
+#define AHB_GIZMO_HSMMC1_0_RESET_MASK                   _MK_MASK_CONST(0xff040000)
+#define AHB_GIZMO_HSMMC1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_READ_MASK                    _MK_MASK_CONST(0xff040000)
+#define AHB_GIZMO_HSMMC1_0_WRITE_MASK                   _MK_MASK_CONST(0xff040000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_HSMMC1_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_HSMMC1_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_XIO_0  
+#define AHB_GIZMO_XIO_0                 _MK_ADDR_CONST(0x48)
+#define AHB_GIZMO_XIO_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_XIO_0_RESET_VAL                       _MK_MASK_CONST(0x40000)
+#define AHB_GIZMO_XIO_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_XIO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_XIO_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_XIO_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_XIO_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_XIO_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_XIO_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_XIO_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_XIO_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_XIO_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_XIO_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_XIO_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Register AHB_GIZMO_BSEV_0  
+#define AHB_GIZMO_BSEV_0                        _MK_ADDR_CONST(0x60)
+#define AHB_GIZMO_BSEV_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_BSEV_0_RESET_VAL                      _MK_MASK_CONST(0x20000)
+#define AHB_GIZMO_BSEV_0_RESET_MASK                     _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_BSEV_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_READ_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_BSEV_0_WRITE_MASK                     _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_BSEV_0_RD_DATA_SHIFT                  _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_BSEV_0_RD_DATA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEV_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_BSEV_0_RD_DATA_RANGE                  19:19
+#define AHB_GIZMO_BSEV_0_RD_DATA_WOFFSET                        0x0
+#define AHB_GIZMO_BSEV_0_RD_DATA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEV_0_RD_DATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_NO_WAIT                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_WAIT                   _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue. !!THIS SHOULD NEVER BE SET TO 
+// ENABLE!! (BSEV requires this bit to be 0) 
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEV_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.
+// 11 = burst-of-16.
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register AHB_GIZMO_BSEA_0  
+#define AHB_GIZMO_BSEA_0                        _MK_ADDR_CONST(0x70)
+#define AHB_GIZMO_BSEA_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_BSEA_0_RESET_VAL                      _MK_MASK_CONST(0x20000)
+#define AHB_GIZMO_BSEA_0_RESET_MASK                     _MK_MASK_CONST(0xff070000)
+#define AHB_GIZMO_BSEA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_READ_MASK                      _MK_MASK_CONST(0xff070000)
+#define AHB_GIZMO_BSEA_0_WRITE_MASK                     _MK_MASK_CONST(0xff070000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device puts data in the AHB gizmos 
+// queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.  !!THIS SHOULD NEVER BE 
+// SET TO ENABLE!! (BSEV requires this bit to be 0) 
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEA_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_NOR_0  
+#define AHB_GIZMO_NOR_0                 _MK_ADDR_CONST(0x74)
+#define AHB_GIZMO_NOR_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_NOR_0_RESET_VAL                       _MK_MASK_CONST(0x85)
+#define AHB_GIZMO_NOR_0_RESET_MASK                      _MK_MASK_CONST(0xc7)
+#define AHB_GIZMO_NOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_READ_MASK                       _MK_MASK_CONST(0xc7)
+#define AHB_GIZMO_NOR_0_WRITE_MASK                      _MK_MASK_CONST(0xc7)
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB 
+// write transaction ever. 0 (and enable_split=1) = allow AHB write  
+// transaction to be split.
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  
+// 1 = always accept AHB write request without checking whether 
+// there is room in the queue to store the write data. 0 = accept 
+// AHB write request only when theres  enough room in the queue 
+// to store all the write data.
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master 
+// re-arbitration as soon as the device returns one read data into the gizmos 
+// queue.  0 = allow AHB master re-arbitration only when the  device returns all 
+// read data into the gizmos queue.
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request 
+// transaction.  1 = force to single data transaction always.  
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable 0 = disable
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Register AHB_ARBITRATION_XBAR_CTRL_0  
+#define AHB_ARBITRATION_XBAR_CTRL_0                     _MK_ADDR_CONST(0xdc)
+#define AHB_ARBITRATION_XBAR_CTRL_0_WORD_COUNT                  0x1
+#define AHB_ARBITRATION_XBAR_CTRL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_RESET_MASK                  _MK_MASK_CONST(0x10003)
+#define AHB_ARBITRATION_XBAR_CTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_READ_MASK                   _MK_MASK_CONST(0x10003)
+#define AHB_ARBITRATION_XBAR_CTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x10003)
+// SW should set this bit when memory has been initialized
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_RANGE                 16:16
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_WOFFSET                       0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_NOT_DONE                      _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DONE                  _MK_ENUM_CONST(1)
+
+// By default CPU accesses to IRAMs will be held if  there are any pending requests from the AHB to the 
+// IRAMs. This is done to  avoid data coherency issues. If SW handles coherency then this can be turned  
+// off to improve performance.SW writes to modify
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SHIFT                      _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_RANGE                      1:1
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_WOFFSET                    0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DISABLE                    _MK_ENUM_CONST(1)
+
+// SW writes to modify
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_RANGE                      0:0
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_WOFFSET                    0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DISABLE                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Register AHB_AVP_PPCS_RD_COH_STATUS_0  
+#define AHB_AVP_PPCS_RD_COH_STATUS_0                    _MK_ADDR_CONST(0xe8)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WORD_COUNT                         0x1
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x10001)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_FIELD                      (_MK_MASK_CONST(0x1) << AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SHIFT)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_RANGE                      16:16
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_WOFFSET                    0x0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_FIELD                      (_MK_MASK_CONST(0x1) << AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SHIFT)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_RANGE                      0:0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_WOFFSET                    0x0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG1_0  
+#define AHB_AHB_MEM_PREFETCH_CFG1_0                     _MK_ADDR_CONST(0xec)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_RESET_VAL                   _MK_MASK_CONST(0x14830800)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// AHBDMA master
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x5)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_0B                        _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_11                        _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_12                        _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_14                        _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 0=0, else 2^(n-1). any value >16 will n=16
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x3)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 2048 cycles
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG2_0  
+#define AHB_AHB_MEM_PREFETCH_CFG2_0                     _MK_ADDR_CONST(0xf0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_RESET_VAL                   _MK_MASK_CONST(0x18830800)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// USB
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x6)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_0B                        _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_11                        _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_12                        _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_14                        _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 0=0, else 2^(n-1). any value >16 will n=16
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x3)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHBSLVMEM_STATUS_0  
+#define AHB_AHBSLVMEM_STATUS_0                  _MK_ADDR_CONST(0xf4)
+#define AHB_AHBSLVMEM_STATUS_0_WORD_COUNT                       0x1
+#define AHB_AHBSLVMEM_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x3)
+#define AHB_AHBSLVMEM_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_FIELD                       (_MK_MASK_CONST(0x1) << AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SHIFT)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_RANGE                       1:1
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_WOFFSET                     0x0
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_FIELD                       (_MK_MASK_CONST(0x1) << AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SHIFT)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_RANGE                       0:0
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_WOFFSET                     0x0
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0  
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0                  _MK_ADDR_CONST(0xf8)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_WORD_COUNT                       0x1
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_RESET_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_READ_MASK                        _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_WRITE_MASK                       _MK_MASK_CONST(0x7fffffff)
+// 0 = there is no write data in the write queue from  that AHB master.
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_FIELD                      (_MK_MASK_CONST(0x7fffffff) << AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SHIFT)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_RANGE                      30:0
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_WOFFSET                    0x0
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_CPU_ABORT_INFO_0  
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0                        _MK_ADDR_CONST(0xfc)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Abort occurred due to an iRAMa protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SHIFT                    _MK_SHIFT_CONST(15)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_RANGE                    15:15
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMb protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SHIFT                    _MK_SHIFT_CONST(14)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_RANGE                    14:14
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMc protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_RANGE                    13:13
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMd protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SHIFT                    _MK_SHIFT_CONST(12)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_RANGE                    12:12
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an access to invalid iRAM  address space
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SHIFT                 _MK_SHIFT_CONST(11)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_RANGE                 11:11
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_WOFFSET                       0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort occurred due to a PPSB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SHIFT                     _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_RANGE                     10:10
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Abort occurred due to an APB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SHIFT                      _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_RANGE                      9:9
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_WOFFSET                    0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to an AHB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SHIFT                      _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_RANGE                      8:8
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_WOFFSET                    0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to a Cache protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SHIFT                    _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_RANGE                    7:7
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for any protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SHIFT                       _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_RANGE                       6:6
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_WOFFSET                     0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_ABT_EN                      _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Misalignment (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SHIFT                    _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_RANGE                    5:5
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Bad Size (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_RANGE                  4:4
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_WOFFSET                        0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_ABT_DIS                        _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_ABT_EN                 _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Write
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SHIFT                    _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_RANGE                    3:3
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Data access
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_RANGE                     2:2
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Aborted transaction Request Size 00=byte,  01=hword, 10=word
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_RANGE                     1:0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_BYTE_ABT                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_HWORD_ABT                 _MK_ENUM_CONST(1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_WORD_ABT                  _MK_ENUM_CONST(2)
+
+
+// Register AHB_ARBITRATION_CPU_ABORT_ADDR_0  
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0                        _MK_ADDR_CONST(0x100)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Instruction Address which caused the abort
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_FIELD                     (_MK_MASK_CONST(0xffffffff) << AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_RANGE                     31:0
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_COP_ABORT_INFO_0  
+#define AHB_ARBITRATION_COP_ABORT_INFO_0                        _MK_ADDR_CONST(0x104)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_RESET_MASK                     _MK_MASK_CONST(0xe7ff)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_READ_MASK                      _MK_MASK_CONST(0xe7ff)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Abort occurred due to an iRAMa protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SHIFT                    _MK_SHIFT_CONST(15)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_RANGE                    15:15
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMb protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SHIFT                    _MK_SHIFT_CONST(14)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_RANGE                    14:14
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMc protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_RANGE                    13:13
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to a PPSB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SHIFT                     _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_RANGE                     10:10
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Abort occurred due to an APB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SHIFT                      _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_RANGE                      9:9
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_WOFFSET                    0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to an AHB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SHIFT                      _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_RANGE                      8:8
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_WOFFSET                    0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to a Cache protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SHIFT                    _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_RANGE                    7:7
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for any protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SHIFT                       _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_RANGE                       6:6
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_WOFFSET                     0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_ABT_EN                      _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Misalignment (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SHIFT                    _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_RANGE                    5:5
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Bad Size (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_RANGE                  4:4
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_WOFFSET                        0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_ABT_DIS                        _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_ABT_EN                 _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Write
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SHIFT                    _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_RANGE                    3:3
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Data access
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_RANGE                     2:2
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Aborted transaction Request Size 00=byte,  01=hword, 10=word
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_RANGE                     1:0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_BYTE_ABT                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_HWORD_ABT                 _MK_ENUM_CONST(1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_WORD_ABT                  _MK_ENUM_CONST(2)
+
+
+// Register AHB_ARBITRATION_COP_ABORT_ADDR_0  
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0                        _MK_ADDR_CONST(0x108)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Instruction Address which caused the abort
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_FIELD                     (_MK_MASK_CONST(0xffffffff) << AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_RANGE                     31:0
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAHB_ARBC_REGS(_op_) \
+_op_(AHB_ARBITRATION_DISABLE_0) \
+_op_(AHB_ARBITRATION_PRIORITY_CTRL_0) \
+_op_(AHB_ARBITRATION_USR_PROTECT_0) \
+_op_(AHB_GIZMO_AHB_MEM_0) \
+_op_(AHB_GIZMO_APB_DMA_0) \
+_op_(AHB_GIZMO_IDE_0) \
+_op_(AHB_GIZMO_USB_0) \
+_op_(AHB_GIZMO_AHB_XBAR_BRIDGE_0) \
+_op_(AHB_GIZMO_CPU_AHB_BRIDGE_0) \
+_op_(AHB_GIZMO_COP_AHB_BRIDGE_0) \
+_op_(AHB_GIZMO_XBAR_APB_CTLR_0) \
+_op_(AHB_GIZMO_NAND_0) \
+_op_(AHB_GIZMO_HSMMC1_0) \
+_op_(AHB_GIZMO_XIO_0) \
+_op_(AHB_GIZMO_BSEV_0) \
+_op_(AHB_GIZMO_BSEA_0) \
+_op_(AHB_GIZMO_NOR_0) \
+_op_(AHB_ARBITRATION_XBAR_CTRL_0) \
+_op_(AHB_AVP_PPCS_RD_COH_STATUS_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG1_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG2_0) \
+_op_(AHB_AHBSLVMEM_STATUS_0) \
+_op_(AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0) \
+_op_(AHB_ARBITRATION_CPU_ABORT_INFO_0) \
+_op_(AHB_ARBITRATION_CPU_ABORT_ADDR_0) \
+_op_(AHB_ARBITRATION_COP_ABORT_INFO_0) \
+_op_(AHB_ARBITRATION_COP_ABORT_ADDR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_AHB        0x00000000
+
+//
+// ARAHB_ARBC REGISTER BANKS
+//
+
+#define AHB0_FIRST_REG 0x0000 // AHB_ARBITRATION_DISABLE_0
+#define AHB0_LAST_REG 0x0010 // AHB_GIZMO_APB_DMA_0
+#define AHB1_FIRST_REG 0x0018 // AHB_GIZMO_IDE_0
+#define AHB1_LAST_REG 0x002c // AHB_GIZMO_XBAR_APB_CTLR_0
+#define AHB2_FIRST_REG 0x003c // AHB_GIZMO_NAND_0
+#define AHB2_LAST_REG 0x003c // AHB_GIZMO_NAND_0
+#define AHB3_FIRST_REG 0x0044 // AHB_GIZMO_HSMMC1_0
+#define AHB3_LAST_REG 0x0048 // AHB_GIZMO_XIO_0
+#define AHB4_FIRST_REG 0x0060 // AHB_GIZMO_BSEV_0
+#define AHB4_LAST_REG 0x0060 // AHB_GIZMO_BSEV_0
+#define AHB5_FIRST_REG 0x0070 // AHB_GIZMO_BSEA_0
+#define AHB5_LAST_REG 0x0074 // AHB_GIZMO_NOR_0
+#define AHB6_FIRST_REG 0x00dc // AHB_ARBITRATION_XBAR_CTRL_0
+#define AHB6_LAST_REG 0x00dc // AHB_ARBITRATION_XBAR_CTRL_0
+#define AHB7_FIRST_REG 0x00e8 // AHB_AVP_PPCS_RD_COH_STATUS_0
+#define AHB7_LAST_REG 0x0108 // AHB_ARBITRATION_COP_ABORT_ADDR_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAHB_ARBC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arapb_cmc.h b/arch/arm/mach-tegra/nv/include/ap15/arapb_cmc.h
new file mode 100644
index 000000000000..246c7b7453d6
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arapb_cmc.h
@@ -0,0 +1,873 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPB_CMC_H_INC_
+#define ___ARAPB_CMC_H_INC_
+// --------------------------------------------------------------------------
+//
+// Copyright (c) 2006, NVIDIA Corp.
+// All Rights Reserved.
+//
+// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
+// the contents of this file may not be disclosed to third parties, copied or
+// duplicated in any form, in whole or in part, without the prior written
+// permission of NVIDIA Corp.
+//
+// RESTRICTED RIGHTS LEGEND:
+// Use, duplication or disclosure by the Government is subject to restrictions
+// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
+// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
+// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
+// rights reserved under the Copyright Laws of the United States.
+//
+// --------------------------------------------------------------------------
+//
+
+// Register APB_CMC_CONFIG_0  
+#define APB_CMC_CONFIG_0                        _MK_ADDR_CONST(0x0)
+#define APB_CMC_CONFIG_0_WORD_COUNT                     0x1
+#define APB_CMC_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define APB_CMC_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define APB_CMC_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+#define APB_CMC_CONFIG_0_ENABLE_CACHE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_CMC_CONFIG_0_ENABLE_CACHE_FIELD                     (_MK_MASK_CONST(0x1) << APB_CMC_CONFIG_0_ENABLE_CACHE_SHIFT)
+#define APB_CMC_CONFIG_0_ENABLE_CACHE_RANGE                     0:0
+#define APB_CMC_CONFIG_0_ENABLE_CACHE_WOFFSET                   0x0
+#define APB_CMC_CONFIG_0_ENABLE_CACHE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_ENABLE_CACHE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_CMC_CONFIG_0_ENABLE_CACHE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_ENABLE_CACHE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_CMC_CONFIG_0_ENABLE_SKEW_ASSOC_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_CMC_CONFIG_0_ENABLE_SKEW_ASSOC_FIELD                        (_MK_MASK_CONST(0x1) << APB_CMC_CONFIG_0_ENABLE_SKEW_ASSOC_SHIFT)
+#define APB_CMC_CONFIG_0_ENABLE_SKEW_ASSOC_RANGE                        1:1
+#define APB_CMC_CONFIG_0_ENABLE_SKEW_ASSOC_WOFFSET                      0x0
+#define APB_CMC_CONFIG_0_ENABLE_SKEW_ASSOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_ENABLE_SKEW_ASSOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_CMC_CONFIG_0_ENABLE_SKEW_ASSOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_ENABLE_SKEW_ASSOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_CMC_CONFIG_0_DISABLE_RANDOM_ALLOC_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_CMC_CONFIG_0_DISABLE_RANDOM_ALLOC_FIELD                     (_MK_MASK_CONST(0x1) << APB_CMC_CONFIG_0_DISABLE_RANDOM_ALLOC_SHIFT)
+#define APB_CMC_CONFIG_0_DISABLE_RANDOM_ALLOC_RANGE                     2:2
+#define APB_CMC_CONFIG_0_DISABLE_RANDOM_ALLOC_WOFFSET                   0x0
+#define APB_CMC_CONFIG_0_DISABLE_RANDOM_ALLOC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_DISABLE_RANDOM_ALLOC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_CMC_CONFIG_0_DISABLE_RANDOM_ALLOC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_DISABLE_RANDOM_ALLOC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_CMC_CONFIG_0_FORCE_WRITE_THROUGH_SHIFT                      _MK_SHIFT_CONST(3)
+#define APB_CMC_CONFIG_0_FORCE_WRITE_THROUGH_FIELD                      (_MK_MASK_CONST(0x1) << APB_CMC_CONFIG_0_FORCE_WRITE_THROUGH_SHIFT)
+#define APB_CMC_CONFIG_0_FORCE_WRITE_THROUGH_RANGE                      3:3
+#define APB_CMC_CONFIG_0_FORCE_WRITE_THROUGH_WOFFSET                    0x0
+#define APB_CMC_CONFIG_0_FORCE_WRITE_THROUGH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_FORCE_WRITE_THROUGH_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_CMC_CONFIG_0_FORCE_WRITE_THROUGH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_FORCE_WRITE_THROUGH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_CMC_CONFIG_0_ENABLE_STEERING_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_CMC_CONFIG_0_ENABLE_STEERING_FIELD                  (_MK_MASK_CONST(0x1) << APB_CMC_CONFIG_0_ENABLE_STEERING_SHIFT)
+#define APB_CMC_CONFIG_0_ENABLE_STEERING_RANGE                  4:4
+#define APB_CMC_CONFIG_0_ENABLE_STEERING_WOFFSET                        0x0
+#define APB_CMC_CONFIG_0_ENABLE_STEERING_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_ENABLE_STEERING_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_CMC_CONFIG_0_ENABLE_STEERING_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_ENABLE_STEERING_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_CMC_CONFIG_0_ENABLE_EXCLUSIVE_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_CMC_CONFIG_0_ENABLE_EXCLUSIVE_FIELD                 (_MK_MASK_CONST(0x1) << APB_CMC_CONFIG_0_ENABLE_EXCLUSIVE_SHIFT)
+#define APB_CMC_CONFIG_0_ENABLE_EXCLUSIVE_RANGE                 5:5
+#define APB_CMC_CONFIG_0_ENABLE_EXCLUSIVE_WOFFSET                       0x0
+#define APB_CMC_CONFIG_0_ENABLE_EXCLUSIVE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_ENABLE_EXCLUSIVE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_CMC_CONFIG_0_ENABLE_EXCLUSIVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_ENABLE_EXCLUSIVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_CMC_CONFIG_0_NEVER_ALLOCATE_SHIFT                   _MK_SHIFT_CONST(6)
+#define APB_CMC_CONFIG_0_NEVER_ALLOCATE_FIELD                   (_MK_MASK_CONST(0x1) << APB_CMC_CONFIG_0_NEVER_ALLOCATE_SHIFT)
+#define APB_CMC_CONFIG_0_NEVER_ALLOCATE_RANGE                   6:6
+#define APB_CMC_CONFIG_0_NEVER_ALLOCATE_WOFFSET                 0x0
+#define APB_CMC_CONFIG_0_NEVER_ALLOCATE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_NEVER_ALLOCATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_CMC_CONFIG_0_NEVER_ALLOCATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_NEVER_ALLOCATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_CMC_CONFIG_0_ENABLE_INTERRUPT_SHIFT                 _MK_SHIFT_CONST(7)
+#define APB_CMC_CONFIG_0_ENABLE_INTERRUPT_FIELD                 (_MK_MASK_CONST(0x1) << APB_CMC_CONFIG_0_ENABLE_INTERRUPT_SHIFT)
+#define APB_CMC_CONFIG_0_ENABLE_INTERRUPT_RANGE                 7:7
+#define APB_CMC_CONFIG_0_ENABLE_INTERRUPT_WOFFSET                       0x0
+#define APB_CMC_CONFIG_0_ENABLE_INTERRUPT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_ENABLE_INTERRUPT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_CMC_CONFIG_0_ENABLE_INTERRUPT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_CMC_CONFIG_0_ENABLE_INTERRUPT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_LOCK_0  
+#define APB_CMC_LOCK_0                  _MK_ADDR_CONST(0x4)
+#define APB_CMC_LOCK_0_WORD_COUNT                       0x1
+#define APB_CMC_LOCK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_LOCK_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APB_CMC_LOCK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_CMC_LOCK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_CMC_LOCK_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APB_CMC_LOCK_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define APB_CMC_LOCK_0_LOCK_BITMAP_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_CMC_LOCK_0_LOCK_BITMAP_FIELD                        (_MK_MASK_CONST(0xff) << APB_CMC_LOCK_0_LOCK_BITMAP_SHIFT)
+#define APB_CMC_LOCK_0_LOCK_BITMAP_RANGE                        7:0
+#define APB_CMC_LOCK_0_LOCK_BITMAP_WOFFSET                      0x0
+#define APB_CMC_LOCK_0_LOCK_BITMAP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_CMC_LOCK_0_LOCK_BITMAP_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define APB_CMC_LOCK_0_LOCK_BITMAP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_LOCK_0_LOCK_BITMAP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//////////////////////////////////////////////////////////////////////
+//
+//     MAX_WAY_INDEX: how many ways in cache
+//
+//                    0 : 1 way
+//                    1 : 2 way
+//                    ...
+//                    7 : 8 way
+//
+/////////////////////////////////////////////////////////////////////
+
+// Register APB_CMC_SIZE_0  
+#define APB_CMC_SIZE_0                  _MK_ADDR_CONST(0x8)
+#define APB_CMC_SIZE_0_WORD_COUNT                       0x1
+#define APB_CMC_SIZE_0_RESET_VAL                        _MK_MASK_CONST(0x7)
+#define APB_CMC_SIZE_0_RESET_MASK                       _MK_MASK_CONST(0x7)
+#define APB_CMC_SIZE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_CMC_SIZE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_CMC_SIZE_0_READ_MASK                        _MK_MASK_CONST(0x7)
+#define APB_CMC_SIZE_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_SIZE_0_MAX_WAY_INDEX_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_CMC_SIZE_0_MAX_WAY_INDEX_FIELD                      (_MK_MASK_CONST(0x7) << APB_CMC_SIZE_0_MAX_WAY_INDEX_SHIFT)
+#define APB_CMC_SIZE_0_MAX_WAY_INDEX_RANGE                      2:0
+#define APB_CMC_SIZE_0_MAX_WAY_INDEX_WOFFSET                    0x0
+#define APB_CMC_SIZE_0_MAX_WAY_INDEX_DEFAULT                    _MK_MASK_CONST(0x7)
+#define APB_CMC_SIZE_0_MAX_WAY_INDEX_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_CMC_SIZE_0_MAX_WAY_INDEX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_CMC_SIZE_0_MAX_WAY_INDEX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_MAINT_0_0  
+#define APB_CMC_MAINT_0_0                       _MK_ADDR_CONST(0xc)
+#define APB_CMC_MAINT_0_0_WORD_COUNT                    0x1
+#define APB_CMC_MAINT_0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_0_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_0_0_ADDR_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_CMC_MAINT_0_0_ADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_CMC_MAINT_0_0_ADDR_SHIFT)
+#define APB_CMC_MAINT_0_0_ADDR_RANGE                    31:0
+#define APB_CMC_MAINT_0_0_ADDR_WOFFSET                  0x0
+#define APB_CMC_MAINT_0_0_ADDR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_0_0_ADDR_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_0_0_ADDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_0_0_ADDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_MAINT_1_0  
+#define APB_CMC_MAINT_1_0                       _MK_ADDR_CONST(0x10)
+#define APB_CMC_MAINT_1_0_WORD_COUNT                    0x1
+#define APB_CMC_MAINT_1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_0_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_CMC_MAINT_1_0_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_CMC_MAINT_1_0_DATA_SHIFT)
+#define APB_CMC_MAINT_1_0_DATA_RANGE                    31:0
+#define APB_CMC_MAINT_1_0_DATA_WOFFSET                  0x0
+#define APB_CMC_MAINT_1_0_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_0_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_0_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_0_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_MAINT_1  
+#define APB_CMC_MAINT_1                 _MK_ADDR_CONST(0x10)
+#define APB_CMC_MAINT_1_WORD_COUNT                      0x1
+#define APB_CMC_MAINT_1_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_DATA_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_CMC_MAINT_1_DATA_FIELD                      (_MK_MASK_CONST(0xffffffff) << APB_CMC_MAINT_1_DATA_SHIFT)
+#define APB_CMC_MAINT_1_DATA_RANGE                      31:0
+#define APB_CMC_MAINT_1_DATA_WOFFSET                    0x0
+#define APB_CMC_MAINT_1_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_MAINT_1_1  
+#define APB_CMC_MAINT_1_1                       _MK_ADDR_CONST(0x14)
+#define APB_CMC_MAINT_1_1_WORD_COUNT                    0x1
+#define APB_CMC_MAINT_1_1_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_1_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_1_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_1_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_1_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_1_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_CMC_MAINT_1_1_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_CMC_MAINT_1_1_DATA_SHIFT)
+#define APB_CMC_MAINT_1_1_DATA_RANGE                    31:0
+#define APB_CMC_MAINT_1_1_DATA_WOFFSET                  0x0
+#define APB_CMC_MAINT_1_1_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_1_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_1_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_1_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_MAINT_1_2  
+#define APB_CMC_MAINT_1_2                       _MK_ADDR_CONST(0x18)
+#define APB_CMC_MAINT_1_2_WORD_COUNT                    0x1
+#define APB_CMC_MAINT_1_2_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_2_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_2_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_2_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_2_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_2_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_CMC_MAINT_1_2_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_CMC_MAINT_1_2_DATA_SHIFT)
+#define APB_CMC_MAINT_1_2_DATA_RANGE                    31:0
+#define APB_CMC_MAINT_1_2_DATA_WOFFSET                  0x0
+#define APB_CMC_MAINT_1_2_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_2_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_2_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_2_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_MAINT_1_3  
+#define APB_CMC_MAINT_1_3                       _MK_ADDR_CONST(0x1c)
+#define APB_CMC_MAINT_1_3_WORD_COUNT                    0x1
+#define APB_CMC_MAINT_1_3_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_3_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_3_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_3_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_3_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_3_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_CMC_MAINT_1_3_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_CMC_MAINT_1_3_DATA_SHIFT)
+#define APB_CMC_MAINT_1_3_DATA_RANGE                    31:0
+#define APB_CMC_MAINT_1_3_DATA_WOFFSET                  0x0
+#define APB_CMC_MAINT_1_3_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_3_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_3_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_3_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_MAINT_1_4  
+#define APB_CMC_MAINT_1_4                       _MK_ADDR_CONST(0x20)
+#define APB_CMC_MAINT_1_4_WORD_COUNT                    0x1
+#define APB_CMC_MAINT_1_4_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_4_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_4_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_4_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_4_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_4_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_CMC_MAINT_1_4_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_CMC_MAINT_1_4_DATA_SHIFT)
+#define APB_CMC_MAINT_1_4_DATA_RANGE                    31:0
+#define APB_CMC_MAINT_1_4_DATA_WOFFSET                  0x0
+#define APB_CMC_MAINT_1_4_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_4_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_4_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_4_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_MAINT_1_5  
+#define APB_CMC_MAINT_1_5                       _MK_ADDR_CONST(0x24)
+#define APB_CMC_MAINT_1_5_WORD_COUNT                    0x1
+#define APB_CMC_MAINT_1_5_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_5_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_5_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_5_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_5_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_5_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_CMC_MAINT_1_5_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_CMC_MAINT_1_5_DATA_SHIFT)
+#define APB_CMC_MAINT_1_5_DATA_RANGE                    31:0
+#define APB_CMC_MAINT_1_5_DATA_WOFFSET                  0x0
+#define APB_CMC_MAINT_1_5_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_5_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_5_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_5_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_MAINT_1_6  
+#define APB_CMC_MAINT_1_6                       _MK_ADDR_CONST(0x28)
+#define APB_CMC_MAINT_1_6_WORD_COUNT                    0x1
+#define APB_CMC_MAINT_1_6_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_6_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_6_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_6_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_6_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_6_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_CMC_MAINT_1_6_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_CMC_MAINT_1_6_DATA_SHIFT)
+#define APB_CMC_MAINT_1_6_DATA_RANGE                    31:0
+#define APB_CMC_MAINT_1_6_DATA_WOFFSET                  0x0
+#define APB_CMC_MAINT_1_6_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_6_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_6_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_6_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_MAINT_1_7  
+#define APB_CMC_MAINT_1_7                       _MK_ADDR_CONST(0x2c)
+#define APB_CMC_MAINT_1_7_WORD_COUNT                    0x1
+#define APB_CMC_MAINT_1_7_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_7_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_7_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_7_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_7_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_MAINT_1_7_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_CMC_MAINT_1_7_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_CMC_MAINT_1_7_DATA_SHIFT)
+#define APB_CMC_MAINT_1_7_DATA_RANGE                    31:0
+#define APB_CMC_MAINT_1_7_DATA_WOFFSET                  0x0
+#define APB_CMC_MAINT_1_7_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_7_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_7_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_1_7_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_MAINT_2_0  
+#define APB_CMC_MAINT_2_0                       _MK_ADDR_CONST(0x30)
+#define APB_CMC_MAINT_2_0_WORD_COUNT                    0x1
+#define APB_CMC_MAINT_2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_2_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define APB_CMC_MAINT_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_2_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define APB_CMC_MAINT_2_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
+#define APB_CMC_MAINT_2_0_OPCODE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_CMC_MAINT_2_0_OPCODE_FIELD                  (_MK_MASK_CONST(0xff) << APB_CMC_MAINT_2_0_OPCODE_SHIFT)
+#define APB_CMC_MAINT_2_0_OPCODE_RANGE                  7:0
+#define APB_CMC_MAINT_2_0_OPCODE_WOFFSET                        0x0
+#define APB_CMC_MAINT_2_0_OPCODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_2_0_OPCODE_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APB_CMC_MAINT_2_0_OPCODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_2_0_OPCODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_2_0_OPCODE_NOP                    _MK_ENUM_CONST(0)    // // no operation. after any op is executed, the field should be reset to NOP
+
+#define APB_CMC_MAINT_2_0_OPCODE_CLEAN_PHY                      _MK_ENUM_CONST(1)    // // clean by physical address
+
+#define APB_CMC_MAINT_2_0_OPCODE_INVALID_PHY                    _MK_ENUM_CONST(2)    // // invalidate by physical address
+
+#define APB_CMC_MAINT_2_0_OPCODE_CLEAN_INVALID_PHY                      _MK_ENUM_CONST(3)    // // clean AND invalidate by physical address
+
+#define APB_CMC_MAINT_2_0_OPCODE_CLEAN_WAY                      _MK_ENUM_CONST(17)    // // clean by way
+
+#define APB_CMC_MAINT_2_0_OPCODE_INVALID_WAY                    _MK_ENUM_CONST(18)    // // invalidate by way
+
+#define APB_CMC_MAINT_2_0_OPCODE_CLEAN_INVALID_WAY                      _MK_ENUM_CONST(19)    // // clean AND invalidate by way
+
+#define APB_CMC_MAINT_2_0_OPCODE_RSVD                   _MK_ENUM_CONST(20)    // // reserved
+
+#define APB_CMC_MAINT_2_0_OPCODE_READ_DATA                      _MK_ENUM_CONST(32)    // // read data ram by tag address
+
+#define APB_CMC_MAINT_2_0_OPCODE_WRITE_DATA                     _MK_ENUM_CONST(33)    // // write data ram by tag address
+
+#define APB_CMC_MAINT_2_0_OPCODE_READ_DIRTY                     _MK_ENUM_CONST(34)    // // read dirty bit by tag address
+
+#define APB_CMC_MAINT_2_0_OPCODE_WRITE_DIRTY                    _MK_ENUM_CONST(35)    // // write dirty bit by tag address
+
+#define APB_CMC_MAINT_2_0_OPCODE_READ_TAG                       _MK_ENUM_CONST(36)    // // read tag ram by tag address
+
+#define APB_CMC_MAINT_2_0_OPCODE_WRITE_TAG                      _MK_ENUM_CONST(37)    // // write tag ram by tag address
+
+
+#define APB_CMC_MAINT_2_0_WAY_BITMAP_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_CMC_MAINT_2_0_WAY_BITMAP_FIELD                      (_MK_MASK_CONST(0xff) << APB_CMC_MAINT_2_0_WAY_BITMAP_SHIFT)
+#define APB_CMC_MAINT_2_0_WAY_BITMAP_RANGE                      15:8
+#define APB_CMC_MAINT_2_0_WAY_BITMAP_WOFFSET                    0x0
+#define APB_CMC_MAINT_2_0_WAY_BITMAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_2_0_WAY_BITMAP_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define APB_CMC_MAINT_2_0_WAY_BITMAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_CMC_MAINT_2_0_WAY_BITMAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_LFSR_0  
+#define APB_CMC_LFSR_0                  _MK_ADDR_CONST(0x34)
+#define APB_CMC_LFSR_0_WORD_COUNT                       0x1
+#define APB_CMC_LFSR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_LFSR_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APB_CMC_LFSR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_CMC_LFSR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_CMC_LFSR_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APB_CMC_LFSR_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_LFSR_0_STATUS_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_CMC_LFSR_0_STATUS_FIELD                     (_MK_MASK_CONST(0xff) << APB_CMC_LFSR_0_STATUS_SHIFT)
+#define APB_CMC_LFSR_0_STATUS_RANGE                     7:0
+#define APB_CMC_LFSR_0_STATUS_WOFFSET                   0x0
+#define APB_CMC_LFSR_0_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_LFSR_0_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define APB_CMC_LFSR_0_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_CMC_LFSR_0_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+/////////////////////////////////////////////////////////////////////
+//
+// STATIC REGS
+//
+////////////////////////////////////////////////////////////////////
+
+// Register APB_CMC_STAT_CONTROL_0  
+#define APB_CMC_STAT_CONTROL_0                  _MK_ADDR_CONST(0x38)
+#define APB_CMC_STAT_CONTROL_0_WORD_COUNT                       0x1
+#define APB_CMC_STAT_CONTROL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CONTROL_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APB_CMC_STAT_CONTROL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CONTROL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CONTROL_0_READ_MASK                        _MK_MASK_CONST(0x3)
+#define APB_CMC_STAT_CONTROL_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define APB_CMC_STAT_CONTROL_0_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_CMC_STAT_CONTROL_0_ENABLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_CMC_STAT_CONTROL_0_ENABLE_SHIFT)
+#define APB_CMC_STAT_CONTROL_0_ENABLE_RANGE                     0:0
+#define APB_CMC_STAT_CONTROL_0_ENABLE_WOFFSET                   0x0
+#define APB_CMC_STAT_CONTROL_0_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CONTROL_0_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_CMC_STAT_CONTROL_0_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CONTROL_0_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_CMC_STAT_CONTROL_0_STATUS_DONE_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_CMC_STAT_CONTROL_0_STATUS_DONE_FIELD                        (_MK_MASK_CONST(0x1) << APB_CMC_STAT_CONTROL_0_STATUS_DONE_SHIFT)
+#define APB_CMC_STAT_CONTROL_0_STATUS_DONE_RANGE                        1:1
+#define APB_CMC_STAT_CONTROL_0_STATUS_DONE_WOFFSET                      0x0
+#define APB_CMC_STAT_CONTROL_0_STATUS_DONE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CONTROL_0_STATUS_DONE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CONTROL_0_STATUS_DONE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CONTROL_0_STATUS_DONE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_STAT_STATE_0  
+#define APB_CMC_STAT_STATE_0                    _MK_ADDR_CONST(0x3c)
+#define APB_CMC_STAT_STATE_0_WORD_COUNT                         0x1
+#define APB_CMC_STAT_STATE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_STATE_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_STATE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_STATE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_STATE_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define APB_CMC_STAT_STATE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
+#define APB_CMC_STAT_STATE_0_CLEAR_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_CMC_STAT_STATE_0_CLEAR_FIELD                        (_MK_MASK_CONST(0x1) << APB_CMC_STAT_STATE_0_CLEAR_SHIFT)
+#define APB_CMC_STAT_STATE_0_CLEAR_RANGE                        0:0
+#define APB_CMC_STAT_STATE_0_CLEAR_WOFFSET                      0x0
+#define APB_CMC_STAT_STATE_0_CLEAR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_STATE_0_CLEAR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_STATE_0_CLEAR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_STATE_0_CLEAR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_STAT_FILTER_0  
+#define APB_CMC_STAT_FILTER_0                   _MK_ADDR_CONST(0x40)
+#define APB_CMC_STAT_FILTER_0_WORD_COUNT                        0x1
+#define APB_CMC_STAT_FILTER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_FILTER_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_FILTER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_FILTER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_FILTER_0_READ_MASK                         _MK_MASK_CONST(0x7)
+#define APB_CMC_STAT_FILTER_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
+#define APB_CMC_STAT_FILTER_0_EVENT_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_CMC_STAT_FILTER_0_EVENT_FIELD                       (_MK_MASK_CONST(0x7) << APB_CMC_STAT_FILTER_0_EVENT_SHIFT)
+#define APB_CMC_STAT_FILTER_0_EVENT_RANGE                       2:0
+#define APB_CMC_STAT_FILTER_0_EVENT_WOFFSET                     0x0
+#define APB_CMC_STAT_FILTER_0_EVENT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_FILTER_0_EVENT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_FILTER_0_EVENT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_FILTER_0_EVENT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_FILTER_0_EVENT_ALL_TRANS                   _MK_ENUM_CONST(0)
+#define APB_CMC_STAT_FILTER_0_EVENT_INSTRUCTION_READ                    _MK_ENUM_CONST(1)
+#define APB_CMC_STAT_FILTER_0_EVENT_DATA_READ                   _MK_ENUM_CONST(2)
+#define APB_CMC_STAT_FILTER_0_EVENT_WRITE_BACK_ALLOC                    _MK_ENUM_CONST(3)
+#define APB_CMC_STAT_FILTER_0_EVENT_WRITE_BACK_NO_ALLOC                 _MK_ENUM_CONST(4)
+#define APB_CMC_STAT_FILTER_0_EVENT_WRITE_THROUGH                       _MK_ENUM_CONST(5)
+
+
+// Register APB_CMC_STAT_CLOCK_0  
+#define APB_CMC_STAT_CLOCK_0                    _MK_ADDR_CONST(0x44)
+#define APB_CMC_STAT_CLOCK_0_WORD_COUNT                         0x1
+#define APB_CMC_STAT_CLOCK_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CLOCK_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CLOCK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CLOCK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CLOCK_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_STAT_CLOCK_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Maximum number of cycles that data may be
+// collected before STATUS_LIMIT bit is set
+#define APB_CMC_STAT_CLOCK_0_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_CMC_STAT_CLOCK_0_COUNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << APB_CMC_STAT_CLOCK_0_COUNT_SHIFT)
+#define APB_CMC_STAT_CLOCK_0_COUNT_RANGE                        31:0
+#define APB_CMC_STAT_CLOCK_0_COUNT_WOFFSET                      0x0
+#define APB_CMC_STAT_CLOCK_0_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CLOCK_0_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CLOCK_0_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_CLOCK_0_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_STAT_HIT_0  
+#define APB_CMC_STAT_HIT_0                      _MK_ADDR_CONST(0x48)
+#define APB_CMC_STAT_HIT_0_WORD_COUNT                   0x1
+#define APB_CMC_STAT_HIT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_HIT_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_HIT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_HIT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_HIT_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_STAT_HIT_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Number of Cache Hit
+#define APB_CMC_STAT_HIT_0_COUNT_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_CMC_STAT_HIT_0_COUNT_FIELD                  (_MK_MASK_CONST(0xffffffff) << APB_CMC_STAT_HIT_0_COUNT_SHIFT)
+#define APB_CMC_STAT_HIT_0_COUNT_RANGE                  31:0
+#define APB_CMC_STAT_HIT_0_COUNT_WOFFSET                        0x0
+#define APB_CMC_STAT_HIT_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_HIT_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_HIT_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_HIT_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_STAT_MISS_ALLOC_0  
+#define APB_CMC_STAT_MISS_ALLOC_0                       _MK_ADDR_CONST(0x4c)
+#define APB_CMC_STAT_MISS_ALLOC_0_WORD_COUNT                    0x1
+#define APB_CMC_STAT_MISS_ALLOC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_ALLOC_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_ALLOC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_ALLOC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_ALLOC_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_STAT_MISS_ALLOC_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Number of cache miss, which cause allocation in cache.
+// This includes fresh allocation from cache entry with tag valid == 0 and
+// eviction allocation from cache entry with dirty bit == 0.
+// The second case doesn't require memory write because the data is not dirty.
+#define APB_CMC_STAT_MISS_ALLOC_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_CMC_STAT_MISS_ALLOC_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << APB_CMC_STAT_MISS_ALLOC_0_COUNT_SHIFT)
+#define APB_CMC_STAT_MISS_ALLOC_0_COUNT_RANGE                   31:0
+#define APB_CMC_STAT_MISS_ALLOC_0_COUNT_WOFFSET                 0x0
+#define APB_CMC_STAT_MISS_ALLOC_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_ALLOC_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_ALLOC_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_ALLOC_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_STAT_MISS_NO_ALLOC_0  
+#define APB_CMC_STAT_MISS_NO_ALLOC_0                    _MK_ADDR_CONST(0x50)
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_WORD_COUNT                         0x1
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Number of cache miss, which are directly sent
+// to memory without any cache allocation/eviction
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_COUNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << APB_CMC_STAT_MISS_NO_ALLOC_0_COUNT_SHIFT)
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_COUNT_RANGE                        31:0
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_COUNT_WOFFSET                      0x0
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_NO_ALLOC_0_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_STAT_MISS_EVICT_0  
+#define APB_CMC_STAT_MISS_EVICT_0                       _MK_ADDR_CONST(0x54)
+#define APB_CMC_STAT_MISS_EVICT_0_WORD_COUNT                    0x1
+#define APB_CMC_STAT_MISS_EVICT_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_EVICT_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_EVICT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_EVICT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_EVICT_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_STAT_MISS_EVICT_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Number of cache miss, which cause cache eviction
+// Anything covered in STAT_MISS_ALLOC should NOT be counted here!!!
+// Only the dirty data will be counted.
+#define APB_CMC_STAT_MISS_EVICT_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_CMC_STAT_MISS_EVICT_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << APB_CMC_STAT_MISS_EVICT_0_COUNT_SHIFT)
+#define APB_CMC_STAT_MISS_EVICT_0_COUNT_RANGE                   31:0
+#define APB_CMC_STAT_MISS_EVICT_0_COUNT_WOFFSET                 0x0
+#define APB_CMC_STAT_MISS_EVICT_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_EVICT_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_EVICT_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_MISS_EVICT_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_STAT_ADDR_HAZARD_0  
+#define APB_CMC_STAT_ADDR_HAZARD_0                      _MK_ADDR_CONST(0x58)
+#define APB_CMC_STAT_ADDR_HAZARD_0_WORD_COUNT                   0x1
+#define APB_CMC_STAT_ADDR_HAZARD_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_ADDR_HAZARD_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_ADDR_HAZARD_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_ADDR_HAZARD_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_ADDR_HAZARD_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_CMC_STAT_ADDR_HAZARD_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Number of address conflict
+#define APB_CMC_STAT_ADDR_HAZARD_0_COUNT_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_CMC_STAT_ADDR_HAZARD_0_COUNT_FIELD                  (_MK_MASK_CONST(0xffffffff) << APB_CMC_STAT_ADDR_HAZARD_0_COUNT_SHIFT)
+#define APB_CMC_STAT_ADDR_HAZARD_0_COUNT_RANGE                  31:0
+#define APB_CMC_STAT_ADDR_HAZARD_0_COUNT_WOFFSET                        0x0
+#define APB_CMC_STAT_ADDR_HAZARD_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_ADDR_HAZARD_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_ADDR_HAZARD_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_CMC_STAT_ADDR_HAZARD_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_INT_MASK_0  
+#define APB_CMC_INT_MASK_0                      _MK_ADDR_CONST(0x5c)
+#define APB_CMC_INT_MASK_0_WORD_COUNT                   0x1
+#define APB_CMC_INT_MASK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_MASK_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_MASK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_MASK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_MASK_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_MASK_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+// Enable interrupt for MAINTENANCE_DONE
+#define APB_CMC_INT_MASK_0_MAINTENANCE_DONE_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_CMC_INT_MASK_0_MAINTENANCE_DONE_FIELD                       (_MK_MASK_CONST(0x1) << APB_CMC_INT_MASK_0_MAINTENANCE_DONE_SHIFT)
+#define APB_CMC_INT_MASK_0_MAINTENANCE_DONE_RANGE                       0:0
+#define APB_CMC_INT_MASK_0_MAINTENANCE_DONE_WOFFSET                     0x0
+#define APB_CMC_INT_MASK_0_MAINTENANCE_DONE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_MASK_0_MAINTENANCE_DONE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_MASK_0_MAINTENANCE_DONE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_MASK_0_MAINTENANCE_DONE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_INT_CLEAR_0  
+#define APB_CMC_INT_CLEAR_0                     _MK_ADDR_CONST(0x60)
+#define APB_CMC_INT_CLEAR_0_WORD_COUNT                  0x1
+#define APB_CMC_INT_CLEAR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_CLEAR_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_CLEAR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_CLEAR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_CLEAR_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_CLEAR_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
+// Clear both RAW_EVEVNT and INT_STATUS
+#define APB_CMC_INT_CLEAR_0_MAINTENANCE_DONE_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_CMC_INT_CLEAR_0_MAINTENANCE_DONE_FIELD                      (_MK_MASK_CONST(0x1) << APB_CMC_INT_CLEAR_0_MAINTENANCE_DONE_SHIFT)
+#define APB_CMC_INT_CLEAR_0_MAINTENANCE_DONE_RANGE                      0:0
+#define APB_CMC_INT_CLEAR_0_MAINTENANCE_DONE_WOFFSET                    0x0
+#define APB_CMC_INT_CLEAR_0_MAINTENANCE_DONE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_CLEAR_0_MAINTENANCE_DONE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_CLEAR_0_MAINTENANCE_DONE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_CLEAR_0_MAINTENANCE_DONE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_INT_RAW_EVENT_0  
+#define APB_CMC_INT_RAW_EVENT_0                 _MK_ADDR_CONST(0x64)
+#define APB_CMC_INT_RAW_EVENT_0_WORD_COUNT                      0x1
+#define APB_CMC_INT_RAW_EVENT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_RAW_EVENT_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_RAW_EVENT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_RAW_EVENT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_RAW_EVENT_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_RAW_EVENT_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// Raw event for MAINTENANCE_DONE
+#define APB_CMC_INT_RAW_EVENT_0_MAINTENANCE_DONE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_CMC_INT_RAW_EVENT_0_MAINTENANCE_DONE_FIELD                  (_MK_MASK_CONST(0x1) << APB_CMC_INT_RAW_EVENT_0_MAINTENANCE_DONE_SHIFT)
+#define APB_CMC_INT_RAW_EVENT_0_MAINTENANCE_DONE_RANGE                  0:0
+#define APB_CMC_INT_RAW_EVENT_0_MAINTENANCE_DONE_WOFFSET                        0x0
+#define APB_CMC_INT_RAW_EVENT_0_MAINTENANCE_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_RAW_EVENT_0_MAINTENANCE_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_RAW_EVENT_0_MAINTENANCE_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_RAW_EVENT_0_MAINTENANCE_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_INT_STATUS_0  
+#define APB_CMC_INT_STATUS_0                    _MK_ADDR_CONST(0x68)
+#define APB_CMC_INT_STATUS_0_WORD_COUNT                         0x1
+#define APB_CMC_INT_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Interrupt status(masked) for MAINTENANCE_DONE
+#define APB_CMC_INT_STATUS_0_MAINTENANCE_DONE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_CMC_INT_STATUS_0_MAINTENANCE_DONE_FIELD                     (_MK_MASK_CONST(0x1) << APB_CMC_INT_STATUS_0_MAINTENANCE_DONE_SHIFT)
+#define APB_CMC_INT_STATUS_0_MAINTENANCE_DONE_RANGE                     0:0
+#define APB_CMC_INT_STATUS_0_MAINTENANCE_DONE_WOFFSET                   0x0
+#define APB_CMC_INT_STATUS_0_MAINTENANCE_DONE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_STATUS_0_MAINTENANCE_DONE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_CMC_INT_STATUS_0_MAINTENANCE_DONE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_CMC_INT_STATUS_0_MAINTENANCE_DONE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_CMC_CLKEN_OVERRIDE_0  
+#define APB_CMC_CLKEN_OVERRIDE_0                        _MK_ADDR_CONST(0x6c)
+#define APB_CMC_CLKEN_OVERRIDE_0_WORD_COUNT                     0x1
+#define APB_CMC_CLKEN_OVERRIDE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_CMC_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_CMC_CLKEN_OVERRIDE_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_CMC_CLKEN_OVERRIDE_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
+// Fine Grain
+#define APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_SHIFT)
+#define APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_RANGE                 0:0
+#define APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_WOFFSET                       0x0
+#define APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define APB_CMC_CLKEN_OVERRIDE_0_CMCCLK_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+
+// Fine Grain override
+#define APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_FIELD                       (_MK_MASK_CONST(0x1) << APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_SHIFT)
+#define APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_RANGE                       1:1
+#define APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_WOFFSET                     0x0
+#define APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_INIT_ENUM                   CLK_GATED
+#define APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_CLK_GATED                   _MK_ENUM_CONST(0)
+#define APB_CMC_CLKEN_OVERRIDE_0_MSLIFCLK_CLKEN_OVR_CLK_ALWAYS_ON                       _MK_ENUM_CONST(1)
+
+// Fine Grain override
+#define APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_SHIFT)
+#define APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_RANGE                        2:2
+#define APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_WOFFSET                      0x0
+#define APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define APB_CMC_CLKEN_OVERRIDE_0_DATACLK_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+
+// Fine Grain override
+#define APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_SHIFT)
+#define APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_RANGE                 3:3
+#define APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_WOFFSET                       0x0
+#define APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define APB_CMC_CLKEN_OVERRIDE_0_TAGCLK_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+
+// Fine Grain override
+#define APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_SHIFT)
+#define APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_RANGE                 4:4
+#define APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_WOFFSET                       0x0
+#define APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define APB_CMC_CLKEN_OVERRIDE_0_APBCLK_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPB_CMC_REGS(_op_) \
+_op_(APB_CMC_CONFIG_0) \
+_op_(APB_CMC_LOCK_0) \
+_op_(APB_CMC_SIZE_0) \
+_op_(APB_CMC_MAINT_0_0) \
+_op_(APB_CMC_MAINT_1_0) \
+_op_(APB_CMC_MAINT_1) \
+_op_(APB_CMC_MAINT_1_1) \
+_op_(APB_CMC_MAINT_1_2) \
+_op_(APB_CMC_MAINT_1_3) \
+_op_(APB_CMC_MAINT_1_4) \
+_op_(APB_CMC_MAINT_1_5) \
+_op_(APB_CMC_MAINT_1_6) \
+_op_(APB_CMC_MAINT_1_7) \
+_op_(APB_CMC_MAINT_2_0) \
+_op_(APB_CMC_LFSR_0) \
+_op_(APB_CMC_STAT_CONTROL_0) \
+_op_(APB_CMC_STAT_STATE_0) \
+_op_(APB_CMC_STAT_FILTER_0) \
+_op_(APB_CMC_STAT_CLOCK_0) \
+_op_(APB_CMC_STAT_HIT_0) \
+_op_(APB_CMC_STAT_MISS_ALLOC_0) \
+_op_(APB_CMC_STAT_MISS_NO_ALLOC_0) \
+_op_(APB_CMC_STAT_MISS_EVICT_0) \
+_op_(APB_CMC_STAT_ADDR_HAZARD_0) \
+_op_(APB_CMC_INT_MASK_0) \
+_op_(APB_CMC_INT_CLEAR_0) \
+_op_(APB_CMC_INT_RAW_EVENT_0) \
+_op_(APB_CMC_INT_STATUS_0) \
+_op_(APB_CMC_CLKEN_OVERRIDE_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APB_CMC    0x00000000
+
+//
+// ARAPB_CMC REGISTER BANKS
+//
+
+#define APB_CMC0_FIRST_REG 0x0000 // APB_CMC_CONFIG_0
+#define APB_CMC0_LAST_REG 0x006c // APB_CMC_CLKEN_OVERRIDE_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPB_CMC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arapb_misc.h b/arch/arm/mach-tegra/nv/include/ap15/arapb_misc.h
new file mode 100644
index 000000000000..f108944eb63d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arapb_misc.h
@@ -0,0 +1,12572 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPB_MISC_H_INC_
+#define ___ARAPB_MISC_H_INC_
+
+// Reserved address 0 [0x0] 
+
+// Reserved address 4 [0x4] 
+
+// Register APB_MISC_PP_STRAPPING_OPT_A_0  
+#define APB_MISC_PP_STRAPPING_OPT_A_0                   _MK_ADDR_CONST(0x8)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_WORD_COUNT                        0x1
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_MASK                        _MK_MASK_CONST(0x101)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_READ_MASK                         _MK_MASK_CONST(0x1c001f1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_WRITE_MASK                        _MK_MASK_CONST(0x1c001f1)
+// read at power-on reset time from hsmmc_wp strap pad
+// note that BOOT_SRC is only valid in pre-production mode
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_RANGE                  24:24
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_WOFFSET                        0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_IROM                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_NOR                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_ENABLE                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DISABLED                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_ENABLED                        _MK_ENUM_CONST(1)
+
+// read at power-on reset time from {nand_cle,nand_ale} strap pads 00=Serial_JTAG, 01=CPU_only, 10=COP_only, 11=Serial_JTAG(same as 00 case)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT                    _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_RANGE                    23:22
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_WOFFSET                  0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_CPU                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_COP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL_ALT                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RANGE                   8:8
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_INIT_ENUM                       IS16BIT
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_IS16BIT                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_IS32BIT                 _MK_ENUM_CONST(1)
+
+// read at power-on reset time from nand_d[3:0] strap pads
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_FIELD                    (_MK_MASK_CONST(0xf) << APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_RANGE                    7:4
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_WOFFSET                  0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RANGE                   0:0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_INIT_ENUM                       IS16BIT
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_IS16BIT                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_IS8BIT                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 12 [0xc] 
+
+// Reserved address 16 [0x10] 
+
+// Register APB_MISC_PP_TRISTATE_REG_A_0  
+#define APB_MISC_PP_TRISTATE_REG_A_0                    _MK_ADDR_CONST(0x14)
+#define APB_MISC_PP_TRISTATE_REG_A_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_VAL                  _MK_MASK_CONST(0x11bffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_MASK                         _MK_MASK_CONST(0xfffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_READ_MASK                  _MK_MASK_CONST(0xfffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_RANGE                       26:26
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT                 _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_RANGE                 25:25
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_WOFFSET                       0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_TRISTATE                      _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_RANGE                        24:24
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_RANGE                        23:23
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_RANGE                       22:22
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_RANGE                       21:21
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_RANGE                       20:20
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_RANGE                       19:19
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_RANGE                       18:18
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_RANGE                        17:17
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_RANGE                        16:16
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_RANGE                        15:15
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_RANGE                        14:14
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_RANGE                        13:13
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_RANGE                        12:12
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_RANGE                        11:11
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_RANGE                       9:9
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_RANGE                       8:8
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_RANGE                       7:7
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_RANGE                       6:6
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_RANGE                      5:5
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_RANGE                      4:4
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_RANGE                        3:3
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_B_0  
+#define APB_MISC_PP_TRISTATE_REG_B_0                    _MK_ADDR_CONST(0x18)
+#define APB_MISC_PP_TRISTATE_REG_B_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_VAL                  _MK_MASK_CONST(0x2ffffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_MASK                         _MK_MASK_CONST(0x3effffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_READ_MASK                  _MK_MASK_CONST(0x3effffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_WRITE_MASK                         _MK_MASK_CONST(0x3effffff)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_RANGE                       29:29
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2S_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_RANGE                       28:28
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2C_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_XM2A_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_RANGE                       26:26
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_RANGE                        25:25
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_RANGE                        23:23
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_RANGE                        22:22
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_RANGE                        21:21
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_RANGE                        20:20
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_RANGE                        19:19
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_RANGE                        18:18
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_RANGE                       17:17
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_RANGE                       16:16
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_RANGE                       15:15
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_RANGE                       13:13
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_RANGE                       12:12
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_RANGE                       9:9
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_RANGE                       8:8
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_RANGE                       7:7
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_RANGE                       6:6
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_RANGE                       5:5
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_RANGE                       4:4
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_RANGE                       3:3
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDB_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_C_0  
+#define APB_MISC_PP_TRISTATE_REG_C_0                    _MK_ADDR_CONST(0x1c)
+#define APB_MISC_PP_TRISTATE_REG_C_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_VAL                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT                       _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_RANGE                       31:31
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_RANGE                        30:30
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_RANGE                       29:29
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_RANGE                       28:28
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_RANGE                        26:26
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_RANGE                        25:25
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_RANGE                        24:24
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_RANGE                      23:23
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_RANGE                       22:22
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_RANGE                       21:21
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_RANGE                       20:20
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_RANGE                       19:19
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_RANGE                       18:18
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_RANGE                       17:17
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_RANGE                       16:16
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_RANGE                       15:15
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_RANGE                       13:13
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_RANGE                       12:12
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_RANGE                        9:9
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_RANGE                        8:8
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_RANGE                        7:7
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_RANGE                        6:6
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_RANGE                        5:5
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_RANGE                        4:4
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_RANGE                        3:3
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_D_0  
+#define APB_MISC_PP_TRISTATE_REG_D_0                    _MK_ADDR_CONST(0x20)
+#define APB_MISC_PP_TRISTATE_REG_D_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_VAL                  _MK_MASK_CONST(0x11ff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_MASK                         _MK_MASK_CONST(0x1dff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_READ_MASK                  _MK_MASK_CONST(0x1dff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_WRITE_MASK                         _MK_MASK_CONST(0x1dff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_RANGE                        12:12
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_RANGE                        8:8
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_RANGE                        7:7
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_RANGE                        6:6
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_RANGE                       5:5
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_RANGE                       4:4
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_RANGE                       3:3
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_RANGE                       2:2
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_RANGE                       1:1
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_RANGE                       0:0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_TRISTATE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_CONFIG_CTL_0  
+#define APB_MISC_PP_CONFIG_CTL_0                        _MK_ADDR_CONST(0x24)
+#define APB_MISC_PP_CONFIG_CTL_0_WORD_COUNT                     0x1
+#define APB_MISC_PP_CONFIG_CTL_0_RESET_VAL                      _MK_MASK_CONST(0x40)
+#define APB_MISC_PP_CONFIG_CTL_0_RESET_MASK                     _MK_MASK_CONST(0xc0)
+#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_READ_MASK                      _MK_MASK_CONST(0xc0)
+#define APB_MISC_PP_CONFIG_CTL_0_WRITE_MASK                     _MK_MASK_CONST(0xc0)
+//  0 = Disable ; 1 = Enable RTCK Daisychaining
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_RANGE                      7:7
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_WOFFSET                    0x0
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_INIT_ENUM                  DISABLE
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_ENABLE                     _MK_ENUM_CONST(1)
+
+//  0 = Disable Debug ; 1 = Enable JTAG DBGEN
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_RANGE                     6:6
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_WOFFSET                   0x0
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_INIT_ENUM                 ENABLE
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_MISC_USB_OTG_0  
+#define APB_MISC_PP_MISC_USB_OTG_0                      _MK_ADDR_CONST(0x28)
+#define APB_MISC_PP_MISC_USB_OTG_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_MISC_USB_OTG_0_RESET_VAL                    _MK_MASK_CONST(0x1000)
+#define APB_MISC_PP_MISC_USB_OTG_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_USB_OTG_0_WRITE_MASK                   _MK_MASK_CONST(0xfc7fff29)
+// Wake on Disconnect Enable (device mode)
+// When enabled (1), USB PHY will wakeup
+// from suspend on a disconnect event.
+// Software should only set this bit when
+// the USB PHY is suspended (bit 2 -
+// SUSPENDED = 1).
+// Also, software should clear it after
+// detecting a wakeup event.
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_RANGE                      31:31
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Wake on Connect Enable (device mode)
+// When enabled (1), USB PHY will wakeup
+// from suspend on a connect event.
+// Software should only set this bit when
+// the USB PHY is suspended (bit 2 -
+// SUSPENDED = 1).
+// Also, software should clear it after
+// detecting a wakeup event.
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_RANGE                        30:30
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Debug bus select for USB 
+// Software should not change this.
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_RANGE                  29:26
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_USB_DEBUG_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// B_SESS_END status from USB PHY.
+// This field is the same as the field
+// B_SESS_END_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_RANGE                        25:25
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SET                  _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status from USB PHY.
+// This field is the same as the field
+// A_VBUS_VLD_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_RANGE                        24:24
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SET                  _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status from USB PHY.
+// This field is the same as the field
+// A_SESS_VLD_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_RANGE                        23:23
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SET                  _MK_ENUM_CONST(1)
+
+// Software_B_SESS_END status.
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This field is the same as the field
+// B_SESS_END_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_RANGE                  22:22
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled B_SESS_END.
+// Software sets this bit to drive the
+// value in  SW_B_SESS_END to the USB
+// controller.
+// This field is the same as the field
+// B_SESS_END_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_RANGE                       21:21
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Software_A_VBUS_VLD status.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This field is the same as the field
+// A_VBUS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_RANGE                  20:20
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in SW_A_VBUS_VLD to the USB
+// controller.
+// This field is the same as the field
+// A_VBUS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_RANGE                       19:19
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Software_A_SESS_VLD status.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This field is the same as the field
+// A_SESS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_RANGE                  18:18
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in SW_A_SESS_VLD to the USB
+// controller.
+// This field is the same as the field
+// A_SESS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_RANGE                       17:17
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Suspend Set
+// Software must write a 1 to this bit to put the USB PHY in
+// suspend mode. Software should do this only after making sure that
+// the USB is indeed in suspend mode. Setting this bit will stop the
+// PHY clock. Software should write a 0 to clear it.
+// NOTE: It is required that software generate a positive pulse on this
+// bit to guarantee proper operation.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_RANGE                       16:16
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SET                 _MK_ENUM_CONST(1)
+
+// VBUS Change Interrupt Enable
+// If set, an interrupt will be generated whenever
+// A_SESS_VLD changes value. Software can read the
+// value of A_SESS_VLD from A_SESS_VLD_STS2 bit.
+// This field is the same as the field
+// A_SESS_VLD_INT_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_RANGE                        15:15
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Software controlled OTG_ID.
+// If SW_OTG_ID_EN = 1, then software needs to monitor
+// actual OTG_ID bit used  as a GPIO and based on the value of OTG_ID,
+// it can set this bit.
+// This field is the same as the field
+// ID_SW_VALUE in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_RANGE                      14:14
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SET                        _MK_ENUM_CONST(1)
+
+// Reserved
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_RANGE                 13:13
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// ID pullup enable.
+// This field controls the internal pull-up to
+// OTG_ID pin. Software should set this to
+// 1 if using internal OTG_ID. If software
+// is using a GPIO for OTG_ID, then it
+// can write this to 0.
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_RANGE                  12:12
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_ENABLE                 _MK_ENUM_CONST(1)
+
+//Suspend Clear
+// Software must write a 1 to this bit to bring the PHY
+// out of suspend mode. This is used when the software stops the PHY
+// clock during suspend and then wants to initiate a resume. Software
+// should also write 0 to clear it.
+// NOTE: It is required that software generate a  positive pulse on this
+// bit to guarantee proper operation.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_RANGE                       11:11
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SET                 _MK_ENUM_CONST(1)
+
+// Wake/resume on VBUS change change detect
+// If enabled, the USB PHY will wake up whenever a
+// change in A_SESS_VLD is detected.
+// This should be set only when USB PHY is already
+// suspended.
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_RANGE                   10:10
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_ENABLE                  _MK_ENUM_CONST(1)
+
+// Resume/Clock valid interrupt enable
+// If this bit is enabled, interrupt is generated
+// whenever PHY clock becomes valid.
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_RANGE                 9:9
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_ENABLE                        _MK_ENUM_CONST(1)
+
+// Wake on resume enable
+// If this bit is enabled, USB PHY will wakeup from
+// suspend whenever resume/reset signaling is
+// detected on USB.
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_RANGE                      8:8
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// PHY clock valid status
+// This bit is set whenever PHY clock becomes valid.
+// It is cleared whenever PHY clock stops.
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_RANGE                        7:7
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SET                  _MK_ENUM_CONST(1)
+
+// VBUS change detect
+// This bit is set whenever a change in A_SESS_VLD
+// is detected.
+// Software can read the status of A_SESS_VLD from 
+// A_SESS_VLD_STS2 bit.
+// This field is the same as the field
+// A_SESS_VLD_CHG_DET in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT                   _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_RANGE                   6:6
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SET                     _MK_ENUM_CONST(1)
+
+// Loopback enable
+// Not for normal software use
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_RANGE                        5:5
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Real OTG_ID status from the USB PHY.
+// This field is the same as the field
+// ID_STS in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_RANGE                 4:4
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SET                   _MK_ENUM_CONST(1)
+
+// Enable Software Controlled OTG_ID
+// If using a GPIO for OTG_ID signal, then
+// software can set this to 1 and write
+// the value from the GPIO to the
+// SW_OTG_ID bit in this register.
+// This field is the same as the field
+// ID_SW_EN in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_RANGE                   3:3
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// USB PHY suspend status
+// This bit is set to 1 whenver USB is suspended and the PHY clock isnt  available.
+// NOTE: Software should not access any
+// registers in USB controller when this
+// bit is set.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_RANGE                      2:2
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SET                        _MK_ENUM_CONST(1)
+
+// Static General purpose input coming from ID pin
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_RANGE                      1:1
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SET                        _MK_ENUM_CONST(1)
+
+// Polarity of the suspend signal going to USB PHY
+// Software should not change this.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_RANGE                        0:0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_LOW                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_HIGH                  _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_XMB_CSR_0  
+#define APB_MISC_PP_XMB_CSR_0                   _MK_ADDR_CONST(0x30)
+#define APB_MISC_PP_XMB_CSR_0_WORD_COUNT                        0x1
+#define APB_MISC_PP_XMB_CSR_0_RESET_VAL                         _MK_MASK_CONST(0x58007410)
+#define APB_MISC_PP_XMB_CSR_0_RESET_MASK                        _MK_MASK_CONST(0xde04ffff)
+#define APB_MISC_PP_XMB_CSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_READ_MASK                         _MK_MASK_CONST(0xde04ffff)
+#define APB_MISC_PP_XMB_CSR_0_WRITE_MASK                        _MK_MASK_CONST(0x5004ffff)
+// External ROM Busy indicator.
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_RANGE                        31:31
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_ROM_IORDY_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0 = Write Protected (def)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_ROM_WE_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_RANGE                      30:30
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_ROM_WE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 0 = Strobe edge
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_RANGE                       28:28
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_DQM_MASK_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0 = Buffer not empty 1 = Buffer empty (default) (RO  register)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SHIFT                  _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_RANGE                  27:27
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_WOFFSET                        0x0
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_MT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 = Buffer Not full (default) 1 = Buffer Full (RO  register)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_RANGE                        26:26
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_AHB_BUF_FULL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0 = Buffer empty (default) 1 = Buffer full (RO  register)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SHIFT                 _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_RANGE                 25:25
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_WOFFSET                       0x0
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_DC_BUF_FULL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 0 = don't mask mio_rdy 1 = mask mio_rdy
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_RANGE                        18:18
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_MASK_MIO_RDY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SHIFT                   _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_RANGE                   15:12
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_DEFAULT                 _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_XMEM1                   _MK_ENUM_CONST(5)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_D_MIO1                    _MK_ENUM_CONST(7)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_RANGE                   11:8
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_DEFAULT                 _MK_MASK_CONST(0x4)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_XMEM0                   _MK_ENUM_CONST(4)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_C_MIO1                    _MK_ENUM_CONST(7)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_RANGE                   7:4
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_B_MIO1                    _MK_ENUM_CONST(7)
+
+//  1XXX = Reserved
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SHIFT)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_RANGE                   3:0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_ROM0                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_ROM1                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_MIO0                    _MK_ENUM_CONST(6)
+#define APB_MISC_PP_XMB_CSR_0_XMB_CSN_A_MIO1                    _MK_ENUM_CONST(7)
+
+
+// Register APB_MISC_PP_XMB_NOR_FLASH_CFG_0  
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0                 _MK_ADDR_CONST(0x34)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_WORD_COUNT                      0x1
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_RESET_VAL                       _MK_MASK_CONST(0x1f1f)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_RESET_MASK                      _MK_MASK_CONST(0xc3ff3f3f)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_READ_MASK                       _MK_MASK_CONST(0xc3ff3f3f)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_WRITE_MASK                      _MK_MASK_CONST(0xc3ff3f3f)
+// writing 1 clears nor_muxerr interrupt
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_RANGE                        31:31
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_CLR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0 = mask interrupt 1 = don't mask interrupt
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_RANGE                       30:30
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MUXERR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// NOR minimum transaction time
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_FIELD                        (_MK_MASK_CONST(0x3ff) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_RANGE                        25:16
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_WOFFSET                      0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_NOR_MIN_TRANS_TIME_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// ROM Wait cycles after Write. (in SCLK)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_RANGE                  13:12
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_WOFFSET                        0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_DEAD_TIME_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// ROM Write time (in number of SCLK cycles)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_RANGE                       11:8
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_WR_TIME_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// ROM Wait cycles after Read (in SCLK)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_RANGE                  5:4
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_WOFFSET                        0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_DEAD_TIME_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// ROM Read time (in number of SCLK cycles)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_RANGE                       3:0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_WOFFSET                     0x0
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_NOR_FLASH_CFG_0_ROM_RD_TIME_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Reserved address 56 [0x38] 
+
+// Register APB_MISC_PP_XMB_MIO_CFG_0  
+#define APB_MISC_PP_XMB_MIO_CFG_0                       _MK_ADDR_CONST(0x40)
+#define APB_MISC_PP_XMB_MIO_CFG_0_WORD_COUNT                    0x1
+#define APB_MISC_PP_XMB_MIO_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x1f1f1f1f)
+#define APB_MISC_PP_XMB_MIO_CFG_0_RESET_MASK                    _MK_MASK_CONST(0x7f7f7f7f)
+#define APB_MISC_PP_XMB_MIO_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_READ_MASK                     _MK_MASK_CONST(0x7f7f7f7f)
+#define APB_MISC_PP_XMB_MIO_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x7f7f7f7f)
+// end of a write access and goes low for the start  of another read or write access.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_RANGE                      30:28
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// signal is set low for MIO1. This period extends  beyond the programmed period as long as MIO_RDY signal remains low. MIO_RDY  is connected to a slave wait pin, both active low. As long as this signal is  low, PP5003 maintains all the MIO signals stable, as it waits for the slave  to complete the access. Request is removed after signal goes high.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SHIFT                   _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_RANGE                   27:24
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_WR_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// start of the following access for MIO1. (The chip  select goes high at the end of a read access and goes low at the start of a  read or write access.)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_RANGE                      22:20
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// signal is set low for MIO1. This period extends  beyond the programmed period as long as MIO_RDY signal remains low. MIO_RDY  is connected to a slave wait pin, both active low. As long as this signal is  low, PP5003 maintains all the MIO signals
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SHIFT                   _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_RANGE                   19:16
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_B_RD_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// the start of the following access (write or read)  for MIO0 . Chip select goes high at the end of a write access and goes low  for the start of another read or write access.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_RANGE                      14:12
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// during a write access for MIO0. This period  extends as long as the MIO_RDY signal remains low.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_RANGE                   11:8
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_WR_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// start of the following access for MIO0. (The chip  select goes high at the end of a read access and goes low at the start of a  read or write access.)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_RANGE                      6:4
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_WOFFSET                    0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_DEAD_TIME_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// MIO RDY Indicator. This signal indicates if the  MIO is ready. This also implies that the MIO is not busy with the present  request. The firmware can poll for this to get device status.
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SHIFT)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_RANGE                   3:0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_WOFFSET                 0x0
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_XMB_MIO_CFG_0_MIO_A_RD_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 68 [0x44] 
+
+// Register APB_MISC_PP_USB_PHY_VCTL_REG_0  
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0                  _MK_ADDR_CONST(0x60)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_RESET_VAL                        _MK_MASK_CONST(0x100020)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_RESET_MASK                       _MK_MASK_CONST(0x10ff3f)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_READ_MASK                        _MK_MASK_CONST(0x10ff3f)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_WRITE_MASK                       _MK_MASK_CONST(0x10003f)
+// Unused
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_RANGE                  20:20
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_MHZ_24                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_CLK12_SEL_MHZ_12                 _MK_ENUM_CONST(1)
+
+// Vendor status from PHY. Read only
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_RANGE                    15:8
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VSTATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Default: 1
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_RANGE                      5:5
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VLOAD_SET                        _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_FIELD                   (_MK_MASK_CONST(0x1f) << APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SHIFT)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_RANGE                   4:0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VCTL_REG_0_VCONTROL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_USB_PHY_PARAM_0  
+#define APB_MISC_PP_USB_PHY_PARAM_0                     _MK_ADDR_CONST(0x64)
+#define APB_MISC_PP_USB_PHY_PARAM_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_MASK                  _MK_MASK_CONST(0x3ff9)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_READ_MASK                   _MK_MASK_CONST(0x3ff9)
+#define APB_MISC_PP_USB_PHY_PARAM_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff9)
+// Lower 32-bits select.
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SHIFT                     _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_RANGE                     13:13
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_UPPER_BITS                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_LOW32BITS_SEL_LOWER_BITS                        _MK_ENUM_CONST(1)
+
+// Enable reception of test packets
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_RANGE                  12:12
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RCV_TEST_PKT_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable transmission of test packets
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SHIFT                 _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_RANGE                 11:11
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_PKT_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable TEST_J transmission
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_RANGE                   10:10
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_K_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable TEST_K transmission
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_RANGE                   9:9
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SEND_TEST_J_ENABLE                  _MK_ENUM_CONST(1)
+
+// If enabled, send SOF with EOP of J, else
+// send SOF with EOP of K
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_RANGE                    8:8
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_TEST_SOF_J_ENABLE                   _MK_ENUM_CONST(1)
+
+// Unused
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_RANGE                        7:7
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_UTMI_DEBUG_SEL_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reserved
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_RANGE                 6:6
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RSVD6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Route USB buffers to AHB interface for debug
+// Not intended for software use.
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_RANGE                        5:5
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_BUF_AHB_IF_SEL_ENABLE                       _MK_ENUM_CONST(1)
+
+// Vbus_sense control
+// Controls which VBUS sensor input is driven to the controller.
+// 00: Use VBUS_WAKEUP.
+// 01: Use A_SESS_VLD output from the PHY if the PHY clock is available.
+// Otherwise, use VBUS_WAKEUP.
+// 10: Use A_SESS_VLD output from the PHY
+// 11: Use VBUS_WAKEUP.
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_RANGE                        4:3
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_VBUS_WAKEUP                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_A_SESS_VLD_OR_VBUS_WAKEUP                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_A_SESS_VLD                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_VBUS_WAKEUP_1                        _MK_ENUM_CONST(3)
+
+// FS/LS serial interface enable
+// If enabled, use FS/LS serial interface for USB transfers.
+// This mode does not support HS transfers.
+// If disabled, use UTMI interface for USB transfers.
+// This mode supports all transfer speeds - HS/FS/LS.
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_RANGE                        0:0
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_FS_LS_SER_MODE_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0  
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0                   _MK_ADDR_CONST(0x68)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_WORD_COUNT                        0x1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RESET_MASK                        _MK_MASK_CONST(0x33f3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_READ_MASK                         _MK_MASK_CONST(0x33f3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// RX compare fail. Comparison on RX data failed.
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_RANGE                       17:17
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SET                 _MK_ENUM_CONST(1)
+
+// Rx valid/Rx validh fail: Indicates that the  Rxvalid/Rxvalidh werent generated according to protocol
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_RANGE                       16:16
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SET                 _MK_ENUM_CONST(1)
+
+// Failed packet no: Points to the failed packet no
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_FIELD                 (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_RANGE                 13:8
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Failed RX byte index: Points to the Rx byte no. in  the current packet which fails
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_FIELD                        (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_RANGE                        5:0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_USB_PHY_SELF_TEST_0  
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0                 _MK_ADDR_CONST(0x6c)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_WORD_COUNT                      0x1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_RESET_VAL                       _MK_MASK_CONST(0x10150888)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_RESET_MASK                      _MK_MASK_CONST(0x3f3ffbff)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_READ_MASK                       _MK_MASK_CONST(0x3f3ffbff)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_WRITE_MASK                      _MK_MASK_CONST(0x3f3f7bf3)
+// Default: 0x10
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_FIELD                      (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_RANGE                      29:24
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_DEFAULT                    _MK_MASK_CONST(0x10)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// default: 0x15
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_FIELD                  (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_RANGE                  21:16
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_DEFAULT                        _MK_MASK_CONST(0x15)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_IPKT_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Status of Disconnect signal from PHY
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SHIFT                    _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_RANGE                    15:15
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DISCON_SET                      _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SHIFT                    _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_RANGE                    14:14
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SOF_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_RANGE                      13:13
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DPPD_ENABLE                     _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_RANGE                      12:12
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DMPD_ENABLE                     _MK_ENUM_CONST(1)
+
+// Unused
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_RANGE                    11:11
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_DB16_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Operational Mode
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_RANGE                    9:8
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_OPMODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Suspend: Default: 1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_RANGE                      7:7
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_SUSP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Term_select
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_RANGE                      6:6
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TERM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// XCVR_select:
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_RANGE                      5:4
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_XCVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// When test is started, this status signal starts as  1 and is set to 0 if an error is detected. Can be sampled when TSTEND is  asserted.
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_RANGE                     3:3
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTPS_SET                       _MK_ENUM_CONST(1)
+
+// Goes to 1 when the test finishes. At that time,  TSTPASS is valid and indicates the tests pass/fail status
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SHIFT                    _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_RANGE                    2:2
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTEND_SET                      _MK_ENUM_CONST(1)
+
+// Sw writes a 1 to start the test. It writes a 0 to  end the test
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_RANGE                     1:1
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTON_SET                       _MK_ENUM_CONST(1)
+
+// Default: 0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SHIFT)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_RANGE                    0:0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_SELF_TEST_0_TSTENB_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_VBUS_SENSORS_0  
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0                      _MK_ADDR_CONST(0x70)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_READ_MASK                    _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WRITE_MASK                   _MK_MASK_CONST(0x39393939)
+// A_VBUS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_RANGE                   29:29
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This is only valid when A_VBUS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_RANGE                    28:28
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software enable.
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in A_VBUS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_RANGE                       27:27
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status.
+// This is set to 1 whenever A_VBUS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_RANGE                 26:26
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_VBUS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_RANGE                     25:25
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever A_VBUS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_RANGE                      24:24
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// A_SESS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_RANGE                   21:21
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This is only valid when A_SESS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_RANGE                    20:20
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software enable.
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in A_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_RANGE                       19:19
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status.
+// This is set to 1 whenever A_SESS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_RANGE                 18:18
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_SESS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_RANGE                     17:17
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// A_SESS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever A_SESS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_RANGE                      16:16
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// B_SESS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_RANGE                   13:13
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_VLD status.
+// This is only valid when B_SESS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_RANGE                    12:12
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software enable.
+// Enable Software Controlled B_SESS_VLD.
+// Software sets this bit to drive the
+// value in B_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_RANGE                       11:11
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD status.
+// This is set to 1 whenever B_SESS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_RANGE                 10:10
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_RANGE                     9:9
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_RANGE                      8:8
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// B_SESS_END debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_RANGE                   5:5
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// B_SESS_END software value
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This is only valid when B_SESS_END_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_RANGE                    4:4
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// B_SESS_END software enable.
+// Enable Software Controlled B_SESS_END
+// Software sets this bit to drive the
+// value in B_SESS_END_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_RANGE                       3:3
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_END status.
+// This is set to 1 whenever B_SESS_END sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_RANGE                 2:2
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_END change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_END.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_RANGE                     1:1
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_END interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_END_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_RANGE                      0:0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0  
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0                    _MK_ADDR_CONST(0x74)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_VAL                  _MK_MASK_CONST(0x6000000)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_MASK                         _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_READ_MASK                  _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WRITE_MASK                         _MK_MASK_CONST(0x3f393939)
+// HS Tx to Tx inter-packet delay counter.
+// Software should not change this.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_RANGE                    29:24
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT                  _MK_MASK_CONST(0x6)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// VDAT_DET debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_RANGE                   21:21
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// VDAT_DET software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the VDAT_DET status.
+// This is only valid when VDAT_DET_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_RANGE                    20:20
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// VDAT_DET software enable.
+// Enable Software Controlled VDAT_DET.
+// Software sets this bit to drive the
+// value in VDAT_DET_SW_VALUE to the USB
+// controller
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_RANGE                       19:19
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VDAT_DET status.
+// This is set to 1 whenever VDAT_DET sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_RANGE                 18:18
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SET                   _MK_ENUM_CONST(1)
+
+// VDAT_DET change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VDAT_DET.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_RANGE                     17:17
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// VDAT_DET interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever VDAT_DET_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_RANGE                      16:16
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_RANGE                        13:13
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_A                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_B                        _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the VBUS_WAKEUP status.
+// This is only valid when VBUS_WAKEUP_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_RANGE                 12:12
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SET                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP software enable.
+// Enable Software Controlled VBUS_WAKEUP.
+// Software sets this bit to drive the
+// value in VBUS_WAKEUP_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_RANGE                    11:11
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP status.
+// This is set to 1 whenever VBUS_WAKEUP sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_RANGE                      10:10
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SET                        _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VBUS_WAKEUP.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_RANGE                  9:9
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SET                    _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever VBUS_WAKEUP_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_RANGE                   8:8
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// ID debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_RANGE                 5:5
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_A                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_B                 _MK_ENUM_CONST(1)
+
+// ID software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the ID status.
+// This is only valid when ID_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_RANGE                  4:4
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SET                    _MK_ENUM_CONST(1)
+
+// ID software enable.
+// Enable Software Controlled ID.
+// Software sets this bit to drive the
+// value in ID_SW_VALUE to the USB
+// controller
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_RANGE                     3:3
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// ID status.
+// This is set to 1 whenever ID sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_RANGE                       2:2
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SET                 _MK_ENUM_CONST(1)
+
+// ID change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of ID.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_RANGE                   1:1
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SET                     _MK_ENUM_CONST(1)
+
+// ID interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever ID_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_RANGE                    0:0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0  
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0                      _MK_ADDR_CONST(0x78)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff80)
+// Reserved
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_FIELD                       (_MK_MASK_CONST(0x1ffffff) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_RANGE                       31:7
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_DEFAULT_MASK                        _MK_MASK_CONST(0x1ffffff)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RSVD31_7_SET                 _MK_ENUM_CONST(1)
+
+// Avalid alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_RANGE                     6:6
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_AVALID_ALT_SET                       _MK_ENUM_CONST(1)
+
+// Bvalid alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_RANGE                     5:5
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_BVALID_ALT_SET                       _MK_ENUM_CONST(1)
+
+// ID alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_RANGE                     4:4
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SET                       _MK_ENUM_CONST(1)
+
+// Session end alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_RANGE                   3:3
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SESS_END_ALT_SET                     _MK_ENUM_CONST(1)
+
+// Static GPI alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_RANGE                 2:2
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SET                   _MK_ENUM_CONST(1)
+
+// VBus valid alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SHIFT                 _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_RANGE                 1:1
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_VALID_ALT_SET                   _MK_ENUM_CONST(1)
+
+// Vbus wakeup alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_RANGE                        0:0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SET                  _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_MISC_SAVE_THE_DAY_0  
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0                 _MK_ADDR_CONST(0x7c)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WORD_COUNT                      0x1
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_RANGE                    31:24
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_RANGE                    23:16
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_RANGE                    15:8
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_RANGE                    7:0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_A_0  
+#define APB_MISC_PP_PIN_MUX_CTL_A_0                     _MK_ADDR_CONST(0x80)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_RANGE                        31:30
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RSVD1                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SDIO1                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RSVD2                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RSVD1                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RSVD2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RANGE                       25:24
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RSVD                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_NAND_ALT                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_RANGE                       21:20
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_NAND_ALT                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_HSMMC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_RANGE                        19:18
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_NAND_ALT                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_HSMMC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RANGE                        15:14
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_I2C                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD1                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD2                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_NAND_ALT                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_HSMMC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_RANGE                        11:8
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RSVD_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_RANGE                       7:6
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_IRDA                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SPDIF                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SFLASH                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SPI2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_UARTB                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SPI3                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_UARTA_ALT3                  _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_B_0  
+#define APB_MISC_PP_PIN_MUX_CTL_B_0                     _MK_ADDR_CONST(0x84)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_MASK                  _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_READ_MASK                   _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SPI1                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SDIO1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RANGE                       27:26
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SPI1                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RANGE                       21:20
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SDIO1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_PWM0                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_UARTC                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_UARTC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD3                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPDIF                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPDIF                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXB_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SDIO1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SLINK4B                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RANGE                     5:4
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD1                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DISPLAYA_HSYNC                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DISPLAYB_HSYNC                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD2                     _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_RANGE                        3:0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RSVD_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_C_0  
+#define APB_MISC_PP_PIN_MUX_CTL_C_0                     _MK_ADDR_CONST(0x88)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_DRAM                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SPI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2S_SEL_SPROM                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_DRAM                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SPI3                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SPI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_XM2A_SEL_SPROM                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DAP4                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DAP3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DAP2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_TWC                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SDIO1                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTA                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTB                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTA                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTB                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SDIO1                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_I2C                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLC_OUT1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_VI_SENSOR_CLK                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_RANGE                     5:4
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_OSC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_AHB_CLK                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_APB_CLK                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_PLLP_OUT4                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_RANGE                     3:2
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_OSC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLA_OUT                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLM_OUT1                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_AUDIO_SYNC                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD1                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSYS_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_D_0  
+#define APB_MISC_PP_PIN_MUX_CTL_D_0                     _MK_ADDR_CONST(0x8c)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_I2C                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_I2C                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_UARTA                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_PWM                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SDIO2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SPI3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_PWM                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_TWC                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SDIO2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SPI3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RANGE                       11:10
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SDIO2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RSVD                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SDIO2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RSVD                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_I2C                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SDIO1                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RSVD                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_I2C                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SDIO1                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_UARTA                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_GPIO_PORT_V                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_JTAG                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_DBG_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_E_0  
+#define APB_MISC_PP_PIN_MUX_CTL_E_0                     _MK_ADDR_CONST(0x90)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_I2C2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_I2C2                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_CRT                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RANGE                       27:26
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SPI3                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_RANGE                       25:24
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_CRT                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_CRT                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_CRT                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_RANGE                      5:4
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RANGE                      3:2
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RSVD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_CRT                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_F_0  
+#define APB_MISC_PP_PIN_MUX_CTL_F_0                     _MK_ADDR_CONST(0x94)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RANGE                       11:10
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RANGE                       9:8
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RANGE                       7:6
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_G_0  
+#define APB_MISC_PP_PIN_MUX_CTL_G_0                     _MK_ADDR_CONST(0x98)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_MASK                  _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_READ_MASK                   _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_I2C2                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RTCK                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD1                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD3                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SDIO1                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_I2C2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_HDMI                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RSVD1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RSVD2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_RANGE                        21:20
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RSVD_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_ON                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_INTR                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SPI1                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SPI1                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_I2C2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_I2C2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_CRT                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RANGE                      5:4
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SPI1                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RANGE                      3:2
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD_ALT                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_H_0  
+#define APB_MISC_PP_PIN_MUX_CTL_H_0                     _MK_ADDR_CONST(0x9c)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_FIELD                        (_MK_MASK_CONST(0x3ff) << APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_RANGE                        31:22
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_DEFAULT_MASK                 _MK_MASK_CONST(0x3ff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RSVD_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT                     _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_RANGE                     21:21
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_RANGE                     20:20
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT                     _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_RANGE                     19:19
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_RANGE                     18:18
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RANGE                 11:9
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD                  _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RANGE                 8:6
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RANGE                 5:3
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RANGE                 2:0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_A_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0                  _MK_ADDR_CONST(0xa0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_VAL                        _MK_MASK_CONST(0x215556aa)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RANGE                  27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RANGE                  25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RANGE                  23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RANGE                  19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RANGE                  9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RANGE                  7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RANGE                  3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RANGE                  1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_B_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0                  _MK_ADDR_CONST(0xa4)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_VAL                        _MK_MASK_CONST(0x6a8aaaaa)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RANGE                 31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RANGE                 29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RANGE                 27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RANGE                 23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RANGE                 19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RANGE                 3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RANGE                   1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_C_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0                  _MK_ADDR_CONST(0xa8)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_VAL                        _MK_MASK_CONST(0xaa6655)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_RANGE                 31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2S_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RANGE                 29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RANGE                 27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2A_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RANGE                 23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT                 _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RANGE                 21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RANGE                 19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RANGE                 5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RANGE                        3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_INIT_ENUM                    PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RANGE                        1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_INIT_ENUM                    PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_D_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0                  _MK_ADDR_CONST(0xac)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_VAL                        _MK_MASK_CONST(0xa8a55a8a)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_RANGE                  27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+// LC_P? for : lcd_pclk, lcd_de, lcd_hsycn, lcd_vsync, lcd_m0, lcd_m1, lcd_vp0, hdmi_int
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+// LS_P? for : lcd_sdin, lcd_sdout, lcd_wr_, lcd_cs0, lcd_dc0, lcd_sck, lcd_pwr0, lcd_pwr1, lcd_pwr2
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RANGE                   23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT                   _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RANGE                   21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RANGE                      19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RANGE                      17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RANGE                      15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RANGE                       13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_WOFFSET                     0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_INIT_ENUM                   PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_DOWN                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_UP                     _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RANGE                  11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RANGE                  9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RANGE                  7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RANGE                  3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RANGE                  1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_E_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0                  _MK_ADDR_CONST(0xb0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_VAL                        _MK_MASK_CONST(0xa)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_FIELD                     (_MK_MASK_CONST(0xffffff) << APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_RANGE                     31:8
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_WOFFSET                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_DEFAULT_MASK                      _MK_MASK_CONST(0xffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RSVD_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RANGE                 5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RANGE                 3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RANGE                 1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_ASYNC_COREPWRCONFIG_0  
+#define APB_MISC_ASYNC_COREPWRCONFIG_0                  _MK_ADDR_CONST(0x400)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_WORD_COUNT                       0x1
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_READ_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
+// Power is on in TDA/TDB partitions
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_RANGE                      0:0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_INIT_ENUM                  DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Power is on in VE/MPE partitions
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_RANGE                      1:1
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_INIT_ENUM                  DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Power is on in CPU partition
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_RANGE                     2:2
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_INIT_ENUM                 DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 1028 [0x404] 
+
+// Register APB_MISC_ASYNC_DLYCTRL_0  
+#define APB_MISC_ASYNC_DLYCTRL_0                        _MK_ADDR_CONST(0x408)
+#define APB_MISC_ASYNC_DLYCTRL_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_DLYCTRL_0_RESET_VAL                      _MK_MASK_CONST(0x8)
+#define APB_MISC_ASYNC_DLYCTRL_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_DLYCTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_DLYCTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_DLYCTRL_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_DLYCTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
+// Delay on RDY output.  
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SHIFT)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_RANGE                  4:0
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_DEFAULT                        _MK_MASK_CONST(0x8)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_DLYCTRL_0_RDY_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_CLKMNTREN_0  
+#define APB_MISC_ASYNC_CLKMNTREN_0                      _MK_ADDR_CONST(0x40c)
+#define APB_MISC_ASYNC_CLKMNTREN_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_CLKMNTREN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_CLKMNTREN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_CLKMNTREN_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+// clock monitor enable
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SHIFT)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_RANGE                 0:0
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_CLKMNTREN_0_CLK_MONITOR_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_EMCPADEN_0  
+#define APB_MISC_ASYNC_EMCPADEN_0                       _MK_ADDR_CONST(0x410)
+#define APB_MISC_ASYNC_EMCPADEN_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_EMCPADEN_0_RESET_VAL                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+// outputs enable for EMC pads
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_RANGE                       0:0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// inputs enable for EMC pads
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_RANGE                        1:1
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_WOFFSET                      0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_EMCPADCTRL_0  
+#define APB_MISC_ASYNC_EMCPADCTRL_0                     _MK_ADDR_CONST(0x414)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_EMCPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xff0f1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0x1ff3f3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0x1ff3f3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x1ff3f3)
+// EMC 3.3V mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_RANGE                    0:0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_WOFFSET                  0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_33V_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// EMC vref enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_RANGE                   1:1
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_VREF_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// EMC data pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_RANGE                       4:4
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// EMC data pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_RANGE                       5:5
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// EMC control pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_RANGE                      6:6
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// EMC control pins high speed mode enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_RANGE                      7:7
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// EMC data pins schmidt enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_RANGE                     8:8
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// EMC data pins schmidt enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_RANGE                     9:9
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// EMC data pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_RANGE                 13:12
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// EMC data pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_RANGE                 15:14
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// EMC control pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_RANGE                        17:16
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM0_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// EMC control pins low power mode select
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_RANGE                        19:18
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM1_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// EMC pull-down enable
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SHIFT)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_RANGE                     20:20
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_WOFFSET                   0x0
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADCTRL_0_MEM_PULLD_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_MEMPADCAL1_0  
+#define APB_MISC_ASYNC_MEMPADCAL1_0                     _MK_ADDR_CONST(0x418)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_MEMPADCAL1_0_RESET_VAL                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_RESET_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_READ_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_WRITE_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_RANGE                 4:0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_RANGE                    6:5
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_WOFFSET                  0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_RANGE                 12:8
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_WOFFSET                       0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SHIFT                    _MK_SHIFT_CONST(13)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_RANGE                    14:13
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_WOFFSET                  0x0
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_MEMPADCAL1_0_MEM_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_LCDPADCTRL_0  
+#define APB_MISC_ASYNC_LCDPADCTRL_0                     _MK_ADDR_CONST(0x41c)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_LCDPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xff0f1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xff5f1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xff5f1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xff5f1)
+// LCD 3.3V mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_RANGE                    0:0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_WOFFSET                  0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_33V_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// LCD data pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_RANGE                       4:4
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCD data pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_RANGE                       5:5
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCD control pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_RANGE                      6:6
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// LCD control pins high speed mode enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_RANGE                      7:7
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_HSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// LCD data pins schmidt enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_RANGE                      8:8
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_DAT_SCHMT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// LCD control pins schmidt enable
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_RANGE                     10:10
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD_CTRL_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCD data pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_RANGE                 13:12
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// LCD data pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_RANGE                 15:14
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_DAT_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// LCD control pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_RANGE                        17:16
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD0_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// LCD control pins low power mode select
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_RANGE                        19:18
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_WOFFSET                      0x0
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCTRL_0_LCD1_CTRL_LPMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_LCDPADCAL1_0  
+#define APB_MISC_ASYNC_LCDPADCAL1_0                     _MK_ADDR_CONST(0x420)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_LCDPADCAL1_0_RESET_VAL                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_RESET_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_READ_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_WRITE_MASK                  _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_RANGE                 4:0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_RANGE                    6:5
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_WOFFSET                  0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_RANGE                 12:8
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_WOFFSET                       0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SHIFT                    _MK_SHIFT_CONST(13)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_RANGE                    14:13
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_WOFFSET                  0x0
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_LCDPADCAL1_0_LCD_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_VIPADCTRL_0  
+#define APB_MISC_ASYNC_VIPADCTRL_0                      _MK_ADDR_CONST(0x424)
+#define APB_MISC_ASYNC_VIPADCTRL_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_VIPADCTRL_0_RESET_VAL                    _MK_MASK_CONST(0x33051)
+#define APB_MISC_ASYNC_VIPADCTRL_0_RESET_MASK                   _MK_MASK_CONST(0x33551)
+#define APB_MISC_ASYNC_VIPADCTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_READ_MASK                    _MK_MASK_CONST(0x33551)
+#define APB_MISC_ASYNC_VIPADCTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x33551)
+// VI 3.3V mode enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_RANGE                      0:0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_33V_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// VI data pins high speed mode enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_RANGE                  4:4
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_HSM_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// VI control pins high speed mode enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_RANGE                 6:6
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VI data pins schmidt enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_RANGE                        8:8
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_WOFFSET                      0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_SCHMT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// VI control pins schmidt enable
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_RANGE                       10:10
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VI data pins low power mode select
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_RANGE                    13:12
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_WOFFSET                  0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_DEFAULT                  _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_DAT_LPMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// VI control pins low power mode select
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SHIFT                   _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SHIFT)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_RANGE                   17:16
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_WOFFSET                 0x0
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCTRL_0_VI_CTRL_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_VIPADCAL1_0  
+#define APB_MISC_ASYNC_VIPADCAL1_0                      _MK_ADDR_CONST(0x428)
+#define APB_MISC_ASYNC_VIPADCAL1_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_VIPADCAL1_0_RESET_VAL                    _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_RESET_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_READ_MASK                    _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_WRITE_MASK                   _MK_MASK_CONST(0x7f7f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_FIELD                   (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_RANGE                   4:0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_DEFAULT                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_RANGE                      6:5
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_FIELD                   (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_RANGE                   12:8
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_WOFFSET                 0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_DEFAULT                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_RANGE                      14:13
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VIPADCAL1_0_VI_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_VCLKCTRL_0  
+#define APB_MISC_ASYNC_VCLKCTRL_0                       _MK_ADDR_CONST(0x42c)
+#define APB_MISC_ASYNC_VCLKCTRL_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VCLKCTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+// VCLK input enable
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_RANGE                     0:0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_WOFFSET                   0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_ENABLE                    _MK_ENUM_CONST(1)
+
+// VCLK invert enable
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_RANGE                      1:1
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Reserved address 1072 [0x430] 
+
+// Reserved address 1076 [0x434] 
+
+// Register APB_MISC_ASYNC_TVDACVHSYNCCTRL_0  
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0                        _MK_ADDR_CONST(0x438)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_RANGE                   1:0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_RANGE                   3:2
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_TVDACCNTL_0  
+#define APB_MISC_ASYNC_TVDACCNTL_0                      _MK_ADDR_CONST(0x43c)
+#define APB_MISC_ASYNC_TVDACCNTL_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_VAL                    _MK_MASK_CONST(0x83b)
+#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_MASK                   _MK_MASK_CONST(0x1effffff)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_READ_MASK                    _MK_MASK_CONST(0x1effffff)
+#define APB_MISC_ASYNC_TVDACCNTL_0_WRITE_MASK                   _MK_MASK_CONST(0x1effffff)
+// Power down everything including the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_RANGE                       0:0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_ENABLE                      _MK_ENUM_CONST(1)
+
+// Power down everything except the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT                  _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_RANGE                  1:1
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Power down everything including the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_RANGE                  2:2
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTR output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_RANGE                     3:3
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_ENABLE                    _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTG output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_RANGE                     4:4
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_ENABLE                    _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTB output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_RANGE                     5:5
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_ENABLE                    _MK_ENUM_CONST(1)
+
+// Adjust threshold voltage of comparator inside DAC
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_RANGE                    7:6
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_WOFFSET                  0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Turn bandgap averaging on/off
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_RANGE                        8:8
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_WOFFSET                      0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+// To adjust temp coeff
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_RANGE                 11:9
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT                       _MK_MASK_CONST(0x4)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Control bits for bandgap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_RANGE                  15:12
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// For debugging. Selects internal analog output to be sent out of VREF pin
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_RANGE                      18:16
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_WOFFSET                    0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Reserved for additional control
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_RANGE                       23:19
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Enable COMPOUTR output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT                   _MK_SHIFT_CONST(25)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_RANGE                   25:25
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COMPOUTG output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT                   _MK_SHIFT_CONST(26)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_RANGE                   26:26
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COMPOUTB output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT                   _MK_SHIFT_CONST(27)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_RANGE                   27:27
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Indicate load status
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_RANGE                    28:28
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_WOFFSET                  0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_UNLOADED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_LOADED                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_TVDACSTATUS_0  
+#define APB_MISC_ASYNC_TVDACSTATUS_0                    _MK_ADDR_CONST(0x440)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_WORD_COUNT                         0x1
+#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_MASK                         _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_READ_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Channel R comparator output for auto-detect
+// 0 = COMPINR > threshold
+// 1 = COMPINR < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_RANGE                 0:0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Channel G comparator output for auto-detect
+// 0 = COMPING > threshold
+// 1 = COMPING < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT                 _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_RANGE                 1:1
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Channel B comparator output for auto-detect
+// 0 = COMPINB > threshold
+// 1 = COMPINB < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_RANGE                 2:2
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_TVDACDINCONFIG_0  
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0                 _MK_ADDR_CONST(0x444)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WORD_COUNT                      0x1
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_MASK                      _MK_MASK_CONST(0xffffd37)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_READ_MASK                       _MK_MASK_CONST(0xffffd37)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WRITE_MASK                      _MK_MASK_CONST(0xffffd37)
+// Data Input FIFO threshold
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_RANGE                       2:0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// INPUT source for TVDAC
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_RANGE                        5:4
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_WOFFSET                      0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVDAC_OFF                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVO                  _MK_ENUM_CONST(1)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAY                      _MK_ENUM_CONST(2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAYB                     _MK_ENUM_CONST(3)
+
+// Override DAC DIN inputs
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_RANGE                  8:8
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// DIN override
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_FIELD                     (_MK_MASK_CONST(0x3ff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_RANGE                     19:10
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// AMPIN
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT                 _MK_SHIFT_CONST(20)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_FIELD                 (_MK_MASK_CONST(0xff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_RANGE                 27:20
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_INT_STATUS_0  // Interrupt Status
+//  This reflects status of all pending
+//  interrupts which is valid as long as
+//  the interrupt is not cleared even if the
+//  interrupt is masked. A pending interrupt
+//  can be cleared by writing a '1' to this
+//  the corresponding interrupt status bit
+//  in this register.
+//        0       rt  HGP0_INT_STATUS          // HGP0 Interrupt Status
+//                                             //  (this is cleared on write)
+//                                             //   0= interrupt not pending
+//                                             //   1= interrupt pending
+//        1       rt  HGP1_INT_STATUS          // HGP1 Interrupt Status
+//                                             //  (this is cleared on write)
+//                                             //   0= interrupt not pending
+//                                            //   1= interrupt pending
+//      2       rt  HGP2_INT_STATUS          // HGP2 Interrupt Status
+//                                          //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      4       rt  HGP4_INT_STATUS          // HGP4 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      5       rt  HGP5_INT_STATUS          // HGP5 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      6       rt  HGP6_INT_STATUS          // HGP6 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0                     _MK_ADDR_CONST(0x448)
+#define APB_MISC_ASYNC_INT_STATUS_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_INT_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// HGP7 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_RANGE                       7:7
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP8 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_RANGE                       8:8
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP9 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_RANGE                       9:9
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP10 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_RANGE                      10:10
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HGP11 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_RANGE                      11:11
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HGP12 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_RANGE                      12:12
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_INT_MASK_0  // Interrupt Mask
+// Setting bits in this register masked the
+//  corresponding interrupt but does not
+//  clear a pending interrupt and does not
+//  prevent a pending interrupt to be generated.
+//  Masking an interrupt also does not clear
+//  a pending interrupt status and does not
+//  a pending interrupt status to be generated.
+//      0       rw  HGP0_INT_MASK  i=0x0     // HGP0 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      1       rw  HGP1_INT_MASK  i=0x0     // HGP1 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      2       rw  HGP2_INT_MASK  i=0x0     // HGP2 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      4       rw  HGP4_INT_MASK  i=0x0     // HGP4 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      5       rw  HGP5_INT_MASK  i=0x0     // HGP5 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      6       rw  HGP6_INT_MASK  i=0x0     // HGP6 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0                       _MK_ADDR_CONST(0x44c)
+#define APB_MISC_ASYNC_INT_MASK_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_INT_MASK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_RESET_MASK                    _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_READ_MASK                     _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_RANGE                   7:7
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_RANGE                   8:8
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_RANGE                   9:9
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_RANGE                  10:10
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_RANGE                  11:11
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_RANGE                  12:12
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_INT_POLARITY_0  // Interrupt Polarity
+//  These bits specify whether a pending interrupt 
+//  is generated on falling edge or on rising edge 
+//  of the corresponding input signal/event.
+//        0       rw  HGP0_INT_POLARITY  i=0x0  // HGP0 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      1       rw  HGP1_INT_POLARITY  i=0x0  // HGP1 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      2       rw  HGP2_INT_POLARITY  i=0x0  // HGP2 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      4       rw  HGP4_INT_POLARITY  i=0x0  // HGP4 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      5       rw  HGP5_INT_POLARITY  i=0x0  // HGP5 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      6       rw  HGP6_INT_POLARITY  i=0x0  // HGP6 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0                   _MK_ADDR_CONST(0x450)
+#define APB_MISC_ASYNC_INT_POLARITY_0_WORD_COUNT                        0x1
+#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_MASK                        _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_READ_MASK                         _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_POLARITY_0_WRITE_MASK                        _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_RANGE                   7:7
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_RANGE                   8:8
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_RANGE                   9:9
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_RANGE                  10:10
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_RANGE                  11:11
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_RANGE                  12:12
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_INT_TYPE_SELECT_0  // Interrupt Type
+//  These bits specify whether an interrupt 
+//  is generated on an edge of a level type.
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0                        _MK_ADDR_CONST(0x454)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_MASK                     _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_READ_MASK                      _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WRITE_MASK                     _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Type   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_RANGE                    7:7
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_RANGE                    8:8
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_RANGE                    9:9
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_RANGE                   10:10
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_RANGE                   11:11
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_RANGE                   12:12
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_MODEREG_0  
+#define APB_MISC_GP_MODEREG_0                   _MK_ADDR_CONST(0x800)
+#define APB_MISC_GP_MODEREG_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_MODEREG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_READ_MASK                         _MK_MASK_CONST(0x301)
+#define APB_MISC_GP_MODEREG_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Standby pad input 1 = STANDBYN is    asserted (low  voltage),                   0 = STANDBYN is desasserted (high voltage)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_RANGE                  0:0
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_WOFFSET                        0x0
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEASSERTED                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_ASSERTED                       _MK_ENUM_CONST(1)
+
+// LP-DDR Strap option bit 0.
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_RANGE                        8:8
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_WOFFSET                      0x0
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// LP-DDR Strap option bit 1.
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_RANGE                        9:9
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_WOFFSET                      0x0
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_HIDREV_0  
+#define APB_MISC_GP_HIDREV_0                    _MK_ADDR_CONST(0x804)
+#define APB_MISC_GP_HIDREV_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_HIDREV_0_RESET_VAL                  _MK_MASK_CONST(0x21517)
+#define APB_MISC_GP_HIDREV_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
+#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
+#define APB_MISC_GP_HIDREV_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Chip ID family register. There maybe a new HIDFAM code
+// added for MG20 products, this is still being descided.
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_RANGE                       3:0
+#define APB_MISC_GP_HIDREV_0_HIDFAM_WOFFSET                     0x0
+#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT                     _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_GPU                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD                    _MK_ENUM_CONST(1)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_BR_CHIPS                    _MK_ENUM_CONST(2)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_CRUSH                       _MK_ENUM_CONST(3)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_MCP                 _MK_ENUM_CONST(4)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_CK                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_VAIO                        _MK_ENUM_CONST(6)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD_SOC                        _MK_ENUM_CONST(7)
+
+// Chip ID major revision (0: Emulation, 1-15: Silicon)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_RANGE                     7:4
+#define APB_MISC_GP_HIDREV_0_MAJORREV_WOFFSET                   0x0
+#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_EMULATION                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_A01                       _MK_ENUM_CONST(1)
+
+// Chip ID
+#define APB_MISC_GP_HIDREV_0_CHIPID_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_HIDREV_0_CHIPID_FIELD                       (_MK_MASK_CONST(0xff) << APB_MISC_GP_HIDREV_0_CHIPID_SHIFT)
+#define APB_MISC_GP_HIDREV_0_CHIPID_RANGE                       15:8
+#define APB_MISC_GP_HIDREV_0_CHIPID_WOFFSET                     0x0
+#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT                     _MK_MASK_CONST(0x15)
+#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Chip ID minor revision (IF MAJORREV==0(Emulation) THEN  0: QT, 1:E388 FPGA)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SHIFT                     _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_HIDREV_0_MINORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MINORREV_SHIFT)
+#define APB_MISC_GP_HIDREV_0_MINORREV_RANGE                     19:16
+#define APB_MISC_GP_HIDREV_0_MINORREV_WOFFSET                   0x0
+#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2056 [0x808] 
+
+// Reserved address 2060 [0x80c] 
+
+// Register APB_MISC_GP_ASDBGREG_0  
+#define APB_MISC_GP_ASDBGREG_0                  _MK_ADDR_CONST(0x810)
+#define APB_MISC_GP_ASDBGREG_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_ASDBGREG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_RESET_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
+#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_READ_MASK                        _MK_MASK_CONST(0x3ff0ffdf)
+#define APB_MISC_GP_ASDBGREG_0_WRITE_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
+// Enables iddq (WARNING: Will functionally kill chip)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_RANGE                    0:0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_WOFFSET                  0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enables pullup
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT                  _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_RANGE                  1:1
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_WOFFSET                        0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enables pulldown
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_RANGE                        2:2
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enables debug mode
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_RANGE                       3:3
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enables performance monitor mode
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_RANGE                  4:4
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_WOFFSET                        0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_RANGE                        7:6
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_RANGE                        8:8
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_RANGE                        9:9
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT                        _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_RANGE                        10:10
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_RANGE                        11:11
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_RANGE                        12:12
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_RANGE                        13:13
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_RANGE                        14:14
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+//  Obsolete previously used with host_pad_macros (jmoskal)
+//16      rw  CFG2TMC_SW_BP_WRNCLK      i=0x0
+//    enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_RANGE                      15:15
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_ENABLE                     _MK_ENUM_CONST(1)
+
+// control timing characteristics for the compiled rams
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT                   _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_RANGE                   21:20
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_WOFFSET                 0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_ENABLE                  _MK_ENUM_CONST(1)
+
+// control write timing characteristics for the compiled RAMDP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_RANGE                        23:22
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMPDP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_RANGE                       25:24
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMREG
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_RANGE                       27:26
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMSP
+// ECO 385781, add reset to RAM_SVOP_SP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_RANGE                        29:28
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_RESERVEREG_0  
+#define APB_MISC_GP_RESERVEREG_0                        _MK_ADDR_CONST(0x814)
+#define APB_MISC_GP_RESERVEREG_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_RESERVEREG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_RESERVEREG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_RESERVEREG_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_RANGE                     0:0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_RANGE                     1:1
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_RANGE                     2:2
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_RANGE                     3:3
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_RANGE                     4:4
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_RANGE                     5:5
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_RANGE                     6:6
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SHIFT                     _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_RANGE                     7:7
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_WOFFSET                   0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_FIELD                   (_MK_MASK_CONST(0xff) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_RANGE                   15:8
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_WOFFSET                 0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SHIFT                   _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_FIELD                   (_MK_MASK_CONST(0xff) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_RANGE                   23:16
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_WOFFSET                 0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SHIFT                   _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_FIELD                   (_MK_MASK_CONST(0xff) << APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SHIFT)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_RANGE                   31:24
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_WOFFSET                 0x0
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_RESERVEREG_0_ECO_RESERVE_B3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_OBSCTRL_0  
+#define APB_MISC_GP_OBSCTRL_0                   _MK_ADDR_CONST(0x818)
+#define APB_MISC_GP_OBSCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_OBSCTRL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_RESET_MASK                        _MK_MASK_CONST(0x80ffffff)
+#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_READ_MASK                         _MK_MASK_CONST(0x80ffffff)
+#define APB_MISC_GP_OBSCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0x80ffffff)
+// Module-level mux select for determining which debug signals to send out
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_FIELD                 (_MK_MASK_CONST(0xffff) << APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_RANGE                 15:0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_WOFFSET                       0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Observation module select
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_RANGE                 19:16
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_WOFFSET                       0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Observation partition select
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_RANGE                        23:20
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_WOFFSET                      0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_AO                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_CPU                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DIS                  _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_GR                   _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_MPE                  _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDA                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDB                  _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VDE                  _MK_ENUM_CONST(7)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VE                   _MK_ENUM_CONST(8)
+
+// Observation bus enable
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_RANGE                      31:31
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_WOFFSET                    0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_OBSDATA_0  
+#define APB_MISC_GP_OBSDATA_0                   _MK_ADDR_CONST(0x81c)
+#define APB_MISC_GP_OBSDATA_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_OBSDATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_OBSDATA_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Observation port data.  This should be the same data that is going out on the observation bus.
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_RANGE                    31:0
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_WOFFSET                  0x0
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEREQ_0  
+#define APB_MISC_GP_EFUSEREQ_0                  _MK_ADDR_CONST(0x820)
+#define APB_MISC_GP_EFUSEREQ_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_EFUSEREQ_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SHIFT)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_RANGE                       0:0
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_WOFFSET                     0x0
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEREQ_0_EF_RESERVED0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEOFF_0  
+#define APB_MISC_GP_EFUSEOFF_0                  _MK_ADDR_CONST(0x824)
+#define APB_MISC_GP_EFUSEOFF_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_EFUSEOFF_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SHIFT)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_RANGE                       0:0
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_WOFFSET                     0x0
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEOFF_0_EF_RESERVED1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEWRDAT_0  
+#define APB_MISC_GP_EFUSEWRDAT_0                        _MK_ADDR_CONST(0x828)
+#define APB_MISC_GP_EFUSEWRDAT_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_EFUSEWRDAT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SHIFT)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_RANGE                     0:0
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_WOFFSET                   0x0
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEWRDAT_0_EF_RESERVED2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSERDDAT_0  
+#define APB_MISC_GP_EFUSERDDAT_0                        _MK_ADDR_CONST(0x82c)
+#define APB_MISC_GP_EFUSERDDAT_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_EFUSERDDAT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SHIFT)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_RANGE                     0:0
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_WOFFSET                   0x0
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSERDDAT_0_EF_RESERVED3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEVAL1_0  
+#define APB_MISC_GP_EFUSEVAL1_0                 _MK_ADDR_CONST(0x830)
+#define APB_MISC_GP_EFUSEVAL1_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_EFUSEVAL1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SHIFT)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_RANGE                      0:0
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_WOFFSET                    0x0
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL1_0_EF_RESERVED4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEVAL2_0  
+#define APB_MISC_GP_EFUSEVAL2_0                 _MK_ADDR_CONST(0x834)
+#define APB_MISC_GP_EFUSEVAL2_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_EFUSEVAL2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SHIFT)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_RANGE                      0:0
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_WOFFSET                    0x0
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEVAL2_0_EF_RESERVED5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EFUSEBYPASSID_0  
+#define APB_MISC_GP_EFUSEBYPASSID_0                     _MK_ADDR_CONST(0x838)
+#define APB_MISC_GP_EFUSEBYPASSID_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_EFUSEBYPASSID_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SHIFT)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_RANGE                  0:0
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_WOFFSET                        0x0
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EFUSEBYPASSID_0_EF_RESERVED6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_BRDCLK_TRIM_0  
+#define APB_MISC_GP_BRDCLK_TRIM_0                       _MK_ADDR_CONST(0x83c)
+#define APB_MISC_GP_BRDCLK_TRIM_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_BRDCLK_TRIM_0_RESET_VAL                     _MK_MASK_CONST(0x4)
+#define APB_MISC_GP_BRDCLK_TRIM_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SHIFT)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_RANGE                      4:0
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_WOFFSET                    0x0
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_DEFAULT                    _MK_MASK_CONST(0x4)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_BRDCLK_TRIM_0_BRDCLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2112 [0x840] 
+
+// Reserved address 2116 [0x844] 
+
+// Reserved address 2120 [0x848] 
+
+// Reserved address 2124 [0x84c] 
+
+// Reserved address 2128 [0x850] 
+
+// Reserved address 2132 [0x854] 
+
+// Register APB_MISC_GP_ASDBGREG2_0  
+#define APB_MISC_GP_ASDBGREG2_0                 _MK_ADDR_CONST(0x858)
+#define APB_MISC_GP_ASDBGREG2_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_ASDBGREG2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_RESET_MASK                      _MK_MASK_CONST(0x7ff80)
+#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_READ_MASK                       _MK_MASK_CONST(0x7ff80)
+#define APB_MISC_GP_ASDBGREG2_0_WRITE_MASK                      _MK_MASK_CONST(0x7ff80)
+//Enable bypass of functional clock with test clock 8
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_RANGE                       7:7
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 9
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_RANGE                       8:8
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 10
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT                      _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_RANGE                      9:9
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 11
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_RANGE                      10:10
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 12
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT                      _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_RANGE                      11:11
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 13
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_RANGE                      12:12
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 14
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_RANGE                      13:13
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 15
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_RANGE                      14:14
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 16
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_RANGE                      15:15
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 17
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_RANGE                      16:16
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 18
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT                      _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_RANGE                      17:17
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of sync Already in NV_car
+//  18       rw  CFG2TMC_OSCFI_BYPASS     i=0x0  //Enable bypass of oscfi
+//            enum ( DISABLE, ENABLE )
+//  19       rw  CFG2TMC_OSCFI_EN         i=0x0  //Enable oscfi refclk
+//      enum ( DISABLE, ENABLE )
+//      enum ( DISABLE, ENABLE )
+//  25:21   rw  CFG2TMC_OSCFI_D           i=0x0  //
+//  31:26   rw  CFG2TMC_OSCFI_S           i=0x0  //
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_RANGE                        18:18
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_EMU_REVID_0  
+#define APB_MISC_GP_EMU_REVID_0                 _MK_ADDR_CONST(0x860)
+#define APB_MISC_GP_EMU_REVID_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_EMU_REVID_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_EMU_REVID_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// USED by emulators to indicate netlist #, 0 for silicon.
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_FIELD                   (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_RANGE                   15:0
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_WOFFSET                 0x0
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_INIT_ENUM                       NV_EMUL_NETLIST
+
+// USED by emulators to indicate patch #, 0 for silicon.
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT                     _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_FIELD                     (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_RANGE                     31:16
+#define APB_MISC_GP_EMU_REVID_0_PATCH_WOFFSET                   0x0
+#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_INIT_ENUM                 NV_EMUL_PATCH
+
+
+// Register APB_MISC_GP_TRANSACTOR_SCRATCH_0  
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0                        _MK_ADDR_CONST(0x864)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// used for emulation to determine test results.
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_FIELD                       (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_RANGE                       31:0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_WOFFSET                     0x0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AOCFG1PADCTRL_0  //        0       rw  CFG2TMC_AOCFG1_PULLD_EN i=0x0   // AOCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_AOCFG1_PULLU_EN i=0x0   // AOCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_AOCFG1PADCTRL_0                     _MK_ADDR_CONST(0x868)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// AOCFG1 data pins high speed mode enable
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// AOCFG1 data pins schmidt enable
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// AOCFG1 data pins low power mode select
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AOCFG2PADCTRL_0  //        0       rw  CFG2TMC_AOCFG2_PULLD_EN i=0x0   // AOCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_AOCFG2_PULLU_EN i=0x0   // AOCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_AOCFG2PADCTRL_0                     _MK_ADDR_CONST(0x86c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// AOCFG2 data pins high speed mode enable
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// AOCFG2 data pins schmidt enable
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// AOCFG2 data pins low power mode select
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_ATCFG1PADCTRL_0  //        0       rw  CFG2TMC_ATCFG1_PULLD_EN   i=0x0   // ATCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_ATCFG1_PULLU_EN   i=0x0   // ATCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ATCFG1PADCTRL_0                     _MK_ADDR_CONST(0x870)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// ATCFG1 data pins high speed mode enable
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ATCFG1 data pins schmidt enable
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// ATCFG1 data pins low power mode select
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_ATCFG2PADCTRL_0  //        0       rw  CFG2TMC_ATCFG2_PULLD_EN   i=0x0   // ATCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_ATCFG2_PULLU_EN   i=0x0   // ATCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ATCFG2PADCTRL_0                     _MK_ADDR_CONST(0x874)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// ATCFG2 data pins high speed mode enable
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ATCFG2 data pins schmidt enable
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// ATCFG2 data pins low power mode select
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CDEV1CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV1CFG_PULLD_EN   i=0x0   // CDEV1CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CDEV1CFG_PULLU_EN   i=0x0   // CDEV1CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0                   _MK_ADDR_CONST(0x878)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// CDEV1CFG data pins high speed mode enable
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CDEV1CFG data pins schmidt enable
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// CDEV1CFG data pins low power mode select
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CDEV2CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV2CFG_PULLD_EN   i=0x0   // CDEV2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CDEV2CFG_PULLU_EN   i=0x0   // CDEV2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0                   _MK_ADDR_CONST(0x87c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// CDEV2CFG data pins high speed mode enable
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CDEV2CFG data pins schmidt enable
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// CDEV2CFG data pins low power mode select
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CSUSCFGPADCTRL_0  //        0       rw  CFG2TMC_CSUSCFG_PULLD_EN   i=0x0   // CSUSCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CSUSCFG_PULLU_EN   i=0x0   // CSUSCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CSUSCFGPADCTRL_0                    _MK_ADDR_CONST(0x880)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// CSUSCFG data pins high speed mode enable
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// CSUSCFG data pins schmidt enable
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CSUSCFG data pins low power mode select
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP1CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP1CFG_PULLD_EN   i=0x0   // DAP1CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP1CFG_PULLU_EN   i=0x0   // DAP1CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP1CFGPADCTRL_0                    _MK_ADDR_CONST(0x884)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP1CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP1CFG data pins schmidt enable
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP1CFG data pins low power mode select
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP2CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP2CFG_PULLD_EN   i=0x0   // DAP2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP2CFG_PULLU_EN   i=0x0   // DAP2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP2CFGPADCTRL_0                    _MK_ADDR_CONST(0x888)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP2CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP2CFG data pins schmidt enable
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP2CFG data pins low power mode select
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP3CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP3CFG_PULLD_EN   i=0x0   // DAP3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP3CFG_PULLU_EN   i=0x0   // DAP3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP3CFGPADCTRL_0                    _MK_ADDR_CONST(0x88c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP3CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP3CFG data pins schmidt enable
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP3CFG data pins low power mode select
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP4CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP4CFG_PULLD_EN   i=0x0   // DAP4CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP4CFG_PULLU_EN   i=0x0   // DAP4CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP4CFGPADCTRL_0                    _MK_ADDR_CONST(0x890)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP4CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP4CFG data pins schmidt enable
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP4CFG data pins low power mode select
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DBGCFGPADCTRL_0  //        0       rw  CFG2TMC_DBGCFG_PULLD_EN   i=0x0   // DBGCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DBGCFG_PULLU_EN   i=0x0   // DBGCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DBGCFGPADCTRL_0                     _MK_ADDR_CONST(0x894)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// DBGCFG data pins high speed mode enable
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// DBGCFG data pins schmidt enable
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DBGCFG data pins low power mode select
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_LCDCFG1PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG1_PULLD_EN   i=0x0   // LCDCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_LCDCFG1_PULLU_EN   i=0x0   // LCDCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_LCDCFG1PADCTRL_0                    _MK_ADDR_CONST(0x898)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// LCDCFG1 data pins high speed mode enable
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCDCFG1 data pins schmidt enable
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCDCFG1 data pins low power mode select
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_RANGE                 5:4
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_LCDCFG2PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG2_PULLD_EN   i=0x0   // LCDCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_LCDCFG2_PULLU_EN   i=0x0   // LCDCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_LCDCFG2PADCTRL_0                    _MK_ADDR_CONST(0x89c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// LCDCFG2 data pins high speed mode enable
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCDCFG2 data pins schmidt enable
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCDCFG2 data pins low power mode select
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_RANGE                 5:4
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO2CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO2CFG_PULLD_EN   i=0x0   // SDIO2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO2CFG_PULLU_EN   i=0x0   // SDIO2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO2CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO2CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO2CFG data pins low power mode select
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO3CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO3CFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO3CFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a4)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SPICFGPADCTRL_0  //        0       rw  CFG2TMC_SPICFG_PULLD_EN   i=0x0   // SPICFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SPICFG_PULLU_EN   i=0x0   // SPICFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SPICFGPADCTRL_0                     _MK_ADDR_CONST(0x8a8)
+#define APB_MISC_GP_SPICFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SPICFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SPICFG data pins high speed mode enable
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SPICFG data pins schmidt enable
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SPICFG data pins low power mode select
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UAACFGPADCTRL_0  //        0       rw  CFG2TMC_UAACFG_PULLD_EN   i=0x0   // UAACFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UAACFG_PULLU_EN   i=0x0   // UAACFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UAACFGPADCTRL_0                     _MK_ADDR_CONST(0x8ac)
+#define APB_MISC_GP_UAACFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UAACFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// UAACFG data pins high speed mode enable
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// UAACFG data pins schmidt enable
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// UAACFG data pins low power mode select
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UABCFGPADCTRL_0  //        0       rw  CFG2TMC_UABCFG_PULLD_EN   i=0x0   // UABCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UABCFG_PULLU_EN   i=0x0   // UABCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UABCFGPADCTRL_0                     _MK_ADDR_CONST(0x8b0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UABCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// UABCFG data pins high speed mode enable
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// UABCFG data pins schmidt enable
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// UABCFG data pins low power mode select
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UART2CFGPADCTRL_0  //        0       rw  CFG2TMC_UART2CFG_PULLD_EN   i=0x0   // UART2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UART2CFG_PULLU_EN   i=0x0   // UART2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UART2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b4)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// UART2CFG data pins high speed mode enable
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// UART2CFG data pins schmidt enable
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// UART2CFG data pins low power mode select
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UART3CFGPADCTRL_0  //        0       rw  CFG2TMC_UART3CFG_PULLD_EN   i=0x0   // UART3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UART3CFG_PULLU_EN   i=0x0   // UART3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UART3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b8)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// UART3CFG data pins high speed mode enable
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// UART3CFG data pins schmidt enable
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// UART3CFG data pins low power mode select
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_VICFG1PADCTRL_0  //        0       rw  CFG2TMC_VICFG1_PULLD_EN   i=0x0   // VICFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_VICFG1_PULLU_EN   i=0x0   // VICFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_VICFG1PADCTRL_0                     _MK_ADDR_CONST(0x8bc)
+#define APB_MISC_GP_VICFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// VICFG1 data pins high speed mode enable
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VICFG1 data pins schmidt enable
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VICFG1 data pins low power mode select
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_VICFG2PADCTRL_0  //        0       rw  CFG2TMC_VICFG2_PULLD_EN   i=0x0   // VICFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_VICFG2_PULLU_EN   i=0x0   // VICFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_VICFG2PADCTRL_0                     _MK_ADDR_CONST(0x8c0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// VICFG2 data pins high speed mode enable
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VICFG2 data pins schmidt enable
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VICFG2 data pins low power mode select
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGAPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGA_PULLD_EN   i=0x0 // XM2CFGA pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGA_PULLU_EN i=0x0   // XM2CFGA pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGAPADCTRL_0                    _MK_ADDR_CONST(0x8c4)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f074)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f074)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f074)
+// XM2CFGA data pins high speed mode enable        3       rw  CFG2TMC_XM2CFGA_SCHMT_EN i=0x0   // XM2CFGA data pins schmidt enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// XM2CFGA data pins low power mode select
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_RANGE                 5:4
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// XM2CFGA data pins vref enable
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_RANGE                      6:6
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_WOFFSET                    0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_VREF_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGCPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGC_PULLD_EN   i=0x0   // XM2CFGC pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGC_PULLU_EN   i=0x0   // XM2CFGC pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGCPADCTRL_0                    _MK_ADDR_CONST(0x8c8)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+// XM2CFGC data pins high speed mode enable
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// XM2CFGC data pins schmidt enable
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// XM2CFGC data pins low power mode select
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_RANGE                 5:4
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// XM2CFGC data pins vref enable
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_RANGE                      6:6
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_WOFFSET                    0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_VREF_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGDPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGD_PULLD_EN   i=0x0   // XM2CFGD pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGD_PULLU_EN   i=0x0   // XM2CFGD pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGDPADCTRL_0                    _MK_ADDR_CONST(0x8cc)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f07c)
+// XM2CFGD data pins high speed mode enable
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins schmidt enable
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins low power mode select
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_RANGE                 5:4
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// XM2CFGD data pins vref enable
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_RANGE                      6:6
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_WOFFSET                    0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_VREF_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CLKCFGPADCTRL_0  //        0       rw  CFG2TMC_XM2CLKCFG_PULLD_EN   i=0x0   // XM2CLKCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CLKCFG_PULLU_EN   i=0x0   // XM2CLKCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0                  _MK_ADDR_CONST(0x8d0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_VAL                        _MK_MASK_CONST(0xf1f1f030)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_MASK                       _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_READ_MASK                        _MK_MASK_CONST(0xf1f1f07c)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xf1f1f07c)
+// XM2CLKCFG data pins high speed mode enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_RANGE                   2:2
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_HSM_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// XM2CLKCFG data pins schmidt enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_RANGE                 3:3
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_SCHMT_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// XM2CLKCFG data pins low power mode select
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_RANGE                     5:4
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_LPMD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// XM2CLKCFG data pins vref enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_RANGE                  6:6
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_VREF_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_RANGE                        16:12
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_RANGE                        24:20
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_RANGE                   29:28
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT                   _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_RANGE                   31:30
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_MEMCOMPPADCTRL_0  //        0       rw  CFG2TMC_MEM_COMP_EN_COMP    i=0x0   // compensation enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_MEMCOMPPADCTRL_0                    _MK_ADDR_CONST(0x8d4)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0x1f1f000)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0x1f1f004)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0x1f1f004)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x1f1f004)
+// high speed mode enable
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SHIFT                    _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SHIFT)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_RANGE                    2:2
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_WOFFSET                  0x0
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM_E_HSM_ENABLE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SHIFT)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SHIFT)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MEMCOMPPADCTRL_0_MEM2COMPPAD_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_PADCTL_DFT_0  
+#define APB_MISC_GP_PADCTL_DFT_0                        _MK_ADDR_CONST(0x8d8)
+#define APB_MISC_GP_PADCTL_DFT_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_PADCTL_DFT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_RESET_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_READ_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_PADCTL_DFT_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
+// Enable pin-shorting for tester mode pin-shorting
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_RANGE                      0:0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_WOFFSET                    0x0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Select which pins are used for test-mode observe
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_RANGE                     1:1
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_WOFFSET                   0x0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_PLL_CFG0_0  // USB_PHY PLL Configuration Register 0
+//
+// The data sampling frequency relies on a 960MHz clock, so the goal of the PLL is to have:
+// In_Frequency*(PLL_VCOMULTBY2+1)*(PLL_NDIV/PLL_MDIV) = 960MHz
+//
+// With a 12MHz input from PLL_U, the default setting of 
+// PLL_VCOMULTBY2=1, PLL_NDIV=40 and PLL_MDIV=1 results in a correct output.
+#define APB_MISC_UTMIP_PLL_CFG0_0                       _MK_ADDR_CONST(0xa00)
+#define APB_MISC_UTMIP_PLL_CFG0_0_WORD_COUNT                    0x1
+#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_VAL                     _MK_MASK_CONST(0x280180)
+#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_READ_MASK                     _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_WRITE_MASK                    _MK_MASK_CONST(0x7fffffff)
+// LOCK_ENABLE input of USB_PHY PLL.
+// Normally only used during test. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_RANGE                    0:0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// LOCKSEL[5:0] input of USB_PHY PLL.
+// Used in test modes only. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_FIELD                       (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_RANGE                       6:1
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_WOFFSET                     0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VCOMULTBY2 control of the UTMIP PHY PLL.
+// Recommended setting is on. Additional divide by 2 on the 
+// VCO feedback. Which is setting the bit to 1. See cell spec.
+//
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT                    _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_RANGE                    7:7
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_WOFFSET                  0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// MDIV[7:0] input of the USB_PHY PLL. This is the predivide on the PLL. 
+// 0x0 is not allowed. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_RANGE                  15:8
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// NDIV[7:0] input of USB_PHY PLL. 
+// This is the feedback divider on the VCO feedback. 
+// 0x0 is not allowed. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_RANGE                  23:16
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT                        _MK_MASK_CONST(0x28)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PDIV[2:0] input of the USB_PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_RANGE                  26:24
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PDIVRST of the UTMIP PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_RANGE                       27:27
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_WOFFSET                     0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Selects which of the eight 60MHz clock phases to produce at the output 
+// of the USB PHY PLL. This is for a test mode. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_RANGE                        30:28
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_PLL_CFG1_0  // UTMIP PLL and PLLU configuration register 1
+#define APB_MISC_UTMIP_PLL_CFG1_0                       _MK_ADDR_CONST(0xa04)
+#define APB_MISC_UTMIP_PLL_CFG1_0_WORD_COUNT                    0x1
+#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_VAL                     _MK_MASK_CONST(0x182000c0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// Determines the time to wait until the output of USB_PHY PLL is considered stable. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_FIELD                   (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_RANGE                   11:0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT                 _MK_MASK_CONST(0xc0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input off. (Overrides FORCE_PLL_ACTIVE_POWERUP.)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE                        12:12
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input on. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT                  _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE                  13:13
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input off. (Overrides FORCE_PLL_ENABLE_POWERUP.)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE                        14:14
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input on. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT                  _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE                  15:15
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power down. (Overrides FORCE_PLLU_POWERUP.)  
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_RANGE                      16:16
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power up.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_RANGE                        17:17
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// SETUP[8:0] input of USB_PHY PLL.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_FIELD                 (_MK_MASK_CONST(0x1ff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_RANGE                 26:18
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_WOFFSET                       0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT                       _MK_MASK_CONST(0x8)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Controls the wait time to enable PLL_U when coming out of suspend or reset.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE                     31:27
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_XCVR_CFG0_0  // UTMIP transceiver cell configuration register 0
+#define APB_MISC_UTMIP_XCVR_CFG0_0                      _MK_ADDR_CONST(0xa08)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x2500)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff)
+// SETUP[3:0] input of XCVR cell. HS driver output control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_RANGE                       3:0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HS slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_RANGE                      5:4
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FS slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_RANGE                      7:6
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// LS rising slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_RANGE                     9:8
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// LS falling slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_RANGE                     11:10
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Internal loopback inside XCVR cell. Used for IOBIST.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_RANGE                  12:12
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_WOFFSET                        0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Enable HS termination.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_RANGE                      13:13
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PD input into power down. (Overrides FORCE_PD_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_RANGE                       14:14
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Force PD input into power up. 
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT                 _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_RANGE                 15:15
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_WOFFSET                       0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power down. (Overrides FORCE_PD2_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_RANGE                      16:16
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_RANGE                        17:17
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power down. (Overrides FORCE_PDZI_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_RANGE                     18:18
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_RANGE                       19:19
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BIAS_CFG0_0  // UTMIP Bias cell configuration register 0
+#define APB_MISC_UTMIP_BIAS_CFG0_0                      _MK_ADDR_CONST(0xa0c)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// HS squelch detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_RANGE                  1:0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// HS disconnect detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_RANGE                   3:2
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// HS chirp detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_RANGE                    5:4
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SessionEnd detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_RANGE                 7:6
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Vbus detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_RANGE                 9:8
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Power down bias circuit.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_RANGE                   10:10
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Power down OTG circuit.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_RANGE                    11:11
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Active 1.5K pullup control offset.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT                     _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_RANGE                     14:12
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_WOFFSET                   0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Active termination control offset.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_RANGE                       17:15
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_WOFFSET                     0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0: StaticGpi = IdDig. 1: StaticGpi = GPI_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_RANGE                  18:18
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// See GPI_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT                  _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_RANGE                  19:19
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: IdDig = IdDig. 1: IdDig = IDDIG_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_RANGE                        20:20
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_WOFFSET                      0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// See IDDIG_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_RANGE                        21:21
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_WOFFSET                      0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0: IDPD = ~IdPullup. 1: IDPD = IDPD_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_RANGE                 22:22
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// See IDPD_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT                 _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_RANGE                 23:23
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_HSRX_CFG0_0  // UTMIP High speed receive config 0 
+#define APB_MISC_UTMIP_HSRX_CFG0_0                      _MK_ADDR_CONST(0xa10)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x91653400)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Require 4 sync pattern transitions (01) instead of 3
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_RANGE                    0:0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sync pattern detection needs 3 consecutive samples instead of 4
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_RANGE                   1:1
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_WOFFSET                 0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Based on incoming edges and current sampling position, adjust phase
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_RANGE                     3:2
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_WOFFSET                   0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Retime the path. 
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_RANGE                   5:4
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_WOFFSET                 0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pass through the feedback, do not block it.
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_RANGE                    6:6
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// When in Chirp Mode, allow chirp rx data through
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_RANGE                       7:7
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Do not declare underrun errors
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_RANGE                 8:8
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Do not declare overrun errors until overflow of FIFO
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_RANGE                  9:9
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Depth of elastic input store
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT                    _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_RANGE                    14:10
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT                  _MK_MASK_CONST(0xd)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of cycles of idle to declare IDLE. 
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_RANGE                        19:15
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT                      _MK_MASK_CONST(0xa)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Do not strip incoming data
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_RANGE                     20:20
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_WOFFSET                   0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Limit the delay of the squelch at EOP time
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT                  _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_RANGE                  23:21
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT                        _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// The number of (edges-1) needed to move the sampling point
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_RANGE                  27:24
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Realign the inertia counters on a new packet
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_RANGE                       28:28
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_WOFFSET                     0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Allow consecutive ups and downs on the bits, debug only, set to 0.
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_RANGE                        29:29
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Keep the stay alive pattern on active
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_RANGE                      31:30
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_WOFFSET                    0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_HSRX_CFG1_0  // UTMIP High speed receive config 1
+#define APB_MISC_UTMIP_HSRX_CFG1_0                      _MK_ADDR_CONST(0xa14)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x13)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
+// Allow Keep Alive packets 
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_RANGE                      0:0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_WOFFSET                    0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// How long to wait before start of sync launches RxActive
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_RANGE                        5:1
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT                      _MK_MASK_CONST(0x9)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_FSLSRX_CFG0_0  // UTMIP full and Low speed receive config 0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0                    _MK_ADDR_CONST(0xa18)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WORD_COUNT                         0x1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_VAL                  _MK_MASK_CONST(0xfd548429)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Give up on packet if a long sequence of J 
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_RANGE                  0:0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 20 bits of idle should end the packet if FsLsIdleCountLimitCfg=1.
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_RANGE                    6:1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT                  _MK_MASK_CONST(0x14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Enable the reset of the state machine on extended SE0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_RANGE                   7:7
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 4 bits of of SEO should exceed the time limit
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_RANGE                     13:8
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT                   _MK_MASK_CONST(0x4)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Require a full sync pattern to declare the data received
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_RANGE                       14:14
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_WOFFSET                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Limit the number of bit times a K can last
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_RANGE                      15:15
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_WOFFSET                    0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Number of K bits in question
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_FIELD                        (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_RANGE                        21:16
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT                      _MK_MASK_CONST(0x14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Only look for transitioning out of EOP
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_RANGE                   22:22
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Do not allow >= dribble bits 
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_RANGE                  25:23
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Do not allow <= dribble bits
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_RANGE                  28:26
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT                    _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_RANGE                    29:29
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Filter SE1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_RANGE                        30:30
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// One SE1, don't allow dribble
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_RANGE                        31:31
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_FSLSRX_CFG1_0  // UTMIP full and Low speed receive config 1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0                    _MK_ADDR_CONST(0xa1c)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WORD_COUNT                         0x1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_VAL                  _MK_MASK_CONST(0x2267400)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_MASK                         _MK_MASK_CONST(0x7ffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_READ_MASK                  _MK_MASK_CONST(0x7ffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WRITE_MASK                         _MK_MASK_CONST(0x7ffffff)
+// Whether full speed EOP  is determined within 3(0) or 4(1) 60MHz cycles
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_RANGE                  0:0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Whether full speed uses debouncing
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_RANGE                    1:1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Only look for a KK pattern, instead of KJKK
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_RANGE                   2:2
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in full speed mode
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_RANGE                     3:3
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in low  speed mode
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_RANGE                     4:4
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Only for this number of 60MHz of SEO and Idle to end packet
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT                   _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_FIELD                   (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_RANGE                   10:5
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT                 _MK_MASK_CONST(0x20)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of SEO clock cycles to block bit extraction
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT                     _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_RANGE                     16:11
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT                   _MK_MASK_CONST(0xe)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Phase count on which LS bits are extracted
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT                    _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_RANGE                    22:17
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT                  _MK_MASK_CONST(0x13)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of clock cycle of LS stable
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT                       _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_RANGE                       25:23
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_WOFFSET                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT                     _MK_MASK_CONST(0x4)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Assumes line state filtering table is inclusive, not exclusive
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_RANGE                        26:26
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_TX_CFG0_0  // UTMIP transmit config signals 
+#define APB_MISC_UTMIP_TX_CFG0_0                        _MK_ADDR_CONST(0xa20)
+#define APB_MISC_UTMIP_TX_CFG0_0_WORD_COUNT                     0x1
+#define APB_MISC_UTMIP_TX_CFG0_0_RESET_VAL                      _MK_MASK_CONST(0x10200)
+#define APB_MISC_UTMIP_TX_CFG0_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_TX_CFG0_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+// Do not sent SYNC or EOP
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_RANGE                     0:0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_WOFFSET                   0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// No encoding, static programming
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_RANGE                        1:1
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// No bit stuffing, static programming
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_RANGE                        2:2
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 2 -- not likely, for Chirp
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_RANGE                   3:3
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_WOFFSET                 0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 3 -- perhaps, when sending controller made packets
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_RANGE                    4:4
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SIE, not macrocell, detects LineState change to resume
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_RANGE                    5:5
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// output enable turns on  1 cycle before
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_RANGE                  6:6
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// output enable turns off 1 cycle after
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 7:7
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Disable high speed disconnect
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_RANGE                  8:8
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Only check during EOP
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_RANGE                 9:9
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_RANGE                      14:10
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_WOFFSET                    0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT                    _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_RANGE                    15:15
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Allow SOP to be source of transmit error stuffing
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_RANGE                        16:16
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// output enable turns on  1/2 cycle before
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_RANGE                  17:17
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// output enable turns off 1/2 cycle after 
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 18:18
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// output enable sends an initial J before sync pattern
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT                      _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_RANGE                      19:19
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_WOFFSET                    0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_MISC_CFG0_0  // UTMIP miscellaneous configurations
+#define APB_MISC_UTMIP_MISC_CFG0_0                      _MK_ADDR_CONST(0xa24)
+#define APB_MISC_UTMIP_MISC_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x3e00078)
+#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffffff)
+// Use combinational terminations or synced through CLKXTAL
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_RANGE                       0:0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Use free running terminations at all time
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_RANGE                        1:1
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Ignore free running terminations, even when no clock
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_RANGE                 2:2
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Don't use free running terminations during suspend.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_RANGE                       3:3
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Determines if all signal need to be stable to not change a config.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_RANGE                       4:4
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Number of cycles of crystal clock of signal not changing to consider stable.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_RANGE                     7:5
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force DM pulldown active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_RANGE                  8:8
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DP pulldown active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_RANGE                  9:9
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DM pullup active.      
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_RANGE                  10:10
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DP pullup active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_RANGE                  11:11
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DM pulldown inactive. (Overrides FORCE_PULLDN_DM.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_RANGE                        12:12
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DP pulldown inactive. (Overrides FORCE_PULLDN_DP.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_RANGE                        13:13
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DM pullup inactive. (Overrides FORCE_PULLUP_DM.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_RANGE                        14:14
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DP pullup inactive. (Overrides FORCE_PULLUP_DP.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_RANGE                        15:15
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force HS termination active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_RANGE                    16:16
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force HS termination inactive.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT                  _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_RANGE                  17:17
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force HS clock always on.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_RANGE                        18:18
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force error insertion into RX path. (Used for IOBIST.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RANGE                        20:19
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_ERR                      _MK_ENUM_CONST(1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RX_ERR                       _MK_ENUM_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_RX_ERR                   _MK_ENUM_CONST(3)
+
+// Don't block changes for 4ms when going from LS to FS (should not happen)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_RANGE                        21:21
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Suspend exit requires edge or simply a value...
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT                     _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_RANGE                     22:22
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT                    _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_RANGE                    23:23
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_RANGE                  24:24
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT                      _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_RANGE                      25:25
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_WOFFSET                    0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Use DP/DM as obs bus
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT                     _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_RANGE                     26:26
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Select DP/DM obs signals
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT                 _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_RANGE                 30:27
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_MISC_CFG1_0  // UTMIP miscellaneous configurations
+#define APB_MISC_UTMIP_MISC_CFG1_0                      _MK_ADDR_CONST(0xa28)
+#define APB_MISC_UTMIP_MISC_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x198024)
+#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
+// Bit 0: 0: 0xa5 -> treat as KeepAlive 
+//        1: treat as regular packet 
+// Bit 1: 0: Turn on FS EOP detection
+//        1: Turn off FS EOP detection
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_RANGE                 1:0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_RANGE                  2:2
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_RANGE                       3:3
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_RANGE                  4:4
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_RANGE                 5:5
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// WRONG! This should be 1ms -> 0x50
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_FIELD                        (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_RANGE                        17:6
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT                      _MK_MASK_CONST(0x600)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0xfff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 5 us / (1/19.2MHz) = 96 / 16 = 6
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE                     22:18
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x6)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_RANGE                      23:23
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_WOFFSET                    0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_RANGE                 24:24
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT                  _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_RANGE                  26:25
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: Use FS filtering on line state when XcvrSel=3
+// 1: Use LS filtering on line state when XcvrSel=3
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_RANGE                       27:27
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Use neg edge sync for linestate
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_RANGE                    28:28
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bypass LineState reclocking logic
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT                 _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_RANGE                 29:29
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_DEBOUNCE_CFG0_0  // UTMIP Avalid and Bvalid debounce
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0                  _MK_ADDR_CONST(0xa2c)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WORD_COUNT                       0x1
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// simulation value -- Used for interrupts
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_RANGE                      15:0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_WOFFSET                    0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// simulation value -- Used for interrupts
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_RANGE                      31:16
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_WOFFSET                    0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BAT_CHRG_CFG0_0  // UTMIP battery charger configuration
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0                  _MK_ADDR_CONST(0xa30)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WORD_COUNT                       0x1
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
+// Power down charger circuit
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_RANGE                      0:0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_WOFFSET                    0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_RANGE                   1:1
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_RANGE                   2:2
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_RANGE                    3:3
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_RANGE                    4:4
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_SPARE_CFG0_0  // Utmip spare configuration bits 
+#define APB_MISC_UTMIP_SPARE_CFG0_0                     _MK_ADDR_CONST(0xa34)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_WORD_COUNT                  0x1
+#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_VAL                   _MK_MASK_CONST(0xffff0000)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Spare register bits
+// 0: HS_RX_IPG_ERROR_ENABLE
+// 1: HS_RX_FLUSH_ALAP. Flush as late as possible
+// 2: HS_RX_LATE_SQUELCH. Delay Squelch by 1 CLK480 cycle.
+// 31 to 3: Reserved
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_FIELD                   (_MK_MASK_CONST(0xffffffff) << APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_RANGE                   31:0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_WOFFSET                 0x0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT                 _MK_MASK_CONST(0xffff0000)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_INIT_ENUM                       -65536
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPB_MISC_REGS(_op_) \
+_op_(APB_MISC_PP_STRAPPING_OPT_A_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_A_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_B_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_C_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_D_0) \
+_op_(APB_MISC_PP_CONFIG_CTL_0) \
+_op_(APB_MISC_PP_MISC_USB_OTG_0) \
+_op_(APB_MISC_PP_XMB_CSR_0) \
+_op_(APB_MISC_PP_XMB_NOR_FLASH_CFG_0) \
+_op_(APB_MISC_PP_XMB_MIO_CFG_0) \
+_op_(APB_MISC_PP_USB_PHY_VCTL_REG_0) \
+_op_(APB_MISC_PP_USB_PHY_PARAM_0) \
+_op_(APB_MISC_PP_USB_PHY_SELF_TEST_DEBUG_0) \
+_op_(APB_MISC_PP_USB_PHY_SELF_TEST_0) \
+_op_(APB_MISC_PP_USB_PHY_VBUS_SENSORS_0) \
+_op_(APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0) \
+_op_(APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0) \
+_op_(APB_MISC_PP_MISC_SAVE_THE_DAY_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_A_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_B_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_C_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_D_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_E_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_F_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_G_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_H_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_A_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_B_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_C_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_D_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_E_0) \
+_op_(APB_MISC_ASYNC_COREPWRCONFIG_0) \
+_op_(APB_MISC_ASYNC_DLYCTRL_0) \
+_op_(APB_MISC_ASYNC_CLKMNTREN_0) \
+_op_(APB_MISC_ASYNC_EMCPADEN_0) \
+_op_(APB_MISC_ASYNC_EMCPADCTRL_0) \
+_op_(APB_MISC_ASYNC_MEMPADCAL1_0) \
+_op_(APB_MISC_ASYNC_LCDPADCTRL_0) \
+_op_(APB_MISC_ASYNC_LCDPADCAL1_0) \
+_op_(APB_MISC_ASYNC_VIPADCTRL_0) \
+_op_(APB_MISC_ASYNC_VIPADCAL1_0) \
+_op_(APB_MISC_ASYNC_VCLKCTRL_0) \
+_op_(APB_MISC_ASYNC_TVDACVHSYNCCTRL_0) \
+_op_(APB_MISC_ASYNC_TVDACCNTL_0) \
+_op_(APB_MISC_ASYNC_TVDACSTATUS_0) \
+_op_(APB_MISC_ASYNC_TVDACDINCONFIG_0) \
+_op_(APB_MISC_ASYNC_INT_STATUS_0) \
+_op_(APB_MISC_ASYNC_INT_MASK_0) \
+_op_(APB_MISC_ASYNC_INT_POLARITY_0) \
+_op_(APB_MISC_ASYNC_INT_TYPE_SELECT_0) \
+_op_(APB_MISC_GP_MODEREG_0) \
+_op_(APB_MISC_GP_HIDREV_0) \
+_op_(APB_MISC_GP_ASDBGREG_0) \
+_op_(APB_MISC_GP_RESERVEREG_0) \
+_op_(APB_MISC_GP_OBSCTRL_0) \
+_op_(APB_MISC_GP_OBSDATA_0) \
+_op_(APB_MISC_GP_EFUSEREQ_0) \
+_op_(APB_MISC_GP_EFUSEOFF_0) \
+_op_(APB_MISC_GP_EFUSEWRDAT_0) \
+_op_(APB_MISC_GP_EFUSERDDAT_0) \
+_op_(APB_MISC_GP_EFUSEVAL1_0) \
+_op_(APB_MISC_GP_EFUSEVAL2_0) \
+_op_(APB_MISC_GP_EFUSEBYPASSID_0) \
+_op_(APB_MISC_GP_BRDCLK_TRIM_0) \
+_op_(APB_MISC_GP_ASDBGREG2_0) \
+_op_(APB_MISC_GP_EMU_REVID_0) \
+_op_(APB_MISC_GP_TRANSACTOR_SCRATCH_0) \
+_op_(APB_MISC_GP_AOCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_AOCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_ATCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_ATCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_CDEV1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_CDEV2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_CSUSCFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP4CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DBGCFGPADCTRL_0) \
+_op_(APB_MISC_GP_LCDCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_LCDCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_SDIO2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_SDIO3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_SPICFGPADCTRL_0) \
+_op_(APB_MISC_GP_UAACFGPADCTRL_0) \
+_op_(APB_MISC_GP_UABCFGPADCTRL_0) \
+_op_(APB_MISC_GP_UART2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_UART3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_VICFG1PADCTRL_0) \
+_op_(APB_MISC_GP_VICFG2PADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGAPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGCPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGDPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CLKCFGPADCTRL_0) \
+_op_(APB_MISC_GP_MEMCOMPPADCTRL_0) \
+_op_(APB_MISC_GP_PADCTL_DFT_0) \
+_op_(APB_MISC_UTMIP_PLL_CFG0_0) \
+_op_(APB_MISC_UTMIP_PLL_CFG1_0) \
+_op_(APB_MISC_UTMIP_XCVR_CFG0_0) \
+_op_(APB_MISC_UTMIP_BIAS_CFG0_0) \
+_op_(APB_MISC_UTMIP_HSRX_CFG0_0) \
+_op_(APB_MISC_UTMIP_HSRX_CFG1_0) \
+_op_(APB_MISC_UTMIP_FSLSRX_CFG0_0) \
+_op_(APB_MISC_UTMIP_FSLSRX_CFG1_0) \
+_op_(APB_MISC_UTMIP_TX_CFG0_0) \
+_op_(APB_MISC_UTMIP_MISC_CFG0_0) \
+_op_(APB_MISC_UTMIP_MISC_CFG1_0) \
+_op_(APB_MISC_UTMIP_DEBOUNCE_CFG0_0) \
+_op_(APB_MISC_UTMIP_BAT_CHRG_CFG0_0) \
+_op_(APB_MISC_UTMIP_SPARE_CFG0_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APB_MISC   0x00000000
+#define BASE_ADDRESS_APB_MISC_PP        0x00000000
+#define BASE_ADDRESS_APB_MISC_ASYNC     0x00000400
+#define BASE_ADDRESS_APB_MISC_GP        0x00000800
+#define BASE_ADDRESS_APB_MISC_UTMIP     0x00000a00
+
+//
+// ARAPB_MISC REGISTER BANKS
+//
+
+#define APB_MISC_PP0_FIRST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
+#define APB_MISC_PP0_LAST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
+#define APB_MISC_PP1_FIRST_REG 0x0014 // APB_MISC_PP_TRISTATE_REG_A_0
+#define APB_MISC_PP1_LAST_REG 0x0028 // APB_MISC_PP_MISC_USB_OTG_0
+#define APB_MISC_PP2_FIRST_REG 0x0030 // APB_MISC_PP_XMB_CSR_0
+#define APB_MISC_PP2_LAST_REG 0x0034 // APB_MISC_PP_XMB_NOR_FLASH_CFG_0
+#define APB_MISC_PP3_FIRST_REG 0x0040 // APB_MISC_PP_XMB_MIO_CFG_0
+#define APB_MISC_PP3_LAST_REG 0x0040 // APB_MISC_PP_XMB_MIO_CFG_0
+#define APB_MISC_PP4_FIRST_REG 0x0060 // APB_MISC_PP_USB_PHY_VCTL_REG_0
+#define APB_MISC_PP4_LAST_REG 0x00b0 // APB_MISC_PP_PULLUPDOWN_REG_E_0
+#define APB_MISC_ASYNC0_FIRST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
+#define APB_MISC_ASYNC0_LAST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
+#define APB_MISC_ASYNC1_FIRST_REG 0x0408 // APB_MISC_ASYNC_DLYCTRL_0
+#define APB_MISC_ASYNC1_LAST_REG 0x042c // APB_MISC_ASYNC_VCLKCTRL_0
+#define APB_MISC_ASYNC2_FIRST_REG 0x0438 // APB_MISC_ASYNC_TVDACVHSYNCCTRL_0
+#define APB_MISC_ASYNC2_LAST_REG 0x0454 // APB_MISC_ASYNC_INT_TYPE_SELECT_0
+#define APB_MISC_GP0_FIRST_REG 0x0800 // APB_MISC_GP_MODEREG_0
+#define APB_MISC_GP0_LAST_REG 0x0804 // APB_MISC_GP_HIDREV_0
+#define APB_MISC_GP1_FIRST_REG 0x0810 // APB_MISC_GP_ASDBGREG_0
+#define APB_MISC_GP1_LAST_REG 0x083c // APB_MISC_GP_BRDCLK_TRIM_0
+#define APB_MISC_GP2_FIRST_REG 0x0858 // APB_MISC_GP_ASDBGREG2_0
+#define APB_MISC_GP2_LAST_REG 0x0858 // APB_MISC_GP_ASDBGREG2_0
+#define APB_MISC_GP3_FIRST_REG 0x0860 // APB_MISC_GP_EMU_REVID_0
+#define APB_MISC_GP3_LAST_REG 0x08d8 // APB_MISC_GP_PADCTL_DFT_0
+#define APB_MISC_UTMIP0_FIRST_REG 0x0a00 // APB_MISC_UTMIP_PLL_CFG0_0
+#define APB_MISC_UTMIP0_LAST_REG 0x0a34 // APB_MISC_UTMIP_SPARE_CFG0_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPB_MISC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arapbdma.h b/arch/arm/mach-tegra/nv/include/ap15/arapbdma.h
new file mode 100644
index 000000000000..860ca6da52aa
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arapbdma.h
@@ -0,0 +1,2466 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBDMA_H_INC_
+#define ___ARAPBDMA_H_INC_
+
+// Register APBDMA_COMMAND_0  
+#define APBDMA_COMMAND_0                        _MK_ADDR_CONST(0x0)
+#define APBDMA_COMMAND_0_WORD_COUNT                     0x1
+#define APBDMA_COMMAND_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_RESET_MASK                     _MK_MASK_CONST(0x80000000)
+#define APBDMA_COMMAND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_READ_MASK                      _MK_MASK_CONST(0x80000000)
+#define APBDMA_COMMAND_0_WRITE_MASK                     _MK_MASK_CONST(0x80000000)
+// Enables Global APB-DMA  
+#define APBDMA_COMMAND_0_GEN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APBDMA_COMMAND_0_GEN_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_COMMAND_0_GEN_SHIFT)
+#define APBDMA_COMMAND_0_GEN_RANGE                      31:31
+#define APBDMA_COMMAND_0_GEN_WOFFSET                    0x0
+#define APBDMA_COMMAND_0_GEN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_COMMAND_0_GEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMA_COMMAND_0_GEN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_STATUS_0  
+#define APBDMA_STATUS_0                 _MK_ADDR_CONST(0x4)
+#define APBDMA_STATUS_0_WORD_COUNT                      0x1
+#define APBDMA_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDMA_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDMA_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// DMA channel15  status 
+#define APBDMA_STATUS_0_BSY_15_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMA_STATUS_0_BSY_15_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_15_SHIFT)
+#define APBDMA_STATUS_0_BSY_15_RANGE                    31:31
+#define APBDMA_STATUS_0_BSY_15_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_15_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_15_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel14  status
+#define APBDMA_STATUS_0_BSY_14_SHIFT                    _MK_SHIFT_CONST(30)
+#define APBDMA_STATUS_0_BSY_14_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_14_SHIFT)
+#define APBDMA_STATUS_0_BSY_14_RANGE                    30:30
+#define APBDMA_STATUS_0_BSY_14_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_14_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_14_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel13  status 
+#define APBDMA_STATUS_0_BSY_13_SHIFT                    _MK_SHIFT_CONST(29)
+#define APBDMA_STATUS_0_BSY_13_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_13_SHIFT)
+#define APBDMA_STATUS_0_BSY_13_RANGE                    29:29
+#define APBDMA_STATUS_0_BSY_13_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_13_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_13_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel12  status 
+#define APBDMA_STATUS_0_BSY_12_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMA_STATUS_0_BSY_12_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_12_SHIFT)
+#define APBDMA_STATUS_0_BSY_12_RANGE                    28:28
+#define APBDMA_STATUS_0_BSY_12_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_12_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_12_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel11  status 
+#define APBDMA_STATUS_0_BSY_11_SHIFT                    _MK_SHIFT_CONST(27)
+#define APBDMA_STATUS_0_BSY_11_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_11_SHIFT)
+#define APBDMA_STATUS_0_BSY_11_RANGE                    27:27
+#define APBDMA_STATUS_0_BSY_11_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_11_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_11_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel10  status
+#define APBDMA_STATUS_0_BSY_10_SHIFT                    _MK_SHIFT_CONST(26)
+#define APBDMA_STATUS_0_BSY_10_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_10_SHIFT)
+#define APBDMA_STATUS_0_BSY_10_RANGE                    26:26
+#define APBDMA_STATUS_0_BSY_10_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_10_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_10_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel9  status 
+#define APBDMA_STATUS_0_BSY_9_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDMA_STATUS_0_BSY_9_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_9_SHIFT)
+#define APBDMA_STATUS_0_BSY_9_RANGE                     25:25
+#define APBDMA_STATUS_0_BSY_9_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_9_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_9_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel8  status 
+#define APBDMA_STATUS_0_BSY_8_SHIFT                     _MK_SHIFT_CONST(24)
+#define APBDMA_STATUS_0_BSY_8_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_8_SHIFT)
+#define APBDMA_STATUS_0_BSY_8_RANGE                     24:24
+#define APBDMA_STATUS_0_BSY_8_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_8_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_8_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel7  status 
+#define APBDMA_STATUS_0_BSY_7_SHIFT                     _MK_SHIFT_CONST(23)
+#define APBDMA_STATUS_0_BSY_7_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_7_SHIFT)
+#define APBDMA_STATUS_0_BSY_7_RANGE                     23:23
+#define APBDMA_STATUS_0_BSY_7_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_7_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel6  status 
+#define APBDMA_STATUS_0_BSY_6_SHIFT                     _MK_SHIFT_CONST(22)
+#define APBDMA_STATUS_0_BSY_6_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_6_SHIFT)
+#define APBDMA_STATUS_0_BSY_6_RANGE                     22:22
+#define APBDMA_STATUS_0_BSY_6_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_6_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel5  status 
+#define APBDMA_STATUS_0_BSY_5_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDMA_STATUS_0_BSY_5_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_5_SHIFT)
+#define APBDMA_STATUS_0_BSY_5_RANGE                     21:21
+#define APBDMA_STATUS_0_BSY_5_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_5_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel4  status 
+#define APBDMA_STATUS_0_BSY_4_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_STATUS_0_BSY_4_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_4_SHIFT)
+#define APBDMA_STATUS_0_BSY_4_RANGE                     20:20
+#define APBDMA_STATUS_0_BSY_4_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_4_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel3  status 
+#define APBDMA_STATUS_0_BSY_3_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_STATUS_0_BSY_3_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_3_SHIFT)
+#define APBDMA_STATUS_0_BSY_3_RANGE                     19:19
+#define APBDMA_STATUS_0_BSY_3_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_3_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel2  status 
+#define APBDMA_STATUS_0_BSY_2_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDMA_STATUS_0_BSY_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_2_SHIFT)
+#define APBDMA_STATUS_0_BSY_2_RANGE                     18:18
+#define APBDMA_STATUS_0_BSY_2_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_2_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel1  status 
+#define APBDMA_STATUS_0_BSY_1_SHIFT                     _MK_SHIFT_CONST(17)
+#define APBDMA_STATUS_0_BSY_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_1_SHIFT)
+#define APBDMA_STATUS_0_BSY_1_RANGE                     17:17
+#define APBDMA_STATUS_0_BSY_1_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_1_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel0  status 
+#define APBDMA_STATUS_0_BSY_0_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMA_STATUS_0_BSY_0_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_0_SHIFT)
+#define APBDMA_STATUS_0_BSY_0_RANGE                     16:16
+#define APBDMA_STATUS_0_BSY_0_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_0_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel15 Interrupt Status
+#define APBDMA_STATUS_0_ISE_EOC_15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_STATUS_0_ISE_EOC_15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_15_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_15_RANGE                        15:15
+#define APBDMA_STATUS_0_ISE_EOC_15_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_15_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel14 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_STATUS_0_ISE_EOC_14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_14_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_14_RANGE                        14:14
+#define APBDMA_STATUS_0_ISE_EOC_14_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_14_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel13 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_STATUS_0_ISE_EOC_13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_13_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_13_RANGE                        13:13
+#define APBDMA_STATUS_0_ISE_EOC_13_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_13_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel12 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_STATUS_0_ISE_EOC_12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_12_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_12_RANGE                        12:12
+#define APBDMA_STATUS_0_ISE_EOC_12_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_12_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel11 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_STATUS_0_ISE_EOC_11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_11_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_11_RANGE                        11:11
+#define APBDMA_STATUS_0_ISE_EOC_11_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_11_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel10 Interrupt Status
+#define APBDMA_STATUS_0_ISE_EOC_10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_STATUS_0_ISE_EOC_10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_10_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_10_RANGE                        10:10
+#define APBDMA_STATUS_0_ISE_EOC_10_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_10_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel9  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_STATUS_0_ISE_EOC_9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_9_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_9_RANGE                 9:9
+#define APBDMA_STATUS_0_ISE_EOC_9_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_9_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel8  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_STATUS_0_ISE_EOC_8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_8_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_8_RANGE                 8:8
+#define APBDMA_STATUS_0_ISE_EOC_8_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_8_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel7  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_STATUS_0_ISE_EOC_7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_7_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_7_RANGE                 7:7
+#define APBDMA_STATUS_0_ISE_EOC_7_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_7_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel6  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_STATUS_0_ISE_EOC_6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_6_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_6_RANGE                 6:6
+#define APBDMA_STATUS_0_ISE_EOC_6_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_6_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel5  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_STATUS_0_ISE_EOC_5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_5_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_5_RANGE                 5:5
+#define APBDMA_STATUS_0_ISE_EOC_5_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_5_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel4  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_STATUS_0_ISE_EOC_4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_4_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_4_RANGE                 4:4
+#define APBDMA_STATUS_0_ISE_EOC_4_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_4_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel3  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_STATUS_0_ISE_EOC_3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_3_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_3_RANGE                 3:3
+#define APBDMA_STATUS_0_ISE_EOC_3_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_3_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel2  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_STATUS_0_ISE_EOC_2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_2_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_2_RANGE                 2:2
+#define APBDMA_STATUS_0_ISE_EOC_2_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_2_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel1  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_STATUS_0_ISE_EOC_1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_1_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_1_RANGE                 1:1
+#define APBDMA_STATUS_0_ISE_EOC_1_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_1_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel0  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_0_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_0_RANGE                 0:0
+#define APBDMA_STATUS_0_ISE_EOC_0_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_0_ACTIVE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_REQUESTORS_TX_0  
+#define APBDMA_REQUESTORS_TX_0                  _MK_ADDR_CONST(0x8)
+#define APBDMA_REQUESTORS_TX_0_WORD_COUNT                       0x1
+#define APBDMA_REQUESTORS_TX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_RESET_MASK                       _MK_MASK_CONST(0x3ffff)
+#define APBDMA_REQUESTORS_TX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_READ_MASK                        _MK_MASK_CONST(0x3ffff)
+#define APBDMA_REQUESTORS_TX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// SLINK 2B-3
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B3_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_RANGE                      17:17
+#define APBDMA_REQUESTORS_TX_0_SL2B3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-2
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_RANGE                      16:16
+#define APBDMA_REQUESTORS_TX_0_SL2B2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-1
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_RANGE                      15:15
+#define APBDMA_REQUESTORS_TX_0_SL2B1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 4B
+#define APBDMA_REQUESTORS_TX_0_SL4B_SHIFT                       _MK_SHIFT_CONST(14)
+#define APBDMA_REQUESTORS_TX_0_SL4B_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL4B_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL4B_RANGE                       14:14
+#define APBDMA_REQUESTORS_TX_0_SL4B_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_SL4B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL4B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL4B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL4B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL4B_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL4B_ACTIVE                      _MK_ENUM_CONST(1)
+
+// ACModem
+#define APBDMA_REQUESTORS_TX_0_ACModem_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_REQUESTORS_TX_0_ACModem_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_ACModem_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_ACModem_RANGE                    13:13
+#define APBDMA_REQUESTORS_TX_0_ACModem_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_TX_0_ACModem_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_ACModem_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_ACTIVE                   _MK_ENUM_CONST(1)
+
+// AC97
+#define APBDMA_REQUESTORS_TX_0_AC97_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDMA_REQUESTORS_TX_0_AC97_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_AC97_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_AC97_RANGE                       12:12
+#define APBDMA_REQUESTORS_TX_0_AC97_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_AC97_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPI Controller
+#define APBDMA_REQUESTORS_TX_0_SPI_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_REQUESTORS_TX_0_SPI_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SPI_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SPI_RANGE                        11:11
+#define APBDMA_REQUESTORS_TX_0_SPI_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_TX_0_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SPI_ACTIVE                       _MK_ENUM_CONST(1)
+
+// UART C
+#define APBDMA_REQUESTORS_TX_0_UART_C_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDMA_REQUESTORS_TX_0_UART_C_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_C_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_C_RANGE                     10:10
+#define APBDMA_REQUESTORS_TX_0_UART_C_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_C_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART B (VFIR)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_REQUESTORS_TX_0_UART_B_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_B_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_B_RANGE                     9:9
+#define APBDMA_REQUESTORS_TX_0_UART_B_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART A
+#define APBDMA_REQUESTORS_TX_0_UART_A_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_REQUESTORS_TX_0_UART_A_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_A_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_A_RANGE                     8:8
+#define APBDMA_REQUESTORS_TX_0_UART_A_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Tx Output FIFO1 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S2_1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_RANGE                     7:7
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Tx Output FIFO2 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S2_2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_RANGE                     6:6
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_ACTIVE                    _MK_ENUM_CONST(1)
+
+// MIPI Rx Input FIFO.
+#define APBDMA_REQUESTORS_TX_0_MIPI_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDMA_REQUESTORS_TX_0_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_MIPI_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_MIPI_RANGE                       5:5
+#define APBDMA_REQUESTORS_TX_0_MIPI_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// EBU USR Output (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_UI_I_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDMA_REQUESTORS_TX_0_UI_I_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UI_I_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UI_I_RANGE                       4:4
+#define APBDMA_REQUESTORS_TX_0_UI_I_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_UI_I_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UI_I_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPDIF Output FIFO (Rx) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SPD_I_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_RANGE                      3:3
+#define APBDMA_REQUESTORS_TX_0_SPD_I_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SPD_I_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2S Tx Output FIFO1 (Record) (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S_1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_RANGE                      2:2
+#define APBDMA_REQUESTORS_TX_0_I2S_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2S_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2S Tx Output FIFO2 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S_2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_RANGE                      1:1
+#define APBDMA_REQUESTORS_TX_0_I2S_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2S_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// Enables counter request.
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_CNTR_REQ_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_RANGE                   0:0
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_WOFFSET                 0x0
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_ACTIVE                  _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_REQUESTORS_RX_0  
+#define APBDMA_REQUESTORS_RX_0                  _MK_ADDR_CONST(0xc)
+#define APBDMA_REQUESTORS_RX_0_WORD_COUNT                       0x1
+#define APBDMA_REQUESTORS_RX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_RESET_MASK                       _MK_MASK_CONST(0x3ffff)
+#define APBDMA_REQUESTORS_RX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_READ_MASK                        _MK_MASK_CONST(0x3ffff)
+#define APBDMA_REQUESTORS_RX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// SLINK 2B-3
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B3_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_RANGE                      17:17
+#define APBDMA_REQUESTORS_RX_0_SL2B3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-2
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_RANGE                      16:16
+#define APBDMA_REQUESTORS_RX_0_SL2B2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-1
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_RANGE                      15:15
+#define APBDMA_REQUESTORS_RX_0_SL2B1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 4B
+#define APBDMA_REQUESTORS_RX_0_SL4B_SHIFT                       _MK_SHIFT_CONST(14)
+#define APBDMA_REQUESTORS_RX_0_SL4B_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL4B_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL4B_RANGE                       14:14
+#define APBDMA_REQUESTORS_RX_0_SL4B_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_SL4B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL4B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL4B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL4B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL4B_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL4B_ACTIVE                      _MK_ENUM_CONST(1)
+
+// ACModem
+#define APBDMA_REQUESTORS_RX_0_ACModem_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_REQUESTORS_RX_0_ACModem_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_ACModem_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_ACModem_RANGE                    13:13
+#define APBDMA_REQUESTORS_RX_0_ACModem_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_RX_0_ACModem_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_ACModem_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_ACTIVE                   _MK_ENUM_CONST(1)
+
+// AC97
+#define APBDMA_REQUESTORS_RX_0_AC97_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDMA_REQUESTORS_RX_0_AC97_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_AC97_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_AC97_RANGE                       12:12
+#define APBDMA_REQUESTORS_RX_0_AC97_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_AC97_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPI Controller
+#define APBDMA_REQUESTORS_RX_0_SPI_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_REQUESTORS_RX_0_SPI_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SPI_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SPI_RANGE                        11:11
+#define APBDMA_REQUESTORS_RX_0_SPI_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_RX_0_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SPI_ACTIVE                       _MK_ENUM_CONST(1)
+
+// UART C
+#define APBDMA_REQUESTORS_RX_0_UART_C_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDMA_REQUESTORS_RX_0_UART_C_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_C_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_C_RANGE                     10:10
+#define APBDMA_REQUESTORS_RX_0_UART_C_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_C_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART B (VFIR)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_REQUESTORS_RX_0_UART_B_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_B_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_B_RANGE                     9:9
+#define APBDMA_REQUESTORS_RX_0_UART_B_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART A
+#define APBDMA_REQUESTORS_RX_0_UART_A_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_REQUESTORS_RX_0_UART_A_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_A_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_A_RANGE                     8:8
+#define APBDMA_REQUESTORS_RX_0_UART_A_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Rx Input FIFO2 (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S2_2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_RANGE                     7:7
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Rx Input FIFO1 (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S2_1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_RANGE                     6:6
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_ACTIVE                    _MK_ENUM_CONST(1)
+
+// MIPI Rx Input FIFO.
+#define APBDMA_REQUESTORS_RX_0_MIPI_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDMA_REQUESTORS_RX_0_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_MIPI_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_MIPI_RANGE                       5:5
+#define APBDMA_REQUESTORS_RX_0_MIPI_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// EBU+SPDIF USR Input (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_UI_I_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDMA_REQUESTORS_RX_0_UI_I_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UI_I_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UI_I_RANGE                       4:4
+#define APBDMA_REQUESTORS_RX_0_UI_I_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_UI_I_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UI_I_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPDIF Input FIFO (Rx) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SPD_I_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_RANGE                      3:3
+#define APBDMA_REQUESTORS_RX_0_SPD_I_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SPD_I_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  I2S Rx Input FIFO2 (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S_2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_RANGE                      2:2
+#define APBDMA_REQUESTORS_RX_0_I2S_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2S_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  I2S Rx Input FIFO1 (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S_1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_RANGE                      1:1
+#define APBDMA_REQUESTORS_RX_0_I2S_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2S_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  indicates Enabled counter request or not 
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_CNTR_REQ_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_RANGE                   0:0
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_WOFFSET                 0x0
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_ACTIVE                  _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_CNTRL_REG_0  
+#define APBDMA_CNTRL_REG_0                      _MK_ADDR_CONST(0x10)
+#define APBDMA_CNTRL_REG_0_WORD_COUNT                   0x1
+#define APBDMA_CNTRL_REG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APBDMA_CNTRL_REG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APBDMA_CNTRL_REG_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Enable the channel15 count
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH15_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_RANGE                    31:31
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel14 count
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH14_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_RANGE                    30:30
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel13 count
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SHIFT                    _MK_SHIFT_CONST(29)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH13_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_RANGE                    29:29
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel12 count
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH12_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_RANGE                    28:28
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel11 count
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SHIFT                    _MK_SHIFT_CONST(27)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH11_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_RANGE                    27:27
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel10 count
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SHIFT                    _MK_SHIFT_CONST(26)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH10_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_RANGE                    26:26
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel9 count
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH9_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_RANGE                     25:25
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel8 count
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SHIFT                     _MK_SHIFT_CONST(24)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH8_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_RANGE                     24:24
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel7 count
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SHIFT                     _MK_SHIFT_CONST(23)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH7_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_RANGE                     23:23
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel6 count
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SHIFT                     _MK_SHIFT_CONST(22)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH6_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_RANGE                     22:22
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel5 count
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH5_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_RANGE                     21:21
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel4 count
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH4_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_RANGE                     20:20
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel3 count
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH3_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_RANGE                     19:19
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel2 count
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH2_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_RANGE                     18:18
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel1 count
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SHIFT                     _MK_SHIFT_CONST(17)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH1_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_RANGE                     17:17
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel0 count
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH0_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_RANGE                     16:16
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DMA COUNT Value.
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_FIELD                    (_MK_MASK_CONST(0xffff) << APBDMA_CNTRL_REG_0_COUNT_VALUE_SHIFT)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_RANGE                    15:0
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDMA_IRQ_STA_CPU_0  
+#define APBDMA_IRQ_STA_CPU_0                    _MK_ADDR_CONST(0x14)
+#define APBDMA_IRQ_STA_CPU_0_WORD_COUNT                         0x1
+#define APBDMA_IRQ_STA_CPU_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_CPU_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_CPU_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Gathers all the after-masking CPU directed IRQ status bits from channel15 
+#define APBDMA_IRQ_STA_CPU_0_CH15_SHIFT                 _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_STA_CPU_0_CH15_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH15_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH15_RANGE                 15:15
+#define APBDMA_IRQ_STA_CPU_0_CH15_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel14 
+#define APBDMA_IRQ_STA_CPU_0_CH14_SHIFT                 _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_STA_CPU_0_CH14_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH14_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH14_RANGE                 14:14
+#define APBDMA_IRQ_STA_CPU_0_CH14_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel13 
+#define APBDMA_IRQ_STA_CPU_0_CH13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_STA_CPU_0_CH13_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH13_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH13_RANGE                 13:13
+#define APBDMA_IRQ_STA_CPU_0_CH13_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel12 
+#define APBDMA_IRQ_STA_CPU_0_CH12_SHIFT                 _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_STA_CPU_0_CH12_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH12_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH12_RANGE                 12:12
+#define APBDMA_IRQ_STA_CPU_0_CH12_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel11 
+#define APBDMA_IRQ_STA_CPU_0_CH11_SHIFT                 _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_STA_CPU_0_CH11_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH11_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH11_RANGE                 11:11
+#define APBDMA_IRQ_STA_CPU_0_CH11_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel10 
+#define APBDMA_IRQ_STA_CPU_0_CH10_SHIFT                 _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_STA_CPU_0_CH10_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH10_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH10_RANGE                 10:10
+#define APBDMA_IRQ_STA_CPU_0_CH10_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel9 
+#define APBDMA_IRQ_STA_CPU_0_CH9_SHIFT                  _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_STA_CPU_0_CH9_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH9_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH9_RANGE                  9:9
+#define APBDMA_IRQ_STA_CPU_0_CH9_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel8 
+#define APBDMA_IRQ_STA_CPU_0_CH8_SHIFT                  _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_STA_CPU_0_CH8_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH8_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH8_RANGE                  8:8
+#define APBDMA_IRQ_STA_CPU_0_CH8_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel7 
+#define APBDMA_IRQ_STA_CPU_0_CH7_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_STA_CPU_0_CH7_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH7_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH7_RANGE                  7:7
+#define APBDMA_IRQ_STA_CPU_0_CH7_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel6 
+#define APBDMA_IRQ_STA_CPU_0_CH6_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_STA_CPU_0_CH6_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH6_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH6_RANGE                  6:6
+#define APBDMA_IRQ_STA_CPU_0_CH6_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel5 
+#define APBDMA_IRQ_STA_CPU_0_CH5_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_STA_CPU_0_CH5_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH5_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH5_RANGE                  5:5
+#define APBDMA_IRQ_STA_CPU_0_CH5_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel4 
+#define APBDMA_IRQ_STA_CPU_0_CH4_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_STA_CPU_0_CH4_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH4_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH4_RANGE                  4:4
+#define APBDMA_IRQ_STA_CPU_0_CH4_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel3 
+#define APBDMA_IRQ_STA_CPU_0_CH3_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_STA_CPU_0_CH3_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH3_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH3_RANGE                  3:3
+#define APBDMA_IRQ_STA_CPU_0_CH3_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel2 
+#define APBDMA_IRQ_STA_CPU_0_CH2_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_STA_CPU_0_CH2_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH2_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH2_RANGE                  2:2
+#define APBDMA_IRQ_STA_CPU_0_CH2_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel1 
+#define APBDMA_IRQ_STA_CPU_0_CH1_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_STA_CPU_0_CH1_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH1_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH1_RANGE                  1:1
+#define APBDMA_IRQ_STA_CPU_0_CH1_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel0 
+#define APBDMA_IRQ_STA_CPU_0_CH0_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH0_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH0_RANGE                  0:0
+#define APBDMA_IRQ_STA_CPU_0_CH0_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_STA_COP_0  
+#define APBDMA_IRQ_STA_COP_0                    _MK_ADDR_CONST(0x18)
+#define APBDMA_IRQ_STA_COP_0_WORD_COUNT                         0x1
+#define APBDMA_IRQ_STA_COP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_COP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_COP_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Gathers all the after-masking COP directed IRQ status bits from channel15 
+#define APBDMA_IRQ_STA_COP_0_CH15_SHIFT                 _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_STA_COP_0_CH15_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH15_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH15_RANGE                 15:15
+#define APBDMA_IRQ_STA_COP_0_CH15_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH15_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel14 
+#define APBDMA_IRQ_STA_COP_0_CH14_SHIFT                 _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_STA_COP_0_CH14_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH14_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH14_RANGE                 14:14
+#define APBDMA_IRQ_STA_COP_0_CH14_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH14_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel13 
+#define APBDMA_IRQ_STA_COP_0_CH13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_STA_COP_0_CH13_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH13_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH13_RANGE                 13:13
+#define APBDMA_IRQ_STA_COP_0_CH13_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH13_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel12 
+#define APBDMA_IRQ_STA_COP_0_CH12_SHIFT                 _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_STA_COP_0_CH12_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH12_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH12_RANGE                 12:12
+#define APBDMA_IRQ_STA_COP_0_CH12_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH12_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel11 
+#define APBDMA_IRQ_STA_COP_0_CH11_SHIFT                 _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_STA_COP_0_CH11_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH11_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH11_RANGE                 11:11
+#define APBDMA_IRQ_STA_COP_0_CH11_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH11_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel10 
+#define APBDMA_IRQ_STA_COP_0_CH10_SHIFT                 _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_STA_COP_0_CH10_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH10_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH10_RANGE                 10:10
+#define APBDMA_IRQ_STA_COP_0_CH10_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH10_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel9 
+#define APBDMA_IRQ_STA_COP_0_CH9_SHIFT                  _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_STA_COP_0_CH9_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH9_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH9_RANGE                  9:9
+#define APBDMA_IRQ_STA_COP_0_CH9_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH9_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel8 
+#define APBDMA_IRQ_STA_COP_0_CH8_SHIFT                  _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_STA_COP_0_CH8_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH8_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH8_RANGE                  8:8
+#define APBDMA_IRQ_STA_COP_0_CH8_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH8_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel7 
+#define APBDMA_IRQ_STA_COP_0_CH7_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_STA_COP_0_CH7_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH7_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH7_RANGE                  7:7
+#define APBDMA_IRQ_STA_COP_0_CH7_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH7_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel6 
+#define APBDMA_IRQ_STA_COP_0_CH6_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_STA_COP_0_CH6_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH6_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH6_RANGE                  6:6
+#define APBDMA_IRQ_STA_COP_0_CH6_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH6_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel5 
+#define APBDMA_IRQ_STA_COP_0_CH5_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_STA_COP_0_CH5_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH5_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH5_RANGE                  5:5
+#define APBDMA_IRQ_STA_COP_0_CH5_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH5_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel4 
+#define APBDMA_IRQ_STA_COP_0_CH4_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_STA_COP_0_CH4_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH4_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH4_RANGE                  4:4
+#define APBDMA_IRQ_STA_COP_0_CH4_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH4_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel3 
+#define APBDMA_IRQ_STA_COP_0_CH3_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_STA_COP_0_CH3_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH3_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH3_RANGE                  3:3
+#define APBDMA_IRQ_STA_COP_0_CH3_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH3_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel2 
+#define APBDMA_IRQ_STA_COP_0_CH2_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_STA_COP_0_CH2_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH2_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH2_RANGE                  2:2
+#define APBDMA_IRQ_STA_COP_0_CH2_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel1 
+#define APBDMA_IRQ_STA_COP_0_CH1_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_STA_COP_0_CH1_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH1_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH1_RANGE                  1:1
+#define APBDMA_IRQ_STA_COP_0_CH1_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel0 
+#define APBDMA_IRQ_STA_COP_0_CH0_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH0_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH0_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH0_RANGE                  0:0
+#define APBDMA_IRQ_STA_COP_0_CH0_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_0  
+#define APBDMA_IRQ_MASK_0                       _MK_ADDR_CONST(0x1c)
+#define APBDMA_IRQ_MASK_0_WORD_COUNT                    0x1
+#define APBDMA_IRQ_MASK_0_RESET_VAL                     _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Each bit allows the associated channel15 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH15_SHIFT                    _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_0_CH15_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH15_RANGE                    15:15
+#define APBDMA_IRQ_MASK_0_CH15_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH15_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH15_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH15_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel14 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH14_SHIFT                    _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_0_CH14_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH14_RANGE                    14:14
+#define APBDMA_IRQ_MASK_0_CH14_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH14_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH14_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH14_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel13 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH13_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_0_CH13_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH13_RANGE                    13:13
+#define APBDMA_IRQ_MASK_0_CH13_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH13_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH13_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH13_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel12 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH12_SHIFT                    _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_0_CH12_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH12_RANGE                    12:12
+#define APBDMA_IRQ_MASK_0_CH12_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH12_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH12_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH12_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel11 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH11_SHIFT                    _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_0_CH11_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH11_RANGE                    11:11
+#define APBDMA_IRQ_MASK_0_CH11_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH11_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH11_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH11_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel10 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH10_SHIFT                    _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_0_CH10_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH10_RANGE                    10:10
+#define APBDMA_IRQ_MASK_0_CH10_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH10_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH10_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH10_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel9 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH9_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_0_CH9_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH9_RANGE                     9:9
+#define APBDMA_IRQ_MASK_0_CH9_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH9_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH9_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH9_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel8 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH8_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_0_CH8_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH8_RANGE                     8:8
+#define APBDMA_IRQ_MASK_0_CH8_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH8_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH8_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH8_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel7 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH7_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_0_CH7_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH7_RANGE                     7:7
+#define APBDMA_IRQ_MASK_0_CH7_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH7_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH7_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH7_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel6 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH6_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_0_CH6_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH6_RANGE                     6:6
+#define APBDMA_IRQ_MASK_0_CH6_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH6_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH6_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH6_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel5 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH5_SHIFT                     _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_0_CH5_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH5_RANGE                     5:5
+#define APBDMA_IRQ_MASK_0_CH5_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH5_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH5_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH5_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel4 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH4_SHIFT                     _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_0_CH4_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH4_RANGE                     4:4
+#define APBDMA_IRQ_MASK_0_CH4_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH4_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH4_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH4_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel3 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH3_SHIFT                     _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_0_CH3_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH3_RANGE                     3:3
+#define APBDMA_IRQ_MASK_0_CH3_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH3_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH3_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH3_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel2 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH2_SHIFT                     _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_0_CH2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH2_RANGE                     2:2
+#define APBDMA_IRQ_MASK_0_CH2_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH2_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH2_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH2_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel1 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH1_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_0_CH1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH1_RANGE                     1:1
+#define APBDMA_IRQ_MASK_0_CH1_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH1_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH1_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH1_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel0 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH0_SHIFT                     _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH0_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH0_RANGE                     0:0
+#define APBDMA_IRQ_MASK_0_CH0_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH0_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH0_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH0_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_SET_0  
+#define APBDMA_IRQ_MASK_SET_0                   _MK_ADDR_CONST(0x20)
+#define APBDMA_IRQ_MASK_SET_0_WORD_COUNT                        0x1
+#define APBDMA_IRQ_MASK_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_READ_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_SET_0_CH15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH15_RANGE                        15:15
+#define APBDMA_IRQ_MASK_SET_0_CH15_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_SET_0_CH14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH14_RANGE                        14:14
+#define APBDMA_IRQ_MASK_SET_0_CH14_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_SET_0_CH13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH13_RANGE                        13:13
+#define APBDMA_IRQ_MASK_SET_0_CH13_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_SET_0_CH12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH12_RANGE                        12:12
+#define APBDMA_IRQ_MASK_SET_0_CH12_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_SET_0_CH11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH11_RANGE                        11:11
+#define APBDMA_IRQ_MASK_SET_0_CH11_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_SET_0_CH10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH10_RANGE                        10:10
+#define APBDMA_IRQ_MASK_SET_0_CH10_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_SET_0_CH9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH9_RANGE                 9:9
+#define APBDMA_IRQ_MASK_SET_0_CH9_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_SET_0_CH8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH8_RANGE                 8:8
+#define APBDMA_IRQ_MASK_SET_0_CH8_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_SET_0_CH7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH7_RANGE                 7:7
+#define APBDMA_IRQ_MASK_SET_0_CH7_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_SET_0_CH6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH6_RANGE                 6:6
+#define APBDMA_IRQ_MASK_SET_0_CH6_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_SET_0_CH5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH5_RANGE                 5:5
+#define APBDMA_IRQ_MASK_SET_0_CH5_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_SET_0_CH4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH4_RANGE                 4:4
+#define APBDMA_IRQ_MASK_SET_0_CH4_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_SET_0_CH3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH3_RANGE                 3:3
+#define APBDMA_IRQ_MASK_SET_0_CH3_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_SET_0_CH2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH2_RANGE                 2:2
+#define APBDMA_IRQ_MASK_SET_0_CH2_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_SET_0_CH1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH1_RANGE                 1:1
+#define APBDMA_IRQ_MASK_SET_0_CH1_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH0_RANGE                 0:0
+#define APBDMA_IRQ_MASK_SET_0_CH0_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_CLR_0  
+#define APBDMA_IRQ_MASK_CLR_0                   _MK_ADDR_CONST(0x24)
+#define APBDMA_IRQ_MASK_CLR_0_WORD_COUNT                        0x1
+#define APBDMA_IRQ_MASK_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_READ_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_RANGE                        15:15
+#define APBDMA_IRQ_MASK_CLR_0_CH15_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_RANGE                        14:14
+#define APBDMA_IRQ_MASK_CLR_0_CH14_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_RANGE                        13:13
+#define APBDMA_IRQ_MASK_CLR_0_CH13_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_RANGE                        12:12
+#define APBDMA_IRQ_MASK_CLR_0_CH12_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_RANGE                        11:11
+#define APBDMA_IRQ_MASK_CLR_0_CH11_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_RANGE                        10:10
+#define APBDMA_IRQ_MASK_CLR_0_CH10_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_RANGE                 9:9
+#define APBDMA_IRQ_MASK_CLR_0_CH9_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_RANGE                 8:8
+#define APBDMA_IRQ_MASK_CLR_0_CH8_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_RANGE                 7:7
+#define APBDMA_IRQ_MASK_CLR_0_CH7_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_RANGE                 6:6
+#define APBDMA_IRQ_MASK_CLR_0_CH6_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_RANGE                 5:5
+#define APBDMA_IRQ_MASK_CLR_0_CH5_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_RANGE                 4:4
+#define APBDMA_IRQ_MASK_CLR_0_CH4_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_RANGE                 3:3
+#define APBDMA_IRQ_MASK_CLR_0_CH3_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_RANGE                 2:2
+#define APBDMA_IRQ_MASK_CLR_0_CH2_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_RANGE                 1:1
+#define APBDMA_IRQ_MASK_CLR_0_CH1_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_RANGE                 0:0
+#define APBDMA_IRQ_MASK_CLR_0_CH0_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_TRIG_REG_0  
+#define APBDMA_TRIG_REG_0                       _MK_ADDR_CONST(0x28)
+#define APBDMA_TRIG_REG_0_WORD_COUNT                    0x1
+#define APBDMA_TRIG_REG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffe)
+#define APBDMA_TRIG_REG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_READ_MASK                     _MK_MASK_CONST(0x1fffffe)
+#define APBDMA_TRIG_REG_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// EOC-15 Initiated DMA Request after transfer completion 
+#define APBDMA_TRIG_REG_0_APB_15_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMA_TRIG_REG_0_APB_15_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_15_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_15_RANGE                  24:24
+#define APBDMA_TRIG_REG_0_APB_15_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_15_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-14 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_14_SHIFT                  _MK_SHIFT_CONST(23)
+#define APBDMA_TRIG_REG_0_APB_14_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_14_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_14_RANGE                  23:23
+#define APBDMA_TRIG_REG_0_APB_14_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_14_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-13 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_13_SHIFT                  _MK_SHIFT_CONST(22)
+#define APBDMA_TRIG_REG_0_APB_13_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_13_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_13_RANGE                  22:22
+#define APBDMA_TRIG_REG_0_APB_13_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_13_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-12 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_12_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMA_TRIG_REG_0_APB_12_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_12_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_12_RANGE                  21:21
+#define APBDMA_TRIG_REG_0_APB_12_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_12_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-11 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_11_SHIFT                  _MK_SHIFT_CONST(20)
+#define APBDMA_TRIG_REG_0_APB_11_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_11_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_11_RANGE                  20:20
+#define APBDMA_TRIG_REG_0_APB_11_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_11_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-10 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_10_SHIFT                  _MK_SHIFT_CONST(19)
+#define APBDMA_TRIG_REG_0_APB_10_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_10_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_10_RANGE                  19:19
+#define APBDMA_TRIG_REG_0_APB_10_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_10_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-9 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_9_SHIFT                   _MK_SHIFT_CONST(18)
+#define APBDMA_TRIG_REG_0_APB_9_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_9_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_9_RANGE                   18:18
+#define APBDMA_TRIG_REG_0_APB_9_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_9_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_9_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_9_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-8 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_8_SHIFT                   _MK_SHIFT_CONST(17)
+#define APBDMA_TRIG_REG_0_APB_8_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_8_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_8_RANGE                   17:17
+#define APBDMA_TRIG_REG_0_APB_8_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_8_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_8_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_8_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-7 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_7_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDMA_TRIG_REG_0_APB_7_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_7_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_7_RANGE                   16:16
+#define APBDMA_TRIG_REG_0_APB_7_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_7_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-6 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_6_SHIFT                   _MK_SHIFT_CONST(15)
+#define APBDMA_TRIG_REG_0_APB_6_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_6_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_6_RANGE                   15:15
+#define APBDMA_TRIG_REG_0_APB_6_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_6_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-5 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_5_SHIFT                   _MK_SHIFT_CONST(14)
+#define APBDMA_TRIG_REG_0_APB_5_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_5_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_5_RANGE                   14:14
+#define APBDMA_TRIG_REG_0_APB_5_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_5_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-4 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_4_SHIFT                   _MK_SHIFT_CONST(13)
+#define APBDMA_TRIG_REG_0_APB_4_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_4_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_4_RANGE                   13:13
+#define APBDMA_TRIG_REG_0_APB_4_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_4_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-3 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_3_SHIFT                   _MK_SHIFT_CONST(12)
+#define APBDMA_TRIG_REG_0_APB_3_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_3_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_3_RANGE                   12:12
+#define APBDMA_TRIG_REG_0_APB_3_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_3_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-2 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_2_SHIFT                   _MK_SHIFT_CONST(11)
+#define APBDMA_TRIG_REG_0_APB_2_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_2_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_2_RANGE                   11:11
+#define APBDMA_TRIG_REG_0_APB_2_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_2_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-1 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_1_SHIFT                   _MK_SHIFT_CONST(10)
+#define APBDMA_TRIG_REG_0_APB_1_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_1_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_1_RANGE                   10:10
+#define APBDMA_TRIG_REG_0_APB_1_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_1_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-0 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_0_SHIFT                   _MK_SHIFT_CONST(9)
+#define APBDMA_TRIG_REG_0_APB_0_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_0_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_0_RANGE                   9:9
+#define APBDMA_TRIG_REG_0_APB_0_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_0_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Trigger select from Timer (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_TMR2_SHIFT                    _MK_SHIFT_CONST(8)
+#define APBDMA_TRIG_REG_0_TMR2_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_TMR2_SHIFT)
+#define APBDMA_TRIG_REG_0_TMR2_RANGE                    8:8
+#define APBDMA_TRIG_REG_0_TMR2_WOFFSET                  0x0
+#define APBDMA_TRIG_REG_0_TMR2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_TMR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_TMR2_ACTIVE                   _MK_ENUM_CONST(1)
+
+// Trigger select from Timer (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_TMR1_SHIFT                    _MK_SHIFT_CONST(7)
+#define APBDMA_TRIG_REG_0_TMR1_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_TMR1_SHIFT)
+#define APBDMA_TRIG_REG_0_TMR1_RANGE                    7:7
+#define APBDMA_TRIG_REG_0_TMR1_WOFFSET                  0x0
+#define APBDMA_TRIG_REG_0_TMR1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_TMR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_TMR1_ACTIVE                   _MK_ENUM_CONST(1)
+
+// XRQ.B (GPIOB) (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_XRQ_B_SHIFT                   _MK_SHIFT_CONST(6)
+#define APBDMA_TRIG_REG_0_XRQ_B_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_XRQ_B_SHIFT)
+#define APBDMA_TRIG_REG_0_XRQ_B_RANGE                   6:6
+#define APBDMA_TRIG_REG_0_XRQ_B_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_XRQ_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_XRQ_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_XRQ_B_ACTIVE                  _MK_ENUM_CONST(1)
+
+// XRQ.A (GPIOA) (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_XRQ_A_SHIFT                   _MK_SHIFT_CONST(5)
+#define APBDMA_TRIG_REG_0_XRQ_A_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_XRQ_A_SHIFT)
+#define APBDMA_TRIG_REG_0_XRQ_A_RANGE                   5:5
+#define APBDMA_TRIG_REG_0_XRQ_A_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_XRQ_A_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_XRQ_A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_XRQ_A_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request
+#define APBDMA_TRIG_REG_0_SMP_27_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_TRIG_REG_0_SMP_27_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_27_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_27_RANGE                  4:4
+#define APBDMA_TRIG_REG_0_SMP_27_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_27_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_27_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_26_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_TRIG_REG_0_SMP_26_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_26_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_26_RANGE                  3:3
+#define APBDMA_TRIG_REG_0_SMP_26_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_26_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_26_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_25_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_TRIG_REG_0_SMP_25_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_25_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_25_RANGE                  2:2
+#define APBDMA_TRIG_REG_0_SMP_25_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_25_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_25_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_24_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_TRIG_REG_0_SMP_24_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_24_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_24_RANGE                  1:1
+#define APBDMA_TRIG_REG_0_SMP_24_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_24_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_24_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_24_ACTIVE                 _MK_ENUM_CONST(1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBDMA_REGS(_op_) \
+_op_(APBDMA_COMMAND_0) \
+_op_(APBDMA_STATUS_0) \
+_op_(APBDMA_REQUESTORS_TX_0) \
+_op_(APBDMA_REQUESTORS_RX_0) \
+_op_(APBDMA_CNTRL_REG_0) \
+_op_(APBDMA_IRQ_STA_CPU_0) \
+_op_(APBDMA_IRQ_STA_COP_0) \
+_op_(APBDMA_IRQ_MASK_0) \
+_op_(APBDMA_IRQ_MASK_SET_0) \
+_op_(APBDMA_IRQ_MASK_CLR_0) \
+_op_(APBDMA_TRIG_REG_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDMA     0x00000000
+
+//
+// ARAPBDMA REGISTER BANKS
+//
+
+#define APBDMA0_FIRST_REG 0x0000 // APBDMA_COMMAND_0
+#define APBDMA0_LAST_REG 0x0028 // APBDMA_TRIG_REG_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBDMA_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arapbdmachan.h b/arch/arm/mach-tegra/nv/include/ap15/arapbdmachan.h
new file mode 100644
index 000000000000..b745faae4fa3
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arapbdmachan.h
@@ -0,0 +1,6991 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBDMACHAN_H_INC_
+#define ___ARAPBDMACHAN_H_INC_
+
+// Register APBDMACHAN_CHANNEL_0_CSR_0  
+#define APBDMACHAN_CHANNEL_0_CSR_0                      _MK_ADDR_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_0_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+//DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_STA_0  
+#define APBDMACHAN_CHANNEL_0_STA_0                      _MK_ADDR_CONST(0x4)
+#define APBDMACHAN_CHANNEL_0_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_0_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_0_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_0_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag                                    
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 8 [0x8] 
+
+// Reserved address 12 [0xc] 
+
+// Register APBDMACHAN_CHANNEL_0_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0                  _MK_ADDR_CONST(0x10)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0                  _MK_ADDR_CONST(0x14)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_0_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0                  _MK_ADDR_CONST(0x18)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus:APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0                  _MK_ADDR_CONST(0x1c)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_1_CSR_0  
+#define APBDMACHAN_CHANNEL_1_CSR_0                      _MK_ADDR_CONST(0x20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_1_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_STA_0  
+#define APBDMACHAN_CHANNEL_1_STA_0                      _MK_ADDR_CONST(0x24)
+#define APBDMACHAN_CHANNEL_1_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_1_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_1_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_1_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Register APBDMACHAN_CHANNEL_1_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0                  _MK_ADDR_CONST(0x30)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0                  _MK_ADDR_CONST(0x34)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_1_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0                  _MK_ADDR_CONST(0x38)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0                  _MK_ADDR_CONST(0x3c)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_2_CSR_0  
+#define APBDMACHAN_CHANNEL_2_CSR_0                      _MK_ADDR_CONST(0x40)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_2_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_STA_0  
+#define APBDMACHAN_CHANNEL_2_STA_0                      _MK_ADDR_CONST(0x44)
+#define APBDMACHAN_CHANNEL_2_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_2_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_2_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_2_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Register APBDMACHAN_CHANNEL_2_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0                  _MK_ADDR_CONST(0x50)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0                  _MK_ADDR_CONST(0x54)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_2_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0                  _MK_ADDR_CONST(0x58)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0                  _MK_ADDR_CONST(0x5c)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_3_CSR_0  
+#define APBDMACHAN_CHANNEL_3_CSR_0                      _MK_ADDR_CONST(0x60)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_3_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_STA_0  
+#define APBDMACHAN_CHANNEL_3_STA_0                      _MK_ADDR_CONST(0x64)
+#define APBDMACHAN_CHANNEL_3_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_3_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_3_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_3_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register APBDMACHAN_CHANNEL_3_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0                  _MK_ADDR_CONST(0x70)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0                  _MK_ADDR_CONST(0x74)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff070000)
+//  0 = send interrupt to COP                                            
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_3_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0                  _MK_ADDR_CONST(0x78)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0                  _MK_ADDR_CONST(0x7c)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_4_CSR_0  
+#define APBDMACHAN_CHANNEL_4_CSR_0                      _MK_ADDR_CONST(0x80)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_4_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_STA_0  
+#define APBDMACHAN_CHANNEL_4_STA_0                      _MK_ADDR_CONST(0x84)
+#define APBDMACHAN_CHANNEL_4_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_4_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_4_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_4_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Register APBDMACHAN_CHANNEL_4_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0                  _MK_ADDR_CONST(0x90)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0                  _MK_ADDR_CONST(0x94)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_4_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0                  _MK_ADDR_CONST(0x98)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0                  _MK_ADDR_CONST(0x9c)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_5_CSR_0  
+#define APBDMACHAN_CHANNEL_5_CSR_0                      _MK_ADDR_CONST(0xa0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_5_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_STA_0  
+#define APBDMACHAN_CHANNEL_5_STA_0                      _MK_ADDR_CONST(0xa4)
+#define APBDMACHAN_CHANNEL_5_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_5_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_5_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_5_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Register APBDMACHAN_CHANNEL_5_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0                  _MK_ADDR_CONST(0xb0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0                  _MK_ADDR_CONST(0xb4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_5_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0                  _MK_ADDR_CONST(0xb8)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0                  _MK_ADDR_CONST(0xbc)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_6_CSR_0  
+#define APBDMACHAN_CHANNEL_6_CSR_0                      _MK_ADDR_CONST(0xc0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_6_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_STA_0  
+#define APBDMACHAN_CHANNEL_6_STA_0                      _MK_ADDR_CONST(0xc4)
+#define APBDMACHAN_CHANNEL_6_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_6_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_6_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_6_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Register APBDMACHAN_CHANNEL_6_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0                  _MK_ADDR_CONST(0xd0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0                  _MK_ADDR_CONST(0xd4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_6_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0                  _MK_ADDR_CONST(0xd8)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0                  _MK_ADDR_CONST(0xdc)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_7_CSR_0  
+#define APBDMACHAN_CHANNEL_7_CSR_0                      _MK_ADDR_CONST(0xe0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_7_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_STA_0  
+#define APBDMACHAN_CHANNEL_7_STA_0                      _MK_ADDR_CONST(0xe4)
+#define APBDMACHAN_CHANNEL_7_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_7_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_7_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_7_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status Active or not 
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Register APBDMACHAN_CHANNEL_7_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0                  _MK_ADDR_CONST(0xf0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0                  _MK_ADDR_CONST(0xf4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_7_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0                  _MK_ADDR_CONST(0xf8)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0                  _MK_ADDR_CONST(0xfc)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_8_CSR_0  
+#define APBDMACHAN_CHANNEL_8_CSR_0                      _MK_ADDR_CONST(0x100)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_8_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_STA_0  
+#define APBDMACHAN_CHANNEL_8_STA_0                      _MK_ADDR_CONST(0x104)
+#define APBDMACHAN_CHANNEL_8_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_8_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_8_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_8_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activate or not
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 264 [0x108] 
+
+// Reserved address 268 [0x10c] 
+
+// Register APBDMACHAN_CHANNEL_8_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0                  _MK_ADDR_CONST(0x110)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0                  _MK_ADDR_CONST(0x114)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_8_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0                  _MK_ADDR_CONST(0x118)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0                  _MK_ADDR_CONST(0x11c)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_9_CSR_0  
+#define APBDMACHAN_CHANNEL_9_CSR_0                      _MK_ADDR_CONST(0x120)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_9_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA18                 _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA19                 _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA20                 _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA21                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA22                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA23                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA24                 _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA25                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_STA_0  
+#define APBDMACHAN_CHANNEL_9_STA_0                      _MK_ADDR_CONST(0x124)
+#define APBDMACHAN_CHANNEL_9_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_9_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_9_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_9_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activate or not
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Register APBDMACHAN_CHANNEL_9_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0                  _MK_ADDR_CONST(0x130)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0                  _MK_ADDR_CONST(0x134)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//When enabled the data going to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_9_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0                  _MK_ADDR_CONST(0x138)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+//APB-DMA Starting address for APB Bus: APB Base address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0                  _MK_ADDR_CONST(0x13c)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DISBALE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_10_CSR_0  
+#define APBDMACHAN_CHANNEL_10_CSR_0                     _MK_ADDR_CONST(0x140)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_10_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_STA_0  
+#define APBDMACHAN_CHANNEL_10_STA_0                     _MK_ADDR_CONST(0x144)
+#define APBDMACHAN_CHANNEL_10_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_10_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_10_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_10_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Register APBDMACHAN_CHANNEL_10_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0                 _MK_ADDR_CONST(0x150)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0                 _MK_ADDR_CONST(0x154)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_10_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0                 _MK_ADDR_CONST(0x158)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0                 _MK_ADDR_CONST(0x15c)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_11_CSR_0  
+#define APBDMACHAN_CHANNEL_11_CSR_0                     _MK_ADDR_CONST(0x160)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_11_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_STA_0  
+#define APBDMACHAN_CHANNEL_11_STA_0                     _MK_ADDR_CONST(0x164)
+#define APBDMACHAN_CHANNEL_11_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_11_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_11_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_11_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or waiting
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Register APBDMACHAN_CHANNEL_11_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0                 _MK_ADDR_CONST(0x170)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0                 _MK_ADDR_CONST(0x174)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff070000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_11_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0                 _MK_ADDR_CONST(0x178)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0                 _MK_ADDR_CONST(0x17c)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_12_CSR_0  
+#define APBDMACHAN_CHANNEL_12_CSR_0                     _MK_ADDR_CONST(0x180)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_12_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_STA_0  
+#define APBDMACHAN_CHANNEL_12_STA_0                     _MK_ADDR_CONST(0x184)
+#define APBDMACHAN_CHANNEL_12_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_12_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_12_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_12_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 392 [0x188] 
+
+// Reserved address 396 [0x18c] 
+
+// Register APBDMACHAN_CHANNEL_12_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0                 _MK_ADDR_CONST(0x190)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0                 _MK_ADDR_CONST(0x194)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_12_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0                 _MK_ADDR_CONST(0x198)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0                 _MK_ADDR_CONST(0x19c)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_13_CSR_0  
+#define APBDMACHAN_CHANNEL_13_CSR_0                     _MK_ADDR_CONST(0x1a0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_13_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_STA_0  
+#define APBDMACHAN_CHANNEL_13_STA_0                     _MK_ADDR_CONST(0x1a4)
+#define APBDMACHAN_CHANNEL_13_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_13_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_13_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_13_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 424 [0x1a8] 
+
+// Reserved address 428 [0x1ac] 
+
+// Register APBDMACHAN_CHANNEL_13_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0                 _MK_ADDR_CONST(0x1b0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0                 _MK_ADDR_CONST(0x1b4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_13_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0                 _MK_ADDR_CONST(0x1b8)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0                 _MK_ADDR_CONST(0x1bc)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_14_CSR_0  
+#define APBDMACHAN_CHANNEL_14_CSR_0                     _MK_ADDR_CONST(0x1c0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_14_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_STA_0  
+#define APBDMACHAN_CHANNEL_14_STA_0                     _MK_ADDR_CONST(0x1c4)
+#define APBDMACHAN_CHANNEL_14_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_14_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_14_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_14_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 456 [0x1c8] 
+
+// Reserved address 460 [0x1cc] 
+
+// Register APBDMACHAN_CHANNEL_14_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0                 _MK_ADDR_CONST(0x1d0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0                 _MK_ADDR_CONST(0x1d4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_14_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0                 _MK_ADDR_CONST(0x1d8)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0                 _MK_ADDR_CONST(0x1dc)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_15_CSR_0  
+#define APBDMACHAN_CHANNEL_15_CSR_0                     _MK_ADDR_CONST(0x1e0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_15_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA18                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA19                        _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA20                        _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA21                        _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA22                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA23                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA24                        _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA25                        _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_STA_0  
+#define APBDMACHAN_CHANNEL_15_STA_0                     _MK_ADDR_CONST(0x1e4)
+#define APBDMACHAN_CHANNEL_15_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_15_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_15_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_15_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 488 [0x1e8] 
+
+// Reserved address 492 [0x1ec] 
+
+// Register APBDMACHAN_CHANNEL_15_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0                 _MK_ADDR_CONST(0x1f0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0                 _MK_ADDR_CONST(0x1f4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x22000000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_15_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0                 _MK_ADDR_CONST(0x1f8)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0                 _MK_ADDR_CONST(0x1fc)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBDMACHAN_REGS(_op_) \
+_op_(APBDMACHAN_CHANNEL_0_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_0_STA_0) \
+_op_(APBDMACHAN_CHANNEL_0_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_0_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_0_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_0_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_1_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_1_STA_0) \
+_op_(APBDMACHAN_CHANNEL_1_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_1_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_1_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_1_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_2_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_2_STA_0) \
+_op_(APBDMACHAN_CHANNEL_2_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_2_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_2_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_2_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_3_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_3_STA_0) \
+_op_(APBDMACHAN_CHANNEL_3_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_3_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_3_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_3_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_4_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_4_STA_0) \
+_op_(APBDMACHAN_CHANNEL_4_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_4_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_4_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_4_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_5_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_5_STA_0) \
+_op_(APBDMACHAN_CHANNEL_5_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_5_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_5_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_5_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_6_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_6_STA_0) \
+_op_(APBDMACHAN_CHANNEL_6_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_6_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_6_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_6_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_7_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_7_STA_0) \
+_op_(APBDMACHAN_CHANNEL_7_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_7_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_7_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_7_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_8_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_8_STA_0) \
+_op_(APBDMACHAN_CHANNEL_8_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_8_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_8_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_8_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_9_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_9_STA_0) \
+_op_(APBDMACHAN_CHANNEL_9_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_9_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_9_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_9_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_10_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_10_STA_0) \
+_op_(APBDMACHAN_CHANNEL_10_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_10_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_10_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_10_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_11_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_11_STA_0) \
+_op_(APBDMACHAN_CHANNEL_11_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_11_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_11_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_11_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_12_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_12_STA_0) \
+_op_(APBDMACHAN_CHANNEL_12_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_12_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_12_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_12_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_13_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_13_STA_0) \
+_op_(APBDMACHAN_CHANNEL_13_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_13_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_13_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_13_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_14_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_14_STA_0) \
+_op_(APBDMACHAN_CHANNEL_14_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_14_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_14_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_14_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_15_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_15_STA_0) \
+_op_(APBDMACHAN_CHANNEL_15_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_15_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_15_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_15_APB_SEQ_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDMACHAN 0x00000000
+
+//
+// ARAPBDMACHAN REGISTER BANKS
+//
+
+#define APBDMACHAN0_FIRST_REG 0x0000 // APBDMACHAN_CHANNEL_0_CSR_0
+#define APBDMACHAN0_LAST_REG 0x0004 // APBDMACHAN_CHANNEL_0_STA_0
+#define APBDMACHAN1_FIRST_REG 0x0010 // APBDMACHAN_CHANNEL_0_AHB_PTR_0
+#define APBDMACHAN1_LAST_REG 0x0024 // APBDMACHAN_CHANNEL_1_STA_0
+#define APBDMACHAN2_FIRST_REG 0x0030 // APBDMACHAN_CHANNEL_1_AHB_PTR_0
+#define APBDMACHAN2_LAST_REG 0x0044 // APBDMACHAN_CHANNEL_2_STA_0
+#define APBDMACHAN3_FIRST_REG 0x0050 // APBDMACHAN_CHANNEL_2_AHB_PTR_0
+#define APBDMACHAN3_LAST_REG 0x0064 // APBDMACHAN_CHANNEL_3_STA_0
+#define APBDMACHAN4_FIRST_REG 0x0070 // APBDMACHAN_CHANNEL_3_AHB_PTR_0
+#define APBDMACHAN4_LAST_REG 0x0084 // APBDMACHAN_CHANNEL_4_STA_0
+#define APBDMACHAN5_FIRST_REG 0x0090 // APBDMACHAN_CHANNEL_4_AHB_PTR_0
+#define APBDMACHAN5_LAST_REG 0x00a4 // APBDMACHAN_CHANNEL_5_STA_0
+#define APBDMACHAN6_FIRST_REG 0x00b0 // APBDMACHAN_CHANNEL_5_AHB_PTR_0
+#define APBDMACHAN6_LAST_REG 0x00c4 // APBDMACHAN_CHANNEL_6_STA_0
+#define APBDMACHAN7_FIRST_REG 0x00d0 // APBDMACHAN_CHANNEL_6_AHB_PTR_0
+#define APBDMACHAN7_LAST_REG 0x00e4 // APBDMACHAN_CHANNEL_7_STA_0
+#define APBDMACHAN8_FIRST_REG 0x00f0 // APBDMACHAN_CHANNEL_7_AHB_PTR_0
+#define APBDMACHAN8_LAST_REG 0x0104 // APBDMACHAN_CHANNEL_8_STA_0
+#define APBDMACHAN9_FIRST_REG 0x0110 // APBDMACHAN_CHANNEL_8_AHB_PTR_0
+#define APBDMACHAN9_LAST_REG 0x0124 // APBDMACHAN_CHANNEL_9_STA_0
+#define APBDMACHAN10_FIRST_REG 0x0130 // APBDMACHAN_CHANNEL_9_AHB_PTR_0
+#define APBDMACHAN10_LAST_REG 0x0144 // APBDMACHAN_CHANNEL_10_STA_0
+#define APBDMACHAN11_FIRST_REG 0x0150 // APBDMACHAN_CHANNEL_10_AHB_PTR_0
+#define APBDMACHAN11_LAST_REG 0x0164 // APBDMACHAN_CHANNEL_11_STA_0
+#define APBDMACHAN12_FIRST_REG 0x0170 // APBDMACHAN_CHANNEL_11_AHB_PTR_0
+#define APBDMACHAN12_LAST_REG 0x0184 // APBDMACHAN_CHANNEL_12_STA_0
+#define APBDMACHAN13_FIRST_REG 0x0190 // APBDMACHAN_CHANNEL_12_AHB_PTR_0
+#define APBDMACHAN13_LAST_REG 0x01a4 // APBDMACHAN_CHANNEL_13_STA_0
+#define APBDMACHAN14_FIRST_REG 0x01b0 // APBDMACHAN_CHANNEL_13_AHB_PTR_0
+#define APBDMACHAN14_LAST_REG 0x01c4 // APBDMACHAN_CHANNEL_14_STA_0
+#define APBDMACHAN15_FIRST_REG 0x01d0 // APBDMACHAN_CHANNEL_14_AHB_PTR_0
+#define APBDMACHAN15_LAST_REG 0x01e4 // APBDMACHAN_CHANNEL_15_STA_0
+#define APBDMACHAN16_FIRST_REG 0x01f0 // APBDMACHAN_CHANNEL_15_AHB_PTR_0
+#define APBDMACHAN16_LAST_REG 0x01fc // APBDMACHAN_CHANNEL_15_APB_SEQ_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBDMACHAN_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arapbpm.h b/arch/arm/mach-tegra/nv/include/ap15/arapbpm.h
new file mode 100644
index 000000000000..25289c58dfd6
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arapbpm.h
@@ -0,0 +1,2166 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBPM_H_INC_
+#define ___ARAPBPM_H_INC_
+
+// Register APBDEV_PMC_CNTRL_0  
+#define APBDEV_PMC_CNTRL_0                      _MK_ADDR_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_CNTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RESET_MASK                   _MK_MASK_CONST(0x7fff)
+#define APBDEV_PMC_CNTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_READ_MASK                    _MK_MASK_CONST(0x7fff)
+#define APBDEV_PMC_CNTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x7fff)
+// Disable 32KHz clock to KBC 
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_RANGE                    0:0
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// Disable  32KHz clock to RTC                          
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_RANGE                    1:1
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// Software reset to RTC
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_RTC_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_RANGE                        2:2
+#define APBDEV_PMC_CNTRL_0_RTC_RST_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Software reset to KBC  
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_KBC_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_RANGE                        3:3
+#define APBDEV_PMC_CNTRL_0_KBC_RST_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset to CAR - generates 2 clock cycle  pulse. 
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_MAIN_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_RANGE                       4:4
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_WOFFSET                     0x0
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enables latching wakeup events - stops latching   on transition from 1 to 0(sequence - set to 1,set to 0) 
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SHIFT                   _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SHIFT)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_RANGE                   5:5
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_WOFFSET                 0x0
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Disable  detecting glitch on wakeup event- in default operation glitches are ignored on wakeup lines. if this bit is set to 1, glitch (event shorter than half 32khz clock, will be causing wakeup from lp0
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_RANGE                  6:6
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_WOFFSET                        0x0
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enables blinking counter and blink output -works only if BLINK field in DPD_PADS_ORIDE is set to 1
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SHIFT                       _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_BLINK_EN_SHIFT)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_RANGE                       7:7
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_WOFFSET                     0x0
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Inverts power request polarity
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SHIFT                        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_RANGE                        8:8
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_NORMAL                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_INVERT                       _MK_ENUM_CONST(1)
+
+// Power request output enable. resets to tristate
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRREQ_OE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_RANGE                      9:9
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_WOFFSET                    0x0
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Inverts system clock enable polarity 
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_RANGE                        10:10
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_NORMAL                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_INVERT                       _MK_ENUM_CONST(1)
+
+// Enables output of system enable clock - works only if SYS_CLK field in DPD_PADS_ORIDE is set to 1. resets to tristate
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SHIFT                      _MK_SHIFT_CONST(11)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SYSCLK_OE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_RANGE                      11:11
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_WOFFSET                    0x0
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Disable  power gating - global override, will override function of PWRGATE_TOGGLE register. all partitions will stay enabled. 
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SHIFT                    _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_RANGE                    12:12
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// AO intitlized  purely sftw diagnostic and interpretation
+#define APBDEV_PMC_CNTRL_0_AOINIT_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDEV_PMC_CNTRL_0_AOINIT_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_AOINIT_SHIFT)
+#define APBDEV_PMC_CNTRL_0_AOINIT_RANGE                 13:13
+#define APBDEV_PMC_CNTRL_0_AOINIT_WOFFSET                       0x0
+#define APBDEV_PMC_CNTRL_0_AOINIT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_AOINIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_NOTDONE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_DONE                  _MK_ENUM_CONST(1)
+
+// when set causes side effect of entering lp0 after powering down cpu
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_RANGE                        14:14
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SEC_DISABLE_0  
+#define APBDEV_PMC_SEC_DISABLE_0                        _MK_ADDR_CONST(0x4)
+#define APBDEV_PMC_SEC_DISABLE_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_SEC_DISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_RESET_MASK                     _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_SEC_DISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_MASK                      _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
+// disable write to secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_WRITE_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_RANGE                    0:0
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_WOFFSET                  0x0
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_ON                       _MK_ENUM_CONST(1)
+
+// disable read  from  secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_READ_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_RANGE                     1:1
+#define APBDEV_PMC_SEC_DISABLE_0_READ_WOFFSET                   0x0
+#define APBDEV_PMC_SEC_DISABLE_0_READ_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_OFF                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_ON                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PMC_SWRST_0  
+#define APBDEV_PMC_PMC_SWRST_0                  _MK_ADDR_CONST(0x8)
+#define APBDEV_PMC_PMC_SWRST_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PMC_SWRST_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+//software reset to pmc only
+#define APBDEV_PMC_PMC_SWRST_0_RST_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_PMC_SWRST_0_RST_SHIFT)
+#define APBDEV_PMC_PMC_SWRST_0_RST_RANGE                        0:0
+#define APBDEV_PMC_PMC_SWRST_0_RST_WOFFSET                      0x0
+#define APBDEV_PMC_PMC_SWRST_0_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_MASK_0  
+#define APBDEV_PMC_WAKE_MASK_0                  _MK_ADDR_CONST(0xc)
+#define APBDEV_PMC_WAKE_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_WAKE_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xfffff)
+// pin  0-15  wake enable      
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_FIELD                      (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_MASK_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RANGE                      15:0
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_ENABLE                     _MK_ENUM_CONST(1)
+
+// RTC  wake enable                
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_RANGE                        16:16
+#define APBDEV_PMC_WAKE_MASK_0_RTC_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_ENABLE                       _MK_ENUM_CONST(1)
+
+// KBC  wake  enable                
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SHIFT                        _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_RANGE                        17:17
+#define APBDEV_PMC_WAKE_MASK_0_KBC_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_ENABLE                       _MK_ENUM_CONST(1)
+
+// PWR_INT wake enable               
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SHIFT                    _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_RANGE                    18:18
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_ENABLE                   _MK_ENUM_CONST(1)
+
+// external reset  wake  enable                
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_RANGE                    19:19
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_LVL_0  
+#define APBDEV_PMC_WAKE_LVL_0                   _MK_ADDR_CONST(0x10)
+#define APBDEV_PMC_WAKE_LVL_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_WAKE_LVL_0_RESET_VAL                         _MK_MASK_CONST(0x7ffff)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_MASK                        _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_LVL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_READ_MASK                         _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_LVL_0_WRITE_MASK                        _MK_MASK_CONST(0xfffff)
+// pin 0-15 wake  level       
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_FIELD                       (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_LVL_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RANGE                       15:0
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_WOFFSET                     0x0
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_DEFAULT                     _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_ACTIVE_LOW                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_ACTIVE_HIGH                 _MK_ENUM_CONST(1)
+
+// RTC  wake  level               
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SHIFT                 _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_RANGE                 16:16
+#define APBDEV_PMC_WAKE_LVL_0_RTC_WOFFSET                       0x0
+#define APBDEV_PMC_WAKE_LVL_0_RTC_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_ACTIVE_LOW                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_ACTIVE_HIGH                   _MK_ENUM_CONST(1)
+
+// KBC  wake level                
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SHIFT                 _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_RANGE                 17:17
+#define APBDEV_PMC_WAKE_LVL_0_KBC_WOFFSET                       0x0
+#define APBDEV_PMC_WAKE_LVL_0_KBC_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_ACTIVE_LOW                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_ACTIVE_HIGH                   _MK_ENUM_CONST(1)
+
+// power interrupt - now pernamently tied to  bit 18            
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_RANGE                     18:18
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_WOFFSET                   0x0
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_ACTIVE_LOW                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_ACTIVE_HIGH                       _MK_ENUM_CONST(1)
+
+// external reset wake level (low active!)              
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_RANGE                     19:19
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_WOFFSET                   0x0
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_ACTIVE_LOW                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_ACTIVE_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_STATUS_0  
+#define APBDEV_PMC_WAKE_STATUS_0                        _MK_ADDR_CONST(0x14)
+#define APBDEV_PMC_WAKE_STATUS_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_WAKE_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+// pin 0-15 wake    
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_FIELD                    (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_STATUS_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RANGE                    15:0
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_NOT_SET                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SET                      _MK_ENUM_CONST(1)
+
+// RTC wake                
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_RANGE                      16:16
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_NOT_SET                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SET                        _MK_ENUM_CONST(1)
+
+// KBC wake              
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_RANGE                      17:17
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_NOT_SET                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SET                        _MK_ENUM_CONST(1)
+
+// power interrupt            
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SHIFT                  _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_RANGE                  18:18
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_NOT_SET                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SET                    _MK_ENUM_CONST(1)
+
+// external reset            
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SHIFT                  _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_RANGE                  19:19
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_NOT_SET                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SET                    _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SW_WAKE_STATUS_0  
+#define APBDEV_PMC_SW_WAKE_STATUS_0                     _MK_ADDR_CONST(0x18)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0xfffff)
+// pin 0-15 wake    
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_FIELD                 (_MK_MASK_CONST(0xffff) << APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RANGE                 15:0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_WOFFSET                       0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_ENABLE                        _MK_ENUM_CONST(1)
+
+// RTC wake                
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_RANGE                   16:16
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_WOFFSET                 0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_ENABLE                  _MK_ENUM_CONST(1)
+
+// KBC wake              
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SHIFT                   _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_RANGE                   17:17
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_WOFFSET                 0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_ENABLE                  _MK_ENUM_CONST(1)
+
+// power interrupt            
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SHIFT                       _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_RANGE                       18:18
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_WOFFSET                     0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_NOT_SET                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SET                 _MK_ENUM_CONST(1)
+
+// external reset            
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SHIFT                       _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_RANGE                       19:19
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_WOFFSET                     0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_NOT_SET                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SET                 _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_PADS_ORIDE_0  
+#define APBDEV_PMC_DPD_PADS_ORIDE_0                     _MK_ADDR_CONST(0x1c)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_RESET_VAL                   _MK_MASK_CONST(0x200000)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_RESET_MASK                  _MK_MASK_CONST(0x3fffff)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffff)
+//override dpd idle state with column 0 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_RANGE                      0:0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 1 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_RANGE                      1:1
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 2 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_RANGE                      2:2
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 3 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_RANGE                      3:3
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 4 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_RANGE                      4:4
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 5 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SHIFT                      _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_RANGE                      5:5
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 6 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SHIFT                      _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_RANGE                      6:6
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 7 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SHIFT                      _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_RANGE                      7:7
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 8 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_RANGE                      8:8
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 9 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_RANGE                      9:9
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 10 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_RANGE                     10:10
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 11 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SHIFT                     _MK_SHIFT_CONST(11)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_RANGE                     11:11
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 12 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SHIFT                     _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_RANGE                     12:12
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 0  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SHIFT                      _MK_SHIFT_CONST(13)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_RANGE                      13:13
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 1  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SHIFT                      _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_RANGE                      14:14
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 2  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_RANGE                      15:15
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 3  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_RANGE                      16:16
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 4  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_RANGE                      17:17
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 5  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SHIFT                      _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_RANGE                      18:18
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 6  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SHIFT                      _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_RANGE                      19:19
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with blink ouptut
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SHIFT                 _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_RANGE                 20:20
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_WOFFSET                       0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_ENABLE                        _MK_ENUM_CONST(1)
+
+//override dpd idle state with column with sys_clk_request output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT                       _MK_SHIFT_CONST(21)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_RANGE                       21:21
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_WOFFSET                     0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_SAMPLE_0  
+#define APBDEV_PMC_DPD_SAMPLE_0                 _MK_ADDR_CONST(0x20)
+#define APBDEV_PMC_DPD_SAMPLE_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_DPD_SAMPLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+// will set sampling of pads value
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_SAMPLE_0_ON_SHIFT)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_RANGE                        0:0
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_WOFFSET                      0x0
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_ENABLE_0  
+#define APBDEV_PMC_DPD_ENABLE_0                 _MK_ADDR_CONST(0x24)
+#define APBDEV_PMC_DPD_ENABLE_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_DPD_ENABLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+// will set sampling of pads value
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_ENABLE_0_ON_SHIFT)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_RANGE                        0:0
+#define APBDEV_PMC_DPD_ENABLE_0_ON_WOFFSET                      0x0
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGATE_TIMER_OFF_0  
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0                  _MK_ADDR_CONST(0x28)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RESET_VAL                        _MK_MASK_CONST(0xeca97531)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// timer value for rail 0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_RANGE                      3:0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 1
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_RANGE                      7:4
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 2
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_RANGE                      11:8
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_DEFAULT                    _MK_MASK_CONST(0x5)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 3
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SHIFT                      _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_RANGE                      15:12
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_DEFAULT                    _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 4
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_RANGE                      19:16
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_DEFAULT                    _MK_MASK_CONST(0x9)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 5
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SHIFT                      _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_RANGE                      23:20
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_DEFAULT                    _MK_MASK_CONST(0xa)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 6
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SHIFT                      _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_RANGE                      27:24
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_DEFAULT                    _MK_MASK_CONST(0xc)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 7
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_RANGE                      31:28
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_DEFAULT                    _MK_MASK_CONST(0xe)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PWRGATE_TIMER_ON_0  
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0                   _MK_ADDR_CONST(0x2c)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RESET_VAL                         _MK_MASK_CONST(0xeca97531)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// timer value for rail 0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_RANGE                       3:0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 1
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_RANGE                       7:4
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 2
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SHIFT                       _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_RANGE                       11:8
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_DEFAULT                     _MK_MASK_CONST(0x5)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 3
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_RANGE                       15:12
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_DEFAULT                     _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 4
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_RANGE                       19:16
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_DEFAULT                     _MK_MASK_CONST(0x9)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 5
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SHIFT                       _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_RANGE                       23:20
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_DEFAULT                     _MK_MASK_CONST(0xa)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 6
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SHIFT                       _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_RANGE                       27:24
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_DEFAULT                     _MK_MASK_CONST(0xc)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 7
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SHIFT                       _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_RANGE                       31:28
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_DEFAULT                     _MK_MASK_CONST(0xe)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PWRGATE_TOGGLE_0  
+#define APBDEV_PMC_PWRGATE_TOGGLE_0                     _MK_ADDR_CONST(0x30)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_RESET_MASK                  _MK_MASK_CONST(0x103)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_READ_MASK                   _MK_MASK_CONST(0x103)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_WRITE_MASK                  _MK_MASK_CONST(0x103)
+//id of partition to be toggled 
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_FIELD                        (_MK_MASK_CONST(0x3) << APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SHIFT)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_RANGE                        1:0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_WOFFSET                      0x0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_CP                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_TD                   _MK_ENUM_CONST(1)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_VE                   _MK_ENUM_CONST(2)
+
+//start power down/up
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_TOGGLE_0_START_SHIFT)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_RANGE                 8:8
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_WOFFSET                       0x0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_REMOVE_CLAMPING_CMD_0  
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0                        _MK_ADDR_CONST(0x34)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_RESET_MASK                     _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_READ_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
+//remove clamping to CPU
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_RANGE                      0:0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_ENABLE                     _MK_ENUM_CONST(1)
+
+//remove clamping to TD
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SHIFT                       _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_RANGE                       1:1
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_WOFFSET                     0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_ENABLE                      _MK_ENUM_CONST(1)
+
+//remove clamping to VE
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SHIFT                       _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_RANGE                       2:2
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_WOFFSET                     0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGATE_STATUS_0  
+#define APBDEV_PMC_PWRGATE_STATUS_0                     _MK_ADDR_CONST(0x38)
+#define APBDEV_PMC_PWRGATE_STATUS_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_PWRGATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+//status of CPU partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_RANGE                   0:0
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_ON                      _MK_ENUM_CONST(1)
+
+//status of TD  Partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SHIFT                    _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_TD_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_RANGE                    1:1
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_WOFFSET                  0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_ON                       _MK_ENUM_CONST(1)
+
+//status of VE  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SHIFT                    _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_VE_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_RANGE                    2:2
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_WOFFSET                  0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_ON                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGOOD_TIMER_0  
+#define APBDEV_PMC_PWRGOOD_TIMER_0                      _MK_ADDR_CONST(0x3c)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_PWRGOOD_TIMER_0_RESET_VAL                    _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+// timer data
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_FIELD                   (_MK_MASK_CONST(0x7f) << APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SHIFT)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_RANGE                   6:0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_DEFAULT                 _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BLINK_TIMER_0  
+#define APBDEV_PMC_BLINK_TIMER_0                        _MK_ADDR_CONST(0x40)
+#define APBDEV_PMC_BLINK_TIMER_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_BLINK_TIMER_0_RESET_VAL                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// time on 
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_FIELD                  (_MK_MASK_CONST(0x7fff) << APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_RANGE                  14:0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_WOFFSET                        0x0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_DEFAULT                        _MK_MASK_CONST(0x7fff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// if 0 32khz clock 
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_RANGE                      15:15
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_WOFFSET                    0x0
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// time off         
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SHIFT                 _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_FIELD                 (_MK_MASK_CONST(0xffff) << APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_RANGE                 31:16
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_WOFFSET                       0x0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_DEFAULT                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_NO_IOPOWER_0  
+#define APBDEV_PMC_NO_IOPOWER_0                 _MK_ADDR_CONST(0x44)
+#define APBDEV_PMC_NO_IOPOWER_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_NO_IOPOWER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
+#define APBDEV_PMC_NO_IOPOWER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
+#define APBDEV_PMC_NO_IOPOWER_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff)
+//rail ao IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_AO_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_AO_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_RANGE                        0:0
+#define APBDEV_PMC_NO_IOPOWER_0_AO_WOFFSET                      0x0
+#define APBDEV_PMC_NO_IOPOWER_0_AO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_AO_ENABLE                       _MK_ENUM_CONST(1)
+
+//rail at3 IOs 
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_SHIFT                       _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_AT3_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_RANGE                       1:1
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_AT3_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail dbg IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_SHIFT                       _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_DBG_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_RANGE                       2:2
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_DBG_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail dlcd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_DLCD_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_RANGE                      3:3
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_WOFFSET                    0x0
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_DLCD_ENABLE                     _MK_ENUM_CONST(1)
+
+//rail dvi IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_DVI_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_RANGE                       4:4
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_DVI_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail i2s IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_I2S_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_RANGE                       5:5
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_I2S_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail lcd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SHIFT                       _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_LCD_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_RANGE                       6:6
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail mem IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SHIFT                       _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_MEM_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_RANGE                       7:7
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail sd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SHIFT                        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_SD_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_RANGE                        8:8
+#define APBDEV_PMC_NO_IOPOWER_0_SD_WOFFSET                      0x0
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_ENABLE                       _MK_ENUM_CONST(1)
+
+//rail mipi IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_MIPI_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_RANGE                      9:9
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_WOFFSET                    0x0
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWR_DET_0  
+#define APBDEV_PMC_PWR_DET_0                    _MK_ADDR_CONST(0x48)
+#define APBDEV_PMC_PWR_DET_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_PWR_DET_0_RESET_VAL                  _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_RESET_MASK                         _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
+//rail ao IOs   
+#define APBDEV_PMC_PWR_DET_0_AO_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_AO_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_AO_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_AO_RANGE                   0:0
+#define APBDEV_PMC_PWR_DET_0_AO_WOFFSET                 0x0
+#define APBDEV_PMC_PWR_DET_0_AO_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AO_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AO_ENABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_AO_DISABLE                 _MK_ENUM_CONST(1)
+
+//rail at3 IOs 
+#define APBDEV_PMC_PWR_DET_0_AT3_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PWR_DET_0_AT3_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_AT3_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_AT3_RANGE                  1:1
+#define APBDEV_PMC_PWR_DET_0_AT3_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_AT3_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AT3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AT3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AT3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AT3_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_AT3_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail dbg IOs   
+#define APBDEV_PMC_PWR_DET_0_DBG_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PWR_DET_0_DBG_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_DBG_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_DBG_RANGE                  2:2
+#define APBDEV_PMC_PWR_DET_0_DBG_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_DBG_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DBG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DBG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DBG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DBG_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_DBG_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail dlcd IOs   
+#define APBDEV_PMC_PWR_DET_0_DLCD_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_PWR_DET_0_DLCD_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_DLCD_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_DLCD_RANGE                 3:3
+#define APBDEV_PMC_PWR_DET_0_DLCD_WOFFSET                       0x0
+#define APBDEV_PMC_PWR_DET_0_DLCD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DLCD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DLCD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DLCD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DLCD_ENABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_DLCD_DISABLE                       _MK_ENUM_CONST(1)
+
+//rail dvi IOs   
+#define APBDEV_PMC_PWR_DET_0_DVI_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWR_DET_0_DVI_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_DVI_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_DVI_RANGE                  4:4
+#define APBDEV_PMC_PWR_DET_0_DVI_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_DVI_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DVI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_DVI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DVI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_DVI_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_DVI_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail i2s IOs   
+#define APBDEV_PMC_PWR_DET_0_I2S_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_PWR_DET_0_I2S_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_I2S_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_I2S_RANGE                  5:5
+#define APBDEV_PMC_PWR_DET_0_I2S_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_I2S_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_I2S_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_I2S_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_I2S_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_I2S_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_I2S_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail lcd IOs   
+#define APBDEV_PMC_PWR_DET_0_LCD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_PWR_DET_0_LCD_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_LCD_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_LCD_RANGE                  6:6
+#define APBDEV_PMC_PWR_DET_0_LCD_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_LCD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_LCD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_LCD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_LCD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_LCD_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_LCD_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail mem IOs   
+#define APBDEV_PMC_PWR_DET_0_MEM_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_PWR_DET_0_MEM_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_MEM_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_MEM_RANGE                  7:7
+#define APBDEV_PMC_PWR_DET_0_MEM_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_MEM_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_MEM_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_MEM_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail sd IOs   
+#define APBDEV_PMC_PWR_DET_0_SD_SHIFT                   _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWR_DET_0_SD_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_SD_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_SD_RANGE                   8:8
+#define APBDEV_PMC_PWR_DET_0_SD_WOFFSET                 0x0
+#define APBDEV_PMC_PWR_DET_0_SD_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SD_ENABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_SD_DISABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWR_DET_LATCH_0  
+#define APBDEV_PMC_PWR_DET_LATCH_0                      _MK_ADDR_CONST(0x4c)
+#define APBDEV_PMC_PWR_DET_LATCH_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_PWR_DET_LATCH_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+//power detect latch, latches value as long set to 1  
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SHIFT)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_RANGE                  0:0
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SCRATCH0_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH0_0                   _MK_ADDR_CONST(0x50)
+#define APBDEV_PMC_SCRATCH0_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage 
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_FIELD                    (_MK_MASK_CONST(0x7fffffff) << APBDEV_PMC_SCRATCH0_0_SCRATCH0_SHIFT)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_RANGE                    30:0
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_DEFAULT_MASK                     _MK_MASK_CONST(0x7fffffff)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// reset power detect latch to 3.3V
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_SHIFT                 _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_SHIFT)
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_RANGE                 31:31
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_WOFFSET                       0x0
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH1_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH1_0                   _MK_ADDR_CONST(0x54)
+#define APBDEV_PMC_SCRATCH1_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH1_0_SCRATCH1_SHIFT)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH2_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH2_0                   _MK_ADDR_CONST(0x58)
+#define APBDEV_PMC_SCRATCH2_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH2_0_SCRATCH2_SHIFT)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH3_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH3_0                   _MK_ADDR_CONST(0x5c)
+#define APBDEV_PMC_SCRATCH3_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH3_0_SCRATCH3_SHIFT)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH4_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH4_0                   _MK_ADDR_CONST(0x60)
+#define APBDEV_PMC_SCRATCH4_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH4_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH4_0_SCRATCH4_SHIFT)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH5_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH5_0                   _MK_ADDR_CONST(0x64)
+#define APBDEV_PMC_SCRATCH5_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH5_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH5_0_SCRATCH5_SHIFT)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH6_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH6_0                   _MK_ADDR_CONST(0x68)
+#define APBDEV_PMC_SCRATCH6_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH6_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH6_0_SCRATCH6_SHIFT)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH7_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH7_0                   _MK_ADDR_CONST(0x6c)
+#define APBDEV_PMC_SCRATCH7_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH7_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH7_0_SCRATCH7_SHIFT)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH8_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH8_0                   _MK_ADDR_CONST(0x70)
+#define APBDEV_PMC_SCRATCH8_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH8_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH8_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH8_0_SCRATCH8_SHIFT)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH9_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH9_0                   _MK_ADDR_CONST(0x74)
+#define APBDEV_PMC_SCRATCH9_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH9_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH9_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH9_0_SCRATCH9_SHIFT)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH10_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH10_0                  _MK_ADDR_CONST(0x78)
+#define APBDEV_PMC_SCRATCH10_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH10_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH10_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH10_0_SCRATCH10_SHIFT)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH11_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH11_0                  _MK_ADDR_CONST(0x7c)
+#define APBDEV_PMC_SCRATCH11_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH11_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH11_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH11_0_SCRATCH11_SHIFT)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH12_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH12_0                  _MK_ADDR_CONST(0x80)
+#define APBDEV_PMC_SCRATCH12_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH12_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH12_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH12_0_SCRATCH12_SHIFT)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH13_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH13_0                  _MK_ADDR_CONST(0x84)
+#define APBDEV_PMC_SCRATCH13_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH13_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH13_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH13_0_SCRATCH13_SHIFT)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH14_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH14_0                  _MK_ADDR_CONST(0x88)
+#define APBDEV_PMC_SCRATCH14_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH14_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH14_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH14_0_SCRATCH14_SHIFT)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH15_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH15_0                  _MK_ADDR_CONST(0x8c)
+#define APBDEV_PMC_SCRATCH15_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH15_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH15_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH15_0_SCRATCH15_SHIFT)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH16_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH16_0                  _MK_ADDR_CONST(0x90)
+#define APBDEV_PMC_SCRATCH16_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH16_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH16_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH16_0_SCRATCH16_SHIFT)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH17_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH17_0                  _MK_ADDR_CONST(0x94)
+#define APBDEV_PMC_SCRATCH17_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH17_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH17_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH17_0_SCRATCH17_SHIFT)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH18_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH18_0                  _MK_ADDR_CONST(0x98)
+#define APBDEV_PMC_SCRATCH18_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH18_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH18_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH18_0_SCRATCH18_SHIFT)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH19_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH19_0                  _MK_ADDR_CONST(0x9c)
+#define APBDEV_PMC_SCRATCH19_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH19_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH19_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH19_0_SCRATCH19_SHIFT)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH20_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH20_0                  _MK_ADDR_CONST(0xa0)
+#define APBDEV_PMC_SCRATCH20_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH20_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH20_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH20_0_SCRATCH20_SHIFT)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH21_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH21_0                  _MK_ADDR_CONST(0xa4)
+#define APBDEV_PMC_SCRATCH21_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH21_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH21_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH21_0_SCRATCH21_SHIFT)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH22_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH22_0                  _MK_ADDR_CONST(0xa8)
+#define APBDEV_PMC_SCRATCH22_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH22_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH22_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH22_0_SCRATCH22_SHIFT)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH23_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH23_0                  _MK_ADDR_CONST(0xac)
+#define APBDEV_PMC_SCRATCH23_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH23_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH23_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH23_0_SCRATCH23_SHIFT)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH0_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH0_0                    _MK_ADDR_CONST(0xb0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH1_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH1_0                    _MK_ADDR_CONST(0xb4)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH2_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH2_0                    _MK_ADDR_CONST(0xb8)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH3_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH3_0                    _MK_ADDR_CONST(0xbc)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBPM_REGS(_op_) \
+_op_(APBDEV_PMC_CNTRL_0) \
+_op_(APBDEV_PMC_SEC_DISABLE_0) \
+_op_(APBDEV_PMC_PMC_SWRST_0) \
+_op_(APBDEV_PMC_WAKE_MASK_0) \
+_op_(APBDEV_PMC_WAKE_LVL_0) \
+_op_(APBDEV_PMC_WAKE_STATUS_0) \
+_op_(APBDEV_PMC_SW_WAKE_STATUS_0) \
+_op_(APBDEV_PMC_DPD_PADS_ORIDE_0) \
+_op_(APBDEV_PMC_DPD_SAMPLE_0) \
+_op_(APBDEV_PMC_DPD_ENABLE_0) \
+_op_(APBDEV_PMC_PWRGATE_TIMER_OFF_0) \
+_op_(APBDEV_PMC_PWRGATE_TIMER_ON_0) \
+_op_(APBDEV_PMC_PWRGATE_TOGGLE_0) \
+_op_(APBDEV_PMC_REMOVE_CLAMPING_CMD_0) \
+_op_(APBDEV_PMC_PWRGATE_STATUS_0) \
+_op_(APBDEV_PMC_PWRGOOD_TIMER_0) \
+_op_(APBDEV_PMC_BLINK_TIMER_0) \
+_op_(APBDEV_PMC_NO_IOPOWER_0) \
+_op_(APBDEV_PMC_PWR_DET_0) \
+_op_(APBDEV_PMC_PWR_DET_LATCH_0) \
+_op_(APBDEV_PMC_SCRATCH0_0) \
+_op_(APBDEV_PMC_SCRATCH1_0) \
+_op_(APBDEV_PMC_SCRATCH2_0) \
+_op_(APBDEV_PMC_SCRATCH3_0) \
+_op_(APBDEV_PMC_SCRATCH4_0) \
+_op_(APBDEV_PMC_SCRATCH5_0) \
+_op_(APBDEV_PMC_SCRATCH6_0) \
+_op_(APBDEV_PMC_SCRATCH7_0) \
+_op_(APBDEV_PMC_SCRATCH8_0) \
+_op_(APBDEV_PMC_SCRATCH9_0) \
+_op_(APBDEV_PMC_SCRATCH10_0) \
+_op_(APBDEV_PMC_SCRATCH11_0) \
+_op_(APBDEV_PMC_SCRATCH12_0) \
+_op_(APBDEV_PMC_SCRATCH13_0) \
+_op_(APBDEV_PMC_SCRATCH14_0) \
+_op_(APBDEV_PMC_SCRATCH15_0) \
+_op_(APBDEV_PMC_SCRATCH16_0) \
+_op_(APBDEV_PMC_SCRATCH17_0) \
+_op_(APBDEV_PMC_SCRATCH18_0) \
+_op_(APBDEV_PMC_SCRATCH19_0) \
+_op_(APBDEV_PMC_SCRATCH20_0) \
+_op_(APBDEV_PMC_SCRATCH21_0) \
+_op_(APBDEV_PMC_SCRATCH22_0) \
+_op_(APBDEV_PMC_SCRATCH23_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH0_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH1_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH2_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH3_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDEV_PMC 0x00000000
+
+//
+// ARAPBPM REGISTER BANKS
+//
+
+#define APBDEV_PMC0_FIRST_REG 0x0000 // APBDEV_PMC_CNTRL_0
+#define APBDEV_PMC0_LAST_REG 0x00bc // APBDEV_PMC_SECURE_SCRATCH3_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBPM_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/ararb_sema.h b/arch/arm/mach-tegra/nv/include/ap15/ararb_sema.h
new file mode 100644
index 000000000000..adc9b4af14b0
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/ararb_sema.h
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARARB_SEMA_H_INC_
+#define ___ARARB_SEMA_H_INC_
+// Arbitration semaphores provide a mechanism by which the two processors can arbitrate
+// for the use of various resources. These semaphores provide a hardware locking mechanism,
+// so that when a processor is already using a resource, the second processor is not 
+// granted that resource. There are 32 bits of Arbitration semaphores provided in the system.
+// The hardware does not enforce any resource association to these bits. It is left to the
+// firmware to assign and use these bits.
+// Any processor that needs to access a particular resource will request for the 
+// corresponding bit in the Arbitration semaphores by writing a one to that bit in the 
+// Arbitration Semaphore Request register (SMP_GET register). Firmware will then
+// check the corresponding bit in the Semaphore Granted Status register (SMP_GNT_ST register) 
+// If the requesting processor has been granted the resource, then the status returned will
+// be a one. 
+// Alternately, the processor can configure the interrupt controller to generate an
+// interrupt when the resource becomes available. Refer to the arictlr_arbgnt specfile for details. 
+// When the processor has finished using the resource, it releases the resource by writing a one
+// to the corresponding bit in the Arbitration Semaphore Put Request register 
+// (SMP_PUT register).  Additionally, pending request status is provided through the
+// Arbitration Request Pending Status register (SMP_REQ_ST register).
+// Semaphore Granted Status Register
+
+// Register ARB_SEMA_SMP_GNT_ST_0  
+#define ARB_SEMA_SMP_GNT_ST_0                   _MK_ADDR_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_WORD_COUNT                        0x1
+#define ARB_SEMA_SMP_GNT_ST_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_GNT_ST_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_GNT_ST_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// A one in any bit indicates that the processor  reading this register as granted status for that bit. A zero indicates  semaphore not granted.
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_FIELD                        (_MK_MASK_CONST(0xffffffff) << ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_SHIFT)
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_RANGE                        31:0
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_WOFFSET                      0x0
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GNT_ST_0_ARB_31_ARB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Request Arbitration Semaphore Register
+
+// Register ARB_SEMA_SMP_GET_0  
+#define ARB_SEMA_SMP_GET_0                      _MK_ADDR_CONST(0x4)
+#define ARB_SEMA_SMP_GET_0_WORD_COUNT                   0x1
+#define ARB_SEMA_SMP_GET_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_GET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Writing a one in any bit is a request for that  semaphore bit by the processor performing the register write.
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_FIELD                   (_MK_MASK_CONST(0xffffffff) << ARB_SEMA_SMP_GET_0_GET_31_GET_0_SHIFT)
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_RANGE                   31:0
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_WOFFSET                 0x0
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_GET_0_GET_31_GET_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Arbitration Semaphore Put Request Register
+
+// Register ARB_SEMA_SMP_PUT_0  
+#define ARB_SEMA_SMP_PUT_0                      _MK_ADDR_CONST(0x8)
+#define ARB_SEMA_SMP_PUT_0_WORD_COUNT                   0x1
+#define ARB_SEMA_SMP_PUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_PUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Writing a one in any bit will clear the  corresponding semaphore bit by the processor performing the register write. 
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_FIELD                   (_MK_MASK_CONST(0xffffffff) << ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_SHIFT)
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_RANGE                   31:0
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_WOFFSET                 0x0
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_PUT_0_PUT_31_PUT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Arbitration Request Pending Status (1=PENDING) Register
+
+// Register ARB_SEMA_SMP_REQ_ST_0  
+#define ARB_SEMA_SMP_REQ_ST_0                   _MK_ADDR_CONST(0xc)
+#define ARB_SEMA_SMP_REQ_ST_0_WORD_COUNT                        0x1
+#define ARB_SEMA_SMP_REQ_ST_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_REQ_ST_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_REQ_ST_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_REQ_ST_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_REQ_ST_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_REQ_ST_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// A one in any bit indicates a request pending status.  The corresponding bits are set when the request for the individual resource  is pending. The read by CPU of this register shows the pending status for CPU  and a read of this register by AVP (COP) shows the pending status for AVP.
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_FIELD                        (_MK_MASK_CONST(0xffffffff) << ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_SHIFT)
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_RANGE                        31:0
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_WOFFSET                      0x0
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARB_SEMA_SMP_REQ_ST_0_REQ_31_REQ_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARARB_SEMA_REGS(_op_) \
+_op_(ARB_SEMA_SMP_GNT_ST_0) \
+_op_(ARB_SEMA_SMP_GET_0) \
+_op_(ARB_SEMA_SMP_PUT_0) \
+_op_(ARB_SEMA_SMP_REQ_ST_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_ARB_SEMA   0x00000000
+
+//
+// ARARB_SEMA REGISTER BANKS
+//
+
+#define ARB_SEMA0_FIRST_REG 0x0000 // ARB_SEMA_SMP_GNT_ST_0
+#define ARB_SEMA0_LAST_REG 0x000c // ARB_SEMA_SMP_REQ_ST_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARARB_SEMA_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arclk_rst.h b/arch/arm/mach-tegra/nv/include/ap15/arclk_rst.h
new file mode 100644
index 000000000000..538e8935ba35
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arclk_rst.h
@@ -0,0 +1,7272 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARCLK_RST_H_INC_
+#define ___ARCLK_RST_H_INC_
+
+// Register CLK_RST_CONTROLLER_RST_SOURCE_0  
+#define CLK_RST_CONTROLLER_RST_SOURCE_0                 _MK_ADDR_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_RESET_MASK                      _MK_MASK_CONST(0x3f37)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_READ_MASK                       _MK_MASK_CONST(0x3f37)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WRITE_MASK                      _MK_MASK_CONST(0x37)
+// System reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SHIFT                   _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_RANGE                   13:13
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// System reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// COP reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// COP reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_RANGE                   10:10
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CPU reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CPU reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Enable Watch Dog Timer (Dead Man Timer)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Watch Dog Timer Select 
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_RANGE                   4:4
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_INIT_ENUM                       TIMER1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_TIMER1                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_TIMER2                  _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for system.
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SHIFT                    _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_RANGE                    2:2
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for COP
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for CPU
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEVICES_L_0  
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0                      _MK_ADDR_CONST(0x4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_RESET_VAL                    _MK_MASK_CONST(0x7ffffec9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Reset COP cache controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_RANGE                 31:31
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset CPU cache controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_RANGE                 30:30
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE1_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset vector co-processor.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset HOST1X.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_RANGE                 28:28
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset DISP1 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_RANGE                  27:27
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset DISP2 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_RANGE                  26:26
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset IDE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset 3D controlelr.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_RANGE                     24:24
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset ISP controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_RANGE                    23:23
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset USB controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset 2D graphics engine controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_RANGE                     21:21
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset VI controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_RANGE                     20:20
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset EPP controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_RANGE                    19:19
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset I2S 2 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset Pulse Width Modulator
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset Three Wire Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset HSMMC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_SHIFT                  _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_RANGE                  15:15
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HSMMC_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset SDIO1 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_SHIFT                  _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_RANGE                  14:14
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO1_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset NAND flash controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_RANGE                        13:13
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_INIT_ENUM                    ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset I2C1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset I2S 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SPDIF Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_RANGE                  10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset SDIO2 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_RANGE                  9:9
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDIO2_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset GPIO Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_RANGE                  7:7
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset UARTA Controller 
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_RANGE                  6:6
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset Timer Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset RTC Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset AC97 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Write 1 to pulse System Reset Signal. HW clears  this bit
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SHIFT                       _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_RANGE                       2:2
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Write 1 to force COP Reset Signal. SW needs to  clear this bit when done.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Write 1 to force CPU Reset Signal. SW needs to  clear this bit when done.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEVICES_H_0  
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0                      _MK_ADDR_CONST(0x8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_RESET_VAL                    _MK_MASK_CONST(0xf3fffb77)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_RESET_MASK                   _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_READ_MASK                    _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_WRITE_MASK                   _MK_MASK_CONST(0xf3fffff7)
+// Reset BSEV controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_RANGE                   31:31
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset BSEA controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_RANGE                   30:30
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset VDE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset MPE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset EMC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset SPROM Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_RANGE                  24:24
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPROM_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset UART C Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_RANGE                  23:23
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset I2C 2 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset TVDAC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_RANGE                  21:21
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset CSI controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_RANGE                    20:20
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset HDMI
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_RANGE                   19:19
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset MIPI base-band controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset TVO/CVE controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset DSI controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset DVC-I2C Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_RANGE                        15:15
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_INIT_ENUM                    ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset SBC 3 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_RANGE                   14:14
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset XIO controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_RANGE                    13:13
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset SBC 2 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SPI 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_RANGE                    10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset SBC 1 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset Serial Link Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SLC1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset Fuse controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_RANGE                   7:7
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset PMC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_RANGE                    6:6
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset statistic monitor
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_INIT_ENUM                   ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Reset Keyboard controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset APB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_RANGE                 2:2
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset AHB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_RANGE                 1:1
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset MC.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Reserved address 12 [0xc] 
+
+// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0  
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0                      _MK_ADDR_CONST(0x10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_RESET_VAL                    _MK_MASK_CONST(0x80000130)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_RESET_MASK                   _MK_MASK_CONST(0xfffffff9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_READ_MASK                    _MK_MASK_CONST(0xfffffff9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffff9)
+// Enable clock to COP cache controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_RANGE                 31:31
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to CPU cache controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_RANGE                 30:30
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to vector co-processor.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_RANGE                    29:29
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to HOST1X.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_RANGE                 28:28
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to DISP1 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_RANGE                  27:27
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to DISP2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to IDE controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_RANGE                    25:25
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to 3D controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_RANGE                     24:24
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to ISP controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_RANGE                    23:23
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to USB controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_RANGE                   22:22
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to 2D graphics engine.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_RANGE                     21:21
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to VI controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_RANGE                     20:20
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to EPP controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_RANGE                    19:19
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to I2S 2 controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_RANGE                   18:18
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_RANGE                    17:17
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_RANGE                    16:16
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to HSMMC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_SHIFT                  _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_RANGE                  15:15
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HSMMC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to SDIO1 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_SHIFT                  _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_RANGE                  14:14
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to NAND flash controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_RANGE                        13:13
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable clock to I2C1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_RANGE                   12:12
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to I2S1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_RANGE                   11:11
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SPDIF Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_RANGE                  10:10
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to SDIO2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_RANGE                  9:9
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDIO2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to GPIO Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_RANGE                   8:8
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_RANGE                  7:7
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to UARTA Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_RANGE                  6:6
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to Timer Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_RANGE                    5:5
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to RTC Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_RANGE                    4:4
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to AC97 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_RANGE                   3:3
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to CPU.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_RANGE                    0:0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0  
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0                      _MK_ADDR_CONST(0x14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_RESET_VAL                    _MK_MASK_CONST(0x480)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_RESET_MASK                   _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_READ_MASK                    _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_WRITE_MASK                   _MK_MASK_CONST(0xf3fffff7)
+// Enable clock to BSEV Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_RANGE                   31:31
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to BSEA Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_RANGE                   30:30
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to VDE Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_RANGE                    29:29
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to MPE controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to EMC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_RANGE                    25:25
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to SPROM Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_RANGE                  24:24
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPROM_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to UART-C Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to I2C2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_RANGE                   22:22
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to TVDAC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_RANGE                  21:21
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to CSI controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_RANGE                    20:20
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to HDMI
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_RANGE                   19:19
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to MIPI base-band controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_RANGE                   18:18
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to TVO/CVE controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_RANGE                    17:17
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to DSI controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_RANGE                    16:16
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to DVC-I2C Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_RANGE                        15:15
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 3 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_RANGE                   14:14
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to XIO Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_RANGE                    13:13
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 2 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_RANGE                   12:12
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SPI 1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_RANGE                   11:11
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_RANGE                    10:10
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 1 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_RANGE                   9:9
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to Serial Link Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_RANGE                   8:8
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SLC1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to FUSE controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_RANGE                   7:7
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to PMC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_RANGE                    6:6
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to statistic monitor.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_RANGE                       5:5
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable clock to keyboard controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_RANGE                    4:4
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to APB-DMA.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_RANGE                 2:2
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to AHB-DMA.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_RANGE                 1:1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to MC/EMC.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_RANGE                    0:0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+
+// Register CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0  
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0                  _MK_ADDR_CONST(0x20)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_RESET_VAL                        _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_RESET_MASK                       _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_READ_MASK                        _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_WRITE_MASK                       _MK_MASK_CONST(0xff007777)
+// 0000=32KHz Clock source; 
+// 0001=IDLE Clock Source;
+// 001X=Run clock source; 
+// 01XX=IRQ Clock Source;
+// 1XXX=FIQ Clock Source
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_RANGE                  31:28
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_STDBY                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_IDLE                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_RUN                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_IRQ                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_FIQ                    _MK_ENUM_CONST(8)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_RANGE                  27:27
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_RANGE                  25:25
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_RANGE                  24:24
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  000 = clk_m,
+//  001 = pllC_out0,
+//  010 = clk_s,
+//  011 = pllM_out0,
+//  100 = pllP_out0,
+//  101 = pllP_out4,
+//  110 = pllP_out3,
+//  111 = clk_d,
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_RANGE                 14:12
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+
+//  Same definitions as CWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_RANGE                 10:8
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+
+//  Same definitions as CWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_RANGE                 6:4
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+
+//  Same definitions as CWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_FIELD                        (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_RANGE                        2:0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKM                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLC_OUT0                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKS                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLM_OUT0                    _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT0                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT4                    _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT3                    _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKD                 _MK_ENUM_CONST(7)
+
+
+// Register CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0  
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0                 _MK_ADDR_CONST(0x24)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_RESET_MASK                      _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_READ_MASK                       _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_WRITE_MASK                      _MK_MASK_CONST(0x8f00ffff)
+//  0 = disable divider.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_RANGE                    31:31
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_RANGE                       27:27
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_RANGE                       26:26
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_RANGE                       25:25
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_RANGE                       24:24
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_RANGE                       15:8
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_RANGE                        7:0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0  
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0                  _MK_ADDR_CONST(0x28)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_RESET_VAL                        _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_RESET_MASK                       _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_READ_MASK                        _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_WRITE_MASK                       _MK_MASK_CONST(0xff007777)
+// 0000=32KHz Clock source; 
+// 0001=IDLE Clock Source;
+// 001X=Run clock source; 
+// 01XX=IRQ Clock Source;
+// 1XXX=FIQ Clock Source
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_RANGE                  31:28
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_STDBY                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_IDLE                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_RUN                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_IRQ                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_FIQ                    _MK_ENUM_CONST(8)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_RANGE                  27:27
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_RANGE                  26:26
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_RANGE                  25:25
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_RANGE                  24:24
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  000 = clk_m,
+//  001 = pllC_out1,
+//  010 = pllP_out4,
+//  011 = pllP_out3,
+//  100 = pllP_out2,
+//  101 = clk_d,
+//  110 = clk_s,
+//  111 = pllM_out1,
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_RANGE                 14:12
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_RANGE                 10:8
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_RANGE                 6:4
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_FIELD                        (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_RANGE                        2:0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKM                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLC_OUT1                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT4                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT3                    _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT2                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKD                 _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKS                 _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLM_OUT1                    _MK_ENUM_CONST(7)
+
+
+// Register CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0  
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0                 _MK_ADDR_CONST(0x2c)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_RESET_MASK                      _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_READ_MASK                       _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_WRITE_MASK                      _MK_MASK_CONST(0x8f00ffff)
+//  0 = disable divider.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_RANGE                    31:31
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_RANGE                       27:27
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_RANGE                       26:26
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_RANGE                       25:25
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_RANGE                       24:24
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_RANGE                       15:8
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_RANGE                        7:0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0  
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0                    _MK_ADDR_CONST(0x30)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_RESET_MASK                         _MK_MASK_CONST(0xf00f00bb)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_READ_MASK                  _MK_MASK_CONST(0xf00f00bb)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_WRITE_MASK                         _MK_MASK_CONST(0xf00f00bb)
+//  0 = Enable AUDIO SYNC CLK
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_RANGE                 31:31
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 000 = SPDIFIN recovered bit clock.
+// 001 = I2S1 bit clock.
+// 010 = I2S2 bit clock.
+// 011 = AC97 bit clock.
+// 100 = pllA_out0.
+// 101 = external audio clock (dap_mclk2).
+// 110 = external audio clock (dap_mclk1).
+// 111 = external vimclk (vimclk).
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_FIELD                        (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_RANGE                        30:28
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_SPDIFIN                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_I2S1                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_I2S2                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_AC97                 _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_PLLA_OUT0                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_EXT_AUDIO_CLK2                       _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_EXT_AUDIO_CLK1                       _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SYNC_CLK_RATE_EXT_VIMCLK                   _MK_ENUM_CONST(7)
+
+// (n+1)/16 of SCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_FIELD                    (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_RANGE                    19:16
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_VCLK_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0=enable HCLK, 1=disable HCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_RANGE                     7:7
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1/(n+1) of SCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SHIFT                     _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_RANGE                     5:4
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  0=enable PCLK, 1=disable PCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT                     _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_RANGE                     3:3
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1/(n+1) of HCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_RANGE                     1:0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PROG_DLY_CLK_0  
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0                       _MK_ADDR_CONST(0x34)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_RESET_VAL                     _MK_MASK_CONST(0x7700)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_RESET_MASK                    _MK_MASK_CONST(0xff00)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_READ_MASK                     _MK_MASK_CONST(0xff00)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_WRITE_MASK                    _MK_MASK_CONST(0xff00)
+// 16 Taps of selectable delay for CLK_M clk doubler
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SHIFT                        _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_RANGE                        15:12
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_DEFAULT                      _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 16 Taps of selectable delay for SYNC_CLK clk doubler
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_FIELD                     (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_RANGE                     11:8
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_DEFAULT                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Register CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0  
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0                        _MK_ADDR_CONST(0x40)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_RESET_MASK                     _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_READ_MASK                      _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_WRITE_MASK                     _MK_MASK_CONST(0xff007777)
+// 0000=no skip.
+// 0001=skip base on IDLE Clock skip rate;
+// 001X=skip base on Run clock skip rate; 
+// 01XX=skip base on IRQ Clock skip rate;
+// 1XXX=skip base on FIQ Clock skip rate
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SHIFT                       _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_FIELD                       (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_RANGE                       31:28
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_RANGE                    27:27
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SHIFT                    _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_RANGE                    26:26
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_RANGE                    25:25
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_RANGE                    24:24
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  skip n/16 clock.
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SHIFT                    _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_RANGE                    14:12
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_RANGE                    10:8
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_RANGE                    6:4
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_RANGE                   2:0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_MASK_ARM_0  
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0                       _MK_ADDR_CONST(0x44)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_MASK                    _MK_MASK_CONST(0x80010003)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_READ_MASK                     _MK_MASK_CONST(0x80010003)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WRITE_MASK                    _MK_MASK_CONST(0x10003)
+//  1 = ARM11 AXI pipe is flushed.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_RANGE                  31:31
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = HW will stop clock to CPU when halt, 0 = no clock stop.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT                       _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_RANGE                       16:16
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  00 = no clock masking.
+//  01 = u2_nwait_r.
+//  10 = u2_nwait_r.
+//  11 = no clock masking.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_FIELD                    (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_RANGE                    1:0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_MISC_CLK_ENB_0  
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0                       _MK_ADDR_CONST(0x48)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_VAL                     _MK_MASK_CONST(0x6003f)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_MASK                    _MK_MASK_CONST(0x1716003f)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_READ_MASK                     _MK_MASK_CONST(0x1716003f)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WRITE_MASK                    _MK_MASK_CONST(0x1716003f)
+// 1 = VISIBLE, 0 = NOT VISIBLE.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_RANGE                 28:28
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 1 = Enable clock to DEV1 pad.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_SHIFT                        _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_RANGE                        26:26
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV1_OUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 1 = Enable clock to DEV2 pad.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_RANGE                        25:25
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_DEV2_OUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 1 = Enable clock to SUS pad.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_SHIFT                 _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_RANGE                 24:24
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_SUS_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 1 = wait for EMC to assert EMC clock divider request.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_RANGE                 20:20
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WAIT_FOR_EMC_CLKDIV_REQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 1 = Enable CLK_M clk doubler.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_RANGE                       18:18
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_M_DOUBLER_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = Enable audio sync clk doubler.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_RANGE                    17:17
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = Enable COP cache ram clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_RANGE                   5:5
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = Enable CPU cache ram clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_RANGE                   4:4
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_CRAM1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = Enable IRAMD clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_RANGE                   3:3
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = Enable IRAMD clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_SHIFT                   _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_RANGE                   2:2
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = Enable IRAMD clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_SHIFT                   _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_RANGE                   1:1
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = Enable IRAMD clk.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_RANGE                   0:0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CLK_ENB_IRAMA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 76 [0x4c] 
+
+// Register CLK_RST_CONTROLLER_OSC_CTRL_0  
+#define CLK_RST_CONTROLLER_OSC_CTRL_0                   _MK_ADDR_CONST(0x50)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_VAL                         _MK_MASK_CONST(0x3f1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_MASK                        _MK_MASK_CONST(0xfff1f3f3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_READ_MASK                         _MK_MASK_CONST(0xfff1f3f3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xfff1f3f3)
+// 00 = 13MHz, 01 = 19.2MHz, 10 = 12MHz, 11 = 26MHz.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT                    _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_FIELD                    (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_RANGE                    31:30
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// PLL reference clock divide.  00 = /1, 01 = /2, 10 = /4, 11 = reserve.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_RANGE                 29:28
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Crystal oscillator spare register control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_RANGE                 27:20
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Crystal oscillator duty cycle control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT                        _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_FIELD                        (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_RANGE                        16:12
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator drive strength control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_FIELD                        (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_RANGE                        9:4
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT                      _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator bypass enable (1 = enable bypass).
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SHIFT                        _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_RANGE                        1:1
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator enable (1 = enable).
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_RANGE                 0:0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLL_LFSR_0  
+#define CLK_RST_CONTROLLER_PLL_LFSR_0                   _MK_ADDR_CONST(0x54)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Random number generated from PLL linear feedback shift register.
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_FIELD                 (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_RANGE                 15:0
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_0  
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0                       _MK_ADDR_CONST(0x58)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_MASK                    _MK_MASK_CONST(0x8000000f)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_READ_MASK                     _MK_MASK_CONST(0x8000000f)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WRITE_MASK                    _MK_MASK_CONST(0x8000000f)
+// 0 = default, 1 = enable osc frequency detect. 
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_RANGE                       31:31
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_ENABLE                      _MK_ENUM_CONST(1)
+
+// Indicate the # of 32KHz clock period as window in n+1 scheme.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_RANGE                 3:0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0  
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0                        _MK_ADDR_CONST(0x5c)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// 0 = not busy, 1 = busy.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_RANGE                        31:31
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// indicate the number of osc count within the 32KHz clock reference window.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_FIELD                 (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_RANGE                 15:0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 96 [0x60] 
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register CLK_RST_CONTROLLER_BOND_OUT_L_0  
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0                 _MK_ADDR_CONST(0x70)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_READ_MASK                       _MK_MASK_CONST(0xfffffff9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff9)
+// Bond out COP cache controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_RANGE                   31:31
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out CPU cache controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_RANGE                   30:30
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out vector co-processor.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SHIFT                      _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_RANGE                      29:29
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out HOST1X.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_RANGE                   28:28
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out DISP1 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_RANGE                    27:27
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out DISP2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SHIFT                    _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_RANGE                    26:26
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IDE controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SHIFT                      _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_RANGE                      25:25
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out 3D controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_RANGE                       24:24
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out ISP controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_RANGE                      23:23
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out USB controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SHIFT                     _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_RANGE                     22:22
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out 2D graphics engine.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SHIFT                       _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_RANGE                       21:21
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out VI controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SHIFT                       _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_RANGE                       20:20
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out EPP controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SHIFT                      _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_RANGE                      19:19
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out I2S 2 controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SHIFT                     _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_RANGE                     18:18
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SHIFT                      _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_RANGE                      17:17
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_RANGE                      16:16
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out HSMMC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_SHIFT                    _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_RANGE                    15:15
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HSMMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out SDIO1 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_SHIFT                    _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_RANGE                    14:14
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out NAND flash controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SHIFT                  _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_RANGE                  13:13
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bond out I2C1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_RANGE                     12:12
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out I2S1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_RANGE                     11:11
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SPDIF Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_RANGE                    10:10
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out SDIO2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_SHIFT                    _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_RANGE                    9:9
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDIO2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out GPIO Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_RANGE                     8:8
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_RANGE                    7:7
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out UARTA Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_RANGE                    6:6
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out Timer Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SHIFT                      _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_RANGE                      5:5
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out RTC Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SHIFT                      _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_RANGE                      4:4
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out AC97 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SHIFT                     _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_RANGE                     3:3
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out CPU.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_RANGE                      0:0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_BOND_OUT_H_0  
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0                 _MK_ADDR_CONST(0x74)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_RESET_MASK                      _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_READ_MASK                       _MK_MASK_CONST(0xf3fffff7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_WRITE_MASK                      _MK_MASK_CONST(0xf3fffff7)
+// Bond out BSEV Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SHIFT                     _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_RANGE                     31:31
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out BSEA Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_RANGE                     30:30
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out VDE Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SHIFT                      _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_RANGE                      29:29
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out MPE controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SHIFT                      _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_RANGE                      28:28
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out EMC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SHIFT                      _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_RANGE                      25:25
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out SPROM Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_RANGE                    24:24
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPROM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out UART-C Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_RANGE                    23:23
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out I2C2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SHIFT                     _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_RANGE                     22:22
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out TVDAC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SHIFT                    _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_RANGE                    21:21
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out CSI controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SHIFT                      _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_RANGE                      20:20
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out HDMI
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SHIFT                     _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_RANGE                     19:19
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out MIPI base-band controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SHIFT                     _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_RANGE                     18:18
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out TVO/CVE controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SHIFT                      _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_RANGE                      17:17
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out DSI controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_RANGE                      16:16
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out DVC-I2C Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SHIFT                  _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_RANGE                  15:15
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bond out SBC 3 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SHIFT                     _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_RANGE                     14:14
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out XIO Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SHIFT                      _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_RANGE                      13:13
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out SBC 2 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_RANGE                     12:12
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SPI 1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_RANGE                     11:11
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out NOR Flash Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SHIFT                      _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_RANGE                      10:10
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out SBC 1 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SHIFT                     _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_RANGE                     9:9
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out Serial Link Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_RANGE                     8:8
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SLC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out FUSE controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_RANGE                     7:7
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out PMC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SHIFT                      _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_RANGE                      6:6
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out statistic monitor.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_RANGE                 5:5
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Bond out keyboard controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SHIFT                      _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_RANGE                      4:4
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out APB-DMA.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SHIFT                   _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_RANGE                   2:2
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out AHB-DMA.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SHIFT                   _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_RANGE                   1:1
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out MC/EMC.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_RANGE                      0:0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Register CLK_RST_CONTROLLER_PLLC_BASE_0  
+#define CLK_RST_CONTROLLER_PLLC_BASE_0                  _MK_ADDR_CONST(0x80)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLC_OUT_0  
+#define CLK_RST_CONTROLLER_PLLC_OUT_0                   _MK_ADDR_CONST(0x84)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLC_OUT1 divider from base PLLC (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  PLLC_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLC_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 136 [0x88] 
+
+// Register CLK_RST_CONTROLLER_PLLC_MISC_0  
+#define CLK_RST_CONTROLLER_PLLC_MISC_0                  _MK_ADDR_CONST(0x8c)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+//  1 = invert PLLC_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLC_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLC test output select.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLC DCCON control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLC charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLC loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLC VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLM_BASE_0  
+#define CLK_RST_CONTROLLER_PLLM_BASE_0                  _MK_ADDR_CONST(0x90)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLM_OUT_0  
+#define CLK_RST_CONTROLLER_PLLM_OUT_0                   _MK_ADDR_CONST(0x94)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLM_OUT1 divider from base PLLM (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  PLLM_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLM_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 152 [0x98] 
+
+// Register CLK_RST_CONTROLLER_PLLM_MISC_0  
+#define CLK_RST_CONTROLLER_PLLM_MISC_0                  _MK_ADDR_CONST(0x9c)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+//  1 = invert PLLM_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLM_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLM test output select.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLM DCCON control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLM charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLM loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLM VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_BASE_0  
+#define CLK_RST_CONTROLLER_PLLP_BASE_0                  _MK_ADDR_CONST(0xa0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xf873ff1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_READ_MASK                        _MK_MASK_CONST(0xf873ff1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xf073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = disallow base override , 1 = allow base override.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_RANGE                  28:28
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_OUTA_0  
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0                  _MK_ADDR_CONST(0xa4)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_VAL                        _MK_MASK_CONST(0x30003)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_MASK                       _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_READ_MASK                        _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WRITE_MASK                       _MK_MASK_CONST(0xff07ff07)
+//  PLLP_OUT2 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_RANGE                    31:24
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT2 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_RANGE                  18:18
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT2 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_RANGE                    17:17
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT2 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT                     _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RANGE                     16:16
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_RANGE                    15:8
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT1 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_RANGE                  2:2
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RANGE                     0:0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_OUTB_0  
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0                  _MK_ADDR_CONST(0xa8)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_RESET_VAL                        _MK_MASK_CONST(0x30003)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_RESET_MASK                       _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_READ_MASK                        _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_WRITE_MASK                       _MK_MASK_CONST(0xff07ff07)
+//  PLLP_OUT4 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_RANGE                    31:24
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT4 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_RANGE                  18:18
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT4 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_RANGE                    17:17
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT4 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT                     _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RANGE                     16:16
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_RANGE                    15:8
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT3 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_RANGE                  2:2
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RANGE                     0:0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_MISC_0  
+#define CLK_RST_CONTROLLER_PLLP_MISC_0                  _MK_ADDR_CONST(0xac)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffd7ffff)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffd7ffff)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffd7ffff)
+//  1 = invert PLLP_OUT4 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT3 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT2 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SHIFT                  _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_RANGE                  29:29
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_RANGE                  28:28
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT4 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT3 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_RANGE                  26:26
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT2 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_RANGE                  25:25
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_RANGE                  24:24
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLP test output select.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLP DCCON control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLP charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLP loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLP VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLA_BASE_0  
+#define CLK_RST_CONTROLLER_PLLA_BASE_0                  _MK_ADDR_CONST(0xb0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLA_OUT_0  
+#define CLK_RST_CONTROLLER_PLLA_OUT_0                   _MK_ADDR_CONST(0xb4)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLA_OUT0 divider from base PLLA (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLA_OUT0 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLA_OUT0 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 184 [0xb8] 
+
+// Register CLK_RST_CONTROLLER_PLLA_MISC_0  
+#define CLK_RST_CONTROLLER_PLLA_MISC_0                  _MK_ADDR_CONST(0xbc)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+//  1 = invert PLLA_OUT0 clock.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLA_OUT0 divider.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLA test output select.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLA DCCON control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLA charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLA loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLA VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLU_BASE_0  
+#define CLK_RST_CONTROLLER_PLLU_BASE_0                  _MK_ADDR_CONST(0xc0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Register CLK_RST_CONTROLLER_PLLU_MISC_0  
+#define CLK_RST_CONTROLLER_PLLU_MISC_0                  _MK_ADDR_CONST(0xcc)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//  1 = 5-125MHz, 0 = 40-1000MHz.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_RANGE                       31:31
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_FO_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = disable, 1 = normal operation.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_RANGE                     30:30
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CLKENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Base PLLU test output select.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_RANGE                   29:27
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  load pulse position adjust.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_FIELD                       (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_RANGE                       26:24
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOADADJ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = normal operation, 1 = reset.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_SHIFT                       _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_RANGE                       23:23
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DIV_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_RANGE                   22:22
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_RANGE                      21:16
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLU DCCON control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_RANGE                 15:12
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLU charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLU loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLU VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLD_BASE_0  
+#define CLK_RST_CONTROLLER_PLLD_BASE_0                  _MK_ADDR_CONST(0xd0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Register CLK_RST_CONTROLLER_PLLD_MISC_0  
+#define CLK_RST_CONTROLLER_PLLD_MISC_0                  _MK_ADDR_CONST(0xdc)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//  1 = 5-125MHz, 0 = 40-1000MHz.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_RANGE                       31:31
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = disable, 1 = normal operation.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_RANGE                     30:30
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Base PLLD test output select.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_RANGE                   29:27
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  load pulse position adjust.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_FIELD                       (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_RANGE                       26:24
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = normal operation, 1 = reset.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SHIFT                       _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_RANGE                       23:23
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_RANGE                   22:22
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_RANGE                      21:16
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLD DCCON control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_RANGE                 15:12
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0  
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0                 _MK_ADDR_CONST(0xf0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_RANGE                  31:31
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_RANGE                   30:30
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_RANGE                   29:29
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_RANGE                   28:28
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_RANGE                    27:27
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_RANGE                        26:26
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_RANGE                        25:25
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_RANGE                      24:24
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_RANGE                      23:23
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_RANGE                       22:22
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_RANGE                        21:21
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_RANGE                        20:20
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_RANGE                        19:19
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_RANGE                       18:18
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_RANGE                     17:17
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_RANGE                        16:16
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_RANGE                     15:15
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_RANGE                    14:14
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_RANGE                 13:13
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_RANGE                     12:12
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_RANGE                    11:11
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_RANGE                 10:10
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_RANGE                        9:9
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_RANGE                   8:8
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_RANGE                     7:7
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_RANGE                        6:6
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_RANGE                   5:5
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_RANGE                    4:4
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_RANGE                    3:3
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_RANGE                    2:2
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_RANGE                     1:1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_RANGE                    0:0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_CMC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0  
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0                 _MK_ADDR_CONST(0xf4)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RESET_MASK                      _MK_MASK_CONST(0xfe0003ff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_READ_MASK                       _MK_MASK_CONST(0xfe0003ff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_WRITE_MASK                      _MK_MASK_CONST(0xfe0003ff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_RANGE                 31:31
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_TEX_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_RANGE                        30:30
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_RAST_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_RANGE                   29:29
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_PIX_XFORM_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_RANGE                        28:28
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEOM_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_RANGE                        27:27
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GATH_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_RANGE                        26:26
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_GEST_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_RANGE                       25:25
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_VG_BLEND_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_RANGE                       9:9
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_RANGE                       8:8
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_RANGE                       7:7
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_RANGE                       6:6
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_RANGE                       5:5
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_RANGE                 4:4
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_RANGE                      3:3
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_RANGE                 2:2
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_RANGE                    1:1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_RANGE                    0:0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0                    _MK_ADDR_CONST(0x100)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_VAL                  _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_MASK                         _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_READ_MASK                  _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WRITE_MASK                         _MK_MASK_CONST(0xd00000ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_INIT_ENUM                     PLLA_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SYNC_CLK_X2                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// 1 = enable I2S1 master clock, disable I2S1 master clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0                    _MK_ADDR_CONST(0x104)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_VAL                  _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_MASK                         _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_READ_MASK                  _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WRITE_MASK                         _MK_MASK_CONST(0xd00000ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_INIT_ENUM                     PLLA_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SYNC_CLK_X2                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// 1 = enable I2S2 master clock, disable I2S2 master clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0                   _MK_ADDR_CONST(0x108)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_RESET_MASK                        _MK_MASK_CONST(0xc0ffc0ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_READ_MASK                         _MK_MASK_CONST(0xc0ffc0ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_WRITE_MASK                        _MK_MASK_CONST(0xc0ffc0ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_SHIFT                    _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_FIELD                    (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_RANGE                    31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_INIT_ENUM                        PLLA_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_PLLA_OUT0                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_SYNC_CLK_X2                      _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_PLLP_OUT0                        _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_SRC_CLK_M                    _MK_ENUM_CONST(3)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_RANGE                        23:16
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFOUT_CLK_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = 1'b0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_RANGE                     15:14
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_INIT_ENUM                 PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0_SPDIFIN_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 268 [0x10c] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0                     _MK_ADDR_CONST(0x110)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = audio SYNC_CLK x 2
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SYNC_CLK_X2                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0                    _MK_ADDR_CONST(0x114)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0                    _MK_ADDR_CONST(0x118)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0                    _MK_ADDR_CONST(0x11c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0                     _MK_ADDR_CONST(0x120)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0                    _MK_ADDR_CONST(0x124)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_MASK                         _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_READ_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WRITE_MASK                         _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_RANGE                     15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0                 _MK_ADDR_CONST(0x128)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_RESET_MASK                      _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_READ_MASK                       _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_WRITE_MASK                      _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_RANGE                       15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0                     _MK_ADDR_CONST(0x12c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0                    _MK_ADDR_CONST(0x130)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0_SLC1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0                    _MK_ADDR_CONST(0x134)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0                   _MK_ADDR_CONST(0x138)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0                   _MK_ADDR_CONST(0x13c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0                     _MK_ADDR_CONST(0x140)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLD_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0                     _MK_ADDR_CONST(0x144)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0                      _MK_ADDR_CONST(0x148)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_MASK                   _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_READ_MASK                    _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WRITE_MASK                   _MK_MASK_CONST(0xc30000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_INIT_ENUM                 PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLA_OUT0                 _MK_ENUM_CONST(3)
+
+// 0 = pd2vi_clk, 1 = vi_sensor_clk.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_RANGE                  25:25
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 = select internal clock, 1 = select external clock (pd2vi_clk).
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_RANGE                     24:24
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INIT_ENUM                 INTERNAL
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INTERNAL                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_EXTERNAL                  _MK_ENUM_CONST(1)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0                     _MK_ADDR_CONST(0x14c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_RESET_MASK                  _MK_MASK_CONST(0x700000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_READ_MASK                   _MK_MASK_CONST(0x700000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_WRITE_MASK                  _MK_MASK_CONST(0x700000ff)
+// 000 = clk_m
+// 001 = pllC_out0
+// 010 = clk_s
+// 011 = pllM_out0
+// 100 = pllP_out0
+// 101 = pllP_out4
+// 110 = pllP_out3
+// 111 = clk_d
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_RANGE                   30:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_CLK_M                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_CLK_S                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLP_OUT4                       _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_PLLP_OUT3                       _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_SRC_CLK_D                   _MK_ENUM_CONST(7)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0_MEM_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0                   _MK_ADDR_CONST(0x150)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0_SDIO1_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0                   _MK_ADDR_CONST(0x154)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0_SDIO2_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0                     _MK_ADDR_CONST(0x158)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0                     _MK_ADDR_CONST(0x15c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0                 _MK_ADDR_CONST(0x160)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_RESET_MASK                      _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_READ_MASK                       _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_WRITE_MASK                      _MK_MASK_CONST(0xc00000ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0                   _MK_ADDR_CONST(0x164)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0_HSMMC_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0                    _MK_ADDR_CONST(0x168)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0                     _MK_ADDR_CONST(0x16c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0                     _MK_ADDR_CONST(0x170)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_INIT_ENUM                       PLLM_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0                    _MK_ADDR_CONST(0x174)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0                   _MK_ADDR_CONST(0x178)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0                   _MK_ADDR_CONST(0x17c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0                  _MK_ADDR_CONST(0x180)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_MASK                       _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_READ_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WRITE_MASK                       _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_INIT_ENUM                 PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLA_OUT0                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 388 [0x184] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0                     _MK_ADDR_CONST(0x188)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_INIT_ENUM                       PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLD_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0                    _MK_ADDR_CONST(0x18c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLD_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 400 [0x190] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0                   _MK_ADDR_CONST(0x194)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_INIT_ENUM                   pllP_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0                    _MK_ADDR_CONST(0x198)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_MASK                         _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_READ_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WRITE_MASK                         _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_INIT_ENUM                     PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_RANGE                     15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0                     _MK_ADDR_CONST(0x19c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_MASK                  _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_READ_MASK                   _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WRITE_MASK                  _MK_MASK_CONST(0xc30000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_RANGE                        31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_INIT_ENUM                    PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_OUT0                    _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLC_OUT0                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLP_OUT0                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_CLK_M                        _MK_ENUM_CONST(3)
+
+//  1 = enable EMC 2X clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_ENABLE                       _MK_ENUM_CONST(1)
+
+//  1 = enable EMC 1X clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SHIFT                        _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_RANGE                        24:24
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_ENABLE                       _MK_ENUM_CONST(1)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_RANGE                    7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0                   _MK_ADDR_CONST(0x1a0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_INIT_ENUM                   PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Reserved address 420 [0x1a4] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0                       _MK_ADDR_CONST(0x1a8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_RESET_MASK                    _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_READ_MASK                     _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_WRITE_MASK                    _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_INIT_ENUM                   PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0                       _MK_ADDR_CONST(0x1ac)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_RESET_MASK                    _MK_MASK_CONST(0x70000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_READ_MASK                     _MK_MASK_CONST(0x70000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_WRITE_MASK                    _MK_MASK_CONST(0x70000000)
+// 000 = SPDIFIN recovered bit clock.
+// 001 = I2S1 bit clock.
+// 010 = I2S2 bit clock.
+// 011 = AC97 bit clock.
+// 100 = pllA_out0.
+// 101 = external audio clock in (dap_mclk2).
+// 110 = external audio clock in (dap_mclk1).
+// 111 = external vimclk (vimclk).
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_RANGE                       30:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_INIT_ENUM                   SPDIFIN
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_SPDIFIN                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_I2S1                        _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_I2S2                        _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_AC97                        _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_EXT_AUDIO_CLK2                      _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_EXT_AUDIO_CLK1                      _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0_MPE_AUDIO_CLK_SRC_EXT_VIMCLK                  _MK_ENUM_CONST(7)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARCLK_RST_REGS(_op_) \
+_op_(CLK_RST_CONTROLLER_RST_SOURCE_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEVICES_L_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEVICES_H_0) \
+_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0) \
+_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0) \
+_op_(CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0) \
+_op_(CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0) \
+_op_(CLK_RST_CONTROLLER_PROG_DLY_CLK_0) \
+_op_(CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_CLK_MASK_ARM_0) \
+_op_(CLK_RST_CONTROLLER_MISC_CLK_ENB_0) \
+_op_(CLK_RST_CONTROLLER_OSC_CTRL_0) \
+_op_(CLK_RST_CONTROLLER_PLL_LFSR_0) \
+_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_0) \
+_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0) \
+_op_(CLK_RST_CONTROLLER_BOND_OUT_L_0) \
+_op_(CLK_RST_CONTROLLER_BOND_OUT_H_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_OUTA_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_OUTB_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLU_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLU_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLD_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLD_MISC_0) \
+_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0) \
+_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SLC1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MEM_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDIO1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDIO2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HSMMC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_CLK_RST_CONTROLLER 0x00000000
+
+//
+// ARCLK_RST REGISTER BANKS
+//
+
+#define CLK_RST_CONTROLLER0_FIRST_REG 0x0000 // CLK_RST_CONTROLLER_RST_SOURCE_0
+#define CLK_RST_CONTROLLER0_LAST_REG 0x0008 // CLK_RST_CONTROLLER_RST_DEVICES_H_0
+#define CLK_RST_CONTROLLER1_FIRST_REG 0x0010 // CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0
+#define CLK_RST_CONTROLLER1_LAST_REG 0x0014 // CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0
+#define CLK_RST_CONTROLLER2_FIRST_REG 0x0020 // CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0
+#define CLK_RST_CONTROLLER2_LAST_REG 0x0034 // CLK_RST_CONTROLLER_PROG_DLY_CLK_0
+#define CLK_RST_CONTROLLER3_FIRST_REG 0x0040 // CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0
+#define CLK_RST_CONTROLLER3_LAST_REG 0x0048 // CLK_RST_CONTROLLER_MISC_CLK_ENB_0
+#define CLK_RST_CONTROLLER4_FIRST_REG 0x0050 // CLK_RST_CONTROLLER_OSC_CTRL_0
+#define CLK_RST_CONTROLLER4_LAST_REG 0x005c // CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0
+#define CLK_RST_CONTROLLER5_FIRST_REG 0x0070 // CLK_RST_CONTROLLER_BOND_OUT_L_0
+#define CLK_RST_CONTROLLER5_LAST_REG 0x0074 // CLK_RST_CONTROLLER_BOND_OUT_H_0
+#define CLK_RST_CONTROLLER6_FIRST_REG 0x0080 // CLK_RST_CONTROLLER_PLLC_BASE_0
+#define CLK_RST_CONTROLLER6_LAST_REG 0x0084 // CLK_RST_CONTROLLER_PLLC_OUT_0
+#define CLK_RST_CONTROLLER7_FIRST_REG 0x008c // CLK_RST_CONTROLLER_PLLC_MISC_0
+#define CLK_RST_CONTROLLER7_LAST_REG 0x0094 // CLK_RST_CONTROLLER_PLLM_OUT_0
+#define CLK_RST_CONTROLLER8_FIRST_REG 0x009c // CLK_RST_CONTROLLER_PLLM_MISC_0
+#define CLK_RST_CONTROLLER8_LAST_REG 0x00b4 // CLK_RST_CONTROLLER_PLLA_OUT_0
+#define CLK_RST_CONTROLLER9_FIRST_REG 0x00bc // CLK_RST_CONTROLLER_PLLA_MISC_0
+#define CLK_RST_CONTROLLER9_LAST_REG 0x00c0 // CLK_RST_CONTROLLER_PLLU_BASE_0
+#define CLK_RST_CONTROLLER10_FIRST_REG 0x00cc // CLK_RST_CONTROLLER_PLLU_MISC_0
+#define CLK_RST_CONTROLLER10_LAST_REG 0x00d0 // CLK_RST_CONTROLLER_PLLD_BASE_0
+#define CLK_RST_CONTROLLER11_FIRST_REG 0x00dc // CLK_RST_CONTROLLER_PLLD_MISC_0
+#define CLK_RST_CONTROLLER11_LAST_REG 0x00dc // CLK_RST_CONTROLLER_PLLD_MISC_0
+#define CLK_RST_CONTROLLER12_FIRST_REG 0x00f0 // CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0
+#define CLK_RST_CONTROLLER12_LAST_REG 0x00f4 // CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0
+#define CLK_RST_CONTROLLER13_FIRST_REG 0x0100 // CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0
+#define CLK_RST_CONTROLLER13_LAST_REG 0x0108 // CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_0
+#define CLK_RST_CONTROLLER14_FIRST_REG 0x0110 // CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0
+#define CLK_RST_CONTROLLER14_LAST_REG 0x0180 // CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0
+#define CLK_RST_CONTROLLER15_FIRST_REG 0x0188 // CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0
+#define CLK_RST_CONTROLLER15_LAST_REG 0x018c // CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0
+#define CLK_RST_CONTROLLER16_FIRST_REG 0x0194 // CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0
+#define CLK_RST_CONTROLLER16_LAST_REG 0x01a0 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0
+#define CLK_RST_CONTROLLER17_FIRST_REG 0x01a8 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0
+#define CLK_RST_CONTROLLER17_LAST_REG 0x01ac // CLK_RST_CONTROLLER_CLK_SOURCE_MPE_AUDIO_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARCLK_RST_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/aremc.h b/arch/arm/mach-tegra/nv/include/ap15/aremc.h
new file mode 100644
index 000000000000..ba241d0e1a47
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/aremc.h
@@ -0,0 +1,4381 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___AREMC_H_INC_
+#define ___AREMC_H_INC_
+#define EMC_FBIO_DATA_MAX       31
+#define EMC_FBIO_DATA_WIDTH     32
+#define EMC_FBIO_DOE_MAX        3
+#define EMC_FBIO_DOE_WIDTH      4
+
+// Register EMC_INTSTATUS_0  
+#define EMC_INTSTATUS_0                 _MK_ADDR_CONST(0x0)
+#define EMC_INTSTATUS_0_WORD_COUNT                      0x1
+#define EMC_INTSTATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_RESET_MASK                      _MK_MASK_CONST(0x4)
+#define EMC_INTSTATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_READ_MASK                       _MK_MASK_CONST(0x4)
+#define EMC_INTSTATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x4)
+// NOR/MIO mux request timeout
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_SHIFT                   _MK_SHIFT_CONST(2)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_FIELD                   (_MK_MASK_CONST(0x1) << EMC_INTSTATUS_0_NOR_TIMEOUT_INT_SHIFT)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_RANGE                   2:2
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_WOFFSET                 0x0
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_INIT_ENUM                       CLEAR
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_CLEAR                   _MK_ENUM_CONST(0)
+#define EMC_INTSTATUS_0_NOR_TIMEOUT_INT_SET                     _MK_ENUM_CONST(1)
+
+
+// Register EMC_INTMASK_0  
+#define EMC_INTMASK_0                   _MK_ADDR_CONST(0x4)
+#define EMC_INTMASK_0_WORD_COUNT                        0x1
+#define EMC_INTMASK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_RESET_MASK                        _MK_MASK_CONST(0x4)
+#define EMC_INTMASK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_READ_MASK                         _MK_MASK_CONST(0x4)
+#define EMC_INTMASK_0_WRITE_MASK                        _MK_MASK_CONST(0x4)
+// NOR/MIO mux request timeout
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_SHIFT                 _MK_SHIFT_CONST(2)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_FIELD                 (_MK_MASK_CONST(0x1) << EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_SHIFT)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_RANGE                 2:2
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_WOFFSET                       0x0
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_INIT_ENUM                     MASKED
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_MASKED                        _MK_ENUM_CONST(0)
+#define EMC_INTMASK_0_NOR_TIMEOUT_INTMASK_UNMASKED                      _MK_ENUM_CONST(1)
+
+
+// Register EMC_DBG_0  // Debug Register
+#define EMC_DBG_0                       _MK_ADDR_CONST(0x8)
+#define EMC_DBG_0_WORD_COUNT                    0x1
+#define EMC_DBG_0_RESET_VAL                     _MK_MASK_CONST(0x1000400)
+#define EMC_DBG_0_RESET_MASK                    _MK_MASK_CONST(0x1000637)
+#define EMC_DBG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MASK                     _MK_MASK_CONST(0x1000637)
+#define EMC_DBG_0_WRITE_MASK                    _MK_MASK_CONST(0x1000637)
+#define EMC_DBG_0_READ_MUX_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DBG_0_READ_MUX_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_READ_MUX_SHIFT)
+#define EMC_DBG_0_READ_MUX_RANGE                        0:0
+#define EMC_DBG_0_READ_MUX_WOFFSET                      0x0
+#define EMC_DBG_0_READ_MUX_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_READ_MUX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_INIT_ENUM                    ACTIVE
+#define EMC_DBG_0_READ_MUX_ACTIVE                       _MK_ENUM_CONST(0)
+#define EMC_DBG_0_READ_MUX_ASSEMBLY                     _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_WRITE_MUX_SHIFT                       _MK_SHIFT_CONST(1)
+#define EMC_DBG_0_WRITE_MUX_FIELD                       (_MK_MASK_CONST(0x1) << EMC_DBG_0_WRITE_MUX_SHIFT)
+#define EMC_DBG_0_WRITE_MUX_RANGE                       1:1
+#define EMC_DBG_0_WRITE_MUX_WOFFSET                     0x0
+#define EMC_DBG_0_WRITE_MUX_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_WRITE_MUX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_INIT_ENUM                   ASSEMBLY
+#define EMC_DBG_0_WRITE_MUX_ASSEMBLY                    _MK_ENUM_CONST(0)
+#define EMC_DBG_0_WRITE_MUX_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_FORCE_UPDATE_SHIFT                    _MK_SHIFT_CONST(2)
+#define EMC_DBG_0_FORCE_UPDATE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DBG_0_FORCE_UPDATE_SHIFT)
+#define EMC_DBG_0_FORCE_UPDATE_RANGE                    2:2
+#define EMC_DBG_0_FORCE_UPDATE_WOFFSET                  0x0
+#define EMC_DBG_0_FORCE_UPDATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_FORCE_UPDATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_INIT_ENUM                        DISABLED
+#define EMC_DBG_0_FORCE_UPDATE_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_FORCE_UPDATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_MRS_WAIT_SHIFT                        _MK_SHIFT_CONST(4)
+#define EMC_DBG_0_MRS_WAIT_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_MRS_WAIT_SHIFT)
+#define EMC_DBG_0_MRS_WAIT_RANGE                        4:4
+#define EMC_DBG_0_MRS_WAIT_WOFFSET                      0x0
+#define EMC_DBG_0_MRS_WAIT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_MRS_WAIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_INIT_ENUM                    MRS_2
+#define EMC_DBG_0_MRS_WAIT_MRS_2                        _MK_ENUM_CONST(0)
+#define EMC_DBG_0_MRS_WAIT_MRS_256                      _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_PERIODIC_QRST_SHIFT                   _MK_SHIFT_CONST(5)
+#define EMC_DBG_0_PERIODIC_QRST_FIELD                   (_MK_MASK_CONST(0x1) << EMC_DBG_0_PERIODIC_QRST_SHIFT)
+#define EMC_DBG_0_PERIODIC_QRST_RANGE                   5:5
+#define EMC_DBG_0_PERIODIC_QRST_WOFFSET                 0x0
+#define EMC_DBG_0_PERIODIC_QRST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_PERIODIC_QRST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_INIT_ENUM                       DISABLED
+#define EMC_DBG_0_PERIODIC_QRST_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_DBG_0_PERIODIC_QRST_ENABLED                 _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_READ_DQM_CTRL_SHIFT                   _MK_SHIFT_CONST(9)
+#define EMC_DBG_0_READ_DQM_CTRL_FIELD                   (_MK_MASK_CONST(0x1) << EMC_DBG_0_READ_DQM_CTRL_SHIFT)
+#define EMC_DBG_0_READ_DQM_CTRL_RANGE                   9:9
+#define EMC_DBG_0_READ_DQM_CTRL_WOFFSET                 0x0
+#define EMC_DBG_0_READ_DQM_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_READ_DQM_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_INIT_ENUM                       MANAGED
+#define EMC_DBG_0_READ_DQM_CTRL_MANAGED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_READ_DQM_CTRL_ALWAYS_ON                       _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SHIFT                        _MK_SHIFT_CONST(10)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_AP_REQ_BUSY_CTRL_SHIFT)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_RANGE                        10:10
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_WOFFSET                      0x0
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_INIT_ENUM                    ENABLED
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DISABLED                     _MK_ENUM_CONST(0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define EMC_DBG_0_CFG_PRIORITY_SHIFT                    _MK_SHIFT_CONST(24)
+#define EMC_DBG_0_CFG_PRIORITY_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DBG_0_CFG_PRIORITY_SHIFT)
+#define EMC_DBG_0_CFG_PRIORITY_RANGE                    24:24
+#define EMC_DBG_0_CFG_PRIORITY_WOFFSET                  0x0
+#define EMC_DBG_0_CFG_PRIORITY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_CFG_PRIORITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_CFG_PRIORITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_CFG_PRIORITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_CFG_PRIORITY_INIT_ENUM                        ENABLED
+#define EMC_DBG_0_CFG_PRIORITY_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_CFG_PRIORITY_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_CFG_0  // Configuration Register
+#define EMC_CFG_0                       _MK_ADDR_CONST(0xc)
+#define EMC_CFG_0_WORD_COUNT                    0x1
+#define EMC_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x300ff00)
+#define EMC_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xa301ff01)
+#define EMC_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_READ_MASK                     _MK_MASK_CONST(0xa301ff01)
+#define EMC_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xa301ff01)
+#define EMC_CFG_0_PRE_IDLE_EN_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_CFG_0_PRE_IDLE_EN_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_PRE_IDLE_EN_SHIFT)
+#define EMC_CFG_0_PRE_IDLE_EN_RANGE                     0:0
+#define EMC_CFG_0_PRE_IDLE_EN_WOFFSET                   0x0
+#define EMC_CFG_0_PRE_IDLE_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_PRE_IDLE_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_INIT_ENUM                 DISABLED
+#define EMC_CFG_0_PRE_IDLE_EN_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_PRE_IDLE_EN_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_FIELD                 (_MK_MASK_CONST(0xff) << EMC_CFG_0_PRE_IDLE_CYCLES_SHIFT)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_RANGE                 15:8
+#define EMC_CFG_0_PRE_IDLE_CYCLES_WOFFSET                       0x0
+#define EMC_CFG_0_PRE_IDLE_CYCLES_DEFAULT                       _MK_MASK_CONST(0xff)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SHIFT)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_RANGE                     16:16
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_WOFFSET                   0x0
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_INIT_ENUM                 DISABLED
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_CFG_0_AUTO_PRE_RD_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_CFG_0_AUTO_PRE_RD_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_AUTO_PRE_RD_SHIFT)
+#define EMC_CFG_0_AUTO_PRE_RD_RANGE                     24:24
+#define EMC_CFG_0_AUTO_PRE_RD_WOFFSET                   0x0
+#define EMC_CFG_0_AUTO_PRE_RD_DEFAULT                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_RD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_RD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_RD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_RD_INIT_ENUM                 ENABLED
+#define EMC_CFG_0_AUTO_PRE_RD_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_AUTO_PRE_RD_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_CFG_0_AUTO_PRE_WR_SHIFT                     _MK_SHIFT_CONST(25)
+#define EMC_CFG_0_AUTO_PRE_WR_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_AUTO_PRE_WR_SHIFT)
+#define EMC_CFG_0_AUTO_PRE_WR_RANGE                     25:25
+#define EMC_CFG_0_AUTO_PRE_WR_WOFFSET                   0x0
+#define EMC_CFG_0_AUTO_PRE_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_WR_INIT_ENUM                 ENABLED
+#define EMC_CFG_0_AUTO_PRE_WR_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_AUTO_PRE_WR_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_CFG_0_DRAM_ACPD_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_CFG_0_DRAM_ACPD_FIELD                       (_MK_MASK_CONST(0x1) << EMC_CFG_0_DRAM_ACPD_SHIFT)
+#define EMC_CFG_0_DRAM_ACPD_RANGE                       29:29
+#define EMC_CFG_0_DRAM_ACPD_WOFFSET                     0x0
+#define EMC_CFG_0_DRAM_ACPD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_DRAM_ACPD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_INIT_ENUM                   NO_POWERDOWN
+#define EMC_CFG_0_DRAM_ACPD_NO_POWERDOWN                        _MK_ENUM_CONST(0)
+#define EMC_CFG_0_DRAM_ACPD_ACTIVE_POWERDOWN                    _MK_ENUM_CONST(1)
+
+#define EMC_CFG_0_DRAM_CLKSTOP_SHIFT                    _MK_SHIFT_CONST(31)
+#define EMC_CFG_0_DRAM_CLKSTOP_FIELD                    (_MK_MASK_CONST(0x1) << EMC_CFG_0_DRAM_CLKSTOP_SHIFT)
+#define EMC_CFG_0_DRAM_CLKSTOP_RANGE                    31:31
+#define EMC_CFG_0_DRAM_CLKSTOP_WOFFSET                  0x0
+#define EMC_CFG_0_DRAM_CLKSTOP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_DRAM_CLKSTOP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_INIT_ENUM                        DISABLED
+#define EMC_CFG_0_DRAM_CLKSTOP_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_CFG_0_DRAM_CLKSTOP_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_ADR_CFG_0  
+#define EMC_ADR_CFG_0                   _MK_ADDR_CONST(0x10)
+#define EMC_ADR_CFG_0_WORD_COUNT                        0x1
+#define EMC_ADR_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x40202)
+#define EMC_ADR_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x3070307)
+#define EMC_ADR_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_READ_MASK                         _MK_MASK_CONST(0x3070307)
+#define EMC_ADR_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x3070307)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_FIELD                       (_MK_MASK_CONST(0x7) << EMC_ADR_CFG_0_EMEM_COLWIDTH_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_RANGE                       2:0
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_WOFFSET                     0x0
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT                     _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_INIT_ENUM                   W9
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W7                  _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W8                  _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W9                  _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W10                 _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W11                 _MK_ENUM_CONST(4)
+
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_FIELD                      (_MK_MASK_CONST(0x3) << EMC_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_RANGE                      9:8
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_WOFFSET                    0x0
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_INIT_ENUM                  W2
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W1                 _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W2                 _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W3                 _MK_ENUM_CONST(3)
+
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_FIELD                        (_MK_MASK_CONST(0x7) << EMC_ADR_CFG_0_EMEM_DEVSIZE_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_RANGE                        18:16
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_WOFFSET                      0x0
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT                      _MK_MASK_CONST(0x4)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_INIT_ENUM                    D64MB
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D4MB                 _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D8MB                 _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D16MB                        _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D32MB                        _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D64MB                        _MK_ENUM_CONST(4)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D128MB                       _MK_ENUM_CONST(5)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D256MB                       _MK_ENUM_CONST(6)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D512MB                       _MK_ENUM_CONST(7)
+
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_FIELD                 (_MK_MASK_CONST(0x3) << EMC_ADR_CFG_0_EMEM_NUMDEV_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_RANGE                 25:24
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_WOFFSET                       0x0
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_INIT_ENUM                     N1
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_N1                    _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_N2                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_REFCTRL_0  // Refresh Control Register
+#define EMC_REFCTRL_0                   _MK_ADDR_CONST(0x14)
+#define EMC_REFCTRL_0_WORD_COUNT                        0x1
+#define EMC_REFCTRL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_RESET_MASK                        _MK_MASK_CONST(0x80000000)
+#define EMC_REFCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_READ_MASK                         _MK_MASK_CONST(0x80000000)
+#define EMC_REFCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0x80000000)
+#define EMC_REFCTRL_0_REF_VALID_SHIFT                   _MK_SHIFT_CONST(31)
+#define EMC_REFCTRL_0_REF_VALID_FIELD                   (_MK_MASK_CONST(0x1) << EMC_REFCTRL_0_REF_VALID_SHIFT)
+#define EMC_REFCTRL_0_REF_VALID_RANGE                   31:31
+#define EMC_REFCTRL_0_REF_VALID_WOFFSET                 0x0
+#define EMC_REFCTRL_0_REF_VALID_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_REFCTRL_0_REF_VALID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_INIT_ENUM                       DISABLED
+#define EMC_REFCTRL_0_REF_VALID_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_REFCTRL_0_REF_VALID_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register EMC_PIN_0  // Controls state of selected DRAM pins
+#define EMC_PIN_0                       _MK_ADDR_CONST(0x18)
+#define EMC_PIN_0_WORD_COUNT                    0x1
+#define EMC_PIN_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_RESET_MASK                    _MK_MASK_CONST(0x11)
+#define EMC_PIN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_READ_MASK                     _MK_MASK_CONST(0x11)
+#define EMC_PIN_0_WRITE_MASK                    _MK_MASK_CONST(0x11)
+#define EMC_PIN_0_PIN_CKE_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_PIN_0_PIN_CKE_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PIN_0_PIN_CKE_SHIFT)
+#define EMC_PIN_0_PIN_CKE_RANGE                 0:0
+#define EMC_PIN_0_PIN_CKE_WOFFSET                       0x0
+#define EMC_PIN_0_PIN_CKE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PIN_0_PIN_CKE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_INIT_ENUM                     POWERDOWN
+#define EMC_PIN_0_PIN_CKE_POWERDOWN                     _MK_ENUM_CONST(0)
+#define EMC_PIN_0_PIN_CKE_NORMAL                        _MK_ENUM_CONST(1)
+
+#define EMC_PIN_0_PIN_DQM_SHIFT                 _MK_SHIFT_CONST(4)
+#define EMC_PIN_0_PIN_DQM_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PIN_0_PIN_DQM_SHIFT)
+#define EMC_PIN_0_PIN_DQM_RANGE                 4:4
+#define EMC_PIN_0_PIN_DQM_WOFFSET                       0x0
+#define EMC_PIN_0_PIN_DQM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PIN_0_PIN_DQM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_INIT_ENUM                     NORMAL
+#define EMC_PIN_0_PIN_DQM_NORMAL                        _MK_ENUM_CONST(0)
+#define EMC_PIN_0_PIN_DQM_INACTIVE                      _MK_ENUM_CONST(1)
+
+
+// Register EMC_TIMING_CONTROL_0  
+#define EMC_TIMING_CONTROL_0                    _MK_ADDR_CONST(0x1c)
+#define EMC_TIMING_CONTROL_0_WORD_COUNT                         0x1
+#define EMC_TIMING_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_TIMING_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_FIELD                        (_MK_MASK_CONST(0x1) << EMC_TIMING_CONTROL_0_TIMING_UPDATE_SHIFT)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_RANGE                        0:0
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_WOFFSET                      0x0
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TIMING0_0  // Timing Control Register 0
+#define EMC_TIMING0_0                   _MK_ADDR_CONST(0x20)
+#define EMC_TIMING0_0_WORD_COUNT                        0x1
+#define EMC_TIMING0_0_RESET_VAL                         _MK_MASK_CONST(0x3f3f3f3f)
+#define EMC_TIMING0_0_RESET_MASK                        _MK_MASK_CONST(0x3f3f3f3f)
+#define EMC_TIMING0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_READ_MASK                         _MK_MASK_CONST(0x3f3f3f3f)
+#define EMC_TIMING0_0_WRITE_MASK                        _MK_MASK_CONST(0x3f3f3f3f)
+#define EMC_TIMING0_0_RC_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_TIMING0_0_RC_FIELD                  (_MK_MASK_CONST(0x3f) << EMC_TIMING0_0_RC_SHIFT)
+#define EMC_TIMING0_0_RC_RANGE                  5:0
+#define EMC_TIMING0_0_RC_WOFFSET                        0x0
+#define EMC_TIMING0_0_RC_DEFAULT                        _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RC_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_RC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING0_0_RFC_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_TIMING0_0_RFC_FIELD                 (_MK_MASK_CONST(0x3f) << EMC_TIMING0_0_RFC_SHIFT)
+#define EMC_TIMING0_0_RFC_RANGE                 13:8
+#define EMC_TIMING0_0_RFC_WOFFSET                       0x0
+#define EMC_TIMING0_0_RFC_DEFAULT                       _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RFC_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RFC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_RFC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING0_0_RAS_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_TIMING0_0_RAS_FIELD                 (_MK_MASK_CONST(0x3f) << EMC_TIMING0_0_RAS_SHIFT)
+#define EMC_TIMING0_0_RAS_RANGE                 21:16
+#define EMC_TIMING0_0_RAS_WOFFSET                       0x0
+#define EMC_TIMING0_0_RAS_DEFAULT                       _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RAS_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RAS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_RAS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING0_0_RP_SHIFT                  _MK_SHIFT_CONST(24)
+#define EMC_TIMING0_0_RP_FIELD                  (_MK_MASK_CONST(0x3f) << EMC_TIMING0_0_RP_SHIFT)
+#define EMC_TIMING0_0_RP_RANGE                  29:24
+#define EMC_TIMING0_0_RP_WOFFSET                        0x0
+#define EMC_TIMING0_0_RP_DEFAULT                        _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RP_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define EMC_TIMING0_0_RP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_TIMING0_0_RP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TIMING1_0  // Timing Control Register 1
+#define EMC_TIMING1_0                   _MK_ADDR_CONST(0x24)
+#define EMC_TIMING1_0_WORD_COUNT                        0x1
+#define EMC_TIMING1_0_RESET_VAL                         _MK_MASK_CONST(0x1f1f1f1f)
+#define EMC_TIMING1_0_RESET_MASK                        _MK_MASK_CONST(0x1f1f1f1f)
+#define EMC_TIMING1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_READ_MASK                         _MK_MASK_CONST(0x1f1f1f1f)
+#define EMC_TIMING1_0_WRITE_MASK                        _MK_MASK_CONST(0x1f1f1f1f)
+#define EMC_TIMING1_0_R2W_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_TIMING1_0_R2W_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_TIMING1_0_R2W_SHIFT)
+#define EMC_TIMING1_0_R2W_RANGE                 4:0
+#define EMC_TIMING1_0_R2W_WOFFSET                       0x0
+#define EMC_TIMING1_0_R2W_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_R2W_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_R2W_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_R2W_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING1_0_W2R_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_TIMING1_0_W2R_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_TIMING1_0_W2R_SHIFT)
+#define EMC_TIMING1_0_W2R_RANGE                 12:8
+#define EMC_TIMING1_0_W2R_WOFFSET                       0x0
+#define EMC_TIMING1_0_W2R_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_W2R_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_W2R_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_W2R_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING1_0_R2P_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_TIMING1_0_R2P_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_TIMING1_0_R2P_SHIFT)
+#define EMC_TIMING1_0_R2P_RANGE                 20:16
+#define EMC_TIMING1_0_R2P_WOFFSET                       0x0
+#define EMC_TIMING1_0_R2P_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_R2P_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_R2P_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_R2P_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING1_0_W2P_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_TIMING1_0_W2P_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_TIMING1_0_W2P_SHIFT)
+#define EMC_TIMING1_0_W2P_RANGE                 28:24
+#define EMC_TIMING1_0_W2P_WOFFSET                       0x0
+#define EMC_TIMING1_0_W2P_DEFAULT                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_W2P_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_TIMING1_0_W2P_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING1_0_W2P_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TIMING2_0  // Timing Control Register 2
+#define EMC_TIMING2_0                   _MK_ADDR_CONST(0x28)
+#define EMC_TIMING2_0_WORD_COUNT                        0x1
+#define EMC_TIMING2_0_RESET_VAL                         _MK_MASK_CONST(0x1f1f1f)
+#define EMC_TIMING2_0_RESET_MASK                        _MK_MASK_CONST(0xfff1f1f)
+#define EMC_TIMING2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_READ_MASK                         _MK_MASK_CONST(0xfff1f1f)
+#define EMC_TIMING2_0_WRITE_MASK                        _MK_MASK_CONST(0xfff1f1f)
+#define EMC_TIMING2_0_RD_RCD_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_TIMING2_0_RD_RCD_FIELD                      (_MK_MASK_CONST(0x1f) << EMC_TIMING2_0_RD_RCD_SHIFT)
+#define EMC_TIMING2_0_RD_RCD_RANGE                      4:0
+#define EMC_TIMING2_0_RD_RCD_WOFFSET                    0x0
+#define EMC_TIMING2_0_RD_RCD_DEFAULT                    _MK_MASK_CONST(0x1f)
+#define EMC_TIMING2_0_RD_RCD_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING2_0_RD_RCD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_RD_RCD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING2_0_WR_RCD_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_TIMING2_0_WR_RCD_FIELD                      (_MK_MASK_CONST(0x1f) << EMC_TIMING2_0_WR_RCD_SHIFT)
+#define EMC_TIMING2_0_WR_RCD_RANGE                      12:8
+#define EMC_TIMING2_0_WR_RCD_WOFFSET                    0x0
+#define EMC_TIMING2_0_WR_RCD_DEFAULT                    _MK_MASK_CONST(0x1f)
+#define EMC_TIMING2_0_WR_RCD_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_TIMING2_0_WR_RCD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_WR_RCD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING2_0_RRD_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_TIMING2_0_RRD_FIELD                 (_MK_MASK_CONST(0xf) << EMC_TIMING2_0_RRD_SHIFT)
+#define EMC_TIMING2_0_RRD_RANGE                 19:16
+#define EMC_TIMING2_0_RRD_WOFFSET                       0x0
+#define EMC_TIMING2_0_RRD_DEFAULT                       _MK_MASK_CONST(0xf)
+#define EMC_TIMING2_0_RRD_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define EMC_TIMING2_0_RRD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_RRD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING2_0_REXT_SHIFT                        _MK_SHIFT_CONST(20)
+#define EMC_TIMING2_0_REXT_FIELD                        (_MK_MASK_CONST(0xf) << EMC_TIMING2_0_REXT_SHIFT)
+#define EMC_TIMING2_0_REXT_RANGE                        23:20
+#define EMC_TIMING2_0_REXT_WOFFSET                      0x0
+#define EMC_TIMING2_0_REXT_DEFAULT                      _MK_MASK_CONST(0x1)
+#define EMC_TIMING2_0_REXT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define EMC_TIMING2_0_REXT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_REXT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING2_0_WDV_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_TIMING2_0_WDV_FIELD                 (_MK_MASK_CONST(0xf) << EMC_TIMING2_0_WDV_SHIFT)
+#define EMC_TIMING2_0_WDV_RANGE                 27:24
+#define EMC_TIMING2_0_WDV_WOFFSET                       0x0
+#define EMC_TIMING2_0_WDV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_WDV_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define EMC_TIMING2_0_WDV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING2_0_WDV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TIMING3_0  // Timing Control Register 3
+#define EMC_TIMING3_0                   _MK_ADDR_CONST(0x2c)
+#define EMC_TIMING3_0_WORD_COUNT                        0x1
+#define EMC_TIMING3_0_RESET_VAL                         _MK_MASK_CONST(0x87102)
+#define EMC_TIMING3_0_RESET_MASK                        _MK_MASK_CONST(0x1fff0f)
+#define EMC_TIMING3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_READ_MASK                         _MK_MASK_CONST(0x1fff0f)
+#define EMC_TIMING3_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff0f)
+#define EMC_TIMING3_0_QUSE_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_TIMING3_0_QUSE_FIELD                        (_MK_MASK_CONST(0xf) << EMC_TIMING3_0_QUSE_SHIFT)
+#define EMC_TIMING3_0_QUSE_RANGE                        3:0
+#define EMC_TIMING3_0_QUSE_WOFFSET                      0x0
+#define EMC_TIMING3_0_QUSE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define EMC_TIMING3_0_QUSE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define EMC_TIMING3_0_QUSE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_QUSE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING3_0_QRST_SHIFT                        _MK_SHIFT_CONST(8)
+#define EMC_TIMING3_0_QRST_FIELD                        (_MK_MASK_CONST(0xf) << EMC_TIMING3_0_QRST_SHIFT)
+#define EMC_TIMING3_0_QRST_RANGE                        11:8
+#define EMC_TIMING3_0_QRST_WOFFSET                      0x0
+#define EMC_TIMING3_0_QRST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define EMC_TIMING3_0_QRST_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define EMC_TIMING3_0_QRST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_QRST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING3_0_QSAFE_SHIFT                       _MK_SHIFT_CONST(12)
+#define EMC_TIMING3_0_QSAFE_FIELD                       (_MK_MASK_CONST(0xf) << EMC_TIMING3_0_QSAFE_SHIFT)
+#define EMC_TIMING3_0_QSAFE_RANGE                       15:12
+#define EMC_TIMING3_0_QSAFE_WOFFSET                     0x0
+#define EMC_TIMING3_0_QSAFE_DEFAULT                     _MK_MASK_CONST(0x7)
+#define EMC_TIMING3_0_QSAFE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_TIMING3_0_QSAFE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_QSAFE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING3_0_RDV_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_TIMING3_0_RDV_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_TIMING3_0_RDV_SHIFT)
+#define EMC_TIMING3_0_RDV_RANGE                 20:16
+#define EMC_TIMING3_0_RDV_WOFFSET                       0x0
+#define EMC_TIMING3_0_RDV_DEFAULT                       _MK_MASK_CONST(0x8)
+#define EMC_TIMING3_0_RDV_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_TIMING3_0_RDV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_RDV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_TIMING3_0_RDV_MAX                   _MK_ENUM_CONST(11)
+
+
+// Register EMC_TIMING4_0  // Timing Control Register 4
+#define EMC_TIMING4_0                   _MK_ADDR_CONST(0x30)
+#define EMC_TIMING4_0_WORD_COUNT                        0x1
+#define EMC_TIMING4_0_RESET_VAL                         _MK_MASK_CONST(0x1f)
+#define EMC_TIMING4_0_RESET_MASK                        _MK_MASK_CONST(0x7001f)
+#define EMC_TIMING4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_READ_MASK                         _MK_MASK_CONST(0x7ffff)
+#define EMC_TIMING4_0_WRITE_MASK                        _MK_MASK_CONST(0x7ffff)
+#define EMC_TIMING4_0_REFRESH_LO_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_TIMING4_0_REFRESH_LO_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_TIMING4_0_REFRESH_LO_SHIFT)
+#define EMC_TIMING4_0_REFRESH_LO_RANGE                  4:0
+#define EMC_TIMING4_0_REFRESH_LO_WOFFSET                        0x0
+#define EMC_TIMING4_0_REFRESH_LO_DEFAULT                        _MK_MASK_CONST(0x1f)
+#define EMC_TIMING4_0_REFRESH_LO_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_TIMING4_0_REFRESH_LO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_REFRESH_LO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_REFRESH_LO_INIT_ENUM                      MAX
+#define EMC_TIMING4_0_REFRESH_LO_MAX                    _MK_ENUM_CONST(31)
+
+#define EMC_TIMING4_0_REFRESH_SHIFT                     _MK_SHIFT_CONST(5)
+#define EMC_TIMING4_0_REFRESH_FIELD                     (_MK_MASK_CONST(0x7ff) << EMC_TIMING4_0_REFRESH_SHIFT)
+#define EMC_TIMING4_0_REFRESH_RANGE                     15:5
+#define EMC_TIMING4_0_REFRESH_WOFFSET                   0x0
+#define EMC_TIMING4_0_REFRESH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_REFRESH_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_REFRESH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_REFRESH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_FIELD                   (_MK_MASK_CONST(0x7) << EMC_TIMING4_0_BURST_REFRESH_NUM_SHIFT)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_RANGE                   18:16
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_WOFFSET                 0x0
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_INIT_ENUM                       BR1
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR1                     _MK_ENUM_CONST(0)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR2                     _MK_ENUM_CONST(1)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR3                     _MK_ENUM_CONST(2)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR4                     _MK_ENUM_CONST(3)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR5                     _MK_ENUM_CONST(4)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR6                     _MK_ENUM_CONST(5)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR7                     _MK_ENUM_CONST(6)
+#define EMC_TIMING4_0_BURST_REFRESH_NUM_BR8                     _MK_ENUM_CONST(7)
+
+
+// Register EMC_TIMING5_0  // Timing Control Register 5
+#define EMC_TIMING5_0                   _MK_ADDR_CONST(0x34)
+#define EMC_TIMING5_0_WORD_COUNT                        0x1
+#define EMC_TIMING5_0_RESET_VAL                         _MK_MASK_CONST(0x1ffffff)
+#define EMC_TIMING5_0_RESET_MASK                        _MK_MASK_CONST(0x1ffffff)
+#define EMC_TIMING5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_READ_MASK                         _MK_MASK_CONST(0x1ffffff)
+#define EMC_TIMING5_0_WRITE_MASK                        _MK_MASK_CONST(0x1ffffff)
+#define EMC_TIMING5_0_PDEX2WR_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_TIMING5_0_PDEX2WR_FIELD                     (_MK_MASK_CONST(0xf) << EMC_TIMING5_0_PDEX2WR_SHIFT)
+#define EMC_TIMING5_0_PDEX2WR_RANGE                     3:0
+#define EMC_TIMING5_0_PDEX2WR_WOFFSET                   0x0
+#define EMC_TIMING5_0_PDEX2WR_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PDEX2WR_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PDEX2WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_PDEX2WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING5_0_PDEX2RD_SHIFT                     _MK_SHIFT_CONST(4)
+#define EMC_TIMING5_0_PDEX2RD_FIELD                     (_MK_MASK_CONST(0xf) << EMC_TIMING5_0_PDEX2RD_SHIFT)
+#define EMC_TIMING5_0_PDEX2RD_RANGE                     7:4
+#define EMC_TIMING5_0_PDEX2RD_WOFFSET                   0x0
+#define EMC_TIMING5_0_PDEX2RD_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PDEX2RD_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PDEX2RD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_PDEX2RD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING5_0_PCHG2PDEN_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_TIMING5_0_PCHG2PDEN_FIELD                   (_MK_MASK_CONST(0xf) << EMC_TIMING5_0_PCHG2PDEN_SHIFT)
+#define EMC_TIMING5_0_PCHG2PDEN_RANGE                   11:8
+#define EMC_TIMING5_0_PCHG2PDEN_WOFFSET                 0x0
+#define EMC_TIMING5_0_PCHG2PDEN_DEFAULT                 _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PCHG2PDEN_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_PCHG2PDEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_PCHG2PDEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING5_0_RW2PDEN_SHIFT                     _MK_SHIFT_CONST(12)
+#define EMC_TIMING5_0_RW2PDEN_FIELD                     (_MK_MASK_CONST(0xf) << EMC_TIMING5_0_RW2PDEN_SHIFT)
+#define EMC_TIMING5_0_RW2PDEN_RANGE                     15:12
+#define EMC_TIMING5_0_RW2PDEN_WOFFSET                   0x0
+#define EMC_TIMING5_0_RW2PDEN_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_RW2PDEN_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_RW2PDEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_RW2PDEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING5_0_ACT2PDEN_SHIFT                    _MK_SHIFT_CONST(16)
+#define EMC_TIMING5_0_ACT2PDEN_FIELD                    (_MK_MASK_CONST(0xf) << EMC_TIMING5_0_ACT2PDEN_SHIFT)
+#define EMC_TIMING5_0_ACT2PDEN_RANGE                    19:16
+#define EMC_TIMING5_0_ACT2PDEN_WOFFSET                  0x0
+#define EMC_TIMING5_0_ACT2PDEN_DEFAULT                  _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_ACT2PDEN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_TIMING5_0_ACT2PDEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_ACT2PDEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_TIMING5_0_AR2PDEN_SHIFT                     _MK_SHIFT_CONST(20)
+#define EMC_TIMING5_0_AR2PDEN_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_TIMING5_0_AR2PDEN_SHIFT)
+#define EMC_TIMING5_0_AR2PDEN_RANGE                     24:20
+#define EMC_TIMING5_0_AR2PDEN_WOFFSET                   0x0
+#define EMC_TIMING5_0_AR2PDEN_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_TIMING5_0_AR2PDEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_TIMING5_0_AR2PDEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_TIMING5_0_AR2PDEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_MRS_0  // MRS value
+#define EMC_MRS_0                       _MK_ADDR_CONST(0x38)
+#define EMC_MRS_0_WORD_COUNT                    0x1
+#define EMC_MRS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_READ_MASK                     _MK_MASK_CONST(0x303fff)
+#define EMC_MRS_0_WRITE_MASK                    _MK_MASK_CONST(0x303fff)
+#define EMC_MRS_0_MRS_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_MRS_0_MRS_ADR_FIELD                 (_MK_MASK_CONST(0x3fff) << EMC_MRS_0_MRS_ADR_SHIFT)
+#define EMC_MRS_0_MRS_ADR_RANGE                 13:0
+#define EMC_MRS_0_MRS_ADR_WOFFSET                       0x0
+#define EMC_MRS_0_MRS_ADR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_MRS_0_MRS_BA_SHIFT                  _MK_SHIFT_CONST(20)
+#define EMC_MRS_0_MRS_BA_FIELD                  (_MK_MASK_CONST(0x3) << EMC_MRS_0_MRS_BA_SHIFT)
+#define EMC_MRS_0_MRS_BA_RANGE                  21:20
+#define EMC_MRS_0_MRS_BA_WOFFSET                        0x0
+#define EMC_MRS_0_MRS_BA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_EMRS_0  // EMRS value
+#define EMC_EMRS_0                      _MK_ADDR_CONST(0x3c)
+#define EMC_EMRS_0_WORD_COUNT                   0x1
+#define EMC_EMRS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_READ_MASK                    _MK_MASK_CONST(0x303fff)
+#define EMC_EMRS_0_WRITE_MASK                   _MK_MASK_CONST(0x303fff)
+#define EMC_EMRS_0_EMRS_ADR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_EMRS_0_EMRS_ADR_FIELD                       (_MK_MASK_CONST(0x3fff) << EMC_EMRS_0_EMRS_ADR_SHIFT)
+#define EMC_EMRS_0_EMRS_ADR_RANGE                       13:0
+#define EMC_EMRS_0_EMRS_ADR_WOFFSET                     0x0
+#define EMC_EMRS_0_EMRS_ADR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_EMRS_0_EMRS_BA_SHIFT                        _MK_SHIFT_CONST(20)
+#define EMC_EMRS_0_EMRS_BA_FIELD                        (_MK_MASK_CONST(0x3) << EMC_EMRS_0_EMRS_BA_SHIFT)
+#define EMC_EMRS_0_EMRS_BA_RANGE                        21:20
+#define EMC_EMRS_0_EMRS_BA_WOFFSET                      0x0
+#define EMC_EMRS_0_EMRS_BA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_REF_0  // Refresh command register
+#define EMC_REF_0                       _MK_ADDR_CONST(0x40)
+#define EMC_REF_0_WORD_COUNT                    0x1
+#define EMC_REF_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_REF_0_RESET_MASK                    _MK_MASK_CONST(0xff01)
+#define EMC_REF_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_REF_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_READ_MASK                     _MK_MASK_CONST(0xff01)
+#define EMC_REF_0_WRITE_MASK                    _MK_MASK_CONST(0xff01)
+#define EMC_REF_0_REF_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_REF_0_REF_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_REF_0_REF_CMD_SHIFT)
+#define EMC_REF_0_REF_CMD_RANGE                 0:0
+#define EMC_REF_0_REF_CMD_WOFFSET                       0x0
+#define EMC_REF_0_REF_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_REF_0_REF_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_REF_0_REF_NUM_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_REF_0_REF_NUM_FIELD                 (_MK_MASK_CONST(0xff) << EMC_REF_0_REF_NUM_SHIFT)
+#define EMC_REF_0_REF_NUM_RANGE                 15:8
+#define EMC_REF_0_REF_NUM_WOFFSET                       0x0
+#define EMC_REF_0_REF_NUM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_NUM_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_REF_0_REF_NUM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_NUM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_PRE_0  // Precharge command register
+#define EMC_PRE_0                       _MK_ADDR_CONST(0x44)
+#define EMC_PRE_0_WORD_COUNT                    0x1
+#define EMC_PRE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_PRE_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_PRE_0_PRE_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PRE_0_PRE_CMD_SHIFT)
+#define EMC_PRE_0_PRE_CMD_RANGE                 0:0
+#define EMC_PRE_0_PRE_CMD_WOFFSET                       0x0
+#define EMC_PRE_0_PRE_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_PRE_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_NOP_0  // NOP command register
+#define EMC_NOP_0                       _MK_ADDR_CONST(0x48)
+#define EMC_NOP_0_WORD_COUNT                    0x1
+#define EMC_NOP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_NOP_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_NOP_0_NOP_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_NOP_0_NOP_CMD_SHIFT)
+#define EMC_NOP_0_NOP_CMD_RANGE                 0:0
+#define EMC_NOP_0_NOP_CMD_WOFFSET                       0x0
+#define EMC_NOP_0_NOP_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_NOP_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_NOP_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_NOP_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_SELF_REF_0  // SELF REFRESH command register
+#define EMC_SELF_REF_0                  _MK_ADDR_CONST(0x4c)
+#define EMC_SELF_REF_0_WORD_COUNT                       0x1
+#define EMC_SELF_REF_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_SELF_REF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_SELF_REF_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_SELF_REF_0_SELF_REF_CMD_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_FIELD                       (_MK_MASK_CONST(0x1) << EMC_SELF_REF_0_SELF_REF_CMD_SHIFT)
+#define EMC_SELF_REF_0_SELF_REF_CMD_RANGE                       0:0
+#define EMC_SELF_REF_0_SELF_REF_CMD_WOFFSET                     0x0
+#define EMC_SELF_REF_0_SELF_REF_CMD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_SELF_REF_0_SELF_REF_CMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_INIT_ENUM                   DISABLED
+#define EMC_SELF_REF_0_SELF_REF_CMD_DISABLED                    _MK_ENUM_CONST(0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_ENABLED                     _MK_ENUM_CONST(1)
+
+
+// Register EMC_DPD_0  // Deep Power Down command register
+#define EMC_DPD_0                       _MK_ADDR_CONST(0x50)
+#define EMC_DPD_0_WORD_COUNT                    0x1
+#define EMC_DPD_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_DPD_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_DPD_0_DPD_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DPD_0_DPD_CMD_SHIFT)
+#define EMC_DPD_0_DPD_CMD_RANGE                 0:0
+#define EMC_DPD_0_DPD_CMD_WOFFSET                       0x0
+#define EMC_DPD_0_DPD_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_DPD_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_INIT_ENUM                     DISABLED
+#define EMC_DPD_0_DPD_CMD_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_DPD_0_DPD_CMD_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register EMC_CMDQ_0  // Command Queue Depth register
+#define EMC_CMDQ_0                      _MK_ADDR_CONST(0x54)
+#define EMC_CMDQ_0_WORD_COUNT                   0x1
+#define EMC_CMDQ_0_RESET_VAL                    _MK_MASK_CONST(0x1304)
+#define EMC_CMDQ_0_RESET_MASK                   _MK_MASK_CONST(0x770f)
+#define EMC_CMDQ_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_READ_MASK                    _MK_MASK_CONST(0x770f)
+#define EMC_CMDQ_0_WRITE_MASK                   _MK_MASK_CONST(0x770f)
+#define EMC_CMDQ_0_RW_DEPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_CMDQ_0_RW_DEPTH_FIELD                       (_MK_MASK_CONST(0xf) << EMC_CMDQ_0_RW_DEPTH_SHIFT)
+#define EMC_CMDQ_0_RW_DEPTH_RANGE                       3:0
+#define EMC_CMDQ_0_RW_DEPTH_WOFFSET                     0x0
+#define EMC_CMDQ_0_RW_DEPTH_DEFAULT                     _MK_MASK_CONST(0x4)
+#define EMC_CMDQ_0_RW_DEPTH_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_CMDQ_0_RW_DEPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_RW_DEPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_CMDQ_0_ACT_DEPTH_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_CMDQ_0_ACT_DEPTH_FIELD                      (_MK_MASK_CONST(0x7) << EMC_CMDQ_0_ACT_DEPTH_SHIFT)
+#define EMC_CMDQ_0_ACT_DEPTH_RANGE                      10:8
+#define EMC_CMDQ_0_ACT_DEPTH_WOFFSET                    0x0
+#define EMC_CMDQ_0_ACT_DEPTH_DEFAULT                    _MK_MASK_CONST(0x3)
+#define EMC_CMDQ_0_ACT_DEPTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_CMDQ_0_ACT_DEPTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_ACT_DEPTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_CMDQ_0_PRE_DEPTH_SHIFT                      _MK_SHIFT_CONST(12)
+#define EMC_CMDQ_0_PRE_DEPTH_FIELD                      (_MK_MASK_CONST(0x7) << EMC_CMDQ_0_PRE_DEPTH_SHIFT)
+#define EMC_CMDQ_0_PRE_DEPTH_RANGE                      14:12
+#define EMC_CMDQ_0_PRE_DEPTH_WOFFSET                    0x0
+#define EMC_CMDQ_0_PRE_DEPTH_DEFAULT                    _MK_MASK_CONST(0x1)
+#define EMC_CMDQ_0_PRE_DEPTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_CMDQ_0_PRE_DEPTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_PRE_DEPTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_CFG1_0  // FBIO configuration register
+#define EMC_FBIO_CFG1_0                 _MK_ADDR_CONST(0x58)
+#define EMC_FBIO_CFG1_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_RESET_MASK                      _MK_MASK_CONST(0x10000)
+#define EMC_FBIO_CFG1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_READ_MASK                       _MK_MASK_CONST(0x10000)
+#define EMC_FBIO_CFG1_0_WRITE_MASK                      _MK_MASK_CONST(0x10000)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_FIELD                     (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SHIFT)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_RANGE                     16:16
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_WOFFSET                   0x0
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_INIT_ENUM                 DISABLE
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DISABLE                   _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_FBIO_DQSIB_DLY_0  // FBIO configuration register
+#define EMC_FBIO_DQSIB_DLY_0                    _MK_ADDR_CONST(0x5c)
+#define EMC_FBIO_DQSIB_DLY_0_WORD_COUNT                         0x1
+#define EMC_FBIO_DQSIB_DLY_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_DQSIB_DLY_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_RANGE                 7:0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_MAX                   _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_RANGE                 15:8
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_MAX                   _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_RANGE                 23:16
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_MAX                   _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_RANGE                 31:24
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_MAX                   _MK_ENUM_CONST(47)
+
+
+// Register EMC_FBIO_SPARE_0  // FBIO spare register
+#define EMC_FBIO_SPARE_0                        _MK_ADDR_CONST(0x60)
+#define EMC_FBIO_SPARE_0_WORD_COUNT                     0x1
+#define EMC_FBIO_SPARE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SHIFT)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_RANGE                   31:0
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WOFFSET                 0x0
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_CFG5_0  // FBIO configuration Register 
+#define EMC_FBIO_CFG5_0                 _MK_ADDR_CONST(0x64)
+#define EMC_FBIO_CFG5_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG5_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_RESET_MASK                      _MK_MASK_CONST(0x11)
+#define EMC_FBIO_CFG5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_READ_MASK                       _MK_MASK_CONST(0x11)
+#define EMC_FBIO_CFG5_0_WRITE_MASK                      _MK_MASK_CONST(0x11)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_FIELD                 (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DRAM_TYPE_SHIFT)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_RANGE                 0:0
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_WOFFSET                       0x0
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_INIT_ENUM                     SDR
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SDR                   _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DDR1                  _MK_ENUM_CONST(1)
+
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SHIFT                        _MK_SHIFT_CONST(4)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_FIELD                        (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DRAM_WIDTH_SHIFT)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_RANGE                        4:4
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_WOFFSET                      0x0
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_INIT_ENUM                    X32
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_X32                  _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_X16                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_FBIO_WRPTR_EQ_2_0  // FBIO wrptr register
+#define EMC_FBIO_WRPTR_EQ_2_0                   _MK_ADDR_CONST(0x68)
+#define EMC_FBIO_WRPTR_EQ_2_0_WORD_COUNT                        0x1
+#define EMC_FBIO_WRPTR_EQ_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define EMC_FBIO_WRPTR_EQ_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_FIELD                       (_MK_MASK_CONST(0xf) << EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SHIFT)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_RANGE                       3:0
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_WOFFSET                     0x0
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_QUSE_DLY_0  // QUSE delay register   
+#define EMC_FBIO_QUSE_DLY_0                     _MK_ADDR_CONST(0x6c)
+#define EMC_FBIO_QUSE_DLY_0_WORD_COUNT                  0x1
+#define EMC_FBIO_QUSE_DLY_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_QUSE_DLY_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_RANGE                   7:0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_MAX                     _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_RANGE                   15:8
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_MAX                     _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_RANGE                   23:16
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_MAX                     _MK_ENUM_CONST(47)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_RANGE                   31:24
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_MAX                     _MK_ENUM_CONST(47)
+
+
+// Register EMC_FBIO_CFG6_0  // FBIO configuration register   
+#define EMC_FBIO_CFG6_0                 _MK_ADDR_CONST(0x70)
+#define EMC_FBIO_CFG6_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG6_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define EMC_FBIO_CFG6_0_RESET_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_READ_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_WRITE_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_FIELD                     (_MK_MASK_CONST(0x7) << EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SHIFT)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_RANGE                     2:0
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_WOFFSET                   0x0
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_BUSARB_0  // Bus Arbitration Timeout register
+#define EMC_BUSARB_0                    _MK_ADDR_CONST(0x74)
+#define EMC_BUSARB_0_WORD_COUNT                         0x1
+#define EMC_BUSARB_0_RESET_VAL                  _MK_MASK_CONST(0x13ff02f)
+#define EMC_BUSARB_0_RESET_MASK                         _MK_MASK_CONST(0x1ffff3ff)
+#define EMC_BUSARB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_BUSARB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_BUSARB_0_READ_MASK                  _MK_MASK_CONST(0x1ffff3ff)
+#define EMC_BUSARB_0_WRITE_MASK                         _MK_MASK_CONST(0x1ffff3ff)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_FIELD                   (_MK_MASK_CONST(0x3ff) << EMC_BUSARB_0_EMC_MIN_TRANS_TIME_SHIFT)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_RANGE                   9:0
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_WOFFSET                 0x0
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_DEFAULT                 _MK_MASK_CONST(0x2f)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0x3ff)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_BUSARB_0_EMC_MIN_TRANS_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_SHIFT                   _MK_SHIFT_CONST(12)
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_FIELD                   (_MK_MASK_CONST(0xfff) << EMC_BUSARB_0_NOR_MAX_TRANS_TIME_SHIFT)
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_RANGE                   23:12
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_WOFFSET                 0x0
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_DEFAULT                 _MK_MASK_CONST(0x3ff)
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_BUSARB_0_NOR_MAX_TRANS_TIME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_BUSARB_0_BUS_TURNAROUND_SHIFT                       _MK_SHIFT_CONST(24)
+#define EMC_BUSARB_0_BUS_TURNAROUND_FIELD                       (_MK_MASK_CONST(0x1f) << EMC_BUSARB_0_BUS_TURNAROUND_SHIFT)
+#define EMC_BUSARB_0_BUS_TURNAROUND_RANGE                       28:24
+#define EMC_BUSARB_0_BUS_TURNAROUND_WOFFSET                     0x0
+#define EMC_BUSARB_0_BUS_TURNAROUND_DEFAULT                     _MK_MASK_CONST(0x1)
+#define EMC_BUSARB_0_BUS_TURNAROUND_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define EMC_BUSARB_0_BUS_TURNAROUND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_BUSARB_0_BUS_TURNAROUND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DYN_DQS_0  
+#define EMC_DYN_DQS_0                   _MK_ADDR_CONST(0x78)
+#define EMC_DYN_DQS_0_WORD_COUNT                        0x1
+#define EMC_DYN_DQS_0_RESET_VAL                         _MK_MASK_CONST(0x8000010)
+#define EMC_DYN_DQS_0_RESET_MASK                        _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_DQS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_READ_MASK                         _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_DQS_0_WRITE_MASK                        _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_FIELD                        (_MK_MASK_CONST(0x1f) << EMC_DYN_DQS_0_DYN_DQS_MULT_SHIFT)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_RANGE                        4:0
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_WOFFSET                      0x0
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_DEFAULT                      _MK_MASK_CONST(0x10)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_MULT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_SHIFT                        _MK_SHIFT_CONST(8)
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_FIELD                        (_MK_MASK_CONST(0x7ff) << EMC_DYN_DQS_0_DYN_DQS_OFFS_SHIFT)
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_RANGE                        18:8
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_WOFFSET                      0x0
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_DEFAULT_MASK                 _MK_MASK_CONST(0x7ff)
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_OFFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_FIELD                     (_MK_MASK_CONST(0xf) << EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_SHIFT)
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_RANGE                     27:24
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_WOFFSET                   0x0
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_MAX_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_SHIFT                      _MK_SHIFT_CONST(28)
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_DYN_DQS_0_DYN_DQS_FREEZE_SHIFT)
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_RANGE                      28:28
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_WOFFSET                    0x0
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_FREEZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_DYN_DQS_0_DYN_DQS_ENABLE_SHIFT)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_RANGE                      31:31
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_WOFFSET                    0x0
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_INIT_ENUM                  DISABLED
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_DYN_DQS_0_DYN_DQS_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_DYN_QUSE_0  
+#define EMC_DYN_QUSE_0                  _MK_ADDR_CONST(0x7c)
+#define EMC_DYN_QUSE_0_WORD_COUNT                       0x1
+#define EMC_DYN_QUSE_0_RESET_VAL                        _MK_MASK_CONST(0x9000008)
+#define EMC_DYN_QUSE_0_RESET_MASK                       _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_QUSE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_READ_MASK                        _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_QUSE_0_WRITE_MASK                       _MK_MASK_CONST(0x9f07ff1f)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_FIELD                      (_MK_MASK_CONST(0x1f) << EMC_DYN_QUSE_0_DYN_QUSE_MULT_SHIFT)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_RANGE                      4:0
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_WOFFSET                    0x0
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_DEFAULT                    _MK_MASK_CONST(0x8)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MULT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_FIELD                      (_MK_MASK_CONST(0x7ff) << EMC_DYN_QUSE_0_DYN_QUSE_OFFS_SHIFT)
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_RANGE                      18:8
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_WOFFSET                    0x0
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_OFFS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_FIELD                   (_MK_MASK_CONST(0xf) << EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_SHIFT)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_RANGE                   27:24
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_WOFFSET                 0x0
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_DEFAULT                 _MK_MASK_CONST(0x9)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_MAX_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_SHIFT                    _MK_SHIFT_CONST(28)
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_SHIFT)
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_RANGE                    28:28
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_WOFFSET                  0x0
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_FREEZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_SHIFT                    _MK_SHIFT_CONST(31)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_SHIFT)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_RANGE                    31:31
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_WOFFSET                  0x0
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_INIT_ENUM                        DISABLED
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_DYN_QUSE_0_DYN_QUSE_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_DQS_TRIMMER_RD0_0  
+#define EMC_DQS_TRIMMER_RD0_0                   _MK_ADDR_CONST(0x80)
+#define EMC_DQS_TRIMMER_RD0_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
+#define EMC_DQS_TRIMMER_RD0_0_WRITE_MASK                        _MK_MASK_CONST(0xe0000000)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_FIELD                    (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_RANGE                    7:0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_WOFFSET                  0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_RANGE                 15:8
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_SHIFT                 _MK_SHIFT_CONST(29)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_RANGE                 29:29
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_NEQ_CURRENT_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_SHIFT                  _MK_SHIFT_CONST(30)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_RANGE                  30:30
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEXT_EQ_CURRENT_BYTE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_SHIFT                  _MK_SHIFT_CONST(31)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_RANGE                  31:31
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_NEW_CURRENT_VAL_BYTE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD1_0  
+#define EMC_DQS_TRIMMER_RD1_0                   _MK_ADDR_CONST(0x84)
+#define EMC_DQS_TRIMMER_RD1_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
+#define EMC_DQS_TRIMMER_RD1_0_WRITE_MASK                        _MK_MASK_CONST(0xe0000000)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_FIELD                    (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_RANGE                    7:0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_WOFFSET                  0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_RANGE                 15:8
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_SHIFT                 _MK_SHIFT_CONST(29)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_RANGE                 29:29
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_NEQ_CURRENT_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_SHIFT                  _MK_SHIFT_CONST(30)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_RANGE                  30:30
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEXT_EQ_CURRENT_BYTE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_SHIFT                  _MK_SHIFT_CONST(31)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_RANGE                  31:31
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_NEW_CURRENT_VAL_BYTE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD2_0  
+#define EMC_DQS_TRIMMER_RD2_0                   _MK_ADDR_CONST(0x88)
+#define EMC_DQS_TRIMMER_RD2_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
+#define EMC_DQS_TRIMMER_RD2_0_WRITE_MASK                        _MK_MASK_CONST(0xe0000000)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_FIELD                    (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_RANGE                    7:0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_WOFFSET                  0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_RANGE                 15:8
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_SHIFT                 _MK_SHIFT_CONST(29)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_RANGE                 29:29
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_NEQ_CURRENT_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_SHIFT                  _MK_SHIFT_CONST(30)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_RANGE                  30:30
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEXT_EQ_CURRENT_BYTE_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_SHIFT                  _MK_SHIFT_CONST(31)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_RANGE                  31:31
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_NEW_CURRENT_VAL_BYTE_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD3_0  
+#define EMC_DQS_TRIMMER_RD3_0                   _MK_ADDR_CONST(0x8c)
+#define EMC_DQS_TRIMMER_RD3_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_READ_MASK                         _MK_MASK_CONST(0xe000ffff)
+#define EMC_DQS_TRIMMER_RD3_0_WRITE_MASK                        _MK_MASK_CONST(0xe0000000)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_FIELD                    (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_RANGE                    7:0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_WOFFSET                  0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_RANGE                 15:8
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_SHIFT                 _MK_SHIFT_CONST(29)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_RANGE                 29:29
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_NEQ_CURRENT_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_SHIFT                  _MK_SHIFT_CONST(30)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_RANGE                  30:30
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEXT_EQ_CURRENT_BYTE_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_SHIFT                  _MK_SHIFT_CONST(31)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_FIELD                  (_MK_MASK_CONST(0x1) << EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_RANGE                  31:31
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_WOFFSET                        0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_NEW_CURRENT_VAL_BYTE_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QUSE_TRIMMER_RD0_0  
+#define EMC_QUSE_TRIMMER_RD0_0                  _MK_ADDR_CONST(0x90)
+#define EMC_QUSE_TRIMMER_RD0_0_WORD_COUNT                       0x1
+#define EMC_QUSE_TRIMMER_RD0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_READ_MASK                        _MK_MASK_CONST(0xe000ffff)
+#define EMC_QUSE_TRIMMER_RD0_0_WRITE_MASK                       _MK_MASK_CONST(0xe0000000)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_FIELD                  (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_RANGE                  7:0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_WOFFSET                        0x0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_FIELD                       (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_RANGE                       15:8
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_FIELD                       (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_SHIFT)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_RANGE                       29:29
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_NEQ_CURRENT_BYTE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_SHIFT                        _MK_SHIFT_CONST(30)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_SHIFT)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_RANGE                        30:30
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEXT_EQ_CURRENT_BYTE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_SHIFT                        _MK_SHIFT_CONST(31)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_SHIFT)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_RANGE                        31:31
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD0_0_QUSE_NEW_CURRENT_VAL_BYTE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QUSE_TRIMMER_RD1_0  
+#define EMC_QUSE_TRIMMER_RD1_0                  _MK_ADDR_CONST(0x94)
+#define EMC_QUSE_TRIMMER_RD1_0_WORD_COUNT                       0x1
+#define EMC_QUSE_TRIMMER_RD1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_READ_MASK                        _MK_MASK_CONST(0xe000ffff)
+#define EMC_QUSE_TRIMMER_RD1_0_WRITE_MASK                       _MK_MASK_CONST(0xe0000000)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_FIELD                  (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_RANGE                  7:0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_WOFFSET                        0x0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_FIELD                       (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_RANGE                       15:8
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_FIELD                       (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_SHIFT)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_RANGE                       29:29
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_NEQ_CURRENT_BYTE_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_SHIFT                        _MK_SHIFT_CONST(30)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_SHIFT)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_RANGE                        30:30
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEXT_EQ_CURRENT_BYTE_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_SHIFT                        _MK_SHIFT_CONST(31)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_SHIFT)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_RANGE                        31:31
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD1_0_QUSE_NEW_CURRENT_VAL_BYTE_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QUSE_TRIMMER_RD2_0  
+#define EMC_QUSE_TRIMMER_RD2_0                  _MK_ADDR_CONST(0x98)
+#define EMC_QUSE_TRIMMER_RD2_0_WORD_COUNT                       0x1
+#define EMC_QUSE_TRIMMER_RD2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_READ_MASK                        _MK_MASK_CONST(0xe000ffff)
+#define EMC_QUSE_TRIMMER_RD2_0_WRITE_MASK                       _MK_MASK_CONST(0xe0000000)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_FIELD                  (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_RANGE                  7:0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_WOFFSET                        0x0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_FIELD                       (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_RANGE                       15:8
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_FIELD                       (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_SHIFT)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_RANGE                       29:29
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_NEQ_CURRENT_BYTE_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_SHIFT                        _MK_SHIFT_CONST(30)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_SHIFT)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_RANGE                        30:30
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEXT_EQ_CURRENT_BYTE_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_SHIFT                        _MK_SHIFT_CONST(31)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_SHIFT)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_RANGE                        31:31
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD2_0_QUSE_NEW_CURRENT_VAL_BYTE_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QUSE_TRIMMER_RD3_0  
+#define EMC_QUSE_TRIMMER_RD3_0                  _MK_ADDR_CONST(0x9c)
+#define EMC_QUSE_TRIMMER_RD3_0_WORD_COUNT                       0x1
+#define EMC_QUSE_TRIMMER_RD3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_READ_MASK                        _MK_MASK_CONST(0xe000ffff)
+#define EMC_QUSE_TRIMMER_RD3_0_WRITE_MASK                       _MK_MASK_CONST(0xe0000000)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_FIELD                  (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_RANGE                  7:0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_WOFFSET                        0x0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_FIELD                       (_MK_MASK_CONST(0xff) << EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_RANGE                       15:8
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_FIELD                       (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_SHIFT)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_RANGE                       29:29
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_WOFFSET                     0x0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_NEQ_CURRENT_BYTE_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_SHIFT                        _MK_SHIFT_CONST(30)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_SHIFT)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_RANGE                        30:30
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEXT_EQ_CURRENT_BYTE_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_SHIFT                        _MK_SHIFT_CONST(31)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_FIELD                        (_MK_MASK_CONST(0x1) << EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_SHIFT)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_RANGE                        31:31
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_WOFFSET                      0x0
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_QUSE_TRIMMER_RD3_0_QUSE_NEW_CURRENT_VAL_BYTE_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_CLKEN_OVERRIDE_0  
+#define EMC_CLKEN_OVERRIDE_0                    _MK_ADDR_CONST(0xa0)
+#define EMC_CLKEN_OVERRIDE_0_WORD_COUNT                         0x1
+#define EMC_CLKEN_OVERRIDE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
+#define EMC_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_READ_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_CLKEN_OVERRIDE_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_RANGE                        0:0
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_WOFFSET                      0x0
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SHIFT                       _MK_SHIFT_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_FIELD                       (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_RANGE                       1:1
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_WOFFSET                     0x0
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_INIT_ENUM                   CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_CLK_GATED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_CLK_ALWAYS_ON                       _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DISABLE                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_ENABLE                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DISABLED                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_ENABLED                     _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SHIFT                      _MK_SHIFT_CONST(2)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_RANGE                      2:2
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_WOFFSET                    0x0
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_INIT_ENUM                  CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_CLK_GATED                  _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_CLK_ALWAYS_ON                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DISABLE                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_ENABLE                     _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_ENABLED                    _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(3)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_RANGE                 3:3
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_WOFFSET                       0x0
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(4)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_RANGE                 4:4
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_WOFFSET                       0x0
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SHIFT                      _MK_SHIFT_CONST(5)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_RANGE                      5:5
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_WOFFSET                    0x0
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_INIT_ENUM                  CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_CLK_GATED                  _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_CLK_ALWAYS_ON                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DISABLE                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_ENABLE                     _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_ENABLED                    _MK_ENUM_CONST(1)
+
+#define NV_MC_EMEM_DFIFO_DEPTH  3
+#define NV_MC_IMEM_DFIFO_DEPTH  5
+#define NV_MC_EMEM_APFIFO_DEPTH 4
+#define NV_MC_ARB_EMEM_REGLEVEL 3
+#define NV_MC_EMEM_REQ_ID_WIDEREQ       9
+#define NV_MC_EMEM_RDI_ID_WIDERDI       9
+#define NV_MC_EMEM_REQ_ID_ILLEGALACC    8
+#define NV_MC_EMEM_RDI_ID_ILLEGALACC    8
+#define NV_MC_EMEM_REQ_ID_LLRAWDECR     7
+#define NV_MC_EMEM_RDI_ID_LLRAWDECR     7
+#define NV_MC_EMEM_REQ_ID_APCIGNORE     6
+#define NV_MC_EMEM_RDI_ID_APCIGNORE     6
+
+// Packet MC2EMC
+#define MC2EMC_SIZE 190
+
+#define MC2EMC_WDO_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_SHIFT)
+#define MC2EMC_WDO_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_ROW                  0
+
+#define MC2EMC_WDO_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_0_SHIFT)
+#define MC2EMC_WDO_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_ROW                        0
+
+#define MC2EMC_WDO_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_1_SHIFT)
+#define MC2EMC_WDO_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_ROW                        0
+
+#define MC2EMC_WDO_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_2_SHIFT)
+#define MC2EMC_WDO_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_ROW                        0
+
+#define MC2EMC_WDO_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_3_SHIFT)
+#define MC2EMC_WDO_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_ROW                        0
+
+#define MC2EMC_BE_SHIFT                 _MK_SHIFT_CONST(128)
+#define MC2EMC_BE_FIELD                 (_MK_MASK_CONST(0xffff) << MC2EMC_BE_SHIFT)
+#define MC2EMC_BE_RANGE                 _MK_SHIFT_CONST(143):_MK_SHIFT_CONST(128)
+#define MC2EMC_BE_ROW                   0
+
+#define MC2EMC_DEV_SHIFT                        _MK_SHIFT_CONST(144)
+#define MC2EMC_DEV_FIELD                        (_MK_MASK_CONST(0x3) << MC2EMC_DEV_SHIFT)
+#define MC2EMC_DEV_RANGE                        _MK_SHIFT_CONST(145):_MK_SHIFT_CONST(144)
+#define MC2EMC_DEV_ROW                  0
+
+#define MC2EMC_BANK_SHIFT                       _MK_SHIFT_CONST(146)
+#define MC2EMC_BANK_FIELD                       (_MK_MASK_CONST(0x3) << MC2EMC_BANK_SHIFT)
+#define MC2EMC_BANK_RANGE                       _MK_SHIFT_CONST(147):_MK_SHIFT_CONST(146)
+#define MC2EMC_BANK_ROW                 0
+
+#define MC2EMC_ROW_SHIFT                        _MK_SHIFT_CONST(148)
+#define MC2EMC_ROW_FIELD                        (_MK_MASK_CONST(0x3fff) << MC2EMC_ROW_SHIFT)
+#define MC2EMC_ROW_RANGE                        _MK_SHIFT_CONST(161):_MK_SHIFT_CONST(148)
+#define MC2EMC_ROW_ROW                  0
+
+#define MC2EMC_COL_SHIFT                        _MK_SHIFT_CONST(162)
+#define MC2EMC_COL_FIELD                        (_MK_MASK_CONST(0x7ff) << MC2EMC_COL_SHIFT)
+#define MC2EMC_COL_RANGE                        _MK_SHIFT_CONST(172):_MK_SHIFT_CONST(162)
+#define MC2EMC_COL_ROW                  0
+
+#define MC2EMC_REQ_ID_SHIFT                     _MK_SHIFT_CONST(173)
+#define MC2EMC_REQ_ID_FIELD                     (_MK_MASK_CONST(0x3ff) << MC2EMC_REQ_ID_SHIFT)
+#define MC2EMC_REQ_ID_RANGE                     _MK_SHIFT_CONST(182):_MK_SHIFT_CONST(173)
+#define MC2EMC_REQ_ID_ROW                       0
+
+#define MC2EMC_AP_SHIFT                 _MK_SHIFT_CONST(183)
+#define MC2EMC_AP_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_AP_SHIFT)
+#define MC2EMC_AP_RANGE                 _MK_SHIFT_CONST(183):_MK_SHIFT_CONST(183)
+#define MC2EMC_AP_ROW                   0
+
+#define MC2EMC_WE_SHIFT                 _MK_SHIFT_CONST(184)
+#define MC2EMC_WE_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_WE_SHIFT)
+#define MC2EMC_WE_RANGE                 _MK_SHIFT_CONST(184):_MK_SHIFT_CONST(184)
+#define MC2EMC_WE_ROW                   0
+
+#define MC2EMC_TAG_SHIFT                        _MK_SHIFT_CONST(185)
+#define MC2EMC_TAG_FIELD                        (_MK_MASK_CONST(0x1f) << MC2EMC_TAG_SHIFT)
+#define MC2EMC_TAG_RANGE                        _MK_SHIFT_CONST(189):_MK_SHIFT_CONST(185)
+#define MC2EMC_TAG_ROW                  0
+
+
+// Packet MC2EMC_APC
+#define MC2EMC_APC_SIZE 3
+
+#define MC2EMC_APC_CLR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_FIELD                    (_MK_MASK_CONST(0x1) << MC2EMC_APC_CLR_SHIFT)
+#define MC2EMC_APC_CLR_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_ROW                      0
+
+#define MC2EMC_APC_BANK_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_FIELD                   (_MK_MASK_CONST(0x3) << MC2EMC_APC_BANK_SHIFT)
+#define MC2EMC_APC_BANK_RANGE                   _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_ROW                     0
+
+
+// Packet EMC2MC
+#define EMC2MC_SIZE 138
+
+#define EMC2MC_RDI_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_SHIFT)
+#define EMC2MC_RDI_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_ROW                  0
+
+#define EMC2MC_RDI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_0_SHIFT)
+#define EMC2MC_RDI_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_ROW                        0
+
+#define EMC2MC_RDI_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_1_SHIFT)
+#define EMC2MC_RDI_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_ROW                        0
+
+#define EMC2MC_RDI_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_2_SHIFT)
+#define EMC2MC_RDI_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_ROW                        0
+
+#define EMC2MC_RDI_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_3_SHIFT)
+#define EMC2MC_RDI_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_ROW                        0
+
+#define EMC2MC_RDI_ID_SHIFT                     _MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_FIELD                     (_MK_MASK_CONST(0x3ff) << EMC2MC_RDI_ID_SHIFT)
+#define EMC2MC_RDI_ID_RANGE                     _MK_SHIFT_CONST(137):_MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_ROW                       0
+
+
+// Packet MC2EMC_LL
+#define MC2EMC_LL_SIZE 35
+
+#define MC2EMC_LL_DEV_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_DEV_FIELD                     (_MK_MASK_CONST(0x3) << MC2EMC_LL_DEV_SHIFT)
+#define MC2EMC_LL_DEV_RANGE                     _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_DEV_ROW                       0
+
+#define MC2EMC_LL_BANK_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC2EMC_LL_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_BANK_SHIFT)
+#define MC2EMC_LL_BANK_RANGE                    _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(2)
+#define MC2EMC_LL_BANK_ROW                      0
+
+#define MC2EMC_LL_ROW_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC2EMC_LL_ROW_FIELD                     (_MK_MASK_CONST(0x3fff) << MC2EMC_LL_ROW_SHIFT)
+#define MC2EMC_LL_ROW_RANGE                     _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(4)
+#define MC2EMC_LL_ROW_ROW                       0
+
+#define MC2EMC_LL_COL_SHIFT                     _MK_SHIFT_CONST(18)
+#define MC2EMC_LL_COL_FIELD                     (_MK_MASK_CONST(0x7ff) << MC2EMC_LL_COL_SHIFT)
+#define MC2EMC_LL_COL_RANGE                     _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(18)
+#define MC2EMC_LL_COL_ROW                       0
+
+#define MC2EMC_LL_TAG_SHIFT                     _MK_SHIFT_CONST(29)
+#define MC2EMC_LL_TAG_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_TAG_SHIFT)
+#define MC2EMC_LL_TAG_RANGE                     _MK_SHIFT_CONST(33):_MK_SHIFT_CONST(29)
+#define MC2EMC_LL_TAG_ROW                       0
+
+#define MC2EMC_LL_DOUBLEREQ_SHIFT                       _MK_SHIFT_CONST(34)
+#define MC2EMC_LL_DOUBLEREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC2EMC_LL_DOUBLEREQ_SHIFT)
+#define MC2EMC_LL_DOUBLEREQ_RANGE                       _MK_SHIFT_CONST(34):_MK_SHIFT_CONST(34)
+#define MC2EMC_LL_DOUBLEREQ_ROW                 0
+
+
+// Packet EMC2MC_LL
+#define EMC2MC_LL_SIZE 64
+
+#define EMC2MC_LL_RDI_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_FIELD                     (_MK_MASK_CONST(0xffffffff) << EMC2MC_LL_RDI_SHIFT)
+#define EMC2MC_LL_RDI_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_ROW                       0
+
+
+// Packet MC2EMC_LL_CRITINFO
+#define MC2EMC_LL_CRITINFO_SIZE 11
+
+#define MC2EMC_LL_CRITINFO_HP_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_CRITINFO_HP_SHIFT)
+#define MC2EMC_LL_CRITINFO_HP_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_ROW                       0
+
+#define MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_FIELD                        (_MK_MASK_CONST(0x3f) << MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_RANGE                        _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_ROW                  0
+
+
+// Packet MC2EMC_LL_ARBINFO
+#define MC2EMC_LL_ARBINFO_SIZE 2
+
+#define MC2EMC_LL_ARBINFO_BANK_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_ARBINFO_BANK_SHIFT)
+#define MC2EMC_LL_ARBINFO_BANK_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_ROW                      0
+
+
+// Packet CMC2MC_AXI_A
+#define CMC2MC_AXI_A_SIZE 58
+
+#define CMC2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_A_AADDR_SHIFT)
+#define CMC2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_ROW                  0
+
+#define CMC2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_A_AID_SHIFT)
+#define CMC2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_ROW                    0
+
+#define CMC2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define CMC2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ALEN_SHIFT)
+#define CMC2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define CMC2MC_AXI_A_ALEN_ROW                   0
+#define CMC2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define CMC2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define CMC2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define CMC2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define CMC2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define CMC2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_ASIZE_SHIFT)
+#define CMC2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define CMC2MC_AXI_A_ASIZE_ROW                  0
+#define CMC2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define CMC2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define CMC2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ABURST_SHIFT)
+#define CMC2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define CMC2MC_AXI_A_ABURST_ROW                 0
+#define CMC2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ALOCK_SHIFT)
+#define CMC2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ALOCK_ROW                  0
+#define CMC2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define CMC2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ACACHE_SHIFT)
+#define CMC2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define CMC2MC_AXI_A_ACACHE_ROW                 0
+#define CMC2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define CMC2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_APROT_SHIFT)
+#define CMC2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define CMC2MC_AXI_A_APROT_ROW                  0
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet CMC2MC_AXI_W
+#define CMC2MC_AXI_W_SIZE 81
+
+#define CMC2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_W_WDATA_SHIFT)
+#define CMC2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_ROW                  0
+
+#define CMC2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WID_SHIFT)
+#define CMC2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_ROW                    0
+
+#define CMC2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WSTRB_SHIFT)
+#define CMC2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_W_WSTRB_ROW                  0
+
+#define CMC2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(80)
+#define CMC2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_W_WLAST_SHIFT)
+#define CMC2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(80):_MK_SHIFT_CONST(80)
+#define CMC2MC_AXI_W_WLAST_ROW                  0
+#define CMC2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet CMC2MC_AXI_B
+#define CMC2MC_AXI_B_SIZE 10
+
+#define CMC2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_B_BID_SHIFT)
+#define CMC2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_ROW                    0
+
+#define CMC2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(8)
+#define CMC2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_B_BRESP_SHIFT)
+#define CMC2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define CMC2MC_AXI_B_BRESP_ROW                  0
+#define CMC2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet CMC2MC_AXI_R
+#define CMC2MC_AXI_R_SIZE 75
+
+#define CMC2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_R_RDATA_SHIFT)
+#define CMC2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_ROW                  0
+
+#define CMC2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_R_RID_SHIFT)
+#define CMC2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_ROW                    0
+
+#define CMC2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_R_RRESP_SHIFT)
+#define CMC2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(73):_MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_R_RRESP_ROW                  0
+#define CMC2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(74)
+#define CMC2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_R_RLAST_SHIFT)
+#define CMC2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(74):_MK_SHIFT_CONST(74)
+#define CMC2MC_AXI_R_RLAST_ROW                  0
+#define CMC2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_A
+#define MSELECT2MC_AXI_A_SIZE 58
+
+#define MSELECT2MC_AXI_A_AADDR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_A_AADDR_SHIFT)
+#define MSELECT2MC_AXI_A_AADDR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_ROW                      0
+
+#define MSELECT2MC_AXI_A_AID_SHIFT                      _MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_A_AID_SHIFT)
+#define MSELECT2MC_AXI_A_AID_RANGE                      _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_ROW                        0
+
+#define MSELECT2MC_AXI_A_ALEN_SHIFT                     _MK_SHIFT_CONST(40)
+#define MSELECT2MC_AXI_A_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ALEN_SHIFT)
+#define MSELECT2MC_AXI_A_ALEN_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define MSELECT2MC_AXI_A_ALEN_ROW                       0
+#define MSELECT2MC_AXI_A_ALEN_ONEDATA                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALEN_TWODATA                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALEN_THREEDATA                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALEN_FOURDATA                  _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ALEN_FIVEDATA                  _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ALEN_SIXDATA                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ALEN_SEVENDATA                 _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ALEN_EIGHTDATA                 _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ALEN_NINEDATA                  _MK_ENUM_CONST(8)
+#define MSELECT2MC_AXI_A_ALEN_TENDATA                   _MK_ENUM_CONST(9)
+#define MSELECT2MC_AXI_A_ALEN_ELEVENDATA                        _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ALEN_TWELVEDATA                        _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ALEN_THIRTEENDATA                      _MK_ENUM_CONST(12)
+#define MSELECT2MC_AXI_A_ALEN_FOURTEENDATA                      _MK_ENUM_CONST(13)
+#define MSELECT2MC_AXI_A_ALEN_FIFTHTEENDATA                     _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ALEN_SIXTEENDATA                       _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_ASIZE_SHIFT                    _MK_SHIFT_CONST(44)
+#define MSELECT2MC_AXI_A_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_ASIZE_SHIFT)
+#define MSELECT2MC_AXI_A_ASIZE_RANGE                    _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define MSELECT2MC_AXI_A_ASIZE_ROW                      0
+#define MSELECT2MC_AXI_A_ASIZE_ONEBYTE                  _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ASIZE_TWOBYTES                 _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ASIZE_FOURBYTES                        _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ASIZE_EIGHTBYTES                       _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTEENBYTES                     _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ASIZE_THIRTYTWOBYTES                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTYFOURBYTES                   _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                       _MK_ENUM_CONST(7)
+
+#define MSELECT2MC_AXI_A_ABURST_SHIFT                   _MK_SHIFT_CONST(47)
+#define MSELECT2MC_AXI_A_ABURST_FIELD                   (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ABURST_SHIFT)
+#define MSELECT2MC_AXI_A_ABURST_RANGE                   _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define MSELECT2MC_AXI_A_ABURST_ROW                     0
+#define MSELECT2MC_AXI_A_ABURST_FIXED                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ABURST_INCR                    _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ABURST_WRAP                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ABURST_RSVD                    _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ALOCK_SHIFT                    _MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ALOCK_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ALOCK_SHIFT)
+#define MSELECT2MC_AXI_A_ALOCK_RANGE                    _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ALOCK_ROW                      0
+#define MSELECT2MC_AXI_A_ALOCK_NORMAL                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALOCK_EXCLUSIVE                        _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALOCK_LOCKED                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALOCK_RSVD                     _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ACACHE_SHIFT                   _MK_SHIFT_CONST(51)
+#define MSELECT2MC_AXI_A_ACACHE_FIELD                   (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ACACHE_SHIFT)
+#define MSELECT2MC_AXI_A_ACACHE_RANGE                   _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define MSELECT2MC_AXI_A_ACACHE_ROW                     0
+#define MSELECT2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                      _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ACACHE_BUFFERABLE                      _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                      _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                       _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                   _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                      _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                       _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                  _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_APROT_SHIFT                    _MK_SHIFT_CONST(55)
+#define MSELECT2MC_AXI_A_APROT_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_APROT_SHIFT)
+#define MSELECT2MC_AXI_A_APROT_RANGE                    _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define MSELECT2MC_AXI_A_APROT_ROW                      0
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_NORMAL                       _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_NORMAL                       _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(7)
+
+
+// Packet MSELECT2MC_AXI_W
+#define MSELECT2MC_AXI_W_SIZE 81
+
+#define MSELECT2MC_AXI_W_WDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_W_WDATA_SHIFT)
+#define MSELECT2MC_AXI_W_WDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_ROW                      0
+
+#define MSELECT2MC_AXI_W_WID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WID_SHIFT)
+#define MSELECT2MC_AXI_W_WID_RANGE                      _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_ROW                        0
+
+#define MSELECT2MC_AXI_W_WSTRB_SHIFT                    _MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_W_WSTRB_FIELD                    (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WSTRB_SHIFT)
+#define MSELECT2MC_AXI_W_WSTRB_RANGE                    _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_W_WSTRB_ROW                      0
+
+#define MSELECT2MC_AXI_W_WLAST_SHIFT                    _MK_SHIFT_CONST(80)
+#define MSELECT2MC_AXI_W_WLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_W_WLAST_SHIFT)
+#define MSELECT2MC_AXI_W_WLAST_RANGE                    _MK_SHIFT_CONST(80):_MK_SHIFT_CONST(80)
+#define MSELECT2MC_AXI_W_WLAST_ROW                      0
+#define MSELECT2MC_AXI_W_WLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_W_WLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_B
+#define MSELECT2MC_AXI_B_SIZE 10
+
+#define MSELECT2MC_AXI_B_BID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_B_BID_SHIFT)
+#define MSELECT2MC_AXI_B_BID_RANGE                      _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_ROW                        0
+
+#define MSELECT2MC_AXI_B_BRESP_SHIFT                    _MK_SHIFT_CONST(8)
+#define MSELECT2MC_AXI_B_BRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_B_BRESP_SHIFT)
+#define MSELECT2MC_AXI_B_BRESP_RANGE                    _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define MSELECT2MC_AXI_B_BRESP_ROW                      0
+#define MSELECT2MC_AXI_B_BRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_B_BRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_B_BRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_B_BRESP_DECERR                   _MK_ENUM_CONST(3)
+
+
+// Packet MSELECT2MC_AXI_R
+#define MSELECT2MC_AXI_R_SIZE 75
+
+#define MSELECT2MC_AXI_R_RDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_R_RDATA_SHIFT)
+#define MSELECT2MC_AXI_R_RDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_ROW                      0
+
+#define MSELECT2MC_AXI_R_RID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_R_RID_SHIFT)
+#define MSELECT2MC_AXI_R_RID_RANGE                      _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_ROW                        0
+
+#define MSELECT2MC_AXI_R_RRESP_SHIFT                    _MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_R_RRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_R_RRESP_SHIFT)
+#define MSELECT2MC_AXI_R_RRESP_RANGE                    _MK_SHIFT_CONST(73):_MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_R_RRESP_ROW                      0
+#define MSELECT2MC_AXI_R_RRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_R_RRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_R_RRESP_DECERR                   _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_R_RLAST_SHIFT                    _MK_SHIFT_CONST(74)
+#define MSELECT2MC_AXI_R_RLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_R_RLAST_SHIFT)
+#define MSELECT2MC_AXI_R_RLAST_RANGE                    _MK_SHIFT_CONST(74):_MK_SHIFT_CONST(74)
+#define MSELECT2MC_AXI_R_RLAST_ROW                      0
+#define MSELECT2MC_AXI_R_RLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_A
+#define AXI2MC_AXI_A_SIZE 58
+
+#define AXI2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_A_AADDR_SHIFT)
+#define AXI2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_ROW                  0
+
+#define AXI2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_A_AID_SHIFT)
+#define AXI2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_ROW                    0
+
+#define AXI2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define AXI2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ALEN_SHIFT)
+#define AXI2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define AXI2MC_AXI_A_ALEN_ROW                   0
+#define AXI2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define AXI2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define AXI2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define AXI2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define AXI2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define AXI2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_ASIZE_SHIFT)
+#define AXI2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define AXI2MC_AXI_A_ASIZE_ROW                  0
+#define AXI2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define AXI2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define AXI2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ABURST_SHIFT)
+#define AXI2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define AXI2MC_AXI_A_ABURST_ROW                 0
+#define AXI2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ALOCK_SHIFT)
+#define AXI2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ALOCK_ROW                  0
+#define AXI2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define AXI2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ACACHE_SHIFT)
+#define AXI2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define AXI2MC_AXI_A_ACACHE_ROW                 0
+#define AXI2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define AXI2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_APROT_SHIFT)
+#define AXI2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define AXI2MC_AXI_A_APROT_ROW                  0
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet AXI2MC_AXI_W
+#define AXI2MC_AXI_W_SIZE 297
+
+#define AXI2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WDATA_SHIFT)
+#define AXI2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_ROW                  0
+
+#define AXI2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_W_WID_SHIFT)
+#define AXI2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(263):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_ROW                    0
+
+#define AXI2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WSTRB_SHIFT)
+#define AXI2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(295):_MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_W_WSTRB_ROW                  0
+
+#define AXI2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(296)
+#define AXI2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_W_WLAST_SHIFT)
+#define AXI2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(296):_MK_SHIFT_CONST(296)
+#define AXI2MC_AXI_W_WLAST_ROW                  0
+#define AXI2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_B
+#define AXI2MC_AXI_B_SIZE 10
+
+#define AXI2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_B_BID_SHIFT)
+#define AXI2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_ROW                    0
+
+#define AXI2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(8)
+#define AXI2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_B_BRESP_SHIFT)
+#define AXI2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define AXI2MC_AXI_B_BRESP_ROW                  0
+#define AXI2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet AXI2MC_AXI_R
+#define AXI2MC_AXI_R_SIZE 267
+
+#define AXI2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_R_RDATA_SHIFT)
+#define AXI2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_ROW                  0
+
+#define AXI2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_R_RID_SHIFT)
+#define AXI2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(263):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_ROW                    0
+
+#define AXI2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_R_RRESP_SHIFT)
+#define AXI2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(265):_MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_R_RRESP_ROW                  0
+#define AXI2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(266)
+#define AXI2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_R_RLAST_SHIFT)
+#define AXI2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(266):_MK_SHIFT_CONST(266)
+#define AXI2MC_AXI_R_RLAST_ROW                  0
+#define AXI2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MC_AXI_RWREQ
+#define MC_AXI_RWREQ_SIZE 107
+
+#define MC_AXI_RWREQ_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_AADDR_SHIFT)
+#define MC_AXI_RWREQ_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_ROW                  0
+
+#define MC_AXI_RWREQ_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_FIELD                  (_MK_MASK_CONST(0xff) << MC_AXI_RWREQ_AID_SHIFT)
+#define MC_AXI_RWREQ_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_ROW                    0
+
+#define MC_AXI_RWREQ_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define MC_AXI_RWREQ_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define MC_AXI_RWREQ_ALEN_ROW                   0
+
+#define MC_AXI_RWREQ_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define MC_AXI_RWREQ_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define MC_AXI_RWREQ_ASIZE_ROW                  2
+
+#define MC_AXI_RWREQ_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define MC_AXI_RWREQ_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ABURST_SHIFT)
+#define MC_AXI_RWREQ_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define MC_AXI_RWREQ_ABURST_ROW                 0
+#define MC_AXI_RWREQ_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define MC_AXI_RWREQ_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define MC_AXI_RWREQ_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define MC_AXI_RWREQ_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define MC_AXI_RWREQ_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ALOCK_SHIFT)
+#define MC_AXI_RWREQ_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ALOCK_ROW                  0
+
+#define MC_AXI_RWREQ_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define MC_AXI_RWREQ_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACACHE_SHIFT)
+#define MC_AXI_RWREQ_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define MC_AXI_RWREQ_ACACHE_ROW                 0
+
+#define MC_AXI_RWREQ_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define MC_AXI_RWREQ_APROT_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_APROT_SHIFT)
+#define MC_AXI_RWREQ_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define MC_AXI_RWREQ_APROT_ROW                  0
+
+#define MC_AXI_RWREQ_ASB_SHIFT                  _MK_SHIFT_CONST(58)
+#define MC_AXI_RWREQ_ASB_FIELD                  (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ASB_SHIFT)
+#define MC_AXI_RWREQ_ASB_RANGE                  _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(58)
+#define MC_AXI_RWREQ_ASB_ROW                    0
+
+#define MC_AXI_RWREQ_ARW_SHIFT                  _MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_ARW_FIELD                  (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ARW_SHIFT)
+#define MC_AXI_RWREQ_ARW_RANGE                  _MK_SHIFT_CONST(60):_MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_ARW_ROW                    0
+
+#define MC_AXI_RWREQ_ACT_AADDR_SHIFT                    _MK_SHIFT_CONST(61)
+#define MC_AXI_RWREQ_ACT_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_ACT_AADDR_SHIFT)
+#define MC_AXI_RWREQ_ACT_AADDR_RANGE                    _MK_SHIFT_CONST(92):_MK_SHIFT_CONST(61)
+#define MC_AXI_RWREQ_ACT_AADDR_ROW                      0
+
+#define MC_AXI_RWREQ_ACT_ALEN_SHIFT                     _MK_SHIFT_CONST(93)
+#define MC_AXI_RWREQ_ACT_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACT_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ACT_ALEN_RANGE                     _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(93)
+#define MC_AXI_RWREQ_ACT_ALEN_ROW                       0
+
+#define MC_AXI_RWREQ_ACT_ASIZE_SHIFT                    _MK_SHIFT_CONST(97)
+#define MC_AXI_RWREQ_ACT_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ACT_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ACT_ASIZE_RANGE                    _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(97)
+#define MC_AXI_RWREQ_ACT_ASIZE_ROW                      0
+
+#define MC_AXI_RWREQ_DOUBLEREQ_SHIFT                    _MK_SHIFT_CONST(100)
+#define MC_AXI_RWREQ_DOUBLEREQ_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_DOUBLEREQ_SHIFT)
+#define MC_AXI_RWREQ_DOUBLEREQ_RANGE                    _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define MC_AXI_RWREQ_DOUBLEREQ_ROW                      0
+
+#define MC_AXI_RWREQ_ILLEGALACC_SHIFT                   _MK_SHIFT_CONST(101)
+#define MC_AXI_RWREQ_ILLEGALACC_FIELD                   (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ILLEGALACC_SHIFT)
+#define MC_AXI_RWREQ_ILLEGALACC_RANGE                   _MK_SHIFT_CONST(101):_MK_SHIFT_CONST(101)
+#define MC_AXI_RWREQ_ILLEGALACC_ROW                     0
+
+#define MC_AXI_RWREQ_TAG_SHIFT                  _MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << MC_AXI_RWREQ_TAG_SHIFT)
+#define MC_AXI_RWREQ_TAG_RANGE                  _MK_SHIFT_CONST(106):_MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_RESET
+#define CSR_C2MC_RESET_SIZE 1
+
+#define CSR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_RESET_RSTN_SHIFT)
+#define CSR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSR_C2MC_REQ
+#define CSR_C2MC_REQ_SIZE 32
+
+#define CSR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_REQ_ADR_SHIFT)
+#define CSR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_ROW                    0
+
+
+// Packet CSR_C2MC_BP_REQ
+#define CSR_C2MC_BP_REQ_SIZE 48
+
+#define CSR_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSR_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSR_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSR_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSR_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_ROW                       0
+
+
+// Packet CSR_C2MC_ADRXY
+#define CSR_C2MC_ADRXY_SIZE 30
+
+#define CSR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSR_C2MC_ADRXY_OFFX_SHIFT)
+#define CSR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSR_C2MC_ADRXY_OFFY_SHIFT)
+#define CSR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSR_C2MC_TILE
+#define CSR_C2MC_TILE_SIZE 33
+
+#define CSR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_TILE_LINADR_SHIFT)
+#define CSR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_ROW                        0
+
+#define CSR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_TILE_TMODE_SHIFT)
+#define CSR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_ROW                 0
+#define CSR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSR_C2MC_RDI
+#define CSR_C2MC_RDI_SIZE 256
+
+#define CSR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_RDI_RDI_SHIFT)
+#define CSR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CSR_C2MC_HP
+#define CSR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CSR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_HP_HPTH_SHIFT)
+#define CSR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CSR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CSR_C2MC_HP_HPTM_SHIFT)
+#define CSR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CSW_C2MC_RESET
+#define CSW_C2MC_RESET_SIZE 1
+
+#define CSW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_RESET_RSTN_SHIFT)
+#define CSW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSW_C2MC_REQ
+#define CSW_C2MC_REQ_SIZE 321
+
+#define CSW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_ADR_SHIFT)
+#define CSW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_ROW                    0
+
+#define CSW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_BE_SHIFT)
+#define CSW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_ROW                     0
+
+#define CSW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_WDO_SHIFT)
+#define CSW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_ROW                    0
+
+#define CSW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_REQ_TAG_SHIFT)
+#define CSW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CSW_C2MC_BP_REQ
+#define CSW_C2MC_BP_REQ_SIZE 337
+
+#define CSW_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSW_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSW_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSW_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSW_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_ROW                       0
+
+#define CSW_C2MC_BP_REQ_BE_SHIFT                        _MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BE_SHIFT)
+#define CSW_C2MC_BP_REQ_BE_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_ROW                  0
+
+#define CSW_C2MC_BP_REQ_WDO_SHIFT                       _MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_FIELD                       (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_WDO_SHIFT)
+#define CSW_C2MC_BP_REQ_WDO_RANGE                       _MK_SHIFT_CONST(335):_MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_ROW                 0
+
+#define CSW_C2MC_BP_REQ_TAG_SHIFT                       _MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_BP_REQ_TAG_SHIFT)
+#define CSW_C2MC_BP_REQ_TAG_RANGE                       _MK_SHIFT_CONST(336):_MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_ROW                 0
+
+
+// Packet CSW_C2MC_ADRXY
+#define CSW_C2MC_ADRXY_SIZE 30
+
+#define CSW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSW_C2MC_ADRXY_OFFX_SHIFT)
+#define CSW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSW_C2MC_ADRXY_OFFY_SHIFT)
+#define CSW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSW_C2MC_TILE
+#define CSW_C2MC_TILE_SIZE 33
+
+#define CSW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_TILE_LINADR_SHIFT)
+#define CSW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_ROW                        0
+
+#define CSW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_TILE_TMODE_SHIFT)
+#define CSW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_ROW                 0
+#define CSW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSW_C2MC_XDI
+#define CSW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CSW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_XDI_XDI_SHIFT)
+#define CSW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CSW_C2MC_HP
+#define CSW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CSW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HP_HPTH_SHIFT)
+#define CSW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CSW_C2MC_WCOAL
+#define CSW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CSW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CSW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CBR_C2MC_RESET
+#define CBR_C2MC_RESET_SIZE 1
+
+#define CBR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RESET_RSTN_SHIFT)
+#define CBR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBR_C2MC_REQP
+#define CBR_C2MC_REQP_SIZE 263
+
+#define CBR_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADR_SHIFT)
+#define CBR_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_ROW                   0
+
+#define CBR_C2MC_REQP_ADRU_SHIFT                        _MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRU_SHIFT)
+#define CBR_C2MC_REQP_ADRU_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_ROW                  0
+
+#define CBR_C2MC_REQP_ADRV_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRV_SHIFT)
+#define CBR_C2MC_REQP_ADRV_RANGE                        _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_ROW                  0
+
+#define CBR_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LS_SHIFT)
+#define CBR_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_ROW                    0
+
+#define CBR_C2MC_REQP_LSUV_SHIFT                        _MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LSUV_SHIFT)
+#define CBR_C2MC_REQP_LSUV_RANGE                        _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_ROW                  0
+
+#define CBR_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_HS_SHIFT)
+#define CBR_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(191):_MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_ROW                    0
+
+#define CBR_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_VS_SHIFT)
+#define CBR_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(223):_MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_ROW                    0
+
+#define CBR_C2MC_REQP_DL_SHIFT                  _MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_DL_SHIFT)
+#define CBR_C2MC_REQP_DL_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_ROW                    0
+
+#define CBR_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_HD_SHIFT)
+#define CBR_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_ROW                    0
+
+#define CBR_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VD_SHIFT)
+#define CBR_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(257):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_ROW                    0
+
+#define CBR_C2MC_REQP_VX2_SHIFT                 _MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VX2_SHIFT)
+#define CBR_C2MC_REQP_VX2_RANGE                 _MK_SHIFT_CONST(258):_MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_ROW                   0
+
+#define CBR_C2MC_REQP_LP_SHIFT                  _MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_LP_SHIFT)
+#define CBR_C2MC_REQP_LP_RANGE                  _MK_SHIFT_CONST(259):_MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_ROW                    0
+
+#define CBR_C2MC_REQP_YUV_SHIFT                 _MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_REQP_YUV_SHIFT)
+#define CBR_C2MC_REQP_YUV_RANGE                 _MK_SHIFT_CONST(262):_MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_ROW                   0
+
+
+// Packet CBR_C2MC_ADRXY
+#define CBR_C2MC_ADRXY_SIZE 44
+
+#define CBR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_ADRXY_OFFX_SHIFT)
+#define CBR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFY_SHIFT)
+#define CBR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFYUV_SHIFT                     _MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_FIELD                     (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFYUV_SHIFT)
+#define CBR_C2MC_ADRXY_OFFYUV_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_ROW                       0
+
+
+// Packet CBR_C2MC_TILE
+#define CBR_C2MC_TILE_SIZE 98
+
+#define CBR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADR_SHIFT)
+#define CBR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_ROW                        0
+
+#define CBR_C2MC_TILE_LINADRU_SHIFT                     _MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRU_SHIFT)
+#define CBR_C2MC_TILE_LINADRU_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_ROW                       0
+
+#define CBR_C2MC_TILE_LINADRV_SHIFT                     _MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRV_SHIFT)
+#define CBR_C2MC_TILE_LINADRV_RANGE                     _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_ROW                       0
+
+#define CBR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODE_SHIFT)
+#define CBR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_ROW                 0
+#define CBR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+#define CBR_C2MC_TILE_TMODEUV_SHIFT                     _MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODEUV_SHIFT)
+#define CBR_C2MC_TILE_TMODEUV_RANGE                     _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_ROW                       0
+#define CBR_C2MC_TILE_TMODEUV_LINEAR                    _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODEUV_TILED                     _MK_ENUM_CONST(1)
+
+
+// Packet CBR_C2MC_RDYP
+#define CBR_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBR_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_RDYP_RDYP_SHIFT)
+#define CBR_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBR_C2MC_OUTSTD
+#define CBR_C2MC_OUTSTD_SIZE 1
+
+#define CBR_C2MC_OUTSTD_OUTSTD_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_OUTSTD_OUTSTD_SHIFT)
+#define CBR_C2MC_OUTSTD_OUTSTD_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_ROW                      0
+
+
+// Packet CBR_C2MC_STOP
+#define CBR_C2MC_STOP_SIZE 1
+
+#define CBR_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_STOP_STOP_SHIFT)
+#define CBR_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBR_C2MC_RDI
+#define CBR_C2MC_RDI_SIZE 262
+
+#define CBR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_RDI_RDI_SHIFT)
+#define CBR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_ROW                    0
+
+#define CBR_C2MC_RDI_RDILST_SHIFT                       _MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RDI_RDILST_SHIFT)
+#define CBR_C2MC_RDI_RDILST_RANGE                       _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_ROW                 0
+
+#define CBR_C2MC_RDI_RDINB_SHIFT                        _MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_FIELD                        (_MK_MASK_CONST(0x1f) << CBR_C2MC_RDI_RDINB_SHIFT)
+#define CBR_C2MC_RDI_RDINB_RANGE                        _MK_SHIFT_CONST(261):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_ROW                  0
+
+
+// Packet CBR_C2MC_DOREQ
+#define CBR_C2MC_DOREQ_SIZE 64
+
+#define CBR_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_ADR_SHIFT)
+#define CBR_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBR_C2MC_DOREQ_LS_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_LS_SHIFT)
+#define CBR_C2MC_DOREQ_LS_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_ROW                   0
+
+
+// Packet CBR_C2MC_HP
+#define CBR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CBR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_HP_HPTH_SHIFT)
+#define CBR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CBR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CBR_C2MC_HP_HPTM_SHIFT)
+#define CBR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CBW_C2MC_RESET
+#define CBW_C2MC_RESET_SIZE 1
+
+#define CBW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_RESET_RSTN_SHIFT)
+#define CBW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBW_C2MC_REQP
+#define CBW_C2MC_REQP_SIZE 134
+
+#define CBW_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_ADR_SHIFT)
+#define CBW_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_ROW                   0
+
+#define CBW_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_LS_SHIFT)
+#define CBW_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_ROW                    0
+
+#define CBW_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_HS_SHIFT)
+#define CBW_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_ROW                    0
+
+#define CBW_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_VS_SHIFT)
+#define CBW_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_ROW                    0
+
+#define CBW_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_HD_SHIFT)
+#define CBW_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(128):_MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_ROW                    0
+
+#define CBW_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_VD_SHIFT)
+#define CBW_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(129):_MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_ROW                    0
+
+#define CBW_C2MC_REQP_BPP_SHIFT                 _MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_FIELD                 (_MK_MASK_CONST(0x3) << CBW_C2MC_REQP_BPP_SHIFT)
+#define CBW_C2MC_REQP_BPP_RANGE                 _MK_SHIFT_CONST(131):_MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_ROW                   0
+
+#define CBW_C2MC_REQP_XY_SHIFT                  _MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_XY_SHIFT)
+#define CBW_C2MC_REQP_XY_RANGE                  _MK_SHIFT_CONST(132):_MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_ROW                    0
+
+#define CBW_C2MC_REQP_PK_SHIFT                  _MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_PK_SHIFT)
+#define CBW_C2MC_REQP_PK_RANGE                  _MK_SHIFT_CONST(133):_MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_ROW                    0
+
+
+// Packet CBW_C2MC_ADRXY
+#define CBW_C2MC_ADRXY_SIZE 30
+
+#define CBW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBW_C2MC_ADRXY_OFFX_SHIFT)
+#define CBW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBW_C2MC_ADRXY_OFFY_SHIFT)
+#define CBW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CBW_C2MC_TILE
+#define CBW_C2MC_TILE_SIZE 33
+
+#define CBW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_TILE_LINADR_SHIFT)
+#define CBW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_ROW                        0
+
+#define CBW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_TILE_TMODE_SHIFT)
+#define CBW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_ROW                 0
+#define CBW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CBW_C2MC_RDYP
+#define CBW_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBW_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_RDYP_RDYP_SHIFT)
+#define CBW_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBW_C2MC_STOP
+#define CBW_C2MC_STOP_SIZE 1
+
+#define CBW_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_STOP_STOP_SHIFT)
+#define CBW_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBW_C2MC_XDI
+#define CBW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CBW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_XDI_XDI_SHIFT)
+#define CBW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CBW_C2MC_DOREQ
+#define CBW_C2MC_DOREQ_SIZE 321
+
+#define CBW_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_ADR_SHIFT)
+#define CBW_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBW_C2MC_DOREQ_BE_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_BE_SHIFT)
+#define CBW_C2MC_DOREQ_BE_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_ROW                   0
+
+#define CBW_C2MC_DOREQ_WDO_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_WDO_SHIFT)
+#define CBW_C2MC_DOREQ_WDO_RANGE                        _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_ROW                  0
+
+#define CBW_C2MC_DOREQ_TAG_SHIFT                        _MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_DOREQ_TAG_SHIFT)
+#define CBW_C2MC_DOREQ_TAG_RANGE                        _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_ROW                  0
+
+
+// Packet CBW_C2MC_HP
+#define CBW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CBW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_HP_HPTH_SHIFT)
+#define CBW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CBW_C2MC_WCOAL
+#define CBW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CBW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CBW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CCR_C2MC_RESET
+#define CCR_C2MC_RESET_SIZE 1
+
+#define CCR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCR_C2MC_RESET_RSTN_SHIFT)
+#define CCR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCR_C2MC_REQ
+#define CCR_C2MC_REQ_SIZE 101
+
+#define CCR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_ADR_SHIFT)
+#define CCR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_ROW                    0
+
+#define CCR_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_LS_SHIFT)
+#define CCR_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCR_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_HINC_SHIFT)
+#define CCR_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_ROW                   0
+
+#define CCR_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCR_C2MC_REQ_ACMD_SHIFT)
+#define CCR_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_ROW                   0
+
+#define CCR_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_LN_SHIFT)
+#define CCR_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_ROW                     0
+
+#define CCR_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_HD_SHIFT)
+#define CCR_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_ROW                     0
+
+#define CCR_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_VD_SHIFT)
+#define CCR_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_ROW                     0
+
+
+// Packet CCR_C2MC_RDI
+#define CCR_C2MC_RDI_SIZE 256
+
+#define CCR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_RDI_RDI_SHIFT)
+#define CCR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CCR_C2MC_HP
+#define CCR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CCR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HP_HPTH_SHIFT)
+#define CCR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CCR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CCR_C2MC_HP_HPTM_SHIFT)
+#define CCR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CCW_C2MC_RESET
+#define CCW_C2MC_RESET_SIZE 1
+
+#define CCW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_RESET_RSTN_SHIFT)
+#define CCW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCW_C2MC_REQ
+#define CCW_C2MC_REQ_SIZE 417
+
+#define CCW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_ADR_SHIFT)
+#define CCW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_ROW                    0
+
+#define CCW_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_LS_SHIFT)
+#define CCW_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCW_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_HINC_SHIFT)
+#define CCW_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_ROW                   0
+
+#define CCW_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_ACMD_SHIFT)
+#define CCW_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_ROW                   0
+
+#define CCW_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_LN_SHIFT)
+#define CCW_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_ROW                     0
+
+#define CCW_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_HD_SHIFT)
+#define CCW_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_ROW                     0
+
+#define CCW_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_VD_SHIFT)
+#define CCW_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_ROW                     0
+
+#define CCW_C2MC_REQ_BPP_SHIFT                  _MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_FIELD                  (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_BPP_SHIFT)
+#define CCW_C2MC_REQ_BPP_RANGE                  _MK_SHIFT_CONST(102):_MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_ROW                    0
+
+#define CCW_C2MC_REQ_XY_SHIFT                   _MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_XY_SHIFT)
+#define CCW_C2MC_REQ_XY_RANGE                   _MK_SHIFT_CONST(103):_MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_ROW                     0
+
+#define CCW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_BE_SHIFT)
+#define CCW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_ROW                     0
+
+#define CCW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_WDO_SHIFT)
+#define CCW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(415):_MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_ROW                    0
+
+#define CCW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_TAG_SHIFT)
+#define CCW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(416):_MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CCW_C2MC_ADRXY
+#define CCW_C2MC_ADRXY_SIZE 30
+
+#define CCW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CCW_C2MC_ADRXY_OFFX_SHIFT)
+#define CCW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CCW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CCW_C2MC_ADRXY_OFFY_SHIFT)
+#define CCW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CCW_C2MC_TILE
+#define CCW_C2MC_TILE_SIZE 33
+
+#define CCW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_TILE_LINADR_SHIFT)
+#define CCW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_ROW                        0
+
+#define CCW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_TILE_TMODE_SHIFT)
+#define CCW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_ROW                 0
+#define CCW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CCW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CCW_C2MC_XDI
+#define CCW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CCW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_XDI_XDI_SHIFT)
+#define CCW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CCW_C2MC_HP
+#define CCW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CCW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_HP_HPTH_SHIFT)
+#define CCW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CCW_C2MC_WCOAL
+#define CCW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CCW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CCW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet SC_MCCIF_ASYNC
+#define SC_MCCIF_ASYNC_SIZE 4
+
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT                        _MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT                        _MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_RANGE                        _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT                        _MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT                        _MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_ROW                  0
+
+
+// Register EMC_LL_ARB_CONFIG_0  // LOW-LATENCY arbiter configuration
+#define EMC_LL_ARB_CONFIG_0                     _MK_ADDR_CONST(0xa4)
+#define EMC_LL_ARB_CONFIG_0_WORD_COUNT                  0x1
+#define EMC_LL_ARB_CONFIG_0_RESET_VAL                   _MK_MASK_CONST(0x2003)
+#define EMC_LL_ARB_CONFIG_0_RESET_MASK                  _MK_MASK_CONST(0x8000f10f)
+#define EMC_LL_ARB_CONFIG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_READ_MASK                   _MK_MASK_CONST(0x8000f10f)
+#define EMC_LL_ARB_CONFIG_0_WRITE_MASK                  _MK_MASK_CONST(0x8000f10f)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_FIELD                   (_MK_MASK_CONST(0xf) << EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_RANGE                   3:0
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_WOFFSET                 0x0
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_DEFAULT                 _MK_MASK_CONST(0x3)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_FIELD                     (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_RANGE                     8:8
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_WOFFSET                   0x0
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_INIT_ENUM                 DISABLED
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SHIFT                  _MK_SHIFT_CONST(12)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_FIELD                  (_MK_MASK_CONST(0xf) << EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_RANGE                  15:12
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_WOFFSET                        0x0
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_DEFAULT                        _MK_MASK_CONST(0x2)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_SHIFT                      _MK_SHIFT_CONST(31)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_RANGE                      31:31
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_WOFFSET                    0x0
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_INIT_ENUM                  DISABLED
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_LL_ARB_CONFIG_0_LL_RETRSV_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_T_MIN_CRITICAL_HP_0  
+#define EMC_T_MIN_CRITICAL_HP_0                 _MK_ADDR_CONST(0xa8)
+#define EMC_T_MIN_CRITICAL_HP_0_WORD_COUNT                      0x1
+#define EMC_T_MIN_CRITICAL_HP_0_RESET_VAL                       _MK_MASK_CONST(0xa080600)
+#define EMC_T_MIN_CRITICAL_HP_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_RANGE                   7:0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_RANGE                   15:8
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_DEFAULT                 _MK_MASK_CONST(0x6)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_RANGE                   23:16
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_DEFAULT                 _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_RANGE                   31:24
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_DEFAULT                 _MK_MASK_CONST(0xa)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MIN_CRITICAL_TIMEOUT_0  
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0                    _MK_ADDR_CONST(0xac)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_WORD_COUNT                         0x1
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_RESET_VAL                  _MK_MASK_CONST(0xa080600)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_RANGE                 7:0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_RANGE                 15:8
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_DEFAULT                       _MK_MASK_CONST(0x6)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_RANGE                 23:16
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_DEFAULT                       _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_RANGE                 31:24
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_DEFAULT                       _MK_MASK_CONST(0xa)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MIN_LOAD_0  
+#define EMC_T_MIN_LOAD_0                        _MK_ADDR_CONST(0xb0)
+#define EMC_T_MIN_LOAD_0_WORD_COUNT                     0x1
+#define EMC_T_MIN_LOAD_0_RESET_VAL                      _MK_MASK_CONST(0x8040200)
+#define EMC_T_MIN_LOAD_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_RANGE                     7:0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_RANGE                     15:8
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_DEFAULT                   _MK_MASK_CONST(0x2)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_RANGE                     23:16
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_DEFAULT                   _MK_MASK_CONST(0x4)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_RANGE                     31:24
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_CRITICAL_HP_0  
+#define EMC_T_MAX_CRITICAL_HP_0                 _MK_ADDR_CONST(0xb4)
+#define EMC_T_MAX_CRITICAL_HP_0_WORD_COUNT                      0x1
+#define EMC_T_MAX_CRITICAL_HP_0_RESET_VAL                       _MK_MASK_CONST(0xb0a0901)
+#define EMC_T_MAX_CRITICAL_HP_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_RANGE                   7:0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_DEFAULT                 _MK_MASK_CONST(0x1)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_RANGE                   15:8
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_DEFAULT                 _MK_MASK_CONST(0x9)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_RANGE                   23:16
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_DEFAULT                 _MK_MASK_CONST(0xa)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_RANGE                   31:24
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_DEFAULT                 _MK_MASK_CONST(0xb)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_CRITICAL_TIMEOUT_0  
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0                    _MK_ADDR_CONST(0xb8)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_WORD_COUNT                         0x1
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_RESET_VAL                  _MK_MASK_CONST(0xb0a0901)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_RANGE                 7:0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_DEFAULT                       _MK_MASK_CONST(0x1)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_RANGE                 15:8
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_DEFAULT                       _MK_MASK_CONST(0x9)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_RANGE                 23:16
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_DEFAULT                       _MK_MASK_CONST(0xa)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_RANGE                 31:24
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_DEFAULT                       _MK_MASK_CONST(0xb)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_LOAD_0  
+#define EMC_T_MAX_LOAD_0                        _MK_ADDR_CONST(0xbc)
+#define EMC_T_MAX_LOAD_0_WORD_COUNT                     0x1
+#define EMC_T_MAX_LOAD_0_RESET_VAL                      _MK_MASK_CONST(0xf080402)
+#define EMC_T_MAX_LOAD_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_RANGE                     7:0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_DEFAULT                   _MK_MASK_CONST(0x2)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_RANGE                     15:8
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_DEFAULT                   _MK_MASK_CONST(0x4)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_RANGE                     23:16
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_RANGE                     31:24
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_CONTROL_0  
+#define EMC_STAT_CONTROL_0                      _MK_ADDR_CONST(0xc0)
+#define EMC_STAT_CONTROL_0_WORD_COUNT                   0x1
+#define EMC_STAT_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x307)
+#define EMC_STAT_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x307)
+#define EMC_STAT_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x307)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_FIELD                    (_MK_MASK_CONST(0x7) << EMC_STAT_CONTROL_0_LLMC_GATHER_SHIFT)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_RANGE                    2:0
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_WOFFSET                  0x0
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_INIT_ENUM                        RST
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_RST                      _MK_ENUM_CONST(0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_CLEAR                    _MK_ENUM_CONST(1)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DISABLE                  _MK_ENUM_CONST(2)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_ENABLE                   _MK_ENUM_CONST(3)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SLAVE_TO_MC                      _MK_ENUM_CONST(4)
+
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_FIELD                     (_MK_MASK_CONST(0x3) << EMC_STAT_CONTROL_0_PWR_GATHER_SHIFT)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_RANGE                     9:8
+#define EMC_STAT_CONTROL_0_PWR_GATHER_WOFFSET                   0x0
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_INIT_ENUM                 RST
+#define EMC_STAT_CONTROL_0_PWR_GATHER_RST                       _MK_ENUM_CONST(0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_CLEAR                     _MK_ENUM_CONST(1)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DISABLE                   _MK_ENUM_CONST(2)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_ENABLE                    _MK_ENUM_CONST(3)
+
+
+// Register EMC_STAT_STATUS_0  
+#define EMC_STAT_STATUS_0                       _MK_ADDR_CONST(0xc4)
+#define EMC_STAT_STATUS_0_WORD_COUNT                    0x1
+#define EMC_STAT_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x101)
+#define EMC_STAT_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << EMC_STAT_STATUS_0_LLMC_LIMIT_SHIFT)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_RANGE                      0:0
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_WOFFSET                    0x0
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_FIELD                       (_MK_MASK_CONST(0x1) << EMC_STAT_STATUS_0_PWR_LIMIT_SHIFT)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_RANGE                       8:8
+#define EMC_STAT_STATUS_0_PWR_LIMIT_WOFFSET                     0x0
+#define EMC_STAT_STATUS_0_PWR_LIMIT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_LLMC_ADDR_LOW_0  
+#define EMC_STAT_LLMC_ADDR_LOW_0                        _MK_ADDR_CONST(0xc8)
+#define EMC_STAT_LLMC_ADDR_LOW_0_WORD_COUNT                     0x1
+#define EMC_STAT_LLMC_ADDR_LOW_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_RESET_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_READ_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_WRITE_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SHIFT                    _MK_SHIFT_CONST(4)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_FIELD                    (_MK_MASK_CONST(0x3ffffff) << EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SHIFT)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_RANGE                    29:4
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_WOFFSET                  0x0
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_DEFAULT_MASK                     _MK_MASK_CONST(0x3ffffff)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_LLMC_ADDR_HIGH_0  
+#define EMC_STAT_LLMC_ADDR_HIGH_0                       _MK_ADDR_CONST(0xcc)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_WORD_COUNT                    0x1
+#define EMC_STAT_LLMC_ADDR_HIGH_0_RESET_VAL                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_RESET_MASK                    _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_READ_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_WRITE_MASK                    _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SHIFT                  _MK_SHIFT_CONST(4)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_FIELD                  (_MK_MASK_CONST(0x3ffffff) << EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SHIFT)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_RANGE                  29:4
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_WOFFSET                        0x0
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_DEFAULT                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_INIT_ENUM                      -1
+
+
+// Register EMC_STAT_LLMC_CLOCK_LIMIT_0  
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0                     _MK_ADDR_CONST(0xd0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_WORD_COUNT                  0x1
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_RESET_VAL                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SHIFT)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_RANGE                      31:0
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_WOFFSET                    0x0
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_DEFAULT                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_INIT_ENUM                  -1
+
+
+// Register EMC_STAT_LLMC_CLOCKS_0  
+#define EMC_STAT_LLMC_CLOCKS_0                  _MK_ADDR_CONST(0xd4)
+#define EMC_STAT_LLMC_CLOCKS_0_WORD_COUNT                       0x1
+#define EMC_STAT_LLMC_CLOCKS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCKS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SHIFT)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_RANGE                        31:0
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_WOFFSET                      0x0
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Packet AREMC_STAT_CONTROL
+#define AREMC_STAT_CONTROL_SIZE 28
+
+#define AREMC_STAT_CONTROL_MODE_SHIFT                   _MK_SHIFT_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_FIELD                   (_MK_MASK_CONST(0x3) << AREMC_STAT_CONTROL_MODE_SHIFT)
+#define AREMC_STAT_CONTROL_MODE_RANGE                   _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_ROW                     0
+#define AREMC_STAT_CONTROL_MODE_BANDWIDTH                       _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_LATENCY_AVG                     _MK_ENUM_CONST(1)
+#define AREMC_STAT_CONTROL_MODE_LATENCY_HISTO                   _MK_ENUM_CONST(2)
+
+#define AREMC_STAT_CONTROL_SKIP_SHIFT                   _MK_SHIFT_CONST(4)
+#define AREMC_STAT_CONTROL_SKIP_FIELD                   (_MK_MASK_CONST(0x7) << AREMC_STAT_CONTROL_SKIP_SHIFT)
+#define AREMC_STAT_CONTROL_SKIP_RANGE                   _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(4)
+#define AREMC_STAT_CONTROL_SKIP_ROW                     0
+
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT                    _MK_SHIFT_CONST(8)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_RANGE                    _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_ROW                      0
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_CMCR                     _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER                  _MK_ENUM_CONST(1)
+
+#define AREMC_STAT_CONTROL_EVENT_SHIFT                  _MK_SHIFT_CONST(16)
+#define AREMC_STAT_CONTROL_EVENT_FIELD                  (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_EVENT_SHIFT)
+#define AREMC_STAT_CONTROL_EVENT_RANGE                  _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
+#define AREMC_STAT_CONTROL_EVENT_ROW                    0
+#define AREMC_STAT_CONTROL_EVENT_QUALIFIED                      _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_EVENT_RD_WR_CHANGE                   _MK_ENUM_CONST(1)
+
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT                  _MK_SHIFT_CONST(26)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_FIELD                  (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_RANGE                  _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_ROW                    0
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_DISABLE                        _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_ENABLE                 _MK_ENUM_CONST(1)
+
+#define AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT                    _MK_SHIFT_CONST(27)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_FIELD                    (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_RANGE                    _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_ROW                      0
+#define AREMC_STAT_CONTROL_FILTER_ADDR_DISABLE                  _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register EMC_STAT_LLMC_CONTROL_0_0  
+#define EMC_STAT_LLMC_CONTROL_0_0                       _MK_ADDR_CONST(0xd8)
+#define EMC_STAT_LLMC_CONTROL_0_0_WORD_COUNT                    0x1
+#define EMC_STAT_LLMC_CONTROL_0_0_RESET_VAL                     _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_CONTROL_0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SHIFT)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_RANGE                  31:0
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_WOFFSET                        0x0
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_DEFAULT                        _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_INIT_ENUM                      -65536
+
+
+// Reserved address 220 [0xdc] 
+
+// Packet AREMC_STAT_HIST_LIMIT
+#define AREMC_STAT_HIST_LIMIT_SIZE 32
+
+#define AREMC_STAT_HIST_LIMIT_LOW_SHIFT                 _MK_SHIFT_CONST(0)
+#define AREMC_STAT_HIST_LIMIT_LOW_FIELD                 (_MK_MASK_CONST(0xffff) << AREMC_STAT_HIST_LIMIT_LOW_SHIFT)
+#define AREMC_STAT_HIST_LIMIT_LOW_RANGE                 _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define AREMC_STAT_HIST_LIMIT_LOW_ROW                   0
+
+#define AREMC_STAT_HIST_LIMIT_HIGH_SHIFT                        _MK_SHIFT_CONST(16)
+#define AREMC_STAT_HIST_LIMIT_HIGH_FIELD                        (_MK_MASK_CONST(0xffff) << AREMC_STAT_HIST_LIMIT_HIGH_SHIFT)
+#define AREMC_STAT_HIST_LIMIT_HIGH_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define AREMC_STAT_HIST_LIMIT_HIGH_ROW                  0
+
+
+// Register EMC_STAT_LLMC_HIST_LIMIT_0_0  
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0                    _MK_ADDR_CONST(0xe0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_WORD_COUNT                         0x1
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_RESET_VAL                  _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_FIELD                    (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SHIFT)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_RANGE                    31:0
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_WOFFSET                  0x0
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_DEFAULT                  _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_INIT_ENUM                        -65536
+
+
+// Reserved address 228 [0xe4] 
+
+// Register EMC_STAT_LLMC_COUNT_0_0  
+#define EMC_STAT_LLMC_COUNT_0_0                 _MK_ADDR_CONST(0xe8)
+#define EMC_STAT_LLMC_COUNT_0_0_WORD_COUNT                      0x1
+#define EMC_STAT_LLMC_COUNT_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_COUNT_0_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SHIFT)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_RANGE                      31:0
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_WOFFSET                    0x0
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 236 [0xec] 
+
+// Register EMC_STAT_LLMC_HIST_0_0  
+#define EMC_STAT_LLMC_HIST_0_0                  _MK_ADDR_CONST(0xf0)
+#define EMC_STAT_LLMC_HIST_0_0_WORD_COUNT                       0x1
+#define EMC_STAT_LLMC_HIST_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_0_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SHIFT)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_RANGE                        31:0
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_WOFFSET                      0x0
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 244 [0xf4] 
+
+// Register EMC_STAT_PWR_CLOCK_LIMIT_0  
+#define EMC_STAT_PWR_CLOCK_LIMIT_0                      _MK_ADDR_CONST(0xf8)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_WORD_COUNT                   0x1
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_RESET_VAL                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SHIFT)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_RANGE                        31:0
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_WOFFSET                      0x0
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_DEFAULT                      _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_INIT_ENUM                    -1
+
+
+// Register EMC_STAT_PWR_CLOCKS_0  
+#define EMC_STAT_PWR_CLOCKS_0                   _MK_ADDR_CONST(0xfc)
+#define EMC_STAT_PWR_CLOCKS_0_WORD_COUNT                        0x1
+#define EMC_STAT_PWR_CLOCKS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCKS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_FIELD                  (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SHIFT)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_RANGE                  31:0
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_WOFFSET                        0x0
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_PWR_COUNT_0  
+#define EMC_STAT_PWR_COUNT_0                    _MK_ADDR_CONST(0x100)
+#define EMC_STAT_PWR_COUNT_0_WORD_COUNT                         0x1
+#define EMC_STAT_PWR_COUNT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_COUNT_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_FIELD                    (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_COUNT_0_PWR_COUNT_SHIFT)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_RANGE                    31:0
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_WOFFSET                  0x0
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AUTO_CAL_CONFIG_0  
+#define EMC_AUTO_CAL_CONFIG_0                   _MK_ADDR_CONST(0x104)
+#define EMC_AUTO_CAL_CONFIG_0_WORD_COUNT                        0x1
+#define EMC_AUTO_CAL_CONFIG_0_RESET_VAL                         _MK_MASK_CONST(0xa60000)
+#define EMC_AUTO_CAL_CONFIG_0_RESET_MASK                        _MK_MASK_CONST(0xc3ff1f1f)
+#define EMC_AUTO_CAL_CONFIG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_READ_MASK                         _MK_MASK_CONST(0xc3ff1f1f)
+#define EMC_AUTO_CAL_CONFIG_0_WRITE_MASK                        _MK_MASK_CONST(0x43ff1f1f)
+// 2's complement offset for pull-up value
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_RANGE                  4:0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_WOFFSET                        0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 2's complement offset for pull-down value
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT                  _MK_SHIFT_CONST(8)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_RANGE                  12:8
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_WOFFSET                        0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Auto Cal calibration step interval (in emc clocks)
+// - the default is set for 1.0us calibration step at 166MHz
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT                       _MK_SHIFT_CONST(16)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_FIELD                       (_MK_MASK_CONST(0x3ff) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_RANGE                       25:16
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_WOFFSET                     0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT                     _MK_MASK_CONST(0xa6)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0 (normal operation): use AUTO_CAL_PU/PD_OFFSET as an offset 
+//                       to the calibration tate machine setting
+// 1 (override)        : use AUTO_CAL_PU/PD_OFFSET register 
+//                       values directly
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(30)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_RANGE                   30:30
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_WOFFSET                 0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Writing a one to this bit starts the calibration state
+// machine.  This bit must be set even if the override is
+// set in order to latch in the override value.
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT                      _MK_SHIFT_CONST(31)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_FIELD                      (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_RANGE                      31:31
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_WOFFSET                    0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AUTO_CAL_INTERVAL_0  
+#define EMC_AUTO_CAL_INTERVAL_0                 _MK_ADDR_CONST(0x108)
+#define EMC_AUTO_CAL_INTERVAL_0_WORD_COUNT                      0x1
+#define EMC_AUTO_CAL_INTERVAL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_READ_MASK                       _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff)
+// 0: do calibration once
+// Otherwise, auto-calibration occurs at intervals equivalent
+// to the programmed number of cycles.
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_FIELD                 (_MK_MASK_CONST(0xfffffff) << EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_RANGE                 27:0
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_WOFFSET                       0x0
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AUTO_CAL_STATUS_0  
+#define EMC_AUTO_CAL_STATUS_0                   _MK_ADDR_CONST(0x10c)
+#define EMC_AUTO_CAL_STATUS_0_WORD_COUNT                        0x1
+#define EMC_AUTO_CAL_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x9f1f1f1f)
+#define EMC_AUTO_CAL_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Pullup code generated by auto-calibration
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_RANGE                     4:0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_WOFFSET                   0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pulldown code generated by auto-calibration
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_FIELD                   (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_RANGE                   12:8
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_WOFFSET                 0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pullup code sent to pads
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_RANGE                 20:16
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_WOFFSET                       0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Pulldown code sent to pads
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT                       _MK_SHIFT_CONST(24)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_FIELD                       (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_RANGE                       28:24
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_WOFFSET                     0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// One when auto calibrate is active
+// - valid only after auto calibrate sequence has 
+// completed (EMC_CAL_ACTIVE == 0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT                     _MK_SHIFT_CONST(31)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_FIELD                     (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_RANGE                     31:31
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_WOFFSET                   0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_AREMC_REGS(_op_) \
+_op_(EMC_INTSTATUS_0) \
+_op_(EMC_INTMASK_0) \
+_op_(EMC_DBG_0) \
+_op_(EMC_CFG_0) \
+_op_(EMC_ADR_CFG_0) \
+_op_(EMC_REFCTRL_0) \
+_op_(EMC_PIN_0) \
+_op_(EMC_TIMING_CONTROL_0) \
+_op_(EMC_TIMING0_0) \
+_op_(EMC_TIMING1_0) \
+_op_(EMC_TIMING2_0) \
+_op_(EMC_TIMING3_0) \
+_op_(EMC_TIMING4_0) \
+_op_(EMC_TIMING5_0) \
+_op_(EMC_MRS_0) \
+_op_(EMC_EMRS_0) \
+_op_(EMC_REF_0) \
+_op_(EMC_PRE_0) \
+_op_(EMC_NOP_0) \
+_op_(EMC_SELF_REF_0) \
+_op_(EMC_DPD_0) \
+_op_(EMC_CMDQ_0) \
+_op_(EMC_FBIO_CFG1_0) \
+_op_(EMC_FBIO_DQSIB_DLY_0) \
+_op_(EMC_FBIO_SPARE_0) \
+_op_(EMC_FBIO_CFG5_0) \
+_op_(EMC_FBIO_WRPTR_EQ_2_0) \
+_op_(EMC_FBIO_QUSE_DLY_0) \
+_op_(EMC_FBIO_CFG6_0) \
+_op_(EMC_BUSARB_0) \
+_op_(EMC_DYN_DQS_0) \
+_op_(EMC_DYN_QUSE_0) \
+_op_(EMC_DQS_TRIMMER_RD0_0) \
+_op_(EMC_DQS_TRIMMER_RD1_0) \
+_op_(EMC_DQS_TRIMMER_RD2_0) \
+_op_(EMC_DQS_TRIMMER_RD3_0) \
+_op_(EMC_QUSE_TRIMMER_RD0_0) \
+_op_(EMC_QUSE_TRIMMER_RD1_0) \
+_op_(EMC_QUSE_TRIMMER_RD2_0) \
+_op_(EMC_QUSE_TRIMMER_RD3_0) \
+_op_(EMC_CLKEN_OVERRIDE_0) \
+_op_(EMC_LL_ARB_CONFIG_0) \
+_op_(EMC_T_MIN_CRITICAL_HP_0) \
+_op_(EMC_T_MIN_CRITICAL_TIMEOUT_0) \
+_op_(EMC_T_MIN_LOAD_0) \
+_op_(EMC_T_MAX_CRITICAL_HP_0) \
+_op_(EMC_T_MAX_CRITICAL_TIMEOUT_0) \
+_op_(EMC_T_MAX_LOAD_0) \
+_op_(EMC_STAT_CONTROL_0) \
+_op_(EMC_STAT_STATUS_0) \
+_op_(EMC_STAT_LLMC_ADDR_LOW_0) \
+_op_(EMC_STAT_LLMC_ADDR_HIGH_0) \
+_op_(EMC_STAT_LLMC_CLOCK_LIMIT_0) \
+_op_(EMC_STAT_LLMC_CLOCKS_0) \
+_op_(EMC_STAT_LLMC_CONTROL_0_0) \
+_op_(EMC_STAT_LLMC_HIST_LIMIT_0_0) \
+_op_(EMC_STAT_LLMC_COUNT_0_0) \
+_op_(EMC_STAT_LLMC_HIST_0_0) \
+_op_(EMC_STAT_PWR_CLOCK_LIMIT_0) \
+_op_(EMC_STAT_PWR_CLOCKS_0) \
+_op_(EMC_STAT_PWR_COUNT_0) \
+_op_(EMC_AUTO_CAL_CONFIG_0) \
+_op_(EMC_AUTO_CAL_INTERVAL_0) \
+_op_(EMC_AUTO_CAL_STATUS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_EMC        0x00000000
+
+//
+// AREMC REGISTER BANKS
+//
+
+#define EMC0_FIRST_REG 0x0000 // EMC_INTSTATUS_0
+#define EMC0_LAST_REG 0x00d8 // EMC_STAT_LLMC_CONTROL_0_0
+#define EMC1_FIRST_REG 0x00e0 // EMC_STAT_LLMC_HIST_LIMIT_0_0
+#define EMC1_LAST_REG 0x00e0 // EMC_STAT_LLMC_HIST_LIMIT_0_0
+#define EMC2_FIRST_REG 0x00e8 // EMC_STAT_LLMC_COUNT_0_0
+#define EMC2_LAST_REG 0x00e8 // EMC_STAT_LLMC_COUNT_0_0
+#define EMC3_FIRST_REG 0x00f0 // EMC_STAT_LLMC_HIST_0_0
+#define EMC3_LAST_REG 0x00f0 // EMC_STAT_LLMC_HIST_0_0
+#define EMC4_FIRST_REG 0x00f8 // EMC_STAT_PWR_CLOCK_LIMIT_0
+#define EMC4_LAST_REG 0x010c // EMC_AUTO_CAL_STATUS_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___AREMC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arevp.h b/arch/arm/mach-tegra/nv/include/ap15/arevp.h
new file mode 100644
index 000000000000..3c87bad8b538
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arevp.h
@@ -0,0 +1,2373 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___AREVP_H_INC_
+#define ___AREVP_H_INC_
+
+// Register EVP_RESET_VECTOR_0  
+#define EVP_RESET_VECTOR_0                      _MK_ADDR_CONST(0x0)
+#define EVP_RESET_VECTOR_0_WORD_COUNT                   0x1
+#define EVP_RESET_VECTOR_0_RESET_VAL                    _MK_MASK_CONST(0xffff0000)
+#define EVP_RESET_VECTOR_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_RESET_VECTOR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EVP_RESET_VECTOR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EVP_RESET_VECTOR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_RESET_VECTOR_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// RESET Exception Vector Pointer 
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_RESET_VECTOR_0_RESET_VECTOR_SHIFT)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_RANGE                   31:0
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_WOFFSET                 0x0
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_DEFAULT                 _MK_MASK_CONST(0xffff0000)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_INIT_ENUM                       -65536
+
+
+// Register EVP_UNDEF_VECTOR_0  
+#define EVP_UNDEF_VECTOR_0                      _MK_ADDR_CONST(0x4)
+#define EVP_UNDEF_VECTOR_0_WORD_COUNT                   0x1
+#define EVP_UNDEF_VECTOR_0_RESET_VAL                    _MK_MASK_CONST(0xffff0004)
+#define EVP_UNDEF_VECTOR_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_UNDEF_VECTOR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EVP_UNDEF_VECTOR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EVP_UNDEF_VECTOR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_UNDEF_VECTOR_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Undefined Exception Vector Pointer
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SHIFT)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_RANGE                   31:0
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_WOFFSET                 0x0
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_DEFAULT                 _MK_MASK_CONST(0xffff0004)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_INIT_ENUM                       -65532
+
+
+// Register EVP_SWI_VECTOR_0  
+#define EVP_SWI_VECTOR_0                        _MK_ADDR_CONST(0x8)
+#define EVP_SWI_VECTOR_0_WORD_COUNT                     0x1
+#define EVP_SWI_VECTOR_0_RESET_VAL                      _MK_MASK_CONST(0xffff0008)
+#define EVP_SWI_VECTOR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_SWI_VECTOR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EVP_SWI_VECTOR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EVP_SWI_VECTOR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_SWI_VECTOR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Software Interrupt Vector Pointer
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_SWI_VECTOR_0_SWI_VECTOR_SHIFT)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_RANGE                       31:0
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_WOFFSET                     0x0
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_DEFAULT                     _MK_MASK_CONST(0xffff0008)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_INIT_ENUM                   -65528
+
+
+// Register EVP_PREFETCH_ABORT_VECTOR_0  
+#define EVP_PREFETCH_ABORT_VECTOR_0                     _MK_ADDR_CONST(0xc)
+#define EVP_PREFETCH_ABORT_VECTOR_0_WORD_COUNT                  0x1
+#define EVP_PREFETCH_ABORT_VECTOR_0_RESET_VAL                   _MK_MASK_CONST(0xffff000c)
+#define EVP_PREFETCH_ABORT_VECTOR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PREFETCH_ABORT_VECTOR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PREFETCH_ABORT_VECTOR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Code Prefetch ABORT Vector Pointer 
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SHIFT                      _MK_SHIFT_CONST(0)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_FIELD                      (_MK_MASK_CONST(0xffffffff) << EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SHIFT)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_RANGE                      31:0
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_WOFFSET                    0x0
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_DEFAULT                    _MK_MASK_CONST(0xffff000c)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_INIT_ENUM                  -65524
+
+
+// Register EVP_DATA_ABORT_VECTOR_0  
+#define EVP_DATA_ABORT_VECTOR_0                 _MK_ADDR_CONST(0x10)
+#define EVP_DATA_ABORT_VECTOR_0_WORD_COUNT                      0x1
+#define EVP_DATA_ABORT_VECTOR_0_RESET_VAL                       _MK_MASK_CONST(0xffff0010)
+#define EVP_DATA_ABORT_VECTOR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_DATA_ABORT_VECTOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_DATA_ABORT_VECTOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_DATA_ABORT_VECTOR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_DATA_ABORT_VECTOR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// Data ABORT Vector Pointer
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SHIFT)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_RANGE                 31:0
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_WOFFSET                       0x0
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_DEFAULT                       _MK_MASK_CONST(0xffff0010)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_INIT_ENUM                     -65520
+
+
+// Register EVP_RSVD_VECTOR_0  
+#define EVP_RSVD_VECTOR_0                       _MK_ADDR_CONST(0x14)
+#define EVP_RSVD_VECTOR_0_WORD_COUNT                    0x1
+#define EVP_RSVD_VECTOR_0_RESET_VAL                     _MK_MASK_CONST(0xffff0014)
+#define EVP_RSVD_VECTOR_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_RSVD_VECTOR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_RSVD_VECTOR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_RSVD_VECTOR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_RSVD_VECTOR_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Reserved Exception Vector Pointer
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_RSVD_VECTOR_0_RSVD_VECTOR_SHIFT)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_RANGE                     31:0
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_WOFFSET                   0x0
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_DEFAULT                   _MK_MASK_CONST(0xffff0014)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_INIT_ENUM                 -65516
+
+
+// Register EVP_IRQ_VECTOR_0  
+#define EVP_IRQ_VECTOR_0                        _MK_ADDR_CONST(0x18)
+#define EVP_IRQ_VECTOR_0_WORD_COUNT                     0x1
+#define EVP_IRQ_VECTOR_0_RESET_VAL                      _MK_MASK_CONST(0xffff0018)
+#define EVP_IRQ_VECTOR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_VECTOR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EVP_IRQ_VECTOR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EVP_IRQ_VECTOR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_VECTOR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// IRQ Vector Pointer 
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_IRQ_VECTOR_0_IRQ_VECTOR_SHIFT)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_RANGE                       31:0
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_WOFFSET                     0x0
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xffff0018)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_INIT_ENUM                   -65512
+
+
+// Register EVP_FIQ_VECTOR_0  
+#define EVP_FIQ_VECTOR_0                        _MK_ADDR_CONST(0x1c)
+#define EVP_FIQ_VECTOR_0_WORD_COUNT                     0x1
+#define EVP_FIQ_VECTOR_0_RESET_VAL                      _MK_MASK_CONST(0xffff001c)
+#define EVP_FIQ_VECTOR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_VECTOR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EVP_FIQ_VECTOR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EVP_FIQ_VECTOR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_VECTOR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// FIQ Vector Pointer 
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_FIQ_VECTOR_0_FIQ_VECTOR_SHIFT)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_RANGE                       31:0
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_WOFFSET                     0x0
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xffff001c)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_INIT_ENUM                   -65508
+
+
+// Register EVP_IRQ_STS_0  
+#define EVP_IRQ_STS_0                   _MK_ADDR_CONST(0x20)
+#define EVP_IRQ_STS_0_WORD_COUNT                        0x1
+#define EVP_IRQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_IRQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_IRQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_IRQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// FFS (from lsb) IRQ index  (0x80 indicates no active IRQ)
+#define EVP_IRQ_STS_0_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_IRQ_STS_0_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_IRQ_STS_0_IRQ_STS_SHIFT)
+#define EVP_IRQ_STS_0_IRQ_STS_RANGE                     31:0
+#define EVP_IRQ_STS_0_IRQ_STS_WOFFSET                   0x0
+#define EVP_IRQ_STS_0_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_IRQ_STS_0_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_STS_0_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_IRQ_STS_0_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_STS_0  
+#define EVP_PRI_IRQ_STS_0                       _MK_ADDR_CONST(0x24)
+#define EVP_PRI_IRQ_STS_0_WORD_COUNT                    0x1
+#define EVP_PRI_IRQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Current highest priority active IRQ (0x80 indicates no active priority IRQ)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SHIFT)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_RANGE                     31:0
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_WOFFSET                   0x0
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_FIQ_STS_0  
+#define EVP_FIQ_STS_0                   _MK_ADDR_CONST(0x28)
+#define EVP_FIQ_STS_0_WORD_COUNT                        0x1
+#define EVP_FIQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_FIQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_FIQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_FIQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// FFS (from lsb) FIQ index (0x80 indicates no active FIQ)
+#define EVP_FIQ_STS_0_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_FIQ_STS_0_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_FIQ_STS_0_FIQ_STS_SHIFT)
+#define EVP_FIQ_STS_0_FIQ_STS_RANGE                     31:0
+#define EVP_FIQ_STS_0_FIQ_STS_WOFFSET                   0x0
+#define EVP_FIQ_STS_0_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_FIQ_STS_0_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_STS_0_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_FIQ_STS_0_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_STS_0  
+#define EVP_PRI_FIQ_STS_0                       _MK_ADDR_CONST(0x2c)
+#define EVP_PRI_FIQ_STS_0_WORD_COUNT                    0x1
+#define EVP_PRI_FIQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Current highest priority active FIQ (0x80 indicates no active priority FIQ)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SHIFT)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_RANGE                     31:0
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_WOFFSET                   0x0
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_0_0  
+#define EVP_PRI_IRQ_NUM_0_0                     _MK_ADDR_CONST(0x40)
+#define EVP_PRI_IRQ_NUM_0_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_0_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT)
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_0_0  
+#define EVP_PRI_IRQ_VEC_0_0                     _MK_ADDR_CONST(0x44)
+#define EVP_PRI_IRQ_VEC_0_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_0_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT)
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_1_0  
+#define EVP_PRI_IRQ_NUM_1_0                     _MK_ADDR_CONST(0x48)
+#define EVP_PRI_IRQ_NUM_1_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_1_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT)
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_1_0  
+#define EVP_PRI_IRQ_VEC_1_0                     _MK_ADDR_CONST(0x4c)
+#define EVP_PRI_IRQ_VEC_1_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_1_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT)
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_2_0  
+#define EVP_PRI_IRQ_NUM_2_0                     _MK_ADDR_CONST(0x50)
+#define EVP_PRI_IRQ_NUM_2_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_2_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT)
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_2_0  
+#define EVP_PRI_IRQ_VEC_2_0                     _MK_ADDR_CONST(0x54)
+#define EVP_PRI_IRQ_VEC_2_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_2_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT)
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_3_0  
+#define EVP_PRI_IRQ_NUM_3_0                     _MK_ADDR_CONST(0x58)
+#define EVP_PRI_IRQ_NUM_3_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_3_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT)
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_3_0  
+#define EVP_PRI_IRQ_VEC_3_0                     _MK_ADDR_CONST(0x5c)
+#define EVP_PRI_IRQ_VEC_3_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_3_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT)
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_4_0  
+#define EVP_PRI_IRQ_NUM_4_0                     _MK_ADDR_CONST(0x60)
+#define EVP_PRI_IRQ_NUM_4_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_4_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_4_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_4_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_4_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT)
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_4_0  
+#define EVP_PRI_IRQ_VEC_4_0                     _MK_ADDR_CONST(0x64)
+#define EVP_PRI_IRQ_VEC_4_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_4_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_4_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_4_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_4_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT)
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_5_0  
+#define EVP_PRI_IRQ_NUM_5_0                     _MK_ADDR_CONST(0x68)
+#define EVP_PRI_IRQ_NUM_5_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_5_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_5_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_5_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_5_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_5_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_5_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT)
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_5_0  
+#define EVP_PRI_IRQ_VEC_5_0                     _MK_ADDR_CONST(0x6c)
+#define EVP_PRI_IRQ_VEC_5_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_5_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_5_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_5_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_5_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_5_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_5_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT)
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_6_0  
+#define EVP_PRI_IRQ_NUM_6_0                     _MK_ADDR_CONST(0x70)
+#define EVP_PRI_IRQ_NUM_6_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_6_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_6_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_6_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_6_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_6_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_6_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT)
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_6_0  
+#define EVP_PRI_IRQ_VEC_6_0                     _MK_ADDR_CONST(0x74)
+#define EVP_PRI_IRQ_VEC_6_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_6_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_6_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_6_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_6_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_6_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_6_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT)
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_7_0  
+#define EVP_PRI_IRQ_NUM_7_0                     _MK_ADDR_CONST(0x78)
+#define EVP_PRI_IRQ_NUM_7_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_7_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_7_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_7_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_7_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_7_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_7_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT)
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_7_0  
+#define EVP_PRI_IRQ_VEC_7_0                     _MK_ADDR_CONST(0x7c)
+#define EVP_PRI_IRQ_VEC_7_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_7_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_7_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_7_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_7_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_7_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_7_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT)
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_NUM_0_0  
+#define EVP_PRI_FIQ_NUM_0_0                     _MK_ADDR_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_0_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_NUM_0_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT)
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_RANGE                 31:0
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_WOFFSET                       0x0
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_VEC_0_0  
+#define EVP_PRI_FIQ_VEC_0_0                     _MK_ADDR_CONST(0x84)
+#define EVP_PRI_FIQ_VEC_0_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_VEC_0_0_RESET_VAL                   _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT)
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_RANGE                 31:0
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_WOFFSET                       0x0
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT                       _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_NUM_1_0  
+#define EVP_PRI_FIQ_NUM_1_0                     _MK_ADDR_CONST(0x88)
+#define EVP_PRI_FIQ_NUM_1_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_NUM_1_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT)
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_RANGE                 31:0
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_WOFFSET                       0x0
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_VEC_1_0  
+#define EVP_PRI_FIQ_VEC_1_0                     _MK_ADDR_CONST(0x8c)
+#define EVP_PRI_FIQ_VEC_1_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_VEC_1_0_RESET_VAL                   _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT)
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_RANGE                 31:0
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_WOFFSET                       0x0
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT                       _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_NUM_2_0  
+#define EVP_PRI_FIQ_NUM_2_0                     _MK_ADDR_CONST(0x90)
+#define EVP_PRI_FIQ_NUM_2_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_NUM_2_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT)
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_RANGE                 31:0
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_WOFFSET                       0x0
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_VEC_2_0  
+#define EVP_PRI_FIQ_VEC_2_0                     _MK_ADDR_CONST(0x94)
+#define EVP_PRI_FIQ_VEC_2_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_VEC_2_0_RESET_VAL                   _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT)
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_RANGE                 31:0
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_WOFFSET                       0x0
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT                       _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_NUM_3_0  
+#define EVP_PRI_FIQ_NUM_3_0                     _MK_ADDR_CONST(0x98)
+#define EVP_PRI_FIQ_NUM_3_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_NUM_3_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT)
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_RANGE                 31:0
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_WOFFSET                       0x0
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_VEC_3_0  
+#define EVP_PRI_FIQ_VEC_3_0                     _MK_ADDR_CONST(0x9c)
+#define EVP_PRI_FIQ_VEC_3_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_VEC_3_0_RESET_VAL                   _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT)
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_RANGE                 31:0
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_WOFFSET                       0x0
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT                       _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_RESET_VECTOR_0  
+#define EVP_CPU_RESET_VECTOR_0                  _MK_ADDR_CONST(0x100)
+#define EVP_CPU_RESET_VECTOR_0_WORD_COUNT                       0x1
+#define EVP_CPU_RESET_VECTOR_0_RESET_VAL                        _MK_MASK_CONST(0xffff0000)
+#define EVP_CPU_RESET_VECTOR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RESET_VECTOR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_RESET_VECTOR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_RESET_VECTOR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RESET_VECTOR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// RESET Exception Vector Pointer 
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SHIFT)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_RANGE                   31:0
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_WOFFSET                 0x0
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_DEFAULT                 _MK_MASK_CONST(0xffff0000)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_INIT_ENUM                       -65536
+
+
+// Register EVP_CPU_UNDEF_VECTOR_0  
+#define EVP_CPU_UNDEF_VECTOR_0                  _MK_ADDR_CONST(0x104)
+#define EVP_CPU_UNDEF_VECTOR_0_WORD_COUNT                       0x1
+#define EVP_CPU_UNDEF_VECTOR_0_RESET_VAL                        _MK_MASK_CONST(0xffff0004)
+#define EVP_CPU_UNDEF_VECTOR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_UNDEF_VECTOR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_UNDEF_VECTOR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_UNDEF_VECTOR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_UNDEF_VECTOR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// Undefined Exception Vector Pointer
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SHIFT)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_RANGE                   31:0
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_WOFFSET                 0x0
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_DEFAULT                 _MK_MASK_CONST(0xffff0004)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_INIT_ENUM                       -65532
+
+
+// Register EVP_CPU_SWI_VECTOR_0  
+#define EVP_CPU_SWI_VECTOR_0                    _MK_ADDR_CONST(0x108)
+#define EVP_CPU_SWI_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_CPU_SWI_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xffff0008)
+#define EVP_CPU_SWI_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_SWI_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_SWI_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_SWI_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_SWI_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Software Interrupt Vector Pointer
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SHIFT)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_RANGE                       31:0
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_WOFFSET                     0x0
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_DEFAULT                     _MK_MASK_CONST(0xffff0008)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_INIT_ENUM                   -65528
+
+
+// Register EVP_CPU_PREFETCH_ABORT_VECTOR_0  
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0                 _MK_ADDR_CONST(0x10c)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_WORD_COUNT                      0x1
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_RESET_VAL                       _MK_MASK_CONST(0xffff000c)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Code Prefetch ABORT Vector Pointer 
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_SHIFT                      _MK_SHIFT_CONST(0)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_FIELD                      (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_SHIFT)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_RANGE                      31:0
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_WOFFSET                    0x0
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_DEFAULT                    _MK_MASK_CONST(0xffff000c)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_INIT_ENUM                  -65524
+
+
+// Register EVP_CPU_DATA_ABORT_VECTOR_0  
+#define EVP_CPU_DATA_ABORT_VECTOR_0                     _MK_ADDR_CONST(0x110)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_WORD_COUNT                  0x1
+#define EVP_CPU_DATA_ABORT_VECTOR_0_RESET_VAL                   _MK_MASK_CONST(0xffff0010)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Data ABORT Vector Pointer
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_SHIFT)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_RANGE                 31:0
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_WOFFSET                       0x0
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_DEFAULT                       _MK_MASK_CONST(0xffff0010)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_INIT_ENUM                     -65520
+
+
+// Register EVP_CPU_RSVD_VECTOR_0  
+#define EVP_CPU_RSVD_VECTOR_0                   _MK_ADDR_CONST(0x114)
+#define EVP_CPU_RSVD_VECTOR_0_WORD_COUNT                        0x1
+#define EVP_CPU_RSVD_VECTOR_0_RESET_VAL                         _MK_MASK_CONST(0xffff0014)
+#define EVP_CPU_RSVD_VECTOR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RSVD_VECTOR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_RSVD_VECTOR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_RSVD_VECTOR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RSVD_VECTOR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Reserved Exception Vector Pointer
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SHIFT)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_RANGE                     31:0
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_WOFFSET                   0x0
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_DEFAULT                   _MK_MASK_CONST(0xffff0014)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_INIT_ENUM                 -65516
+
+
+// Register EVP_CPU_IRQ_VECTOR_0  
+#define EVP_CPU_IRQ_VECTOR_0                    _MK_ADDR_CONST(0x118)
+#define EVP_CPU_IRQ_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_CPU_IRQ_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xffff0018)
+#define EVP_CPU_IRQ_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// IRQ Vector Pointer 
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SHIFT)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_RANGE                       31:0
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_WOFFSET                     0x0
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xffff0018)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_INIT_ENUM                   -65512
+
+
+// Register EVP_CPU_FIQ_VECTOR_0  
+#define EVP_CPU_FIQ_VECTOR_0                    _MK_ADDR_CONST(0x11c)
+#define EVP_CPU_FIQ_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_CPU_FIQ_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xffff001c)
+#define EVP_CPU_FIQ_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// FIQ Vector Pointer 
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SHIFT)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_RANGE                       31:0
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_WOFFSET                     0x0
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xffff001c)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_INIT_ENUM                   -65508
+
+
+// Register EVP_CPU_IRQ_STS_0  
+#define EVP_CPU_IRQ_STS_0                       _MK_ADDR_CONST(0x120)
+#define EVP_CPU_IRQ_STS_0_WORD_COUNT                    0x1
+#define EVP_CPU_IRQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_CPU_IRQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// FFS (from lsb) IRQ index  (0x80 indicates no active IRQ)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SHIFT)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_RANGE                     31:0
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_WOFFSET                   0x0
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_STS_0  
+#define EVP_CPU_PRI_IRQ_STS_0                   _MK_ADDR_CONST(0x124)
+#define EVP_CPU_PRI_IRQ_STS_0_WORD_COUNT                        0x1
+#define EVP_CPU_PRI_IRQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Current highest priority active IRQ (0x80 indicates no active priority IRQ)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SHIFT)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_FIQ_STS_0  
+#define EVP_CPU_FIQ_STS_0                       _MK_ADDR_CONST(0x128)
+#define EVP_CPU_FIQ_STS_0_WORD_COUNT                    0x1
+#define EVP_CPU_FIQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_CPU_FIQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// FFS (from lsb) FIQ index (0x80 indicates no active FIQ)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SHIFT)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_RANGE                     31:0
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_WOFFSET                   0x0
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_STS_0  
+#define EVP_CPU_PRI_FIQ_STS_0                   _MK_ADDR_CONST(0x12c)
+#define EVP_CPU_PRI_FIQ_STS_0_WORD_COUNT                        0x1
+#define EVP_CPU_PRI_FIQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Current highest priority active FIQ (0x80 indicates no active priority FIQ)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SHIFT)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_0_0  
+#define EVP_CPU_PRI_IRQ_NUM_0_0                 _MK_ADDR_CONST(0x140)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_0_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_0_0  
+#define EVP_CPU_PRI_IRQ_VEC_0_0                 _MK_ADDR_CONST(0x144)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_0_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_1_0  
+#define EVP_CPU_PRI_IRQ_NUM_1_0                 _MK_ADDR_CONST(0x148)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_1_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_1_0  
+#define EVP_CPU_PRI_IRQ_VEC_1_0                 _MK_ADDR_CONST(0x14c)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_1_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_2_0  
+#define EVP_CPU_PRI_IRQ_NUM_2_0                 _MK_ADDR_CONST(0x150)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_2_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_2_0  
+#define EVP_CPU_PRI_IRQ_VEC_2_0                 _MK_ADDR_CONST(0x154)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_2_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_3_0  
+#define EVP_CPU_PRI_IRQ_NUM_3_0                 _MK_ADDR_CONST(0x158)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_3_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_3_0  
+#define EVP_CPU_PRI_IRQ_VEC_3_0                 _MK_ADDR_CONST(0x15c)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_3_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_4_0  
+#define EVP_CPU_PRI_IRQ_NUM_4_0                 _MK_ADDR_CONST(0x160)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_4_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_4_0  
+#define EVP_CPU_PRI_IRQ_VEC_4_0                 _MK_ADDR_CONST(0x164)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_4_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_5_0  
+#define EVP_CPU_PRI_IRQ_NUM_5_0                 _MK_ADDR_CONST(0x168)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_5_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_5_0  
+#define EVP_CPU_PRI_IRQ_VEC_5_0                 _MK_ADDR_CONST(0x16c)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_5_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_6_0  
+#define EVP_CPU_PRI_IRQ_NUM_6_0                 _MK_ADDR_CONST(0x170)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_6_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_6_0  
+#define EVP_CPU_PRI_IRQ_VEC_6_0                 _MK_ADDR_CONST(0x174)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_6_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_7_0  
+#define EVP_CPU_PRI_IRQ_NUM_7_0                 _MK_ADDR_CONST(0x178)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_7_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_7_0  
+#define EVP_CPU_PRI_IRQ_VEC_7_0                 _MK_ADDR_CONST(0x17c)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_7_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_NUM_0_0  
+#define EVP_CPU_PRI_FIQ_NUM_0_0                 _MK_ADDR_CONST(0x180)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_NUM_0_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_VEC_0_0  
+#define EVP_CPU_PRI_FIQ_VEC_0_0                 _MK_ADDR_CONST(0x184)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_VEC_0_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_NUM_1_0  
+#define EVP_CPU_PRI_FIQ_NUM_1_0                 _MK_ADDR_CONST(0x188)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_NUM_1_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_VEC_1_0  
+#define EVP_CPU_PRI_FIQ_VEC_1_0                 _MK_ADDR_CONST(0x18c)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_VEC_1_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_NUM_2_0  
+#define EVP_CPU_PRI_FIQ_NUM_2_0                 _MK_ADDR_CONST(0x190)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_NUM_2_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_VEC_2_0  
+#define EVP_CPU_PRI_FIQ_VEC_2_0                 _MK_ADDR_CONST(0x194)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_VEC_2_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_NUM_3_0  
+#define EVP_CPU_PRI_FIQ_NUM_3_0                 _MK_ADDR_CONST(0x198)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_NUM_3_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_VEC_3_0  
+#define EVP_CPU_PRI_FIQ_VEC_3_0                 _MK_ADDR_CONST(0x19c)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_VEC_3_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_RESET_VECTOR_0  
+#define EVP_COP_RESET_VECTOR_0                  _MK_ADDR_CONST(0x200)
+#define EVP_COP_RESET_VECTOR_0_WORD_COUNT                       0x1
+#define EVP_COP_RESET_VECTOR_0_RESET_VAL                        _MK_MASK_CONST(0xffff0000)
+#define EVP_COP_RESET_VECTOR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RESET_VECTOR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EVP_COP_RESET_VECTOR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EVP_COP_RESET_VECTOR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RESET_VECTOR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// RESET Exception Vector Pointer 
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SHIFT)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_RANGE                   31:0
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_WOFFSET                 0x0
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_DEFAULT                 _MK_MASK_CONST(0xffff0000)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_INIT_ENUM                       -65536
+
+
+// Register EVP_COP_UNDEF_VECTOR_0  
+#define EVP_COP_UNDEF_VECTOR_0                  _MK_ADDR_CONST(0x204)
+#define EVP_COP_UNDEF_VECTOR_0_WORD_COUNT                       0x1
+#define EVP_COP_UNDEF_VECTOR_0_RESET_VAL                        _MK_MASK_CONST(0xffff0004)
+#define EVP_COP_UNDEF_VECTOR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_UNDEF_VECTOR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EVP_COP_UNDEF_VECTOR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EVP_COP_UNDEF_VECTOR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_UNDEF_VECTOR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// Undefined Exception Vector Pointer
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SHIFT)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_RANGE                   31:0
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_WOFFSET                 0x0
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_DEFAULT                 _MK_MASK_CONST(0xffff0004)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_INIT_ENUM                       -65532
+
+
+// Register EVP_COP_SWI_VECTOR_0  
+#define EVP_COP_SWI_VECTOR_0                    _MK_ADDR_CONST(0x208)
+#define EVP_COP_SWI_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_COP_SWI_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xffff0008)
+#define EVP_COP_SWI_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_SWI_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_COP_SWI_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_COP_SWI_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_SWI_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Software Interrupt Vector Pointer
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SHIFT)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_RANGE                       31:0
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_WOFFSET                     0x0
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_DEFAULT                     _MK_MASK_CONST(0xffff0008)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_INIT_ENUM                   -65528
+
+
+// Register EVP_COP_PREFETCH_ABORT_VECTOR_0  
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0                 _MK_ADDR_CONST(0x20c)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_WORD_COUNT                      0x1
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_RESET_VAL                       _MK_MASK_CONST(0xffff000c)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Code Prefetch ABORT Vector Pointer 
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_SHIFT                      _MK_SHIFT_CONST(0)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_FIELD                      (_MK_MASK_CONST(0xffffffff) << EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_SHIFT)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_RANGE                      31:0
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_WOFFSET                    0x0
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_DEFAULT                    _MK_MASK_CONST(0xffff000c)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_INIT_ENUM                  -65524
+
+
+// Register EVP_COP_DATA_ABORT_VECTOR_0  
+#define EVP_COP_DATA_ABORT_VECTOR_0                     _MK_ADDR_CONST(0x210)
+#define EVP_COP_DATA_ABORT_VECTOR_0_WORD_COUNT                  0x1
+#define EVP_COP_DATA_ABORT_VECTOR_0_RESET_VAL                   _MK_MASK_CONST(0xffff0010)
+#define EVP_COP_DATA_ABORT_VECTOR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_DATA_ABORT_VECTOR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_COP_DATA_ABORT_VECTOR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_COP_DATA_ABORT_VECTOR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_DATA_ABORT_VECTOR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Data ABORT Vector Pointer
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_SHIFT)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_RANGE                 31:0
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_WOFFSET                       0x0
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_DEFAULT                       _MK_MASK_CONST(0xffff0010)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_INIT_ENUM                     -65520
+
+
+// Register EVP_COP_RSVD_VECTOR_0  
+#define EVP_COP_RSVD_VECTOR_0                   _MK_ADDR_CONST(0x214)
+#define EVP_COP_RSVD_VECTOR_0_WORD_COUNT                        0x1
+#define EVP_COP_RSVD_VECTOR_0_RESET_VAL                         _MK_MASK_CONST(0xffff0014)
+#define EVP_COP_RSVD_VECTOR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RSVD_VECTOR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_COP_RSVD_VECTOR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_COP_RSVD_VECTOR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RSVD_VECTOR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Reserved Exception Vector Pointer
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SHIFT)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_RANGE                     31:0
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_WOFFSET                   0x0
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_DEFAULT                   _MK_MASK_CONST(0xffff0014)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_INIT_ENUM                 -65516
+
+
+// Register EVP_COP_IRQ_VECTOR_0  
+#define EVP_COP_IRQ_VECTOR_0                    _MK_ADDR_CONST(0x218)
+#define EVP_COP_IRQ_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_COP_IRQ_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xffff0018)
+#define EVP_COP_IRQ_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// IRQ Vector Pointer 
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SHIFT)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_RANGE                       31:0
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_WOFFSET                     0x0
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xffff0018)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_INIT_ENUM                   -65512
+
+
+// Register EVP_COP_FIQ_VECTOR_0  
+#define EVP_COP_FIQ_VECTOR_0                    _MK_ADDR_CONST(0x21c)
+#define EVP_COP_FIQ_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_COP_FIQ_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xffff001c)
+#define EVP_COP_FIQ_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// FIQ Vector Pointer 
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SHIFT)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_RANGE                       31:0
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_WOFFSET                     0x0
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xffff001c)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_INIT_ENUM                   -65508
+
+
+// Register EVP_COP_IRQ_STS_0  
+#define EVP_COP_IRQ_STS_0                       _MK_ADDR_CONST(0x220)
+#define EVP_COP_IRQ_STS_0_WORD_COUNT                    0x1
+#define EVP_COP_IRQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_COP_IRQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// FFS (from lsb) IRQ index  (0x80 indicates no active IRQ)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_IRQ_STS_0_COP_IRQ_STS_SHIFT)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_RANGE                     31:0
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_WOFFSET                   0x0
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_STS_0  
+#define EVP_COP_PRI_IRQ_STS_0                   _MK_ADDR_CONST(0x224)
+#define EVP_COP_PRI_IRQ_STS_0_WORD_COUNT                        0x1
+#define EVP_COP_PRI_IRQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Current highest priority active IRQ (0x80 indicates no active priority IRQ)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SHIFT)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_FIQ_STS_0  
+#define EVP_COP_FIQ_STS_0                       _MK_ADDR_CONST(0x228)
+#define EVP_COP_FIQ_STS_0_WORD_COUNT                    0x1
+#define EVP_COP_FIQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_COP_FIQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// FFS (from lsb) FIQ index (0x80 indicates no active FIQ)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_FIQ_STS_0_COP_FIQ_STS_SHIFT)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_RANGE                     31:0
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_WOFFSET                   0x0
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_STS_0  
+#define EVP_COP_PRI_FIQ_STS_0                   _MK_ADDR_CONST(0x22c)
+#define EVP_COP_PRI_FIQ_STS_0_WORD_COUNT                        0x1
+#define EVP_COP_PRI_FIQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Current highest priority active FIQ (0x80 indicates no active priority FIQ)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SHIFT)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_0_0  
+#define EVP_COP_PRI_IRQ_NUM_0_0                 _MK_ADDR_CONST(0x240)
+#define EVP_COP_PRI_IRQ_NUM_0_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_0_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_0_0  
+#define EVP_COP_PRI_IRQ_VEC_0_0                 _MK_ADDR_CONST(0x244)
+#define EVP_COP_PRI_IRQ_VEC_0_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_0_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_1_0  
+#define EVP_COP_PRI_IRQ_NUM_1_0                 _MK_ADDR_CONST(0x248)
+#define EVP_COP_PRI_IRQ_NUM_1_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_1_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_1_0  
+#define EVP_COP_PRI_IRQ_VEC_1_0                 _MK_ADDR_CONST(0x24c)
+#define EVP_COP_PRI_IRQ_VEC_1_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_1_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_2_0  
+#define EVP_COP_PRI_IRQ_NUM_2_0                 _MK_ADDR_CONST(0x250)
+#define EVP_COP_PRI_IRQ_NUM_2_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_2_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_2_0  
+#define EVP_COP_PRI_IRQ_VEC_2_0                 _MK_ADDR_CONST(0x254)
+#define EVP_COP_PRI_IRQ_VEC_2_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_2_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_3_0  
+#define EVP_COP_PRI_IRQ_NUM_3_0                 _MK_ADDR_CONST(0x258)
+#define EVP_COP_PRI_IRQ_NUM_3_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_3_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_3_0  
+#define EVP_COP_PRI_IRQ_VEC_3_0                 _MK_ADDR_CONST(0x25c)
+#define EVP_COP_PRI_IRQ_VEC_3_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_3_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_4_0  
+#define EVP_COP_PRI_IRQ_NUM_4_0                 _MK_ADDR_CONST(0x260)
+#define EVP_COP_PRI_IRQ_NUM_4_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_4_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_4_0  
+#define EVP_COP_PRI_IRQ_VEC_4_0                 _MK_ADDR_CONST(0x264)
+#define EVP_COP_PRI_IRQ_VEC_4_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_4_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_5_0  
+#define EVP_COP_PRI_IRQ_NUM_5_0                 _MK_ADDR_CONST(0x268)
+#define EVP_COP_PRI_IRQ_NUM_5_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_5_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_5_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_5_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_5_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_5_0  
+#define EVP_COP_PRI_IRQ_VEC_5_0                 _MK_ADDR_CONST(0x26c)
+#define EVP_COP_PRI_IRQ_VEC_5_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_5_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_5_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_5_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_5_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_6_0  
+#define EVP_COP_PRI_IRQ_NUM_6_0                 _MK_ADDR_CONST(0x270)
+#define EVP_COP_PRI_IRQ_NUM_6_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_6_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_6_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_6_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_6_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_6_0  
+#define EVP_COP_PRI_IRQ_VEC_6_0                 _MK_ADDR_CONST(0x274)
+#define EVP_COP_PRI_IRQ_VEC_6_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_6_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_6_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_6_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_6_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_7_0  
+#define EVP_COP_PRI_IRQ_NUM_7_0                 _MK_ADDR_CONST(0x278)
+#define EVP_COP_PRI_IRQ_NUM_7_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_7_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_7_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_7_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_7_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_7_0  
+#define EVP_COP_PRI_IRQ_VEC_7_0                 _MK_ADDR_CONST(0x27c)
+#define EVP_COP_PRI_IRQ_VEC_7_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_7_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_7_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_7_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_7_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_NUM_0_0  
+#define EVP_COP_PRI_FIQ_NUM_0_0                 _MK_ADDR_CONST(0x280)
+#define EVP_COP_PRI_FIQ_NUM_0_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_NUM_0_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT)
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_VEC_0_0  
+#define EVP_COP_PRI_FIQ_VEC_0_0                 _MK_ADDR_CONST(0x284)
+#define EVP_COP_PRI_FIQ_VEC_0_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_VEC_0_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT)
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_NUM_1_0  
+#define EVP_COP_PRI_FIQ_NUM_1_0                 _MK_ADDR_CONST(0x288)
+#define EVP_COP_PRI_FIQ_NUM_1_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_NUM_1_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT)
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_VEC_1_0  
+#define EVP_COP_PRI_FIQ_VEC_1_0                 _MK_ADDR_CONST(0x28c)
+#define EVP_COP_PRI_FIQ_VEC_1_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_VEC_1_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT)
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_NUM_2_0  
+#define EVP_COP_PRI_FIQ_NUM_2_0                 _MK_ADDR_CONST(0x290)
+#define EVP_COP_PRI_FIQ_NUM_2_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_NUM_2_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT)
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_VEC_2_0  
+#define EVP_COP_PRI_FIQ_VEC_2_0                 _MK_ADDR_CONST(0x294)
+#define EVP_COP_PRI_FIQ_VEC_2_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_VEC_2_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT)
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_NUM_3_0  
+#define EVP_COP_PRI_FIQ_NUM_3_0                 _MK_ADDR_CONST(0x298)
+#define EVP_COP_PRI_FIQ_NUM_3_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_NUM_3_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT)
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_VEC_3_0  
+#define EVP_COP_PRI_FIQ_VEC_3_0                 _MK_ADDR_CONST(0x29c)
+#define EVP_COP_PRI_FIQ_VEC_3_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_VEC_3_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT)
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_AREVP_REGS(_op_) \
+_op_(EVP_RESET_VECTOR_0) \
+_op_(EVP_UNDEF_VECTOR_0) \
+_op_(EVP_SWI_VECTOR_0) \
+_op_(EVP_PREFETCH_ABORT_VECTOR_0) \
+_op_(EVP_DATA_ABORT_VECTOR_0) \
+_op_(EVP_RSVD_VECTOR_0) \
+_op_(EVP_IRQ_VECTOR_0) \
+_op_(EVP_FIQ_VECTOR_0) \
+_op_(EVP_IRQ_STS_0) \
+_op_(EVP_PRI_IRQ_STS_0) \
+_op_(EVP_FIQ_STS_0) \
+_op_(EVP_PRI_FIQ_STS_0) \
+_op_(EVP_PRI_IRQ_NUM_0_0) \
+_op_(EVP_PRI_IRQ_VEC_0_0) \
+_op_(EVP_PRI_IRQ_NUM_1_0) \
+_op_(EVP_PRI_IRQ_VEC_1_0) \
+_op_(EVP_PRI_IRQ_NUM_2_0) \
+_op_(EVP_PRI_IRQ_VEC_2_0) \
+_op_(EVP_PRI_IRQ_NUM_3_0) \
+_op_(EVP_PRI_IRQ_VEC_3_0) \
+_op_(EVP_PRI_IRQ_NUM_4_0) \
+_op_(EVP_PRI_IRQ_VEC_4_0) \
+_op_(EVP_PRI_IRQ_NUM_5_0) \
+_op_(EVP_PRI_IRQ_VEC_5_0) \
+_op_(EVP_PRI_IRQ_NUM_6_0) \
+_op_(EVP_PRI_IRQ_VEC_6_0) \
+_op_(EVP_PRI_IRQ_NUM_7_0) \
+_op_(EVP_PRI_IRQ_VEC_7_0) \
+_op_(EVP_PRI_FIQ_NUM_0_0) \
+_op_(EVP_PRI_FIQ_VEC_0_0) \
+_op_(EVP_PRI_FIQ_NUM_1_0) \
+_op_(EVP_PRI_FIQ_VEC_1_0) \
+_op_(EVP_PRI_FIQ_NUM_2_0) \
+_op_(EVP_PRI_FIQ_VEC_2_0) \
+_op_(EVP_PRI_FIQ_NUM_3_0) \
+_op_(EVP_PRI_FIQ_VEC_3_0) \
+_op_(EVP_CPU_RESET_VECTOR_0) \
+_op_(EVP_CPU_UNDEF_VECTOR_0) \
+_op_(EVP_CPU_SWI_VECTOR_0) \
+_op_(EVP_CPU_PREFETCH_ABORT_VECTOR_0) \
+_op_(EVP_CPU_DATA_ABORT_VECTOR_0) \
+_op_(EVP_CPU_RSVD_VECTOR_0) \
+_op_(EVP_CPU_IRQ_VECTOR_0) \
+_op_(EVP_CPU_FIQ_VECTOR_0) \
+_op_(EVP_CPU_IRQ_STS_0) \
+_op_(EVP_CPU_PRI_IRQ_STS_0) \
+_op_(EVP_CPU_FIQ_STS_0) \
+_op_(EVP_CPU_PRI_FIQ_STS_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_0_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_0_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_1_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_1_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_2_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_2_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_3_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_3_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_4_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_4_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_5_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_5_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_6_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_6_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_7_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_7_0) \
+_op_(EVP_CPU_PRI_FIQ_NUM_0_0) \
+_op_(EVP_CPU_PRI_FIQ_VEC_0_0) \
+_op_(EVP_CPU_PRI_FIQ_NUM_1_0) \
+_op_(EVP_CPU_PRI_FIQ_VEC_1_0) \
+_op_(EVP_CPU_PRI_FIQ_NUM_2_0) \
+_op_(EVP_CPU_PRI_FIQ_VEC_2_0) \
+_op_(EVP_CPU_PRI_FIQ_NUM_3_0) \
+_op_(EVP_CPU_PRI_FIQ_VEC_3_0) \
+_op_(EVP_COP_RESET_VECTOR_0) \
+_op_(EVP_COP_UNDEF_VECTOR_0) \
+_op_(EVP_COP_SWI_VECTOR_0) \
+_op_(EVP_COP_PREFETCH_ABORT_VECTOR_0) \
+_op_(EVP_COP_DATA_ABORT_VECTOR_0) \
+_op_(EVP_COP_RSVD_VECTOR_0) \
+_op_(EVP_COP_IRQ_VECTOR_0) \
+_op_(EVP_COP_FIQ_VECTOR_0) \
+_op_(EVP_COP_IRQ_STS_0) \
+_op_(EVP_COP_PRI_IRQ_STS_0) \
+_op_(EVP_COP_FIQ_STS_0) \
+_op_(EVP_COP_PRI_FIQ_STS_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_0_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_0_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_1_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_1_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_2_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_2_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_3_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_3_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_4_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_4_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_5_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_5_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_6_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_6_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_7_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_7_0) \
+_op_(EVP_COP_PRI_FIQ_NUM_0_0) \
+_op_(EVP_COP_PRI_FIQ_VEC_0_0) \
+_op_(EVP_COP_PRI_FIQ_NUM_1_0) \
+_op_(EVP_COP_PRI_FIQ_VEC_1_0) \
+_op_(EVP_COP_PRI_FIQ_NUM_2_0) \
+_op_(EVP_COP_PRI_FIQ_VEC_2_0) \
+_op_(EVP_COP_PRI_FIQ_NUM_3_0) \
+_op_(EVP_COP_PRI_FIQ_VEC_3_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_EVP        0x00000000
+
+//
+// AREVP REGISTER BANKS
+//
+
+#define EVP0_FIRST_REG 0x0000 // EVP_RESET_VECTOR_0
+#define EVP0_LAST_REG 0x002c // EVP_PRI_FIQ_STS_0
+#define EVP1_FIRST_REG 0x0040 // EVP_PRI_IRQ_NUM_0_0
+#define EVP1_LAST_REG 0x009c // EVP_PRI_FIQ_VEC_3_0
+#define EVP2_FIRST_REG 0x0100 // EVP_CPU_RESET_VECTOR_0
+#define EVP2_LAST_REG 0x012c // EVP_CPU_PRI_FIQ_STS_0
+#define EVP3_FIRST_REG 0x0140 // EVP_CPU_PRI_IRQ_NUM_0_0
+#define EVP3_LAST_REG 0x019c // EVP_CPU_PRI_FIQ_VEC_3_0
+#define EVP4_FIRST_REG 0x0200 // EVP_COP_RESET_VECTOR_0
+#define EVP4_LAST_REG 0x022c // EVP_COP_PRI_FIQ_STS_0
+#define EVP5_FIRST_REG 0x0240 // EVP_COP_PRI_IRQ_NUM_0_0
+#define EVP5_LAST_REG 0x029c // EVP_COP_PRI_FIQ_VEC_3_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___AREVP_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arflow_ctlr.h b/arch/arm/mach-tegra/nv/include/ap15/arflow_ctlr.h
new file mode 100644
index 000000000000..e1ddb7e4fdbb
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arflow_ctlr.h
@@ -0,0 +1,836 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARFLOW_CTLR_H_INC_
+#define ___ARFLOW_CTLR_H_INC_
+
+// Register FLOW_CTLR_HALT_CPU_EVENTS_0  
+#define FLOW_CTLR_HALT_CPU_EVENTS_0                     _MK_ADDR_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_WORD_COUNT                  0x1
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// 7 = reserved 
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SHIFT                  _MK_SHIFT_CONST(29)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FIELD                  (_MK_MASK_CONST(0x7) << FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_RANGE                  31:29
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_NONE                 _MK_ENUM_CONST(0)    // // No flow control
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_RUN_AND_INT                  _MK_ENUM_CONST(1)    // // Keep running but generate interrupt when event conditions met
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_WAITEVENT                    _MK_ENUM_CONST(2)    // // Stop running until event conditions met
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_WAITEVENT_AND_INT                    _MK_ENUM_CONST(3)    // // Same as FLOW_MODE_STOP but generate an interrupt when resumed
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ                       _MK_ENUM_CONST(4)    // // Stop until an interrupt controller interrupt occurs
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ_AND_INT                       _MK_ENUM_CONST(5)    // // Same as FLOW_MODE_STOP_UNTIL_INT but generate another interrupt when resumed
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ                     _MK_ENUM_CONST(6)    // // Stop until event conditions met AND an interrupt controller interrupt occurs
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP                 _MK_ENUM_CONST(2)    // // DO NOT USE. LEGACY NAME WILL BE REMOVED
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_AND_INT                 _MK_ENUM_CONST(3)    // // DO NOT USE. LEGACY NAME WILL BE REMOVED
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT                       _MK_ENUM_CONST(4)    // // DO NOT USE. LEGACY NAME WILL BE REMOVED
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT_AND_INT                       _MK_ENUM_CONST(5)    // // DO NOT USE. LEGACY NAME WILL BE REMOVED
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_OR_INT                  _MK_ENUM_CONST(6)    // // DO NOT USE. LEGACY NAME WILL BE REMOVED
+
+
+// Resume on JTAG activity
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SHIFT                  _MK_SHIFT_CONST(28)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_RANGE                  28:28
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Resume on Nth SYSCLK cycle ticks. Modified by SW
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SHIFT                  _MK_SHIFT_CONST(27)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_RANGE                  27:27
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Resume on Nth X32K clock input ticks Modified by  SW
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SHIFT                  _MK_SHIFT_CONST(26)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_RANGE                  26:26
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Resume on Nth SEC clock ticks Modified by SW
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SHIFT                  _MK_SHIFT_CONST(25)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_RANGE                  25:25
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Resume on Nth mSEC clock ticks Modified by SW
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SHIFT                  _MK_SHIFT_CONST(24)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_RANGE                  24:24
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Resume on Nth second RTC clock ticks Modified by  SW
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SHIFT                   _MK_SHIFT_CONST(23)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_RANGE                   23:23
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Resume on Nth XIO.RDY Ext. IO Ready events Read-only,  status changed by HW
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SHIFT                 _MK_SHIFT_CONST(22)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_RANGE                 22:22
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth SMP.31 Semaphore set events 
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SHIFT                 _MK_SHIFT_CONST(21)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_RANGE                 21:21
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth SMP.30 Semaphore set events
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SHIFT                 _MK_SHIFT_CONST(20)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_RANGE                 20:20
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth XRQ.D External Trigger events
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SHIFT                 _MK_SHIFT_CONST(19)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_RANGE                 19:19
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth XRQ.C External Trigger events
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SHIFT                 _MK_SHIFT_CONST(18)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_RANGE                 18:18
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth XRQ.B External Trigger events
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SHIFT                 _MK_SHIFT_CONST(17)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_RANGE                 17:17
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth XRQ.A External Trigger events
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SHIFT                 _MK_SHIFT_CONST(16)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_RANGE                 16:16
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth OBE Outbox Empty Events
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SHIFT                   _MK_SHIFT_CONST(15)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_RANGE                   15:15
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Resume on Nth OBF Outbox Full Events
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SHIFT                   _MK_SHIFT_CONST(14)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_RANGE                   14:14
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Resume on Nth IBE Inbox Empty Events
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SHIFT                   _MK_SHIFT_CONST(13)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_RANGE                   13:13
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Resume on Nth IBE Inbox Empty Events
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SHIFT                   _MK_SHIFT_CONST(12)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_RANGE                   12:12
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Resume on IRQ.1 COP IRQ Valid
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SHIFT                 _MK_SHIFT_CONST(11)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_RANGE                 11:11
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on IRQ.0 CPU IRQ Valid
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SHIFT                 _MK_SHIFT_CONST(10)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_RANGE                 10:10
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on FIQ.1 Valid COP FIQ
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SHIFT                 _MK_SHIFT_CONST(9)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_RANGE                 9:9
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on FIQ.0 Valid CPU FIQ
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SHIFT                 _MK_SHIFT_CONST(8)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_RANGE                 8:8
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Note: If more than one event is enabled, the event counter
+// will decrement based on an or condition of enabled events. 
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_FIELD                  (_MK_MASK_CONST(0xff) << FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_RANGE                  7:0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FLOW_CTLR_HALT_COP_EVENTS_0  
+#define FLOW_CTLR_HALT_COP_EVENTS_0                     _MK_ADDR_CONST(0x4)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_WORD_COUNT                  0x1
+#define FLOW_CTLR_HALT_COP_EVENTS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// 7 = reserved 
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SHIFT                  _MK_SHIFT_CONST(29)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FIELD                  (_MK_MASK_CONST(0x7) << FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_RANGE                  31:29
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_NONE                 _MK_ENUM_CONST(0)    // // No flow control
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_RUN_AND_INT                  _MK_ENUM_CONST(1)    // // Keep running but generate interrupt when event conditions met
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_WAITEVENT                    _MK_ENUM_CONST(2)    // // Stop running until event conditions met
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_WAITEVENT_AND_INT                    _MK_ENUM_CONST(3)    // // Same as FLOW_MODE_STOP but generate an interrupt when resumed
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ                       _MK_ENUM_CONST(4)    // // Stop until an interrupt controller interrupt occurs
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ_AND_INT                       _MK_ENUM_CONST(5)    // // Same as FLOW_MODE_STOP_UNTIL_INT but generate another interrupt when resumed
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ                     _MK_ENUM_CONST(6)    // // Stop until event conditions met AND an interrupt controller interrupt occurs
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP                 _MK_ENUM_CONST(2)    // // DO NOT USE. LEGACY NAME WILL BE REMOVED
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_AND_INT                 _MK_ENUM_CONST(3)    // // DO NOT USE. LEGACY NAME WILL BE REMOVED
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT                       _MK_ENUM_CONST(4)    // // DO NOT USE. LEGACY NAME WILL BE REMOVED
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT_AND_INT                       _MK_ENUM_CONST(5)    // // DO NOT USE. LEGACY NAME WILL BE REMOVED
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_OR_INT                  _MK_ENUM_CONST(6)    // // DO NOT USE. LEGACY NAME WILL BE REMOVED
+
+
+// Resume on JTAG activity
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SHIFT                  _MK_SHIFT_CONST(28)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_RANGE                  28:28
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Resume on Nth SYSCLK cycle ticks. Modified by SW
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SHIFT                  _MK_SHIFT_CONST(27)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_RANGE                  27:27
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Resume on Nth X32K clock input ticks Modified by  SW
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SHIFT                  _MK_SHIFT_CONST(26)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_RANGE                  26:26
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Resume on Nth SEC clock ticks Modified by SW
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SHIFT                  _MK_SHIFT_CONST(25)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_RANGE                  25:25
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Resume on Nth mSEC clock ticks Modified by SW
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SHIFT                  _MK_SHIFT_CONST(24)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_RANGE                  24:24
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Resume on Nth second RTC clock ticks Modified by  SW
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SHIFT                   _MK_SHIFT_CONST(23)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_RANGE                   23:23
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Resume on Nth XIO.RDY Ext. IO Ready events Read-only,  status changed by HW
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SHIFT                 _MK_SHIFT_CONST(22)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_RANGE                 22:22
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth SMP.31 Semaphore set events 
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SHIFT                 _MK_SHIFT_CONST(21)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_RANGE                 21:21
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth SMP.30 Semaphore set events
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SHIFT                 _MK_SHIFT_CONST(20)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_RANGE                 20:20
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth XRQ.D External Trigger events
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SHIFT                 _MK_SHIFT_CONST(19)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_RANGE                 19:19
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth XRQ.C External Trigger events
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SHIFT                 _MK_SHIFT_CONST(18)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_RANGE                 18:18
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth XRQ.B External Trigger events
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SHIFT                 _MK_SHIFT_CONST(17)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_RANGE                 17:17
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth XRQ.A External Trigger events
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SHIFT                 _MK_SHIFT_CONST(16)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_RANGE                 16:16
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on Nth OBE Outbox Empty Events
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SHIFT                   _MK_SHIFT_CONST(15)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_RANGE                   15:15
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Resume on Nth OBF Outbox Full Events
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SHIFT                   _MK_SHIFT_CONST(14)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_RANGE                   14:14
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Resume on Nth IBE Inbox Empty Events
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SHIFT                   _MK_SHIFT_CONST(13)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_RANGE                   13:13
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Resume on Nth IBE Inbox Empty Events
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SHIFT                   _MK_SHIFT_CONST(12)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_RANGE                   12:12
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Resume on IRQ.1 COP IRQ Valid
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SHIFT                 _MK_SHIFT_CONST(11)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_RANGE                 11:11
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on IRQ.0 CPU IRQ Valid
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SHIFT                 _MK_SHIFT_CONST(10)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_RANGE                 10:10
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on FIQ.1 Valid COP FIQ
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SHIFT                 _MK_SHIFT_CONST(9)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_RANGE                 9:9
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Resume on FIQ.0 Valid CPU FIQ
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SHIFT                 _MK_SHIFT_CONST(8)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_RANGE                 8:8
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Note: If more than one event is enabled, the event counter
+// will decrement based on an or condition of enabled events. 
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_FIELD                  (_MK_MASK_CONST(0xff) << FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_RANGE                  7:0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FLOW_CTLR_CPU_CSR_0  
+#define FLOW_CTLR_CPU_CSR_0                     _MK_ADDR_CONST(0x8)
+#define FLOW_CTLR_CPU_CSR_0_WORD_COUNT                  0x1
+#define FLOW_CTLR_CPU_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_CPU_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_CPU_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0x8001)
+// Reserved 
+#define FLOW_CTLR_CPU_CSR_0_RSVD_3128_SHIFT                     _MK_SHIFT_CONST(28)
+#define FLOW_CTLR_CPU_CSR_0_RSVD_3128_FIELD                     (_MK_MASK_CONST(0xf) << FLOW_CTLR_CPU_CSR_0_RSVD_3128_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_RSVD_3128_RANGE                     31:28
+#define FLOW_CTLR_CPU_CSR_0_RSVD_3128_WOFFSET                   0x0
+#define FLOW_CTLR_CPU_CSR_0_RSVD_3128_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_RSVD_3128_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define FLOW_CTLR_CPU_CSR_0_RSVD_3128_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_RSVD_3128_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// PowerGate State Machine
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_SHIFT                     _MK_SHIFT_CONST(24)
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_FIELD                     (_MK_MASK_CONST(0xf) << FLOW_CTLR_CPU_CSR_0_PWR_STATE_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_RANGE                     27:24
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_WOFFSET                   0x0
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CPU is waiting until event 
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SHIFT                    _MK_SHIFT_CONST(23)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_FIELD                    (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_RANGE                    23:23
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_WOFFSET                  0x0
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CPU is halted 
+#define FLOW_CTLR_CPU_CSR_0_HALT_SHIFT                  _MK_SHIFT_CONST(22)
+#define FLOW_CTLR_CPU_CSR_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_HALT_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_HALT_RANGE                  22:22
+#define FLOW_CTLR_CPU_CSR_0_HALT_WOFFSET                        0x0
+#define FLOW_CTLR_CPU_CSR_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// pmc2flow_ack
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_SHIFT                       _MK_SHIFT_CONST(21)
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_FIELD                       (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_P2F_ACK_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_RANGE                       21:21
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_WOFFSET                     0x0
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// flow2pmc_pwrup
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SHIFT                     _MK_SHIFT_CONST(20)
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_FIELD                     (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_RANGE                     20:20
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_WOFFSET                   0x0
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// flow2pmc_req valid
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_SHIFT                       _MK_SHIFT_CONST(19)
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_FIELD                       (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_F2P_REQ_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_RANGE                       19:19
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_WOFFSET                     0x0
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// TRUE when CPU transactions are flushed 
+#define FLOW_CTLR_CPU_CSR_0_FLUSH_DONE_SHIFT                    _MK_SHIFT_CONST(18)
+#define FLOW_CTLR_CPU_CSR_0_FLUSH_DONE_FIELD                    (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_FLUSH_DONE_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_FLUSH_DONE_RANGE                    18:18
+#define FLOW_CTLR_CPU_CSR_0_FLUSH_DONE_WOFFSET                  0x0
+#define FLOW_CTLR_CPU_CSR_0_FLUSH_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_FLUSH_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_FLUSH_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_FLUSH_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// TRUE when Requesting Reset of MPCore 
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SHIFT                        _MK_SHIFT_CONST(17)
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_RANGE                        17:17
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_WOFFSET                      0x0
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// TRUE when CPU PowerGated OFF by Flow Controller 
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SHIFT                   _MK_SHIFT_CONST(16)
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_RANGE                   16:16
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_WOFFSET                 0x0
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// TRUE when Interrupt is Active -- Write-1-to-Clear
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SHIFT                     _MK_SHIFT_CONST(15)
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_FIELD                     (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_RANGE                     15:15
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_WOFFSET                   0x0
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Reserved
+#define FLOW_CTLR_CPU_CSR_0_RSVD_1401_SHIFT                     _MK_SHIFT_CONST(1)
+#define FLOW_CTLR_CPU_CSR_0_RSVD_1401_FIELD                     (_MK_MASK_CONST(0x3fff) << FLOW_CTLR_CPU_CSR_0_RSVD_1401_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_RSVD_1401_RANGE                     14:1
+#define FLOW_CTLR_CPU_CSR_0_RSVD_1401_WOFFSET                   0x0
+#define FLOW_CTLR_CPU_CSR_0_RSVD_1401_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_RSVD_1401_DEFAULT_MASK                      _MK_MASK_CONST(0x3fff)
+#define FLOW_CTLR_CPU_CSR_0_RSVD_1401_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_RSVD_1401_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// PowerGate Enable - Halt or Event-wait causes CPU PowerGating
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_ENABLE_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_RANGE                        0:0
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_WOFFSET                      0x0
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FLOW_CTLR_COP_CSR_0  
+#define FLOW_CTLR_COP_CSR_0                     _MK_ADDR_CONST(0xc)
+#define FLOW_CTLR_COP_CSR_0_WORD_COUNT                  0x1
+#define FLOW_CTLR_COP_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_COP_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_COP_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0x8000)
+// Reserved 
+#define FLOW_CTLR_COP_CSR_0_RSVD_3116_SHIFT                     _MK_SHIFT_CONST(16)
+#define FLOW_CTLR_COP_CSR_0_RSVD_3116_FIELD                     (_MK_MASK_CONST(0xffff) << FLOW_CTLR_COP_CSR_0_RSVD_3116_SHIFT)
+#define FLOW_CTLR_COP_CSR_0_RSVD_3116_RANGE                     31:16
+#define FLOW_CTLR_COP_CSR_0_RSVD_3116_WOFFSET                   0x0
+#define FLOW_CTLR_COP_CSR_0_RSVD_3116_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_RSVD_3116_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define FLOW_CTLR_COP_CSR_0_RSVD_3116_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_RSVD_3116_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// TRUE when Interrupt is Active -- Write-1-to-Clear
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_SHIFT                     _MK_SHIFT_CONST(15)
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_FIELD                     (_MK_MASK_CONST(0x1) << FLOW_CTLR_COP_CSR_0_INTR_FLAG_SHIFT)
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_RANGE                     15:15
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_WOFFSET                   0x0
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Reserved
+#define FLOW_CTLR_COP_CSR_0_RSVD_1400_SHIFT                     _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_COP_CSR_0_RSVD_1400_FIELD                     (_MK_MASK_CONST(0x7fff) << FLOW_CTLR_COP_CSR_0_RSVD_1400_SHIFT)
+#define FLOW_CTLR_COP_CSR_0_RSVD_1400_RANGE                     14:0
+#define FLOW_CTLR_COP_CSR_0_RSVD_1400_WOFFSET                   0x0
+#define FLOW_CTLR_COP_CSR_0_RSVD_1400_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_RSVD_1400_DEFAULT_MASK                      _MK_MASK_CONST(0x7fff)
+#define FLOW_CTLR_COP_CSR_0_RSVD_1400_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_RSVD_1400_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FLOW_CTLR_XRQ_EVENTS_0  
+#define FLOW_CTLR_XRQ_EVENTS_0                  _MK_ADDR_CONST(0x10)
+#define FLOW_CTLR_XRQ_EVENTS_0_WORD_COUNT                       0x1
+#define FLOW_CTLR_XRQ_EVENTS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_XRQ_EVENTS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_XRQ_EVENTS_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// Setting a bit to 1 enables event triggering for  the corresponding bit in GPIO port D. The assertion level is determined by  GPIO_INT.LVL.D. If more than one XRQ.D bit is set, the events are ORed  together. The resultant event is enabled by setting the XRQ.D bit in the  HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SHIFT                      _MK_SHIFT_CONST(24)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_FIELD                      (_MK_MASK_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SHIFT)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_RANGE                      31:24
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_WOFFSET                    0x0
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Setting a bit to 1 enables event triggering for  the corresponding bit in GPIO port C. The assertion level is determined by  GPIO_INT.LVL.C. If more than one XRQ.C bit is set, the events are ORed  together. The resultant event is enabled by setting the XRQ.C bit in the  HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SHIFT                      _MK_SHIFT_CONST(16)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_FIELD                      (_MK_MASK_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SHIFT)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_RANGE                      23:16
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_WOFFSET                    0x0
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Setting a bit to 1 enables event triggering for  the corresponding bit in GPIO port B. The assertion level is determined by  GPIO_INT.LVL.B. If more than one XRQ.B bit is set, the events are ORed  together. The resultant event is enabled by setting the XRQ.B bit in the  HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SHIFT                      _MK_SHIFT_CONST(8)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_FIELD                      (_MK_MASK_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SHIFT)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_RANGE                      15:8
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_WOFFSET                    0x0
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Setting a bit to 1 enables event triggering for  the corresponding bit in GPIO port A. The assertion level is determined by  GPIO_INT.LVL.A. If more than one XRQ.A bit is set, the events are ORed  together. The resultant event is enabled by setting the XRQ.A bit in the  HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_FIELD                      (_MK_MASK_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SHIFT)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_RANGE                      7:0
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_WOFFSET                    0x0
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARFLOW_CTLR_REGS(_op_) \
+_op_(FLOW_CTLR_HALT_CPU_EVENTS_0) \
+_op_(FLOW_CTLR_HALT_COP_EVENTS_0) \
+_op_(FLOW_CTLR_CPU_CSR_0) \
+_op_(FLOW_CTLR_COP_CSR_0) \
+_op_(FLOW_CTLR_XRQ_EVENTS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_FLOW_CTLR  0x00000000
+
+//
+// ARFLOW_CTLR REGISTER BANKS
+//
+
+#define FLOW_CTLR0_FIRST_REG 0x0000 // FLOW_CTLR_HALT_CPU_EVENTS_0
+#define FLOW_CTLR0_LAST_REG 0x0010 // FLOW_CTLR_XRQ_EVENTS_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARFLOW_CTLR_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arfuse.h b/arch/arm/mach-tegra/nv/include/ap15/arfuse.h
new file mode 100644
index 000000000000..67f8e5c142a6
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arfuse.h
@@ -0,0 +1,3997 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARFUSE_H_INC_
+#define ___ARFUSE_H_INC_
+
+// Register FUSE_FUSECTRL_0  
+#define FUSE_FUSECTRL_0                 _MK_ADDR_CONST(0x0)
+#define FUSE_FUSECTRL_0_WORD_COUNT                      0x1
+#define FUSE_FUSECTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_RESET_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_READ_MASK                       _MK_MASK_CONST(0x10f0003)
+#define FUSE_FUSECTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_FIELD                      (_MK_MASK_CONST(0x3) << FUSE_FUSECTRL_0_FUSECTRL_CMD_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_RANGE                      1:0
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_WOFFSET                    0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_INIT_ENUM                  IDLE
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_IDLE                       _MK_ENUM_CONST(0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_READ                       _MK_ENUM_CONST(1)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_WRITE                      _MK_ENUM_CONST(2)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_VERIFY                     _MK_ENUM_CONST(3)
+
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SHIFT                    _MK_SHIFT_CONST(16)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_FUSECTRL_0_FUSECTRL_STATE_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_RANGE                    19:16
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_WOFFSET                  0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_SHIFT                   _MK_SHIFT_CONST(24)
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSECTRL_0_FUSECTRL_VERIFY_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_RANGE                   24:24
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_WOFFSET                 0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_VERIFY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME1_0  
+#define FUSE_FUSETIME1_0                        _MK_ADDR_CONST(0x4)
+#define FUSE_FUSETIME1_0_WORD_COUNT                     0x1
+#define FUSE_FUSETIME1_0_RESET_VAL                      _MK_MASK_CONST(0x11100000)
+#define FUSE_FUSETIME1_0_RESET_MASK                     _MK_MASK_CONST(0xfff00000)
+#define FUSE_FUSETIME1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME1_0_READ_MASK                      _MK_MASK_CONST(0xfff00000)
+#define FUSE_FUSETIME1_0_WRITE_MASK                     _MK_MASK_CONST(0xfff00000)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_FIELD                      (_MK_MASK_CONST(0xf) << FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_SHIFT)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_RANGE                      23:20
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_WOFFSET                    0x0
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_SHIFT                    _MK_SHIFT_CONST(24)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_SHIFT)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_RANGE                    27:24
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_WOFFSET                  0x0
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME1_0_FUSETIME1_TSU_FUSEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_SHIFT)
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_RANGE                    31:28
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_WOFFSET                  0x0
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME1_0_FUSETIME1_THOLD_FUSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME2_0  
+#define FUSE_FUSETIME2_0                        _MK_ADDR_CONST(0x8)
+#define FUSE_FUSETIME2_0_WORD_COUNT                     0x1
+#define FUSE_FUSETIME2_0_RESET_VAL                      _MK_MASK_CONST(0x300001a)
+#define FUSE_FUSETIME2_0_RESET_MASK                     _MK_MASK_CONST(0xff0fffff)
+#define FUSE_FUSETIME2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME2_0_READ_MASK                      _MK_MASK_CONST(0xff0fffff)
+#define FUSE_FUSETIME2_0_WRITE_MASK                     _MK_MASK_CONST(0xff0fffff)
+// Calculation based on 1us program time and 38.4615 ns fuse_clk period.
+// Unfortunately the 1us program time is wrong, the real value is 5us.
+// So the init value is wrong and must be multiplied by 5 to obtain the correct value:
+//    init=0x00000082
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_FIELD                       (_MK_MASK_CONST(0xfffff) << FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_SHIFT)
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_RANGE                       19:0
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_WOFFSET                     0x0
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_DEFAULT                     _MK_MASK_CONST(0x1a)
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME2_0_FUSETIME2_TPROGRAM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_SHIFT                 _MK_SHIFT_CONST(24)
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_FIELD                 (_MK_MASK_CONST(0xff) << FUSE_FUSETIME2_0_FUSETIME2_TSENSE_SHIFT)
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_RANGE                 31:24
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_WOFFSET                       0x0
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_DEFAULT                       _MK_MASK_CONST(0x3)
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME2_0_FUSETIME2_TSENSE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA0_0  
+#define FUSE_FUSEDATA0_0                        _MK_ADDR_CONST(0xc)
+#define FUSE_FUSEDATA0_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA0_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA0_0_FUSEDATA0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_RANGE                        31:0
+#define FUSE_FUSEDATA0_0_FUSEDATA0_WOFFSET                      0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_RANGE                      0:0
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_ENABLE__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_RANGE                     1:1
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_MASTER_DISABLE__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(2)
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_RANGE                     2:2
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_BYPASS__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(3)
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_RANGE                        3:3
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_RESERVE_BIT__PRI_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(4)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_RANGE                    4:4
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PRODUCTION_MODE__PRI_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(5)
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_RANGE                        5:5
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(6)
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_RANGE                   13:6
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_SKU_INFO__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(14)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_RANGE                      15:14
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_PROCESS_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x3ff) << FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_RANGE                   25:16
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3ff)
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_IO_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(26)
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_RANGE                      31:26
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA0_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA1_0  
+#define FUSE_FUSEDATA1_0                        _MK_ADDR_CONST(0x10)
+#define FUSE_FUSEDATA1_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA1_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA1_0_FUSEDATA1_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_RANGE                        31:0
+#define FUSE_FUSEDATA1_0_FUSEDATA1_WOFFSET                      0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_FIELD                      (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_RANGE                      1:0
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_WOFFSET                    0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(2)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_RANGE                     9:2
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(10)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_RANGE                     17:10
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(18)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_RANGE                     24:18
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(25)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_RANGE                     31:25
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA1_0_FUSEDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA2_0  
+#define FUSE_FUSEDATA2_0                        _MK_ADDR_CONST(0x14)
+#define FUSE_FUSEDATA2_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA2_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA2_0_FUSEDATA2_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_RANGE                        31:0
+#define FUSE_FUSEDATA2_0_FUSEDATA2_WOFFSET                      0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_RANGE                     6:0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(7)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_RANGE                     13:7
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(14)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_RANGE                     20:14
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(21)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_RANGE                     27:21
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(28)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0xf) << FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_RANGE                     31:28
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA2_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA3_0  
+#define FUSE_FUSEDATA3_0                        _MK_ADDR_CONST(0x18)
+#define FUSE_FUSEDATA3_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA3_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA3_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA3_0_FUSEDATA3_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_RANGE                        31:0
+#define FUSE_FUSEDATA3_0_FUSEDATA3_WOFFSET                      0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_FIELD                     (_MK_MASK_CONST(0x7) << FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_RANGE                     2:0
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_WOFFSET                   0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(3)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_RANGE                     9:3
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(10)
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_RANGE                 10:10
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_FA__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(11)
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_FIELD                        (_MK_MASK_CONST(0xf) << FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_RANGE                        14:11
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(15)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_RANGE                   20:15
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(21)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_RANGE                   26:21
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(27)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1f) << FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_RANGE                   31:27
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA3_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA4_0  
+#define FUSE_FUSEDATA4_0                        _MK_ADDR_CONST(0x1c)
+#define FUSE_FUSEDATA4_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA4_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA4_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA4_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA4_0_FUSEDATA4_SHIFT)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_RANGE                        31:0
+#define FUSE_FUSEDATA4_0_FUSEDATA4_WOFFSET                      0x0
+#define FUSE_FUSEDATA4_0_FUSEDATA4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_RANGE                   0:0
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(1)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_RANGE                   6:1
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(7)
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_RANGE                      7:7
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_SECURITY_MODE__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffffff) << FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_RANGE                       31:8
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA4_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA5_0  
+#define FUSE_FUSEDATA5_0                        _MK_ADDR_CONST(0x20)
+#define FUSE_FUSEDATA5_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA5_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA5_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA5_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA5_0_FUSEDATA5_SHIFT)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_RANGE                        31:0
+#define FUSE_FUSEDATA5_0_FUSEDATA5_WOFFSET                      0x0
+#define FUSE_FUSEDATA5_0_FUSEDATA5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_RANGE                       7:0
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY0__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffffff) << FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_RANGE                       31:8
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA5_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA6_0  
+#define FUSE_FUSEDATA6_0                        _MK_ADDR_CONST(0x24)
+#define FUSE_FUSEDATA6_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA6_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA6_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA6_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA6_0_FUSEDATA6_SHIFT)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_RANGE                        31:0
+#define FUSE_FUSEDATA6_0_FUSEDATA6_WOFFSET                      0x0
+#define FUSE_FUSEDATA6_0_FUSEDATA6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_RANGE                       7:0
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY1__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffffff) << FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_RANGE                       31:8
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA6_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA7_0  
+#define FUSE_FUSEDATA7_0                        _MK_ADDR_CONST(0x28)
+#define FUSE_FUSEDATA7_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA7_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA7_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA7_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA7_0_FUSEDATA7_SHIFT)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_RANGE                        31:0
+#define FUSE_FUSEDATA7_0_FUSEDATA7_WOFFSET                      0x0
+#define FUSE_FUSEDATA7_0_FUSEDATA7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_RANGE                       7:0
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY2__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffffff) << FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_RANGE                       31:8
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA7_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA8_0  
+#define FUSE_FUSEDATA8_0                        _MK_ADDR_CONST(0x2c)
+#define FUSE_FUSEDATA8_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA8_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA8_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA8_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA8_0_FUSEDATA8_SHIFT)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_RANGE                        31:0
+#define FUSE_FUSEDATA8_0_FUSEDATA8_WOFFSET                      0x0
+#define FUSE_FUSEDATA8_0_FUSEDATA8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_RANGE                       7:0
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY3__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffffff) << FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_RANGE                       31:8
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA8_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA9_0  
+#define FUSE_FUSEDATA9_0                        _MK_ADDR_CONST(0x30)
+#define FUSE_FUSEDATA9_0_WORD_COUNT                     0x1
+#define FUSE_FUSEDATA9_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA9_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA9_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA9_0_FUSEDATA9_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_RANGE                        31:0
+#define FUSE_FUSEDATA9_0_FUSEDATA9_WOFFSET                      0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(24)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_RANGE                      24:24
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_ENABLE__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(25)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_RANGE                     25:25
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_MASTER_DISABLE__RED_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(26)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_RANGE                     26:26
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BYPASS__RED_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(27)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_RANGE                        27:27
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVE_BIT__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(28)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_RANGE                    28:28
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRODUCTION_MODE__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(29)
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_RANGE                        29:29
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(30)
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_RANGE                   31:30
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_SKU_INFO__RED_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_RANGE                       7:0
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_PRIVATE_KEY4__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_RANGE                       8:8
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(9)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_RANGE                   15:9
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(16)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_FIELD                        (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_RANGE                        23:16
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA9_0_FUSEDATA_RESERVED_SW__PRI_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA10_0  
+#define FUSE_FUSEDATA10_0                       _MK_ADDR_CONST(0x34)
+#define FUSE_FUSEDATA10_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA10_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA10_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA10_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA10_0_FUSEDATA10_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_RANGE                      31:0
+#define FUSE_FUSEDATA10_0_FUSEDATA10_WOFFSET                    0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA10_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_RANGE                  5:0
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_WOFFSET                        0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_SKU_INFO__RED_ALIAS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(6)
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_RANGE                     7:6
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_PROCESS_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3ff) << FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_RANGE                  17:8
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_IO_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(18)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_FIELD                     (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_RANGE                     25:18
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_CRT_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(26)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_RANGE                    31:26
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA10_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA11_0  
+#define FUSE_FUSEDATA11_0                       _MK_ADDR_CONST(0x38)
+#define FUSE_FUSEDATA11_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA11_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA11_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA11_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA11_0_FUSEDATA11_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_RANGE                      31:0
+#define FUSE_FUSEDATA11_0_FUSEDATA11_WOFFSET                    0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA11_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_FIELD                    (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_RANGE                    1:0
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(2)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_RANGE                    9:2
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(10)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_RANGE                    16:10
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_0__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(17)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_RANGE                    23:17
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_1__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(24)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_RANGE                    30:24
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_2__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(31)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_RANGE                    31:31
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA11_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA12_0  
+#define FUSE_FUSEDATA12_0                       _MK_ADDR_CONST(0x3c)
+#define FUSE_FUSEDATA12_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA12_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA12_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA12_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA12_0_FUSEDATA12_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_RANGE                      31:0
+#define FUSE_FUSEDATA12_0_FUSEDATA12_WOFFSET                    0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA12_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_FIELD                    (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_RANGE                    5:0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_WOFFSET                  0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM0_3__RED_ALIAS_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(6)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_RANGE                    12:6
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_0__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(13)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_RANGE                    19:13
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_1__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(20)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_RANGE                    26:20
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_2__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(27)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1f) << FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_RANGE                    31:27
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA12_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA13_0  
+#define FUSE_FUSEDATA13_0                       _MK_ADDR_CONST(0x40)
+#define FUSE_FUSEDATA13_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA13_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA13_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA13_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA13_0_FUSEDATA13_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_RANGE                      31:0
+#define FUSE_FUSEDATA13_0_FUSEDATA13_WOFFSET                    0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA13_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_FIELD                    (_MK_MASK_CONST(0x3) << FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_RANGE                    1:0
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_WOFFSET                  0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_CMC_DATARAM1_3__RED_ALIAS_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(2)
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_RANGE                        2:2
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_FA__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xf) << FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_RANGE                       6:3
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(7)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_RANGE                  12:7
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(13)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_RANGE                  18:13
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(19)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_RANGE                  24:19
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(25)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_RANGE                  30:25
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(31)
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_RANGE                     31:31
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA13_0_FUSEDATA_SECURITY_MODE__RED_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA14_0  
+#define FUSE_FUSEDATA14_0                       _MK_ADDR_CONST(0x44)
+#define FUSE_FUSEDATA14_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA14_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA14_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA14_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA14_0_FUSEDATA14_SHIFT)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_RANGE                      31:0
+#define FUSE_FUSEDATA14_0_FUSEDATA14_WOFFSET                    0x0
+#define FUSE_FUSEDATA14_0_FUSEDATA14_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_FUSEDATA14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_RANGE                      31:0
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA14_0_FUSEDATA_PRIVATE_KEY0__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA15_0  
+#define FUSE_FUSEDATA15_0                       _MK_ADDR_CONST(0x48)
+#define FUSE_FUSEDATA15_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA15_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA15_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA15_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA15_0_FUSEDATA15_SHIFT)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_RANGE                      31:0
+#define FUSE_FUSEDATA15_0_FUSEDATA15_WOFFSET                    0x0
+#define FUSE_FUSEDATA15_0_FUSEDATA15_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_FUSEDATA15_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_RANGE                      31:0
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA15_0_FUSEDATA_PRIVATE_KEY1__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA16_0  
+#define FUSE_FUSEDATA16_0                       _MK_ADDR_CONST(0x4c)
+#define FUSE_FUSEDATA16_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA16_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA16_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA16_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA16_0_FUSEDATA16_SHIFT)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_RANGE                      31:0
+#define FUSE_FUSEDATA16_0_FUSEDATA16_WOFFSET                    0x0
+#define FUSE_FUSEDATA16_0_FUSEDATA16_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_FUSEDATA16_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_RANGE                      31:0
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA16_0_FUSEDATA_PRIVATE_KEY2__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA17_0  
+#define FUSE_FUSEDATA17_0                       _MK_ADDR_CONST(0x50)
+#define FUSE_FUSEDATA17_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA17_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA17_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA17_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA17_0_FUSEDATA17_SHIFT)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_RANGE                      31:0
+#define FUSE_FUSEDATA17_0_FUSEDATA17_WOFFSET                    0x0
+#define FUSE_FUSEDATA17_0_FUSEDATA17_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_FUSEDATA17_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_RANGE                      31:0
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA17_0_FUSEDATA_PRIVATE_KEY3__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA18_0  
+#define FUSE_FUSEDATA18_0                       _MK_ADDR_CONST(0x54)
+#define FUSE_FUSEDATA18_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA18_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA18_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA18_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA18_0_FUSEDATA18_SHIFT)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_RANGE                      31:0
+#define FUSE_FUSEDATA18_0_FUSEDATA18_WOFFSET                    0x0
+#define FUSE_FUSEDATA18_0_FUSEDATA18_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_FUSEDATA18_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_RANGE                      31:0
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA18_0_FUSEDATA_PRIVATE_KEY4__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA19_0  
+#define FUSE_FUSEDATA19_0                       _MK_ADDR_CONST(0x58)
+#define FUSE_FUSEDATA19_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA19_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA19_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA19_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA19_0_FUSEDATA19_SHIFT)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_RANGE                      31:0
+#define FUSE_FUSEDATA19_0_FUSEDATA19_WOFFSET                    0x0
+#define FUSE_FUSEDATA19_0_FUSEDATA19_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA19_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_RANGE                      0:0
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_ARM_JTAG_DIS__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(1)
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x7f) << FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_RANGE                  7:1
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_RANGE                       15:8
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_RESERVED_SW__RED_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffff) << FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_RANGE                   31:16
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA19_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA20_0  
+#define FUSE_FUSEDATA20_0                       _MK_ADDR_CONST(0x5c)
+#define FUSE_FUSEDATA20_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA20_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA20_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA20_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA20_0_FUSEDATA20_SHIFT)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_RANGE                      31:0
+#define FUSE_FUSEDATA20_0_FUSEDATA20_WOFFSET                    0x0
+#define FUSE_FUSEDATA20_0_FUSEDATA20_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA20_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xffff) << FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_RANGE                   15:0
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffff) << FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_RANGE                   31:16
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA20_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEDATA21_0  
+#define FUSE_FUSEDATA21_0                       _MK_ADDR_CONST(0x60)
+#define FUSE_FUSEDATA21_0_WORD_COUNT                    0x1
+#define FUSE_FUSEDATA21_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA21_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA21_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_FIELD                      (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEDATA21_0_FUSEDATA21_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_RANGE                      31:0
+#define FUSE_FUSEDATA21_0_FUSEDATA21_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA21_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA21_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xffff) << FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_RANGE                   15:0
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(16)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_RANGE                       16:16
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_0__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(17)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_RANGE                       17:17
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_1__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(18)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_RANGE                       18:18
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_2__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(19)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_RANGE                       19:19
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_3__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(20)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_RANGE                       20:20
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_4__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(21)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_RANGE                       21:21
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_5__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(22)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_RANGE                       22:22
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_6__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(23)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_RANGE                       23:23
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_7__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(24)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_RANGE                       24:24
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_8__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(25)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_RANGE                       25:25
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_9__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(26)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_RANGE                      26:26
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_10__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(27)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_RANGE                      27:27
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_11__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(28)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_RANGE                      28:28
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_12__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(29)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_RANGE                      29:29
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_13__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(30)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_RANGE                      30:30
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_14__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(31)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_RANGE                      31:31
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEDATA21_0_FUSEDATA_SPARE_BIT_15__PRI_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA0_0  
+#define FUSE_FUSEWRDATA0_0                      _MK_ADDR_CONST(0x64)
+#define FUSE_FUSEWRDATA0_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA0_0_FUSEWRDATA0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_RANGE                    31:0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_RANGE                  0:0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_ENABLE__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_RANGE                 1:1
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_MASTER_DISABLE__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(2)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_RANGE                 2:2
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_BYPASS__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(3)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_RANGE                    3:3
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_RESERVE_BIT__PRI_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(4)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_RANGE                        4:4
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PRODUCTION_MODE__PRI_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(5)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_RANGE                    5:5
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_JTAG_SECUREID_VALID__PRI_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(6)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_RANGE                       13:6
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_SKU_INFO__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(14)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_RANGE                  15:14
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_PROCESS_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(16)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x3ff) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_RANGE                       25:16
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_IO_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(26)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_RANGE                  31:26
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA0_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA1_0  
+#define FUSE_FUSEWRDATA1_0                      _MK_ADDR_CONST(0x68)
+#define FUSE_FUSEWRDATA1_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA1_0_FUSEWRDATA1_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_RANGE                    31:0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_FIELD                  (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_RANGE                  1:0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_CRT_CALIB__PRI_ALIAS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(2)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_RANGE                 9:2
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_HDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(10)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_RANGE                 17:10
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_DAC_SDTV_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(18)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_RANGE                 24:18
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_0__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(25)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_RANGE                 31:25
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA1_0_FUSEWRDATA_CMC_DATARAM0_1__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA2_0  
+#define FUSE_FUSEWRDATA2_0                      _MK_ADDR_CONST(0x6c)
+#define FUSE_FUSEWRDATA2_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA2_0_FUSEWRDATA2_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_RANGE                    31:0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_RANGE                 6:0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_2__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(7)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_RANGE                 13:7
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM0_3__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(14)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_RANGE                 20:14
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_0__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(21)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_RANGE                 27:21
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_1__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(28)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0xf) << FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_RANGE                 31:28
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA2_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA3_0  
+#define FUSE_FUSEWRDATA3_0                      _MK_ADDR_CONST(0x70)
+#define FUSE_FUSEWRDATA3_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA3_0_FUSEWRDATA3_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_RANGE                    31:0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_FIELD                 (_MK_MASK_CONST(0x7) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_RANGE                 2:0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_2__PRI_ALIAS_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(3)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_RANGE                 9:3
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_CMC_DATARAM1_3__PRI_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_SHIFT                     _MK_SHIFT_CONST(10)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_RANGE                     10:10
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_WOFFSET                   0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_FA__PRI_ALIAS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(11)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_RANGE                    14:11
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_RESERVED_PRODUCTION__PRI_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(15)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_RANGE                       20:15
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE0_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(21)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_RANGE                       26:21
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE1_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(27)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x1f) << FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_RANGE                       31:27
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA3_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA4_0  
+#define FUSE_FUSEWRDATA4_0                      _MK_ADDR_CONST(0x74)
+#define FUSE_FUSEWRDATA4_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA4_0_FUSEWRDATA4_SHIFT)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_RANGE                    31:0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_RANGE                       0:0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE2_CALIB__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(1)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_RANGE                       6:1
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_HDMI_LANE3_CALIB__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(7)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_RANGE                  7:7
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_SECURITY_MODE__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffffff) << FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_RANGE                   31:8
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA4_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA5_0  
+#define FUSE_FUSEWRDATA5_0                      _MK_ADDR_CONST(0x78)
+#define FUSE_FUSEWRDATA5_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA5_0_FUSEWRDATA5_SHIFT)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_RANGE                    31:0
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_RANGE                   7:0
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY0__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffffff) << FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_RANGE                   31:8
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA5_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA6_0  
+#define FUSE_FUSEWRDATA6_0                      _MK_ADDR_CONST(0x7c)
+#define FUSE_FUSEWRDATA6_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA6_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA6_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA6_0_FUSEWRDATA6_SHIFT)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_RANGE                    31:0
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_RANGE                   7:0
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY1__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffffff) << FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_RANGE                   31:8
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA6_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA7_0  
+#define FUSE_FUSEWRDATA7_0                      _MK_ADDR_CONST(0x80)
+#define FUSE_FUSEWRDATA7_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA7_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA7_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA7_0_FUSEWRDATA7_SHIFT)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_RANGE                    31:0
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_RANGE                   7:0
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY2__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffffff) << FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_RANGE                   31:8
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA7_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA8_0  
+#define FUSE_FUSEWRDATA8_0                      _MK_ADDR_CONST(0x84)
+#define FUSE_FUSEWRDATA8_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA8_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA8_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA8_0_FUSEWRDATA8_SHIFT)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_RANGE                    31:0
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_RANGE                   7:0
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY3__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xffffff) << FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_RANGE                   31:8
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA8_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA9_0  
+#define FUSE_FUSEWRDATA9_0                      _MK_ADDR_CONST(0x88)
+#define FUSE_FUSEWRDATA9_0_WORD_COUNT                   0x1
+#define FUSE_FUSEWRDATA9_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA9_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA9_0_FUSEWRDATA9_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_RANGE                    31:0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(24)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_RANGE                  24:24
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_ENABLE__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(25)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_RANGE                 25:25
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_MASTER_DISABLE__RED_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(26)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_RANGE                 26:26
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BYPASS__RED_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(27)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_RANGE                    27:27
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVE_BIT__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(28)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_RANGE                        28:28
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRODUCTION_MODE__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(29)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_RANGE                    29:29
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_JTAG_SECUREID_VALID__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(30)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_RANGE                       31:30
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_RANGE                   7:0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_PRIVATE_KEY4__PRI_ALIAS_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_RANGE                   8:8
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_ARM_JTAG_DIS__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(9)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_RANGE                       15:9
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_BOOT_DEVICE_INFO__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(16)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_FIELD                    (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_RANGE                    23:16
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA9_0_FUSEWRDATA_RESERVED_SW__PRI_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA10_0  
+#define FUSE_FUSEWRDATA10_0                     _MK_ADDR_CONST(0x8c)
+#define FUSE_FUSEWRDATA10_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA10_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA10_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA10_0_FUSEWRDATA10_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_RANGE                  31:0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_RANGE                      5:0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_SKU_INFO__RED_ALIAS_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(6)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_RANGE                 7:6
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_PROCESS_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3ff) << FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_RANGE                      17:8
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3ff)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_IO_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(18)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_FIELD                 (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_RANGE                 25:18
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_CRT_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(26)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_RANGE                        31:26
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA10_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA11_0  
+#define FUSE_FUSEWRDATA11_0                     _MK_ADDR_CONST(0x90)
+#define FUSE_FUSEWRDATA11_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA11_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA11_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA11_0_FUSEWRDATA11_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_RANGE                  31:0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_FIELD                        (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_RANGE                        1:0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_HDTV_CALIB__RED_ALIAS_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(2)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_RANGE                        9:2
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_DAC_SDTV_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(10)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_RANGE                        16:10
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_0__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(17)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_RANGE                        23:17
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_1__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(24)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_RANGE                        30:24
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_2__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(31)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_RANGE                        31:31
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA11_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA12_0  
+#define FUSE_FUSEWRDATA12_0                     _MK_ADDR_CONST(0x94)
+#define FUSE_FUSEWRDATA12_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA12_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA12_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA12_0_FUSEWRDATA12_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_RANGE                  31:0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_FIELD                        (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_RANGE                        5:0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM0_3__RED_ALIAS_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(6)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_RANGE                        12:6
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_0__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(13)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_RANGE                        19:13
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_1__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(20)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_RANGE                        26:20
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_2__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_SHIFT                        _MK_SHIFT_CONST(27)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_FIELD                        (_MK_MASK_CONST(0x1f) << FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_RANGE                        31:27
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA12_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA13_0  
+#define FUSE_FUSEWRDATA13_0                     _MK_ADDR_CONST(0x98)
+#define FUSE_FUSEWRDATA13_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA13_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA13_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA13_0_FUSEWRDATA13_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_RANGE                  31:0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_FIELD                        (_MK_MASK_CONST(0x3) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_RANGE                        1:0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_WOFFSET                      0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_CMC_DATARAM1_3__RED_ALIAS_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_SHIFT                    _MK_SHIFT_CONST(2)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_RANGE                    2:2
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_WOFFSET                  0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_FA__RED_ALIAS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(3)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xf) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_RANGE                   6:3
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_RESERVED_PRODUCTION__RED_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(7)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_RANGE                      12:7
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE0_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(13)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_RANGE                      18:13
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE1_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(19)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_RANGE                      24:19
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE2_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(25)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x3f) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_RANGE                      30:25
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_HDMI_LANE3_CALIB__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_SHIFT                 _MK_SHIFT_CONST(31)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_RANGE                 31:31
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_WOFFSET                       0x0
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA13_0_FUSEWRDATA_SECURITY_MODE__RED_ALIAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA14_0  
+#define FUSE_FUSEWRDATA14_0                     _MK_ADDR_CONST(0x9c)
+#define FUSE_FUSEWRDATA14_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA14_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA14_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA14_0_FUSEWRDATA14_SHIFT)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_RANGE                  31:0
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_RANGE                  31:0
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA14_0_FUSEWRDATA_PRIVATE_KEY0__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA15_0  
+#define FUSE_FUSEWRDATA15_0                     _MK_ADDR_CONST(0xa0)
+#define FUSE_FUSEWRDATA15_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA15_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA15_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA15_0_FUSEWRDATA15_SHIFT)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_RANGE                  31:0
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_RANGE                  31:0
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA15_0_FUSEWRDATA_PRIVATE_KEY1__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA16_0  
+#define FUSE_FUSEWRDATA16_0                     _MK_ADDR_CONST(0xa4)
+#define FUSE_FUSEWRDATA16_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA16_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA16_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA16_0_FUSEWRDATA16_SHIFT)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_RANGE                  31:0
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA16_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_RANGE                  31:0
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA16_0_FUSEWRDATA_PRIVATE_KEY2__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA17_0  
+#define FUSE_FUSEWRDATA17_0                     _MK_ADDR_CONST(0xa8)
+#define FUSE_FUSEWRDATA17_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA17_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA17_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA17_0_FUSEWRDATA17_SHIFT)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_RANGE                  31:0
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA17_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_RANGE                  31:0
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA17_0_FUSEWRDATA_PRIVATE_KEY3__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA18_0  
+#define FUSE_FUSEWRDATA18_0                     _MK_ADDR_CONST(0xac)
+#define FUSE_FUSEWRDATA18_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA18_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA18_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA18_0_FUSEWRDATA18_SHIFT)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_RANGE                  31:0
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_RANGE                  31:0
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA18_0_FUSEWRDATA_PRIVATE_KEY4__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA19_0  
+#define FUSE_FUSEWRDATA19_0                     _MK_ADDR_CONST(0xb0)
+#define FUSE_FUSEWRDATA19_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA19_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA19_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA19_0_FUSEWRDATA19_SHIFT)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_RANGE                  31:0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_RANGE                  0:0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_ARM_JTAG_DIS__RED_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SHIFT                      _MK_SHIFT_CONST(1)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_RANGE                      7:1
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_WOFFSET                    0x0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_BOOT_DEVICE_INFO__RED_ALIAS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_RANGE                   15:8
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_RESERVED_SW__RED_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(16)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffff) << FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_RANGE                       31:16
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA19_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA20_0  
+#define FUSE_FUSEWRDATA20_0                     _MK_ADDR_CONST(0xb4)
+#define FUSE_FUSEWRDATA20_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA20_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA20_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA20_0_FUSEWRDATA20_SHIFT)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_RANGE                  31:0
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xffff) << FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_RANGE                       15:0
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_0__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SHIFT                       _MK_SHIFT_CONST(16)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_FIELD                       (_MK_MASK_CONST(0xffff) << FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_RANGE                       31:16
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA20_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWRDATA21_0  
+#define FUSE_FUSEWRDATA21_0                     _MK_ADDR_CONST(0xb8)
+#define FUSE_FUSEWRDATA21_0_WORD_COUNT                  0x1
+#define FUSE_FUSEWRDATA21_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA21_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWRDATA21_0_FUSEWRDATA21_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_RANGE                  31:0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA21_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_FIELD                       (_MK_MASK_CONST(0xffff) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_RANGE                       15:0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_WOFFSET                     0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_JTAG_SECUREID_1__PRI_ALIAS_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_RANGE                   16:16
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_0__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(17)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_RANGE                   17:17
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_1__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(18)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_RANGE                   18:18
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_2__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(19)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_RANGE                   19:19
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_3__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(20)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_RANGE                   20:20
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_4__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(21)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_RANGE                   21:21
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_5__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(22)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_RANGE                   22:22
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_6__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(23)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_RANGE                   23:23
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_7__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_RANGE                   24:24
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_8__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_SHIFT                   _MK_SHIFT_CONST(25)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_FIELD                   (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_RANGE                   25:25
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_WOFFSET                 0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_9__PRI_ALIAS_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(26)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_RANGE                  26:26
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_10__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(27)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_RANGE                  27:27
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_11__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(28)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_RANGE                  28:28
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_12__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(29)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_RANGE                  29:29
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_13__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(30)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_RANGE                  30:30
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_14__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_SHIFT                  _MK_SHIFT_CONST(31)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_SHIFT)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_RANGE                  31:31
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_WOFFSET                        0x0
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWRDATA21_0_FUSEWRDATA_SPARE_BIT_15__PRI_ALIAS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Register FUSE_FUSEBYPASS_0  
+#define FUSE_FUSEBYPASS_0                       _MK_ADDR_CONST(0xe0)
+#define FUSE_FUSEBYPASS_0_WORD_COUNT                    0x1
+#define FUSE_FUSEBYPASS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SHIFT)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_RANGE                  0:0
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_WOFFSET                        0x0
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_INIT_ENUM                      DISABLED
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DISABLED                       _MK_ENUM_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_ENABLED                        _MK_ENUM_CONST(1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DISABLE                        _MK_ENUM_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register FUSE_PRIVATEKEYDISABLE_0  
+#define FUSE_PRIVATEKEYDISABLE_0                        _MK_ADDR_CONST(0xe4)
+#define FUSE_PRIVATEKEYDISABLE_0_WORD_COUNT                     0x1
+#define FUSE_PRIVATEKEYDISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SHIFT)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_RANGE                    0:0
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_WOFFSET                  0x0
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_INIT_ENUM                        KEY_VISIBLE
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_KEY_VISIBLE                      _MK_ENUM_CONST(0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_KEY_INVISIBLE                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Reserved address 240 [0xf0] 
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register FUSE_PRODUCTION_MODE_0  
+#define FUSE_PRODUCTION_MODE_0                  _MK_ADDR_CONST(0x100)
+#define FUSE_PRODUCTION_MODE_0_WORD_COUNT                       0x1
+#define FUSE_PRODUCTION_MODE_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SHIFT)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_RANGE                    0:0
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_WOFFSET                  0x0
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_VALID_0  
+#define FUSE_JTAG_SECUREID_VALID_0                      _MK_ADDR_CONST(0x104)
+#define FUSE_JTAG_SECUREID_VALID_0_WORD_COUNT                   0x1
+#define FUSE_JTAG_SECUREID_VALID_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SHIFT)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_RANGE                    0:0
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_0_0  
+#define FUSE_JTAG_SECUREID_0_0                  _MK_ADDR_CONST(0x108)
+#define FUSE_JTAG_SECUREID_0_0_WORD_COUNT                       0x1
+#define FUSE_JTAG_SECUREID_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SHIFT)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_RANGE                    31:0
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_1_0  
+#define FUSE_JTAG_SECUREID_1_0                  _MK_ADDR_CONST(0x10c)
+#define FUSE_JTAG_SECUREID_1_0_WORD_COUNT                       0x1
+#define FUSE_JTAG_SECUREID_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SHIFT)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_RANGE                    31:0
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SKU_INFO_0  
+#define FUSE_SKU_INFO_0                 _MK_ADDR_CONST(0x110)
+#define FUSE_SKU_INFO_0_WORD_COUNT                      0x1
+#define FUSE_SKU_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SKU_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SKU_INFO_0_SKU_INFO_FIELD                  (_MK_MASK_CONST(0xff) << FUSE_SKU_INFO_0_SKU_INFO_SHIFT)
+#define FUSE_SKU_INFO_0_SKU_INFO_RANGE                  7:0
+#define FUSE_SKU_INFO_0_SKU_INFO_WOFFSET                        0x0
+#define FUSE_SKU_INFO_0_SKU_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SKU_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_SKU_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SKU_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PROCESS_CALIB_0  
+#define FUSE_PROCESS_CALIB_0                    _MK_ADDR_CONST(0x114)
+#define FUSE_PROCESS_CALIB_0_WORD_COUNT                         0x1
+#define FUSE_PROCESS_CALIB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_RESET_MASK                         _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_READ_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_FIELD                        (_MK_MASK_CONST(0x3) << FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SHIFT)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_RANGE                        1:0
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_WOFFSET                      0x0
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_IO_CALIB_0  
+#define FUSE_IO_CALIB_0                 _MK_ADDR_CONST(0x118)
+#define FUSE_IO_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_IO_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_IO_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_IO_CALIB_0_IO_CALIB_FIELD                  (_MK_MASK_CONST(0x3ff) << FUSE_IO_CALIB_0_IO_CALIB_SHIFT)
+#define FUSE_IO_CALIB_0_IO_CALIB_RANGE                  9:0
+#define FUSE_IO_CALIB_0_IO_CALIB_WOFFSET                        0x0
+#define FUSE_IO_CALIB_0_IO_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_IO_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_IO_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_IO_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_CRT_CALIB_0  
+#define FUSE_DAC_CRT_CALIB_0                    _MK_ADDR_CONST(0x11c)
+#define FUSE_DAC_CRT_CALIB_0_WORD_COUNT                         0x1
+#define FUSE_DAC_CRT_CALIB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_FIELD                        (_MK_MASK_CONST(0xff) << FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SHIFT)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_RANGE                        7:0
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_WOFFSET                      0x0
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_HDTV_CALIB_0  
+#define FUSE_DAC_HDTV_CALIB_0                   _MK_ADDR_CONST(0x120)
+#define FUSE_DAC_HDTV_CALIB_0_WORD_COUNT                        0x1
+#define FUSE_DAC_HDTV_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_FIELD                      (_MK_MASK_CONST(0xff) << FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SHIFT)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_RANGE                      7:0
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_WOFFSET                    0x0
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_SDTV_CALIB_0  
+#define FUSE_DAC_SDTV_CALIB_0                   _MK_ADDR_CONST(0x124)
+#define FUSE_DAC_SDTV_CALIB_0_WORD_COUNT                        0x1
+#define FUSE_DAC_SDTV_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_FIELD                      (_MK_MASK_CONST(0xff) << FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SHIFT)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_RANGE                      7:0
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_WOFFSET                    0x0
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM0_0_0  
+#define FUSE_CMC_DATARAM0_0_0                   _MK_ADDR_CONST(0x128)
+#define FUSE_CMC_DATARAM0_0_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM0_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_SHIFT)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_RANGE                      6:0
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_0_0_CMC_DATARAM0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM0_1_0  
+#define FUSE_CMC_DATARAM0_1_0                   _MK_ADDR_CONST(0x12c)
+#define FUSE_CMC_DATARAM0_1_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM0_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_SHIFT)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_RANGE                      6:0
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_1_0_CMC_DATARAM0_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM0_2_0  
+#define FUSE_CMC_DATARAM0_2_0                   _MK_ADDR_CONST(0x130)
+#define FUSE_CMC_DATARAM0_2_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM0_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_SHIFT)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_RANGE                      6:0
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_2_0_CMC_DATARAM0_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM0_3_0  
+#define FUSE_CMC_DATARAM0_3_0                   _MK_ADDR_CONST(0x134)
+#define FUSE_CMC_DATARAM0_3_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM0_3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_3_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_SHIFT)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_RANGE                      6:0
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM0_3_0_CMC_DATARAM0_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM1_0_0  
+#define FUSE_CMC_DATARAM1_0_0                   _MK_ADDR_CONST(0x138)
+#define FUSE_CMC_DATARAM1_0_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM1_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_SHIFT)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_RANGE                      6:0
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_0_0_CMC_DATARAM1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM1_1_0  
+#define FUSE_CMC_DATARAM1_1_0                   _MK_ADDR_CONST(0x13c)
+#define FUSE_CMC_DATARAM1_1_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM1_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_SHIFT)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_RANGE                      6:0
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_1_0_CMC_DATARAM1_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM1_2_0  
+#define FUSE_CMC_DATARAM1_2_0                   _MK_ADDR_CONST(0x140)
+#define FUSE_CMC_DATARAM1_2_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM1_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_SHIFT)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_RANGE                      6:0
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_2_0_CMC_DATARAM1_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_CMC_DATARAM1_3_0  
+#define FUSE_CMC_DATARAM1_3_0                   _MK_ADDR_CONST(0x144)
+#define FUSE_CMC_DATARAM1_3_0_WORD_COUNT                        0x1
+#define FUSE_CMC_DATARAM1_3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_3_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_FIELD                      (_MK_MASK_CONST(0x7f) << FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_SHIFT)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_RANGE                      6:0
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_WOFFSET                    0x0
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_CMC_DATARAM1_3_0_CMC_DATARAM1_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FA_0  
+#define FUSE_FA_0                       _MK_ADDR_CONST(0x148)
+#define FUSE_FA_0_WORD_COUNT                    0x1
+#define FUSE_FA_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_FA_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FA_0_FA_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FA_0_FA_SHIFT)
+#define FUSE_FA_0_FA_RANGE                      0:0
+#define FUSE_FA_0_FA_WOFFSET                    0x0
+#define FUSE_FA_0_FA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_FA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_FA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_FA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_PRODUCTION_0  
+#define FUSE_RESERVED_PRODUCTION_0                      _MK_ADDR_CONST(0x14c)
+#define FUSE_RESERVED_PRODUCTION_0_WORD_COUNT                   0x1
+#define FUSE_RESERVED_PRODUCTION_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SHIFT)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_RANGE                    3:0
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_WOFFSET                  0x0
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE0_CALIB_0  
+#define FUSE_HDMI_LANE0_CALIB_0                 _MK_ADDR_CONST(0x150)
+#define FUSE_HDMI_LANE0_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE0_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SHIFT)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE1_CALIB_0  
+#define FUSE_HDMI_LANE1_CALIB_0                 _MK_ADDR_CONST(0x154)
+#define FUSE_HDMI_LANE1_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE1_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SHIFT)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE2_CALIB_0  
+#define FUSE_HDMI_LANE2_CALIB_0                 _MK_ADDR_CONST(0x158)
+#define FUSE_HDMI_LANE2_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE2_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SHIFT)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE3_CALIB_0  
+#define FUSE_HDMI_LANE3_CALIB_0                 _MK_ADDR_CONST(0x15c)
+#define FUSE_HDMI_LANE3_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE3_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SHIFT)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 352 [0x160] 
+
+// Reserved address 356 [0x164] 
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Reserved address 384 [0x180] 
+
+// Reserved address 388 [0x184] 
+
+// Reserved address 392 [0x188] 
+
+// Reserved address 396 [0x18c] 
+
+// Reserved address 400 [0x190] 
+
+// Reserved address 404 [0x194] 
+
+// Reserved address 408 [0x198] 
+
+// Reserved address 412 [0x19c] 
+
+// Register FUSE_SECURITY_MODE_0  
+#define FUSE_SECURITY_MODE_0                    _MK_ADDR_CONST(0x1a0)
+#define FUSE_SECURITY_MODE_0_WORD_COUNT                         0x1
+#define FUSE_SECURITY_MODE_0_RESET_VAL                  _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_SECURITY_MODE_0_SECURITY_MODE_SHIFT)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_RANGE                        0:0
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_WOFFSET                      0x0
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY0_0  
+#define FUSE_PRIVATE_KEY0_0                     _MK_ADDR_CONST(0x1a4)
+#define FUSE_PRIVATE_KEY0_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SHIFT)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_RANGE                  31:0
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY1_0  
+#define FUSE_PRIVATE_KEY1_0                     _MK_ADDR_CONST(0x1a8)
+#define FUSE_PRIVATE_KEY1_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SHIFT)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_RANGE                  31:0
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY2_0  
+#define FUSE_PRIVATE_KEY2_0                     _MK_ADDR_CONST(0x1ac)
+#define FUSE_PRIVATE_KEY2_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SHIFT)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_RANGE                  31:0
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY3_0  
+#define FUSE_PRIVATE_KEY3_0                     _MK_ADDR_CONST(0x1b0)
+#define FUSE_PRIVATE_KEY3_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SHIFT)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_RANGE                  31:0
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY4_0  
+#define FUSE_PRIVATE_KEY4_0                     _MK_ADDR_CONST(0x1b4)
+#define FUSE_PRIVATE_KEY4_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY4_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SHIFT)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_RANGE                  31:0
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_ARM_JTAG_DIS_0  
+#define FUSE_ARM_JTAG_DIS_0                     _MK_ADDR_CONST(0x1b8)
+#define FUSE_ARM_JTAG_DIS_0_WORD_COUNT                  0x1
+#define FUSE_ARM_JTAG_DIS_0_RESET_VAL                   _MK_MASK_CONST(0x1)
+#define FUSE_ARM_JTAG_DIS_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_ARM_JTAG_DIS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_ARM_JTAG_DIS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_ARM_JTAG_DIS_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_ARM_JTAG_DIS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SHIFT)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_RANGE                  0:0
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_WOFFSET                        0x0
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_DEFAULT                        _MK_MASK_CONST(0x1)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_ARM_JTAG_DIS_0_ARM_JTAG_DIS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_BOOT_DEVICE_INFO_0  
+#define FUSE_BOOT_DEVICE_INFO_0                 _MK_ADDR_CONST(0x1bc)
+#define FUSE_BOOT_DEVICE_INFO_0_WORD_COUNT                      0x1
+#define FUSE_BOOT_DEVICE_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_RESET_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_BOOT_DEVICE_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_READ_MASK                       _MK_MASK_CONST(0x7f)
+#define FUSE_BOOT_DEVICE_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_FIELD                  (_MK_MASK_CONST(0x7f) << FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SHIFT)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_RANGE                  6:0
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_WOFFSET                        0x0
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_SW_0  
+#define FUSE_RESERVED_SW_0                      _MK_ADDR_CONST(0x1c0)
+#define FUSE_RESERVED_SW_0_WORD_COUNT                   0x1
+#define FUSE_RESERVED_SW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_FIELD                    (_MK_MASK_CONST(0xff) << FUSE_RESERVED_SW_0_RESERVED_SW_SHIFT)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_RANGE                    7:0
+#define FUSE_RESERVED_SW_0_RESERVED_SW_WOFFSET                  0x0
+#define FUSE_RESERVED_SW_0_RESERVED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_0_0  
+#define FUSE_SPARE_BIT_0_0                      _MK_ADDR_CONST(0x1c4)
+#define FUSE_SPARE_BIT_0_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SHIFT)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_RANGE                    0:0
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_1_0  
+#define FUSE_SPARE_BIT_1_0                      _MK_ADDR_CONST(0x1c8)
+#define FUSE_SPARE_BIT_1_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SHIFT)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_RANGE                    0:0
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_2_0  
+#define FUSE_SPARE_BIT_2_0                      _MK_ADDR_CONST(0x1cc)
+#define FUSE_SPARE_BIT_2_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SHIFT)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_RANGE                    0:0
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_3_0  
+#define FUSE_SPARE_BIT_3_0                      _MK_ADDR_CONST(0x1d0)
+#define FUSE_SPARE_BIT_3_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SHIFT)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_RANGE                    0:0
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_4_0  
+#define FUSE_SPARE_BIT_4_0                      _MK_ADDR_CONST(0x1d4)
+#define FUSE_SPARE_BIT_4_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SHIFT)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_RANGE                    0:0
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_5_0  
+#define FUSE_SPARE_BIT_5_0                      _MK_ADDR_CONST(0x1d8)
+#define FUSE_SPARE_BIT_5_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SHIFT)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_RANGE                    0:0
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_6_0  
+#define FUSE_SPARE_BIT_6_0                      _MK_ADDR_CONST(0x1dc)
+#define FUSE_SPARE_BIT_6_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_6_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SHIFT)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_RANGE                    0:0
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_7_0  
+#define FUSE_SPARE_BIT_7_0                      _MK_ADDR_CONST(0x1e0)
+#define FUSE_SPARE_BIT_7_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_7_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SHIFT)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_RANGE                    0:0
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_8_0  
+#define FUSE_SPARE_BIT_8_0                      _MK_ADDR_CONST(0x1e4)
+#define FUSE_SPARE_BIT_8_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_8_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SHIFT)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_RANGE                    0:0
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_9_0  
+#define FUSE_SPARE_BIT_9_0                      _MK_ADDR_CONST(0x1e8)
+#define FUSE_SPARE_BIT_9_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_9_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SHIFT)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_RANGE                    0:0
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_10_0  
+#define FUSE_SPARE_BIT_10_0                     _MK_ADDR_CONST(0x1ec)
+#define FUSE_SPARE_BIT_10_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_10_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SHIFT)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_RANGE                  0:0
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_11_0  
+#define FUSE_SPARE_BIT_11_0                     _MK_ADDR_CONST(0x1f0)
+#define FUSE_SPARE_BIT_11_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_11_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SHIFT)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_RANGE                  0:0
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_12_0  
+#define FUSE_SPARE_BIT_12_0                     _MK_ADDR_CONST(0x1f4)
+#define FUSE_SPARE_BIT_12_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_12_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SHIFT)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_RANGE                  0:0
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_13_0  
+#define FUSE_SPARE_BIT_13_0                     _MK_ADDR_CONST(0x1f8)
+#define FUSE_SPARE_BIT_13_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_13_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SHIFT)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_RANGE                  0:0
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_14_0  
+#define FUSE_SPARE_BIT_14_0                     _MK_ADDR_CONST(0x1fc)
+#define FUSE_SPARE_BIT_14_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_14_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SHIFT)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_RANGE                  0:0
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_15_0  
+#define FUSE_SPARE_BIT_15_0                     _MK_ADDR_CONST(0x200)
+#define FUSE_SPARE_BIT_15_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_15_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SHIFT)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_RANGE                  0:0
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARFUSE_REGS(_op_) \
+_op_(FUSE_FUSECTRL_0) \
+_op_(FUSE_FUSETIME1_0) \
+_op_(FUSE_FUSETIME2_0) \
+_op_(FUSE_FUSEDATA0_0) \
+_op_(FUSE_FUSEDATA1_0) \
+_op_(FUSE_FUSEDATA2_0) \
+_op_(FUSE_FUSEDATA3_0) \
+_op_(FUSE_FUSEDATA4_0) \
+_op_(FUSE_FUSEDATA5_0) \
+_op_(FUSE_FUSEDATA6_0) \
+_op_(FUSE_FUSEDATA7_0) \
+_op_(FUSE_FUSEDATA8_0) \
+_op_(FUSE_FUSEDATA9_0) \
+_op_(FUSE_FUSEDATA10_0) \
+_op_(FUSE_FUSEDATA11_0) \
+_op_(FUSE_FUSEDATA12_0) \
+_op_(FUSE_FUSEDATA13_0) \
+_op_(FUSE_FUSEDATA14_0) \
+_op_(FUSE_FUSEDATA15_0) \
+_op_(FUSE_FUSEDATA16_0) \
+_op_(FUSE_FUSEDATA17_0) \
+_op_(FUSE_FUSEDATA18_0) \
+_op_(FUSE_FUSEDATA19_0) \
+_op_(FUSE_FUSEDATA20_0) \
+_op_(FUSE_FUSEDATA21_0) \
+_op_(FUSE_FUSEWRDATA0_0) \
+_op_(FUSE_FUSEWRDATA1_0) \
+_op_(FUSE_FUSEWRDATA2_0) \
+_op_(FUSE_FUSEWRDATA3_0) \
+_op_(FUSE_FUSEWRDATA4_0) \
+_op_(FUSE_FUSEWRDATA5_0) \
+_op_(FUSE_FUSEWRDATA6_0) \
+_op_(FUSE_FUSEWRDATA7_0) \
+_op_(FUSE_FUSEWRDATA8_0) \
+_op_(FUSE_FUSEWRDATA9_0) \
+_op_(FUSE_FUSEWRDATA10_0) \
+_op_(FUSE_FUSEWRDATA11_0) \
+_op_(FUSE_FUSEWRDATA12_0) \
+_op_(FUSE_FUSEWRDATA13_0) \
+_op_(FUSE_FUSEWRDATA14_0) \
+_op_(FUSE_FUSEWRDATA15_0) \
+_op_(FUSE_FUSEWRDATA16_0) \
+_op_(FUSE_FUSEWRDATA17_0) \
+_op_(FUSE_FUSEWRDATA18_0) \
+_op_(FUSE_FUSEWRDATA19_0) \
+_op_(FUSE_FUSEWRDATA20_0) \
+_op_(FUSE_FUSEWRDATA21_0) \
+_op_(FUSE_FUSEBYPASS_0) \
+_op_(FUSE_PRIVATEKEYDISABLE_0) \
+_op_(FUSE_PRODUCTION_MODE_0) \
+_op_(FUSE_JTAG_SECUREID_VALID_0) \
+_op_(FUSE_JTAG_SECUREID_0_0) \
+_op_(FUSE_JTAG_SECUREID_1_0) \
+_op_(FUSE_SKU_INFO_0) \
+_op_(FUSE_PROCESS_CALIB_0) \
+_op_(FUSE_IO_CALIB_0) \
+_op_(FUSE_DAC_CRT_CALIB_0) \
+_op_(FUSE_DAC_HDTV_CALIB_0) \
+_op_(FUSE_DAC_SDTV_CALIB_0) \
+_op_(FUSE_CMC_DATARAM0_0_0) \
+_op_(FUSE_CMC_DATARAM0_1_0) \
+_op_(FUSE_CMC_DATARAM0_2_0) \
+_op_(FUSE_CMC_DATARAM0_3_0) \
+_op_(FUSE_CMC_DATARAM1_0_0) \
+_op_(FUSE_CMC_DATARAM1_1_0) \
+_op_(FUSE_CMC_DATARAM1_2_0) \
+_op_(FUSE_CMC_DATARAM1_3_0) \
+_op_(FUSE_FA_0) \
+_op_(FUSE_RESERVED_PRODUCTION_0) \
+_op_(FUSE_HDMI_LANE0_CALIB_0) \
+_op_(FUSE_HDMI_LANE1_CALIB_0) \
+_op_(FUSE_HDMI_LANE2_CALIB_0) \
+_op_(FUSE_HDMI_LANE3_CALIB_0) \
+_op_(FUSE_SECURITY_MODE_0) \
+_op_(FUSE_PRIVATE_KEY0_0) \
+_op_(FUSE_PRIVATE_KEY1_0) \
+_op_(FUSE_PRIVATE_KEY2_0) \
+_op_(FUSE_PRIVATE_KEY3_0) \
+_op_(FUSE_PRIVATE_KEY4_0) \
+_op_(FUSE_ARM_JTAG_DIS_0) \
+_op_(FUSE_BOOT_DEVICE_INFO_0) \
+_op_(FUSE_RESERVED_SW_0) \
+_op_(FUSE_SPARE_BIT_0_0) \
+_op_(FUSE_SPARE_BIT_1_0) \
+_op_(FUSE_SPARE_BIT_2_0) \
+_op_(FUSE_SPARE_BIT_3_0) \
+_op_(FUSE_SPARE_BIT_4_0) \
+_op_(FUSE_SPARE_BIT_5_0) \
+_op_(FUSE_SPARE_BIT_6_0) \
+_op_(FUSE_SPARE_BIT_7_0) \
+_op_(FUSE_SPARE_BIT_8_0) \
+_op_(FUSE_SPARE_BIT_9_0) \
+_op_(FUSE_SPARE_BIT_10_0) \
+_op_(FUSE_SPARE_BIT_11_0) \
+_op_(FUSE_SPARE_BIT_12_0) \
+_op_(FUSE_SPARE_BIT_13_0) \
+_op_(FUSE_SPARE_BIT_14_0) \
+_op_(FUSE_SPARE_BIT_15_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_FUSE       0x00000000
+
+//
+// ARFUSE REGISTER BANKS
+//
+
+#define FUSE0_FIRST_REG 0x0000 // FUSE_FUSECTRL_0
+#define FUSE0_LAST_REG 0x00b8 // FUSE_FUSEWRDATA21_0
+#define FUSE1_FIRST_REG 0x00e0 // FUSE_FUSEBYPASS_0
+#define FUSE1_LAST_REG 0x00e4 // FUSE_PRIVATEKEYDISABLE_0
+#define FUSE2_FIRST_REG 0x0100 // FUSE_PRODUCTION_MODE_0
+#define FUSE2_LAST_REG 0x015c // FUSE_HDMI_LANE3_CALIB_0
+#define FUSE3_FIRST_REG 0x01a0 // FUSE_SECURITY_MODE_0
+#define FUSE3_LAST_REG 0x0200 // FUSE_SPARE_BIT_15_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARFUSE_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/argpio.h b/arch/arm/mach-tegra/nv/include/ap15/argpio.h
new file mode 100644
index 000000000000..13579050cace
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/argpio.h
@@ -0,0 +1,12173 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARGPIO_H_INC_
+#define ___ARGPIO_H_INC_
+
+// Register GPIO_CNF_0  
+#define GPIO_CNF_0                      _MK_ADDR_CONST(0x0)
+#define GPIO_CNF_0_WORD_COUNT                   0x1
+#define GPIO_CNF_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define GPIO_CNF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_CNF_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_0_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_CNF_0_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_0_BIT_7_SHIFT)
+#define GPIO_CNF_0_BIT_7_RANGE                  7:7
+#define GPIO_CNF_0_BIT_7_WOFFSET                        0x0
+#define GPIO_CNF_0_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_0_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_7_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_0_BIT_7_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_0_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_CNF_0_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_0_BIT_6_SHIFT)
+#define GPIO_CNF_0_BIT_6_RANGE                  6:6
+#define GPIO_CNF_0_BIT_6_WOFFSET                        0x0
+#define GPIO_CNF_0_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_0_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_6_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_0_BIT_6_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_0_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_CNF_0_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_0_BIT_5_SHIFT)
+#define GPIO_CNF_0_BIT_5_RANGE                  5:5
+#define GPIO_CNF_0_BIT_5_WOFFSET                        0x0
+#define GPIO_CNF_0_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_0_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_5_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_0_BIT_5_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_0_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_CNF_0_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_0_BIT_4_SHIFT)
+#define GPIO_CNF_0_BIT_4_RANGE                  4:4
+#define GPIO_CNF_0_BIT_4_WOFFSET                        0x0
+#define GPIO_CNF_0_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_0_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_4_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_0_BIT_4_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_0_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_CNF_0_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_0_BIT_3_SHIFT)
+#define GPIO_CNF_0_BIT_3_RANGE                  3:3
+#define GPIO_CNF_0_BIT_3_WOFFSET                        0x0
+#define GPIO_CNF_0_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_0_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_3_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_0_BIT_3_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_0_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_CNF_0_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_0_BIT_2_SHIFT)
+#define GPIO_CNF_0_BIT_2_RANGE                  2:2
+#define GPIO_CNF_0_BIT_2_WOFFSET                        0x0
+#define GPIO_CNF_0_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_0_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_2_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_0_BIT_2_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_0_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_CNF_0_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_0_BIT_1_SHIFT)
+#define GPIO_CNF_0_BIT_1_RANGE                  1:1
+#define GPIO_CNF_0_BIT_1_WOFFSET                        0x0
+#define GPIO_CNF_0_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_0_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_1_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_0_BIT_1_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_0_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_CNF_0_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_0_BIT_0_SHIFT)
+#define GPIO_CNF_0_BIT_0_RANGE                  0:0
+#define GPIO_CNF_0_BIT_0_WOFFSET                        0x0
+#define GPIO_CNF_0_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_0_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_0_BIT_0_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_0_BIT_0_GPIO                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_CNF  
+#define GPIO_CNF                        _MK_ADDR_CONST(0x0)
+#define GPIO_CNF_WORD_COUNT                     0x1
+#define GPIO_CNF_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define GPIO_CNF_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define GPIO_CNF_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define GPIO_CNF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_READ_MASK                      _MK_MASK_CONST(0xff)
+#define GPIO_CNF_WRITE_MASK                     _MK_MASK_CONST(0xff)
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_BIT_7_SHIFT                    _MK_SHIFT_CONST(7)
+#define GPIO_CNF_BIT_7_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_CNF_BIT_7_SHIFT)
+#define GPIO_CNF_BIT_7_RANGE                    7:7
+#define GPIO_CNF_BIT_7_WOFFSET                  0x0
+#define GPIO_CNF_BIT_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_CNF_BIT_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_7_SPIO                     _MK_ENUM_CONST(0)
+#define GPIO_CNF_BIT_7_GPIO                     _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_BIT_6_SHIFT                    _MK_SHIFT_CONST(6)
+#define GPIO_CNF_BIT_6_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_CNF_BIT_6_SHIFT)
+#define GPIO_CNF_BIT_6_RANGE                    6:6
+#define GPIO_CNF_BIT_6_WOFFSET                  0x0
+#define GPIO_CNF_BIT_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_CNF_BIT_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_6_SPIO                     _MK_ENUM_CONST(0)
+#define GPIO_CNF_BIT_6_GPIO                     _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_BIT_5_SHIFT                    _MK_SHIFT_CONST(5)
+#define GPIO_CNF_BIT_5_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_CNF_BIT_5_SHIFT)
+#define GPIO_CNF_BIT_5_RANGE                    5:5
+#define GPIO_CNF_BIT_5_WOFFSET                  0x0
+#define GPIO_CNF_BIT_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_CNF_BIT_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_5_SPIO                     _MK_ENUM_CONST(0)
+#define GPIO_CNF_BIT_5_GPIO                     _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_BIT_4_SHIFT                    _MK_SHIFT_CONST(4)
+#define GPIO_CNF_BIT_4_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_CNF_BIT_4_SHIFT)
+#define GPIO_CNF_BIT_4_RANGE                    4:4
+#define GPIO_CNF_BIT_4_WOFFSET                  0x0
+#define GPIO_CNF_BIT_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_CNF_BIT_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_4_SPIO                     _MK_ENUM_CONST(0)
+#define GPIO_CNF_BIT_4_GPIO                     _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_BIT_3_SHIFT                    _MK_SHIFT_CONST(3)
+#define GPIO_CNF_BIT_3_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_CNF_BIT_3_SHIFT)
+#define GPIO_CNF_BIT_3_RANGE                    3:3
+#define GPIO_CNF_BIT_3_WOFFSET                  0x0
+#define GPIO_CNF_BIT_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_CNF_BIT_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_3_SPIO                     _MK_ENUM_CONST(0)
+#define GPIO_CNF_BIT_3_GPIO                     _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_BIT_2_SHIFT                    _MK_SHIFT_CONST(2)
+#define GPIO_CNF_BIT_2_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_CNF_BIT_2_SHIFT)
+#define GPIO_CNF_BIT_2_RANGE                    2:2
+#define GPIO_CNF_BIT_2_WOFFSET                  0x0
+#define GPIO_CNF_BIT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_CNF_BIT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_2_SPIO                     _MK_ENUM_CONST(0)
+#define GPIO_CNF_BIT_2_GPIO                     _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_BIT_1_SHIFT                    _MK_SHIFT_CONST(1)
+#define GPIO_CNF_BIT_1_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_CNF_BIT_1_SHIFT)
+#define GPIO_CNF_BIT_1_RANGE                    1:1
+#define GPIO_CNF_BIT_1_WOFFSET                  0x0
+#define GPIO_CNF_BIT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_CNF_BIT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_1_SPIO                     _MK_ENUM_CONST(0)
+#define GPIO_CNF_BIT_1_GPIO                     _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_BIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define GPIO_CNF_BIT_0_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_CNF_BIT_0_SHIFT)
+#define GPIO_CNF_BIT_0_RANGE                    0:0
+#define GPIO_CNF_BIT_0_WOFFSET                  0x0
+#define GPIO_CNF_BIT_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_CNF_BIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_CNF_BIT_0_SPIO                     _MK_ENUM_CONST(0)
+#define GPIO_CNF_BIT_0_GPIO                     _MK_ENUM_CONST(1)
+
+
+// Register GPIO_CNF_1  
+#define GPIO_CNF_1                      _MK_ADDR_CONST(0x4)
+#define GPIO_CNF_1_WORD_COUNT                   0x1
+#define GPIO_CNF_1_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define GPIO_CNF_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_CNF_1_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_1_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_CNF_1_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_1_BIT_7_SHIFT)
+#define GPIO_CNF_1_BIT_7_RANGE                  7:7
+#define GPIO_CNF_1_BIT_7_WOFFSET                        0x0
+#define GPIO_CNF_1_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_1_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_7_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_1_BIT_7_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_1_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_CNF_1_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_1_BIT_6_SHIFT)
+#define GPIO_CNF_1_BIT_6_RANGE                  6:6
+#define GPIO_CNF_1_BIT_6_WOFFSET                        0x0
+#define GPIO_CNF_1_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_1_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_6_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_1_BIT_6_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_1_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_CNF_1_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_1_BIT_5_SHIFT)
+#define GPIO_CNF_1_BIT_5_RANGE                  5:5
+#define GPIO_CNF_1_BIT_5_WOFFSET                        0x0
+#define GPIO_CNF_1_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_1_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_5_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_1_BIT_5_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_1_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_CNF_1_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_1_BIT_4_SHIFT)
+#define GPIO_CNF_1_BIT_4_RANGE                  4:4
+#define GPIO_CNF_1_BIT_4_WOFFSET                        0x0
+#define GPIO_CNF_1_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_1_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_4_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_1_BIT_4_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_1_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_CNF_1_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_1_BIT_3_SHIFT)
+#define GPIO_CNF_1_BIT_3_RANGE                  3:3
+#define GPIO_CNF_1_BIT_3_WOFFSET                        0x0
+#define GPIO_CNF_1_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_1_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_3_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_1_BIT_3_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_1_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_CNF_1_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_1_BIT_2_SHIFT)
+#define GPIO_CNF_1_BIT_2_RANGE                  2:2
+#define GPIO_CNF_1_BIT_2_WOFFSET                        0x0
+#define GPIO_CNF_1_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_1_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_2_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_1_BIT_2_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_1_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_CNF_1_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_1_BIT_1_SHIFT)
+#define GPIO_CNF_1_BIT_1_RANGE                  1:1
+#define GPIO_CNF_1_BIT_1_WOFFSET                        0x0
+#define GPIO_CNF_1_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_1_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_1_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_1_BIT_1_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_1_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_CNF_1_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_1_BIT_0_SHIFT)
+#define GPIO_CNF_1_BIT_0_RANGE                  0:0
+#define GPIO_CNF_1_BIT_0_WOFFSET                        0x0
+#define GPIO_CNF_1_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_1_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_1_BIT_0_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_1_BIT_0_GPIO                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_CNF_2  
+#define GPIO_CNF_2                      _MK_ADDR_CONST(0x8)
+#define GPIO_CNF_2_WORD_COUNT                   0x1
+#define GPIO_CNF_2_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define GPIO_CNF_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_CNF_2_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_2_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_CNF_2_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_2_BIT_7_SHIFT)
+#define GPIO_CNF_2_BIT_7_RANGE                  7:7
+#define GPIO_CNF_2_BIT_7_WOFFSET                        0x0
+#define GPIO_CNF_2_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_2_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_7_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_2_BIT_7_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_2_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_CNF_2_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_2_BIT_6_SHIFT)
+#define GPIO_CNF_2_BIT_6_RANGE                  6:6
+#define GPIO_CNF_2_BIT_6_WOFFSET                        0x0
+#define GPIO_CNF_2_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_2_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_6_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_2_BIT_6_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_2_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_CNF_2_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_2_BIT_5_SHIFT)
+#define GPIO_CNF_2_BIT_5_RANGE                  5:5
+#define GPIO_CNF_2_BIT_5_WOFFSET                        0x0
+#define GPIO_CNF_2_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_2_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_5_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_2_BIT_5_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_2_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_CNF_2_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_2_BIT_4_SHIFT)
+#define GPIO_CNF_2_BIT_4_RANGE                  4:4
+#define GPIO_CNF_2_BIT_4_WOFFSET                        0x0
+#define GPIO_CNF_2_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_2_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_4_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_2_BIT_4_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_2_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_CNF_2_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_2_BIT_3_SHIFT)
+#define GPIO_CNF_2_BIT_3_RANGE                  3:3
+#define GPIO_CNF_2_BIT_3_WOFFSET                        0x0
+#define GPIO_CNF_2_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_2_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_3_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_2_BIT_3_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_2_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_CNF_2_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_2_BIT_2_SHIFT)
+#define GPIO_CNF_2_BIT_2_RANGE                  2:2
+#define GPIO_CNF_2_BIT_2_WOFFSET                        0x0
+#define GPIO_CNF_2_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_2_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_2_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_2_BIT_2_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_2_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_CNF_2_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_2_BIT_1_SHIFT)
+#define GPIO_CNF_2_BIT_1_RANGE                  1:1
+#define GPIO_CNF_2_BIT_1_WOFFSET                        0x0
+#define GPIO_CNF_2_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_2_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_1_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_2_BIT_1_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_2_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_CNF_2_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_2_BIT_0_SHIFT)
+#define GPIO_CNF_2_BIT_0_RANGE                  0:0
+#define GPIO_CNF_2_BIT_0_WOFFSET                        0x0
+#define GPIO_CNF_2_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_2_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_2_BIT_0_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_2_BIT_0_GPIO                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_CNF_3  
+#define GPIO_CNF_3                      _MK_ADDR_CONST(0xc)
+#define GPIO_CNF_3_WORD_COUNT                   0x1
+#define GPIO_CNF_3_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define GPIO_CNF_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_CNF_3_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_3_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_CNF_3_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_3_BIT_7_SHIFT)
+#define GPIO_CNF_3_BIT_7_RANGE                  7:7
+#define GPIO_CNF_3_BIT_7_WOFFSET                        0x0
+#define GPIO_CNF_3_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_3_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_7_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_3_BIT_7_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_3_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_CNF_3_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_3_BIT_6_SHIFT)
+#define GPIO_CNF_3_BIT_6_RANGE                  6:6
+#define GPIO_CNF_3_BIT_6_WOFFSET                        0x0
+#define GPIO_CNF_3_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_3_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_6_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_3_BIT_6_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_3_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_CNF_3_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_3_BIT_5_SHIFT)
+#define GPIO_CNF_3_BIT_5_RANGE                  5:5
+#define GPIO_CNF_3_BIT_5_WOFFSET                        0x0
+#define GPIO_CNF_3_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_3_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_5_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_3_BIT_5_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_3_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_CNF_3_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_3_BIT_4_SHIFT)
+#define GPIO_CNF_3_BIT_4_RANGE                  4:4
+#define GPIO_CNF_3_BIT_4_WOFFSET                        0x0
+#define GPIO_CNF_3_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_3_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_4_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_3_BIT_4_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_3_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_CNF_3_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_3_BIT_3_SHIFT)
+#define GPIO_CNF_3_BIT_3_RANGE                  3:3
+#define GPIO_CNF_3_BIT_3_WOFFSET                        0x0
+#define GPIO_CNF_3_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_3_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_3_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_3_BIT_3_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_3_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_CNF_3_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_3_BIT_2_SHIFT)
+#define GPIO_CNF_3_BIT_2_RANGE                  2:2
+#define GPIO_CNF_3_BIT_2_WOFFSET                        0x0
+#define GPIO_CNF_3_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_3_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_2_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_3_BIT_2_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_3_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_CNF_3_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_3_BIT_1_SHIFT)
+#define GPIO_CNF_3_BIT_1_RANGE                  1:1
+#define GPIO_CNF_3_BIT_1_WOFFSET                        0x0
+#define GPIO_CNF_3_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_3_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_1_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_3_BIT_1_GPIO                   _MK_ENUM_CONST(1)
+
+// Configures each pin to be in either GPIO or SFIO  mode
+#define GPIO_CNF_3_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_CNF_3_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_CNF_3_BIT_0_SHIFT)
+#define GPIO_CNF_3_BIT_0_RANGE                  0:0
+#define GPIO_CNF_3_BIT_0_WOFFSET                        0x0
+#define GPIO_CNF_3_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_CNF_3_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_CNF_3_BIT_0_SPIO                   _MK_ENUM_CONST(0)
+#define GPIO_CNF_3_BIT_0_GPIO                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_OE_0  
+#define GPIO_OE_0                       _MK_ADDR_CONST(0x10)
+#define GPIO_OE_0_WORD_COUNT                    0x1
+#define GPIO_OE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_OE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define GPIO_OE_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid.
+#define GPIO_OE_0_BIT_7_SHIFT                   _MK_SHIFT_CONST(7)
+#define GPIO_OE_0_BIT_7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_0_BIT_7_SHIFT)
+#define GPIO_OE_0_BIT_7_RANGE                   7:7
+#define GPIO_OE_0_BIT_7_WOFFSET                 0x0
+#define GPIO_OE_0_BIT_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_0_BIT_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_7_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_0_BIT_7_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_0_BIT_6_SHIFT                   _MK_SHIFT_CONST(6)
+#define GPIO_OE_0_BIT_6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_0_BIT_6_SHIFT)
+#define GPIO_OE_0_BIT_6_RANGE                   6:6
+#define GPIO_OE_0_BIT_6_WOFFSET                 0x0
+#define GPIO_OE_0_BIT_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_0_BIT_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_6_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_0_BIT_6_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_0_BIT_5_SHIFT                   _MK_SHIFT_CONST(5)
+#define GPIO_OE_0_BIT_5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_0_BIT_5_SHIFT)
+#define GPIO_OE_0_BIT_5_RANGE                   5:5
+#define GPIO_OE_0_BIT_5_WOFFSET                 0x0
+#define GPIO_OE_0_BIT_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_0_BIT_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_5_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_0_BIT_5_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_0_BIT_4_SHIFT                   _MK_SHIFT_CONST(4)
+#define GPIO_OE_0_BIT_4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_0_BIT_4_SHIFT)
+#define GPIO_OE_0_BIT_4_RANGE                   4:4
+#define GPIO_OE_0_BIT_4_WOFFSET                 0x0
+#define GPIO_OE_0_BIT_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_0_BIT_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_4_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_0_BIT_4_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_0_BIT_3_SHIFT                   _MK_SHIFT_CONST(3)
+#define GPIO_OE_0_BIT_3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_0_BIT_3_SHIFT)
+#define GPIO_OE_0_BIT_3_RANGE                   3:3
+#define GPIO_OE_0_BIT_3_WOFFSET                 0x0
+#define GPIO_OE_0_BIT_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_0_BIT_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_3_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_0_BIT_3_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_0_BIT_2_SHIFT                   _MK_SHIFT_CONST(2)
+#define GPIO_OE_0_BIT_2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_0_BIT_2_SHIFT)
+#define GPIO_OE_0_BIT_2_RANGE                   2:2
+#define GPIO_OE_0_BIT_2_WOFFSET                 0x0
+#define GPIO_OE_0_BIT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_0_BIT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_2_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_0_BIT_2_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_0_BIT_1_SHIFT                   _MK_SHIFT_CONST(1)
+#define GPIO_OE_0_BIT_1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_0_BIT_1_SHIFT)
+#define GPIO_OE_0_BIT_1_RANGE                   1:1
+#define GPIO_OE_0_BIT_1_WOFFSET                 0x0
+#define GPIO_OE_0_BIT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_0_BIT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_1_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_0_BIT_1_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_0_BIT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define GPIO_OE_0_BIT_0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_0_BIT_0_SHIFT)
+#define GPIO_OE_0_BIT_0_RANGE                   0:0
+#define GPIO_OE_0_BIT_0_WOFFSET                 0x0
+#define GPIO_OE_0_BIT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_0_BIT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_0_BIT_0_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_0_BIT_0_DRIVEN                  _MK_ENUM_CONST(1)
+
+
+// Register GPIO_OE  
+#define GPIO_OE                 _MK_ADDR_CONST(0x10)
+#define GPIO_OE_WORD_COUNT                      0x1
+#define GPIO_OE_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_OE_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define GPIO_OE_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define GPIO_OE_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define GPIO_OE_READ_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_OE_WRITE_MASK                      _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid.
+#define GPIO_OE_BIT_7_SHIFT                     _MK_SHIFT_CONST(7)
+#define GPIO_OE_BIT_7_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_OE_BIT_7_SHIFT)
+#define GPIO_OE_BIT_7_RANGE                     7:7
+#define GPIO_OE_BIT_7_WOFFSET                   0x0
+#define GPIO_OE_BIT_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_OE_BIT_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_7_TRI_STATE                 _MK_ENUM_CONST(0)
+#define GPIO_OE_BIT_7_DRIVEN                    _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_BIT_6_SHIFT                     _MK_SHIFT_CONST(6)
+#define GPIO_OE_BIT_6_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_OE_BIT_6_SHIFT)
+#define GPIO_OE_BIT_6_RANGE                     6:6
+#define GPIO_OE_BIT_6_WOFFSET                   0x0
+#define GPIO_OE_BIT_6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_OE_BIT_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_6_TRI_STATE                 _MK_ENUM_CONST(0)
+#define GPIO_OE_BIT_6_DRIVEN                    _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_BIT_5_SHIFT                     _MK_SHIFT_CONST(5)
+#define GPIO_OE_BIT_5_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_OE_BIT_5_SHIFT)
+#define GPIO_OE_BIT_5_RANGE                     5:5
+#define GPIO_OE_BIT_5_WOFFSET                   0x0
+#define GPIO_OE_BIT_5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_OE_BIT_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_5_TRI_STATE                 _MK_ENUM_CONST(0)
+#define GPIO_OE_BIT_5_DRIVEN                    _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_BIT_4_SHIFT                     _MK_SHIFT_CONST(4)
+#define GPIO_OE_BIT_4_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_OE_BIT_4_SHIFT)
+#define GPIO_OE_BIT_4_RANGE                     4:4
+#define GPIO_OE_BIT_4_WOFFSET                   0x0
+#define GPIO_OE_BIT_4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_OE_BIT_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_4_TRI_STATE                 _MK_ENUM_CONST(0)
+#define GPIO_OE_BIT_4_DRIVEN                    _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_BIT_3_SHIFT                     _MK_SHIFT_CONST(3)
+#define GPIO_OE_BIT_3_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_OE_BIT_3_SHIFT)
+#define GPIO_OE_BIT_3_RANGE                     3:3
+#define GPIO_OE_BIT_3_WOFFSET                   0x0
+#define GPIO_OE_BIT_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_OE_BIT_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_3_TRI_STATE                 _MK_ENUM_CONST(0)
+#define GPIO_OE_BIT_3_DRIVEN                    _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_BIT_2_SHIFT                     _MK_SHIFT_CONST(2)
+#define GPIO_OE_BIT_2_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_OE_BIT_2_SHIFT)
+#define GPIO_OE_BIT_2_RANGE                     2:2
+#define GPIO_OE_BIT_2_WOFFSET                   0x0
+#define GPIO_OE_BIT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_OE_BIT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_2_TRI_STATE                 _MK_ENUM_CONST(0)
+#define GPIO_OE_BIT_2_DRIVEN                    _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_BIT_1_SHIFT                     _MK_SHIFT_CONST(1)
+#define GPIO_OE_BIT_1_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_OE_BIT_1_SHIFT)
+#define GPIO_OE_BIT_1_RANGE                     1:1
+#define GPIO_OE_BIT_1_WOFFSET                   0x0
+#define GPIO_OE_BIT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_OE_BIT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_1_TRI_STATE                 _MK_ENUM_CONST(0)
+#define GPIO_OE_BIT_1_DRIVEN                    _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_BIT_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define GPIO_OE_BIT_0_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_OE_BIT_0_SHIFT)
+#define GPIO_OE_BIT_0_RANGE                     0:0
+#define GPIO_OE_BIT_0_WOFFSET                   0x0
+#define GPIO_OE_BIT_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_OE_BIT_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_OE_BIT_0_TRI_STATE                 _MK_ENUM_CONST(0)
+#define GPIO_OE_BIT_0_DRIVEN                    _MK_ENUM_CONST(1)
+
+
+// Register GPIO_OE_1  
+#define GPIO_OE_1                       _MK_ADDR_CONST(0x14)
+#define GPIO_OE_1_WORD_COUNT                    0x1
+#define GPIO_OE_1_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_OE_1_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_READ_MASK                     _MK_MASK_CONST(0xff)
+#define GPIO_OE_1_WRITE_MASK                    _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid.
+#define GPIO_OE_1_BIT_7_SHIFT                   _MK_SHIFT_CONST(7)
+#define GPIO_OE_1_BIT_7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_1_BIT_7_SHIFT)
+#define GPIO_OE_1_BIT_7_RANGE                   7:7
+#define GPIO_OE_1_BIT_7_WOFFSET                 0x0
+#define GPIO_OE_1_BIT_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_1_BIT_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_7_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_1_BIT_7_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_1_BIT_6_SHIFT                   _MK_SHIFT_CONST(6)
+#define GPIO_OE_1_BIT_6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_1_BIT_6_SHIFT)
+#define GPIO_OE_1_BIT_6_RANGE                   6:6
+#define GPIO_OE_1_BIT_6_WOFFSET                 0x0
+#define GPIO_OE_1_BIT_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_1_BIT_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_6_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_1_BIT_6_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_1_BIT_5_SHIFT                   _MK_SHIFT_CONST(5)
+#define GPIO_OE_1_BIT_5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_1_BIT_5_SHIFT)
+#define GPIO_OE_1_BIT_5_RANGE                   5:5
+#define GPIO_OE_1_BIT_5_WOFFSET                 0x0
+#define GPIO_OE_1_BIT_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_1_BIT_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_5_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_1_BIT_5_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_1_BIT_4_SHIFT                   _MK_SHIFT_CONST(4)
+#define GPIO_OE_1_BIT_4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_1_BIT_4_SHIFT)
+#define GPIO_OE_1_BIT_4_RANGE                   4:4
+#define GPIO_OE_1_BIT_4_WOFFSET                 0x0
+#define GPIO_OE_1_BIT_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_1_BIT_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_4_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_1_BIT_4_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_1_BIT_3_SHIFT                   _MK_SHIFT_CONST(3)
+#define GPIO_OE_1_BIT_3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_1_BIT_3_SHIFT)
+#define GPIO_OE_1_BIT_3_RANGE                   3:3
+#define GPIO_OE_1_BIT_3_WOFFSET                 0x0
+#define GPIO_OE_1_BIT_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_1_BIT_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_3_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_1_BIT_3_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_1_BIT_2_SHIFT                   _MK_SHIFT_CONST(2)
+#define GPIO_OE_1_BIT_2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_1_BIT_2_SHIFT)
+#define GPIO_OE_1_BIT_2_RANGE                   2:2
+#define GPIO_OE_1_BIT_2_WOFFSET                 0x0
+#define GPIO_OE_1_BIT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_1_BIT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_2_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_1_BIT_2_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_1_BIT_1_SHIFT                   _MK_SHIFT_CONST(1)
+#define GPIO_OE_1_BIT_1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_1_BIT_1_SHIFT)
+#define GPIO_OE_1_BIT_1_RANGE                   1:1
+#define GPIO_OE_1_BIT_1_WOFFSET                 0x0
+#define GPIO_OE_1_BIT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_1_BIT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_1_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_1_BIT_1_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_1_BIT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define GPIO_OE_1_BIT_0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_1_BIT_0_SHIFT)
+#define GPIO_OE_1_BIT_0_RANGE                   0:0
+#define GPIO_OE_1_BIT_0_WOFFSET                 0x0
+#define GPIO_OE_1_BIT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_1_BIT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_1_BIT_0_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_1_BIT_0_DRIVEN                  _MK_ENUM_CONST(1)
+
+
+// Register GPIO_OE_2  
+#define GPIO_OE_2                       _MK_ADDR_CONST(0x18)
+#define GPIO_OE_2_WORD_COUNT                    0x1
+#define GPIO_OE_2_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_OE_2_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_READ_MASK                     _MK_MASK_CONST(0xff)
+#define GPIO_OE_2_WRITE_MASK                    _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid.
+#define GPIO_OE_2_BIT_7_SHIFT                   _MK_SHIFT_CONST(7)
+#define GPIO_OE_2_BIT_7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_2_BIT_7_SHIFT)
+#define GPIO_OE_2_BIT_7_RANGE                   7:7
+#define GPIO_OE_2_BIT_7_WOFFSET                 0x0
+#define GPIO_OE_2_BIT_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_2_BIT_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_7_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_2_BIT_7_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_2_BIT_6_SHIFT                   _MK_SHIFT_CONST(6)
+#define GPIO_OE_2_BIT_6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_2_BIT_6_SHIFT)
+#define GPIO_OE_2_BIT_6_RANGE                   6:6
+#define GPIO_OE_2_BIT_6_WOFFSET                 0x0
+#define GPIO_OE_2_BIT_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_2_BIT_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_6_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_2_BIT_6_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_2_BIT_5_SHIFT                   _MK_SHIFT_CONST(5)
+#define GPIO_OE_2_BIT_5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_2_BIT_5_SHIFT)
+#define GPIO_OE_2_BIT_5_RANGE                   5:5
+#define GPIO_OE_2_BIT_5_WOFFSET                 0x0
+#define GPIO_OE_2_BIT_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_2_BIT_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_5_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_2_BIT_5_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_2_BIT_4_SHIFT                   _MK_SHIFT_CONST(4)
+#define GPIO_OE_2_BIT_4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_2_BIT_4_SHIFT)
+#define GPIO_OE_2_BIT_4_RANGE                   4:4
+#define GPIO_OE_2_BIT_4_WOFFSET                 0x0
+#define GPIO_OE_2_BIT_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_2_BIT_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_4_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_2_BIT_4_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_2_BIT_3_SHIFT                   _MK_SHIFT_CONST(3)
+#define GPIO_OE_2_BIT_3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_2_BIT_3_SHIFT)
+#define GPIO_OE_2_BIT_3_RANGE                   3:3
+#define GPIO_OE_2_BIT_3_WOFFSET                 0x0
+#define GPIO_OE_2_BIT_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_2_BIT_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_3_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_2_BIT_3_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_2_BIT_2_SHIFT                   _MK_SHIFT_CONST(2)
+#define GPIO_OE_2_BIT_2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_2_BIT_2_SHIFT)
+#define GPIO_OE_2_BIT_2_RANGE                   2:2
+#define GPIO_OE_2_BIT_2_WOFFSET                 0x0
+#define GPIO_OE_2_BIT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_2_BIT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_2_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_2_BIT_2_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_2_BIT_1_SHIFT                   _MK_SHIFT_CONST(1)
+#define GPIO_OE_2_BIT_1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_2_BIT_1_SHIFT)
+#define GPIO_OE_2_BIT_1_RANGE                   1:1
+#define GPIO_OE_2_BIT_1_WOFFSET                 0x0
+#define GPIO_OE_2_BIT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_2_BIT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_1_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_2_BIT_1_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_2_BIT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define GPIO_OE_2_BIT_0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_2_BIT_0_SHIFT)
+#define GPIO_OE_2_BIT_0_RANGE                   0:0
+#define GPIO_OE_2_BIT_0_WOFFSET                 0x0
+#define GPIO_OE_2_BIT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_2_BIT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_2_BIT_0_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_2_BIT_0_DRIVEN                  _MK_ENUM_CONST(1)
+
+
+// Register GPIO_OE_3  
+#define GPIO_OE_3                       _MK_ADDR_CONST(0x1c)
+#define GPIO_OE_3_WORD_COUNT                    0x1
+#define GPIO_OE_3_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_OE_3_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_READ_MASK                     _MK_MASK_CONST(0xff)
+#define GPIO_OE_3_WRITE_MASK                    _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid.
+#define GPIO_OE_3_BIT_7_SHIFT                   _MK_SHIFT_CONST(7)
+#define GPIO_OE_3_BIT_7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_3_BIT_7_SHIFT)
+#define GPIO_OE_3_BIT_7_RANGE                   7:7
+#define GPIO_OE_3_BIT_7_WOFFSET                 0x0
+#define GPIO_OE_3_BIT_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_3_BIT_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_7_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_3_BIT_7_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_3_BIT_6_SHIFT                   _MK_SHIFT_CONST(6)
+#define GPIO_OE_3_BIT_6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_3_BIT_6_SHIFT)
+#define GPIO_OE_3_BIT_6_RANGE                   6:6
+#define GPIO_OE_3_BIT_6_WOFFSET                 0x0
+#define GPIO_OE_3_BIT_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_3_BIT_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_6_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_3_BIT_6_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_3_BIT_5_SHIFT                   _MK_SHIFT_CONST(5)
+#define GPIO_OE_3_BIT_5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_3_BIT_5_SHIFT)
+#define GPIO_OE_3_BIT_5_RANGE                   5:5
+#define GPIO_OE_3_BIT_5_WOFFSET                 0x0
+#define GPIO_OE_3_BIT_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_3_BIT_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_5_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_3_BIT_5_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_3_BIT_4_SHIFT                   _MK_SHIFT_CONST(4)
+#define GPIO_OE_3_BIT_4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_3_BIT_4_SHIFT)
+#define GPIO_OE_3_BIT_4_RANGE                   4:4
+#define GPIO_OE_3_BIT_4_WOFFSET                 0x0
+#define GPIO_OE_3_BIT_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_3_BIT_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_4_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_3_BIT_4_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_3_BIT_3_SHIFT                   _MK_SHIFT_CONST(3)
+#define GPIO_OE_3_BIT_3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_3_BIT_3_SHIFT)
+#define GPIO_OE_3_BIT_3_RANGE                   3:3
+#define GPIO_OE_3_BIT_3_WOFFSET                 0x0
+#define GPIO_OE_3_BIT_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_3_BIT_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_3_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_3_BIT_3_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_3_BIT_2_SHIFT                   _MK_SHIFT_CONST(2)
+#define GPIO_OE_3_BIT_2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_3_BIT_2_SHIFT)
+#define GPIO_OE_3_BIT_2_RANGE                   2:2
+#define GPIO_OE_3_BIT_2_WOFFSET                 0x0
+#define GPIO_OE_3_BIT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_3_BIT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_2_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_3_BIT_2_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_3_BIT_1_SHIFT                   _MK_SHIFT_CONST(1)
+#define GPIO_OE_3_BIT_1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_3_BIT_1_SHIFT)
+#define GPIO_OE_3_BIT_1_RANGE                   1:1
+#define GPIO_OE_3_BIT_1_WOFFSET                 0x0
+#define GPIO_OE_3_BIT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_3_BIT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_1_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_3_BIT_1_DRIVEN                  _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) must be true for this  condition to be valid
+#define GPIO_OE_3_BIT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define GPIO_OE_3_BIT_0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_OE_3_BIT_0_SHIFT)
+#define GPIO_OE_3_BIT_0_RANGE                   0:0
+#define GPIO_OE_3_BIT_0_WOFFSET                 0x0
+#define GPIO_OE_3_BIT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_OE_3_BIT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_OE_3_BIT_0_TRI_STATE                       _MK_ENUM_CONST(0)
+#define GPIO_OE_3_BIT_0_DRIVEN                  _MK_ENUM_CONST(1)
+
+
+// Register GPIO_OUT_0  
+#define GPIO_OUT_0                      _MK_ADDR_CONST(0x20)
+#define GPIO_OUT_0_WORD_COUNT                   0x1
+#define GPIO_OUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define GPIO_OUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_OUT_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_0_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_OUT_0_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_0_BIT_7_SHIFT)
+#define GPIO_OUT_0_BIT_7_RANGE                  7:7
+#define GPIO_OUT_0_BIT_7_WOFFSET                        0x0
+#define GPIO_OUT_0_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_0_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_7_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_0_BIT_7_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_0_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_OUT_0_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_0_BIT_6_SHIFT)
+#define GPIO_OUT_0_BIT_6_RANGE                  6:6
+#define GPIO_OUT_0_BIT_6_WOFFSET                        0x0
+#define GPIO_OUT_0_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_0_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_6_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_0_BIT_6_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_0_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_OUT_0_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_0_BIT_5_SHIFT)
+#define GPIO_OUT_0_BIT_5_RANGE                  5:5
+#define GPIO_OUT_0_BIT_5_WOFFSET                        0x0
+#define GPIO_OUT_0_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_0_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_5_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_0_BIT_5_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_0_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_OUT_0_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_0_BIT_4_SHIFT)
+#define GPIO_OUT_0_BIT_4_RANGE                  4:4
+#define GPIO_OUT_0_BIT_4_WOFFSET                        0x0
+#define GPIO_OUT_0_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_0_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_4_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_0_BIT_4_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_0_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_OUT_0_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_0_BIT_3_SHIFT)
+#define GPIO_OUT_0_BIT_3_RANGE                  3:3
+#define GPIO_OUT_0_BIT_3_WOFFSET                        0x0
+#define GPIO_OUT_0_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_0_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_3_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_0_BIT_3_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_0_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_OUT_0_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_0_BIT_2_SHIFT)
+#define GPIO_OUT_0_BIT_2_RANGE                  2:2
+#define GPIO_OUT_0_BIT_2_WOFFSET                        0x0
+#define GPIO_OUT_0_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_0_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_2_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_0_BIT_2_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_0_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_OUT_0_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_0_BIT_1_SHIFT)
+#define GPIO_OUT_0_BIT_1_RANGE                  1:1
+#define GPIO_OUT_0_BIT_1_WOFFSET                        0x0
+#define GPIO_OUT_0_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_0_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_1_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_0_BIT_1_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_0_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_OUT_0_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_0_BIT_0_SHIFT)
+#define GPIO_OUT_0_BIT_0_RANGE                  0:0
+#define GPIO_OUT_0_BIT_0_WOFFSET                        0x0
+#define GPIO_OUT_0_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_0_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_0_BIT_0_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_0_BIT_0_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_OUT  
+#define GPIO_OUT                        _MK_ADDR_CONST(0x20)
+#define GPIO_OUT_WORD_COUNT                     0x1
+#define GPIO_OUT_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define GPIO_OUT_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define GPIO_OUT_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define GPIO_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_READ_MASK                      _MK_MASK_CONST(0xff)
+#define GPIO_OUT_WRITE_MASK                     _MK_MASK_CONST(0xff)
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_BIT_7_SHIFT                    _MK_SHIFT_CONST(7)
+#define GPIO_OUT_BIT_7_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_OUT_BIT_7_SHIFT)
+#define GPIO_OUT_BIT_7_RANGE                    7:7
+#define GPIO_OUT_BIT_7_WOFFSET                  0x0
+#define GPIO_OUT_BIT_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_OUT_BIT_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_7_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_OUT_BIT_7_HIGH                     _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_BIT_6_SHIFT                    _MK_SHIFT_CONST(6)
+#define GPIO_OUT_BIT_6_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_OUT_BIT_6_SHIFT)
+#define GPIO_OUT_BIT_6_RANGE                    6:6
+#define GPIO_OUT_BIT_6_WOFFSET                  0x0
+#define GPIO_OUT_BIT_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_OUT_BIT_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_6_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_OUT_BIT_6_HIGH                     _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_BIT_5_SHIFT                    _MK_SHIFT_CONST(5)
+#define GPIO_OUT_BIT_5_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_OUT_BIT_5_SHIFT)
+#define GPIO_OUT_BIT_5_RANGE                    5:5
+#define GPIO_OUT_BIT_5_WOFFSET                  0x0
+#define GPIO_OUT_BIT_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_OUT_BIT_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_5_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_OUT_BIT_5_HIGH                     _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_BIT_4_SHIFT                    _MK_SHIFT_CONST(4)
+#define GPIO_OUT_BIT_4_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_OUT_BIT_4_SHIFT)
+#define GPIO_OUT_BIT_4_RANGE                    4:4
+#define GPIO_OUT_BIT_4_WOFFSET                  0x0
+#define GPIO_OUT_BIT_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_OUT_BIT_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_4_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_OUT_BIT_4_HIGH                     _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_BIT_3_SHIFT                    _MK_SHIFT_CONST(3)
+#define GPIO_OUT_BIT_3_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_OUT_BIT_3_SHIFT)
+#define GPIO_OUT_BIT_3_RANGE                    3:3
+#define GPIO_OUT_BIT_3_WOFFSET                  0x0
+#define GPIO_OUT_BIT_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_OUT_BIT_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_3_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_OUT_BIT_3_HIGH                     _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_BIT_2_SHIFT                    _MK_SHIFT_CONST(2)
+#define GPIO_OUT_BIT_2_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_OUT_BIT_2_SHIFT)
+#define GPIO_OUT_BIT_2_RANGE                    2:2
+#define GPIO_OUT_BIT_2_WOFFSET                  0x0
+#define GPIO_OUT_BIT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_OUT_BIT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_2_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_OUT_BIT_2_HIGH                     _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_BIT_1_SHIFT                    _MK_SHIFT_CONST(1)
+#define GPIO_OUT_BIT_1_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_OUT_BIT_1_SHIFT)
+#define GPIO_OUT_BIT_1_RANGE                    1:1
+#define GPIO_OUT_BIT_1_WOFFSET                  0x0
+#define GPIO_OUT_BIT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_OUT_BIT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_1_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_OUT_BIT_1_HIGH                     _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_BIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define GPIO_OUT_BIT_0_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_OUT_BIT_0_SHIFT)
+#define GPIO_OUT_BIT_0_RANGE                    0:0
+#define GPIO_OUT_BIT_0_WOFFSET                  0x0
+#define GPIO_OUT_BIT_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_OUT_BIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_OUT_BIT_0_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_OUT_BIT_0_HIGH                     _MK_ENUM_CONST(1)
+
+
+// Register GPIO_OUT_1  
+#define GPIO_OUT_1                      _MK_ADDR_CONST(0x24)
+#define GPIO_OUT_1_WORD_COUNT                   0x1
+#define GPIO_OUT_1_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define GPIO_OUT_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_OUT_1_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_1_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_OUT_1_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_1_BIT_7_SHIFT)
+#define GPIO_OUT_1_BIT_7_RANGE                  7:7
+#define GPIO_OUT_1_BIT_7_WOFFSET                        0x0
+#define GPIO_OUT_1_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_1_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_7_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_1_BIT_7_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_1_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_OUT_1_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_1_BIT_6_SHIFT)
+#define GPIO_OUT_1_BIT_6_RANGE                  6:6
+#define GPIO_OUT_1_BIT_6_WOFFSET                        0x0
+#define GPIO_OUT_1_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_1_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_6_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_1_BIT_6_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_1_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_OUT_1_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_1_BIT_5_SHIFT)
+#define GPIO_OUT_1_BIT_5_RANGE                  5:5
+#define GPIO_OUT_1_BIT_5_WOFFSET                        0x0
+#define GPIO_OUT_1_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_1_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_5_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_1_BIT_5_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_1_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_OUT_1_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_1_BIT_4_SHIFT)
+#define GPIO_OUT_1_BIT_4_RANGE                  4:4
+#define GPIO_OUT_1_BIT_4_WOFFSET                        0x0
+#define GPIO_OUT_1_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_1_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_4_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_1_BIT_4_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_1_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_OUT_1_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_1_BIT_3_SHIFT)
+#define GPIO_OUT_1_BIT_3_RANGE                  3:3
+#define GPIO_OUT_1_BIT_3_WOFFSET                        0x0
+#define GPIO_OUT_1_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_1_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_3_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_1_BIT_3_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_1_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_OUT_1_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_1_BIT_2_SHIFT)
+#define GPIO_OUT_1_BIT_2_RANGE                  2:2
+#define GPIO_OUT_1_BIT_2_WOFFSET                        0x0
+#define GPIO_OUT_1_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_1_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_2_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_1_BIT_2_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_1_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_OUT_1_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_1_BIT_1_SHIFT)
+#define GPIO_OUT_1_BIT_1_RANGE                  1:1
+#define GPIO_OUT_1_BIT_1_WOFFSET                        0x0
+#define GPIO_OUT_1_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_1_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_1_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_1_BIT_1_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_1_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_OUT_1_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_1_BIT_0_SHIFT)
+#define GPIO_OUT_1_BIT_0_RANGE                  0:0
+#define GPIO_OUT_1_BIT_0_WOFFSET                        0x0
+#define GPIO_OUT_1_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_1_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_1_BIT_0_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_1_BIT_0_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_OUT_2  
+#define GPIO_OUT_2                      _MK_ADDR_CONST(0x28)
+#define GPIO_OUT_2_WORD_COUNT                   0x1
+#define GPIO_OUT_2_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define GPIO_OUT_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_OUT_2_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_2_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_OUT_2_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_2_BIT_7_SHIFT)
+#define GPIO_OUT_2_BIT_7_RANGE                  7:7
+#define GPIO_OUT_2_BIT_7_WOFFSET                        0x0
+#define GPIO_OUT_2_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_2_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_7_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_2_BIT_7_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_2_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_OUT_2_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_2_BIT_6_SHIFT)
+#define GPIO_OUT_2_BIT_6_RANGE                  6:6
+#define GPIO_OUT_2_BIT_6_WOFFSET                        0x0
+#define GPIO_OUT_2_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_2_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_6_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_2_BIT_6_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_2_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_OUT_2_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_2_BIT_5_SHIFT)
+#define GPIO_OUT_2_BIT_5_RANGE                  5:5
+#define GPIO_OUT_2_BIT_5_WOFFSET                        0x0
+#define GPIO_OUT_2_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_2_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_5_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_2_BIT_5_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_2_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_OUT_2_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_2_BIT_4_SHIFT)
+#define GPIO_OUT_2_BIT_4_RANGE                  4:4
+#define GPIO_OUT_2_BIT_4_WOFFSET                        0x0
+#define GPIO_OUT_2_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_2_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_4_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_2_BIT_4_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_2_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_OUT_2_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_2_BIT_3_SHIFT)
+#define GPIO_OUT_2_BIT_3_RANGE                  3:3
+#define GPIO_OUT_2_BIT_3_WOFFSET                        0x0
+#define GPIO_OUT_2_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_2_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_3_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_2_BIT_3_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_2_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_OUT_2_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_2_BIT_2_SHIFT)
+#define GPIO_OUT_2_BIT_2_RANGE                  2:2
+#define GPIO_OUT_2_BIT_2_WOFFSET                        0x0
+#define GPIO_OUT_2_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_2_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_2_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_2_BIT_2_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_2_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_OUT_2_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_2_BIT_1_SHIFT)
+#define GPIO_OUT_2_BIT_1_RANGE                  1:1
+#define GPIO_OUT_2_BIT_1_WOFFSET                        0x0
+#define GPIO_OUT_2_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_2_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_1_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_2_BIT_1_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_2_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_OUT_2_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_2_BIT_0_SHIFT)
+#define GPIO_OUT_2_BIT_0_RANGE                  0:0
+#define GPIO_OUT_2_BIT_0_WOFFSET                        0x0
+#define GPIO_OUT_2_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_2_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_2_BIT_0_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_2_BIT_0_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_OUT_3  
+#define GPIO_OUT_3                      _MK_ADDR_CONST(0x2c)
+#define GPIO_OUT_3_WORD_COUNT                   0x1
+#define GPIO_OUT_3_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define GPIO_OUT_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_OUT_3_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_3_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_OUT_3_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_3_BIT_7_SHIFT)
+#define GPIO_OUT_3_BIT_7_RANGE                  7:7
+#define GPIO_OUT_3_BIT_7_WOFFSET                        0x0
+#define GPIO_OUT_3_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_3_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_7_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_3_BIT_7_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_3_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_OUT_3_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_3_BIT_6_SHIFT)
+#define GPIO_OUT_3_BIT_6_RANGE                  6:6
+#define GPIO_OUT_3_BIT_6_WOFFSET                        0x0
+#define GPIO_OUT_3_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_3_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_6_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_3_BIT_6_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_3_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_OUT_3_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_3_BIT_5_SHIFT)
+#define GPIO_OUT_3_BIT_5_RANGE                  5:5
+#define GPIO_OUT_3_BIT_5_WOFFSET                        0x0
+#define GPIO_OUT_3_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_3_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_5_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_3_BIT_5_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_3_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_OUT_3_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_3_BIT_4_SHIFT)
+#define GPIO_OUT_3_BIT_4_RANGE                  4:4
+#define GPIO_OUT_3_BIT_4_WOFFSET                        0x0
+#define GPIO_OUT_3_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_3_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_4_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_3_BIT_4_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_3_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_OUT_3_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_3_BIT_3_SHIFT)
+#define GPIO_OUT_3_BIT_3_RANGE                  3:3
+#define GPIO_OUT_3_BIT_3_WOFFSET                        0x0
+#define GPIO_OUT_3_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_3_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_3_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_3_BIT_3_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_3_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_OUT_3_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_3_BIT_2_SHIFT)
+#define GPIO_OUT_3_BIT_2_RANGE                  2:2
+#define GPIO_OUT_3_BIT_2_WOFFSET                        0x0
+#define GPIO_OUT_3_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_3_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_2_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_3_BIT_2_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_3_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_OUT_3_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_3_BIT_1_SHIFT)
+#define GPIO_OUT_3_BIT_1_RANGE                  1:1
+#define GPIO_OUT_3_BIT_1_WOFFSET                        0x0
+#define GPIO_OUT_3_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_3_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_1_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_3_BIT_1_HIGH                   _MK_ENUM_CONST(1)
+
+// GPIO_CNF.x=1 (in GPIO mode) AND GPIO_OE.x=1 (GPIO  output enabled) mxst be true for this to be a valid state
+#define GPIO_OUT_3_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_OUT_3_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_OUT_3_BIT_0_SHIFT)
+#define GPIO_OUT_3_BIT_0_RANGE                  0:0
+#define GPIO_OUT_3_BIT_0_WOFFSET                        0x0
+#define GPIO_OUT_3_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_OUT_3_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_OUT_3_BIT_0_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_OUT_3_BIT_0_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_IN_0  
+#define GPIO_IN_0                       _MK_ADDR_CONST(0x30)
+#define GPIO_IN_0_WORD_COUNT                    0x1
+#define GPIO_IN_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_IN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define GPIO_IN_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_IN_0_BIT_7_SHIFT                   _MK_SHIFT_CONST(7)
+#define GPIO_IN_0_BIT_7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_0_BIT_7_SHIFT)
+#define GPIO_IN_0_BIT_7_RANGE                   7:7
+#define GPIO_IN_0_BIT_7_WOFFSET                 0x0
+#define GPIO_IN_0_BIT_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_0_BIT_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_7_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_0_BIT_7_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_0_BIT_6_SHIFT                   _MK_SHIFT_CONST(6)
+#define GPIO_IN_0_BIT_6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_0_BIT_6_SHIFT)
+#define GPIO_IN_0_BIT_6_RANGE                   6:6
+#define GPIO_IN_0_BIT_6_WOFFSET                 0x0
+#define GPIO_IN_0_BIT_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_0_BIT_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_6_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_0_BIT_6_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_0_BIT_5_SHIFT                   _MK_SHIFT_CONST(5)
+#define GPIO_IN_0_BIT_5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_0_BIT_5_SHIFT)
+#define GPIO_IN_0_BIT_5_RANGE                   5:5
+#define GPIO_IN_0_BIT_5_WOFFSET                 0x0
+#define GPIO_IN_0_BIT_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_0_BIT_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_5_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_0_BIT_5_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_0_BIT_4_SHIFT                   _MK_SHIFT_CONST(4)
+#define GPIO_IN_0_BIT_4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_0_BIT_4_SHIFT)
+#define GPIO_IN_0_BIT_4_RANGE                   4:4
+#define GPIO_IN_0_BIT_4_WOFFSET                 0x0
+#define GPIO_IN_0_BIT_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_0_BIT_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_4_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_0_BIT_4_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_0_BIT_3_SHIFT                   _MK_SHIFT_CONST(3)
+#define GPIO_IN_0_BIT_3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_0_BIT_3_SHIFT)
+#define GPIO_IN_0_BIT_3_RANGE                   3:3
+#define GPIO_IN_0_BIT_3_WOFFSET                 0x0
+#define GPIO_IN_0_BIT_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_0_BIT_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_3_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_0_BIT_3_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_0_BIT_2_SHIFT                   _MK_SHIFT_CONST(2)
+#define GPIO_IN_0_BIT_2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_0_BIT_2_SHIFT)
+#define GPIO_IN_0_BIT_2_RANGE                   2:2
+#define GPIO_IN_0_BIT_2_WOFFSET                 0x0
+#define GPIO_IN_0_BIT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_0_BIT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_2_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_0_BIT_2_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_0_BIT_1_SHIFT                   _MK_SHIFT_CONST(1)
+#define GPIO_IN_0_BIT_1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_0_BIT_1_SHIFT)
+#define GPIO_IN_0_BIT_1_RANGE                   1:1
+#define GPIO_IN_0_BIT_1_WOFFSET                 0x0
+#define GPIO_IN_0_BIT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_0_BIT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_1_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_0_BIT_1_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_0_BIT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define GPIO_IN_0_BIT_0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_0_BIT_0_SHIFT)
+#define GPIO_IN_0_BIT_0_RANGE                   0:0
+#define GPIO_IN_0_BIT_0_WOFFSET                 0x0
+#define GPIO_IN_0_BIT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_0_BIT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_0_BIT_0_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_0_BIT_0_HIGH                    _MK_ENUM_CONST(1)
+
+
+// Register GPIO_IN  
+#define GPIO_IN                 _MK_ADDR_CONST(0x30)
+#define GPIO_IN_WORD_COUNT                      0x1
+#define GPIO_IN_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_IN_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define GPIO_IN_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define GPIO_IN_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define GPIO_IN_READ_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_IN_WRITE_MASK                      _MK_MASK_CONST(0xff)
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_IN_BIT_7_SHIFT                     _MK_SHIFT_CONST(7)
+#define GPIO_IN_BIT_7_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_IN_BIT_7_SHIFT)
+#define GPIO_IN_BIT_7_RANGE                     7:7
+#define GPIO_IN_BIT_7_WOFFSET                   0x0
+#define GPIO_IN_BIT_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_IN_BIT_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_7_LOW                       _MK_ENUM_CONST(0)
+#define GPIO_IN_BIT_7_HIGH                      _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_BIT_6_SHIFT                     _MK_SHIFT_CONST(6)
+#define GPIO_IN_BIT_6_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_IN_BIT_6_SHIFT)
+#define GPIO_IN_BIT_6_RANGE                     6:6
+#define GPIO_IN_BIT_6_WOFFSET                   0x0
+#define GPIO_IN_BIT_6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_IN_BIT_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_6_LOW                       _MK_ENUM_CONST(0)
+#define GPIO_IN_BIT_6_HIGH                      _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_BIT_5_SHIFT                     _MK_SHIFT_CONST(5)
+#define GPIO_IN_BIT_5_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_IN_BIT_5_SHIFT)
+#define GPIO_IN_BIT_5_RANGE                     5:5
+#define GPIO_IN_BIT_5_WOFFSET                   0x0
+#define GPIO_IN_BIT_5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_IN_BIT_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_5_LOW                       _MK_ENUM_CONST(0)
+#define GPIO_IN_BIT_5_HIGH                      _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_BIT_4_SHIFT                     _MK_SHIFT_CONST(4)
+#define GPIO_IN_BIT_4_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_IN_BIT_4_SHIFT)
+#define GPIO_IN_BIT_4_RANGE                     4:4
+#define GPIO_IN_BIT_4_WOFFSET                   0x0
+#define GPIO_IN_BIT_4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_IN_BIT_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_4_LOW                       _MK_ENUM_CONST(0)
+#define GPIO_IN_BIT_4_HIGH                      _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_BIT_3_SHIFT                     _MK_SHIFT_CONST(3)
+#define GPIO_IN_BIT_3_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_IN_BIT_3_SHIFT)
+#define GPIO_IN_BIT_3_RANGE                     3:3
+#define GPIO_IN_BIT_3_WOFFSET                   0x0
+#define GPIO_IN_BIT_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_IN_BIT_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_3_LOW                       _MK_ENUM_CONST(0)
+#define GPIO_IN_BIT_3_HIGH                      _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_BIT_2_SHIFT                     _MK_SHIFT_CONST(2)
+#define GPIO_IN_BIT_2_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_IN_BIT_2_SHIFT)
+#define GPIO_IN_BIT_2_RANGE                     2:2
+#define GPIO_IN_BIT_2_WOFFSET                   0x0
+#define GPIO_IN_BIT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_IN_BIT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_2_LOW                       _MK_ENUM_CONST(0)
+#define GPIO_IN_BIT_2_HIGH                      _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_BIT_1_SHIFT                     _MK_SHIFT_CONST(1)
+#define GPIO_IN_BIT_1_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_IN_BIT_1_SHIFT)
+#define GPIO_IN_BIT_1_RANGE                     1:1
+#define GPIO_IN_BIT_1_WOFFSET                   0x0
+#define GPIO_IN_BIT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_IN_BIT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_1_LOW                       _MK_ENUM_CONST(0)
+#define GPIO_IN_BIT_1_HIGH                      _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_BIT_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define GPIO_IN_BIT_0_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_IN_BIT_0_SHIFT)
+#define GPIO_IN_BIT_0_RANGE                     0:0
+#define GPIO_IN_BIT_0_WOFFSET                   0x0
+#define GPIO_IN_BIT_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_IN_BIT_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_IN_BIT_0_LOW                       _MK_ENUM_CONST(0)
+#define GPIO_IN_BIT_0_HIGH                      _MK_ENUM_CONST(1)
+
+
+// Register GPIO_IN_1  
+#define GPIO_IN_1                       _MK_ADDR_CONST(0x34)
+#define GPIO_IN_1_WORD_COUNT                    0x1
+#define GPIO_IN_1_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_IN_1_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_READ_MASK                     _MK_MASK_CONST(0xff)
+#define GPIO_IN_1_WRITE_MASK                    _MK_MASK_CONST(0xff)
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_IN_1_BIT_7_SHIFT                   _MK_SHIFT_CONST(7)
+#define GPIO_IN_1_BIT_7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_1_BIT_7_SHIFT)
+#define GPIO_IN_1_BIT_7_RANGE                   7:7
+#define GPIO_IN_1_BIT_7_WOFFSET                 0x0
+#define GPIO_IN_1_BIT_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_1_BIT_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_7_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_1_BIT_7_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_1_BIT_6_SHIFT                   _MK_SHIFT_CONST(6)
+#define GPIO_IN_1_BIT_6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_1_BIT_6_SHIFT)
+#define GPIO_IN_1_BIT_6_RANGE                   6:6
+#define GPIO_IN_1_BIT_6_WOFFSET                 0x0
+#define GPIO_IN_1_BIT_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_1_BIT_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_6_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_1_BIT_6_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_1_BIT_5_SHIFT                   _MK_SHIFT_CONST(5)
+#define GPIO_IN_1_BIT_5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_1_BIT_5_SHIFT)
+#define GPIO_IN_1_BIT_5_RANGE                   5:5
+#define GPIO_IN_1_BIT_5_WOFFSET                 0x0
+#define GPIO_IN_1_BIT_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_1_BIT_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_5_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_1_BIT_5_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_1_BIT_4_SHIFT                   _MK_SHIFT_CONST(4)
+#define GPIO_IN_1_BIT_4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_1_BIT_4_SHIFT)
+#define GPIO_IN_1_BIT_4_RANGE                   4:4
+#define GPIO_IN_1_BIT_4_WOFFSET                 0x0
+#define GPIO_IN_1_BIT_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_1_BIT_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_4_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_1_BIT_4_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_1_BIT_3_SHIFT                   _MK_SHIFT_CONST(3)
+#define GPIO_IN_1_BIT_3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_1_BIT_3_SHIFT)
+#define GPIO_IN_1_BIT_3_RANGE                   3:3
+#define GPIO_IN_1_BIT_3_WOFFSET                 0x0
+#define GPIO_IN_1_BIT_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_1_BIT_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_3_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_1_BIT_3_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_1_BIT_2_SHIFT                   _MK_SHIFT_CONST(2)
+#define GPIO_IN_1_BIT_2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_1_BIT_2_SHIFT)
+#define GPIO_IN_1_BIT_2_RANGE                   2:2
+#define GPIO_IN_1_BIT_2_WOFFSET                 0x0
+#define GPIO_IN_1_BIT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_1_BIT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_2_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_1_BIT_2_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_1_BIT_1_SHIFT                   _MK_SHIFT_CONST(1)
+#define GPIO_IN_1_BIT_1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_1_BIT_1_SHIFT)
+#define GPIO_IN_1_BIT_1_RANGE                   1:1
+#define GPIO_IN_1_BIT_1_WOFFSET                 0x0
+#define GPIO_IN_1_BIT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_1_BIT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_1_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_1_BIT_1_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_1_BIT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define GPIO_IN_1_BIT_0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_1_BIT_0_SHIFT)
+#define GPIO_IN_1_BIT_0_RANGE                   0:0
+#define GPIO_IN_1_BIT_0_WOFFSET                 0x0
+#define GPIO_IN_1_BIT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_1_BIT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_1_BIT_0_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_1_BIT_0_HIGH                    _MK_ENUM_CONST(1)
+
+
+// Register GPIO_IN_2  
+#define GPIO_IN_2                       _MK_ADDR_CONST(0x38)
+#define GPIO_IN_2_WORD_COUNT                    0x1
+#define GPIO_IN_2_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_IN_2_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_READ_MASK                     _MK_MASK_CONST(0xff)
+#define GPIO_IN_2_WRITE_MASK                    _MK_MASK_CONST(0xff)
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_IN_2_BIT_7_SHIFT                   _MK_SHIFT_CONST(7)
+#define GPIO_IN_2_BIT_7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_2_BIT_7_SHIFT)
+#define GPIO_IN_2_BIT_7_RANGE                   7:7
+#define GPIO_IN_2_BIT_7_WOFFSET                 0x0
+#define GPIO_IN_2_BIT_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_2_BIT_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_7_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_2_BIT_7_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_2_BIT_6_SHIFT                   _MK_SHIFT_CONST(6)
+#define GPIO_IN_2_BIT_6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_2_BIT_6_SHIFT)
+#define GPIO_IN_2_BIT_6_RANGE                   6:6
+#define GPIO_IN_2_BIT_6_WOFFSET                 0x0
+#define GPIO_IN_2_BIT_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_2_BIT_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_6_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_2_BIT_6_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_2_BIT_5_SHIFT                   _MK_SHIFT_CONST(5)
+#define GPIO_IN_2_BIT_5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_2_BIT_5_SHIFT)
+#define GPIO_IN_2_BIT_5_RANGE                   5:5
+#define GPIO_IN_2_BIT_5_WOFFSET                 0x0
+#define GPIO_IN_2_BIT_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_2_BIT_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_5_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_2_BIT_5_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_2_BIT_4_SHIFT                   _MK_SHIFT_CONST(4)
+#define GPIO_IN_2_BIT_4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_2_BIT_4_SHIFT)
+#define GPIO_IN_2_BIT_4_RANGE                   4:4
+#define GPIO_IN_2_BIT_4_WOFFSET                 0x0
+#define GPIO_IN_2_BIT_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_2_BIT_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_4_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_2_BIT_4_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_2_BIT_3_SHIFT                   _MK_SHIFT_CONST(3)
+#define GPIO_IN_2_BIT_3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_2_BIT_3_SHIFT)
+#define GPIO_IN_2_BIT_3_RANGE                   3:3
+#define GPIO_IN_2_BIT_3_WOFFSET                 0x0
+#define GPIO_IN_2_BIT_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_2_BIT_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_3_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_2_BIT_3_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_2_BIT_2_SHIFT                   _MK_SHIFT_CONST(2)
+#define GPIO_IN_2_BIT_2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_2_BIT_2_SHIFT)
+#define GPIO_IN_2_BIT_2_RANGE                   2:2
+#define GPIO_IN_2_BIT_2_WOFFSET                 0x0
+#define GPIO_IN_2_BIT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_2_BIT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_2_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_2_BIT_2_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_2_BIT_1_SHIFT                   _MK_SHIFT_CONST(1)
+#define GPIO_IN_2_BIT_1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_2_BIT_1_SHIFT)
+#define GPIO_IN_2_BIT_1_RANGE                   1:1
+#define GPIO_IN_2_BIT_1_WOFFSET                 0x0
+#define GPIO_IN_2_BIT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_2_BIT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_1_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_2_BIT_1_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_2_BIT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define GPIO_IN_2_BIT_0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_2_BIT_0_SHIFT)
+#define GPIO_IN_2_BIT_0_RANGE                   0:0
+#define GPIO_IN_2_BIT_0_WOFFSET                 0x0
+#define GPIO_IN_2_BIT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_2_BIT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_2_BIT_0_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_2_BIT_0_HIGH                    _MK_ENUM_CONST(1)
+
+
+// Register GPIO_IN_3  
+#define GPIO_IN_3                       _MK_ADDR_CONST(0x3c)
+#define GPIO_IN_3_WORD_COUNT                    0x1
+#define GPIO_IN_3_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_IN_3_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_READ_MASK                     _MK_MASK_CONST(0xff)
+#define GPIO_IN_3_WRITE_MASK                    _MK_MASK_CONST(0xff)
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_IN_3_BIT_7_SHIFT                   _MK_SHIFT_CONST(7)
+#define GPIO_IN_3_BIT_7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_3_BIT_7_SHIFT)
+#define GPIO_IN_3_BIT_7_RANGE                   7:7
+#define GPIO_IN_3_BIT_7_WOFFSET                 0x0
+#define GPIO_IN_3_BIT_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_3_BIT_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_7_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_3_BIT_7_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_3_BIT_6_SHIFT                   _MK_SHIFT_CONST(6)
+#define GPIO_IN_3_BIT_6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_3_BIT_6_SHIFT)
+#define GPIO_IN_3_BIT_6_RANGE                   6:6
+#define GPIO_IN_3_BIT_6_WOFFSET                 0x0
+#define GPIO_IN_3_BIT_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_3_BIT_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_6_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_3_BIT_6_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_3_BIT_5_SHIFT                   _MK_SHIFT_CONST(5)
+#define GPIO_IN_3_BIT_5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_3_BIT_5_SHIFT)
+#define GPIO_IN_3_BIT_5_RANGE                   5:5
+#define GPIO_IN_3_BIT_5_WOFFSET                 0x0
+#define GPIO_IN_3_BIT_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_3_BIT_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_5_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_3_BIT_5_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_3_BIT_4_SHIFT                   _MK_SHIFT_CONST(4)
+#define GPIO_IN_3_BIT_4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_3_BIT_4_SHIFT)
+#define GPIO_IN_3_BIT_4_RANGE                   4:4
+#define GPIO_IN_3_BIT_4_WOFFSET                 0x0
+#define GPIO_IN_3_BIT_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_3_BIT_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_4_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_3_BIT_4_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_3_BIT_3_SHIFT                   _MK_SHIFT_CONST(3)
+#define GPIO_IN_3_BIT_3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_3_BIT_3_SHIFT)
+#define GPIO_IN_3_BIT_3_RANGE                   3:3
+#define GPIO_IN_3_BIT_3_WOFFSET                 0x0
+#define GPIO_IN_3_BIT_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_3_BIT_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_3_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_3_BIT_3_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_3_BIT_2_SHIFT                   _MK_SHIFT_CONST(2)
+#define GPIO_IN_3_BIT_2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_3_BIT_2_SHIFT)
+#define GPIO_IN_3_BIT_2_RANGE                   2:2
+#define GPIO_IN_3_BIT_2_WOFFSET                 0x0
+#define GPIO_IN_3_BIT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_3_BIT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_2_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_3_BIT_2_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid
+#define GPIO_IN_3_BIT_1_SHIFT                   _MK_SHIFT_CONST(1)
+#define GPIO_IN_3_BIT_1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_3_BIT_1_SHIFT)
+#define GPIO_IN_3_BIT_1_RANGE                   1:1
+#define GPIO_IN_3_BIT_1_WOFFSET                 0x0
+#define GPIO_IN_3_BIT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_3_BIT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_1_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_3_BIT_1_HIGH                    _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid 
+#define GPIO_IN_3_BIT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define GPIO_IN_3_BIT_0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_IN_3_BIT_0_SHIFT)
+#define GPIO_IN_3_BIT_0_RANGE                   0:0
+#define GPIO_IN_3_BIT_0_WOFFSET                 0x0
+#define GPIO_IN_3_BIT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_IN_3_BIT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_IN_3_BIT_0_LOW                     _MK_ENUM_CONST(0)
+#define GPIO_IN_3_BIT_0_HIGH                    _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_STA_0  
+#define GPIO_INT_STA_0                  _MK_ADDR_CONST(0x40)
+#define GPIO_INT_STA_0_WORD_COUNT                       0x1
+#define GPIO_INT_STA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_STA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_STA_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_0_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_STA_0_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_0_BIT_7_SHIFT)
+#define GPIO_INT_STA_0_BIT_7_RANGE                      7:7
+#define GPIO_INT_STA_0_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_STA_0_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_0_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_7_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_0_BIT_7_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_0_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_STA_0_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_0_BIT_6_SHIFT)
+#define GPIO_INT_STA_0_BIT_6_RANGE                      6:6
+#define GPIO_INT_STA_0_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_STA_0_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_0_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_6_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_0_BIT_6_ACTIVE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid. 
+#define GPIO_INT_STA_0_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_STA_0_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_0_BIT_5_SHIFT)
+#define GPIO_INT_STA_0_BIT_5_RANGE                      5:5
+#define GPIO_INT_STA_0_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_STA_0_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_0_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_5_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_0_BIT_5_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_0_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_STA_0_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_0_BIT_4_SHIFT)
+#define GPIO_INT_STA_0_BIT_4_RANGE                      4:4
+#define GPIO_INT_STA_0_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_STA_0_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_0_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_4_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_0_BIT_4_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_0_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_STA_0_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_0_BIT_3_SHIFT)
+#define GPIO_INT_STA_0_BIT_3_RANGE                      3:3
+#define GPIO_INT_STA_0_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_STA_0_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_0_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_3_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_0_BIT_3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_0_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_STA_0_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_0_BIT_2_SHIFT)
+#define GPIO_INT_STA_0_BIT_2_RANGE                      2:2
+#define GPIO_INT_STA_0_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_STA_0_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_0_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_2_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_0_BIT_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid. 
+#define GPIO_INT_STA_0_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_STA_0_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_0_BIT_1_SHIFT)
+#define GPIO_INT_STA_0_BIT_1_RANGE                      1:1
+#define GPIO_INT_STA_0_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_STA_0_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_0_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_1_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_0_BIT_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_0_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_STA_0_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_0_BIT_0_SHIFT)
+#define GPIO_INT_STA_0_BIT_0_RANGE                      0:0
+#define GPIO_INT_STA_0_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_STA_0_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_0_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_0_BIT_0_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_0_BIT_0_ACTIVE                     _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_STA  
+#define GPIO_INT_STA                    _MK_ADDR_CONST(0x40)
+#define GPIO_INT_STA_WORD_COUNT                         0x1
+#define GPIO_INT_STA_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define GPIO_INT_STA_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_READ_MASK                  _MK_MASK_CONST(0xff)
+#define GPIO_INT_STA_WRITE_MASK                         _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_BIT_7_SHIFT                        _MK_SHIFT_CONST(7)
+#define GPIO_INT_STA_BIT_7_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_STA_BIT_7_SHIFT)
+#define GPIO_INT_STA_BIT_7_RANGE                        7:7
+#define GPIO_INT_STA_BIT_7_WOFFSET                      0x0
+#define GPIO_INT_STA_BIT_7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_BIT_7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_7_IN_ACTIVE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_BIT_7_ACTIVE                       _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_BIT_6_SHIFT                        _MK_SHIFT_CONST(6)
+#define GPIO_INT_STA_BIT_6_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_STA_BIT_6_SHIFT)
+#define GPIO_INT_STA_BIT_6_RANGE                        6:6
+#define GPIO_INT_STA_BIT_6_WOFFSET                      0x0
+#define GPIO_INT_STA_BIT_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_BIT_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_6_IN_ACTIVE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_BIT_6_ACTIVE                       _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid. 
+#define GPIO_INT_STA_BIT_5_SHIFT                        _MK_SHIFT_CONST(5)
+#define GPIO_INT_STA_BIT_5_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_STA_BIT_5_SHIFT)
+#define GPIO_INT_STA_BIT_5_RANGE                        5:5
+#define GPIO_INT_STA_BIT_5_WOFFSET                      0x0
+#define GPIO_INT_STA_BIT_5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_BIT_5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_5_IN_ACTIVE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_BIT_5_ACTIVE                       _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_BIT_4_SHIFT                        _MK_SHIFT_CONST(4)
+#define GPIO_INT_STA_BIT_4_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_STA_BIT_4_SHIFT)
+#define GPIO_INT_STA_BIT_4_RANGE                        4:4
+#define GPIO_INT_STA_BIT_4_WOFFSET                      0x0
+#define GPIO_INT_STA_BIT_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_BIT_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_4_IN_ACTIVE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_BIT_4_ACTIVE                       _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_BIT_3_SHIFT                        _MK_SHIFT_CONST(3)
+#define GPIO_INT_STA_BIT_3_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_STA_BIT_3_SHIFT)
+#define GPIO_INT_STA_BIT_3_RANGE                        3:3
+#define GPIO_INT_STA_BIT_3_WOFFSET                      0x0
+#define GPIO_INT_STA_BIT_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_BIT_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_3_IN_ACTIVE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_BIT_3_ACTIVE                       _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_BIT_2_SHIFT                        _MK_SHIFT_CONST(2)
+#define GPIO_INT_STA_BIT_2_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_STA_BIT_2_SHIFT)
+#define GPIO_INT_STA_BIT_2_RANGE                        2:2
+#define GPIO_INT_STA_BIT_2_WOFFSET                      0x0
+#define GPIO_INT_STA_BIT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_BIT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_2_IN_ACTIVE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_BIT_2_ACTIVE                       _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid. 
+#define GPIO_INT_STA_BIT_1_SHIFT                        _MK_SHIFT_CONST(1)
+#define GPIO_INT_STA_BIT_1_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_STA_BIT_1_SHIFT)
+#define GPIO_INT_STA_BIT_1_RANGE                        1:1
+#define GPIO_INT_STA_BIT_1_WOFFSET                      0x0
+#define GPIO_INT_STA_BIT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_BIT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_1_IN_ACTIVE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_BIT_1_ACTIVE                       _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_BIT_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define GPIO_INT_STA_BIT_0_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_STA_BIT_0_SHIFT)
+#define GPIO_INT_STA_BIT_0_RANGE                        0:0
+#define GPIO_INT_STA_BIT_0_WOFFSET                      0x0
+#define GPIO_INT_STA_BIT_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_BIT_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_BIT_0_IN_ACTIVE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_BIT_0_ACTIVE                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_STA_1  
+#define GPIO_INT_STA_1                  _MK_ADDR_CONST(0x44)
+#define GPIO_INT_STA_1_WORD_COUNT                       0x1
+#define GPIO_INT_STA_1_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_STA_1_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_STA_1_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_1_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_STA_1_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_1_BIT_7_SHIFT)
+#define GPIO_INT_STA_1_BIT_7_RANGE                      7:7
+#define GPIO_INT_STA_1_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_STA_1_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_1_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_7_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_1_BIT_7_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_1_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_STA_1_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_1_BIT_6_SHIFT)
+#define GPIO_INT_STA_1_BIT_6_RANGE                      6:6
+#define GPIO_INT_STA_1_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_STA_1_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_1_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_6_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_1_BIT_6_ACTIVE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid. 
+#define GPIO_INT_STA_1_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_STA_1_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_1_BIT_5_SHIFT)
+#define GPIO_INT_STA_1_BIT_5_RANGE                      5:5
+#define GPIO_INT_STA_1_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_STA_1_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_1_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_5_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_1_BIT_5_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_1_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_STA_1_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_1_BIT_4_SHIFT)
+#define GPIO_INT_STA_1_BIT_4_RANGE                      4:4
+#define GPIO_INT_STA_1_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_STA_1_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_1_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_4_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_1_BIT_4_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_1_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_STA_1_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_1_BIT_3_SHIFT)
+#define GPIO_INT_STA_1_BIT_3_RANGE                      3:3
+#define GPIO_INT_STA_1_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_STA_1_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_1_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_3_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_1_BIT_3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_1_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_STA_1_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_1_BIT_2_SHIFT)
+#define GPIO_INT_STA_1_BIT_2_RANGE                      2:2
+#define GPIO_INT_STA_1_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_STA_1_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_1_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_2_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_1_BIT_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid. 
+#define GPIO_INT_STA_1_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_STA_1_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_1_BIT_1_SHIFT)
+#define GPIO_INT_STA_1_BIT_1_RANGE                      1:1
+#define GPIO_INT_STA_1_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_STA_1_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_1_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_1_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_1_BIT_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_1_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_STA_1_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_1_BIT_0_SHIFT)
+#define GPIO_INT_STA_1_BIT_0_RANGE                      0:0
+#define GPIO_INT_STA_1_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_STA_1_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_1_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_1_BIT_0_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_1_BIT_0_ACTIVE                     _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_STA_2  
+#define GPIO_INT_STA_2                  _MK_ADDR_CONST(0x48)
+#define GPIO_INT_STA_2_WORD_COUNT                       0x1
+#define GPIO_INT_STA_2_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_STA_2_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_STA_2_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_2_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_STA_2_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_2_BIT_7_SHIFT)
+#define GPIO_INT_STA_2_BIT_7_RANGE                      7:7
+#define GPIO_INT_STA_2_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_STA_2_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_2_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_7_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_2_BIT_7_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_2_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_STA_2_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_2_BIT_6_SHIFT)
+#define GPIO_INT_STA_2_BIT_6_RANGE                      6:6
+#define GPIO_INT_STA_2_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_STA_2_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_2_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_6_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_2_BIT_6_ACTIVE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid. 
+#define GPIO_INT_STA_2_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_STA_2_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_2_BIT_5_SHIFT)
+#define GPIO_INT_STA_2_BIT_5_RANGE                      5:5
+#define GPIO_INT_STA_2_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_STA_2_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_2_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_5_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_2_BIT_5_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_2_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_STA_2_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_2_BIT_4_SHIFT)
+#define GPIO_INT_STA_2_BIT_4_RANGE                      4:4
+#define GPIO_INT_STA_2_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_STA_2_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_2_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_4_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_2_BIT_4_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_2_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_STA_2_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_2_BIT_3_SHIFT)
+#define GPIO_INT_STA_2_BIT_3_RANGE                      3:3
+#define GPIO_INT_STA_2_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_STA_2_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_2_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_3_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_2_BIT_3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_2_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_STA_2_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_2_BIT_2_SHIFT)
+#define GPIO_INT_STA_2_BIT_2_RANGE                      2:2
+#define GPIO_INT_STA_2_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_STA_2_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_2_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_2_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_2_BIT_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid. 
+#define GPIO_INT_STA_2_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_STA_2_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_2_BIT_1_SHIFT)
+#define GPIO_INT_STA_2_BIT_1_RANGE                      1:1
+#define GPIO_INT_STA_2_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_STA_2_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_2_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_1_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_2_BIT_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_2_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_STA_2_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_2_BIT_0_SHIFT)
+#define GPIO_INT_STA_2_BIT_0_RANGE                      0:0
+#define GPIO_INT_STA_2_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_STA_2_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_2_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_2_BIT_0_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_2_BIT_0_ACTIVE                     _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_STA_3  
+#define GPIO_INT_STA_3                  _MK_ADDR_CONST(0x4c)
+#define GPIO_INT_STA_3_WORD_COUNT                       0x1
+#define GPIO_INT_STA_3_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_STA_3_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_STA_3_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_3_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_STA_3_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_3_BIT_7_SHIFT)
+#define GPIO_INT_STA_3_BIT_7_RANGE                      7:7
+#define GPIO_INT_STA_3_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_STA_3_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_3_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_7_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_3_BIT_7_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_3_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_STA_3_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_3_BIT_6_SHIFT)
+#define GPIO_INT_STA_3_BIT_6_RANGE                      6:6
+#define GPIO_INT_STA_3_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_STA_3_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_3_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_6_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_3_BIT_6_ACTIVE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid. 
+#define GPIO_INT_STA_3_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_STA_3_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_3_BIT_5_SHIFT)
+#define GPIO_INT_STA_3_BIT_5_RANGE                      5:5
+#define GPIO_INT_STA_3_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_STA_3_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_3_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_5_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_3_BIT_5_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_3_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_STA_3_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_3_BIT_4_SHIFT)
+#define GPIO_INT_STA_3_BIT_4_RANGE                      4:4
+#define GPIO_INT_STA_3_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_STA_3_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_3_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_4_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_3_BIT_4_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_3_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_STA_3_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_3_BIT_3_SHIFT)
+#define GPIO_INT_STA_3_BIT_3_RANGE                      3:3
+#define GPIO_INT_STA_3_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_STA_3_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_3_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_3_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_3_BIT_3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_3_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_STA_3_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_3_BIT_2_SHIFT)
+#define GPIO_INT_STA_3_BIT_2_RANGE                      2:2
+#define GPIO_INT_STA_3_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_STA_3_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_3_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_2_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_3_BIT_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid. 
+#define GPIO_INT_STA_3_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_STA_3_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_3_BIT_1_SHIFT)
+#define GPIO_INT_STA_3_BIT_1_RANGE                      1:1
+#define GPIO_INT_STA_3_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_STA_3_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_3_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_1_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_3_BIT_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_STA_3_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_STA_3_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_STA_3_BIT_0_SHIFT)
+#define GPIO_INT_STA_3_BIT_0_RANGE                      0:0
+#define GPIO_INT_STA_3_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_STA_3_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_STA_3_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_STA_3_BIT_0_IN_ACTIVE                  _MK_ENUM_CONST(0)
+#define GPIO_INT_STA_3_BIT_0_ACTIVE                     _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_ENB_0  
+#define GPIO_INT_ENB_0                  _MK_ADDR_CONST(0x50)
+#define GPIO_INT_ENB_0_WORD_COUNT                       0x1
+#define GPIO_INT_ENB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_ENB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_ENB_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_0_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_ENB_0_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_0_BIT_7_SHIFT)
+#define GPIO_INT_ENB_0_BIT_7_RANGE                      7:7
+#define GPIO_INT_ENB_0_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_ENB_0_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_0_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_7_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_0_BIT_7_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_0_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_ENB_0_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_0_BIT_6_SHIFT)
+#define GPIO_INT_ENB_0_BIT_6_RANGE                      6:6
+#define GPIO_INT_ENB_0_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_ENB_0_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_0_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_6_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_0_BIT_6_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_0_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_ENB_0_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_0_BIT_5_SHIFT)
+#define GPIO_INT_ENB_0_BIT_5_RANGE                      5:5
+#define GPIO_INT_ENB_0_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_ENB_0_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_0_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_5_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_0_BIT_5_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_0_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_ENB_0_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_0_BIT_4_SHIFT)
+#define GPIO_INT_ENB_0_BIT_4_RANGE                      4:4
+#define GPIO_INT_ENB_0_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_ENB_0_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_0_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_4_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_0_BIT_4_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_0_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_ENB_0_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_0_BIT_3_SHIFT)
+#define GPIO_INT_ENB_0_BIT_3_RANGE                      3:3
+#define GPIO_INT_ENB_0_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_ENB_0_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_0_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_3_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_0_BIT_3_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_0_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_ENB_0_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_0_BIT_2_SHIFT)
+#define GPIO_INT_ENB_0_BIT_2_RANGE                      2:2
+#define GPIO_INT_ENB_0_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_ENB_0_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_0_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_2_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_0_BIT_2_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_0_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_ENB_0_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_0_BIT_1_SHIFT)
+#define GPIO_INT_ENB_0_BIT_1_RANGE                      1:1
+#define GPIO_INT_ENB_0_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_ENB_0_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_0_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_1_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_0_BIT_1_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_0_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_ENB_0_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_0_BIT_0_SHIFT)
+#define GPIO_INT_ENB_0_BIT_0_RANGE                      0:0
+#define GPIO_INT_ENB_0_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_ENB_0_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_0_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_0_BIT_0_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_0_BIT_0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_ENB  
+#define GPIO_INT_ENB                    _MK_ADDR_CONST(0x50)
+#define GPIO_INT_ENB_WORD_COUNT                         0x1
+#define GPIO_INT_ENB_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define GPIO_INT_ENB_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_READ_MASK                  _MK_MASK_CONST(0xff)
+#define GPIO_INT_ENB_WRITE_MASK                         _MK_MASK_CONST(0xff)
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_BIT_7_SHIFT                        _MK_SHIFT_CONST(7)
+#define GPIO_INT_ENB_BIT_7_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_BIT_7_SHIFT)
+#define GPIO_INT_ENB_BIT_7_RANGE                        7:7
+#define GPIO_INT_ENB_BIT_7_WOFFSET                      0x0
+#define GPIO_INT_ENB_BIT_7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_BIT_7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_7_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_BIT_7_ENABLE                       _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_BIT_6_SHIFT                        _MK_SHIFT_CONST(6)
+#define GPIO_INT_ENB_BIT_6_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_BIT_6_SHIFT)
+#define GPIO_INT_ENB_BIT_6_RANGE                        6:6
+#define GPIO_INT_ENB_BIT_6_WOFFSET                      0x0
+#define GPIO_INT_ENB_BIT_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_BIT_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_6_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_BIT_6_ENABLE                       _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_BIT_5_SHIFT                        _MK_SHIFT_CONST(5)
+#define GPIO_INT_ENB_BIT_5_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_BIT_5_SHIFT)
+#define GPIO_INT_ENB_BIT_5_RANGE                        5:5
+#define GPIO_INT_ENB_BIT_5_WOFFSET                      0x0
+#define GPIO_INT_ENB_BIT_5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_BIT_5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_5_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_BIT_5_ENABLE                       _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_BIT_4_SHIFT                        _MK_SHIFT_CONST(4)
+#define GPIO_INT_ENB_BIT_4_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_BIT_4_SHIFT)
+#define GPIO_INT_ENB_BIT_4_RANGE                        4:4
+#define GPIO_INT_ENB_BIT_4_WOFFSET                      0x0
+#define GPIO_INT_ENB_BIT_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_BIT_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_4_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_BIT_4_ENABLE                       _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_BIT_3_SHIFT                        _MK_SHIFT_CONST(3)
+#define GPIO_INT_ENB_BIT_3_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_BIT_3_SHIFT)
+#define GPIO_INT_ENB_BIT_3_RANGE                        3:3
+#define GPIO_INT_ENB_BIT_3_WOFFSET                      0x0
+#define GPIO_INT_ENB_BIT_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_BIT_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_3_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_BIT_3_ENABLE                       _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_BIT_2_SHIFT                        _MK_SHIFT_CONST(2)
+#define GPIO_INT_ENB_BIT_2_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_BIT_2_SHIFT)
+#define GPIO_INT_ENB_BIT_2_RANGE                        2:2
+#define GPIO_INT_ENB_BIT_2_WOFFSET                      0x0
+#define GPIO_INT_ENB_BIT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_BIT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_2_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_BIT_2_ENABLE                       _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_BIT_1_SHIFT                        _MK_SHIFT_CONST(1)
+#define GPIO_INT_ENB_BIT_1_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_BIT_1_SHIFT)
+#define GPIO_INT_ENB_BIT_1_RANGE                        1:1
+#define GPIO_INT_ENB_BIT_1_WOFFSET                      0x0
+#define GPIO_INT_ENB_BIT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_BIT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_1_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_BIT_1_ENABLE                       _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_BIT_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define GPIO_INT_ENB_BIT_0_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_BIT_0_SHIFT)
+#define GPIO_INT_ENB_BIT_0_RANGE                        0:0
+#define GPIO_INT_ENB_BIT_0_WOFFSET                      0x0
+#define GPIO_INT_ENB_BIT_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_BIT_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_BIT_0_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_BIT_0_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_ENB_1  
+#define GPIO_INT_ENB_1                  _MK_ADDR_CONST(0x54)
+#define GPIO_INT_ENB_1_WORD_COUNT                       0x1
+#define GPIO_INT_ENB_1_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_ENB_1_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_ENB_1_WRITE_MASK                       _MK_MASK_CONST(0xff)
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_1_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_ENB_1_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_1_BIT_7_SHIFT)
+#define GPIO_INT_ENB_1_BIT_7_RANGE                      7:7
+#define GPIO_INT_ENB_1_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_ENB_1_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_1_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_7_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_1_BIT_7_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_1_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_ENB_1_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_1_BIT_6_SHIFT)
+#define GPIO_INT_ENB_1_BIT_6_RANGE                      6:6
+#define GPIO_INT_ENB_1_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_ENB_1_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_1_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_6_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_1_BIT_6_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_1_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_ENB_1_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_1_BIT_5_SHIFT)
+#define GPIO_INT_ENB_1_BIT_5_RANGE                      5:5
+#define GPIO_INT_ENB_1_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_ENB_1_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_1_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_5_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_1_BIT_5_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_1_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_ENB_1_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_1_BIT_4_SHIFT)
+#define GPIO_INT_ENB_1_BIT_4_RANGE                      4:4
+#define GPIO_INT_ENB_1_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_ENB_1_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_1_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_4_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_1_BIT_4_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_1_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_ENB_1_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_1_BIT_3_SHIFT)
+#define GPIO_INT_ENB_1_BIT_3_RANGE                      3:3
+#define GPIO_INT_ENB_1_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_ENB_1_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_1_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_3_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_1_BIT_3_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_1_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_ENB_1_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_1_BIT_2_SHIFT)
+#define GPIO_INT_ENB_1_BIT_2_RANGE                      2:2
+#define GPIO_INT_ENB_1_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_ENB_1_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_1_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_2_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_1_BIT_2_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_1_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_ENB_1_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_1_BIT_1_SHIFT)
+#define GPIO_INT_ENB_1_BIT_1_RANGE                      1:1
+#define GPIO_INT_ENB_1_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_ENB_1_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_1_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_1_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_1_BIT_1_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_1_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_ENB_1_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_1_BIT_0_SHIFT)
+#define GPIO_INT_ENB_1_BIT_0_RANGE                      0:0
+#define GPIO_INT_ENB_1_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_ENB_1_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_1_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_1_BIT_0_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_1_BIT_0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_ENB_2  
+#define GPIO_INT_ENB_2                  _MK_ADDR_CONST(0x58)
+#define GPIO_INT_ENB_2_WORD_COUNT                       0x1
+#define GPIO_INT_ENB_2_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_ENB_2_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_ENB_2_WRITE_MASK                       _MK_MASK_CONST(0xff)
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_2_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_ENB_2_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_2_BIT_7_SHIFT)
+#define GPIO_INT_ENB_2_BIT_7_RANGE                      7:7
+#define GPIO_INT_ENB_2_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_ENB_2_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_2_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_7_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_2_BIT_7_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_2_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_ENB_2_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_2_BIT_6_SHIFT)
+#define GPIO_INT_ENB_2_BIT_6_RANGE                      6:6
+#define GPIO_INT_ENB_2_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_ENB_2_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_2_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_6_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_2_BIT_6_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_2_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_ENB_2_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_2_BIT_5_SHIFT)
+#define GPIO_INT_ENB_2_BIT_5_RANGE                      5:5
+#define GPIO_INT_ENB_2_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_ENB_2_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_2_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_5_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_2_BIT_5_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_2_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_ENB_2_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_2_BIT_4_SHIFT)
+#define GPIO_INT_ENB_2_BIT_4_RANGE                      4:4
+#define GPIO_INT_ENB_2_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_ENB_2_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_2_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_4_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_2_BIT_4_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_2_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_ENB_2_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_2_BIT_3_SHIFT)
+#define GPIO_INT_ENB_2_BIT_3_RANGE                      3:3
+#define GPIO_INT_ENB_2_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_ENB_2_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_2_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_3_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_2_BIT_3_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_2_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_ENB_2_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_2_BIT_2_SHIFT)
+#define GPIO_INT_ENB_2_BIT_2_RANGE                      2:2
+#define GPIO_INT_ENB_2_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_ENB_2_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_2_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_2_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_2_BIT_2_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_2_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_ENB_2_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_2_BIT_1_SHIFT)
+#define GPIO_INT_ENB_2_BIT_1_RANGE                      1:1
+#define GPIO_INT_ENB_2_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_ENB_2_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_2_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_1_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_2_BIT_1_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_2_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_ENB_2_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_2_BIT_0_SHIFT)
+#define GPIO_INT_ENB_2_BIT_0_RANGE                      0:0
+#define GPIO_INT_ENB_2_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_ENB_2_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_2_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_2_BIT_0_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_2_BIT_0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_ENB_3  
+#define GPIO_INT_ENB_3                  _MK_ADDR_CONST(0x5c)
+#define GPIO_INT_ENB_3_WORD_COUNT                       0x1
+#define GPIO_INT_ENB_3_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_ENB_3_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_ENB_3_WRITE_MASK                       _MK_MASK_CONST(0xff)
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_3_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_ENB_3_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_3_BIT_7_SHIFT)
+#define GPIO_INT_ENB_3_BIT_7_RANGE                      7:7
+#define GPIO_INT_ENB_3_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_ENB_3_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_3_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_7_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_3_BIT_7_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_3_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_ENB_3_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_3_BIT_6_SHIFT)
+#define GPIO_INT_ENB_3_BIT_6_RANGE                      6:6
+#define GPIO_INT_ENB_3_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_ENB_3_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_3_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_6_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_3_BIT_6_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_3_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_ENB_3_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_3_BIT_5_SHIFT)
+#define GPIO_INT_ENB_3_BIT_5_RANGE                      5:5
+#define GPIO_INT_ENB_3_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_ENB_3_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_3_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_5_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_3_BIT_5_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_3_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_ENB_3_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_3_BIT_4_SHIFT)
+#define GPIO_INT_ENB_3_BIT_4_RANGE                      4:4
+#define GPIO_INT_ENB_3_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_ENB_3_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_3_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_4_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_3_BIT_4_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_3_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_ENB_3_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_3_BIT_3_SHIFT)
+#define GPIO_INT_ENB_3_BIT_3_RANGE                      3:3
+#define GPIO_INT_ENB_3_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_ENB_3_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_3_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_3_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_3_BIT_3_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_3_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_ENB_3_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_3_BIT_2_SHIFT)
+#define GPIO_INT_ENB_3_BIT_2_RANGE                      2:2
+#define GPIO_INT_ENB_3_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_ENB_3_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_3_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_2_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_3_BIT_2_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_3_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_ENB_3_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_3_BIT_1_SHIFT)
+#define GPIO_INT_ENB_3_BIT_1_RANGE                      1:1
+#define GPIO_INT_ENB_3_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_ENB_3_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_3_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_1_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_3_BIT_1_ENABLE                     _MK_ENUM_CONST(1)
+
+//GPIO mode (GPIO_CNF.x=1) must be true for this condition to be valid. 
+#define GPIO_INT_ENB_3_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_ENB_3_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_ENB_3_BIT_0_SHIFT)
+#define GPIO_INT_ENB_3_BIT_0_RANGE                      0:0
+#define GPIO_INT_ENB_3_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_ENB_3_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_ENB_3_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_ENB_3_BIT_0_DISABLE                    _MK_ENUM_CONST(0)
+#define GPIO_INT_ENB_3_BIT_0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_LVL_0  
+#define GPIO_INT_LVL_0                  _MK_ADDR_CONST(0x60)
+#define GPIO_INT_LVL_0_WORD_COUNT                       0x1
+#define GPIO_INT_LVL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_RESET_MASK                       _MK_MASK_CONST(0xffffff)
+#define GPIO_INT_LVL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_READ_MASK                        _MK_MASK_CONST(0xffffff)
+#define GPIO_INT_LVL_0_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_0_DELTA_7_SHIFT                    _MK_SHIFT_CONST(23)
+#define GPIO_INT_LVL_0_DELTA_7_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_DELTA_7_SHIFT)
+#define GPIO_INT_LVL_0_DELTA_7_RANGE                    23:23
+#define GPIO_INT_LVL_0_DELTA_7_WOFFSET                  0x0
+#define GPIO_INT_LVL_0_DELTA_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_DELTA_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_0_DELTA_6_SHIFT                    _MK_SHIFT_CONST(22)
+#define GPIO_INT_LVL_0_DELTA_6_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_DELTA_6_SHIFT)
+#define GPIO_INT_LVL_0_DELTA_6_RANGE                    22:22
+#define GPIO_INT_LVL_0_DELTA_6_WOFFSET                  0x0
+#define GPIO_INT_LVL_0_DELTA_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_DELTA_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_0_DELTA_5_SHIFT                    _MK_SHIFT_CONST(21)
+#define GPIO_INT_LVL_0_DELTA_5_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_DELTA_5_SHIFT)
+#define GPIO_INT_LVL_0_DELTA_5_RANGE                    21:21
+#define GPIO_INT_LVL_0_DELTA_5_WOFFSET                  0x0
+#define GPIO_INT_LVL_0_DELTA_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_DELTA_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_0_DELTA_4_SHIFT                    _MK_SHIFT_CONST(20)
+#define GPIO_INT_LVL_0_DELTA_4_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_DELTA_4_SHIFT)
+#define GPIO_INT_LVL_0_DELTA_4_RANGE                    20:20
+#define GPIO_INT_LVL_0_DELTA_4_WOFFSET                  0x0
+#define GPIO_INT_LVL_0_DELTA_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_DELTA_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_0_DELTA_3_SHIFT                    _MK_SHIFT_CONST(19)
+#define GPIO_INT_LVL_0_DELTA_3_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_DELTA_3_SHIFT)
+#define GPIO_INT_LVL_0_DELTA_3_RANGE                    19:19
+#define GPIO_INT_LVL_0_DELTA_3_WOFFSET                  0x0
+#define GPIO_INT_LVL_0_DELTA_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_DELTA_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_0_DELTA_2_SHIFT                    _MK_SHIFT_CONST(18)
+#define GPIO_INT_LVL_0_DELTA_2_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_DELTA_2_SHIFT)
+#define GPIO_INT_LVL_0_DELTA_2_RANGE                    18:18
+#define GPIO_INT_LVL_0_DELTA_2_WOFFSET                  0x0
+#define GPIO_INT_LVL_0_DELTA_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_DELTA_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_0_DELTA_1_SHIFT                    _MK_SHIFT_CONST(17)
+#define GPIO_INT_LVL_0_DELTA_1_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_DELTA_1_SHIFT)
+#define GPIO_INT_LVL_0_DELTA_1_RANGE                    17:17
+#define GPIO_INT_LVL_0_DELTA_1_WOFFSET                  0x0
+#define GPIO_INT_LVL_0_DELTA_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_DELTA_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_0_DELTA_0_SHIFT                    _MK_SHIFT_CONST(16)
+#define GPIO_INT_LVL_0_DELTA_0_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_DELTA_0_SHIFT)
+#define GPIO_INT_LVL_0_DELTA_0_RANGE                    16:16
+#define GPIO_INT_LVL_0_DELTA_0_WOFFSET                  0x0
+#define GPIO_INT_LVL_0_DELTA_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_DELTA_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_DELTA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_0_EDGE_7_SHIFT                     _MK_SHIFT_CONST(15)
+#define GPIO_INT_LVL_0_EDGE_7_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_EDGE_7_SHIFT)
+#define GPIO_INT_LVL_0_EDGE_7_RANGE                     15:15
+#define GPIO_INT_LVL_0_EDGE_7_WOFFSET                   0x0
+#define GPIO_INT_LVL_0_EDGE_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_EDGE_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_0_EDGE_6_SHIFT                     _MK_SHIFT_CONST(14)
+#define GPIO_INT_LVL_0_EDGE_6_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_EDGE_6_SHIFT)
+#define GPIO_INT_LVL_0_EDGE_6_RANGE                     14:14
+#define GPIO_INT_LVL_0_EDGE_6_WOFFSET                   0x0
+#define GPIO_INT_LVL_0_EDGE_6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_EDGE_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_0_EDGE_5_SHIFT                     _MK_SHIFT_CONST(13)
+#define GPIO_INT_LVL_0_EDGE_5_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_EDGE_5_SHIFT)
+#define GPIO_INT_LVL_0_EDGE_5_RANGE                     13:13
+#define GPIO_INT_LVL_0_EDGE_5_WOFFSET                   0x0
+#define GPIO_INT_LVL_0_EDGE_5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_EDGE_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_0_EDGE_4_SHIFT                     _MK_SHIFT_CONST(12)
+#define GPIO_INT_LVL_0_EDGE_4_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_EDGE_4_SHIFT)
+#define GPIO_INT_LVL_0_EDGE_4_RANGE                     12:12
+#define GPIO_INT_LVL_0_EDGE_4_WOFFSET                   0x0
+#define GPIO_INT_LVL_0_EDGE_4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_EDGE_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_0_EDGE_3_SHIFT                     _MK_SHIFT_CONST(11)
+#define GPIO_INT_LVL_0_EDGE_3_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_EDGE_3_SHIFT)
+#define GPIO_INT_LVL_0_EDGE_3_RANGE                     11:11
+#define GPIO_INT_LVL_0_EDGE_3_WOFFSET                   0x0
+#define GPIO_INT_LVL_0_EDGE_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_EDGE_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_0_EDGE_2_SHIFT                     _MK_SHIFT_CONST(10)
+#define GPIO_INT_LVL_0_EDGE_2_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_EDGE_2_SHIFT)
+#define GPIO_INT_LVL_0_EDGE_2_RANGE                     10:10
+#define GPIO_INT_LVL_0_EDGE_2_WOFFSET                   0x0
+#define GPIO_INT_LVL_0_EDGE_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_EDGE_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_0_EDGE_1_SHIFT                     _MK_SHIFT_CONST(9)
+#define GPIO_INT_LVL_0_EDGE_1_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_EDGE_1_SHIFT)
+#define GPIO_INT_LVL_0_EDGE_1_RANGE                     9:9
+#define GPIO_INT_LVL_0_EDGE_1_WOFFSET                   0x0
+#define GPIO_INT_LVL_0_EDGE_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_EDGE_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_0_EDGE_0_SHIFT                     _MK_SHIFT_CONST(8)
+#define GPIO_INT_LVL_0_EDGE_0_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_EDGE_0_SHIFT)
+#define GPIO_INT_LVL_0_EDGE_0_RANGE                     8:8
+#define GPIO_INT_LVL_0_EDGE_0_WOFFSET                   0x0
+#define GPIO_INT_LVL_0_EDGE_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_EDGE_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_EDGE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_0_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_LVL_0_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_BIT_7_SHIFT)
+#define GPIO_INT_LVL_0_BIT_7_RANGE                      7:7
+#define GPIO_INT_LVL_0_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_LVL_0_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_7_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_0_BIT_7_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_0_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_LVL_0_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_BIT_6_SHIFT)
+#define GPIO_INT_LVL_0_BIT_6_RANGE                      6:6
+#define GPIO_INT_LVL_0_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_LVL_0_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_6_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_0_BIT_6_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_0_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_LVL_0_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_BIT_5_SHIFT)
+#define GPIO_INT_LVL_0_BIT_5_RANGE                      5:5
+#define GPIO_INT_LVL_0_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_LVL_0_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_5_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_0_BIT_5_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_0_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_LVL_0_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_BIT_4_SHIFT)
+#define GPIO_INT_LVL_0_BIT_4_RANGE                      4:4
+#define GPIO_INT_LVL_0_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_LVL_0_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_4_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_0_BIT_4_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_0_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_LVL_0_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_BIT_3_SHIFT)
+#define GPIO_INT_LVL_0_BIT_3_RANGE                      3:3
+#define GPIO_INT_LVL_0_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_LVL_0_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_3_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_0_BIT_3_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_0_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_LVL_0_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_BIT_2_SHIFT)
+#define GPIO_INT_LVL_0_BIT_2_RANGE                      2:2
+#define GPIO_INT_LVL_0_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_LVL_0_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_2_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_0_BIT_2_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_0_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_LVL_0_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_BIT_1_SHIFT)
+#define GPIO_INT_LVL_0_BIT_1_RANGE                      1:1
+#define GPIO_INT_LVL_0_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_LVL_0_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_1_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_0_BIT_1_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_0_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_LVL_0_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_0_BIT_0_SHIFT)
+#define GPIO_INT_LVL_0_BIT_0_RANGE                      0:0
+#define GPIO_INT_LVL_0_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_LVL_0_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_0_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_0_BIT_0_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_0_BIT_0_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_LVL  
+#define GPIO_INT_LVL                    _MK_ADDR_CONST(0x60)
+#define GPIO_INT_LVL_WORD_COUNT                         0x1
+#define GPIO_INT_LVL_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_RESET_MASK                         _MK_MASK_CONST(0xffffff)
+#define GPIO_INT_LVL_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_READ_MASK                  _MK_MASK_CONST(0xffffff)
+#define GPIO_INT_LVL_WRITE_MASK                         _MK_MASK_CONST(0xffffff)
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_DELTA_7_SHIFT                      _MK_SHIFT_CONST(23)
+#define GPIO_INT_LVL_DELTA_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_DELTA_7_SHIFT)
+#define GPIO_INT_LVL_DELTA_7_RANGE                      23:23
+#define GPIO_INT_LVL_DELTA_7_WOFFSET                    0x0
+#define GPIO_INT_LVL_DELTA_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_DELTA_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_DELTA_6_SHIFT                      _MK_SHIFT_CONST(22)
+#define GPIO_INT_LVL_DELTA_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_DELTA_6_SHIFT)
+#define GPIO_INT_LVL_DELTA_6_RANGE                      22:22
+#define GPIO_INT_LVL_DELTA_6_WOFFSET                    0x0
+#define GPIO_INT_LVL_DELTA_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_DELTA_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_DELTA_5_SHIFT                      _MK_SHIFT_CONST(21)
+#define GPIO_INT_LVL_DELTA_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_DELTA_5_SHIFT)
+#define GPIO_INT_LVL_DELTA_5_RANGE                      21:21
+#define GPIO_INT_LVL_DELTA_5_WOFFSET                    0x0
+#define GPIO_INT_LVL_DELTA_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_DELTA_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_DELTA_4_SHIFT                      _MK_SHIFT_CONST(20)
+#define GPIO_INT_LVL_DELTA_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_DELTA_4_SHIFT)
+#define GPIO_INT_LVL_DELTA_4_RANGE                      20:20
+#define GPIO_INT_LVL_DELTA_4_WOFFSET                    0x0
+#define GPIO_INT_LVL_DELTA_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_DELTA_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_DELTA_3_SHIFT                      _MK_SHIFT_CONST(19)
+#define GPIO_INT_LVL_DELTA_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_DELTA_3_SHIFT)
+#define GPIO_INT_LVL_DELTA_3_RANGE                      19:19
+#define GPIO_INT_LVL_DELTA_3_WOFFSET                    0x0
+#define GPIO_INT_LVL_DELTA_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_DELTA_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_DELTA_2_SHIFT                      _MK_SHIFT_CONST(18)
+#define GPIO_INT_LVL_DELTA_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_DELTA_2_SHIFT)
+#define GPIO_INT_LVL_DELTA_2_RANGE                      18:18
+#define GPIO_INT_LVL_DELTA_2_WOFFSET                    0x0
+#define GPIO_INT_LVL_DELTA_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_DELTA_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_DELTA_1_SHIFT                      _MK_SHIFT_CONST(17)
+#define GPIO_INT_LVL_DELTA_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_DELTA_1_SHIFT)
+#define GPIO_INT_LVL_DELTA_1_RANGE                      17:17
+#define GPIO_INT_LVL_DELTA_1_WOFFSET                    0x0
+#define GPIO_INT_LVL_DELTA_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_DELTA_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_DELTA_0_SHIFT                      _MK_SHIFT_CONST(16)
+#define GPIO_INT_LVL_DELTA_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_DELTA_0_SHIFT)
+#define GPIO_INT_LVL_DELTA_0_RANGE                      16:16
+#define GPIO_INT_LVL_DELTA_0_WOFFSET                    0x0
+#define GPIO_INT_LVL_DELTA_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_DELTA_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_DELTA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_EDGE_7_SHIFT                       _MK_SHIFT_CONST(15)
+#define GPIO_INT_LVL_EDGE_7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_EDGE_7_SHIFT)
+#define GPIO_INT_LVL_EDGE_7_RANGE                       15:15
+#define GPIO_INT_LVL_EDGE_7_WOFFSET                     0x0
+#define GPIO_INT_LVL_EDGE_7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_EDGE_7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_EDGE_6_SHIFT                       _MK_SHIFT_CONST(14)
+#define GPIO_INT_LVL_EDGE_6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_EDGE_6_SHIFT)
+#define GPIO_INT_LVL_EDGE_6_RANGE                       14:14
+#define GPIO_INT_LVL_EDGE_6_WOFFSET                     0x0
+#define GPIO_INT_LVL_EDGE_6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_EDGE_6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_EDGE_5_SHIFT                       _MK_SHIFT_CONST(13)
+#define GPIO_INT_LVL_EDGE_5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_EDGE_5_SHIFT)
+#define GPIO_INT_LVL_EDGE_5_RANGE                       13:13
+#define GPIO_INT_LVL_EDGE_5_WOFFSET                     0x0
+#define GPIO_INT_LVL_EDGE_5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_EDGE_5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_EDGE_4_SHIFT                       _MK_SHIFT_CONST(12)
+#define GPIO_INT_LVL_EDGE_4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_EDGE_4_SHIFT)
+#define GPIO_INT_LVL_EDGE_4_RANGE                       12:12
+#define GPIO_INT_LVL_EDGE_4_WOFFSET                     0x0
+#define GPIO_INT_LVL_EDGE_4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_EDGE_4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_EDGE_3_SHIFT                       _MK_SHIFT_CONST(11)
+#define GPIO_INT_LVL_EDGE_3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_EDGE_3_SHIFT)
+#define GPIO_INT_LVL_EDGE_3_RANGE                       11:11
+#define GPIO_INT_LVL_EDGE_3_WOFFSET                     0x0
+#define GPIO_INT_LVL_EDGE_3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_EDGE_3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_EDGE_2_SHIFT                       _MK_SHIFT_CONST(10)
+#define GPIO_INT_LVL_EDGE_2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_EDGE_2_SHIFT)
+#define GPIO_INT_LVL_EDGE_2_RANGE                       10:10
+#define GPIO_INT_LVL_EDGE_2_WOFFSET                     0x0
+#define GPIO_INT_LVL_EDGE_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_EDGE_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_EDGE_1_SHIFT                       _MK_SHIFT_CONST(9)
+#define GPIO_INT_LVL_EDGE_1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_EDGE_1_SHIFT)
+#define GPIO_INT_LVL_EDGE_1_RANGE                       9:9
+#define GPIO_INT_LVL_EDGE_1_WOFFSET                     0x0
+#define GPIO_INT_LVL_EDGE_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_EDGE_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_EDGE_0_SHIFT                       _MK_SHIFT_CONST(8)
+#define GPIO_INT_LVL_EDGE_0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_EDGE_0_SHIFT)
+#define GPIO_INT_LVL_EDGE_0_RANGE                       8:8
+#define GPIO_INT_LVL_EDGE_0_WOFFSET                     0x0
+#define GPIO_INT_LVL_EDGE_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_EDGE_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_EDGE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_BIT_7_SHIFT                        _MK_SHIFT_CONST(7)
+#define GPIO_INT_LVL_BIT_7_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_BIT_7_SHIFT)
+#define GPIO_INT_LVL_BIT_7_RANGE                        7:7
+#define GPIO_INT_LVL_BIT_7_WOFFSET                      0x0
+#define GPIO_INT_LVL_BIT_7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_BIT_7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_7_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_BIT_7_HIGH                 _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_BIT_6_SHIFT                        _MK_SHIFT_CONST(6)
+#define GPIO_INT_LVL_BIT_6_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_BIT_6_SHIFT)
+#define GPIO_INT_LVL_BIT_6_RANGE                        6:6
+#define GPIO_INT_LVL_BIT_6_WOFFSET                      0x0
+#define GPIO_INT_LVL_BIT_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_BIT_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_6_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_BIT_6_HIGH                 _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_BIT_5_SHIFT                        _MK_SHIFT_CONST(5)
+#define GPIO_INT_LVL_BIT_5_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_BIT_5_SHIFT)
+#define GPIO_INT_LVL_BIT_5_RANGE                        5:5
+#define GPIO_INT_LVL_BIT_5_WOFFSET                      0x0
+#define GPIO_INT_LVL_BIT_5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_BIT_5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_5_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_BIT_5_HIGH                 _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_BIT_4_SHIFT                        _MK_SHIFT_CONST(4)
+#define GPIO_INT_LVL_BIT_4_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_BIT_4_SHIFT)
+#define GPIO_INT_LVL_BIT_4_RANGE                        4:4
+#define GPIO_INT_LVL_BIT_4_WOFFSET                      0x0
+#define GPIO_INT_LVL_BIT_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_BIT_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_4_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_BIT_4_HIGH                 _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_BIT_3_SHIFT                        _MK_SHIFT_CONST(3)
+#define GPIO_INT_LVL_BIT_3_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_BIT_3_SHIFT)
+#define GPIO_INT_LVL_BIT_3_RANGE                        3:3
+#define GPIO_INT_LVL_BIT_3_WOFFSET                      0x0
+#define GPIO_INT_LVL_BIT_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_BIT_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_3_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_BIT_3_HIGH                 _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_BIT_2_SHIFT                        _MK_SHIFT_CONST(2)
+#define GPIO_INT_LVL_BIT_2_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_BIT_2_SHIFT)
+#define GPIO_INT_LVL_BIT_2_RANGE                        2:2
+#define GPIO_INT_LVL_BIT_2_WOFFSET                      0x0
+#define GPIO_INT_LVL_BIT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_BIT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_2_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_BIT_2_HIGH                 _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_BIT_1_SHIFT                        _MK_SHIFT_CONST(1)
+#define GPIO_INT_LVL_BIT_1_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_BIT_1_SHIFT)
+#define GPIO_INT_LVL_BIT_1_RANGE                        1:1
+#define GPIO_INT_LVL_BIT_1_WOFFSET                      0x0
+#define GPIO_INT_LVL_BIT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_BIT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_1_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_BIT_1_HIGH                 _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_BIT_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define GPIO_INT_LVL_BIT_0_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_BIT_0_SHIFT)
+#define GPIO_INT_LVL_BIT_0_RANGE                        0:0
+#define GPIO_INT_LVL_BIT_0_WOFFSET                      0x0
+#define GPIO_INT_LVL_BIT_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_BIT_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_BIT_0_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_BIT_0_HIGH                 _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_LVL_1  
+#define GPIO_INT_LVL_1                  _MK_ADDR_CONST(0x64)
+#define GPIO_INT_LVL_1_WORD_COUNT                       0x1
+#define GPIO_INT_LVL_1_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_RESET_MASK                       _MK_MASK_CONST(0xffffff)
+#define GPIO_INT_LVL_1_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_READ_MASK                        _MK_MASK_CONST(0xffffff)
+#define GPIO_INT_LVL_1_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_1_DELTA_7_SHIFT                    _MK_SHIFT_CONST(23)
+#define GPIO_INT_LVL_1_DELTA_7_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_DELTA_7_SHIFT)
+#define GPIO_INT_LVL_1_DELTA_7_RANGE                    23:23
+#define GPIO_INT_LVL_1_DELTA_7_WOFFSET                  0x0
+#define GPIO_INT_LVL_1_DELTA_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_DELTA_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_1_DELTA_6_SHIFT                    _MK_SHIFT_CONST(22)
+#define GPIO_INT_LVL_1_DELTA_6_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_DELTA_6_SHIFT)
+#define GPIO_INT_LVL_1_DELTA_6_RANGE                    22:22
+#define GPIO_INT_LVL_1_DELTA_6_WOFFSET                  0x0
+#define GPIO_INT_LVL_1_DELTA_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_DELTA_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_1_DELTA_5_SHIFT                    _MK_SHIFT_CONST(21)
+#define GPIO_INT_LVL_1_DELTA_5_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_DELTA_5_SHIFT)
+#define GPIO_INT_LVL_1_DELTA_5_RANGE                    21:21
+#define GPIO_INT_LVL_1_DELTA_5_WOFFSET                  0x0
+#define GPIO_INT_LVL_1_DELTA_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_DELTA_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_1_DELTA_4_SHIFT                    _MK_SHIFT_CONST(20)
+#define GPIO_INT_LVL_1_DELTA_4_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_DELTA_4_SHIFT)
+#define GPIO_INT_LVL_1_DELTA_4_RANGE                    20:20
+#define GPIO_INT_LVL_1_DELTA_4_WOFFSET                  0x0
+#define GPIO_INT_LVL_1_DELTA_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_DELTA_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_1_DELTA_3_SHIFT                    _MK_SHIFT_CONST(19)
+#define GPIO_INT_LVL_1_DELTA_3_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_DELTA_3_SHIFT)
+#define GPIO_INT_LVL_1_DELTA_3_RANGE                    19:19
+#define GPIO_INT_LVL_1_DELTA_3_WOFFSET                  0x0
+#define GPIO_INT_LVL_1_DELTA_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_DELTA_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_1_DELTA_2_SHIFT                    _MK_SHIFT_CONST(18)
+#define GPIO_INT_LVL_1_DELTA_2_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_DELTA_2_SHIFT)
+#define GPIO_INT_LVL_1_DELTA_2_RANGE                    18:18
+#define GPIO_INT_LVL_1_DELTA_2_WOFFSET                  0x0
+#define GPIO_INT_LVL_1_DELTA_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_DELTA_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_1_DELTA_1_SHIFT                    _MK_SHIFT_CONST(17)
+#define GPIO_INT_LVL_1_DELTA_1_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_DELTA_1_SHIFT)
+#define GPIO_INT_LVL_1_DELTA_1_RANGE                    17:17
+#define GPIO_INT_LVL_1_DELTA_1_WOFFSET                  0x0
+#define GPIO_INT_LVL_1_DELTA_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_DELTA_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_1_DELTA_0_SHIFT                    _MK_SHIFT_CONST(16)
+#define GPIO_INT_LVL_1_DELTA_0_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_DELTA_0_SHIFT)
+#define GPIO_INT_LVL_1_DELTA_0_RANGE                    16:16
+#define GPIO_INT_LVL_1_DELTA_0_WOFFSET                  0x0
+#define GPIO_INT_LVL_1_DELTA_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_DELTA_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_DELTA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_1_EDGE_7_SHIFT                     _MK_SHIFT_CONST(15)
+#define GPIO_INT_LVL_1_EDGE_7_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_EDGE_7_SHIFT)
+#define GPIO_INT_LVL_1_EDGE_7_RANGE                     15:15
+#define GPIO_INT_LVL_1_EDGE_7_WOFFSET                   0x0
+#define GPIO_INT_LVL_1_EDGE_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_EDGE_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_1_EDGE_6_SHIFT                     _MK_SHIFT_CONST(14)
+#define GPIO_INT_LVL_1_EDGE_6_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_EDGE_6_SHIFT)
+#define GPIO_INT_LVL_1_EDGE_6_RANGE                     14:14
+#define GPIO_INT_LVL_1_EDGE_6_WOFFSET                   0x0
+#define GPIO_INT_LVL_1_EDGE_6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_EDGE_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_1_EDGE_5_SHIFT                     _MK_SHIFT_CONST(13)
+#define GPIO_INT_LVL_1_EDGE_5_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_EDGE_5_SHIFT)
+#define GPIO_INT_LVL_1_EDGE_5_RANGE                     13:13
+#define GPIO_INT_LVL_1_EDGE_5_WOFFSET                   0x0
+#define GPIO_INT_LVL_1_EDGE_5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_EDGE_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_1_EDGE_4_SHIFT                     _MK_SHIFT_CONST(12)
+#define GPIO_INT_LVL_1_EDGE_4_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_EDGE_4_SHIFT)
+#define GPIO_INT_LVL_1_EDGE_4_RANGE                     12:12
+#define GPIO_INT_LVL_1_EDGE_4_WOFFSET                   0x0
+#define GPIO_INT_LVL_1_EDGE_4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_EDGE_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_1_EDGE_3_SHIFT                     _MK_SHIFT_CONST(11)
+#define GPIO_INT_LVL_1_EDGE_3_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_EDGE_3_SHIFT)
+#define GPIO_INT_LVL_1_EDGE_3_RANGE                     11:11
+#define GPIO_INT_LVL_1_EDGE_3_WOFFSET                   0x0
+#define GPIO_INT_LVL_1_EDGE_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_EDGE_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_1_EDGE_2_SHIFT                     _MK_SHIFT_CONST(10)
+#define GPIO_INT_LVL_1_EDGE_2_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_EDGE_2_SHIFT)
+#define GPIO_INT_LVL_1_EDGE_2_RANGE                     10:10
+#define GPIO_INT_LVL_1_EDGE_2_WOFFSET                   0x0
+#define GPIO_INT_LVL_1_EDGE_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_EDGE_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_1_EDGE_1_SHIFT                     _MK_SHIFT_CONST(9)
+#define GPIO_INT_LVL_1_EDGE_1_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_EDGE_1_SHIFT)
+#define GPIO_INT_LVL_1_EDGE_1_RANGE                     9:9
+#define GPIO_INT_LVL_1_EDGE_1_WOFFSET                   0x0
+#define GPIO_INT_LVL_1_EDGE_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_EDGE_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_1_EDGE_0_SHIFT                     _MK_SHIFT_CONST(8)
+#define GPIO_INT_LVL_1_EDGE_0_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_EDGE_0_SHIFT)
+#define GPIO_INT_LVL_1_EDGE_0_RANGE                     8:8
+#define GPIO_INT_LVL_1_EDGE_0_WOFFSET                   0x0
+#define GPIO_INT_LVL_1_EDGE_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_EDGE_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_EDGE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_1_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_LVL_1_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_BIT_7_SHIFT)
+#define GPIO_INT_LVL_1_BIT_7_RANGE                      7:7
+#define GPIO_INT_LVL_1_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_LVL_1_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_7_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_1_BIT_7_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_1_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_LVL_1_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_BIT_6_SHIFT)
+#define GPIO_INT_LVL_1_BIT_6_RANGE                      6:6
+#define GPIO_INT_LVL_1_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_LVL_1_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_6_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_1_BIT_6_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_1_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_LVL_1_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_BIT_5_SHIFT)
+#define GPIO_INT_LVL_1_BIT_5_RANGE                      5:5
+#define GPIO_INT_LVL_1_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_LVL_1_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_5_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_1_BIT_5_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_1_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_LVL_1_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_BIT_4_SHIFT)
+#define GPIO_INT_LVL_1_BIT_4_RANGE                      4:4
+#define GPIO_INT_LVL_1_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_LVL_1_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_4_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_1_BIT_4_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_1_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_LVL_1_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_BIT_3_SHIFT)
+#define GPIO_INT_LVL_1_BIT_3_RANGE                      3:3
+#define GPIO_INT_LVL_1_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_LVL_1_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_3_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_1_BIT_3_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_1_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_LVL_1_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_BIT_2_SHIFT)
+#define GPIO_INT_LVL_1_BIT_2_RANGE                      2:2
+#define GPIO_INT_LVL_1_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_LVL_1_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_2_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_1_BIT_2_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_1_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_LVL_1_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_BIT_1_SHIFT)
+#define GPIO_INT_LVL_1_BIT_1_RANGE                      1:1
+#define GPIO_INT_LVL_1_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_LVL_1_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_1_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_1_BIT_1_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_1_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_LVL_1_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_1_BIT_0_SHIFT)
+#define GPIO_INT_LVL_1_BIT_0_RANGE                      0:0
+#define GPIO_INT_LVL_1_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_LVL_1_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_1_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_1_BIT_0_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_1_BIT_0_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_LVL_2  
+#define GPIO_INT_LVL_2                  _MK_ADDR_CONST(0x68)
+#define GPIO_INT_LVL_2_WORD_COUNT                       0x1
+#define GPIO_INT_LVL_2_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_RESET_MASK                       _MK_MASK_CONST(0xffffff)
+#define GPIO_INT_LVL_2_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_READ_MASK                        _MK_MASK_CONST(0xffffff)
+#define GPIO_INT_LVL_2_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_2_DELTA_7_SHIFT                    _MK_SHIFT_CONST(23)
+#define GPIO_INT_LVL_2_DELTA_7_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_DELTA_7_SHIFT)
+#define GPIO_INT_LVL_2_DELTA_7_RANGE                    23:23
+#define GPIO_INT_LVL_2_DELTA_7_WOFFSET                  0x0
+#define GPIO_INT_LVL_2_DELTA_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_DELTA_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_2_DELTA_6_SHIFT                    _MK_SHIFT_CONST(22)
+#define GPIO_INT_LVL_2_DELTA_6_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_DELTA_6_SHIFT)
+#define GPIO_INT_LVL_2_DELTA_6_RANGE                    22:22
+#define GPIO_INT_LVL_2_DELTA_6_WOFFSET                  0x0
+#define GPIO_INT_LVL_2_DELTA_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_DELTA_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_2_DELTA_5_SHIFT                    _MK_SHIFT_CONST(21)
+#define GPIO_INT_LVL_2_DELTA_5_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_DELTA_5_SHIFT)
+#define GPIO_INT_LVL_2_DELTA_5_RANGE                    21:21
+#define GPIO_INT_LVL_2_DELTA_5_WOFFSET                  0x0
+#define GPIO_INT_LVL_2_DELTA_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_DELTA_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_2_DELTA_4_SHIFT                    _MK_SHIFT_CONST(20)
+#define GPIO_INT_LVL_2_DELTA_4_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_DELTA_4_SHIFT)
+#define GPIO_INT_LVL_2_DELTA_4_RANGE                    20:20
+#define GPIO_INT_LVL_2_DELTA_4_WOFFSET                  0x0
+#define GPIO_INT_LVL_2_DELTA_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_DELTA_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_2_DELTA_3_SHIFT                    _MK_SHIFT_CONST(19)
+#define GPIO_INT_LVL_2_DELTA_3_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_DELTA_3_SHIFT)
+#define GPIO_INT_LVL_2_DELTA_3_RANGE                    19:19
+#define GPIO_INT_LVL_2_DELTA_3_WOFFSET                  0x0
+#define GPIO_INT_LVL_2_DELTA_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_DELTA_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_2_DELTA_2_SHIFT                    _MK_SHIFT_CONST(18)
+#define GPIO_INT_LVL_2_DELTA_2_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_DELTA_2_SHIFT)
+#define GPIO_INT_LVL_2_DELTA_2_RANGE                    18:18
+#define GPIO_INT_LVL_2_DELTA_2_WOFFSET                  0x0
+#define GPIO_INT_LVL_2_DELTA_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_DELTA_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_2_DELTA_1_SHIFT                    _MK_SHIFT_CONST(17)
+#define GPIO_INT_LVL_2_DELTA_1_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_DELTA_1_SHIFT)
+#define GPIO_INT_LVL_2_DELTA_1_RANGE                    17:17
+#define GPIO_INT_LVL_2_DELTA_1_WOFFSET                  0x0
+#define GPIO_INT_LVL_2_DELTA_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_DELTA_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_2_DELTA_0_SHIFT                    _MK_SHIFT_CONST(16)
+#define GPIO_INT_LVL_2_DELTA_0_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_DELTA_0_SHIFT)
+#define GPIO_INT_LVL_2_DELTA_0_RANGE                    16:16
+#define GPIO_INT_LVL_2_DELTA_0_WOFFSET                  0x0
+#define GPIO_INT_LVL_2_DELTA_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_DELTA_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_DELTA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_2_EDGE_7_SHIFT                     _MK_SHIFT_CONST(15)
+#define GPIO_INT_LVL_2_EDGE_7_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_EDGE_7_SHIFT)
+#define GPIO_INT_LVL_2_EDGE_7_RANGE                     15:15
+#define GPIO_INT_LVL_2_EDGE_7_WOFFSET                   0x0
+#define GPIO_INT_LVL_2_EDGE_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_EDGE_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_2_EDGE_6_SHIFT                     _MK_SHIFT_CONST(14)
+#define GPIO_INT_LVL_2_EDGE_6_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_EDGE_6_SHIFT)
+#define GPIO_INT_LVL_2_EDGE_6_RANGE                     14:14
+#define GPIO_INT_LVL_2_EDGE_6_WOFFSET                   0x0
+#define GPIO_INT_LVL_2_EDGE_6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_EDGE_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_2_EDGE_5_SHIFT                     _MK_SHIFT_CONST(13)
+#define GPIO_INT_LVL_2_EDGE_5_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_EDGE_5_SHIFT)
+#define GPIO_INT_LVL_2_EDGE_5_RANGE                     13:13
+#define GPIO_INT_LVL_2_EDGE_5_WOFFSET                   0x0
+#define GPIO_INT_LVL_2_EDGE_5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_EDGE_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_2_EDGE_4_SHIFT                     _MK_SHIFT_CONST(12)
+#define GPIO_INT_LVL_2_EDGE_4_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_EDGE_4_SHIFT)
+#define GPIO_INT_LVL_2_EDGE_4_RANGE                     12:12
+#define GPIO_INT_LVL_2_EDGE_4_WOFFSET                   0x0
+#define GPIO_INT_LVL_2_EDGE_4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_EDGE_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_2_EDGE_3_SHIFT                     _MK_SHIFT_CONST(11)
+#define GPIO_INT_LVL_2_EDGE_3_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_EDGE_3_SHIFT)
+#define GPIO_INT_LVL_2_EDGE_3_RANGE                     11:11
+#define GPIO_INT_LVL_2_EDGE_3_WOFFSET                   0x0
+#define GPIO_INT_LVL_2_EDGE_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_EDGE_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_2_EDGE_2_SHIFT                     _MK_SHIFT_CONST(10)
+#define GPIO_INT_LVL_2_EDGE_2_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_EDGE_2_SHIFT)
+#define GPIO_INT_LVL_2_EDGE_2_RANGE                     10:10
+#define GPIO_INT_LVL_2_EDGE_2_WOFFSET                   0x0
+#define GPIO_INT_LVL_2_EDGE_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_EDGE_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_2_EDGE_1_SHIFT                     _MK_SHIFT_CONST(9)
+#define GPIO_INT_LVL_2_EDGE_1_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_EDGE_1_SHIFT)
+#define GPIO_INT_LVL_2_EDGE_1_RANGE                     9:9
+#define GPIO_INT_LVL_2_EDGE_1_WOFFSET                   0x0
+#define GPIO_INT_LVL_2_EDGE_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_EDGE_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_2_EDGE_0_SHIFT                     _MK_SHIFT_CONST(8)
+#define GPIO_INT_LVL_2_EDGE_0_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_EDGE_0_SHIFT)
+#define GPIO_INT_LVL_2_EDGE_0_RANGE                     8:8
+#define GPIO_INT_LVL_2_EDGE_0_WOFFSET                   0x0
+#define GPIO_INT_LVL_2_EDGE_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_EDGE_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_EDGE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_2_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_LVL_2_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_BIT_7_SHIFT)
+#define GPIO_INT_LVL_2_BIT_7_RANGE                      7:7
+#define GPIO_INT_LVL_2_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_LVL_2_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_7_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_2_BIT_7_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_2_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_LVL_2_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_BIT_6_SHIFT)
+#define GPIO_INT_LVL_2_BIT_6_RANGE                      6:6
+#define GPIO_INT_LVL_2_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_LVL_2_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_6_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_2_BIT_6_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_2_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_LVL_2_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_BIT_5_SHIFT)
+#define GPIO_INT_LVL_2_BIT_5_RANGE                      5:5
+#define GPIO_INT_LVL_2_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_LVL_2_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_5_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_2_BIT_5_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_2_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_LVL_2_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_BIT_4_SHIFT)
+#define GPIO_INT_LVL_2_BIT_4_RANGE                      4:4
+#define GPIO_INT_LVL_2_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_LVL_2_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_4_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_2_BIT_4_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_2_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_LVL_2_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_BIT_3_SHIFT)
+#define GPIO_INT_LVL_2_BIT_3_RANGE                      3:3
+#define GPIO_INT_LVL_2_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_LVL_2_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_3_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_2_BIT_3_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_2_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_LVL_2_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_BIT_2_SHIFT)
+#define GPIO_INT_LVL_2_BIT_2_RANGE                      2:2
+#define GPIO_INT_LVL_2_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_LVL_2_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_2_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_2_BIT_2_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_2_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_LVL_2_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_BIT_1_SHIFT)
+#define GPIO_INT_LVL_2_BIT_1_RANGE                      1:1
+#define GPIO_INT_LVL_2_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_LVL_2_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_1_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_2_BIT_1_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_2_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_LVL_2_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_2_BIT_0_SHIFT)
+#define GPIO_INT_LVL_2_BIT_0_RANGE                      0:0
+#define GPIO_INT_LVL_2_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_LVL_2_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_2_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_2_BIT_0_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_2_BIT_0_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_LVL_3  
+#define GPIO_INT_LVL_3                  _MK_ADDR_CONST(0x6c)
+#define GPIO_INT_LVL_3_WORD_COUNT                       0x1
+#define GPIO_INT_LVL_3_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_RESET_MASK                       _MK_MASK_CONST(0xffffff)
+#define GPIO_INT_LVL_3_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_READ_MASK                        _MK_MASK_CONST(0xffffff)
+#define GPIO_INT_LVL_3_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_3_DELTA_7_SHIFT                    _MK_SHIFT_CONST(23)
+#define GPIO_INT_LVL_3_DELTA_7_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_DELTA_7_SHIFT)
+#define GPIO_INT_LVL_3_DELTA_7_RANGE                    23:23
+#define GPIO_INT_LVL_3_DELTA_7_WOFFSET                  0x0
+#define GPIO_INT_LVL_3_DELTA_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_DELTA_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_3_DELTA_6_SHIFT                    _MK_SHIFT_CONST(22)
+#define GPIO_INT_LVL_3_DELTA_6_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_DELTA_6_SHIFT)
+#define GPIO_INT_LVL_3_DELTA_6_RANGE                    22:22
+#define GPIO_INT_LVL_3_DELTA_6_WOFFSET                  0x0
+#define GPIO_INT_LVL_3_DELTA_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_DELTA_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_3_DELTA_5_SHIFT                    _MK_SHIFT_CONST(21)
+#define GPIO_INT_LVL_3_DELTA_5_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_DELTA_5_SHIFT)
+#define GPIO_INT_LVL_3_DELTA_5_RANGE                    21:21
+#define GPIO_INT_LVL_3_DELTA_5_WOFFSET                  0x0
+#define GPIO_INT_LVL_3_DELTA_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_DELTA_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_3_DELTA_4_SHIFT                    _MK_SHIFT_CONST(20)
+#define GPIO_INT_LVL_3_DELTA_4_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_DELTA_4_SHIFT)
+#define GPIO_INT_LVL_3_DELTA_4_RANGE                    20:20
+#define GPIO_INT_LVL_3_DELTA_4_WOFFSET                  0x0
+#define GPIO_INT_LVL_3_DELTA_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_DELTA_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_3_DELTA_3_SHIFT                    _MK_SHIFT_CONST(19)
+#define GPIO_INT_LVL_3_DELTA_3_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_DELTA_3_SHIFT)
+#define GPIO_INT_LVL_3_DELTA_3_RANGE                    19:19
+#define GPIO_INT_LVL_3_DELTA_3_WOFFSET                  0x0
+#define GPIO_INT_LVL_3_DELTA_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_DELTA_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_3_DELTA_2_SHIFT                    _MK_SHIFT_CONST(18)
+#define GPIO_INT_LVL_3_DELTA_2_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_DELTA_2_SHIFT)
+#define GPIO_INT_LVL_3_DELTA_2_RANGE                    18:18
+#define GPIO_INT_LVL_3_DELTA_2_WOFFSET                  0x0
+#define GPIO_INT_LVL_3_DELTA_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_DELTA_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_3_DELTA_1_SHIFT                    _MK_SHIFT_CONST(17)
+#define GPIO_INT_LVL_3_DELTA_1_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_DELTA_1_SHIFT)
+#define GPIO_INT_LVL_3_DELTA_1_RANGE                    17:17
+#define GPIO_INT_LVL_3_DELTA_1_WOFFSET                  0x0
+#define GPIO_INT_LVL_3_DELTA_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_DELTA_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Trigger Interrupt on ANY change of input if EDGE is TRUE
+#define GPIO_INT_LVL_3_DELTA_0_SHIFT                    _MK_SHIFT_CONST(16)
+#define GPIO_INT_LVL_3_DELTA_0_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_DELTA_0_SHIFT)
+#define GPIO_INT_LVL_3_DELTA_0_RANGE                    16:16
+#define GPIO_INT_LVL_3_DELTA_0_WOFFSET                  0x0
+#define GPIO_INT_LVL_3_DELTA_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_DELTA_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_DELTA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_3_EDGE_7_SHIFT                     _MK_SHIFT_CONST(15)
+#define GPIO_INT_LVL_3_EDGE_7_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_EDGE_7_SHIFT)
+#define GPIO_INT_LVL_3_EDGE_7_RANGE                     15:15
+#define GPIO_INT_LVL_3_EDGE_7_WOFFSET                   0x0
+#define GPIO_INT_LVL_3_EDGE_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_EDGE_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_3_EDGE_6_SHIFT                     _MK_SHIFT_CONST(14)
+#define GPIO_INT_LVL_3_EDGE_6_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_EDGE_6_SHIFT)
+#define GPIO_INT_LVL_3_EDGE_6_RANGE                     14:14
+#define GPIO_INT_LVL_3_EDGE_6_WOFFSET                   0x0
+#define GPIO_INT_LVL_3_EDGE_6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_EDGE_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_3_EDGE_5_SHIFT                     _MK_SHIFT_CONST(13)
+#define GPIO_INT_LVL_3_EDGE_5_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_EDGE_5_SHIFT)
+#define GPIO_INT_LVL_3_EDGE_5_RANGE                     13:13
+#define GPIO_INT_LVL_3_EDGE_5_WOFFSET                   0x0
+#define GPIO_INT_LVL_3_EDGE_5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_EDGE_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_3_EDGE_4_SHIFT                     _MK_SHIFT_CONST(12)
+#define GPIO_INT_LVL_3_EDGE_4_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_EDGE_4_SHIFT)
+#define GPIO_INT_LVL_3_EDGE_4_RANGE                     12:12
+#define GPIO_INT_LVL_3_EDGE_4_WOFFSET                   0x0
+#define GPIO_INT_LVL_3_EDGE_4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_EDGE_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_3_EDGE_3_SHIFT                     _MK_SHIFT_CONST(11)
+#define GPIO_INT_LVL_3_EDGE_3_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_EDGE_3_SHIFT)
+#define GPIO_INT_LVL_3_EDGE_3_RANGE                     11:11
+#define GPIO_INT_LVL_3_EDGE_3_WOFFSET                   0x0
+#define GPIO_INT_LVL_3_EDGE_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_EDGE_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_3_EDGE_2_SHIFT                     _MK_SHIFT_CONST(10)
+#define GPIO_INT_LVL_3_EDGE_2_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_EDGE_2_SHIFT)
+#define GPIO_INT_LVL_3_EDGE_2_RANGE                     10:10
+#define GPIO_INT_LVL_3_EDGE_2_WOFFSET                   0x0
+#define GPIO_INT_LVL_3_EDGE_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_EDGE_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_3_EDGE_1_SHIFT                     _MK_SHIFT_CONST(9)
+#define GPIO_INT_LVL_3_EDGE_1_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_EDGE_1_SHIFT)
+#define GPIO_INT_LVL_3_EDGE_1_RANGE                     9:9
+#define GPIO_INT_LVL_3_EDGE_1_WOFFSET                   0x0
+#define GPIO_INT_LVL_3_EDGE_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_EDGE_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 means Configure as Edge-Triggerred Interrupt
+#define GPIO_INT_LVL_3_EDGE_0_SHIFT                     _MK_SHIFT_CONST(8)
+#define GPIO_INT_LVL_3_EDGE_0_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_EDGE_0_SHIFT)
+#define GPIO_INT_LVL_3_EDGE_0_RANGE                     8:8
+#define GPIO_INT_LVL_3_EDGE_0_WOFFSET                   0x0
+#define GPIO_INT_LVL_3_EDGE_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_EDGE_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_EDGE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_3_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_LVL_3_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_BIT_7_SHIFT)
+#define GPIO_INT_LVL_3_BIT_7_RANGE                      7:7
+#define GPIO_INT_LVL_3_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_LVL_3_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_7_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_3_BIT_7_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_3_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_LVL_3_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_BIT_6_SHIFT)
+#define GPIO_INT_LVL_3_BIT_6_RANGE                      6:6
+#define GPIO_INT_LVL_3_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_LVL_3_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_6_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_3_BIT_6_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_3_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_LVL_3_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_BIT_5_SHIFT)
+#define GPIO_INT_LVL_3_BIT_5_RANGE                      5:5
+#define GPIO_INT_LVL_3_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_LVL_3_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_5_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_3_BIT_5_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_3_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_LVL_3_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_BIT_4_SHIFT)
+#define GPIO_INT_LVL_3_BIT_4_RANGE                      4:4
+#define GPIO_INT_LVL_3_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_LVL_3_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_4_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_3_BIT_4_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_3_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_LVL_3_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_BIT_3_SHIFT)
+#define GPIO_INT_LVL_3_BIT_3_RANGE                      3:3
+#define GPIO_INT_LVL_3_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_LVL_3_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_3_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_3_BIT_3_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_3_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_LVL_3_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_BIT_2_SHIFT)
+#define GPIO_INT_LVL_3_BIT_2_RANGE                      2:2
+#define GPIO_INT_LVL_3_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_LVL_3_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_2_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_3_BIT_2_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_3_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_LVL_3_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_BIT_1_SHIFT)
+#define GPIO_INT_LVL_3_BIT_1_RANGE                      1:1
+#define GPIO_INT_LVL_3_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_LVL_3_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_1_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_3_BIT_1_HIGH                       _MK_ENUM_CONST(1)
+
+// Interrupt Activation Level or Edge (HIGH for High level or Rising Edge)
+#define GPIO_INT_LVL_3_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_LVL_3_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_LVL_3_BIT_0_SHIFT)
+#define GPIO_INT_LVL_3_BIT_0_RANGE                      0:0
+#define GPIO_INT_LVL_3_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_LVL_3_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_LVL_3_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_LVL_3_BIT_0_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_INT_LVL_3_BIT_0_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_CLR_0  
+#define GPIO_INT_CLR_0                  _MK_ADDR_CONST(0x70)
+#define GPIO_INT_CLR_0_WORD_COUNT                       0x1
+#define GPIO_INT_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_0_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_CLR_0_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_0_BIT_7_SHIFT)
+#define GPIO_INT_CLR_0_BIT_7_RANGE                      7:7
+#define GPIO_INT_CLR_0_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_CLR_0_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_0_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_7_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_0_BIT_7_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_0_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_CLR_0_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_0_BIT_6_SHIFT)
+#define GPIO_INT_CLR_0_BIT_6_RANGE                      6:6
+#define GPIO_INT_CLR_0_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_CLR_0_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_0_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_6_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_0_BIT_6_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_0_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_CLR_0_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_0_BIT_5_SHIFT)
+#define GPIO_INT_CLR_0_BIT_5_RANGE                      5:5
+#define GPIO_INT_CLR_0_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_CLR_0_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_0_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_5_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_0_BIT_5_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_0_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_CLR_0_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_0_BIT_4_SHIFT)
+#define GPIO_INT_CLR_0_BIT_4_RANGE                      4:4
+#define GPIO_INT_CLR_0_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_CLR_0_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_0_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_4_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_0_BIT_4_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_0_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_CLR_0_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_0_BIT_3_SHIFT)
+#define GPIO_INT_CLR_0_BIT_3_RANGE                      3:3
+#define GPIO_INT_CLR_0_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_CLR_0_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_0_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_3_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_0_BIT_3_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_0_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_CLR_0_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_0_BIT_2_SHIFT)
+#define GPIO_INT_CLR_0_BIT_2_RANGE                      2:2
+#define GPIO_INT_CLR_0_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_CLR_0_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_0_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_2_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_0_BIT_2_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_0_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_CLR_0_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_0_BIT_1_SHIFT)
+#define GPIO_INT_CLR_0_BIT_1_RANGE                      1:1
+#define GPIO_INT_CLR_0_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_CLR_0_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_0_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_1_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_0_BIT_1_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_0_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_CLR_0_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_0_BIT_0_SHIFT)
+#define GPIO_INT_CLR_0_BIT_0_RANGE                      0:0
+#define GPIO_INT_CLR_0_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_CLR_0_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_0_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_0_BIT_0_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_0_BIT_0_CLEAR                      _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_CLR  
+#define GPIO_INT_CLR                    _MK_ADDR_CONST(0x70)
+#define GPIO_INT_CLR_WORD_COUNT                         0x1
+#define GPIO_INT_CLR_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define GPIO_INT_CLR_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_READ_MASK                  _MK_MASK_CONST(0xff)
+#define GPIO_INT_CLR_WRITE_MASK                         _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_BIT_7_SHIFT                        _MK_SHIFT_CONST(7)
+#define GPIO_INT_CLR_BIT_7_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_BIT_7_SHIFT)
+#define GPIO_INT_CLR_BIT_7_RANGE                        7:7
+#define GPIO_INT_CLR_BIT_7_WOFFSET                      0x0
+#define GPIO_INT_CLR_BIT_7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_BIT_7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_7_SET                  _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_BIT_7_CLEAR                        _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_BIT_6_SHIFT                        _MK_SHIFT_CONST(6)
+#define GPIO_INT_CLR_BIT_6_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_BIT_6_SHIFT)
+#define GPIO_INT_CLR_BIT_6_RANGE                        6:6
+#define GPIO_INT_CLR_BIT_6_WOFFSET                      0x0
+#define GPIO_INT_CLR_BIT_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_BIT_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_6_SET                  _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_BIT_6_CLEAR                        _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_BIT_5_SHIFT                        _MK_SHIFT_CONST(5)
+#define GPIO_INT_CLR_BIT_5_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_BIT_5_SHIFT)
+#define GPIO_INT_CLR_BIT_5_RANGE                        5:5
+#define GPIO_INT_CLR_BIT_5_WOFFSET                      0x0
+#define GPIO_INT_CLR_BIT_5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_BIT_5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_5_SET                  _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_BIT_5_CLEAR                        _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_BIT_4_SHIFT                        _MK_SHIFT_CONST(4)
+#define GPIO_INT_CLR_BIT_4_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_BIT_4_SHIFT)
+#define GPIO_INT_CLR_BIT_4_RANGE                        4:4
+#define GPIO_INT_CLR_BIT_4_WOFFSET                      0x0
+#define GPIO_INT_CLR_BIT_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_BIT_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_4_SET                  _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_BIT_4_CLEAR                        _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_BIT_3_SHIFT                        _MK_SHIFT_CONST(3)
+#define GPIO_INT_CLR_BIT_3_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_BIT_3_SHIFT)
+#define GPIO_INT_CLR_BIT_3_RANGE                        3:3
+#define GPIO_INT_CLR_BIT_3_WOFFSET                      0x0
+#define GPIO_INT_CLR_BIT_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_BIT_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_3_SET                  _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_BIT_3_CLEAR                        _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_BIT_2_SHIFT                        _MK_SHIFT_CONST(2)
+#define GPIO_INT_CLR_BIT_2_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_BIT_2_SHIFT)
+#define GPIO_INT_CLR_BIT_2_RANGE                        2:2
+#define GPIO_INT_CLR_BIT_2_WOFFSET                      0x0
+#define GPIO_INT_CLR_BIT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_BIT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_2_SET                  _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_BIT_2_CLEAR                        _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_BIT_1_SHIFT                        _MK_SHIFT_CONST(1)
+#define GPIO_INT_CLR_BIT_1_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_BIT_1_SHIFT)
+#define GPIO_INT_CLR_BIT_1_RANGE                        1:1
+#define GPIO_INT_CLR_BIT_1_WOFFSET                      0x0
+#define GPIO_INT_CLR_BIT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_BIT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_1_SET                  _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_BIT_1_CLEAR                        _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_BIT_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define GPIO_INT_CLR_BIT_0_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_BIT_0_SHIFT)
+#define GPIO_INT_CLR_BIT_0_RANGE                        0:0
+#define GPIO_INT_CLR_BIT_0_WOFFSET                      0x0
+#define GPIO_INT_CLR_BIT_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_BIT_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_BIT_0_SET                  _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_BIT_0_CLEAR                        _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_CLR_1  
+#define GPIO_INT_CLR_1                  _MK_ADDR_CONST(0x74)
+#define GPIO_INT_CLR_1_WORD_COUNT                       0x1
+#define GPIO_INT_CLR_1_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_CLR_1_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_CLR_1_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_1_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_CLR_1_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_1_BIT_7_SHIFT)
+#define GPIO_INT_CLR_1_BIT_7_RANGE                      7:7
+#define GPIO_INT_CLR_1_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_CLR_1_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_1_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_7_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_1_BIT_7_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_1_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_CLR_1_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_1_BIT_6_SHIFT)
+#define GPIO_INT_CLR_1_BIT_6_RANGE                      6:6
+#define GPIO_INT_CLR_1_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_CLR_1_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_1_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_6_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_1_BIT_6_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_1_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_CLR_1_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_1_BIT_5_SHIFT)
+#define GPIO_INT_CLR_1_BIT_5_RANGE                      5:5
+#define GPIO_INT_CLR_1_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_CLR_1_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_1_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_5_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_1_BIT_5_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_1_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_CLR_1_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_1_BIT_4_SHIFT)
+#define GPIO_INT_CLR_1_BIT_4_RANGE                      4:4
+#define GPIO_INT_CLR_1_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_CLR_1_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_1_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_4_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_1_BIT_4_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_1_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_CLR_1_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_1_BIT_3_SHIFT)
+#define GPIO_INT_CLR_1_BIT_3_RANGE                      3:3
+#define GPIO_INT_CLR_1_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_CLR_1_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_1_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_3_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_1_BIT_3_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_1_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_CLR_1_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_1_BIT_2_SHIFT)
+#define GPIO_INT_CLR_1_BIT_2_RANGE                      2:2
+#define GPIO_INT_CLR_1_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_CLR_1_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_1_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_2_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_1_BIT_2_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_1_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_CLR_1_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_1_BIT_1_SHIFT)
+#define GPIO_INT_CLR_1_BIT_1_RANGE                      1:1
+#define GPIO_INT_CLR_1_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_CLR_1_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_1_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_1_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_1_BIT_1_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_1_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_CLR_1_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_1_BIT_0_SHIFT)
+#define GPIO_INT_CLR_1_BIT_0_RANGE                      0:0
+#define GPIO_INT_CLR_1_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_CLR_1_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_1_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_1_BIT_0_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_1_BIT_0_CLEAR                      _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_CLR_2  
+#define GPIO_INT_CLR_2                  _MK_ADDR_CONST(0x78)
+#define GPIO_INT_CLR_2_WORD_COUNT                       0x1
+#define GPIO_INT_CLR_2_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_CLR_2_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_CLR_2_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_2_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_CLR_2_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_2_BIT_7_SHIFT)
+#define GPIO_INT_CLR_2_BIT_7_RANGE                      7:7
+#define GPIO_INT_CLR_2_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_CLR_2_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_2_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_7_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_2_BIT_7_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_2_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_CLR_2_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_2_BIT_6_SHIFT)
+#define GPIO_INT_CLR_2_BIT_6_RANGE                      6:6
+#define GPIO_INT_CLR_2_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_CLR_2_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_2_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_6_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_2_BIT_6_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_2_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_CLR_2_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_2_BIT_5_SHIFT)
+#define GPIO_INT_CLR_2_BIT_5_RANGE                      5:5
+#define GPIO_INT_CLR_2_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_CLR_2_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_2_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_5_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_2_BIT_5_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_2_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_CLR_2_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_2_BIT_4_SHIFT)
+#define GPIO_INT_CLR_2_BIT_4_RANGE                      4:4
+#define GPIO_INT_CLR_2_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_CLR_2_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_2_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_4_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_2_BIT_4_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_2_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_CLR_2_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_2_BIT_3_SHIFT)
+#define GPIO_INT_CLR_2_BIT_3_RANGE                      3:3
+#define GPIO_INT_CLR_2_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_CLR_2_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_2_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_3_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_2_BIT_3_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_2_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_CLR_2_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_2_BIT_2_SHIFT)
+#define GPIO_INT_CLR_2_BIT_2_RANGE                      2:2
+#define GPIO_INT_CLR_2_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_CLR_2_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_2_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_2_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_2_BIT_2_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_2_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_CLR_2_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_2_BIT_1_SHIFT)
+#define GPIO_INT_CLR_2_BIT_1_RANGE                      1:1
+#define GPIO_INT_CLR_2_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_CLR_2_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_2_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_1_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_2_BIT_1_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_2_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_CLR_2_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_2_BIT_0_SHIFT)
+#define GPIO_INT_CLR_2_BIT_0_RANGE                      0:0
+#define GPIO_INT_CLR_2_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_CLR_2_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_2_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_2_BIT_0_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_2_BIT_0_CLEAR                      _MK_ENUM_CONST(1)
+
+
+// Register GPIO_INT_CLR_3  
+#define GPIO_INT_CLR_3                  _MK_ADDR_CONST(0x7c)
+#define GPIO_INT_CLR_3_WORD_COUNT                       0x1
+#define GPIO_INT_CLR_3_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define GPIO_INT_CLR_3_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_INT_CLR_3_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_3_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_INT_CLR_3_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_3_BIT_7_SHIFT)
+#define GPIO_INT_CLR_3_BIT_7_RANGE                      7:7
+#define GPIO_INT_CLR_3_BIT_7_WOFFSET                    0x0
+#define GPIO_INT_CLR_3_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_3_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_7_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_3_BIT_7_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_3_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_INT_CLR_3_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_3_BIT_6_SHIFT)
+#define GPIO_INT_CLR_3_BIT_6_RANGE                      6:6
+#define GPIO_INT_CLR_3_BIT_6_WOFFSET                    0x0
+#define GPIO_INT_CLR_3_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_3_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_6_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_3_BIT_6_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_3_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_INT_CLR_3_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_3_BIT_5_SHIFT)
+#define GPIO_INT_CLR_3_BIT_5_RANGE                      5:5
+#define GPIO_INT_CLR_3_BIT_5_WOFFSET                    0x0
+#define GPIO_INT_CLR_3_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_3_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_5_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_3_BIT_5_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_3_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_INT_CLR_3_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_3_BIT_4_SHIFT)
+#define GPIO_INT_CLR_3_BIT_4_RANGE                      4:4
+#define GPIO_INT_CLR_3_BIT_4_WOFFSET                    0x0
+#define GPIO_INT_CLR_3_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_3_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_4_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_3_BIT_4_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_3_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_INT_CLR_3_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_3_BIT_3_SHIFT)
+#define GPIO_INT_CLR_3_BIT_3_RANGE                      3:3
+#define GPIO_INT_CLR_3_BIT_3_WOFFSET                    0x0
+#define GPIO_INT_CLR_3_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_3_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_3_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_3_BIT_3_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_3_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_INT_CLR_3_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_3_BIT_2_SHIFT)
+#define GPIO_INT_CLR_3_BIT_2_RANGE                      2:2
+#define GPIO_INT_CLR_3_BIT_2_WOFFSET                    0x0
+#define GPIO_INT_CLR_3_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_3_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_2_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_3_BIT_2_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_3_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_INT_CLR_3_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_3_BIT_1_SHIFT)
+#define GPIO_INT_CLR_3_BIT_1_RANGE                      1:1
+#define GPIO_INT_CLR_3_BIT_1_WOFFSET                    0x0
+#define GPIO_INT_CLR_3_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_3_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_1_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_3_BIT_1_CLEAR                      _MK_ENUM_CONST(1)
+
+// GPIO mode (GPIO_CNF.x=1) and GPIO_INT.ENB.x=1 must be true for this condition to be valid.
+#define GPIO_INT_CLR_3_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_INT_CLR_3_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_INT_CLR_3_BIT_0_SHIFT)
+#define GPIO_INT_CLR_3_BIT_0_RANGE                      0:0
+#define GPIO_INT_CLR_3_BIT_0_WOFFSET                    0x0
+#define GPIO_INT_CLR_3_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_INT_CLR_3_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_INT_CLR_3_BIT_0_SET                        _MK_ENUM_CONST(0)
+#define GPIO_INT_CLR_3_BIT_0_CLEAR                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Reserved address 240 [0xf0] 
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Reserved address 256 [0x100] 
+
+// Reserved address 260 [0x104] 
+
+// Reserved address 264 [0x108] 
+
+// Reserved address 268 [0x10c] 
+
+// Reserved address 272 [0x110] 
+
+// Reserved address 276 [0x114] 
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Reserved address 288 [0x120] 
+
+// Reserved address 292 [0x124] 
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Reserved address 320 [0x140] 
+
+// Reserved address 324 [0x144] 
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Reserved address 336 [0x150] 
+
+// Reserved address 340 [0x154] 
+
+// Reserved address 344 [0x158] 
+
+// Reserved address 348 [0x15c] 
+
+// Reserved address 352 [0x160] 
+
+// Reserved address 356 [0x164] 
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Reserved address 384 [0x180] 
+
+// Reserved address 388 [0x184] 
+
+// Reserved address 392 [0x188] 
+
+// Reserved address 396 [0x18c] 
+
+// Reserved address 400 [0x190] 
+
+// Reserved address 404 [0x194] 
+
+// Reserved address 408 [0x198] 
+
+// Reserved address 412 [0x19c] 
+
+// Reserved address 416 [0x1a0] 
+
+// Reserved address 420 [0x1a4] 
+
+// Reserved address 424 [0x1a8] 
+
+// Reserved address 428 [0x1ac] 
+
+// Reserved address 432 [0x1b0] 
+
+// Reserved address 436 [0x1b4] 
+
+// Reserved address 440 [0x1b8] 
+
+// Reserved address 444 [0x1bc] 
+
+// Reserved address 448 [0x1c0] 
+
+// Reserved address 452 [0x1c4] 
+
+// Reserved address 456 [0x1c8] 
+
+// Reserved address 460 [0x1cc] 
+
+// Reserved address 464 [0x1d0] 
+
+// Reserved address 468 [0x1d4] 
+
+// Reserved address 472 [0x1d8] 
+
+// Reserved address 476 [0x1dc] 
+
+// Reserved address 480 [0x1e0] 
+
+// Reserved address 484 [0x1e4] 
+
+// Reserved address 488 [0x1e8] 
+
+// Reserved address 492 [0x1ec] 
+
+// Reserved address 496 [0x1f0] 
+
+// Reserved address 500 [0x1f4] 
+
+// Reserved address 504 [0x1f8] 
+
+// Reserved address 508 [0x1fc] 
+
+// Reserved address 512 [0x200] 
+
+// Reserved address 516 [0x204] 
+
+// Reserved address 520 [0x208] 
+
+// Reserved address 524 [0x20c] 
+
+// Reserved address 528 [0x210] 
+
+// Reserved address 532 [0x214] 
+
+// Reserved address 536 [0x218] 
+
+// Reserved address 540 [0x21c] 
+
+// Reserved address 544 [0x220] 
+
+// Reserved address 548 [0x224] 
+
+// Reserved address 552 [0x228] 
+
+// Reserved address 556 [0x22c] 
+
+// Reserved address 560 [0x230] 
+
+// Reserved address 564 [0x234] 
+
+// Reserved address 568 [0x238] 
+
+// Reserved address 572 [0x23c] 
+
+// Reserved address 576 [0x240] 
+
+// Reserved address 580 [0x244] 
+
+// Reserved address 584 [0x248] 
+
+// Reserved address 588 [0x24c] 
+
+// Reserved address 592 [0x250] 
+
+// Reserved address 596 [0x254] 
+
+// Reserved address 600 [0x258] 
+
+// Reserved address 604 [0x25c] 
+
+// Reserved address 608 [0x260] 
+
+// Reserved address 612 [0x264] 
+
+// Reserved address 616 [0x268] 
+
+// Reserved address 620 [0x26c] 
+
+// Reserved address 624 [0x270] 
+
+// Reserved address 628 [0x274] 
+
+// Reserved address 632 [0x278] 
+
+// Reserved address 636 [0x27c] 
+
+// Reserved address 640 [0x280] 
+
+// Reserved address 644 [0x284] 
+
+// Reserved address 648 [0x288] 
+
+// Reserved address 652 [0x28c] 
+
+// Reserved address 656 [0x290] 
+
+// Reserved address 660 [0x294] 
+
+// Reserved address 664 [0x298] 
+
+// Reserved address 668 [0x29c] 
+
+// Reserved address 672 [0x2a0] 
+
+// Reserved address 676 [0x2a4] 
+
+// Reserved address 680 [0x2a8] 
+
+// Reserved address 684 [0x2ac] 
+
+// Reserved address 688 [0x2b0] 
+
+// Reserved address 692 [0x2b4] 
+
+// Reserved address 696 [0x2b8] 
+
+// Reserved address 700 [0x2bc] 
+
+// Reserved address 704 [0x2c0] 
+
+// Reserved address 708 [0x2c4] 
+
+// Reserved address 712 [0x2c8] 
+
+// Reserved address 716 [0x2cc] 
+
+// Reserved address 720 [0x2d0] 
+
+// Reserved address 724 [0x2d4] 
+
+// Reserved address 728 [0x2d8] 
+
+// Reserved address 732 [0x2dc] 
+
+// Reserved address 736 [0x2e0] 
+
+// Reserved address 740 [0x2e4] 
+
+// Reserved address 744 [0x2e8] 
+
+// Reserved address 748 [0x2ec] 
+
+// Reserved address 752 [0x2f0] 
+
+// Reserved address 756 [0x2f4] 
+
+// Reserved address 760 [0x2f8] 
+
+// Reserved address 764 [0x2fc] 
+
+// Reserved address 768 [0x300] 
+
+// Reserved address 772 [0x304] 
+
+// Reserved address 776 [0x308] 
+
+// Reserved address 780 [0x30c] 
+
+// Reserved address 784 [0x310] 
+
+// Reserved address 788 [0x314] 
+
+// Reserved address 792 [0x318] 
+
+// Reserved address 796 [0x31c] 
+
+// Reserved address 800 [0x320] 
+
+// Reserved address 804 [0x324] 
+
+// Reserved address 808 [0x328] 
+
+// Reserved address 812 [0x32c] 
+
+// Reserved address 816 [0x330] 
+
+// Reserved address 820 [0x334] 
+
+// Reserved address 824 [0x338] 
+
+// Reserved address 828 [0x33c] 
+
+// Reserved address 832 [0x340] 
+
+// Reserved address 836 [0x344] 
+
+// Reserved address 840 [0x348] 
+
+// Reserved address 844 [0x34c] 
+
+// Reserved address 848 [0x350] 
+
+// Reserved address 852 [0x354] 
+
+// Reserved address 856 [0x358] 
+
+// Reserved address 860 [0x35c] 
+
+// Reserved address 864 [0x360] 
+
+// Reserved address 868 [0x364] 
+
+// Reserved address 872 [0x368] 
+
+// Reserved address 876 [0x36c] 
+
+// Reserved address 880 [0x370] 
+
+// Reserved address 884 [0x374] 
+
+// Reserved address 888 [0x378] 
+
+// Reserved address 892 [0x37c] 
+
+// Reserved address 896 [0x380] 
+
+// Reserved address 900 [0x384] 
+
+// Reserved address 904 [0x388] 
+
+// Reserved address 908 [0x38c] 
+
+// Reserved address 912 [0x390] 
+
+// Reserved address 916 [0x394] 
+
+// Reserved address 920 [0x398] 
+
+// Reserved address 924 [0x39c] 
+
+// Reserved address 928 [0x3a0] 
+
+// Reserved address 932 [0x3a4] 
+
+// Reserved address 936 [0x3a8] 
+
+// Reserved address 940 [0x3ac] 
+
+// Reserved address 944 [0x3b0] 
+
+// Reserved address 948 [0x3b4] 
+
+// Reserved address 952 [0x3b8] 
+
+// Reserved address 956 [0x3bc] 
+
+// Reserved address 960 [0x3c0] 
+
+// Reserved address 964 [0x3c4] 
+
+// Reserved address 968 [0x3c8] 
+
+// Reserved address 972 [0x3cc] 
+
+// Reserved address 976 [0x3d0] 
+
+// Reserved address 980 [0x3d4] 
+
+// Reserved address 984 [0x3d8] 
+
+// Reserved address 988 [0x3dc] 
+
+// Reserved address 992 [0x3e0] 
+
+// Reserved address 996 [0x3e4] 
+
+// Reserved address 1000 [0x3e8] 
+
+// Reserved address 1004 [0x3ec] 
+
+// Reserved address 1008 [0x3f0] 
+
+// Reserved address 1012 [0x3f4] 
+
+// Reserved address 1016 [0x3f8] 
+
+// Reserved address 1020 [0x3fc] 
+
+// Reserved address 1024 [0x400] 
+
+// Reserved address 1028 [0x404] 
+
+// Reserved address 1032 [0x408] 
+
+// Reserved address 1036 [0x40c] 
+
+// Reserved address 1040 [0x410] 
+
+// Reserved address 1044 [0x414] 
+
+// Reserved address 1048 [0x418] 
+
+// Reserved address 1052 [0x41c] 
+
+// Reserved address 1056 [0x420] 
+
+// Reserved address 1060 [0x424] 
+
+// Reserved address 1064 [0x428] 
+
+// Reserved address 1068 [0x42c] 
+
+// Reserved address 1072 [0x430] 
+
+// Reserved address 1076 [0x434] 
+
+// Reserved address 1080 [0x438] 
+
+// Reserved address 1084 [0x43c] 
+
+// Reserved address 1088 [0x440] 
+
+// Reserved address 1092 [0x444] 
+
+// Reserved address 1096 [0x448] 
+
+// Reserved address 1100 [0x44c] 
+
+// Reserved address 1104 [0x450] 
+
+// Reserved address 1108 [0x454] 
+
+// Reserved address 1112 [0x458] 
+
+// Reserved address 1116 [0x45c] 
+
+// Reserved address 1120 [0x460] 
+
+// Reserved address 1124 [0x464] 
+
+// Reserved address 1128 [0x468] 
+
+// Reserved address 1132 [0x46c] 
+
+// Reserved address 1136 [0x470] 
+
+// Reserved address 1140 [0x474] 
+
+// Reserved address 1144 [0x478] 
+
+// Reserved address 1148 [0x47c] 
+
+// Reserved address 1152 [0x480] 
+
+// Reserved address 1156 [0x484] 
+
+// Reserved address 1160 [0x488] 
+
+// Reserved address 1164 [0x48c] 
+
+// Reserved address 1168 [0x490] 
+
+// Reserved address 1172 [0x494] 
+
+// Reserved address 1176 [0x498] 
+
+// Reserved address 1180 [0x49c] 
+
+// Reserved address 1184 [0x4a0] 
+
+// Reserved address 1188 [0x4a4] 
+
+// Reserved address 1192 [0x4a8] 
+
+// Reserved address 1196 [0x4ac] 
+
+// Reserved address 1200 [0x4b0] 
+
+// Reserved address 1204 [0x4b4] 
+
+// Reserved address 1208 [0x4b8] 
+
+// Reserved address 1212 [0x4bc] 
+
+// Reserved address 1216 [0x4c0] 
+
+// Reserved address 1220 [0x4c4] 
+
+// Reserved address 1224 [0x4c8] 
+
+// Reserved address 1228 [0x4cc] 
+
+// Reserved address 1232 [0x4d0] 
+
+// Reserved address 1236 [0x4d4] 
+
+// Reserved address 1240 [0x4d8] 
+
+// Reserved address 1244 [0x4dc] 
+
+// Reserved address 1248 [0x4e0] 
+
+// Reserved address 1252 [0x4e4] 
+
+// Reserved address 1256 [0x4e8] 
+
+// Reserved address 1260 [0x4ec] 
+
+// Reserved address 1264 [0x4f0] 
+
+// Reserved address 1268 [0x4f4] 
+
+// Reserved address 1272 [0x4f8] 
+
+// Reserved address 1276 [0x4fc] 
+
+// Reserved address 1280 [0x500] 
+
+// Reserved address 1284 [0x504] 
+
+// Reserved address 1288 [0x508] 
+
+// Reserved address 1292 [0x50c] 
+
+// Reserved address 1296 [0x510] 
+
+// Reserved address 1300 [0x514] 
+
+// Reserved address 1304 [0x518] 
+
+// Reserved address 1308 [0x51c] 
+
+// Reserved address 1312 [0x520] 
+
+// Reserved address 1316 [0x524] 
+
+// Reserved address 1320 [0x528] 
+
+// Reserved address 1324 [0x52c] 
+
+// Reserved address 1328 [0x530] 
+
+// Reserved address 1332 [0x534] 
+
+// Reserved address 1336 [0x538] 
+
+// Reserved address 1340 [0x53c] 
+
+// Reserved address 1344 [0x540] 
+
+// Reserved address 1348 [0x544] 
+
+// Reserved address 1352 [0x548] 
+
+// Reserved address 1356 [0x54c] 
+
+// Reserved address 1360 [0x550] 
+
+// Reserved address 1364 [0x554] 
+
+// Reserved address 1368 [0x558] 
+
+// Reserved address 1372 [0x55c] 
+
+// Reserved address 1376 [0x560] 
+
+// Reserved address 1380 [0x564] 
+
+// Reserved address 1384 [0x568] 
+
+// Reserved address 1388 [0x56c] 
+
+// Reserved address 1392 [0x570] 
+
+// Reserved address 1396 [0x574] 
+
+// Reserved address 1400 [0x578] 
+
+// Reserved address 1404 [0x57c] 
+
+// Reserved address 1408 [0x580] 
+
+// Reserved address 1412 [0x584] 
+
+// Reserved address 1416 [0x588] 
+
+// Reserved address 1420 [0x58c] 
+
+// Reserved address 1424 [0x590] 
+
+// Reserved address 1428 [0x594] 
+
+// Reserved address 1432 [0x598] 
+
+// Reserved address 1436 [0x59c] 
+
+// Reserved address 1440 [0x5a0] 
+
+// Reserved address 1444 [0x5a4] 
+
+// Reserved address 1448 [0x5a8] 
+
+// Reserved address 1452 [0x5ac] 
+
+// Reserved address 1456 [0x5b0] 
+
+// Reserved address 1460 [0x5b4] 
+
+// Reserved address 1464 [0x5b8] 
+
+// Reserved address 1468 [0x5bc] 
+
+// Reserved address 1472 [0x5c0] 
+
+// Reserved address 1476 [0x5c4] 
+
+// Reserved address 1480 [0x5c8] 
+
+// Reserved address 1484 [0x5cc] 
+
+// Reserved address 1488 [0x5d0] 
+
+// Reserved address 1492 [0x5d4] 
+
+// Reserved address 1496 [0x5d8] 
+
+// Reserved address 1500 [0x5dc] 
+
+// Reserved address 1504 [0x5e0] 
+
+// Reserved address 1508 [0x5e4] 
+
+// Reserved address 1512 [0x5e8] 
+
+// Reserved address 1516 [0x5ec] 
+
+// Reserved address 1520 [0x5f0] 
+
+// Reserved address 1524 [0x5f4] 
+
+// Reserved address 1528 [0x5f8] 
+
+// Reserved address 1532 [0x5fc] 
+
+// Reserved address 1536 [0x600] 
+
+// Reserved address 1540 [0x604] 
+
+// Reserved address 1544 [0x608] 
+
+// Reserved address 1548 [0x60c] 
+
+// Reserved address 1552 [0x610] 
+
+// Reserved address 1556 [0x614] 
+
+// Reserved address 1560 [0x618] 
+
+// Reserved address 1564 [0x61c] 
+
+// Reserved address 1568 [0x620] 
+
+// Reserved address 1572 [0x624] 
+
+// Reserved address 1576 [0x628] 
+
+// Reserved address 1580 [0x62c] 
+
+// Reserved address 1584 [0x630] 
+
+// Reserved address 1588 [0x634] 
+
+// Reserved address 1592 [0x638] 
+
+// Reserved address 1596 [0x63c] 
+
+// Reserved address 1600 [0x640] 
+
+// Reserved address 1604 [0x644] 
+
+// Reserved address 1608 [0x648] 
+
+// Reserved address 1612 [0x64c] 
+
+// Reserved address 1616 [0x650] 
+
+// Reserved address 1620 [0x654] 
+
+// Reserved address 1624 [0x658] 
+
+// Reserved address 1628 [0x65c] 
+
+// Reserved address 1632 [0x660] 
+
+// Reserved address 1636 [0x664] 
+
+// Reserved address 1640 [0x668] 
+
+// Reserved address 1644 [0x66c] 
+
+// Reserved address 1648 [0x670] 
+
+// Reserved address 1652 [0x674] 
+
+// Reserved address 1656 [0x678] 
+
+// Reserved address 1660 [0x67c] 
+
+// Reserved address 1664 [0x680] 
+
+// Reserved address 1668 [0x684] 
+
+// Reserved address 1672 [0x688] 
+
+// Reserved address 1676 [0x68c] 
+
+// Reserved address 1680 [0x690] 
+
+// Reserved address 1684 [0x694] 
+
+// Reserved address 1688 [0x698] 
+
+// Reserved address 1692 [0x69c] 
+
+// Reserved address 1696 [0x6a0] 
+
+// Reserved address 1700 [0x6a4] 
+
+// Reserved address 1704 [0x6a8] 
+
+// Reserved address 1708 [0x6ac] 
+
+// Reserved address 1712 [0x6b0] 
+
+// Reserved address 1716 [0x6b4] 
+
+// Reserved address 1720 [0x6b8] 
+
+// Reserved address 1724 [0x6bc] 
+
+// Reserved address 1728 [0x6c0] 
+
+// Reserved address 1732 [0x6c4] 
+
+// Reserved address 1736 [0x6c8] 
+
+// Reserved address 1740 [0x6cc] 
+
+// Reserved address 1744 [0x6d0] 
+
+// Reserved address 1748 [0x6d4] 
+
+// Reserved address 1752 [0x6d8] 
+
+// Reserved address 1756 [0x6dc] 
+
+// Reserved address 1760 [0x6e0] 
+
+// Reserved address 1764 [0x6e4] 
+
+// Reserved address 1768 [0x6e8] 
+
+// Reserved address 1772 [0x6ec] 
+
+// Reserved address 1776 [0x6f0] 
+
+// Reserved address 1780 [0x6f4] 
+
+// Reserved address 1784 [0x6f8] 
+
+// Reserved address 1788 [0x6fc] 
+
+// Reserved address 1792 [0x700] 
+
+// Reserved address 1796 [0x704] 
+
+// Reserved address 1800 [0x708] 
+
+// Reserved address 1804 [0x70c] 
+
+// Reserved address 1808 [0x710] 
+
+// Reserved address 1812 [0x714] 
+
+// Reserved address 1816 [0x718] 
+
+// Reserved address 1820 [0x71c] 
+
+// Reserved address 1824 [0x720] 
+
+// Reserved address 1828 [0x724] 
+
+// Reserved address 1832 [0x728] 
+
+// Reserved address 1836 [0x72c] 
+
+// Reserved address 1840 [0x730] 
+
+// Reserved address 1844 [0x734] 
+
+// Reserved address 1848 [0x738] 
+
+// Reserved address 1852 [0x73c] 
+
+// Reserved address 1856 [0x740] 
+
+// Reserved address 1860 [0x744] 
+
+// Reserved address 1864 [0x748] 
+
+// Reserved address 1868 [0x74c] 
+
+// Reserved address 1872 [0x750] 
+
+// Reserved address 1876 [0x754] 
+
+// Reserved address 1880 [0x758] 
+
+// Reserved address 1884 [0x75c] 
+
+// Reserved address 1888 [0x760] 
+
+// Reserved address 1892 [0x764] 
+
+// Reserved address 1896 [0x768] 
+
+// Reserved address 1900 [0x76c] 
+
+// Reserved address 1904 [0x770] 
+
+// Reserved address 1908 [0x774] 
+
+// Reserved address 1912 [0x778] 
+
+// Reserved address 1916 [0x77c] 
+
+// Reserved address 1920 [0x780] 
+
+// Reserved address 1924 [0x784] 
+
+// Reserved address 1928 [0x788] 
+
+// Reserved address 1932 [0x78c] 
+
+// Reserved address 1936 [0x790] 
+
+// Reserved address 1940 [0x794] 
+
+// Reserved address 1944 [0x798] 
+
+// Reserved address 1948 [0x79c] 
+
+// Reserved address 1952 [0x7a0] 
+
+// Reserved address 1956 [0x7a4] 
+
+// Reserved address 1960 [0x7a8] 
+
+// Reserved address 1964 [0x7ac] 
+
+// Reserved address 1968 [0x7b0] 
+
+// Reserved address 1972 [0x7b4] 
+
+// Reserved address 1976 [0x7b8] 
+
+// Reserved address 1980 [0x7bc] 
+
+// Reserved address 1984 [0x7c0] 
+
+// Reserved address 1988 [0x7c4] 
+
+// Reserved address 1992 [0x7c8] 
+
+// Reserved address 1996 [0x7cc] 
+
+// Reserved address 2000 [0x7d0] 
+
+// Reserved address 2004 [0x7d4] 
+
+// Reserved address 2008 [0x7d8] 
+
+// Reserved address 2012 [0x7dc] 
+
+// Reserved address 2016 [0x7e0] 
+
+// Reserved address 2020 [0x7e4] 
+
+// Reserved address 2024 [0x7e8] 
+
+// Reserved address 2028 [0x7ec] 
+
+// Reserved address 2032 [0x7f0] 
+
+// Reserved address 2036 [0x7f4] 
+
+// Reserved address 2040 [0x7f8] 
+
+// Reserved address 2044 [0x7fc] 
+
+// Register GPIO_MSK_CNF_0  
+#define GPIO_MSK_CNF_0                  _MK_ADDR_CONST(0x800)
+#define GPIO_MSK_CNF_0_WORD_COUNT                       0x1
+#define GPIO_MSK_CNF_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_CNF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_MSK_CNF_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_0_MSK7_SHIFT                       _MK_SHIFT_CONST(15)
+#define GPIO_MSK_CNF_0_MSK7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_MSK7_SHIFT)
+#define GPIO_MSK_CNF_0_MSK7_RANGE                       15:15
+#define GPIO_MSK_CNF_0_MSK7_WOFFSET                     0x0
+#define GPIO_MSK_CNF_0_MSK7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_MSK7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK7_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_MSK7_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_0_MSK6_SHIFT                       _MK_SHIFT_CONST(14)
+#define GPIO_MSK_CNF_0_MSK6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_MSK6_SHIFT)
+#define GPIO_MSK_CNF_0_MSK6_RANGE                       14:14
+#define GPIO_MSK_CNF_0_MSK6_WOFFSET                     0x0
+#define GPIO_MSK_CNF_0_MSK6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_MSK6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK6_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_MSK6_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_0_MSK5_SHIFT                       _MK_SHIFT_CONST(13)
+#define GPIO_MSK_CNF_0_MSK5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_MSK5_SHIFT)
+#define GPIO_MSK_CNF_0_MSK5_RANGE                       13:13
+#define GPIO_MSK_CNF_0_MSK5_WOFFSET                     0x0
+#define GPIO_MSK_CNF_0_MSK5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_MSK5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK5_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_MSK5_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_0_MSK4_SHIFT                       _MK_SHIFT_CONST(12)
+#define GPIO_MSK_CNF_0_MSK4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_MSK4_SHIFT)
+#define GPIO_MSK_CNF_0_MSK4_RANGE                       12:12
+#define GPIO_MSK_CNF_0_MSK4_WOFFSET                     0x0
+#define GPIO_MSK_CNF_0_MSK4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_MSK4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK4_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_MSK4_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_0_MSK3_SHIFT                       _MK_SHIFT_CONST(11)
+#define GPIO_MSK_CNF_0_MSK3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_MSK3_SHIFT)
+#define GPIO_MSK_CNF_0_MSK3_RANGE                       11:11
+#define GPIO_MSK_CNF_0_MSK3_WOFFSET                     0x0
+#define GPIO_MSK_CNF_0_MSK3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_MSK3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK3_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_MSK3_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_0_MSK2_SHIFT                       _MK_SHIFT_CONST(10)
+#define GPIO_MSK_CNF_0_MSK2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_MSK2_SHIFT)
+#define GPIO_MSK_CNF_0_MSK2_RANGE                       10:10
+#define GPIO_MSK_CNF_0_MSK2_WOFFSET                     0x0
+#define GPIO_MSK_CNF_0_MSK2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_MSK2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK2_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_MSK2_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_0_MSK1_SHIFT                       _MK_SHIFT_CONST(9)
+#define GPIO_MSK_CNF_0_MSK1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_MSK1_SHIFT)
+#define GPIO_MSK_CNF_0_MSK1_RANGE                       9:9
+#define GPIO_MSK_CNF_0_MSK1_WOFFSET                     0x0
+#define GPIO_MSK_CNF_0_MSK1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_MSK1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK1_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_MSK1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_0_MSK0_SHIFT                       _MK_SHIFT_CONST(8)
+#define GPIO_MSK_CNF_0_MSK0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_MSK0_SHIFT)
+#define GPIO_MSK_CNF_0_MSK0_RANGE                       8:8
+#define GPIO_MSK_CNF_0_MSK0_WOFFSET                     0x0
+#define GPIO_MSK_CNF_0_MSK0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_MSK0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_MSK0_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_MSK0_ENABLE                      _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_0_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_MSK_CNF_0_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_BIT_7_SHIFT)
+#define GPIO_MSK_CNF_0_BIT_7_RANGE                      7:7
+#define GPIO_MSK_CNF_0_BIT_7_WOFFSET                    0x0
+#define GPIO_MSK_CNF_0_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_7_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_BIT_7_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_0_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_MSK_CNF_0_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_BIT_6_SHIFT)
+#define GPIO_MSK_CNF_0_BIT_6_RANGE                      6:6
+#define GPIO_MSK_CNF_0_BIT_6_WOFFSET                    0x0
+#define GPIO_MSK_CNF_0_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_6_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_BIT_6_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_0_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_MSK_CNF_0_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_BIT_5_SHIFT)
+#define GPIO_MSK_CNF_0_BIT_5_RANGE                      5:5
+#define GPIO_MSK_CNF_0_BIT_5_WOFFSET                    0x0
+#define GPIO_MSK_CNF_0_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_5_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_BIT_5_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_0_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_MSK_CNF_0_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_BIT_4_SHIFT)
+#define GPIO_MSK_CNF_0_BIT_4_RANGE                      4:4
+#define GPIO_MSK_CNF_0_BIT_4_WOFFSET                    0x0
+#define GPIO_MSK_CNF_0_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_4_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_BIT_4_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_0_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_MSK_CNF_0_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_BIT_3_SHIFT)
+#define GPIO_MSK_CNF_0_BIT_3_RANGE                      3:3
+#define GPIO_MSK_CNF_0_BIT_3_WOFFSET                    0x0
+#define GPIO_MSK_CNF_0_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_3_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_BIT_3_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_0_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_MSK_CNF_0_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_BIT_2_SHIFT)
+#define GPIO_MSK_CNF_0_BIT_2_RANGE                      2:2
+#define GPIO_MSK_CNF_0_BIT_2_WOFFSET                    0x0
+#define GPIO_MSK_CNF_0_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_2_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_BIT_2_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_0_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_MSK_CNF_0_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_BIT_1_SHIFT)
+#define GPIO_MSK_CNF_0_BIT_1_RANGE                      1:1
+#define GPIO_MSK_CNF_0_BIT_1_WOFFSET                    0x0
+#define GPIO_MSK_CNF_0_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_1_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_BIT_1_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_0_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_MSK_CNF_0_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_0_BIT_0_SHIFT)
+#define GPIO_MSK_CNF_0_BIT_0_RANGE                      0:0
+#define GPIO_MSK_CNF_0_BIT_0_WOFFSET                    0x0
+#define GPIO_MSK_CNF_0_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_0_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_0_BIT_0_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_0_BIT_0_GPIO                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_CNF  
+#define GPIO_MSK_CNF                    _MK_ADDR_CONST(0x800)
+#define GPIO_MSK_CNF_WORD_COUNT                         0x1
+#define GPIO_MSK_CNF_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_CNF_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_READ_MASK                  _MK_MASK_CONST(0xff)
+#define GPIO_MSK_CNF_WRITE_MASK                         _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_MSK7_SHIFT                 _MK_SHIFT_CONST(15)
+#define GPIO_MSK_CNF_MSK7_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_MSK7_SHIFT)
+#define GPIO_MSK_CNF_MSK7_RANGE                 15:15
+#define GPIO_MSK_CNF_MSK7_WOFFSET                       0x0
+#define GPIO_MSK_CNF_MSK7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_MSK7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK7_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_MSK7_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_MSK6_SHIFT                 _MK_SHIFT_CONST(14)
+#define GPIO_MSK_CNF_MSK6_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_MSK6_SHIFT)
+#define GPIO_MSK_CNF_MSK6_RANGE                 14:14
+#define GPIO_MSK_CNF_MSK6_WOFFSET                       0x0
+#define GPIO_MSK_CNF_MSK6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_MSK6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK6_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_MSK6_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_MSK5_SHIFT                 _MK_SHIFT_CONST(13)
+#define GPIO_MSK_CNF_MSK5_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_MSK5_SHIFT)
+#define GPIO_MSK_CNF_MSK5_RANGE                 13:13
+#define GPIO_MSK_CNF_MSK5_WOFFSET                       0x0
+#define GPIO_MSK_CNF_MSK5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_MSK5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK5_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_MSK5_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_MSK4_SHIFT                 _MK_SHIFT_CONST(12)
+#define GPIO_MSK_CNF_MSK4_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_MSK4_SHIFT)
+#define GPIO_MSK_CNF_MSK4_RANGE                 12:12
+#define GPIO_MSK_CNF_MSK4_WOFFSET                       0x0
+#define GPIO_MSK_CNF_MSK4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_MSK4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK4_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_MSK4_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_MSK3_SHIFT                 _MK_SHIFT_CONST(11)
+#define GPIO_MSK_CNF_MSK3_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_MSK3_SHIFT)
+#define GPIO_MSK_CNF_MSK3_RANGE                 11:11
+#define GPIO_MSK_CNF_MSK3_WOFFSET                       0x0
+#define GPIO_MSK_CNF_MSK3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_MSK3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK3_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_MSK3_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_MSK2_SHIFT                 _MK_SHIFT_CONST(10)
+#define GPIO_MSK_CNF_MSK2_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_MSK2_SHIFT)
+#define GPIO_MSK_CNF_MSK2_RANGE                 10:10
+#define GPIO_MSK_CNF_MSK2_WOFFSET                       0x0
+#define GPIO_MSK_CNF_MSK2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_MSK2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK2_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_MSK2_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_MSK1_SHIFT                 _MK_SHIFT_CONST(9)
+#define GPIO_MSK_CNF_MSK1_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_MSK1_SHIFT)
+#define GPIO_MSK_CNF_MSK1_RANGE                 9:9
+#define GPIO_MSK_CNF_MSK1_WOFFSET                       0x0
+#define GPIO_MSK_CNF_MSK1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_MSK1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK1_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_MSK1_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_MSK0_SHIFT                 _MK_SHIFT_CONST(8)
+#define GPIO_MSK_CNF_MSK0_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_MSK0_SHIFT)
+#define GPIO_MSK_CNF_MSK0_RANGE                 8:8
+#define GPIO_MSK_CNF_MSK0_WOFFSET                       0x0
+#define GPIO_MSK_CNF_MSK0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_MSK0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_MSK0_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_MSK0_ENABLE                        _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_BIT_7_SHIFT                        _MK_SHIFT_CONST(7)
+#define GPIO_MSK_CNF_BIT_7_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_BIT_7_SHIFT)
+#define GPIO_MSK_CNF_BIT_7_RANGE                        7:7
+#define GPIO_MSK_CNF_BIT_7_WOFFSET                      0x0
+#define GPIO_MSK_CNF_BIT_7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_BIT_7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_7_SPIO                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_BIT_7_GPIO                 _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_BIT_6_SHIFT                        _MK_SHIFT_CONST(6)
+#define GPIO_MSK_CNF_BIT_6_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_BIT_6_SHIFT)
+#define GPIO_MSK_CNF_BIT_6_RANGE                        6:6
+#define GPIO_MSK_CNF_BIT_6_WOFFSET                      0x0
+#define GPIO_MSK_CNF_BIT_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_BIT_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_6_SPIO                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_BIT_6_GPIO                 _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_BIT_5_SHIFT                        _MK_SHIFT_CONST(5)
+#define GPIO_MSK_CNF_BIT_5_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_BIT_5_SHIFT)
+#define GPIO_MSK_CNF_BIT_5_RANGE                        5:5
+#define GPIO_MSK_CNF_BIT_5_WOFFSET                      0x0
+#define GPIO_MSK_CNF_BIT_5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_BIT_5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_5_SPIO                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_BIT_5_GPIO                 _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_BIT_4_SHIFT                        _MK_SHIFT_CONST(4)
+#define GPIO_MSK_CNF_BIT_4_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_BIT_4_SHIFT)
+#define GPIO_MSK_CNF_BIT_4_RANGE                        4:4
+#define GPIO_MSK_CNF_BIT_4_WOFFSET                      0x0
+#define GPIO_MSK_CNF_BIT_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_BIT_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_4_SPIO                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_BIT_4_GPIO                 _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_BIT_3_SHIFT                        _MK_SHIFT_CONST(3)
+#define GPIO_MSK_CNF_BIT_3_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_BIT_3_SHIFT)
+#define GPIO_MSK_CNF_BIT_3_RANGE                        3:3
+#define GPIO_MSK_CNF_BIT_3_WOFFSET                      0x0
+#define GPIO_MSK_CNF_BIT_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_BIT_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_3_SPIO                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_BIT_3_GPIO                 _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_BIT_2_SHIFT                        _MK_SHIFT_CONST(2)
+#define GPIO_MSK_CNF_BIT_2_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_BIT_2_SHIFT)
+#define GPIO_MSK_CNF_BIT_2_RANGE                        2:2
+#define GPIO_MSK_CNF_BIT_2_WOFFSET                      0x0
+#define GPIO_MSK_CNF_BIT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_BIT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_2_SPIO                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_BIT_2_GPIO                 _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_BIT_1_SHIFT                        _MK_SHIFT_CONST(1)
+#define GPIO_MSK_CNF_BIT_1_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_BIT_1_SHIFT)
+#define GPIO_MSK_CNF_BIT_1_RANGE                        1:1
+#define GPIO_MSK_CNF_BIT_1_WOFFSET                      0x0
+#define GPIO_MSK_CNF_BIT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_BIT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_1_SPIO                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_BIT_1_GPIO                 _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_BIT_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define GPIO_MSK_CNF_BIT_0_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_BIT_0_SHIFT)
+#define GPIO_MSK_CNF_BIT_0_RANGE                        0:0
+#define GPIO_MSK_CNF_BIT_0_WOFFSET                      0x0
+#define GPIO_MSK_CNF_BIT_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_BIT_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_BIT_0_SPIO                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_BIT_0_GPIO                 _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_CNF_1  
+#define GPIO_MSK_CNF_1                  _MK_ADDR_CONST(0x804)
+#define GPIO_MSK_CNF_1_WORD_COUNT                       0x1
+#define GPIO_MSK_CNF_1_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_CNF_1_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_MSK_CNF_1_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_1_MSK7_SHIFT                       _MK_SHIFT_CONST(15)
+#define GPIO_MSK_CNF_1_MSK7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_MSK7_SHIFT)
+#define GPIO_MSK_CNF_1_MSK7_RANGE                       15:15
+#define GPIO_MSK_CNF_1_MSK7_WOFFSET                     0x0
+#define GPIO_MSK_CNF_1_MSK7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_MSK7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK7_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_MSK7_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_1_MSK6_SHIFT                       _MK_SHIFT_CONST(14)
+#define GPIO_MSK_CNF_1_MSK6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_MSK6_SHIFT)
+#define GPIO_MSK_CNF_1_MSK6_RANGE                       14:14
+#define GPIO_MSK_CNF_1_MSK6_WOFFSET                     0x0
+#define GPIO_MSK_CNF_1_MSK6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_MSK6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK6_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_MSK6_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_1_MSK5_SHIFT                       _MK_SHIFT_CONST(13)
+#define GPIO_MSK_CNF_1_MSK5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_MSK5_SHIFT)
+#define GPIO_MSK_CNF_1_MSK5_RANGE                       13:13
+#define GPIO_MSK_CNF_1_MSK5_WOFFSET                     0x0
+#define GPIO_MSK_CNF_1_MSK5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_MSK5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK5_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_MSK5_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_1_MSK4_SHIFT                       _MK_SHIFT_CONST(12)
+#define GPIO_MSK_CNF_1_MSK4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_MSK4_SHIFT)
+#define GPIO_MSK_CNF_1_MSK4_RANGE                       12:12
+#define GPIO_MSK_CNF_1_MSK4_WOFFSET                     0x0
+#define GPIO_MSK_CNF_1_MSK4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_MSK4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK4_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_MSK4_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_1_MSK3_SHIFT                       _MK_SHIFT_CONST(11)
+#define GPIO_MSK_CNF_1_MSK3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_MSK3_SHIFT)
+#define GPIO_MSK_CNF_1_MSK3_RANGE                       11:11
+#define GPIO_MSK_CNF_1_MSK3_WOFFSET                     0x0
+#define GPIO_MSK_CNF_1_MSK3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_MSK3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK3_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_MSK3_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_1_MSK2_SHIFT                       _MK_SHIFT_CONST(10)
+#define GPIO_MSK_CNF_1_MSK2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_MSK2_SHIFT)
+#define GPIO_MSK_CNF_1_MSK2_RANGE                       10:10
+#define GPIO_MSK_CNF_1_MSK2_WOFFSET                     0x0
+#define GPIO_MSK_CNF_1_MSK2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_MSK2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK2_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_MSK2_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_1_MSK1_SHIFT                       _MK_SHIFT_CONST(9)
+#define GPIO_MSK_CNF_1_MSK1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_MSK1_SHIFT)
+#define GPIO_MSK_CNF_1_MSK1_RANGE                       9:9
+#define GPIO_MSK_CNF_1_MSK1_WOFFSET                     0x0
+#define GPIO_MSK_CNF_1_MSK1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_MSK1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK1_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_MSK1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_1_MSK0_SHIFT                       _MK_SHIFT_CONST(8)
+#define GPIO_MSK_CNF_1_MSK0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_MSK0_SHIFT)
+#define GPIO_MSK_CNF_1_MSK0_RANGE                       8:8
+#define GPIO_MSK_CNF_1_MSK0_WOFFSET                     0x0
+#define GPIO_MSK_CNF_1_MSK0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_MSK0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_MSK0_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_MSK0_ENABLE                      _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_1_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_MSK_CNF_1_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_BIT_7_SHIFT)
+#define GPIO_MSK_CNF_1_BIT_7_RANGE                      7:7
+#define GPIO_MSK_CNF_1_BIT_7_WOFFSET                    0x0
+#define GPIO_MSK_CNF_1_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_7_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_BIT_7_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_1_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_MSK_CNF_1_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_BIT_6_SHIFT)
+#define GPIO_MSK_CNF_1_BIT_6_RANGE                      6:6
+#define GPIO_MSK_CNF_1_BIT_6_WOFFSET                    0x0
+#define GPIO_MSK_CNF_1_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_6_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_BIT_6_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_1_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_MSK_CNF_1_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_BIT_5_SHIFT)
+#define GPIO_MSK_CNF_1_BIT_5_RANGE                      5:5
+#define GPIO_MSK_CNF_1_BIT_5_WOFFSET                    0x0
+#define GPIO_MSK_CNF_1_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_5_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_BIT_5_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_1_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_MSK_CNF_1_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_BIT_4_SHIFT)
+#define GPIO_MSK_CNF_1_BIT_4_RANGE                      4:4
+#define GPIO_MSK_CNF_1_BIT_4_WOFFSET                    0x0
+#define GPIO_MSK_CNF_1_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_4_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_BIT_4_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_1_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_MSK_CNF_1_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_BIT_3_SHIFT)
+#define GPIO_MSK_CNF_1_BIT_3_RANGE                      3:3
+#define GPIO_MSK_CNF_1_BIT_3_WOFFSET                    0x0
+#define GPIO_MSK_CNF_1_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_3_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_BIT_3_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_1_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_MSK_CNF_1_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_BIT_2_SHIFT)
+#define GPIO_MSK_CNF_1_BIT_2_RANGE                      2:2
+#define GPIO_MSK_CNF_1_BIT_2_WOFFSET                    0x0
+#define GPIO_MSK_CNF_1_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_2_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_BIT_2_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_1_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_MSK_CNF_1_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_BIT_1_SHIFT)
+#define GPIO_MSK_CNF_1_BIT_1_RANGE                      1:1
+#define GPIO_MSK_CNF_1_BIT_1_WOFFSET                    0x0
+#define GPIO_MSK_CNF_1_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_1_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_BIT_1_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_1_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_MSK_CNF_1_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_1_BIT_0_SHIFT)
+#define GPIO_MSK_CNF_1_BIT_0_RANGE                      0:0
+#define GPIO_MSK_CNF_1_BIT_0_WOFFSET                    0x0
+#define GPIO_MSK_CNF_1_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_1_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_1_BIT_0_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_1_BIT_0_GPIO                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_CNF_2  
+#define GPIO_MSK_CNF_2                  _MK_ADDR_CONST(0x808)
+#define GPIO_MSK_CNF_2_WORD_COUNT                       0x1
+#define GPIO_MSK_CNF_2_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_CNF_2_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_MSK_CNF_2_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_2_MSK7_SHIFT                       _MK_SHIFT_CONST(15)
+#define GPIO_MSK_CNF_2_MSK7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_MSK7_SHIFT)
+#define GPIO_MSK_CNF_2_MSK7_RANGE                       15:15
+#define GPIO_MSK_CNF_2_MSK7_WOFFSET                     0x0
+#define GPIO_MSK_CNF_2_MSK7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_MSK7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK7_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_MSK7_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_2_MSK6_SHIFT                       _MK_SHIFT_CONST(14)
+#define GPIO_MSK_CNF_2_MSK6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_MSK6_SHIFT)
+#define GPIO_MSK_CNF_2_MSK6_RANGE                       14:14
+#define GPIO_MSK_CNF_2_MSK6_WOFFSET                     0x0
+#define GPIO_MSK_CNF_2_MSK6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_MSK6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK6_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_MSK6_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_2_MSK5_SHIFT                       _MK_SHIFT_CONST(13)
+#define GPIO_MSK_CNF_2_MSK5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_MSK5_SHIFT)
+#define GPIO_MSK_CNF_2_MSK5_RANGE                       13:13
+#define GPIO_MSK_CNF_2_MSK5_WOFFSET                     0x0
+#define GPIO_MSK_CNF_2_MSK5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_MSK5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK5_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_MSK5_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_2_MSK4_SHIFT                       _MK_SHIFT_CONST(12)
+#define GPIO_MSK_CNF_2_MSK4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_MSK4_SHIFT)
+#define GPIO_MSK_CNF_2_MSK4_RANGE                       12:12
+#define GPIO_MSK_CNF_2_MSK4_WOFFSET                     0x0
+#define GPIO_MSK_CNF_2_MSK4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_MSK4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK4_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_MSK4_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_2_MSK3_SHIFT                       _MK_SHIFT_CONST(11)
+#define GPIO_MSK_CNF_2_MSK3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_MSK3_SHIFT)
+#define GPIO_MSK_CNF_2_MSK3_RANGE                       11:11
+#define GPIO_MSK_CNF_2_MSK3_WOFFSET                     0x0
+#define GPIO_MSK_CNF_2_MSK3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_MSK3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK3_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_MSK3_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_2_MSK2_SHIFT                       _MK_SHIFT_CONST(10)
+#define GPIO_MSK_CNF_2_MSK2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_MSK2_SHIFT)
+#define GPIO_MSK_CNF_2_MSK2_RANGE                       10:10
+#define GPIO_MSK_CNF_2_MSK2_WOFFSET                     0x0
+#define GPIO_MSK_CNF_2_MSK2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_MSK2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK2_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_MSK2_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_2_MSK1_SHIFT                       _MK_SHIFT_CONST(9)
+#define GPIO_MSK_CNF_2_MSK1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_MSK1_SHIFT)
+#define GPIO_MSK_CNF_2_MSK1_RANGE                       9:9
+#define GPIO_MSK_CNF_2_MSK1_WOFFSET                     0x0
+#define GPIO_MSK_CNF_2_MSK1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_MSK1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK1_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_MSK1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_2_MSK0_SHIFT                       _MK_SHIFT_CONST(8)
+#define GPIO_MSK_CNF_2_MSK0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_MSK0_SHIFT)
+#define GPIO_MSK_CNF_2_MSK0_RANGE                       8:8
+#define GPIO_MSK_CNF_2_MSK0_WOFFSET                     0x0
+#define GPIO_MSK_CNF_2_MSK0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_MSK0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_MSK0_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_MSK0_ENABLE                      _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_2_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_MSK_CNF_2_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_BIT_7_SHIFT)
+#define GPIO_MSK_CNF_2_BIT_7_RANGE                      7:7
+#define GPIO_MSK_CNF_2_BIT_7_WOFFSET                    0x0
+#define GPIO_MSK_CNF_2_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_7_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_BIT_7_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_2_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_MSK_CNF_2_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_BIT_6_SHIFT)
+#define GPIO_MSK_CNF_2_BIT_6_RANGE                      6:6
+#define GPIO_MSK_CNF_2_BIT_6_WOFFSET                    0x0
+#define GPIO_MSK_CNF_2_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_6_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_BIT_6_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_2_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_MSK_CNF_2_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_BIT_5_SHIFT)
+#define GPIO_MSK_CNF_2_BIT_5_RANGE                      5:5
+#define GPIO_MSK_CNF_2_BIT_5_WOFFSET                    0x0
+#define GPIO_MSK_CNF_2_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_5_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_BIT_5_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_2_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_MSK_CNF_2_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_BIT_4_SHIFT)
+#define GPIO_MSK_CNF_2_BIT_4_RANGE                      4:4
+#define GPIO_MSK_CNF_2_BIT_4_WOFFSET                    0x0
+#define GPIO_MSK_CNF_2_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_4_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_BIT_4_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_2_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_MSK_CNF_2_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_BIT_3_SHIFT)
+#define GPIO_MSK_CNF_2_BIT_3_RANGE                      3:3
+#define GPIO_MSK_CNF_2_BIT_3_WOFFSET                    0x0
+#define GPIO_MSK_CNF_2_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_3_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_BIT_3_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_2_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_MSK_CNF_2_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_BIT_2_SHIFT)
+#define GPIO_MSK_CNF_2_BIT_2_RANGE                      2:2
+#define GPIO_MSK_CNF_2_BIT_2_WOFFSET                    0x0
+#define GPIO_MSK_CNF_2_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_2_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_BIT_2_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_2_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_MSK_CNF_2_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_BIT_1_SHIFT)
+#define GPIO_MSK_CNF_2_BIT_1_RANGE                      1:1
+#define GPIO_MSK_CNF_2_BIT_1_WOFFSET                    0x0
+#define GPIO_MSK_CNF_2_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_1_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_BIT_1_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_2_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_MSK_CNF_2_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_2_BIT_0_SHIFT)
+#define GPIO_MSK_CNF_2_BIT_0_RANGE                      0:0
+#define GPIO_MSK_CNF_2_BIT_0_WOFFSET                    0x0
+#define GPIO_MSK_CNF_2_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_2_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_2_BIT_0_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_2_BIT_0_GPIO                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_CNF_3  
+#define GPIO_MSK_CNF_3                  _MK_ADDR_CONST(0x80c)
+#define GPIO_MSK_CNF_3_WORD_COUNT                       0x1
+#define GPIO_MSK_CNF_3_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_CNF_3_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_MSK_CNF_3_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_3_MSK7_SHIFT                       _MK_SHIFT_CONST(15)
+#define GPIO_MSK_CNF_3_MSK7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_MSK7_SHIFT)
+#define GPIO_MSK_CNF_3_MSK7_RANGE                       15:15
+#define GPIO_MSK_CNF_3_MSK7_WOFFSET                     0x0
+#define GPIO_MSK_CNF_3_MSK7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_MSK7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK7_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_MSK7_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_3_MSK6_SHIFT                       _MK_SHIFT_CONST(14)
+#define GPIO_MSK_CNF_3_MSK6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_MSK6_SHIFT)
+#define GPIO_MSK_CNF_3_MSK6_RANGE                       14:14
+#define GPIO_MSK_CNF_3_MSK6_WOFFSET                     0x0
+#define GPIO_MSK_CNF_3_MSK6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_MSK6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK6_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_MSK6_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_3_MSK5_SHIFT                       _MK_SHIFT_CONST(13)
+#define GPIO_MSK_CNF_3_MSK5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_MSK5_SHIFT)
+#define GPIO_MSK_CNF_3_MSK5_RANGE                       13:13
+#define GPIO_MSK_CNF_3_MSK5_WOFFSET                     0x0
+#define GPIO_MSK_CNF_3_MSK5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_MSK5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK5_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_MSK5_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_3_MSK4_SHIFT                       _MK_SHIFT_CONST(12)
+#define GPIO_MSK_CNF_3_MSK4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_MSK4_SHIFT)
+#define GPIO_MSK_CNF_3_MSK4_RANGE                       12:12
+#define GPIO_MSK_CNF_3_MSK4_WOFFSET                     0x0
+#define GPIO_MSK_CNF_3_MSK4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_MSK4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK4_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_MSK4_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_3_MSK3_SHIFT                       _MK_SHIFT_CONST(11)
+#define GPIO_MSK_CNF_3_MSK3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_MSK3_SHIFT)
+#define GPIO_MSK_CNF_3_MSK3_RANGE                       11:11
+#define GPIO_MSK_CNF_3_MSK3_WOFFSET                     0x0
+#define GPIO_MSK_CNF_3_MSK3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_MSK3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK3_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_MSK3_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_3_MSK2_SHIFT                       _MK_SHIFT_CONST(10)
+#define GPIO_MSK_CNF_3_MSK2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_MSK2_SHIFT)
+#define GPIO_MSK_CNF_3_MSK2_RANGE                       10:10
+#define GPIO_MSK_CNF_3_MSK2_WOFFSET                     0x0
+#define GPIO_MSK_CNF_3_MSK2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_MSK2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK2_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_MSK2_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_3_MSK1_SHIFT                       _MK_SHIFT_CONST(9)
+#define GPIO_MSK_CNF_3_MSK1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_MSK1_SHIFT)
+#define GPIO_MSK_CNF_3_MSK1_RANGE                       9:9
+#define GPIO_MSK_CNF_3_MSK1_WOFFSET                     0x0
+#define GPIO_MSK_CNF_3_MSK1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_MSK1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK1_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_MSK1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_CNF_3_MSK0_SHIFT                       _MK_SHIFT_CONST(8)
+#define GPIO_MSK_CNF_3_MSK0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_MSK0_SHIFT)
+#define GPIO_MSK_CNF_3_MSK0_RANGE                       8:8
+#define GPIO_MSK_CNF_3_MSK0_WOFFSET                     0x0
+#define GPIO_MSK_CNF_3_MSK0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_MSK0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_MSK0_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_MSK0_ENABLE                      _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_3_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_MSK_CNF_3_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_BIT_7_SHIFT)
+#define GPIO_MSK_CNF_3_BIT_7_RANGE                      7:7
+#define GPIO_MSK_CNF_3_BIT_7_WOFFSET                    0x0
+#define GPIO_MSK_CNF_3_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_7_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_BIT_7_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_3_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_MSK_CNF_3_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_BIT_6_SHIFT)
+#define GPIO_MSK_CNF_3_BIT_6_RANGE                      6:6
+#define GPIO_MSK_CNF_3_BIT_6_WOFFSET                    0x0
+#define GPIO_MSK_CNF_3_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_6_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_BIT_6_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_3_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_MSK_CNF_3_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_BIT_5_SHIFT)
+#define GPIO_MSK_CNF_3_BIT_5_RANGE                      5:5
+#define GPIO_MSK_CNF_3_BIT_5_WOFFSET                    0x0
+#define GPIO_MSK_CNF_3_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_5_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_BIT_5_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_3_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_MSK_CNF_3_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_BIT_4_SHIFT)
+#define GPIO_MSK_CNF_3_BIT_4_RANGE                      4:4
+#define GPIO_MSK_CNF_3_BIT_4_WOFFSET                    0x0
+#define GPIO_MSK_CNF_3_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_4_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_BIT_4_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_3_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_MSK_CNF_3_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_BIT_3_SHIFT)
+#define GPIO_MSK_CNF_3_BIT_3_RANGE                      3:3
+#define GPIO_MSK_CNF_3_BIT_3_WOFFSET                    0x0
+#define GPIO_MSK_CNF_3_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_3_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_BIT_3_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_3_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_MSK_CNF_3_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_BIT_2_SHIFT)
+#define GPIO_MSK_CNF_3_BIT_2_RANGE                      2:2
+#define GPIO_MSK_CNF_3_BIT_2_WOFFSET                    0x0
+#define GPIO_MSK_CNF_3_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_2_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_BIT_2_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_3_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_MSK_CNF_3_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_BIT_1_SHIFT)
+#define GPIO_MSK_CNF_3_BIT_1_RANGE                      1:1
+#define GPIO_MSK_CNF_3_BIT_1_WOFFSET                    0x0
+#define GPIO_MSK_CNF_3_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_1_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_BIT_1_GPIO                       _MK_ENUM_CONST(1)
+
+#define GPIO_MSK_CNF_3_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_MSK_CNF_3_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_CNF_3_BIT_0_SHIFT)
+#define GPIO_MSK_CNF_3_BIT_0_RANGE                      0:0
+#define GPIO_MSK_CNF_3_BIT_0_WOFFSET                    0x0
+#define GPIO_MSK_CNF_3_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_CNF_3_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_CNF_3_BIT_0_SPIO                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_CNF_3_BIT_0_GPIO                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_OE_0  
+#define GPIO_MSK_OE_0                   _MK_ADDR_CONST(0x810)
+#define GPIO_MSK_OE_0_WORD_COUNT                        0x1
+#define GPIO_MSK_OE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_OE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define GPIO_MSK_OE_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_0_MSK7_SHIFT                        _MK_SHIFT_CONST(15)
+#define GPIO_MSK_OE_0_MSK7_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_MSK7_SHIFT)
+#define GPIO_MSK_OE_0_MSK7_RANGE                        15:15
+#define GPIO_MSK_OE_0_MSK7_WOFFSET                      0x0
+#define GPIO_MSK_OE_0_MSK7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_MSK7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK7_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_MSK7_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_0_MSK6_SHIFT                        _MK_SHIFT_CONST(14)
+#define GPIO_MSK_OE_0_MSK6_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_MSK6_SHIFT)
+#define GPIO_MSK_OE_0_MSK6_RANGE                        14:14
+#define GPIO_MSK_OE_0_MSK6_WOFFSET                      0x0
+#define GPIO_MSK_OE_0_MSK6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_MSK6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK6_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_MSK6_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_0_MSK5_SHIFT                        _MK_SHIFT_CONST(13)
+#define GPIO_MSK_OE_0_MSK5_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_MSK5_SHIFT)
+#define GPIO_MSK_OE_0_MSK5_RANGE                        13:13
+#define GPIO_MSK_OE_0_MSK5_WOFFSET                      0x0
+#define GPIO_MSK_OE_0_MSK5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_MSK5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK5_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_MSK5_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_0_MSK4_SHIFT                        _MK_SHIFT_CONST(12)
+#define GPIO_MSK_OE_0_MSK4_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_MSK4_SHIFT)
+#define GPIO_MSK_OE_0_MSK4_RANGE                        12:12
+#define GPIO_MSK_OE_0_MSK4_WOFFSET                      0x0
+#define GPIO_MSK_OE_0_MSK4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_MSK4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK4_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_MSK4_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_0_MSK3_SHIFT                        _MK_SHIFT_CONST(11)
+#define GPIO_MSK_OE_0_MSK3_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_MSK3_SHIFT)
+#define GPIO_MSK_OE_0_MSK3_RANGE                        11:11
+#define GPIO_MSK_OE_0_MSK3_WOFFSET                      0x0
+#define GPIO_MSK_OE_0_MSK3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_MSK3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK3_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_MSK3_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_0_MSK2_SHIFT                        _MK_SHIFT_CONST(10)
+#define GPIO_MSK_OE_0_MSK2_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_MSK2_SHIFT)
+#define GPIO_MSK_OE_0_MSK2_RANGE                        10:10
+#define GPIO_MSK_OE_0_MSK2_WOFFSET                      0x0
+#define GPIO_MSK_OE_0_MSK2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_MSK2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK2_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_MSK2_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_0_MSK1_SHIFT                        _MK_SHIFT_CONST(9)
+#define GPIO_MSK_OE_0_MSK1_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_MSK1_SHIFT)
+#define GPIO_MSK_OE_0_MSK1_RANGE                        9:9
+#define GPIO_MSK_OE_0_MSK1_WOFFSET                      0x0
+#define GPIO_MSK_OE_0_MSK1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_MSK1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK1_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_MSK1_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_0_MSK0_SHIFT                        _MK_SHIFT_CONST(8)
+#define GPIO_MSK_OE_0_MSK0_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_MSK0_SHIFT)
+#define GPIO_MSK_OE_0_MSK0_RANGE                        8:8
+#define GPIO_MSK_OE_0_MSK0_WOFFSET                      0x0
+#define GPIO_MSK_OE_0_MSK0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_MSK0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_MSK0_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_MSK0_ENABLE                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_0_BIT_7_SHIFT                       _MK_SHIFT_CONST(7)
+#define GPIO_MSK_OE_0_BIT_7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_BIT_7_SHIFT)
+#define GPIO_MSK_OE_0_BIT_7_RANGE                       7:7
+#define GPIO_MSK_OE_0_BIT_7_WOFFSET                     0x0
+#define GPIO_MSK_OE_0_BIT_7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_BIT_7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_7_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_BIT_7_DRIVEN                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_0_BIT_6_SHIFT                       _MK_SHIFT_CONST(6)
+#define GPIO_MSK_OE_0_BIT_6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_BIT_6_SHIFT)
+#define GPIO_MSK_OE_0_BIT_6_RANGE                       6:6
+#define GPIO_MSK_OE_0_BIT_6_WOFFSET                     0x0
+#define GPIO_MSK_OE_0_BIT_6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_BIT_6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_6_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_BIT_6_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_0_BIT_5_SHIFT                       _MK_SHIFT_CONST(5)
+#define GPIO_MSK_OE_0_BIT_5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_BIT_5_SHIFT)
+#define GPIO_MSK_OE_0_BIT_5_RANGE                       5:5
+#define GPIO_MSK_OE_0_BIT_5_WOFFSET                     0x0
+#define GPIO_MSK_OE_0_BIT_5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_BIT_5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_5_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_BIT_5_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_0_BIT_4_SHIFT                       _MK_SHIFT_CONST(4)
+#define GPIO_MSK_OE_0_BIT_4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_BIT_4_SHIFT)
+#define GPIO_MSK_OE_0_BIT_4_RANGE                       4:4
+#define GPIO_MSK_OE_0_BIT_4_WOFFSET                     0x0
+#define GPIO_MSK_OE_0_BIT_4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_BIT_4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_4_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_BIT_4_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_0_BIT_3_SHIFT                       _MK_SHIFT_CONST(3)
+#define GPIO_MSK_OE_0_BIT_3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_BIT_3_SHIFT)
+#define GPIO_MSK_OE_0_BIT_3_RANGE                       3:3
+#define GPIO_MSK_OE_0_BIT_3_WOFFSET                     0x0
+#define GPIO_MSK_OE_0_BIT_3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_BIT_3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_3_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_BIT_3_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_0_BIT_2_SHIFT                       _MK_SHIFT_CONST(2)
+#define GPIO_MSK_OE_0_BIT_2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_BIT_2_SHIFT)
+#define GPIO_MSK_OE_0_BIT_2_RANGE                       2:2
+#define GPIO_MSK_OE_0_BIT_2_WOFFSET                     0x0
+#define GPIO_MSK_OE_0_BIT_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_BIT_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_2_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_BIT_2_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_0_BIT_1_SHIFT                       _MK_SHIFT_CONST(1)
+#define GPIO_MSK_OE_0_BIT_1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_BIT_1_SHIFT)
+#define GPIO_MSK_OE_0_BIT_1_RANGE                       1:1
+#define GPIO_MSK_OE_0_BIT_1_WOFFSET                     0x0
+#define GPIO_MSK_OE_0_BIT_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_BIT_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_1_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_BIT_1_DRIVEN                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_0_BIT_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define GPIO_MSK_OE_0_BIT_0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_0_BIT_0_SHIFT)
+#define GPIO_MSK_OE_0_BIT_0_RANGE                       0:0
+#define GPIO_MSK_OE_0_BIT_0_WOFFSET                     0x0
+#define GPIO_MSK_OE_0_BIT_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_0_BIT_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_0_BIT_0_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_0_BIT_0_DRIVEN                      _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_OE  
+#define GPIO_MSK_OE                     _MK_ADDR_CONST(0x810)
+#define GPIO_MSK_OE_WORD_COUNT                  0x1
+#define GPIO_MSK_OE_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_RESET_MASK                  _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_OE_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_READ_MASK                   _MK_MASK_CONST(0xff)
+#define GPIO_MSK_OE_WRITE_MASK                  _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_MSK7_SHIFT                  _MK_SHIFT_CONST(15)
+#define GPIO_MSK_OE_MSK7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_MSK7_SHIFT)
+#define GPIO_MSK_OE_MSK7_RANGE                  15:15
+#define GPIO_MSK_OE_MSK7_WOFFSET                        0x0
+#define GPIO_MSK_OE_MSK7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_MSK7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK7_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_MSK7_ENABLE                 _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_MSK6_SHIFT                  _MK_SHIFT_CONST(14)
+#define GPIO_MSK_OE_MSK6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_MSK6_SHIFT)
+#define GPIO_MSK_OE_MSK6_RANGE                  14:14
+#define GPIO_MSK_OE_MSK6_WOFFSET                        0x0
+#define GPIO_MSK_OE_MSK6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_MSK6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK6_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_MSK6_ENABLE                 _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_MSK5_SHIFT                  _MK_SHIFT_CONST(13)
+#define GPIO_MSK_OE_MSK5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_MSK5_SHIFT)
+#define GPIO_MSK_OE_MSK5_RANGE                  13:13
+#define GPIO_MSK_OE_MSK5_WOFFSET                        0x0
+#define GPIO_MSK_OE_MSK5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_MSK5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK5_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_MSK5_ENABLE                 _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_MSK4_SHIFT                  _MK_SHIFT_CONST(12)
+#define GPIO_MSK_OE_MSK4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_MSK4_SHIFT)
+#define GPIO_MSK_OE_MSK4_RANGE                  12:12
+#define GPIO_MSK_OE_MSK4_WOFFSET                        0x0
+#define GPIO_MSK_OE_MSK4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_MSK4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK4_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_MSK4_ENABLE                 _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_MSK3_SHIFT                  _MK_SHIFT_CONST(11)
+#define GPIO_MSK_OE_MSK3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_MSK3_SHIFT)
+#define GPIO_MSK_OE_MSK3_RANGE                  11:11
+#define GPIO_MSK_OE_MSK3_WOFFSET                        0x0
+#define GPIO_MSK_OE_MSK3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_MSK3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK3_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_MSK3_ENABLE                 _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_MSK2_SHIFT                  _MK_SHIFT_CONST(10)
+#define GPIO_MSK_OE_MSK2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_MSK2_SHIFT)
+#define GPIO_MSK_OE_MSK2_RANGE                  10:10
+#define GPIO_MSK_OE_MSK2_WOFFSET                        0x0
+#define GPIO_MSK_OE_MSK2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_MSK2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK2_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_MSK2_ENABLE                 _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_MSK1_SHIFT                  _MK_SHIFT_CONST(9)
+#define GPIO_MSK_OE_MSK1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_MSK1_SHIFT)
+#define GPIO_MSK_OE_MSK1_RANGE                  9:9
+#define GPIO_MSK_OE_MSK1_WOFFSET                        0x0
+#define GPIO_MSK_OE_MSK1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_MSK1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK1_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_MSK1_ENABLE                 _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_MSK0_SHIFT                  _MK_SHIFT_CONST(8)
+#define GPIO_MSK_OE_MSK0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_MSK0_SHIFT)
+#define GPIO_MSK_OE_MSK0_RANGE                  8:8
+#define GPIO_MSK_OE_MSK0_WOFFSET                        0x0
+#define GPIO_MSK_OE_MSK0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_MSK0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_MSK0_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_MSK0_ENABLE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_BIT_7_SHIFT                 _MK_SHIFT_CONST(7)
+#define GPIO_MSK_OE_BIT_7_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_BIT_7_SHIFT)
+#define GPIO_MSK_OE_BIT_7_RANGE                 7:7
+#define GPIO_MSK_OE_BIT_7_WOFFSET                       0x0
+#define GPIO_MSK_OE_BIT_7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_BIT_7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_7_TRI_STATE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_BIT_7_DRIVEN                        _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_BIT_6_SHIFT                 _MK_SHIFT_CONST(6)
+#define GPIO_MSK_OE_BIT_6_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_BIT_6_SHIFT)
+#define GPIO_MSK_OE_BIT_6_RANGE                 6:6
+#define GPIO_MSK_OE_BIT_6_WOFFSET                       0x0
+#define GPIO_MSK_OE_BIT_6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_BIT_6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_6_TRI_STATE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_BIT_6_DRIVEN                        _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_BIT_5_SHIFT                 _MK_SHIFT_CONST(5)
+#define GPIO_MSK_OE_BIT_5_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_BIT_5_SHIFT)
+#define GPIO_MSK_OE_BIT_5_RANGE                 5:5
+#define GPIO_MSK_OE_BIT_5_WOFFSET                       0x0
+#define GPIO_MSK_OE_BIT_5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_BIT_5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_5_TRI_STATE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_BIT_5_DRIVEN                        _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_BIT_4_SHIFT                 _MK_SHIFT_CONST(4)
+#define GPIO_MSK_OE_BIT_4_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_BIT_4_SHIFT)
+#define GPIO_MSK_OE_BIT_4_RANGE                 4:4
+#define GPIO_MSK_OE_BIT_4_WOFFSET                       0x0
+#define GPIO_MSK_OE_BIT_4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_BIT_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_4_TRI_STATE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_BIT_4_DRIVEN                        _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_BIT_3_SHIFT                 _MK_SHIFT_CONST(3)
+#define GPIO_MSK_OE_BIT_3_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_BIT_3_SHIFT)
+#define GPIO_MSK_OE_BIT_3_RANGE                 3:3
+#define GPIO_MSK_OE_BIT_3_WOFFSET                       0x0
+#define GPIO_MSK_OE_BIT_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_BIT_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_3_TRI_STATE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_BIT_3_DRIVEN                        _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_BIT_2_SHIFT                 _MK_SHIFT_CONST(2)
+#define GPIO_MSK_OE_BIT_2_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_BIT_2_SHIFT)
+#define GPIO_MSK_OE_BIT_2_RANGE                 2:2
+#define GPIO_MSK_OE_BIT_2_WOFFSET                       0x0
+#define GPIO_MSK_OE_BIT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_BIT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_2_TRI_STATE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_BIT_2_DRIVEN                        _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_BIT_1_SHIFT                 _MK_SHIFT_CONST(1)
+#define GPIO_MSK_OE_BIT_1_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_BIT_1_SHIFT)
+#define GPIO_MSK_OE_BIT_1_RANGE                 1:1
+#define GPIO_MSK_OE_BIT_1_WOFFSET                       0x0
+#define GPIO_MSK_OE_BIT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_BIT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_1_TRI_STATE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_BIT_1_DRIVEN                        _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_BIT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define GPIO_MSK_OE_BIT_0_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_BIT_0_SHIFT)
+#define GPIO_MSK_OE_BIT_0_RANGE                 0:0
+#define GPIO_MSK_OE_BIT_0_WOFFSET                       0x0
+#define GPIO_MSK_OE_BIT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_BIT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_BIT_0_TRI_STATE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_BIT_0_DRIVEN                        _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_OE_1  
+#define GPIO_MSK_OE_1                   _MK_ADDR_CONST(0x814)
+#define GPIO_MSK_OE_1_WORD_COUNT                        0x1
+#define GPIO_MSK_OE_1_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_OE_1_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_READ_MASK                         _MK_MASK_CONST(0xff)
+#define GPIO_MSK_OE_1_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_1_MSK7_SHIFT                        _MK_SHIFT_CONST(15)
+#define GPIO_MSK_OE_1_MSK7_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_MSK7_SHIFT)
+#define GPIO_MSK_OE_1_MSK7_RANGE                        15:15
+#define GPIO_MSK_OE_1_MSK7_WOFFSET                      0x0
+#define GPIO_MSK_OE_1_MSK7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_MSK7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK7_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_MSK7_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_1_MSK6_SHIFT                        _MK_SHIFT_CONST(14)
+#define GPIO_MSK_OE_1_MSK6_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_MSK6_SHIFT)
+#define GPIO_MSK_OE_1_MSK6_RANGE                        14:14
+#define GPIO_MSK_OE_1_MSK6_WOFFSET                      0x0
+#define GPIO_MSK_OE_1_MSK6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_MSK6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK6_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_MSK6_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_1_MSK5_SHIFT                        _MK_SHIFT_CONST(13)
+#define GPIO_MSK_OE_1_MSK5_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_MSK5_SHIFT)
+#define GPIO_MSK_OE_1_MSK5_RANGE                        13:13
+#define GPIO_MSK_OE_1_MSK5_WOFFSET                      0x0
+#define GPIO_MSK_OE_1_MSK5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_MSK5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK5_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_MSK5_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_1_MSK4_SHIFT                        _MK_SHIFT_CONST(12)
+#define GPIO_MSK_OE_1_MSK4_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_MSK4_SHIFT)
+#define GPIO_MSK_OE_1_MSK4_RANGE                        12:12
+#define GPIO_MSK_OE_1_MSK4_WOFFSET                      0x0
+#define GPIO_MSK_OE_1_MSK4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_MSK4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK4_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_MSK4_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_1_MSK3_SHIFT                        _MK_SHIFT_CONST(11)
+#define GPIO_MSK_OE_1_MSK3_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_MSK3_SHIFT)
+#define GPIO_MSK_OE_1_MSK3_RANGE                        11:11
+#define GPIO_MSK_OE_1_MSK3_WOFFSET                      0x0
+#define GPIO_MSK_OE_1_MSK3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_MSK3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK3_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_MSK3_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_1_MSK2_SHIFT                        _MK_SHIFT_CONST(10)
+#define GPIO_MSK_OE_1_MSK2_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_MSK2_SHIFT)
+#define GPIO_MSK_OE_1_MSK2_RANGE                        10:10
+#define GPIO_MSK_OE_1_MSK2_WOFFSET                      0x0
+#define GPIO_MSK_OE_1_MSK2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_MSK2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK2_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_MSK2_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_1_MSK1_SHIFT                        _MK_SHIFT_CONST(9)
+#define GPIO_MSK_OE_1_MSK1_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_MSK1_SHIFT)
+#define GPIO_MSK_OE_1_MSK1_RANGE                        9:9
+#define GPIO_MSK_OE_1_MSK1_WOFFSET                      0x0
+#define GPIO_MSK_OE_1_MSK1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_MSK1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK1_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_MSK1_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_1_MSK0_SHIFT                        _MK_SHIFT_CONST(8)
+#define GPIO_MSK_OE_1_MSK0_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_MSK0_SHIFT)
+#define GPIO_MSK_OE_1_MSK0_RANGE                        8:8
+#define GPIO_MSK_OE_1_MSK0_WOFFSET                      0x0
+#define GPIO_MSK_OE_1_MSK0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_MSK0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_MSK0_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_MSK0_ENABLE                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_1_BIT_7_SHIFT                       _MK_SHIFT_CONST(7)
+#define GPIO_MSK_OE_1_BIT_7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_BIT_7_SHIFT)
+#define GPIO_MSK_OE_1_BIT_7_RANGE                       7:7
+#define GPIO_MSK_OE_1_BIT_7_WOFFSET                     0x0
+#define GPIO_MSK_OE_1_BIT_7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_BIT_7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_7_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_BIT_7_DRIVEN                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_1_BIT_6_SHIFT                       _MK_SHIFT_CONST(6)
+#define GPIO_MSK_OE_1_BIT_6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_BIT_6_SHIFT)
+#define GPIO_MSK_OE_1_BIT_6_RANGE                       6:6
+#define GPIO_MSK_OE_1_BIT_6_WOFFSET                     0x0
+#define GPIO_MSK_OE_1_BIT_6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_BIT_6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_6_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_BIT_6_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_1_BIT_5_SHIFT                       _MK_SHIFT_CONST(5)
+#define GPIO_MSK_OE_1_BIT_5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_BIT_5_SHIFT)
+#define GPIO_MSK_OE_1_BIT_5_RANGE                       5:5
+#define GPIO_MSK_OE_1_BIT_5_WOFFSET                     0x0
+#define GPIO_MSK_OE_1_BIT_5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_BIT_5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_5_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_BIT_5_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_1_BIT_4_SHIFT                       _MK_SHIFT_CONST(4)
+#define GPIO_MSK_OE_1_BIT_4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_BIT_4_SHIFT)
+#define GPIO_MSK_OE_1_BIT_4_RANGE                       4:4
+#define GPIO_MSK_OE_1_BIT_4_WOFFSET                     0x0
+#define GPIO_MSK_OE_1_BIT_4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_BIT_4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_4_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_BIT_4_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_1_BIT_3_SHIFT                       _MK_SHIFT_CONST(3)
+#define GPIO_MSK_OE_1_BIT_3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_BIT_3_SHIFT)
+#define GPIO_MSK_OE_1_BIT_3_RANGE                       3:3
+#define GPIO_MSK_OE_1_BIT_3_WOFFSET                     0x0
+#define GPIO_MSK_OE_1_BIT_3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_BIT_3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_3_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_BIT_3_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_1_BIT_2_SHIFT                       _MK_SHIFT_CONST(2)
+#define GPIO_MSK_OE_1_BIT_2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_BIT_2_SHIFT)
+#define GPIO_MSK_OE_1_BIT_2_RANGE                       2:2
+#define GPIO_MSK_OE_1_BIT_2_WOFFSET                     0x0
+#define GPIO_MSK_OE_1_BIT_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_BIT_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_2_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_BIT_2_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_1_BIT_1_SHIFT                       _MK_SHIFT_CONST(1)
+#define GPIO_MSK_OE_1_BIT_1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_BIT_1_SHIFT)
+#define GPIO_MSK_OE_1_BIT_1_RANGE                       1:1
+#define GPIO_MSK_OE_1_BIT_1_WOFFSET                     0x0
+#define GPIO_MSK_OE_1_BIT_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_BIT_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_1_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_BIT_1_DRIVEN                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_1_BIT_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define GPIO_MSK_OE_1_BIT_0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_1_BIT_0_SHIFT)
+#define GPIO_MSK_OE_1_BIT_0_RANGE                       0:0
+#define GPIO_MSK_OE_1_BIT_0_WOFFSET                     0x0
+#define GPIO_MSK_OE_1_BIT_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_1_BIT_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_1_BIT_0_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_1_BIT_0_DRIVEN                      _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_OE_2  
+#define GPIO_MSK_OE_2                   _MK_ADDR_CONST(0x818)
+#define GPIO_MSK_OE_2_WORD_COUNT                        0x1
+#define GPIO_MSK_OE_2_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_OE_2_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_READ_MASK                         _MK_MASK_CONST(0xff)
+#define GPIO_MSK_OE_2_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_2_MSK7_SHIFT                        _MK_SHIFT_CONST(15)
+#define GPIO_MSK_OE_2_MSK7_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_MSK7_SHIFT)
+#define GPIO_MSK_OE_2_MSK7_RANGE                        15:15
+#define GPIO_MSK_OE_2_MSK7_WOFFSET                      0x0
+#define GPIO_MSK_OE_2_MSK7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_MSK7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK7_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_MSK7_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_2_MSK6_SHIFT                        _MK_SHIFT_CONST(14)
+#define GPIO_MSK_OE_2_MSK6_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_MSK6_SHIFT)
+#define GPIO_MSK_OE_2_MSK6_RANGE                        14:14
+#define GPIO_MSK_OE_2_MSK6_WOFFSET                      0x0
+#define GPIO_MSK_OE_2_MSK6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_MSK6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK6_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_MSK6_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_2_MSK5_SHIFT                        _MK_SHIFT_CONST(13)
+#define GPIO_MSK_OE_2_MSK5_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_MSK5_SHIFT)
+#define GPIO_MSK_OE_2_MSK5_RANGE                        13:13
+#define GPIO_MSK_OE_2_MSK5_WOFFSET                      0x0
+#define GPIO_MSK_OE_2_MSK5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_MSK5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK5_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_MSK5_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_2_MSK4_SHIFT                        _MK_SHIFT_CONST(12)
+#define GPIO_MSK_OE_2_MSK4_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_MSK4_SHIFT)
+#define GPIO_MSK_OE_2_MSK4_RANGE                        12:12
+#define GPIO_MSK_OE_2_MSK4_WOFFSET                      0x0
+#define GPIO_MSK_OE_2_MSK4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_MSK4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK4_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_MSK4_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_2_MSK3_SHIFT                        _MK_SHIFT_CONST(11)
+#define GPIO_MSK_OE_2_MSK3_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_MSK3_SHIFT)
+#define GPIO_MSK_OE_2_MSK3_RANGE                        11:11
+#define GPIO_MSK_OE_2_MSK3_WOFFSET                      0x0
+#define GPIO_MSK_OE_2_MSK3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_MSK3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK3_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_MSK3_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_2_MSK2_SHIFT                        _MK_SHIFT_CONST(10)
+#define GPIO_MSK_OE_2_MSK2_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_MSK2_SHIFT)
+#define GPIO_MSK_OE_2_MSK2_RANGE                        10:10
+#define GPIO_MSK_OE_2_MSK2_WOFFSET                      0x0
+#define GPIO_MSK_OE_2_MSK2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_MSK2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK2_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_MSK2_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_2_MSK1_SHIFT                        _MK_SHIFT_CONST(9)
+#define GPIO_MSK_OE_2_MSK1_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_MSK1_SHIFT)
+#define GPIO_MSK_OE_2_MSK1_RANGE                        9:9
+#define GPIO_MSK_OE_2_MSK1_WOFFSET                      0x0
+#define GPIO_MSK_OE_2_MSK1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_MSK1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK1_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_MSK1_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_2_MSK0_SHIFT                        _MK_SHIFT_CONST(8)
+#define GPIO_MSK_OE_2_MSK0_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_MSK0_SHIFT)
+#define GPIO_MSK_OE_2_MSK0_RANGE                        8:8
+#define GPIO_MSK_OE_2_MSK0_WOFFSET                      0x0
+#define GPIO_MSK_OE_2_MSK0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_MSK0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_MSK0_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_MSK0_ENABLE                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_2_BIT_7_SHIFT                       _MK_SHIFT_CONST(7)
+#define GPIO_MSK_OE_2_BIT_7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_BIT_7_SHIFT)
+#define GPIO_MSK_OE_2_BIT_7_RANGE                       7:7
+#define GPIO_MSK_OE_2_BIT_7_WOFFSET                     0x0
+#define GPIO_MSK_OE_2_BIT_7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_BIT_7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_7_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_BIT_7_DRIVEN                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_2_BIT_6_SHIFT                       _MK_SHIFT_CONST(6)
+#define GPIO_MSK_OE_2_BIT_6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_BIT_6_SHIFT)
+#define GPIO_MSK_OE_2_BIT_6_RANGE                       6:6
+#define GPIO_MSK_OE_2_BIT_6_WOFFSET                     0x0
+#define GPIO_MSK_OE_2_BIT_6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_BIT_6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_6_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_BIT_6_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_2_BIT_5_SHIFT                       _MK_SHIFT_CONST(5)
+#define GPIO_MSK_OE_2_BIT_5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_BIT_5_SHIFT)
+#define GPIO_MSK_OE_2_BIT_5_RANGE                       5:5
+#define GPIO_MSK_OE_2_BIT_5_WOFFSET                     0x0
+#define GPIO_MSK_OE_2_BIT_5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_BIT_5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_5_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_BIT_5_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_2_BIT_4_SHIFT                       _MK_SHIFT_CONST(4)
+#define GPIO_MSK_OE_2_BIT_4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_BIT_4_SHIFT)
+#define GPIO_MSK_OE_2_BIT_4_RANGE                       4:4
+#define GPIO_MSK_OE_2_BIT_4_WOFFSET                     0x0
+#define GPIO_MSK_OE_2_BIT_4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_BIT_4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_4_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_BIT_4_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_2_BIT_3_SHIFT                       _MK_SHIFT_CONST(3)
+#define GPIO_MSK_OE_2_BIT_3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_BIT_3_SHIFT)
+#define GPIO_MSK_OE_2_BIT_3_RANGE                       3:3
+#define GPIO_MSK_OE_2_BIT_3_WOFFSET                     0x0
+#define GPIO_MSK_OE_2_BIT_3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_BIT_3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_3_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_BIT_3_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_2_BIT_2_SHIFT                       _MK_SHIFT_CONST(2)
+#define GPIO_MSK_OE_2_BIT_2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_BIT_2_SHIFT)
+#define GPIO_MSK_OE_2_BIT_2_RANGE                       2:2
+#define GPIO_MSK_OE_2_BIT_2_WOFFSET                     0x0
+#define GPIO_MSK_OE_2_BIT_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_BIT_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_2_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_BIT_2_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_2_BIT_1_SHIFT                       _MK_SHIFT_CONST(1)
+#define GPIO_MSK_OE_2_BIT_1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_BIT_1_SHIFT)
+#define GPIO_MSK_OE_2_BIT_1_RANGE                       1:1
+#define GPIO_MSK_OE_2_BIT_1_WOFFSET                     0x0
+#define GPIO_MSK_OE_2_BIT_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_BIT_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_1_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_BIT_1_DRIVEN                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_2_BIT_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define GPIO_MSK_OE_2_BIT_0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_2_BIT_0_SHIFT)
+#define GPIO_MSK_OE_2_BIT_0_RANGE                       0:0
+#define GPIO_MSK_OE_2_BIT_0_WOFFSET                     0x0
+#define GPIO_MSK_OE_2_BIT_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_2_BIT_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_2_BIT_0_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_2_BIT_0_DRIVEN                      _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_OE_3  
+#define GPIO_MSK_OE_3                   _MK_ADDR_CONST(0x81c)
+#define GPIO_MSK_OE_3_WORD_COUNT                        0x1
+#define GPIO_MSK_OE_3_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_OE_3_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_READ_MASK                         _MK_MASK_CONST(0xff)
+#define GPIO_MSK_OE_3_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_3_MSK7_SHIFT                        _MK_SHIFT_CONST(15)
+#define GPIO_MSK_OE_3_MSK7_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_MSK7_SHIFT)
+#define GPIO_MSK_OE_3_MSK7_RANGE                        15:15
+#define GPIO_MSK_OE_3_MSK7_WOFFSET                      0x0
+#define GPIO_MSK_OE_3_MSK7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_MSK7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK7_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_MSK7_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_3_MSK6_SHIFT                        _MK_SHIFT_CONST(14)
+#define GPIO_MSK_OE_3_MSK6_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_MSK6_SHIFT)
+#define GPIO_MSK_OE_3_MSK6_RANGE                        14:14
+#define GPIO_MSK_OE_3_MSK6_WOFFSET                      0x0
+#define GPIO_MSK_OE_3_MSK6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_MSK6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK6_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_MSK6_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_3_MSK5_SHIFT                        _MK_SHIFT_CONST(13)
+#define GPIO_MSK_OE_3_MSK5_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_MSK5_SHIFT)
+#define GPIO_MSK_OE_3_MSK5_RANGE                        13:13
+#define GPIO_MSK_OE_3_MSK5_WOFFSET                      0x0
+#define GPIO_MSK_OE_3_MSK5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_MSK5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK5_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_MSK5_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_3_MSK4_SHIFT                        _MK_SHIFT_CONST(12)
+#define GPIO_MSK_OE_3_MSK4_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_MSK4_SHIFT)
+#define GPIO_MSK_OE_3_MSK4_RANGE                        12:12
+#define GPIO_MSK_OE_3_MSK4_WOFFSET                      0x0
+#define GPIO_MSK_OE_3_MSK4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_MSK4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK4_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_MSK4_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_3_MSK3_SHIFT                        _MK_SHIFT_CONST(11)
+#define GPIO_MSK_OE_3_MSK3_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_MSK3_SHIFT)
+#define GPIO_MSK_OE_3_MSK3_RANGE                        11:11
+#define GPIO_MSK_OE_3_MSK3_WOFFSET                      0x0
+#define GPIO_MSK_OE_3_MSK3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_MSK3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK3_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_MSK3_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_3_MSK2_SHIFT                        _MK_SHIFT_CONST(10)
+#define GPIO_MSK_OE_3_MSK2_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_MSK2_SHIFT)
+#define GPIO_MSK_OE_3_MSK2_RANGE                        10:10
+#define GPIO_MSK_OE_3_MSK2_WOFFSET                      0x0
+#define GPIO_MSK_OE_3_MSK2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_MSK2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK2_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_MSK2_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_3_MSK1_SHIFT                        _MK_SHIFT_CONST(9)
+#define GPIO_MSK_OE_3_MSK1_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_MSK1_SHIFT)
+#define GPIO_MSK_OE_3_MSK1_RANGE                        9:9
+#define GPIO_MSK_OE_3_MSK1_WOFFSET                      0x0
+#define GPIO_MSK_OE_3_MSK1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_MSK1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK1_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_MSK1_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OE_3_MSK0_SHIFT                        _MK_SHIFT_CONST(8)
+#define GPIO_MSK_OE_3_MSK0_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_MSK0_SHIFT)
+#define GPIO_MSK_OE_3_MSK0_RANGE                        8:8
+#define GPIO_MSK_OE_3_MSK0_WOFFSET                      0x0
+#define GPIO_MSK_OE_3_MSK0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_MSK0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_MSK0_DISABLE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_MSK0_ENABLE                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_3_BIT_7_SHIFT                       _MK_SHIFT_CONST(7)
+#define GPIO_MSK_OE_3_BIT_7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_BIT_7_SHIFT)
+#define GPIO_MSK_OE_3_BIT_7_RANGE                       7:7
+#define GPIO_MSK_OE_3_BIT_7_WOFFSET                     0x0
+#define GPIO_MSK_OE_3_BIT_7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_BIT_7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_7_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_BIT_7_DRIVEN                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_3_BIT_6_SHIFT                       _MK_SHIFT_CONST(6)
+#define GPIO_MSK_OE_3_BIT_6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_BIT_6_SHIFT)
+#define GPIO_MSK_OE_3_BIT_6_RANGE                       6:6
+#define GPIO_MSK_OE_3_BIT_6_WOFFSET                     0x0
+#define GPIO_MSK_OE_3_BIT_6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_BIT_6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_6_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_BIT_6_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_3_BIT_5_SHIFT                       _MK_SHIFT_CONST(5)
+#define GPIO_MSK_OE_3_BIT_5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_BIT_5_SHIFT)
+#define GPIO_MSK_OE_3_BIT_5_RANGE                       5:5
+#define GPIO_MSK_OE_3_BIT_5_WOFFSET                     0x0
+#define GPIO_MSK_OE_3_BIT_5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_BIT_5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_5_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_BIT_5_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_3_BIT_4_SHIFT                       _MK_SHIFT_CONST(4)
+#define GPIO_MSK_OE_3_BIT_4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_BIT_4_SHIFT)
+#define GPIO_MSK_OE_3_BIT_4_RANGE                       4:4
+#define GPIO_MSK_OE_3_BIT_4_WOFFSET                     0x0
+#define GPIO_MSK_OE_3_BIT_4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_BIT_4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_4_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_BIT_4_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_3_BIT_3_SHIFT                       _MK_SHIFT_CONST(3)
+#define GPIO_MSK_OE_3_BIT_3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_BIT_3_SHIFT)
+#define GPIO_MSK_OE_3_BIT_3_RANGE                       3:3
+#define GPIO_MSK_OE_3_BIT_3_WOFFSET                     0x0
+#define GPIO_MSK_OE_3_BIT_3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_BIT_3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_3_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_BIT_3_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_3_BIT_2_SHIFT                       _MK_SHIFT_CONST(2)
+#define GPIO_MSK_OE_3_BIT_2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_BIT_2_SHIFT)
+#define GPIO_MSK_OE_3_BIT_2_RANGE                       2:2
+#define GPIO_MSK_OE_3_BIT_2_WOFFSET                     0x0
+#define GPIO_MSK_OE_3_BIT_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_BIT_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_2_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_BIT_2_DRIVEN                      _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OE_3_BIT_1_SHIFT                       _MK_SHIFT_CONST(1)
+#define GPIO_MSK_OE_3_BIT_1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_BIT_1_SHIFT)
+#define GPIO_MSK_OE_3_BIT_1_RANGE                       1:1
+#define GPIO_MSK_OE_3_BIT_1_WOFFSET                     0x0
+#define GPIO_MSK_OE_3_BIT_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_BIT_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_1_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_BIT_1_DRIVEN                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OE_3_BIT_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define GPIO_MSK_OE_3_BIT_0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OE_3_BIT_0_SHIFT)
+#define GPIO_MSK_OE_3_BIT_0_RANGE                       0:0
+#define GPIO_MSK_OE_3_BIT_0_WOFFSET                     0x0
+#define GPIO_MSK_OE_3_BIT_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OE_3_BIT_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OE_3_BIT_0_TRI_STATE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_OE_3_BIT_0_DRIVEN                      _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_OUT_0  
+#define GPIO_MSK_OUT_0                  _MK_ADDR_CONST(0x820)
+#define GPIO_MSK_OUT_0_WORD_COUNT                       0x1
+#define GPIO_MSK_OUT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_OUT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_MSK_OUT_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_0_MSK7_SHIFT                       _MK_SHIFT_CONST(15)
+#define GPIO_MSK_OUT_0_MSK7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_MSK7_SHIFT)
+#define GPIO_MSK_OUT_0_MSK7_RANGE                       15:15
+#define GPIO_MSK_OUT_0_MSK7_WOFFSET                     0x0
+#define GPIO_MSK_OUT_0_MSK7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_MSK7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK7_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_MSK7_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_0_MSK6_SHIFT                       _MK_SHIFT_CONST(14)
+#define GPIO_MSK_OUT_0_MSK6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_MSK6_SHIFT)
+#define GPIO_MSK_OUT_0_MSK6_RANGE                       14:14
+#define GPIO_MSK_OUT_0_MSK6_WOFFSET                     0x0
+#define GPIO_MSK_OUT_0_MSK6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_MSK6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK6_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_MSK6_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_0_MSK5_SHIFT                       _MK_SHIFT_CONST(13)
+#define GPIO_MSK_OUT_0_MSK5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_MSK5_SHIFT)
+#define GPIO_MSK_OUT_0_MSK5_RANGE                       13:13
+#define GPIO_MSK_OUT_0_MSK5_WOFFSET                     0x0
+#define GPIO_MSK_OUT_0_MSK5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_MSK5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK5_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_MSK5_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_0_MSK4_SHIFT                       _MK_SHIFT_CONST(12)
+#define GPIO_MSK_OUT_0_MSK4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_MSK4_SHIFT)
+#define GPIO_MSK_OUT_0_MSK4_RANGE                       12:12
+#define GPIO_MSK_OUT_0_MSK4_WOFFSET                     0x0
+#define GPIO_MSK_OUT_0_MSK4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_MSK4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK4_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_MSK4_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_0_MSK3_SHIFT                       _MK_SHIFT_CONST(11)
+#define GPIO_MSK_OUT_0_MSK3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_MSK3_SHIFT)
+#define GPIO_MSK_OUT_0_MSK3_RANGE                       11:11
+#define GPIO_MSK_OUT_0_MSK3_WOFFSET                     0x0
+#define GPIO_MSK_OUT_0_MSK3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_MSK3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK3_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_MSK3_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_0_MSK2_SHIFT                       _MK_SHIFT_CONST(10)
+#define GPIO_MSK_OUT_0_MSK2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_MSK2_SHIFT)
+#define GPIO_MSK_OUT_0_MSK2_RANGE                       10:10
+#define GPIO_MSK_OUT_0_MSK2_WOFFSET                     0x0
+#define GPIO_MSK_OUT_0_MSK2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_MSK2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK2_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_MSK2_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_0_MSK1_SHIFT                       _MK_SHIFT_CONST(9)
+#define GPIO_MSK_OUT_0_MSK1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_MSK1_SHIFT)
+#define GPIO_MSK_OUT_0_MSK1_RANGE                       9:9
+#define GPIO_MSK_OUT_0_MSK1_WOFFSET                     0x0
+#define GPIO_MSK_OUT_0_MSK1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_MSK1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK1_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_MSK1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_0_MSK0_SHIFT                       _MK_SHIFT_CONST(8)
+#define GPIO_MSK_OUT_0_MSK0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_MSK0_SHIFT)
+#define GPIO_MSK_OUT_0_MSK0_RANGE                       8:8
+#define GPIO_MSK_OUT_0_MSK0_WOFFSET                     0x0
+#define GPIO_MSK_OUT_0_MSK0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_MSK0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_MSK0_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_MSK0_ENABLE                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_0_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_MSK_OUT_0_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_BIT_7_SHIFT)
+#define GPIO_MSK_OUT_0_BIT_7_RANGE                      7:7
+#define GPIO_MSK_OUT_0_BIT_7_WOFFSET                    0x0
+#define GPIO_MSK_OUT_0_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_7_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_BIT_7_HIGH                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_0_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_MSK_OUT_0_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_BIT_6_SHIFT)
+#define GPIO_MSK_OUT_0_BIT_6_RANGE                      6:6
+#define GPIO_MSK_OUT_0_BIT_6_WOFFSET                    0x0
+#define GPIO_MSK_OUT_0_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_6_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_BIT_6_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_0_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_MSK_OUT_0_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_BIT_5_SHIFT)
+#define GPIO_MSK_OUT_0_BIT_5_RANGE                      5:5
+#define GPIO_MSK_OUT_0_BIT_5_WOFFSET                    0x0
+#define GPIO_MSK_OUT_0_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_5_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_BIT_5_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_0_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_MSK_OUT_0_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_BIT_4_SHIFT)
+#define GPIO_MSK_OUT_0_BIT_4_RANGE                      4:4
+#define GPIO_MSK_OUT_0_BIT_4_WOFFSET                    0x0
+#define GPIO_MSK_OUT_0_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_4_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_BIT_4_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_0_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_MSK_OUT_0_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_BIT_3_SHIFT)
+#define GPIO_MSK_OUT_0_BIT_3_RANGE                      3:3
+#define GPIO_MSK_OUT_0_BIT_3_WOFFSET                    0x0
+#define GPIO_MSK_OUT_0_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_3_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_BIT_3_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_0_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_MSK_OUT_0_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_BIT_2_SHIFT)
+#define GPIO_MSK_OUT_0_BIT_2_RANGE                      2:2
+#define GPIO_MSK_OUT_0_BIT_2_WOFFSET                    0x0
+#define GPIO_MSK_OUT_0_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_2_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_BIT_2_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_0_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_MSK_OUT_0_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_BIT_1_SHIFT)
+#define GPIO_MSK_OUT_0_BIT_1_RANGE                      1:1
+#define GPIO_MSK_OUT_0_BIT_1_WOFFSET                    0x0
+#define GPIO_MSK_OUT_0_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_1_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_BIT_1_HIGH                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_0_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_MSK_OUT_0_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_0_BIT_0_SHIFT)
+#define GPIO_MSK_OUT_0_BIT_0_RANGE                      0:0
+#define GPIO_MSK_OUT_0_BIT_0_WOFFSET                    0x0
+#define GPIO_MSK_OUT_0_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_0_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_0_BIT_0_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_0_BIT_0_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_OUT  
+#define GPIO_MSK_OUT                    _MK_ADDR_CONST(0x820)
+#define GPIO_MSK_OUT_WORD_COUNT                         0x1
+#define GPIO_MSK_OUT_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_OUT_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_READ_MASK                  _MK_MASK_CONST(0xff)
+#define GPIO_MSK_OUT_WRITE_MASK                         _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_MSK7_SHIFT                 _MK_SHIFT_CONST(15)
+#define GPIO_MSK_OUT_MSK7_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_MSK7_SHIFT)
+#define GPIO_MSK_OUT_MSK7_RANGE                 15:15
+#define GPIO_MSK_OUT_MSK7_WOFFSET                       0x0
+#define GPIO_MSK_OUT_MSK7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_MSK7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK7_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_MSK7_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_MSK6_SHIFT                 _MK_SHIFT_CONST(14)
+#define GPIO_MSK_OUT_MSK6_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_MSK6_SHIFT)
+#define GPIO_MSK_OUT_MSK6_RANGE                 14:14
+#define GPIO_MSK_OUT_MSK6_WOFFSET                       0x0
+#define GPIO_MSK_OUT_MSK6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_MSK6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK6_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_MSK6_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_MSK5_SHIFT                 _MK_SHIFT_CONST(13)
+#define GPIO_MSK_OUT_MSK5_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_MSK5_SHIFT)
+#define GPIO_MSK_OUT_MSK5_RANGE                 13:13
+#define GPIO_MSK_OUT_MSK5_WOFFSET                       0x0
+#define GPIO_MSK_OUT_MSK5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_MSK5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK5_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_MSK5_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_MSK4_SHIFT                 _MK_SHIFT_CONST(12)
+#define GPIO_MSK_OUT_MSK4_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_MSK4_SHIFT)
+#define GPIO_MSK_OUT_MSK4_RANGE                 12:12
+#define GPIO_MSK_OUT_MSK4_WOFFSET                       0x0
+#define GPIO_MSK_OUT_MSK4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_MSK4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK4_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_MSK4_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_MSK3_SHIFT                 _MK_SHIFT_CONST(11)
+#define GPIO_MSK_OUT_MSK3_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_MSK3_SHIFT)
+#define GPIO_MSK_OUT_MSK3_RANGE                 11:11
+#define GPIO_MSK_OUT_MSK3_WOFFSET                       0x0
+#define GPIO_MSK_OUT_MSK3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_MSK3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK3_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_MSK3_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_MSK2_SHIFT                 _MK_SHIFT_CONST(10)
+#define GPIO_MSK_OUT_MSK2_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_MSK2_SHIFT)
+#define GPIO_MSK_OUT_MSK2_RANGE                 10:10
+#define GPIO_MSK_OUT_MSK2_WOFFSET                       0x0
+#define GPIO_MSK_OUT_MSK2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_MSK2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK2_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_MSK2_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_MSK1_SHIFT                 _MK_SHIFT_CONST(9)
+#define GPIO_MSK_OUT_MSK1_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_MSK1_SHIFT)
+#define GPIO_MSK_OUT_MSK1_RANGE                 9:9
+#define GPIO_MSK_OUT_MSK1_WOFFSET                       0x0
+#define GPIO_MSK_OUT_MSK1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_MSK1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK1_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_MSK1_ENABLE                        _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_MSK0_SHIFT                 _MK_SHIFT_CONST(8)
+#define GPIO_MSK_OUT_MSK0_FIELD                 (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_MSK0_SHIFT)
+#define GPIO_MSK_OUT_MSK0_RANGE                 8:8
+#define GPIO_MSK_OUT_MSK0_WOFFSET                       0x0
+#define GPIO_MSK_OUT_MSK0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_MSK0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_MSK0_DISABLE                       _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_MSK0_ENABLE                        _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_BIT_7_SHIFT                        _MK_SHIFT_CONST(7)
+#define GPIO_MSK_OUT_BIT_7_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_BIT_7_SHIFT)
+#define GPIO_MSK_OUT_BIT_7_RANGE                        7:7
+#define GPIO_MSK_OUT_BIT_7_WOFFSET                      0x0
+#define GPIO_MSK_OUT_BIT_7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_BIT_7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_7_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_BIT_7_HIGH                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_BIT_6_SHIFT                        _MK_SHIFT_CONST(6)
+#define GPIO_MSK_OUT_BIT_6_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_BIT_6_SHIFT)
+#define GPIO_MSK_OUT_BIT_6_RANGE                        6:6
+#define GPIO_MSK_OUT_BIT_6_WOFFSET                      0x0
+#define GPIO_MSK_OUT_BIT_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_BIT_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_6_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_BIT_6_HIGH                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_BIT_5_SHIFT                        _MK_SHIFT_CONST(5)
+#define GPIO_MSK_OUT_BIT_5_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_BIT_5_SHIFT)
+#define GPIO_MSK_OUT_BIT_5_RANGE                        5:5
+#define GPIO_MSK_OUT_BIT_5_WOFFSET                      0x0
+#define GPIO_MSK_OUT_BIT_5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_BIT_5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_5_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_BIT_5_HIGH                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_BIT_4_SHIFT                        _MK_SHIFT_CONST(4)
+#define GPIO_MSK_OUT_BIT_4_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_BIT_4_SHIFT)
+#define GPIO_MSK_OUT_BIT_4_RANGE                        4:4
+#define GPIO_MSK_OUT_BIT_4_WOFFSET                      0x0
+#define GPIO_MSK_OUT_BIT_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_BIT_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_4_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_BIT_4_HIGH                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_BIT_3_SHIFT                        _MK_SHIFT_CONST(3)
+#define GPIO_MSK_OUT_BIT_3_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_BIT_3_SHIFT)
+#define GPIO_MSK_OUT_BIT_3_RANGE                        3:3
+#define GPIO_MSK_OUT_BIT_3_WOFFSET                      0x0
+#define GPIO_MSK_OUT_BIT_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_BIT_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_3_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_BIT_3_HIGH                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_BIT_2_SHIFT                        _MK_SHIFT_CONST(2)
+#define GPIO_MSK_OUT_BIT_2_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_BIT_2_SHIFT)
+#define GPIO_MSK_OUT_BIT_2_RANGE                        2:2
+#define GPIO_MSK_OUT_BIT_2_WOFFSET                      0x0
+#define GPIO_MSK_OUT_BIT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_BIT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_2_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_BIT_2_HIGH                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_BIT_1_SHIFT                        _MK_SHIFT_CONST(1)
+#define GPIO_MSK_OUT_BIT_1_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_BIT_1_SHIFT)
+#define GPIO_MSK_OUT_BIT_1_RANGE                        1:1
+#define GPIO_MSK_OUT_BIT_1_WOFFSET                      0x0
+#define GPIO_MSK_OUT_BIT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_BIT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_1_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_BIT_1_HIGH                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_BIT_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define GPIO_MSK_OUT_BIT_0_FIELD                        (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_BIT_0_SHIFT)
+#define GPIO_MSK_OUT_BIT_0_RANGE                        0:0
+#define GPIO_MSK_OUT_BIT_0_WOFFSET                      0x0
+#define GPIO_MSK_OUT_BIT_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_BIT_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_BIT_0_LOW                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_BIT_0_HIGH                 _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_OUT_1  
+#define GPIO_MSK_OUT_1                  _MK_ADDR_CONST(0x824)
+#define GPIO_MSK_OUT_1_WORD_COUNT                       0x1
+#define GPIO_MSK_OUT_1_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_OUT_1_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_MSK_OUT_1_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_1_MSK7_SHIFT                       _MK_SHIFT_CONST(15)
+#define GPIO_MSK_OUT_1_MSK7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_MSK7_SHIFT)
+#define GPIO_MSK_OUT_1_MSK7_RANGE                       15:15
+#define GPIO_MSK_OUT_1_MSK7_WOFFSET                     0x0
+#define GPIO_MSK_OUT_1_MSK7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_MSK7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK7_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_MSK7_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_1_MSK6_SHIFT                       _MK_SHIFT_CONST(14)
+#define GPIO_MSK_OUT_1_MSK6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_MSK6_SHIFT)
+#define GPIO_MSK_OUT_1_MSK6_RANGE                       14:14
+#define GPIO_MSK_OUT_1_MSK6_WOFFSET                     0x0
+#define GPIO_MSK_OUT_1_MSK6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_MSK6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK6_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_MSK6_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_1_MSK5_SHIFT                       _MK_SHIFT_CONST(13)
+#define GPIO_MSK_OUT_1_MSK5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_MSK5_SHIFT)
+#define GPIO_MSK_OUT_1_MSK5_RANGE                       13:13
+#define GPIO_MSK_OUT_1_MSK5_WOFFSET                     0x0
+#define GPIO_MSK_OUT_1_MSK5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_MSK5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK5_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_MSK5_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_1_MSK4_SHIFT                       _MK_SHIFT_CONST(12)
+#define GPIO_MSK_OUT_1_MSK4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_MSK4_SHIFT)
+#define GPIO_MSK_OUT_1_MSK4_RANGE                       12:12
+#define GPIO_MSK_OUT_1_MSK4_WOFFSET                     0x0
+#define GPIO_MSK_OUT_1_MSK4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_MSK4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK4_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_MSK4_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_1_MSK3_SHIFT                       _MK_SHIFT_CONST(11)
+#define GPIO_MSK_OUT_1_MSK3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_MSK3_SHIFT)
+#define GPIO_MSK_OUT_1_MSK3_RANGE                       11:11
+#define GPIO_MSK_OUT_1_MSK3_WOFFSET                     0x0
+#define GPIO_MSK_OUT_1_MSK3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_MSK3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK3_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_MSK3_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_1_MSK2_SHIFT                       _MK_SHIFT_CONST(10)
+#define GPIO_MSK_OUT_1_MSK2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_MSK2_SHIFT)
+#define GPIO_MSK_OUT_1_MSK2_RANGE                       10:10
+#define GPIO_MSK_OUT_1_MSK2_WOFFSET                     0x0
+#define GPIO_MSK_OUT_1_MSK2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_MSK2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK2_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_MSK2_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_1_MSK1_SHIFT                       _MK_SHIFT_CONST(9)
+#define GPIO_MSK_OUT_1_MSK1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_MSK1_SHIFT)
+#define GPIO_MSK_OUT_1_MSK1_RANGE                       9:9
+#define GPIO_MSK_OUT_1_MSK1_WOFFSET                     0x0
+#define GPIO_MSK_OUT_1_MSK1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_MSK1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK1_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_MSK1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_1_MSK0_SHIFT                       _MK_SHIFT_CONST(8)
+#define GPIO_MSK_OUT_1_MSK0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_MSK0_SHIFT)
+#define GPIO_MSK_OUT_1_MSK0_RANGE                       8:8
+#define GPIO_MSK_OUT_1_MSK0_WOFFSET                     0x0
+#define GPIO_MSK_OUT_1_MSK0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_MSK0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_MSK0_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_MSK0_ENABLE                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_1_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_MSK_OUT_1_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_BIT_7_SHIFT)
+#define GPIO_MSK_OUT_1_BIT_7_RANGE                      7:7
+#define GPIO_MSK_OUT_1_BIT_7_WOFFSET                    0x0
+#define GPIO_MSK_OUT_1_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_7_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_BIT_7_HIGH                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_1_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_MSK_OUT_1_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_BIT_6_SHIFT)
+#define GPIO_MSK_OUT_1_BIT_6_RANGE                      6:6
+#define GPIO_MSK_OUT_1_BIT_6_WOFFSET                    0x0
+#define GPIO_MSK_OUT_1_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_6_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_BIT_6_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_1_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_MSK_OUT_1_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_BIT_5_SHIFT)
+#define GPIO_MSK_OUT_1_BIT_5_RANGE                      5:5
+#define GPIO_MSK_OUT_1_BIT_5_WOFFSET                    0x0
+#define GPIO_MSK_OUT_1_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_5_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_BIT_5_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_1_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_MSK_OUT_1_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_BIT_4_SHIFT)
+#define GPIO_MSK_OUT_1_BIT_4_RANGE                      4:4
+#define GPIO_MSK_OUT_1_BIT_4_WOFFSET                    0x0
+#define GPIO_MSK_OUT_1_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_4_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_BIT_4_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_1_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_MSK_OUT_1_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_BIT_3_SHIFT)
+#define GPIO_MSK_OUT_1_BIT_3_RANGE                      3:3
+#define GPIO_MSK_OUT_1_BIT_3_WOFFSET                    0x0
+#define GPIO_MSK_OUT_1_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_3_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_BIT_3_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_1_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_MSK_OUT_1_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_BIT_2_SHIFT)
+#define GPIO_MSK_OUT_1_BIT_2_RANGE                      2:2
+#define GPIO_MSK_OUT_1_BIT_2_WOFFSET                    0x0
+#define GPIO_MSK_OUT_1_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_2_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_BIT_2_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_1_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_MSK_OUT_1_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_BIT_1_SHIFT)
+#define GPIO_MSK_OUT_1_BIT_1_RANGE                      1:1
+#define GPIO_MSK_OUT_1_BIT_1_WOFFSET                    0x0
+#define GPIO_MSK_OUT_1_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_1_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_BIT_1_HIGH                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_1_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_MSK_OUT_1_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_1_BIT_0_SHIFT)
+#define GPIO_MSK_OUT_1_BIT_0_RANGE                      0:0
+#define GPIO_MSK_OUT_1_BIT_0_WOFFSET                    0x0
+#define GPIO_MSK_OUT_1_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_1_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_1_BIT_0_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_1_BIT_0_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_OUT_2  
+#define GPIO_MSK_OUT_2                  _MK_ADDR_CONST(0x828)
+#define GPIO_MSK_OUT_2_WORD_COUNT                       0x1
+#define GPIO_MSK_OUT_2_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_OUT_2_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_MSK_OUT_2_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_2_MSK7_SHIFT                       _MK_SHIFT_CONST(15)
+#define GPIO_MSK_OUT_2_MSK7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_MSK7_SHIFT)
+#define GPIO_MSK_OUT_2_MSK7_RANGE                       15:15
+#define GPIO_MSK_OUT_2_MSK7_WOFFSET                     0x0
+#define GPIO_MSK_OUT_2_MSK7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_MSK7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK7_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_MSK7_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_2_MSK6_SHIFT                       _MK_SHIFT_CONST(14)
+#define GPIO_MSK_OUT_2_MSK6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_MSK6_SHIFT)
+#define GPIO_MSK_OUT_2_MSK6_RANGE                       14:14
+#define GPIO_MSK_OUT_2_MSK6_WOFFSET                     0x0
+#define GPIO_MSK_OUT_2_MSK6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_MSK6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK6_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_MSK6_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_2_MSK5_SHIFT                       _MK_SHIFT_CONST(13)
+#define GPIO_MSK_OUT_2_MSK5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_MSK5_SHIFT)
+#define GPIO_MSK_OUT_2_MSK5_RANGE                       13:13
+#define GPIO_MSK_OUT_2_MSK5_WOFFSET                     0x0
+#define GPIO_MSK_OUT_2_MSK5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_MSK5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK5_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_MSK5_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_2_MSK4_SHIFT                       _MK_SHIFT_CONST(12)
+#define GPIO_MSK_OUT_2_MSK4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_MSK4_SHIFT)
+#define GPIO_MSK_OUT_2_MSK4_RANGE                       12:12
+#define GPIO_MSK_OUT_2_MSK4_WOFFSET                     0x0
+#define GPIO_MSK_OUT_2_MSK4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_MSK4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK4_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_MSK4_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_2_MSK3_SHIFT                       _MK_SHIFT_CONST(11)
+#define GPIO_MSK_OUT_2_MSK3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_MSK3_SHIFT)
+#define GPIO_MSK_OUT_2_MSK3_RANGE                       11:11
+#define GPIO_MSK_OUT_2_MSK3_WOFFSET                     0x0
+#define GPIO_MSK_OUT_2_MSK3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_MSK3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK3_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_MSK3_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_2_MSK2_SHIFT                       _MK_SHIFT_CONST(10)
+#define GPIO_MSK_OUT_2_MSK2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_MSK2_SHIFT)
+#define GPIO_MSK_OUT_2_MSK2_RANGE                       10:10
+#define GPIO_MSK_OUT_2_MSK2_WOFFSET                     0x0
+#define GPIO_MSK_OUT_2_MSK2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_MSK2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK2_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_MSK2_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_2_MSK1_SHIFT                       _MK_SHIFT_CONST(9)
+#define GPIO_MSK_OUT_2_MSK1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_MSK1_SHIFT)
+#define GPIO_MSK_OUT_2_MSK1_RANGE                       9:9
+#define GPIO_MSK_OUT_2_MSK1_WOFFSET                     0x0
+#define GPIO_MSK_OUT_2_MSK1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_MSK1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK1_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_MSK1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_2_MSK0_SHIFT                       _MK_SHIFT_CONST(8)
+#define GPIO_MSK_OUT_2_MSK0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_MSK0_SHIFT)
+#define GPIO_MSK_OUT_2_MSK0_RANGE                       8:8
+#define GPIO_MSK_OUT_2_MSK0_WOFFSET                     0x0
+#define GPIO_MSK_OUT_2_MSK0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_MSK0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_MSK0_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_MSK0_ENABLE                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_2_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_MSK_OUT_2_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_BIT_7_SHIFT)
+#define GPIO_MSK_OUT_2_BIT_7_RANGE                      7:7
+#define GPIO_MSK_OUT_2_BIT_7_WOFFSET                    0x0
+#define GPIO_MSK_OUT_2_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_7_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_BIT_7_HIGH                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_2_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_MSK_OUT_2_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_BIT_6_SHIFT)
+#define GPIO_MSK_OUT_2_BIT_6_RANGE                      6:6
+#define GPIO_MSK_OUT_2_BIT_6_WOFFSET                    0x0
+#define GPIO_MSK_OUT_2_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_6_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_BIT_6_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_2_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_MSK_OUT_2_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_BIT_5_SHIFT)
+#define GPIO_MSK_OUT_2_BIT_5_RANGE                      5:5
+#define GPIO_MSK_OUT_2_BIT_5_WOFFSET                    0x0
+#define GPIO_MSK_OUT_2_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_5_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_BIT_5_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_2_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_MSK_OUT_2_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_BIT_4_SHIFT)
+#define GPIO_MSK_OUT_2_BIT_4_RANGE                      4:4
+#define GPIO_MSK_OUT_2_BIT_4_WOFFSET                    0x0
+#define GPIO_MSK_OUT_2_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_4_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_BIT_4_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_2_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_MSK_OUT_2_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_BIT_3_SHIFT)
+#define GPIO_MSK_OUT_2_BIT_3_RANGE                      3:3
+#define GPIO_MSK_OUT_2_BIT_3_WOFFSET                    0x0
+#define GPIO_MSK_OUT_2_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_3_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_BIT_3_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_2_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_MSK_OUT_2_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_BIT_2_SHIFT)
+#define GPIO_MSK_OUT_2_BIT_2_RANGE                      2:2
+#define GPIO_MSK_OUT_2_BIT_2_WOFFSET                    0x0
+#define GPIO_MSK_OUT_2_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_2_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_BIT_2_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_2_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_MSK_OUT_2_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_BIT_1_SHIFT)
+#define GPIO_MSK_OUT_2_BIT_1_RANGE                      1:1
+#define GPIO_MSK_OUT_2_BIT_1_WOFFSET                    0x0
+#define GPIO_MSK_OUT_2_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_1_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_BIT_1_HIGH                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_2_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_MSK_OUT_2_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_2_BIT_0_SHIFT)
+#define GPIO_MSK_OUT_2_BIT_0_RANGE                      0:0
+#define GPIO_MSK_OUT_2_BIT_0_WOFFSET                    0x0
+#define GPIO_MSK_OUT_2_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_2_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_2_BIT_0_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_2_BIT_0_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_OUT_3  
+#define GPIO_MSK_OUT_3                  _MK_ADDR_CONST(0x82c)
+#define GPIO_MSK_OUT_3_WORD_COUNT                       0x1
+#define GPIO_MSK_OUT_3_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_OUT_3_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_READ_MASK                        _MK_MASK_CONST(0xff)
+#define GPIO_MSK_OUT_3_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_3_MSK7_SHIFT                       _MK_SHIFT_CONST(15)
+#define GPIO_MSK_OUT_3_MSK7_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_MSK7_SHIFT)
+#define GPIO_MSK_OUT_3_MSK7_RANGE                       15:15
+#define GPIO_MSK_OUT_3_MSK7_WOFFSET                     0x0
+#define GPIO_MSK_OUT_3_MSK7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_MSK7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK7_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_MSK7_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_3_MSK6_SHIFT                       _MK_SHIFT_CONST(14)
+#define GPIO_MSK_OUT_3_MSK6_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_MSK6_SHIFT)
+#define GPIO_MSK_OUT_3_MSK6_RANGE                       14:14
+#define GPIO_MSK_OUT_3_MSK6_WOFFSET                     0x0
+#define GPIO_MSK_OUT_3_MSK6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_MSK6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK6_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_MSK6_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_3_MSK5_SHIFT                       _MK_SHIFT_CONST(13)
+#define GPIO_MSK_OUT_3_MSK5_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_MSK5_SHIFT)
+#define GPIO_MSK_OUT_3_MSK5_RANGE                       13:13
+#define GPIO_MSK_OUT_3_MSK5_WOFFSET                     0x0
+#define GPIO_MSK_OUT_3_MSK5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_MSK5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK5_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_MSK5_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_3_MSK4_SHIFT                       _MK_SHIFT_CONST(12)
+#define GPIO_MSK_OUT_3_MSK4_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_MSK4_SHIFT)
+#define GPIO_MSK_OUT_3_MSK4_RANGE                       12:12
+#define GPIO_MSK_OUT_3_MSK4_WOFFSET                     0x0
+#define GPIO_MSK_OUT_3_MSK4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_MSK4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK4_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_MSK4_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_3_MSK3_SHIFT                       _MK_SHIFT_CONST(11)
+#define GPIO_MSK_OUT_3_MSK3_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_MSK3_SHIFT)
+#define GPIO_MSK_OUT_3_MSK3_RANGE                       11:11
+#define GPIO_MSK_OUT_3_MSK3_WOFFSET                     0x0
+#define GPIO_MSK_OUT_3_MSK3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_MSK3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK3_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_MSK3_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_3_MSK2_SHIFT                       _MK_SHIFT_CONST(10)
+#define GPIO_MSK_OUT_3_MSK2_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_MSK2_SHIFT)
+#define GPIO_MSK_OUT_3_MSK2_RANGE                       10:10
+#define GPIO_MSK_OUT_3_MSK2_WOFFSET                     0x0
+#define GPIO_MSK_OUT_3_MSK2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_MSK2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK2_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_MSK2_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_3_MSK1_SHIFT                       _MK_SHIFT_CONST(9)
+#define GPIO_MSK_OUT_3_MSK1_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_MSK1_SHIFT)
+#define GPIO_MSK_OUT_3_MSK1_RANGE                       9:9
+#define GPIO_MSK_OUT_3_MSK1_WOFFSET                     0x0
+#define GPIO_MSK_OUT_3_MSK1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_MSK1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK1_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_MSK1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_OUT_3_MSK0_SHIFT                       _MK_SHIFT_CONST(8)
+#define GPIO_MSK_OUT_3_MSK0_FIELD                       (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_MSK0_SHIFT)
+#define GPIO_MSK_OUT_3_MSK0_RANGE                       8:8
+#define GPIO_MSK_OUT_3_MSK0_WOFFSET                     0x0
+#define GPIO_MSK_OUT_3_MSK0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_MSK0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_MSK0_DISABLE                     _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_MSK0_ENABLE                      _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_3_BIT_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define GPIO_MSK_OUT_3_BIT_7_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_BIT_7_SHIFT)
+#define GPIO_MSK_OUT_3_BIT_7_RANGE                      7:7
+#define GPIO_MSK_OUT_3_BIT_7_WOFFSET                    0x0
+#define GPIO_MSK_OUT_3_BIT_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_BIT_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_7_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_BIT_7_HIGH                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_3_BIT_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define GPIO_MSK_OUT_3_BIT_6_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_BIT_6_SHIFT)
+#define GPIO_MSK_OUT_3_BIT_6_RANGE                      6:6
+#define GPIO_MSK_OUT_3_BIT_6_WOFFSET                    0x0
+#define GPIO_MSK_OUT_3_BIT_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_BIT_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_6_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_BIT_6_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_3_BIT_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define GPIO_MSK_OUT_3_BIT_5_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_BIT_5_SHIFT)
+#define GPIO_MSK_OUT_3_BIT_5_RANGE                      5:5
+#define GPIO_MSK_OUT_3_BIT_5_WOFFSET                    0x0
+#define GPIO_MSK_OUT_3_BIT_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_BIT_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_5_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_BIT_5_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_3_BIT_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define GPIO_MSK_OUT_3_BIT_4_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_BIT_4_SHIFT)
+#define GPIO_MSK_OUT_3_BIT_4_RANGE                      4:4
+#define GPIO_MSK_OUT_3_BIT_4_WOFFSET                    0x0
+#define GPIO_MSK_OUT_3_BIT_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_BIT_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_4_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_BIT_4_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_3_BIT_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define GPIO_MSK_OUT_3_BIT_3_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_BIT_3_SHIFT)
+#define GPIO_MSK_OUT_3_BIT_3_RANGE                      3:3
+#define GPIO_MSK_OUT_3_BIT_3_WOFFSET                    0x0
+#define GPIO_MSK_OUT_3_BIT_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_BIT_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_3_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_BIT_3_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_3_BIT_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define GPIO_MSK_OUT_3_BIT_2_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_BIT_2_SHIFT)
+#define GPIO_MSK_OUT_3_BIT_2_RANGE                      2:2
+#define GPIO_MSK_OUT_3_BIT_2_WOFFSET                    0x0
+#define GPIO_MSK_OUT_3_BIT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_BIT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_2_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_BIT_2_HIGH                       _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_OUT_3_BIT_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define GPIO_MSK_OUT_3_BIT_1_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_BIT_1_SHIFT)
+#define GPIO_MSK_OUT_3_BIT_1_RANGE                      1:1
+#define GPIO_MSK_OUT_3_BIT_1_WOFFSET                    0x0
+#define GPIO_MSK_OUT_3_BIT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_BIT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_1_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_BIT_1_HIGH                       _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_OUT_3_BIT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define GPIO_MSK_OUT_3_BIT_0_FIELD                      (_MK_MASK_CONST(0x1) << GPIO_MSK_OUT_3_BIT_0_SHIFT)
+#define GPIO_MSK_OUT_3_BIT_0_RANGE                      0:0
+#define GPIO_MSK_OUT_3_BIT_0_WOFFSET                    0x0
+#define GPIO_MSK_OUT_3_BIT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define GPIO_MSK_OUT_3_BIT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_OUT_3_BIT_0_LOW                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_OUT_3_BIT_0_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Reserved address 2096 [0x830] 
+
+// Reserved address 2100 [0x834] 
+
+// Reserved address 2104 [0x838] 
+
+// Reserved address 2108 [0x83c] 
+
+// Register GPIO_MSK_INT_STA_0  
+#define GPIO_MSK_INT_STA_0                      _MK_ADDR_CONST(0x840)
+#define GPIO_MSK_INT_STA_0_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_STA_0_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_0_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_STA_0_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_MSK7_SHIFT)
+#define GPIO_MSK_INT_STA_0_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_STA_0_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_0_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_0_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_STA_0_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_MSK6_SHIFT)
+#define GPIO_MSK_INT_STA_0_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_STA_0_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_0_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_0_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_STA_0_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_MSK5_SHIFT)
+#define GPIO_MSK_INT_STA_0_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_STA_0_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_0_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_0_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_STA_0_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_MSK4_SHIFT)
+#define GPIO_MSK_INT_STA_0_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_STA_0_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_0_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_0_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_STA_0_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_MSK3_SHIFT)
+#define GPIO_MSK_INT_STA_0_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_STA_0_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_0_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_0_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_STA_0_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_MSK2_SHIFT)
+#define GPIO_MSK_INT_STA_0_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_STA_0_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_0_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_0_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_STA_0_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_MSK1_SHIFT)
+#define GPIO_MSK_INT_STA_0_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_STA_0_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_0_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_0_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_STA_0_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_MSK0_SHIFT)
+#define GPIO_MSK_INT_STA_0_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_STA_0_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_0_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_0_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_STA_0_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_BIT_7_SHIFT)
+#define GPIO_MSK_INT_STA_0_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_STA_0_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_0_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_7_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_BIT_7_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_0_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_STA_0_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_BIT_6_SHIFT)
+#define GPIO_MSK_INT_STA_0_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_STA_0_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_0_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_6_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_BIT_6_ACTIVE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_STA_0_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_STA_0_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_BIT_5_SHIFT)
+#define GPIO_MSK_INT_STA_0_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_STA_0_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_0_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_5_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_BIT_5_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_0_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_STA_0_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_BIT_4_SHIFT)
+#define GPIO_MSK_INT_STA_0_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_STA_0_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_0_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_4_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_BIT_4_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_0_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_STA_0_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_BIT_3_SHIFT)
+#define GPIO_MSK_INT_STA_0_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_STA_0_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_0_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_3_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_BIT_3_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_0_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_STA_0_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_BIT_2_SHIFT)
+#define GPIO_MSK_INT_STA_0_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_STA_0_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_0_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_2_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_BIT_2_ACTIVE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_STA_0_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_STA_0_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_BIT_1_SHIFT)
+#define GPIO_MSK_INT_STA_0_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_STA_0_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_0_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_1_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_BIT_1_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_0_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_STA_0_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_0_BIT_0_SHIFT)
+#define GPIO_MSK_INT_STA_0_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_STA_0_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_0_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_0_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_0_BIT_0_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_0_BIT_0_ACTIVE                 _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_STA  
+#define GPIO_MSK_INT_STA                        _MK_ADDR_CONST(0x840)
+#define GPIO_MSK_INT_STA_WORD_COUNT                     0x1
+#define GPIO_MSK_INT_STA_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_STA_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_READ_MASK                      _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_STA_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_MSK7_SHIFT                     _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_STA_MSK7_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_MSK7_SHIFT)
+#define GPIO_MSK_INT_STA_MSK7_RANGE                     15:15
+#define GPIO_MSK_INT_STA_MSK7_WOFFSET                   0x0
+#define GPIO_MSK_INT_STA_MSK7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_MSK7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK7_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_MSK7_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_MSK6_SHIFT                     _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_STA_MSK6_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_MSK6_SHIFT)
+#define GPIO_MSK_INT_STA_MSK6_RANGE                     14:14
+#define GPIO_MSK_INT_STA_MSK6_WOFFSET                   0x0
+#define GPIO_MSK_INT_STA_MSK6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_MSK6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK6_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_MSK6_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_MSK5_SHIFT                     _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_STA_MSK5_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_MSK5_SHIFT)
+#define GPIO_MSK_INT_STA_MSK5_RANGE                     13:13
+#define GPIO_MSK_INT_STA_MSK5_WOFFSET                   0x0
+#define GPIO_MSK_INT_STA_MSK5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_MSK5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK5_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_MSK5_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_MSK4_SHIFT                     _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_STA_MSK4_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_MSK4_SHIFT)
+#define GPIO_MSK_INT_STA_MSK4_RANGE                     12:12
+#define GPIO_MSK_INT_STA_MSK4_WOFFSET                   0x0
+#define GPIO_MSK_INT_STA_MSK4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_MSK4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK4_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_MSK4_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_MSK3_SHIFT                     _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_STA_MSK3_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_MSK3_SHIFT)
+#define GPIO_MSK_INT_STA_MSK3_RANGE                     11:11
+#define GPIO_MSK_INT_STA_MSK3_WOFFSET                   0x0
+#define GPIO_MSK_INT_STA_MSK3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_MSK3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK3_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_MSK3_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_MSK2_SHIFT                     _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_STA_MSK2_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_MSK2_SHIFT)
+#define GPIO_MSK_INT_STA_MSK2_RANGE                     10:10
+#define GPIO_MSK_INT_STA_MSK2_WOFFSET                   0x0
+#define GPIO_MSK_INT_STA_MSK2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_MSK2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK2_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_MSK2_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_MSK1_SHIFT                     _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_STA_MSK1_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_MSK1_SHIFT)
+#define GPIO_MSK_INT_STA_MSK1_RANGE                     9:9
+#define GPIO_MSK_INT_STA_MSK1_WOFFSET                   0x0
+#define GPIO_MSK_INT_STA_MSK1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_MSK1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK1_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_MSK1_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_MSK0_SHIFT                     _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_STA_MSK0_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_MSK0_SHIFT)
+#define GPIO_MSK_INT_STA_MSK0_RANGE                     8:8
+#define GPIO_MSK_INT_STA_MSK0_WOFFSET                   0x0
+#define GPIO_MSK_INT_STA_MSK0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_MSK0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_MSK0_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_MSK0_ENABLE                    _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_BIT_7_SHIFT                    _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_STA_BIT_7_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_BIT_7_SHIFT)
+#define GPIO_MSK_INT_STA_BIT_7_RANGE                    7:7
+#define GPIO_MSK_INT_STA_BIT_7_WOFFSET                  0x0
+#define GPIO_MSK_INT_STA_BIT_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_BIT_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_7_IN_ACTIVE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_BIT_7_ACTIVE                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_BIT_6_SHIFT                    _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_STA_BIT_6_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_BIT_6_SHIFT)
+#define GPIO_MSK_INT_STA_BIT_6_RANGE                    6:6
+#define GPIO_MSK_INT_STA_BIT_6_WOFFSET                  0x0
+#define GPIO_MSK_INT_STA_BIT_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_BIT_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_6_IN_ACTIVE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_BIT_6_ACTIVE                   _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_STA_BIT_5_SHIFT                    _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_STA_BIT_5_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_BIT_5_SHIFT)
+#define GPIO_MSK_INT_STA_BIT_5_RANGE                    5:5
+#define GPIO_MSK_INT_STA_BIT_5_WOFFSET                  0x0
+#define GPIO_MSK_INT_STA_BIT_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_BIT_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_5_IN_ACTIVE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_BIT_5_ACTIVE                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_BIT_4_SHIFT                    _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_STA_BIT_4_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_BIT_4_SHIFT)
+#define GPIO_MSK_INT_STA_BIT_4_RANGE                    4:4
+#define GPIO_MSK_INT_STA_BIT_4_WOFFSET                  0x0
+#define GPIO_MSK_INT_STA_BIT_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_BIT_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_4_IN_ACTIVE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_BIT_4_ACTIVE                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_BIT_3_SHIFT                    _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_STA_BIT_3_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_BIT_3_SHIFT)
+#define GPIO_MSK_INT_STA_BIT_3_RANGE                    3:3
+#define GPIO_MSK_INT_STA_BIT_3_WOFFSET                  0x0
+#define GPIO_MSK_INT_STA_BIT_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_BIT_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_3_IN_ACTIVE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_BIT_3_ACTIVE                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_BIT_2_SHIFT                    _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_STA_BIT_2_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_BIT_2_SHIFT)
+#define GPIO_MSK_INT_STA_BIT_2_RANGE                    2:2
+#define GPIO_MSK_INT_STA_BIT_2_WOFFSET                  0x0
+#define GPIO_MSK_INT_STA_BIT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_BIT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_2_IN_ACTIVE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_BIT_2_ACTIVE                   _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_STA_BIT_1_SHIFT                    _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_STA_BIT_1_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_BIT_1_SHIFT)
+#define GPIO_MSK_INT_STA_BIT_1_RANGE                    1:1
+#define GPIO_MSK_INT_STA_BIT_1_WOFFSET                  0x0
+#define GPIO_MSK_INT_STA_BIT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_BIT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_1_IN_ACTIVE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_BIT_1_ACTIVE                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_BIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_STA_BIT_0_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_BIT_0_SHIFT)
+#define GPIO_MSK_INT_STA_BIT_0_RANGE                    0:0
+#define GPIO_MSK_INT_STA_BIT_0_WOFFSET                  0x0
+#define GPIO_MSK_INT_STA_BIT_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_BIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_BIT_0_IN_ACTIVE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_BIT_0_ACTIVE                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_STA_1  
+#define GPIO_MSK_INT_STA_1                      _MK_ADDR_CONST(0x844)
+#define GPIO_MSK_INT_STA_1_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_STA_1_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_STA_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_STA_1_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_1_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_STA_1_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_MSK7_SHIFT)
+#define GPIO_MSK_INT_STA_1_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_STA_1_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_1_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_1_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_STA_1_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_MSK6_SHIFT)
+#define GPIO_MSK_INT_STA_1_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_STA_1_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_1_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_1_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_STA_1_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_MSK5_SHIFT)
+#define GPIO_MSK_INT_STA_1_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_STA_1_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_1_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_1_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_STA_1_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_MSK4_SHIFT)
+#define GPIO_MSK_INT_STA_1_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_STA_1_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_1_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_1_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_STA_1_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_MSK3_SHIFT)
+#define GPIO_MSK_INT_STA_1_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_STA_1_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_1_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_1_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_STA_1_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_MSK2_SHIFT)
+#define GPIO_MSK_INT_STA_1_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_STA_1_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_1_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_1_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_STA_1_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_MSK1_SHIFT)
+#define GPIO_MSK_INT_STA_1_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_STA_1_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_1_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_1_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_STA_1_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_MSK0_SHIFT)
+#define GPIO_MSK_INT_STA_1_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_STA_1_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_1_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_1_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_STA_1_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_BIT_7_SHIFT)
+#define GPIO_MSK_INT_STA_1_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_STA_1_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_1_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_7_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_BIT_7_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_1_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_STA_1_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_BIT_6_SHIFT)
+#define GPIO_MSK_INT_STA_1_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_STA_1_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_1_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_6_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_BIT_6_ACTIVE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_STA_1_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_STA_1_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_BIT_5_SHIFT)
+#define GPIO_MSK_INT_STA_1_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_STA_1_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_1_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_5_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_BIT_5_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_1_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_STA_1_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_BIT_4_SHIFT)
+#define GPIO_MSK_INT_STA_1_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_STA_1_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_1_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_4_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_BIT_4_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_1_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_STA_1_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_BIT_3_SHIFT)
+#define GPIO_MSK_INT_STA_1_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_STA_1_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_1_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_3_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_BIT_3_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_1_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_STA_1_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_BIT_2_SHIFT)
+#define GPIO_MSK_INT_STA_1_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_STA_1_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_1_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_2_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_BIT_2_ACTIVE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_STA_1_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_STA_1_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_BIT_1_SHIFT)
+#define GPIO_MSK_INT_STA_1_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_STA_1_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_1_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_1_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_BIT_1_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_1_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_STA_1_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_1_BIT_0_SHIFT)
+#define GPIO_MSK_INT_STA_1_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_STA_1_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_1_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_1_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_1_BIT_0_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_1_BIT_0_ACTIVE                 _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_STA_2  
+#define GPIO_MSK_INT_STA_2                      _MK_ADDR_CONST(0x848)
+#define GPIO_MSK_INT_STA_2_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_STA_2_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_STA_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_STA_2_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_2_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_STA_2_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_MSK7_SHIFT)
+#define GPIO_MSK_INT_STA_2_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_STA_2_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_2_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_2_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_STA_2_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_MSK6_SHIFT)
+#define GPIO_MSK_INT_STA_2_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_STA_2_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_2_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_2_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_STA_2_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_MSK5_SHIFT)
+#define GPIO_MSK_INT_STA_2_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_STA_2_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_2_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_2_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_STA_2_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_MSK4_SHIFT)
+#define GPIO_MSK_INT_STA_2_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_STA_2_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_2_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_2_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_STA_2_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_MSK3_SHIFT)
+#define GPIO_MSK_INT_STA_2_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_STA_2_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_2_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_2_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_STA_2_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_MSK2_SHIFT)
+#define GPIO_MSK_INT_STA_2_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_STA_2_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_2_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_2_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_STA_2_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_MSK1_SHIFT)
+#define GPIO_MSK_INT_STA_2_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_STA_2_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_2_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_2_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_STA_2_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_MSK0_SHIFT)
+#define GPIO_MSK_INT_STA_2_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_STA_2_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_2_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_2_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_STA_2_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_BIT_7_SHIFT)
+#define GPIO_MSK_INT_STA_2_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_STA_2_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_2_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_7_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_BIT_7_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_2_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_STA_2_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_BIT_6_SHIFT)
+#define GPIO_MSK_INT_STA_2_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_STA_2_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_2_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_6_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_BIT_6_ACTIVE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_STA_2_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_STA_2_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_BIT_5_SHIFT)
+#define GPIO_MSK_INT_STA_2_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_STA_2_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_2_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_5_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_BIT_5_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_2_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_STA_2_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_BIT_4_SHIFT)
+#define GPIO_MSK_INT_STA_2_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_STA_2_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_2_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_4_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_BIT_4_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_2_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_STA_2_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_BIT_3_SHIFT)
+#define GPIO_MSK_INT_STA_2_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_STA_2_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_2_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_3_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_BIT_3_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_2_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_STA_2_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_BIT_2_SHIFT)
+#define GPIO_MSK_INT_STA_2_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_STA_2_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_2_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_2_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_BIT_2_ACTIVE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_STA_2_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_STA_2_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_BIT_1_SHIFT)
+#define GPIO_MSK_INT_STA_2_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_STA_2_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_2_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_1_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_BIT_1_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_2_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_STA_2_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_2_BIT_0_SHIFT)
+#define GPIO_MSK_INT_STA_2_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_STA_2_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_2_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_2_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_2_BIT_0_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_2_BIT_0_ACTIVE                 _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_STA_3  
+#define GPIO_MSK_INT_STA_3                      _MK_ADDR_CONST(0x84c)
+#define GPIO_MSK_INT_STA_3_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_STA_3_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_STA_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_STA_3_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_3_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_STA_3_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_MSK7_SHIFT)
+#define GPIO_MSK_INT_STA_3_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_STA_3_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_3_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_3_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_STA_3_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_MSK6_SHIFT)
+#define GPIO_MSK_INT_STA_3_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_STA_3_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_3_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_3_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_STA_3_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_MSK5_SHIFT)
+#define GPIO_MSK_INT_STA_3_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_STA_3_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_3_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_3_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_STA_3_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_MSK4_SHIFT)
+#define GPIO_MSK_INT_STA_3_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_STA_3_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_3_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_3_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_STA_3_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_MSK3_SHIFT)
+#define GPIO_MSK_INT_STA_3_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_STA_3_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_3_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_3_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_STA_3_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_MSK2_SHIFT)
+#define GPIO_MSK_INT_STA_3_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_STA_3_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_3_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_3_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_STA_3_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_MSK1_SHIFT)
+#define GPIO_MSK_INT_STA_3_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_STA_3_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_3_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_STA_3_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_STA_3_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_MSK0_SHIFT)
+#define GPIO_MSK_INT_STA_3_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_STA_3_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_STA_3_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_3_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_STA_3_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_BIT_7_SHIFT)
+#define GPIO_MSK_INT_STA_3_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_STA_3_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_3_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_7_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_BIT_7_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_3_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_STA_3_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_BIT_6_SHIFT)
+#define GPIO_MSK_INT_STA_3_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_STA_3_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_3_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_6_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_BIT_6_ACTIVE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_STA_3_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_STA_3_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_BIT_5_SHIFT)
+#define GPIO_MSK_INT_STA_3_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_STA_3_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_3_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_5_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_BIT_5_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_3_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_STA_3_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_BIT_4_SHIFT)
+#define GPIO_MSK_INT_STA_3_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_STA_3_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_3_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_4_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_BIT_4_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_3_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_STA_3_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_BIT_3_SHIFT)
+#define GPIO_MSK_INT_STA_3_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_STA_3_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_3_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_3_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_BIT_3_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_3_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_STA_3_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_BIT_2_SHIFT)
+#define GPIO_MSK_INT_STA_3_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_STA_3_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_3_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_2_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_BIT_2_ACTIVE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_STA_3_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_STA_3_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_BIT_1_SHIFT)
+#define GPIO_MSK_INT_STA_3_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_STA_3_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_3_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_1_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_BIT_1_ACTIVE                 _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_STA_3_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_STA_3_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_STA_3_BIT_0_SHIFT)
+#define GPIO_MSK_INT_STA_3_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_STA_3_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_STA_3_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_STA_3_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_STA_3_BIT_0_IN_ACTIVE                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_STA_3_BIT_0_ACTIVE                 _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_ENB_0  
+#define GPIO_MSK_INT_ENB_0                      _MK_ADDR_CONST(0x850)
+#define GPIO_MSK_INT_ENB_0_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_ENB_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_ENB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_ENB_0_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_0_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_ENB_0_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_MSK7_SHIFT)
+#define GPIO_MSK_INT_ENB_0_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_ENB_0_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_0_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_0_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_ENB_0_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_MSK6_SHIFT)
+#define GPIO_MSK_INT_ENB_0_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_ENB_0_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_0_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_0_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_ENB_0_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_MSK5_SHIFT)
+#define GPIO_MSK_INT_ENB_0_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_ENB_0_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_0_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_0_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_ENB_0_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_MSK4_SHIFT)
+#define GPIO_MSK_INT_ENB_0_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_ENB_0_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_0_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_0_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_ENB_0_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_MSK3_SHIFT)
+#define GPIO_MSK_INT_ENB_0_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_ENB_0_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_0_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_0_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_ENB_0_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_MSK2_SHIFT)
+#define GPIO_MSK_INT_ENB_0_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_ENB_0_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_0_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_0_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_ENB_0_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_MSK1_SHIFT)
+#define GPIO_MSK_INT_ENB_0_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_ENB_0_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_0_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_0_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_ENB_0_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_MSK0_SHIFT)
+#define GPIO_MSK_INT_ENB_0_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_ENB_0_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_0_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_0_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_ENB_0_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_BIT_7_SHIFT)
+#define GPIO_MSK_INT_ENB_0_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_ENB_0_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_0_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_7_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_BIT_7_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_0_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_ENB_0_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_BIT_6_SHIFT)
+#define GPIO_MSK_INT_ENB_0_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_ENB_0_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_0_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_6_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_BIT_6_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_0_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_ENB_0_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_BIT_5_SHIFT)
+#define GPIO_MSK_INT_ENB_0_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_ENB_0_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_0_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_5_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_BIT_5_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_0_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_ENB_0_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_BIT_4_SHIFT)
+#define GPIO_MSK_INT_ENB_0_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_ENB_0_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_0_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_4_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_BIT_4_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_0_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_ENB_0_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_BIT_3_SHIFT)
+#define GPIO_MSK_INT_ENB_0_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_ENB_0_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_0_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_3_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_BIT_3_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_0_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_ENB_0_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_BIT_2_SHIFT)
+#define GPIO_MSK_INT_ENB_0_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_ENB_0_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_0_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_2_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_BIT_2_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_0_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_ENB_0_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_BIT_1_SHIFT)
+#define GPIO_MSK_INT_ENB_0_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_ENB_0_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_0_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_1_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_BIT_1_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_0_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_ENB_0_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_0_BIT_0_SHIFT)
+#define GPIO_MSK_INT_ENB_0_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_ENB_0_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_0_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_0_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_0_BIT_0_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_0_BIT_0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_ENB  
+#define GPIO_MSK_INT_ENB                        _MK_ADDR_CONST(0x850)
+#define GPIO_MSK_INT_ENB_WORD_COUNT                     0x1
+#define GPIO_MSK_INT_ENB_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_ENB_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_READ_MASK                      _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_ENB_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_MSK7_SHIFT                     _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_ENB_MSK7_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_MSK7_SHIFT)
+#define GPIO_MSK_INT_ENB_MSK7_RANGE                     15:15
+#define GPIO_MSK_INT_ENB_MSK7_WOFFSET                   0x0
+#define GPIO_MSK_INT_ENB_MSK7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_MSK7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK7_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_MSK7_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_MSK6_SHIFT                     _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_ENB_MSK6_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_MSK6_SHIFT)
+#define GPIO_MSK_INT_ENB_MSK6_RANGE                     14:14
+#define GPIO_MSK_INT_ENB_MSK6_WOFFSET                   0x0
+#define GPIO_MSK_INT_ENB_MSK6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_MSK6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK6_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_MSK6_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_MSK5_SHIFT                     _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_ENB_MSK5_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_MSK5_SHIFT)
+#define GPIO_MSK_INT_ENB_MSK5_RANGE                     13:13
+#define GPIO_MSK_INT_ENB_MSK5_WOFFSET                   0x0
+#define GPIO_MSK_INT_ENB_MSK5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_MSK5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK5_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_MSK5_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_MSK4_SHIFT                     _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_ENB_MSK4_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_MSK4_SHIFT)
+#define GPIO_MSK_INT_ENB_MSK4_RANGE                     12:12
+#define GPIO_MSK_INT_ENB_MSK4_WOFFSET                   0x0
+#define GPIO_MSK_INT_ENB_MSK4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_MSK4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK4_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_MSK4_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_MSK3_SHIFT                     _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_ENB_MSK3_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_MSK3_SHIFT)
+#define GPIO_MSK_INT_ENB_MSK3_RANGE                     11:11
+#define GPIO_MSK_INT_ENB_MSK3_WOFFSET                   0x0
+#define GPIO_MSK_INT_ENB_MSK3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_MSK3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK3_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_MSK3_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_MSK2_SHIFT                     _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_ENB_MSK2_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_MSK2_SHIFT)
+#define GPIO_MSK_INT_ENB_MSK2_RANGE                     10:10
+#define GPIO_MSK_INT_ENB_MSK2_WOFFSET                   0x0
+#define GPIO_MSK_INT_ENB_MSK2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_MSK2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK2_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_MSK2_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_MSK1_SHIFT                     _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_ENB_MSK1_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_MSK1_SHIFT)
+#define GPIO_MSK_INT_ENB_MSK1_RANGE                     9:9
+#define GPIO_MSK_INT_ENB_MSK1_WOFFSET                   0x0
+#define GPIO_MSK_INT_ENB_MSK1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_MSK1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK1_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_MSK1_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_MSK0_SHIFT                     _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_ENB_MSK0_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_MSK0_SHIFT)
+#define GPIO_MSK_INT_ENB_MSK0_RANGE                     8:8
+#define GPIO_MSK_INT_ENB_MSK0_WOFFSET                   0x0
+#define GPIO_MSK_INT_ENB_MSK0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_MSK0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_MSK0_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_MSK0_ENABLE                    _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_BIT_7_SHIFT                    _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_ENB_BIT_7_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_BIT_7_SHIFT)
+#define GPIO_MSK_INT_ENB_BIT_7_RANGE                    7:7
+#define GPIO_MSK_INT_ENB_BIT_7_WOFFSET                  0x0
+#define GPIO_MSK_INT_ENB_BIT_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_BIT_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_7_DISABLE                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_BIT_7_ENABLE                   _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_BIT_6_SHIFT                    _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_ENB_BIT_6_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_BIT_6_SHIFT)
+#define GPIO_MSK_INT_ENB_BIT_6_RANGE                    6:6
+#define GPIO_MSK_INT_ENB_BIT_6_WOFFSET                  0x0
+#define GPIO_MSK_INT_ENB_BIT_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_BIT_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_6_DISABLE                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_BIT_6_ENABLE                   _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_BIT_5_SHIFT                    _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_ENB_BIT_5_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_BIT_5_SHIFT)
+#define GPIO_MSK_INT_ENB_BIT_5_RANGE                    5:5
+#define GPIO_MSK_INT_ENB_BIT_5_WOFFSET                  0x0
+#define GPIO_MSK_INT_ENB_BIT_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_BIT_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_5_DISABLE                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_BIT_5_ENABLE                   _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_BIT_4_SHIFT                    _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_ENB_BIT_4_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_BIT_4_SHIFT)
+#define GPIO_MSK_INT_ENB_BIT_4_RANGE                    4:4
+#define GPIO_MSK_INT_ENB_BIT_4_WOFFSET                  0x0
+#define GPIO_MSK_INT_ENB_BIT_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_BIT_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_4_DISABLE                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_BIT_4_ENABLE                   _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_BIT_3_SHIFT                    _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_ENB_BIT_3_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_BIT_3_SHIFT)
+#define GPIO_MSK_INT_ENB_BIT_3_RANGE                    3:3
+#define GPIO_MSK_INT_ENB_BIT_3_WOFFSET                  0x0
+#define GPIO_MSK_INT_ENB_BIT_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_BIT_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_3_DISABLE                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_BIT_3_ENABLE                   _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_BIT_2_SHIFT                    _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_ENB_BIT_2_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_BIT_2_SHIFT)
+#define GPIO_MSK_INT_ENB_BIT_2_RANGE                    2:2
+#define GPIO_MSK_INT_ENB_BIT_2_WOFFSET                  0x0
+#define GPIO_MSK_INT_ENB_BIT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_BIT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_2_DISABLE                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_BIT_2_ENABLE                   _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_BIT_1_SHIFT                    _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_ENB_BIT_1_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_BIT_1_SHIFT)
+#define GPIO_MSK_INT_ENB_BIT_1_RANGE                    1:1
+#define GPIO_MSK_INT_ENB_BIT_1_WOFFSET                  0x0
+#define GPIO_MSK_INT_ENB_BIT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_BIT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_1_DISABLE                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_BIT_1_ENABLE                   _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_BIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_ENB_BIT_0_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_BIT_0_SHIFT)
+#define GPIO_MSK_INT_ENB_BIT_0_RANGE                    0:0
+#define GPIO_MSK_INT_ENB_BIT_0_WOFFSET                  0x0
+#define GPIO_MSK_INT_ENB_BIT_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_BIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_BIT_0_DISABLE                  _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_BIT_0_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_ENB_1  
+#define GPIO_MSK_INT_ENB_1                      _MK_ADDR_CONST(0x854)
+#define GPIO_MSK_INT_ENB_1_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_ENB_1_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_ENB_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_ENB_1_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_1_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_ENB_1_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_MSK7_SHIFT)
+#define GPIO_MSK_INT_ENB_1_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_ENB_1_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_1_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_1_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_ENB_1_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_MSK6_SHIFT)
+#define GPIO_MSK_INT_ENB_1_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_ENB_1_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_1_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_1_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_ENB_1_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_MSK5_SHIFT)
+#define GPIO_MSK_INT_ENB_1_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_ENB_1_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_1_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_1_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_ENB_1_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_MSK4_SHIFT)
+#define GPIO_MSK_INT_ENB_1_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_ENB_1_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_1_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_1_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_ENB_1_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_MSK3_SHIFT)
+#define GPIO_MSK_INT_ENB_1_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_ENB_1_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_1_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_1_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_ENB_1_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_MSK2_SHIFT)
+#define GPIO_MSK_INT_ENB_1_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_ENB_1_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_1_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_1_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_ENB_1_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_MSK1_SHIFT)
+#define GPIO_MSK_INT_ENB_1_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_ENB_1_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_1_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_1_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_ENB_1_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_MSK0_SHIFT)
+#define GPIO_MSK_INT_ENB_1_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_ENB_1_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_1_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_1_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_ENB_1_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_BIT_7_SHIFT)
+#define GPIO_MSK_INT_ENB_1_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_ENB_1_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_1_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_7_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_BIT_7_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_1_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_ENB_1_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_BIT_6_SHIFT)
+#define GPIO_MSK_INT_ENB_1_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_ENB_1_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_1_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_6_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_BIT_6_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_1_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_ENB_1_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_BIT_5_SHIFT)
+#define GPIO_MSK_INT_ENB_1_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_ENB_1_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_1_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_5_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_BIT_5_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_1_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_ENB_1_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_BIT_4_SHIFT)
+#define GPIO_MSK_INT_ENB_1_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_ENB_1_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_1_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_4_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_BIT_4_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_1_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_ENB_1_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_BIT_3_SHIFT)
+#define GPIO_MSK_INT_ENB_1_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_ENB_1_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_1_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_3_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_BIT_3_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_1_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_ENB_1_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_BIT_2_SHIFT)
+#define GPIO_MSK_INT_ENB_1_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_ENB_1_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_1_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_2_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_BIT_2_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_1_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_ENB_1_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_BIT_1_SHIFT)
+#define GPIO_MSK_INT_ENB_1_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_ENB_1_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_1_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_1_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_BIT_1_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_1_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_ENB_1_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_1_BIT_0_SHIFT)
+#define GPIO_MSK_INT_ENB_1_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_ENB_1_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_1_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_1_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_1_BIT_0_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_1_BIT_0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_ENB_2  
+#define GPIO_MSK_INT_ENB_2                      _MK_ADDR_CONST(0x858)
+#define GPIO_MSK_INT_ENB_2_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_ENB_2_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_ENB_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_ENB_2_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_2_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_ENB_2_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_MSK7_SHIFT)
+#define GPIO_MSK_INT_ENB_2_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_ENB_2_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_2_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_2_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_ENB_2_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_MSK6_SHIFT)
+#define GPIO_MSK_INT_ENB_2_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_ENB_2_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_2_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_2_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_ENB_2_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_MSK5_SHIFT)
+#define GPIO_MSK_INT_ENB_2_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_ENB_2_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_2_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_2_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_ENB_2_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_MSK4_SHIFT)
+#define GPIO_MSK_INT_ENB_2_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_ENB_2_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_2_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_2_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_ENB_2_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_MSK3_SHIFT)
+#define GPIO_MSK_INT_ENB_2_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_ENB_2_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_2_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_2_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_ENB_2_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_MSK2_SHIFT)
+#define GPIO_MSK_INT_ENB_2_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_ENB_2_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_2_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_2_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_ENB_2_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_MSK1_SHIFT)
+#define GPIO_MSK_INT_ENB_2_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_ENB_2_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_2_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_2_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_ENB_2_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_MSK0_SHIFT)
+#define GPIO_MSK_INT_ENB_2_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_ENB_2_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_2_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_2_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_ENB_2_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_BIT_7_SHIFT)
+#define GPIO_MSK_INT_ENB_2_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_ENB_2_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_2_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_7_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_BIT_7_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_2_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_ENB_2_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_BIT_6_SHIFT)
+#define GPIO_MSK_INT_ENB_2_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_ENB_2_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_2_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_6_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_BIT_6_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_2_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_ENB_2_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_BIT_5_SHIFT)
+#define GPIO_MSK_INT_ENB_2_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_ENB_2_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_2_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_5_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_BIT_5_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_2_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_ENB_2_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_BIT_4_SHIFT)
+#define GPIO_MSK_INT_ENB_2_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_ENB_2_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_2_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_4_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_BIT_4_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_2_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_ENB_2_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_BIT_3_SHIFT)
+#define GPIO_MSK_INT_ENB_2_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_ENB_2_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_2_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_3_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_BIT_3_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_2_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_ENB_2_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_BIT_2_SHIFT)
+#define GPIO_MSK_INT_ENB_2_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_ENB_2_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_2_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_2_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_BIT_2_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_2_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_ENB_2_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_BIT_1_SHIFT)
+#define GPIO_MSK_INT_ENB_2_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_ENB_2_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_2_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_1_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_BIT_1_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_2_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_ENB_2_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_2_BIT_0_SHIFT)
+#define GPIO_MSK_INT_ENB_2_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_ENB_2_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_2_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_2_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_2_BIT_0_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_2_BIT_0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_ENB_3  
+#define GPIO_MSK_INT_ENB_3                      _MK_ADDR_CONST(0x85c)
+#define GPIO_MSK_INT_ENB_3_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_ENB_3_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_ENB_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_ENB_3_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_3_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_ENB_3_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_MSK7_SHIFT)
+#define GPIO_MSK_INT_ENB_3_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_ENB_3_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_3_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_3_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_ENB_3_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_MSK6_SHIFT)
+#define GPIO_MSK_INT_ENB_3_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_ENB_3_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_3_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_3_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_ENB_3_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_MSK5_SHIFT)
+#define GPIO_MSK_INT_ENB_3_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_ENB_3_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_3_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_3_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_ENB_3_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_MSK4_SHIFT)
+#define GPIO_MSK_INT_ENB_3_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_ENB_3_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_3_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_3_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_ENB_3_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_MSK3_SHIFT)
+#define GPIO_MSK_INT_ENB_3_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_ENB_3_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_3_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_3_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_ENB_3_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_MSK2_SHIFT)
+#define GPIO_MSK_INT_ENB_3_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_ENB_3_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_3_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_3_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_ENB_3_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_MSK1_SHIFT)
+#define GPIO_MSK_INT_ENB_3_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_ENB_3_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_3_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_ENB_3_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_ENB_3_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_MSK0_SHIFT)
+#define GPIO_MSK_INT_ENB_3_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_ENB_3_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_ENB_3_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_3_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_ENB_3_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_BIT_7_SHIFT)
+#define GPIO_MSK_INT_ENB_3_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_ENB_3_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_3_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_7_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_BIT_7_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_3_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_ENB_3_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_BIT_6_SHIFT)
+#define GPIO_MSK_INT_ENB_3_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_ENB_3_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_3_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_6_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_BIT_6_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_3_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_ENB_3_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_BIT_5_SHIFT)
+#define GPIO_MSK_INT_ENB_3_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_ENB_3_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_3_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_5_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_BIT_5_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_3_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_ENB_3_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_BIT_4_SHIFT)
+#define GPIO_MSK_INT_ENB_3_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_ENB_3_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_3_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_4_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_BIT_4_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_3_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_ENB_3_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_BIT_3_SHIFT)
+#define GPIO_MSK_INT_ENB_3_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_ENB_3_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_3_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_3_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_BIT_3_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_3_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_ENB_3_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_BIT_2_SHIFT)
+#define GPIO_MSK_INT_ENB_3_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_ENB_3_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_3_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_2_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_BIT_2_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_3_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_ENB_3_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_BIT_1_SHIFT)
+#define GPIO_MSK_INT_ENB_3_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_ENB_3_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_3_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_1_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_BIT_1_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define GPIO_MSK_INT_ENB_3_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_ENB_3_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_ENB_3_BIT_0_SHIFT)
+#define GPIO_MSK_INT_ENB_3_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_ENB_3_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_ENB_3_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_ENB_3_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_ENB_3_BIT_0_DISABLE                        _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_ENB_3_BIT_0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_LVL_0  
+#define GPIO_MSK_INT_LVL_0                      _MK_ADDR_CONST(0x860)
+#define GPIO_MSK_INT_LVL_0_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_LVL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_LVL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_LVL_0_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_0_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_LVL_0_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_MSK7_SHIFT)
+#define GPIO_MSK_INT_LVL_0_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_LVL_0_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_0_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_0_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_LVL_0_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_MSK6_SHIFT)
+#define GPIO_MSK_INT_LVL_0_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_LVL_0_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_0_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_0_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_LVL_0_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_MSK5_SHIFT)
+#define GPIO_MSK_INT_LVL_0_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_LVL_0_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_0_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_0_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_LVL_0_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_MSK4_SHIFT)
+#define GPIO_MSK_INT_LVL_0_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_LVL_0_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_0_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_0_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_LVL_0_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_MSK3_SHIFT)
+#define GPIO_MSK_INT_LVL_0_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_LVL_0_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_0_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_0_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_LVL_0_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_MSK2_SHIFT)
+#define GPIO_MSK_INT_LVL_0_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_LVL_0_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_0_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_0_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_LVL_0_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_MSK1_SHIFT)
+#define GPIO_MSK_INT_LVL_0_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_LVL_0_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_0_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_0_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_LVL_0_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_MSK0_SHIFT)
+#define GPIO_MSK_INT_LVL_0_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_LVL_0_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_0_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_0_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_LVL_0_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_BIT_7_SHIFT)
+#define GPIO_MSK_INT_LVL_0_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_LVL_0_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_0_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_7_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_BIT_7_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_0_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_LVL_0_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_BIT_6_SHIFT)
+#define GPIO_MSK_INT_LVL_0_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_LVL_0_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_0_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_6_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_BIT_6_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_0_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_LVL_0_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_BIT_5_SHIFT)
+#define GPIO_MSK_INT_LVL_0_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_LVL_0_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_0_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_5_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_BIT_5_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_0_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_LVL_0_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_BIT_4_SHIFT)
+#define GPIO_MSK_INT_LVL_0_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_LVL_0_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_0_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_4_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_BIT_4_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_0_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_LVL_0_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_BIT_3_SHIFT)
+#define GPIO_MSK_INT_LVL_0_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_LVL_0_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_0_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_3_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_BIT_3_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_0_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_LVL_0_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_BIT_2_SHIFT)
+#define GPIO_MSK_INT_LVL_0_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_LVL_0_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_0_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_2_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_BIT_2_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_0_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_LVL_0_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_BIT_1_SHIFT)
+#define GPIO_MSK_INT_LVL_0_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_LVL_0_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_0_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_1_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_BIT_1_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_0_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_LVL_0_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_0_BIT_0_SHIFT)
+#define GPIO_MSK_INT_LVL_0_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_LVL_0_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_0_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_0_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_0_BIT_0_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_0_BIT_0_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_LVL  
+#define GPIO_MSK_INT_LVL                        _MK_ADDR_CONST(0x860)
+#define GPIO_MSK_INT_LVL_WORD_COUNT                     0x1
+#define GPIO_MSK_INT_LVL_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_LVL_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_READ_MASK                      _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_LVL_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_MSK7_SHIFT                     _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_LVL_MSK7_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_MSK7_SHIFT)
+#define GPIO_MSK_INT_LVL_MSK7_RANGE                     15:15
+#define GPIO_MSK_INT_LVL_MSK7_WOFFSET                   0x0
+#define GPIO_MSK_INT_LVL_MSK7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_MSK7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK7_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_MSK7_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_MSK6_SHIFT                     _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_LVL_MSK6_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_MSK6_SHIFT)
+#define GPIO_MSK_INT_LVL_MSK6_RANGE                     14:14
+#define GPIO_MSK_INT_LVL_MSK6_WOFFSET                   0x0
+#define GPIO_MSK_INT_LVL_MSK6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_MSK6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK6_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_MSK6_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_MSK5_SHIFT                     _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_LVL_MSK5_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_MSK5_SHIFT)
+#define GPIO_MSK_INT_LVL_MSK5_RANGE                     13:13
+#define GPIO_MSK_INT_LVL_MSK5_WOFFSET                   0x0
+#define GPIO_MSK_INT_LVL_MSK5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_MSK5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK5_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_MSK5_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_MSK4_SHIFT                     _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_LVL_MSK4_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_MSK4_SHIFT)
+#define GPIO_MSK_INT_LVL_MSK4_RANGE                     12:12
+#define GPIO_MSK_INT_LVL_MSK4_WOFFSET                   0x0
+#define GPIO_MSK_INT_LVL_MSK4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_MSK4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK4_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_MSK4_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_MSK3_SHIFT                     _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_LVL_MSK3_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_MSK3_SHIFT)
+#define GPIO_MSK_INT_LVL_MSK3_RANGE                     11:11
+#define GPIO_MSK_INT_LVL_MSK3_WOFFSET                   0x0
+#define GPIO_MSK_INT_LVL_MSK3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_MSK3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK3_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_MSK3_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_MSK2_SHIFT                     _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_LVL_MSK2_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_MSK2_SHIFT)
+#define GPIO_MSK_INT_LVL_MSK2_RANGE                     10:10
+#define GPIO_MSK_INT_LVL_MSK2_WOFFSET                   0x0
+#define GPIO_MSK_INT_LVL_MSK2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_MSK2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK2_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_MSK2_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_MSK1_SHIFT                     _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_LVL_MSK1_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_MSK1_SHIFT)
+#define GPIO_MSK_INT_LVL_MSK1_RANGE                     9:9
+#define GPIO_MSK_INT_LVL_MSK1_WOFFSET                   0x0
+#define GPIO_MSK_INT_LVL_MSK1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_MSK1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK1_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_MSK1_ENABLE                    _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_MSK0_SHIFT                     _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_LVL_MSK0_FIELD                     (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_MSK0_SHIFT)
+#define GPIO_MSK_INT_LVL_MSK0_RANGE                     8:8
+#define GPIO_MSK_INT_LVL_MSK0_WOFFSET                   0x0
+#define GPIO_MSK_INT_LVL_MSK0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_MSK0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_MSK0_DISABLE                   _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_MSK0_ENABLE                    _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_BIT_7_SHIFT                    _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_LVL_BIT_7_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_BIT_7_SHIFT)
+#define GPIO_MSK_INT_LVL_BIT_7_RANGE                    7:7
+#define GPIO_MSK_INT_LVL_BIT_7_WOFFSET                  0x0
+#define GPIO_MSK_INT_LVL_BIT_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_BIT_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_7_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_BIT_7_HIGH                     _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_BIT_6_SHIFT                    _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_LVL_BIT_6_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_BIT_6_SHIFT)
+#define GPIO_MSK_INT_LVL_BIT_6_RANGE                    6:6
+#define GPIO_MSK_INT_LVL_BIT_6_WOFFSET                  0x0
+#define GPIO_MSK_INT_LVL_BIT_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_BIT_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_6_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_BIT_6_HIGH                     _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_BIT_5_SHIFT                    _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_LVL_BIT_5_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_BIT_5_SHIFT)
+#define GPIO_MSK_INT_LVL_BIT_5_RANGE                    5:5
+#define GPIO_MSK_INT_LVL_BIT_5_WOFFSET                  0x0
+#define GPIO_MSK_INT_LVL_BIT_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_BIT_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_5_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_BIT_5_HIGH                     _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_BIT_4_SHIFT                    _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_LVL_BIT_4_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_BIT_4_SHIFT)
+#define GPIO_MSK_INT_LVL_BIT_4_RANGE                    4:4
+#define GPIO_MSK_INT_LVL_BIT_4_WOFFSET                  0x0
+#define GPIO_MSK_INT_LVL_BIT_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_BIT_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_4_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_BIT_4_HIGH                     _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_BIT_3_SHIFT                    _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_LVL_BIT_3_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_BIT_3_SHIFT)
+#define GPIO_MSK_INT_LVL_BIT_3_RANGE                    3:3
+#define GPIO_MSK_INT_LVL_BIT_3_WOFFSET                  0x0
+#define GPIO_MSK_INT_LVL_BIT_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_BIT_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_3_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_BIT_3_HIGH                     _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_BIT_2_SHIFT                    _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_LVL_BIT_2_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_BIT_2_SHIFT)
+#define GPIO_MSK_INT_LVL_BIT_2_RANGE                    2:2
+#define GPIO_MSK_INT_LVL_BIT_2_WOFFSET                  0x0
+#define GPIO_MSK_INT_LVL_BIT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_BIT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_2_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_BIT_2_HIGH                     _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_BIT_1_SHIFT                    _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_LVL_BIT_1_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_BIT_1_SHIFT)
+#define GPIO_MSK_INT_LVL_BIT_1_RANGE                    1:1
+#define GPIO_MSK_INT_LVL_BIT_1_WOFFSET                  0x0
+#define GPIO_MSK_INT_LVL_BIT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_BIT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_1_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_BIT_1_HIGH                     _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_BIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_LVL_BIT_0_FIELD                    (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_BIT_0_SHIFT)
+#define GPIO_MSK_INT_LVL_BIT_0_RANGE                    0:0
+#define GPIO_MSK_INT_LVL_BIT_0_WOFFSET                  0x0
+#define GPIO_MSK_INT_LVL_BIT_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_BIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_BIT_0_LOW                      _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_BIT_0_HIGH                     _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_LVL_1  
+#define GPIO_MSK_INT_LVL_1                      _MK_ADDR_CONST(0x864)
+#define GPIO_MSK_INT_LVL_1_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_LVL_1_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_LVL_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_LVL_1_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_1_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_LVL_1_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_MSK7_SHIFT)
+#define GPIO_MSK_INT_LVL_1_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_LVL_1_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_1_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_1_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_LVL_1_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_MSK6_SHIFT)
+#define GPIO_MSK_INT_LVL_1_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_LVL_1_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_1_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_1_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_LVL_1_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_MSK5_SHIFT)
+#define GPIO_MSK_INT_LVL_1_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_LVL_1_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_1_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_1_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_LVL_1_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_MSK4_SHIFT)
+#define GPIO_MSK_INT_LVL_1_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_LVL_1_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_1_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_1_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_LVL_1_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_MSK3_SHIFT)
+#define GPIO_MSK_INT_LVL_1_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_LVL_1_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_1_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_1_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_LVL_1_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_MSK2_SHIFT)
+#define GPIO_MSK_INT_LVL_1_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_LVL_1_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_1_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_1_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_LVL_1_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_MSK1_SHIFT)
+#define GPIO_MSK_INT_LVL_1_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_LVL_1_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_1_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_1_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_LVL_1_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_MSK0_SHIFT)
+#define GPIO_MSK_INT_LVL_1_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_LVL_1_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_1_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_1_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_LVL_1_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_BIT_7_SHIFT)
+#define GPIO_MSK_INT_LVL_1_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_LVL_1_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_1_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_7_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_BIT_7_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_1_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_LVL_1_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_BIT_6_SHIFT)
+#define GPIO_MSK_INT_LVL_1_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_LVL_1_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_1_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_6_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_BIT_6_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_1_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_LVL_1_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_BIT_5_SHIFT)
+#define GPIO_MSK_INT_LVL_1_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_LVL_1_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_1_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_5_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_BIT_5_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_1_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_LVL_1_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_BIT_4_SHIFT)
+#define GPIO_MSK_INT_LVL_1_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_LVL_1_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_1_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_4_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_BIT_4_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_1_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_LVL_1_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_BIT_3_SHIFT)
+#define GPIO_MSK_INT_LVL_1_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_LVL_1_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_1_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_3_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_BIT_3_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_1_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_LVL_1_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_BIT_2_SHIFT)
+#define GPIO_MSK_INT_LVL_1_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_LVL_1_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_1_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_2_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_BIT_2_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_1_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_LVL_1_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_BIT_1_SHIFT)
+#define GPIO_MSK_INT_LVL_1_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_LVL_1_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_1_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_1_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_BIT_1_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_1_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_LVL_1_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_1_BIT_0_SHIFT)
+#define GPIO_MSK_INT_LVL_1_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_LVL_1_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_1_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_1_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_1_BIT_0_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_1_BIT_0_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_LVL_2  
+#define GPIO_MSK_INT_LVL_2                      _MK_ADDR_CONST(0x868)
+#define GPIO_MSK_INT_LVL_2_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_LVL_2_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_LVL_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_LVL_2_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_2_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_LVL_2_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_MSK7_SHIFT)
+#define GPIO_MSK_INT_LVL_2_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_LVL_2_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_2_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_2_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_LVL_2_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_MSK6_SHIFT)
+#define GPIO_MSK_INT_LVL_2_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_LVL_2_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_2_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_2_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_LVL_2_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_MSK5_SHIFT)
+#define GPIO_MSK_INT_LVL_2_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_LVL_2_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_2_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_2_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_LVL_2_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_MSK4_SHIFT)
+#define GPIO_MSK_INT_LVL_2_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_LVL_2_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_2_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_2_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_LVL_2_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_MSK3_SHIFT)
+#define GPIO_MSK_INT_LVL_2_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_LVL_2_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_2_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_2_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_LVL_2_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_MSK2_SHIFT)
+#define GPIO_MSK_INT_LVL_2_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_LVL_2_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_2_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_2_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_LVL_2_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_MSK1_SHIFT)
+#define GPIO_MSK_INT_LVL_2_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_LVL_2_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_2_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_2_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_LVL_2_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_MSK0_SHIFT)
+#define GPIO_MSK_INT_LVL_2_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_LVL_2_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_2_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_2_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_LVL_2_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_BIT_7_SHIFT)
+#define GPIO_MSK_INT_LVL_2_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_LVL_2_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_2_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_7_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_BIT_7_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_2_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_LVL_2_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_BIT_6_SHIFT)
+#define GPIO_MSK_INT_LVL_2_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_LVL_2_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_2_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_6_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_BIT_6_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_2_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_LVL_2_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_BIT_5_SHIFT)
+#define GPIO_MSK_INT_LVL_2_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_LVL_2_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_2_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_5_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_BIT_5_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_2_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_LVL_2_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_BIT_4_SHIFT)
+#define GPIO_MSK_INT_LVL_2_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_LVL_2_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_2_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_4_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_BIT_4_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_2_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_LVL_2_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_BIT_3_SHIFT)
+#define GPIO_MSK_INT_LVL_2_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_LVL_2_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_2_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_3_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_BIT_3_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_2_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_LVL_2_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_BIT_2_SHIFT)
+#define GPIO_MSK_INT_LVL_2_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_LVL_2_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_2_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_2_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_BIT_2_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_2_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_LVL_2_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_BIT_1_SHIFT)
+#define GPIO_MSK_INT_LVL_2_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_LVL_2_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_2_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_1_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_BIT_1_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_2_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_LVL_2_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_2_BIT_0_SHIFT)
+#define GPIO_MSK_INT_LVL_2_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_LVL_2_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_2_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_2_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_2_BIT_0_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_2_BIT_0_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register GPIO_MSK_INT_LVL_3  
+#define GPIO_MSK_INT_LVL_3                      _MK_ADDR_CONST(0x86c)
+#define GPIO_MSK_INT_LVL_3_WORD_COUNT                   0x1
+#define GPIO_MSK_INT_LVL_3_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define GPIO_MSK_INT_LVL_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_READ_MASK                    _MK_MASK_CONST(0xff)
+#define GPIO_MSK_INT_LVL_3_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_3_MSK7_SHIFT                   _MK_SHIFT_CONST(15)
+#define GPIO_MSK_INT_LVL_3_MSK7_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_MSK7_SHIFT)
+#define GPIO_MSK_INT_LVL_3_MSK7_RANGE                   15:15
+#define GPIO_MSK_INT_LVL_3_MSK7_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_3_MSK7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_MSK7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK7_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_MSK7_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_3_MSK6_SHIFT                   _MK_SHIFT_CONST(14)
+#define GPIO_MSK_INT_LVL_3_MSK6_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_MSK6_SHIFT)
+#define GPIO_MSK_INT_LVL_3_MSK6_RANGE                   14:14
+#define GPIO_MSK_INT_LVL_3_MSK6_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_3_MSK6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_MSK6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK6_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_MSK6_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_3_MSK5_SHIFT                   _MK_SHIFT_CONST(13)
+#define GPIO_MSK_INT_LVL_3_MSK5_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_MSK5_SHIFT)
+#define GPIO_MSK_INT_LVL_3_MSK5_RANGE                   13:13
+#define GPIO_MSK_INT_LVL_3_MSK5_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_3_MSK5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_MSK5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK5_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_MSK5_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_3_MSK4_SHIFT                   _MK_SHIFT_CONST(12)
+#define GPIO_MSK_INT_LVL_3_MSK4_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_MSK4_SHIFT)
+#define GPIO_MSK_INT_LVL_3_MSK4_RANGE                   12:12
+#define GPIO_MSK_INT_LVL_3_MSK4_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_3_MSK4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_MSK4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK4_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_MSK4_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_3_MSK3_SHIFT                   _MK_SHIFT_CONST(11)
+#define GPIO_MSK_INT_LVL_3_MSK3_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_MSK3_SHIFT)
+#define GPIO_MSK_INT_LVL_3_MSK3_RANGE                   11:11
+#define GPIO_MSK_INT_LVL_3_MSK3_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_3_MSK3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_MSK3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK3_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_MSK3_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_3_MSK2_SHIFT                   _MK_SHIFT_CONST(10)
+#define GPIO_MSK_INT_LVL_3_MSK2_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_MSK2_SHIFT)
+#define GPIO_MSK_INT_LVL_3_MSK2_RANGE                   10:10
+#define GPIO_MSK_INT_LVL_3_MSK2_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_3_MSK2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_MSK2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK2_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_MSK2_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_3_MSK1_SHIFT                   _MK_SHIFT_CONST(9)
+#define GPIO_MSK_INT_LVL_3_MSK1_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_MSK1_SHIFT)
+#define GPIO_MSK_INT_LVL_3_MSK1_RANGE                   9:9
+#define GPIO_MSK_INT_LVL_3_MSK1_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_3_MSK1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_MSK1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK1_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_MSK1_ENABLE                  _MK_ENUM_CONST(1)
+
+//  0=Disable bit for write 
+#define GPIO_MSK_INT_LVL_3_MSK0_SHIFT                   _MK_SHIFT_CONST(8)
+#define GPIO_MSK_INT_LVL_3_MSK0_FIELD                   (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_MSK0_SHIFT)
+#define GPIO_MSK_INT_LVL_3_MSK0_RANGE                   8:8
+#define GPIO_MSK_INT_LVL_3_MSK0_WOFFSET                 0x0
+#define GPIO_MSK_INT_LVL_3_MSK0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_MSK0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_MSK0_DISABLE                 _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_MSK0_ENABLE                  _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_3_BIT_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define GPIO_MSK_INT_LVL_3_BIT_7_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_BIT_7_SHIFT)
+#define GPIO_MSK_INT_LVL_3_BIT_7_RANGE                  7:7
+#define GPIO_MSK_INT_LVL_3_BIT_7_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_3_BIT_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_BIT_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_7_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_BIT_7_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_3_BIT_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define GPIO_MSK_INT_LVL_3_BIT_6_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_BIT_6_SHIFT)
+#define GPIO_MSK_INT_LVL_3_BIT_6_RANGE                  6:6
+#define GPIO_MSK_INT_LVL_3_BIT_6_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_3_BIT_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_BIT_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_6_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_BIT_6_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_3_BIT_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define GPIO_MSK_INT_LVL_3_BIT_5_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_BIT_5_SHIFT)
+#define GPIO_MSK_INT_LVL_3_BIT_5_RANGE                  5:5
+#define GPIO_MSK_INT_LVL_3_BIT_5_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_3_BIT_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_BIT_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_5_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_BIT_5_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_3_BIT_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define GPIO_MSK_INT_LVL_3_BIT_4_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_BIT_4_SHIFT)
+#define GPIO_MSK_INT_LVL_3_BIT_4_RANGE                  4:4
+#define GPIO_MSK_INT_LVL_3_BIT_4_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_3_BIT_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_BIT_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_4_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_BIT_4_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_3_BIT_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define GPIO_MSK_INT_LVL_3_BIT_3_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_BIT_3_SHIFT)
+#define GPIO_MSK_INT_LVL_3_BIT_3_RANGE                  3:3
+#define GPIO_MSK_INT_LVL_3_BIT_3_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_3_BIT_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_BIT_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_3_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_BIT_3_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_3_BIT_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define GPIO_MSK_INT_LVL_3_BIT_2_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_BIT_2_SHIFT)
+#define GPIO_MSK_INT_LVL_3_BIT_2_RANGE                  2:2
+#define GPIO_MSK_INT_LVL_3_BIT_2_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_3_BIT_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_BIT_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_2_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_BIT_2_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_3_BIT_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define GPIO_MSK_INT_LVL_3_BIT_1_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_BIT_1_SHIFT)
+#define GPIO_MSK_INT_LVL_3_BIT_1_RANGE                  1:1
+#define GPIO_MSK_INT_LVL_3_BIT_1_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_3_BIT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_BIT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_1_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_BIT_1_HIGH                   _MK_ENUM_CONST(1)
+
+// 
+#define GPIO_MSK_INT_LVL_3_BIT_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define GPIO_MSK_INT_LVL_3_BIT_0_FIELD                  (_MK_MASK_CONST(0x1) << GPIO_MSK_INT_LVL_3_BIT_0_SHIFT)
+#define GPIO_MSK_INT_LVL_3_BIT_0_RANGE                  0:0
+#define GPIO_MSK_INT_LVL_3_BIT_0_WOFFSET                        0x0
+#define GPIO_MSK_INT_LVL_3_BIT_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define GPIO_MSK_INT_LVL_3_BIT_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define GPIO_MSK_INT_LVL_3_BIT_0_LOW                    _MK_ENUM_CONST(0)
+#define GPIO_MSK_INT_LVL_3_BIT_0_HIGH                   _MK_ENUM_CONST(1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARGPIO_REGS(_op_) \
+_op_(GPIO_CNF_0) \
+_op_(GPIO_CNF) \
+_op_(GPIO_CNF_1) \
+_op_(GPIO_CNF_2) \
+_op_(GPIO_CNF_3) \
+_op_(GPIO_OE_0) \
+_op_(GPIO_OE) \
+_op_(GPIO_OE_1) \
+_op_(GPIO_OE_2) \
+_op_(GPIO_OE_3) \
+_op_(GPIO_OUT_0) \
+_op_(GPIO_OUT) \
+_op_(GPIO_OUT_1) \
+_op_(GPIO_OUT_2) \
+_op_(GPIO_OUT_3) \
+_op_(GPIO_IN_0) \
+_op_(GPIO_IN) \
+_op_(GPIO_IN_1) \
+_op_(GPIO_IN_2) \
+_op_(GPIO_IN_3) \
+_op_(GPIO_INT_STA_0) \
+_op_(GPIO_INT_STA) \
+_op_(GPIO_INT_STA_1) \
+_op_(GPIO_INT_STA_2) \
+_op_(GPIO_INT_STA_3) \
+_op_(GPIO_INT_ENB_0) \
+_op_(GPIO_INT_ENB) \
+_op_(GPIO_INT_ENB_1) \
+_op_(GPIO_INT_ENB_2) \
+_op_(GPIO_INT_ENB_3) \
+_op_(GPIO_INT_LVL_0) \
+_op_(GPIO_INT_LVL) \
+_op_(GPIO_INT_LVL_1) \
+_op_(GPIO_INT_LVL_2) \
+_op_(GPIO_INT_LVL_3) \
+_op_(GPIO_INT_CLR_0) \
+_op_(GPIO_INT_CLR) \
+_op_(GPIO_INT_CLR_1) \
+_op_(GPIO_INT_CLR_2) \
+_op_(GPIO_INT_CLR_3) \
+_op_(GPIO_MSK_CNF_0) \
+_op_(GPIO_MSK_CNF) \
+_op_(GPIO_MSK_CNF_1) \
+_op_(GPIO_MSK_CNF_2) \
+_op_(GPIO_MSK_CNF_3) \
+_op_(GPIO_MSK_OE_0) \
+_op_(GPIO_MSK_OE) \
+_op_(GPIO_MSK_OE_1) \
+_op_(GPIO_MSK_OE_2) \
+_op_(GPIO_MSK_OE_3) \
+_op_(GPIO_MSK_OUT_0) \
+_op_(GPIO_MSK_OUT) \
+_op_(GPIO_MSK_OUT_1) \
+_op_(GPIO_MSK_OUT_2) \
+_op_(GPIO_MSK_OUT_3) \
+_op_(GPIO_MSK_INT_STA_0) \
+_op_(GPIO_MSK_INT_STA) \
+_op_(GPIO_MSK_INT_STA_1) \
+_op_(GPIO_MSK_INT_STA_2) \
+_op_(GPIO_MSK_INT_STA_3) \
+_op_(GPIO_MSK_INT_ENB_0) \
+_op_(GPIO_MSK_INT_ENB) \
+_op_(GPIO_MSK_INT_ENB_1) \
+_op_(GPIO_MSK_INT_ENB_2) \
+_op_(GPIO_MSK_INT_ENB_3) \
+_op_(GPIO_MSK_INT_LVL_0) \
+_op_(GPIO_MSK_INT_LVL) \
+_op_(GPIO_MSK_INT_LVL_1) \
+_op_(GPIO_MSK_INT_LVL_2) \
+_op_(GPIO_MSK_INT_LVL_3)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_GPIO       0x00000000
+
+//
+// ARGPIO REGISTER BANKS
+//
+
+#define GPIO0_FIRST_REG 0x0000 // GPIO_CNF_0
+#define GPIO0_LAST_REG 0x007c // GPIO_INT_CLR_3
+#define GPIO1_FIRST_REG 0x0800 // GPIO_MSK_CNF_0
+#define GPIO1_LAST_REG 0x082c // GPIO_MSK_OUT_3
+#define GPIO2_FIRST_REG 0x0840 // GPIO_MSK_INT_STA_0
+#define GPIO2_LAST_REG 0x086c // GPIO_MSK_INT_LVL_3
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARGPIO_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/ari2c.h b/arch/arm/mach-tegra/nv/include/ap15/ari2c.h
new file mode 100644
index 000000000000..335639f1cc99
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/ari2c.h
@@ -0,0 +1,789 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARI2C_H_INC_
+#define ___ARI2C_H_INC_
+////////////////////////////////////////////////////////////////////////////////////////
+//
+// NOTE: 
+// ----- 
+// The FREQUENCY DIVISOR register (CLK_SOURCE_I2C register) must be programmed as a
+// function of the CLK_SOURCE Selected for I2C as follows:
+// I2C_CLK =  CLK_SOURCE.I2C / ( 8 *  I2C FREQUENCY DIVISOR)
+// The I2C bus specification defines the minimum low period for the I2C_CLK as 4.7 s in standard mode 
+// and 1.3 s in fast mode. Because of this, the maximum I2C_CLK frequency in the 
+// standard mode can be 100 KHz but in fast mode, it is limited to 348 KHz, assuming I2C_CLK as rise and
+// fall delays of 300ns per the I2C specification.
+// The clock enable (bit-12 of CLK_OUT_ENB.L register)
+// must also be given to I2C controller, before any of the registers are written.
+//
+////////////////////////////////////////////////////////////////////////////////////////
+//IC Controller Configuration Register  (Master)
+//I2C_CNFG register is used to configure,
+//The number of bytes to be transmitted or received,
+//the slave device type either a 7-bit device or a 10-bit device,
+//Enable mode to send Start-Byte or not,
+//to select either a single slave transaction or two slave transaction,
+//Enable mode to handle devices that do not generate  ACK.
+
+// Register I2C_I2C_CNFG_0  
+#define I2C_I2C_CNFG_0                  _MK_ADDR_CONST(0x0)
+#define I2C_I2C_CNFG_0_WORD_COUNT                       0x1
+#define I2C_I2C_CNFG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CNFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CNFG_0_WRITE_MASK                       _MK_MASK_CONST(0x3ff)
+// Reserved = 0
+#define I2C_I2C_CNFG_0_N_A1_SHIFT                       _MK_SHIFT_CONST(10)
+#define I2C_I2C_CNFG_0_N_A1_FIELD                       (_MK_MASK_CONST(0x3fffff) << I2C_I2C_CNFG_0_N_A1_SHIFT)
+#define I2C_I2C_CNFG_0_N_A1_RANGE                       31:10
+#define I2C_I2C_CNFG_0_N_A1_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_N_A1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_N_A1_DEFAULT_MASK                        _MK_MASK_CONST(0x3fffff)
+#define I2C_I2C_CNFG_0_N_A1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_N_A1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Writing a 1 causes the master to initiate the
+// transaction. Values of other  bits are not
+// affected when this bit is 1,Cleared by 
+// hardware.  Other bits of the register are
+// masked for writes when this bit is programmed
+// to one.hence,firware should first configure
+// all other registrs and  bits [8:0] of 
+// I2C_CNFG register before the bit I2C_CNFG[9] is programmed to one..
+#define I2C_I2C_CNFG_0_SEND_SHIFT                       _MK_SHIFT_CONST(9)
+#define I2C_I2C_CNFG_0_SEND_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_SEND_SHIFT)
+#define I2C_I2C_CNFG_0_SEND_RANGE                       9:9
+#define I2C_I2C_CNFG_0_SEND_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_SEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_SEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_NOP                 _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_SEND_GO                  _MK_ENUM_CONST(1)
+
+// Enable mode to handle devices that do not generate ACK. 
+// 1 - dont look for an ack at the end of the transaction.
+#define I2C_I2C_CNFG_0_NOACK_SHIFT                      _MK_SHIFT_CONST(8)
+#define I2C_I2C_CNFG_0_NOACK_FIELD                      (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_NOACK_SHIFT)
+#define I2C_I2C_CNFG_0_NOACK_RANGE                      8:8
+#define I2C_I2C_CNFG_0_NOACK_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_NOACK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_NOACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_DISABLE                    _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_NOACK_ENABLE                     _MK_ENUM_CONST(1)
+
+// Read/Write Command for Slave 2:
+// 1 -  Read Transaction;
+// 0 -  write Transaction.
+// For a 7-bit slave address,this bit must match
+// with the LSB of address byte for slave 2.
+// Valid only when  bit-4 (SLV2) of this register is 
+// set
+#define I2C_I2C_CNFG_0_CMD2_SHIFT                       _MK_SHIFT_CONST(7)
+#define I2C_I2C_CNFG_0_CMD2_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_CMD2_SHIFT)
+#define I2C_I2C_CNFG_0_CMD2_RANGE                       7:7
+#define I2C_I2C_CNFG_0_CMD2_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_CMD2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_CMD2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_CMD2_ENABLE                      _MK_ENUM_CONST(1)
+
+// Read/Write Command for Slave 1: 
+// 1 - Read Transaction;
+// 0 -  write Transaction.
+// Command for Slave 1: For a 7-bit slave address
+// this bit must match with the LSB of address 
+// byte for slave2.
+#define I2C_I2C_CNFG_0_CMD1_SHIFT                       _MK_SHIFT_CONST(6)
+#define I2C_I2C_CNFG_0_CMD1_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_CMD1_SHIFT)
+#define I2C_I2C_CNFG_0_CMD1_RANGE                       6:6
+#define I2C_I2C_CNFG_0_CMD1_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_CMD1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_CMD1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_CMD1_ENABLE                      _MK_ENUM_CONST(1)
+
+// 1 = Yes, a Start byte needs to be  sent.
+#define I2C_I2C_CNFG_0_START_SHIFT                      _MK_SHIFT_CONST(5)
+#define I2C_I2C_CNFG_0_START_FIELD                      (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_START_SHIFT)
+#define I2C_I2C_CNFG_0_START_RANGE                      5:5
+#define I2C_I2C_CNFG_0_START_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_DISABLE                    _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_START_ENABLE                     _MK_ENUM_CONST(1)
+
+// 1 - Enables a two slave transaction;
+// 0 = No command for Slave 2 present.
+#define I2C_I2C_CNFG_0_SLV2_SHIFT                       _MK_SHIFT_CONST(4)
+#define I2C_I2C_CNFG_0_SLV2_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_SLV2_SHIFT)
+#define I2C_I2C_CNFG_0_SLV2_RANGE                       4:4
+#define I2C_I2C_CNFG_0_SLV2_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_SLV2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_SLV2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_SLV2_ENABLE                      _MK_ENUM_CONST(1)
+
+// The Number of bytes to be transmitted per
+// transaction 000= 1byte ... 111 = 8bytes;
+// In a two slave transaction number of bytes
+// should be programmed less than 011. 
+#define I2C_I2C_CNFG_0_LENGTH_SHIFT                     _MK_SHIFT_CONST(1)
+#define I2C_I2C_CNFG_0_LENGTH_FIELD                     (_MK_MASK_CONST(0x7) << I2C_I2C_CNFG_0_LENGTH_SHIFT)
+#define I2C_I2C_CNFG_0_LENGTH_RANGE                     3:1
+#define I2C_I2C_CNFG_0_LENGTH_WOFFSET                   0x0
+#define I2C_I2C_CNFG_0_LENGTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_LENGTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define I2C_I2C_CNFG_0_LENGTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_LENGTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Address mode defines whether a 7-bit or a 
+// 10-bit slave address is programmed.
+// 1 = 10-bit device address 
+// 0 = 7-bit device address
+#define I2C_I2C_CNFG_0_A_MOD_SHIFT                      _MK_SHIFT_CONST(0)
+#define I2C_I2C_CNFG_0_A_MOD_FIELD                      (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_A_MOD_SHIFT)
+#define I2C_I2C_CNFG_0_A_MOD_RANGE                      0:0
+#define I2C_I2C_CNFG_0_A_MOD_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_A_MOD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_A_MOD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_SEVEN_BIT_DEVICE_ADDRESS                   _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_A_MOD_TEN_BIT_DEVICE_ADDRESS                     _MK_ENUM_CONST(1)
+
+//I2C Slave-1 Address 
+//I2C_CMD_ADDR0 is programmed the 7 Bit or 10 Bit address of slave 1 with which the transaction is intended; 
+
+// Register I2C_I2C_CMD_ADDR0_0  
+#define I2C_I2C_CMD_ADDR0_0                     _MK_ADDR_CONST(0x4)
+#define I2C_I2C_CMD_ADDR0_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_ADDR0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_ADDR0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_ADDR0_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+// Reserved = 0
+#define I2C_I2C_CMD_ADDR0_0_N_A2_SHIFT                  _MK_SHIFT_CONST(10)
+#define I2C_I2C_CMD_ADDR0_0_N_A2_FIELD                  (_MK_MASK_CONST(0x3fffff) << I2C_I2C_CMD_ADDR0_0_N_A2_SHIFT)
+#define I2C_I2C_CMD_ADDR0_0_N_A2_RANGE                  31:10
+#define I2C_I2C_CMD_ADDR0_0_N_A2_WOFFSET                        0x0
+#define I2C_I2C_CMD_ADDR0_0_N_A2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_N_A2_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffff)
+#define I2C_I2C_CMD_ADDR0_0_N_A2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_N_A2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// In case of 7-Bit mode address is written in the 
+// I2C_CMD_ADDR0[7:1] and I2C_CMD_ADDR0[0] indicates the
+// read/write transaction.I2C_CMD_ADDR0[0] bit must match 
+// with the I2C_CNFG[6].   
+// In case of 10-Bit mode addess is written in 
+// I2C_CMD_ADDR0[9:0] and I2C_CNFG[6]  indicates the 
+// read/write transaction.                                     
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_FIELD                 (_MK_MASK_CONST(0x3ff) << I2C_I2C_CMD_ADDR0_0_ADDR0_SHIFT)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_RANGE                 9:0
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_WOFFSET                       0x0
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//I2C Slave-2 Address
+//I2C_CMD_ADDR1 is programmed the 7 Bit or 10 Bit address of slave 2 with which the transaction is intended;
+
+// Register I2C_I2C_CMD_ADDR1_0  
+#define I2C_I2C_CMD_ADDR1_0                     _MK_ADDR_CONST(0x8)
+#define I2C_I2C_CMD_ADDR1_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_ADDR1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_ADDR1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_ADDR1_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+// Reserved = 0
+#define I2C_I2C_CMD_ADDR1_0_N_A3_SHIFT                  _MK_SHIFT_CONST(10)
+#define I2C_I2C_CMD_ADDR1_0_N_A3_FIELD                  (_MK_MASK_CONST(0x3fffff) << I2C_I2C_CMD_ADDR1_0_N_A3_SHIFT)
+#define I2C_I2C_CMD_ADDR1_0_N_A3_RANGE                  31:10
+#define I2C_I2C_CMD_ADDR1_0_N_A3_WOFFSET                        0x0
+#define I2C_I2C_CMD_ADDR1_0_N_A3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_N_A3_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffff)
+#define I2C_I2C_CMD_ADDR1_0_N_A3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_N_A3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// In case of 7-Bit mode address is written in the 
+// I2C_CMD_ADDR0[7:1] and I2C_CMD_ADDR0[0] indicates the 
+// read/write transaction.I2C_CMD_ADDR0[0] bit must match 
+// with the I2C_CNFG[7].
+// In case of 10-Bit mode addess is written in 
+// I2C_CMD_ADDR0[9:0] and I2C_CNFG[7] indicates the 
+// read/write transaction.
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_FIELD                 (_MK_MASK_CONST(0x3ff) << I2C_I2C_CMD_ADDR1_0_ADDR1_SHIFT)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_RANGE                 9:0
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_WOFFSET                       0x0
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//IC Controller Data 1: Transmit/Receive
+//The four Least Significant Bytes of Data to be Transamitted is loaded into the register when I2c Master 
+//is in Write Mode;
+//The four Least Significant Bytes of Data are Read through this register when I2c Master is in Read mode.               
+
+// Register I2C_I2C_CMD_DATA1_0  
+#define I2C_I2C_CMD_DATA1_0                     _MK_ADDR_CONST(0xc)
+#define I2C_I2C_CMD_DATA1_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_DATA1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Fourth data byte to be sent/received
+#define I2C_I2C_CMD_DATA1_0_DATA4_SHIFT                 _MK_SHIFT_CONST(24)
+#define I2C_I2C_CMD_DATA1_0_DATA4_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA4_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA4_RANGE                 31:24
+#define I2C_I2C_CMD_DATA1_0_DATA4_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Third data byte to be sent/received
+#define I2C_I2C_CMD_DATA1_0_DATA3_SHIFT                 _MK_SHIFT_CONST(16)
+#define I2C_I2C_CMD_DATA1_0_DATA3_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA3_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA3_RANGE                 23:16
+#define I2C_I2C_CMD_DATA1_0_DATA3_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Second data byte to be sent/received
+#define I2C_I2C_CMD_DATA1_0_DATA2_SHIFT                 _MK_SHIFT_CONST(8)
+#define I2C_I2C_CMD_DATA1_0_DATA2_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA2_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA2_RANGE                 15:8
+#define I2C_I2C_CMD_DATA1_0_DATA2_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This register contains the first data byte to be  sent/received.
+#define I2C_I2C_CMD_DATA1_0_DATA1_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA1_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA1_RANGE                 7:0
+#define I2C_I2C_CMD_DATA1_0_DATA1_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//IC Controller Data 2: Transmit/Receive
+//The four Most Significant Bytes of Data to be Transamitted is loaded into the register when I2c Master is in Write Mode;
+//The four Most Significant Bytes of Data are Read through this register when I2c Master is in Read mode.
+
+// Register I2C_I2C_CMD_DATA2_0  
+#define I2C_I2C_CMD_DATA2_0                     _MK_ADDR_CONST(0x10)
+#define I2C_I2C_CMD_DATA2_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_DATA2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Eighth data byte to be sent/received
+#define I2C_I2C_CMD_DATA2_0_DATA8_SHIFT                 _MK_SHIFT_CONST(24)
+#define I2C_I2C_CMD_DATA2_0_DATA8_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA8_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA8_RANGE                 31:24
+#define I2C_I2C_CMD_DATA2_0_DATA8_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA8_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Seventh data byte to be sent/received
+#define I2C_I2C_CMD_DATA2_0_DATA7_SHIFT                 _MK_SHIFT_CONST(16)
+#define I2C_I2C_CMD_DATA2_0_DATA7_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA7_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA7_RANGE                 23:16
+#define I2C_I2C_CMD_DATA2_0_DATA7_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA7_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sixth data byte to be sent/received
+#define I2C_I2C_CMD_DATA2_0_DATA6_SHIFT                 _MK_SHIFT_CONST(8)
+#define I2C_I2C_CMD_DATA2_0_DATA6_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA6_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA6_RANGE                 15:8
+#define I2C_I2C_CMD_DATA2_0_DATA6_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This register contains the Fifth data byte to be  sent/received.
+#define I2C_I2C_CMD_DATA2_0_DATA5_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA5_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA5_RANGE                 7:0
+#define I2C_I2C_CMD_DATA2_0_DATA5_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+//IC Controller Status (Master)
+//I2C_STATUS gives the status of I2c Master operation
+
+// Register I2C_I2C_STATUS_0  
+#define I2C_I2C_STATUS_0                        _MK_ADDR_CONST(0x1c)
+#define I2C_I2C_STATUS_0_WORD_COUNT                     0x1
+#define I2C_I2C_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Reserved = 0
+#define I2C_I2C_STATUS_0_N_A4_SHIFT                     _MK_SHIFT_CONST(9)
+#define I2C_I2C_STATUS_0_N_A4_FIELD                     (_MK_MASK_CONST(0x7fffff) << I2C_I2C_STATUS_0_N_A4_SHIFT)
+#define I2C_I2C_STATUS_0_N_A4_RANGE                     31:9
+#define I2C_I2C_STATUS_0_N_A4_WOFFSET                   0x0
+#define I2C_I2C_STATUS_0_N_A4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_N_A4_DEFAULT_MASK                      _MK_MASK_CONST(0x7fffff)
+#define I2C_I2C_STATUS_0_N_A4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_N_A4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1 = Bus Busy.
+#define I2C_I2C_STATUS_0_BUSY_SHIFT                     _MK_SHIFT_CONST(8)
+#define I2C_I2C_STATUS_0_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << I2C_I2C_STATUS_0_BUSY_SHIFT)
+#define I2C_I2C_STATUS_0_BUSY_RANGE                     8:8
+#define I2C_I2C_STATUS_0_BUSY_WOFFSET                   0x0
+#define I2C_I2C_STATUS_0_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_I2C_STATUS_0_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_BUSY_BUSY                      _MK_ENUM_CONST(1)
+
+// Transaction for Slave2 for x byte failed. x is 'h0 to 'ha.
+// all others invalid
+#define I2C_I2C_STATUS_0_CMD2_STAT_SHIFT                        _MK_SHIFT_CONST(4)
+#define I2C_I2C_STATUS_0_CMD2_STAT_FIELD                        (_MK_MASK_CONST(0xf) << I2C_I2C_STATUS_0_CMD2_STAT_SHIFT)
+#define I2C_I2C_STATUS_0_CMD2_STAT_RANGE                        7:4
+#define I2C_I2C_STATUS_0_CMD2_STAT_WOFFSET                      0x0
+#define I2C_I2C_STATUS_0_CMD2_STAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_XFER_SUCCESSFUL                  _MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE1                  _MK_ENUM_CONST(1)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE2                  _MK_ENUM_CONST(2)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE3                  _MK_ENUM_CONST(3)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE4                  _MK_ENUM_CONST(4)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE5                  _MK_ENUM_CONST(5)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE6                  _MK_ENUM_CONST(6)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE7                  _MK_ENUM_CONST(7)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE8                  _MK_ENUM_CONST(8)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE9                  _MK_ENUM_CONST(9)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE10                 _MK_ENUM_CONST(10)
+
+// Transaction for Slave1 for x byte failed. x is 'h0 to 'ha
+// all others invalid
+#define I2C_I2C_STATUS_0_CMD1_STAT_SHIFT                        _MK_SHIFT_CONST(0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_FIELD                        (_MK_MASK_CONST(0xf) << I2C_I2C_STATUS_0_CMD1_STAT_SHIFT)
+#define I2C_I2C_STATUS_0_CMD1_STAT_RANGE                        3:0
+#define I2C_I2C_STATUS_0_CMD1_STAT_WOFFSET                      0x0
+#define I2C_I2C_STATUS_0_CMD1_STAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_XFER_SUCCESSFUL                  _MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE1                  _MK_ENUM_CONST(1)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE2                  _MK_ENUM_CONST(2)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE3                  _MK_ENUM_CONST(3)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE4                  _MK_ENUM_CONST(4)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE5                  _MK_ENUM_CONST(5)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE6                  _MK_ENUM_CONST(6)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE7                  _MK_ENUM_CONST(7)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE8                  _MK_ENUM_CONST(8)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE9                  _MK_ENUM_CONST(9)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE10                 _MK_ENUM_CONST(10)
+
+//IC Controller Configuration (Slave)
+//I2C_SL_CNFG register is used to configure,
+//Enable mode of slave Ack,
+//Enable mode of slave response to general call address.
+//The register should be programmed when I2c controller is configured as slave.  
+
+// Register I2C_I2C_SL_CNFG_0  
+#define I2C_I2C_SL_CNFG_0                       _MK_ADDR_CONST(0x20)
+#define I2C_I2C_SL_CNFG_0_WORD_COUNT                    0x1
+#define I2C_I2C_SL_CNFG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_CNFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_CNFG_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+// Reserved = 0
+#define I2C_I2C_SL_CNFG_0_N_A5_SHIFT                    _MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_CNFG_0_N_A5_FIELD                    (_MK_MASK_CONST(0x3fffffff) << I2C_I2C_SL_CNFG_0_N_A5_SHIFT)
+#define I2C_I2C_SL_CNFG_0_N_A5_RANGE                    31:2
+#define I2C_I2C_SL_CNFG_0_N_A5_WOFFSET                  0x0
+#define I2C_I2C_SL_CNFG_0_N_A5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_N_A5_DEFAULT_MASK                     _MK_MASK_CONST(0x3fffffff)
+#define I2C_I2C_SL_CNFG_0_N_A5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_N_A5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Disable Slave Ack. when bit set to 1 slave will not ack
+// reception of address or data byte. 
+#define I2C_I2C_SL_CNFG_0_NACK_SHIFT                    _MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_CNFG_0_NACK_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_CNFG_0_NACK_SHIFT)
+#define I2C_I2C_SL_CNFG_0_NACK_RANGE                    1:1
+#define I2C_I2C_SL_CNFG_0_NACK_WOFFSET                  0x0
+#define I2C_I2C_SL_CNFG_0_NACK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_NACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_NACK_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable Slave response to general call address (zero 
+// address) when bit is set to 1.
+#define I2C_I2C_SL_CNFG_0_RESP_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_CNFG_0_RESP_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_CNFG_0_RESP_SHIFT)
+#define I2C_I2C_SL_CNFG_0_RESP_RANGE                    0:0
+#define I2C_I2C_SL_CNFG_0_RESP_WOFFSET                  0x0
+#define I2C_I2C_SL_CNFG_0_RESP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_RESP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_RESP_ENABLE                   _MK_ENUM_CONST(1)
+
+//IC Controller Slave Receive/Transmit Data (Slave)
+
+// Register I2C_I2C_SL_RCVD_0  
+#define I2C_I2C_SL_RCVD_0                       _MK_ADDR_CONST(0x24)
+#define I2C_I2C_SL_RCVD_0_WORD_COUNT                    0x1
+#define I2C_I2C_SL_RCVD_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_RCVD_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_RCVD_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+// Reserved = 0
+#define I2C_I2C_SL_RCVD_0_N_A6_SHIFT                    _MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_RCVD_0_N_A6_FIELD                    (_MK_MASK_CONST(0xffffff) << I2C_I2C_SL_RCVD_0_N_A6_SHIFT)
+#define I2C_I2C_SL_RCVD_0_N_A6_RANGE                    31:8
+#define I2C_I2C_SL_RCVD_0_N_A6_WOFFSET                  0x0
+#define I2C_I2C_SL_RCVD_0_N_A6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_N_A6_DEFAULT_MASK                     _MK_MASK_CONST(0xffffff)
+#define I2C_I2C_SL_RCVD_0_N_A6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_N_A6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//slave Received data 
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_SL_RCVD_0_SL_DATA_SHIFT)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_RANGE                 7:0
+#define I2C_I2C_SL_RCVD_0_SL_DATA_WOFFSET                       0x0
+#define I2C_I2C_SL_RCVD_0_SL_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//IC Controller Slave Status (Slave)
+
+// Register I2C_I2C_SL_STATUS_0  
+#define I2C_I2C_SL_STATUS_0                     _MK_ADDR_CONST(0x28)
+#define I2C_I2C_SL_STATUS_0_WORD_COUNT                  0x1
+#define I2C_I2C_SL_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Reserved = 0
+#define I2C_I2C_SL_STATUS_0_N_A7_SHIFT                  _MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_STATUS_0_N_A7_FIELD                  (_MK_MASK_CONST(0xfffffff) << I2C_I2C_SL_STATUS_0_N_A7_SHIFT)
+#define I2C_I2C_SL_STATUS_0_N_A7_RANGE                  31:4
+#define I2C_I2C_SL_STATUS_0_N_A7_WOFFSET                        0x0
+#define I2C_I2C_SL_STATUS_0_N_A7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_N_A7_DEFAULT_MASK                   _MK_MASK_CONST(0xfffffff)
+#define I2C_I2C_SL_STATUS_0_N_A7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_N_A7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 1 = Interrupt has been generated by  slave 
+// 0 = No interrupt generated  
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SHIFT                        _MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_FIELD                        (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_SL_IRQ_SHIFT)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_RANGE                        3:3
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_WOFFSET                      0x0
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_UNSET                        _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SET                  _MK_ENUM_CONST(1)
+
+// New Transaction Receieved status 
+// 1 = Transaction occurred
+// 0 = No transaction occurred 
+#define I2C_I2C_SL_STATUS_0_RCVD_SHIFT                  _MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_STATUS_0_RCVD_FIELD                  (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_RCVD_SHIFT)
+#define I2C_I2C_SL_STATUS_0_RCVD_RANGE                  2:2
+#define I2C_I2C_SL_STATUS_0_RCVD_WOFFSET                        0x0
+#define I2C_I2C_SL_STATUS_0_RCVD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RCVD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_NO_TRANSACTION_OCCURED                 _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_RCVD_TRANSACTION_OCCURED                    _MK_ENUM_CONST(1)
+
+// Slave Transaction status 0 = Write 1=Read
+#define I2C_I2C_SL_STATUS_0_RNW_SHIFT                   _MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_STATUS_0_RNW_FIELD                   (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_RNW_SHIFT)
+#define I2C_I2C_SL_STATUS_0_RNW_RANGE                   1:1
+#define I2C_I2C_SL_STATUS_0_RNW_WOFFSET                 0x0
+#define I2C_I2C_SL_STATUS_0_RNW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RNW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_WRITE                   _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_RNW_READ                    _MK_ENUM_CONST(1)
+
+// Zero Address Status 1 = Yes, slave responded  0  = No,
+// slave did not respond
+#define I2C_I2C_SL_STATUS_0_ZA_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_STATUS_0_ZA_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_ZA_SHIFT)
+#define I2C_I2C_SL_STATUS_0_ZA_RANGE                    0:0
+#define I2C_I2C_SL_STATUS_0_ZA_WOFFSET                  0x0
+#define I2C_I2C_SL_STATUS_0_ZA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_ZA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_NO_SLAVE_RESPONSE                        _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_ZA_SLAVE_RESPONSE                   _MK_ENUM_CONST(1)
+
+//IC Controller Slave Address 1 Register (Slave)
+
+// Register I2C_I2C_SL_ADDR1_0  
+#define I2C_I2C_SL_ADDR1_0                      _MK_ADDR_CONST(0x2c)
+#define I2C_I2C_SL_ADDR1_0_WORD_COUNT                   0x1
+#define I2C_I2C_SL_ADDR1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_ADDR1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_ADDR1_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// Reserved = 0
+#define I2C_I2C_SL_ADDR1_0_N_A8_SHIFT                   _MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_ADDR1_0_N_A8_FIELD                   (_MK_MASK_CONST(0xffffff) << I2C_I2C_SL_ADDR1_0_N_A8_SHIFT)
+#define I2C_I2C_SL_ADDR1_0_N_A8_RANGE                   31:8
+#define I2C_I2C_SL_ADDR1_0_N_A8_WOFFSET                 0x0
+#define I2C_I2C_SL_ADDR1_0_N_A8_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_N_A8_DEFAULT_MASK                    _MK_MASK_CONST(0xffffff)
+#define I2C_I2C_SL_ADDR1_0_N_A8_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_N_A8_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// For a 10-bit slave address, this field is the 
+// least significant 8 bits. 
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SHIFT                       _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_FIELD                       (_MK_MASK_CONST(0xff) << I2C_I2C_SL_ADDR1_0_SL_ADDR0_SHIFT)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_RANGE                       7:0
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_WOFFSET                     0x0
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//IC Controller Slave Address 2 Register (Slave)
+
+// Register I2C_I2C_SL_ADDR2_0  
+#define I2C_I2C_SL_ADDR2_0                      _MK_ADDR_CONST(0x30)
+#define I2C_I2C_SL_ADDR2_0_WORD_COUNT                   0x1
+#define I2C_I2C_SL_ADDR2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_ADDR2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_ADDR2_0_WRITE_MASK                   _MK_MASK_CONST(0x7)
+// Reserved = 0
+#define I2C_I2C_SL_ADDR2_0_N_A9_SHIFT                   _MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_ADDR2_0_N_A9_FIELD                   (_MK_MASK_CONST(0x1fffffff) << I2C_I2C_SL_ADDR2_0_N_A9_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_N_A9_RANGE                   31:3
+#define I2C_I2C_SL_ADDR2_0_N_A9_WOFFSET                 0x0
+#define I2C_I2C_SL_ADDR2_0_N_A9_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_N_A9_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define I2C_I2C_SL_ADDR2_0_N_A9_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_N_A9_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// In 7 bit address mode these bits are dont care;
+// In 10 bit address mode they represent the 2 MSB of the
+// address.
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SHIFT                     _MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_FIELD                     (_MK_MASK_CONST(0x3) << I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_RANGE                     2:1
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_WOFFSET                   0x0
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//0 = 7-bit addressing,                                                                                                 // 1 - 10 bit addressing
+#define I2C_I2C_SL_ADDR2_0_VLD_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_ADDR2_0_VLD_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_ADDR2_0_VLD_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_VLD_RANGE                    0:0
+#define I2C_I2C_SL_ADDR2_0_VLD_WOFFSET                  0x0
+#define I2C_I2C_SL_ADDR2_0_VLD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_ADDR2_0_VLD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_SEVEN_BIT_ADDR_MODE                      _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_ADDR2_0_VLD_TEN_BIT_ADDR_MODE                        _MK_ENUM_CONST(1)
+
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+//IC Slave Controller Delay Count
+
+// Register I2C_I2C_SL_DELAY_COUNT_0  
+#define I2C_I2C_SL_DELAY_COUNT_0                        _MK_ADDR_CONST(0x3c)
+#define I2C_I2C_SL_DELAY_COUNT_0_WORD_COUNT                     0x1
+#define I2C_I2C_SL_DELAY_COUNT_0_RESET_VAL                      _MK_MASK_CONST(0x1e)
+#define I2C_I2C_SL_DELAY_COUNT_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+// Reserved = 0
+#define I2C_I2C_SL_DELAY_COUNT_0_N_A10_SHIFT                    _MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_DELAY_COUNT_0_N_A10_FIELD                    (_MK_MASK_CONST(0xffffff) << I2C_I2C_SL_DELAY_COUNT_0_N_A10_SHIFT)
+#define I2C_I2C_SL_DELAY_COUNT_0_N_A10_RANGE                    31:8
+#define I2C_I2C_SL_DELAY_COUNT_0_N_A10_WOFFSET                  0x0
+#define I2C_I2C_SL_DELAY_COUNT_0_N_A10_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_N_A10_DEFAULT_MASK                     _MK_MASK_CONST(0xffffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_N_A10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_N_A10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// The value determines the timing  between an address 
+// cycle and a subsequent data cycle or two consecutive 
+// data  cycles on the bus.The I2C_SL_DELAY_COUNT is valid
+// only when internal slave is accessed.
+// I2C_SL_DELAY_COUNT has to be programmed such that 
+// TIMING = T * DLY where T is period of clock source
+// selected for I2c; and DLY is I2C_SL_DELAY_COUNT ;
+// TIMING is the desired timing, A value of >= 1250 ns is
+// advisable
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_FIELD                   (_MK_MASK_CONST(0xff) << I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SHIFT)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_RANGE                   7:0
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_WOFFSET                 0x0
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_DEFAULT                 _MK_MASK_CONST(0x1e)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARI2C_REGS(_op_) \
+_op_(I2C_I2C_CNFG_0) \
+_op_(I2C_I2C_CMD_ADDR0_0) \
+_op_(I2C_I2C_CMD_ADDR1_0) \
+_op_(I2C_I2C_CMD_DATA1_0) \
+_op_(I2C_I2C_CMD_DATA2_0) \
+_op_(I2C_I2C_STATUS_0) \
+_op_(I2C_I2C_SL_CNFG_0) \
+_op_(I2C_I2C_SL_RCVD_0) \
+_op_(I2C_I2C_SL_STATUS_0) \
+_op_(I2C_I2C_SL_ADDR1_0) \
+_op_(I2C_I2C_SL_ADDR2_0) \
+_op_(I2C_I2C_SL_DELAY_COUNT_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_I2C        0x00000000
+
+//
+// ARI2C REGISTER BANKS
+//
+
+#define I2C0_FIRST_REG 0x0000 // I2C_I2C_CNFG_0
+#define I2C0_LAST_REG 0x0010 // I2C_I2C_CMD_DATA2_0
+#define I2C1_FIRST_REG 0x001c // I2C_I2C_STATUS_0
+#define I2C1_LAST_REG 0x0030 // I2C_I2C_SL_ADDR2_0
+#define I2C2_FIRST_REG 0x003c // I2C_I2C_SL_DELAY_COUNT_0
+#define I2C2_LAST_REG 0x003c // I2C_I2C_SL_DELAY_COUNT_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARI2C_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arictlr.h b/arch/arm/mach-tegra/nv/include/ap15/arictlr.h
new file mode 100644
index 000000000000..e7e534faa38d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arictlr.h
@@ -0,0 +1,407 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARICTLR_H_INC_
+#define ___ARICTLR_H_INC_
+
+// Register ICTLR_VIRQ_CPU_0  
+#define ICTLR_VIRQ_CPU_0                        _MK_ADDR_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_WORD_COUNT                     0x1
+#define ICTLR_VIRQ_CPU_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_CPU_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_CPU_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Flags set by Hardware, cleared by SW
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_SHIFT)
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_RANGE                       31:0
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_WOFFSET                     0x0
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_CPU_0_IRQ31_IRQ0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_VIRQ_COP_0  
+#define ICTLR_VIRQ_COP_0                        _MK_ADDR_CONST(0x4)
+#define ICTLR_VIRQ_COP_0_WORD_COUNT                     0x1
+#define ICTLR_VIRQ_COP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_COP_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_COP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_COP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_COP_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_COP_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Flags set by Hardware, cleared by SW
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_VIRQ_COP_0_IRQ31_IRQ0_SHIFT)
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_RANGE                       31:0
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_WOFFSET                     0x0
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_VIRQ_COP_0_IRQ31_IRQ0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_VFIQ_CPU_0  
+#define ICTLR_VFIQ_CPU_0                        _MK_ADDR_CONST(0x8)
+#define ICTLR_VFIQ_CPU_0_WORD_COUNT                     0x1
+#define ICTLR_VFIQ_CPU_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_CPU_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_CPU_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_CPU_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_CPU_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_CPU_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Flags set by Hardware, cleared by SW
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_SHIFT)
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_RANGE                       31:0
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_WOFFSET                     0x0
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_CPU_0_FIQ31_FIQ0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_VFIQ_COP_0  
+#define ICTLR_VFIQ_COP_0                        _MK_ADDR_CONST(0xc)
+#define ICTLR_VFIQ_COP_0_WORD_COUNT                     0x1
+#define ICTLR_VFIQ_COP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_COP_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_COP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_COP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_COP_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_COP_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Flags set by Hardware, cleared by SW
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_VFIQ_COP_0_FIQ31_FIQ0_SHIFT)
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_RANGE                       31:0
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_WOFFSET                     0x0
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_VFIQ_COP_0_FIQ31_FIQ0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_ISR_0  
+#define ICTLR_ISR_0                     _MK_ADDR_CONST(0x10)
+#define ICTLR_ISR_0_WORD_COUNT                  0x1
+#define ICTLR_ISR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_ISR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_ISR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_ISR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_ISR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ICTLR_ISR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Read-only. Set by hardware event, cleared at  source by software.
+#define ICTLR_ISR_0_ISR31_ISR0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ICTLR_ISR_0_ISR31_ISR0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ICTLR_ISR_0_ISR31_ISR0_SHIFT)
+#define ICTLR_ISR_0_ISR31_ISR0_RANGE                    31:0
+#define ICTLR_ISR_0_ISR31_ISR0_WOFFSET                  0x0
+#define ICTLR_ISR_0_ISR31_ISR0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_ISR_0_ISR31_ISR0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_ISR_0_ISR31_ISR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ICTLR_ISR_0_ISR31_ISR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_FIR_0  
+#define ICTLR_FIR_0                     _MK_ADDR_CONST(0x14)
+#define ICTLR_FIR_0_WORD_COUNT                  0x1
+#define ICTLR_FIR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Read only: Set during write to FIR_SET, cleared  during write to FIR_CLR.
+#define ICTLR_FIR_0_FIR31_FIR0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ICTLR_FIR_0_FIR31_FIR0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ICTLR_FIR_0_FIR31_FIR0_SHIFT)
+#define ICTLR_FIR_0_FIR31_FIR0_RANGE                    31:0
+#define ICTLR_FIR_0_FIR31_FIR0_WOFFSET                  0x0
+#define ICTLR_FIR_0_FIR31_FIR0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_0_FIR31_FIR0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_0_FIR31_FIR0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_0_FIR31_FIR0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_FIR_SET_0  
+#define ICTLR_FIR_SET_0                 _MK_ADDR_CONST(0x18)
+#define ICTLR_FIR_SET_0_WORD_COUNT                      0x1
+#define ICTLR_FIR_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_READ_MASK                       _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Set Forced Interrupt Bit. Writing a 1 will set an  interrupt
+#define ICTLR_FIR_SET_0_FIR_SET_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_FIR_SET_0_FIR_SET_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_FIR_SET_0_FIR_SET_SHIFT)
+#define ICTLR_FIR_SET_0_FIR_SET_RANGE                   31:0
+#define ICTLR_FIR_SET_0_FIR_SET_WOFFSET                 0x0
+#define ICTLR_FIR_SET_0_FIR_SET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_FIR_SET_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_SET_0_FIR_SET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_FIR_CLR_0  
+#define ICTLR_FIR_CLR_0                 _MK_ADDR_CONST(0x1c)
+#define ICTLR_FIR_CLR_0_WORD_COUNT                      0x1
+#define ICTLR_FIR_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_READ_MASK                       _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Clear Forced Interrupt Bit: Writing a 1 will clear  the forced interrupt
+#define ICTLR_FIR_CLR_0_FIR_CLR_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_FIR_CLR_0_FIR_CLR_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_FIR_CLR_0_FIR_CLR_SHIFT)
+#define ICTLR_FIR_CLR_0_FIR_CLR_RANGE                   31:0
+#define ICTLR_FIR_CLR_0_FIR_CLR_WOFFSET                 0x0
+#define ICTLR_FIR_CLR_0_FIR_CLR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_FIR_CLR_0_FIR_CLR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_CPU_IER_0  
+#define ICTLR_CPU_IER_0                 _MK_ADDR_CONST(0x20)
+#define ICTLR_CPU_IER_0_WORD_COUNT                      0x1
+#define ICTLR_CPU_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+//  Interrupt Enable Status. 0 = Disabled
+#define ICTLR_CPU_IER_0_IER31_IER0_SHIFT                        _MK_SHIFT_CONST(0)
+#define ICTLR_CPU_IER_0_IER31_IER0_FIELD                        (_MK_MASK_CONST(0xffffffff) << ICTLR_CPU_IER_0_IER31_IER0_SHIFT)
+#define ICTLR_CPU_IER_0_IER31_IER0_RANGE                        31:0
+#define ICTLR_CPU_IER_0_IER31_IER0_WOFFSET                      0x0
+#define ICTLR_CPU_IER_0_IER31_IER0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_0_IER31_IER0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_0_IER31_IER0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_0_IER31_IER0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_CPU_IER_SET_0  
+#define ICTLR_CPU_IER_SET_0                     _MK_ADDR_CONST(0x24)
+#define ICTLR_CPU_IER_SET_0_WORD_COUNT                  0x1
+#define ICTLR_CPU_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will enable the  corresponding Interrupt Source for CPU 
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_CPU_IER_SET_0_CPU_IER_SET_SHIFT)
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_RANGE                   31:0
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_WOFFSET                 0x0
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_SET_0_CPU_IER_SET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_CPU_IER_CLR_0  
+#define ICTLR_CPU_IER_CLR_0                     _MK_ADDR_CONST(0x28)
+#define ICTLR_CPU_IER_CLR_0_WORD_COUNT                  0x1
+#define ICTLR_CPU_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will disable the  corresponding Interrupt Source for CPU 
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_SHIFT)
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_RANGE                   31:0
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_WOFFSET                 0x0
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IER_CLR_0_CPU_IER_CLR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_CPU_IEP_CLASS_0  
+#define ICTLR_CPU_IEP_CLASS_0                   _MK_ADDR_CONST(0x2c)
+#define ICTLR_CPU_IEP_CLASS_0_WORD_COUNT                        0x1
+#define ICTLR_CPU_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+//  Set Priority Interrupt Source For CPU. 1 = FIQ, 0 = IRQ.
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_SHIFT)
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_RANGE                       31:0
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_WOFFSET                     0x0
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_CPU_IEP_CLASS_0_CPU_IEP_CLASS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_COP_IER_0  
+#define ICTLR_COP_IER_0                 _MK_ADDR_CONST(0x30)
+#define ICTLR_COP_IER_0_WORD_COUNT                      0x1
+#define ICTLR_COP_IER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+//  Interrupt Enable Status. 0 = Disabled.
+#define ICTLR_COP_IER_0_IER31_IER0_SHIFT                        _MK_SHIFT_CONST(0)
+#define ICTLR_COP_IER_0_IER31_IER0_FIELD                        (_MK_MASK_CONST(0xffffffff) << ICTLR_COP_IER_0_IER31_IER0_SHIFT)
+#define ICTLR_COP_IER_0_IER31_IER0_RANGE                        31:0
+#define ICTLR_COP_IER_0_IER31_IER0_WOFFSET                      0x0
+#define ICTLR_COP_IER_0_IER31_IER0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_0_IER31_IER0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_0_IER31_IER0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_0_IER31_IER0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_COP_IER_SET_0  
+#define ICTLR_COP_IER_SET_0                     _MK_ADDR_CONST(0x34)
+#define ICTLR_COP_IER_SET_0_WORD_COUNT                  0x1
+#define ICTLR_COP_IER_SET_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_SET_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will enable the  corresponding Interrupt Source for COP 
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_COP_IER_SET_0_COP_IER_SET_SHIFT)
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_RANGE                   31:0
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_WOFFSET                 0x0
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_SET_0_COP_IER_SET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_COP_IER_CLR_0  
+#define ICTLR_COP_IER_CLR_0                     _MK_ADDR_CONST(0x38)
+#define ICTLR_COP_IER_CLR_0_WORD_COUNT                  0x1
+#define ICTLR_COP_IER_CLR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_CLR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_READ_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will disable the  corresponding Interrupt Source for COP
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_SHIFT                   _MK_SHIFT_CONST(0)
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_FIELD                   (_MK_MASK_CONST(0xffffffff) << ICTLR_COP_IER_CLR_0_COP_IER_CLR_SHIFT)
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_RANGE                   31:0
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_WOFFSET                 0x0
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IER_CLR_0_COP_IER_CLR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register ICTLR_COP_IEP_CLASS_0  
+#define ICTLR_COP_IEP_CLASS_0                   _MK_ADDR_CONST(0x3c)
+#define ICTLR_COP_IEP_CLASS_0_WORD_COUNT                        0x1
+#define ICTLR_COP_IEP_CLASS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IEP_CLASS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IEP_CLASS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IEP_CLASS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IEP_CLASS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IEP_CLASS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+//  Set Priority Interrupt Source For COP. 1 = FIQ, 0 = IRQ.
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_SHIFT                       _MK_SHIFT_CONST(0)
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_FIELD                       (_MK_MASK_CONST(0xffffffff) << ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_SHIFT)
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_RANGE                       31:0
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_WOFFSET                     0x0
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ICTLR_COP_IEP_CLASS_0_COP_IEP_CLASS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARICTLR_REGS(_op_) \
+_op_(ICTLR_VIRQ_CPU_0) \
+_op_(ICTLR_VIRQ_COP_0) \
+_op_(ICTLR_VFIQ_CPU_0) \
+_op_(ICTLR_VFIQ_COP_0) \
+_op_(ICTLR_ISR_0) \
+_op_(ICTLR_FIR_0) \
+_op_(ICTLR_FIR_SET_0) \
+_op_(ICTLR_FIR_CLR_0) \
+_op_(ICTLR_CPU_IER_0) \
+_op_(ICTLR_CPU_IER_SET_0) \
+_op_(ICTLR_CPU_IER_CLR_0) \
+_op_(ICTLR_CPU_IEP_CLASS_0) \
+_op_(ICTLR_COP_IER_0) \
+_op_(ICTLR_COP_IER_SET_0) \
+_op_(ICTLR_COP_IER_CLR_0) \
+_op_(ICTLR_COP_IEP_CLASS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_ICTLR      0x00000000
+
+//
+// ARICTLR REGISTER BANKS
+//
+
+#define ICTLR0_FIRST_REG 0x0000 // ICTLR_VIRQ_CPU_0
+#define ICTLR0_LAST_REG 0x003c // ICTLR_COP_IEP_CLASS_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARICTLR_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arictlr_arbgnt.h b/arch/arm/mach-tegra/nv/include/ap15/arictlr_arbgnt.h
new file mode 100644
index 000000000000..2d9790b7cc58
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arictlr_arbgnt.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARICTLR_ARBGNT_H_INC_
+#define ___ARICTLR_ARBGNT_H_INC_
+//
+// this spec file is for sw header generation
+//
+// hw should use headers generated from:
+//     arintr_ctlr.spec
+//
+//
+// arb_gnt specific interrupt controller registers
+//
+// Arbitration semaphores provide a mechanism by which the two processors can arbitrate
+// for the use of various resources. These semaphores provide a hardware locking mechanism,
+// so that when a processor is already using a resource, the second processor is not 
+// granted that resource. There are 32 bits of Arbitration semaphores provided in the system.
+// The hardware does not enforce any resource association to these bits. It is left to the
+// firmware to assign and use these bits.
+// The setup/usage of the Arbitration Semaphores is described in the ararb_sema specfile.
+//
+// The Arbitration Semaphores can also generate an interrupt when a hardware resource 
+// becomes available.  The registers in this module configure these interrupts.
+// When a 1 is set in the corresponding bit position of the Arbitration Semaphore Interrupt 
+// Source Register (CPU_enable or COP_enable), an interrupt will be generated when the 
+// processor achieves Grant Status for that resource.
+// The current Grant status can be viewed in the CPU_STATUS or COP_STATUS registers.
+//
+// CPU Arbitration Semaphore Interrupt Status Register
+
+// Register ARBGNT_CPU_STATUS_0  
+#define ARBGNT_CPU_STATUS_0                     _MK_ADDR_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_WORD_COUNT                  0x1
+#define ARBGNT_CPU_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Each bit is set by hardware when the corresponding  arbitration semaphore ownership is granted to CPU. Interrupt is cleared when  the CPU writes the ARB_SMP.PUT register with the corresponding bit set.
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ARBGNT_CPU_STATUS_0_GNT31_GNG0_SHIFT)
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_RANGE                    31:0
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_WOFFSET                  0x0
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_STATUS_0_GNT31_GNG0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CPU Arbitration Semaphore Interrupt Enable Register
+
+// Register ARBGNT_CPU_ENABLE_0  
+#define ARBGNT_CPU_ENABLE_0                     _MK_ADDR_CONST(0x4)
+#define ARBGNT_CPU_ENABLE_0_WORD_COUNT                  0x1
+#define ARBGNT_CPU_ENABLE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_ENABLE_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_ENABLE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_ENABLE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_ENABLE_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_ENABLE_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will enable the  corresponding arbitration semaphore interrupt.
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ARBGNT_CPU_ENABLE_0_GER31_GER0_SHIFT)
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_RANGE                    31:0
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_WOFFSET                  0x0
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARBGNT_CPU_ENABLE_0_GER31_GER0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// COP Arbitration Semaphore Interrupt Status Register
+
+// Register ARBGNT_COP_STATUS_0  
+#define ARBGNT_COP_STATUS_0                     _MK_ADDR_CONST(0x8)
+#define ARBGNT_COP_STATUS_0_WORD_COUNT                  0x1
+#define ARBGNT_COP_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Each bit is set by hardware when the corresponding  arbitration semaphore ownership is granted to COP. Interrupt is cleared when  the COP writes the ARB_SMP.PUT register with the corresponding bit set.
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ARBGNT_COP_STATUS_0_GNT31_GNG0_SHIFT)
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_RANGE                    31:0
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_WOFFSET                  0x0
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_STATUS_0_GNT31_GNG0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// COP Arbitration Semaphore Interrupt Enable Register
+
+// Register ARBGNT_COP_ENABLE_0  
+#define ARBGNT_COP_ENABLE_0                     _MK_ADDR_CONST(0xc)
+#define ARBGNT_COP_ENABLE_0_WORD_COUNT                  0x1
+#define ARBGNT_COP_ENABLE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_ENABLE_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_ENABLE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_ENABLE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_ENABLE_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_ENABLE_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Writing a 1 in any bit position will enable the  corresponding arbitration semaphore interrupt. 
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_FIELD                    (_MK_MASK_CONST(0xffffffff) << ARBGNT_COP_ENABLE_0_GER31_GER0_SHIFT)
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_RANGE                    31:0
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_WOFFSET                  0x0
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARBGNT_COP_ENABLE_0_GER31_GER0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARICTLR_ARBGNT_REGS(_op_) \
+_op_(ARBGNT_CPU_STATUS_0) \
+_op_(ARBGNT_CPU_ENABLE_0) \
+_op_(ARBGNT_COP_STATUS_0) \
+_op_(ARBGNT_COP_ENABLE_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_ARBGNT     0x00000000
+
+//
+// ARICTLR_ARBGNT REGISTER BANKS
+//
+
+#define ARBGNT0_FIRST_REG 0x0000 // ARBGNT_CPU_STATUS_0
+#define ARBGNT0_LAST_REG 0x000c // ARBGNT_COP_ENABLE_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARICTLR_ARBGNT_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/armc.h b/arch/arm/mach-tegra/nv/include/ap15/armc.h
new file mode 100644
index 000000000000..f831cef1d6cb
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/armc.h
@@ -0,0 +1,9593 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARMC_H_INC_
+#define ___ARMC_H_INC_
+
+// Register MC_INTSTATUS_0  
+#define MC_INTSTATUS_0                  _MK_ADDR_CONST(0x0)
+#define MC_INTSTATUS_0_WORD_COUNT                       0x1
+#define MC_INTSTATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_RESET_MASK                       _MK_MASK_CONST(0xc8)
+#define MC_INTSTATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_READ_MASK                        _MK_MASK_CONST(0xc8)
+#define MC_INTSTATUS_0_WRITE_MASK                       _MK_MASK_CONST(0xc8)
+// Address decode error for AXI client.
+#define MC_INTSTATUS_0_DECERR_AXI_INT_SHIFT                     _MK_SHIFT_CONST(3)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_FIELD                     (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_DECERR_AXI_INT_SHIFT)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_RANGE                     3:3
+#define MC_INTSTATUS_0_DECERR_AXI_INT_WOFFSET                   0x0
+#define MC_INTSTATUS_0_DECERR_AXI_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_INIT_ENUM                 CLEAR
+#define MC_INTSTATUS_0_DECERR_AXI_INT_CLEAR                     _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_DECERR_AXI_INT_SET                       _MK_ENUM_CONST(1)
+
+// EMEM Address Decode Error for a non AXI client.
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_FIELD                     (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SHIFT)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_RANGE                     6:6
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_WOFFSET                   0x0
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_INIT_ENUM                 CLEAR
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_CLEAR                     _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SET                       _MK_ENUM_CONST(1)
+
+// A GART access was attepted to an invalid page.
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SHIFT                      _MK_SHIFT_CONST(7)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_FIELD                      (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SHIFT)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_RANGE                      7:7
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_WOFFSET                    0x0
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_INIT_ENUM                  CLEAR
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_CLEAR                      _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SET                        _MK_ENUM_CONST(1)
+
+
+// Register MC_INTMASK_0  
+#define MC_INTMASK_0                    _MK_ADDR_CONST(0x4)
+#define MC_INTMASK_0_WORD_COUNT                         0x1
+#define MC_INTMASK_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_RESET_MASK                         _MK_MASK_CONST(0xc8)
+#define MC_INTMASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_READ_MASK                  _MK_MASK_CONST(0xc8)
+#define MC_INTMASK_0_WRITE_MASK                         _MK_MASK_CONST(0xc8)
+// Address decode error from an AXI client
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_SHIFT                   _MK_SHIFT_CONST(3)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_FIELD                   (_MK_MASK_CONST(0x1) << MC_INTMASK_0_DECERR_AXI_INTMASK_SHIFT)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_RANGE                   3:3
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_WOFFSET                 0x0
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_INIT_ENUM                       MASKED
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_MASKED                  _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_DECERR_AXI_INTMASK_UNMASKED                        _MK_ENUM_CONST(1)
+
+// EMEM Address Decode Error for a non AXI client.
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_FIELD                   (_MK_MASK_CONST(0x1) << MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SHIFT)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_RANGE                   6:6
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_WOFFSET                 0x0
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_INIT_ENUM                       MASKED
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_MASKED                  _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_UNMASKED                        _MK_ENUM_CONST(1)
+
+// A GART access was attepted to an invalid page.
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_FIELD                    (_MK_MASK_CONST(0x1) << MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SHIFT)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_RANGE                    7:7
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_WOFFSET                  0x0
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_INIT_ENUM                        MASKED
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_MASKED                   _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_UNMASKED                 _MK_ENUM_CONST(1)
+
+
+// Reserved address 8 [0x8] 
+
+// Register MC_EMEM_CFG_0  
+#define MC_EMEM_CFG_0                   _MK_ADDR_CONST(0xc)
+#define MC_EMEM_CFG_0_WORD_COUNT                        0x1
+#define MC_EMEM_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x10000)
+#define MC_EMEM_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_READ_MASK                         _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_FIELD                        (_MK_MASK_CONST(0x3fffff) << MC_EMEM_CFG_0_EMEM_SIZE_KB_SHIFT)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_RANGE                        21:0
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_WOFFSET                      0x0
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_DEFAULT                      _MK_MASK_CONST(0x10000)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_DEFAULT_MASK                 _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_EMEM_ADR_CFG_0  
+#define MC_EMEM_ADR_CFG_0                       _MK_ADDR_CONST(0x10)
+#define MC_EMEM_ADR_CFG_0_WORD_COUNT                    0x1
+#define MC_EMEM_ADR_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x40202)
+#define MC_EMEM_ADR_CFG_0_RESET_MASK                    _MK_MASK_CONST(0x3070307)
+#define MC_EMEM_ADR_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_READ_MASK                     _MK_MASK_CONST(0x3070307)
+#define MC_EMEM_ADR_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x3070307)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_FIELD                   (_MK_MASK_CONST(0x7) << MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_RANGE                   2:0
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_WOFFSET                 0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT                 _MK_MASK_CONST(0x2)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_INIT_ENUM                       W9
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W7                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W8                      _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W9                      _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W10                     _MK_ENUM_CONST(3)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W11                     _MK_ENUM_CONST(4)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT                  _MK_SHIFT_CONST(8)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_FIELD                  (_MK_MASK_CONST(0x3) << MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_RANGE                  9:8
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_WOFFSET                        0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT                        _MK_MASK_CONST(0x2)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_INIT_ENUM                      W2
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W1                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W2                     _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W3                     _MK_ENUM_CONST(3)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SHIFT                    _MK_SHIFT_CONST(16)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_RANGE                    18:16
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_WOFFSET                  0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_INIT_ENUM                        D64MB
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D4MB                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D8MB                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D16MB                    _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D32MB                    _MK_ENUM_CONST(3)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D64MB                    _MK_ENUM_CONST(4)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D128MB                   _MK_ENUM_CONST(5)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D256MB                   _MK_ENUM_CONST(6)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D512MB                   _MK_ENUM_CONST(7)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SHIFT                     _MK_SHIFT_CONST(24)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_FIELD                     (_MK_MASK_CONST(0x3) << MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_RANGE                     25:24
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_WOFFSET                   0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_INIT_ENUM                 N1
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_N1                        _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_N2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_EMEM_ARB_CFG0_0  
+#define MC_EMEM_ARB_CFG0_0                      _MK_ADDR_CONST(0x14)
+#define MC_EMEM_ARB_CFG0_0_WORD_COUNT                   0x1
+#define MC_EMEM_ARB_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x48a1010)
+#define MC_EMEM_ARB_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define MC_EMEM_ARB_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define MC_EMEM_ARB_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_FIELD                  (_MK_MASK_CONST(0xff) << MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_RANGE                  7:0
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_DEFAULT                        _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SHIFT                  _MK_SHIFT_CONST(8)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_FIELD                  (_MK_MASK_CONST(0xff) << MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_RANGE                  15:8
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_DEFAULT                        _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_FIELD                        (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_RANGE                        21:16
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_DEFAULT                      _MK_MASK_CONST(0xa)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_TH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_SHIFT                    _MK_SHIFT_CONST(22)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_FIELD                    (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_RANGE                    27:22
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_WOFFSET                  0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_DEFAULT                  _MK_MASK_CONST(0x12)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_BANKCNT_NSP_TH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_RANGE                        28:28
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_INIT_ENUM                    DISABLE
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SHIFT                       _MK_SHIFT_CONST(29)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_RANGE                       29:29
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_WOFFSET                     0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_INIT_ENUM                   DISABLE
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_ENABLED                     _MK_ENUM_CONST(1)
+
+#define NV_MC_ARB_EMEM_SPMSB    5
+
+// Register MC_EMEM_ARB_CFG1_0  
+#define MC_EMEM_ARB_CFG1_0                      _MK_ADDR_CONST(0x18)
+#define MC_EMEM_ARB_CFG1_0_WORD_COUNT                   0x1
+#define MC_EMEM_ARB_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x10cfff)
+#define MC_EMEM_ARB_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_ARB_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_ARB_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_FIELD                  (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_RANGE                  5:0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_DEFAULT                        _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_INIT_ENUM                      ALL
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_NONE                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_ALL                    _MK_ENUM_CONST(63)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SHIFT                  _MK_SHIFT_CONST(6)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_FIELD                  (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_RANGE                  11:6
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_DEFAULT                        _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_INIT_ENUM                      ALL
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_NONE                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_ALL                    _MK_ENUM_CONST(63)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_RANGE                        12:12
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_INIT_ENUM                    DISABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SHIFT                        _MK_SHIFT_CONST(13)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_RANGE                        13:13
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_INIT_ENUM                    DISABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SHIFT                      _MK_SHIFT_CONST(14)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_FIELD                      (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_RANGE                      14:14
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_INIT_ENUM                  ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_FIELD                      (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_RANGE                      15:15
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_INIT_ENUM                  ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SHIFT                      _MK_SHIFT_CONST(16)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_FIELD                      (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RANGE                      21:16
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_DEFAULT                    _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_CONFIG_0  
+#define MC_GART_CONFIG_0                        _MK_ADDR_CONST(0x1c)
+#define MC_GART_CONFIG_0_WORD_COUNT                     0x1
+#define MC_GART_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_GART_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_GART_CONFIG_0_GART_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_GART_CONFIG_0_GART_ENABLE_SHIFT)
+#define MC_GART_CONFIG_0_GART_ENABLE_RANGE                      0:0
+#define MC_GART_CONFIG_0_GART_ENABLE_WOFFSET                    0x0
+#define MC_GART_CONFIG_0_GART_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_GART_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_INIT_ENUM                  DISABLE
+#define MC_GART_CONFIG_0_GART_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_GART_CONFIG_0_GART_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register MC_GART_ENTRY_ADDR_0  
+#define MC_GART_ENTRY_ADDR_0                    _MK_ADDR_CONST(0x20)
+#define MC_GART_ENTRY_ADDR_0_WORD_COUNT                         0x1
+#define MC_GART_ENTRY_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_READ_MASK                  _MK_MASK_CONST(0xfff000)
+#define MC_GART_ENTRY_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0xfff000)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_FIELD                   (_MK_MASK_CONST(0xfff) << MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SHIFT)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_RANGE                   23:12
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_WOFFSET                 0x0
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ENTRY_DATA_0  
+#define MC_GART_ENTRY_DATA_0                    _MK_ADDR_CONST(0x24)
+#define MC_GART_ENTRY_DATA_0_WORD_COUNT                         0x1
+#define MC_GART_ENTRY_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_READ_MASK                  _MK_MASK_CONST(0xfffff000)
+#define MC_GART_ENTRY_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff000)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_FIELD                      (_MK_MASK_CONST(0x1) << MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SHIFT)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_RANGE                      31:31
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_WOFFSET                    0x0
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_FIELD                    (_MK_MASK_CONST(0x7ffff) << MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SHIFT)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_RANGE                    30:12
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_WOFFSET                  0x0
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ERROR_REQ_0  
+#define MC_GART_ERROR_REQ_0                     _MK_ADDR_CONST(0x28)
+#define MC_GART_ERROR_REQ_0_WORD_COUNT                  0x1
+#define MC_GART_ERROR_REQ_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_READ_MASK                   _MK_MASK_CONST(0x7f)
+#define MC_GART_ERROR_REQ_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SHIFT)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_RANGE                  0:0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_WOFFSET                        0x0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_READ                   _MK_ENUM_CONST(0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_WRITE                  _MK_ENUM_CONST(1)
+
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SHIFT                  _MK_SHIFT_CONST(1)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_FIELD                  (_MK_MASK_CONST(0x3f) << MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SHIFT)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_RANGE                  6:1
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_WOFFSET                        0x0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ERROR_ADDR_0  
+#define MC_GART_ERROR_ADDR_0                    _MK_ADDR_CONST(0x2c)
+#define MC_GART_ERROR_ADDR_0_WORD_COUNT                         0x1
+#define MC_GART_ERROR_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_GART_ERROR_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SHIFT)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_RANGE                   31:0
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_WOFFSET                 0x0
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_PARTITION_CONFLICT_CFG_0  
+#define MC_PARTITION_CONFLICT_CFG_0                     _MK_ADDR_CONST(0x30)
+#define MC_PARTITION_CONFLICT_CFG_0_WORD_COUNT                  0x1
+#define MC_PARTITION_CONFLICT_CFG_0_RESET_VAL                   _MK_MASK_CONST(0x2)
+#define MC_PARTITION_CONFLICT_CFG_0_RESET_MASK                  _MK_MASK_CONST(0x2)
+#define MC_PARTITION_CONFLICT_CFG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_PARTITION_CONFLICT_CFG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_PARTITION_CONFLICT_CFG_0_READ_MASK                   _MK_MASK_CONST(0x2)
+#define MC_PARTITION_CONFLICT_CFG_0_WRITE_MASK                  _MK_MASK_CONST(0x2)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_FIELD                   (_MK_MASK_CONST(0x1) << MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_SHIFT)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_RANGE                   1:1
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_WOFFSET                 0x0
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_INIT_ENUM                       MULTI
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_SINGLE                  _MK_ENUM_CONST(0)
+#define MC_PARTITION_CONFLICT_CFG_0_MEM_RDPATHS_MULTI                   _MK_ENUM_CONST(1)
+
+
+// Register MC_TIMEOUT_CTRL_0  
+#define MC_TIMEOUT_CTRL_0                       _MK_ADDR_CONST(0x34)
+#define MC_TIMEOUT_CTRL_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_READ_MASK                     _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SHIFT                 _MK_SHIFT_CONST(3)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_FIELD                 (_MK_MASK_CONST(0x7) << MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SHIFT)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_RANGE                 5:3
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_WOFFSET                       0x0
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_FIELD                       (_MK_MASK_CONST(0x1) << MC_TIMEOUT_CTRL_0_TMCREDITS_SHIFT)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_RANGE                       6:6
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_WOFFSET                     0x0
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_INIT_ENUM                   FROM_CIF_FIFO
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_FROM_CIF_FIFO                       _MK_ENUM_CONST(0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_ONE                 _MK_ENUM_CONST(1)
+
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Register MC_DECERR_AXI_STATUS_0  
+#define MC_DECERR_AXI_STATUS_0                  _MK_ADDR_CONST(0x40)
+#define MC_DECERR_AXI_STATUS_0_WORD_COUNT                       0x1
+#define MC_DECERR_AXI_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_DECERR_AXI_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_FIELD                      (_MK_MASK_CONST(0x1) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_RANGE                      0:0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_WOFFSET                    0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_READ                       _MK_ENUM_CONST(0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_RW_WRITE                      _MK_ENUM_CONST(1)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_SHIFT                      _MK_SHIFT_CONST(1)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_FIELD                      (_MK_MASK_CONST(0xff) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_RANGE                      8:1
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_WOFFSET                    0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_SHIFT                     _MK_SHIFT_CONST(9)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_FIELD                     (_MK_MASK_CONST(0xf) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_RANGE                     12:9
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_WOFFSET                   0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_SHIFT                    _MK_SHIFT_CONST(13)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_RANGE                    15:13
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_WOFFSET                  0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_FIELD                   (_MK_MASK_CONST(0x3) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_RANGE                   17:16
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_WOFFSET                 0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_BURST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_SHIFT                   _MK_SHIFT_CONST(18)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_FIELD                   (_MK_MASK_CONST(0xf) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_RANGE                   21:18
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_WOFFSET                 0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_CACHE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_SHIFT                    _MK_SHIFT_CONST(22)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_FIELD                    (_MK_MASK_CONST(0x7) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_RANGE                    24:22
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_WOFFSET                  0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_PROT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_SHIFT                    _MK_SHIFT_CONST(25)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_FIELD                    (_MK_MASK_CONST(0x3) << MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_RANGE                    26:25
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_WOFFSET                  0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_AXI_LOCK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_SHIFT                      _MK_SHIFT_CONST(27)
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_FIELD                      (_MK_MASK_CONST(0x1f) << MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_SHIFT)
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_RANGE                      31:27
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_WOFFSET                    0x0
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_STATUS_0_DECERR_SOURCE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_DECERR_AXI_ADR_0  
+#define MC_DECERR_AXI_ADR_0                     _MK_ADDR_CONST(0x44)
+#define MC_DECERR_AXI_ADR_0_WORD_COUNT                  0x1
+#define MC_DECERR_AXI_ADR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_DECERR_AXI_ADR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_SHIFT)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_RANGE                        31:0
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_WOFFSET                      0x0
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_AXI_ADR_0_DECERR_AXI_ADR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Register MC_DECERR_EMEM_OTHERS_STATUS_0  
+#define MC_DECERR_EMEM_OTHERS_STATUS_0                  _MK_ADDR_CONST(0x50)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_WORD_COUNT                       0x1
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x7f)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_FIELD                      (_MK_MASK_CONST(0x1) << MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_RANGE                      0:0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_WOFFSET                    0x0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_READ                       _MK_ENUM_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_WRITE                      _MK_ENUM_CONST(1)
+
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SHIFT                      _MK_SHIFT_CONST(1)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_FIELD                      (_MK_MASK_CONST(0x3f) << MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_RANGE                      6:1
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_WOFFSET                    0x0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_DECERR_EMEM_OTHERS_ADR_0  
+#define MC_DECERR_EMEM_OTHERS_ADR_0                     _MK_ADDR_CONST(0x54)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_WORD_COUNT                  0x1
+#define MC_DECERR_EMEM_OTHERS_ADR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_RANGE                        31:0
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_WOFFSET                      0x0
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Register MC_CLKEN_OVERRIDE_0  
+#define MC_CLKEN_OVERRIDE_0                     _MK_ADDR_CONST(0x60)
+#define MC_CLKEN_OVERRIDE_0_WORD_COUNT                  0x1
+#define MC_CLKEN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_RANGE                 0:0
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_WOFFSET                       0x0
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_RANGE                        2:2
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(3)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_RANGE                        3:3
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_RANGE                        4:4
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Register MC_STAT_CONTROL_0  
+#define MC_STAT_CONTROL_0                       _MK_ADDR_CONST(0x64)
+#define MC_STAT_CONTROL_0_WORD_COUNT                    0x1
+#define MC_STAT_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_STAT_CONTROL_0_EMC_GATHER_FIELD                      (_MK_MASK_CONST(0x3) << MC_STAT_CONTROL_0_EMC_GATHER_SHIFT)
+#define MC_STAT_CONTROL_0_EMC_GATHER_RANGE                      9:8
+#define MC_STAT_CONTROL_0_EMC_GATHER_WOFFSET                    0x0
+#define MC_STAT_CONTROL_0_EMC_GATHER_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_INIT_ENUM                  RST
+#define MC_STAT_CONTROL_0_EMC_GATHER_RST                        _MK_ENUM_CONST(0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_CLEAR                      _MK_ENUM_CONST(1)
+#define MC_STAT_CONTROL_0_EMC_GATHER_DISABLE                    _MK_ENUM_CONST(2)
+#define MC_STAT_CONTROL_0_EMC_GATHER_ENABLE                     _MK_ENUM_CONST(3)
+
+
+// Register MC_STAT_STATUS_0  
+#define MC_STAT_STATUS_0                        _MK_ADDR_CONST(0x68)
+#define MC_STAT_STATUS_0_WORD_COUNT                     0x1
+#define MC_STAT_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x100)
+#define MC_STAT_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_STAT_STATUS_0_EMC_LIMIT_FIELD                        (_MK_MASK_CONST(0x1) << MC_STAT_STATUS_0_EMC_LIMIT_SHIFT)
+#define MC_STAT_STATUS_0_EMC_LIMIT_RANGE                        8:8
+#define MC_STAT_STATUS_0_EMC_LIMIT_WOFFSET                      0x0
+#define MC_STAT_STATUS_0_EMC_LIMIT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_ADDR_LOW_0  
+#define MC_STAT_EMC_ADDR_LOW_0                  _MK_ADDR_CONST(0x6c)
+#define MC_STAT_EMC_ADDR_LOW_0_WORD_COUNT                       0x1
+#define MC_STAT_EMC_ADDR_LOW_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_RESET_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_READ_MASK                        _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_WRITE_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_FIELD                       (_MK_MASK_CONST(0x3ffffff) << MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SHIFT)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_RANGE                       29:4
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_WOFFSET                     0x0
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_DEFAULT_MASK                        _MK_MASK_CONST(0x3ffffff)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_ADDR_HIGH_0  
+#define MC_STAT_EMC_ADDR_HIGH_0                 _MK_ADDR_CONST(0x70)
+#define MC_STAT_EMC_ADDR_HIGH_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_ADDR_HIGH_0_RESET_VAL                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_RESET_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_READ_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_WRITE_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_FIELD                     (_MK_MASK_CONST(0x3ffffff) << MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SHIFT)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_RANGE                     29:4
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_WOFFSET                   0x0
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_DEFAULT                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_DEFAULT_MASK                      _MK_MASK_CONST(0x3ffffff)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_INIT_ENUM                 -1
+
+
+// Register MC_STAT_EMC_CLOCK_LIMIT_0  
+#define MC_STAT_EMC_CLOCK_LIMIT_0                       _MK_ADDR_CONST(0x74)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_WORD_COUNT                    0x1
+#define MC_STAT_EMC_CLOCK_LIMIT_0_RESET_VAL                     _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SHIFT)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_RANGE                 31:0
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_WOFFSET                       0x0
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_DEFAULT                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_INIT_ENUM                     -1
+
+
+// Register MC_STAT_EMC_CLOCKS_0  
+#define MC_STAT_EMC_CLOCKS_0                    _MK_ADDR_CONST(0x78)
+#define MC_STAT_EMC_CLOCKS_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_CLOCKS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCKS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SHIFT)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_RANGE                   31:0
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_WOFFSET                 0x0
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Packet ARMC_STAT_CONTROL
+#define ARMC_STAT_CONTROL_SIZE 32
+
+#define ARMC_STAT_CONTROL_MODE_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_FIELD                    (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_MODE_SHIFT)
+#define ARMC_STAT_CONTROL_MODE_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_ROW                      0
+#define ARMC_STAT_CONTROL_MODE_BANDWIDTH                        _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_LATENCY_AVG                      _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_MODE_LATENCY_HISTO                    _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_SKIP_SHIFT                    _MK_SHIFT_CONST(4)
+#define ARMC_STAT_CONTROL_SKIP_FIELD                    (_MK_MASK_CONST(0x7) << ARMC_STAT_CONTROL_SKIP_SHIFT)
+#define ARMC_STAT_CONTROL_SKIP_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(4)
+#define ARMC_STAT_CONTROL_SKIP_ROW                      0
+
+#define ARMC_STAT_CONTROL_CLIENT_ID_SHIFT                       _MK_SHIFT_CONST(8)
+#define ARMC_STAT_CONTROL_CLIENT_ID_FIELD                       (_MK_MASK_CONST(0x3f) << ARMC_STAT_CONTROL_CLIENT_ID_SHIFT)
+#define ARMC_STAT_CONTROL_CLIENT_ID_RANGE                       _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(8)
+#define ARMC_STAT_CONTROL_CLIENT_ID_ROW                 0
+
+#define ARMC_STAT_CONTROL_EVENT_SHIFT                   _MK_SHIFT_CONST(16)
+#define ARMC_STAT_CONTROL_EVENT_FIELD                   (_MK_MASK_CONST(0xff) << ARMC_STAT_CONTROL_EVENT_SHIFT)
+#define ARMC_STAT_CONTROL_EVENT_RANGE                   _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define ARMC_STAT_CONTROL_EVENT_ROW                     0
+#define ARMC_STAT_CONTROL_EVENT_QUALIFIED                       _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_EVENT_ANY_READ                        _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_EVENT_ANY_WRITE                       _MK_ENUM_CONST(2)
+#define ARMC_STAT_CONTROL_EVENT_RD_WR_CHANGE                    _MK_ENUM_CONST(3)
+#define ARMC_STAT_CONTROL_EVENT_SUCCESSIVE                      _MK_ENUM_CONST(4)
+#define ARMC_STAT_CONTROL_EVENT_ARB_BANK_AA                     _MK_ENUM_CONST(5)
+#define ARMC_STAT_CONTROL_EVENT_ARB_BANK_BB                     _MK_ENUM_CONST(6)
+#define ARMC_STAT_CONTROL_EVENT_PAGE_MISS                       _MK_ENUM_CONST(7)
+#define ARMC_STAT_CONTROL_EVENT_AUTO_PRECHARGE                  _MK_ENUM_CONST(8)
+
+#define ARMC_STAT_CONTROL_PRI_EVENT_SHIFT                       _MK_SHIFT_CONST(24)
+#define ARMC_STAT_CONTROL_PRI_EVENT_FIELD                       (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_PRI_EVENT_SHIFT)
+#define ARMC_STAT_CONTROL_PRI_EVENT_RANGE                       _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(24)
+#define ARMC_STAT_CONTROL_PRI_EVENT_ROW                 0
+#define ARMC_STAT_CONTROL_PRI_EVENT_HP                  _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_PRI_EVENT_TM                  _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_PRI_EVENT_BW                  _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT                   _MK_SHIFT_CONST(26)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_FIELD                   (_MK_MASK_CONST(0x1) << ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_RANGE                   _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_ROW                     0
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_DISABLE                 _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE                  _MK_ENUM_CONST(1)
+
+#define ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT                     _MK_SHIFT_CONST(27)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_FIELD                     (_MK_MASK_CONST(0x1) << ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_ROW                       0
+#define ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE                   _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_ENABLE                    _MK_ENUM_CONST(1)
+
+#define ARMC_STAT_CONTROL_FILTER_PRI_SHIFT                      _MK_SHIFT_CONST(28)
+#define ARMC_STAT_CONTROL_FILTER_PRI_FIELD                      (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_FILTER_PRI_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_PRI_RANGE                      _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(28)
+#define ARMC_STAT_CONTROL_FILTER_PRI_ROW                        0
+#define ARMC_STAT_CONTROL_FILTER_PRI_DISABLE                    _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_PRI_NO                 _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_FILTER_PRI_YES                        _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT                        _MK_SHIFT_CONST(30)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_FIELD                        (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_ROW                  0
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE                      _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_NO                   _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_YES                  _MK_ENUM_CONST(2)
+
+
+// Register MC_STAT_EMC_CONTROL_0_0  
+#define MC_STAT_EMC_CONTROL_0_0                 _MK_ADDR_CONST(0x7c)
+#define MC_STAT_EMC_CONTROL_0_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_CONTROL_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SHIFT)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_RANGE                     31:0
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_WOFFSET                   0x0
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_CONTROL_1_0  
+#define MC_STAT_EMC_CONTROL_1_0                 _MK_ADDR_CONST(0x80)
+#define MC_STAT_EMC_CONTROL_1_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_CONTROL_1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SHIFT)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_RANGE                     31:0
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_WOFFSET                   0x0
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Packet ARMC_STAT_HIST_LIMIT
+#define ARMC_STAT_HIST_LIMIT_SIZE 32
+
+#define ARMC_STAT_HIST_LIMIT_LOW_SHIFT                  _MK_SHIFT_CONST(0)
+#define ARMC_STAT_HIST_LIMIT_LOW_FIELD                  (_MK_MASK_CONST(0xffff) << ARMC_STAT_HIST_LIMIT_LOW_SHIFT)
+#define ARMC_STAT_HIST_LIMIT_LOW_RANGE                  _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define ARMC_STAT_HIST_LIMIT_LOW_ROW                    0
+
+#define ARMC_STAT_HIST_LIMIT_HIGH_SHIFT                 _MK_SHIFT_CONST(16)
+#define ARMC_STAT_HIST_LIMIT_HIGH_FIELD                 (_MK_MASK_CONST(0xffff) << ARMC_STAT_HIST_LIMIT_HIGH_SHIFT)
+#define ARMC_STAT_HIST_LIMIT_HIGH_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define ARMC_STAT_HIST_LIMIT_HIGH_ROW                   0
+
+
+// Register MC_STAT_EMC_HIST_LIMIT_0_0  
+#define MC_STAT_EMC_HIST_LIMIT_0_0                      _MK_ADDR_CONST(0x84)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_WORD_COUNT                   0x1
+#define MC_STAT_EMC_HIST_LIMIT_0_0_RESET_VAL                    _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_FIELD                       (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SHIFT)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_RANGE                       31:0
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_WOFFSET                     0x0
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_DEFAULT                     _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_INIT_ENUM                   -65536
+
+
+// Register MC_STAT_EMC_HIST_LIMIT_1_0  
+#define MC_STAT_EMC_HIST_LIMIT_1_0                      _MK_ADDR_CONST(0x88)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_WORD_COUNT                   0x1
+#define MC_STAT_EMC_HIST_LIMIT_1_0_RESET_VAL                    _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_FIELD                       (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SHIFT)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_RANGE                       31:0
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_WOFFSET                     0x0
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_DEFAULT                     _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_INIT_ENUM                   -65536
+
+
+// Register MC_STAT_EMC_COUNT_0_0  
+#define MC_STAT_EMC_COUNT_0_0                   _MK_ADDR_CONST(0x8c)
+#define MC_STAT_EMC_COUNT_0_0_WORD_COUNT                        0x1
+#define MC_STAT_EMC_COUNT_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_COUNT_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SHIFT)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_RANGE                 31:0
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_WOFFSET                       0x0
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_COUNT_1_0  
+#define MC_STAT_EMC_COUNT_1_0                   _MK_ADDR_CONST(0x90)
+#define MC_STAT_EMC_COUNT_1_0_WORD_COUNT                        0x1
+#define MC_STAT_EMC_COUNT_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_COUNT_1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SHIFT)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_RANGE                 31:0
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_WOFFSET                       0x0
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_HIST_0_0  
+#define MC_STAT_EMC_HIST_0_0                    _MK_ADDR_CONST(0x94)
+#define MC_STAT_EMC_HIST_0_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_HIST_0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SHIFT)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_RANGE                   31:0
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_WOFFSET                 0x0
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_HIST_1_0  
+#define MC_STAT_EMC_HIST_1_0                    _MK_ADDR_CONST(0x98)
+#define MC_STAT_EMC_HIST_1_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_HIST_1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SHIFT)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_RANGE                   31:0
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_WOFFSET                 0x0
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_CLIENT_CTRL_DISABLE  0
+#define MC_CLIENT_CTRL_ENABLE   1
+
+// Register MC_CLIENT_CTRL_0  
+#define MC_CLIENT_CTRL_0                        _MK_ADDR_CONST(0x9c)
+#define MC_CLIENT_CTRL_0_WORD_COUNT                     0x1
+#define MC_CLIENT_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_READ_MASK                      _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_CMC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_RANGE                       0:0
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_CMC_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_DC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_RANGE                        1:1
+#define MC_CLIENT_CTRL_0_DC_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_DCB_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_RANGE                       2:2
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_EPP_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_RANGE                       3:3
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_G2_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_RANGE                        4:4
+#define MC_CLIENT_CTRL_0_G2_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_HC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_RANGE                        5:5
+#define MC_CLIENT_CTRL_0_HC_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_ISP_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_RANGE                       6:6
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPCORE_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_RANGE                    7:7
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_WOFFSET                  0x0
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_INIT_ENUM                        ENABLE
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEA_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_RANGE                      8:8
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SHIFT                      _MK_SHIFT_CONST(9)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEB_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_RANGE                      9:9
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SHIFT                      _MK_SHIFT_CONST(10)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_RANGE                      10:10
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_NV_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_RANGE                        11:11
+#define MC_CLIENT_CTRL_0_NV_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_PPCS_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_RANGE                      12:12
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SHIFT                       _MK_SHIFT_CONST(13)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_VDE_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_RANGE                       13:13
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_VI_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_RANGE                        14:14
+#define MC_CLIENT_CTRL_0_VI_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_DISABLE     1
+#define MC_CLIENT_HOTRESETN_ENABLE      0
+
+// Register MC_CLIENT_HOTRESETN_0  
+#define MC_CLIENT_HOTRESETN_0                   _MK_ADDR_CONST(0xa0)
+#define MC_CLIENT_HOTRESETN_0_WORD_COUNT                        0x1
+#define MC_CLIENT_HOTRESETN_0_RESET_VAL                         _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_RESET_MASK                        _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_READ_MASK                         _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_RANGE                       0:0
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_CMC_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_RANGE                        1:1
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_RANGE                       2:2
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_RANGE                       3:3
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_RANGE                        4:4
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_RANGE                        5:5
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_RANGE                       6:6
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_RANGE                    7:7
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_WOFFSET                  0x0
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_INIT_ENUM                        DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_ENABLE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DISABLE                  _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_ENABLED                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DISABLED                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_RANGE                      8:8
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(9)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_RANGE                      9:9
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(10)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_RANGE                      10:10
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_RANGE                        11:11
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_RANGE                      12:12
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(13)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_RANGE                       13:13
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_RANGE                        14:14
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+
+// Register MC_CMC_ORRC_0  
+#define MC_CMC_ORRC_0                   _MK_ADDR_CONST(0xa4)
+#define MC_CMC_ORRC_0_WORD_COUNT                        0x1
+#define MC_CMC_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_CMC_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_CMC_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_CMC_ORRC_0_CMC_OUTREQCNT_SHIFT)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_RANGE                       7:0
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_WOFFSET                     0x0
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CMC_ORRC_0_CMC_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_DC_ORRC_0  
+#define MC_DC_ORRC_0                    _MK_ADDR_CONST(0xa8)
+#define MC_DC_ORRC_0_WORD_COUNT                         0x1
+#define MC_DC_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_DC_ORRC_0_DC_OUTREQCNT_SHIFT)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_RANGE                 7:0
+#define MC_DC_ORRC_0_DC_OUTREQCNT_WOFFSET                       0x0
+#define MC_DC_ORRC_0_DC_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_DCB_ORRC_0  
+#define MC_DCB_ORRC_0                   _MK_ADDR_CONST(0xac)
+#define MC_DCB_ORRC_0_WORD_COUNT                        0x1
+#define MC_DCB_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_DCB_ORRC_0_DCB_OUTREQCNT_SHIFT)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_RANGE                       7:0
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_WOFFSET                     0x0
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_EPP_ORRC_0  
+#define MC_EPP_ORRC_0                   _MK_ADDR_CONST(0xb0)
+#define MC_EPP_ORRC_0_WORD_COUNT                        0x1
+#define MC_EPP_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_EPP_ORRC_0_EPP_OUTREQCNT_SHIFT)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_RANGE                       7:0
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_WOFFSET                     0x0
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_G2_ORRC_0  
+#define MC_G2_ORRC_0                    _MK_ADDR_CONST(0xb4)
+#define MC_G2_ORRC_0_WORD_COUNT                         0x1
+#define MC_G2_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_G2_ORRC_0_G2_OUTREQCNT_SHIFT)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_RANGE                 7:0
+#define MC_G2_ORRC_0_G2_OUTREQCNT_WOFFSET                       0x0
+#define MC_G2_ORRC_0_G2_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_HC_ORRC_0  
+#define MC_HC_ORRC_0                    _MK_ADDR_CONST(0xb8)
+#define MC_HC_ORRC_0_WORD_COUNT                         0x1
+#define MC_HC_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_HC_ORRC_0_HC_OUTREQCNT_SHIFT)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_RANGE                 7:0
+#define MC_HC_ORRC_0_HC_OUTREQCNT_WOFFSET                       0x0
+#define MC_HC_ORRC_0_HC_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_ISP_ORRC_0  
+#define MC_ISP_ORRC_0                   _MK_ADDR_CONST(0xbc)
+#define MC_ISP_ORRC_0_WORD_COUNT                        0x1
+#define MC_ISP_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_ISP_ORRC_0_ISP_OUTREQCNT_SHIFT)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_RANGE                       7:0
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_WOFFSET                     0x0
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPCORE_ORRC_0  
+#define MC_MPCORE_ORRC_0                        _MK_ADDR_CONST(0xc0)
+#define MC_MPCORE_ORRC_0_WORD_COUNT                     0x1
+#define MC_MPCORE_ORRC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SHIFT)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_RANGE                 7:0
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_WOFFSET                       0x0
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEA_ORRC_0  
+#define MC_MPEA_ORRC_0                  _MK_ADDR_CONST(0xc4)
+#define MC_MPEA_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEA_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SHIFT)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_RANGE                     7:0
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEB_ORRC_0  
+#define MC_MPEB_ORRC_0                  _MK_ADDR_CONST(0xc8)
+#define MC_MPEB_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEB_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SHIFT)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_RANGE                     7:0
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEC_ORRC_0  
+#define MC_MPEC_ORRC_0                  _MK_ADDR_CONST(0xcc)
+#define MC_MPEC_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEC_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SHIFT)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_RANGE                     7:0
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_NV_ORRC_0  
+#define MC_NV_ORRC_0                    _MK_ADDR_CONST(0xd0)
+#define MC_NV_ORRC_0_WORD_COUNT                         0x1
+#define MC_NV_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_NV_ORRC_0_NV_OUTREQCNT_SHIFT)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_RANGE                 7:0
+#define MC_NV_ORRC_0_NV_OUTREQCNT_WOFFSET                       0x0
+#define MC_NV_ORRC_0_NV_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_PPCS_ORRC_0  
+#define MC_PPCS_ORRC_0                  _MK_ADDR_CONST(0xd4)
+#define MC_PPCS_ORRC_0_WORD_COUNT                       0x1
+#define MC_PPCS_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SHIFT)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_RANGE                     7:0
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_WOFFSET                   0x0
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_VDE_ORRC_0  
+#define MC_VDE_ORRC_0                   _MK_ADDR_CONST(0xd8)
+#define MC_VDE_ORRC_0_WORD_COUNT                        0x1
+#define MC_VDE_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_VDE_ORRC_0_VDE_OUTREQCNT_SHIFT)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_RANGE                       7:0
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_WOFFSET                     0x0
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_VI_ORRC_0  
+#define MC_VI_ORRC_0                    _MK_ADDR_CONST(0xdc)
+#define MC_VI_ORRC_0_WORD_COUNT                         0x1
+#define MC_VI_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_VI_ORRC_0_VI_OUTREQCNT_SHIFT)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_RANGE                 7:0
+#define MC_VI_ORRC_0_VI_OUTREQCNT_WOFFSET                       0x0
+#define MC_VI_ORRC_0_VI_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_CLIENT_AP_CTRL_DISABLE       0
+#define MC_CLIENT_AP_CTRL_ENABLE        1
+
+// Register MC_AP_CTRL_0_0  
+#define MC_AP_CTRL_0_0                  _MK_ADDR_CONST(0xe0)
+#define MC_AP_CTRL_0_0_WORD_COUNT                       0x1
+#define MC_AP_CTRL_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_RANGE                    0:0
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_RANGE                   1:1
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_RANGE                    2:2
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SHIFT                   _MK_SHIFT_CONST(3)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_RANGE                   3:3
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_RANGE                    4:4
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SHIFT                   _MK_SHIFT_CONST(5)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_RANGE                   5:5
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_RANGE                    6:6
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SHIFT                   _MK_SHIFT_CONST(7)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_RANGE                   7:7
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_EPPUP_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_RANGE                        8:8
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SHIFT                 _MK_SHIFT_CONST(9)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2PR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_RANGE                 9:9
+#define MC_AP_CTRL_0_0_G2PR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SHIFT                 _MK_SHIFT_CONST(10)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2SR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_RANGE                 10:10
+#define MC_AP_CTRL_0_0_G2SR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_RANGE                    11:11
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VIRUV_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_RANGE                        12:12
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_CMCR_APVAL_SHIFT                 _MK_SHIFT_CONST(13)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_CMCR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_RANGE                 13:13
+#define MC_AP_CTRL_0_0_CMCR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_CMCR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_CMCR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_CMCR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SHIFT                    _MK_SHIFT_CONST(14)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_RANGE                    14:14
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SHIFT                   _MK_SHIFT_CONST(15)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_RANGE                   15:15
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SHIFT                       _MK_SHIFT_CONST(16)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_FDCDRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_RANGE                       16:16
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SHIFT                 _MK_SHIFT_CONST(17)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2DR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_RANGE                 17:17
+#define MC_AP_CTRL_0_0_G2DR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SHIFT                   _MK_SHIFT_CONST(18)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_RANGE                   18:18
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SHIFT                      _MK_SHIFT_CONST(19)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_HOST1XR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_RANGE                      19:19
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SHIFT                       _MK_SHIFT_CONST(20)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_IDXSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_RANGE                       20:20
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SHIFT                      _MK_SHIFT_CONST(21)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPCORER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_RANGE                      21:21
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SHIFT                    _MK_SHIFT_CONST(22)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_RANGE                    22:22
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SHIFT                    _MK_SHIFT_CONST(23)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_RANGE                    23:23
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SHIFT                      _MK_SHIFT_CONST(24)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPECSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_RANGE                      24:24
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SHIFT                  _MK_SHIFT_CONST(25)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_RANGE                  25:25
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SHIFT                  _MK_SHIFT_CONST(26)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_RANGE                  26:26
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_SHIFT                    _MK_SHIFT_CONST(27)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_PPCSARM7R_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_RANGE                    27:27
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSARM7R_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SHIFT                       _MK_SHIFT_CONST(28)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_TEXSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_RANGE                       28:28
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_SHIFT                     _MK_SHIFT_CONST(29)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEBSEAR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_RANGE                     29:29
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEAR_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SHIFT                     _MK_SHIFT_CONST(30)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_RANGE                     30:30
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEMBER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_RANGE                      31:31
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register MC_AP_CTRL_1_0  
+#define MC_AP_CTRL_1_0                  _MK_ADDR_CONST(0xe4)
+#define MC_AP_CTRL_1_0_WORD_COUNT                       0x1
+#define MC_AP_CTRL_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_RESET_MASK                       _MK_MASK_CONST(0xffffff)
+#define MC_AP_CTRL_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_READ_MASK                        _MK_MASK_CONST(0xffffff)
+#define MC_AP_CTRL_1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEMCER_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_RANGE                      0:0
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMCER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_SHIFT                      _MK_SHIFT_CONST(1)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDETPER_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_RANGE                      1:1
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SHIFT                 _MK_SHIFT_CONST(2)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPU_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_RANGE                 2:2
+#define MC_AP_CTRL_1_0_EPPU_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SHIFT                 _MK_SHIFT_CONST(3)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPV_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_RANGE                 3:3
+#define MC_AP_CTRL_1_0_EPPV_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPY_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_RANGE                 4:4
+#define MC_AP_CTRL_1_0_EPPY_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SHIFT                    _MK_SHIFT_CONST(5)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_RANGE                    5:5
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SHIFT                        _MK_SHIFT_CONST(6)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWSB_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_RANGE                        6:6
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SHIFT                 _MK_SHIFT_CONST(7)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWU_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_RANGE                 7:7
+#define MC_AP_CTRL_1_0_VIWU_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWV_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_RANGE                 8:8
+#define MC_AP_CTRL_1_0_VIWV_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SHIFT                 _MK_SHIFT_CONST(9)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWY_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_RANGE                 9:9
+#define MC_AP_CTRL_1_0_VIWY_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SHIFT                 _MK_SHIFT_CONST(10)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_G2DW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_RANGE                 10:10
+#define MC_AP_CTRL_1_0_G2DW_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_CMCW_APVAL_SHIFT                 _MK_SHIFT_CONST(11)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_CMCW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_RANGE                 11:11
+#define MC_AP_CTRL_1_0_CMCW_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_CMCW_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_CMCW_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_CMCW_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_FDCDWR_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_RANGE                       12:12
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SHIFT                      _MK_SHIFT_CONST(13)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_HOST1XW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_RANGE                      13:13
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SHIFT                 _MK_SHIFT_CONST(14)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_ISPW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_RANGE                 14:14
+#define MC_AP_CTRL_1_0_ISPW_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPCOREW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_RANGE                      15:15
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SHIFT                      _MK_SHIFT_CONST(16)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPECSWR_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_RANGE                      16:16
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SHIFT                  _MK_SHIFT_CONST(17)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_RANGE                  17:17
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SHIFT                  _MK_SHIFT_CONST(18)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_RANGE                  18:18
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_SHIFT                    _MK_SHIFT_CONST(19)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_PPCSARM7W_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_RANGE                    19:19
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSARM7W_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_SHIFT                     _MK_SHIFT_CONST(20)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEBSEAW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_RANGE                     20:20
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEAW_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SHIFT                     _MK_SHIFT_CONST(21)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_RANGE                     21:21
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SHIFT                      _MK_SHIFT_CONST(22)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEMBEW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_RANGE                      22:22
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SHIFT                      _MK_SHIFT_CONST(23)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDETPMW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_RANGE                      23:23
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register MC_FPRI_CTRL_CMC_0  
+#define MC_FPRI_CTRL_CMC_0                      _MK_ADDR_CONST(0xe8)
+#define MC_FPRI_CTRL_CMC_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_CMC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_CMC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_CMC_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_CMC_0_CMCR_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_CMC_0_CMCW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_DC_0  
+#define MC_FPRI_CTRL_DC_0                       _MK_ADDR_CONST(0xec)
+#define MC_FPRI_CTRL_DC_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_DC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_RESET_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_READ_MASK                     _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_WRITE_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_RANGE                        3:2
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_RANGE                        5:4
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SHIFT                        _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_RANGE                        7:6
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_RANGE                        9:8
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_DCB_0  
+#define MC_FPRI_CTRL_DCB_0                      _MK_ADDR_CONST(0xf0)
+#define MC_FPRI_CTRL_DCB_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_DCB_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_RANGE                      5:4
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_RANGE                      7:6
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_RANGE                      9:8
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_EPP_0  
+#define MC_FPRI_CTRL_EPP_0                      _MK_ADDR_CONST(0xf4)
+#define MC_FPRI_CTRL_EPP_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_EPP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_RANGE                   1:0
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_RANGE                    5:4
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_RANGE                    7:6
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_G2_0  
+#define MC_FPRI_CTRL_G2_0                       _MK_ADDR_CONST(0xf8)
+#define MC_FPRI_CTRL_G2_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_G2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_RANGE                     1:0
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_RANGE                     3:2
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_RANGE                     5:4
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_RANGE                     7:6
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_HC_0  
+#define MC_FPRI_CTRL_HC_0                       _MK_ADDR_CONST(0xfc)
+#define MC_FPRI_CTRL_HC_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_HC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_RESET_MASK                    _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_READ_MASK                     _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_WRITE_MASK                    _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_FIELD                       (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_RANGE                       1:0
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_WOFFSET                     0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_INIT_ENUM                   LOWEST
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_LOWEST                      _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_LOW                 _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_MED                 _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_HIGH                        _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SHIFT                  _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_FIELD                  (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_RANGE                  3:2
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_WOFFSET                        0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_INIT_ENUM                      LOWEST
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_LOWEST                 _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_LOW                    _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_MED                    _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_HIGH                   _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SHIFT                  _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_FIELD                  (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_RANGE                  5:4
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_WOFFSET                        0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_INIT_ENUM                      LOWEST
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_LOWEST                 _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_LOW                    _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_MED                    _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_HIGH                   _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_ISP_0  
+#define MC_FPRI_CTRL_ISP_0                      _MK_ADDR_CONST(0x100)
+#define MC_FPRI_CTRL_ISP_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_ISP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_RESET_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_READ_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPCORE_0  
+#define MC_FPRI_CTRL_MPCORE_0                   _MK_ADDR_CONST(0x104)
+#define MC_FPRI_CTRL_MPCORE_0_WORD_COUNT                        0x1
+#define MC_FPRI_CTRL_MPCORE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_RESET_MASK                        _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEA_0  
+#define MC_FPRI_CTRL_MPEA_0                     _MK_ADDR_CONST(0x108)
+#define MC_FPRI_CTRL_MPEA_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEB_0  
+#define MC_FPRI_CTRL_MPEB_0                     _MK_ADDR_CONST(0x10c)
+#define MC_FPRI_CTRL_MPEB_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_READ_MASK                   _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_RANGE                      5:4
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEC_0  
+#define MC_FPRI_CTRL_MPEC_0                     _MK_ADDR_CONST(0x110)
+#define MC_FPRI_CTRL_MPEC_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_RANGE                        3:2
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_NV_0  
+#define MC_FPRI_CTRL_NV_0                       _MK_ADDR_CONST(0x114)
+#define MC_FPRI_CTRL_NV_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_NV_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_RANGE                   1:0
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_RANGE                   3:2
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_RANGE                   5:4
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_RANGE                   7:6
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_PPCS_0  
+#define MC_FPRI_CTRL_PPCS_0                     _MK_ADDR_CONST(0x118)
+#define MC_FPRI_CTRL_PPCS_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_PPCS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_RESET_MASK                  _MK_MASK_CONST(0xfff)
+#define MC_FPRI_CTRL_PPCS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_READ_MASK                   _MK_MASK_CONST(0xfff)
+#define MC_FPRI_CTRL_PPCS_0_WRITE_MASK                  _MK_MASK_CONST(0xfff)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_RANGE                      5:4
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7R_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_RANGE                    7:6
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_RANGE                    9:8
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_SHIFT                      _MK_SHIFT_CONST(10)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_RANGE                      11:10
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_INIT_ENUM                  LOWEST
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSARM7W_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_VDE_0  
+#define MC_FPRI_CTRL_VDE_0                      _MK_ADDR_CONST(0x11c)
+#define MC_FPRI_CTRL_VDE_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_VDE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_RESET_MASK                   _MK_MASK_CONST(0x3ffff)
+#define MC_FPRI_CTRL_VDE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_READ_MASK                    _MK_MASK_CONST(0x3ffff)
+#define MC_FPRI_CTRL_VDE_0_WRITE_MASK                   _MK_MASK_CONST(0x3ffff)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAR_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_RANGE                        3:2
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_RANGE                 5:4
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_INIT_ENUM                     LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_RANGE                 7:6
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_INIT_ENUM                     LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_RANGE                 9:8
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_INIT_ENUM                     LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_SHIFT                        _MK_SHIFT_CONST(10)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_RANGE                        11:10
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEAW_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_RANGE                        13:12
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_INIT_ENUM                    LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SHIFT                 _MK_SHIFT_CONST(14)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_RANGE                 15:14
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_INIT_ENUM                     LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SHIFT                 _MK_SHIFT_CONST(16)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_RANGE                 17:16
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_INIT_ENUM                     LOWEST
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_VI_0  
+#define MC_FPRI_CTRL_VI_0                       _MK_ADDR_CONST(0x120)
+#define MC_FPRI_CTRL_VI_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_VI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_RESET_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_READ_MASK                     _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_WRITE_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_INIT_ENUM                        LOWEST
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_RANGE                     5:4
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_RANGE                     7:6
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_RANGE                     9:8
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+
+// Register MC_TIMEOUT_CMC_0  
+#define MC_TIMEOUT_CMC_0                        _MK_ADDR_CONST(0x124)
+#define MC_TIMEOUT_CMC_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_CMC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_CMC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_CMC_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_CMC_0_CMCR_TMVAL_SHIFT)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_CMCR_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_CMC_0_CMCW_TMVAL_SHIFT)
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CMC_0_CMCW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_DC_0  
+#define MC_TIMEOUT_DC_0                 _MK_ADDR_CONST(0x128)
+#define MC_TIMEOUT_DC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_DC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_RANGE                   11:8
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_RANGE                   15:12
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_RANGE                   19:16
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_DCB_0  
+#define MC_TIMEOUT_DCB_0                        _MK_ADDR_CONST(0x12c)
+#define MC_TIMEOUT_DCB_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_DCB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_RANGE                 11:8
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SHIFT                 _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_RANGE                 15:12
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SHIFT                 _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_RANGE                 19:16
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_EPP_0  
+#define MC_TIMEOUT_EPP_0                        _MK_ADDR_CONST(0x130)
+#define MC_TIMEOUT_EPP_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_EPP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_RANGE                      3:0
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPU_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPV_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_RANGE                       11:8
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPY_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_RANGE                       15:12
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_G2_0  
+#define MC_TIMEOUT_G2_0                 _MK_ADDR_CONST(0x134)
+#define MC_TIMEOUT_G2_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_G2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2PR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_RANGE                        3:0
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2SR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_RANGE                        7:4
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2DR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_RANGE                        11:8
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2DW_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_RANGE                        15:12
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_HC_0  
+#define MC_TIMEOUT_HC_0                 _MK_ADDR_CONST(0x138)
+#define MC_TIMEOUT_HC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_HC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_READ_MASK                       _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_FIELD                  (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_RANGE                  3:0
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_RANGE                     7:4
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_RANGE                     11:8
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_ISP_0  
+#define MC_TIMEOUT_ISP_0                        _MK_ADDR_CONST(0x13c)
+#define MC_TIMEOUT_ISP_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_ISP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_ISP_0_ISPW_TMVAL_SHIFT)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPCORE_0  
+#define MC_TIMEOUT_MPCORE_0                     _MK_ADDR_CONST(0x140)
+#define MC_TIMEOUT_MPCORE_0_WORD_COUNT                  0x1
+#define MC_TIMEOUT_MPCORE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEA_0  
+#define MC_TIMEOUT_MPEA_0                       _MK_ADDR_CONST(0x144)
+#define MC_TIMEOUT_MPEA_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEA_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEB_0  
+#define MC_TIMEOUT_MPEB_0                       _MK_ADDR_CONST(0x148)
+#define MC_TIMEOUT_MPEB_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_RESET_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_READ_MASK                     _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_WRITE_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_RANGE                 11:8
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEC_0  
+#define MC_TIMEOUT_MPEC_0                       _MK_ADDR_CONST(0x14c)
+#define MC_TIMEOUT_MPEC_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_NV_0  
+#define MC_TIMEOUT_NV_0                 _MK_ADDR_CONST(0x150)
+#define MC_TIMEOUT_NV_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_NV_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_RANGE                      3:0
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_RANGE                      7:4
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_RANGE                      11:8
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_RANGE                      15:12
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_PPCS_0  
+#define MC_TIMEOUT_PPCS_0                       _MK_ADDR_CONST(0x154)
+#define MC_TIMEOUT_PPCS_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_PPCS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_RESET_MASK                    _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_PPCS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_READ_MASK                     _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_PPCS_0_WRITE_MASK                    _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_RANGE                 11:8
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7R_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_RANGE                       15:12
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SHIFT                       _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_RANGE                       19:16
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_SHIFT                 _MK_SHIFT_CONST(20)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_RANGE                 23:20
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSARM7W_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_VDE_0  
+#define MC_TIMEOUT_VDE_0                        _MK_ADDR_CONST(0x158)
+#define MC_TIMEOUT_VDE_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_VDE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_VDE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_VDE_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEAR_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_RANGE                    11:8
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_RANGE                    15:12
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SHIFT                    _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_RANGE                    19:16
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_SHIFT                   _MK_SHIFT_CONST(20)
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_RANGE                   23:20
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEAW_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SHIFT                   _MK_SHIFT_CONST(24)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_RANGE                   27:24
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_RANGE                    31:28
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT1_VDE_0  
+#define MC_TIMEOUT1_VDE_0                       _MK_ADDR_CONST(0x15c)
+#define MC_TIMEOUT1_VDE_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT1_VDE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_VDE_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT1_VDE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_VDE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_VDE_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT1_VDE_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_SHIFT)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_VDE_0_VDETPMW_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_VI_0  
+#define MC_TIMEOUT_VI_0                 _MK_ADDR_CONST(0x160)
+#define MC_TIMEOUT_VI_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_VI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIRUV_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWSB_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWU_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_RANGE                        11:8
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWV_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_RANGE                        15:12
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWY_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_RANGE                        19:16
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_CMC_0  
+#define MC_TIMEOUT_RCOAL_CMC_0                  _MK_ADDR_CONST(0x164)
+#define MC_TIMEOUT_RCOAL_CMC_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_CMC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_CMC_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_CMC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_CMC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_CMC_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_CMC_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_CMC_0_CMCR_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_DC_0  
+#define MC_TIMEOUT_RCOAL_DC_0                   _MK_ADDR_CONST(0x168)
+#define MC_TIMEOUT_RCOAL_DC_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_DC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_RESET_MASK                        _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_READ_MASK                         _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DC_0_WRITE_MASK                        _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_RANGE                       11:8
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_RANGE                       15:12
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_RANGE                       19:16
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_DCB_0  
+#define MC_TIMEOUT_RCOAL_DCB_0                  _MK_ADDR_CONST(0x16c)
+#define MC_TIMEOUT_RCOAL_DCB_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_DCB_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_WRITE_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_RANGE                     3:0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_RANGE                     7:4
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_RANGE                     11:8
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_RANGE                     15:12
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_RANGE                     19:16
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_EPP_0  
+#define MC_TIMEOUT_RCOAL_EPP_0                  _MK_ADDR_CONST(0x170)
+#define MC_TIMEOUT_RCOAL_EPP_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_EPP_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_EPP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_EPP_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_RANGE                  3:0
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_G2_0  
+#define MC_TIMEOUT_RCOAL_G2_0                   _MK_ADDR_CONST(0x174)
+#define MC_TIMEOUT_RCOAL_G2_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_G2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_RESET_MASK                        _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_G2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_READ_MASK                         _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_G2_0_WRITE_MASK                        _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_RANGE                    3:0
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_RANGE                    7:4
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_RANGE                    11:8
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_HC_0  
+#define MC_TIMEOUT_RCOAL_HC_0                   _MK_ADDR_CONST(0x178)
+#define MC_TIMEOUT_RCOAL_HC_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_HC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_HC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_HC_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_RANGE                      3:0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPCORE_0  
+#define MC_TIMEOUT_RCOAL_MPCORE_0                       _MK_ADDR_CONST(0x17c)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_RCOAL_MPCORE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_RANGE                     3:0
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEA_0  
+#define MC_TIMEOUT_RCOAL_MPEA_0                 _MK_ADDR_CONST(0x180)
+#define MC_TIMEOUT_RCOAL_MPEA_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_RESET_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_READ_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEA_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_RANGE                     3:0
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEB_0  
+#define MC_TIMEOUT_RCOAL_MPEB_0                 _MK_ADDR_CONST(0x184)
+#define MC_TIMEOUT_RCOAL_MPEB_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_RANGE                     3:0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_RANGE                     7:4
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEC_0  
+#define MC_TIMEOUT_RCOAL_MPEC_0                 _MK_ADDR_CONST(0x188)
+#define MC_TIMEOUT_RCOAL_MPEC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_RESET_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_READ_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEC_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_NV_0  
+#define MC_TIMEOUT_RCOAL_NV_0                   _MK_ADDR_CONST(0x18c)
+#define MC_TIMEOUT_RCOAL_NV_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_NV_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_NV_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_NV_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_RANGE                  3:0
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_RANGE                  7:4
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_PPCS_0  
+#define MC_TIMEOUT_RCOAL_PPCS_0                 _MK_ADDR_CONST(0x190)
+#define MC_TIMEOUT_RCOAL_PPCS_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_PPCS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_READ_MASK                       _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_RANGE                     11:8
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSARM7R_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_VDE_0  
+#define MC_TIMEOUT_RCOAL_VDE_0                  _MK_ADDR_CONST(0x194)
+#define MC_TIMEOUT_RCOAL_VDE_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_VDE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_WRITE_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEAR_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_RANGE                        11:8
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_RANGE                        15:12
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_RANGE                        19:16
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_VI_0  
+#define MC_TIMEOUT_RCOAL_VI_0                   _MK_ADDR_CONST(0x198)
+#define MC_TIMEOUT_RCOAL_VI_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_VI_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_RESET_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VI_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_CLIENT_BWSHARE_DISABLE       0
+#define MC_CLIENT_BWSHARE_ENABLE        1
+
+// Register MC_BWSHARE_EMEM_CTRL_0_0  
+#define MC_BWSHARE_EMEM_CTRL_0_0                        _MK_ADDR_CONST(0x19c)
+#define MC_BWSHARE_EMEM_CTRL_0_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EMEM_CTRL_0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_RANGE                        0:0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_RANGE                       1:1
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_RANGE                        2:2
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_RANGE                       3:3
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_RANGE                        4:4
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(5)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_RANGE                       5:5
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(6)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_RANGE                        6:6
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(7)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_RANGE                       7:7
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_RANGE                    8:8
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(9)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_RANGE                     9:9
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(10)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_RANGE                     10:10
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_RANGE                        11:11
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_RANGE                    12:12
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(13)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_RANGE                     13:13
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_CMCR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_RANGE                        14:14
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(15)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_RANGE                       15:15
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_RANGE                   16:16
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(17)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_RANGE                     17:17
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(18)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_RANGE                       18:18
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_RANGE                  19:19
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(20)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_RANGE                   20:20
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(21)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_RANGE                  21:21
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(22)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_RANGE                        22:22
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(23)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_RANGE                        23:23
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(24)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_RANGE                  24:24
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(25)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_RANGE                      25:25
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(26)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_RANGE                      26:26
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_RANGE                        27:27
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSARM7R_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_RANGE                   28:28
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(29)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_RANGE                 29:29
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEAR_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(30)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_RANGE                 30:30
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(31)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_RANGE                  31:31
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_EMEM_CTRL_1_0  
+#define MC_BWSHARE_EMEM_CTRL_1_0                        _MK_ADDR_CONST(0x1a0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EMEM_CTRL_1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_RANGE                  0:0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMCER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_RANGE                  1:1
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(2)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_RANGE                     2:2
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(3)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_RANGE                     3:3
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_RANGE                     4:4
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_RANGE                        5:5
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_RANGE                    6:6
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(7)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_RANGE                     7:7
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_RANGE                     8:8
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(9)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_RANGE                     9:9
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(10)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_RANGE                     10:10
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_RANGE                     11:11
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_CMCW_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_RANGE                   12:12
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(13)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_RANGE                  13:13
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(14)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_RANGE                     14:14
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(15)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_RANGE                  15:15
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(16)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_RANGE                  16:16
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(17)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_RANGE                      17:17
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(18)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_RANGE                      18:18
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_RANGE                        19:19
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSARM7W_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(20)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_RANGE                 20:20
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEAW_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(21)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_RANGE                 21:21
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(22)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_RANGE                  22:22
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(23)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_RANGE                  23:23
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_INCVAL_SIZE  11
+#define MC_BWSHARE_HIGHTH_SIZE  8
+#define MC_BWSHARE_MAXTH_SIZE   8
+#define MC_BWSHARE_ALWAYSINC_DISABLE    0
+#define MC_BWSHARE_ALWAYSINC_ENABLE     1
+#define MC_BWSHARE_TMSFACTORSEL_1       0
+#define MC_BWSHARE_TMSFACTORSEL_2       1
+
+// Register MC_BWSHARE_CMC_0  
+#define MC_BWSHARE_CMC_0                        _MK_ADDR_CONST(0x1a4)
+#define MC_BWSHARE_CMC_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_CMC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_CMC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_CMC_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_CMC_0_CMC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_CMC_0_CMC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_CMC_0_CMC_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_CMC_0_CMC_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_DISPLAY_0  
+#define MC_BWSHARE_DISPLAY_0                    _MK_ADDR_CONST(0x1a8)
+#define MC_BWSHARE_DISPLAY_0_WORD_COUNT                         0x1
+#define MC_BWSHARE_DISPLAY_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_RESET_MASK                         _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_READ_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAY_0_WRITE_MASK                         _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAY_0_DISPLAY_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_DISPLAYB_0  
+#define MC_BWSHARE_DISPLAYB_0                   _MK_ADDR_CONST(0x1ac)
+#define MC_BWSHARE_DISPLAYB_0_WORD_COUNT                        0x1
+#define MC_BWSHARE_DISPLAYB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_RESET_MASK                        _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAYB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_READ_MASK                         _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAYB_0_WRITE_MASK                        _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DISPLAYB_0_DISPLAYB_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_EPP_0  
+#define MC_BWSHARE_EPP_0                        _MK_ADDR_CONST(0x1b0)
+#define MC_BWSHARE_EPP_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EPP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_FDC_0  
+#define MC_BWSHARE_FDC_0                        _MK_ADDR_CONST(0x1b4)
+#define MC_BWSHARE_FDC_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_FDC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_FDC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_FDC_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_FDC_0_FDC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_FDC_0_FDC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_FDC_0_FDC_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_FDC_0_FDC_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_GR2D_0  
+#define MC_BWSHARE_GR2D_0                       _MK_ADDR_CONST(0x1b8)
+#define MC_BWSHARE_GR2D_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_GR2D_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_GR2D_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_GR2D_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_GR2D_0_GR2D_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_HOST1X_0  
+#define MC_BWSHARE_HOST1X_0                     _MK_ADDR_CONST(0x1bc)
+#define MC_BWSHARE_HOST1X_0_WORD_COUNT                  0x1
+#define MC_BWSHARE_HOST1X_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_RESET_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HOST1X_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_READ_MASK                   _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HOST1X_0_WRITE_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HOST1X_0_HOST1X_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_IDX_0  
+#define MC_BWSHARE_IDX_0                        _MK_ADDR_CONST(0x1c0)
+#define MC_BWSHARE_IDX_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_IDX_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_IDX_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_IDX_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_IDX_0_IDX_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_IDX_0_IDX_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_IDX_0_IDX_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_IDX_0_IDX_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_ISP_0  
+#define MC_BWSHARE_ISP_0                        _MK_ADDR_CONST(0x1c4)
+#define MC_BWSHARE_ISP_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_ISP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPCORE_0  
+#define MC_BWSHARE_MPCORE_0                     _MK_ADDR_CONST(0x1c8)
+#define MC_BWSHARE_MPCORE_0_WORD_COUNT                  0x1
+#define MC_BWSHARE_MPCORE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_RESET_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_READ_MASK                   _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_WRITE_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEA_0  
+#define MC_BWSHARE_MPEA_0                       _MK_ADDR_CONST(0x1cc)
+#define MC_BWSHARE_MPEA_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEA_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEB_0  
+#define MC_BWSHARE_MPEB_0                       _MK_ADDR_CONST(0x1d0)
+#define MC_BWSHARE_MPEB_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEC_0  
+#define MC_BWSHARE_MPEC_0                       _MK_ADDR_CONST(0x1d4)
+#define MC_BWSHARE_MPEC_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_PPCS_0  
+#define MC_BWSHARE_PPCS_0                       _MK_ADDR_CONST(0x1d8)
+#define MC_BWSHARE_PPCS_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_PPCS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_TEX_0  
+#define MC_BWSHARE_TEX_0                        _MK_ADDR_CONST(0x1dc)
+#define MC_BWSHARE_TEX_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_TEX_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_TEX_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_TEX_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_TEX_0_TEX_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_TEX_0_TEX_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_TEX_0_TEX_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_TEX_0_TEX_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_VDE_0  
+#define MC_BWSHARE_VDE_0                        _MK_ADDR_CONST(0x1e0)
+#define MC_BWSHARE_VDE_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_VDE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_VI_0  
+#define MC_BWSHARE_VI_0                 _MK_ADDR_CONST(0x1e4)
+#define MC_BWSHARE_VI_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_VI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_VI_0_VI_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_VI_0_VI_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_VI_0_VI_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_TMVAL_0  
+#define MC_BWSHARE_TMVAL_0                      _MK_ADDR_CONST(0x1e8)
+#define MC_BWSHARE_TMVAL_0_WORD_COUNT                   0x1
+#define MC_BWSHARE_TMVAL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_FIELD                 (_MK_MASK_CONST(0xf) << MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SHIFT)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_RANGE                 3:0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_WOFFSET                       0x0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_FIELD                 (_MK_MASK_CONST(0xf) << MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SHIFT)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_RANGE                 7:4
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_WOFFSET                       0x0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_AXI_DECERR_OVR_0  
+#define MC_AXI_DECERR_OVR_0                     _MK_ADDR_CONST(0x1ec)
+#define MC_AXI_DECERR_OVR_0_WORD_COUNT                  0x1
+#define MC_AXI_DECERR_OVR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define MC_AXI_DECERR_OVR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define MC_AXI_DECERR_OVR_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_FIELD                       (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_RANGE                       0:0
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_WOFFSET                     0x0
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_INIT_ENUM                   DISABLE
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_DECERR_ALLOWED                      _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_ALWAYS_OK                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCR_DECERR_OVR_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_FIELD                       (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_RANGE                       1:1
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_WOFFSET                     0x0
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_INIT_ENUM                   DISABLE
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_DECERR_ALLOWED                      _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_ALWAYS_OK                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_CMCW_DECERR_OVR_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_RANGE                    2:2
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_WOFFSET                  0x0
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_INIT_ENUM                        DISABLE
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DECERR_ALLOWED                   _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ALWAYS_OK                        _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SHIFT                    _MK_SHIFT_CONST(3)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_RANGE                    3:3
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_WOFFSET                  0x0
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_INIT_ENUM                        DISABLE
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DECERR_ALLOWED                   _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ALWAYS_OK                        _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_LL_CTRL_DISABLE       0
+#define MC_CLIENT_LL_CTRL_ENABLE        1
+
+// Register MC_LOWLATENCY_CONFIG_0  
+#define MC_LOWLATENCY_CONFIG_0                  _MK_ADDR_CONST(0x1f0)
+#define MC_LOWLATENCY_CONFIG_0_WORD_COUNT                       0x1
+#define MC_LOWLATENCY_CONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x8000000f)
+#define MC_LOWLATENCY_CONFIG_0_RESET_MASK                       _MK_MASK_CONST(0x8000000f)
+#define MC_LOWLATENCY_CONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_READ_MASK                        _MK_MASK_CONST(0x8000000f)
+#define MC_LOWLATENCY_CONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0x8000000f)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_RANGE                       0:0
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_WOFFSET                     0x0
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_CTRL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_SHIFT                  _MK_SHIFT_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_FIELD                  (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_RANGE                  1:1
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_WOFFSET                        0x0
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_INIT_ENUM                      ENABLE
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_CMCR_LL_SEND_BOTH_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_RANGE                    2:2
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_WOFFSET                  0x0
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_RANGE                       3:3
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_WOFFSET                     0x0
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SHIFT                 _MK_SHIFT_CONST(31)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_FIELD                 (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_RANGE                 31:31
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_WOFFSET                       0x0
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_INIT_ENUM                     ENABLE
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0  
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0                     _MK_ADDR_CONST(0x1f4)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_WORD_COUNT                  0x1
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_RESET_VAL                   _MK_MASK_CONST(0x3fffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_RESET_MASK                  _MK_MASK_CONST(0x3fffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_RANGE                       0:0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_RANGE                       1:1
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_RANGE                       2:2
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SHIFT                  _MK_SHIFT_CONST(3)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_FIELD                  (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_RANGE                  3:3
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_WOFFSET                        0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_INIT_ENUM                      ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_FIELD                      (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_RANGE                      4:4
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_WOFFSET                    0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_INIT_ENUM                  ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(5)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_RANGE                       5:5
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_RANGE                       6:6
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(7)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_RANGE                       7:7
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_RANGE                       8:8
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(9)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_RANGE                       9:9
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_CMCW_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SHIFT                     _MK_SHIFT_CONST(10)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_FIELD                     (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_RANGE                     10:10
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_WOFFSET                   0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_INIT_ENUM                 ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_RANGE                    11:11
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_RANGE                       12:12
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(13)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_RANGE                    13:13
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(14)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_RANGE                    14:14
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SHIFT                        _MK_SHIFT_CONST(15)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_FIELD                        (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_RANGE                        15:15
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_WOFFSET                      0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_INIT_ENUM                    ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_FIELD                        (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_RANGE                        16:16
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_WOFFSET                      0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_INIT_ENUM                    ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_SHIFT                  _MK_SHIFT_CONST(17)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_FIELD                  (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_RANGE                  17:17
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_WOFFSET                        0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_INIT_ENUM                      ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSARM7W_LL_RAW_PARTICIPATE_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_SHIFT                   _MK_SHIFT_CONST(18)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_FIELD                   (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_RANGE                   18:18
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_WOFFSET                 0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_INIT_ENUM                       ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEAW_LL_RAW_PARTICIPATE_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_FIELD                   (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_RANGE                   19:19
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_WOFFSET                 0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_INIT_ENUM                       ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(20)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_RANGE                    20:20
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(21)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_RANGE                    21:21
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_INACTIVE     0
+#define MC_CLIENT_ACTIVITY_MONITOR_ACTIVE       1
+
+// Register MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0  
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0                     _MK_ADDR_CONST(0x1f8)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_WORD_COUNT                  0x1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_RANGE                       0:0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_RANGE                      1:1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_RANGE                       2:2
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(3)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_RANGE                      3:3
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_RANGE                       4:4
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(5)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_RANGE                      5:5
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_RANGE                       6:6
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(7)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_RANGE                      7:7
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_RANGE                   8:8
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(9)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_RANGE                    9:9
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(10)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_RANGE                    10:10
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(11)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_RANGE                       11:11
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_RANGE                   12:12
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(13)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_RANGE                    13:13
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_CMCR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(14)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_RANGE                       14:14
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_RANGE                      15:15
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(16)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_RANGE                  16:16
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(17)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_RANGE                    17:17
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(18)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_RANGE                      18:18
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(19)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_RANGE                 19:19
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(20)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_RANGE                  20:20
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(21)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_RANGE                 21:21
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(22)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_RANGE                       22:22
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(23)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_RANGE                       23:23
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(24)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_RANGE                 24:24
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(25)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_RANGE                     25:25
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(26)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_RANGE                     26:26
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_RANGE                       27:27
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSARM7R_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(28)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_RANGE                  28:28
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(29)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_RANGE                        29:29
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEAR_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(30)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_RANGE                        30:30
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(31)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_RANGE                 31:31
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+
+// Register MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0  
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0                     _MK_ADDR_CONST(0x1fc)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_WORD_COUNT                  0x1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_RANGE                 0:0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMCER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_RANGE                 1:1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_RANGE                    2:2
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(3)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_RANGE                    3:3
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_RANGE                    4:4
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(5)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_RANGE                       5:5
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_RANGE                   6:6
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_RANGE                    7:7
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_RANGE                    8:8
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(9)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_RANGE                    9:9
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(10)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_RANGE                    10:10
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_RANGE                    11:11
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_CMCW_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(12)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_RANGE                  12:12
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(13)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_RANGE                 13:13
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(14)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_RANGE                    14:14
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(15)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_RANGE                 15:15
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(16)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_RANGE                 16:16
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(17)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_RANGE                     17:17
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(18)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_RANGE                     18:18
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_RANGE                       19:19
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSARM7W_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(20)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_RANGE                        20:20
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEAW_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(21)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_RANGE                        21:21
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(22)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_RANGE                 22:22
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(23)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_RANGE                 23:23
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define NV_MC_EMEM_DFIFO_DEPTH  3
+#define NV_MC_IMEM_DFIFO_DEPTH  5
+#define NV_MC_EMEM_APFIFO_DEPTH 4
+#define NV_MC_ARB_EMEM_REGLEVEL 3
+#define NV_MC_EMEM_REQ_ID_WIDEREQ       9
+#define NV_MC_EMEM_RDI_ID_WIDERDI       9
+#define NV_MC_EMEM_REQ_ID_ILLEGALACC    8
+#define NV_MC_EMEM_RDI_ID_ILLEGALACC    8
+#define NV_MC_EMEM_REQ_ID_LLRAWDECR     7
+#define NV_MC_EMEM_RDI_ID_LLRAWDECR     7
+#define NV_MC_EMEM_REQ_ID_APCIGNORE     6
+#define NV_MC_EMEM_RDI_ID_APCIGNORE     6
+
+// Packet MC2EMC
+#define MC2EMC_SIZE 190
+
+#define MC2EMC_WDO_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_SHIFT)
+#define MC2EMC_WDO_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_ROW                  0
+
+#define MC2EMC_WDO_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_0_SHIFT)
+#define MC2EMC_WDO_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_ROW                        0
+
+#define MC2EMC_WDO_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_1_SHIFT)
+#define MC2EMC_WDO_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_ROW                        0
+
+#define MC2EMC_WDO_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_2_SHIFT)
+#define MC2EMC_WDO_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_ROW                        0
+
+#define MC2EMC_WDO_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_3_SHIFT)
+#define MC2EMC_WDO_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_ROW                        0
+
+#define MC2EMC_BE_SHIFT                 _MK_SHIFT_CONST(128)
+#define MC2EMC_BE_FIELD                 (_MK_MASK_CONST(0xffff) << MC2EMC_BE_SHIFT)
+#define MC2EMC_BE_RANGE                 _MK_SHIFT_CONST(143):_MK_SHIFT_CONST(128)
+#define MC2EMC_BE_ROW                   0
+
+#define MC2EMC_DEV_SHIFT                        _MK_SHIFT_CONST(144)
+#define MC2EMC_DEV_FIELD                        (_MK_MASK_CONST(0x3) << MC2EMC_DEV_SHIFT)
+#define MC2EMC_DEV_RANGE                        _MK_SHIFT_CONST(145):_MK_SHIFT_CONST(144)
+#define MC2EMC_DEV_ROW                  0
+
+#define MC2EMC_BANK_SHIFT                       _MK_SHIFT_CONST(146)
+#define MC2EMC_BANK_FIELD                       (_MK_MASK_CONST(0x3) << MC2EMC_BANK_SHIFT)
+#define MC2EMC_BANK_RANGE                       _MK_SHIFT_CONST(147):_MK_SHIFT_CONST(146)
+#define MC2EMC_BANK_ROW                 0
+
+#define MC2EMC_ROW_SHIFT                        _MK_SHIFT_CONST(148)
+#define MC2EMC_ROW_FIELD                        (_MK_MASK_CONST(0x3fff) << MC2EMC_ROW_SHIFT)
+#define MC2EMC_ROW_RANGE                        _MK_SHIFT_CONST(161):_MK_SHIFT_CONST(148)
+#define MC2EMC_ROW_ROW                  0
+
+#define MC2EMC_COL_SHIFT                        _MK_SHIFT_CONST(162)
+#define MC2EMC_COL_FIELD                        (_MK_MASK_CONST(0x7ff) << MC2EMC_COL_SHIFT)
+#define MC2EMC_COL_RANGE                        _MK_SHIFT_CONST(172):_MK_SHIFT_CONST(162)
+#define MC2EMC_COL_ROW                  0
+
+#define MC2EMC_REQ_ID_SHIFT                     _MK_SHIFT_CONST(173)
+#define MC2EMC_REQ_ID_FIELD                     (_MK_MASK_CONST(0x3ff) << MC2EMC_REQ_ID_SHIFT)
+#define MC2EMC_REQ_ID_RANGE                     _MK_SHIFT_CONST(182):_MK_SHIFT_CONST(173)
+#define MC2EMC_REQ_ID_ROW                       0
+
+#define MC2EMC_AP_SHIFT                 _MK_SHIFT_CONST(183)
+#define MC2EMC_AP_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_AP_SHIFT)
+#define MC2EMC_AP_RANGE                 _MK_SHIFT_CONST(183):_MK_SHIFT_CONST(183)
+#define MC2EMC_AP_ROW                   0
+
+#define MC2EMC_WE_SHIFT                 _MK_SHIFT_CONST(184)
+#define MC2EMC_WE_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_WE_SHIFT)
+#define MC2EMC_WE_RANGE                 _MK_SHIFT_CONST(184):_MK_SHIFT_CONST(184)
+#define MC2EMC_WE_ROW                   0
+
+#define MC2EMC_TAG_SHIFT                        _MK_SHIFT_CONST(185)
+#define MC2EMC_TAG_FIELD                        (_MK_MASK_CONST(0x1f) << MC2EMC_TAG_SHIFT)
+#define MC2EMC_TAG_RANGE                        _MK_SHIFT_CONST(189):_MK_SHIFT_CONST(185)
+#define MC2EMC_TAG_ROW                  0
+
+
+// Packet MC2EMC_APC
+#define MC2EMC_APC_SIZE 3
+
+#define MC2EMC_APC_CLR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_FIELD                    (_MK_MASK_CONST(0x1) << MC2EMC_APC_CLR_SHIFT)
+#define MC2EMC_APC_CLR_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_ROW                      0
+
+#define MC2EMC_APC_BANK_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_FIELD                   (_MK_MASK_CONST(0x3) << MC2EMC_APC_BANK_SHIFT)
+#define MC2EMC_APC_BANK_RANGE                   _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_ROW                     0
+
+
+// Packet EMC2MC
+#define EMC2MC_SIZE 138
+
+#define EMC2MC_RDI_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_SHIFT)
+#define EMC2MC_RDI_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_ROW                  0
+
+#define EMC2MC_RDI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_0_SHIFT)
+#define EMC2MC_RDI_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_ROW                        0
+
+#define EMC2MC_RDI_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_1_SHIFT)
+#define EMC2MC_RDI_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_ROW                        0
+
+#define EMC2MC_RDI_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_2_SHIFT)
+#define EMC2MC_RDI_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_ROW                        0
+
+#define EMC2MC_RDI_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_3_SHIFT)
+#define EMC2MC_RDI_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_ROW                        0
+
+#define EMC2MC_RDI_ID_SHIFT                     _MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_FIELD                     (_MK_MASK_CONST(0x3ff) << EMC2MC_RDI_ID_SHIFT)
+#define EMC2MC_RDI_ID_RANGE                     _MK_SHIFT_CONST(137):_MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_ROW                       0
+
+
+// Packet MC2EMC_LL
+#define MC2EMC_LL_SIZE 35
+
+#define MC2EMC_LL_DEV_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_DEV_FIELD                     (_MK_MASK_CONST(0x3) << MC2EMC_LL_DEV_SHIFT)
+#define MC2EMC_LL_DEV_RANGE                     _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_DEV_ROW                       0
+
+#define MC2EMC_LL_BANK_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC2EMC_LL_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_BANK_SHIFT)
+#define MC2EMC_LL_BANK_RANGE                    _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(2)
+#define MC2EMC_LL_BANK_ROW                      0
+
+#define MC2EMC_LL_ROW_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC2EMC_LL_ROW_FIELD                     (_MK_MASK_CONST(0x3fff) << MC2EMC_LL_ROW_SHIFT)
+#define MC2EMC_LL_ROW_RANGE                     _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(4)
+#define MC2EMC_LL_ROW_ROW                       0
+
+#define MC2EMC_LL_COL_SHIFT                     _MK_SHIFT_CONST(18)
+#define MC2EMC_LL_COL_FIELD                     (_MK_MASK_CONST(0x7ff) << MC2EMC_LL_COL_SHIFT)
+#define MC2EMC_LL_COL_RANGE                     _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(18)
+#define MC2EMC_LL_COL_ROW                       0
+
+#define MC2EMC_LL_TAG_SHIFT                     _MK_SHIFT_CONST(29)
+#define MC2EMC_LL_TAG_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_TAG_SHIFT)
+#define MC2EMC_LL_TAG_RANGE                     _MK_SHIFT_CONST(33):_MK_SHIFT_CONST(29)
+#define MC2EMC_LL_TAG_ROW                       0
+
+#define MC2EMC_LL_DOUBLEREQ_SHIFT                       _MK_SHIFT_CONST(34)
+#define MC2EMC_LL_DOUBLEREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC2EMC_LL_DOUBLEREQ_SHIFT)
+#define MC2EMC_LL_DOUBLEREQ_RANGE                       _MK_SHIFT_CONST(34):_MK_SHIFT_CONST(34)
+#define MC2EMC_LL_DOUBLEREQ_ROW                 0
+
+
+// Packet EMC2MC_LL
+#define EMC2MC_LL_SIZE 64
+
+#define EMC2MC_LL_RDI_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_FIELD                     (_MK_MASK_CONST(0xffffffff) << EMC2MC_LL_RDI_SHIFT)
+#define EMC2MC_LL_RDI_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_ROW                       0
+
+
+// Packet MC2EMC_LL_CRITINFO
+#define MC2EMC_LL_CRITINFO_SIZE 11
+
+#define MC2EMC_LL_CRITINFO_HP_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_CRITINFO_HP_SHIFT)
+#define MC2EMC_LL_CRITINFO_HP_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_ROW                       0
+
+#define MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_FIELD                        (_MK_MASK_CONST(0x3f) << MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_RANGE                        _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_ROW                  0
+
+
+// Packet MC2EMC_LL_ARBINFO
+#define MC2EMC_LL_ARBINFO_SIZE 2
+
+#define MC2EMC_LL_ARBINFO_BANK_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_ARBINFO_BANK_SHIFT)
+#define MC2EMC_LL_ARBINFO_BANK_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_ROW                      0
+
+
+// Packet CMC2MC_AXI_A
+#define CMC2MC_AXI_A_SIZE 58
+
+#define CMC2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_A_AADDR_SHIFT)
+#define CMC2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_ROW                  0
+
+#define CMC2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_A_AID_SHIFT)
+#define CMC2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_ROW                    0
+
+#define CMC2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define CMC2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ALEN_SHIFT)
+#define CMC2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define CMC2MC_AXI_A_ALEN_ROW                   0
+#define CMC2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define CMC2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define CMC2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define CMC2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define CMC2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define CMC2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_ASIZE_SHIFT)
+#define CMC2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define CMC2MC_AXI_A_ASIZE_ROW                  0
+#define CMC2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define CMC2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define CMC2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ABURST_SHIFT)
+#define CMC2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define CMC2MC_AXI_A_ABURST_ROW                 0
+#define CMC2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ALOCK_SHIFT)
+#define CMC2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ALOCK_ROW                  0
+#define CMC2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define CMC2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ACACHE_SHIFT)
+#define CMC2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define CMC2MC_AXI_A_ACACHE_ROW                 0
+#define CMC2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define CMC2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_APROT_SHIFT)
+#define CMC2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define CMC2MC_AXI_A_APROT_ROW                  0
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet CMC2MC_AXI_W
+#define CMC2MC_AXI_W_SIZE 81
+
+#define CMC2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_W_WDATA_SHIFT)
+#define CMC2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_ROW                  0
+
+#define CMC2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WID_SHIFT)
+#define CMC2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_ROW                    0
+
+#define CMC2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WSTRB_SHIFT)
+#define CMC2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_W_WSTRB_ROW                  0
+
+#define CMC2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(80)
+#define CMC2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_W_WLAST_SHIFT)
+#define CMC2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(80):_MK_SHIFT_CONST(80)
+#define CMC2MC_AXI_W_WLAST_ROW                  0
+#define CMC2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet CMC2MC_AXI_B
+#define CMC2MC_AXI_B_SIZE 10
+
+#define CMC2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_B_BID_SHIFT)
+#define CMC2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_ROW                    0
+
+#define CMC2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(8)
+#define CMC2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_B_BRESP_SHIFT)
+#define CMC2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define CMC2MC_AXI_B_BRESP_ROW                  0
+#define CMC2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet CMC2MC_AXI_R
+#define CMC2MC_AXI_R_SIZE 75
+
+#define CMC2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_R_RDATA_SHIFT)
+#define CMC2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_ROW                  0
+
+#define CMC2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0xff) << CMC2MC_AXI_R_RID_SHIFT)
+#define CMC2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_ROW                    0
+
+#define CMC2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_R_RRESP_SHIFT)
+#define CMC2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(73):_MK_SHIFT_CONST(72)
+#define CMC2MC_AXI_R_RRESP_ROW                  0
+#define CMC2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(74)
+#define CMC2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_R_RLAST_SHIFT)
+#define CMC2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(74):_MK_SHIFT_CONST(74)
+#define CMC2MC_AXI_R_RLAST_ROW                  0
+#define CMC2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_A
+#define MSELECT2MC_AXI_A_SIZE 58
+
+#define MSELECT2MC_AXI_A_AADDR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_A_AADDR_SHIFT)
+#define MSELECT2MC_AXI_A_AADDR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_ROW                      0
+
+#define MSELECT2MC_AXI_A_AID_SHIFT                      _MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_A_AID_SHIFT)
+#define MSELECT2MC_AXI_A_AID_RANGE                      _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_ROW                        0
+
+#define MSELECT2MC_AXI_A_ALEN_SHIFT                     _MK_SHIFT_CONST(40)
+#define MSELECT2MC_AXI_A_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ALEN_SHIFT)
+#define MSELECT2MC_AXI_A_ALEN_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define MSELECT2MC_AXI_A_ALEN_ROW                       0
+#define MSELECT2MC_AXI_A_ALEN_ONEDATA                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALEN_TWODATA                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALEN_THREEDATA                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALEN_FOURDATA                  _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ALEN_FIVEDATA                  _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ALEN_SIXDATA                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ALEN_SEVENDATA                 _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ALEN_EIGHTDATA                 _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ALEN_NINEDATA                  _MK_ENUM_CONST(8)
+#define MSELECT2MC_AXI_A_ALEN_TENDATA                   _MK_ENUM_CONST(9)
+#define MSELECT2MC_AXI_A_ALEN_ELEVENDATA                        _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ALEN_TWELVEDATA                        _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ALEN_THIRTEENDATA                      _MK_ENUM_CONST(12)
+#define MSELECT2MC_AXI_A_ALEN_FOURTEENDATA                      _MK_ENUM_CONST(13)
+#define MSELECT2MC_AXI_A_ALEN_FIFTHTEENDATA                     _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ALEN_SIXTEENDATA                       _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_ASIZE_SHIFT                    _MK_SHIFT_CONST(44)
+#define MSELECT2MC_AXI_A_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_ASIZE_SHIFT)
+#define MSELECT2MC_AXI_A_ASIZE_RANGE                    _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define MSELECT2MC_AXI_A_ASIZE_ROW                      0
+#define MSELECT2MC_AXI_A_ASIZE_ONEBYTE                  _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ASIZE_TWOBYTES                 _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ASIZE_FOURBYTES                        _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ASIZE_EIGHTBYTES                       _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTEENBYTES                     _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ASIZE_THIRTYTWOBYTES                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTYFOURBYTES                   _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                       _MK_ENUM_CONST(7)
+
+#define MSELECT2MC_AXI_A_ABURST_SHIFT                   _MK_SHIFT_CONST(47)
+#define MSELECT2MC_AXI_A_ABURST_FIELD                   (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ABURST_SHIFT)
+#define MSELECT2MC_AXI_A_ABURST_RANGE                   _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define MSELECT2MC_AXI_A_ABURST_ROW                     0
+#define MSELECT2MC_AXI_A_ABURST_FIXED                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ABURST_INCR                    _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ABURST_WRAP                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ABURST_RSVD                    _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ALOCK_SHIFT                    _MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ALOCK_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ALOCK_SHIFT)
+#define MSELECT2MC_AXI_A_ALOCK_RANGE                    _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ALOCK_ROW                      0
+#define MSELECT2MC_AXI_A_ALOCK_NORMAL                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALOCK_EXCLUSIVE                        _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALOCK_LOCKED                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALOCK_RSVD                     _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ACACHE_SHIFT                   _MK_SHIFT_CONST(51)
+#define MSELECT2MC_AXI_A_ACACHE_FIELD                   (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ACACHE_SHIFT)
+#define MSELECT2MC_AXI_A_ACACHE_RANGE                   _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define MSELECT2MC_AXI_A_ACACHE_ROW                     0
+#define MSELECT2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                      _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ACACHE_BUFFERABLE                      _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                      _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                       _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                   _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                      _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                       _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                  _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_APROT_SHIFT                    _MK_SHIFT_CONST(55)
+#define MSELECT2MC_AXI_A_APROT_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_APROT_SHIFT)
+#define MSELECT2MC_AXI_A_APROT_RANGE                    _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define MSELECT2MC_AXI_A_APROT_ROW                      0
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_NORMAL                       _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_NORMAL                       _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(7)
+
+
+// Packet MSELECT2MC_AXI_W
+#define MSELECT2MC_AXI_W_SIZE 81
+
+#define MSELECT2MC_AXI_W_WDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_W_WDATA_SHIFT)
+#define MSELECT2MC_AXI_W_WDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_ROW                      0
+
+#define MSELECT2MC_AXI_W_WID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WID_SHIFT)
+#define MSELECT2MC_AXI_W_WID_RANGE                      _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_ROW                        0
+
+#define MSELECT2MC_AXI_W_WSTRB_SHIFT                    _MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_W_WSTRB_FIELD                    (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WSTRB_SHIFT)
+#define MSELECT2MC_AXI_W_WSTRB_RANGE                    _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_W_WSTRB_ROW                      0
+
+#define MSELECT2MC_AXI_W_WLAST_SHIFT                    _MK_SHIFT_CONST(80)
+#define MSELECT2MC_AXI_W_WLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_W_WLAST_SHIFT)
+#define MSELECT2MC_AXI_W_WLAST_RANGE                    _MK_SHIFT_CONST(80):_MK_SHIFT_CONST(80)
+#define MSELECT2MC_AXI_W_WLAST_ROW                      0
+#define MSELECT2MC_AXI_W_WLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_W_WLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_B
+#define MSELECT2MC_AXI_B_SIZE 10
+
+#define MSELECT2MC_AXI_B_BID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_B_BID_SHIFT)
+#define MSELECT2MC_AXI_B_BID_RANGE                      _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_ROW                        0
+
+#define MSELECT2MC_AXI_B_BRESP_SHIFT                    _MK_SHIFT_CONST(8)
+#define MSELECT2MC_AXI_B_BRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_B_BRESP_SHIFT)
+#define MSELECT2MC_AXI_B_BRESP_RANGE                    _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define MSELECT2MC_AXI_B_BRESP_ROW                      0
+#define MSELECT2MC_AXI_B_BRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_B_BRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_B_BRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_B_BRESP_DECERR                   _MK_ENUM_CONST(3)
+
+
+// Packet MSELECT2MC_AXI_R
+#define MSELECT2MC_AXI_R_SIZE 75
+
+#define MSELECT2MC_AXI_R_RDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_R_RDATA_SHIFT)
+#define MSELECT2MC_AXI_R_RDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_ROW                      0
+
+#define MSELECT2MC_AXI_R_RID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_FIELD                      (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_R_RID_SHIFT)
+#define MSELECT2MC_AXI_R_RID_RANGE                      _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_ROW                        0
+
+#define MSELECT2MC_AXI_R_RRESP_SHIFT                    _MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_R_RRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_R_RRESP_SHIFT)
+#define MSELECT2MC_AXI_R_RRESP_RANGE                    _MK_SHIFT_CONST(73):_MK_SHIFT_CONST(72)
+#define MSELECT2MC_AXI_R_RRESP_ROW                      0
+#define MSELECT2MC_AXI_R_RRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_R_RRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_R_RRESP_DECERR                   _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_R_RLAST_SHIFT                    _MK_SHIFT_CONST(74)
+#define MSELECT2MC_AXI_R_RLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_R_RLAST_SHIFT)
+#define MSELECT2MC_AXI_R_RLAST_RANGE                    _MK_SHIFT_CONST(74):_MK_SHIFT_CONST(74)
+#define MSELECT2MC_AXI_R_RLAST_ROW                      0
+#define MSELECT2MC_AXI_R_RLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_A
+#define AXI2MC_AXI_A_SIZE 58
+
+#define AXI2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_A_AADDR_SHIFT)
+#define AXI2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_ROW                  0
+
+#define AXI2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_A_AID_SHIFT)
+#define AXI2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_ROW                    0
+
+#define AXI2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define AXI2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ALEN_SHIFT)
+#define AXI2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define AXI2MC_AXI_A_ALEN_ROW                   0
+#define AXI2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define AXI2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define AXI2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define AXI2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define AXI2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define AXI2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_ASIZE_SHIFT)
+#define AXI2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define AXI2MC_AXI_A_ASIZE_ROW                  0
+#define AXI2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define AXI2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define AXI2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ABURST_SHIFT)
+#define AXI2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define AXI2MC_AXI_A_ABURST_ROW                 0
+#define AXI2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ALOCK_SHIFT)
+#define AXI2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ALOCK_ROW                  0
+#define AXI2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define AXI2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ACACHE_SHIFT)
+#define AXI2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define AXI2MC_AXI_A_ACACHE_ROW                 0
+#define AXI2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define AXI2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_APROT_SHIFT)
+#define AXI2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define AXI2MC_AXI_A_APROT_ROW                  0
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet AXI2MC_AXI_W
+#define AXI2MC_AXI_W_SIZE 297
+
+#define AXI2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WDATA_SHIFT)
+#define AXI2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_ROW                  0
+
+#define AXI2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_W_WID_SHIFT)
+#define AXI2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(263):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_ROW                    0
+
+#define AXI2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WSTRB_SHIFT)
+#define AXI2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(295):_MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_W_WSTRB_ROW                  0
+
+#define AXI2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(296)
+#define AXI2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_W_WLAST_SHIFT)
+#define AXI2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(296):_MK_SHIFT_CONST(296)
+#define AXI2MC_AXI_W_WLAST_ROW                  0
+#define AXI2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_B
+#define AXI2MC_AXI_B_SIZE 10
+
+#define AXI2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_B_BID_SHIFT)
+#define AXI2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_ROW                    0
+
+#define AXI2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(8)
+#define AXI2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_B_BRESP_SHIFT)
+#define AXI2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define AXI2MC_AXI_B_BRESP_ROW                  0
+#define AXI2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet AXI2MC_AXI_R
+#define AXI2MC_AXI_R_SIZE 267
+
+#define AXI2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_R_RDATA_SHIFT)
+#define AXI2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_ROW                  0
+
+#define AXI2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0xff) << AXI2MC_AXI_R_RID_SHIFT)
+#define AXI2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(263):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_ROW                    0
+
+#define AXI2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_R_RRESP_SHIFT)
+#define AXI2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(265):_MK_SHIFT_CONST(264)
+#define AXI2MC_AXI_R_RRESP_ROW                  0
+#define AXI2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(266)
+#define AXI2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_R_RLAST_SHIFT)
+#define AXI2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(266):_MK_SHIFT_CONST(266)
+#define AXI2MC_AXI_R_RLAST_ROW                  0
+#define AXI2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MC_AXI_RWREQ
+#define MC_AXI_RWREQ_SIZE 107
+
+#define MC_AXI_RWREQ_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_AADDR_SHIFT)
+#define MC_AXI_RWREQ_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_ROW                  0
+
+#define MC_AXI_RWREQ_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_FIELD                  (_MK_MASK_CONST(0xff) << MC_AXI_RWREQ_AID_SHIFT)
+#define MC_AXI_RWREQ_AID_RANGE                  _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_ROW                    0
+
+#define MC_AXI_RWREQ_ALEN_SHIFT                 _MK_SHIFT_CONST(40)
+#define MC_AXI_RWREQ_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ALEN_RANGE                 _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(40)
+#define MC_AXI_RWREQ_ALEN_ROW                   0
+
+#define MC_AXI_RWREQ_ASIZE_SHIFT                        _MK_SHIFT_CONST(44)
+#define MC_AXI_RWREQ_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ASIZE_RANGE                        _MK_SHIFT_CONST(46):_MK_SHIFT_CONST(44)
+#define MC_AXI_RWREQ_ASIZE_ROW                  2
+
+#define MC_AXI_RWREQ_ABURST_SHIFT                       _MK_SHIFT_CONST(47)
+#define MC_AXI_RWREQ_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ABURST_SHIFT)
+#define MC_AXI_RWREQ_ABURST_RANGE                       _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(47)
+#define MC_AXI_RWREQ_ABURST_ROW                 0
+#define MC_AXI_RWREQ_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define MC_AXI_RWREQ_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define MC_AXI_RWREQ_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define MC_AXI_RWREQ_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define MC_AXI_RWREQ_ALOCK_SHIFT                        _MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ALOCK_SHIFT)
+#define MC_AXI_RWREQ_ALOCK_RANGE                        _MK_SHIFT_CONST(50):_MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ALOCK_ROW                  0
+
+#define MC_AXI_RWREQ_ACACHE_SHIFT                       _MK_SHIFT_CONST(51)
+#define MC_AXI_RWREQ_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACACHE_SHIFT)
+#define MC_AXI_RWREQ_ACACHE_RANGE                       _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(51)
+#define MC_AXI_RWREQ_ACACHE_ROW                 0
+
+#define MC_AXI_RWREQ_APROT_SHIFT                        _MK_SHIFT_CONST(55)
+#define MC_AXI_RWREQ_APROT_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_APROT_SHIFT)
+#define MC_AXI_RWREQ_APROT_RANGE                        _MK_SHIFT_CONST(57):_MK_SHIFT_CONST(55)
+#define MC_AXI_RWREQ_APROT_ROW                  0
+
+#define MC_AXI_RWREQ_ASB_SHIFT                  _MK_SHIFT_CONST(58)
+#define MC_AXI_RWREQ_ASB_FIELD                  (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ASB_SHIFT)
+#define MC_AXI_RWREQ_ASB_RANGE                  _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(58)
+#define MC_AXI_RWREQ_ASB_ROW                    0
+
+#define MC_AXI_RWREQ_ARW_SHIFT                  _MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_ARW_FIELD                  (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ARW_SHIFT)
+#define MC_AXI_RWREQ_ARW_RANGE                  _MK_SHIFT_CONST(60):_MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_ARW_ROW                    0
+
+#define MC_AXI_RWREQ_ACT_AADDR_SHIFT                    _MK_SHIFT_CONST(61)
+#define MC_AXI_RWREQ_ACT_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_ACT_AADDR_SHIFT)
+#define MC_AXI_RWREQ_ACT_AADDR_RANGE                    _MK_SHIFT_CONST(92):_MK_SHIFT_CONST(61)
+#define MC_AXI_RWREQ_ACT_AADDR_ROW                      0
+
+#define MC_AXI_RWREQ_ACT_ALEN_SHIFT                     _MK_SHIFT_CONST(93)
+#define MC_AXI_RWREQ_ACT_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACT_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ACT_ALEN_RANGE                     _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(93)
+#define MC_AXI_RWREQ_ACT_ALEN_ROW                       0
+
+#define MC_AXI_RWREQ_ACT_ASIZE_SHIFT                    _MK_SHIFT_CONST(97)
+#define MC_AXI_RWREQ_ACT_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ACT_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ACT_ASIZE_RANGE                    _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(97)
+#define MC_AXI_RWREQ_ACT_ASIZE_ROW                      0
+
+#define MC_AXI_RWREQ_DOUBLEREQ_SHIFT                    _MK_SHIFT_CONST(100)
+#define MC_AXI_RWREQ_DOUBLEREQ_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_DOUBLEREQ_SHIFT)
+#define MC_AXI_RWREQ_DOUBLEREQ_RANGE                    _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define MC_AXI_RWREQ_DOUBLEREQ_ROW                      0
+
+#define MC_AXI_RWREQ_ILLEGALACC_SHIFT                   _MK_SHIFT_CONST(101)
+#define MC_AXI_RWREQ_ILLEGALACC_FIELD                   (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ILLEGALACC_SHIFT)
+#define MC_AXI_RWREQ_ILLEGALACC_RANGE                   _MK_SHIFT_CONST(101):_MK_SHIFT_CONST(101)
+#define MC_AXI_RWREQ_ILLEGALACC_ROW                     0
+
+#define MC_AXI_RWREQ_TAG_SHIFT                  _MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << MC_AXI_RWREQ_TAG_SHIFT)
+#define MC_AXI_RWREQ_TAG_RANGE                  _MK_SHIFT_CONST(106):_MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_RESET
+#define CSR_C2MC_RESET_SIZE 1
+
+#define CSR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_RESET_RSTN_SHIFT)
+#define CSR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSR_C2MC_REQ
+#define CSR_C2MC_REQ_SIZE 32
+
+#define CSR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_REQ_ADR_SHIFT)
+#define CSR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_ROW                    0
+
+
+// Packet CSR_C2MC_BP_REQ
+#define CSR_C2MC_BP_REQ_SIZE 48
+
+#define CSR_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSR_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSR_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSR_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSR_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_ROW                       0
+
+
+// Packet CSR_C2MC_ADRXY
+#define CSR_C2MC_ADRXY_SIZE 30
+
+#define CSR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSR_C2MC_ADRXY_OFFX_SHIFT)
+#define CSR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSR_C2MC_ADRXY_OFFY_SHIFT)
+#define CSR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSR_C2MC_TILE
+#define CSR_C2MC_TILE_SIZE 33
+
+#define CSR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_TILE_LINADR_SHIFT)
+#define CSR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_ROW                        0
+
+#define CSR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_TILE_TMODE_SHIFT)
+#define CSR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_ROW                 0
+#define CSR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSR_C2MC_RDI
+#define CSR_C2MC_RDI_SIZE 256
+
+#define CSR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_RDI_RDI_SHIFT)
+#define CSR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CSR_C2MC_HP
+#define CSR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CSR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_HP_HPTH_SHIFT)
+#define CSR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CSR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CSR_C2MC_HP_HPTM_SHIFT)
+#define CSR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CSW_C2MC_RESET
+#define CSW_C2MC_RESET_SIZE 1
+
+#define CSW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_RESET_RSTN_SHIFT)
+#define CSW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSW_C2MC_REQ
+#define CSW_C2MC_REQ_SIZE 321
+
+#define CSW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_ADR_SHIFT)
+#define CSW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_ROW                    0
+
+#define CSW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_BE_SHIFT)
+#define CSW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_ROW                     0
+
+#define CSW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_WDO_SHIFT)
+#define CSW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_ROW                    0
+
+#define CSW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_REQ_TAG_SHIFT)
+#define CSW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CSW_C2MC_BP_REQ
+#define CSW_C2MC_BP_REQ_SIZE 337
+
+#define CSW_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSW_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSW_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSW_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSW_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_ROW                       0
+
+#define CSW_C2MC_BP_REQ_BE_SHIFT                        _MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BE_SHIFT)
+#define CSW_C2MC_BP_REQ_BE_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_ROW                  0
+
+#define CSW_C2MC_BP_REQ_WDO_SHIFT                       _MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_FIELD                       (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_WDO_SHIFT)
+#define CSW_C2MC_BP_REQ_WDO_RANGE                       _MK_SHIFT_CONST(335):_MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_ROW                 0
+
+#define CSW_C2MC_BP_REQ_TAG_SHIFT                       _MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_BP_REQ_TAG_SHIFT)
+#define CSW_C2MC_BP_REQ_TAG_RANGE                       _MK_SHIFT_CONST(336):_MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_ROW                 0
+
+
+// Packet CSW_C2MC_ADRXY
+#define CSW_C2MC_ADRXY_SIZE 30
+
+#define CSW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSW_C2MC_ADRXY_OFFX_SHIFT)
+#define CSW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSW_C2MC_ADRXY_OFFY_SHIFT)
+#define CSW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSW_C2MC_TILE
+#define CSW_C2MC_TILE_SIZE 33
+
+#define CSW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_TILE_LINADR_SHIFT)
+#define CSW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_ROW                        0
+
+#define CSW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_TILE_TMODE_SHIFT)
+#define CSW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_ROW                 0
+#define CSW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSW_C2MC_XDI
+#define CSW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CSW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_XDI_XDI_SHIFT)
+#define CSW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CSW_C2MC_HP
+#define CSW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CSW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HP_HPTH_SHIFT)
+#define CSW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CSW_C2MC_WCOAL
+#define CSW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CSW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CSW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CBR_C2MC_RESET
+#define CBR_C2MC_RESET_SIZE 1
+
+#define CBR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RESET_RSTN_SHIFT)
+#define CBR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBR_C2MC_REQP
+#define CBR_C2MC_REQP_SIZE 263
+
+#define CBR_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADR_SHIFT)
+#define CBR_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_ROW                   0
+
+#define CBR_C2MC_REQP_ADRU_SHIFT                        _MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRU_SHIFT)
+#define CBR_C2MC_REQP_ADRU_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_ROW                  0
+
+#define CBR_C2MC_REQP_ADRV_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRV_SHIFT)
+#define CBR_C2MC_REQP_ADRV_RANGE                        _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_ROW                  0
+
+#define CBR_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LS_SHIFT)
+#define CBR_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_ROW                    0
+
+#define CBR_C2MC_REQP_LSUV_SHIFT                        _MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LSUV_SHIFT)
+#define CBR_C2MC_REQP_LSUV_RANGE                        _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_ROW                  0
+
+#define CBR_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_HS_SHIFT)
+#define CBR_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(191):_MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_ROW                    0
+
+#define CBR_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_VS_SHIFT)
+#define CBR_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(223):_MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_ROW                    0
+
+#define CBR_C2MC_REQP_DL_SHIFT                  _MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_DL_SHIFT)
+#define CBR_C2MC_REQP_DL_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_ROW                    0
+
+#define CBR_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_HD_SHIFT)
+#define CBR_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_ROW                    0
+
+#define CBR_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VD_SHIFT)
+#define CBR_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(257):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_ROW                    0
+
+#define CBR_C2MC_REQP_VX2_SHIFT                 _MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VX2_SHIFT)
+#define CBR_C2MC_REQP_VX2_RANGE                 _MK_SHIFT_CONST(258):_MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_ROW                   0
+
+#define CBR_C2MC_REQP_LP_SHIFT                  _MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_LP_SHIFT)
+#define CBR_C2MC_REQP_LP_RANGE                  _MK_SHIFT_CONST(259):_MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_ROW                    0
+
+#define CBR_C2MC_REQP_YUV_SHIFT                 _MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_REQP_YUV_SHIFT)
+#define CBR_C2MC_REQP_YUV_RANGE                 _MK_SHIFT_CONST(262):_MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_ROW                   0
+
+
+// Packet CBR_C2MC_ADRXY
+#define CBR_C2MC_ADRXY_SIZE 44
+
+#define CBR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_ADRXY_OFFX_SHIFT)
+#define CBR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFY_SHIFT)
+#define CBR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFYUV_SHIFT                     _MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_FIELD                     (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFYUV_SHIFT)
+#define CBR_C2MC_ADRXY_OFFYUV_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_ROW                       0
+
+
+// Packet CBR_C2MC_TILE
+#define CBR_C2MC_TILE_SIZE 98
+
+#define CBR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADR_SHIFT)
+#define CBR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_ROW                        0
+
+#define CBR_C2MC_TILE_LINADRU_SHIFT                     _MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRU_SHIFT)
+#define CBR_C2MC_TILE_LINADRU_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_ROW                       0
+
+#define CBR_C2MC_TILE_LINADRV_SHIFT                     _MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRV_SHIFT)
+#define CBR_C2MC_TILE_LINADRV_RANGE                     _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_ROW                       0
+
+#define CBR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODE_SHIFT)
+#define CBR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_ROW                 0
+#define CBR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+#define CBR_C2MC_TILE_TMODEUV_SHIFT                     _MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODEUV_SHIFT)
+#define CBR_C2MC_TILE_TMODEUV_RANGE                     _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_ROW                       0
+#define CBR_C2MC_TILE_TMODEUV_LINEAR                    _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODEUV_TILED                     _MK_ENUM_CONST(1)
+
+
+// Packet CBR_C2MC_RDYP
+#define CBR_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBR_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_RDYP_RDYP_SHIFT)
+#define CBR_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBR_C2MC_OUTSTD
+#define CBR_C2MC_OUTSTD_SIZE 1
+
+#define CBR_C2MC_OUTSTD_OUTSTD_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_OUTSTD_OUTSTD_SHIFT)
+#define CBR_C2MC_OUTSTD_OUTSTD_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_ROW                      0
+
+
+// Packet CBR_C2MC_STOP
+#define CBR_C2MC_STOP_SIZE 1
+
+#define CBR_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_STOP_STOP_SHIFT)
+#define CBR_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBR_C2MC_RDI
+#define CBR_C2MC_RDI_SIZE 262
+
+#define CBR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_RDI_RDI_SHIFT)
+#define CBR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_ROW                    0
+
+#define CBR_C2MC_RDI_RDILST_SHIFT                       _MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RDI_RDILST_SHIFT)
+#define CBR_C2MC_RDI_RDILST_RANGE                       _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_ROW                 0
+
+#define CBR_C2MC_RDI_RDINB_SHIFT                        _MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_FIELD                        (_MK_MASK_CONST(0x1f) << CBR_C2MC_RDI_RDINB_SHIFT)
+#define CBR_C2MC_RDI_RDINB_RANGE                        _MK_SHIFT_CONST(261):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_ROW                  0
+
+
+// Packet CBR_C2MC_DOREQ
+#define CBR_C2MC_DOREQ_SIZE 64
+
+#define CBR_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_ADR_SHIFT)
+#define CBR_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBR_C2MC_DOREQ_LS_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_LS_SHIFT)
+#define CBR_C2MC_DOREQ_LS_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_ROW                   0
+
+
+// Packet CBR_C2MC_HP
+#define CBR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CBR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_HP_HPTH_SHIFT)
+#define CBR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CBR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CBR_C2MC_HP_HPTM_SHIFT)
+#define CBR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CBW_C2MC_RESET
+#define CBW_C2MC_RESET_SIZE 1
+
+#define CBW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_RESET_RSTN_SHIFT)
+#define CBW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBW_C2MC_REQP
+#define CBW_C2MC_REQP_SIZE 134
+
+#define CBW_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_ADR_SHIFT)
+#define CBW_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_ROW                   0
+
+#define CBW_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_LS_SHIFT)
+#define CBW_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_ROW                    0
+
+#define CBW_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_HS_SHIFT)
+#define CBW_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_ROW                    0
+
+#define CBW_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_VS_SHIFT)
+#define CBW_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_ROW                    0
+
+#define CBW_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_HD_SHIFT)
+#define CBW_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(128):_MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_ROW                    0
+
+#define CBW_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_VD_SHIFT)
+#define CBW_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(129):_MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_ROW                    0
+
+#define CBW_C2MC_REQP_BPP_SHIFT                 _MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_FIELD                 (_MK_MASK_CONST(0x3) << CBW_C2MC_REQP_BPP_SHIFT)
+#define CBW_C2MC_REQP_BPP_RANGE                 _MK_SHIFT_CONST(131):_MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_ROW                   0
+
+#define CBW_C2MC_REQP_XY_SHIFT                  _MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_XY_SHIFT)
+#define CBW_C2MC_REQP_XY_RANGE                  _MK_SHIFT_CONST(132):_MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_ROW                    0
+
+#define CBW_C2MC_REQP_PK_SHIFT                  _MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_PK_SHIFT)
+#define CBW_C2MC_REQP_PK_RANGE                  _MK_SHIFT_CONST(133):_MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_ROW                    0
+
+
+// Packet CBW_C2MC_ADRXY
+#define CBW_C2MC_ADRXY_SIZE 30
+
+#define CBW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBW_C2MC_ADRXY_OFFX_SHIFT)
+#define CBW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBW_C2MC_ADRXY_OFFY_SHIFT)
+#define CBW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CBW_C2MC_TILE
+#define CBW_C2MC_TILE_SIZE 33
+
+#define CBW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_TILE_LINADR_SHIFT)
+#define CBW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_ROW                        0
+
+#define CBW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_TILE_TMODE_SHIFT)
+#define CBW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_ROW                 0
+#define CBW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CBW_C2MC_RDYP
+#define CBW_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBW_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_RDYP_RDYP_SHIFT)
+#define CBW_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBW_C2MC_STOP
+#define CBW_C2MC_STOP_SIZE 1
+
+#define CBW_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_STOP_STOP_SHIFT)
+#define CBW_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBW_C2MC_XDI
+#define CBW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CBW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_XDI_XDI_SHIFT)
+#define CBW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CBW_C2MC_DOREQ
+#define CBW_C2MC_DOREQ_SIZE 321
+
+#define CBW_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_ADR_SHIFT)
+#define CBW_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBW_C2MC_DOREQ_BE_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_BE_SHIFT)
+#define CBW_C2MC_DOREQ_BE_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_ROW                   0
+
+#define CBW_C2MC_DOREQ_WDO_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_WDO_SHIFT)
+#define CBW_C2MC_DOREQ_WDO_RANGE                        _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_ROW                  0
+
+#define CBW_C2MC_DOREQ_TAG_SHIFT                        _MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_DOREQ_TAG_SHIFT)
+#define CBW_C2MC_DOREQ_TAG_RANGE                        _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_ROW                  0
+
+
+// Packet CBW_C2MC_HP
+#define CBW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CBW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_HP_HPTH_SHIFT)
+#define CBW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CBW_C2MC_WCOAL
+#define CBW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CBW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CBW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CCR_C2MC_RESET
+#define CCR_C2MC_RESET_SIZE 1
+
+#define CCR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCR_C2MC_RESET_RSTN_SHIFT)
+#define CCR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCR_C2MC_REQ
+#define CCR_C2MC_REQ_SIZE 101
+
+#define CCR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_ADR_SHIFT)
+#define CCR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_ROW                    0
+
+#define CCR_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_LS_SHIFT)
+#define CCR_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCR_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_HINC_SHIFT)
+#define CCR_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_ROW                   0
+
+#define CCR_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCR_C2MC_REQ_ACMD_SHIFT)
+#define CCR_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_ROW                   0
+
+#define CCR_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_LN_SHIFT)
+#define CCR_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_ROW                     0
+
+#define CCR_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_HD_SHIFT)
+#define CCR_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_ROW                     0
+
+#define CCR_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_VD_SHIFT)
+#define CCR_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_ROW                     0
+
+
+// Packet CCR_C2MC_RDI
+#define CCR_C2MC_RDI_SIZE 256
+
+#define CCR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_RDI_RDI_SHIFT)
+#define CCR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CCR_C2MC_HP
+#define CCR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CCR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HP_HPTH_SHIFT)
+#define CCR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CCR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CCR_C2MC_HP_HPTM_SHIFT)
+#define CCR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CCW_C2MC_RESET
+#define CCW_C2MC_RESET_SIZE 1
+
+#define CCW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_RESET_RSTN_SHIFT)
+#define CCW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCW_C2MC_REQ
+#define CCW_C2MC_REQ_SIZE 417
+
+#define CCW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_ADR_SHIFT)
+#define CCW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_ROW                    0
+
+#define CCW_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_LS_SHIFT)
+#define CCW_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCW_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_HINC_SHIFT)
+#define CCW_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_ROW                   0
+
+#define CCW_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_ACMD_SHIFT)
+#define CCW_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_ROW                   0
+
+#define CCW_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_LN_SHIFT)
+#define CCW_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_ROW                     0
+
+#define CCW_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_HD_SHIFT)
+#define CCW_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_ROW                     0
+
+#define CCW_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_VD_SHIFT)
+#define CCW_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_ROW                     0
+
+#define CCW_C2MC_REQ_BPP_SHIFT                  _MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_FIELD                  (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_BPP_SHIFT)
+#define CCW_C2MC_REQ_BPP_RANGE                  _MK_SHIFT_CONST(102):_MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_ROW                    0
+
+#define CCW_C2MC_REQ_XY_SHIFT                   _MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_XY_SHIFT)
+#define CCW_C2MC_REQ_XY_RANGE                   _MK_SHIFT_CONST(103):_MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_ROW                     0
+
+#define CCW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_BE_SHIFT)
+#define CCW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_ROW                     0
+
+#define CCW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_WDO_SHIFT)
+#define CCW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(415):_MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_ROW                    0
+
+#define CCW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_TAG_SHIFT)
+#define CCW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(416):_MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CCW_C2MC_ADRXY
+#define CCW_C2MC_ADRXY_SIZE 30
+
+#define CCW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CCW_C2MC_ADRXY_OFFX_SHIFT)
+#define CCW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CCW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CCW_C2MC_ADRXY_OFFY_SHIFT)
+#define CCW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CCW_C2MC_TILE
+#define CCW_C2MC_TILE_SIZE 33
+
+#define CCW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_TILE_LINADR_SHIFT)
+#define CCW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_ROW                        0
+
+#define CCW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_TILE_TMODE_SHIFT)
+#define CCW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_ROW                 0
+#define CCW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CCW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CCW_C2MC_XDI
+#define CCW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CCW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_XDI_XDI_SHIFT)
+#define CCW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CCW_C2MC_HP
+#define CCW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CCW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_HP_HPTH_SHIFT)
+#define CCW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CCW_C2MC_WCOAL
+#define CCW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CCW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CCW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet SC_MCCIF_ASYNC
+#define SC_MCCIF_ASYNC_SIZE 4
+
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT                        _MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT                        _MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_RANGE                        _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT                        _MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT                        _MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_ROW                  0
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARMC_REGS(_op_) \
+_op_(MC_INTSTATUS_0) \
+_op_(MC_INTMASK_0) \
+_op_(MC_EMEM_CFG_0) \
+_op_(MC_EMEM_ADR_CFG_0) \
+_op_(MC_EMEM_ARB_CFG0_0) \
+_op_(MC_EMEM_ARB_CFG1_0) \
+_op_(MC_GART_CONFIG_0) \
+_op_(MC_GART_ENTRY_ADDR_0) \
+_op_(MC_GART_ENTRY_DATA_0) \
+_op_(MC_GART_ERROR_REQ_0) \
+_op_(MC_GART_ERROR_ADDR_0) \
+_op_(MC_PARTITION_CONFLICT_CFG_0) \
+_op_(MC_TIMEOUT_CTRL_0) \
+_op_(MC_DECERR_AXI_STATUS_0) \
+_op_(MC_DECERR_AXI_ADR_0) \
+_op_(MC_DECERR_EMEM_OTHERS_STATUS_0) \
+_op_(MC_DECERR_EMEM_OTHERS_ADR_0) \
+_op_(MC_CLKEN_OVERRIDE_0) \
+_op_(MC_STAT_CONTROL_0) \
+_op_(MC_STAT_STATUS_0) \
+_op_(MC_STAT_EMC_ADDR_LOW_0) \
+_op_(MC_STAT_EMC_ADDR_HIGH_0) \
+_op_(MC_STAT_EMC_CLOCK_LIMIT_0) \
+_op_(MC_STAT_EMC_CLOCKS_0) \
+_op_(MC_STAT_EMC_CONTROL_0_0) \
+_op_(MC_STAT_EMC_CONTROL_1_0) \
+_op_(MC_STAT_EMC_HIST_LIMIT_0_0) \
+_op_(MC_STAT_EMC_HIST_LIMIT_1_0) \
+_op_(MC_STAT_EMC_COUNT_0_0) \
+_op_(MC_STAT_EMC_COUNT_1_0) \
+_op_(MC_STAT_EMC_HIST_0_0) \
+_op_(MC_STAT_EMC_HIST_1_0) \
+_op_(MC_CLIENT_CTRL_0) \
+_op_(MC_CLIENT_HOTRESETN_0) \
+_op_(MC_CMC_ORRC_0) \
+_op_(MC_DC_ORRC_0) \
+_op_(MC_DCB_ORRC_0) \
+_op_(MC_EPP_ORRC_0) \
+_op_(MC_G2_ORRC_0) \
+_op_(MC_HC_ORRC_0) \
+_op_(MC_ISP_ORRC_0) \
+_op_(MC_MPCORE_ORRC_0) \
+_op_(MC_MPEA_ORRC_0) \
+_op_(MC_MPEB_ORRC_0) \
+_op_(MC_MPEC_ORRC_0) \
+_op_(MC_NV_ORRC_0) \
+_op_(MC_PPCS_ORRC_0) \
+_op_(MC_VDE_ORRC_0) \
+_op_(MC_VI_ORRC_0) \
+_op_(MC_AP_CTRL_0_0) \
+_op_(MC_AP_CTRL_1_0) \
+_op_(MC_FPRI_CTRL_CMC_0) \
+_op_(MC_FPRI_CTRL_DC_0) \
+_op_(MC_FPRI_CTRL_DCB_0) \
+_op_(MC_FPRI_CTRL_EPP_0) \
+_op_(MC_FPRI_CTRL_G2_0) \
+_op_(MC_FPRI_CTRL_HC_0) \
+_op_(MC_FPRI_CTRL_ISP_0) \
+_op_(MC_FPRI_CTRL_MPCORE_0) \
+_op_(MC_FPRI_CTRL_MPEA_0) \
+_op_(MC_FPRI_CTRL_MPEB_0) \
+_op_(MC_FPRI_CTRL_MPEC_0) \
+_op_(MC_FPRI_CTRL_NV_0) \
+_op_(MC_FPRI_CTRL_PPCS_0) \
+_op_(MC_FPRI_CTRL_VDE_0) \
+_op_(MC_FPRI_CTRL_VI_0) \
+_op_(MC_TIMEOUT_CMC_0) \
+_op_(MC_TIMEOUT_DC_0) \
+_op_(MC_TIMEOUT_DCB_0) \
+_op_(MC_TIMEOUT_EPP_0) \
+_op_(MC_TIMEOUT_G2_0) \
+_op_(MC_TIMEOUT_HC_0) \
+_op_(MC_TIMEOUT_ISP_0) \
+_op_(MC_TIMEOUT_MPCORE_0) \
+_op_(MC_TIMEOUT_MPEA_0) \
+_op_(MC_TIMEOUT_MPEB_0) \
+_op_(MC_TIMEOUT_MPEC_0) \
+_op_(MC_TIMEOUT_NV_0) \
+_op_(MC_TIMEOUT_PPCS_0) \
+_op_(MC_TIMEOUT_VDE_0) \
+_op_(MC_TIMEOUT1_VDE_0) \
+_op_(MC_TIMEOUT_VI_0) \
+_op_(MC_TIMEOUT_RCOAL_CMC_0) \
+_op_(MC_TIMEOUT_RCOAL_DC_0) \
+_op_(MC_TIMEOUT_RCOAL_DCB_0) \
+_op_(MC_TIMEOUT_RCOAL_EPP_0) \
+_op_(MC_TIMEOUT_RCOAL_G2_0) \
+_op_(MC_TIMEOUT_RCOAL_HC_0) \
+_op_(MC_TIMEOUT_RCOAL_MPCORE_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEA_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEB_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEC_0) \
+_op_(MC_TIMEOUT_RCOAL_NV_0) \
+_op_(MC_TIMEOUT_RCOAL_PPCS_0) \
+_op_(MC_TIMEOUT_RCOAL_VDE_0) \
+_op_(MC_TIMEOUT_RCOAL_VI_0) \
+_op_(MC_BWSHARE_EMEM_CTRL_0_0) \
+_op_(MC_BWSHARE_EMEM_CTRL_1_0) \
+_op_(MC_BWSHARE_CMC_0) \
+_op_(MC_BWSHARE_DISPLAY_0) \
+_op_(MC_BWSHARE_DISPLAYB_0) \
+_op_(MC_BWSHARE_EPP_0) \
+_op_(MC_BWSHARE_FDC_0) \
+_op_(MC_BWSHARE_GR2D_0) \
+_op_(MC_BWSHARE_HOST1X_0) \
+_op_(MC_BWSHARE_IDX_0) \
+_op_(MC_BWSHARE_ISP_0) \
+_op_(MC_BWSHARE_MPCORE_0) \
+_op_(MC_BWSHARE_MPEA_0) \
+_op_(MC_BWSHARE_MPEB_0) \
+_op_(MC_BWSHARE_MPEC_0) \
+_op_(MC_BWSHARE_PPCS_0) \
+_op_(MC_BWSHARE_TEX_0) \
+_op_(MC_BWSHARE_VDE_0) \
+_op_(MC_BWSHARE_VI_0) \
+_op_(MC_BWSHARE_TMVAL_0) \
+_op_(MC_AXI_DECERR_OVR_0) \
+_op_(MC_LOWLATENCY_CONFIG_0) \
+_op_(MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0) \
+_op_(MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0) \
+_op_(MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_MC 0x00000000
+
+//
+// ARMC REGISTER BANKS
+//
+
+#define MC0_FIRST_REG 0x0000 // MC_INTSTATUS_0
+#define MC0_LAST_REG 0x0004 // MC_INTMASK_0
+#define MC1_FIRST_REG 0x000c // MC_EMEM_CFG_0
+#define MC1_LAST_REG 0x0034 // MC_TIMEOUT_CTRL_0
+#define MC2_FIRST_REG 0x0040 // MC_DECERR_AXI_STATUS_0
+#define MC2_LAST_REG 0x0044 // MC_DECERR_AXI_ADR_0
+#define MC3_FIRST_REG 0x0050 // MC_DECERR_EMEM_OTHERS_STATUS_0
+#define MC3_LAST_REG 0x0054 // MC_DECERR_EMEM_OTHERS_ADR_0
+#define MC4_FIRST_REG 0x0060 // MC_CLKEN_OVERRIDE_0
+#define MC4_LAST_REG 0x01fc // MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARMC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arpwfm.h b/arch/arm/mach-tegra/nv/include/ap15/arpwfm.h
new file mode 100644
index 000000000000..2139d4bfa51a
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arpwfm.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARPWFM_H_INC_
+#define ___ARPWFM_H_INC_
+
+// Register PWM_CONTROLLER_PWM_CSR_0_0  
+#define PWM_CONTROLLER_PWM_CSR_0_0                      _MK_ADDR_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_WORD_COUNT                   0x1
+#define PWM_CONTROLLER_PWM_CSR_0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_RESET_MASK                   _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_READ_MASK                    _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_0_0_WRITE_MASK                   _MK_MASK_CONST(0x80ff1fff)
+// Enable Pulse width modulator
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_0_0_ENB_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_RANGE                    31:31
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_WOFFSET                  0x0
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// pulse width thats needs to be programmed. 
+//0=Always low 1=1/256 Pulse high 2=2/256 Pulse  High .N=N/256 Pulse high
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SHIFT                  _MK_SHIFT_CONST(16)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_FIELD                  (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_RANGE                  23:16
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PWM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Frequency divider that needs to be Programmed. 
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_FIELD                  (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_RANGE                  12:0
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1fff)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_0_0_PFM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 4 [0x4] 
+
+// Reserved address 8 [0x8] 
+
+// Reserved address 12 [0xc] 
+
+// Register PWM_CONTROLLER_PWM_CSR_1_0  
+#define PWM_CONTROLLER_PWM_CSR_1_0                      _MK_ADDR_CONST(0x10)
+#define PWM_CONTROLLER_PWM_CSR_1_0_WORD_COUNT                   0x1
+#define PWM_CONTROLLER_PWM_CSR_1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_RESET_MASK                   _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_READ_MASK                    _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_1_0_WRITE_MASK                   _MK_MASK_CONST(0x80ff1fff)
+//  Enable pulse width modulator 
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_1_0_ENB_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_RANGE                    31:31
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_WOFFSET                  0x0
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// pulse width that needs to be programmed
+// 0=Always low 1=1/256 Pulse high 2=2/256 Pulse  High .N=N/256 Pulse high
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SHIFT                  _MK_SHIFT_CONST(16)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_FIELD                  (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_RANGE                  23:16
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PWM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Frequency divider that needs to be Programmed. 
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_FIELD                  (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_RANGE                  12:0
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1fff)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_1_0_PFM_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+
+// Register PWM_CONTROLLER_PWM_CSR_2_0  
+#define PWM_CONTROLLER_PWM_CSR_2_0                      _MK_ADDR_CONST(0x20)
+#define PWM_CONTROLLER_PWM_CSR_2_0_WORD_COUNT                   0x1
+#define PWM_CONTROLLER_PWM_CSR_2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_RESET_MASK                   _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_READ_MASK                    _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_2_0_WRITE_MASK                   _MK_MASK_CONST(0x80ff1fff)
+//  Enable pulse width modulator 
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_2_0_ENB_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_RANGE                    31:31
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_WOFFSET                  0x0
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Pulse Width that needs to be programmed.
+// 0=Always low 1=1/256 Pulse high 2=2/256 Pulse  High .N=N/256 Pulse high
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SHIFT                  _MK_SHIFT_CONST(16)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_FIELD                  (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_RANGE                  23:16
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PWM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Frequency divider that needs to be Programmed. 
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SHIFT                  _MK_SHIFT_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_FIELD                  (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_RANGE                  12:0
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1fff)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_2_0_PFM_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 36 [0x24] 
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Register PWM_CONTROLLER_PWM_CSR_3_0  
+#define PWM_CONTROLLER_PWM_CSR_3_0                      _MK_ADDR_CONST(0x30)
+#define PWM_CONTROLLER_PWM_CSR_3_0_WORD_COUNT                   0x1
+#define PWM_CONTROLLER_PWM_CSR_3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_RESET_MASK                   _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_READ_MASK                    _MK_MASK_CONST(0x80ff1fff)
+#define PWM_CONTROLLER_PWM_CSR_3_0_WRITE_MASK                   _MK_MASK_CONST(0x80ff1fff)
+//  Enable pulse width modulator 
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << PWM_CONTROLLER_PWM_CSR_3_0_ENB_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_RANGE                    31:31
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_WOFFSET                  0x0
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// pulse width  that needs to be programmed
+// 0=Always low 1=1/256 Pulse high 2=2/256 Pulse  High .N=N/256 Pulse high
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SHIFT                  _MK_SHIFT_CONST(16)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_FIELD                  (_MK_MASK_CONST(0xff) << PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_RANGE                  23:16
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PWM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Frequency divider that needs to be Programmed. 
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SHIFT                  _MK_SHIFT_CONST(0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_FIELD                  (_MK_MASK_CONST(0x1fff) << PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SHIFT)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_RANGE                  12:0
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_WOFFSET                        0x0
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1fff)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PWM_CONTROLLER_PWM_CSR_3_0_PFM_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARPWFM_REGS(_op_) \
+_op_(PWM_CONTROLLER_PWM_CSR_0_0) \
+_op_(PWM_CONTROLLER_PWM_CSR_1_0) \
+_op_(PWM_CONTROLLER_PWM_CSR_2_0) \
+_op_(PWM_CONTROLLER_PWM_CSR_3_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_PWM_CONTROLLER     0x00000000
+
+//
+// ARPWFM REGISTER BANKS
+//
+
+#define PWM_CONTROLLER0_FIRST_REG 0x0000 // PWM_CONTROLLER_PWM_CSR_0_0
+#define PWM_CONTROLLER0_LAST_REG 0x0000 // PWM_CONTROLLER_PWM_CSR_0_0
+#define PWM_CONTROLLER1_FIRST_REG 0x0010 // PWM_CONTROLLER_PWM_CSR_1_0
+#define PWM_CONTROLLER1_LAST_REG 0x0010 // PWM_CONTROLLER_PWM_CSR_1_0
+#define PWM_CONTROLLER2_FIRST_REG 0x0020 // PWM_CONTROLLER_PWM_CSR_2_0
+#define PWM_CONTROLLER2_LAST_REG 0x0020 // PWM_CONTROLLER_PWM_CSR_2_0
+#define PWM_CONTROLLER3_FIRST_REG 0x0030 // PWM_CONTROLLER_PWM_CSR_3_0
+#define PWM_CONTROLLER3_LAST_REG 0x0030 // PWM_CONTROLLER_PWM_CSR_3_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARPWFM_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arres_sema.h b/arch/arm/mach-tegra/nv/include/ap15/arres_sema.h
new file mode 100644
index 000000000000..093439d20511
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arres_sema.h
@@ -0,0 +1,325 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARRES_SEMA_H_INC_
+#define ___ARRES_SEMA_H_INC_
+// Shared Resource Semaphore Status
+
+// Register RES_SEMA_SHRD_SMP_STA_0  
+#define RES_SEMA_SHRD_SMP_STA_0                 _MK_ADDR_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_WORD_COUNT                      0x1
+#define RES_SEMA_SHRD_SMP_STA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_STA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_STA_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// SMP.27:SMP.24: Available in APB_DMA.REQUESTORS  register
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_SHIFT)
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_RANGE                      31:0
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_WOFFSET                    0x0
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_STA_0_SMP_31_SMP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Shared Resource Semaphore Set-bit Request
+
+// Register RES_SEMA_SHRD_SMP_SET_0  
+#define RES_SEMA_SHRD_SMP_SET_0                 _MK_ADDR_CONST(0x4)
+#define RES_SEMA_SHRD_SMP_SET_0_WORD_COUNT                      0x1
+#define RES_SEMA_SHRD_SMP_SET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_SET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_READ_MASK                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Semaphore set register. Writing a one to any bit  will set the corresponding semaphore bit. Shared resource set-bit requests
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_SHIFT)
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_RANGE                      31:0
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_WOFFSET                    0x0
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_SET_0_SET_31_SET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Shared Resource Semaphore Clr-bit Request Register
+
+// Register RES_SEMA_SHRD_SMP_CLR_0  
+#define RES_SEMA_SHRD_SMP_CLR_0                 _MK_ADDR_CONST(0x8)
+#define RES_SEMA_SHRD_SMP_CLR_0_WORD_COUNT                      0x1
+#define RES_SEMA_SHRD_SMP_CLR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_CLR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_READ_MASK                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// corresponding semaphore bit
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_SHIFT)
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_RANGE                      31:0
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_WOFFSET                    0x0
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_SMP_CLR_0_CLR_31_CLR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 12 [0xc] 
+// Shared Resource Inbox (messages from COP to CPU)
+
+// Register RES_SEMA_SHRD_INBOX_0  
+#define RES_SEMA_SHRD_INBOX_0                   _MK_ADDR_CONST(0x10)
+#define RES_SEMA_SHRD_INBOX_0_WORD_COUNT                        0x1
+#define RES_SEMA_SHRD_INBOX_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_INBOX_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_INBOX_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Interrupt CPU on INBOX Full (TAG=1)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_SHIFT                      _MK_SHIFT_CONST(31)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_FIELD                      (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_INBOX_0_IE_IBF_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_RANGE                      31:31
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_WOFFSET                    0x0
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_EMPTY                      _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBF_FULL                       _MK_ENUM_CONST(1)
+
+// Interrupt COP on INBOX Empty (TAG=0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_SHIFT                      _MK_SHIFT_CONST(30)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_FIELD                      (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_INBOX_0_IE_IBE_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_RANGE                      30:30
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_WOFFSET                    0x0
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_EMPTY                      _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_INBOX_0_IE_IBE_FULL                       _MK_ENUM_CONST(1)
+
+// Read-only. Set when COP writes this register and  cleared when CPU Reads this register.
+#define RES_SEMA_SHRD_INBOX_0_TAG_SHIFT                 _MK_SHIFT_CONST(29)
+#define RES_SEMA_SHRD_INBOX_0_TAG_FIELD                 (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_INBOX_0_TAG_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_TAG_RANGE                 29:29
+#define RES_SEMA_SHRD_INBOX_0_TAG_WOFFSET                       0x0
+#define RES_SEMA_SHRD_INBOX_0_TAG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_TAG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_INBOX_0_TAG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_TAG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_TAG_INVALID                       _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_INBOX_0_TAG_VALID                 _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define RES_SEMA_SHRD_INBOX_0_N_A1_SHIFT                        _MK_SHIFT_CONST(28)
+#define RES_SEMA_SHRD_INBOX_0_N_A1_FIELD                        (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_INBOX_0_N_A1_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_N_A1_RANGE                        28:28
+#define RES_SEMA_SHRD_INBOX_0_N_A1_WOFFSET                      0x0
+#define RES_SEMA_SHRD_INBOX_0_N_A1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_N_A1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_INBOX_0_N_A1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_N_A1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// definition)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_SHIFT                 _MK_SHIFT_CONST(24)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_FIELD                 (_MK_MASK_CONST(0xf) << RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_RANGE                 27:24
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_WOFFSET                       0x0
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_STAT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// General purpose data bits, suggested usage is for  INBOX command (SW can change definition)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_SHIFT                  _MK_SHIFT_CONST(17)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_FIELD                  (_MK_MASK_CONST(0x7f) << RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_RANGE                  23:17
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_WOFFSET                        0x0
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_CMD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// definition)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_SHIFT                 _MK_SHIFT_CONST(0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_FIELD                 (_MK_MASK_CONST(0x1ffff) << RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_SHIFT)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_RANGE                 16:0
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_WOFFSET                       0x0
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0x1ffff)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_INBOX_0_IN_BOX_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+// Shared Resource Outbox (messages from CPU to COP)
+
+// Register RES_SEMA_SHRD_OUTBOX_0  
+#define RES_SEMA_SHRD_OUTBOX_0                  _MK_ADDR_CONST(0x20)
+#define RES_SEMA_SHRD_OUTBOX_0_WORD_COUNT                       0x1
+#define RES_SEMA_SHRD_OUTBOX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_OUTBOX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define RES_SEMA_SHRD_OUTBOX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// Interrupt COP on OUTBOX Full (TAG=1)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_SHIFT                     _MK_SHIFT_CONST(31)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_FIELD                     (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_OUTBOX_0_IE_OBF_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_RANGE                     31:31
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_WOFFSET                   0x0
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_EMPTY                     _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBF_FULL                      _MK_ENUM_CONST(1)
+
+// Interrupt CPU on OUTBOX Empty (TAG=0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_SHIFT                     _MK_SHIFT_CONST(30)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_FIELD                     (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_OUTBOX_0_IE_OBE_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_RANGE                     30:30
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_WOFFSET                   0x0
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_EMPTY                     _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_OUTBOX_0_IE_OBE_FULL                      _MK_ENUM_CONST(1)
+
+// HW clears this bit when COP Reads the Outbox Register.  Read-only. Set when CPU writes this register and cleared when COP reads this  register.
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_SHIFT                        _MK_SHIFT_CONST(29)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_FIELD                        (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_OUTBOX_0_TAG_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_RANGE                        29:29
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_WOFFSET                      0x0
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_DEFAULT                      _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_INVALID                      _MK_ENUM_CONST(0)
+#define RES_SEMA_SHRD_OUTBOX_0_TAG_VALID                        _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_SHIFT                       _MK_SHIFT_CONST(28)
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_FIELD                       (_MK_MASK_CONST(0x1) << RES_SEMA_SHRD_OUTBOX_0_N_A1_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_RANGE                       28:28
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_WOFFSET                     0x0
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_N_A1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// General purpose data bits, suggested usage is for  Out Box OUTBOX status (SW can change definition)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_SHIFT                       _MK_SHIFT_CONST(24)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_FIELD                       (_MK_MASK_CONST(0xf) << RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_RANGE                       27:24
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_WOFFSET                     0x0
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_STAT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// General purpose data bits, suggested usage is for  Out Box OUTBOX command (SW can change definition)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_SHIFT                        _MK_SHIFT_CONST(17)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_FIELD                        (_MK_MASK_CONST(0x7f) << RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_RANGE                        23:17
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_WOFFSET                      0x0
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_CMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// General purpose Out Box data bits, suggested usage  is for OUTBOX data (SW can change definition)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_SHIFT                       _MK_SHIFT_CONST(0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_FIELD                       (_MK_MASK_CONST(0x1ffff) << RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_SHIFT)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_RANGE                       16:0
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_WOFFSET                     0x0
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1ffff)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define RES_SEMA_SHRD_OUTBOX_0_OUT_BOX_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARRES_SEMA_REGS(_op_) \
+_op_(RES_SEMA_SHRD_SMP_STA_0) \
+_op_(RES_SEMA_SHRD_SMP_SET_0) \
+_op_(RES_SEMA_SHRD_SMP_CLR_0) \
+_op_(RES_SEMA_SHRD_INBOX_0) \
+_op_(RES_SEMA_SHRD_OUTBOX_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_RES_SEMA   0x00000000
+
+//
+// ARRES_SEMA REGISTER BANKS
+//
+
+#define RES_SEMA0_FIRST_REG 0x0000 // RES_SEMA_SHRD_SMP_STA_0
+#define RES_SEMA0_LAST_REG 0x0008 // RES_SEMA_SHRD_SMP_CLR_0
+#define RES_SEMA1_FIRST_REG 0x0010 // RES_SEMA_SHRD_INBOX_0
+#define RES_SEMA1_LAST_REG 0x0010 // RES_SEMA_SHRD_INBOX_0
+#define RES_SEMA2_FIRST_REG 0x0020 // RES_SEMA_SHRD_OUTBOX_0
+#define RES_SEMA2_LAST_REG 0x0020 // RES_SEMA_SHRD_OUTBOX_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARRES_SEMA_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arslink.h b/arch/arm/mach-tegra/nv/include/ap15/arslink.h
new file mode 100644
index 000000000000..36c5031de57d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arslink.h
@@ -0,0 +1,1178 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARSLINK_H_INC_
+#define ___ARSLINK_H_INC_
+
+// Register SLINK_COMMAND_0  
+#define SLINK_COMMAND_0                 _MK_ADDR_CONST(0x0)
+#define SLINK_COMMAND_0_WORD_COUNT                      0x1
+#define SLINK_COMMAND_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_COMMAND_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_COMMAND_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// RD/WD access to Data Register would start the next  transfer. (This allows continuous Receive via RD of Buffer and Automated  Transmit per WD of Buffer Register)
+#define SLINK_COMMAND_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define SLINK_COMMAND_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_ENB_SHIFT)
+#define SLINK_COMMAND_0_ENB_RANGE                       31:31
+#define SLINK_COMMAND_0_ENB_WOFFSET                     0x0
+#define SLINK_COMMAND_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_DISABLE                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Program 1 after all the other bits in the COMMAND2 and COMMAND are programmed to start the trasnfer
+// HW clears this bit automatically after the trasnfer is done
+// Clearing of the bit by SW will stop the Shifter  and latch the partial data into buffer
+#define SLINK_COMMAND_0_GO_SHIFT                        _MK_SHIFT_CONST(30)
+#define SLINK_COMMAND_0_GO_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_GO_SHIFT)
+#define SLINK_COMMAND_0_GO_RANGE                        30:30
+#define SLINK_COMMAND_0_GO_WOFFSET                      0x0
+#define SLINK_COMMAND_0_GO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_GO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_STOP                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_GO_GO                   _MK_ENUM_CONST(1)
+
+//  1 = Hold APB Cycle from writing another data into COMMAND register until RDY 0  = NOP. Use of this bit is deprecated.
+#define SLINK_COMMAND_0_WAIT_SHIFT                      _MK_SHIFT_CONST(29)
+#define SLINK_COMMAND_0_WAIT_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_WAIT_SHIFT)
+#define SLINK_COMMAND_0_WAIT_RANGE                      29:29
+#define SLINK_COMMAND_0_WAIT_WOFFSET                    0x0
+#define SLINK_COMMAND_0_WAIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_WAIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_NOP                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_WAIT_WAIT                       _MK_ENUM_CONST(1)
+
+// 1 = Master Mode (internal Clock) 0 = Slave Mode  (external Clock)
+#define SLINK_COMMAND_0_M_S_SHIFT                       _MK_SHIFT_CONST(28)
+#define SLINK_COMMAND_0_M_S_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_M_S_SHIFT)
+#define SLINK_COMMAND_0_M_S_RANGE                       28:28
+#define SLINK_COMMAND_0_M_S_WOFFSET                     0x0
+#define SLINK_COMMAND_0_M_S_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_M_S_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_SLAVE                       _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_M_S_MASTER                      _MK_ENUM_CONST(1)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High (o.H) 00 = Driven Low (o.L)  (def)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_SHIFT                       _MK_SHIFT_CONST(26)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_FIELD                       (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_ACTIVE_SCLK_SHIFT)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_RANGE                       27:26
+#define SLINK_COMMAND_0_ACTIVE_SCLK_WOFFSET                     0x0
+#define SLINK_COMMAND_0_ACTIVE_SCLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_DRIVE_LOW                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_DRIVE_HIGH                  _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_PULL_LOW                    _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_ACTIVE_SCLK_PULL_HIGH                   _MK_ENUM_CONST(3)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High 00 =  Driven Low (def)
+#define SLINK_COMMAND_0_IDLE_SCLK_SHIFT                 _MK_SHIFT_CONST(24)
+#define SLINK_COMMAND_0_IDLE_SCLK_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_IDLE_SCLK_SHIFT)
+#define SLINK_COMMAND_0_IDLE_SCLK_RANGE                 25:24
+#define SLINK_COMMAND_0_IDLE_SCLK_WOFFSET                       0x0
+#define SLINK_COMMAND_0_IDLE_SCLK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_IDLE_SCLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DRIVE_LOW                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DRIVE_HIGH                    _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_IDLE_SCLK_PULL_LOW                      _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_IDLE_SCLK_PULL_HIGH                     _MK_ENUM_CONST(3)
+
+// Reserved = 0
+#define SLINK_COMMAND_0_N_A_0_SHIFT                     _MK_SHIFT_CONST(22)
+#define SLINK_COMMAND_0_N_A_0_FIELD                     (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_N_A_0_SHIFT)
+#define SLINK_COMMAND_0_N_A_0_RANGE                     23:22
+#define SLINK_COMMAND_0_N_A_0_WOFFSET                   0x0
+#define SLINK_COMMAND_0_N_A_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_0_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_N_A_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1 = Second Edge 0 =  First Edge (def)
+#define SLINK_COMMAND_0_CK_SDA_SHIFT                    _MK_SHIFT_CONST(21)
+#define SLINK_COMMAND_0_CK_SDA_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CK_SDA_SHIFT)
+#define SLINK_COMMAND_0_CK_SDA_RANGE                    21:21
+#define SLINK_COMMAND_0_CK_SDA_WOFFSET                  0x0
+#define SLINK_COMMAND_0_CK_SDA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CK_SDA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_FIRST_CLK_EDGE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CK_SDA_SECOND_CLK_EDGE                  _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SLINK_COMMAND_0_N_A_1_SHIFT                     _MK_SHIFT_CONST(20)
+#define SLINK_COMMAND_0_N_A_1_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_N_A_1_SHIFT)
+#define SLINK_COMMAND_0_N_A_1_RANGE                     20:20
+#define SLINK_COMMAND_0_N_A_1_WOFFSET                   0x0
+#define SLINK_COMMAND_0_N_A_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_N_A_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High (o.H) 00 = Driven  Low (o.L)
+#define SLINK_COMMAND_0_ACTIVE_SDA_SHIFT                        _MK_SHIFT_CONST(18)
+#define SLINK_COMMAND_0_ACTIVE_SDA_FIELD                        (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_ACTIVE_SDA_SHIFT)
+#define SLINK_COMMAND_0_ACTIVE_SDA_RANGE                        19:18
+#define SLINK_COMMAND_0_ACTIVE_SDA_WOFFSET                      0x0
+#define SLINK_COMMAND_0_ACTIVE_SDA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SDA_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_ACTIVE_SDA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SDA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ACTIVE_SDA_DRIVE_LOW                    _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_ACTIVE_SDA_DRIVE_HIGH                   _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_ACTIVE_SDA_PULL_LOW                     _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_ACTIVE_SDA_PULL_HIGH                    _MK_ENUM_CONST(3)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High 00  = Driven Low
+#define SLINK_COMMAND_0_IDLE_SDA_SHIFT                  _MK_SHIFT_CONST(16)
+#define SLINK_COMMAND_0_IDLE_SDA_FIELD                  (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_IDLE_SDA_SHIFT)
+#define SLINK_COMMAND_0_IDLE_SDA_RANGE                  17:16
+#define SLINK_COMMAND_0_IDLE_SDA_WOFFSET                        0x0
+#define SLINK_COMMAND_0_IDLE_SDA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_IDLE_SDA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_DRIVE_LOW                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_IDLE_SDA_DRIVE_HIGH                     _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_IDLE_SDA_PULL_LOW                       _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_IDLE_SDA_PULL_HIGH                      _MK_ENUM_CONST(3)
+
+// Reserved = 0
+#define SLINK_COMMAND_0_N_A_2_SHIFT                     _MK_SHIFT_CONST(14)
+#define SLINK_COMMAND_0_N_A_2_FIELD                     (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_N_A_2_SHIFT)
+#define SLINK_COMMAND_0_N_A_2_RANGE                     15:14
+#define SLINK_COMMAND_0_N_A_2_WOFFSET                   0x0
+#define SLINK_COMMAND_0_N_A_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_2_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_N_A_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_N_A_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1 = CS active high  0  = CS active low
+#define SLINK_COMMAND_0_CS_POLARITY_SHIFT                       _MK_SHIFT_CONST(13)
+#define SLINK_COMMAND_0_CS_POLARITY_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_POLARITY_SHIFT)
+#define SLINK_COMMAND_0_CS_POLARITY_RANGE                       13:13
+#define SLINK_COMMAND_0_CS_POLARITY_WOFFSET                     0x0
+#define SLINK_COMMAND_0_CS_POLARITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_POLARITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY_LOW                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_POLARITY_HIGH                        _MK_ENUM_CONST(1)
+
+//  1 = CS is high  0  = CS is low  
+#define SLINK_COMMAND_0_CS_VALUE_SHIFT                  _MK_SHIFT_CONST(12)
+#define SLINK_COMMAND_0_CS_VALUE_FIELD                  (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_VALUE_SHIFT)
+#define SLINK_COMMAND_0_CS_VALUE_RANGE                  12:12
+#define SLINK_COMMAND_0_CS_VALUE_WOFFSET                        0x0
+#define SLINK_COMMAND_0_CS_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_LOW                    _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_VALUE_HIGH                   _MK_ENUM_CONST(1)
+
+//  1 = CS controlled by SW   0  = CS controlled by hardware
+#define SLINK_COMMAND_0_CS_SW_SHIFT                     _MK_SHIFT_CONST(11)
+#define SLINK_COMMAND_0_CS_SW_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_SW_SHIFT)
+#define SLINK_COMMAND_0_CS_SW_RANGE                     11:11
+#define SLINK_COMMAND_0_CS_SW_WOFFSET                   0x0
+#define SLINK_COMMAND_0_CS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_SW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_HARD                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_SW_SOFT                      _MK_ENUM_CONST(1)
+
+//  1 = both lines transmit/receive   0  = one line transmit and other receive 
+#define SLINK_COMMAND_0_BOTH_EN_SHIFT                   _MK_SHIFT_CONST(10)
+#define SLINK_COMMAND_0_BOTH_EN_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_BOTH_EN_SHIFT)
+#define SLINK_COMMAND_0_BOTH_EN_RANGE                   10:10
+#define SLINK_COMMAND_0_BOTH_EN_WOFFSET                 0x0
+#define SLINK_COMMAND_0_BOTH_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_BOTH_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_BOTH_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// 31 = Thirty Two words (Max)
+#define SLINK_COMMAND_0_WORD_SIZE_SHIFT                 _MK_SHIFT_CONST(5)
+#define SLINK_COMMAND_0_WORD_SIZE_FIELD                 (_MK_MASK_CONST(0x1f) << SLINK_COMMAND_0_WORD_SIZE_SHIFT)
+#define SLINK_COMMAND_0_WORD_SIZE_RANGE                 9:5
+#define SLINK_COMMAND_0_WORD_SIZE_WOFFSET                       0x0
+#define SLINK_COMMAND_0_WORD_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WORD_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND_0_WORD_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WORD_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 31 = Thirty Two bit Transfers (Max)
+#define SLINK_COMMAND_0_BIT_LENGTH_SHIFT                        _MK_SHIFT_CONST(0)
+#define SLINK_COMMAND_0_BIT_LENGTH_FIELD                        (_MK_MASK_CONST(0x1f) << SLINK_COMMAND_0_BIT_LENGTH_SHIFT)
+#define SLINK_COMMAND_0_BIT_LENGTH_RANGE                        4:0
+#define SLINK_COMMAND_0_BIT_LENGTH_WOFFSET                      0x0
+#define SLINK_COMMAND_0_BIT_LENGTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BIT_LENGTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND_0_BIT_LENGTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BIT_LENGTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_COMMAND2_0  
+#define SLINK_COMMAND2_0                        _MK_ADDR_CONST(0x4)
+#define SLINK_COMMAND2_0_WORD_COUNT                     0x1
+#define SLINK_COMMAND2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SLINK_COMMAND2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_COMMAND2_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Receive enable 
+#define SLINK_COMMAND2_0_RXEN_SHIFT                     _MK_SHIFT_CONST(31)
+#define SLINK_COMMAND2_0_RXEN_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_RXEN_SHIFT)
+#define SLINK_COMMAND2_0_RXEN_RANGE                     31:31
+#define SLINK_COMMAND2_0_RXEN_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_RXEN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_RXEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_RXEN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Transmit enable 
+#define SLINK_COMMAND2_0_TXEN_SHIFT                     _MK_SHIFT_CONST(30)
+#define SLINK_COMMAND2_0_TXEN_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_TXEN_SHIFT)
+#define SLINK_COMMAND2_0_TXEN_RANGE                     30:30
+#define SLINK_COMMAND2_0_TXEN_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_TXEN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_TXEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_TXEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  1 = bi directional mode 0 = Normal mode
+#define SLINK_COMMAND2_0_SPC0_SHIFT                     _MK_SHIFT_CONST(29)
+#define SLINK_COMMAND2_0_SPC0_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SPC0_SHIFT)
+#define SLINK_COMMAND2_0_SPC0_RANGE                     29:29
+#define SLINK_COMMAND2_0_SPC0_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SPC0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SPC0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_NORMAL                    _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SPC0_BIDIR                     _MK_ENUM_CONST(1)
+
+// number of cycles between two packs in the DMA. Use of this field is deprecated. Use INT_SIZE 8 = number of cycles between 2 packs (Max) 
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SHIFT                    _MK_SHIFT_CONST(26)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_FIELD                    (_MK_MASK_CONST(0x7) << SLINK_COMMAND2_0_WAIT_PACK_INT_SHIFT)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_RANGE                    28:26
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved = 0
+#define SLINK_COMMAND2_0_N_A_3_SHIFT                    _MK_SHIFT_CONST(24)
+#define SLINK_COMMAND2_0_N_A_3_FIELD                    (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_N_A_3_SHIFT)
+#define SLINK_COMMAND2_0_N_A_3_RANGE                    25:24
+#define SLINK_COMMAND2_0_N_A_3_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_3_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_N_A_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved = 0
+#define SLINK_COMMAND2_0_N_A_4_SHIFT                    _MK_SHIFT_CONST(22)
+#define SLINK_COMMAND2_0_N_A_4_FIELD                    (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_N_A_4_SHIFT)
+#define SLINK_COMMAND2_0_N_A_4_RANGE                    23:22
+#define SLINK_COMMAND2_0_N_A_4_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_4_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_N_A_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// number of cycles CS should stay inactive between packets 4 = number of cycles in setup for chip select (Max)   
+#define SLINK_COMMAND2_0_SS_SETUP_SHIFT                 _MK_SHIFT_CONST(20)
+#define SLINK_COMMAND2_0_SS_SETUP_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_SS_SETUP_SHIFT)
+#define SLINK_COMMAND2_0_SS_SETUP_RANGE                 21:20
+#define SLINK_COMMAND2_0_SS_SETUP_WOFFSET                       0x0
+#define SLINK_COMMAND2_0_SS_SETUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_SS_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 11 = chip select3 10 = chip select2 01 = chip select1 00 = chip select0(def)
+#define SLINK_COMMAND2_0_SS_EN_SHIFT                    _MK_SHIFT_CONST(18)
+#define SLINK_COMMAND2_0_SS_EN_FIELD                    (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_SS_EN_SHIFT)
+#define SLINK_COMMAND2_0_SS_EN_RANGE                    19:18
+#define SLINK_COMMAND2_0_SS_EN_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_SS_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_SS_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_CS0                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SS_EN_CS1                      _MK_ENUM_CONST(1)
+#define SLINK_COMMAND2_0_SS_EN_CS2                      _MK_ENUM_CONST(2)
+#define SLINK_COMMAND2_0_SS_EN_CS3                      _MK_ENUM_CONST(3)
+
+// Reserved = 0
+#define SLINK_COMMAND2_0_N_A_5_SHIFT                    _MK_SHIFT_CONST(13)
+#define SLINK_COMMAND2_0_N_A_5_FIELD                    (_MK_MASK_CONST(0x1f) << SLINK_COMMAND2_0_N_A_5_SHIFT)
+#define SLINK_COMMAND2_0_N_A_5_RANGE                    17:13
+#define SLINK_COMMAND2_0_N_A_5_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND2_0_N_A_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// number of IDLE cycles between two packets
+// 31 = thirty two cycles between 2 packets
+#define SLINK_COMMAND2_0_INT_SIZE_SHIFT                 _MK_SHIFT_CONST(8)
+#define SLINK_COMMAND2_0_INT_SIZE_FIELD                 (_MK_MASK_CONST(0x1f) << SLINK_COMMAND2_0_INT_SIZE_SHIFT)
+#define SLINK_COMMAND2_0_INT_SIZE_RANGE                 12:8
+#define SLINK_COMMAND2_0_INT_SIZE_WOFFSET                       0x0
+#define SLINK_COMMAND2_0_INT_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_INT_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND2_0_INT_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_INT_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = Enable Modef   0 = Disable Modef (def)
+#define SLINK_COMMAND2_0_MODFEN_SHIFT                   _MK_SHIFT_CONST(7)
+#define SLINK_COMMAND2_0_MODFEN_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_MODFEN_SHIFT)
+#define SLINK_COMMAND2_0_MODFEN_RANGE                   7:7
+#define SLINK_COMMAND2_0_MODFEN_WOFFSET                 0x0
+#define SLINK_COMMAND2_0_MODFEN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_MODFEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_DISABLE                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_MODFEN_ENABLE                  _MK_ENUM_CONST(1)
+
+// When set to 1 SLINK uses only one data line (mosi/miso) for Tx and Rx depending on Master/Slave mode.
+// This has effect only when SPC0 is set to 1
+// 1 = Enable Output buffer 0 = Disable Output buffer (def)
+#define SLINK_COMMAND2_0_BIDIROE_SHIFT                  _MK_SHIFT_CONST(6)
+#define SLINK_COMMAND2_0_BIDIROE_FIELD                  (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_BIDIROE_SHIFT)
+#define SLINK_COMMAND2_0_BIDIROE_RANGE                  6:6
+#define SLINK_COMMAND2_0_BIDIROE_WOFFSET                        0x0
+#define SLINK_COMMAND2_0_BIDIROE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_BIDIROE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_DISABLE                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_BIDIROE_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reserved
+#define SLINK_COMMAND2_0_N_A_6_SHIFT                    _MK_SHIFT_CONST(5)
+#define SLINK_COMMAND2_0_N_A_6_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_N_A_6_SHIFT)
+#define SLINK_COMMAND2_0_N_A_6_RANGE                    5:5
+#define SLINK_COMMAND2_0_N_A_6_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_N_A_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = Enable SPIE interrupt 0 = Disable SPIE interrupt
+#define SLINK_COMMAND2_0_SPIE_SHIFT                     _MK_SHIFT_CONST(4)
+#define SLINK_COMMAND2_0_SPIE_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SPIE_SHIFT)
+#define SLINK_COMMAND2_0_SPIE_RANGE                     4:4
+#define SLINK_COMMAND2_0_SPIE_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SPIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SPIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SPIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reserved
+#define SLINK_COMMAND2_0_N_A_8_SHIFT                    _MK_SHIFT_CONST(3)
+#define SLINK_COMMAND2_0_N_A_8_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_N_A_8_SHIFT)
+#define SLINK_COMMAND2_0_N_A_8_RANGE                    3:3
+#define SLINK_COMMAND2_0_N_A_8_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_N_A_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define SLINK_COMMAND2_0_N_A_9_SHIFT                    _MK_SHIFT_CONST(2)
+#define SLINK_COMMAND2_0_N_A_9_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_N_A_9_SHIFT)
+#define SLINK_COMMAND2_0_N_A_9_RANGE                    2:2
+#define SLINK_COMMAND2_0_N_A_9_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_N_A_9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_N_A_9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_N_A_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = Enable 0 = Disable (def)
+#define SLINK_COMMAND2_0_SSOE_SHIFT                     _MK_SHIFT_CONST(1)
+#define SLINK_COMMAND2_0_SSOE_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SSOE_SHIFT)
+#define SLINK_COMMAND2_0_SSOE_RANGE                     1:1
+#define SLINK_COMMAND2_0_SSOE_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SSOE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SSOE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SSOE_ENABLE                    _MK_ENUM_CONST(1)
+
+//  1 = Transmit LSB first 0 = Transmit LSB last
+#define SLINK_COMMAND2_0_LSBFE_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_COMMAND2_0_LSBFE_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_LSBFE_SHIFT)
+#define SLINK_COMMAND2_0_LSBFE_RANGE                    0:0
+#define SLINK_COMMAND2_0_LSBFE_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_LSBFE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_LSBFE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_LAST                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_LSBFE_FIRST                    _MK_ENUM_CONST(1)
+
+
+// Register SLINK_STATUS_0  
+#define SLINK_STATUS_0                  _MK_ADDR_CONST(0x8)
+#define SLINK_STATUS_0_WORD_COUNT                       0x1
+#define SLINK_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0xa00000)
+#define SLINK_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SLINK_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//  1 = Controller is Busy 0 =  Controller is Free
+#define SLINK_STATUS_0_BSY_SHIFT                        _MK_SHIFT_CONST(31)
+#define SLINK_STATUS_0_BSY_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_BSY_SHIFT)
+#define SLINK_STATUS_0_BSY_RANGE                        31:31
+#define SLINK_STATUS_0_BSY_WOFFSET                      0x0
+#define SLINK_STATUS_0_BSY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_BSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_IDLE                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_BSY_BUSY                 _MK_ENUM_CONST(1)
+
+// 1= contoller is Ready for transfer 0 = controller is Busy. Write 1 to clear the flag
+#define SLINK_STATUS_0_RDY_SHIFT                        _MK_SHIFT_CONST(30)
+#define SLINK_STATUS_0_RDY_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RDY_SHIFT)
+#define SLINK_STATUS_0_RDY_RANGE                        30:30
+#define SLINK_STATUS_0_RDY_WOFFSET                      0x0
+#define SLINK_STATUS_0_RDY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RDY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_NOT_READY                    _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RDY_READY                        _MK_ENUM_CONST(1)
+
+// Will be set to 1 by HW when Errors such as Underflow/overflow occurs.Write 1 to clear the flag
+#define SLINK_STATUS_0_ERR_SHIFT                        _MK_SHIFT_CONST(29)
+#define SLINK_STATUS_0_ERR_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_ERR_SHIFT)
+#define SLINK_STATUS_0_ERR_RANGE                        29:29
+#define SLINK_STATUS_0_ERR_WOFFSET                      0x0
+#define SLINK_STATUS_0_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_OK                   _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_ERR_ERROR                        _MK_ENUM_CONST(1)
+
+// SCLK input signal State
+#define SLINK_STATUS_0_SCLK_SHIFT                       _MK_SHIFT_CONST(28)
+#define SLINK_STATUS_0_SCLK_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_SCLK_SHIFT)
+#define SLINK_STATUS_0_SCLK_RANGE                       28:28
+#define SLINK_STATUS_0_SCLK_WOFFSET                     0x0
+#define SLINK_STATUS_0_SCLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_SCLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_LOW                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_SCLK_HIGH                        _MK_ENUM_CONST(1)
+
+// Flush the RX FIFO
+#define SLINK_STATUS_0_RX_FLUSH_SHIFT                   _MK_SHIFT_CONST(27)
+#define SLINK_STATUS_0_RX_FLUSH_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_FLUSH_SHIFT)
+#define SLINK_STATUS_0_RX_FLUSH_RANGE                   27:27
+#define SLINK_STATUS_0_RX_FLUSH_WOFFSET                 0x0
+#define SLINK_STATUS_0_RX_FLUSH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_FLUSH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_NOP                     _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_FLUSH_FLUSH                   _MK_ENUM_CONST(1)
+
+// Flush the TX FIFO
+#define SLINK_STATUS_0_TX_FLUSH_SHIFT                   _MK_SHIFT_CONST(26)
+#define SLINK_STATUS_0_TX_FLUSH_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_FLUSH_SHIFT)
+#define SLINK_STATUS_0_TX_FLUSH_RANGE                   26:26
+#define SLINK_STATUS_0_TX_FLUSH_WOFFSET                 0x0
+#define SLINK_STATUS_0_TX_FLUSH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_FLUSH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_NOP                     _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_FLUSH_FLUSH                   _MK_ENUM_CONST(1)
+
+// RX FIFO Overflow
+#define SLINK_STATUS_0_RX_OVF_SHIFT                     _MK_SHIFT_CONST(25)
+#define SLINK_STATUS_0_RX_OVF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_OVF_SHIFT)
+#define SLINK_STATUS_0_RX_OVF_RANGE                     25:25
+#define SLINK_STATUS_0_RX_OVF_WOFFSET                   0x0
+#define SLINK_STATUS_0_RX_OVF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_OVF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_OVF_ERROR                     _MK_ENUM_CONST(1)
+
+// TX FIFO Underflow
+#define SLINK_STATUS_0_TX_UNF_SHIFT                     _MK_SHIFT_CONST(24)
+#define SLINK_STATUS_0_TX_UNF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_UNF_SHIFT)
+#define SLINK_STATUS_0_TX_UNF_RANGE                     24:24
+#define SLINK_STATUS_0_TX_UNF_WOFFSET                   0x0
+#define SLINK_STATUS_0_TX_UNF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_UNF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_UNF_ERROR                     _MK_ENUM_CONST(1)
+
+// RX FIFO Empty
+#define SLINK_STATUS_0_RX_EMPTY_SHIFT                   _MK_SHIFT_CONST(23)
+#define SLINK_STATUS_0_RX_EMPTY_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_EMPTY_SHIFT)
+#define SLINK_STATUS_0_RX_EMPTY_RANGE                   23:23
+#define SLINK_STATUS_0_RX_EMPTY_WOFFSET                 0x0
+#define SLINK_STATUS_0_RX_EMPTY_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_EMPTY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_EMPTY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_EMPTY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_EMPTY_NOT_EMPTY                       _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_EMPTY_EMPTY                   _MK_ENUM_CONST(1)
+
+// RX FIFO Full
+#define SLINK_STATUS_0_RX_FULL_SHIFT                    _MK_SHIFT_CONST(22)
+#define SLINK_STATUS_0_RX_FULL_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_FULL_SHIFT)
+#define SLINK_STATUS_0_RX_FULL_RANGE                    22:22
+#define SLINK_STATUS_0_RX_FULL_WOFFSET                  0x0
+#define SLINK_STATUS_0_RX_FULL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_FULL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_NOT_FULL                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_FULL_FULL                     _MK_ENUM_CONST(1)
+
+// TX FIFO Empty
+#define SLINK_STATUS_0_TX_EMPTY_SHIFT                   _MK_SHIFT_CONST(21)
+#define SLINK_STATUS_0_TX_EMPTY_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_EMPTY_SHIFT)
+#define SLINK_STATUS_0_TX_EMPTY_RANGE                   21:21
+#define SLINK_STATUS_0_TX_EMPTY_WOFFSET                 0x0
+#define SLINK_STATUS_0_TX_EMPTY_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_EMPTY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_EMPTY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_EMPTY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_EMPTY_NOT_EMPTY                       _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_EMPTY_EMPTY                   _MK_ENUM_CONST(1)
+
+// TX FIFO Full
+#define SLINK_STATUS_0_TX_FULL_SHIFT                    _MK_SHIFT_CONST(20)
+#define SLINK_STATUS_0_TX_FULL_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_FULL_SHIFT)
+#define SLINK_STATUS_0_TX_FULL_RANGE                    20:20
+#define SLINK_STATUS_0_TX_FULL_WOFFSET                  0x0
+#define SLINK_STATUS_0_TX_FULL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_FULL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_NOT_FULL                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_FULL_FULL                     _MK_ENUM_CONST(1)
+
+// TX FIFO Overflow
+#define SLINK_STATUS_0_TX_OVF_SHIFT                     _MK_SHIFT_CONST(19)
+#define SLINK_STATUS_0_TX_OVF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_OVF_SHIFT)
+#define SLINK_STATUS_0_TX_OVF_RANGE                     19:19
+#define SLINK_STATUS_0_TX_OVF_WOFFSET                   0x0
+#define SLINK_STATUS_0_TX_OVF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_OVF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_OVF_ERROR                     _MK_ENUM_CONST(1)
+
+// RX FIFO Underflow
+#define SLINK_STATUS_0_RX_UNF_SHIFT                     _MK_SHIFT_CONST(18)
+#define SLINK_STATUS_0_RX_UNF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_UNF_SHIFT)
+#define SLINK_STATUS_0_RX_UNF_RANGE                     18:18
+#define SLINK_STATUS_0_RX_UNF_WOFFSET                   0x0
+#define SLINK_STATUS_0_RX_UNF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_UNF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_UNF_ERROR                     _MK_ENUM_CONST(1)
+
+// Reserved
+#define SLINK_STATUS_0_N_A_10_SHIFT                     _MK_SHIFT_CONST(17)
+#define SLINK_STATUS_0_N_A_10_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_N_A_10_SHIFT)
+#define SLINK_STATUS_0_N_A_10_RANGE                     17:17
+#define SLINK_STATUS_0_N_A_10_WOFFSET                   0x0
+#define SLINK_STATUS_0_N_A_10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_N_A_10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_N_A_10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_N_A_10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Mode fault
+#define SLINK_STATUS_0_MODF_SHIFT                       _MK_SHIFT_CONST(16)
+#define SLINK_STATUS_0_MODF_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_MODF_SHIFT)
+#define SLINK_STATUS_0_MODF_RANGE                       16:16
+#define SLINK_STATUS_0_MODF_WOFFSET                     0x0
+#define SLINK_STATUS_0_MODF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_MODF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_OK                  _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_MODF_ERROR                       _MK_ENUM_CONST(1)
+
+// number of blocks transferred (BLOCK count) during dma
+#define SLINK_STATUS_0_BLK_CNT_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_STATUS_0_BLK_CNT_FIELD                    (_MK_MASK_CONST(0xffff) << SLINK_STATUS_0_BLK_CNT_SHIFT)
+#define SLINK_STATUS_0_BLK_CNT_RANGE                    15:0
+#define SLINK_STATUS_0_BLK_CNT_WOFFSET                  0x0
+#define SLINK_STATUS_0_BLK_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BLK_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define SLINK_STATUS_0_BLK_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BLK_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define SLINK_STATUS_0_N_A_100_SHIFT                    _MK_SHIFT_CONST(10)
+#define SLINK_STATUS_0_N_A_100_FIELD                    (_MK_MASK_CONST(0x3f) << SLINK_STATUS_0_N_A_100_SHIFT)
+#define SLINK_STATUS_0_N_A_100_RANGE                    15:10
+#define SLINK_STATUS_0_N_A_100_WOFFSET                  0x0
+#define SLINK_STATUS_0_N_A_100_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_N_A_100_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define SLINK_STATUS_0_N_A_100_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_N_A_100_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// In GO mode indicates number of words transferred (word count) 
+#define SLINK_STATUS_0_WORD_SHIFT                       _MK_SHIFT_CONST(5)
+#define SLINK_STATUS_0_WORD_FIELD                       (_MK_MASK_CONST(0x1f) << SLINK_STATUS_0_WORD_SHIFT)
+#define SLINK_STATUS_0_WORD_RANGE                       9:5
+#define SLINK_STATUS_0_WORD_WOFFSET                     0x0
+#define SLINK_STATUS_0_WORD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_WORD_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define SLINK_STATUS_0_WORD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_WORD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// In Go mode indicates mumber of bits trasnferred (bit count)
+#define SLINK_STATUS_0_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
+#define SLINK_STATUS_0_COUNT_FIELD                      (_MK_MASK_CONST(0x1f) << SLINK_STATUS_0_COUNT_SHIFT)
+#define SLINK_STATUS_0_COUNT_RANGE                      4:0
+#define SLINK_STATUS_0_COUNT_WOFFSET                    0x0
+#define SLINK_STATUS_0_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define SLINK_STATUS_0_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 12 [0xc] 
+
+// Register SLINK_MAS_DATA_0  
+#define SLINK_MAS_DATA_0                        _MK_ADDR_CONST(0x10)
+#define SLINK_MAS_DATA_0_WORD_COUNT                     0x1
+#define SLINK_MAS_DATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_FIELD                    (_MK_MASK_CONST(0xffffffff) << SLINK_MAS_DATA_0_MASTER_BUFFER_SHIFT)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_RANGE                    31:0
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_WOFFSET                  0x0
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_SLAVE_DATA_0  
+#define SLINK_SLAVE_DATA_0                      _MK_ADDR_CONST(0x14)
+#define SLINK_SLAVE_DATA_0_WORD_COUNT                   0x1
+#define SLINK_SLAVE_DATA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SHIFT                   _MK_SHIFT_CONST(0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_FIELD                   (_MK_MASK_CONST(0xffffffff) << SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SHIFT)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_RANGE                   31:0
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_WOFFSET                 0x0
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_DMA_CTL_0  
+#define SLINK_DMA_CTL_0                 _MK_ADDR_CONST(0x18)
+#define SLINK_DMA_CTL_0_WORD_COUNT                      0x1
+#define SLINK_DMA_CTL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_DMA_CTL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_DMA_CTL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+//  1 = DMA mode is enabled, 0 = DMA disabled
+#define SLINK_DMA_CTL_0_DMA_EN_SHIFT                    _MK_SHIFT_CONST(31)
+#define SLINK_DMA_CTL_0_DMA_EN_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_DMA_EN_SHIFT)
+#define SLINK_DMA_CTL_0_DMA_EN_RANGE                    31:31
+#define SLINK_DMA_CTL_0_DMA_EN_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_DMA_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_DMA_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_DMA_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reserved
+#define SLINK_DMA_CTL_0_N_A_11_SHIFT                    _MK_SHIFT_CONST(28)
+#define SLINK_DMA_CTL_0_N_A_11_FIELD                    (_MK_MASK_CONST(0x7) << SLINK_DMA_CTL_0_N_A_11_SHIFT)
+#define SLINK_DMA_CTL_0_N_A_11_RANGE                    30:28
+#define SLINK_DMA_CTL_0_N_A_11_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_N_A_11_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_N_A_11_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SLINK_DMA_CTL_0_N_A_11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_N_A_11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Interrupt enable on receive completion.
+// 1 = Enable interrupt generation at the end of a receive transfer.
+// 0 = Disable interrupt generation for receive.
+#define SLINK_DMA_CTL_0_IE_RXC_SHIFT                    _MK_SHIFT_CONST(27)
+#define SLINK_DMA_CTL_0_IE_RXC_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_IE_RXC_SHIFT)
+#define SLINK_DMA_CTL_0_IE_RXC_RANGE                    27:27
+#define SLINK_DMA_CTL_0_IE_RXC_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_IE_RXC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_IE_RXC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_IE_RXC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupt enable on transmit completion.
+// 1 = Enable interrupt generation at the end of a transmit transfer.
+// 0 = Disable interrupt generation for transmit.
+#define SLINK_DMA_CTL_0_IE_TXC_SHIFT                    _MK_SHIFT_CONST(26)
+#define SLINK_DMA_CTL_0_IE_TXC_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_IE_TXC_SHIFT)
+#define SLINK_DMA_CTL_0_IE_TXC_RANGE                    26:26
+#define SLINK_DMA_CTL_0_IE_TXC_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_IE_TXC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_IE_TXC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_IE_TXC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reserved
+#define SLINK_DMA_CTL_0_N_A_12_SHIFT                    _MK_SHIFT_CONST(23)
+#define SLINK_DMA_CTL_0_N_A_12_FIELD                    (_MK_MASK_CONST(0x7) << SLINK_DMA_CTL_0_N_A_12_SHIFT)
+#define SLINK_DMA_CTL_0_N_A_12_RANGE                    25:23
+#define SLINK_DMA_CTL_0_N_A_12_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_N_A_12_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_N_A_12_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SLINK_DMA_CTL_0_N_A_12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_N_A_12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Specifies the packet size during the DMA mode
+//             00      = 4 bits in a pack
+//           01      = 8bits in a pack
+//            10      = 16 in a pack
+//               10      = 32 in a pack
+#define SLINK_DMA_CTL_0_PACK_SIZE_SHIFT                 _MK_SHIFT_CONST(21)
+#define SLINK_DMA_CTL_0_PACK_SIZE_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_PACK_SIZE_SHIFT)
+#define SLINK_DMA_CTL_0_PACK_SIZE_RANGE                 22:21
+#define SLINK_DMA_CTL_0_PACK_SIZE_WOFFSET                       0x0
+#define SLINK_DMA_CTL_0_PACK_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_PACK_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK4                 _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK8                 _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK16                        _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK32                        _MK_ENUM_CONST(3)
+
+// Packed mode enable bit.
+//  1 = Packed mode is enabled. This is only valid if BIT_LENGTH in SBCX_COMMAND register is set to 3, 7, 15 or 31
+// When enabled, all 32-bits of data in the FIFO contains valid
+// data packets of either 8-bit or 16-bit length.
+// 0 = Packed mode is disabled.
+#define SLINK_DMA_CTL_0_PACKED_SHIFT                    _MK_SHIFT_CONST(20)
+#define SLINK_DMA_CTL_0_PACKED_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_PACKED_SHIFT)
+#define SLINK_DMA_CTL_0_PACKED_RANGE                    20:20
+#define SLINK_DMA_CTL_0_PACKED_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_PACKED_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_PACKED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_PACKED_ENABLE                   _MK_ENUM_CONST(1)
+
+// Receive FIFO trigger level.
+// 00: 1 word. DMA trigger is asserted whenever there is at least 1 word in the RX FIFO.
+// 01: 4 word. DMA trigger is asserted when there are at least 4 words in the RX FIFO.
+// 10: 8 word. DMA trigger is asserted when there are at least 8 words in the RX FIFO.
+// 11: 16 word. DMA trigger is asserted when there are at least 16 words in the RX FIFO.
+#define SLINK_DMA_CTL_0_RX_TRIG_SHIFT                   _MK_SHIFT_CONST(18)
+#define SLINK_DMA_CTL_0_RX_TRIG_FIELD                   (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_RX_TRIG_SHIFT)
+#define SLINK_DMA_CTL_0_RX_TRIG_RANGE                   19:18
+#define SLINK_DMA_CTL_0_RX_TRIG_WOFFSET                 0x0
+#define SLINK_DMA_CTL_0_RX_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_RX_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG1                   _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG4                   _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG8                   _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG16                  _MK_ENUM_CONST(3)
+
+// Transmit FIFO trigger level.
+// 00: 1 word. DMA trigger is asserted whenever there is at least 1 word in the TX FIFO.
+// 01: 4 word. DMA trigger is asserted when there are at least 4 words in the TX FIFO.
+// 10: 8 word. DMA trigger is asserted when there are at least 8 words in the TX FIFO.
+// 11: 16 word. DMA trigger is asserted when there are at least 16 words in the TX FIFO.
+#define SLINK_DMA_CTL_0_TX_TRIG_SHIFT                   _MK_SHIFT_CONST(16)
+#define SLINK_DMA_CTL_0_TX_TRIG_FIELD                   (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_TX_TRIG_SHIFT)
+#define SLINK_DMA_CTL_0_TX_TRIG_RANGE                   17:16
+#define SLINK_DMA_CTL_0_TX_TRIG_WOFFSET                 0x0
+#define SLINK_DMA_CTL_0_TX_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_TX_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG1                   _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG4                   _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG8                   _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG16                  _MK_ENUM_CONST(3)
+
+// N = N+1 packets
+// number of packets should be aligned in the packed mode trasnfers.
+// packed mode     --> Number of packets
+//    3                                        multiple of 8
+//    7                                   multiple of 4
+//    15                          multiple of 2
+//    31                          from 0 to N
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_FIELD                    (_MK_MASK_CONST(0xffff) << SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_RANGE                    15:0
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 28 [0x1c] 
+
+// Reserved address 32 [0x20] 
+
+// Reserved address 36 [0x24] 
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Reserved address 96 [0x60] 
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Reserved address 112 [0x70] 
+
+// Reserved address 116 [0x74] 
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Reserved address 240 [0xf0] 
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register SLINK_TX_FIFO_0  
+#define SLINK_TX_FIFO_0                 _MK_ADDR_CONST(0x100)
+#define SLINK_TX_FIFO_0_WORD_COUNT                      0x1
+#define SLINK_TX_FIFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT                  _MK_SHIFT_CONST(0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_FIELD                  (_MK_MASK_CONST(0xffffffff) << SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_RANGE                  31:0
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_WOFFSET                        0x0
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 260 [0x104] 
+
+// Reserved address 264 [0x108] 
+
+// Reserved address 268 [0x10c] 
+
+// Reserved address 272 [0x110] 
+
+// Reserved address 276 [0x114] 
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Reserved address 288 [0x120] 
+
+// Reserved address 292 [0x124] 
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Reserved address 320 [0x140] 
+
+// Reserved address 324 [0x144] 
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Reserved address 336 [0x150] 
+
+// Reserved address 340 [0x154] 
+
+// Reserved address 344 [0x158] 
+
+// Reserved address 348 [0x15c] 
+
+// Reserved address 352 [0x160] 
+
+// Reserved address 356 [0x164] 
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Register SLINK_RX_FIFO_0  
+#define SLINK_RX_FIFO_0                 _MK_ADDR_CONST(0x180)
+#define SLINK_RX_FIFO_0_WORD_COUNT                      0x1
+#define SLINK_RX_FIFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT                  _MK_SHIFT_CONST(0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_FIELD                  (_MK_MASK_CONST(0xffffffff) << SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_RANGE                  31:0
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_WOFFSET                        0x0
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSLINK_REGS(_op_) \
+_op_(SLINK_COMMAND_0) \
+_op_(SLINK_COMMAND2_0) \
+_op_(SLINK_STATUS_0) \
+_op_(SLINK_MAS_DATA_0) \
+_op_(SLINK_SLAVE_DATA_0) \
+_op_(SLINK_DMA_CTL_0) \
+_op_(SLINK_TX_FIFO_0) \
+_op_(SLINK_RX_FIFO_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_SLINK      0x00000000
+
+//
+// ARSLINK REGISTER BANKS
+//
+
+#define SLINK0_FIRST_REG 0x0000 // SLINK_COMMAND_0
+#define SLINK0_LAST_REG 0x0008 // SLINK_STATUS_0
+#define SLINK1_FIRST_REG 0x0010 // SLINK_MAS_DATA_0
+#define SLINK1_LAST_REG 0x0018 // SLINK_DMA_CTL_0
+#define SLINK2_FIRST_REG 0x0100 // SLINK_TX_FIFO_0
+#define SLINK2_LAST_REG 0x0100 // SLINK_TX_FIFO_0
+#define SLINK3_FIRST_REG 0x0180 // SLINK_RX_FIFO_0
+#define SLINK3_LAST_REG 0x0180 // SLINK_RX_FIFO_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARSLINK_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arspi.h b/arch/arm/mach-tegra/nv/include/ap15/arspi.h
new file mode 100644
index 000000000000..45ef3d2699e0
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arspi.h
@@ -0,0 +1,703 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARSPI_H_INC_
+#define ___ARSPI_H_INC_
+
+// Register SPI_COMMAND_0  
+#define SPI_COMMAND_0                   _MK_ADDR_CONST(0x0)
+#define SPI_COMMAND_0_WORD_COUNT                        0x1
+#define SPI_COMMAND_0_RESET_VAL                         _MK_MASK_CONST(0x10000420)
+#define SPI_COMMAND_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SPI_COMMAND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define SPI_COMMAND_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Reserved = 0
+#define SPI_COMMAND_0_N_A_1_SHIFT                       _MK_SHIFT_CONST(31)
+#define SPI_COMMAND_0_N_A_1_FIELD                       (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_N_A_1_SHIFT)
+#define SPI_COMMAND_0_N_A_1_RANGE                       31:31
+#define SPI_COMMAND_0_N_A_1_WOFFSET                     0x0
+#define SPI_COMMAND_0_N_A_1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_N_A_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Default: 0 Go Mode enable bit. Software sets this bit to 1 to enable transmit or receive of packets without specifying the no. of packets.  In receive mode, the controller receives one packet whenever software sets this bit.  In transmit mode, controller transmits all data present in the TX FIFO until TX FIFO becomes empty. If packed mode is enabled, then all packets in the last word from the TX FIFO are transmitted before finishing the transfer.  Software must set up all fields in SPI_COMMAND and SPI_DMA_CTL registers before setting this bit to 1.  This bit clears to 0 by the hardware on the completion of the transfer.  
+#define SPI_COMMAND_0_GO_SHIFT                  _MK_SHIFT_CONST(30)
+#define SPI_COMMAND_0_GO_FIELD                  (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_GO_SHIFT)
+#define SPI_COMMAND_0_GO_RANGE                  30:30
+#define SPI_COMMAND_0_GO_WOFFSET                        0x0
+#define SPI_COMMAND_0_GO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_GO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_GO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_GO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_GO_DISABLE                        _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_GO_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SPI_COMMAND_0_N_A_2_SHIFT                       _MK_SHIFT_CONST(29)
+#define SPI_COMMAND_0_N_A_2_FIELD                       (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_N_A_2_SHIFT)
+#define SPI_COMMAND_0_N_A_2_RANGE                       29:29
+#define SPI_COMMAND_0_N_A_2_WOFFSET                     0x0
+#define SPI_COMMAND_0_N_A_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_N_A_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Default: 1.  Master/slave mode select. RO 1 = Controller is operating in master mode.  0 = Controller is operating in slave mode. This bit is read-only and fixed to 1. Only master mode is supported in this design.  
+#define SPI_COMMAND_0_M_S_SHIFT                 _MK_SHIFT_CONST(28)
+#define SPI_COMMAND_0_M_S_FIELD                 (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_M_S_SHIFT)
+#define SPI_COMMAND_0_M_S_RANGE                 28:28
+#define SPI_COMMAND_0_M_S_WOFFSET                       0x0
+#define SPI_COMMAND_0_M_S_DEFAULT                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_M_S_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_M_S_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_M_S_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_M_S_SLAVE                 _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_M_S_MASTER                        _MK_ENUM_CONST(1)
+
+// Active clock signal format. Controls the output enable of the SCK line when the controller is actively doing data transfers.  00: Drive low.  01: Drive high.  10: Pull low.  11: Pull high.  Default: 00
+#define SPI_COMMAND_0_ACTIVE_SCLK_SHIFT                 _MK_SHIFT_CONST(26)
+#define SPI_COMMAND_0_ACTIVE_SCLK_FIELD                 (_MK_MASK_CONST(0x3) << SPI_COMMAND_0_ACTIVE_SCLK_SHIFT)
+#define SPI_COMMAND_0_ACTIVE_SCLK_RANGE                 27:26
+#define SPI_COMMAND_0_ACTIVE_SCLK_WOFFSET                       0x0
+#define SPI_COMMAND_0_ACTIVE_SCLK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SCLK_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SPI_COMMAND_0_ACTIVE_SCLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SCLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SCLK_DRIVE_LOW                     _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_ACTIVE_SCLK_DRIVE_HIGH                    _MK_ENUM_CONST(1)
+#define SPI_COMMAND_0_ACTIVE_SCLK_PULL_LOW                      _MK_ENUM_CONST(2)
+#define SPI_COMMAND_0_ACTIVE_SCLK_PULL_HIGH                     _MK_ENUM_CONST(3)
+
+// Reserved = 0
+#define SPI_COMMAND_0_N_A_3_SHIFT                       _MK_SHIFT_CONST(22)
+#define SPI_COMMAND_0_N_A_3_FIELD                       (_MK_MASK_CONST(0xf) << SPI_COMMAND_0_N_A_3_SHIFT)
+#define SPI_COMMAND_0_N_A_3_RANGE                       25:22
+#define SPI_COMMAND_0_N_A_3_WOFFSET                     0x0
+#define SPI_COMMAND_0_N_A_3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_3_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define SPI_COMMAND_0_N_A_3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Clock phase. Controls how the data is transferred with respect to clock edge.  0 = Data is transferred on first clock edge after CS is driven low.  1 = Data is transferred on second clock edge after CS is driven low.
+#define SPI_COMMAND_0_CK_SDA_SHIFT                      _MK_SHIFT_CONST(21)
+#define SPI_COMMAND_0_CK_SDA_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CK_SDA_SHIFT)
+#define SPI_COMMAND_0_CK_SDA_RANGE                      21:21
+#define SPI_COMMAND_0_CK_SDA_WOFFSET                    0x0
+#define SPI_COMMAND_0_CK_SDA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CK_SDA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CK_SDA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CK_SDA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CK_SDA_FIRST_CLK_EDGE                     _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CK_SDA_SECOND_CLK_EDGE                    _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SPI_COMMAND_0_N_A_4_SHIFT                       _MK_SHIFT_CONST(20)
+#define SPI_COMMAND_0_N_A_4_FIELD                       (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_N_A_4_SHIFT)
+#define SPI_COMMAND_0_N_A_4_RANGE                       20:20
+#define SPI_COMMAND_0_N_A_4_WOFFSET                     0x0
+#define SPI_COMMAND_0_N_A_4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_N_A_4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Active Data signal format. Controls the output enable of the SCK line when the controller is actively doing data transfers.  00: Drive low.  01: Drive high.  10: Pull low.  11: Pull high.  Default: 00.
+#define SPI_COMMAND_0_ACTIVE_SDA_SHIFT                  _MK_SHIFT_CONST(18)
+#define SPI_COMMAND_0_ACTIVE_SDA_FIELD                  (_MK_MASK_CONST(0x3) << SPI_COMMAND_0_ACTIVE_SDA_SHIFT)
+#define SPI_COMMAND_0_ACTIVE_SDA_RANGE                  19:18
+#define SPI_COMMAND_0_ACTIVE_SDA_WOFFSET                        0x0
+#define SPI_COMMAND_0_ACTIVE_SDA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SDA_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define SPI_COMMAND_0_ACTIVE_SDA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SDA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_ACTIVE_SDA_DRIVE_LOW                      _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_ACTIVE_SDA_DRIVE_HIGH                     _MK_ENUM_CONST(1)
+#define SPI_COMMAND_0_ACTIVE_SDA_PULL_LOW                       _MK_ENUM_CONST(2)
+#define SPI_COMMAND_0_ACTIVE_SDA_PULL_HIGH                      _MK_ENUM_CONST(3)
+
+// Reserved
+#define SPI_COMMAND_0_N_A_5_SHIFT                       _MK_SHIFT_CONST(17)
+#define SPI_COMMAND_0_N_A_5_FIELD                       (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_N_A_5_SHIFT)
+#define SPI_COMMAND_0_N_A_5_RANGE                       17:17
+#define SPI_COMMAND_0_N_A_5_WOFFSET                     0x0
+#define SPI_COMMAND_0_N_A_5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_N_A_5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_N_A_5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// CS signal Polarity.  For both SW and HW CS modes, this bit works as the polarity of the CS signal Default:0 
+#define SPI_COMMAND_0_CS_POL_SHIFT                      _MK_SHIFT_CONST(16)
+#define SPI_COMMAND_0_CS_POL_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS_POL_SHIFT)
+#define SPI_COMMAND_0_CS_POL_RANGE                      16:16
+#define SPI_COMMAND_0_CS_POL_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS_POL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_ACTIVE_LOW                 _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_POL_ACTIVE_HIGH                        _MK_ENUM_CONST(1)
+
+// Transmit enable.  1 = Transmit is enabled. Data is transmitted out from the TX FIFO to SDA output.  0 = Transmit is disabled.  Default: 0 
+#define SPI_COMMAND_0_TXEN_SHIFT                        _MK_SHIFT_CONST(15)
+#define SPI_COMMAND_0_TXEN_FIELD                        (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_TXEN_SHIFT)
+#define SPI_COMMAND_0_TXEN_RANGE                        15:15
+#define SPI_COMMAND_0_TXEN_WOFFSET                      0x0
+#define SPI_COMMAND_0_TXEN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_TXEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_TXEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_TXEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_TXEN_DISABLE                      _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_TXEN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Receive enable.  1 = Receive is enabled. Data is received on SDI line and placed in the RX FIFO.  0 = Receive is disabled.  Default: 0 
+#define SPI_COMMAND_0_RXEN_SHIFT                        _MK_SHIFT_CONST(14)
+#define SPI_COMMAND_0_RXEN_FIELD                        (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_RXEN_SHIFT)
+#define SPI_COMMAND_0_RXEN_RANGE                        14:14
+#define SPI_COMMAND_0_RXEN_WOFFSET                      0x0
+#define SPI_COMMAND_0_RXEN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_RXEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_RXEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_RXEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_RXEN_DISABLE                      _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_RXEN_ENABLE                       _MK_ENUM_CONST(1)
+
+// CS signal value/polarity.  If CS_SOFT is 1, then the value in CS_VAL is driven out on SPI_CS. If  CS_SOFT is 0, then this bit works as the polarity of the CS signal and is driven to active state during packet transfers and inactive state in between packet transfers. 
+#define SPI_COMMAND_0_CS_VAL_SHIFT                      _MK_SHIFT_CONST(13)
+#define SPI_COMMAND_0_CS_VAL_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS_VAL_SHIFT)
+#define SPI_COMMAND_0_CS_VAL_RANGE                      13:13
+#define SPI_COMMAND_0_CS_VAL_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_VAL_LOW                        _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_VAL_HIGH                       _MK_ENUM_CONST(1)
+
+// Software control of SPI_CS signal 1 = SPI_CS is driven with the value in the CS bit.  0 = SPI_CS is driven to active during packet transfers by the hardware.  Default: 0
+#define SPI_COMMAND_0_CS_SOFT_SHIFT                     _MK_SHIFT_CONST(12)
+#define SPI_COMMAND_0_CS_SOFT_FIELD                     (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS_SOFT_SHIFT)
+#define SPI_COMMAND_0_CS_SOFT_RANGE                     12:12
+#define SPI_COMMAND_0_CS_SOFT_WOFFSET                   0x0
+#define SPI_COMMAND_0_CS_SOFT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SOFT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_SOFT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SOFT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SOFT_HW_CTL                    _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_SOFT_SW_CTL                    _MK_ENUM_CONST(1)
+
+// Programmable delay between two packets if CS is used in hardware mode (CS_SOFT = 0).  Default: 2.
+#define SPI_COMMAND_0_CS_DELAY_SHIFT                    _MK_SHIFT_CONST(9)
+#define SPI_COMMAND_0_CS_DELAY_FIELD                    (_MK_MASK_CONST(0x7) << SPI_COMMAND_0_CS_DELAY_SHIFT)
+#define SPI_COMMAND_0_CS_DELAY_RANGE                    11:9
+#define SPI_COMMAND_0_CS_DELAY_WOFFSET                  0x0
+#define SPI_COMMAND_0_CS_DELAY_DEFAULT                  _MK_MASK_CONST(0x2)
+#define SPI_COMMAND_0_CS_DELAY_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SPI_COMMAND_0_CS_DELAY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_DELAY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Enable for Chip select 3: 1 = cs3 is enabled.  0 = cs3 is disabled. (Default)
+#define SPI_COMMAND_0_CS3_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define SPI_COMMAND_0_CS3_EN_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS3_EN_SHIFT)
+#define SPI_COMMAND_0_CS3_EN_RANGE                      8:8
+#define SPI_COMMAND_0_CS3_EN_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS3_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS3_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS3_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS3_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS3_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS3_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Enable for Chip select 2: 1 = cs2 is enabled.  0 = cs2 is disabled. (Default)
+#define SPI_COMMAND_0_CS2_EN_SHIFT                      _MK_SHIFT_CONST(7)
+#define SPI_COMMAND_0_CS2_EN_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS2_EN_SHIFT)
+#define SPI_COMMAND_0_CS2_EN_RANGE                      7:7
+#define SPI_COMMAND_0_CS2_EN_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS2_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS2_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS2_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS2_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS2_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS2_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Enable for Chip select 1: 1 = cs1 is enabled.  0 = cs1 is disabled. (Default)
+#define SPI_COMMAND_0_CS1_EN_SHIFT                      _MK_SHIFT_CONST(6)
+#define SPI_COMMAND_0_CS1_EN_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS1_EN_SHIFT)
+#define SPI_COMMAND_0_CS1_EN_RANGE                      6:6
+#define SPI_COMMAND_0_CS1_EN_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS1_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS1_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS1_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS1_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS1_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS1_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Enable for Chip select 0: 1 = cs0 is enabled(Default).  0 = cs0 is disabled
+#define SPI_COMMAND_0_CS0_EN_SHIFT                      _MK_SHIFT_CONST(5)
+#define SPI_COMMAND_0_CS0_EN_FIELD                      (_MK_MASK_CONST(0x1) << SPI_COMMAND_0_CS0_EN_SHIFT)
+#define SPI_COMMAND_0_CS0_EN_RANGE                      5:5
+#define SPI_COMMAND_0_CS0_EN_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS0_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS0_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS0_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS0_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS0_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS0_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Bit stream length.  0 = Single bit transfer.  1 = 2 bit transfer N = N + 1 bit transfer.  31 = 32 bit transfer (max) Default: 0 
+#define SPI_COMMAND_0_BIT_LENGTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define SPI_COMMAND_0_BIT_LENGTH_FIELD                  (_MK_MASK_CONST(0x1f) << SPI_COMMAND_0_BIT_LENGTH_SHIFT)
+#define SPI_COMMAND_0_BIT_LENGTH_RANGE                  4:0
+#define SPI_COMMAND_0_BIT_LENGTH_WOFFSET                        0x0
+#define SPI_COMMAND_0_BIT_LENGTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIT_LENGTH_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define SPI_COMMAND_0_BIT_LENGTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIT_LENGTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register SPI_STATUS_0  
+#define SPI_STATUS_0                    _MK_ADDR_CONST(0x4)
+#define SPI_STATUS_0_WORD_COUNT                         0x1
+#define SPI_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x2800000)
+#define SPI_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define SPI_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SPI_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Busy bit. Indicates that the controller is currently doing a data transfer.  This bit is set at the start of every transfer and will be cleared at the end of every transfer.  Default: 0 
+#define SPI_STATUS_0_BSY_SHIFT                  _MK_SHIFT_CONST(31)
+#define SPI_STATUS_0_BSY_FIELD                  (_MK_MASK_CONST(0x1) << SPI_STATUS_0_BSY_SHIFT)
+#define SPI_STATUS_0_BSY_RANGE                  31:31
+#define SPI_STATUS_0_BSY_WOFFSET                        0x0
+#define SPI_STATUS_0_BSY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_BSY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_BSY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_BSY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_BSY_NOT_BUSY                       _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_BSY_BUSY                   _MK_ENUM_CONST(1)
+
+// Ready bit. This bit is set at the end of every transfer and an interrupt is also generated if the corresponding interrupt enable is set. Software writes a 1 to clear it. The interrupt is also cleared when this bit is cleared.  Default: 0 
+#define SPI_STATUS_0_RDY_SHIFT                  _MK_SHIFT_CONST(30)
+#define SPI_STATUS_0_RDY_FIELD                  (_MK_MASK_CONST(0x1) << SPI_STATUS_0_RDY_SHIFT)
+#define SPI_STATUS_0_RDY_RANGE                  30:30
+#define SPI_STATUS_0_RDY_WOFFSET                        0x0
+#define SPI_STATUS_0_RDY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RDY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RDY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RDY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RDY_NOT_READY                      _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_RDY_READY                  _MK_ENUM_CONST(1)
+
+// RX FIFO Flush: WO. Software writes 1 to this bit to flush the RX FIFO. This bit will read 1 when the flush operation is in progress and will return to 0 when it is finished.  Default: 0 
+#define SPI_STATUS_0_RXF_FLUSH_SHIFT                    _MK_SHIFT_CONST(29)
+#define SPI_STATUS_0_RXF_FLUSH_FIELD                    (_MK_MASK_CONST(0x1) << SPI_STATUS_0_RXF_FLUSH_SHIFT)
+#define SPI_STATUS_0_RXF_FLUSH_RANGE                    29:29
+#define SPI_STATUS_0_RXF_FLUSH_WOFFSET                  0x0
+#define SPI_STATUS_0_RXF_FLUSH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FLUSH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RXF_FLUSH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FLUSH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FLUSH_DISABLE                  _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_RXF_FLUSH_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX FIFO Flush: WO. Software writes 1 to this bit to flush the TX FIFO. This bit will read 1 when the flush operation is in progress and will return to 0 when it is finished.  Default: 0 
+#define SPI_STATUS_0_TXF_FLUSH_SHIFT                    _MK_SHIFT_CONST(28)
+#define SPI_STATUS_0_TXF_FLUSH_FIELD                    (_MK_MASK_CONST(0x1) << SPI_STATUS_0_TXF_FLUSH_SHIFT)
+#define SPI_STATUS_0_TXF_FLUSH_RANGE                    28:28
+#define SPI_STATUS_0_TXF_FLUSH_WOFFSET                  0x0
+#define SPI_STATUS_0_TXF_FLUSH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FLUSH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_TXF_FLUSH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FLUSH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FLUSH_DISABLE                  _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_TXF_FLUSH_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX FIFO Under run: RO.  This bit is set to 1 whenever software tries to read from an empty RX FIFO. An interrupt is generated if the interrupt enable is set for receive operation (IE.RXC in SPI_DMA_CTL register). Software writes a 1 to clear this bit. Clearing this bit also clears the interrupt.  Default: 0 
+#define SPI_STATUS_0_RXF_UNR_SHIFT                      _MK_SHIFT_CONST(27)
+#define SPI_STATUS_0_RXF_UNR_FIELD                      (_MK_MASK_CONST(0x1) << SPI_STATUS_0_RXF_UNR_SHIFT)
+#define SPI_STATUS_0_RXF_UNR_RANGE                      27:27
+#define SPI_STATUS_0_RXF_UNR_WOFFSET                    0x0
+#define SPI_STATUS_0_RXF_UNR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_UNR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RXF_UNR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_UNR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_UNR_UNSET                      _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_RXF_UNR_SET                        _MK_ENUM_CONST(1)
+
+// TX FIFO Overflow: RO.  This bit is set to 1 whenever software tries to write to a full TX FIFO. An interrupt is generated if the interrupt enable is set for transmit operation (IE.TXC in SPI_DMA_CTL register). Software writes a 1 to clear this bit. Clearing this bit also clears the interrupt.  Default: 0 
+#define SPI_STATUS_0_TXF_OVF_SHIFT                      _MK_SHIFT_CONST(26)
+#define SPI_STATUS_0_TXF_OVF_FIELD                      (_MK_MASK_CONST(0x1) << SPI_STATUS_0_TXF_OVF_SHIFT)
+#define SPI_STATUS_0_TXF_OVF_RANGE                      26:26
+#define SPI_STATUS_0_TXF_OVF_WOFFSET                    0x0
+#define SPI_STATUS_0_TXF_OVF_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_OVF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_TXF_OVF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_OVF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_OVF_UNSET                      _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_TXF_OVF_SET                        _MK_ENUM_CONST(1)
+
+// RX FIFO empty status: RO.  Hardware sets this bit to 1 if RX FIFO is empty. Otherwise, this bit is set to 0.  Default: 1. FIFO is empty at POR.  
+#define SPI_STATUS_0_RXF_EMPTY_SHIFT                    _MK_SHIFT_CONST(25)
+#define SPI_STATUS_0_RXF_EMPTY_FIELD                    (_MK_MASK_CONST(0x1) << SPI_STATUS_0_RXF_EMPTY_SHIFT)
+#define SPI_STATUS_0_RXF_EMPTY_RANGE                    25:25
+#define SPI_STATUS_0_RXF_EMPTY_WOFFSET                  0x0
+#define SPI_STATUS_0_RXF_EMPTY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RXF_EMPTY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RXF_EMPTY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_EMPTY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_EMPTY_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_RXF_EMPTY_EMPTY                    _MK_ENUM_CONST(1)
+
+// RX FIFO full status: RO.  Hardware sets this bit to 1 if RX FIFO is full. Otherwise, this bit is set to 0.  Default: 0. FIFO is empty at POR.  
+#define SPI_STATUS_0_RXF_FULL_SHIFT                     _MK_SHIFT_CONST(24)
+#define SPI_STATUS_0_RXF_FULL_FIELD                     (_MK_MASK_CONST(0x1) << SPI_STATUS_0_RXF_FULL_SHIFT)
+#define SPI_STATUS_0_RXF_FULL_RANGE                     24:24
+#define SPI_STATUS_0_RXF_FULL_WOFFSET                   0x0
+#define SPI_STATUS_0_RXF_FULL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FULL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_RXF_FULL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FULL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_RXF_FULL_NOT_FULL                  _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_RXF_FULL_FULL                      _MK_ENUM_CONST(1)
+
+// TX FIFO empty status: RO.  Hardware sets this bit to 1 if TX FIFO is empty. Otherwise, this bit is set to 0.  Default: 1. FIFO is empty at POR.  
+#define SPI_STATUS_0_TXF_EMPTY_SHIFT                    _MK_SHIFT_CONST(23)
+#define SPI_STATUS_0_TXF_EMPTY_FIELD                    (_MK_MASK_CONST(0x1) << SPI_STATUS_0_TXF_EMPTY_SHIFT)
+#define SPI_STATUS_0_TXF_EMPTY_RANGE                    23:23
+#define SPI_STATUS_0_TXF_EMPTY_WOFFSET                  0x0
+#define SPI_STATUS_0_TXF_EMPTY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_TXF_EMPTY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_TXF_EMPTY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_EMPTY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_EMPTY_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_TXF_EMPTY_EMPTY                    _MK_ENUM_CONST(1)
+
+// TX FIFO full status: RO.  Hardware sets this bit to 1 if TX FIFO is full. Otherwise, this bit is set to 0.  Default: 0. FIFO is empty at POR.  
+#define SPI_STATUS_0_TXF_FULL_SHIFT                     _MK_SHIFT_CONST(22)
+#define SPI_STATUS_0_TXF_FULL_FIELD                     (_MK_MASK_CONST(0x1) << SPI_STATUS_0_TXF_FULL_SHIFT)
+#define SPI_STATUS_0_TXF_FULL_RANGE                     22:22
+#define SPI_STATUS_0_TXF_FULL_WOFFSET                   0x0
+#define SPI_STATUS_0_TXF_FULL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FULL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_TXF_FULL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FULL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_TXF_FULL_NOT_FULL                  _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_TXF_FULL_FULL                      _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SPI_STATUS_0_N_A_6_SHIFT                        _MK_SHIFT_CONST(17)
+#define SPI_STATUS_0_N_A_6_FIELD                        (_MK_MASK_CONST(0x1f) << SPI_STATUS_0_N_A_6_SHIFT)
+#define SPI_STATUS_0_N_A_6_RANGE                        21:17
+#define SPI_STATUS_0_N_A_6_WOFFSET                      0x0
+#define SPI_STATUS_0_N_A_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_N_A_6_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define SPI_STATUS_0_N_A_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_N_A_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Selects whether the receive or transmit block count to be read in the field CUR_BLOCK_COUNT.  1: Transmit block count will be read in CUR_BLOCK_COUNT.  0: Receive block count will be read in CUR_BLOCK_COUNT.  Default: 0.  
+#define SPI_STATUS_0_SEL_TX_RX_N_SHIFT                  _MK_SHIFT_CONST(16)
+#define SPI_STATUS_0_SEL_TX_RX_N_FIELD                  (_MK_MASK_CONST(0x1) << SPI_STATUS_0_SEL_TX_RX_N_SHIFT)
+#define SPI_STATUS_0_SEL_TX_RX_N_RANGE                  16:16
+#define SPI_STATUS_0_SEL_TX_RX_N_WOFFSET                        0x0
+#define SPI_STATUS_0_SEL_TX_RX_N_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_SEL_TX_RX_N_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SPI_STATUS_0_SEL_TX_RX_N_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_SEL_TX_RX_N_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_SEL_TX_RX_N_SEL_RX_CNT                     _MK_ENUM_CONST(0)
+#define SPI_STATUS_0_SEL_TX_RX_N_SEL_TX_CNT                     _MK_ENUM_CONST(1)
+
+// Selects whether the receive or transmit block count to be read in the field CUR_BLOCK_COUNT.  1: Transmit block count will be read in CUR_BLOCK_COUNT.  0: Receive block count will be read in CUR_BLOCK_COUNT.  Default: 0.  
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_FIELD                      (_MK_MASK_CONST(0xffff) << SPI_STATUS_0_CUR_BLOCK_COUNT_SHIFT)
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_RANGE                      15:0
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_WOFFSET                    0x0
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_STATUS_0_CUR_BLOCK_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register SPI_RX_CMP_0  
+#define SPI_RX_CMP_0                    _MK_ADDR_CONST(0x8)
+#define SPI_RX_CMP_0_WORD_COUNT                         0x1
+#define SPI_RX_CMP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define SPI_RX_CMP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SPI_RX_CMP_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Reserved = 0
+#define SPI_RX_CMP_0_N_A_7_SHIFT                        _MK_SHIFT_CONST(17)
+#define SPI_RX_CMP_0_N_A_7_FIELD                        (_MK_MASK_CONST(0x7fff) << SPI_RX_CMP_0_N_A_7_SHIFT)
+#define SPI_RX_CMP_0_N_A_7_RANGE                        31:17
+#define SPI_RX_CMP_0_N_A_7_WOFFSET                      0x0
+#define SPI_RX_CMP_0_N_A_7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_N_A_7_DEFAULT_MASK                 _MK_MASK_CONST(0x7fff)
+#define SPI_RX_CMP_0_N_A_7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_N_A_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Enable Receive Compare mode.  1 = Enable receive compare mode. Data received on SDI signal is ignored until a compare match occurs, that is, if the mask on the data input by RXCMP_MASK matches the RXCMP_VAL. This is only valid if the BIT_LENGTH field in SPI_COMMAND register is set to 7 (8-bit packet length).  0 = Disable receive compare mode. All data received on SDI signal is placed in the RX FIFO.  Default: 0 
+#define SPI_RX_CMP_0_RXCMP_EN_SHIFT                     _MK_SHIFT_CONST(16)
+#define SPI_RX_CMP_0_RXCMP_EN_FIELD                     (_MK_MASK_CONST(0x1) << SPI_RX_CMP_0_RXCMP_EN_SHIFT)
+#define SPI_RX_CMP_0_RXCMP_EN_RANGE                     16:16
+#define SPI_RX_CMP_0_RXCMP_EN_WOFFSET                   0x0
+#define SPI_RX_CMP_0_RXCMP_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SPI_RX_CMP_0_RXCMP_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define SPI_RX_CMP_0_RXCMP_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Mask on the receive data.  This mask value is applied to the receive data before comparing it to RXCMP_VAL for a match. A 1 in any bit position in RXCMP_MASK will exclude that bit position in the received data from comparing against corresponding bit position in RXCMP_VAL. Only the bits that have 0 will be compared.  Default: 0 
+#define SPI_RX_CMP_0_RXCMP_MASK_SHIFT                   _MK_SHIFT_CONST(8)
+#define SPI_RX_CMP_0_RXCMP_MASK_FIELD                   (_MK_MASK_CONST(0xff) << SPI_RX_CMP_0_RXCMP_MASK_SHIFT)
+#define SPI_RX_CMP_0_RXCMP_MASK_RANGE                   15:8
+#define SPI_RX_CMP_0_RXCMP_MASK_WOFFSET                 0x0
+#define SPI_RX_CMP_0_RXCMP_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define SPI_RX_CMP_0_RXCMP_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Receive compare value.  This value is compared to the received data after applying the mask in RXCMP_MASK.  Default:0 
+#define SPI_RX_CMP_0_RXCMP_VAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define SPI_RX_CMP_0_RXCMP_VAL_FIELD                    (_MK_MASK_CONST(0xff) << SPI_RX_CMP_0_RXCMP_VAL_SHIFT)
+#define SPI_RX_CMP_0_RXCMP_VAL_RANGE                    7:0
+#define SPI_RX_CMP_0_RXCMP_VAL_WOFFSET                  0x0
+#define SPI_RX_CMP_0_RXCMP_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define SPI_RX_CMP_0_RXCMP_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_RX_CMP_0_RXCMP_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SPI_DMA_CTL_0  
+#define SPI_DMA_CTL_0                   _MK_ADDR_CONST(0xc)
+#define SPI_DMA_CTL_0_WORD_COUNT                        0x1
+#define SPI_DMA_CTL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SPI_DMA_CTL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define SPI_DMA_CTL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Enable DMA mode transfer.  Software writes a 1 to this bit to start a transfer in the DMA mode. All fields in the SPI_COMMAND and SPI_DMA_CTL register must be set before writing a 1 to this bit. This bit is cleared by the controller after all packets have been transferred as indicated by the DMA_BLOCK_SIZE field.  Default: 0 
+#define SPI_DMA_CTL_0_DMA_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define SPI_DMA_CTL_0_DMA_EN_FIELD                      (_MK_MASK_CONST(0x1) << SPI_DMA_CTL_0_DMA_EN_SHIFT)
+#define SPI_DMA_CTL_0_DMA_EN_RANGE                      31:31
+#define SPI_DMA_CTL_0_DMA_EN_WOFFSET                    0x0
+#define SPI_DMA_CTL_0_DMA_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_DMA_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_DMA_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SPI_DMA_CTL_0_N_A_8_SHIFT                       _MK_SHIFT_CONST(28)
+#define SPI_DMA_CTL_0_N_A_8_FIELD                       (_MK_MASK_CONST(0x7) << SPI_DMA_CTL_0_N_A_8_SHIFT)
+#define SPI_DMA_CTL_0_N_A_8_RANGE                       30:28
+#define SPI_DMA_CTL_0_N_A_8_WOFFSET                     0x0
+#define SPI_DMA_CTL_0_N_A_8_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_N_A_8_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define SPI_DMA_CTL_0_N_A_8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_N_A_8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Interrupt enable on receive completion.  1 = Enable interrupt generation at the end of a receive transfer.  0 = Disable interrupt generation for receive.  Default: 0 
+#define SPI_DMA_CTL_0_IE_RXC_SHIFT                      _MK_SHIFT_CONST(27)
+#define SPI_DMA_CTL_0_IE_RXC_FIELD                      (_MK_MASK_CONST(0x1) << SPI_DMA_CTL_0_IE_RXC_SHIFT)
+#define SPI_DMA_CTL_0_IE_RXC_RANGE                      27:27
+#define SPI_DMA_CTL_0_IE_RXC_WOFFSET                    0x0
+#define SPI_DMA_CTL_0_IE_RXC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_RXC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_IE_RXC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_RXC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_RXC_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_IE_RXC_ENABLE                     _MK_ENUM_CONST(1)
+
+// Interrupt enable on transmit completion.  1 = Enable interrupt generation at the end of a transmit transfer.  0 = Disable interrupt generation for transmit.  Default: 0 
+#define SPI_DMA_CTL_0_IE_TXC_SHIFT                      _MK_SHIFT_CONST(26)
+#define SPI_DMA_CTL_0_IE_TXC_FIELD                      (_MK_MASK_CONST(0x1) << SPI_DMA_CTL_0_IE_TXC_SHIFT)
+#define SPI_DMA_CTL_0_IE_TXC_RANGE                      26:26
+#define SPI_DMA_CTL_0_IE_TXC_WOFFSET                    0x0
+#define SPI_DMA_CTL_0_IE_TXC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_TXC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_IE_TXC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_TXC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_IE_TXC_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_IE_TXC_ENABLE                     _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define SPI_DMA_CTL_0_N_A_9_SHIFT                       _MK_SHIFT_CONST(21)
+#define SPI_DMA_CTL_0_N_A_9_FIELD                       (_MK_MASK_CONST(0x1f) << SPI_DMA_CTL_0_N_A_9_SHIFT)
+#define SPI_DMA_CTL_0_N_A_9_RANGE                       25:21
+#define SPI_DMA_CTL_0_N_A_9_WOFFSET                     0x0
+#define SPI_DMA_CTL_0_N_A_9_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_N_A_9_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define SPI_DMA_CTL_0_N_A_9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_N_A_9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Packed mode enable bit.  1 = Packed mode is enabled. This is only valid if BIT_LENGTH in SPI_COMMAND register is set to either 7 (8-bit transfer) or 15 (16-bit transfer). When enabled, all 32-bits of data in the FIFO contains valid data packets of either 8-bit or 16-bit length.  0 = Packed mode is disabled.  Default: 0 
+#define SPI_DMA_CTL_0_PACKED_SHIFT                      _MK_SHIFT_CONST(20)
+#define SPI_DMA_CTL_0_PACKED_FIELD                      (_MK_MASK_CONST(0x1) << SPI_DMA_CTL_0_PACKED_SHIFT)
+#define SPI_DMA_CTL_0_PACKED_RANGE                      20:20
+#define SPI_DMA_CTL_0_PACKED_WOFFSET                    0x0
+#define SPI_DMA_CTL_0_PACKED_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_PACKED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_PACKED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_PACKED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_PACKED_DISABLE                    _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_PACKED_ENABLE                     _MK_ENUM_CONST(1)
+
+//  Receive FIFO Trigger level 00: 1 word. DMA trigger is asserted whenever there is space for at least 1 word in the TX FIFO.  01: 4 words. DMA trigger is asserted when there is space for 4 words in the TX FIFO.  10: Reserved.  11: Reserved
+#define SPI_DMA_CTL_0_RX_TRIG_SHIFT                     _MK_SHIFT_CONST(18)
+#define SPI_DMA_CTL_0_RX_TRIG_FIELD                     (_MK_MASK_CONST(0x3) << SPI_DMA_CTL_0_RX_TRIG_SHIFT)
+#define SPI_DMA_CTL_0_RX_TRIG_RANGE                     19:18
+#define SPI_DMA_CTL_0_RX_TRIG_WOFFSET                   0x0
+#define SPI_DMA_CTL_0_RX_TRIG_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RX_TRIG_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SPI_DMA_CTL_0_RX_TRIG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RX_TRIG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RX_TRIG_TRIG1                     _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_RX_TRIG_TRIG4                     _MK_ENUM_CONST(1)
+
+// Transmit FIFO trigger level.  00: 1 word. DMA trigger is asserted whenever there is space for at least 1 word in the TX FIFO.  01: 4 words. DMA trigger is asserted when there is space for 4 words in the TX FIFO.  10: Reserved.  11: Reserved.  Default: 00 
+#define SPI_DMA_CTL_0_TX_TRIG_SHIFT                     _MK_SHIFT_CONST(16)
+#define SPI_DMA_CTL_0_TX_TRIG_FIELD                     (_MK_MASK_CONST(0x3) << SPI_DMA_CTL_0_TX_TRIG_SHIFT)
+#define SPI_DMA_CTL_0_TX_TRIG_RANGE                     17:16
+#define SPI_DMA_CTL_0_TX_TRIG_WOFFSET                   0x0
+#define SPI_DMA_CTL_0_TX_TRIG_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_TX_TRIG_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SPI_DMA_CTL_0_TX_TRIG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_TX_TRIG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_TX_TRIG_TRIG1                     _MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_TX_TRIG_TRIG4                     _MK_ENUM_CONST(1)
+
+// Size of data block to be transferred using DMA mode.  This field specifies the size of the data block to be transferred through DMA mode.  N: N + 1 Data packets.  Default: 0 
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT                      _MK_SHIFT_CONST(0)
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_FIELD                      (_MK_MASK_CONST(0xffff) << SPI_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT)
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_RANGE                      15:0
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_WOFFSET                    0x0
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register SPI_TX_FIFO_0  
+#define SPI_TX_FIFO_0                   _MK_ADDR_CONST(0x10)
+#define SPI_TX_FIFO_0_WORD_COUNT                        0x1
+#define SPI_TX_FIFO_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SPI_TX_FIFO_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_READ_MASK                         _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// TX FIFO
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_SHIFT                 _MK_SHIFT_CONST(0)
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_FIELD                 (_MK_MASK_CONST(0xffffffff) << SPI_TX_FIFO_0_SPI_TX_FIFO_SHIFT)
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_RANGE                 31:0
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_WOFFSET                       0x0
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_SPI_TX_FIFO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+
+// Register SPI_RX_FIFO_0  
+#define SPI_RX_FIFO_0                   _MK_ADDR_CONST(0x20)
+#define SPI_RX_FIFO_0_WORD_COUNT                        0x1
+#define SPI_RX_FIFO_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SPI_RX_FIFO_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define SPI_RX_FIFO_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// RX FIFO
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_SHIFT                 _MK_SHIFT_CONST(0)
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_FIELD                 (_MK_MASK_CONST(0xffffffff) << SPI_RX_FIFO_0_SPI_RX_FIFO_SHIFT)
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_RANGE                 31:0
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_WOFFSET                       0x0
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_SPI_RX_FIFO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSPI_REGS(_op_) \
+_op_(SPI_COMMAND_0) \
+_op_(SPI_STATUS_0) \
+_op_(SPI_RX_CMP_0) \
+_op_(SPI_DMA_CTL_0) \
+_op_(SPI_TX_FIFO_0) \
+_op_(SPI_RX_FIFO_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_SPI        0x00000000
+
+//
+// ARSPI REGISTER BANKS
+//
+
+#define SPI0_FIRST_REG 0x0000 // SPI_COMMAND_0
+#define SPI0_LAST_REG 0x0010 // SPI_TX_FIFO_0
+#define SPI1_FIRST_REG 0x0020 // SPI_RX_FIFO_0
+#define SPI1_LAST_REG 0x0020 // SPI_RX_FIFO_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARSPI_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arstat_mon.h b/arch/arm/mach-tegra/nv/include/ap15/arstat_mon.h
new file mode 100644
index 000000000000..f755e20b2571
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arstat_mon.h
@@ -0,0 +1,1696 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARSTAT_MON_H_INC_
+#define ___ARSTAT_MON_H_INC_
+
+// Register STAT_MON_GLB_INT_STATUS_0  
+#define STAT_MON_GLB_INT_STATUS_0                       _MK_ADDR_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_GLB_INT_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_GLB_INT_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_GLB_INT_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// CPU Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_SHIFT                 _MK_SHIFT_CONST(31)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_CPU_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_RANGE                 31:31
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_CPU_INT_INT                   _MK_ENUM_CONST(1)
+
+// COP Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_SHIFT                 _MK_SHIFT_CONST(30)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_COP_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_RANGE                 30:30
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_COP_INT_INT                   _MK_ENUM_CONST(1)
+
+// Rsvd
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_SHIFT                    _MK_SHIFT_CONST(29)
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_N_A4_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_RANGE                    29:29
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_WOFFSET                  0x0
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// COP Cache Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_SHIFT                      _MK_SHIFT_CONST(28)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_FIELD                      (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_RANGE                      28:28
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_WOFFSET                    0x0
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_NOINT                      _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_INT_INT                        _MK_ENUM_CONST(1)
+
+// Memory Controller Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_SHIFT                 _MK_SHIFT_CONST(27)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_MEM_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_RANGE                 27:27
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_MEM_INT_INT                   _MK_ENUM_CONST(1)
+
+// Video Pipe Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_SHIFT                       _MK_SHIFT_CONST(26)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_RANGE                       26:26
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_WOFFSET                     0x0
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_INT_INT                 _MK_ENUM_CONST(1)
+
+// AHB Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_SHIFT                 _MK_SHIFT_CONST(25)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_AHB_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_RANGE                 25:25
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_AHB_INT_INT                   _MK_ENUM_CONST(1)
+
+// APB Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_SHIFT                 _MK_SHIFT_CONST(24)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_APB_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_RANGE                 24:24
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_APB_INT_INT                   _MK_ENUM_CONST(1)
+
+// Semaphore Monitor interrupt status. 1 = interrupt detected
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_SHIFT                 _MK_SHIFT_CONST(23)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_SMP_INT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_RANGE                 23:23
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_WOFFSET                       0x0
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_NOINT                 _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_GLB_INT_STATUS_0_SMP_INT_INT                   _MK_ENUM_CONST(1)
+
+// Rsvd
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_SHIFT                    _MK_SHIFT_CONST(16)
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_FIELD                    (_MK_MASK_CONST(0x7f) << STAT_MON_GLB_INT_STATUS_0_N_A3_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_RANGE                    22:16
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_WOFFSET                  0x0
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CPU monitor active status.  1 = active
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_SHIFT                     _MK_SHIFT_CONST(15)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_RANGE                     15:15
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_WOFFSET                   0x0
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_INACTIVE                  _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_CPU_MON_ACT_ACTIVE                    _MK_ENUM_CONST(1)
+
+// COP monitor active status. 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_SHIFT                     _MK_SHIFT_CONST(14)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_RANGE                     14:14
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_WOFFSET                   0x0
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_INACTIVE                  _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_COP_MON_ACT_ACTIVE                    _MK_ENUM_CONST(1)
+
+// Rsvd
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_SHIFT                    _MK_SHIFT_CONST(13)
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_N_A2_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_RANGE                    13:13
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_WOFFSET                  0x0
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// COP cache monitor active status. 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_SHIFT                  _MK_SHIFT_CONST(12)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_FIELD                  (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_RANGE                  12:12
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_WOFFSET                        0x0
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_INACTIVE                       _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_CACHE2_MON_ACT_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Rsvd
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_SHIFT                    _MK_SHIFT_CONST(11)
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_N_A1_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_RANGE                    11:11
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_WOFFSET                  0x0
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_SHIFT                   _MK_SHIFT_CONST(10)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_FIELD                   (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_RANGE                   10:10
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_WOFFSET                 0x0
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_INACTIVE                        _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_VPIPE_MON_ACT_ACTIVE                  _MK_ENUM_CONST(1)
+
+// 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_SHIFT                     _MK_SHIFT_CONST(9)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_RANGE                     9:9
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_WOFFSET                   0x0
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_INACTIVE                  _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_AHB_MON_ACT_ACTIVE                    _MK_ENUM_CONST(1)
+
+// 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_SHIFT                     _MK_SHIFT_CONST(8)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_RANGE                     8:8
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_WOFFSET                   0x0
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_INACTIVE                  _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_APB_MON_ACT_ACTIVE                    _MK_ENUM_CONST(1)
+
+// 0 = inactive. 1 = active
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_SHIFT                     _MK_SHIFT_CONST(7)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_RANGE                     7:7
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_WOFFSET                   0x0
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_INACTIVE                  _MK_ENUM_CONST(0)    // // 0 = inactive
+
+#define STAT_MON_GLB_INT_STATUS_0_SMP_MON_ACT_ACTIVE                    _MK_ENUM_CONST(1)
+
+// Rsvd
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_SHIFT                    _MK_SHIFT_CONST(0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_FIELD                    (_MK_MASK_CONST(0x7f) << STAT_MON_GLB_INT_STATUS_0_N_A0_SHIFT)
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_RANGE                    6:0
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_WOFFSET                  0x0
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_GLB_INT_STATUS_0_N_A0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 4 [0x4] 
+
+// Reserved address 8 [0x8] 
+
+// Reserved address 12 [0xc] 
+
+// Reserved address 16 [0x10] 
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+
+// Reserved address 32 [0x20] 
+
+// Reserved address 36 [0x24] 
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Reserved address 96 [0x60] 
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Reserved address 112 [0x70] 
+
+// Reserved address 116 [0x74] 
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Reserved address 240 [0xf0] 
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register STAT_MON_CPU_MON_CTRL_0  
+#define STAT_MON_CPU_MON_CTRL_0                 _MK_ADDR_CONST(0x100)
+#define STAT_MON_CPU_MON_CTRL_0_WORD_COUNT                      0x1
+#define STAT_MON_CPU_MON_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CPU_MON_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CPU_MON_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling. cpu monitor is enabled.
+// Cleared in one of the following ways,
+// (a) When SW intends to stop the  monitor, it can do so by clearing this field,
+// (b) when the sampling period  expires, or
+// (c) in case of indefinite sampling mode, 
+// the field is cleared  when the statistic counter overflows.
+#define STAT_MON_CPU_MON_CTRL_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_CPU_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_RANGE                       31:31
+#define STAT_MON_CPU_MON_CTRL_0_ENB_WOFFSET                     0x0
+#define STAT_MON_CPU_MON_CTRL_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_ENB_DISABLE                     _MK_ENUM_CONST(0)    // // cpu monitor is disabled.     
+
+#define STAT_MON_CPU_MON_CTRL_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable interrupt when sampling period expires. interrupt is enabled.
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_CPU_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_RANGE                    30:30
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_WOFFSET                  0x0
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_DISABLE                  _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_CPU_MON_CTRL_0_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_CPU_MON_CTRL_0_INT_SHIFT                       _MK_SHIFT_CONST(29)
+#define STAT_MON_CPU_MON_CTRL_0_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_CPU_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_INT_RANGE                       29:29
+#define STAT_MON_CPU_MON_CTRL_0_INT_WOFFSET                     0x0
+#define STAT_MON_CPU_MON_CTRL_0_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_CPU_MON_CTRL_0_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_CPU_MON_CTRL_0_INT_INT                 _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_RANGE                       28:28
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_WOFFSET                     0x0
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_DISABLE                     _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_MODE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                     _MK_SHIFT_CONST(20)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_FIELD                     (_MK_MASK_CONST(0xff) << STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_RANGE                     27:20
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                   0x0
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Reserved
+#define STAT_MON_CPU_MON_CTRL_0_N_A_SHIFT                       _MK_SHIFT_CONST(4)
+#define STAT_MON_CPU_MON_CTRL_0_N_A_FIELD                       (_MK_MASK_CONST(0xffff) << STAT_MON_CPU_MON_CTRL_0_N_A_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_N_A_RANGE                       19:4
+#define STAT_MON_CPU_MON_CTRL_0_N_A_WOFFSET                     0x0
+#define STAT_MON_CPU_MON_CTRL_0_N_A_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_N_A_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define STAT_MON_CPU_MON_CTRL_0_N_A_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_N_A_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 4b0000 = automatically detect CPU idle  condition.
+// Idle is defined as the period when the halt bit to the 
+// processor is asserted in the flow controller.
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_SHIFT                       _MK_SHIFT_CONST(0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_FIELD                       (_MK_MASK_CONST(0xf) << STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_RANGE                       3:0
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_WOFFSET                     0x0
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_CPU_MON_STATUS_0  
+#define STAT_MON_CPU_MON_STATUS_0                       _MK_ADDR_CONST(0x104)
+#define STAT_MON_CPU_MON_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_CPU_MON_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CPU_MON_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CPU_MON_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Indicates the number of idle cycles.
+// A value of  FFFF:FFFF is an overflow condition.
+// If the counter hits this value, it does  not increment from here.
+// This counter is always reset when the monitor is  enabled the next time.
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << STAT_MON_CPU_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_RANGE                   31:0
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_WOFFSET                 0x0
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_CPU_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 264 [0x108] 
+
+// Reserved address 268 [0x10c] 
+
+// Reserved address 272 [0x110] 
+
+// Reserved address 276 [0x114] 
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Register STAT_MON_COP_MON_CTRL_0  
+#define STAT_MON_COP_MON_CTRL_0                 _MK_ADDR_CONST(0x120)
+#define STAT_MON_COP_MON_CTRL_0_WORD_COUNT                      0x1
+#define STAT_MON_COP_MON_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_COP_MON_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_COP_MON_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling. cop monitor is enabled.
+// Cleared in one of the following ways, 
+// (a) When SW intends to stop the  monitor, it can do so by clearing this field, 
+// (b) when the sampling period  expires, or
+// (c) in case of indefinite sampling mode, the field is cleared
+// when the statistic counter overflows.
+#define STAT_MON_COP_MON_CTRL_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define STAT_MON_COP_MON_CTRL_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_COP_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_ENB_RANGE                       31:31
+#define STAT_MON_COP_MON_CTRL_0_ENB_WOFFSET                     0x0
+#define STAT_MON_COP_MON_CTRL_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_COP_MON_CTRL_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_ENB_DISABLE                     _MK_ENUM_CONST(0)    // // cop monitor is disabled.     
+
+#define STAT_MON_COP_MON_CTRL_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable interrupt when sampling period expires. interrupt is enabled.
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_COP_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_RANGE                    30:30
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_WOFFSET                  0x0
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_DISABLE                  _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_COP_MON_CTRL_0_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_COP_MON_CTRL_0_INT_SHIFT                       _MK_SHIFT_CONST(29)
+#define STAT_MON_COP_MON_CTRL_0_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_COP_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_INT_RANGE                       29:29
+#define STAT_MON_COP_MON_CTRL_0_INT_WOFFSET                     0x0
+#define STAT_MON_COP_MON_CTRL_0_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_COP_MON_CTRL_0_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_COP_MON_CTRL_0_INT_INT                 _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_RANGE                       28:28
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_WOFFSET                     0x0
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_DISABLE                     _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_MODE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                     _MK_SHIFT_CONST(20)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_FIELD                     (_MK_MASK_CONST(0xff) << STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_RANGE                     27:20
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                   0x0
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Reserved
+#define STAT_MON_COP_MON_CTRL_0_N_A_SHIFT                       _MK_SHIFT_CONST(4)
+#define STAT_MON_COP_MON_CTRL_0_N_A_FIELD                       (_MK_MASK_CONST(0xffff) << STAT_MON_COP_MON_CTRL_0_N_A_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_N_A_RANGE                       19:4
+#define STAT_MON_COP_MON_CTRL_0_N_A_WOFFSET                     0x0
+#define STAT_MON_COP_MON_CTRL_0_N_A_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_N_A_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define STAT_MON_COP_MON_CTRL_0_N_A_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_N_A_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 4b0000 = automatically detect COP idle  condition.
+// Idle is defined as the period when the halt bit to the 
+// processor is asserted in the flow controller.
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_SHIFT                       _MK_SHIFT_CONST(0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_FIELD                       (_MK_MASK_CONST(0xf) << STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_RANGE                       3:0
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_WOFFSET                     0x0
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_COP_MON_STATUS_0  
+#define STAT_MON_COP_MON_STATUS_0                       _MK_ADDR_CONST(0x124)
+#define STAT_MON_COP_MON_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_COP_MON_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_COP_MON_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_COP_MON_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Indicates the number of idle cycles.
+// A value of  FFFF:FFFF is an overflow condition.
+// If the counter hits this value, it does  not increment from here. 
+// This counter is always reset when the monitor is  enabled the next time.
+#define STAT_MON_COP_MON_STATUS_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define STAT_MON_COP_MON_STATUS_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << STAT_MON_COP_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_COP_MON_STATUS_0_COUNT_RANGE                   31:0
+#define STAT_MON_COP_MON_STATUS_0_COUNT_WOFFSET                 0x0
+#define STAT_MON_COP_MON_STATUS_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_STATUS_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_COP_MON_STATUS_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_COP_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Reserved address 320 [0x140] 
+
+// Reserved address 324 [0x144] 
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Reserved address 336 [0x150] 
+
+// Reserved address 340 [0x154] 
+
+// Reserved address 344 [0x158] 
+
+// Reserved address 348 [0x15c] 
+
+// Register STAT_MON_CACHE2_MON_CTRL_0  
+#define STAT_MON_CACHE2_MON_CTRL_0                      _MK_ADDR_CONST(0x160)
+#define STAT_MON_CACHE2_MON_CTRL_0_WORD_COUNT                   0x1
+#define STAT_MON_CACHE2_MON_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_MON_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_MON_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling.  cache2 monitor is enabled.
+// Cleared in one of the following ways,
+// (a) When SW intends to stop the  monitor, it can do so by clearing this field, or
+// (b) when the sampling period  expires.
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_CACHE2_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_RANGE                    31:31
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_WOFFSET                  0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_DISABLE                  _MK_ENUM_CONST(0)    // // cache2 monitor is disabled.     
+
+#define STAT_MON_CACHE2_MON_CTRL_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable interrupt when sampling period expires. interrupt is enabled.
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_SHIFT                 _MK_SHIFT_CONST(30)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_FIELD                 (_MK_MASK_CONST(0x1) << STAT_MON_CACHE2_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_RANGE                 30:30
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_WOFFSET                       0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_DISABLE                       _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_SHIFT                    _MK_SHIFT_CONST(29)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_CACHE2_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_RANGE                    29:29
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_WOFFSET                  0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_NOINT                    _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_CACHE2_MON_CTRL_0_INT_INT                      _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_SHIFT                    _MK_SHIFT_CONST(28)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_RANGE                    28:28
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_WOFFSET                  0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_DISABLE                  _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_MODE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                  _MK_SHIFT_CONST(20)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_FIELD                  (_MK_MASK_CONST(0xff) << STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_RANGE                  27:20
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                        0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Reserved
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_SHIFT                    _MK_SHIFT_CONST(4)
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_FIELD                    (_MK_MASK_CONST(0xffff) << STAT_MON_CACHE2_MON_CTRL_0_N_A_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_RANGE                    19:4
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_WOFFSET                  0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_N_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 4b0010 = calculate hit/miss for cacheable data  only.
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_SHIFT                    _MK_SHIFT_CONST(0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_FIELD                    (_MK_MASK_CONST(0xf) << STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_RANGE                    3:0
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_WOFFSET                  0x0
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_CACHE2_REQ_STATUS_0  
+#define STAT_MON_CACHE2_REQ_STATUS_0                    _MK_ADDR_CONST(0x164)
+#define STAT_MON_CACHE2_REQ_STATUS_0_WORD_COUNT                         0x1
+#define STAT_MON_CACHE2_REQ_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_REQ_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_REQ_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Number of cacheable requests from COP during the  sampling period.
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_CACHE2_REQ_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_RANGE                        31:0
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_WOFFSET                      0x0
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_REQ_STATUS_0_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_CACHE2_HIT_STATUS_0  
+#define STAT_MON_CACHE2_HIT_STATUS_0                    _MK_ADDR_CONST(0x168)
+#define STAT_MON_CACHE2_HIT_STATUS_0_WORD_COUNT                         0x1
+#define STAT_MON_CACHE2_HIT_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_HIT_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_HIT_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Number of cacheable requests that were hit during  the sampling period.
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_CACHE2_HIT_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_RANGE                        31:0
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_WOFFSET                      0x0
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_CACHE2_HIT_STATUS_0_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Register STAT_MON_AHB_MON_CTRL_0  
+#define STAT_MON_AHB_MON_CTRL_0                 _MK_ADDR_CONST(0x180)
+#define STAT_MON_AHB_MON_CTRL_0_WORD_COUNT                      0x1
+#define STAT_MON_AHB_MON_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_MON_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_MON_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling.  Cleared when the sampling period expires. AHB monitor is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_RANGE                       31:31
+#define STAT_MON_AHB_MON_CTRL_0_ENB_WOFFSET                     0x0
+#define STAT_MON_AHB_MON_CTRL_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_DISABLE                     _MK_ENUM_CONST(0)    // // AHB monitor is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable interrupt. interrupt is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_RANGE                    30:30
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_WOFFSET                  0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_DISABLE                  _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_AHB_MON_CTRL_0_INT_SHIFT                       _MK_SHIFT_CONST(29)
+#define STAT_MON_AHB_MON_CTRL_0_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_RANGE                       29:29
+#define STAT_MON_AHB_MON_CTRL_0_INT_WOFFSET                     0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_INT                 _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_RANGE                       28:28
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_WOFFSET                     0x0
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_DISABLE                     _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_MODE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                     _MK_SHIFT_CONST(20)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_FIELD                     (_MK_MASK_CONST(0xff) << STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_RANGE                     27:20
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                   0x0
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Enable periodic mode. periodic mode is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_SHIFT                      _MK_SHIFT_CONST(19)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_FIELD                      (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_RANGE                      19:19
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_WOFFSET                    0x0
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_DISABLE                    _MK_ENUM_CONST(0)    // // periodic mode is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_ENB_PERIODIC_ENABLE                     _MK_ENUM_CONST(1)
+
+// 
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_SHIFT                      _MK_SHIFT_CONST(16)
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_FIELD                      (_MK_MASK_CONST(0x7) << STAT_MON_AHB_MON_CTRL_0_N_A1_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_RANGE                      18:16
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_WOFFSET                    0x0
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_N_A1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Interrupt always at end of sample period. interrupt is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_SHIFT                        _MK_SHIFT_CONST(15)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_AT_END_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_RANGE                        15:15
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_WOFFSET                      0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_AT_END_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt only if count is below the lower  watermark at the end of sample period. interrupt is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_SHIFT                        _MK_SHIFT_CONST(14)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_RANGE                        14:14
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_WOFFSET                      0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_BELOW_WMARK_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt only if count is above the upper  watermark at the end of sample period. interrupt is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SHIFT                        _MK_SHIFT_CONST(13)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_RANGE                        13:13
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_WOFFSET                      0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_IF_ABOVE_WMARK_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt when count rolls over. interrupt is enabled.
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SHIFT                        _MK_SHIFT_CONST(12)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_RANGE                        12:12
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_WOFFSET                      0x0
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_AHB_MON_CTRL_0_INT_WHEN_CNT_ROVER_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reserved
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_SHIFT                      _MK_SHIFT_CONST(9)
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_FIELD                      (_MK_MASK_CONST(0x7) << STAT_MON_AHB_MON_CTRL_0_N_A0_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_RANGE                      11:9
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_WOFFSET                    0x0
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_N_A0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicate which AHB master to monitor. ALL 1s  means any master.
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_SHIFT                        _MK_SHIFT_CONST(4)
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_FIELD                        (_MK_MASK_CONST(0x1f) << STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_RANGE                        8:4
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_WOFFSET                      0x0
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_MST_NUMBER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 4b0010 = request/grant latency (one master only). 
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_SHIFT                       _MK_SHIFT_CONST(0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_FIELD                       (_MK_MASK_CONST(0xf) << STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_RANGE                       3:0
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_WOFFSET                     0x0
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_AHB_MON_STATUS_0  
+#define STAT_MON_AHB_MON_STATUS_0                       _MK_ADDR_CONST(0x184)
+#define STAT_MON_AHB_MON_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_AHB_MON_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_MON_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_MON_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Count.
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << STAT_MON_AHB_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_RANGE                   31:0
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_WOFFSET                 0x0
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_AHB_LOWER_WMARK_0  
+#define STAT_MON_AHB_LOWER_WMARK_0                      _MK_ADDR_CONST(0x188)
+#define STAT_MON_AHB_LOWER_WMARK_0_WORD_COUNT                   0x1
+#define STAT_MON_AHB_LOWER_WMARK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_LOWER_WMARK_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_LOWER_WMARK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_LOWER_WMARK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_LOWER_WMARK_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_LOWER_WMARK_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Lower watermark count value.
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_SHIFT)
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_RANGE                        31:0
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_WOFFSET                      0x0
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_LOWER_WMARK_0_LOWER_WMARK_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_AHB_UPPER_WMARK_0  
+#define STAT_MON_AHB_UPPER_WMARK_0                      _MK_ADDR_CONST(0x18c)
+#define STAT_MON_AHB_UPPER_WMARK_0_WORD_COUNT                   0x1
+#define STAT_MON_AHB_UPPER_WMARK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_UPPER_WMARK_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_UPPER_WMARK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_UPPER_WMARK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_UPPER_WMARK_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_UPPER_WMARK_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Upper watermark count value.
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_SHIFT)
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_RANGE                        31:0
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_WOFFSET                      0x0
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_AHB_UPPER_WMARK_0_UPPER_WMARK_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 400 [0x190] 
+
+// Reserved address 404 [0x194] 
+
+// Reserved address 408 [0x198] 
+
+// Reserved address 412 [0x19c] 
+
+// Register STAT_MON_APB_MON_CTRL_0  
+#define STAT_MON_APB_MON_CTRL_0                 _MK_ADDR_CONST(0x1a0)
+#define STAT_MON_APB_MON_CTRL_0_WORD_COUNT                      0x1
+#define STAT_MON_APB_MON_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_MON_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_MON_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling.  Cleared when the sampling period expires. APB monitor is enabled.
+#define STAT_MON_APB_MON_CTRL_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define STAT_MON_APB_MON_CTRL_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_ENB_RANGE                       31:31
+#define STAT_MON_APB_MON_CTRL_0_ENB_WOFFSET                     0x0
+#define STAT_MON_APB_MON_CTRL_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_DISABLE                     _MK_ENUM_CONST(0)    // // APB monitor is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable interrupt. interrupt is enabled.
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_RANGE                    30:30
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_WOFFSET                  0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_DISABLE                  _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_APB_MON_CTRL_0_INT_SHIFT                       _MK_SHIFT_CONST(29)
+#define STAT_MON_APB_MON_CTRL_0_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_RANGE                       29:29
+#define STAT_MON_APB_MON_CTRL_0_INT_WOFFSET                     0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_APB_MON_CTRL_0_INT_INT                 _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_RANGE                       28:28
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_WOFFSET                     0x0
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_DISABLE                     _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_MODE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                     _MK_SHIFT_CONST(20)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_FIELD                     (_MK_MASK_CONST(0xff) << STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_RANGE                     27:20
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                   0x0
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Enable periodic mode. periodic mode is enabled.
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_SHIFT                      _MK_SHIFT_CONST(19)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_FIELD                      (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_RANGE                      19:19
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_WOFFSET                    0x0
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_DISABLE                    _MK_ENUM_CONST(0)    // // periodic mode is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_ENB_PERIODIC_ENABLE                     _MK_ENUM_CONST(1)
+
+// 
+#define STAT_MON_APB_MON_CTRL_0_N_A1_SHIFT                      _MK_SHIFT_CONST(16)
+#define STAT_MON_APB_MON_CTRL_0_N_A1_FIELD                      (_MK_MASK_CONST(0x7) << STAT_MON_APB_MON_CTRL_0_N_A1_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_N_A1_RANGE                      18:16
+#define STAT_MON_APB_MON_CTRL_0_N_A1_WOFFSET                    0x0
+#define STAT_MON_APB_MON_CTRL_0_N_A1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_N_A1_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define STAT_MON_APB_MON_CTRL_0_N_A1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_N_A1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Interrupt always at end of sample period. interrupt is enabled.
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_SHIFT                        _MK_SHIFT_CONST(15)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_AT_END_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_RANGE                        15:15
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_WOFFSET                      0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_INT_AT_END_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt only if count is below the lower  watermark at the end of sample period. interrupt is enabled.
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_SHIFT                        _MK_SHIFT_CONST(14)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_RANGE                        14:14
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_WOFFSET                      0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_BELOW_WMARK_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt only if count is above the upper  watermark at the end of sample period. interrupt is enabled.
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SHIFT                        _MK_SHIFT_CONST(13)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_RANGE                        13:13
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_WOFFSET                      0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_INT_IF_ABOVE_WMARK_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt when count rolls over. interrupt is enabled.
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SHIFT                        _MK_SHIFT_CONST(12)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_FIELD                        (_MK_MASK_CONST(0x1) << STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_RANGE                        12:12
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_WOFFSET                      0x0
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_DISABLE                      _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_APB_MON_CTRL_0_INT_WHEN_CNT_ROVER_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reserved
+#define STAT_MON_APB_MON_CTRL_0_N_A0_SHIFT                      _MK_SHIFT_CONST(9)
+#define STAT_MON_APB_MON_CTRL_0_N_A0_FIELD                      (_MK_MASK_CONST(0x7) << STAT_MON_APB_MON_CTRL_0_N_A0_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_N_A0_RANGE                      11:9
+#define STAT_MON_APB_MON_CTRL_0_N_A0_WOFFSET                    0x0
+#define STAT_MON_APB_MON_CTRL_0_N_A0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_N_A0_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define STAT_MON_APB_MON_CTRL_0_N_A0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_N_A0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicate which APB slave to monitor. ALL 1s  means any master.
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_SHIFT                        _MK_SHIFT_CONST(4)
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_FIELD                        (_MK_MASK_CONST(0x1f) << STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_RANGE                        8:4
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_WOFFSET                      0x0
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SLV_NUMBER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 4b0001 = active data transfer count (one or any  slaves). 
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_SHIFT                       _MK_SHIFT_CONST(0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_FIELD                       (_MK_MASK_CONST(0xf) << STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_RANGE                       3:0
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_WOFFSET                     0x0
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_APB_MON_STATUS_0  
+#define STAT_MON_APB_MON_STATUS_0                       _MK_ADDR_CONST(0x1a4)
+#define STAT_MON_APB_MON_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_APB_MON_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_MON_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_MON_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Count.
+#define STAT_MON_APB_MON_STATUS_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define STAT_MON_APB_MON_STATUS_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << STAT_MON_APB_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_APB_MON_STATUS_0_COUNT_RANGE                   31:0
+#define STAT_MON_APB_MON_STATUS_0_COUNT_WOFFSET                 0x0
+#define STAT_MON_APB_MON_STATUS_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_STATUS_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_MON_STATUS_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_APB_LOWER_WMARK_0  
+#define STAT_MON_APB_LOWER_WMARK_0                      _MK_ADDR_CONST(0x1a8)
+#define STAT_MON_APB_LOWER_WMARK_0_WORD_COUNT                   0x1
+#define STAT_MON_APB_LOWER_WMARK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_LOWER_WMARK_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_LOWER_WMARK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_LOWER_WMARK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_LOWER_WMARK_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_LOWER_WMARK_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Lower watermark count value.
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_SHIFT)
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_RANGE                        31:0
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_WOFFSET                      0x0
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_LOWER_WMARK_0_LOWER_WMARK_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_APB_UPPER_WMARK_0  
+#define STAT_MON_APB_UPPER_WMARK_0                      _MK_ADDR_CONST(0x1ac)
+#define STAT_MON_APB_UPPER_WMARK_0_WORD_COUNT                   0x1
+#define STAT_MON_APB_UPPER_WMARK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_UPPER_WMARK_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_UPPER_WMARK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_UPPER_WMARK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_UPPER_WMARK_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_UPPER_WMARK_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Upper watermark count value.
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_FIELD                        (_MK_MASK_CONST(0xffffffff) << STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_SHIFT)
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_RANGE                        31:0
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_WOFFSET                      0x0
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_APB_UPPER_WMARK_0_UPPER_WMARK_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 432 [0x1b0] 
+
+// Reserved address 436 [0x1b4] 
+
+// Reserved address 440 [0x1b8] 
+
+// Reserved address 444 [0x1bc] 
+
+// Register STAT_MON_VPIPE_MON_CTRL_0  
+#define STAT_MON_VPIPE_MON_CTRL_0                       _MK_ADDR_CONST(0x1c0)
+#define STAT_MON_VPIPE_MON_CTRL_0_WORD_COUNT                    0x1
+#define STAT_MON_VPIPE_MON_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_VPIPE_MON_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_VPIPE_MON_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling.  vpipe monitor is enabled.
+// Cleared in one of the following ways,
+// (a) When SW intends to stop the  monitor, it can do so by clearing this field, or
+// (b) when the sampling period  expires.
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_SHIFT                     _MK_SHIFT_CONST(31)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_VPIPE_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_RANGE                     31:31
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_WOFFSET                   0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_DISABLE                   _MK_ENUM_CONST(0)    // // vpipe monitor is disabled.     
+
+#define STAT_MON_VPIPE_MON_CTRL_0_ENB_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable interrupt when sampling period expires. interrupt is enabled.
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_SHIFT                  _MK_SHIFT_CONST(30)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << STAT_MON_VPIPE_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_RANGE                  30:30
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_WOFFSET                        0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_DISABLE                        _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when  INT_EN is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_SHIFT                     _MK_SHIFT_CONST(29)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_VPIPE_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_RANGE                     29:29
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_WOFFSET                   0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_NOINT                     _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_VPIPE_MON_CTRL_0_INT_INT                       _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_SHIFT                     _MK_SHIFT_CONST(28)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_FIELD                     (_MK_MASK_CONST(0x1) << STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_RANGE                     28:28
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_WOFFSET                   0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_DISABLE                   _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_MODE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                   _MK_SHIFT_CONST(20)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_FIELD                   (_MK_MASK_CONST(0xff) << STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_RANGE                   27:20
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                 0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Reserved
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_SHIFT                     _MK_SHIFT_CONST(4)
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_FIELD                     (_MK_MASK_CONST(0xffff) << STAT_MON_VPIPE_MON_CTRL_0_N_A_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_RANGE                     19:4
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_WOFFSET                   0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_N_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 4b0011 = Monitor total words written during the 
+// sample period (writing to external Memory) on slot 2 + AHB: 32-bit data
+// writes only (not command data).
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_SHIFT                     _MK_SHIFT_CONST(0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_FIELD                     (_MK_MASK_CONST(0xf) << STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_SHIFT)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_RANGE                     3:0
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_WOFFSET                   0x0
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_CTRL_0_SAMPLE_COND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_VPIPE_MON_STATUS_0  
+#define STAT_MON_VPIPE_MON_STATUS_0                     _MK_ADDR_CONST(0x1c4)
+#define STAT_MON_VPIPE_MON_STATUS_0_WORD_COUNT                  0x1
+#define STAT_MON_VPIPE_MON_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_VPIPE_MON_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_VPIPE_MON_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// SAMPLE_COND = 4b0011: number of words written to  external memory in the Sample period.
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_FIELD                 (_MK_MASK_CONST(0xffffffff) << STAT_MON_VPIPE_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_RANGE                 31:0
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_WOFFSET                       0x0
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_VPIPE_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 456 [0x1c8] 
+
+// Reserved address 460 [0x1cc] 
+
+// Reserved address 464 [0x1d0] 
+
+// Reserved address 468 [0x1d4] 
+
+// Reserved address 472 [0x1d8] 
+
+// Reserved address 476 [0x1dc] 
+
+// Register STAT_MON_SMP_MON_CTRL_0  
+#define STAT_MON_SMP_MON_CTRL_0                 _MK_ADDR_CONST(0x1e0)
+#define STAT_MON_SMP_MON_CTRL_0_WORD_COUNT                      0x1
+#define STAT_MON_SMP_MON_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_SMP_MON_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_SMP_MON_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Monitor. Set by SW to enable sampling. semaphore monitor is enabled.
+// Cleared in one of the following ways,
+// (a) When SW intends to stop the  monitor, it can do so by clearing this field, or
+// (b) when the sampling period  expires.
+#define STAT_MON_SMP_MON_CTRL_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_ENB_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_RANGE                       31:31
+#define STAT_MON_SMP_MON_CTRL_0_ENB_WOFFSET                     0x0
+#define STAT_MON_SMP_MON_CTRL_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_ENB_DISABLE                     _MK_ENUM_CONST(0)    // // semaphore monitor is disabled.     
+
+#define STAT_MON_SMP_MON_CTRL_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable interrupt when sampling period expires. interrupt is enabled.
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_INT_EN_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_RANGE                    30:30
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_WOFFSET                  0x0
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_DISABLE                  _MK_ENUM_CONST(0)    // // interrupt is disabled.     
+
+#define STAT_MON_SMP_MON_CTRL_0_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Assert by HW when sampling period expires when INT_EN  is set. 1 = interrupt detected
+// SW writing a 1 clears this bit. Writing 0 is ignored.
+#define STAT_MON_SMP_MON_CTRL_0_INT_SHIFT                       _MK_SHIFT_CONST(29)
+#define STAT_MON_SMP_MON_CTRL_0_INT_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_INT_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_INT_RANGE                       29:29
+#define STAT_MON_SMP_MON_CTRL_0_INT_WOFFSET                     0x0
+#define STAT_MON_SMP_MON_CTRL_0_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_INT_NOINT                       _MK_ENUM_CONST(0)    // // 0 = interrupt not detected
+
+#define STAT_MON_SMP_MON_CTRL_0_INT_INT                 _MK_ENUM_CONST(1)
+
+// 0 = sample only for the period mentioned in  SAMPLE_PERIOD. sample mode is enabled.
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_SHIFT                       _MK_SHIFT_CONST(28)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_FIELD                       (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_RANGE                       28:28
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_WOFFSET                     0x0
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_DISABLE                     _MK_ENUM_CONST(0)    // // sample mode is disabled.     
+
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_MODE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Sampling period in milliseconds (implemented as  n+1 counter).
+// Programming a 0 imply a 1 millisecond sampling period.
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_SHIFT                     _MK_SHIFT_CONST(20)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_FIELD                     (_MK_MASK_CONST(0xff) << STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_RANGE                     27:20
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_WOFFSET                   0x0
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_SHIFT                      _MK_SHIFT_CONST(19)
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_FIELD                      (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_N_A1_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_RANGE                      19:19
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_WOFFSET                    0x0
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_N_A1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  0 = clk count mode (in number of  sclk).  countmode is enabled.
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_SHIFT                      _MK_SHIFT_CONST(18)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_FIELD                      (_MK_MASK_CONST(0x1) << STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_RANGE                      18:18
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_WOFFSET                    0x0
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_DISABLE                    _MK_ENUM_CONST(0)    // // count mode is disabled.     
+
+#define STAT_MON_SMP_MON_CTRL_0_CLK_CNT_MODE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Reserved
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_SHIFT                      _MK_SHIFT_CONST(9)
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_FIELD                      (_MK_MASK_CONST(0x1ff) << STAT_MON_SMP_MON_CTRL_0_N_A0_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_RANGE                      17:9
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_WOFFSET                    0x0
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_DEFAULT_MASK                       _MK_MASK_CONST(0x1ff)
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_N_A0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 5h1F: start counter when CMP.31 is set.
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_SHIFT                        _MK_SHIFT_CONST(4)
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_FIELD                        (_MK_MASK_CONST(0x1f) << STAT_MON_SMP_MON_CTRL_0_START_COND_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_RANGE                        8:4
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_WOFFSET                      0x0
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_START_COND_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  The sample period expires, whichever happens  first.
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_SHIFT                 _MK_SHIFT_CONST(0)
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_FIELD                 (_MK_MASK_CONST(0xf) << STAT_MON_SMP_MON_CTRL_0_STOP_COND_SHIFT)
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_RANGE                 3:0
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_WOFFSET                       0x0
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_CTRL_0_STOP_COND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register STAT_MON_SMP_MON_STATUS_0  
+#define STAT_MON_SMP_MON_STATUS_0                       _MK_ADDR_CONST(0x1e4)
+#define STAT_MON_SMP_MON_STATUS_0_WORD_COUNT                    0x1
+#define STAT_MON_SMP_MON_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_SMP_MON_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_SMP_MON_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// count
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_FIELD                   (_MK_MASK_CONST(0xffffffff) << STAT_MON_SMP_MON_STATUS_0_COUNT_SHIFT)
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_RANGE                   31:0
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_WOFFSET                 0x0
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define STAT_MON_SMP_MON_STATUS_0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSTAT_MON_REGS(_op_) \
+_op_(STAT_MON_GLB_INT_STATUS_0) \
+_op_(STAT_MON_CPU_MON_CTRL_0) \
+_op_(STAT_MON_CPU_MON_STATUS_0) \
+_op_(STAT_MON_COP_MON_CTRL_0) \
+_op_(STAT_MON_COP_MON_STATUS_0) \
+_op_(STAT_MON_CACHE2_MON_CTRL_0) \
+_op_(STAT_MON_CACHE2_REQ_STATUS_0) \
+_op_(STAT_MON_CACHE2_HIT_STATUS_0) \
+_op_(STAT_MON_AHB_MON_CTRL_0) \
+_op_(STAT_MON_AHB_MON_STATUS_0) \
+_op_(STAT_MON_AHB_LOWER_WMARK_0) \
+_op_(STAT_MON_AHB_UPPER_WMARK_0) \
+_op_(STAT_MON_APB_MON_CTRL_0) \
+_op_(STAT_MON_APB_MON_STATUS_0) \
+_op_(STAT_MON_APB_LOWER_WMARK_0) \
+_op_(STAT_MON_APB_UPPER_WMARK_0) \
+_op_(STAT_MON_VPIPE_MON_CTRL_0) \
+_op_(STAT_MON_VPIPE_MON_STATUS_0) \
+_op_(STAT_MON_SMP_MON_CTRL_0) \
+_op_(STAT_MON_SMP_MON_STATUS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_STAT_MON   0x00000000
+
+//
+// ARSTAT_MON REGISTER BANKS
+//
+
+#define STAT_MON0_FIRST_REG 0x0000 // STAT_MON_GLB_INT_STATUS_0
+#define STAT_MON0_LAST_REG 0x0000 // STAT_MON_GLB_INT_STATUS_0
+#define STAT_MON1_FIRST_REG 0x0100 // STAT_MON_CPU_MON_CTRL_0
+#define STAT_MON1_LAST_REG 0x0104 // STAT_MON_CPU_MON_STATUS_0
+#define STAT_MON2_FIRST_REG 0x0120 // STAT_MON_COP_MON_CTRL_0
+#define STAT_MON2_LAST_REG 0x0124 // STAT_MON_COP_MON_STATUS_0
+#define STAT_MON3_FIRST_REG 0x0160 // STAT_MON_CACHE2_MON_CTRL_0
+#define STAT_MON3_LAST_REG 0x0168 // STAT_MON_CACHE2_HIT_STATUS_0
+#define STAT_MON4_FIRST_REG 0x0180 // STAT_MON_AHB_MON_CTRL_0
+#define STAT_MON4_LAST_REG 0x018c // STAT_MON_AHB_UPPER_WMARK_0
+#define STAT_MON5_FIRST_REG 0x01a0 // STAT_MON_APB_MON_CTRL_0
+#define STAT_MON5_LAST_REG 0x01ac // STAT_MON_APB_UPPER_WMARK_0
+#define STAT_MON6_FIRST_REG 0x01c0 // STAT_MON_VPIPE_MON_CTRL_0
+#define STAT_MON6_LAST_REG 0x01c4 // STAT_MON_VPIPE_MON_STATUS_0
+#define STAT_MON7_FIRST_REG 0x01e0 // STAT_MON_SMP_MON_CTRL_0
+#define STAT_MON7_LAST_REG 0x01e4 // STAT_MON_SMP_MON_STATUS_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARSTAT_MON_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/artimer.h b/arch/arm/mach-tegra/nv/include/ap15/artimer.h
new file mode 100644
index 000000000000..235d6b512fab
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/artimer.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARTIMER_H_INC_
+#define ___ARTIMER_H_INC_
+
+// Register TIMER_TMR_PTV_0  
+#define TIMER_TMR_PTV_0                 _MK_ADDR_CONST(0x0)
+#define TIMER_TMR_PTV_0_WORD_COUNT                      0x1
+#define TIMER_TMR_PTV_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define TIMER_TMR_PTV_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define TIMER_TMR_PTV_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Enable Timer 
+#define TIMER_TMR_PTV_0_EN_SHIFT                        _MK_SHIFT_CONST(31)
+#define TIMER_TMR_PTV_0_EN_FIELD                        (_MK_MASK_CONST(0x1) << TIMER_TMR_PTV_0_EN_SHIFT)
+#define TIMER_TMR_PTV_0_EN_RANGE                        31:31
+#define TIMER_TMR_PTV_0_EN_WOFFSET                      0x0
+#define TIMER_TMR_PTV_0_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PTV_0_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define TIMER_TMR_PTV_0_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable Periodic Interrupt
+#define TIMER_TMR_PTV_0_PER_SHIFT                       _MK_SHIFT_CONST(30)
+#define TIMER_TMR_PTV_0_PER_FIELD                       (_MK_MASK_CONST(0x1) << TIMER_TMR_PTV_0_PER_SHIFT)
+#define TIMER_TMR_PTV_0_PER_RANGE                       30:30
+#define TIMER_TMR_PTV_0_PER_WOFFSET                     0x0
+#define TIMER_TMR_PTV_0_PER_DEFAULT                     _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_PER_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PTV_0_PER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_PER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_PER_DISABLE                     _MK_ENUM_CONST(0)
+#define TIMER_TMR_PTV_0_PER_ENABLE                      _MK_ENUM_CONST(1)
+
+// Reserved 
+#define TIMER_TMR_PTV_0_N_A_SHIFT                       _MK_SHIFT_CONST(29)
+#define TIMER_TMR_PTV_0_N_A_FIELD                       (_MK_MASK_CONST(0x1) << TIMER_TMR_PTV_0_N_A_SHIFT)
+#define TIMER_TMR_PTV_0_N_A_RANGE                       29:29
+#define TIMER_TMR_PTV_0_N_A_WOFFSET                     0x0
+#define TIMER_TMR_PTV_0_N_A_DEFAULT                     _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_N_A_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PTV_0_N_A_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_N_A_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Trigger Value: count trigger value (count length).  This
+// is in n+1 scheme.  If you program the value n, the count
+// trigger value will actually be n+1.
+#define TIMER_TMR_PTV_0_TMR_PTV_SHIFT                   _MK_SHIFT_CONST(0)
+#define TIMER_TMR_PTV_0_TMR_PTV_FIELD                   (_MK_MASK_CONST(0x1fffffff) << TIMER_TMR_PTV_0_TMR_PTV_SHIFT)
+#define TIMER_TMR_PTV_0_TMR_PTV_RANGE                   28:0
+#define TIMER_TMR_PTV_0_TMR_PTV_WOFFSET                 0x0
+#define TIMER_TMR_PTV_0_TMR_PTV_DEFAULT                 _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_TMR_PTV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define TIMER_TMR_PTV_0_TMR_PTV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_TMR_PTV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register TIMER_TMR_PCR_0  
+#define TIMER_TMR_PCR_0                 _MK_ADDR_CONST(0x4)
+#define TIMER_TMR_PCR_0_WORD_COUNT                      0x1
+#define TIMER_TMR_PCR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define TIMER_TMR_PCR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define TIMER_TMR_PCR_0_WRITE_MASK                      _MK_MASK_CONST(0x40000000)
+// Reserved = 0
+#define TIMER_TMR_PCR_0_N_A2_SHIFT                      _MK_SHIFT_CONST(31)
+#define TIMER_TMR_PCR_0_N_A2_FIELD                      (_MK_MASK_CONST(0x1) << TIMER_TMR_PCR_0_N_A2_SHIFT)
+#define TIMER_TMR_PCR_0_N_A2_RANGE                      31:31
+#define TIMER_TMR_PCR_0_N_A2_WOFFSET                    0x0
+#define TIMER_TMR_PCR_0_N_A2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_N_A2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PCR_0_N_A2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_N_A2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = clears the interrupt, 0 = no affect. Wtite-1-to-Clear
+#define TIMER_TMR_PCR_0_INTR_CLR_SHIFT                  _MK_SHIFT_CONST(30)
+#define TIMER_TMR_PCR_0_INTR_CLR_FIELD                  (_MK_MASK_CONST(0x1) << TIMER_TMR_PCR_0_INTR_CLR_SHIFT)
+#define TIMER_TMR_PCR_0_INTR_CLR_RANGE                  30:30
+#define TIMER_TMR_PCR_0_INTR_CLR_WOFFSET                        0x0
+#define TIMER_TMR_PCR_0_INTR_CLR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_INTR_CLR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PCR_0_INTR_CLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_INTR_CLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Reserved = 0 
+#define TIMER_TMR_PCR_0_N_A1_SHIFT                      _MK_SHIFT_CONST(29)
+#define TIMER_TMR_PCR_0_N_A1_FIELD                      (_MK_MASK_CONST(0x1) << TIMER_TMR_PCR_0_N_A1_SHIFT)
+#define TIMER_TMR_PCR_0_N_A1_RANGE                      29:29
+#define TIMER_TMR_PCR_0_N_A1_WOFFSET                    0x0
+#define TIMER_TMR_PCR_0_N_A1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_N_A1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define TIMER_TMR_PCR_0_N_A1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_N_A1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Counter value: decrements from PTV.
+#define TIMER_TMR_PCR_0_TMR_PCV_SHIFT                   _MK_SHIFT_CONST(0)
+#define TIMER_TMR_PCR_0_TMR_PCV_FIELD                   (_MK_MASK_CONST(0x1fffffff) << TIMER_TMR_PCR_0_TMR_PCV_SHIFT)
+#define TIMER_TMR_PCR_0_TMR_PCV_RANGE                   28:0
+#define TIMER_TMR_PCR_0_TMR_PCV_WOFFSET                 0x0
+#define TIMER_TMR_PCR_0_TMR_PCV_DEFAULT                 _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_TMR_PCV_DEFAULT_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define TIMER_TMR_PCR_0_TMR_PCV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_TMR_PCV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARTIMER_REGS(_op_) \
+_op_(TIMER_TMR_PTV_0) \
+_op_(TIMER_TMR_PCR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_TIMER      0x00000000
+
+//
+// ARTIMER REGISTER BANKS
+//
+
+#define TIMER0_FIRST_REG 0x0000 // TIMER_TMR_PTV_0
+#define TIMER0_LAST_REG 0x0004 // TIMER_TMR_PCR_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARTIMER_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/artimerus.h b/arch/arm/mach-tegra/nv/include/ap15/artimerus.h
new file mode 100644
index 000000000000..8cabac1f4349
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/artimerus.h
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARTIMERUS_H_INC_
+#define ___ARTIMERUS_H_INC_
+
+// Register TIMERUS_CNTR_1US_0  
+#define TIMERUS_CNTR_1US_0                      _MK_ADDR_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_WORD_COUNT                   0x1
+#define TIMERUS_CNTR_1US_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define TIMERUS_CNTR_1US_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define TIMERUS_CNTR_1US_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Elapsed time in micro-second 
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_SHIFT                     _MK_SHIFT_CONST(16)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_FIELD                     (_MK_MASK_CONST(0xffff) << TIMERUS_CNTR_1US_0_HIGH_VALUE_SHIFT)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_RANGE                     31:16
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_WOFFSET                   0x0
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_HIGH_VALUE_INIT_ENUM                 x
+
+// Elapsed time in micro-second 
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_FIELD                      (_MK_MASK_CONST(0xffff) << TIMERUS_CNTR_1US_0_LOW_VALUE_SHIFT)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_RANGE                      15:0
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_WOFFSET                    0x0
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define TIMERUS_CNTR_1US_0_LOW_VALUE_INIT_ENUM                  x
+
+
+// Register TIMERUS_USEC_CFG_0  
+#define TIMERUS_USEC_CFG_0                      _MK_ADDR_CONST(0x4)
+#define TIMERUS_USEC_CFG_0_WORD_COUNT                   0x1
+#define TIMERUS_USEC_CFG_0_RESET_VAL                    _MK_MASK_CONST(0xc)
+#define TIMERUS_USEC_CFG_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define TIMERUS_USEC_CFG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define TIMERUS_USEC_CFG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define TIMERUS_USEC_CFG_0_READ_MASK                    _MK_MASK_CONST(0xffff)
+#define TIMERUS_USEC_CFG_0_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+// usec dividend.
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SHIFT                  _MK_SHIFT_CONST(8)
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_FIELD                  (_MK_MASK_CONST(0xff) << TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SHIFT)
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_RANGE                  15:8
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_WOFFSET                        0x0
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_DEFAULT                        _MK_MASK_CONST(0x0)
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define TIMERUS_USEC_CFG_0_USEC_DIVIDEND_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// usec divisor.
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << TIMERUS_USEC_CFG_0_USEC_DIVISOR_SHIFT)
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_RANGE                   7:0
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_WOFFSET                 0x0
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_DEFAULT                 _MK_MASK_CONST(0xc)
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define TIMERUS_USEC_CFG_0_USEC_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARTIMERUS_REGS(_op_) \
+_op_(TIMERUS_CNTR_1US_0) \
+_op_(TIMERUS_USEC_CFG_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_TIMERUS    0x00000000
+
+//
+// ARTIMERUS REGISTER BANKS
+//
+
+#define TIMERUS0_FIRST_REG 0x0000 // TIMERUS_CNTR_1US_0
+#define TIMERUS0_LAST_REG 0x0004 // TIMERUS_USEC_CFG_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARTIMERUS_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/aruart.h b/arch/arm/mach-tegra/nv/include/ap15/aruart.h
new file mode 100644
index 000000000000..55f2d2ce4423
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/aruart.h
@@ -0,0 +1,971 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARUART_H_INC_
+#define ___ARUART_H_INC_
+
+// Register UART_THR_DLAB_0_0  
+#define UART_THR_DLAB_0_0                       _MK_ADDR_CONST(0x0)
+#define UART_THR_DLAB_0_0_WORD_COUNT                    0x1
+#define UART_THR_DLAB_0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define UART_THR_DLAB_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define UART_THR_DLAB_0_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+// Transmit holding register, holds the character to  be transmitted by the UART. In FIFO mode, a write to this FIFO places the  data at the end of the FIFO.
+#define UART_THR_DLAB_0_0_THR_A_SHIFT                   _MK_SHIFT_CONST(0)
+#define UART_THR_DLAB_0_0_THR_A_FIELD                   (_MK_MASK_CONST(0xff) << UART_THR_DLAB_0_0_THR_A_SHIFT)
+#define UART_THR_DLAB_0_0_THR_A_RANGE                   7:0
+#define UART_THR_DLAB_0_0_THR_A_WOFFSET                 0x0
+#define UART_THR_DLAB_0_0_THR_A_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_THR_A_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define UART_THR_DLAB_0_0_THR_A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_THR_A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Receive Buffer Register.  Rx Data read from here.
+#define UART_THR_DLAB_0_0_RBR_A_SHIFT                   _MK_SHIFT_CONST(0)
+#define UART_THR_DLAB_0_0_RBR_A_FIELD                   (_MK_MASK_CONST(0xff) << UART_THR_DLAB_0_0_RBR_A_SHIFT)
+#define UART_THR_DLAB_0_0_RBR_A_RANGE                   7:0
+#define UART_THR_DLAB_0_0_RBR_A_WOFFSET                 0x0
+#define UART_THR_DLAB_0_0_RBR_A_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_RBR_A_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define UART_THR_DLAB_0_0_RBR_A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_RBR_A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Divisor Latch LSB (low 8 bits of 16-bit Baud Divisor)
+#define UART_THR_DLAB_0_0_DLL_A_SHIFT                   _MK_SHIFT_CONST(0)
+#define UART_THR_DLAB_0_0_DLL_A_FIELD                   (_MK_MASK_CONST(0xff) << UART_THR_DLAB_0_0_DLL_A_SHIFT)
+#define UART_THR_DLAB_0_0_DLL_A_RANGE                   7:0
+#define UART_THR_DLAB_0_0_DLL_A_WOFFSET                 0x0
+#define UART_THR_DLAB_0_0_DLL_A_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_DLL_A_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define UART_THR_DLAB_0_0_DLL_A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_DLL_A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register UART_IER_DLAB_0_0  
+#define UART_IER_DLAB_0_0                       _MK_ADDR_CONST(0x4)
+#define UART_IER_DLAB_0_0_WORD_COUNT                    0x1
+#define UART_IER_DLAB_0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define UART_IER_DLAB_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define UART_IER_DLAB_0_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+// Reserved
+#define UART_IER_DLAB_0_0_N_A_SHIFT                     _MK_SHIFT_CONST(6)
+#define UART_IER_DLAB_0_0_N_A_FIELD                     (_MK_MASK_CONST(0x3) << UART_IER_DLAB_0_0_N_A_SHIFT)
+#define UART_IER_DLAB_0_0_N_A_RANGE                     7:6
+#define UART_IER_DLAB_0_0_N_A_WOFFSET                   0x0
+#define UART_IER_DLAB_0_0_N_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_N_A_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define UART_IER_DLAB_0_0_N_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_N_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Interrupt Enable for End of Received Data  1 = Enable    
+#define UART_IER_DLAB_0_0_IE_EORD_SHIFT                 _MK_SHIFT_CONST(5)
+#define UART_IER_DLAB_0_0_IE_EORD_FIELD                 (_MK_MASK_CONST(0x1) << UART_IER_DLAB_0_0_IE_EORD_SHIFT)
+#define UART_IER_DLAB_0_0_IE_EORD_RANGE                 5:5
+#define UART_IER_DLAB_0_0_IE_EORD_WOFFSET                       0x0
+#define UART_IER_DLAB_0_0_IE_EORD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_EORD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_EORD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_EORD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_EORD_DISABLE                       _MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_EORD_ENABLE                        _MK_ENUM_CONST(1)
+
+// Interrupt Enable for Rx FIFO timeout       1 = Enable
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SHIFT                   _MK_SHIFT_CONST(4)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_FIELD                   (_MK_MASK_CONST(0x1) << UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SHIFT)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_RANGE                   4:4
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_WOFFSET                 0x0
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_DISABLE                 _MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupt Enable for Modem Status Interrupt 
+#define UART_IER_DLAB_0_0_IE_MSI_SHIFT                  _MK_SHIFT_CONST(3)
+#define UART_IER_DLAB_0_0_IE_MSI_FIELD                  (_MK_MASK_CONST(0x1) << UART_IER_DLAB_0_0_IE_MSI_SHIFT)
+#define UART_IER_DLAB_0_0_IE_MSI_RANGE                  3:3
+#define UART_IER_DLAB_0_0_IE_MSI_WOFFSET                        0x0
+#define UART_IER_DLAB_0_0_IE_MSI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_MSI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_MSI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_MSI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_MSI_DISABLE                        _MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_MSI_ENABLE                 _MK_ENUM_CONST(1)
+
+// Interrupt Enable for Receiver Line Status Interrupt 
+#define UART_IER_DLAB_0_0_IE_RXS_SHIFT                  _MK_SHIFT_CONST(2)
+#define UART_IER_DLAB_0_0_IE_RXS_FIELD                  (_MK_MASK_CONST(0x1) << UART_IER_DLAB_0_0_IE_RXS_SHIFT)
+#define UART_IER_DLAB_0_0_IE_RXS_RANGE                  2:2
+#define UART_IER_DLAB_0_0_IE_RXS_WOFFSET                        0x0
+#define UART_IER_DLAB_0_0_IE_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RXS_DISABLE                        _MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_RXS_ENABLE                 _MK_ENUM_CONST(1)
+
+// Interrupt Enable for Transmitter Holding Register Empty interrupt 
+#define UART_IER_DLAB_0_0_IE_THR_SHIFT                  _MK_SHIFT_CONST(1)
+#define UART_IER_DLAB_0_0_IE_THR_FIELD                  (_MK_MASK_CONST(0x1) << UART_IER_DLAB_0_0_IE_THR_SHIFT)
+#define UART_IER_DLAB_0_0_IE_THR_RANGE                  1:1
+#define UART_IER_DLAB_0_0_IE_THR_WOFFSET                        0x0
+#define UART_IER_DLAB_0_0_IE_THR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_THR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_THR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_THR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_THR_DISABLE                        _MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_THR_ENABLE                 _MK_ENUM_CONST(1)
+
+// Interrupt Enable for Received Data Interrupt 
+#define UART_IER_DLAB_0_0_IE_RHR_SHIFT                  _MK_SHIFT_CONST(0)
+#define UART_IER_DLAB_0_0_IE_RHR_FIELD                  (_MK_MASK_CONST(0x1) << UART_IER_DLAB_0_0_IE_RHR_SHIFT)
+#define UART_IER_DLAB_0_0_IE_RHR_RANGE                  0:0
+#define UART_IER_DLAB_0_0_IE_RHR_WOFFSET                        0x0
+#define UART_IER_DLAB_0_0_IE_RHR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RHR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_RHR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RHR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RHR_DISABLE                        _MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_RHR_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register UART_IIR_FCR_0  
+#define UART_IIR_FCR_0                  _MK_ADDR_CONST(0x8)
+#define UART_IIR_FCR_0_WORD_COUNT                       0x1
+#define UART_IIR_FCR_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define UART_IIR_FCR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define UART_IIR_FCR_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// FIFO Mode Status  0=16450 mode(no FIFO), 1 = 16550 mode(FIFO)
+#define UART_IIR_FCR_0_EN_FIFO_SHIFT                    _MK_SHIFT_CONST(6)
+#define UART_IIR_FCR_0_EN_FIFO_FIELD                    (_MK_MASK_CONST(0x3) << UART_IIR_FCR_0_EN_FIFO_SHIFT)
+#define UART_IIR_FCR_0_EN_FIFO_RANGE                    7:6
+#define UART_IIR_FCR_0_EN_FIFO_WOFFSET                  0x0
+#define UART_IIR_FCR_0_EN_FIFO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_EN_FIFO_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define UART_IIR_FCR_0_EN_FIFO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_EN_FIFO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_EN_FIFO_MODE_16550                       _MK_ENUM_CONST(1)
+#define UART_IIR_FCR_0_EN_FIFO_MODE_16450                       _MK_ENUM_CONST(0)
+
+// Reserved
+#define UART_IIR_FCR_0_N_A_SHIFT                        _MK_SHIFT_CONST(4)
+#define UART_IIR_FCR_0_N_A_FIELD                        (_MK_MASK_CONST(0x3) << UART_IIR_FCR_0_N_A_SHIFT)
+#define UART_IIR_FCR_0_N_A_RANGE                        5:4
+#define UART_IIR_FCR_0_N_A_WOFFSET                      0x0
+#define UART_IIR_FCR_0_N_A_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_N_A_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define UART_IIR_FCR_0_N_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_N_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Encoded Interrupt ID   Refer to IIR[3:0] table above
+#define UART_IIR_FCR_0_IS_PRI2_SHIFT                    _MK_SHIFT_CONST(3)
+#define UART_IIR_FCR_0_IS_PRI2_FIELD                    (_MK_MASK_CONST(0x1) << UART_IIR_FCR_0_IS_PRI2_SHIFT)
+#define UART_IIR_FCR_0_IS_PRI2_RANGE                    3:3
+#define UART_IIR_FCR_0_IS_PRI2_WOFFSET                  0x0
+#define UART_IIR_FCR_0_IS_PRI2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_PRI2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI2_DISABLE                  _MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_IS_PRI2_ENABLE                   _MK_ENUM_CONST(1)
+
+// Encoded Interrupt ID   Refer to IIR[3:0] table above
+#define UART_IIR_FCR_0_IS_PRI1_SHIFT                    _MK_SHIFT_CONST(2)
+#define UART_IIR_FCR_0_IS_PRI1_FIELD                    (_MK_MASK_CONST(0x1) << UART_IIR_FCR_0_IS_PRI1_SHIFT)
+#define UART_IIR_FCR_0_IS_PRI1_RANGE                    2:2
+#define UART_IIR_FCR_0_IS_PRI1_WOFFSET                  0x0
+#define UART_IIR_FCR_0_IS_PRI1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_PRI1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI1_DISABLE                  _MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_IS_PRI1_ENABLE                   _MK_ENUM_CONST(1)
+
+// Encoded Interrupt ID   Refer to IIR[3:0] table above
+#define UART_IIR_FCR_0_IS_PRI0_SHIFT                    _MK_SHIFT_CONST(1)
+#define UART_IIR_FCR_0_IS_PRI0_FIELD                    (_MK_MASK_CONST(0x1) << UART_IIR_FCR_0_IS_PRI0_SHIFT)
+#define UART_IIR_FCR_0_IS_PRI0_RANGE                    1:1
+#define UART_IIR_FCR_0_IS_PRI0_WOFFSET                  0x0
+#define UART_IIR_FCR_0_IS_PRI0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_PRI0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI0_DISABLE                  _MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_IS_PRI0_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupt Pending if ZERO
+#define UART_IIR_FCR_0_IS_STA_SHIFT                     _MK_SHIFT_CONST(0)
+#define UART_IIR_FCR_0_IS_STA_FIELD                     (_MK_MASK_CONST(0x1) << UART_IIR_FCR_0_IS_STA_SHIFT)
+#define UART_IIR_FCR_0_IS_STA_RANGE                     0:0
+#define UART_IIR_FCR_0_IS_STA_WOFFSET                   0x0
+#define UART_IIR_FCR_0_IS_STA_DEFAULT                   _MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_STA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_STA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_STA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_STA_INTR_PEND                 _MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_IS_STA_NO_INTR_PEND                      _MK_ENUM_CONST(1)
+
+// 11 = FIFO full count >= 16 
+#define UART_IIR_FCR_0_RX_TRIG_SHIFT                    _MK_SHIFT_CONST(6)
+#define UART_IIR_FCR_0_RX_TRIG_FIELD                    (_MK_MASK_CONST(0x3) << UART_IIR_FCR_0_RX_TRIG_SHIFT)
+#define UART_IIR_FCR_0_RX_TRIG_RANGE                    7:6
+#define UART_IIR_FCR_0_RX_TRIG_WOFFSET                  0x0
+#define UART_IIR_FCR_0_RX_TRIG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_TRIG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define UART_IIR_FCR_0_RX_TRIG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_TRIG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_1                     _MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_4                     _MK_ENUM_CONST(1)
+#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_8                     _MK_ENUM_CONST(2)
+#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_12                    _MK_ENUM_CONST(3)
+
+// 11 = FIFO empty count >= 16 
+#define UART_IIR_FCR_0_TX_TRIG_SHIFT                    _MK_SHIFT_CONST(4)
+#define UART_IIR_FCR_0_TX_TRIG_FIELD                    (_MK_MASK_CONST(0x3) << UART_IIR_FCR_0_TX_TRIG_SHIFT)
+#define UART_IIR_FCR_0_TX_TRIG_RANGE                    5:4
+#define UART_IIR_FCR_0_TX_TRIG_WOFFSET                  0x0
+#define UART_IIR_FCR_0_TX_TRIG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_TRIG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define UART_IIR_FCR_0_TX_TRIG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_TRIG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_1                     _MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_4                     _MK_ENUM_CONST(1)
+#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_8                     _MK_ENUM_CONST(2)
+#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_12                    _MK_ENUM_CONST(3)
+
+// 0:DMA_Mode_0     1:DMA_MODE_1
+#define UART_IIR_FCR_0_DMA_SHIFT                        _MK_SHIFT_CONST(3)
+#define UART_IIR_FCR_0_DMA_FIELD                        (_MK_MASK_CONST(0x1) << UART_IIR_FCR_0_DMA_SHIFT)
+#define UART_IIR_FCR_0_DMA_RANGE                        3:3
+#define UART_IIR_FCR_0_DMA_WOFFSET                      0x0
+#define UART_IIR_FCR_0_DMA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_DMA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_DMA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_DMA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_DMA_NO_CHANGE                    _MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_DMA_CHANGE                       _MK_ENUM_CONST(1)
+
+// 1 = Clears the contents of the transmit FIFO and  resets its counter logic to 0 (the transmit shift register is not cleared or  altered). This bit returns to 0 after clearing the FIFOs.
+#define UART_IIR_FCR_0_TX_CLR_SHIFT                     _MK_SHIFT_CONST(2)
+#define UART_IIR_FCR_0_TX_CLR_FIELD                     (_MK_MASK_CONST(0x1) << UART_IIR_FCR_0_TX_CLR_SHIFT)
+#define UART_IIR_FCR_0_TX_CLR_RANGE                     2:2
+#define UART_IIR_FCR_0_TX_CLR_WOFFSET                   0x0
+#define UART_IIR_FCR_0_TX_CLR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_CLR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_TX_CLR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_CLR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_CLR_NO_CLEAR                  _MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_TX_CLR_CLEAR                     _MK_ENUM_CONST(1)
+
+// 1 = Clears the contents of the receive FIFO and  resets its counter logic to 0 (the receive shift register is not cleared or  altered). This bit returns to 0 after clearing the FIFOs.
+#define UART_IIR_FCR_0_RX_CLR_SHIFT                     _MK_SHIFT_CONST(1)
+#define UART_IIR_FCR_0_RX_CLR_FIELD                     (_MK_MASK_CONST(0x1) << UART_IIR_FCR_0_RX_CLR_SHIFT)
+#define UART_IIR_FCR_0_RX_CLR_RANGE                     1:1
+#define UART_IIR_FCR_0_RX_CLR_WOFFSET                   0x0
+#define UART_IIR_FCR_0_RX_CLR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_CLR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_RX_CLR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_CLR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_CLR_NO_CLEAR                  _MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_RX_CLR_CLEAR                     _MK_ENUM_CONST(1)
+
+// 1 = Enable the transmit and receive FIFO. This  bit should be enabled
+#define UART_IIR_FCR_0_FCR_EN_FIFO_SHIFT                        _MK_SHIFT_CONST(0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_FIELD                        (_MK_MASK_CONST(0x1) << UART_IIR_FCR_0_FCR_EN_FIFO_SHIFT)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_RANGE                        0:0
+#define UART_IIR_FCR_0_FCR_EN_FIFO_WOFFSET                      0x0
+#define UART_IIR_FCR_0_FCR_EN_FIFO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_DISABLE                      _MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register UART_LCR_0  
+#define UART_LCR_0                      _MK_ADDR_CONST(0xc)
+#define UART_LCR_0_WORD_COUNT                   0x1
+#define UART_LCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define UART_LCR_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define UART_LCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define UART_LCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_LCR_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define UART_LCR_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// Divisor Latch Access Bit (set to allow programming of the DLH,DLM Divisors)
+#define UART_LCR_0_DLAB_SHIFT                   _MK_SHIFT_CONST(7)
+#define UART_LCR_0_DLAB_FIELD                   (_MK_MASK_CONST(0x1) << UART_LCR_0_DLAB_SHIFT)
+#define UART_LCR_0_DLAB_RANGE                   7:7
+#define UART_LCR_0_DLAB_WOFFSET                 0x0
+#define UART_LCR_0_DLAB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_LCR_0_DLAB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_LCR_0_DLAB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_LCR_0_DLAB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_LCR_0_DLAB_DISABLE                 _MK_ENUM_CONST(0)
+#define UART_LCR_0_DLAB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Set BREAK condition -- Transmitter will send all zeroes to indicate BREAK
+#define UART_LCR_0_SET_B_SHIFT                  _MK_SHIFT_CONST(6)
+#define UART_LCR_0_SET_B_FIELD                  (_MK_MASK_CONST(0x1) << UART_LCR_0_SET_B_SHIFT)
+#define UART_LCR_0_SET_B_RANGE                  6:6
+#define UART_LCR_0_SET_B_WOFFSET                        0x0
+#define UART_LCR_0_SET_B_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_B_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define UART_LCR_0_SET_B_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_B_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_B_NO_BREAK                       _MK_ENUM_CONST(0)
+#define UART_LCR_0_SET_B_BREAK                  _MK_ENUM_CONST(1)
+
+// Set (force) parity to value in LCR [4]
+#define UART_LCR_0_SET_P_SHIFT                  _MK_SHIFT_CONST(5)
+#define UART_LCR_0_SET_P_FIELD                  (_MK_MASK_CONST(0x1) << UART_LCR_0_SET_P_SHIFT)
+#define UART_LCR_0_SET_P_RANGE                  5:5
+#define UART_LCR_0_SET_P_WOFFSET                        0x0
+#define UART_LCR_0_SET_P_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_P_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define UART_LCR_0_SET_P_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_P_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_P_NO_PARITY                      _MK_ENUM_CONST(0)
+#define UART_LCR_0_SET_P_PARITY                 _MK_ENUM_CONST(1)
+
+// Even parity format. There will always be an even  number of 1s in the binary representation (PAR = 1)
+#define UART_LCR_0_EVEN_SHIFT                   _MK_SHIFT_CONST(4)
+#define UART_LCR_0_EVEN_FIELD                   (_MK_MASK_CONST(0x1) << UART_LCR_0_EVEN_SHIFT)
+#define UART_LCR_0_EVEN_RANGE                   4:4
+#define UART_LCR_0_EVEN_WOFFSET                 0x0
+#define UART_LCR_0_EVEN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_LCR_0_EVEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_LCR_0_EVEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_LCR_0_EVEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_LCR_0_EVEN_DISABLE                 _MK_ENUM_CONST(0)
+#define UART_LCR_0_EVEN_ENABLE                  _MK_ENUM_CONST(1)
+
+// 0 = No parity sent
+#define UART_LCR_0_PAR_SHIFT                    _MK_SHIFT_CONST(3)
+#define UART_LCR_0_PAR_FIELD                    (_MK_MASK_CONST(0x1) << UART_LCR_0_PAR_SHIFT)
+#define UART_LCR_0_PAR_RANGE                    3:3
+#define UART_LCR_0_PAR_WOFFSET                  0x0
+#define UART_LCR_0_PAR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_LCR_0_PAR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_LCR_0_PAR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_LCR_0_PAR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_LCR_0_PAR_NO_PARITY                        _MK_ENUM_CONST(0)
+#define UART_LCR_0_PAR_PARITY                   _MK_ENUM_CONST(1)
+
+// 0 = Transmit 1 stop bit, 1 = Transmit 2 stop bits (receiver always checks for 1 stop bit)
+#define UART_LCR_0_STOP_SHIFT                   _MK_SHIFT_CONST(2)
+#define UART_LCR_0_STOP_FIELD                   (_MK_MASK_CONST(0x1) << UART_LCR_0_STOP_SHIFT)
+#define UART_LCR_0_STOP_RANGE                   2:2
+#define UART_LCR_0_STOP_WOFFSET                 0x0
+#define UART_LCR_0_STOP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_LCR_0_STOP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_LCR_0_STOP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_LCR_0_STOP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_LCR_0_STOP_DISABLE                 _MK_ENUM_CONST(0)
+#define UART_LCR_0_STOP_ENABLE                  _MK_ENUM_CONST(1)
+
+// 3=Word length of 8
+#define UART_LCR_0_WD_SIZE_SHIFT                        _MK_SHIFT_CONST(0)
+#define UART_LCR_0_WD_SIZE_FIELD                        (_MK_MASK_CONST(0x3) << UART_LCR_0_WD_SIZE_SHIFT)
+#define UART_LCR_0_WD_SIZE_RANGE                        1:0
+#define UART_LCR_0_WD_SIZE_WOFFSET                      0x0
+#define UART_LCR_0_WD_SIZE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_LCR_0_WD_SIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define UART_LCR_0_WD_SIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_LCR_0_WD_SIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_LCR_0_WD_SIZE_WORD_LENGTH_5                        _MK_ENUM_CONST(0)
+#define UART_LCR_0_WD_SIZE_WORD_LENGTH_6                        _MK_ENUM_CONST(1)
+#define UART_LCR_0_WD_SIZE_WORD_LENGTH_7                        _MK_ENUM_CONST(2)
+#define UART_LCR_0_WD_SIZE_WORD_LENGTH_8                        _MK_ENUM_CONST(3)
+
+
+// Register UART_MCR_0  
+#define UART_MCR_0                      _MK_ADDR_CONST(0x10)
+#define UART_MCR_0_WORD_COUNT                   0x1
+#define UART_MCR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define UART_MCR_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define UART_MCR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define UART_MCR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_MCR_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define UART_MCR_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// Reserved
+#define UART_MCR_0_N_A_SHIFT                    _MK_SHIFT_CONST(7)
+#define UART_MCR_0_N_A_FIELD                    (_MK_MASK_CONST(0x1) << UART_MCR_0_N_A_SHIFT)
+#define UART_MCR_0_N_A_RANGE                    7:7
+#define UART_MCR_0_N_A_WOFFSET                  0x0
+#define UART_MCR_0_N_A_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_MCR_0_N_A_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_MCR_0_N_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_MCR_0_N_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = Enable RTS Hardware Flow Control
+#define UART_MCR_0_RTS_EN_SHIFT                 _MK_SHIFT_CONST(6)
+#define UART_MCR_0_RTS_EN_FIELD                 (_MK_MASK_CONST(0x1) << UART_MCR_0_RTS_EN_SHIFT)
+#define UART_MCR_0_RTS_EN_RANGE                 6:6
+#define UART_MCR_0_RTS_EN_WOFFSET                       0x0
+#define UART_MCR_0_RTS_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define UART_MCR_0_RTS_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define UART_MCR_0_RTS_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// 1 = Enable CTS Hardware Flow Control
+#define UART_MCR_0_CTS_EN_SHIFT                 _MK_SHIFT_CONST(5)
+#define UART_MCR_0_CTS_EN_FIELD                 (_MK_MASK_CONST(0x1) << UART_MCR_0_CTS_EN_SHIFT)
+#define UART_MCR_0_CTS_EN_RANGE                 5:5
+#define UART_MCR_0_CTS_EN_WOFFSET                       0x0
+#define UART_MCR_0_CTS_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_MCR_0_CTS_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define UART_MCR_0_CTS_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define UART_MCR_0_CTS_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define UART_MCR_0_CTS_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define UART_MCR_0_CTS_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// 1 = enable internal loop back of Serial Out to In
+#define UART_MCR_0_LOOPBK_SHIFT                 _MK_SHIFT_CONST(4)
+#define UART_MCR_0_LOOPBK_FIELD                 (_MK_MASK_CONST(0x1) << UART_MCR_0_LOOPBK_SHIFT)
+#define UART_MCR_0_LOOPBK_RANGE                 4:4
+#define UART_MCR_0_LOOPBK_WOFFSET                       0x0
+#define UART_MCR_0_LOOPBK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_MCR_0_LOOPBK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define UART_MCR_0_LOOPBK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define UART_MCR_0_LOOPBK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define UART_MCR_0_LOOPBK_DISABLE                       _MK_ENUM_CONST(0)
+#define UART_MCR_0_LOOPBK_ENABLE                        _MK_ENUM_CONST(1)
+
+// nOUT2  (Not Used)
+#define UART_MCR_0_OUT2_SHIFT                   _MK_SHIFT_CONST(3)
+#define UART_MCR_0_OUT2_FIELD                   (_MK_MASK_CONST(0x1) << UART_MCR_0_OUT2_SHIFT)
+#define UART_MCR_0_OUT2_RANGE                   3:3
+#define UART_MCR_0_OUT2_WOFFSET                 0x0
+#define UART_MCR_0_OUT2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_MCR_0_OUT2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT2_DISABLE                 _MK_ENUM_CONST(0)
+#define UART_MCR_0_OUT2_ENABLE                  _MK_ENUM_CONST(1)
+
+// nOUT1  (Not Used)
+#define UART_MCR_0_OUT1_SHIFT                   _MK_SHIFT_CONST(2)
+#define UART_MCR_0_OUT1_FIELD                   (_MK_MASK_CONST(0x1) << UART_MCR_0_OUT1_SHIFT)
+#define UART_MCR_0_OUT1_RANGE                   2:2
+#define UART_MCR_0_OUT1_WOFFSET                 0x0
+#define UART_MCR_0_OUT1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_MCR_0_OUT1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT1_DISABLE                 _MK_ENUM_CONST(0)
+#define UART_MCR_0_OUT1_ENABLE                  _MK_ENUM_CONST(1)
+
+// 0 = Force RTS to high if RTS HW flow control not enabled
+#define UART_MCR_0_RTS_SHIFT                    _MK_SHIFT_CONST(1)
+#define UART_MCR_0_RTS_FIELD                    (_MK_MASK_CONST(0x1) << UART_MCR_0_RTS_SHIFT)
+#define UART_MCR_0_RTS_RANGE                    1:1
+#define UART_MCR_0_RTS_WOFFSET                  0x0
+#define UART_MCR_0_RTS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_MCR_0_RTS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_FORCE_RTS_HI                     _MK_ENUM_CONST(0)
+#define UART_MCR_0_RTS_FORCE_RTS_LOW                    _MK_ENUM_CONST(1)
+
+// 1 = Force DTR to high
+#define UART_MCR_0_DTR_SHIFT                    _MK_SHIFT_CONST(0)
+#define UART_MCR_0_DTR_FIELD                    (_MK_MASK_CONST(0x1) << UART_MCR_0_DTR_SHIFT)
+#define UART_MCR_0_DTR_RANGE                    0:0
+#define UART_MCR_0_DTR_WOFFSET                  0x0
+#define UART_MCR_0_DTR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_MCR_0_DTR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_MCR_0_DTR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_MCR_0_DTR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_MCR_0_DTR_FORCE_DTR_HI                     _MK_ENUM_CONST(0)
+#define UART_MCR_0_DTR_FORCE_DTR_LOW                    _MK_ENUM_CONST(1)
+
+
+// Register UART_LSR_0  
+#define UART_LSR_0                      _MK_ADDR_CONST(0x14)
+#define UART_LSR_0_WORD_COUNT                   0x1
+#define UART_LSR_0_RESET_VAL                    _MK_MASK_CONST(0x60)
+#define UART_LSR_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define UART_LSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define UART_LSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_LSR_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define UART_LSR_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// 1 = Receive FIFO Error
+#define UART_LSR_0_FIFOE_SHIFT                  _MK_SHIFT_CONST(7)
+#define UART_LSR_0_FIFOE_FIELD                  (_MK_MASK_CONST(0x1) << UART_LSR_0_FIFOE_SHIFT)
+#define UART_LSR_0_FIFOE_RANGE                  7:7
+#define UART_LSR_0_FIFOE_WOFFSET                        0x0
+#define UART_LSR_0_FIFOE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_LSR_0_FIFOE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define UART_LSR_0_FIFOE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define UART_LSR_0_FIFOE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define UART_LSR_0_FIFOE_NO_ERR                 _MK_ENUM_CONST(0)
+#define UART_LSR_0_FIFOE_ERR                    _MK_ENUM_CONST(1)
+
+// Transmit Shift Reg empty status
+#define UART_LSR_0_TMTY_SHIFT                   _MK_SHIFT_CONST(6)
+#define UART_LSR_0_TMTY_FIELD                   (_MK_MASK_CONST(0x1) << UART_LSR_0_TMTY_SHIFT)
+#define UART_LSR_0_TMTY_RANGE                   6:6
+#define UART_LSR_0_TMTY_WOFFSET                 0x0
+#define UART_LSR_0_TMTY_DEFAULT                 _MK_MASK_CONST(0x1)
+#define UART_LSR_0_TMTY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_LSR_0_TMTY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_LSR_0_TMTY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_LSR_0_TMTY_NO_EMPTY                        _MK_ENUM_CONST(0)
+#define UART_LSR_0_TMTY_EMPTY                   _MK_ENUM_CONST(1)
+
+// 1 = Transmit Holding Register is  Empty -- OK to write data
+#define UART_LSR_0_THRE_SHIFT                   _MK_SHIFT_CONST(5)
+#define UART_LSR_0_THRE_FIELD                   (_MK_MASK_CONST(0x1) << UART_LSR_0_THRE_SHIFT)
+#define UART_LSR_0_THRE_RANGE                   5:5
+#define UART_LSR_0_THRE_WOFFSET                 0x0
+#define UART_LSR_0_THRE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define UART_LSR_0_THRE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_LSR_0_THRE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_LSR_0_THRE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_LSR_0_THRE_FULL                    _MK_ENUM_CONST(0)
+#define UART_LSR_0_THRE_EMPTY                   _MK_ENUM_CONST(1)
+
+// 1 = BREAK condition detected on line
+#define UART_LSR_0_BRK_SHIFT                    _MK_SHIFT_CONST(4)
+#define UART_LSR_0_BRK_FIELD                    (_MK_MASK_CONST(0x1) << UART_LSR_0_BRK_SHIFT)
+#define UART_LSR_0_BRK_RANGE                    4:4
+#define UART_LSR_0_BRK_WOFFSET                  0x0
+#define UART_LSR_0_BRK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_LSR_0_BRK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_LSR_0_BRK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_LSR_0_BRK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_LSR_0_BRK_NO_BREAK                 _MK_ENUM_CONST(0)
+#define UART_LSR_0_BRK_BREAK                    _MK_ENUM_CONST(1)
+
+// 1 = Framing Errpr
+#define UART_LSR_0_FERR_SHIFT                   _MK_SHIFT_CONST(3)
+#define UART_LSR_0_FERR_FIELD                   (_MK_MASK_CONST(0x1) << UART_LSR_0_FERR_SHIFT)
+#define UART_LSR_0_FERR_RANGE                   3:3
+#define UART_LSR_0_FERR_WOFFSET                 0x0
+#define UART_LSR_0_FERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_LSR_0_FERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_LSR_0_FERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_LSR_0_FERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_LSR_0_FERR_NO_FRAME_ERR                    _MK_ENUM_CONST(0)
+#define UART_LSR_0_FERR_FRAME_ERR                       _MK_ENUM_CONST(1)
+
+// 1 = Parity Error
+#define UART_LSR_0_PERR_SHIFT                   _MK_SHIFT_CONST(2)
+#define UART_LSR_0_PERR_FIELD                   (_MK_MASK_CONST(0x1) << UART_LSR_0_PERR_SHIFT)
+#define UART_LSR_0_PERR_RANGE                   2:2
+#define UART_LSR_0_PERR_WOFFSET                 0x0
+#define UART_LSR_0_PERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_LSR_0_PERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_LSR_0_PERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_LSR_0_PERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_LSR_0_PERR_NO_PARITY_ERR                   _MK_ENUM_CONST(0)
+#define UART_LSR_0_PERR_PARITY_ERR                      _MK_ENUM_CONST(1)
+
+// 1 = Receiver Overrun Error
+#define UART_LSR_0_OVRF_SHIFT                   _MK_SHIFT_CONST(1)
+#define UART_LSR_0_OVRF_FIELD                   (_MK_MASK_CONST(0x1) << UART_LSR_0_OVRF_SHIFT)
+#define UART_LSR_0_OVRF_RANGE                   1:1
+#define UART_LSR_0_OVRF_WOFFSET                 0x0
+#define UART_LSR_0_OVRF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_LSR_0_OVRF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_LSR_0_OVRF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_LSR_0_OVRF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_LSR_0_OVRF_NO_OVERRUN_ERROR                        _MK_ENUM_CONST(0)
+#define UART_LSR_0_OVRF_OVERRUN_ERROR                   _MK_ENUM_CONST(1)
+
+// 1 = Receiver Data Ready (Data available to read)
+#define UART_LSR_0_RDR_SHIFT                    _MK_SHIFT_CONST(0)
+#define UART_LSR_0_RDR_FIELD                    (_MK_MASK_CONST(0x1) << UART_LSR_0_RDR_SHIFT)
+#define UART_LSR_0_RDR_RANGE                    0:0
+#define UART_LSR_0_RDR_WOFFSET                  0x0
+#define UART_LSR_0_RDR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_LSR_0_RDR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_LSR_0_RDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_LSR_0_RDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_LSR_0_RDR_NO_DATA_IN_FIFO                  _MK_ENUM_CONST(0)
+#define UART_LSR_0_RDR_DATA_IN_FIFO                     _MK_ENUM_CONST(1)
+
+
+// Register UART_MSR_0  
+#define UART_MSR_0                      _MK_ADDR_CONST(0x18)
+#define UART_MSR_0_WORD_COUNT                   0x1
+#define UART_MSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define UART_MSR_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define UART_MSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define UART_MSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_MSR_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define UART_MSR_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// State of Carrier detect pin
+#define UART_MSR_0_CD_SHIFT                     _MK_SHIFT_CONST(7)
+#define UART_MSR_0_CD_FIELD                     (_MK_MASK_CONST(0x1) << UART_MSR_0_CD_SHIFT)
+#define UART_MSR_0_CD_RANGE                     7:7
+#define UART_MSR_0_CD_WOFFSET                   0x0
+#define UART_MSR_0_CD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_MSR_0_CD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define UART_MSR_0_CD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_MSR_0_CD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define UART_MSR_0_CD_DISABLE                   _MK_ENUM_CONST(0)
+#define UART_MSR_0_CD_ENABLE                    _MK_ENUM_CONST(1)
+
+// State of Ring Indicator pin
+#define UART_MSR_0_RI_SHIFT                     _MK_SHIFT_CONST(6)
+#define UART_MSR_0_RI_FIELD                     (_MK_MASK_CONST(0x1) << UART_MSR_0_RI_SHIFT)
+#define UART_MSR_0_RI_RANGE                     6:6
+#define UART_MSR_0_RI_WOFFSET                   0x0
+#define UART_MSR_0_RI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_MSR_0_RI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define UART_MSR_0_RI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_MSR_0_RI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define UART_MSR_0_RI_DISABLE                   _MK_ENUM_CONST(0)
+#define UART_MSR_0_RI_ENABLE                    _MK_ENUM_CONST(1)
+
+// State of Data set ready pin
+#define UART_MSR_0_DSR_SHIFT                    _MK_SHIFT_CONST(5)
+#define UART_MSR_0_DSR_FIELD                    (_MK_MASK_CONST(0x1) << UART_MSR_0_DSR_SHIFT)
+#define UART_MSR_0_DSR_RANGE                    5:5
+#define UART_MSR_0_DSR_WOFFSET                  0x0
+#define UART_MSR_0_DSR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DSR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_MSR_0_DSR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DSR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DSR_DISABLE                  _MK_ENUM_CONST(0)
+#define UART_MSR_0_DSR_ENABLE                   _MK_ENUM_CONST(1)
+
+// State of Clear to send pin
+#define UART_MSR_0_CTS_SHIFT                    _MK_SHIFT_CONST(4)
+#define UART_MSR_0_CTS_FIELD                    (_MK_MASK_CONST(0x1) << UART_MSR_0_CTS_SHIFT)
+#define UART_MSR_0_CTS_RANGE                    4:4
+#define UART_MSR_0_CTS_WOFFSET                  0x0
+#define UART_MSR_0_CTS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_MSR_0_CTS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_MSR_0_CTS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_MSR_0_CTS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_MSR_0_CTS_DISABLE                  _MK_ENUM_CONST(0)
+#define UART_MSR_0_CTS_ENABLE                   _MK_ENUM_CONST(1)
+
+// Change (Delta) in CD state detected 
+#define UART_MSR_0_DCD_SHIFT                    _MK_SHIFT_CONST(3)
+#define UART_MSR_0_DCD_FIELD                    (_MK_MASK_CONST(0x1) << UART_MSR_0_DCD_SHIFT)
+#define UART_MSR_0_DCD_RANGE                    3:3
+#define UART_MSR_0_DCD_WOFFSET                  0x0
+#define UART_MSR_0_DCD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_MSR_0_DCD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCD_DISABLE                  _MK_ENUM_CONST(0)
+#define UART_MSR_0_DCD_ENABLE                   _MK_ENUM_CONST(1)
+
+// Change (Delta) in RI state detected
+#define UART_MSR_0_DRI_SHIFT                    _MK_SHIFT_CONST(2)
+#define UART_MSR_0_DRI_FIELD                    (_MK_MASK_CONST(0x1) << UART_MSR_0_DRI_SHIFT)
+#define UART_MSR_0_DRI_RANGE                    2:2
+#define UART_MSR_0_DRI_WOFFSET                  0x0
+#define UART_MSR_0_DRI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DRI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define UART_MSR_0_DRI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DRI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DRI_DISABLE                  _MK_ENUM_CONST(0)
+#define UART_MSR_0_DRI_ENABLE                   _MK_ENUM_CONST(1)
+
+// Change (Delta) in DSR state detected
+#define UART_MSR_0_DDSR_SHIFT                   _MK_SHIFT_CONST(1)
+#define UART_MSR_0_DDSR_FIELD                   (_MK_MASK_CONST(0x1) << UART_MSR_0_DDSR_SHIFT)
+#define UART_MSR_0_DDSR_RANGE                   1:1
+#define UART_MSR_0_DDSR_WOFFSET                 0x0
+#define UART_MSR_0_DDSR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DDSR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_MSR_0_DDSR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DDSR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DDSR_DISABLE                 _MK_ENUM_CONST(0)
+#define UART_MSR_0_DDSR_ENABLE                  _MK_ENUM_CONST(1)
+
+// Change (Delta) in CTS state detected
+#define UART_MSR_0_DCTS_SHIFT                   _MK_SHIFT_CONST(0)
+#define UART_MSR_0_DCTS_FIELD                   (_MK_MASK_CONST(0x1) << UART_MSR_0_DCTS_SHIFT)
+#define UART_MSR_0_DCTS_RANGE                   0:0
+#define UART_MSR_0_DCTS_WOFFSET                 0x0
+#define UART_MSR_0_DCTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCTS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_MSR_0_DCTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCTS_DISABLE                 _MK_ENUM_CONST(0)
+#define UART_MSR_0_DCTS_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Register UART_SPR_0  
+#define UART_SPR_0                      _MK_ADDR_CONST(0x1c)
+#define UART_SPR_0_WORD_COUNT                   0x1
+#define UART_SPR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define UART_SPR_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define UART_SPR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define UART_SPR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_SPR_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define UART_SPR_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+// Scratchpad register (not used internally) 
+#define UART_SPR_0_SPR_A_SHIFT                  _MK_SHIFT_CONST(0)
+#define UART_SPR_0_SPR_A_FIELD                  (_MK_MASK_CONST(0xff) << UART_SPR_0_SPR_A_SHIFT)
+#define UART_SPR_0_SPR_A_RANGE                  7:0
+#define UART_SPR_0_SPR_A_WOFFSET                        0x0
+#define UART_SPR_0_SPR_A_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_SPR_0_SPR_A_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define UART_SPR_0_SPR_A_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define UART_SPR_0_SPR_A_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register UART_IRDA_CSR_0  
+#define UART_IRDA_CSR_0                 _MK_ADDR_CONST(0x20)
+#define UART_IRDA_CSR_0_WORD_COUNT                      0x1
+#define UART_IRDA_CSR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define UART_IRDA_CSR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define UART_IRDA_CSR_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+//  1 = Enable SIR coder 0 = Disable  SIR coder
+#define UART_IRDA_CSR_0_SIR_A_SHIFT                     _MK_SHIFT_CONST(7)
+#define UART_IRDA_CSR_0_SIR_A_FIELD                     (_MK_MASK_CONST(0x1) << UART_IRDA_CSR_0_SIR_A_SHIFT)
+#define UART_IRDA_CSR_0_SIR_A_RANGE                     7:7
+#define UART_IRDA_CSR_0_SIR_A_WOFFSET                   0x0
+#define UART_IRDA_CSR_0_SIR_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_SIR_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_SIR_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_SIR_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_SIR_A_DISABLE                   _MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_SIR_A_ENABLE                    _MK_ENUM_CONST(1)
+
+// 0=3/16th Baud Pulse, 1=4/16
+#define UART_IRDA_CSR_0_PWT_A_SHIFT                     _MK_SHIFT_CONST(6)
+#define UART_IRDA_CSR_0_PWT_A_FIELD                     (_MK_MASK_CONST(0x1) << UART_IRDA_CSR_0_PWT_A_SHIFT)
+#define UART_IRDA_CSR_0_PWT_A_RANGE                     6:6
+#define UART_IRDA_CSR_0_PWT_A_WOFFSET                   0x0
+#define UART_IRDA_CSR_0_PWT_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_PWT_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_PWT_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_PWT_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_PWT_A_BAUD_PULSE_3_14                   _MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_PWT_A_BAUD_PULSE_4_14                   _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define UART_IRDA_CSR_0_N_A_SHIFT                       _MK_SHIFT_CONST(4)
+#define UART_IRDA_CSR_0_N_A_FIELD                       (_MK_MASK_CONST(0x3) << UART_IRDA_CSR_0_N_A_SHIFT)
+#define UART_IRDA_CSR_0_N_A_RANGE                       5:4
+#define UART_IRDA_CSR_0_N_A_WOFFSET                     0x0
+#define UART_IRDA_CSR_0_N_A_DEFAULT                     _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_N_A_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define UART_IRDA_CSR_0_N_A_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_N_A_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Inverts the normally inactive high nRTS pin
+#define UART_IRDA_CSR_0_INVERT_RTS_SHIFT                        _MK_SHIFT_CONST(3)
+#define UART_IRDA_CSR_0_INVERT_RTS_FIELD                        (_MK_MASK_CONST(0x1) << UART_IRDA_CSR_0_INVERT_RTS_SHIFT)
+#define UART_IRDA_CSR_0_INVERT_RTS_RANGE                        3:3
+#define UART_IRDA_CSR_0_INVERT_RTS_WOFFSET                      0x0
+#define UART_IRDA_CSR_0_INVERT_RTS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RTS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_RTS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RTS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RTS_DISABLE                      _MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_RTS_ENABLE                       _MK_ENUM_CONST(1)
+
+// Inverts the normally inactive high nCTS pin
+#define UART_IRDA_CSR_0_INVERT_CTS_SHIFT                        _MK_SHIFT_CONST(2)
+#define UART_IRDA_CSR_0_INVERT_CTS_FIELD                        (_MK_MASK_CONST(0x1) << UART_IRDA_CSR_0_INVERT_CTS_SHIFT)
+#define UART_IRDA_CSR_0_INVERT_CTS_RANGE                        2:2
+#define UART_IRDA_CSR_0_INVERT_CTS_WOFFSET                      0x0
+#define UART_IRDA_CSR_0_INVERT_CTS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_CTS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_CTS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_CTS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_CTS_DISABLE                      _MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_CTS_ENABLE                       _MK_ENUM_CONST(1)
+
+// Inverts the normally inactive high TXD pin
+#define UART_IRDA_CSR_0_INVERT_TXD_SHIFT                        _MK_SHIFT_CONST(1)
+#define UART_IRDA_CSR_0_INVERT_TXD_FIELD                        (_MK_MASK_CONST(0x1) << UART_IRDA_CSR_0_INVERT_TXD_SHIFT)
+#define UART_IRDA_CSR_0_INVERT_TXD_RANGE                        1:1
+#define UART_IRDA_CSR_0_INVERT_TXD_WOFFSET                      0x0
+#define UART_IRDA_CSR_0_INVERT_TXD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_TXD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_TXD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_TXD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_TXD_DISABLE                      _MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_TXD_ENABLE                       _MK_ENUM_CONST(1)
+
+// Inverts the normally inactive high RXD pin
+#define UART_IRDA_CSR_0_INVERT_RXD_SHIFT                        _MK_SHIFT_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_RXD_FIELD                        (_MK_MASK_CONST(0x1) << UART_IRDA_CSR_0_INVERT_RXD_SHIFT)
+#define UART_IRDA_CSR_0_INVERT_RXD_RANGE                        0:0
+#define UART_IRDA_CSR_0_INVERT_RXD_WOFFSET                      0x0
+#define UART_IRDA_CSR_0_INVERT_RXD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RXD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_RXD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RXD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RXD_DISABLE                      _MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_RXD_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Reserved address 36 [0x24] 
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Register UART_ASR_0  
+#define UART_ASR_0                      _MK_ADDR_CONST(0x3c)
+#define UART_ASR_0_WORD_COUNT                   0x1
+#define UART_ASR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define UART_ASR_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define UART_ASR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define UART_ASR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define UART_ASR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define UART_ASR_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// This bit is set when the controller finishes  counting the clocks between two successive clock edges after there is a write  to ASR with dont care data. 
+#define UART_ASR_0_VALID_SHIFT                  _MK_SHIFT_CONST(31)
+#define UART_ASR_0_VALID_FIELD                  (_MK_MASK_CONST(0x1) << UART_ASR_0_VALID_SHIFT)
+#define UART_ASR_0_VALID_RANGE                  31:31
+#define UART_ASR_0_VALID_WOFFSET                        0x0
+#define UART_ASR_0_VALID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define UART_ASR_0_VALID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define UART_ASR_0_VALID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define UART_ASR_0_VALID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define UART_ASR_0_VALID_UN_SET                 _MK_ENUM_CONST(0)
+#define UART_ASR_0_VALID_SET                    _MK_ENUM_CONST(1)
+
+// This bit is set when there is a write to ASR and  is reset when the controller finishes counting the clock edges between two  successive clock edges.
+#define UART_ASR_0_BUSY_SHIFT                   _MK_SHIFT_CONST(30)
+#define UART_ASR_0_BUSY_FIELD                   (_MK_MASK_CONST(0x1) << UART_ASR_0_BUSY_SHIFT)
+#define UART_ASR_0_BUSY_RANGE                   30:30
+#define UART_ASR_0_BUSY_WOFFSET                 0x0
+#define UART_ASR_0_BUSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define UART_ASR_0_BUSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define UART_ASR_0_BUSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_ASR_0_BUSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define UART_ASR_0_BUSY_NO_BUSY                 _MK_ENUM_CONST(0)
+#define UART_ASR_0_BUSY_BUSY                    _MK_ENUM_CONST(1)
+
+// Reserved = 0
+#define UART_ASR_0_N_A_SHIFT                    _MK_SHIFT_CONST(16)
+#define UART_ASR_0_N_A_FIELD                    (_MK_MASK_CONST(0x3fff) << UART_ASR_0_N_A_SHIFT)
+#define UART_ASR_0_N_A_RANGE                    29:16
+#define UART_ASR_0_N_A_WOFFSET                  0x0
+#define UART_ASR_0_N_A_DEFAULT                  _MK_MASK_CONST(0x0)
+#define UART_ASR_0_N_A_DEFAULT_MASK                     _MK_MASK_CONST(0x3fff)
+#define UART_ASR_0_N_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define UART_ASR_0_N_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Shows the bits [15:8] of the count of clock edges  between two successive clock edges.
+#define UART_ASR_0_RX_RATE_SENSE_H_SHIFT                        _MK_SHIFT_CONST(8)
+#define UART_ASR_0_RX_RATE_SENSE_H_FIELD                        (_MK_MASK_CONST(0xff) << UART_ASR_0_RX_RATE_SENSE_H_SHIFT)
+#define UART_ASR_0_RX_RATE_SENSE_H_RANGE                        15:8
+#define UART_ASR_0_RX_RATE_SENSE_H_WOFFSET                      0x0
+#define UART_ASR_0_RX_RATE_SENSE_H_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_H_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define UART_ASR_0_RX_RATE_SENSE_H_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_H_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Shows the bits[7:0] of the count of clock edges  between two successive clock edges.
+#define UART_ASR_0_RX_RATE_SENSE_L_SHIFT                        _MK_SHIFT_CONST(0)
+#define UART_ASR_0_RX_RATE_SENSE_L_FIELD                        (_MK_MASK_CONST(0xff) << UART_ASR_0_RX_RATE_SENSE_L_SHIFT)
+#define UART_ASR_0_RX_RATE_SENSE_L_RANGE                        7:0
+#define UART_ASR_0_RX_RATE_SENSE_L_WOFFSET                      0x0
+#define UART_ASR_0_RX_RATE_SENSE_L_DEFAULT                      _MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_L_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define UART_ASR_0_RX_RATE_SENSE_L_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_L_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARUART_REGS(_op_) \
+_op_(UART_THR_DLAB_0_0) \
+_op_(UART_IER_DLAB_0_0) \
+_op_(UART_IIR_FCR_0) \
+_op_(UART_LCR_0) \
+_op_(UART_MCR_0) \
+_op_(UART_LSR_0) \
+_op_(UART_MSR_0) \
+_op_(UART_SPR_0) \
+_op_(UART_IRDA_CSR_0) \
+_op_(UART_ASR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_UART       0x00000000
+
+//
+// ARUART REGISTER BANKS
+//
+
+#define UART0_FIRST_REG 0x0000 // UART_THR_DLAB_0_0
+#define UART0_LAST_REG 0x0020 // UART_IRDA_CSR_0
+#define UART1_FIRST_REG 0x003c // UART_ASR_0
+#define UART1_LAST_REG 0x003c // UART_ASR_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARUART_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arvde_mon.h b/arch/arm/mach-tegra/nv/include/ap15/arvde_mon.h
new file mode 100644
index 000000000000..0ab6185bee33
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arvde_mon.h
@@ -0,0 +1,268 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef ___ARVDE_MON_H_INC_
+#define ___ARVDE_MON_H_INC_
+//----------------------------------------------------------
+// PPB, IDLE, & debug-observability
+// --------------------------------------------------
+// PPB, IDLE, & debug-observability registers in VDE
+// --------------------------------------------------
+// This IDLE monitor is intended to count the number of cycles where
+// all of the NV_VDE_<submodule>'s are all idle. This information is
+// expected to be used by software to adjust the system clock and video
+// clock to optimal values.
+
+// Register ARVDE_PPB_IDLE_MON_0  
+#define ARVDE_PPB_IDLE_MON_0                    _MK_ADDR_CONST(0x2800)
+#define ARVDE_PPB_IDLE_MON_0_WORD_COUNT                         0x1
+#define ARVDE_PPB_IDLE_MON_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_RESET_MASK                         _MK_MASK_CONST(0xbfffffff)
+#define ARVDE_PPB_IDLE_MON_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_READ_MASK                  _MK_MASK_CONST(0xbfffffff)
+#define ARVDE_PPB_IDLE_MON_0_WRITE_MASK                         _MK_MASK_CONST(0xbfffffff)
+// read=1 means monitoring active. read=0 means monitoring inactive
+// write1 means start monitoring. write0 means stop monitoring.
+// monitor will also become inactive automatically if either
+// 1. sample period ends, or
+// 2. overflow is reached (in either indefinite sampling or sample-period mode).
+#define ARVDE_PPB_IDLE_MON_0_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define ARVDE_PPB_IDLE_MON_0_ENB_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_MON_0_ENB_SHIFT)
+#define ARVDE_PPB_IDLE_MON_0_ENB_RANGE                  31:31
+#define ARVDE_PPB_IDLE_MON_0_ENB_WOFFSET                        0x0
+#define ARVDE_PPB_IDLE_MON_0_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_MON_0_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// read=1 means monitoring transitioned to inactive automically
+// because of cause 1 or 2 above.
+// write1 means clear this interrupt bit. write0 is ignored
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_SHIFT                   _MK_SHIFT_CONST(29)
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_FIELD                   (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_MON_0_INT_STATUS_SHIFT)
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_RANGE                   29:29
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_WOFFSET                 0x0
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_INT_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 means indefinite/continous sampling
+// 0 means use SAMPLE_PERIOD for duration
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_SHIFT                  _MK_SHIFT_CONST(28)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_FIELD                  (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_SHIFT)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_RANGE                  28:28
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_WOFFSET                        0x0
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// sample period in clock cycles. implemented as n+1, so that
+// "0" means sample period is 1 clock cycle
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_SHIFT                        _MK_SHIFT_CONST(3)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_FIELD                        (_MK_MASK_CONST(0x1ffffff) << ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_SHIFT)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_RANGE                        27:3
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_WOFFSET                      0x0
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_DEFAULT_MASK                 _MK_MASK_CONST(0x1ffffff)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// power-of-2 encoding for # of required continously active IDLE cycles
+// before counting will start. 0 means don't use thresh, just count directly.
+// 1 means start counting after 1 continuous idle cycle  has  been observed. (if idle active for 10 clocks, count would be 9)
+// 2 means start counting after 2 continuous idle cycles have been observed. (if idle active for 10 clocks, count would be 8)
+// 3 means start counting after 4 continuous idle cycles have been observed. (if idle active for 10 clocks, count would be 6)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_SHIFT                       _MK_SHIFT_CONST(0)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_FIELD                       (_MK_MASK_CONST(0x7) << ARVDE_PPB_IDLE_MON_0_THRESH_SHIFT)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_RANGE                       2:0
+#define ARVDE_PPB_IDLE_MON_0_THRESH_WOFFSET                     0x0
+#define ARVDE_PPB_IDLE_MON_0_THRESH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_MON_0_THRESH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register ARVDE_PPB_IDLE_STATUS_0  
+#define ARVDE_PPB_IDLE_STATUS_0                 _MK_ADDR_CONST(0x2804)
+#define ARVDE_PPB_IDLE_STATUS_0_WORD_COUNT                      0x1
+#define ARVDE_PPB_IDLE_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_STATUS_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// # of cycles of idle observed. value of 0xFFFF.FFFF indicates overflow
+// condition. COUNT will not stay at 0xFFFF.FFFF once overflow has been
+// detected. Value is cleared to 0 whenever VDE_IDLE_MON.ENB field is
+// written to 1 (see above register)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_FIELD                     (_MK_MASK_CONST(0xffffffff) << ARVDE_PPB_IDLE_STATUS_0_COUNT_SHIFT)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_RANGE                     31:0
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_WOFFSET                   0x0
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_STATUS_0_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 10248 [0x2808] 
+
+// Reserved address 10252 [0x280c] 
+// This submodule IDLE monitor is intended measure the activity/idle status of a single selected VDE_<submodule>. 
+// Software can use these registers to measure the effectiveness of hardware controlled dynamic clock-enable
+// power-gating, or to profile submodule activity during a particular video stream or set of streams.
+
+// Register ARVDE_PPB_IDLE_SUBMOD_MON_0  
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0                     _MK_ADDR_CONST(0x2810)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_WORD_COUNT                  0x1
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// read=1 means monitoring active. read=0 means monitoring inactive
+// write1 means start monitoring. write0 means stop monitoring.
+// monitor will also become inactive automatically if either
+// 1. sample period ends, or
+// 2. overflow is reached in indefinite sampling mode.
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_RANGE                   31:31
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_WOFFSET                 0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// AND'd with INT_STATUS below for passing interrupt signal. 0=mask, 1=enable
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_SHIFT                       _MK_SHIFT_CONST(30)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_FIELD                       (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_RANGE                       30:30
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_WOFFSET                     0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// read=1 means monitoring transitioned to inactive automically
+// because of one of the two causes above.
+// write1 means clear this interrupt bit. write0 is ignored
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_SHIFT                    _MK_SHIFT_CONST(29)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_FIELD                    (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_RANGE                    29:29
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_WOFFSET                  0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_INT_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 means indefinite/continous sampling
+// 0 means use SAMPLE_PERIOD for duration
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_SHIFT                   _MK_SHIFT_CONST(28)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_FIELD                   (_MK_MASK_CONST(0x1) << ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_RANGE                   28:28
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_WOFFSET                 0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_MODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// sample period in clock cycles. implemented as n+1, so that
+// "0" means sample period is 1 clock cycle
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_SHIFT                 _MK_SHIFT_CONST(3)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_FIELD                 (_MK_MASK_CONST(0x1ffffff) << ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_RANGE                 27:3
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_WOFFSET                       0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_DEFAULT_MASK                  _MK_MASK_CONST(0x1ffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_SAMPLE_PERIOD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// power-of-2 encoding for # of required continously active IDLE cycles
+// before counting will start.
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_SHIFT                        _MK_SHIFT_CONST(0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_FIELD                        (_MK_MASK_CONST(0x7) << ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_RANGE                        2:0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_WOFFSET                      0x0
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_MON_0_THRESH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register ARVDE_PPB_IDLE_SUBMOD_STATUS_0  
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0                  _MK_ADDR_CONST(0x2814)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_WORD_COUNT                       0x1
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// # of cycles of idle observed. value of 0xFFFF.FFFF indicates overflow
+// condition. COUNT will not stay at 0xFFFF.FFFF once overflow has been
+// detected. Value is cleared to 0 whenever VDE_IDLE_MON.ENB field is
+// written to 1 (see above register)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_FIELD                      (_MK_MASK_CONST(0xffffffff) << ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_RANGE                      31:0
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_WOFFSET                    0x0
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_STATUS_0_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register ARVDE_PPB_IDLE_SUBMOD_SELECT_0  
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0                  _MK_ADDR_CONST(0x2818)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_WORD_COUNT                       0x1
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_RESET_MASK                       _MK_MASK_CONST(0x7)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_READ_MASK                        _MK_MASK_CONST(0x7)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// 0=SXE, 1=BSEV, 2=TFE, 3=MBE, 4=MCE, 5=PPE, others=RESERVED
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_SHIFT                     _MK_SHIFT_CONST(0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_FIELD                     (_MK_MASK_CONST(0x7) << ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_SHIFT)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_RANGE                     2:0
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_WOFFSET                   0x0
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define ARVDE_PPB_IDLE_SUBMOD_SELECT_0_MODULE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#endif // ifndef ___ARVDE_MON_H_INC_
+
diff --git a/arch/arm/mach-tegra/nv/include/ap15/arvi.h b/arch/arm/mach-tegra/nv/include/ap15/arvi.h
new file mode 100644
index 000000000000..bc9d9244844c
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/arvi.h
@@ -0,0 +1,13401 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARVI_H_INC_
+#define ___ARVI_H_INC_
+#define NV_VI_OUT_1_INCR_SYNCPT_NB_CONDS        5
+
+// Register VI_OUT_1_INCR_SYNCPT_0  
+#define VI_OUT_1_INCR_SYNCPT_0                  _MK_ADDR_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_WORD_COUNT                       0x1
+#define VI_OUT_1_INCR_SYNCPT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_OUT_1_INCR_SYNCPT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_OUT_1_INCR_SYNCPT_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Condition mapped from raise/wait
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SHIFT                 _MK_SHIFT_CONST(8)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_RANGE                 15:8
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_WOFFSET                       0x0
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_IMMEDIATE                     _MK_ENUM_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_OP_DONE                       _MK_ENUM_CONST(1)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_RD_DONE                       _MK_ENUM_CONST(2)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_REG_WR_SAFE                   _MK_ENUM_CONST(3)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_START_WRITE                   _MK_ENUM_CONST(4)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_5                        _MK_ENUM_CONST(5)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_6                        _MK_ENUM_CONST(6)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_7                        _MK_ENUM_CONST(7)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_8                        _MK_ENUM_CONST(8)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_9                        _MK_ENUM_CONST(9)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_10                       _MK_ENUM_CONST(10)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_11                       _MK_ENUM_CONST(11)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_12                       _MK_ENUM_CONST(12)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_13                       _MK_ENUM_CONST(13)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_14                       _MK_ENUM_CONST(14)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_15                       _MK_ENUM_CONST(15)
+
+// syncpt index value
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_RANGE                 7:0
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_WOFFSET                       0x0
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_1_INCR_SYNCPT_CNTRL_0  
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0                    _MK_ADDR_CONST(0x1)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_WORD_COUNT                         0x1
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_RESET_MASK                         _MK_MASK_CONST(0x101)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_READ_MASK                  _MK_MASK_CONST(0x101)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x101)
+// If NO_STALL is 1, then when fifos are full,
+// INCR_SYNCPT methods will be dropped and the
+// INCR_SYNCPT_ERROR[COND] bit will be set.
+// If NO_STALL is 0, then when fifos are full,
+// the client host interface will be stalled.
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_FIELD                   (_MK_MASK_CONST(0x1) << VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_RANGE                   8:8
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_WOFFSET                 0x0
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// If SOFT_RESET is set, then all internal state
+// of the client syncpt block will be reset.
+// To do soft reset, first set SOFT_RESET of
+// all host1x clients affected, then clear all
+// SOFT_RESETs.
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_FIELD                 (_MK_MASK_CONST(0x1) << VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_RANGE                 0:0
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_WOFFSET                       0x0
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_1_INCR_SYNCPT_ERROR_0  
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0                    _MK_ADDR_CONST(0x2)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_WORD_COUNT                         0x1
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// COND_STATUS[COND] is set if the fifo for COND overflows.
+// This bit is sticky and will remain set until cleared.
+// Cleared by writing 1.
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_FIELD                    (_MK_MASK_CONST(0xffffffff) << VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_RANGE                    31:0
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_WOFFSET                  0x0
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 3 [0x3] 
+
+// Reserved address 4 [0x4] 
+
+// Reserved address 5 [0x5] 
+
+// Reserved address 6 [0x6] 
+
+// Reserved address 7 [0x7] 
+#define NV_VI_OUT_2_INCR_SYNCPT_NB_CONDS        5
+
+// Register VI_OUT_2_INCR_SYNCPT_0  
+#define VI_OUT_2_INCR_SYNCPT_0                  _MK_ADDR_CONST(0x8)
+#define VI_OUT_2_INCR_SYNCPT_0_WORD_COUNT                       0x1
+#define VI_OUT_2_INCR_SYNCPT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_OUT_2_INCR_SYNCPT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_OUT_2_INCR_SYNCPT_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Condition mapped from raise/wait
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SHIFT                 _MK_SHIFT_CONST(8)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_RANGE                 15:8
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_WOFFSET                       0x0
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_IMMEDIATE                     _MK_ENUM_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_OP_DONE                       _MK_ENUM_CONST(1)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_RD_DONE                       _MK_ENUM_CONST(2)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_REG_WR_SAFE                   _MK_ENUM_CONST(3)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_START_WRITE                   _MK_ENUM_CONST(4)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_5                        _MK_ENUM_CONST(5)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_6                        _MK_ENUM_CONST(6)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_7                        _MK_ENUM_CONST(7)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_8                        _MK_ENUM_CONST(8)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_9                        _MK_ENUM_CONST(9)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_10                       _MK_ENUM_CONST(10)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_11                       _MK_ENUM_CONST(11)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_12                       _MK_ENUM_CONST(12)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_13                       _MK_ENUM_CONST(13)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_14                       _MK_ENUM_CONST(14)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_15                       _MK_ENUM_CONST(15)
+
+// syncpt index value
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_RANGE                 7:0
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_WOFFSET                       0x0
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_2_INCR_SYNCPT_CNTRL_0  
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0                    _MK_ADDR_CONST(0x9)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_WORD_COUNT                         0x1
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_RESET_MASK                         _MK_MASK_CONST(0x101)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_READ_MASK                  _MK_MASK_CONST(0x101)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x101)
+// If NO_STALL is 1, then when fifos are full,
+// INCR_SYNCPT methods will be dropped and the
+// INCR_SYNCPT_ERROR[COND] bit will be set.
+// If NO_STALL is 0, then when fifos are full,
+// the client host interface will be stalled.
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_FIELD                   (_MK_MASK_CONST(0x1) << VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_RANGE                   8:8
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_WOFFSET                 0x0
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// If SOFT_RESET is set, then all internal state
+// of the client syncpt block will be reset.
+// To do soft reset, first set SOFT_RESET of
+// all host1x clients affected, then clear all
+// SOFT_RESETs.
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_FIELD                 (_MK_MASK_CONST(0x1) << VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_RANGE                 0:0
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_WOFFSET                       0x0
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_2_INCR_SYNCPT_ERROR_0  
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0                    _MK_ADDR_CONST(0xa)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_WORD_COUNT                         0x1
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// COND_STATUS[COND] is set if the fifo for COND overflows.
+// This bit is sticky and will remain set until cleared.
+// Cleared by writing 1.
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_FIELD                    (_MK_MASK_CONST(0xffffffff) << VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_RANGE                    31:0
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_WOFFSET                  0x0
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 11 [0xb] 
+
+// Reserved address 12 [0xc] 
+
+// Reserved address 13 [0xd] 
+
+// Reserved address 14 [0xe] 
+
+// Reserved address 15 [0xf] 
+#define NV_VI_MISC_INCR_SYNCPT_NB_CONDS 9
+
+// Register VI_MISC_INCR_SYNCPT_0  
+#define VI_MISC_INCR_SYNCPT_0                   _MK_ADDR_CONST(0x10)
+#define VI_MISC_INCR_SYNCPT_0_WORD_COUNT                        0x1
+#define VI_MISC_INCR_SYNCPT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_MISC_INCR_SYNCPT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define VI_MISC_INCR_SYNCPT_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+// Condition mapped from raise/wait
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_FIELD                   (_MK_MASK_CONST(0xff) << VI_MISC_INCR_SYNCPT_0_MISC_COND_SHIFT)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_RANGE                   15:8
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_WOFFSET                 0x0
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_IMMEDIATE                       _MK_ENUM_CONST(0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_OP_DONE                 _MK_ENUM_CONST(1)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_RD_DONE                 _MK_ENUM_CONST(2)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_REG_WR_SAFE                     _MK_ENUM_CONST(3)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_VIP_VSYNC                  _MK_ENUM_CONST(4)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPA_FRAME_START                        _MK_ENUM_CONST(5)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPA_FRAME_END                  _MK_ENUM_CONST(6)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPB_FRAME_START                        _MK_ENUM_CONST(7)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPB_FRAME_END                  _MK_ENUM_CONST(8)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_9                  _MK_ENUM_CONST(9)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_10                 _MK_ENUM_CONST(10)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_11                 _MK_ENUM_CONST(11)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_12                 _MK_ENUM_CONST(12)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_13                 _MK_ENUM_CONST(13)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_14                 _MK_ENUM_CONST(14)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_15                 _MK_ENUM_CONST(15)
+
+// syncpt index value
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_FIELD                   (_MK_MASK_CONST(0xff) << VI_MISC_INCR_SYNCPT_0_MISC_INDX_SHIFT)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_RANGE                   7:0
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_WOFFSET                 0x0
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_MISC_INCR_SYNCPT_CNTRL_0  
+#define VI_MISC_INCR_SYNCPT_CNTRL_0                     _MK_ADDR_CONST(0x11)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_WORD_COUNT                  0x1
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_RESET_MASK                  _MK_MASK_CONST(0x101)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_READ_MASK                   _MK_MASK_CONST(0x101)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x101)
+// If NO_STALL is 1, then when fifos are full,
+// INCR_SYNCPT methods will be dropped and the
+// INCR_SYNCPT_ERROR[COND] bit will be set.
+// If NO_STALL is 0, then when fifos are full,
+// the client host interface will be stalled.
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_FIELD                     (_MK_MASK_CONST(0x1) << VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SHIFT)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_RANGE                     8:8
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_WOFFSET                   0x0
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// If SOFT_RESET is set, then all internal state
+// of the client syncpt block will be reset.
+// To do soft reset, first set SOFT_RESET of
+// all host1x clients affected, then clear all
+// SOFT_RESETs.
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_FIELD                   (_MK_MASK_CONST(0x1) << VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SHIFT)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_RANGE                   0:0
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_WOFFSET                 0x0
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_MISC_INCR_SYNCPT_ERROR_0  
+#define VI_MISC_INCR_SYNCPT_ERROR_0                     _MK_ADDR_CONST(0x12)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_WORD_COUNT                  0x1
+#define VI_MISC_INCR_SYNCPT_ERROR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// COND_STATUS[COND] is set if the fifo for COND overflows.
+// This bit is sticky and will remain set until cleared.
+// Cleared by writing 1.
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SHIFT)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_RANGE                      31:0
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_WOFFSET                    0x0
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 19 [0x13] 
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 21 [0x15] 
+
+// Reserved address 22 [0x16] 
+
+// Reserved address 23 [0x17] 
+
+// Register VI_CONT_SYNCPT_OUT_1_0  
+#define VI_CONT_SYNCPT_OUT_1_0                  _MK_ADDR_CONST(0x18)
+#define VI_CONT_SYNCPT_OUT_1_0_WORD_COUNT                       0x1
+#define VI_CONT_SYNCPT_OUT_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_RESET_MASK                       _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_OUT_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_OUT_1_0_WRITE_MASK                       _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SHIFT)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_RANGE                 7:0
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time OUT_1 condition is true and OUT_1_EN is set
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SHIFT)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_RANGE                   8:8
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_OUT_2_0  
+#define VI_CONT_SYNCPT_OUT_2_0                  _MK_ADDR_CONST(0x19)
+#define VI_CONT_SYNCPT_OUT_2_0_WORD_COUNT                       0x1
+#define VI_CONT_SYNCPT_OUT_2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_RESET_MASK                       _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_OUT_2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_OUT_2_0_WRITE_MASK                       _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SHIFT)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_RANGE                 7:0
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time OUT_2 condition is true and OUT_2_EN is set
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SHIFT)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_RANGE                   8:8
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_VIP_VSYNC_0  
+#define VI_CONT_SYNCPT_VIP_VSYNC_0                      _MK_ADDR_CONST(0x1a)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_WORD_COUNT                   0x1
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_RESET_MASK                   _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SHIFT)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_RANGE                 7:0
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time VSYNC condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SHIFT)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_RANGE                   8:8
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_VI2EPP_0  
+#define VI_CONT_SYNCPT_VI2EPP_0                 _MK_ADDR_CONST(0x1b)
+#define VI_CONT_SYNCPT_VI2EPP_0_WORD_COUNT                      0x1
+#define VI_CONT_SYNCPT_VI2EPP_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_RESET_MASK                      _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_VI2EPP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_READ_MASK                       _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_VI2EPP_0_WRITE_MASK                      _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_FIELD                       (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SHIFT)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_RANGE                       7:0
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_WOFFSET                     0x0
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// on host read bus every time VI2EPP condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SHIFT                 _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_FIELD                 (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SHIFT)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_RANGE                 8:8
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0  
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0                    _MK_ADDR_CONST(0x1c)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_WORD_COUNT                         0x1
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_RESET_MASK                         _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_FIELD                     (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_RANGE                     7:0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_WOFFSET                   0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPA_FRAME_START condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_FIELD                       (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_RANGE                       8:8
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_WOFFSET                     0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0  
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0                      _MK_ADDR_CONST(0x1d)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_WORD_COUNT                   0x1
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_RESET_MASK                   _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_RANGE                 7:0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPA_FRAME_END condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_RANGE                   8:8
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0  
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0                    _MK_ADDR_CONST(0x1e)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_WORD_COUNT                         0x1
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_RESET_MASK                         _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_FIELD                     (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_RANGE                     7:0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_WOFFSET                   0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPB_FRAME_START condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_FIELD                       (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_RANGE                       8:8
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_WOFFSET                     0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0  
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0                      _MK_ADDR_CONST(0x1f)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_WORD_COUNT                   0x1
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_RESET_MASK                   _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_RANGE                 7:0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPB_FRAME_END condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_RANGE                   8:8
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CTXSW_0  
+#define VI_CTXSW_0                      _MK_ADDR_CONST(0x20)
+#define VI_CTXSW_0_WORD_COUNT                   0x1
+#define VI_CTXSW_0_RESET_VAL                    _MK_MASK_CONST(0xf000f800)
+#define VI_CTXSW_0_RESET_MASK                   _MK_MASK_CONST(0xf3fffbff)
+#define VI_CTXSW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_READ_MASK                    _MK_MASK_CONST(0xf3fffbff)
+#define VI_CTXSW_0_WRITE_MASK                   _MK_MASK_CONST(0xfbff)
+// Current working class
+#define VI_CTXSW_0_CURR_CLASS_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_CTXSW_0_CURR_CLASS_FIELD                     (_MK_MASK_CONST(0x3ff) << VI_CTXSW_0_CURR_CLASS_SHIFT)
+#define VI_CTXSW_0_CURR_CLASS_RANGE                     9:0
+#define VI_CTXSW_0_CURR_CLASS_WOFFSET                   0x0
+#define VI_CTXSW_0_CURR_CLASS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_CURR_CLASS_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
+#define VI_CTXSW_0_CURR_CLASS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_CURR_CLASS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Automatically acknowledge any incoming context switch requests
+#define VI_CTXSW_0_AUTO_ACK_SHIFT                       _MK_SHIFT_CONST(11)
+#define VI_CTXSW_0_AUTO_ACK_FIELD                       (_MK_MASK_CONST(0x1) << VI_CTXSW_0_AUTO_ACK_SHIFT)
+#define VI_CTXSW_0_AUTO_ACK_RANGE                       11:11
+#define VI_CTXSW_0_AUTO_ACK_WOFFSET                     0x0
+#define VI_CTXSW_0_AUTO_ACK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define VI_CTXSW_0_AUTO_ACK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_CTXSW_0_AUTO_ACK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_AUTO_ACK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_AUTO_ACK_MANUAL                      _MK_ENUM_CONST(0)
+#define VI_CTXSW_0_AUTO_ACK_AUTOACK                     _MK_ENUM_CONST(1)
+
+// Current working channel, reset to 'invalid'
+#define VI_CTXSW_0_CURR_CHANNEL_SHIFT                   _MK_SHIFT_CONST(12)
+#define VI_CTXSW_0_CURR_CHANNEL_FIELD                   (_MK_MASK_CONST(0xf) << VI_CTXSW_0_CURR_CHANNEL_SHIFT)
+#define VI_CTXSW_0_CURR_CHANNEL_RANGE                   15:12
+#define VI_CTXSW_0_CURR_CHANNEL_WOFFSET                 0x0
+#define VI_CTXSW_0_CURR_CHANNEL_DEFAULT                 _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_CURR_CHANNEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_CURR_CHANNEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_CURR_CHANNEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Next requested class
+#define VI_CTXSW_0_NEXT_CLASS_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CTXSW_0_NEXT_CLASS_FIELD                     (_MK_MASK_CONST(0x3ff) << VI_CTXSW_0_NEXT_CLASS_SHIFT)
+#define VI_CTXSW_0_NEXT_CLASS_RANGE                     25:16
+#define VI_CTXSW_0_NEXT_CLASS_WOFFSET                   0x0
+#define VI_CTXSW_0_NEXT_CLASS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_NEXT_CLASS_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
+#define VI_CTXSW_0_NEXT_CLASS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_NEXT_CLASS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Next requested channel
+#define VI_CTXSW_0_NEXT_CHANNEL_SHIFT                   _MK_SHIFT_CONST(28)
+#define VI_CTXSW_0_NEXT_CHANNEL_FIELD                   (_MK_MASK_CONST(0xf) << VI_CTXSW_0_NEXT_CHANNEL_SHIFT)
+#define VI_CTXSW_0_NEXT_CHANNEL_RANGE                   31:28
+#define VI_CTXSW_0_NEXT_CHANNEL_WOFFSET                 0x0
+#define VI_CTXSW_0_NEXT_CHANNEL_DEFAULT                 _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_NEXT_CHANNEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_INTSTATUS_0  
+#define VI_INTSTATUS_0                  _MK_ADDR_CONST(0x21)
+#define VI_INTSTATUS_0_WORD_COUNT                       0x1
+#define VI_INTSTATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define VI_INTSTATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTSTATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// Context switch interrupt status (clear on write)
+#define VI_INTSTATUS_0_CTXSW_INT_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_INTSTATUS_0_CTXSW_INT_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTSTATUS_0_CTXSW_INT_SHIFT)
+#define VI_INTSTATUS_0_CTXSW_INT_RANGE                  0:0
+#define VI_INTSTATUS_0_CTXSW_INT_WOFFSET                        0x0
+#define VI_INTSTATUS_0_CTXSW_INT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_CTXSW_INT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTSTATUS_0_CTXSW_INT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_CTXSW_INT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_INPUT_CONTROL_0  // VI Input Control
+#define VI_VI_INPUT_CONTROL_0                   _MK_ADDR_CONST(0x22)
+#define VI_VI_INPUT_CONTROL_0_WORD_COUNT                        0x1
+#define VI_VI_INPUT_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x7f801fff)
+#define VI_VI_INPUT_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x7f801fff)
+#define VI_VI_INPUT_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x7f801fff)
+// Host Input Enable   0= DISABLED
+//   1= ENABLED
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_RANGE                   0:0
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VIP Input Enable   0= DISABLED
+//   1= ENABLED
+// This bit turn on clocks for VIP input logic. This
+//   bit has to be enabled before CAMERA_CONTROL's
+//   VIP_ENABLE bit for any VIP logic to start!
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_RANGE                    1:1
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// Input port data Format  (effective if input source is VI Port)
+//   0000= YUV422 or ITU-R BT.656
+//   0001= Reserved 1
+//   0010= Bayer Pattern, enables ISP
+//   0011= Reserved 2
+//   0100= Pattern A, written directly to memory
+//   0101= Pattern B, written directly to memory
+//   0110= Pattern C, written directly to memory
+//   0111= Pattern C, do not remove the 0xFF, 0x02
+//   1000= Pattern D, ISDB-T input
+//   1001= YUV420NP, written directly to memory as YUV420P
+//   1010= RGB565, written directly to EPP
+//   1011= RGB888, written directly to EPP
+//   1100= RGB444, written directly to EPP
+//   1101= CSI,    written directly to CSI
+//         For YUV420NP no cropping will be done.
+//         For RGB565,RGB888,RGB444 written to EPP
+//         all cropping will be done in the EPP.
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SHIFT                   _MK_SHIFT_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_FIELD                   (_MK_MASK_CONST(0xf) << VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RANGE                   5:2
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_YUV422                  _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RESERVED_1                      _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_BAYER                   _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RESERVED_2                      _MK_ENUM_CONST(3)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_A                       _MK_ENUM_CONST(4)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_B                       _MK_ENUM_CONST(5)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_C                       _MK_ENUM_CONST(6)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_C_RAW                   _MK_ENUM_CONST(7)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_D                       _MK_ENUM_CONST(8)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_YUV420                  _MK_ENUM_CONST(9)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RGB565                  _MK_ENUM_CONST(10)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RGB888                  _MK_ENUM_CONST(11)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RGB444                  _MK_ENUM_CONST(12)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_CSI                     _MK_ENUM_CONST(13)
+
+// Host data Format  (effective if input source is host)
+//   00= Non-planar YUV422
+//      (only Y-FIFO is used)
+//   01= Planar YUV420
+//      (Y-FIFO, U-FIFO, V-FIFO are used)
+//   10= Bayer 8-bit  - enables ISP
+//   11= Bayer 12-bit - enables ISP
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_FIELD                 (_MK_MASK_CONST(0x3) << VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_RANGE                 7:6
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_NONPLANAR                     _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_PLANAR                        _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_BAYER8                        _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_BAYER12                       _MK_ENUM_CONST(3)
+
+// YUV Input Format This is applicable when input source is
+// VI Port and format is YUV422/ITU-R BT.656
+// or when input source is host and host
+// format is non-planar YUV422.
+//  8 bits per component
+//   00= UYVY => Y1_V0_Y0_U0 MSB to LSB 32bit mapping
+//   01= VYUY => Y1_U0_Y0_V0
+//   10= YUYV => V0_Y1_U0_Y0
+//   11= YVYU => U0_Y1_V0_Y0
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_RANGE                    9:8
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_WOFFSET                  0x0
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_UYVY                     _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_VYUY                     _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_YUYV                     _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_YVYU                     _MK_ENUM_CONST(3)
+
+// Select a data source input to HOST (extension field).  (use when input source is host)
+//  000= Source is selected with HOST_FORMAT field (backward compatible)
+//  001= Bayer 10 bpp: 2 16-bit values packed into 32-bit, LSbit aligned {6'b0, bayer, 6'b0, bayer} (to ISP)
+//  010= Bayer 14 bpp: 2 16-bit values packed into 32-bit, LSbit aligned {2'b0, bayer, 2'b0, bayer} (to ISP)
+//  011= RGB565             (to EPP)
+//  100= MSB Alpha + RGB888 (to EPP)
+//  101= MSB Alpha + BGR888 (to EPP)
+//  110= CSI                (to CSI)
+//  111= reserved
+// 22:13 reserved
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SHIFT                     _MK_SHIFT_CONST(10)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_FIELD                     (_MK_MASK_CONST(0x7) << VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_RANGE                     12:10
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_WOFFSET                   0x0
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_USE_HOST_FORMAT                   _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_BAYER10                   _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_BAYER14                   _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_RGB565                    _MK_ENUM_CONST(3)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_ARGB8888                  _MK_ENUM_CONST(4)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_ABGR8888                  _MK_ENUM_CONST(5)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_CSI                       _MK_ENUM_CONST(6)
+
+// VHS input signal active edge which is used  as horizontal reference of input data.
+//  VHS input inversion is evaluated first
+//  before determining active edge.
+//   0= Rising edge of VHS is active edge.
+//      For ITU-R BT.656 data, leading edge of
+//      horizontal sync is the active edge.
+//   1= Falling edge of VHS is active edge
+//      For ITU-R BT.656 data, trailing edge
+//      of horizontal sync is the active edge.
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SHIFT                 _MK_SHIFT_CONST(23)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_FIELD                 (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_RANGE                 23:23
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_RISING                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_FALLING                       _MK_ENUM_CONST(1)
+
+// VVS input signal active edge which is used  as vertical reference of input data
+//  VVS input inversion is evaluated first
+//  before determining active edge.
+//   0= Rising edge of VVS is active edge
+//      For ITU-R BT.656 data, leading edge of
+//      vertical sync is the active edge.
+//   1= Falling edge of VVS is active edge
+//      For ITU-R BT.656 data, trailing edge
+//      of vertical sync is the active edge.
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SHIFT                 _MK_SHIFT_CONST(24)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_FIELD                 (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_RANGE                 24:24
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_RISING                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_FALLING                       _MK_ENUM_CONST(1)
+
+// Horizontal and Vertical Sync Format  (effective if VIDEO_SOURCE is VIP)
+//   00= horizontal sync comes from VHS pin
+//       and vertical sync comes from VVS pin
+//       consistent with standard YUV422 data
+//       format.
+//       In this case, VHS_Input_Control and
+//       VVS_Input_Control must be enabled.
+//   01= horizontal and vertical syncs are
+//       decoded from the received video data
+//       bytes as specified in ITU-R BT.656
+//       (CCIR656) standard.
+//   10= horizontal and vertical syncs are
+//       generated internally and they are
+//       output on VHS and VVS pins if VHS and
+//       VVS are in output mode.
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SHIFT                 _MK_SHIFT_CONST(25)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_FIELD                 (_MK_MASK_CONST(0x3) << VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_RANGE                 26:25
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_YUV422                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_ITU656                        _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_INTHVS                        _MK_ENUM_CONST(2)
+
+// Interlaced video Field Detection  (effective if VIDEO_SOURCE is VIP)
+//   0= Disabled (top field only)
+//   1= Enabled
+//      When H/V syncs are decoded per ITU-R
+//      BT.656 standard, odd/even field is
+//      detected from the control bytes.
+//      When H/V syncs come from VHS/VVS pins
+//      (YUV422), odd/even field is detected
+//      from the position of VVS active edge
+//      with respect to VHS active pulse.
+//      This bit should be disabled for non-
+//      interlaced source or when H/V syncs
+//      are generated internally.
+//  If VIDEO_SOURCE is HOST, field information
+//  is always specified by host.
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SHIFT                        _MK_SHIFT_CONST(27)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_RANGE                        27:27
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_WOFFSET                      0x0
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_ENABLED                      _MK_ENUM_CONST(1)
+
+// Odd/Even Field type  (effective for interlaced video source)
+//   0= Top field is odd field
+//   1= Top field is even field
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SHIFT                  _MK_SHIFT_CONST(28)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_RANGE                  28:28
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_WOFFSET                        0x0
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_TOPODD                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_TOPEVEN                        _MK_ENUM_CONST(1)
+
+// Horizontal Counter   0= Enabled
+//   1= Disabled (reset to 0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_SHIFT                   _MK_SHIFT_CONST(29)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_H_COUNTER_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_RANGE                   29:29
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_ENABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_DISABLED                        _MK_ENUM_CONST(1)
+
+// Vertical Counter   0= Enabled
+//   1= Disabled (reset to 0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_SHIFT                   _MK_SHIFT_CONST(30)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_V_COUNTER_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_RANGE                   30:30
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_ENABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_DISABLED                        _MK_ENUM_CONST(1)
+
+
+// Register VI_VI_CORE_CONTROL_0  // VI Core Control and Output to EPP/ISP
+#define VI_VI_CORE_CONTROL_0                    _MK_ADDR_CONST(0x23)
+#define VI_VI_CORE_CONTROL_0_WORD_COUNT                         0x1
+#define VI_VI_CORE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x7ff0f7f)
+#define VI_VI_CORE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x7ef0f7f)
+#define VI_VI_CORE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x7ff0f7f)
+// Output to ISP  Enable data output to ISP
+//   00= Output to ISP is disabled
+//   01= Parallel Video Input Port data
+//   10= Host I/F data
+//   11= reserved
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_FIELD                        (_MK_MASK_CONST(0x3) << VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SHIFT)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_RANGE                        1:0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_VIP                  _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_HOST                 _MK_ENUM_CONST(2)
+
+// Output to EPP enable  VI can output a YUV pixel stream to
+//  Encoder Pre-Processor (EPP) module
+//   000= Output to EPP is disabled
+//   001= YUV444 stream after down-scaling
+//   010= YUV444 stream before down-scaling
+//        WARNING: FOR YUV444PRE, only the selects
+//        in INPUT_TO_CORE are supported.  Selects from
+//        INPUT_TO_CORE_EXT are not supported since they
+//        are duplicated in the CSI* selections of this field.
+//   011= YUV444 stream from ISP, no LPF or down-scaling
+//   100= RGB565,RGB444,RGB888 from VIP, no LPF or down-scaling
+//   101= RGB565,RGB888 from Host
+//   110= CSI_PPA
+//   111= CSI_PPB
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SHIFT                        _MK_SHIFT_CONST(2)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_FIELD                        (_MK_MASK_CONST(0x7) << VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SHIFT)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_RANGE                        4:2
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_YUV444POST                   _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_YUV444PRE                    _MK_ENUM_CONST(2)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_YUV444ISP                    _MK_ENUM_CONST(3)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_RGB                  _MK_ENUM_CONST(4)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_HOST_RGB                     _MK_ENUM_CONST(5)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_CSI_PPA                      _MK_ENUM_CONST(6)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_CSI_PPB                      _MK_ENUM_CONST(7)
+
+// Downsample from YUV444 to YUV422   00 = Cosited, take even UV's for each two Y's.
+//   01 = Cosited, take odd UV's for each two Y's. (Not implemented)
+//   10 = Non Cosited, take even U and odd V, use for Bayer passthru
+//   11 = Averaged, average the odd and even UVs. (Not Implemented)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SHIFT                       _MK_SHIFT_CONST(5)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_FIELD                       (_MK_MASK_CONST(0x3) << VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SHIFT)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_RANGE                       6:5
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_WOFFSET                     0x0
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_COSITED_EVEN                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_COSITED_ODD                 _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_NONCOSITED                  _MK_ENUM_CONST(2)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_AVERAGED                    _MK_ENUM_CONST(3)
+
+// Input to VI Core  Select between possible data input sources
+//   00= Parallel Video Input Port data
+//   01= Host I/F data
+//   10= ISP data, from 444 to 422 converter
+//   11= reserved
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_FIELD                        (_MK_MASK_CONST(0x3) << VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SHIFT)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_RANGE                        9:8
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_VIP                  _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_HOST                 _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_ISP                  _MK_ENUM_CONST(2)
+
+// Planar Conversion Module Input select   0= YUV422 after down-scaling, POST core
+//   1= YUV422 before down-scaling, PRE core
+//
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SHIFT                        _MK_SHIFT_CONST(10)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SHIFT)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_RANGE                        10:10
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_YUV422POST                   _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_YUV422PRE                    _MK_ENUM_CONST(1)
+
+// Color Space Conversion Input select   0= YUV422 after down-scaling, POST core
+//   1= YUV422 before down-scaling, PRE core
+// 15:12 reserved
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SHIFT                        _MK_SHIFT_CONST(11)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SHIFT)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_RANGE                        11:11
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_YUV422POST                   _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_YUV422PRE                    _MK_ENUM_CONST(1)
+
+// Horizontal Averaging   0= disabled, H_DOWNSCALING can be used
+//      to enable horizontal downscaling
+//   1= enabled, H_DOWNSCALING is ignored
+//      and horizontal downscaling is
+//      controlled by H_AVG_FACTOR
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_H_AVERAGING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_RANGE                  16:16
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_WOFFSET                        0x0
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_ENABLED                        _MK_ENUM_CONST(1)
+
+// Horizontal Down-scaling  (effective if H_AVERAGING is DISABLED)
+//   0= disabled
+//   1= enabled and controlled by H_DOWN_M
+//      and H_DOWN_N parameters
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SHIFT                        _MK_SHIFT_CONST(17)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_RANGE                        17:17
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_ENABLED                      _MK_ENUM_CONST(1)
+
+// Vertical Averaging   0= disabled, V_DOWNSCALING can be used
+//      to enable vertical downscaling
+//   1= enabled, V_DOWNSCALING is ignored
+//      and vertical downscaling is
+//      controlled by V_AVG_FACTOR
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_SHIFT                  _MK_SHIFT_CONST(18)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_V_AVERAGING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_RANGE                  18:18
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_WOFFSET                        0x0
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_ENABLED                        _MK_ENUM_CONST(1)
+
+// Vertical Down-scaling  (effective if V_AVERAGING is DISABLED)
+//   0= disabled
+//   1= enabled and controlled by V_DOWN_M
+//      and V_DOWN_N parameters
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SHIFT                        _MK_SHIFT_CONST(19)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_RANGE                        19:19
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_ENABLED                      _MK_ENUM_CONST(1)
+
+// ISP Host data stall capability is enabled by default  Use this bit to disable the host data stall capability
+//   0= disabled - default allows for VI to turn off
+//                 the ISP clock to stall the Host.
+//   1= enabled - to turn off the VI's ability to stall the Host
+//                when data from ISP comes from Host.
+//
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SHIFT                   _MK_SHIFT_CONST(20)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SHIFT)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_RANGE                   20:20
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_WOFFSET                 0x0
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_ENABLED                 _MK_ENUM_CONST(1)
+
+// Select a data source output to ISP (extension field).
+//   000= Source is selected with OUTPUT_TO_ISP field (backward compatible)
+//   001= CSI Pixel Parser A
+//   010= CSI Pixel Parser B
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SHIFT                    _MK_SHIFT_CONST(21)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_FIELD                    (_MK_MASK_CONST(0x7) << VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SHIFT)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_RANGE                    23:21
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_WOFFSET                  0x0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_USE_OUTPUT_TO_ISP                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_CSI_PPA                  _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_CSI_PPB                  _MK_ENUM_CONST(2)
+
+// Select a data source input to core (extension field).
+//   000= Source is selected with INPUT_TO_CORE field (backward compatible)
+//   001= CSI_PPA data in YUV444NP format
+//   010= CSI_PPA data in YUV422NP format
+//   011= CSI_PPB data in YUV444NP format
+//   100= CSI_PPB data in YUV422NP format
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SHIFT                    _MK_SHIFT_CONST(24)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_FIELD                    (_MK_MASK_CONST(0x7) << VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SHIFT)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_RANGE                    26:24
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_WOFFSET                  0x0
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_USE_INPUT_TO_CORE                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPA_YUV444                   _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPA_YUV422                   _MK_ENUM_CONST(2)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPB_YUV444                   _MK_ENUM_CONST(3)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPB_YUV422                   _MK_ENUM_CONST(4)
+
+
+// Register VI_VI_FIRST_OUTPUT_CONTROL_0  // VI Output Control of YUV/RGB and YUV420P
+#define VI_VI_FIRST_OUTPUT_CONTROL_0                    _MK_ADDR_CONST(0x24)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_WORD_COUNT                         0x1
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x3f0107)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x3f0107)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x3f0107)
+// Output data Format  Take from the CSC Unit:
+//   000= 16-bit RGB (B5G6R5)
+//   001= 16-bit RGB (B5G6R5) Dithered
+//        (This is currently NOT implemented)
+//   010= 24-bit RGB (B8G8R8)
+//  Take from the YUV422 Core output path:
+//      (Same thing as using YUV422PRE and YUV_SOURCE==CORE_OUTPUT)
+//   011= YUV422 non-planar (U8Y8V8Y8) after down-scaling, POST
+//  Take from the YUV422 paths: (see YUV_SOURCE field)
+//   100= YUV422 non-planar (U8Y8V8Y8) before down-scaling, PRE
+//   101= YUV422 Planar
+//   110= YUV420 Planar
+//   111= YUV420 Planar with Averaging
+//        (UV is averaged for each line pair)
+// 7:3 reserved
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_FIELD                        (_MK_MASK_CONST(0x7) << VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RANGE                        2:0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_WOFFSET                      0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RGB16                        _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RGB16D                       _MK_ENUM_CONST(1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RGB24                        _MK_ENUM_CONST(2)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV422POST                   _MK_ENUM_CONST(3)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV422PRE                    _MK_ENUM_CONST(4)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV422P                      _MK_ENUM_CONST(5)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV420P                      _MK_ENUM_CONST(6)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV420PA                     _MK_ENUM_CONST(7)
+
+// For Planar Output Only, enabling this register  duplicates the last pixel of each line when
+//  the output width is set to an odd number of pixels.
+//  Used when JPEGE/MPEGE which requires valid data filled
+//  to the word(16-bit) boundary.
+//  The Buffer Horizontal Size (Line Stride) must be
+//  set to accomodate the extra pixel.
+//  Example: Disabled - y0,y1,y2,y3,y4
+//           Enabled - y0,y1,y2,y3,y4,y4
+// 15:9 reserved
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_RANGE                       8:8
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_WOFFSET                     0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_ENABLED                     _MK_ENUM_CONST(1)
+
+// Output Byte Swap  (effective if input source is host)
+//   0= disabled
+//   1= enabled
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_RANGE                     16:16
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_WOFFSET                   0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_ENABLED                   _MK_ENUM_CONST(1)
+
+// YUV Output Format This is applicable when output format is
+// non-planar YUV422.
+//   00= UYVY => Y1_V0_Y1_U0 MSB to LSB 32bit mapping
+//   01= VYUY => Y1_U0_Y1_V0
+//   10= YUYV => V0_Y1_U0_Y0
+//   11= YVYU => U0_Y1_V0_Y0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SHIFT                    _MK_SHIFT_CONST(17)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_RANGE                    18:17
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_WOFFSET                  0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_UYVY                     _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_VYUY                     _MK_ENUM_CONST(1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_YUYV                     _MK_ENUM_CONST(2)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_YVYU                     _MK_ENUM_CONST(3)
+
+//  H-direction in internal memory
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SHIFT                  _MK_SHIFT_CONST(19)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_RANGE                  19:19
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_WOFFSET                        0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  V-direction in internal memory
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SHIFT                  _MK_SHIFT_CONST(20)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_RANGE                  20:20
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_WOFFSET                        0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  XY-Swap in internal memory
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SHIFT                      _MK_SHIFT_CONST(21)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_RANGE                      21:21
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_WOFFSET                    0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_SECOND_OUTPUT_CONTROL_0  // VI Second Output Control of YUV422NP and RGB
+#define VI_VI_SECOND_OUTPUT_CONTROL_0                   _MK_ADDR_CONST(0x25)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_WORD_COUNT                        0x1
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x3f000f)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x3f000f)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x3f000f)
+// Secondary Output to MC  Use case: when VI needs to send decimated preview data
+//  and at the same time send non-decimated data
+//  to the memory for StretchBLT, meanwhile the StretchBLT
+//  is sending EPP stretched data to be encoded.
+//  Only YUV422, RGB888, RGB565 is supported
+//
+//  Take from the CSC Unit
+//  0000= 16-bit RGB (B5G6R5), all RGB data can be pre or
+//        post decimated depending on mux select programming
+//        on the input to the Color Space Converter
+//  0001= 16-bit RGB (B5G6R5) Dithered
+//        (This is currently NOT implemented)
+//  0010= 24-bit RGB (B8G8R8)
+//  Take from the YUV422 Core output path:
+//      (Same thing as using YUV422PRE and YUV_SOURCE==CORE_OUTPUT)
+//  0011= YUV422 stream after down-scaling, POST
+//  Take from the YUV422 paths: (see YUV_SOURCE field)
+//  0100= YUV422 stream before down-scaling, PRE
+//  Take from the WriteBuffer interface logic, which is used for JPEG Stream
+//  0101= JPEG Stream (Pattern A,B,C)
+//  0110= VIP Bayer     direct to memory as a 16-bit value {6'b0, VIP_pad[9:0]}
+//  0111= CSI_PPA Bayer direct to memory as a 16-bit value {6'b0, CSI_SVD[15:6]}
+//  1000= CSI_PPB Bayer direct to memory as a 16-bit value {6'b0, CSI_SVD[15:6]}
+// 15:4 reserved
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_FIELD                        (_MK_MASK_CONST(0xf) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RANGE                        3:0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_WOFFSET                      0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RGB16                        _MK_ENUM_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RGB16D                       _MK_ENUM_CONST(1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RGB24                        _MK_ENUM_CONST(2)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_YUV422POST                   _MK_ENUM_CONST(3)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_YUV422PRE                    _MK_ENUM_CONST(4)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_JPEG_STREAM                  _MK_ENUM_CONST(5)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_VIP_BAYER                    _MK_ENUM_CONST(6)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_CSI_PPA_BAYER                        _MK_ENUM_CONST(7)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_CSI_PPB_BAYER                        _MK_ENUM_CONST(8)
+
+// Output Byte Swap  (effective if input source is host)
+//   0= disabled
+//   1= enabled
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_RANGE                     16:16
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_WOFFSET                   0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_ENABLED                   _MK_ENUM_CONST(1)
+
+// YUV Second Output Format This is applicable when output format is
+// non-planar YUV422.
+//   00= UYVY => Y1_V0_Y1_U0 MSB to LSB 32bit mapping
+//   01= VYUY => Y1_U0_Y1_V0
+//   10= YUYV => V0_Y1_U0_Y0
+//   11= YVYU => U0_Y1_V0_Y0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SHIFT                    _MK_SHIFT_CONST(17)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_RANGE                    18:17
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_WOFFSET                  0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_UYVY                     _MK_ENUM_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_VYUY                     _MK_ENUM_CONST(1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_YUYV                     _MK_ENUM_CONST(2)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_YVYU                     _MK_ENUM_CONST(3)
+
+//  Second output's H-direction in internal memory
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SHIFT                  _MK_SHIFT_CONST(19)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_RANGE                  19:19
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_WOFFSET                        0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Second output's V-direction in internal memory
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SHIFT                  _MK_SHIFT_CONST(20)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_RANGE                  20:20
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_WOFFSET                        0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Second output's XY-Swap in internal memory
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SHIFT                      _MK_SHIFT_CONST(21)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_RANGE                      21:21
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_WOFFSET                    0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_INPUT_FRAME_SIZE_0  // Host Input Frame Width
+#define VI_HOST_INPUT_FRAME_SIZE_0                      _MK_ADDR_CONST(0x26)
+#define VI_HOST_INPUT_FRAME_SIZE_0_WORD_COUNT                   0x1
+#define VI_HOST_INPUT_FRAME_SIZE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_HOST_INPUT_FRAME_SIZE_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Specifies in terms of pixels the width of
+// the input data coming from host.
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SHIFT)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_RANGE                      12:0
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_WOFFSET                    0x0
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Host Input Frame Height
+// Specifies in terms of lines the height of
+// the input data coming from host.
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SHIFT)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_RANGE                     28:16
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_WOFFSET                   0x0
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_H_ACTIVE_0  // VI Horizontal Active
+#define VI_HOST_H_ACTIVE_0                      _MK_ADDR_CONST(0x27)
+#define VI_HOST_H_ACTIVE_0_WORD_COUNT                   0x1
+#define VI_HOST_H_ACTIVE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_HOST_H_ACTIVE_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  pixels to be discarded until the first
+//  active pixel. If programmed to 0, the
+//  first active pixel is the first pixel popped
+//  from the Host YUV FIFO.
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_FIELD                    (_MK_MASK_CONST(0x1fff) << VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SHIFT)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_RANGE                    12:0
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_WOFFSET                  0x0
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  H_ACTIVE_START + H_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_H_IN (or 8192) This parameter
+//  should be programmed with an even number
+//  (bit 16 is ignored internally).
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SHIFT)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_RANGE                   28:16
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_WOFFSET                 0x0
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_V_ACTIVE_0  // Vertical Active
+#define VI_HOST_V_ACTIVE_0                      _MK_ADDR_CONST(0x28)
+#define VI_HOST_V_ACTIVE_0_WORD_COUNT                   0x1
+#define VI_HOST_V_ACTIVE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_HOST_V_ACTIVE_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_FIELD                    (_MK_MASK_CONST(0x1fff) << VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SHIFT)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_RANGE                    12:0
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_WOFFSET                  0x0
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  V_ACTIVE_START + V_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_V_IN (or 8192).
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SHIFT)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_RANGE                   28:16
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_WOFFSET                 0x0
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_VIP_H_ACTIVE_0  // VI Horizontal Active
+#define VI_VIP_H_ACTIVE_0                       _MK_ADDR_CONST(0x29)
+#define VI_VIP_H_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_VIP_H_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff1fff)
+#define VI_VIP_H_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  clock active edges from horizontal
+//  sync active edge to the first horizontal
+//  active pixel. If programmed to 0, the
+//  first active line starts after the first
+//  active clock edge following the horizontal
+//  sync active edge.
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SHIFT)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_RANGE                      12:0
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_WOFFSET                    0x0
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  Bug #178631
+//  The value is the END of the active region,
+//  so PERIOD-START = active area
+//  This parameter should be programmed
+//  with an even number
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SHIFT)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_VIP_V_ACTIVE_0  // Vertical Active
+#define VI_VIP_V_ACTIVE_0                       _MK_ADDR_CONST(0x2a)
+#define VI_VIP_V_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_VIP_V_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff1fff)
+#define VI_VIP_V_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SHIFT)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_RANGE                      12:0
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_WOFFSET                    0x0
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  Bug #178631
+//  The value is the END of the active region,
+//  so PERIOD-START = active area
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SHIFT)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_PEER_CONTROL_0  // VI Peer to Peer Control
+// For all fields:
+//   00= Disabled
+//   01= First memory
+//   10= Second memory
+//   11= not defined
+#define VI_VI_PEER_CONTROL_0                    _MK_ADDR_CONST(0x2b)
+#define VI_VI_PEER_CONTROL_0_WORD_COUNT                         0x1
+#define VI_VI_PEER_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define VI_VI_PEER_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define VI_VI_PEER_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
+// VI to Display Control Bus enable  VI will send a valid buffer signal
+//  along with Y,U,V buffer addresses
+//  and Frame Start and Frame End
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_FIELD                      (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_RANGE                      1:0
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_WOFFSET                    0x0
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_FIRST                      _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SECOND                     _MK_ENUM_CONST(2)
+
+// VI to JPEGE & MPEGE Control Bus enable  VI will send a valid buffer signal
+//  along with buffer index
+//  and Frame Start and Frame End
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_FIELD                      (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_RANGE                      3:2
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_WOFFSET                    0x0
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_FIRST                      _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SECOND                     _MK_ENUM_CONST(2)
+
+// VI to StretchBLT Control Bus enable  VI will send a valid buffer signal
+//  along with buffer index
+//  and Frame Start and Frame End
+//  The VI to SB control bus is separate from
+//  the VI to JPEGE/MPEGE bus.  This control
+//  bus is controlled by the "2nd Output to
+//  MC" write client interface.
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SHIFT                   _MK_SHIFT_CONST(4)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_FIELD                   (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_SB_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_RANGE                   5:4
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_WOFFSET                 0x0
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_FIRST                   _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SECOND                  _MK_ENUM_CONST(2)
+
+// VI to Display B Control Bus enable  VI will send a valid buffer signal
+//  along with Y,U,V buffer addresses
+//  and Frame Start and Frame End
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SHIFT                    _MK_SHIFT_CONST(6)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_RANGE                    7:6
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_WOFFSET                  0x0
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_FIRST                    _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SECOND                   _MK_ENUM_CONST(2)
+
+
+// Register VI_VI_DMA_SELECT_0  // Host DMA select
+#define VI_VI_DMA_SELECT_0                      _MK_ADDR_CONST(0x2c)
+#define VI_VI_DMA_SELECT_0_WORD_COUNT                   0x1
+#define VI_VI_DMA_SELECT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_RESET_MASK                   _MK_MASK_CONST(0x3)
+#define VI_VI_DMA_SELECT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_READ_MASK                    _MK_MASK_CONST(0x3)
+#define VI_VI_DMA_SELECT_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
+// Host DMA Request enable at end of block  Request to host DMA can be enabled every
+//  time a block of video input data is
+//  written to memory.
+//   00= Disabled
+//   01= Write Buffer DMA for RAW data stream
+//   10= First memory
+//   11= Second memory
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_DMA_SELECT_0_DMA_REQUEST_SHIFT)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_RANGE                    1:0
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_WOFFSET                  0x0
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_STREAM                   _MK_ENUM_CONST(1)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_FIRST                    _MK_ENUM_CONST(2)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SECOND                   _MK_ENUM_CONST(3)
+
+
+// Register VI_HOST_DMA_WRITE_BUFFER_0  // Host DMA Write Buffer Configuration Registers
+#define VI_HOST_DMA_WRITE_BUFFER_0                      _MK_ADDR_CONST(0x2d)
+#define VI_HOST_DMA_WRITE_BUFFER_0_WORD_COUNT                   0x1
+#define VI_HOST_DMA_WRITE_BUFFER_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_RESET_MASK                   _MK_MASK_CONST(0xe000000)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_READ_MASK                    _MK_MASK_CONST(0xfffffff)
+#define VI_HOST_DMA_WRITE_BUFFER_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffff)
+// Buffer Size
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_FIELD                    (_MK_MASK_CONST(0xffff) << VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_RANGE                    15:0
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_WOFFSET                  0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Buffer Number
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_FIELD                  (_MK_MASK_CONST(0x1ff) << VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_RANGE                  24:16
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_WOFFSET                        0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// DMA Enable
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SHIFT                     _MK_SHIFT_CONST(25)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_FIELD                     (_MK_MASK_CONST(0x1) << VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_RANGE                     25:25
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_WOFFSET                   0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_ENABLED                   _MK_ENUM_CONST(1)
+
+// Data source selection 00= VIP     (backward compatible)
+// 01= CSI_PPA
+// 10= CSI_PPB
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SHIFT                     _MK_SHIFT_CONST(26)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_FIELD                     (_MK_MASK_CONST(0x3) << VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_RANGE                     27:26
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_WOFFSET                   0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_VIP                       _MK_ENUM_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_CSI_PPA                   _MK_ENUM_CONST(1)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_CSI_PPB                   _MK_ENUM_CONST(2)
+
+
+// Register VI_HOST_DMA_BASE_ADDRESS_0  // Host DMA Write Buffer Configuration Registers
+#define VI_HOST_DMA_BASE_ADDRESS_0                      _MK_ADDR_CONST(0x2e)
+#define VI_HOST_DMA_BASE_ADDRESS_0_WORD_COUNT                   0x1
+#define VI_HOST_DMA_BASE_ADDRESS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_HOST_DMA_BASE_ADDRESS_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Base Address
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_FIELD                  (_MK_MASK_CONST(0xffffffff) << VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SHIFT)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_RANGE                  31:0
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_WOFFSET                        0x0
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_DMA_WRITE_BUFFER_STATUS_0  // Host DMA Write Buffer Status Register
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0                       _MK_ADDR_CONST(0x2f)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WORD_COUNT                    0x1
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7ffffff)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Read Only
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_FIELD                       (_MK_MASK_CONST(0x7ffffff) << VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_RANGE                       26:0
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_WOFFSET                     0x0
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0  // Host DMA Write Buffer Pending Buffer Count
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0                       _MK_ADDR_CONST(0x30)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_WORD_COUNT                    0x1
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_READ_MASK                     _MK_MASK_CONST(0x1ff)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Read Only
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_FIELD                   (_MK_MASK_CONST(0x1ff) << VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SHIFT)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_RANGE                   8:0
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_WOFFSET                 0x0
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_START_ADDRESS_FIRST_0  // Video Buffer O Start Address for First Output
+#define VI_VB0_START_ADDRESS_FIRST_0                    _MK_ADDR_CONST(0x31)
+#define VI_VB0_START_ADDRESS_FIRST_0_WORD_COUNT                         0x1
+#define VI_VB0_START_ADDRESS_FIRST_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_FIRST_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0 if
+//  output data format is RGB or YUV non-planar.
+//  This is byte address of video buffer 0
+//  Y-plane if output data format is YUV planar.
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_FIELD                  (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SHIFT)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_RANGE                  31:0
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_WOFFSET                        0x0
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BASE_ADDRESS_FIRST_0  // Video Buffer O BASE Address for First Output
+#define VI_VB0_BASE_ADDRESS_FIRST_0                     _MK_ADDR_CONST(0x32)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_WORD_COUNT                  0x1
+#define VI_VB0_BASE_ADDRESS_FIRST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+//  This is the first byte address of video
+//  buffer 0.
+//  This is byte address of video buffer 0
+//  Y-plane if output data format is planar.
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_FIELD                    (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SHIFT)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_RANGE                    31:0
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_WOFFSET                  0x0
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_START_ADDRESS_U_0  // Video Buffer O Start Address U (linked to First Output)
+#define VI_VB0_START_ADDRESS_U_0                        _MK_ADDR_CONST(0x33)
+#define VI_VB0_START_ADDRESS_U_0_WORD_COUNT                     0x1
+#define VI_VB0_START_ADDRESS_U_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_U_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0
+//  U-plane if output data format is YUV planar.
+//  output data format is YUV planar.
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SHIFT)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_RANGE                      31:0
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_WOFFSET                    0x0
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BASE_ADDRESS_U_0  // Video Buffer O BASE Address U
+//(linked to First Output)
+#define VI_VB0_BASE_ADDRESS_U_0                 _MK_ADDR_CONST(0x34)
+#define VI_VB0_BASE_ADDRESS_U_0_WORD_COUNT                      0x1
+#define VI_VB0_BASE_ADDRESS_U_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_U_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+//  This is the first byte address of video
+//  buffer 0 U-plane if output data format
+//  is planar.
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_FIELD                        (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SHIFT)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_RANGE                        31:0
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_WOFFSET                      0x0
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_START_ADDRESS_V_0  // Video Buffer O Start Address V (linked to First Output)
+#define VI_VB0_START_ADDRESS_V_0                        _MK_ADDR_CONST(0x35)
+#define VI_VB0_START_ADDRESS_V_0_WORD_COUNT                     0x1
+#define VI_VB0_START_ADDRESS_V_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_V_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0
+//  V-plane if output data format is YUV planar.
+//  output data format is YUV planar.
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SHIFT)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_RANGE                      31:0
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_WOFFSET                    0x0
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BASE_ADDRESS_V_0  // Video Buffer O BASE Address V
+//(linked to First Output)
+#define VI_VB0_BASE_ADDRESS_V_0                 _MK_ADDR_CONST(0x36)
+#define VI_VB0_BASE_ADDRESS_V_0_WORD_COUNT                      0x1
+#define VI_VB0_BASE_ADDRESS_V_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_V_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0
+//  V-plane if output data format is YUV planar.
+//  output data format is YUV planar.
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_FIELD                        (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SHIFT)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_RANGE                        31:0
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_WOFFSET                      0x0
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_SCRATCH_ADDRESS_UV_0  // Video Buffer O Scratch Address UV (linked to First Output)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0                     _MK_ADDR_CONST(0x37)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_WORD_COUNT                  0x1
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+//  If OUTPUT_FORMAT is YUV420PA, this is used.
+//  This is byte address of video buffer 0
+//  UV intermediate data is saved here during the
+//  YUV422 to YUV420PA conversion.
+//  The size allocated needs to match the
+//  FIRST_FRAME_WIDTH register setting
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_FIELD                        (_MK_MASK_CONST(0xffffffff) << VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SHIFT)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_RANGE                        31:0
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_WOFFSET                      0x0
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_FIRST_OUTPUT_FRAME_SIZE_0  // Width and height of first output frame
+// This is the size of the frame being written to memory.
+// Apply decimation or averaging to calculate the output frame
+// size.  Whether or not downscaling is used specify whatever the
+// size of the frame being written to memory.
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0                    _MK_ADDR_CONST(0x38)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_WORD_COUNT                         0x1
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_READ_MASK                  _MK_MASK_CONST(0x1fff1fff)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff1fff)
+// frame width in pixel which VI needs to process
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_FIELD                    (_MK_MASK_CONST(0x1fff) << VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SHIFT)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_RANGE                    12:0
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_WOFFSET                  0x0
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// frame height in lines which VI needs to process
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SHIFT)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_RANGE                   28:16
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_WOFFSET                 0x0
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_COUNT_FIRST_0  // Video Buffer Set 0 Count for First Output
+#define VI_VB0_COUNT_FIRST_0                    _MK_ADDR_CONST(0x39)
+#define VI_VB0_COUNT_FIRST_0_WORD_COUNT                         0x1
+#define VI_VB0_COUNT_FIRST_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define VI_VB0_COUNT_FIRST_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
+// Video Buffer Set 0 Count
+//  This specifies the number of buffers in
+//  video buffer set 0.
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_FIELD                  (_MK_MASK_CONST(0xff) << VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SHIFT)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_RANGE                  7:0
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_WOFFSET                        0x0
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_SIZE_FIRST_0  // Video Buffer Set 0 Size for First Output
+#define VI_VB0_SIZE_FIRST_0                     _MK_ADDR_CONST(0x3a)
+#define VI_VB0_SIZE_FIRST_0_WORD_COUNT                  0x1
+#define VI_VB0_SIZE_FIRST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_READ_MASK                   _MK_MASK_CONST(0x1fff1fff)
+#define VI_VB0_SIZE_FIRST_0_WRITE_MASK                  _MK_MASK_CONST(0x1fff1fff)
+// Video Buffer Set 0 Horizontal Size
+//  This parameter specifies the line stride
+//  (in pixels) for lines in the video buffer
+//  set 0.
+//  For YUV non-planar format, this parameter
+//  must be programmed as multiple of 2 pixels
+//  (bit 0 is ignored).
+//  For YUV planar format, this parameter
+//  must be programmed as multiple of 8 pixels
+//  (bits 2-0 are ignored) and it specifies the
+//  luma line stride or twice the chroma line
+//  stride.
+//  This value will be divided by 2 for chroma
+//  buffers for YUV422 and YUV420 planar formats
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SHIFT)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_RANGE                  12:0
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_WOFFSET                        0x0
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Video Buffer Set 0 Vertical Size
+//  This specifies the number of lines in each
+//  buffer in video buffer set 0.
+//  This value will be divided by 2 for chroma
+//  buffers for YUV420 planar formats
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SHIFT)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_RANGE                  28:16
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_WOFFSET                        0x0
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BUFFER_STRIDE_FIRST_0  // Video Buffer Set 0 Buffer Stride
+#define VI_VB0_BUFFER_STRIDE_FIRST_0                    _MK_ADDR_CONST(0x3b)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_WORD_COUNT                         0x1
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Video Buffer Set 0 Luma Buffer Stride
+//  This is luma buffer stride (in bytes)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_FIELD                  (_MK_MASK_CONST(0x3fffffff) << VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SHIFT)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_RANGE                  29:0
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_WOFFSET                        0x0
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Video Buffer Set 0 Chroma Buffer Stride   00= Equal to Luma Buffer Stride
+//   01= Equal to Luma Buffer Stride divided by 2
+//       in this case Luma Buffer Stride should
+//       be multiple of 2 bytes.
+//   10= Equal to Luma Buffer Stride divided by 4
+//       in this case Luma Buffer Stride should
+//       be multiple of 4 bytes.
+//   1x= Reserved
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SHIFT                  _MK_SHIFT_CONST(30)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_FIELD                  (_MK_MASK_CONST(0x3) << VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SHIFT)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_RANGE                  31:30
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_WOFFSET                        0x0
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_CBS1X                  _MK_ENUM_CONST(0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_CBS2X                  _MK_ENUM_CONST(1)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_CBS4X                  _MK_ENUM_CONST(2)
+
+
+// Register VI_VB0_START_ADDRESS_SECOND_0  // Video Buffer O Start Address for Second Output
+#define VI_VB0_START_ADDRESS_SECOND_0                   _MK_ADDR_CONST(0x3c)
+#define VI_VB0_START_ADDRESS_SECOND_0_WORD_COUNT                        0x1
+#define VI_VB0_START_ADDRESS_SECOND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_SECOND_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0 if
+//  output data format is RGB or YUV non-planar.
+//  This is byte address of video buffer 0
+//  This output data is read by the SB
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_FIELD                 (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SHIFT)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_RANGE                 31:0
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_WOFFSET                       0x0
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BASE_ADDRESS_SECOND_0  // Video Buffer O Base Address for Second Output
+#define VI_VB0_BASE_ADDRESS_SECOND_0                    _MK_ADDR_CONST(0x3d)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_WORD_COUNT                         0x1
+#define VI_VB0_BASE_ADDRESS_SECOND_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0 if
+//  output data format is RGB or non-planar.
+//  This is the first byte address of video
+//  buffer
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_FIELD                   (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SHIFT)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_RANGE                   31:0
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_WOFFSET                 0x0
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_SECOND_OUTPUT_FRAME_SIZE_0  // width and height of second output frame
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0                   _MK_ADDR_CONST(0x3e)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_WORD_COUNT                        0x1
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// frame width in pixel which VI needs to process
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SHIFT)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_RANGE                  12:0
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_WOFFSET                        0x0
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// frame height in lines which VI needs to process
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_FIELD                 (_MK_MASK_CONST(0x1fff) << VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SHIFT)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_RANGE                 28:16
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_WOFFSET                       0x0
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_COUNT_SECOND_0  // Video Buffer Set 0 Count for Second Output
+#define VI_VB0_COUNT_SECOND_0                   _MK_ADDR_CONST(0x3f)
+#define VI_VB0_COUNT_SECOND_0_WORD_COUNT                        0x1
+#define VI_VB0_COUNT_SECOND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define VI_VB0_COUNT_SECOND_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+//
+//  This specifies the number of buffers in
+//  video buffer set 0.
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_FIELD                 (_MK_MASK_CONST(0xff) << VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SHIFT)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_RANGE                 7:0
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_WOFFSET                       0x0
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_SIZE_SECOND_0  // Video Buffer Set 0 Size for Second Output
+#define VI_VB0_SIZE_SECOND_0                    _MK_ADDR_CONST(0x40)
+#define VI_VB0_SIZE_SECOND_0_WORD_COUNT                         0x1
+#define VI_VB0_SIZE_SECOND_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_READ_MASK                  _MK_MASK_CONST(0x1fff1fff)
+#define VI_VB0_SIZE_SECOND_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff1fff)
+// Video Buffer Set 0 Horizontal Size
+//  This parameter specifies the line stride
+//  (in pixels) for lines in the video buffer
+//  set 0.
+//  For YUV non-planar format, this parameter
+//  must be programmed as multiple of 2 pixels
+//  (bit 0 is ignored).
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_FIELD                 (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SHIFT)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_RANGE                 12:0
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_WOFFSET                       0x0
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Video Buffer Set 0 Vertical Size
+//  This specifies the number of lines in each
+//  buffer in video buffer set 0.
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_FIELD                 (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SHIFT)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_RANGE                 28:16
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_WOFFSET                       0x0
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BUFFER_STRIDE_SECOND_0  // Video Buffer Set 0 Buffer Stride for Second Output
+#define VI_VB0_BUFFER_STRIDE_SECOND_0                   _MK_ADDR_CONST(0x41)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_WORD_COUNT                        0x1
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_READ_MASK                         _MK_MASK_CONST(0x3fffffff)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffffff)
+// Video Buffer Set 0 Luma Buffer Stride
+//  This is luma buffer stride (in bytes)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_FIELD                 (_MK_MASK_CONST(0x3fffffff) << VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SHIFT)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_RANGE                 29:0
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_WOFFSET                       0x0
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define VI_H_LPF_NO_FILTER      576
+#define VI_H_LPF_ONE_MINUS_HPF_CUBED_C  3518
+#define VI_H_LPF_ONE_MINUS_HPF_CUBED_L  2350
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_C        438
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_L        294
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_PLUS_LPF_C       1463
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_PLUS_LPF_L       295
+#define VI_H_LPF_LPF_C  1608
+#define VI_H_LPF_LPF_L  584
+#define VI_H_LPF_LPF_PLUS_LPF_SQUARED_C 1169
+#define VI_H_LPF_LPF_PLUS_LPF_SQUARED_L 1
+#define VI_H_LPF_LPF_SQUARED_C  144
+#define VI_H_LPF_LPF_SQUARED_L  0
+#define VI_H_LPF_LPF_CUBED_C    1176
+#define VI_H_LPF_LPF_CUBED_L    8
+#define VI_H_LPF_LPF_SQUARED_SCALED_C   1944
+#define VI_H_LPF_LPF_SQUARED_SCALED_L   776
+#define VI_H_LPF_LPF_SQUARED_SCALED2_C  2040
+#define VI_H_LPF_LPF_SQUARED_SCALED2_L  872
+
+// Register VI_H_LPF_CONTROL_0  // VI Horizontal Low-Pass Filter (LPF) Control
+#define VI_H_LPF_CONTROL_0                      _MK_ADDR_CONST(0x42)
+#define VI_H_LPF_CONTROL_0_WORD_COUNT                   0x1
+#define VI_H_LPF_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x2400240)
+#define VI_H_LPF_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x1fff1fff)
+#define VI_H_LPF_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_H_LPF_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Horizontal LPF Luminance filter
+//  This controls low pass filter for Y data.
+#define VI_H_LPF_CONTROL_0_H_LPF_L_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_H_LPF_CONTROL_0_H_LPF_L_SHIFT)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_RANGE                        12:0
+#define VI_H_LPF_CONTROL_0_H_LPF_L_WOFFSET                      0x0
+#define VI_H_LPF_CONTROL_0_H_LPF_L_DEFAULT                      _MK_MASK_CONST(0x240)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_DEFAULT_MASK                 _MK_MASK_CONST(0x1fff)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Horizontal LPF Chrominance filter
+//  This controls low pass filter for U V data.
+#define VI_H_LPF_CONTROL_0_H_LPF_C_SHIFT                        _MK_SHIFT_CONST(16)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_H_LPF_CONTROL_0_H_LPF_C_SHIFT)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_RANGE                        28:16
+#define VI_H_LPF_CONTROL_0_H_LPF_C_WOFFSET                      0x0
+#define VI_H_LPF_CONTROL_0_H_LPF_C_DEFAULT                      _MK_MASK_CONST(0x240)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_DEFAULT_MASK                 _MK_MASK_CONST(0x1fff)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_H_DOWNSCALE_CONTROL_0  // VI Horizontal Down-scaling Control
+#define VI_H_DOWNSCALE_CONTROL_0                        _MK_ADDR_CONST(0x43)
+#define VI_H_DOWNSCALE_CONTROL_0_WORD_COUNT                     0x1
+#define VI_H_DOWNSCALE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x1fff000c)
+#define VI_H_DOWNSCALE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x1fff070f)
+#define VI_H_DOWNSCALE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x1fff070f)
+// Input Horizontal Size Select  Selects between the VIP and HOST input active
+//  area widths for the denominator in the
+//  downscaling ratio.  Uses VIP_H_ACTIVE_PERIOD or
+//  HOST_H_ACTIVE_PERIOD, which is the width of the
+//  data after cropping.  This is effective only when
+//  H_AVERAGING is DISABLED and H_DOWNSCALING is
+//  ENABLED.
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_FIELD                 (_MK_MASK_CONST(0x1) << VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_RANGE                 0:0
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_WOFFSET                       0x0
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_VIP                   _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_HOST                  _MK_ENUM_CONST(1)
+
+// Output Horizontal Size Select  Selects between the first and second memory output
+//  frame widths for the numerator in the downscaling
+//  ratio.  Uses FIRST_FRAME_WIDTH or
+//  SECOND_FRAME_WIDTH.
+//  This is effective
+//  only when H_AVERAGING is DISABLED and
+//  H_DOWNSCALING is ENABLED.
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_RANGE                        1:1
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_WOFFSET                      0x0
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_FIRST                        _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SECOND                       _MK_ENUM_CONST(1)
+
+//  Selects input horizontal size into scalers (extension field)
+//  00= Hor. size selected with INPUT_H_SIZE_SEL field (backward compatible)
+//  01= Hor. size of CSI_PPA is provided by CSI_PPA_H_ACTIVE register
+//  10= Hor. size of CSI_PPB is provided by CSI_PPB_H_ACTIVE register
+//  11= Hor. size of ISP     is provided by ISP_H_ACTIVE     register
+// 7:4 reserved
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_FIELD                     (_MK_MASK_CONST(0x3) << VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_RANGE                     3:2
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_WOFFSET                   0x0
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_USE_INPUT_H_SIZE_SEL                      _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_CSI_PPA                   _MK_ENUM_CONST(1)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_CSI_PPB                   _MK_ENUM_CONST(2)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_ISP                       _MK_ENUM_CONST(3)
+
+// Horizontal Averaging Control  This specifies the number of pixels to
+//  average and to decimate horizontally.
+//   000= 2-pixel averaging and 1/2 down-scaling
+//   001= 4-pixel averaging and 1/3 down-scaling
+//   010= 4-pixel averaging and 1/4 down-scaling
+//   011= 8-pixel averaging and 1/7 down-scaling
+//   100= 8-pixel averaging and 1/8 down-scaling
+//   other= reserved
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_FIELD                    (_MK_MASK_CONST(0x7) << VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_RANGE                    10:8
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_WOFFSET                  0x0
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A2D2                     _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A4D3                     _MK_ENUM_CONST(1)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A4D4                     _MK_ENUM_CONST(2)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A8D7                     _MK_ENUM_CONST(3)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A8D8                     _MK_ENUM_CONST(4)
+
+// Horizontal Decimation Accumulator Initial Value
+//  The user may initialized the H-Dec accumulator with
+//  a value between 0-(H_ACTIVE_PERIOD) to change the phase
+//  of the decimation pattern.  This will allow the user
+//  to decide which is the first pixel to keep.
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_RANGE                   28:16
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_WOFFSET                 0x0
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_V_DOWNSCALE_CONTROL_0  // VI Vertical Down-scaling Control
+#define VI_V_DOWNSCALE_CONTROL_0                        _MK_ADDR_CONST(0x44)
+#define VI_V_DOWNSCALE_CONTROL_0_WORD_COUNT                     0x1
+#define VI_V_DOWNSCALE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x1fff000c)
+#define VI_V_DOWNSCALE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x1fff370f)
+#define VI_V_DOWNSCALE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x1fff370f)
+// Input Vertical Size Select  Selects between the VIP and HOST input active
+//  area heights for the denominator in the
+//  downscaling ratio.  Uses VIP_V_ACTIVE_PERIOD or
+//  HOST_V_ACTIVE_PERIOD, which is the height of the
+//  data after cropping.  This is effective only when
+//  V_AVERAGING is DISABLED and V_DOWNSCALING is
+//  ENABLED.
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_FIELD                 (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_RANGE                 0:0
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_WOFFSET                       0x0
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_VIP                   _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_HOST                  _MK_ENUM_CONST(1)
+
+// Output Vertical Size Select  Selects between the first and second memory output
+//  frame heights for the numerator in the downscaling
+//  ratio.  Uses FIRST_FRAME_HEIGHT or
+//  SECOND_FRAME_HEIGHT.
+//  This is effective
+//  only when V_AVERAGING is DISABLED and
+//  V_DOWNSCALING is ENABLED.
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_RANGE                        1:1
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_WOFFSET                      0x0
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_FIRST                        _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SECOND                       _MK_ENUM_CONST(1)
+
+//  Selects input vertical size into scalers (extension field)
+//  00= Vert. size selected with INPUT_V_SIZE_SEL field (backward compatible)
+//  01= Vert. size of CSI_PPA is provided by CSI_PPA_V_ACTIVE register
+//  10= Vert. size of CSI_PPB is provided by CSI_PPB_V_ACTIVE register
+//  11= Vert. size of ISP     is provided by ISP_V_ACTIVE     register
+// 7:4 reserved
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_FIELD                     (_MK_MASK_CONST(0x3) << VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_RANGE                     3:2
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_WOFFSET                   0x0
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_USE_INPUT_V_SIZE_SEL                      _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_CSI_PPA                   _MK_ENUM_CONST(1)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_CSI_PPB                   _MK_ENUM_CONST(2)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_ISP                       _MK_ENUM_CONST(3)
+
+// Vertical Averaging Control  This specifies the number of lines to
+//  average and to decimate vertically.
+//   000= 2-line averaging and 1/2 down-scaling
+//   001= 4-line averaging and 1/3 down-scaling
+//   010= 4-line averaging and 1/4 down-scaling
+//   011= 8-line averaging and 1/7 down-scaling
+//   100= 8-line averaging and 1/8 down-scaling
+//   other= reserved
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_FIELD                    (_MK_MASK_CONST(0x7) << VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_RANGE                    10:8
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_WOFFSET                  0x0
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A2D2                     _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A4D3                     _MK_ENUM_CONST(1)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A4D4                     _MK_ENUM_CONST(2)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A8D7                     _MK_ENUM_CONST(3)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A8D8                     _MK_ENUM_CONST(4)
+
+// Flexible Vertical Scaling   0 = disabled, V_AVG_CONTROL specifies both
+//       vertical averaging and down-scaling
+//       factor.
+//   1 = enabled, fixed 2-line averaging with
+//       vertical downscaling controlled by
+//       V_DOWN_N and V_DOWN_D.
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SHIFT                  _MK_SHIFT_CONST(12)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_FIELD                  (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_RANGE                  12:12
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_WOFFSET                        0x0
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_ENABLED                        _MK_ENUM_CONST(1)
+
+// Multi-Tap Vertical Averaging Filter   0 = disabled
+//   1 = enabled
+//  This will enable the Multi-Tap filtering
+//  when the Vertical Averaging is enabled.
+//  The filter settings will depend on the
+//  V_AVG_CONTROL value.
+//  000 - 3 Taps (1,2,1)/4
+//  001 - 5 Taps (1,2,2,2,1)/8
+//  010 - 6 Taps (1,1,2,2,1,1)/8
+//  011 - 11 Taps (1,1,1,2,2,2,2,2,1,1,1)/16
+//  100 - 12 Taps (1,1,1,1,2,2,2,2,1,1,1,1)/16
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SHIFT                   _MK_SHIFT_CONST(13)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_FIELD                   (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_RANGE                   13:13
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_WOFFSET                 0x0
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_ENABLED                 _MK_ENUM_CONST(1)
+
+// Vertical Decimation Accumulator Initial Value
+//  The user may initialized the V-Dec accumulator with
+//  a value between 0-(V_ACTIVE_PERIOD) to change the phase
+//  of the decimation pattern.  This will allow the user
+//  to decide which is the first line to keep.
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_RANGE                   28:16
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_WOFFSET                 0x0
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Specifies whether odd/even field affects vertical  decimation.
+//   0 = disabled - odd/even field affects the vertical downscaling
+//   1 = enabled - field is ignored in vertical downscaling
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SHIFT                     _MK_SHIFT_CONST(28)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_FIELD                     (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_RANGE                     28:28
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_WOFFSET                   0x0
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_ENABLED                   _MK_ENUM_CONST(1)
+
+
+// Register VI_CSC_Y_0  // CSC Y Offset and Gain
+#define VI_CSC_Y_0                      _MK_ADDR_CONST(0x45)
+#define VI_CSC_Y_0_WORD_COUNT                   0x1
+#define VI_CSC_Y_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_READ_MASK                    _MK_MASK_CONST(0x3ff00ff)
+#define VI_CSC_Y_0_WRITE_MASK                   _MK_MASK_CONST(0x3ff00ff)
+// Y Offset in s.7.0 format
+#define VI_CSC_Y_0_YOF_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_CSC_Y_0_YOF_FIELD                    (_MK_MASK_CONST(0xff) << VI_CSC_Y_0_YOF_SHIFT)
+#define VI_CSC_Y_0_YOF_RANGE                    7:0
+#define VI_CSC_Y_0_YOF_WOFFSET                  0x0
+#define VI_CSC_Y_0_YOF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_YOF_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_YOF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_YOF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Y Gain for R, G, B colors in 2.8 format
+#define VI_CSC_Y_0_KYRGB_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_CSC_Y_0_KYRGB_FIELD                  (_MK_MASK_CONST(0x3ff) << VI_CSC_Y_0_KYRGB_SHIFT)
+#define VI_CSC_Y_0_KYRGB_RANGE                  25:16
+#define VI_CSC_Y_0_KYRGB_WOFFSET                        0x0
+#define VI_CSC_Y_0_KYRGB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_KYRGB_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_KYRGB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_KYRGB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_UV_R_0  // CSC U & V coefficent for R
+#define VI_CSC_UV_R_0                   _MK_ADDR_CONST(0x46)
+#define VI_CSC_UV_R_0_WORD_COUNT                        0x1
+#define VI_CSC_UV_R_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_READ_MASK                         _MK_MASK_CONST(0x7ff07ff)
+#define VI_CSC_UV_R_0_WRITE_MASK                        _MK_MASK_CONST(0x7ff07ff)
+// U coefficients for R in s.2.8 format
+#define VI_CSC_UV_R_0_KUR_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CSC_UV_R_0_KUR_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_R_0_KUR_SHIFT)
+#define VI_CSC_UV_R_0_KUR_RANGE                 10:0
+#define VI_CSC_UV_R_0_KUR_WOFFSET                       0x0
+#define VI_CSC_UV_R_0_KUR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KUR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KUR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KUR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// V coefficients for R in s.2.8 format
+#define VI_CSC_UV_R_0_KVR_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_CSC_UV_R_0_KVR_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_R_0_KVR_SHIFT)
+#define VI_CSC_UV_R_0_KVR_RANGE                 26:16
+#define VI_CSC_UV_R_0_KVR_WOFFSET                       0x0
+#define VI_CSC_UV_R_0_KVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KVR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_UV_G_0  // CSC U & V coefficent for G
+#define VI_CSC_UV_G_0                   _MK_ADDR_CONST(0x47)
+#define VI_CSC_UV_G_0_WORD_COUNT                        0x1
+#define VI_CSC_UV_G_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_READ_MASK                         _MK_MASK_CONST(0x3ff03ff)
+#define VI_CSC_UV_G_0_WRITE_MASK                        _MK_MASK_CONST(0x3ff03ff)
+// U coefficients for G in s.1.8 format
+#define VI_CSC_UV_G_0_KUG_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CSC_UV_G_0_KUG_FIELD                 (_MK_MASK_CONST(0x3ff) << VI_CSC_UV_G_0_KUG_SHIFT)
+#define VI_CSC_UV_G_0_KUG_RANGE                 9:0
+#define VI_CSC_UV_G_0_KUG_WOFFSET                       0x0
+#define VI_CSC_UV_G_0_KUG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KUG_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KUG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KUG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// V coefficients for G in s.1.8 format
+#define VI_CSC_UV_G_0_KVG_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_CSC_UV_G_0_KVG_FIELD                 (_MK_MASK_CONST(0x3ff) << VI_CSC_UV_G_0_KVG_SHIFT)
+#define VI_CSC_UV_G_0_KVG_RANGE                 25:16
+#define VI_CSC_UV_G_0_KVG_WOFFSET                       0x0
+#define VI_CSC_UV_G_0_KVG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KVG_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KVG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KVG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_UV_B_0  // CSC U & V coefficent for B
+#define VI_CSC_UV_B_0                   _MK_ADDR_CONST(0x48)
+#define VI_CSC_UV_B_0_WORD_COUNT                        0x1
+#define VI_CSC_UV_B_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_READ_MASK                         _MK_MASK_CONST(0x7ff07ff)
+#define VI_CSC_UV_B_0_WRITE_MASK                        _MK_MASK_CONST(0x7ff07ff)
+// U coefficients for B in s.2.8 format
+#define VI_CSC_UV_B_0_KUB_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CSC_UV_B_0_KUB_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_B_0_KUB_SHIFT)
+#define VI_CSC_UV_B_0_KUB_RANGE                 10:0
+#define VI_CSC_UV_B_0_KUB_WOFFSET                       0x0
+#define VI_CSC_UV_B_0_KUB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KUB_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KUB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KUB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// V coefficients for B in s.2.8 format
+#define VI_CSC_UV_B_0_KVB_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_CSC_UV_B_0_KVB_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_B_0_KVB_SHIFT)
+#define VI_CSC_UV_B_0_KVB_RANGE                 26:16
+#define VI_CSC_UV_B_0_KVB_WOFFSET                       0x0
+#define VI_CSC_UV_B_0_KVB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KVB_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KVB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KVB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_ALPHA_0  // RGB Color Space Converter Alpha value
+#define VI_CSC_ALPHA_0                  _MK_ADDR_CONST(0x49)
+#define VI_CSC_ALPHA_0_WORD_COUNT                       0x1
+#define VI_CSC_ALPHA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define VI_CSC_ALPHA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define VI_CSC_ALPHA_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// When output format to memory is selected
+//  for RGB888, the pixel data is 32-bit aligned
+//  The value programmed here will be appended to the
+//  RGB888 data as the 8 MSBs and can be used as an
+//  alpha value.
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_FIELD                       (_MK_MASK_CONST(0xff) << VI_CSC_ALPHA_0_RGB888_ALPHA_SHIFT)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_RANGE                       7:0
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_WOFFSET                     0x0
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_VSYNC_0  // Valid when INPUT_SOURCE is HOST
+#define VI_HOST_VSYNC_0                 _MK_ADDR_CONST(0x4a)
+#define VI_HOST_VSYNC_0_WORD_COUNT                      0x1
+#define VI_HOST_VSYNC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define VI_HOST_VSYNC_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// This triggers VI's internal VSYNC generation
+// Always write once to this register with '1'
+// before writing the Frame's data to Y_FIFO_DATA
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_FIELD                        (_MK_MASK_CONST(0x1) << VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SHIFT)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_RANGE                        0:0
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_WOFFSET                      0x0
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_COMMAND_0  // VI Command
+#define VI_COMMAND_0                    _MK_ADDR_CONST(0x4b)
+#define VI_COMMAND_0_WORD_COUNT                         0x1
+#define VI_COMMAND_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define VI_COMMAND_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_READ_MASK                  _MK_MASK_CONST(0x1fff0f01)
+#define VI_COMMAND_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff0f01)
+// Process Odd/Even field  (effective when INPUT_SOURCE is HOST)
+//  Writing to this bit will initialize VI
+//  to receive one field of video.
+//   0= odd field
+//   1= even field
+#define VI_COMMAND_0_PROCESS_FIELD_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_COMMAND_0_PROCESS_FIELD_FIELD                        (_MK_MASK_CONST(0x1) << VI_COMMAND_0_PROCESS_FIELD_SHIFT)
+#define VI_COMMAND_0_PROCESS_FIELD_RANGE                        0:0
+#define VI_COMMAND_0_PROCESS_FIELD_WOFFSET                      0x0
+#define VI_COMMAND_0_PROCESS_FIELD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_PROCESS_FIELD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_COMMAND_0_PROCESS_FIELD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_PROCESS_FIELD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_PROCESS_FIELD_ODD                  _MK_ENUM_CONST(0)
+#define VI_COMMAND_0_PROCESS_FIELD_EVEN                 _MK_ENUM_CONST(1)
+
+// Y-FIFO Threshold
+//  This specifies maximum number of filled
+//  locations in Y-FIFO for the Y-FIFO Threshold
+//  Status bit.
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_FIELD                     (_MK_MASK_CONST(0xf) << VI_COMMAND_0_Y_FIFO_THRESHOLD_SHIFT)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_RANGE                     11:8
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_WOFFSET                   0x0
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Vertical Counter Threshold
+//  This specifies a threshold which, when
+//  exceeded, would generate the vertical
+//  counter interrupt if the interrupt is
+//  enabled. This is used to detect the case
+//  when the host is sending too many input data
+//  than expected by VI module.
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_COMMAND_0_V_COUNTER_THRESHOLD_SHIFT)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_RANGE                  28:16
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_WOFFSET                        0x0
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_FIFO_STATUS_0  // Host FIFO status
+#define VI_HOST_FIFO_STATUS_0                   _MK_ADDR_CONST(0x4c)
+#define VI_HOST_FIFO_STATUS_0_WORD_COUNT                        0x1
+#define VI_HOST_FIFO_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x770f)
+#define VI_HOST_FIFO_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// This indicates the number of filled locations
+//  in Y-FIFO. If the returned value is 4'h0, the
+//  fifo is empty and if the returned value is
+//  4'hF then the fifo is full.
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_FIELD                       (_MK_MASK_CONST(0xf) << VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SHIFT)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_RANGE                       3:0
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_WOFFSET                     0x0
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// This indicates the number of filled locations
+//  in U-FIFO. If the returned value is 3'h0, the
+//  fifo is empty and if the returned value is
+//  3'h7 then the fifo is full.
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_FIELD                       (_MK_MASK_CONST(0x7) << VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SHIFT)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_RANGE                       10:8
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_WOFFSET                     0x0
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// This indicates the number of filled locations
+//  in V-FIFO. If the returned value is 3'h0, the
+//  fifo is empty and if the returned value is
+//  3'h7 then the fifo is full.
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SHIFT                       _MK_SHIFT_CONST(12)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_FIELD                       (_MK_MASK_CONST(0x7) << VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SHIFT)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_RANGE                       14:12
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_WOFFSET                     0x0
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_INTERRUPT_MASK_0  // Interrupt Mask
+#define VI_INTERRUPT_MASK_0                     _MK_ADDR_CONST(0x4d)
+#define VI_INTERRUPT_MASK_0_WORD_COUNT                  0x1
+#define VI_INTERRUPT_MASK_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RESET_MASK                  _MK_MASK_CONST(0x1fefffff)
+#define VI_INTERRUPT_MASK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_READ_MASK                   _MK_MASK_CONST(0x1fefffff)
+#define VI_INTERRUPT_MASK_0_WRITE_MASK                  _MK_MASK_CONST(0x1fefffff)
+// VD8 pin Interrupt Mask  This bit controls interrupt when VD8
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD8_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_RANGE                  0:0
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Mask  This bit controls interrupt when VD9
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_SHIFT                  _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD9_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_RANGE                  1:1
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Mask  This bit controls interrupt when VD10
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_SHIFT                 _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD10_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_RANGE                 2:2
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Mask  This bit controls interrupt when VD11
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_SHIFT                 _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD11_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_RANGE                 3:3
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Mask  This bit controls interrupt when VGP4
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SHIFT                 _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_RANGE                 4:4
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Mask  This bit controls interrupt when VGP5
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SHIFT                 _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_RANGE                 5:5
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Mask  This bit controls interrupt when VGP6
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_RANGE                 6:6
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Mask  This bit controls interrupt when VHS
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_SHIFT                  _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VHS_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_RANGE                  7:7
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Mask  This bit controls interrupt when VVS
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_SHIFT                  _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VVS_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_RANGE                  8:8
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Vertical Counter Interrupt Mask  (effective when VIDEO_SOURCE is HOST)
+//  This bit controls interrupt when the
+//  vertical counter threshold is reached.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SHIFT                    _MK_SHIFT_CONST(9)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_RANGE                    9:9
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Y-FIFO Threshold Interrupt Mask  This bit controls interrupt when the number
+//  of filled locations in Y-FIFO is equal or
+//  greater than the Y_FIFO_THRESHOLD value.
+//  This bit should be set to 1 only when
+//  INPUT_SOURCE is HOST.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SHIFT                  _MK_SHIFT_CONST(10)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_RANGE                  10:10
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Buffer Done First Output Interrupt Mask  This bit controls interrupt when the
+//  First Output to memory has written
+//  a buffer to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SHIFT                  _MK_SHIFT_CONST(11)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_RANGE                  11:11
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Frame Done First Output Interrupt Mask  This bit controls interrupt when the
+//  First Output to memory has written
+//  a frame to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SHIFT                   _MK_SHIFT_CONST(12)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_RANGE                   12:12
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_WOFFSET                 0x0
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Buffer Done Second Output Interrupt Mask  This bit controls interrupt when the
+//  Second Output to memory has written
+//  a buffer to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SHIFT                 _MK_SHIFT_CONST(13)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_RANGE                 13:13
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Buffer Done Second Output Interrupt Mask  This bit controls interrupt when the
+//  Second Output to memory has written
+//  a frame to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SHIFT                  _MK_SHIFT_CONST(14)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_RANGE                  14:14
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VI to EPP Error Interrupt Mask  This bit controls interrupt when the
+//  VI drops data to the EPP because the
+//  EPP is stalling the vi2epp bus and
+//  data is coming from the pins
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(15)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_RANGE                    15:15
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// YUV420PA Error Interrupt Mask  This bit controls interrupt when the
+//  VI does not average data because the
+//  line buffer data is not ready from the
+//  memory controller.  The VI will write
+//  unaveraged data and will write the U,V
+//  data from the even line in such cases.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(16)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_RANGE                       16:16
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_WOFFSET                     0x0
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// VI to Peer stall - First Memory Output  This bit controls interrupt when the
+//  VI drops peer bus packet(s) because the
+//  peer is stalling the first output peer
+//  bus and data is coming from the pins
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SHIFT                      _MK_SHIFT_CONST(17)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_RANGE                      17:17
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_WOFFSET                    0x0
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// VI to Peer stall - Second Memory Output  This bit controls interrupt when the
+//  VI drops peer bus packet(s) because the
+//  peer is stalling the second output peer
+//  bus and data is coming from the pins
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SHIFT                     _MK_SHIFT_CONST(18)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_RANGE                     18:18
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_WOFFSET                   0x0
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Write Buffer DMA to VI Stalls VI and causes an error  This bit controls interrupt when the
+//  VI drops raw 8-bit stream data because
+//  the Write Buffer DMA is stalling.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SHIFT                    _MK_SHIFT_CONST(19)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_RANGE                    19:19
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Stream 1 raise  This bit controls interrupt when the
+//  the Stream 1 Raise is enabled and
+//  returned
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SHIFT                       _MK_SHIFT_CONST(21)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_RANGE                       21:21
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_WOFFSET                     0x0
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Stream 2 raise  This bit controls interrupt when the
+//  the Stream 2 Raise is enabled and
+//  returned
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SHIFT                       _MK_SHIFT_CONST(22)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_RANGE                       22:22
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_WOFFSET                     0x0
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T vi input gets an upstream error.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(23)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_RANGE                    23:23
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T input get an underrun error
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(24)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_RANGE                    24:24
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T input get an overrun error
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(25)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_RANGE                     25:25
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_WOFFSET                   0x0
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T input get a packet which means
+//  FEC+BODY in totalsize but FEC and BODY
+//  do not match FEC_SIZE and BODY_SIZE
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SHIFT                      _MK_SHIFT_CONST(26)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_RANGE                      26:26
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_WOFFSET                    0x0
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when VI drops
+// data to MC.
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT                    _MK_SHIFT_CONST(27)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_RANGE                    27:27
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when VI drops
+// data to MC.
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT                   _MK_SHIFT_CONST(28)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_RANGE                   28:28
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_WOFFSET                 0x0
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register VI_INTERRUPT_TYPE_SELECT_0  // Interrupt Type Select
+#define VI_INTERRUPT_TYPE_SELECT_0                      _MK_ADDR_CONST(0x4e)
+#define VI_INTERRUPT_TYPE_SELECT_0_WORD_COUNT                   0x1
+#define VI_INTERRUPT_TYPE_SELECT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_RESET_MASK                   _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_TYPE_SELECT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_TYPE_SELECT_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// VD8 pin Interrupt Type  This bit controls interrupt VD8
+//  if edge or level type
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_RANGE                   0:0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Type  This bit controls interrupt VD9
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_RANGE                   1:1
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Type  This bit controls interrupt VD10
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_RANGE                  2:2
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Type  This bit controls interrupt VD11
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_RANGE                  3:3
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Type  This bit controls interrupt VGP4
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_RANGE                  4:4
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Type  This bit controls interrupt VGP5
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_RANGE                  5:5
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Type  This bit controls interrupt VGP6
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_RANGE                  6:6
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Type  This bit controls interrupt VHS
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_RANGE                   7:7
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Type  This bit controls interrupt VVS
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_RANGE                   8:8
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+
+// Register VI_INTERRUPT_POLARITY_SELECT_0  // Interrupt Polarity Select
+#define VI_INTERRUPT_POLARITY_SELECT_0                  _MK_ADDR_CONST(0x4f)
+#define VI_INTERRUPT_POLARITY_SELECT_0_WORD_COUNT                       0x1
+#define VI_INTERRUPT_POLARITY_SELECT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_RESET_MASK                       _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_POLARITY_SELECT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_POLARITY_SELECT_0_WRITE_MASK                       _MK_MASK_CONST(0x1ff)
+// VD8 pin Interrupt Type  This bit controls interrupt VD8
+//  if edge or level type
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_RANGE                   0:0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Type  This bit controls interrupt VD9
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_RANGE                   1:1
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Type  This bit controls interrupt VD10
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_RANGE                  2:2
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Type  This bit controls interrupt VD11
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_RANGE                  3:3
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Type  This bit controls interrupt VGP4
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_RANGE                  4:4
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Type  This bit controls interrupt VGP5
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_RANGE                  5:5
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Type  This bit controls interrupt VGP6
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_RANGE                  6:6
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Type  This bit controls interrupt VHS
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_RANGE                   7:7
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Type  This bit controls interrupt VVS
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_RANGE                   8:8
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+
+// Register VI_INTERRUPT_STATUS_0  // Interrupt Enable
+#define VI_INTERRUPT_STATUS_0                   _MK_ADDR_CONST(0x50)
+#define VI_INTERRUPT_STATUS_0_WORD_COUNT                        0x1
+#define VI_INTERRUPT_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x1fffffff)
+#define VI_INTERRUPT_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// VD8 pin Interrupt Status  This bit controls interrupt when VD8
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_RANGE                      0:0
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Status  This bit controls interrupt when VD9
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_RANGE                      1:1
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Status  This bit controls interrupt when VD10
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_RANGE                     2:2
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Status  This bit controls interrupt when VD11
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_RANGE                     3:3
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Status  This bit controls interrupt when VGP4
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_RANGE                     4:4
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Status  This bit controls interrupt when VGP5
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_RANGE                     5:5
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Status  This bit controls interrupt when VGP6
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_RANGE                     6:6
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Status  This bit controls interrupt when VHS
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_RANGE                      7:7
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Status  This bit controls interrupt when VVS
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_RANGE                      8:8
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// Vertical Counter Interrupt Status  (effective when VIDEO_SOURCE is HOST)
+//  This bit controls interrupt when the
+//  vertical counter threshold is reached.
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(9)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_RANGE                        9:9
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// Y-FIFO Threshold Interrupt Enable  This bit controls interrupt when the number
+//  of filled locations in Y-FIFO is equal or
+//  greater than the Y_FIFO_THRESHOLD value.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(10)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_RANGE                      10:10
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// Buffer Done First Output Interrupt Status  This bit is set when a buffer has been
+//  written to memory by the first output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(11)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_RANGE                      11:11
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// Frame Done First Output Interrupt Status  This bit is set when a frame has been
+//  written to memory by the first output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(12)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_RANGE                       12:12
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_WOFFSET                     0x0
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_NOINTR                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_INTR                        _MK_ENUM_CONST(1)
+
+// Buffer Done Second Output Interrupt Status  This bit is set when a buffer has been
+//  written to memory by the second output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(13)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_RANGE                     13:13
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// Frame Done Second Output Interrupt Status  This bit is set when a frame has been
+//  written to memory by the second output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(14)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_RANGE                      14:14
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VI to EPP Error Interrupt Enable  This bit controls interrupt when the
+//  VI drops data to the EPP because the
+//  EPP is stalling the vi2epp bus and
+//  data is coming from the pins
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(15)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_RANGE                        15:15
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// YUV420PA Error Interrupt Enable This bit shows the status of if the
+//  VI does not average data because the
+//  line buffer data is not ready from the
+//  memory controller.  The VI will write
+//  unaveraged data and will write the U,V
+//  data from the even line in such cases.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_RANGE                   16:16
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_WOFFSET                 0x0
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_NOINTR                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_INTR                    _MK_ENUM_CONST(1)
+
+// This bit shows the status of if the
+//  VI dropped a buffer packet to the
+//  peer communicating with the first memory
+//  output
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SHIFT                  _MK_SHIFT_CONST(17)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_RANGE                  17:17
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_WOFFSET                        0x0
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_NOINTR                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_INTR                   _MK_ENUM_CONST(1)
+
+// This bit shows the status of if the
+//  VI dropped a buffer packet to the
+//  peer communicating with the second memory
+//  output
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SHIFT                 _MK_SHIFT_CONST(18)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_RANGE                 18:18
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_WOFFSET                       0x0
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_NOINTR                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_INTR                  _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  VI drops data to the Write Buffer DMA
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(19)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_RANGE                        19:19
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// Top or Bottom Field Status  This bit specifies whether the last received
+//  video data field is top field or bottom
+//  field as defined by FIELD_TYPE bit. This bit
+//  is forced to 0 if FIELD_DETECT is DISABLED
+//  when VIDEO_SOURCE is VIP.
+//  This bit cannot be reset by software by
+//  writing a 1.
+//   0= Bottom field received
+//   1= Top field received
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_SHIFT                        _MK_SHIFT_CONST(20)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FIELD_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_RANGE                        20:20
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_BOTTOM                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_TOP                  _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  Raise Stream 1 returns to the Host
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SHIFT                   _MK_SHIFT_CONST(21)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_RANGE                   21:21
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_WOFFSET                 0x0
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_NOINTR                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_INTR                    _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  Raise Stream 2 returns to the Host
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SHIFT                   _MK_SHIFT_CONST(22)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_RANGE                   22:22
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_WOFFSET                 0x0
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_NOINTR                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_INTR                    _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T vi input gets an upstream error (error from the tuner)
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(23)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_RANGE                        23:23
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T input get an underrun error (START condition detected
+//  prior to receiving a full packet)
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(24)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_RANGE                        24:24
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T input get an overrun error (more bytes in packet than specified
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SHIFT                 _MK_SHIFT_CONST(25)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_RANGE                 25:25
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_WOFFSET                       0x0
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_NOINTR                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_INTR                  _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T input an other protocol error (ex:
+//  total packet received is FEC_SIZE+BODY_SIZE but
+//  the individual FEC portion != FEC_SIZE and
+//  the individual BODY portion != BODY_SIZE
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SHIFT                  _MK_SHIFT_CONST(26)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_RANGE                  26:26
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_WOFFSET                        0x0
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_NOINTR                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_INTR                   _MK_ENUM_CONST(1)
+
+// If FIRST_OUTPUT is dropping data to MC, INTR
+//   will be set.
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(27)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_RANGE                        27:27
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// If SECOND_OUTPUT is dropping data to MC, INTR
+//   will be set.
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(28)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_RANGE                       28:28
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_WOFFSET                     0x0
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_NOINTR                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_INTR                        _MK_ENUM_CONST(1)
+
+
+// Register VI_VIP_INPUT_STATUS_0  // Video Input Port status
+#define VI_VIP_INPUT_STATUS_0                   _MK_ADDR_CONST(0x51)
+#define VI_VIP_INPUT_STATUS_0_WORD_COUNT                        0x1
+#define VI_VIP_INPUT_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define VI_VIP_INPUT_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// The number of lines received (hsyncs)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_FIELD                  (_MK_MASK_CONST(0xffff) << VI_VIP_INPUT_STATUS_0_LINE_COUNT_SHIFT)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_RANGE                  15:0
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_WOFFSET                        0x0
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// The number of frames received (vsyncs)
+// Any write to this register, clears.
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_FIELD                 (_MK_MASK_CONST(0xffff) << VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SHIFT)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_RANGE                 31:16
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_WOFFSET                       0x0
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VIDEO_BUFFER_STATUS_0  // Interrupt Enable
+#define VI_VIDEO_BUFFER_STATUS_0                        _MK_ADDR_CONST(0x52)
+#define VI_VIDEO_BUFFER_STATUS_0_WORD_COUNT                     0x1
+#define VI_VIDEO_BUFFER_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define VI_VIDEO_BUFFER_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Buffer status
+//  This specifies the buffer number of the
+//  the last video data field written to memory
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_FIELD                        (_MK_MASK_CONST(0xff) << VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SHIFT)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_RANGE                        7:0
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_WOFFSET                      0x0
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Buffer status
+//  This specifies the buffer number of the
+//  the last video data field written to memory
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_FIELD                       (_MK_MASK_CONST(0xff) << VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SHIFT)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_RANGE                       15:8
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_WOFFSET                     0x0
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Write count of the Raw Stream Write FIFO
+//  This is the fifo used to synchronize the
+//  data coming from pads into the vi clock domain.
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_FIELD                   (_MK_MASK_CONST(0xf) << VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SHIFT)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_RANGE                   19:16
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_WOFFSET                 0x0
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_SYNC_OUTPUT_0  // VI H and V sync Output control
+#define VI_SYNC_OUTPUT_0                        _MK_ADDR_CONST(0x53)
+#define VI_SYNC_OUTPUT_0_WORD_COUNT                     0x1
+#define VI_SYNC_OUTPUT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_SYNC_OUTPUT_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// This specifies VHS output pulse width in
+//  term of number of VI clock cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 1 to 8.
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_FIELD                 (_MK_MASK_CONST(0x7) << VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SHIFT)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_RANGE                 2:0
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_WOFFSET                       0x0
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This specifies VHS output pulse period in
+//  term of number of VI clock cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 32 to 8192.
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SHIFT                        _MK_SHIFT_CONST(3)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SHIFT)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_RANGE                        15:3
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_WOFFSET                      0x0
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// This specifies VVS output pulse width in
+//  term of number of VHS cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 1 to 8.
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_FIELD                 (_MK_MASK_CONST(0x7) << VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SHIFT)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_RANGE                 18:16
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_WOFFSET                       0x0
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This specifies VVS output pulse period in
+//  term of number of VHS cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 2 to 4096.
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SHIFT                        _MK_SHIFT_CONST(19)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SHIFT)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_RANGE                        31:19
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_WOFFSET                      0x0
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_VVS_OUTPUT_DELAY_0  // VI V sync Output Delay
+#define VI_VVS_OUTPUT_DELAY_0                   _MK_ADDR_CONST(0x54)
+#define VI_VVS_OUTPUT_DELAY_0_WORD_COUNT                        0x1
+#define VI_VVS_OUTPUT_DELAY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define VI_VVS_OUTPUT_DELAY_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+// This specifies the number of VI clock cycles
+//  from leading edge of VHS to leading edge of
+//  VVS.
+//  Programmed value is actual value + 2 so
+//  valid value ranges from -2 to 13.
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_FIELD                    (_MK_MASK_CONST(0xf) << VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SHIFT)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_RANGE                    3:0
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_WOFFSET                  0x0
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_CONTROL_0  // VI Pulse Width Modulation Control
+#define VI_PWM_CONTROL_0                        _MK_ADDR_CONST(0x55)
+#define VI_PWM_CONTROL_0_WORD_COUNT                     0x1
+#define VI_PWM_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0xff30ff11)
+#define VI_PWM_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0xff30ff11)
+#define VI_PWM_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0xff30ff11)
+// PWM Enable  0= Disabled
+//  1= Enabled
+#define VI_PWM_CONTROL_0_PWM_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << VI_PWM_CONTROL_0_PWM_ENABLE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_RANGE                       0:0
+#define VI_PWM_CONTROL_0_PWM_ENABLE_WOFFSET                     0x0
+#define VI_PWM_CONTROL_0_PWM_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+// PWM Direction  0= Incrementing
+//  1= Decrementing
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_SHIFT                    _MK_SHIFT_CONST(4)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_FIELD                    (_MK_MASK_CONST(0x1) << VI_PWM_CONTROL_0_PWM_DIRECTION_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_RANGE                    4:4
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_WOFFSET                  0x0
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_INCR                     _MK_ENUM_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_DECR                     _MK_ENUM_CONST(1)
+
+// PWM High Pulse (1 to 16)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_FIELD                   (_MK_MASK_CONST(0xf) << VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_RANGE                   11:8
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_WOFFSET                 0x0
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// PWM Low Pulse  (1 to 16)
+// 19:16 reserved
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_SHIFT                    _MK_SHIFT_CONST(12)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_FIELD                    (_MK_MASK_CONST(0xf) << VI_PWM_CONTROL_0_PWM_LOW_PULSE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_RANGE                    15:12
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_WOFFSET                  0x0
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// PWM Mode Continous - after PWM is turned on, continue
+//              through the PWM's 128 cycles
+//              repeatedly until the pwm is turned off.
+// Single - after PWM is turned on, cycle once through
+//          the 128 cycles and stop.
+// Counter - after PWM is turned on, cycle through
+//           the 128 cycles PWM_COUNTER number of
+//           times then stop.
+// 23:22 reserved
+#define VI_PWM_CONTROL_0_PWM_MODE_SHIFT                 _MK_SHIFT_CONST(20)
+#define VI_PWM_CONTROL_0_PWM_MODE_FIELD                 (_MK_MASK_CONST(0x3) << VI_PWM_CONTROL_0_PWM_MODE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_MODE_RANGE                 21:20
+#define VI_PWM_CONTROL_0_PWM_MODE_WOFFSET                       0x0
+#define VI_PWM_CONTROL_0_PWM_MODE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_MODE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define VI_PWM_CONTROL_0_PWM_MODE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_MODE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_MODE_CONTINUOUS                    _MK_ENUM_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_MODE_SINGLE                        _MK_ENUM_CONST(1)
+#define VI_PWM_CONTROL_0_PWM_MODE_COUNTER                       _MK_ENUM_CONST(2)
+
+// PWM Counter
+//  8-bit value used when PWM_MODE is set to COUNTER
+//  to determine how many times the PWM will cycle
+//  through the 128 cycles
+//  before stopping.
+#define VI_PWM_CONTROL_0_PWM_COUNTER_SHIFT                      _MK_SHIFT_CONST(24)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_FIELD                      (_MK_MASK_CONST(0xff) << VI_PWM_CONTROL_0_PWM_COUNTER_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_RANGE                      31:24
+#define VI_PWM_CONTROL_0_PWM_COUNTER_WOFFSET                    0x0
+#define VI_PWM_CONTROL_0_PWM_COUNTER_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_SELECT_PULSE_A_0  // PWM Pulse Select A
+#define VI_PWM_SELECT_PULSE_A_0                 _MK_ADDR_CONST(0x56)
+#define VI_PWM_SELECT_PULSE_A_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_A_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_A_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 31 to 0
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SHIFT)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_SELECT_PULSE_B_0  // PWM Pulse Select B
+#define VI_PWM_SELECT_PULSE_B_0                 _MK_ADDR_CONST(0x57)
+#define VI_PWM_SELECT_PULSE_B_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_B_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_B_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 63 to 32
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SHIFT)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_SELECT_PULSE_C_0  // PWM Pulse Select C
+#define VI_PWM_SELECT_PULSE_C_0                 _MK_ADDR_CONST(0x58)
+#define VI_PWM_SELECT_PULSE_C_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_C_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_C_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 95 to 64
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SHIFT)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_SELECT_PULSE_D_0  // PWM Pulse Select D
+#define VI_PWM_SELECT_PULSE_D_0                 _MK_ADDR_CONST(0x59)
+#define VI_PWM_SELECT_PULSE_D_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_D_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_D_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 127 to 96
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SHIFT)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_DATA_INPUT_CONTROL_0  // VI Input Mask
+#define VI_VI_DATA_INPUT_CONTROL_0                      _MK_ADDR_CONST(0x5a)
+#define VI_VI_DATA_INPUT_CONTROL_0_WORD_COUNT                   0x1
+#define VI_VI_DATA_INPUT_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VI_DATA_INPUT_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_DATA_INPUT_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0xfff)
+// Mask the VD[11:0] pin inputs to the VI core and ISP
+// The mask is not applied to the Host GPIO read value
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_FIELD                     (_MK_MASK_CONST(0xfff) << VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SHIFT)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_RANGE                     11:0
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_WOFFSET                   0x0
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_DEFAULT                   _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_PIN_INPUT_ENABLE_0  // VI pins Input Enable
+#define VI_PIN_INPUT_ENABLE_0                   _MK_ADDR_CONST(0x5b)
+#define VI_PIN_INPUT_ENABLE_0_WORD_COUNT                        0x1
+#define VI_PIN_INPUT_ENABLE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_RESET_MASK                        _MK_MASK_CONST(0x3fefff)
+#define VI_PIN_INPUT_ENABLE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_READ_MASK                         _MK_MASK_CONST(0x3fefff)
+#define VI_PIN_INPUT_ENABLE_0_WRITE_MASK                        _MK_MASK_CONST(0x3fefff)
+// VD0 pin Input Enable  This bit controls VD0 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_RANGE                    0:0
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD1 pin Input Enable  This bit controls VD1 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_RANGE                    1:1
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD2 pin Input Enable  This bit controls VD2 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(2)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_RANGE                    2:2
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD3 pin Input Enable  This bit controls VD3 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(3)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_RANGE                    3:3
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD4 pin Input Enable  This bit controls VD4 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(4)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_RANGE                    4:4
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD5 pin Input Enable  This bit controls VD5 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(5)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_RANGE                    5:5
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD6 pin Input Enable  This bit controls VD6 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(6)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_RANGE                    6:6
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD7 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(7)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_RANGE                    7:7
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD8 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_RANGE                    8:8
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD9 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(9)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_RANGE                    9:9
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD10 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(10)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_RANGE                   10:10
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VD11 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+// 12 reserved
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(11)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_RANGE                   11:11
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VHS pin Input Enable  This bit controls VHS pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(13)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_RANGE                    13:13
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VVS pin Input Enable  This bit controls VVS pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(14)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_RANGE                    14:14
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VGP0 pin Input Enable  This bit controls VGP0 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(15)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_RANGE                   15:15
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP1 pin Input Enable  This bit controls VGP1 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_RANGE                   16:16
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP2 pin Input Enable  This bit controls VGP2 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(17)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_RANGE                   17:17
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP3 pin Input Enable  This bit controls VGP3 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_RANGE                   18:18
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP4 pin Input Enable  This bit controls VGP4 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(19)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_RANGE                   19:19
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP5 pin Input Enable  This bit controls VGP5 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(20)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_RANGE                   20:20
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP6 pin Input Enable  This bit controls VGP6 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(21)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_RANGE                   21:21
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register VI_PIN_OUTPUT_ENABLE_0  // VI pins Output Enable
+#define VI_PIN_OUTPUT_ENABLE_0                  _MK_ADDR_CONST(0x5c)
+#define VI_PIN_OUTPUT_ENABLE_0_WORD_COUNT                       0x1
+#define VI_PIN_OUTPUT_ENABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_RESET_MASK                       _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_ENABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_READ_MASK                        _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_ENABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffff)
+// VD0 pin Output Enable  This bit controls VD0 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_RANGE                  0:0
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD1 pin Output Enable  This bit controls VD1 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_RANGE                  1:1
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD2 pin Output Enable  This bit controls VD2 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_RANGE                  2:2
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD3 pin Output Enable  This bit controls VD3 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_RANGE                  3:3
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD4 pin Output Enable  This bit controls VD4 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_RANGE                  4:4
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD5 pin Output Enable  This bit controls VD5 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_RANGE                  5:5
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD6 pin Output Enable  This bit controls VD6 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_RANGE                  6:6
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD7 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_RANGE                  7:7
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD8 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(8)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_RANGE                  8:8
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD9 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(9)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_RANGE                  9:9
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD10 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(10)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_RANGE                 10:10
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VD11 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(11)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_RANGE                 11:11
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VSCK pin Output Enable  This bit controls VSCK pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(12)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_RANGE                 12:12
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VHS pin Output Enable  This bit controls VHS pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(13)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_RANGE                  13:13
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VVS pin Output Enable  This bit controls VVS pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(14)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_RANGE                  14:14
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VGP0 pin Output Enable  This bit controls VGP0 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(15)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_RANGE                 15:15
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP1 pin Output Enable  This bit controls VGP1 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_RANGE                 16:16
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP2 pin Output Enable  This bit controls VGP2 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(17)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_RANGE                 17:17
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP3 pin Output Enable  This bit controls VGP3 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(18)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_RANGE                 18:18
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP4 pin Output Enable  This bit controls VGP4 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(19)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_RANGE                 19:19
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP5 pin Output Enable  This bit controls VGP5 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(20)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_RANGE                 20:20
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP6 pin Output Enable  This bit controls VGP6 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(21)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_RANGE                 21:21
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register VI_PIN_INVERSION_0  // VI pins input/output Inversion
+//    0  reserved
+#define VI_PIN_INVERSION_0                      _MK_ADDR_CONST(0x5d)
+#define VI_PIN_INVERSION_0_WORD_COUNT                   0x1
+#define VI_PIN_INVERSION_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_RESET_MASK                   _MK_MASK_CONST(0x70006)
+#define VI_PIN_INVERSION_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_READ_MASK                    _MK_MASK_CONST(0x70006)
+#define VI_PIN_INVERSION_0_WRITE_MASK                   _MK_MASK_CONST(0x70006)
+// VHS pin Input Inversion   0= VHS input is not inverted
+//      (VHS input is active high)
+//   1= VHS input is inverted
+//      (VHS input is active low)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_SHIFT                       _MK_SHIFT_CONST(1)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VHS_IN_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_RANGE                       1:1
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_WOFFSET                     0x0
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_ENABLED                     _MK_ENUM_CONST(1)
+
+// VVS pin Input Inversion   0= VVS input is not inverted
+//      (VVS input is active high)
+//   1= VVS input is inverted
+//      (VVS input is active low)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_SHIFT                       _MK_SHIFT_CONST(2)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VVS_IN_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_RANGE                       2:2
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_WOFFSET                     0x0
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_ENABLED                     _MK_ENUM_CONST(1)
+
+// VSCK pin Output Inversion   0= VSCK output is not inverted
+//   1= VSCK output is inverted
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_RANGE                     16:16
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_WOFFSET                   0x0
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_ENABLED                   _MK_ENUM_CONST(1)
+
+// VHS pin Output Inversion   0= VHS output is not inverted
+//      (VHS output is active high)
+//   1= VHS output is inverted
+//      (VHS output is active low)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SHIFT                      _MK_SHIFT_CONST(17)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_RANGE                      17:17
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_WOFFSET                    0x0
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_ENABLED                    _MK_ENUM_CONST(1)
+
+// VVS pin Output Inversion   0= VVS output is not inverted
+//      (VVS output is active high)
+//   1= VVS output is inverted
+//      (VVS output is active low)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SHIFT                      _MK_SHIFT_CONST(18)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_RANGE                      18:18
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_WOFFSET                    0x0
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register VI_PIN_INPUT_DATA_0  // VI pins Input Data
+#define VI_PIN_INPUT_DATA_0                     _MK_ADDR_CONST(0x5e)
+#define VI_PIN_INPUT_DATA_0_WORD_COUNT                  0x1
+#define VI_PIN_INPUT_DATA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_INPUT_DATA_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// VD0 pin Input Data
+//  (effective if VD0_INPUT_ENABLE is ENABLED)
+//   0= VD0 input low
+//   1= VD0 input high
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_RANGE                        0:0
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD1 pin Input Data
+//  (effective if VD1_INPUT_ENABLE is ENABLED)
+//   0= VD1 input low
+//   1= VD1 input high
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_RANGE                        1:1
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD2 pin Input Data
+//  (effective if VD2_INPUT_ENABLE is ENABLED)
+//   0= VD2 input low
+//   1= VD2 input high
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(2)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_RANGE                        2:2
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD3 pin Input Data
+//  (effective if VD3_INPUT_ENABLE is ENABLED)
+//   0= VD3 input low
+//   1= VD3 input high
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(3)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_RANGE                        3:3
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD4 pin Input Data
+//  (effective if VD4_INPUT_ENABLE is ENABLED)
+//   0= VD4 input low
+//   1= VD4 input high
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(4)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_RANGE                        4:4
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD5 pin Input Data
+//  (effective if VD5_INPUT_ENABLE is ENABLED)
+//   0= VD5 input low
+//   1= VD5 input high
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(5)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_RANGE                        5:5
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD6 pin Input Data
+//  (effective if VD6_INPUT_ENABLE is ENABLED)
+//   0= VD6 input low
+//   1= VD6 input high
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(6)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_RANGE                        6:6
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD7 pin Input Data
+//  (effective if VD7_INPUT_ENABLE is ENABLED)
+//   0= VD7 input low
+//   1= VD7 input high
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(7)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_RANGE                        7:7
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD8 pin Input Data
+//  (effective if VD8_INPUT_ENABLE is ENABLED)
+//   0= VD8 input low
+//   1= VD8 input high
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_RANGE                        8:8
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD9 pin Input Data
+//  (effective if VD9_INPUT_ENABLE is ENABLED)
+//   0= VD9 input low
+//   1= VD9 input high
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(9)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_RANGE                        9:9
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD10 pin Input Data
+//  (effective if VD10_INPUT_ENABLE is ENABLED)
+//   0= VD10 input low
+//   1= VD10 input high
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(10)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_RANGE                       10:10
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VD11 pin Input Data
+//  (effective if VD11_INPUT_ENABLE is ENABLED)
+//   0= VD11 input low
+//   1= VD11 input high
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(11)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_RANGE                       11:11
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VSCK pin Input Data
+//  (effective if VSCK_INPUT_ENABLE is ENABLED)
+//   0= VSCK input low
+//   1= VSCK input high
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(12)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_RANGE                       12:12
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VHS pin Input Data
+//  (effective if VHS_INPUT_ENABLE is ENABLED)
+//   0= VHS input low
+//   1= VHS input high
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(13)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_RANGE                        13:13
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VVS pin Input Data
+//  (effective if VVS_INPUT_ENABLE is ENABLED)
+//   0= VVS input low
+//   1= VVS input high
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(14)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_RANGE                        14:14
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VGP0 pin Input Data
+//  (effective if VGP0_INPUT_ENABLE is ENABLED)
+//   0= VGP0 input low
+//   1= VGP0 input high
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(15)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_RANGE                       15:15
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP1 pin Input Data
+//  (effective if VGP1_INPUT_ENABLE is ENABLED)
+//   0= VGP1 input low
+//   1= VGP1 input high
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(16)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_RANGE                       16:16
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP2 pin Input Data
+//  (effective if VGP2_INPUT_ENABLE is ENABLED)
+//   0= VGP2 input low
+//   1= VGP2 input high
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(17)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_RANGE                       17:17
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP3 pin Input Data
+//  (effective if VGP3_INPUT_ENABLE is ENABLED)
+//   0= VGP3 input low
+//   1= VGP3 input high
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(18)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_RANGE                       18:18
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP4 pin Input Data
+//  (effective if VGP4_INPUT_ENABLE is ENABLED)
+//   0= VGP4 input low
+//   1= VGP4 input high
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(19)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_RANGE                       19:19
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP5 pin Input Data
+//  (effective if VGP5_INPUT_ENABLE is ENABLED)
+//   0= VGP5 input low
+//   1= VGP5 input high
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(20)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_RANGE                       20:20
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP6 pin Input Data
+//  (effective if VGP6_INPUT_ENABLE is ENABLED)
+//   0= VGP6 input low
+//   1= VGP6 input high
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(21)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_RANGE                       21:21
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_PIN_OUTPUT_DATA_0  // VI pins Output Data
+#define VI_PIN_OUTPUT_DATA_0                    _MK_ADDR_CONST(0x5f)
+#define VI_PIN_OUTPUT_DATA_0_WORD_COUNT                         0x1
+#define VI_PIN_OUTPUT_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_READ_MASK                  _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffff)
+// VD0 pin Output Data
+//  (effective if VD0_OUTPUT_ENABLE is ENABLED
+//   and VD0_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_RANGE                      0:0
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD1 pin Output Data
+//  (effective if VD1_OUTPUT_ENABLE is ENABLED
+//   and VD1_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_RANGE                      1:1
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD2 pin Output Data
+//  (effective if VD2_OUTPUT_ENABLE is ENABLED
+//   and VD2_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_RANGE                      2:2
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD3 pin Output Data
+//  (effective if VD3_OUTPUT_ENABLE is ENABLED
+//   and VD3_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(3)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_RANGE                      3:3
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD4 pin Output Data
+//  (effective if VD4_OUTPUT_ENABLE is ENABLED
+//   and VD4_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(4)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_RANGE                      4:4
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD5 pin Output Data
+//  (effective if VD5_OUTPUT_ENABLE is ENABLED
+//   and VD5_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(5)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_RANGE                      5:5
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD6 pin Output Data
+//  (effective if VD6_OUTPUT_ENABLE is ENABLED
+//   and VD6_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(6)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_RANGE                      6:6
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD7 pin Output Data
+//  (effective if VD7_OUTPUT_ENABLE is ENABLED
+//   and VD7_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_RANGE                      7:7
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD8 pin Output Data
+//  (effective if VD8_OUTPUT_ENABLE is ENABLED
+//   and VD8_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(8)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_RANGE                      8:8
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD9 pin Output Data
+//  (effective if VD9_OUTPUT_ENABLE is ENABLED
+//   and VD9_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(9)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_RANGE                      9:9
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD10 pin Output Data
+//  (effective if VD10_OUTPUT_ENABLE is ENABLED
+//   and VD10_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(10)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_RANGE                     10:10
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VD11 pin Output Data
+//  (effective if VD11_OUTPUT_ENABLE is ENABLED
+//   and VD11_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(11)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_RANGE                     11:11
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VSCK pin Output Data
+//  (effective if VSCK_OUTPUT_ENABLE is ENABLED
+//   and VSCK_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_RANGE                     12:12
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VHS pin Output Data
+//  (effective if VHS_OUTPUT_ENABLE is ENABLED
+//   and VHS_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(13)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_RANGE                      13:13
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VVS pin Output Data
+//  (effective if VVS_OUTPUT_ENABLE is ENABLED
+//   and VVS_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(14)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_RANGE                      14:14
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VGP0 pin Output Data
+//  (effective if VGP0_OUTPUT_ENABLE is ENABLED
+//   and VGP0_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(15)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_RANGE                     15:15
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP1 pin Output Data
+//  (effective if VGP1_OUTPUT_ENABLE is ENABLED
+//   and VGP1_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_RANGE                     16:16
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP2 pin Output Data
+//  (effective if VGP2_OUTPUT_ENABLE is ENABLED
+//   and VGP2_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(17)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_RANGE                     17:17
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP3 pin Output Data
+//  (effective if VGP3_OUTPUT_ENABLE is ENABLED
+//   and VGP3_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(18)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_RANGE                     18:18
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP4 pin Output Data
+//  (effective if VGP4_OUTPUT_ENABLE is ENABLED
+//   and VGP4_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(19)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_RANGE                     19:19
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP5 pin Output Data
+//  (effective if VGP5_OUTPUT_ENABLE is ENABLED
+//   and VGP5_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(20)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_RANGE                     20:20
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP6 pin Output Data
+//  (effective if VGP6_OUTPUT_ENABLE is ENABLED
+//   and VGP6_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(21)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_RANGE                     21:21
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_PIN_OUTPUT_SELECT_0  // VI pins Output Select
+// This is the mux select used at the Pad Macro
+// For VCLK, VHSYNC, VVSYNC
+// Selects between the register programmed GPIO outputs (set to 0)
+// and the internally generated viclk, hsync, vsync (set to 1)
+// For VGP1-VGP2
+// Selects between the I^2C outputs (set to 0)
+// and the VI register programmed GPIO outputs (set to 1)
+// For VD0-VD11
+// Reserved for future use
+// data pins output will be driven by GPIO outputs if enabled
+#define VI_PIN_OUTPUT_SELECT_0                  _MK_ADDR_CONST(0x60)
+#define VI_PIN_OUTPUT_SELECT_0_WORD_COUNT                       0x1
+#define VI_PIN_OUTPUT_SELECT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_RESET_MASK                       _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_SELECT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_READ_MASK                        _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_SELECT_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffff)
+// Pin Output Select VD0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_RANGE                      0:0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD1
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_RANGE                      1:1
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD2
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_RANGE                      2:2
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD3
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SHIFT                      _MK_SHIFT_CONST(3)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_RANGE                      3:3
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD4
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SHIFT                      _MK_SHIFT_CONST(4)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_RANGE                      4:4
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD5
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SHIFT                      _MK_SHIFT_CONST(5)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_RANGE                      5:5
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD6
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SHIFT                      _MK_SHIFT_CONST(6)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_RANGE                      6:6
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD7
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_RANGE                      7:7
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD8
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SHIFT                      _MK_SHIFT_CONST(8)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_RANGE                      8:8
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD9
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SHIFT                      _MK_SHIFT_CONST(9)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_RANGE                      9:9
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD10
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SHIFT                     _MK_SHIFT_CONST(10)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_RANGE                     10:10
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD11
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SHIFT                     _MK_SHIFT_CONST(11)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_RANGE                     11:11
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VCLK
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_RANGE                     12:12
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VHSYNC
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SHIFT                      _MK_SHIFT_CONST(13)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_RANGE                      13:13
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VVSYNC
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SHIFT                      _MK_SHIFT_CONST(14)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_RANGE                      14:14
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP0
+//  0 = VGP0 output register
+//  1 = refclk
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SHIFT                     _MK_SHIFT_CONST(15)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_RANGE                     15:15
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP1
+//  0 = I^2C SCK pin
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_RANGE                     16:16
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP2
+//  0 = I^2C SDA pin
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SHIFT                     _MK_SHIFT_CONST(17)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_RANGE                     17:17
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP3
+//  0 = VGP3 output register
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SHIFT                     _MK_SHIFT_CONST(18)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_RANGE                     18:18
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP4
+//  0 = VGP4 output register
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SHIFT                     _MK_SHIFT_CONST(19)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_RANGE                     19:19
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP5
+//  0 = VGP5 output register
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SHIFT                     _MK_SHIFT_CONST(20)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_RANGE                     20:20
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP6   0= select VGP6 register data out
+//   1= select PWM out
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SHIFT                     _MK_SHIFT_CONST(21)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_RANGE                     21:21
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_DATA                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_PWM                       _MK_ENUM_CONST(1)
+
+
+// Register VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0  // raise vector at buffer end
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0                      _MK_ADDR_CONST(0x61)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_WORD_COUNT                   0x1
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_READ_MASK                    _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_WRITE_MASK                   _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_FIELD                  (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SHIFT)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_RANGE                  4:0
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_WOFFSET                        0x0
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_FIELD                 (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_RANGE                 19:16
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_WOFFSET                       0x0
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0  // raise vector at frame end
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0                       _MK_ADDR_CONST(0x62)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_WORD_COUNT                    0x1
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_WRITE_MASK                    _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_FIELD                    (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SHIFT)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_RANGE                    4:0
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_WOFFSET                  0x0
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_FIELD                   (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_RANGE                   19:16
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_WOFFSET                 0x0
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0  // raise vector at buffer end
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0                     _MK_ADDR_CONST(0x63)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_WORD_COUNT                  0x1
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_READ_MASK                   _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_WRITE_MASK                  _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_FIELD                 (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SHIFT)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_RANGE                 4:0
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_WOFFSET                       0x0
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_FIELD                        (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_RANGE                        19:16
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_WOFFSET                      0x0
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0  // raise vector at frame end
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0                      _MK_ADDR_CONST(0x64)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_WORD_COUNT                   0x1
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_READ_MASK                    _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_WRITE_MASK                   _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SHIFT)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_RANGE                   4:0
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_WOFFSET                 0x0
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_RANGE                  19:16
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_WOFFSET                        0x0
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_HOST_FIRST_OUTPUT_0  // raise vector when from host
+#define VI_RAISE_HOST_FIRST_OUTPUT_0                    _MK_ADDR_CONST(0x65)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_WORD_COUNT                         0x1
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_WRITE_MASK                         _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_FIELD                  (_MK_MASK_CONST(0x1f) << VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SHIFT)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_RANGE                  4:0
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_WOFFSET                        0x0
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_FIELD                 (_MK_MASK_CONST(0xf) << VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SHIFT)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_RANGE                 19:16
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_WOFFSET                       0x0
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_HOST_SECOND_OUTPUT_0  // raise vector when from host
+#define VI_RAISE_HOST_SECOND_OUTPUT_0                   _MK_ADDR_CONST(0x66)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_WORD_COUNT                        0x1
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_READ_MASK                         _MK_MASK_CONST(0x1f)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_WRITE_MASK                        _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_FIELD                 (_MK_MASK_CONST(0x1f) << VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SHIFT)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_RANGE                 4:0
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_WOFFSET                       0x0
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_FIELD                        (_MK_MASK_CONST(0xf) << VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SHIFT)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_RANGE                        19:16
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_WOFFSET                      0x0
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_EPP_0  // raise vector at line end
+#define VI_RAISE_EPP_0                  _MK_ADDR_CONST(0x67)
+#define VI_RAISE_EPP_0_WORD_COUNT                       0x1
+#define VI_RAISE_EPP_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_READ_MASK                        _MK_MASK_CONST(0x1f)
+#define VI_RAISE_EPP_0_WRITE_MASK                       _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SHIFT)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_RANGE                   4:0
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_WOFFSET                 0x0
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SHIFT)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_RANGE                  19:16
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_WOFFSET                        0x0
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_CAMERA_CONTROL_0  // VI camera control bits
+#define VI_CAMERA_CONTROL_0                     _MK_ADDR_CONST(0x68)
+#define VI_CAMERA_CONTROL_0_WORD_COUNT                  0x1
+#define VI_CAMERA_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x7)
+#define VI_CAMERA_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x7)
+#define VI_CAMERA_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x6)
+// VI camera input module Enable   0= Ignored - use the STOP_CAPTURE to turn off the capturing
+//   1= Enabled
+// Write a 1'b1 to this register to enable
+// the camera interface to start capturing data.
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_CAMERA_CONTROL_0_VIP_ENABLE_SHIFT)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_RANGE                    0:0
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_WOFFSET                  0x0
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// Test Mode Enable   0= Disabled
+//   1= Enabled
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SHIFT)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_RANGE                      1:1
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_WOFFSET                    0x0
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+// Disables camera capturing VI_ENABLE after the  next end of frame.
+//   0= Disabled
+//   1= Enabled
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_FIELD                  (_MK_MASK_CONST(0x1) << VI_CAMERA_CONTROL_0_STOP_CAPTURE_SHIFT)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_RANGE                  2:2
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_WOFFSET                        0x0
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_ENABLED                        _MK_ENUM_CONST(1)
+
+
+// Register VI_VI_ENABLE_0  // VI Enables
+#define VI_VI_ENABLE_0                  _MK_ADDR_CONST(0x69)
+#define VI_VI_ENABLE_0_WORD_COUNT                       0x1
+#define VI_VI_ENABLE_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_RESET_MASK                       _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_READ_MASK                        _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
+// First Output to Memory   0= Enabled
+//   1= Disabled
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SHIFT)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_RANGE                     0:0
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_WOFFSET                   0x0
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_DEFAULT                   _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_ENABLED                   _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_DISABLED                  _MK_ENUM_CONST(1)
+
+// SW enable flow control for output1
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SHIFT                       _MK_SHIFT_CONST(1)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SHIFT)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_RANGE                       1:1
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_WOFFSET                     0x0
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register VI_VI_ENABLE_2_0  // VI Enables second output
+#define VI_VI_ENABLE_2_0                        _MK_ADDR_CONST(0x6a)
+#define VI_VI_ENABLE_2_0_WORD_COUNT                     0x1
+#define VI_VI_ENABLE_2_0_RESET_VAL                      _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_RESET_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_READ_MASK                      _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_2_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
+// Second Output to Memory   0= Enabled
+//   1= Disabled
+//  Disabling output to memory may be set
+//  if only output to encoder pre-processor
+//  is needed. This will also power-down
+//  all logic which is only used to send
+//  output data to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SHIFT)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_RANGE                  0:0
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_WOFFSET                        0x0
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_DEFAULT                        _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_ENABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_DISABLED                       _MK_ENUM_CONST(1)
+
+// SW enable flow control for output2
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SHIFT                     _MK_SHIFT_CONST(1)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SHIFT)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_RANGE                     1:1
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_WOFFSET                   0x0
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_DISABLE                   _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register VI_VI_RAISE_0  // VI Enables second output
+#define VI_VI_RAISE_0                   _MK_ADDR_CONST(0x6b)
+#define VI_VI_RAISE_0_WORD_COUNT                        0x1
+#define VI_VI_RAISE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RESET_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_RAISE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_READ_MASK                         _MK_MASK_CONST(0x1)
+#define VI_VI_RAISE_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
+// Makes Raises edge triggered not level sensitive  i.e. only return raise at the end of frame, not
+//  in the middle of the v-blank time.
+//   0= Disabled
+//   1= Enabled
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_RAISE_0_RAISE_ON_EDGE_SHIFT)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_RANGE                       0:0
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_WOFFSET                     0x0
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_ENABLED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_Y_FIFO_WRITE_0  // YUV 4:2:0 Planar Y-FIFO, YUV 4:2:2 non-Planar YUV FIFO
+#define VI_Y_FIFO_WRITE_0                       _MK_ADDR_CONST(0x6c)
+#define VI_Y_FIFO_WRITE_0_WORD_COUNT                    0x1
+#define VI_Y_FIFO_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_Y_FIFO_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define VI_Y_FIFO_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SHIFT)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_RANGE                     31:0
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_WOFFSET                   0x0
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_U_FIFO_WRITE_0  // YUV 4:2:0 Planar U-FIFO
+#define VI_U_FIFO_WRITE_0                       _MK_ADDR_CONST(0x6d)
+#define VI_U_FIFO_WRITE_0_WORD_COUNT                    0x1
+#define VI_U_FIFO_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_U_FIFO_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define VI_U_FIFO_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << VI_U_FIFO_WRITE_0_U_FIFO_DATA_SHIFT)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_RANGE                     31:0
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_WOFFSET                   0x0
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_V_FIFO_WRITE_0  // YUV 4:2:0 Planar V-FIFO
+#define VI_V_FIFO_WRITE_0                       _MK_ADDR_CONST(0x6e)
+#define VI_V_FIFO_WRITE_0_WORD_COUNT                    0x1
+#define VI_V_FIFO_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_V_FIFO_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define VI_V_FIFO_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << VI_V_FIFO_WRITE_0_V_FIFO_DATA_SHIFT)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_RANGE                     31:0
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_WOFFSET                   0x0
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_MCCIF_FIFOCTRL_0  
+#define VI_VI_MCCIF_FIFOCTRL_0                  _MK_ADDR_CONST(0x6f)
+#define VI_VI_MCCIF_FIFOCTRL_0_WORD_COUNT                       0x1
+#define VI_VI_MCCIF_FIFOCTRL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define VI_VI_MCCIF_FIFOCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define VI_VI_MCCIF_FIFOCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_RANGE                       0:0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_ENABLE                      _MK_ENUM_CONST(1)
+
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SHIFT                       _MK_SHIFT_CONST(1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_RANGE                       1:1
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_ENABLE                      _MK_ENUM_CONST(1)
+
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SHIFT                       _MK_SHIFT_CONST(2)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_RANGE                       2:2
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_ENABLE                      _MK_ENUM_CONST(1)
+
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SHIFT                       _MK_SHIFT_CONST(3)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_RANGE                       3:3
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register VI_TIMEOUT_WCOAL_VI_0  
+#define VI_TIMEOUT_WCOAL_VI_0                   _MK_ADDR_CONST(0x70)
+#define VI_TIMEOUT_WCOAL_VI_0_WORD_COUNT                        0x1
+#define VI_TIMEOUT_WCOAL_VI_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_TIMEOUT_WCOAL_VI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define VI_TIMEOUT_WCOAL_VI_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_RANGE                   3:0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_WOFFSET                 0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_RANGE                    7:4
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_WOFFSET                  0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_RANGE                    11:8
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_WOFFSET                  0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(12)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_RANGE                    15:12
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_WOFFSET                  0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register VI_MCCIF_VIRUV_HP_0  
+#define VI_MCCIF_VIRUV_HP_0                     _MK_ADDR_CONST(0x71)
+#define VI_MCCIF_VIRUV_HP_0_WORD_COUNT                  0x1
+#define VI_MCCIF_VIRUV_HP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_RESET_MASK                  _MK_MASK_CONST(0x3f000f)
+#define VI_MCCIF_VIRUV_HP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_READ_MASK                   _MK_MASK_CONST(0x3f000f)
+#define VI_MCCIF_VIRUV_HP_0_WRITE_MASK                  _MK_MASK_CONST(0x3f000f)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_FIELD                     (_MK_MASK_CONST(0xf) << VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_RANGE                     3:0
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_WOFFSET                   0x0
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_FIELD                     (_MK_MASK_CONST(0x3f) << VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SHIFT)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_RANGE                     21:16
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_WOFFSET                   0x0
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_MCCIF_VIWSB_HP_0  
+#define VI_MCCIF_VIWSB_HP_0                     _MK_ADDR_CONST(0x72)
+#define VI_MCCIF_VIWSB_HP_0_WORD_COUNT                  0x1
+#define VI_MCCIF_VIWSB_HP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_RESET_MASK                  _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_READ_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_WRITE_MASK                  _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_FIELD                     (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_RANGE                     6:0
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_WOFFSET                   0x0
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_MCCIF_VIWU_HP_0  
+#define VI_MCCIF_VIWU_HP_0                      _MK_ADDR_CONST(0x73)
+#define VI_MCCIF_VIWU_HP_0_WORD_COUNT                   0x1
+#define VI_MCCIF_VIWU_HP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_FIELD                       (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_RANGE                       6:0
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_WOFFSET                     0x0
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_MCCIF_VIWV_HP_0  
+#define VI_MCCIF_VIWV_HP_0                      _MK_ADDR_CONST(0x74)
+#define VI_MCCIF_VIWV_HP_0_WORD_COUNT                   0x1
+#define VI_MCCIF_VIWV_HP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_FIELD                       (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_RANGE                       6:0
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_WOFFSET                     0x0
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_MCCIF_VIWY_HP_0  
+#define VI_MCCIF_VIWY_HP_0                      _MK_ADDR_CONST(0x75)
+#define VI_MCCIF_VIWY_HP_0_WORD_COUNT                   0x1
+#define VI_MCCIF_VIWY_HP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_FIELD                       (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_RANGE                       6:0
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_WOFFSET                     0x0
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPA_RAISE_FRAME_START_0  // CSI Pixel Parser A Raise
+#define VI_CSI_PPA_RAISE_FRAME_START_0                  _MK_ADDR_CONST(0x76)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_WORD_COUNT                       0x1
+#define VI_CSI_PPA_RAISE_FRAME_START_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_READ_MASK                        _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_WRITE_MASK                       _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPA
+//   issues a frame start to consumer.
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_RANGE                   4:0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_WOFFSET                 0x0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//   Number of frame start since last raise >= count for raise to be returned
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_FIELD                    (_MK_MASK_CONST(0xff) << VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_RANGE                    15:8
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_WOFFSET                  0x0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_RANGE                  19:16
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_WOFFSET                        0x0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPA_RAISE_FRAME_END_0  // CSI Pixel Parser A Raise
+#define VI_CSI_PPA_RAISE_FRAME_END_0                    _MK_ADDR_CONST(0x77)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_WORD_COUNT                         0x1
+#define VI_CSI_PPA_RAISE_FRAME_END_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_READ_MASK                  _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_WRITE_MASK                         _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPA
+//   issues a frame end to consumer.
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_FIELD                       (_MK_MASK_CONST(0x1f) << VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_RANGE                       4:0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_WOFFSET                     0x0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//   Number of frame end since last raise >= count for raise to be returned
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_FIELD                        (_MK_MASK_CONST(0xff) << VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_RANGE                        15:8
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_WOFFSET                      0x0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_FIELD                      (_MK_MASK_CONST(0xf) << VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_RANGE                      19:16
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_WOFFSET                    0x0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPB_RAISE_FRAME_START_0  // CSI Pixel Parser B Raise
+#define VI_CSI_PPB_RAISE_FRAME_START_0                  _MK_ADDR_CONST(0x78)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_WORD_COUNT                       0x1
+#define VI_CSI_PPB_RAISE_FRAME_START_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_READ_MASK                        _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_WRITE_MASK                       _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPB
+//   issues a frame start to consumer.
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_RANGE                   4:0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_WOFFSET                 0x0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//   Number of frame start since last raise >= count for raise to be returned
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_FIELD                    (_MK_MASK_CONST(0xff) << VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_RANGE                    15:8
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_WOFFSET                  0x0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_RANGE                  19:16
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_WOFFSET                        0x0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPB_RAISE_FRAME_END_0  // CSI Pixel Parser B Raise
+#define VI_CSI_PPB_RAISE_FRAME_END_0                    _MK_ADDR_CONST(0x79)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_WORD_COUNT                         0x1
+#define VI_CSI_PPB_RAISE_FRAME_END_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_READ_MASK                  _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_WRITE_MASK                         _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPB
+//   issues a frame end to consumer.
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_FIELD                       (_MK_MASK_CONST(0x1f) << VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_RANGE                       4:0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_WOFFSET                     0x0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//   Number of frame end since last raise >= count for raise to be returned
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_FIELD                        (_MK_MASK_CONST(0xff) << VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_RANGE                        15:8
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_WOFFSET                      0x0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_FIELD                      (_MK_MASK_CONST(0xf) << VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_RANGE                      19:16
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_WOFFSET                    0x0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPA_H_ACTIVE_0  // VI Horizontal Active
+#define VI_CSI_PPA_H_ACTIVE_0                   _MK_ADDR_CONST(0x7a)
+#define VI_CSI_PPA_H_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPA_H_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPA_H_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  clock active edges from horizontal
+//  sync active edge to the first horizontal
+//  active pixel. If programmed to 0, the
+//  first active line starts after the first
+//  active clock edge following the horizontal
+//  sync active edge.
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SHIFT)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  H_ACTIVE_START + H_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_H_IN (or 8192). This parameter
+//  should be programmed with an even number
+//  (bit 16 is ignored internally).
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPA_V_ACTIVE_0  // Vertical Active
+#define VI_CSI_PPA_V_ACTIVE_0                   _MK_ADDR_CONST(0x7b)
+#define VI_CSI_PPA_V_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPA_V_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPA_V_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SHIFT)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  V_ACTIVE_START + V_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_V_IN (or 8192).
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPB_H_ACTIVE_0  // VI Horizontal Active
+#define VI_CSI_PPB_H_ACTIVE_0                   _MK_ADDR_CONST(0x7c)
+#define VI_CSI_PPB_H_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPB_H_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPB_H_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  clock active edges from horizontal
+//  sync active edge to the first horizontal
+//  active pixel. If programmed to 0, the
+//  first active line starts after the first
+//  active clock edge following the horizontal
+//  sync active edge.
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SHIFT)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  H_ACTIVE_START + H_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_H_IN (or 8192). This parameter
+//  should be programmed with an even number
+//  (bit 16 is ignored internally).
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPB_V_ACTIVE_0  // Vertical Active
+#define VI_CSI_PPB_V_ACTIVE_0                   _MK_ADDR_CONST(0x7d)
+#define VI_CSI_PPB_V_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPB_V_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPB_V_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SHIFT)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  V_ACTIVE_START + V_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_V_IN (or 8192).
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_ISP_H_ACTIVE_0  // Used when an image comes from ISP
+#define VI_ISP_H_ACTIVE_0                       _MK_ADDR_CONST(0x7e)
+#define VI_ISP_H_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_ISP_H_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff)
+#define VI_ISP_H_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff)
+// Horizontal image size in pixels coming out of ISP.
+// Must be an even number (bit 0 is ignored).
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SHIFT)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_RANGE                     12:0
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_ISP_V_ACTIVE_0  // Used when an image comes from ISP
+#define VI_ISP_V_ACTIVE_0                       _MK_ADDR_CONST(0x7f)
+#define VI_ISP_V_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_ISP_V_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff)
+#define VI_ISP_V_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff)
+// Vertical image size in lines coming out of ISP.
+// Must be an even number (bit 0 is ignored).
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SHIFT)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_RANGE                     12:0
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_STREAM_1_RESOURCE_DEFINE_0  // defines resources used by stream 1.
+// Field definition is: 0 = resource not used; 1 = resource used.
+#define VI_STREAM_1_RESOURCE_DEFINE_0                   _MK_ADDR_CONST(0x80)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_WORD_COUNT                        0x1
+#define VI_STREAM_1_RESOURCE_DEFINE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_RESET_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_READ_MASK                         _MK_MASK_CONST(0xfff)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_WRITE_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_RANGE                 0:0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_WOFFSET                       0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_RANGE                        1:1
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_WOFFSET                      0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_RANGE                     2:2
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SHIFT                   _MK_SHIFT_CONST(3)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_RANGE                   3:3
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_WOFFSET                 0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_RANGE                     4:4
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SHIFT                   _MK_SHIFT_CONST(5)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_RANGE                   5:5
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_WOFFSET                 0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_RANGE                 6:6
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_WOFFSET                       0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_FIELD                      (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_RANGE                      7:7
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_WOFFSET                    0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_NOT_USED                   _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_USED                       _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_RANGE                     8:8
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SHIFT                     _MK_SHIFT_CONST(9)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_RANGE                     9:9
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SHIFT                        _MK_SHIFT_CONST(10)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_RANGE                        10:10
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_WOFFSET                      0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SHIFT                    _MK_SHIFT_CONST(11)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_FIELD                    (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_RANGE                    11:11
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_WOFFSET                  0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_NOT_USED                 _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_USED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_STREAM_2_RESOURCE_DEFINE_0  // defines resources used by stream 2.
+// Field definition is: 0 = resource not used; 1 = resource used.
+#define VI_STREAM_2_RESOURCE_DEFINE_0                   _MK_ADDR_CONST(0x81)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_WORD_COUNT                        0x1
+#define VI_STREAM_2_RESOURCE_DEFINE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_RESET_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_READ_MASK                         _MK_MASK_CONST(0xfff)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_WRITE_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_RANGE                 0:0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_WOFFSET                       0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_RANGE                        1:1
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_WOFFSET                      0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_RANGE                     2:2
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SHIFT                   _MK_SHIFT_CONST(3)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_RANGE                   3:3
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_WOFFSET                 0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_RANGE                     4:4
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SHIFT                   _MK_SHIFT_CONST(5)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_RANGE                   5:5
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_WOFFSET                 0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_RANGE                 6:6
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_WOFFSET                       0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_FIELD                      (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_RANGE                      7:7
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_WOFFSET                    0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_NOT_USED                   _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_USED                       _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_RANGE                     8:8
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SHIFT                     _MK_SHIFT_CONST(9)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_RANGE                     9:9
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SHIFT                        _MK_SHIFT_CONST(10)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_RANGE                        10:10
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_WOFFSET                      0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SHIFT                    _MK_SHIFT_CONST(11)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_FIELD                    (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_RANGE                    11:11
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_WOFFSET                  0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_NOT_USED                 _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_USED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_RAISE_STREAM_1_DONE_0  // raise vector when all stream 1 resources,
+// as defined by STREAM_1_RESOURCE_DEFINE register,
+// become idle after the start of the following frame.
+#define VI_RAISE_STREAM_1_DONE_0                        _MK_ADDR_CONST(0x82)
+#define VI_RAISE_STREAM_1_DONE_0_WORD_COUNT                     0x1
+#define VI_RAISE_STREAM_1_DONE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define VI_RAISE_STREAM_1_DONE_0_WRITE_MASK                     _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_FIELD                    (_MK_MASK_CONST(0x1f) << VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SHIFT)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_RANGE                    4:0
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_WOFFSET                  0x0
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_FIELD                   (_MK_MASK_CONST(0xf) << VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SHIFT)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_RANGE                   19:16
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_WOFFSET                 0x0
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_STREAM_2_DONE_0  // raise vector when all stream 2 resources,
+// as defined by STREAM_2_RESOURCE_DEFINE register,
+// become idle after the start of the following frame
+#define VI_RAISE_STREAM_2_DONE_0                        _MK_ADDR_CONST(0x83)
+#define VI_RAISE_STREAM_2_DONE_0_WORD_COUNT                     0x1
+#define VI_RAISE_STREAM_2_DONE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define VI_RAISE_STREAM_2_DONE_0_WRITE_MASK                     _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_FIELD                    (_MK_MASK_CONST(0x1f) << VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SHIFT)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_RANGE                    4:0
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_WOFFSET                  0x0
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_FIELD                   (_MK_MASK_CONST(0xf) << VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SHIFT)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_RANGE                   19:16
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_WOFFSET                 0x0
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_TS_MODE_0  // ISDB-T mode selection register
+#define VI_TS_MODE_0                    _MK_ADDR_CONST(0x84)
+#define VI_TS_MODE_0_WORD_COUNT                         0x1
+#define VI_TS_MODE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_READ_MASK                  _MK_MASK_CONST(0x3f)
+#define VI_TS_MODE_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
+// This field indicates the global enable for ISDB-T protocol handling
+#define VI_TS_MODE_0_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_TS_MODE_0_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << VI_TS_MODE_0_ENABLE_SHIFT)
+#define VI_TS_MODE_0_ENABLE_RANGE                       0:0
+#define VI_TS_MODE_0_ENABLE_WOFFSET                     0x0
+#define VI_TS_MODE_0_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+// This field determines if input data is in serial or parallel format
+#define VI_TS_MODE_0_INPUT_MODE_SHIFT                   _MK_SHIFT_CONST(1)
+#define VI_TS_MODE_0_INPUT_MODE_FIELD                   (_MK_MASK_CONST(0x1) << VI_TS_MODE_0_INPUT_MODE_SHIFT)
+#define VI_TS_MODE_0_INPUT_MODE_RANGE                   1:1
+#define VI_TS_MODE_0_INPUT_MODE_WOFFSET                 0x0
+#define VI_TS_MODE_0_INPUT_MODE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_PARALLEL                        _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_INPUT_MODE_SERIAL                  _MK_ENUM_CONST(1)
+
+// This field selected the pin configuration used for VD[1]  NONE:     TS_ERROR is tied to 0
+//            TS_PSYNC is tied to 0
+//  TS_ERROR: TS_ERROR is on VD[1]
+//            TS_PSYNC is tied to 0
+//  TS_PSYNC: TS_ERROR is tied to 0
+//            TS_PSYNC is on VD[1]
+#define VI_TS_MODE_0_PROTOCOL_SELECT_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_FIELD                      (_MK_MASK_CONST(0x3) << VI_TS_MODE_0_PROTOCOL_SELECT_SHIFT)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_RANGE                      3:2
+#define VI_TS_MODE_0_PROTOCOL_SELECT_WOFFSET                    0x0
+#define VI_TS_MODE_0_PROTOCOL_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_NONE                       _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_TS_ERROR                   _MK_ENUM_CONST(1)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_TS_PSYNC                   _MK_ENUM_CONST(2)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_RESERVED                   _MK_ENUM_CONST(3)
+
+// This field selects the buffer flow control for the Write DMA RDMA:      The RDMA engine will release the buffers back to the WDMA
+//            as the buffers are consumed
+// NONE:      The VI will automatically release the buffer back to the
+//            WMDA after each buffer ready is generated.
+// CPU:       SW needs to write the TS_CPU_FLOW_CTL register to release
+//            each buffer to the WDMA
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_SHIFT                    _MK_SHIFT_CONST(4)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_FIELD                    (_MK_MASK_CONST(0x3) << VI_TS_MODE_0_FLOW_CONTROL_MODE_SHIFT)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_RANGE                    5:4
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_WOFFSET                  0x0
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_RDMA                     _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_NONE                     _MK_ENUM_CONST(1)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_CPU                      _MK_ENUM_CONST(2)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_RESERVED                 _MK_ENUM_CONST(3)
+
+
+// Register VI_TS_CONTROL_0  // ISDB-T mode control register
+#define VI_TS_CONTROL_0                 _MK_ADDR_CONST(0x85)
+#define VI_TS_CONTROL_0_WORD_COUNT                      0x1
+#define VI_TS_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x7fff00ff)
+#define VI_TS_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x7fff00ff)
+// This field indicates the polarity of TS_VALID. Only has affect when TS_MODE.ENABLE == ENABLED    LOW indicates that the polarity of TS_VALID is active low.
+//    HIGH indicates that the polarity of TS_VALID is active high.
+#define VI_TS_CONTROL_0_VALID_POLARITY_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_FIELD                    (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_VALID_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_VALID_POLARITY_RANGE                    0:0
+#define VI_TS_CONTROL_0_VALID_POLARITY_WOFFSET                  0x0
+#define VI_TS_CONTROL_0_VALID_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_HIGH                     _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_LOW                      _MK_ENUM_CONST(1)
+
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_SHIFT                    _MK_SHIFT_CONST(1)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_FIELD                    (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_PSYNC_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_RANGE                    1:1
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_WOFFSET                  0x0
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_HIGH                     _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_LOW                      _MK_ENUM_CONST(1)
+
+#define VI_TS_CONTROL_0_ERROR_POLARITY_SHIFT                    _MK_SHIFT_CONST(2)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_FIELD                    (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_ERROR_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_RANGE                    2:2
+#define VI_TS_CONTROL_0_ERROR_POLARITY_WOFFSET                  0x0
+#define VI_TS_CONTROL_0_ERROR_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_HIGH                     _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_LOW                      _MK_ENUM_CONST(1)
+
+#define VI_TS_CONTROL_0_CLK_POLARITY_SHIFT                      _MK_SHIFT_CONST(3)
+#define VI_TS_CONTROL_0_CLK_POLARITY_FIELD                      (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_CLK_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_CLK_POLARITY_RANGE                      3:3
+#define VI_TS_CONTROL_0_CLK_POLARITY_WOFFSET                    0x0
+#define VI_TS_CONTROL_0_CLK_POLARITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_HIGH                       _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_LOW                        _MK_ENUM_CONST(1)
+
+// This field defines how the START of packet condition is determined  PSYNC: PSYNC assertion rising edge
+//  VALID: VALID assertion rising edge
+//  BOTH:  PSYNC && VALID asserted rising edge
+#define VI_TS_CONTROL_0_START_SELECT_SHIFT                      _MK_SHIFT_CONST(4)
+#define VI_TS_CONTROL_0_START_SELECT_FIELD                      (_MK_MASK_CONST(0x3) << VI_TS_CONTROL_0_START_SELECT_SHIFT)
+#define VI_TS_CONTROL_0_START_SELECT_RANGE                      5:4
+#define VI_TS_CONTROL_0_START_SELECT_WOFFSET                    0x0
+#define VI_TS_CONTROL_0_START_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_RESERVED                   _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_START_SELECT_PSYNC                      _MK_ENUM_CONST(1)
+#define VI_TS_CONTROL_0_START_SELECT_VALID                      _MK_ENUM_CONST(2)
+#define VI_TS_CONTROL_0_START_SELECT_BOTH                       _MK_ENUM_CONST(3)
+
+// This field determines if VALID is used during BODY packet capture  IGNORE: the VALID signal is ignored during the capture
+//  GATE: the VALID signal gates the capture of BODY data.
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_FIELD                 (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_BODY_VALID_SELECT_SHIFT)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_RANGE                 6:6
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_WOFFSET                       0x0
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_IGNORE                        _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_GATE                  _MK_ENUM_CONST(1)
+
+// This field determines is VI should store packets to memory that have been flagged as UPSTREAM_ERROR packets.
+//  DISCARD: Do not store packets in memory
+//  STORE:   Store UPSTREAM_ERROR packets in memory
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SHIFT                 _MK_SHIFT_CONST(7)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_FIELD                 (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SHIFT)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_RANGE                 7:7
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_WOFFSET                       0x0
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_DISCARD                       _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_STORE                 _MK_ENUM_CONST(1)
+
+// This field stores the number of BODY bytes to capture (including PSYNC)
+#define VI_TS_CONTROL_0_BODY_SIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_TS_CONTROL_0_BODY_SIZE_FIELD                 (_MK_MASK_CONST(0xff) << VI_TS_CONTROL_0_BODY_SIZE_SHIFT)
+#define VI_TS_CONTROL_0_BODY_SIZE_RANGE                 23:16
+#define VI_TS_CONTROL_0_BODY_SIZE_WOFFSET                       0x0
+#define VI_TS_CONTROL_0_BODY_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This field stores the number of FEC bytes to catpure (after the BODY has been captured)
+#define VI_TS_CONTROL_0_FEC_SIZE_SHIFT                  _MK_SHIFT_CONST(24)
+#define VI_TS_CONTROL_0_FEC_SIZE_FIELD                  (_MK_MASK_CONST(0x7f) << VI_TS_CONTROL_0_FEC_SIZE_SHIFT)
+#define VI_TS_CONTROL_0_FEC_SIZE_RANGE                  30:24
+#define VI_TS_CONTROL_0_FEC_SIZE_WOFFSET                        0x0
+#define VI_TS_CONTROL_0_FEC_SIZE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_FEC_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_FEC_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_FEC_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_TS_PACKET_COUNT_0  // ISDB-T packet count register
+#define VI_TS_PACKET_COUNT_0                    _MK_ADDR_CONST(0x86)
+#define VI_TS_PACKET_COUNT_0_WORD_COUNT                         0x1
+#define VI_TS_PACKET_COUNT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_READ_MASK                  _MK_MASK_CONST(0x1ffff)
+#define VI_TS_PACKET_COUNT_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// This field holds the current value of the received packet counter.  This counter increments
+// in the presence of a new packet, regardless of whether it is flagged as an error
+// The counter can be cleared by writing this register with 0's and can also
+// be preloaded to any value by writing the preload value to the register.
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_FIELD                        (_MK_MASK_CONST(0xffff) << VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SHIFT)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_RANGE                        15:0
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_WOFFSET                      0x0
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// This field is set to OVERFLOW when VALUE passes from 0xFFFF to 0x0000. It stays high until the CPU writes a zero to this bit to reset it.
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(16)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_FIELD                       (_MK_MASK_CONST(0x1) << VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SHIFT)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_RANGE                       16:16
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_WOFFSET                     0x0
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_NONE                        _MK_ENUM_CONST(0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_OVERFLOW                    _MK_ENUM_CONST(1)
+
+
+// Register VI_TS_ERROR_COUNT_0  // ISDB-T error count register
+#define VI_TS_ERROR_COUNT_0                     _MK_ADDR_CONST(0x87)
+#define VI_TS_ERROR_COUNT_0_WORD_COUNT                  0x1
+#define VI_TS_ERROR_COUNT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_READ_MASK                   _MK_MASK_CONST(0x1ffff)
+#define VI_TS_ERROR_COUNT_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// This field holds the current value of the error packet counter.  This counter increments in the
+// presence of a packet flagged as error (see TS_ERROR)0000 or a detected protocol violation.
+// The counter can be cleared by writing this register with 0's and can also
+// be preloaded to any value by writing the preload value to the register.
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_FIELD                  (_MK_MASK_CONST(0xffff) << VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SHIFT)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_RANGE                  15:0
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_WOFFSET                        0x0
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// This field is set to OVEFLOW when VALUE passes from 0xFFFF to 0x0000. It stays high until the CPU writes a zero to this bit to reset it.
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_FIELD                 (_MK_MASK_CONST(0x1) << VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SHIFT)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_RANGE                 16:16
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_WOFFSET                       0x0
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_NONE                  _MK_ENUM_CONST(0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_OVERFLOW                      _MK_ENUM_CONST(1)
+
+
+// Register VI_TS_CPU_FLOW_CTL_0  // ISDB-T CPU flow control register
+#define VI_TS_CPU_FLOW_CTL_0                    _MK_ADDR_CONST(0x88)
+#define VI_TS_CPU_FLOW_CTL_0_WORD_COUNT                         0x1
+#define VI_TS_CPU_FLOW_CTL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define VI_TS_CPU_FLOW_CTL_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Used only when the FLOW_CONTROL_MODE register is set to CPU
+// SW must write this register to release each buffer back to
+// WDMA.  Failure to write this register when buffers are
+// consumed will result in the WDMA stalling when it consumes all
+// allocated/free buffers.
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_FIELD                       (_MK_MASK_CONST(0x1) << VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SHIFT)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_RANGE                       0:0
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_WOFFSET                     0x0
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0  // Video Buffer Set 0 Chroma Buffer Stride.
+// This feature was introduced in SC17,
+// and represents an alternative value to using
+// VB0_BUFFER_STRIDE_C.
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0                     _MK_ADDR_CONST(0x89)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_WORD_COUNT                  0x1
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_RESET_MASK                  _MK_MASK_CONST(0x80000000)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_READ_MASK                   _MK_MASK_CONST(0xbfffffff)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_WRITE_MASK                  _MK_MASK_CONST(0xbfffffff)
+// Chroma buffer stride in bytes
+// 30 reserved
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_FIELD                      (_MK_MASK_CONST(0x3fffffff) << VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SHIFT)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_RANGE                      29:0
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_WOFFSET                    0x0
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// select type of Chroma buffer stride: 0 = Use VB0_BUFFER_STRIDE_C, deriving chroma
+// buffer stride from luma buffer stride
+// (default and backward compatible to SC15).
+// 1 = Use VB0_CHROMA_BUFFER_STRIDE.
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SHIFT                       _MK_SHIFT_CONST(31)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_FIELD                       (_MK_MASK_CONST(0x1) << VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SHIFT)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_RANGE                       31:31
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_WOFFSET                     0x0
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_RATIO                       _MK_ENUM_CONST(0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_VALUE                       _MK_ENUM_CONST(1)
+
+
+// Register VI_VB0_CHROMA_LINE_STRIDE_FIRST_0  // Video Buffer Set 0 chroma line stride for First Output of planar YUV formats
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0                       _MK_ADDR_CONST(0x8a)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_WORD_COUNT                    0x1
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_RESET_MASK                    _MK_MASK_CONST(0x80000000)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_READ_MASK                     _MK_MASK_CONST(0x80001fff)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_WRITE_MASK                    _MK_MASK_CONST(0x80001fff)
+// Video Buffer Set 0 chroma horizontal size
+//  This parameter specifies the chroma line stride
+//  (in pixels) for lines in the video buffer
+//  set 0.
+//  this parameter
+//  must be programmed as multiple of 4 pixels
+//  (bits 1-0 are ignored).
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SHIFT)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_RANGE                     12:0
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_WOFFSET                   0x0
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// select type of Chroma line stride: 0 = Use VB0_H_SIZE_1, deriving chroma line stride from luma line stride (default and backward compatible to SC15).
+// 1 = Use VB0_CHROMA_H_SIZE_1.
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SHIFT                   _MK_SHIFT_CONST(31)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_FIELD                   (_MK_MASK_CONST(0x1) << VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SHIFT)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_RANGE                   31:31
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_WOFFSET                 0x0
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_RATIO                   _MK_ENUM_CONST(0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_VALUE                   _MK_ENUM_CONST(1)
+
+
+// Register VI_EPP_LINES_PER_BUFFER_0  // number of buffers per output frame in EPP
+#define VI_EPP_LINES_PER_BUFFER_0                       _MK_ADDR_CONST(0x8b)
+#define VI_EPP_LINES_PER_BUFFER_0_WORD_COUNT                    0x1
+#define VI_EPP_LINES_PER_BUFFER_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_READ_MASK                     _MK_MASK_CONST(0x1fff)
+#define VI_EPP_LINES_PER_BUFFER_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff)
+// maximum 256 buffers per frame.
+// linesPerBuffer = FLOOR(eppLineCount/eppBufferCount)
+// linesPerBuffer must be > 2
+// eppLineCount must take into account any cropping in EPP.
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SHIFT)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_RANGE                        12:0
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_WOFFSET                      0x0
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_BUFFER_RELEASE_OUTPUT1_0  // write to this register will decrease
+// BUFFER_COUNTER by 1
+#define VI_BUFFER_RELEASE_OUTPUT1_0                     _MK_ADDR_CONST(0x8c)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_WORD_COUNT                  0x1
+#define VI_BUFFER_RELEASE_OUTPUT1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_FIELD                        (_MK_MASK_CONST(0x1) << VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SHIFT)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_RANGE                        0:0
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_WOFFSET                      0x0
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_BUFFER_RELEASE_OUTPUT2_0  
+#define VI_BUFFER_RELEASE_OUTPUT2_0                     _MK_ADDR_CONST(0x8d)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_WORD_COUNT                  0x1
+#define VI_BUFFER_RELEASE_OUTPUT2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_FIELD                        (_MK_MASK_CONST(0x1) << VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SHIFT)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_RANGE                        0:0
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_WOFFSET                      0x0
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0  // this is a debug register
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0                 _MK_ADDR_CONST(0x8e)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_WORD_COUNT                      0x1
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_FIELD                      (_MK_MASK_CONST(0xff) << VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SHIFT)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_RANGE                      7:0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_WOFFSET                    0x0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0  
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0                 _MK_ADDR_CONST(0x8f)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_WORD_COUNT                      0x1
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_FIELD                      (_MK_MASK_CONST(0xff) << VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SHIFT)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_RANGE                      7:0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_WOFFSET                    0x0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_TERMINATE_BW_FIRST_0  // write to this register will terminate
+// MC on BW operation in FIRST output.
+#define VI_TERMINATE_BW_FIRST_0                 _MK_ADDR_CONST(0x90)
+#define VI_TERMINATE_BW_FIRST_0_WORD_COUNT                      0x1
+#define VI_TERMINATE_BW_FIRST_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_FIRST_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_FIELD                        (_MK_MASK_CONST(0x1) << VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SHIFT)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_RANGE                        0:0
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_WOFFSET                      0x0
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_TERMINATE_BW_SECOND_0  // write to this register will terminate
+// MC on BW operationn in SECOND output.
+#define VI_TERMINATE_BW_SECOND_0                        _MK_ADDR_CONST(0x91)
+#define VI_TERMINATE_BW_SECOND_0_WORD_COUNT                     0x1
+#define VI_TERMINATE_BW_SECOND_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_SECOND_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_FIELD                      (_MK_MASK_CONST(0x1) << VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SHIFT)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_RANGE                      0:0
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_WOFFSET                    0x0
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_FIRST_BUFFER_ADDR_MODE_0  
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0                 _MK_ADDR_CONST(0x92)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_WORD_COUNT                      0x1
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_RESET_MASK                      _MK_MASK_CONST(0x101)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_READ_MASK                       _MK_MASK_CONST(0x101)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_WRITE_MASK                      _MK_MASK_CONST(0x101)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_FIELD                      (_MK_MASK_CONST(0x1) << VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SHIFT)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_RANGE                      0:0
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_WOFFSET                    0x0
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_LINEAR                     _MK_ENUM_CONST(0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_TILED                      _MK_ENUM_CONST(1)
+
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_FIELD                     (_MK_MASK_CONST(0x1) << VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SHIFT)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_RANGE                     8:8
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_WOFFSET                   0x0
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_LINEAR                    _MK_ENUM_CONST(0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_TILED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_VB0_SECOND_BUFFER_ADDR_MODE_0  
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0                        _MK_ADDR_CONST(0x93)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_WORD_COUNT                     0x1
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_FIELD                     (_MK_MASK_CONST(0x1) << VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SHIFT)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_RANGE                     0:0
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_WOFFSET                   0x0
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_LINEAR                    _MK_ENUM_CONST(0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_TILED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_RESERVE_0_0  // reserved register for emergency ...
+// bits[13:0] are reserved for
+// VIP Pattern Gen (Pattern Width)
+#define VI_RESERVE_0_0                  _MK_ADDR_CONST(0x94)
+#define VI_RESERVE_0_0_WORD_COUNT                       0x1
+#define VI_RESERVE_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_0_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  Program to *one less* than the desired
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_0_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_RANGE                     3:0
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  pattern width in clocks. (note that
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_1_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_RANGE                     7:4
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  there are 2 clocker per pixel for YUV422)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_2_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_RANGE                     11:8
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_3_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_RANGE                     15:12
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_1_0  // reserved register for emergency ...
+// bits[13:0] are reserved for
+// VIP Pattern Gen (Pattern Height)
+#define VI_RESERVE_1_0                  _MK_ADDR_CONST(0x95)
+#define VI_RESERVE_1_0_WORD_COUNT                       0x1
+#define VI_RESERVE_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_1_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  Program to *one less* than the desired
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_0_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_RANGE                     3:0
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  pattern height in lines
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_1_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_RANGE                     7:4
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_2_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_RANGE                     11:8
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_3_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_RANGE                     15:12
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_2_0  // reserved register for emergency ...
+// bit 0 is reserved for VIP Pattern Gen Enable
+// bit 1 is reserved for VIP Pattern Gen BayerSelect
+#define VI_RESERVE_2_0                  _MK_ADDR_CONST(0x96)
+#define VI_RESERVE_2_0_WORD_COUNT                       0x1
+#define VI_RESERVE_2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define VI_RESERVE_2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_2_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// 1 for BAYER pattern and 0 for YUV pattern
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_0_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_RANGE                     3:0
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_1_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_RANGE                     7:4
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_2_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_RANGE                     11:8
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_3_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_RANGE                     15:12
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_3_0  // reserved register for emergency ...
+#define VI_RESERVE_3_0                  _MK_ADDR_CONST(0x97)
+#define VI_RESERVE_3_0_WORD_COUNT                       0x1
+#define VI_RESERVE_3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_3_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_0_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_RANGE                     3:0
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_1_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_RANGE                     7:4
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_2_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_RANGE                     11:8
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_3_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_RANGE                     15:12
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_4_0  // reserved register for emergency ...
+#define VI_RESERVE_4_0                  _MK_ADDR_CONST(0x98)
+#define VI_RESERVE_4_0_WORD_COUNT                       0x1
+#define VI_RESERVE_4_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_4_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_0_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_RANGE                     3:0
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_1_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_RANGE                     7:4
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_2_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_RANGE                     11:8
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_3_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_RANGE                     15:12
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CSI_VI_INPUT_STREAM_CONTROL_0  // VI Input Stream Control
+#define CSI_VI_INPUT_STREAM_CONTROL_0                   _MK_ADDR_CONST(0x200)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_WORD_COUNT                        0x1
+#define CSI_VI_INPUT_STREAM_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x80)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x80)
+// VIP Start Frame Generation Don't use vi2csi_vip_vsync to generate start frame
+// (SF), or end frame (EF) markers in the pixel parser
+// output stream.
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SHIFT                  _MK_SHIFT_CONST(7)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_FIELD                  (_MK_MASK_CONST(0x1) << CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SHIFT)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_RANGE                  7:7
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_WOFFSET                        0x0
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_VSYNC_SF                       _MK_ENUM_CONST(0)    // // Pulses on vi2csi_vip_vsync will be used to
+// generate start frame (SF) and end frame (EF) markers
+// in the pixel parser output stream.
+// In AP15, only payload_only mode is supported in
+// the VIP input stream path, and this fields may 
+// always be programmed to VSYNC_SF.
+
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_NO_VSYNC_SF                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 513 [0x201] 
+
+// Register CSI_HOST_INPUT_STREAM_CONTROL_0  // Host Input Stream Control
+#define CSI_HOST_INPUT_STREAM_CONTROL_0                 _MK_ADDR_CONST(0x202)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_WORD_COUNT                      0x1
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1fff018f)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1fff008f)
+// Host Data Format Data written to Y_FIFO_WRITE port should be in CSI
+// packet format. To indicate end of packet a 1 should
+// be written to HOST_END_OF_PACKET. A 1 should also be
+// written to HOST_END_OF_PACKET before writing the first
+// word of packet data to Y_FIFO_WRITE.
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_FIELD                  (_MK_MASK_CONST(0xf) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_RANGE                  3:0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_WOFFSET                        0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_PAYLOAD_ONLY                   _MK_ENUM_CONST(0)    // // Data written to Y_FIFO_WRITE port should be
+// CSI line payload data only (no header, no footer,
+// and  no short packets). A value of 1 should not
+// be written to HOST_END_OF_PACKET (end of packet
+// pulse only gets generated when a 1 is written to
+// this bit). 
+// First line will be indicated when one of the pixel
+// parsers is first enabled with its 
+// CSI_PPA/B_STREAM_SOURCE set to "HOST".
+// The values in the following PIXEL_STREAM_A/B_CONTROL0 
+// fields, for the pixel parser that is receiving host
+// data, will be ignored;
+// CSI_PPA/B_PACKET_HEADER overridden with "NOT_SENT",
+// CSI_PPA/B_DATA_IDENTIFIER overridden with "DISABLED",
+// CSI_PPA/B_WORD_COUNT_SELECT overridden with "REGISTER".
+// CSI_PPA/B_CRC_CHECK overridden with "DISABLE",
+// CSI_PPA/B_VIRTUAL_CHANNEL_ID,
+// CSI_PPA/B_EMBEDDED_DATA_OPTIONS, and
+// CSI_PPA/B_HEADER_EC_ENABLE.
+// CSI_PPA/B_DATA_TYPE should be programmed with the 
+// 6 bit data type that is to be used to interpret the
+// stream. CSI_PPA/B_WORD_COUNT should be programmed with
+// the number of bytes per line.
+
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_PACKETS                        _MK_ENUM_CONST(1)
+
+// Host Start Frame Generation Don't use CSI Host Line counter to generate start, or
+// End, of Frame control outputs. This setting should only
+// be used if HOST_DATA_FORMAT is set to PACKETS, and the
+// Host data stream has frame sync packets.
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SHIFT                       _MK_SHIFT_CONST(7)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_FIELD                       (_MK_MASK_CONST(0x1) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_RANGE                       7:7
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_WOFFSET                     0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_LINE_COUNTER                        _MK_ENUM_CONST(0)    // // CSI Host Line counter will be used to generate Frame
+// start and end control. To signal the start of the first
+// frame the pixel parser will send a SF control, and
+// signal start of frame mark, when it is first enabled
+// with Host as its source. This setting should be used 
+// when HOST_DATA_FORMAT is set to PAYLOAD_ONLY.
+
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SHORT_PACKETS                       _MK_ENUM_CONST(1)
+
+// Writing this bit with a 1 indicates End of Packet,
+// when CSI Host data is being received in Packet Format.
+// In Packet Format vi2csi_host_hsync is not used to 
+// indicate beginning of packet.
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_FIELD                        (_MK_MASK_CONST(0x1) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_RANGE                        8:8
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_WOFFSET                      0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Host Frame Height
+// Specifies the height of the host frame when the host
+// is supplying CSI format payload only data to one of 
+// the CSI pixel parsers.
+// Programmed Value = number of lines - 1
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_FIELD                 (_MK_MASK_CONST(0x1fff) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_RANGE                 28:16
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_WOFFSET                       0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 515 [0x203] 
+
+// Register CSI_INPUT_STREAM_A_CONTROL_0  // CSI Input Stream A Control
+#define CSI_INPUT_STREAM_A_CONTROL_0                    _MK_ADDR_CONST(0x204)
+#define CSI_INPUT_STREAM_A_CONTROL_0_WORD_COUNT                         0x1
+#define CSI_INPUT_STREAM_A_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x7f0001)
+#define CSI_INPUT_STREAM_A_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0xff0013)
+#define CSI_INPUT_STREAM_A_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0xff0013)
+#define CSI_INPUT_STREAM_A_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0xff0013)
+// CSI-A Data Lane
+//   0= 1 data lane
+//   1= 2 data lanes
+//   2= 3 data lanes (not supported on SC17 & SC25)
+//   3= 4 data lanes (not supported on SC17 & SC25)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SHIFT)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_RANGE                      1:0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_WOFFSET                    0x0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Enables skip packet threshold feature. Skip packet feature is enabled.
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT                   _MK_SHIFT_CONST(4)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_RANGE                   4:4
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_WOFFSET                 0x0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_DISABLE                 _MK_ENUM_CONST(0)    // // Skip packet feature is disabled.     
+
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI-A Skip Packet Threshold
+//  This value is compared against the internal
+//  FIFO that buffer the input streams. A packet
+//  will be skipped (discarded) if the pixel
+//  stream processor is busy (probably due to
+//  padding process of a short line) and the
+//  number of entries in the internal FIFO
+//  exceeds this threshold value. Note that
+//  each entry in the internal FIFO buffer is
+//  four bytes.
+//  To turn off this feature, set the value
+//  to its maximum value (all ones).
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_FIELD                  (_MK_MASK_CONST(0xff) << CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SHIFT)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_RANGE                  23:16
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_WOFFSET                        0x0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x7f)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 517 [0x205] 
+
+// Register CSI_PIXEL_STREAM_A_CONTROL0_0  // CSI Pixel Stream A Control 0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0                   _MK_ADDR_CONST(0x206)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_RESET_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_READ_MASK                         _MK_MASK_CONST(0x3b3ffff7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_WRITE_MASK                        _MK_MASK_CONST(0x3b3ffff7)
+// CSI Pixel Parser A Stream Source   Host
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_FIELD                       (_MK_MASK_CONST(0x7) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_RANGE                       2:0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_CSI_A                       _MK_ENUM_CONST(0)    // //   CSI Interface A
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_CSI_B                       _MK_ENUM_CONST(1)    // //   CSI Interface B
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_VI_PORT                     _MK_ENUM_CONST(6)    // //   VI port
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_HOST                        _MK_ENUM_CONST(7)
+
+// CSI Pixel Parser A Packet Header processing
+//  This specifies whether packet header is
+//  sent in the beginning of packet or not.      Packet header is sent.
+//      This setting should be used if the
+//      stream source is CSI Interface A or B.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SHIFT                       _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_RANGE                       4:4
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_NOT_SENT                    _MK_ENUM_CONST(0)    // //      Packet header is not sent.
+//      This setting should not be used if the
+//      stream source is CSI Interface A or B.
+//      Unless CSI-A, or CSI-B, is operating in a
+//      stream capture debug mode.
+//      In this case, CSI_PPA_DATA_TYPE specifies
+//      the stream data format and the number
+//      of bytes per line/packet is
+//      specified by CSI_PPA_WORD_COUNT.
+//      This implies that a packet footer
+//      is also not sent.  In this case, no 
+//      packet footer CRC check should be performed.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SENT                        _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Data Identifier (DI) byte processing
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      Enabled  - Data Identifier byte in
+//      packet header should be compared against
+//      the CSI_PPA_DATA_TYPE and the
+//      CSI_PPA_VIRTUAL_CHANNEL_ID.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SHIFT                     _MK_SHIFT_CONST(5)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_FIELD                     (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_RANGE                     5:5
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_DISABLED                  _MK_ENUM_CONST(0)    // //      Disabled - Data Identifier byte in
+//      packet header should be ignored
+//      (not checked against CSI_PPA_DATA_TYPE
+//      and against CSI_PPA_VIRTUAL_CHANNEL_ID).
+//      In this case, CSI_PPA_DATA_TYPE specifies
+//      the stream data format.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_ENABLED                   _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Word Count Select
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      The number of bytes per line is to be
+//      extracted from Word Count field in the
+//      packet header. Note that if the serial
+//      link is not error free, programming this
+//      bit to HEADER may be dangerous because 
+//      the word count information in the header 
+//      may be corrupted. 
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_RANGE                   6:6
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_REGISTER                        _MK_ENUM_CONST(0)    // //      Word Count in packet header is ignored
+//      and the number of bytes per line/packet
+//      is specified by CSI_PPA_WORD_COUNT. Payload
+//      CRC check will not be valid if the word
+//      count in CSI_PPA_WORD_COUNT is different 
+//      than the count in the packet header.
+//      It is recommended to always program
+//      this bit to REGISTER and always program
+//      CSI_PPA_WORD_COUNT.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_HEADER                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Data CRC Check
+//  This parameter specifies whether the last
+//  2 bytes of packet should be treated as
+//  CRC checksum and used to perform CRC check
+//  on the payload data. Note that in case there
+//  are 2 bytes of data CRC at the end of the
+//  packet, the packet word count does not
+//  include the CRC bytes.      Data CRC Check is enabled.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SHIFT                   _MK_SHIFT_CONST(7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_RANGE                   7:7
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_DISABLE                 _MK_ENUM_CONST(0)    // //      Data CRC Check is disabled regardless
+//      of whether there are CRC checksum at
+//      the end of the packet.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Data Type  This is CSI compatible data type as defined
+//  in CSI specification. If the source stream
+//  contains packet headers this value can be compared
+//  to the CSI Data Type value in the 6 LSB of the
+//  CSI Data Identifier (DI) byte. If the source stream
+//  doesn't contain packet headers, or CSI_PPA_DATA_IDENTIFIER
+//  is DISABLED, this value will be used to determine how
+//  the stream will be converted to pixels.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SHIFT                   _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_FIELD                   (_MK_MASK_CONST(0x3f) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RANGE                   13:8
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420_8                        _MK_ENUM_CONST(24)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420_10                       _MK_ENUM_CONST(25)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_LEG_YUV420_8                    _MK_ENUM_CONST(26)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420CSPS_8                    _MK_ENUM_CONST(28)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420CSPS_10                   _MK_ENUM_CONST(29)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV422_8                        _MK_ENUM_CONST(30)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV422_10                       _MK_ENUM_CONST(31)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB444                  _MK_ENUM_CONST(32)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB555                  _MK_ENUM_CONST(33)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB565                  _MK_ENUM_CONST(34)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB666                  _MK_ENUM_CONST(35)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB888                  _MK_ENUM_CONST(36)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW6                    _MK_ENUM_CONST(40)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW7                    _MK_ENUM_CONST(41)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW8                    _MK_ENUM_CONST(42)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW10                   _MK_ENUM_CONST(43)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW12                   _MK_ENUM_CONST(44)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW14                   _MK_ENUM_CONST(45)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT1                 _MK_ENUM_CONST(48)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT2                 _MK_ENUM_CONST(49)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT3                 _MK_ENUM_CONST(50)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT4                 _MK_ENUM_CONST(51)
+
+// CSI Pixel Parser A Virtual Channel Identifier  
+//  This is CSI compatible virtual channel
+//  identifier as defined in CSI specification.
+//  If the source stream contains packet headers
+//  and CSI_PPA_DATA_IDENTIFIER is ENABLED this
+//  value will be compared to the CSI Virtual
+//  Channel Identifier value in the 2 MSB of the
+//  CSI Data Identifier (DI) byte. This value will
+//  be ignored if the source stream doesn't contain
+//  packet headers, or CSI_PPA_DATA_IDENTIFIER is 
+//  DISABLED, then this value will be ignored.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SHIFT                  _MK_SHIFT_CONST(14)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_FIELD                  (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_RANGE                  15:14
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_ONE                    _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_TWO                    _MK_ENUM_CONST(1)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_THREE                  _MK_ENUM_CONST(2)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_FOUR                   _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser A Output Format Options
+//  This parameter specifies options for output data 
+//  format.       Output for storing RAW data to memory through
+//       ISP. Undefined LS color bits for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be zeroed.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_FIELD                       (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_RANGE                       19:16
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_ARBITRARY                   _MK_ENUM_CONST(0)    // //       Output as 8-bit arbitrary data stream
+//       This may be used for compressed JPEG stream
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_PIXEL                       _MK_ENUM_CONST(1)    // //       Output the normal 1 pixel/clock. Undefined 
+//       LS color bits for RGB_666, RGB_565, RGB_555,
+//       and RGB_444, will be zeroed.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_PIXEL_REP                   _MK_ENUM_CONST(2)    // //       Same as PIXEL except MS color bits, for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be 
+//       replicated to their undefined LS bits.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_STORE                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser A Embedded Data Options 
+//  This specifies how to deal with embedded
+//  data within the specified input stream
+//  assuming that the CSI_PPA_DATA_TYPE is not
+//  embedded data and assuming that embedded
+//  data is not already processed by other
+//  CSI pixel stream processor.       output embedded data as 8-bpp arbitrary
+//       data stream.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SHIFT                       _MK_SHIFT_CONST(20)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_FIELD                       (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_RANGE                       21:20
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_DISCARD                     _MK_ENUM_CONST(0)    // //       discard (throw away) embedded data
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_EMBEDDED                    _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Pad Short Line
+//  This specifies how to deal with shorter than
+//  expected line (the number of bytes received
+//  is less than the specified word count)       short line is not padded (will output
+//       less pixels than expected).
+//       This option is not recommended and may
+//       cause other modules that receives CSI
+//       output stream to hang up.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SHIFT                      _MK_SHIFT_CONST(24)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_RANGE                      25:24
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_WOFFSET                    0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_PAD0S                      _MK_ENUM_CONST(0)    // //       short line is padded by pixel of zeros
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_PAD1S                      _MK_ENUM_CONST(1)    // //       short line is padded by pixel of ones
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_NOPAD                      _MK_ENUM_CONST(2)
+
+// CSI Pixel Parser A Packet Header Error Correction Enable
+//  This parameter specifies whether single bit
+//  errors in the packet header will be
+//  automatically corrected, or not.    Single bit errors in the header will not
+//    be corrected. Header ECC check will still
+//    set header ECC status bits and the packet
+//    will be processed by Pixel Parser A. DISABLE
+//    should not be used when processing interleaved
+//    streams (Same stream going to both PPA and PPB).
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SHIFT                    _MK_SHIFT_CONST(27)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_RANGE                    27:27
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_WOFFSET                  0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_ENABLE                   _MK_ENUM_CONST(0)    // //    Single bit errors in the header will be
+//    automatically corrected.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_DISABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Pad Frame
+//  This specifies how to deal with frames that are
+//  shorter (fewer lines) that expected. Short frames
+//  are usually caused by line packets being dropped
+//  because of packet errors. Expected frame height is
+//  specified in PPA_EXP_FRAME_HEIGHT. To do padding the
+//  value in CSI_PPA_WORD_COUNT needs to be set to the
+//  number of input bytes in each line's payload.  Short frames will not be padded out.   
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SHIFT                   _MK_SHIFT_CONST(28)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_FIELD                   (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_RANGE                   29:28
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_PAD0S                   _MK_ENUM_CONST(0)    // //  Lines of all zeros will be used to pad out frames
+//  that are shorter than expected height. 
+//  PPA_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD0S.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_PAD1S                   _MK_ENUM_CONST(1)    // //  Lines of all ones will be used to pad out frames
+//  that are shorter than expected height.      
+//  PPA_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD1S.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_NOPAD                   _MK_ENUM_CONST(2)
+
+
+// Register CSI_PIXEL_STREAM_A_CONTROL1_0  // CSI Pixel Stream A Control 1
+#define CSI_PIXEL_STREAM_A_CONTROL1_0                   _MK_ADDR_CONST(0x207)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+// CSI Pixel Parser A Top Field Frame
+//  This parameter specifies the frame number for 
+//  top field detection for interlaced input video
+//  stream. Top Field is indicated when each of the
+//  least significant four bits of the frame number
+//  that has a one in its mask bit matches the 
+//  corresponding bit in this parameter. In other
+//  words, Top Field is detected when the bitwise
+//  AND of  
+// ~(CSI_PPA_TOP_FIELD_FRAME ^ <frame number>) & CSI_PPA_TOP_FIELD_FRAME_MASK
+//  is one. Frame Number is taken from the WC field
+//  of the Frame Start short packet.
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_RANGE                     3:0
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser A Top Field Frame Mask
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_FIELD                        (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_RANGE                        7:4
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_A_WORD_COUNT_0  // CSI Pixel Stream A Word Count
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0                 _MK_ADDR_CONST(0x208)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_WORD_COUNT                      0x1
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+// CSI Pixel Parser A Word Count
+//  This parameter specifies the number of
+//  bytes per line/packet in the case where
+//  Word Count field in packet header is not
+//  used or where packet header is not sent.
+//  This count does not includes the additional
+//  2 bytes of CRC checksum if data CRC check
+//  is enabled. 
+//  When the input stream comes from a CSI camera
+//  port, this parameter must be programmed when 
+//  CSI_PPA_PAD_SHORT_LINE is set to either PAD0S
+//  or PAD1S, no matter whether CSI_PPA_WORD_COUNT_SELECT
+//  is set to REGISTER or HEADER.
+//  When the input stream comes from the host path
+//  or from the VIP path, and the data mode is
+//  PAYLOAD_ONLY, this count must be programmed.
+// Given a line width of N pixels, the programming 
+//  value of this parameters is as follows
+//  --------------------------------------
+//  data format            value
+//  --------------------------------------
+//  YUV420_8               N bytes
+//  YUV420_10              N/4*5 bytes
+//  LEG_YUV420_8           N/2*3 bytes
+//  YUV422_8               N*2 bytes
+//  YUV422_10              N/2*5 bytes
+//  RGB888                 N*3 bytes 
+//  RGB666                 N/4*9 bytes                 
+//  RGB565                 N*2 bytes
+//  RGB555                 N*2 bytes 
+//  RGB444                 N*2 bytes 
+//  RAW6                   N/4*3 bytes
+//  RAW7                   N/8*7 bytes
+//  RAW8                   N bytes 
+//  RAW10                  N/4*5 bytes
+//  RAW12                  N/2*3 bytes
+//  RAW14                  N/4*7 bytes
+//  ---------------------------------------
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SHIFT)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_RANGE                        15:0
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_A_GAP_0  // CSI Pixel Stream A Gap
+#define CSI_PIXEL_STREAM_A_GAP_0                        _MK_ADDR_CONST(0x209)
+#define CSI_PIXEL_STREAM_A_GAP_0_WORD_COUNT                     0x1
+#define CSI_PIXEL_STREAM_A_GAP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Minium number of viclk cycles from end of 
+// previous line (Video_control = EL_DATA) to start
+// of next line (Video_control = SL).
+// This parameter is to ensure that minimum H-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the line gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_FIELD                 (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_RANGE                 15:0
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minium number of viclk cycles from end of 
+// frame (Video_control = EF) to start of next
+// frame (Video_control = SF).
+// This parameter is to ensure that minimum V-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the frame gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_RANGE                        31:16
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_PPA_COMMAND_0  // CSI Pixel Parser A Command
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0                  _MK_ADDR_CONST(0x20a)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_WORD_COUNT                       0x1
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_RESET_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_READ_MASK                        _MK_MASK_CONST(0xff17)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_WRITE_MASK                       _MK_MASK_CONST(0xff17)
+// CSI Pixel Parser A Enable
+//  This parameter controls CSI Pixel Parser A
+//  to start or stop receiving data.       reset (disable immediately)
+//  Enabling the pixel Parser does not enable 
+//  the corresponding input source to receive 
+//  data. If Pixel parser is enabled later than
+//  the  corresponding input source, csi will keep
+//  on rejecting incoming stream, till it encounters
+//  a valid SF. 
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_FIELD                     (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_RANGE                     1:0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_NOP                       _MK_ENUM_CONST(0)    // //       no operation
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_ENABLE                    _MK_ENUM_CONST(1)    // //       enable at the next frame start as
+//       specified by the CSI Start Marker
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_DISABLE                   _MK_ENUM_CONST(2)    // //       disable after current frame end and before
+//       next frame start.
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_RST                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser A Single Shot Mode SW should Clear it along with disabling the 
+// CSI_PPA_ENABLE, once a frame is captured
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SHIFT                        _MK_SHIFT_CONST(2)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_RANGE                        2:2
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_DISABLE                      _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_ENABLE                       _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A VSYNC Start Marker  start of frame is indicated when VSYNC signal 
+//  is received. When the input stream is from the
+//  VIP path and the data mode is PACKET, then this
+//  field may be programmed to VSYNC.
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SHIFT                 _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_FIELD                 (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_RANGE                 4:4
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_FSPKT                 _MK_ENUM_CONST(0)    // //  Start of frame is indicated when a Frame
+//  Start short packet is received with a frame
+//  number whose least significant four bits are
+//  greater than, or equal to, 
+//  CSI_PPA_START_MARKER_FRAME_MIN and less than,
+//  or equal to, CSI_PPA_START_MARKER_FRAME_MAX.
+//  When the input stream is from a CSI port, or 
+//  from the host path, or from the VIP path and 
+//  the data mode is PAYLOAD_ONLY, then this field
+//  may be programmed to FSPKT.
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_VSYNC                 _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Start Marker Minimum
+// Start Frame is indicated when Max condition below
+// is met and the least significant four bits of the
+// frame number are greater than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_RANGE                     11:8
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser A Start Marker Maximum
+// Start Frame is indicated when Min condition above
+// is met and the least significant four bits of the
+// frame number are less than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SHIFT                     _MK_SHIFT_CONST(12)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_RANGE                     15:12
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 523 [0x20b] 
+
+// Reserved address 524 [0x20c] 
+
+// Reserved address 525 [0x20d] 
+
+// Reserved address 526 [0x20e] 
+
+// Register CSI_INPUT_STREAM_B_CONTROL_0  // CSI Input Stream B Control
+#define CSI_INPUT_STREAM_B_CONTROL_0                    _MK_ADDR_CONST(0x20f)
+#define CSI_INPUT_STREAM_B_CONTROL_0_WORD_COUNT                         0x1
+#define CSI_INPUT_STREAM_B_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x3f0000)
+#define CSI_INPUT_STREAM_B_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x7f0013)
+#define CSI_INPUT_STREAM_B_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x7f0013)
+#define CSI_INPUT_STREAM_B_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x7f0013)
+// CSI-B Data Lane
+//   0= 1 data lane
+//   1= 2 data lanes (not supported on SC17 & SC25)
+//   2= 3 data lanes (not supported on SC17 & SC25)
+//   3= 4 data lanes (not supported on SC17 & SC25)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SHIFT)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_RANGE                      1:0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_WOFFSET                    0x0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Enables skip packet threshold feature. Skip packet feature is enabled.
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT                   _MK_SHIFT_CONST(4)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_RANGE                   4:4
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_WOFFSET                 0x0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_DISABLE                 _MK_ENUM_CONST(0)    // // Skip packet feature is disabled.     
+
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI-B Skip Packet Threshold
+//  This value is compared against the internal
+//  FIFO that buffer the input streams. A packet
+//  will be skipped (discarded) if the pixel
+//  stream processor is busy (probably due to
+//  padding process of a short line) and the
+//  number of entries in the internal FIFO
+//  exceeds this threshold value. Note that
+//  each entry in the internal FIFO buffer is
+//  four bytes.
+//  To turn off this feature, set the value
+//  to its maximum value (all ones).
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_FIELD                  (_MK_MASK_CONST(0x7f) << CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SHIFT)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_RANGE                  22:16
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_WOFFSET                        0x0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x3f)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 528 [0x210] 
+
+// Register CSI_PIXEL_STREAM_B_CONTROL0_0  // CSI Pixel Stream A Control 0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0                   _MK_ADDR_CONST(0x211)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_RESET_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_READ_MASK                         _MK_MASK_CONST(0x3b3ffff7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_WRITE_MASK                        _MK_MASK_CONST(0x3b3ffff7)
+// CSI Pixel Parser B Stream Source   Host
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_FIELD                       (_MK_MASK_CONST(0x7) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_RANGE                       2:0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_CSI_A                       _MK_ENUM_CONST(0)    // //   CSI Interface A
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_CSI_B                       _MK_ENUM_CONST(1)    // //   CSI Interface B
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_VI_PORT                     _MK_ENUM_CONST(6)    // //   VI port
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_HOST                        _MK_ENUM_CONST(7)
+
+// CSI Pixel Parser B Packet Header processing
+//  This specifies whether packet header is
+//  sent in the beginning of packet or not.      Packet header is sent.
+//      This setting should be used if the
+//      stream source is CSI Interface A or B.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SHIFT                       _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_RANGE                       4:4
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_NOT_SENT                    _MK_ENUM_CONST(0)    // //      Packet header is not sent.
+//      This setting should not be used if the
+//      stream source is CSI Interface A or B.
+//      Unless CSI-A, or CSI-B, is operating in a
+//      stream capture debug mode.
+//      In this case, CSI_PPB_DATA_TYPE specifies
+//      the stream data format and the number
+//      of bytes per line/packet is
+//      specified by CSI_PPB_WORD_COUNT.
+//      This implies that a packet footer
+//      is also not sent.  In this case, no 
+//      packet footer CRC check should be performed.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SENT                        _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Data Identifier (DI) byte processing
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      Enabled  - Data Identifier byte in
+//      packet header should be compared against
+//      the CSI_PPB_DATA_TYPE and the
+//      CSI_PPB_VIRTUAL_CHANNEL_ID.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SHIFT                     _MK_SHIFT_CONST(5)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_FIELD                     (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_RANGE                     5:5
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_DISABLED                  _MK_ENUM_CONST(0)    // //      Disabled - Data Identifier byte in
+//      packet header should be ignored
+//      (not checked against CSI_PPB_DATA_TYPE
+//      and against CSI_PPB_VIRTUAL_CHANNEL_ID).
+//      In this case, CSI_PPB_DATA_TYPE specifies
+//      the stream data format.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_ENABLED                   _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Word Count Select
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      The number of bytes per line is to be
+//      extracted from Word Count field in the
+//      packet header. Note that if the serial
+//      link is not error free, programming this
+//      bit to HEADER may be dangerous because 
+//      the word count information in the header
+//      may be corrupted. 
+//
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_RANGE                   6:6
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_REGISTER                        _MK_ENUM_CONST(0)    // //      Word Count in packet header is ignored
+//      and the number of bytes per line/packet
+//      is specified by CSI_PPB_WORD_COUNT. Payload
+//      CRC check will not be valid if the word
+//      count in CSI_PPB_WORD_COUNT is different 
+//      than the count in the packet header.
+//      It is recommended to always program
+//      this bit to REGISTER and always program
+//      CSI_PPB_WORD_COUNT.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_HEADER                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Data CRC Check
+//  This parameter specifies whether the last
+//  2 bytes of packet should be treated as
+//  CRC checksum and used to perform CRC check
+//  on the payload data. Note that in case there
+//  are 2 bytes of data CRC at the end of the
+//  packet, the packet word count does not
+//  include the CRC bytes.      Data CRC Check is enabled.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SHIFT                   _MK_SHIFT_CONST(7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_RANGE                   7:7
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_DISABLE                 _MK_ENUM_CONST(0)    // //      Data CRC Check is disabled regardless
+//      of whether there are CRC checksum at
+//      the end of the packet.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Data Type  This is CSI compatible data type as defined
+//  in CSI specification. If the source stream
+//  contains packet headers this value can be compared
+//  to the CSI Data Type value in the 6 LSB of the
+//  CSI Data Identifier (DI) byte. If the source stream
+//  doesn't contain packet headers, or CSI_PPB_DATA_IDENTIFIER
+//  is DISABLED, this value will be used to determine how
+//  the stream will be converted to pixels.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SHIFT                   _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_FIELD                   (_MK_MASK_CONST(0x3f) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RANGE                   13:8
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420_8                        _MK_ENUM_CONST(24)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420_10                       _MK_ENUM_CONST(25)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_LEG_YUV420_8                    _MK_ENUM_CONST(26)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420CSPS_8                    _MK_ENUM_CONST(28)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420CSPS_10                   _MK_ENUM_CONST(29)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV422_8                        _MK_ENUM_CONST(30)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV422_10                       _MK_ENUM_CONST(31)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB444                  _MK_ENUM_CONST(32)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB555                  _MK_ENUM_CONST(33)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB565                  _MK_ENUM_CONST(34)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB666                  _MK_ENUM_CONST(35)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB888                  _MK_ENUM_CONST(36)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW6                    _MK_ENUM_CONST(40)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW7                    _MK_ENUM_CONST(41)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW8                    _MK_ENUM_CONST(42)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW10                   _MK_ENUM_CONST(43)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW12                   _MK_ENUM_CONST(44)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW14                   _MK_ENUM_CONST(45)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT1                 _MK_ENUM_CONST(48)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT2                 _MK_ENUM_CONST(49)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT3                 _MK_ENUM_CONST(50)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT4                 _MK_ENUM_CONST(51)
+
+// CSI Pixel Parser B Virtual Channel Identifier  
+//  This is CSI compatible virtual channel
+//  identifier as defined in CSI specification.
+//  If the source stream contains packet headers
+//  and CSI_PPB_DATA_IDENTIFIER is ENABLED this
+//  value will be compared to the CSI Virtual
+//  Channel Identifier value in the 2 MSB of the
+//  CSI Data Identifier (DI) byte. This value will
+//  be ignored if the source stream doesn't contain
+//  packet headers, or CSI_PPB_DATA_IDENTIFIER is 
+//  DISABLED, then this value will be ignored.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SHIFT                  _MK_SHIFT_CONST(14)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_FIELD                  (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_RANGE                  15:14
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_ONE                    _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_TWO                    _MK_ENUM_CONST(1)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_THREE                  _MK_ENUM_CONST(2)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_FOUR                   _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser B Output Format Options
+//  This parameter specifies output data format.       Output for storing RAW data to memory through
+//       ISP. Undefined LS color bits for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be zeroed.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_FIELD                       (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_RANGE                       19:16
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_ARBITRARY                   _MK_ENUM_CONST(0)    // //       Output as 8-bit arbitrary data stream
+//       This may be used for compressed JPEG stream
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_PIXEL                       _MK_ENUM_CONST(1)    // //       Output the normal 1 pixel/clock. Undefined 
+//       LS color bits for RGB_666, RGB_565, RGB_555,
+//       and RGB_444, will be zeroed.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_PIXEL_REP                   _MK_ENUM_CONST(2)    // //       Same as PIXEL except MS color bits, for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be 
+//       replicated to their undefined LS bits.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_STORE                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser B Embedded Data Options 
+//  This specifies how to deal with embedded
+//  data within the specified input stream
+//  assuming that the CSI_PPB_DATA_TYPE is not
+//  embedded data and assuming that embedded
+//  data is not already processed by other
+//  CSI pixel stream processor.       output embedded data as 8-bpp arbitrary
+//       data stream.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SHIFT                       _MK_SHIFT_CONST(20)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_FIELD                       (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_RANGE                       21:20
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_DISCARD                     _MK_ENUM_CONST(0)    // //       discard (throw away) embedded data
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_EMBEDDED                    _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Pad Short Line
+//  This specifies how to deal with shorter than
+//  expected line (the number of bytes received
+//  is less than the specified word count)       short line is not padded (will output
+//       less pixels than expected).
+//       This option is not recommended and may
+//       cause other modules that receives CSI
+//       output stream to hang up.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SHIFT                      _MK_SHIFT_CONST(24)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_RANGE                      25:24
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_WOFFSET                    0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_PAD0S                      _MK_ENUM_CONST(0)    // //       short line is padded by pixel of zeros
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_PAD1S                      _MK_ENUM_CONST(1)    // //       short line is padded by pixel of ones
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_NOPAD                      _MK_ENUM_CONST(2)
+
+// CSI Pixel Parser B Packet Header Error Correction Enable
+//  This parameter specifies whether single bit
+//  errors in the packet header will be
+//  automatically corrected, or not.    Single bit errors in the header will not
+//    be corrected. Header ECC check will still
+//    set header ECC status bits and the packet
+//    will be processed by Pixel Parser B. DISABLE
+//    should not be used when processing interleaved
+//    streams (Same stream going to both PPA and PPB).
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SHIFT                    _MK_SHIFT_CONST(27)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_RANGE                    27:27
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_WOFFSET                  0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_ENABLE                   _MK_ENUM_CONST(0)    // //    Single bit errors in the header will be
+//    automatically corrected.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_DISABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Pad Frame
+//  This specifies how to deal with frames that are
+//  shorter (fewer lines) that expected. Short frames
+//  are usually caused by line packets being dropped
+//  because of packet errors. Expected frame height is
+//  specified in PPB_EXP_FRAME_HEIGHT. To do padding the
+//  value in CSI_PPB_WORD_COUNT needs to be set to the
+//  number of input bytes in each lines payload.  Short frames will not be padded out.   
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SHIFT                   _MK_SHIFT_CONST(28)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_FIELD                   (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_RANGE                   29:28
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_PAD0S                   _MK_ENUM_CONST(0)    // //  Lines of all zeros will be used to pad out frames
+//  that are shorter than expected height.   
+//  PPB_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD0S.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_PAD1S                   _MK_ENUM_CONST(1)    // //  Lines of all ones will be used to pad out frames
+//  that are shorter than expected height.      
+//  PPB_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD1S.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_NOPAD                   _MK_ENUM_CONST(2)
+
+
+// Register CSI_PIXEL_STREAM_B_CONTROL1_0  // CSI Pixel Stream B Control 1
+#define CSI_PIXEL_STREAM_B_CONTROL1_0                   _MK_ADDR_CONST(0x212)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+// CSI Pixel Parser B Top Field Frame
+//  This parameter specifies the frame number for 
+//  top field detection for interlaced input video
+//  stream. Top Field is indicated when each of the
+//  least significant four bits of the frame number
+//  that has a one in its mask bit matches the 
+//  corresponding bit in this parameter. In other
+//  words, Top Field is detected when the bitwise
+//  AND of  
+// ~(CSI_PPB_TOP_FIELD_FRAME ^ <frame number>) & CSI_PPB_TOP_FIELD_FRAME_MASK
+//  is one. Frame Number is taken from the WC field
+//  of the Frame Start short packet.
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_RANGE                     3:0
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser B Top Field Frame Mask
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_FIELD                        (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_RANGE                        7:4
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_B_WORD_COUNT_0  // CSI Pixel Stream A Word Count
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0                 _MK_ADDR_CONST(0x213)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_WORD_COUNT                      0x1
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+// CSI Pixel Parser B Word Count
+//  This parameter specifies the number of
+//  bytes per line/packet in the case where
+//  Word Count field in packet header is not
+//  used or where packet header is not sent.
+//  This count does not includes the additional
+//  2 bytes of CRC checksum if data CRC check
+//  is enabled.
+//  When the input stream comes from a CSI camera
+//  port, this parameter must be programmed when 
+//  CSI_PPB_PAD_SHORT_LINE is set to either PAD0S
+//  or PAD1S, no matter whether CSI_PPB_WORD_COUNT_SELECT
+//  is set to REGISTER or HEADER.
+//  When the input stream comes from the host path
+//  or from the VIP path, and the data mode is
+//  PAYLOAD_ONLY, this count must be programmed.
+// Given a line width of N pixels, the programming 
+//  value of this parameters is as follows
+//  --------------------------------------
+//  data format            value
+//  --------------------------------------
+//  YUV420_8               N bytes
+//  YUV420_10              N/4*5 bytes
+//  LEG_YUV420_8           N/2*3 bytes
+//  YUV422_8               N*2 bytes
+//  YUV422_10              N/2*5 bytes
+//  RGB888                 N*3 bytes 
+//  RGB666                 N/4*9 bytes                 
+//  RGB565                 N*2 bytes
+//  RGB555                 N*2 bytes 
+//  RGB444                 N*2 bytes 
+//  RAW6                   N/4*3 bytes
+//  RAW7                   N/8*7 bytes
+//  RAW8                   N bytes 
+//  RAW10                  N/4*5 bytes
+//  RAW12                  N/2*3 bytes
+//  RAW14                  N/4*7 bytes
+//  ---------------------------------------
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SHIFT)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_RANGE                        15:0
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_B_GAP_0  // CSI Pixel Stream B Gap
+#define CSI_PIXEL_STREAM_B_GAP_0                        _MK_ADDR_CONST(0x214)
+#define CSI_PIXEL_STREAM_B_GAP_0_WORD_COUNT                     0x1
+#define CSI_PIXEL_STREAM_B_GAP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Minium number of viclk cycles from end of 
+// previous line (Video_control = EL_DATA) to start
+// of next line (Video_control = SL).
+// This parameter is to ensure that minimum H-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the line gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_FIELD                 (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_RANGE                 15:0
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minium number of viclk cycles from end of 
+// frame (Video_control = EF) to start of next
+// frame (Video_control = SF).
+// This parameter is to ensure that minimum V-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the frame gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_RANGE                        31:16
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_PPB_COMMAND_0  // CSI Pixel Parser B Command
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0                  _MK_ADDR_CONST(0x215)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_WORD_COUNT                       0x1
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_RESET_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_READ_MASK                        _MK_MASK_CONST(0xff17)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_WRITE_MASK                       _MK_MASK_CONST(0xff17)
+// CSI Pixel Parser B Enable
+//  This parameter controls CSI Pixel Parser B
+//  to start or stop receiving data.       reset (disable immediately)
+//  Enabling the pixel Parser does not enable 
+//  the corresponding input source to receive 
+//  data. If Pixel parser is enabled later than
+//  the  corresponding input source, csi will keep
+//  on rejecting incoming stream, till it encounters
+//  a valid SF.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_FIELD                     (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_RANGE                     1:0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_NOP                       _MK_ENUM_CONST(0)    // //       no operation
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_ENABLE                    _MK_ENUM_CONST(1)    // //       enable at the next frame start as
+//       specified by the CSI Start Marker
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_DISABLE                   _MK_ENUM_CONST(2)    // //       disable after current frame end and before
+//       next frame start.
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_RST                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser B Single Shot Mode SW should Clear it alongwith disabling the 
+// CSI_PPB_ENABLE, once a frame is captured
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SHIFT                        _MK_SHIFT_CONST(2)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_RANGE                        2:2
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_DISABLE                      _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_ENABLE                       _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B VSYNC Start Marker  Start of frame is indicated when VSYNC signal 
+//  is received. When the input stream is from the
+//  VIP path and the data mode is PACKET, then this
+//  field may be programmed to VSYNC.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SHIFT                 _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_FIELD                 (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_RANGE                 4:4
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_FSPKT                 _MK_ENUM_CONST(0)    // //      Start of frame is indicated when a Frame
+//    Start short packet is received with a frame
+//    number who's least significant four bits are
+//    greater than, or equal to, 
+//    CSI_PPB_START_MARKER_FRAME_MIN and less than,
+//    or equal to, CSI_PPB_START_MARKER_FRAME_MAX.
+//  When the input stream is from a CSI port, or 
+//  from the host path, or from the VIP path and 
+//  the data mode is PAYLOAD_ONLY, then this field
+//  may be programmed to FSPKT.
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_VSYNC                 _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Start Marker Minimum
+// Start Frame is indicated when Max condition below
+// is met and the least significant four bits of the
+// frame number are greater than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_RANGE                     11:8
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser B Start Marker Maximum
+// Start Frame is indicated when Min condition above
+// is met and the least significant four bits of the
+// frame number are less than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SHIFT                     _MK_SHIFT_CONST(12)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_RANGE                     15:12
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 534 [0x216] 
+
+// Reserved address 535 [0x217] 
+
+// Reserved address 536 [0x218] 
+
+// Reserved address 537 [0x219] 
+
+// Register CSI_PHY_CIL_COMMAND_0  // CSI Phy and CIL Command
+#define CSI_PHY_CIL_COMMAND_0                   _MK_ADDR_CONST(0x21a)
+#define CSI_PHY_CIL_COMMAND_0_WORD_COUNT                        0x1
+#define CSI_PHY_CIL_COMMAND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_RESET_MASK                        _MK_MASK_CONST(0x30003)
+#define CSI_PHY_CIL_COMMAND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_READ_MASK                         _MK_MASK_CONST(0x30003)
+#define CSI_PHY_CIL_COMMAND_0_WRITE_MASK                        _MK_MASK_CONST(0x30003)
+// CSI A Phy and CIL Enable
+//  This parameter controls CSI A Phy and CIL
+//  receiver to start or stop receiving data.    disable (reset)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_FIELD                        (_MK_MASK_CONST(0x3) << CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SHIFT)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_RANGE                        1:0
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_WOFFSET                      0x0
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_NOP                  _MK_ENUM_CONST(0)    // //    no operation
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_ENABLE                       _MK_ENUM_CONST(1)    // //    enable
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_DISABLE                      _MK_ENUM_CONST(2)
+
+// CSI B Phy and CIL Enable
+//  This parameter controls CSI B Phy and CIL
+//  receiver to start or stop receiving data.    disable (reset)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_FIELD                        (_MK_MASK_CONST(0x3) << CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SHIFT)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_RANGE                        17:16
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_WOFFSET                      0x0
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_NOP                  _MK_ENUM_CONST(0)    // //    no operation
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_ENABLE                       _MK_ENUM_CONST(1)    // //    enable
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_DISABLE                      _MK_ENUM_CONST(2)
+
+
+// Register CSI_PHY_CILA_CONTROL0_0  // CSI-A Phy and CIL Control
+#define CSI_PHY_CILA_CONTROL0_0                 _MK_ADDR_CONST(0x21b)
+#define CSI_PHY_CILA_CONTROL0_0_WORD_COUNT                      0x1
+#define CSI_PHY_CILA_CONTROL0_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILA_CONTROL0_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILA_CONTROL0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILA_CONTROL0_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+// When moving from LP mode to High Speed (LP11->LP01->LP00),
+// this setting determines how many csicil clock cycles (72 MHz
+// lp clock cycles) to wait, after LP00, 
+// before starting to look at the data.
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_FIELD                   (_MK_MASK_CONST(0xf) << CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SHIFT)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_RANGE                   3:0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_WOFFSET                 0x0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_DEFAULT                 _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// The LP signals are sampled using csi_cil_clk.
+// Normally this happens on 2 clock edges assuming
+// the clock is running at least 50 Mhz.  If the
+// clock needs to run slower, then this bit can be
+// SET so that the sampling takes place on a single
+// edge (clock rate is 25 Mhz min).  This sampling
+// may not be as reliable so setting this bit is
+// not recommended.
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SHIFT)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_RANGE                        4:4
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_WOFFSET                      0x0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// The LP signals should sequence through LP11->LP01->LP00 state,
+// to indicate to CLOCK CIL about the mode switching to HS Rx mode.
+// In case Camera is enabled earlier than CIL , it is highly likely
+// that camera sends this control sequence sooner than cil can detect it.
+// Enabling this bit allows the CLOCK CIL to overlook the LP control sequence
+// and step in HS Rx mode directly looking at LP00 only.
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SHIFT                        _MK_SHIFT_CONST(5)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SHIFT)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_RANGE                        5:5
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_WOFFSET                      0x0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PHY_CILB_CONTROL0_0  // CSI-B Phy and CIL Control
+#define CSI_PHY_CILB_CONTROL0_0                 _MK_ADDR_CONST(0x21c)
+#define CSI_PHY_CILB_CONTROL0_0_WORD_COUNT                      0x1
+#define CSI_PHY_CILB_CONTROL0_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILB_CONTROL0_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILB_CONTROL0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILB_CONTROL0_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+// When moving from LP mode to High Speed (LP11->LP01->LP00),
+// this setting determines how many  csicil clock cycles (72 MHz
+// lp clock cycles) to wait, after LP00,
+// before starting to look at the data.
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_FIELD                   (_MK_MASK_CONST(0xf) << CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SHIFT)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_RANGE                   3:0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_WOFFSET                 0x0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_DEFAULT                 _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// see CILA_SINGLE_SAMPLE above
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SHIFT)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_RANGE                        4:4
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_WOFFSET                      0x0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// see CILA_BYPASS_LP_SEQ above
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SHIFT                        _MK_SHIFT_CONST(5)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SHIFT)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_RANGE                        5:5
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_WOFFSET                      0x0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 541 [0x21d] 
+
+// Register CSI_CSI_PIXEL_PARSER_STATUS_0  // Pixel Parser Status
+// These status bits are cleared to
+// zero when its bit position is written with one. For
+// example write 0x2 to CSI_PIXEL_PARSER_STATUS will 
+// clear only PPA_ILL_WD_CNT.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0                   _MK_ADDR_CONST(0x21e)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_WORD_COUNT                        0x1
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xcfffcfff)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Header Error Corrected, Set when a packet that was
+// processed by PPA has a single bit header error. This error
+// will be detected by the headers ECC, and corrected by
+// it if header error correction is enabled 
+// (CSI_A_HEADER_EC_ENABLE = 0). This flag will be set and 
+// the packet will be processed even if the error is not
+// corrected.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_RANGE                     0:0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Illegal Word Count, set when a line with a word count that
+// doesn't generate an integer number of pixels (Unused bytes
+// at the end of payload) is processed by PPA.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SHIFT                      _MK_SHIFT_CONST(1)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_RANGE                      1:1
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Short Line Processed, Set when a line with a payload that
+// is shorter than its packet header word count is processed
+// by PPA.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SHIFT                    _MK_SHIFT_CONST(2)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_RANGE                    2:2
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Short Line Packet Dropped, set when a in coming packet
+// gets dropped because the input FIFO level reaches
+// CSI_A_SKIP_PACKET_THRESHOLD when padding a short line.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SHIFT                  _MK_SHIFT_CONST(3)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_RANGE                  3:3
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PayLoad CRC Error, Set when a packet that was processed by
+// PPA had a payload CRC error.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SHIFT                      _MK_SHIFT_CONST(4)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_RANGE                      4:4
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FIFO Overflow, set when the fifo that is feeding packets
+// to PPA overflows.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SHIFT                       _MK_SHIFT_CONST(5)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_RANGE                       5:5
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Stream Error, set when the control output of PPA doesn't
+// follow the correct sequence. The correct sequence for CSI
+// is: SF -> (SL_DATA or EF), SL_DATA -> (DATA or EL_DATA),
+// DATA -> EL_DATA, EL_DATA -> (SL_DATA or EF), EF -> SF.
+// Stream Errors can be caused by receiving a corrupted
+// stream, or a CSI RTL bug.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SHIFT                  _MK_SHIFT_CONST(6)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_RANGE                  6:6
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPA receives a short frame. This bit gets
+// set even if CSI_PPA_PAD_FRAME specifies that short frames
+// are to be padded to the correct line length.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SHIFT                     _MK_SHIFT_CONST(7)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_RANGE                     7:7
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPA receives a SF when it is expecting an EF.
+// This happens when EF of the frame gets corrupted before arriving CSI.
+// CSI-PPA will insert a fake EF and the drop the current 
+// frame with Correct SF.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_RANGE                        8:8
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPA receives a request to output a line
+// that is not in the active part of the frame output. That
+// is after EF and before SF, or before start marker is found.
+// The interframe line will not be outputted by the Pixel 
+// Parser.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SHIFT                 _MK_SHIFT_CONST(9)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_RANGE                 9:9
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// PPA Spare Status bit. This bit will get set when Pixel Parser
+// A has a line timeout. Line timeout needs to be enabled by setting
+// PPA_ENABLE_LINE_TIMEOUT and programming PPA_MAX_CLOCKS for
+// the MAX clocks between lines.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(10)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_RANGE                  10:10
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PPA Spare Status bit.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(11)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_RANGE                  11:11
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when header parser A
+// parses a header with a multi bit error. This error will
+// be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(14)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_RANGE                     14:14
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when header parser B
+// parses a header with a multi bit error. This error will
+// be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.a multi bit error. This error will
+// be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(15)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_RANGE                     15:15
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Header Error Corrected, set when a packet that was
+// processed by PPB has a single bit header error. This error
+// will be detected by the headers ECC, and corrected by
+// it if header error correction is enabled 
+// (CSI_B_HEADER_EC_ENABLE = 0). This flag will be set and 
+// the packet will be processed even if the error is not
+// corrected.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_RANGE                     16:16
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Illegal Word Count, set when a line with a word count that
+// doesn't generate an integer number of pixels (Unused bytes
+// at the end of payload) is processed by PPB.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SHIFT                      _MK_SHIFT_CONST(17)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_RANGE                      17:17
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Short Line Processed, Set when a line with a payload that
+// is shorter than its packet header word count is processed
+// by PPB.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SHIFT                    _MK_SHIFT_CONST(18)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_RANGE                    18:18
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Short Line Packet Dropped, set when a in coming packet
+// gets dropped because the input FIFO level reaches
+// CSI_B_SKIP_PACKET_THRESHOLD when padding a short line.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SHIFT                  _MK_SHIFT_CONST(19)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_RANGE                  19:19
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PayLoad CRC Error, Set when a packet that was processed
+// by PPB had a payload CRC error.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SHIFT                      _MK_SHIFT_CONST(20)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_RANGE                      20:20
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FIFO Overflow, set when the fifo that is feeding packets
+// to PPB overflows.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SHIFT                       _MK_SHIFT_CONST(21)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_RANGE                       21:21
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Stream Error, set when the control output of PPB doesn't
+// follow the correct sequence. The correct sequence for CSI
+// is: SF -> (SL_DATA or EF), SL_DATA -> (DATA or EL_DATA),
+// DATA -> EL_DATA, EL_DATA -> (SL_DATA or EF), EF -> SF.
+// Stream Errors can be caused by receiving a corrupted
+// stream, or a CSI RTL bug.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SHIFT                  _MK_SHIFT_CONST(22)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_RANGE                  22:22
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPB receives a short frame. This bit gets
+// set even if CSI_PPB_PAD_FRAME specifies that short frames
+// are to be padded to the correct line length.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SHIFT                     _MK_SHIFT_CONST(23)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_RANGE                     23:23
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPB receives a SF when it is expecting an EF. 
+// This happens when EF of the frame gets corrupted before arriving CSI.
+// CSI-PPB will insert a fake EF and the drop the current 
+// frame with Correct SF.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SHIFT                        _MK_SHIFT_CONST(24)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_RANGE                        24:24
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPB receives a request to output a line
+// that is not in the active part of the frame output. That
+// is after EF and before SF, or before start marker is found.
+// The interframe line will not be outputted by the Pixel 
+// Parser.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SHIFT                 _MK_SHIFT_CONST(25)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_RANGE                 25:25
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// PPB Spare Status bit. This bit will get set when Pixel Parser
+// B has a line timeout. Line timeout needs to be enabled by setting
+// PPB_ENABLE_LINE_TIMEOUT and programming PPB_MAX_CLOCKS for
+// the MAX clocks between lines.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(26)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_RANGE                  26:26
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PPB Spare Status bit.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(27)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_RANGE                  27:27
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when the VI port header
+// parser parses a header with a multi bit error. This error
+// will be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(30)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_RANGE                     30:30
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when the Host port header
+// parser parses a header with a multi bit error. This error
+// will be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(31)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_RANGE                     31:31
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CSI_CIL_STATUS_0  // CSI Control and Interface Logic Status
+// These status bits are cleared to
+// zero when its bit position is written with one. For
+// example write 0x2 to CSI_CIL_STATUS will clear only
+// CILA_SOT_MB_ERR.
+#define CSI_CSI_CIL_STATUS_0                    _MK_ADDR_CONST(0x21f)
+#define CSI_CSI_CIL_STATUS_0_WORD_COUNT                         0x1
+#define CSI_CSI_CIL_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1ff81ff)
+#define CSI_CSI_CIL_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Start of Transmission Single Bit Error, set when CIL-A 
+// detects a single bit error in one of the 
+// packets Start of Transmission bytes. The packet will be
+// sent to the CSI-A for processing.
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_RANGE                      0:0
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Start of Transmission Multi Bit Error, set when CIL-A
+// detects a multi bit start of transmission byte error in
+// one of the packets SOT bytes. The packet will be discarded.
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SHIFT                      _MK_SHIFT_CONST(1)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_RANGE                      1:1
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Sync Escape Error, set when CIL-A detects that the wrong 
+// (non-multiple of 8) number of bits have been received for
+// an Escape Command, or Data Byte.
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SHIFT                    _MK_SHIFT_CONST(2)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_RANGE                    2:2
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Escape Mode Entry Error, set when CIL-A detects an escape
+// mode entry error. The Escape mode command byte will not be
+// received.
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SHIFT                   _MK_SHIFT_CONST(3)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_RANGE                   3:3
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_WOFFSET                 0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Control Error, set when CIL-A detects LP state 01 or 10
+// followed by a stop state (LP11) instead of transitioning
+// into the Escape mode or Turn Around mode (LP00).
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_RANGE                        4:4
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_WOFFSET                      0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Escape Mode Command Received, set when CIL-A receives an
+// Escape Mode Command byte. The Command Byte can be read 
+// from bits 7-0 of ESCAPE_MODE_COMMAND.
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SHIFT                     _MK_SHIFT_CONST(5)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_RANGE                     5:5
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_WOFFSET                   0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Escape Mode Data Received, set when CIL-A receives an
+// Escape Mode Data byte. The Data Byte can be read 
+// from bits 7-0 of ESCAPE_MODE_DATA. This status bit will
+// will also be cleared when CILA_ESC_CMD_REC is set.
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SHIFT                    _MK_SHIFT_CONST(6)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_RANGE                    6:6
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CILA Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(7)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_RANGE                  7:7
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// CILA Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(8)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_RANGE                  8:8
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// MIPI Auto Calibrate done, set when the auto calibrate 
+// sequence for MIPI pad bricks is done.
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SHIFT                   _MK_SHIFT_CONST(15)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_RANGE                   15:15
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_WOFFSET                 0x0
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Start of Transmission Single Bit Error, set when CIL-B
+// detects a single bit error in one of the packets start
+// of transmission bytes. The packet will be sent to CSI-B
+// for processing.
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SHIFT                      _MK_SHIFT_CONST(16)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_RANGE                      16:16
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Start of Transmission Multi Bit Error, set when CIL-B
+// detects a multi bit start of transmission byte error in
+// one of the packets SOT bytes. The packet will be discarded.
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SHIFT                      _MK_SHIFT_CONST(17)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_RANGE                      17:17
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Sync Escape Error, set when CIL-B detects that the wrong 
+// (non-multiple of 8) number of bits have been received for
+// an Escape Command, or Data Byte.
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SHIFT                    _MK_SHIFT_CONST(18)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_RANGE                    18:18
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Escape Mode Entry Error, set when CIL-B detects an Escape
+// Mode Entry Error. The Escape mode command byte will not be
+// received.
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SHIFT                   _MK_SHIFT_CONST(19)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_RANGE                   19:19
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_WOFFSET                 0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Control Error, set when CIL-B detects LP state 01 or 10
+// followed by a stop state (LP11) instead of transitioning
+// into the Escape mode or Turn Around mode (LP00)..
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SHIFT                        _MK_SHIFT_CONST(20)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_RANGE                        20:20
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_WOFFSET                      0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Escape Mode Command Received, set when CIL-B receives an
+// Escape Mode Command byte. The Command Byte can be read 
+// from bits 23-16 of ESCAPE_MODE_COMMAND.
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SHIFT                     _MK_SHIFT_CONST(21)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_RANGE                     21:21
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_WOFFSET                   0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Escape Mode Data Received, set when CIL-B receives an
+// Escape Mode Data byte. The Data Byte can be read 
+// from bits 23-16 of ESCAPE_MODE_DATA. This status bit will
+// will also be cleared when CILB_ESC_CMD_REC is set.
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SHIFT                    _MK_SHIFT_CONST(22)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_RANGE                    22:22
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CILB Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(23)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_RANGE                  23:23
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// CILB Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(24)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_RANGE                  24:24
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0  // CSI Pixel Parser Interrupt Mask
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0                   _MK_ADDR_CONST(0x220)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_WORD_COUNT                        0x1
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_RESET_MASK                        _MK_MASK_CONST(0xcfffcfff)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_READ_MASK                         _MK_MASK_CONST(0xcfffcfff)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_WRITE_MASK                        _MK_MASK_CONST(0xcfffcfff)
+// Interrupt Mask for PPA_HDR_ERR_COR. Generate an interrupt when PPA_HDR_ERR_COR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_RANGE                    0:0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_HDR_ERR_COR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_ILL_WD_CNT. Generate an interrupt when PPA_ILL_WD_CNT
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SHIFT                     _MK_SHIFT_CONST(1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_RANGE                     1:1
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_ILL_WD_CNT
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SL_PROCESSED. Generate an interrupt when PPA_SL_PROCESSED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_RANGE                   2:2
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SL_PROCESSED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SL_PKT_DROPPED. Generate an interrupt when PPA_SL_PKT_DROPPED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SHIFT                 _MK_SHIFT_CONST(3)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_RANGE                 3:3
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SL_PKT_DROPPED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_PL_CRC_ERR. Generate an interrupt when PPA_PL_CRC_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(4)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_RANGE                     4:4
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_PL_CRC_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_FIFO_OVRF. Generate an interrupt when PPA_FIFO_OVRF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SHIFT                      _MK_SHIFT_CONST(5)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_RANGE                      5:5
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_FIFO_OVRF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_STMERR. Generate an interrupt when PPA_STMERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SHIFT                 _MK_SHIFT_CONST(6)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_RANGE                 6:6
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_STMERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SHORT_FRAME. Generate an interrupt when PPA_SHORT_FRAME
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SHIFT                    _MK_SHIFT_CONST(7)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_RANGE                    7:7
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SHORT_FRAME
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_EXTRA_SF. Generate an interrupt when PPA_EXTRA_SF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_RANGE                       8:8
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_EXTRA_SF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_INTERFRAME_LINE. Generate an interrupt when PPA_INTERFRAME_LINE
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SHIFT                        _MK_SHIFT_CONST(9)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_RANGE                        9:9
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_DISABLED                     _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_INTERFRAME_LINE
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_ENABLED                      _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SPARE_STATUS_1. Generate an interrupt when PPA_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(10)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_RANGE                 10:10
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SPARE_STATUS_2. Generate an interrupt when PPA_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(11)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_RANGE                 11:11
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPA_UNC_HDR_ERR. Generate an interrupt when HPA_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(14)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_RANGE                    14:14
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPA_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPB_UNC_HDR_ERR. Generate an interrupt when HPB_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(15)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_RANGE                    15:15
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPB_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_HDR_ERR_COR. Generate an interrupt when PPB_HDR_ERR_COR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_RANGE                    16:16
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_HDR_ERR_COR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_ILL_WD_CNT. Generate an interrupt when PPB_ILL_WD_CNT
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SHIFT                     _MK_SHIFT_CONST(17)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_RANGE                     17:17
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_ILL_WD_CNT
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SL_PROCESSED. Generate an interrupt when PPB_SL_PROCESSED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SHIFT                   _MK_SHIFT_CONST(18)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_RANGE                   18:18
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SL_PROCESSED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SL_PKT_DROPPED. Generate an interrupt when PPB_SL_PKT_DROPPED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SHIFT                 _MK_SHIFT_CONST(19)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_RANGE                 19:19
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SL_PKT_DROPPED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_PL_CRC_ERR. Generate an interrupt when PPB_PL_CRC_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(20)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_RANGE                     20:20
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_PL_CRC_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_FIFO_OVRF. Generate an interrupt when PPB_FIFO_OVRF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SHIFT                      _MK_SHIFT_CONST(21)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_RANGE                      21:21
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_FIFO_OVRF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_STMERR. Generate an interrupt when PPB_STMERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SHIFT                 _MK_SHIFT_CONST(22)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_RANGE                 22:22
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_STMERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SHORT_FRAME. Generate an interrupt when PPB_SHORT_FRAME
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SHIFT                    _MK_SHIFT_CONST(23)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_RANGE                    23:23
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SHORT_FRAME
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_EXTRA_SF. Generate an interrupt when PPB_EXTRA_SF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SHIFT                       _MK_SHIFT_CONST(24)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_RANGE                       24:24
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_EXTRA_SF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_INTERFRAME_LINE. Generate an interrupt when PPB_INTERFRAME_LINE
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SHIFT                        _MK_SHIFT_CONST(25)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_RANGE                        25:25
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_DISABLED                     _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_INTERFRAME_LINE
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_ENABLED                      _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SPARE_STATUS_1. Generate an interrupt when PPB_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(26)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_RANGE                 26:26
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SPARE_STATUS_2. Generate an interrupt when PPB_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(27)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_RANGE                 27:27
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPV_UNC_HDR_ERR. Generate an interrupt when HPV_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(30)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_RANGE                    30:30
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPV_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPH_UNC_HDR_ERR. Generate an interrupt when HPH_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(31)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_RANGE                    31:31
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPH_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register CSI_CSI_CIL_INTERRUPT_MASK_0  // CSI Control and Interface Logic Interrupt Mask
+#define CSI_CSI_CIL_INTERRUPT_MASK_0                    _MK_ADDR_CONST(0x221)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_WORD_COUNT                         0x1
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_RESET_MASK                         _MK_MASK_CONST(0x1ff81ff)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_READ_MASK                  _MK_MASK_CONST(0x1ff81ff)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff81ff)
+// Interrupt Mask for CILA_SOT_SB_ERR. Generate an interrupt when CILA_SOT_SB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_RANGE                     0:0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SOT_SB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SOT_MB_ERR. Generate an interrupt when CILA_SOT_MB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_RANGE                     1:1
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SOT_MB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SYNC_ESC_ERR. Generate an interrupt when CILA_SYNC_ESC_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_RANGE                   2:2
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SYNC_ESC_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_ESC_ENTRY_ERR. Generate an interrupt when CILA_ESC_ENTRY_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SHIFT                  _MK_SHIFT_CONST(3)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_RANGE                  3:3
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_WOFFSET                        0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_ESC_ENTRY_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_CTRL_ERR. Generate an interrupt when CILA_CTRL_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(4)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_RANGE                       4:4
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_CTRL_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_ESC_CMD_REC. Generate an interrupt when CILA_ESC_CMD_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SHIFT                    _MK_SHIFT_CONST(5)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_RANGE                    5:5
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_ESC_CMD_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_ESC_DATA_REC. Generate an interrupt when CILA_ESC_DATA_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_RANGE                   6:6
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_ESC_DATA_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SPARE_STATUS_1. Generate an interrupt when CILA_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(7)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_RANGE                 7:7
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SPARE_STATUS_2. Generate an interrupt when CILA_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(8)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_RANGE                 8:8
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for MIPI_AUTO_CAL_DONE. Generate an interrupt when MIPI_AUTO_CAL_DONE
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SHIFT                  _MK_SHIFT_CONST(15)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_RANGE                  15:15
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_WOFFSET                        0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)    // // Don't generate an interrupt when MIPI_AUTO_CAL_DONE
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SOT_SB_ERR. Generate an interrupt when CILB_SOT_SB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_RANGE                     16:16
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SOT_SB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SOT_MB_ERR. Generate an interrupt when CILB_SOT_MB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(17)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_RANGE                     17:17
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SOT_MB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SYNC_ESC_ERR. Generate an interrupt when CILB_SYNC_ESC_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SHIFT                   _MK_SHIFT_CONST(18)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_RANGE                   18:18
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SYNC_ESC_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_ESC_ENTRY_ERR. Generate an interrupt when CILB_ESC_ENTRY_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SHIFT                  _MK_SHIFT_CONST(19)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_RANGE                  19:19
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_WOFFSET                        0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_ESC_ENTRY_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_CTRL_ERR. Generate an interrupt when CILB_CTRL_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(20)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_RANGE                       20:20
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_CTRL_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_ESC_CMD_REC. Generate an interrupt when CILB_ESC_CMD_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SHIFT                    _MK_SHIFT_CONST(21)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_RANGE                    21:21
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_ESC_CMD_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_ESC_DATA_REC. Generate an interrupt when CILB_ESC_DATA_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SHIFT                   _MK_SHIFT_CONST(22)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_RANGE                   22:22
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_ESC_DATA_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SPARE_STATUS_1. Generate an interrupt when CILB_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(23)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_RANGE                 23:23
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SPARE_STATUS_2. Generate an interrupt when CILB_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_RANGE                 24:24
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register CSI_CSI_READONLY_STATUS_0  // CSI Read Only Status, this register is used to return
+// CSI read only status.
+#define CSI_CSI_READONLY_STATUS_0                       _MK_ADDR_CONST(0x222)
+#define CSI_CSI_READONLY_STATUS_0_WORD_COUNT                    0x1
+#define CSI_CSI_READONLY_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define CSI_CSI_READONLY_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// One only when Pixel Parser A is capturing frame data.
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_RANGE                  0:0
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_WOFFSET                        0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// One only when Pixel Parser B is capturing frame data.
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SHIFT                  _MK_SHIFT_CONST(1)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_RANGE                  1:1
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_WOFFSET                        0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Reads back CSI's interrupt line. This is being used test
+// the CSI logic that generates interrupt.
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_RANGE                   2:2
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SHIFT                   _MK_SHIFT_CONST(3)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_RANGE                   3:3
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SHIFT                   _MK_SHIFT_CONST(4)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_RANGE                   4:4
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SHIFT                   _MK_SHIFT_CONST(5)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_RANGE                   5:5
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_RANGE                   6:6
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SHIFT                   _MK_SHIFT_CONST(7)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_RANGE                   7:7
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_ESCAPE_MODE_COMMAND_0  // Escape Mode Command, this register is used to receive
+// escape mode command bytes from CIL-A and CIL-B.
+#define CSI_ESCAPE_MODE_COMMAND_0                       _MK_ADDR_CONST(0x223)
+#define CSI_ESCAPE_MODE_COMMAND_0_WORD_COUNT                    0x1
+#define CSI_ESCAPE_MODE_COMMAND_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_READ_MASK                     _MK_MASK_CONST(0xff00ff)
+#define CSI_ESCAPE_MODE_COMMAND_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// CIL-A Escape Mode Command Byte, this is the 8 bit entry
+// command that was received, by CIL-A, during the last 
+// escape Mode sequence. CIL-A monitors Byte Lane 0, only,
+// for escape mode sequences. This command byte can only 
+// be  assummed to be valid when CILA_ESC_CMD_REC status
+// bit is set.
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_FIELD                       (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_RANGE                       7:0
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_WOFFSET                     0x0
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// CIL-B Escape Mode Command Byte, this is the 8 bit entry
+// command that was received, by CIL-B, during the last 
+// escape Mode sequence. This command byte can only be 
+// assummed to be valid when CILB_ESC_CMD_REC status bit
+// is set.
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_FIELD                       (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_RANGE                       23:16
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_WOFFSET                     0x0
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CSI_ESCAPE_MODE_DATA_0  // Escape Mode Data, this register is used to receive
+// escape mode data bytes from CIL-A and CIL-B.
+#define CSI_ESCAPE_MODE_DATA_0                  _MK_ADDR_CONST(0x224)
+#define CSI_ESCAPE_MODE_DATA_0_WORD_COUNT                       0x1
+#define CSI_ESCAPE_MODE_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_READ_MASK                        _MK_MASK_CONST(0xff00ff)
+#define CSI_ESCAPE_MODE_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// CIL-A Escape Mode Data Byte, when read this field returns
+// the last Escape Mode Data byte that was received by CIL-A.
+// Escape Mode Data bytes are the bytes that are received
+// in Escape Mode after receiving the Escape Mode Command.
+// These bytes can be used to implement MIPI's CSI Specs Low
+// Power Data Transmition. This field is only valid when 
+// the status bit, CILA_ESC_DATA_REC, is set, and will be
+// overwritten by the next Escape Mode data byte if not read
+// before the next byte come in.
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_FIELD                 (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_RANGE                 7:0
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_WOFFSET                       0x0
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// CIL-B Escape Mode Data Byte, when read this field returns
+// the last Escape Mode Data byte that was received by CIL-B.
+// Escape Mode Data bytes are the bytes that are received
+// in Escape Mode after receiving the Escape Mode Command.
+// These bytes can be used to implement MIPI's CSI Specs Low
+// Power Data Transmition. This field is only valid when 
+// the status bit, CILB_ESC_DATA_REC, is set, and will be
+// overwritten by the next Escape Mode data byte if not read
+// before the next byte come in.
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_FIELD                 (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_RANGE                 23:16
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_WOFFSET                       0x0
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILA_PAD_CONFIG0_0  // CIL-A Pad Configuration 0
+#define CSI_CILA_PAD_CONFIG0_0                  _MK_ADDR_CONST(0x225)
+#define CSI_CILA_PAD_CONFIG0_0_WORD_COUNT                       0x1
+#define CSI_CILA_PAD_CONFIG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_RESET_MASK                       _MK_MASK_CONST(0x77f1777f)
+#define CSI_CILA_PAD_CONFIG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_READ_MASK                        _MK_MASK_CONST(0x77f1777f)
+#define CSI_CILA_PAD_CONFIG0_0_WRITE_MASK                       _MK_MASK_CONST(0x77f1777f)
+// Power down for each data bit, including drivers,
+// receivers and contention detectors
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_FIELD                      (_MK_MASK_CONST(0x3) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_RANGE                      1:0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_WOFFSET                    0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Power down for clock bit, including drivers, 
+// receivers and contention detectors
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SHIFT                  _MK_SHIFT_CONST(2)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_RANGE                  2:2
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_WOFFSET                        0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// HS driver preemphasis enable,1= preemphasis enabled
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SHIFT                 _MK_SHIFT_CONST(3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_RANGE                 3:3
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clock bit input delay trimmer, each tap delays 20ps
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SHIFT                  _MK_SHIFT_CONST(4)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_FIELD                  (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_RANGE                  6:4
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_WOFFSET                        0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// bit 0 input delay trimmer, each tap delays 20ps
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_FIELD                    (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_RANGE                    10:8
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_WOFFSET                  0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// bit 1 input delay trimmer, each tap delays 20ps
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SHIFT                    _MK_SHIFT_CONST(12)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_FIELD                    (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_RANGE                    14:12
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_WOFFSET                  0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Increase bandwidth of differential receiver
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_RANGE                 16:16
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Driver pull up impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SHIFT                   _MK_SHIFT_CONST(20)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_RANGE                   21:20
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_WOFFSET                 0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Driver pull down impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SHIFT                   _MK_SHIFT_CONST(22)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_RANGE                   23:22
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_WOFFSET                 0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pull up slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_RANGE                 26:24
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Pull down slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SHIFT                 _MK_SHIFT_CONST(28)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_RANGE                 30:28
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILA_PAD_CONFIG1_0  // CIL-A Pad Configuration 4
+#define CSI_CILA_PAD_CONFIG1_0                  _MK_ADDR_CONST(0x226)
+#define CSI_CILA_PAD_CONFIG1_0_WORD_COUNT                       0x1
+#define CSI_CILA_PAD_CONFIG1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_CILA_PAD_CONFIG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CSI_CILA_PAD_CONFIG1_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Spare bits for CILA Config
+// PAD_CILA_SPARE[15] is being used to disable 
+// the CSI-A RTL code that blocks fifo pushs 
+// that are past the end of the line packet.
+// 0: disabled, 1: push blocking enabled
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_FIELD                     (_MK_MASK_CONST(0xffff) << CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SHIFT)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RANGE                     15:0
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_WOFFSET                   0x0
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Spare Read only bits for CILA Config
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_FIELD                  (_MK_MASK_CONST(0xffff) << CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SHIFT)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_RANGE                  31:16
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_WOFFSET                        0x0
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILB_PAD_CONFIG0_0  // CIL-B Pad Configuration 0
+#define CSI_CILB_PAD_CONFIG0_0                  _MK_ADDR_CONST(0x227)
+#define CSI_CILB_PAD_CONFIG0_0_WORD_COUNT                       0x1
+#define CSI_CILB_PAD_CONFIG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_RESET_MASK                       _MK_MASK_CONST(0x77f1077d)
+#define CSI_CILB_PAD_CONFIG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_READ_MASK                        _MK_MASK_CONST(0x77f1077d)
+#define CSI_CILB_PAD_CONFIG0_0_WRITE_MASK                       _MK_MASK_CONST(0x77f1077d)
+// Power down for each data bit, including drivers,
+// receivers and contention detectors
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_RANGE                      0:0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_WOFFSET                    0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Power down for clock bit, including drivers, 
+// receivers and contention detectors
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SHIFT                  _MK_SHIFT_CONST(2)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_RANGE                  2:2
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_WOFFSET                        0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// HS driver preemphasis enable,1= preemphasis enabled
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SHIFT                 _MK_SHIFT_CONST(3)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_RANGE                 3:3
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clock bit input delay trimmer, each tap delays 20ps
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SHIFT                  _MK_SHIFT_CONST(4)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_FIELD                  (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_RANGE                  6:4
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_WOFFSET                        0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// bit 0 input delay trimmer, each tap delays 20ps
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_FIELD                    (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_RANGE                    10:8
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_WOFFSET                  0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Increase bandwidth of differential receiver
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_RANGE                 16:16
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Driver pull up impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SHIFT                   _MK_SHIFT_CONST(20)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_RANGE                   21:20
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_WOFFSET                 0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Driver pull down impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SHIFT                   _MK_SHIFT_CONST(22)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_RANGE                   23:22
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_WOFFSET                 0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pull up slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_RANGE                 26:24
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Pull down slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SHIFT                 _MK_SHIFT_CONST(28)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_RANGE                 30:28
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILB_PAD_CONFIG1_0  // CIL-B Pad Configuration 4
+#define CSI_CILB_PAD_CONFIG1_0                  _MK_ADDR_CONST(0x228)
+#define CSI_CILB_PAD_CONFIG1_0_WORD_COUNT                       0x1
+#define CSI_CILB_PAD_CONFIG1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_CILB_PAD_CONFIG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CSI_CILB_PAD_CONFIG1_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Spare bits for CILB Config
+// PAD_CILB_SPARE[15] is being used to disable 
+// the CSI-B RTL code that blocks fifo pushs 
+// that are past the end of the line packet.
+// 0: disabled, 1: push blocking enabled
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_FIELD                     (_MK_MASK_CONST(0xffff) << CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SHIFT)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RANGE                     15:0
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_WOFFSET                   0x0
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Spare Read only bits for CILB Config
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_FIELD                  (_MK_MASK_CONST(0xffff) << CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SHIFT)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_RANGE                  31:16
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_WOFFSET                        0x0
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CIL_PAD_CONFIG0_0  // CIL Pad Configuration 0
+#define CSI_CIL_PAD_CONFIG0_0                   _MK_ADDR_CONST(0x229)
+#define CSI_CIL_PAD_CONFIG0_0_WORD_COUNT                        0x1
+#define CSI_CIL_PAD_CONFIG0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_RESET_MASK                        _MK_MASK_CONST(0xff73)
+#define CSI_CIL_PAD_CONFIG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_READ_MASK                         _MK_MASK_CONST(0xff73)
+#define CSI_CIL_PAD_CONFIG0_0_WRITE_MASK                        _MK_MASK_CONST(0xff73)
+// Bypass bang gap voltage reference
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_RANGE                     0:0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_WOFFSET                   0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Power down voltage regulator, 1=power down
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SHIFT                      _MK_SHIFT_CONST(1)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_RANGE                      1:1
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_WOFFSET                    0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VAUXP level adjustment
+// 00 -> no adjustment, default
+// 01 -> 105% 
+// 10 -> 110% 
+// 11 -> 115%
+// 100 -> no adjustment
+// 101 -> 95%
+// 110 -> 90%
+// 111 -> 85%
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_FIELD                        (_MK_MASK_CONST(0x7) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_RANGE                        6:4
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_WOFFSET                      0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Spare bit for CIL BIAS Config
+// PAD_CIL_SPARE[7] is used is being used to flush VI's
+// Y-FIFO when it is being use as a stream source for 
+// one of the Pixel Parsers. Setting PAD_CIL_SPARE[7]
+// to 1 will hold vi2csi_host_stall low. Which will
+// force VI's Y-FIFO to be purged. PAD_CIL_SPARE[7]
+// must be low for the pixel parser to receive source
+// data from VI's Y-FIFO. 
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_FIELD                       (_MK_MASK_CONST(0xff) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_RANGE                       15:8
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_WOFFSET                     0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILA_MIPI_CAL_CONFIG_0  // Calibration settings for CIL-A mipi pads
+#define CSI_CILA_MIPI_CAL_CONFIG_0                      _MK_ADDR_CONST(0x22a)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_WORD_COUNT                   0x1
+#define CSI_CILA_MIPI_CAL_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x2a000000)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0xff1f1f1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0xff1f1f1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x7f1f1f1f)
+// 2's complement offset for TERMADJ going to channel A
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_RANGE                       4:0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_WOFFSET                     0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPUADJ going to channel A
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_RANGE                       12:8
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_WOFFSET                     0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPDADJ going to channel A
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_RANGE                       20:16
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_WOFFSET                     0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Auto Cal calibration step prescale:
+// Set to 00 when calibration step should be 0.1 us
+// Set to 01 when calibration step should be 0.5 us
+// Set to 10 when calibration step should be 1.0 us
+// Set to 11 when calibration step should be 1.5 us
+// this will keep the mipi bias cal step between 0.1-1.5 usec
+// Default set for 1.0 us calibraiton step.
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SHIFT                      _MK_SHIFT_CONST(24)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_RANGE                      25:24
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_WOFFSET                    0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// The DRIVRY & TERMRY signals coming from MIPI Pads are
+// utilized by Calibration state machine for PAD Calibration.
+// The drivry/termry comes from a noisy analog source 
+// and it could have some glitches.
+// The filter in calibsm is sensitive to these noises.
+// If the calibration done status does not show up, we
+// can change the sensitivity of the filter through these bits.
+// Ideally this has to be programmed in a range from 10 to 15.
+// For the case when MIPI_CAL_PRESCALE = 2'b00, this needs to be
+// programmed between 2 to 5.
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SHIFT                     _MK_SHIFT_CONST(26)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_FIELD                     (_MK_MASK_CONST(0xf) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_RANGE                     29:26
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_WOFFSET                   0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_DEFAULT                   _MK_MASK_CONST(0xa)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// When 0 (normal operation), use the above registers
+// as an offset to the Calibration State machine setting
+// for channel A TERMADJ/HSPUADJ/HSPDADJ values to the 
+// Mipi Pads. When 1, use the register values above as
+// the actual value going to channel A TERMADJ/HSPUADJ/HSPDADJ
+// on the Mipi Pads.
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SHIFT                      _MK_SHIFT_CONST(30)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_RANGE                      30:30
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_WOFFSET                    0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Writting a one to this bit starts the Calibration State
+// machine.  This bit must be set even if both overrides
+// set in order to latch in the over ride value
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SHIFT                      _MK_SHIFT_CONST(31)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_RANGE                      31:31
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_WOFFSET                    0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILB_MIPI_CAL_CONFIG_0  // Calibration settings for CIL-B mipi pads
+#define CSI_CILB_MIPI_CAL_CONFIG_0                      _MK_ADDR_CONST(0x22b)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_WORD_COUNT                   0x1
+#define CSI_CILB_MIPI_CAL_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0x401f1f1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0x401f1f1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x401f1f1f)
+// 2's complement offset for TERMADJ going to channel B
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_RANGE                       4:0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_WOFFSET                     0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPUADJ going to channel B
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_RANGE                       12:8
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_WOFFSET                     0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPDADJ going to channel B
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_RANGE                       20:16
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_WOFFSET                     0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// When 0 (normal operation), use the above registers
+// as an offset to the Calibration State machine setting
+// for channel B TERMADJ/HSPUADJ/HSPDADJ values to the 
+// Mipi Pads. When 1, use the register values above as
+// the actual value going to channel B TERMADJ/HSPUADJ/HSPDADJ
+// on the Mipi Pads.
+// Writting a one to Bit 31 of CILA_MIPI_CAL_CONFIG 
+// (MIPI_CAL_STARTCAL) starts the Calibration State
+// machine.
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SHIFT                      _MK_SHIFT_CONST(30)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_RANGE                      30:30
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_WOFFSET                    0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CIL_MIPI_CAL_STATUS_0  // CIL MIPI Calibrate Status
+#define CSI_CIL_MIPI_CAL_STATUS_0                       _MK_ADDR_CONST(0x22c)
+#define CSI_CIL_MIPI_CAL_STATUS_0_WORD_COUNT                    0x1
+#define CSI_CIL_MIPI_CAL_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xff1)
+#define CSI_CIL_MIPI_CAL_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// One when auto calibrate is active.
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_RANGE                 0:0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_WOFFSET                       0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Termination code generated by MIPI auto Calibrate.
+// Valid only after auto calibrate sequence has 
+// completed (MIPI_CAL_ACTIVE == 0).
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_FIELD                        (_MK_MASK_CONST(0xf) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_RANGE                        7:4
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_WOFFSET                      0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Driver code generated by MIPI auto Calibrate.
+// Valid only after auto calibrate sequence has 
+// completed (MIPI_CAL_ACTIVE == 0).
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_FIELD                        (_MK_MASK_CONST(0xf) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_RANGE                        11:8
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_WOFFSET                      0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CLKEN_OVERRIDE_0  
+#define CSI_CLKEN_OVERRIDE_0                    _MK_ADDR_CONST(0x22d)
+#define CSI_CLKEN_OVERRIDE_0_WORD_COUNT                         0x1
+#define CSI_CLKEN_OVERRIDE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_RESET_MASK                         _MK_MASK_CONST(0x3fff)
+#define CSI_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_READ_MASK                  _MK_MASK_CONST(0x3fff)
+#define CSI_CLKEN_OVERRIDE_0_WRITE_MASK                         _MK_MASK_CONST(0x3fff)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_RANGE                        0:0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_WOFFSET                      0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_RANGE                    1:1
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SHIFT                     _MK_SHIFT_CONST(2)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_RANGE                     2:2
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_WOFFSET                   0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_INIT_ENUM                 CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_CLK_GATED                 _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_CLK_ALWAYS_ON                     _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SHIFT                     _MK_SHIFT_CONST(3)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_RANGE                     3:3
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_WOFFSET                   0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_INIT_ENUM                 CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_CLK_GATED                 _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_CLK_ALWAYS_ON                     _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SHIFT                     _MK_SHIFT_CONST(4)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_RANGE                     4:4
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_WOFFSET                   0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_INIT_ENUM                 CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_CLK_GATED                 _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_CLK_ALWAYS_ON                     _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(5)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_RANGE                    5:5
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(6)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_RANGE                    6:6
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(7)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_RANGE                    7:7
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_RANGE                    8:8
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(9)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_RANGE                    9:9
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(10)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_RANGE                    10:10
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SHIFT                   _MK_SHIFT_CONST(11)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_RANGE                   11:11
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_WOFFSET                 0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_INIT_ENUM                       CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_CLK_GATED                       _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_CLK_ALWAYS_ON                   _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SHIFT                   _MK_SHIFT_CONST(12)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_RANGE                   12:12
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_WOFFSET                 0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_INIT_ENUM                       CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_CLK_GATED                       _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_CLK_ALWAYS_ON                   _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(13)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_RANGE                    13:13
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+
+// Register CSI_DEBUG_CONTROL_0  // Debug Control
+#define CSI_DEBUG_CONTROL_0                     _MK_ADDR_CONST(0x22e)
+#define CSI_DEBUG_CONTROL_0_WORD_COUNT                  0x1
+#define CSI_DEBUG_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_DEBUG_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0xffffff7d)
+#define CSI_DEBUG_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x7f7f7f01)
+// Debug Enable Second level CSI Debug clock is enabled. Debug counters
+// 2, 1 & 0 are powered up.
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DEBUG_EN_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_RANGE                      0:0
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_DISABLED                   _MK_ENUM_CONST(0)    // // Debug counters 2, 1 & 0 are powered down. Second level
+// CSI Debug clock is disabled.
+
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_ENABLED                    _MK_ENUM_CONST(1)
+
+// When CSI-A is operating in a "Header Not Sent mode",
+// writting a 1 to this bit indicates start frame (SF)
+// or end frame (EF) control code. After the pixel parser 
+// is enabled, writing a 1 to this bit will start frame 
+// capture and send start frame (SF) control code. Writing
+// a 1 to this bit again will stop frame capture and send
+// end frame (EF) control code. "Header Not Sent mode" can 
+// be used as a debug mode to capture what the sensor
+// is sending without interpeting the packets. Writing a
+// 1 to this bit continually will generate SF and EF control
+// codes. Note that a wait for MISC_CSI_PPA_FRAME_END syncpt
+// is needed between an EF trigger for the current frame and 
+// an SF trigger for the next frame.
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_FIELD                   (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_RANGE                   2:2
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_WOFFSET                 0x0
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// When CSI-B is operating in a "Header Not Sent mode",
+// writting a 1 to this bit indicates start frame (SF)
+// or end frame (EF) control code. After the pixel parser 
+// is enabled, writing a 1 to this bit will start frame 
+// capture and send start frame (SF) control code. Writing
+// a 1 to this bit again will stop frame capture and send
+// end frame (EF) control code. "Header Not Sent mode" can 
+// be used as a debug mode to capture what the sensor
+// is sending without interpeting the packets. Writing a
+// 1 to this bit continually will generate SF and EF control
+// codes. Note that a wait for MISC_CSI_PPB_FRAME_END syncpt
+// is needed between an EF trigger for the current frame and 
+// an SF trigger for the next frame.
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SHIFT                   _MK_SHIFT_CONST(3)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_FIELD                   (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_RANGE                   3:3
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_WOFFSET                 0x0
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Clear Debug Counter 0, write a one to this bit to clear
+// debug counter 0 and dbg_cnt_rolled_0.
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SHIFT                 _MK_SHIFT_CONST(4)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_FIELD                 (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_RANGE                 4:4
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clear Debug Counter 1, write a one to this bit to clear
+// debug counter 1 and dbg_cnt_rolled_1.
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SHIFT                 _MK_SHIFT_CONST(5)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_FIELD                 (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_RANGE                 5:5
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clear Debug Counter 2, write a one to this bit to clear
+// debug counter 2 and dbg_cnt_rolled_2.
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SHIFT                 _MK_SHIFT_CONST(6)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_FIELD                 (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_RANGE                 6:6
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Debug Count Select 0, this field selects what will be 
+// counted by debug counter 0.
+// Encodings 00 to 31 selects the set signal for one of 
+// the CSI_PIXEL_PARSER_STATUS register bits. In this case
+// the select encoding of this field is the same as the
+// bit position, in CSI_PIXEL_PARSER_STATUS, of the status
+// bit who's set signal will be used to increment DBG_CNT_0.
+// Encodings 32 to 63 selects the set signal for one of 
+// the CSI_CIL_STATUS status bits. The least significant 
+// 5 bits of this select field give the bit position, in
+// CSI_CIL_STATUS, of the status bit whos set signal pluses
+// will be counted by dbg_cnt_0. Selections for encodings 64
+// to 127 are given below: 
+// 64 - PPA Line packets processed
+// 65 - PPA short packets processed
+// 66 - Total packets processed by PPA
+// 67 - PPA Frame Starts Outputted
+// 68 - PPA Frame Ends Outputted
+// 69 - Reserved encoding
+// 70 - PPB Line packets processed
+// 71 - PPB short packets processed
+// 72 - Total packets processed by PPB
+// 73 - PPB Frame Starts Outputted
+// 74 - PPB Frame Ends Outputted
+// 75 - Reserved encoding
+// 76 - HPA Headers Parsed
+// 77 - HPA Headers Parsed with no ECC Errors
+// 78 - HPB Headers Parsed
+// 79 - HPB Headers Parsed with no ECC Errors
+// 80 - HPV Headers Parsed
+// 81 - HPV Headers Parsed with no ECC Errors
+// 82 - HPH Headers Parsed
+// 83 - HPH Headers Parsed with no ECC Errors
+// 84 - 32 bit words read from vi2csi_host_data
+// 85 to 127 - Reserved encodings
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SHIFT                 _MK_SHIFT_CONST(8)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_FIELD                 (_MK_MASK_CONST(0x7f) << CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_RANGE                 14:8
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Set when dbg_cnt_0 is incremented past max count, cleared
+// when clr_dbg_cnt_0 is written with a value of 1.
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SHIFT                      _MK_SHIFT_CONST(15)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_RANGE                      15:15
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Debug Count Select 1, this field selects what will be 
+// counted by debug counter 1.
+// Encodings 00 to 31 selects the set signal for one of 
+// the CSI_PIXEL_PARSER_STATUS register bits. In this case
+// the select encoding of this field is the same as the
+// bit position, in CSI_PIXEL_PARSER_STATUS, of the status
+// bit who's set signal will be used to increment DBG_CNT_0.
+// Encodings 32 to 63 selects the set signal for one of 
+// the CSI_CIL_STATUS status bits. The least significant 
+// 5 bits of this select field give the bit position, in
+// CSI_CIL_STATUS, of the status bit whos set signal pluses
+// will be counted by dbg_cnt_0. Selections for encodings 64
+// to 127 are given below: 
+// 64 - PPA Line packets processed
+// 65 - PPA short packets processed
+// 66 - Total packets processed by PPA
+// 67 - PPA Frame Starts Outputted
+// 68 - PPA Frame Ends Outputted
+// 69 - Reserved encoding
+// 70 - PPB Line packets processed
+// 71 - PPB short packets processed
+// 72 - Total packets processed by PPB
+// 73 - PPB Frame Starts Outputted
+// 74 - PPB Frame Ends Outputted
+// 75 - Reserved encoding
+// 76 - HPA Headers Parsed
+// 77 - HPA Headers Parsed with no ECC Errors
+// 78 - HPB Headers Parsed
+// 79 - HPB Headers Parsed with no ECC Errors
+// 80 - HPV Headers Parsed
+// 81 - HPV Headers Parsed with no ECC Errors
+// 82 - HPH Headers Parsed
+// 83 - HPH Headers Parsed with no ECC Errors
+// 84 - 32 bit words read from vi2csi_host_data
+// 85 to 127 - Reserved encodings
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_FIELD                 (_MK_MASK_CONST(0x7f) << CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_RANGE                 22:16
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Set when dbg_cnt_1 is incremented past max count, cleared
+// when clr_dbg_cnt_1 is written with a value of 1.
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SHIFT                      _MK_SHIFT_CONST(23)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_RANGE                      23:23
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Debug Count Select 2, this field selects what will be 
+// counted by debug counter 2.
+// Encodings 00 to 31 selects the set signal for one of 
+// the CSI_PIXEL_PARSER_STATUS register bits. In this case
+// the select encoding of this field is the same as the
+// bit position, in CSI_PIXEL_PARSER_STATUS, of the status
+// bit who's set signal will be used to increment DBG_CNT_0.
+// Encodings 32 to 63 selects the set signal for one of 
+// the CSI_CIL_STATUS status bits. The least significant 
+// 5 bits of this select field give the bit position, in
+// CSI_CIL_STATUS, of the status bit whos set signal pluses
+// will be counted by dbg_cnt_0. Selections for encodings 64
+// to 127 are given below: 
+// 64 - PPA Line packets processed
+// 65 - PPA short packets processed
+// 66 - Total packets processed by PPA
+// 67 - PPA Frame Starts Outputted
+// 68 - PPA Frame Ends Outputted
+// 69 - Reserved encoding
+// 70 - PPB Line packets processed
+// 71 - PPB short packets processed
+// 72 - Total packets processed by PPB
+// 73 - PPB Frame Starts Outputted
+// 74 - PPB Frame Ends Outputted
+// 75 - Reserved encoding
+// 76 - HPA Headers Parsed
+// 77 - HPA Headers Parsed with no ECC Errors
+// 78 - HPB Headers Parsed
+// 79 - HPB Headers Parsed with no ECC Errors
+// 80 - HPV Headers Parsed
+// 81 - HPV Headers Parsed with no ECC Errors
+// 82 - HPH Headers Parsed
+// 83 - HPH Headers Parsed with no ECC Errors
+// 84 - 32 bit words read from vi2csi_host_data
+// 85 to 127 - Reserved encodings
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_FIELD                 (_MK_MASK_CONST(0x7f) << CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_RANGE                 30:24
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Set when dbg_cnt_2 is incremented past max count, cleared
+// when clr_dbg_cnt_2 is written with a value of 1.
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SHIFT                      _MK_SHIFT_CONST(31)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_RANGE                      31:31
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DEBUG_COUNTER_0_0  // Debug Counter 0, this register can be used to count 
+// error conditions or packets processed.
+#define CSI_DEBUG_COUNTER_0_0                   _MK_ADDR_CONST(0x22f)
+#define CSI_DEBUG_COUNTER_0_0_WORD_COUNT                        0x1
+#define CSI_DEBUG_COUNTER_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define CSI_DEBUG_COUNTER_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// When read returns the value of debug counter 0.
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SHIFT)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_RANGE                   31:0
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_WOFFSET                 0x0
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DEBUG_COUNTER_1_0  // Debug Counter 1, this register can be used to count 
+// error conditions or packets processed.
+#define CSI_DEBUG_COUNTER_1_0                   _MK_ADDR_CONST(0x230)
+#define CSI_DEBUG_COUNTER_1_0_WORD_COUNT                        0x1
+#define CSI_DEBUG_COUNTER_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define CSI_DEBUG_COUNTER_1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// When read returns the value of debug counter 1.
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SHIFT)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_RANGE                   31:0
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_WOFFSET                 0x0
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DEBUG_COUNTER_2_0  // Debug Counter 2, this register can be used to count 
+// error conditions or packets processed.
+#define CSI_DEBUG_COUNTER_2_0                   _MK_ADDR_CONST(0x231)
+#define CSI_DEBUG_COUNTER_2_0_WORD_COUNT                        0x1
+#define CSI_DEBUG_COUNTER_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define CSI_DEBUG_COUNTER_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// When read returns the value of debug counter 2.
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SHIFT)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_RANGE                   31:0
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_WOFFSET                 0x0
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0  // CSI Pixel Stream A Expected Frame
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0                     _MK_ADDR_CONST(0x232)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_WORD_COUNT                  0x1
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_READ_MASK                   _MK_MASK_CONST(0x1ffffff1)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_WRITE_MASK                  _MK_MASK_CONST(0x1ffffff1)
+// When set to one enables checking of the time between
+// start line requests from the Header Parser to CSI-PPA.
+// A fake EF will be outputted by CSI-PPA if this time 
+// between line starts exceeds the value in 
+// MAX_CLOCKS_BETWEEN_LINES. Padding lines can be inserted
+// before the fake EF, if the number of lines outputted,
+// when the fake EF is generated is less than the expected
+// frame height. The type of padding is specified using
+// CSI_PPA_PAD_FRAME.
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SHIFT)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_RANGE                       0:0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Maximum Number of viclk clock cycles between line
+// start requests. The value in this field is in terms
+// of 256 viclk clock cycles.
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_FIELD                        (_MK_MASK_CONST(0xfff) << CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SHIFT)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_RANGE                        15:4
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// CSI-PPA Expected Frame Height
+// Specifies the expected height of the CSI-PPA frame 
+// output. Padding out of frames that are shorter
+// than this expected height can be specified using
+// CSI_PPA_PAD_FRAME. If CSI_PPA_PAD_FRAME is set to
+// PAD0S or PAD1S, this parameter must be programmed.
+// If CSI_PPA_PAD_FRAME is set to NOPAD, this parameter
+// may not be programmed. 
+// Programmed Value = number of lines
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_FIELD                  (_MK_MASK_CONST(0x1fff) << CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SHIFT)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_RANGE                  28:16
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0  // CSI Pixel Stream B Expected Frame
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0                     _MK_ADDR_CONST(0x233)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_WORD_COUNT                  0x1
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_READ_MASK                   _MK_MASK_CONST(0x1ffffff1)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_WRITE_MASK                  _MK_MASK_CONST(0x1ffffff1)
+// When set to one enables checking of the time between
+// start line requests from the Header Parser to CSI-PPB.
+// A fake EF will be outputted by CSI-PPB if this time 
+// between line starts exceeds the value in 
+// MAX_CLOCKS_BETWEEN_LINES. Padding lines can be inserted
+// before the fake EF, if the number of lines outputted,
+// when the fake EF is generated is less than the expected
+// frame height. The type of padding is specified using
+// CSI_PPB_PAD_FRAME.
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SHIFT)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_RANGE                       0:0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Maximum Number of viclk clock cycles between line
+// start requests. The value in this field is in terms
+// of 256 viclk clock cycles.
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_FIELD                        (_MK_MASK_CONST(0xfff) << CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SHIFT)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_RANGE                        15:4
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// CSI-PPB Expected Frame Height
+// Specifies the expected height of the CSI-PPB frame 
+// output. Padding out of frames that are shorter
+// than this expected height can be specified using
+// CSI_PPB_PAD_FRAME. If CSI_PPB_PAD_FRAME is set to
+// PAD0S or PAD1S, this parameter must be programmed.
+// If CSI_PPB_PAD_FRAME is set to NOPAD, this parameter
+// may not be programmed.
+// Programmed Value = number of lines
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_FIELD                  (_MK_MASK_CONST(0x1fff) << CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SHIFT)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_RANGE                  28:16
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DSI_MIPI_CAL_CONFIG_0  // Calibration settings for DSI mipi pad
+#define CSI_DSI_MIPI_CAL_CONFIG_0                       _MK_ADDR_CONST(0x234)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_WORD_COUNT                    0x1
+#define CSI_DSI_MIPI_CAL_CONFIG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_RESET_MASK                    _MK_MASK_CONST(0x401f1f1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_READ_MASK                     _MK_MASK_CONST(0x401f1f1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_WRITE_MASK                    _MK_MASK_CONST(0x401f1f1f)
+// 2's complement offset for TERMADJ
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_FIELD                        (_MK_MASK_CONST(0x1f) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_RANGE                        4:0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_WOFFSET                      0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPUADJ
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_FIELD                        (_MK_MASK_CONST(0x1f) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_RANGE                        12:8
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_WOFFSET                      0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPDADJ
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_FIELD                        (_MK_MASK_CONST(0x1f) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_RANGE                        20:16
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_WOFFSET                      0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// When 0 (normal operation), use the above registers
+// as an offset to the Calibration State machine setting
+// for TERMADJ/HSPUADJ/HSPDADJ values to the 
+// Mipi Pads. When 1, use the register values above as
+// the actual value going to TERMADJ/HSPUADJ/HSPDADJ
+// on the Mipi Pads.
+// Writting a one to Bit 31 of CILA_MIPI_CAL_CONFIG 
+// (MIPI_CAL_STARTCAL) starts the Calibration State
+// machine.
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SHIFT                       _MK_SHIFT_CONST(30)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_FIELD                       (_MK_MASK_CONST(0x1) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_RANGE                       30:30
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_WOFFSET                     0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Packet SENSOR2CIL_PKT
+#define SENSOR2CIL_PKT_SIZE 10
+
+// Data
+#define SENSOR2CIL_PKT_BYTE_SHIFT                       _MK_SHIFT_CONST(0)
+#define SENSOR2CIL_PKT_BYTE_FIELD                       (_MK_MASK_CONST(0xff) << SENSOR2CIL_PKT_BYTE_SHIFT)
+#define SENSOR2CIL_PKT_BYTE_RANGE                       _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define SENSOR2CIL_PKT_BYTE_ROW                 0
+
+// Start of frame
+#define SENSOR2CIL_PKT_SOT_SHIFT                        _MK_SHIFT_CONST(8)
+#define SENSOR2CIL_PKT_SOT_FIELD                        (_MK_MASK_CONST(0x1) << SENSOR2CIL_PKT_SOT_SHIFT)
+#define SENSOR2CIL_PKT_SOT_RANGE                        _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
+#define SENSOR2CIL_PKT_SOT_ROW                  0
+
+// End of frame
+#define SENSOR2CIL_PKT_EOT_SHIFT                        _MK_SHIFT_CONST(9)
+#define SENSOR2CIL_PKT_EOT_FIELD                        (_MK_MASK_CONST(0x1) << SENSOR2CIL_PKT_EOT_SHIFT)
+#define SENSOR2CIL_PKT_EOT_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
+#define SENSOR2CIL_PKT_EOT_ROW                  0
+
+
+// Packet CIL2CSI_PKT
+#define CIL2CSI_PKT_SIZE 8
+
+// Data
+#define CIL2CSI_PKT_BYTE_SHIFT                  _MK_SHIFT_CONST(0)
+#define CIL2CSI_PKT_BYTE_FIELD                  (_MK_MASK_CONST(0xff) << CIL2CSI_PKT_BYTE_SHIFT)
+#define CIL2CSI_PKT_BYTE_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CIL2CSI_PKT_BYTE_ROW                    0
+
+
+// Packet VI2CSI_HOST_PKT
+#define VI2CSI_HOST_PKT_SIZE 33
+
+// Data
+#define VI2CSI_HOST_PKT_HOSTDATA_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI2CSI_HOST_PKT_HOSTDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << VI2CSI_HOST_PKT_HOSTDATA_SHIFT)
+#define VI2CSI_HOST_PKT_HOSTDATA_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define VI2CSI_HOST_PKT_HOSTDATA_ROW                    0
+
+// End of packet tag, 0: end of packet, 1: valid packet data
+#define VI2CSI_HOST_PKT_TAG_SHIFT                       _MK_SHIFT_CONST(32)
+#define VI2CSI_HOST_PKT_TAG_FIELD                       (_MK_MASK_CONST(0x1) << VI2CSI_HOST_PKT_TAG_SHIFT)
+#define VI2CSI_HOST_PKT_TAG_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define VI2CSI_HOST_PKT_TAG_ROW                 0
+
+
+// Packet VI2CSI_VIP_PKT
+#define VI2CSI_VIP_PKT_SIZE 16
+
+// Data
+#define VI2CSI_VIP_PKT_VIPDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI2CSI_VIP_PKT_VIPDATA_FIELD                    (_MK_MASK_CONST(0xffff) << VI2CSI_VIP_PKT_VIPDATA_SHIFT)
+#define VI2CSI_VIP_PKT_VIPDATA_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define VI2CSI_VIP_PKT_VIPDATA_ROW                      0
+
+
+// Packet SENSOR2CIL_TIMING_PKT
+#define SENSOR2CIL_TIMING_PKT_SIZE 73
+
+// 
+#define SENSOR2CIL_TIMING_PKT_LPX_SHIFT                 _MK_SHIFT_CONST(0)
+#define SENSOR2CIL_TIMING_PKT_LPX_FIELD                 (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_LPX_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_LPX_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define SENSOR2CIL_TIMING_PKT_LPX_ROW                   0
+
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_SHIFT                  _MK_SHIFT_CONST(8)
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_FIELD                  (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_PREPARE_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_RANGE                  _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_ROW                    0
+
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_SHIFT                     _MK_SHIFT_CONST(16)
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_FIELD                     (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_ZERO_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_ROW                       0
+
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_SHIFT                    _MK_SHIFT_CONST(24)
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_FIELD                    (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_TRAIL_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_ROW                      0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_SHIFT                    _MK_SHIFT_CONST(32)
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_FIELD                    (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_ZERO_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_RANGE                    _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_ROW                      0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_SHIFT                     _MK_SHIFT_CONST(40)
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_FIELD                     (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_PRE_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(40)
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_ROW                       0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_SHIFT                    _MK_SHIFT_CONST(48)
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_FIELD                    (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_POST_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_RANGE                    _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(48)
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_ROW                      0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_SHIFT                   _MK_SHIFT_CONST(56)
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_FIELD                   (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_TRAIL_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(56)
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_ROW                     0
+
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_SHIFT                     _MK_SHIFT_CONST(64)
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_FIELD                     (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_EXIT_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_RANGE                     _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_ROW                       0
+
+// default to use RTL internal
+#define SENSOR2CIL_TIMING_PKT_RANDOM_SHIFT                      _MK_SHIFT_CONST(72)
+#define SENSOR2CIL_TIMING_PKT_RANDOM_FIELD                      (_MK_MASK_CONST(0x1) << SENSOR2CIL_TIMING_PKT_RANDOM_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_RANDOM_RANGE                      _MK_SHIFT_CONST(72):_MK_SHIFT_CONST(72)
+#define SENSOR2CIL_TIMING_PKT_RANDOM_ROW                        0
+
+
+// Packet SENSOR2CIL_COMMAND_PKT
+#define SENSOR2CIL_COMMAND_PKT_SIZE 33
+
+// 
+// NO_OP    =0x0,   
+// ESC_ULPS =0x1, // escape mode: ultra low power state
+// ESC_LPDT =0x2, // escape mode: low power data transmission
+// ESC_RAR  =0x3, // escape mode: remote application reset
+// SOT_ERR  =0x4  // use SOT_CODE for SOT error injection
+// FR_HSCLK =0x5  // set high speed clock free running
+#define SENSOR2CIL_COMMAND_PKT_CMD_SHIFT                        _MK_SHIFT_CONST(0)
+#define SENSOR2CIL_COMMAND_PKT_CMD_FIELD                        (_MK_MASK_CONST(0x1f) << SENSOR2CIL_COMMAND_PKT_CMD_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_CMD_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define SENSOR2CIL_COMMAND_PKT_CMD_ROW                  0
+
+// sot or escape delay in esc mode
+#define SENSOR2CIL_COMMAND_PKT_PARAM_SHIFT                      _MK_SHIFT_CONST(5)
+#define SENSOR2CIL_COMMAND_PKT_PARAM_FIELD                      (_MK_MASK_CONST(0xff) << SENSOR2CIL_COMMAND_PKT_PARAM_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_PARAM_RANGE                      _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(5)
+#define SENSOR2CIL_COMMAND_PKT_PARAM_ROW                        0
+
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_SHIFT                 _MK_SHIFT_CONST(13)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_FIELD                 (_MK_MASK_CONST(0xff) << SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_RANGE                 _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(13)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_ROW                   0
+
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_SHIFT                      _MK_SHIFT_CONST(21)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_FIELD                      (_MK_MASK_CONST(0xff) << SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_RANGE                      _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(21)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_ROW                        0
+
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_SHIFT                     _MK_SHIFT_CONST(29)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_FIELD                     (_MK_MASK_CONST(0xf) << SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_RANGE                     _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(29)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_ROW                       0
+
+
+// Packet CSI_HEADER
+#define CSI_HEADER_SIZE 32
+
+// Data type in packet
+#define CSI_HEADER_DATA_TYPE_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_HEADER_DATA_TYPE_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_HEADER_DATA_TYPE_SHIFT)
+#define CSI_HEADER_DATA_TYPE_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define CSI_HEADER_DATA_TYPE_ROW                        0
+
+// Virtual channel number
+#define CSI_HEADER_VIRTUAL_CHANNEL_SHIFT                        _MK_SHIFT_CONST(6)
+#define CSI_HEADER_VIRTUAL_CHANNEL_FIELD                        (_MK_MASK_CONST(0x3) << CSI_HEADER_VIRTUAL_CHANNEL_SHIFT)
+#define CSI_HEADER_VIRTUAL_CHANNEL_RANGE                        _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(6)
+#define CSI_HEADER_VIRTUAL_CHANNEL_ROW                  0
+
+// Number of bytes in packet payload
+#define CSI_HEADER_WORD_COUNT_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_HEADER_WORD_COUNT_FIELD                     (_MK_MASK_CONST(0xffff) << CSI_HEADER_WORD_COUNT_SHIFT)
+#define CSI_HEADER_WORD_COUNT_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(8)
+#define CSI_HEADER_WORD_COUNT_ROW                       0
+
+// Error correction code for packet
+#define CSI_HEADER_ECC_SHIFT                    _MK_SHIFT_CONST(24)
+#define CSI_HEADER_ECC_FIELD                    (_MK_MASK_CONST(0xff) << CSI_HEADER_ECC_SHIFT)
+#define CSI_HEADER_ECC_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_HEADER_ECC_ROW                      0
+
+
+// Packet CSI_RAISE
+#define CSI_RAISE_SIZE 20
+
+#define CSI_RAISE_VECTOR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSI_RAISE_VECTOR_FIELD                  (_MK_MASK_CONST(0x1f) << CSI_RAISE_VECTOR_SHIFT)
+#define CSI_RAISE_VECTOR_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define CSI_RAISE_VECTOR_ROW                    0
+
+#define CSI_RAISE_COUNT_SHIFT                   _MK_SHIFT_CONST(8)
+#define CSI_RAISE_COUNT_FIELD                   (_MK_MASK_CONST(0xff) << CSI_RAISE_COUNT_SHIFT)
+#define CSI_RAISE_COUNT_RANGE                   _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAISE_COUNT_ROW                     0
+
+#define CSI_RAISE_CHID_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSI_RAISE_CHID_FIELD                    (_MK_MASK_CONST(0xf) << CSI_RAISE_CHID_SHIFT)
+#define CSI_RAISE_CHID_RANGE                    _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(16)
+#define CSI_RAISE_CHID_ROW                      0
+
+
+// Packet CSI_GENERIC_BYTE
+#define CSI_GENERIC_BYTE_SIZE 72
+
+#define CSI_GENERIC_BYTE_BYTE0_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_GENERIC_BYTE_BYTE0_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE0_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE0_RANGE                    _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_GENERIC_BYTE_BYTE0_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE1_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_GENERIC_BYTE_BYTE1_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE1_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE1_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_GENERIC_BYTE_BYTE1_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE2_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSI_GENERIC_BYTE_BYTE2_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE2_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE2_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSI_GENERIC_BYTE_BYTE2_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE3_SHIFT                    _MK_SHIFT_CONST(24)
+#define CSI_GENERIC_BYTE_BYTE3_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE3_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE3_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_GENERIC_BYTE_BYTE3_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE4_SHIFT                    _MK_SHIFT_CONST(32)
+#define CSI_GENERIC_BYTE_BYTE4_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE4_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE4_RANGE                    _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define CSI_GENERIC_BYTE_BYTE4_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE5_SHIFT                    _MK_SHIFT_CONST(40)
+#define CSI_GENERIC_BYTE_BYTE5_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE5_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE5_RANGE                    _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(40)
+#define CSI_GENERIC_BYTE_BYTE5_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE6_SHIFT                    _MK_SHIFT_CONST(48)
+#define CSI_GENERIC_BYTE_BYTE6_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE6_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE6_RANGE                    _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(48)
+#define CSI_GENERIC_BYTE_BYTE6_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE7_SHIFT                    _MK_SHIFT_CONST(56)
+#define CSI_GENERIC_BYTE_BYTE7_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE7_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE7_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(56)
+#define CSI_GENERIC_BYTE_BYTE7_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE8_SHIFT                    _MK_SHIFT_CONST(64)
+#define CSI_GENERIC_BYTE_BYTE8_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE8_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE8_RANGE                    _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define CSI_GENERIC_BYTE_BYTE8_ROW                      0
+
+
+// Packet CSI_RGB_666
+#define CSI_RGB_666_SIZE 72
+
+#define CSI_RGB_666_B0_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_RGB_666_B0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B0_SHIFT)
+#define CSI_RGB_666_B0_RANGE                    _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define CSI_RGB_666_B0_ROW                      0
+
+#define CSI_RGB_666_G0_SHIFT                    _MK_SHIFT_CONST(6)
+#define CSI_RGB_666_G0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G0_SHIFT)
+#define CSI_RGB_666_G0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(6)
+#define CSI_RGB_666_G0_ROW                      0
+
+#define CSI_RGB_666_R0_SHIFT                    _MK_SHIFT_CONST(12)
+#define CSI_RGB_666_R0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R0_SHIFT)
+#define CSI_RGB_666_R0_RANGE                    _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(12)
+#define CSI_RGB_666_R0_ROW                      0
+
+#define CSI_RGB_666_B1_SHIFT                    _MK_SHIFT_CONST(18)
+#define CSI_RGB_666_B1_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B1_SHIFT)
+#define CSI_RGB_666_B1_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(18)
+#define CSI_RGB_666_B1_ROW                      0
+
+#define CSI_RGB_666_G1_SHIFT                    _MK_SHIFT_CONST(24)
+#define CSI_RGB_666_G1_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G1_SHIFT)
+#define CSI_RGB_666_G1_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(24)
+#define CSI_RGB_666_G1_ROW                      0
+
+#define CSI_RGB_666_R1_SHIFT                    _MK_SHIFT_CONST(30)
+#define CSI_RGB_666_R1_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R1_SHIFT)
+#define CSI_RGB_666_R1_RANGE                    _MK_SHIFT_CONST(35):_MK_SHIFT_CONST(30)
+#define CSI_RGB_666_R1_ROW                      0
+
+#define CSI_RGB_666_B2_SHIFT                    _MK_SHIFT_CONST(36)
+#define CSI_RGB_666_B2_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B2_SHIFT)
+#define CSI_RGB_666_B2_RANGE                    _MK_SHIFT_CONST(41):_MK_SHIFT_CONST(36)
+#define CSI_RGB_666_B2_ROW                      0
+
+#define CSI_RGB_666_G2_SHIFT                    _MK_SHIFT_CONST(42)
+#define CSI_RGB_666_G2_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G2_SHIFT)
+#define CSI_RGB_666_G2_RANGE                    _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(42)
+#define CSI_RGB_666_G2_ROW                      0
+
+#define CSI_RGB_666_R2_SHIFT                    _MK_SHIFT_CONST(48)
+#define CSI_RGB_666_R2_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R2_SHIFT)
+#define CSI_RGB_666_R2_RANGE                    _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(48)
+#define CSI_RGB_666_R2_ROW                      0
+
+#define CSI_RGB_666_B3_SHIFT                    _MK_SHIFT_CONST(54)
+#define CSI_RGB_666_B3_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B3_SHIFT)
+#define CSI_RGB_666_B3_RANGE                    _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(54)
+#define CSI_RGB_666_B3_ROW                      0
+
+#define CSI_RGB_666_G3_SHIFT                    _MK_SHIFT_CONST(60)
+#define CSI_RGB_666_G3_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G3_SHIFT)
+#define CSI_RGB_666_G3_RANGE                    _MK_SHIFT_CONST(65):_MK_SHIFT_CONST(60)
+#define CSI_RGB_666_G3_ROW                      0
+
+#define CSI_RGB_666_R3_SHIFT                    _MK_SHIFT_CONST(66)
+#define CSI_RGB_666_R3_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R3_SHIFT)
+#define CSI_RGB_666_R3_RANGE                    _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(66)
+#define CSI_RGB_666_R3_ROW                      0
+
+
+// Packet CSI_RGB_565
+#define CSI_RGB_565_SIZE 16
+
+#define CSI_RGB_565_B0_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_RGB_565_B0_FIELD                    (_MK_MASK_CONST(0x1f) << CSI_RGB_565_B0_SHIFT)
+#define CSI_RGB_565_B0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define CSI_RGB_565_B0_ROW                      0
+
+#define CSI_RGB_565_G0_SHIFT                    _MK_SHIFT_CONST(5)
+#define CSI_RGB_565_G0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_565_G0_SHIFT)
+#define CSI_RGB_565_G0_RANGE                    _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(5)
+#define CSI_RGB_565_G0_ROW                      0
+
+#define CSI_RGB_565_R0_SHIFT                    _MK_SHIFT_CONST(11)
+#define CSI_RGB_565_R0_FIELD                    (_MK_MASK_CONST(0x1f) << CSI_RGB_565_R0_SHIFT)
+#define CSI_RGB_565_R0_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(11)
+#define CSI_RGB_565_R0_ROW                      0
+
+
+// Packet CSI_RAW_6
+#define CSI_RAW_6_SIZE 24
+
+#define CSI_RAW_6_S0_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_RAW_6_S0_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S0_SHIFT)
+#define CSI_RAW_6_S0_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define CSI_RAW_6_S0_ROW                        0
+
+#define CSI_RAW_6_S1_SHIFT                      _MK_SHIFT_CONST(6)
+#define CSI_RAW_6_S1_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S1_SHIFT)
+#define CSI_RAW_6_S1_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(6)
+#define CSI_RAW_6_S1_ROW                        0
+
+#define CSI_RAW_6_S2_SHIFT                      _MK_SHIFT_CONST(12)
+#define CSI_RAW_6_S2_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S2_SHIFT)
+#define CSI_RAW_6_S2_RANGE                      _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(12)
+#define CSI_RAW_6_S2_ROW                        0
+
+#define CSI_RAW_6_S3_SHIFT                      _MK_SHIFT_CONST(18)
+#define CSI_RAW_6_S3_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S3_SHIFT)
+#define CSI_RAW_6_S3_RANGE                      _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(18)
+#define CSI_RAW_6_S3_ROW                        0
+
+
+// Packet CSI_RAW_7
+#define CSI_RAW_7_SIZE 56
+
+#define CSI_RAW_7_S0_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_RAW_7_S0_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S0_SHIFT)
+#define CSI_RAW_7_S0_RANGE                      _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define CSI_RAW_7_S0_ROW                        0
+
+#define CSI_RAW_7_S1_SHIFT                      _MK_SHIFT_CONST(7)
+#define CSI_RAW_7_S1_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S1_SHIFT)
+#define CSI_RAW_7_S1_RANGE                      _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(7)
+#define CSI_RAW_7_S1_ROW                        0
+
+#define CSI_RAW_7_S2_SHIFT                      _MK_SHIFT_CONST(14)
+#define CSI_RAW_7_S2_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S2_SHIFT)
+#define CSI_RAW_7_S2_RANGE                      _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(14)
+#define CSI_RAW_7_S2_ROW                        0
+
+#define CSI_RAW_7_S3_SHIFT                      _MK_SHIFT_CONST(21)
+#define CSI_RAW_7_S3_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S3_SHIFT)
+#define CSI_RAW_7_S3_RANGE                      _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(21)
+#define CSI_RAW_7_S3_ROW                        0
+
+#define CSI_RAW_7_S4_SHIFT                      _MK_SHIFT_CONST(28)
+#define CSI_RAW_7_S4_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S4_SHIFT)
+#define CSI_RAW_7_S4_RANGE                      _MK_SHIFT_CONST(34):_MK_SHIFT_CONST(28)
+#define CSI_RAW_7_S4_ROW                        0
+
+#define CSI_RAW_7_S5_SHIFT                      _MK_SHIFT_CONST(35)
+#define CSI_RAW_7_S5_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S5_SHIFT)
+#define CSI_RAW_7_S5_RANGE                      _MK_SHIFT_CONST(41):_MK_SHIFT_CONST(35)
+#define CSI_RAW_7_S5_ROW                        0
+
+#define CSI_RAW_7_S6_SHIFT                      _MK_SHIFT_CONST(42)
+#define CSI_RAW_7_S6_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S6_SHIFT)
+#define CSI_RAW_7_S6_RANGE                      _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(42)
+#define CSI_RAW_7_S6_ROW                        0
+
+#define CSI_RAW_7_S7_SHIFT                      _MK_SHIFT_CONST(49)
+#define CSI_RAW_7_S7_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S7_SHIFT)
+#define CSI_RAW_7_S7_RANGE                      _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(49)
+#define CSI_RAW_7_S7_ROW                        0
+
+
+// Packet CSI_RAW_10
+#define CSI_RAW_10_SIZE 40
+
+#define CSI_RAW_10_S0_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_RAW_10_S0_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S0_SHIFT)
+#define CSI_RAW_10_S0_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_RAW_10_S0_ROW                       0
+
+#define CSI_RAW_10_S1_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_RAW_10_S1_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S1_SHIFT)
+#define CSI_RAW_10_S1_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAW_10_S1_ROW                       0
+
+#define CSI_RAW_10_S2_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_RAW_10_S2_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S2_SHIFT)
+#define CSI_RAW_10_S2_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSI_RAW_10_S2_ROW                       0
+
+#define CSI_RAW_10_S3_SHIFT                     _MK_SHIFT_CONST(24)
+#define CSI_RAW_10_S3_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S3_SHIFT)
+#define CSI_RAW_10_S3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_RAW_10_S3_ROW                       0
+
+#define CSI_RAW_10_L0_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSI_RAW_10_L0_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L0_SHIFT)
+#define CSI_RAW_10_L0_RANGE                     _MK_SHIFT_CONST(33):_MK_SHIFT_CONST(32)
+#define CSI_RAW_10_L0_ROW                       0
+
+#define CSI_RAW_10_L1_SHIFT                     _MK_SHIFT_CONST(34)
+#define CSI_RAW_10_L1_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L1_SHIFT)
+#define CSI_RAW_10_L1_RANGE                     _MK_SHIFT_CONST(35):_MK_SHIFT_CONST(34)
+#define CSI_RAW_10_L1_ROW                       0
+
+#define CSI_RAW_10_L2_SHIFT                     _MK_SHIFT_CONST(36)
+#define CSI_RAW_10_L2_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L2_SHIFT)
+#define CSI_RAW_10_L2_RANGE                     _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(36)
+#define CSI_RAW_10_L2_ROW                       0
+
+#define CSI_RAW_10_L3_SHIFT                     _MK_SHIFT_CONST(38)
+#define CSI_RAW_10_L3_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L3_SHIFT)
+#define CSI_RAW_10_L3_RANGE                     _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(38)
+#define CSI_RAW_10_L3_ROW                       0
+
+
+// Packet CSI_RAW_12
+#define CSI_RAW_12_SIZE 24
+
+#define CSI_RAW_12_S0_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_RAW_12_S0_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_12_S0_SHIFT)
+#define CSI_RAW_12_S0_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_RAW_12_S0_ROW                       0
+
+#define CSI_RAW_12_S1_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_RAW_12_S1_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_12_S1_SHIFT)
+#define CSI_RAW_12_S1_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAW_12_S1_ROW                       0
+
+#define CSI_RAW_12_L0_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_RAW_12_L0_FIELD                     (_MK_MASK_CONST(0xf) << CSI_RAW_12_L0_SHIFT)
+#define CSI_RAW_12_L0_RANGE                     _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(16)
+#define CSI_RAW_12_L0_ROW                       0
+
+#define CSI_RAW_12_L1_SHIFT                     _MK_SHIFT_CONST(20)
+#define CSI_RAW_12_L1_FIELD                     (_MK_MASK_CONST(0xf) << CSI_RAW_12_L1_SHIFT)
+#define CSI_RAW_12_L1_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(20)
+#define CSI_RAW_12_L1_ROW                       0
+
+
+// Packet CSI_RAW_14
+#define CSI_RAW_14_SIZE 56
+
+#define CSI_RAW_14_S0_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_RAW_14_S0_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S0_SHIFT)
+#define CSI_RAW_14_S0_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_RAW_14_S0_ROW                       0
+
+#define CSI_RAW_14_S1_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_RAW_14_S1_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S1_SHIFT)
+#define CSI_RAW_14_S1_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAW_14_S1_ROW                       0
+
+#define CSI_RAW_14_S2_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_RAW_14_S2_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S2_SHIFT)
+#define CSI_RAW_14_S2_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSI_RAW_14_S2_ROW                       0
+
+#define CSI_RAW_14_S3_SHIFT                     _MK_SHIFT_CONST(24)
+#define CSI_RAW_14_S3_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S3_SHIFT)
+#define CSI_RAW_14_S3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_RAW_14_S3_ROW                       0
+
+#define CSI_RAW_14_L0_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSI_RAW_14_L0_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L0_SHIFT)
+#define CSI_RAW_14_L0_RANGE                     _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CSI_RAW_14_L0_ROW                       0
+
+#define CSI_RAW_14_L1_SHIFT                     _MK_SHIFT_CONST(38)
+#define CSI_RAW_14_L1_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L1_SHIFT)
+#define CSI_RAW_14_L1_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(38)
+#define CSI_RAW_14_L1_ROW                       0
+
+#define CSI_RAW_14_L2_SHIFT                     _MK_SHIFT_CONST(44)
+#define CSI_RAW_14_L2_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L2_SHIFT)
+#define CSI_RAW_14_L2_RANGE                     _MK_SHIFT_CONST(49):_MK_SHIFT_CONST(44)
+#define CSI_RAW_14_L2_ROW                       0
+
+#define CSI_RAW_14_L3_SHIFT                     _MK_SHIFT_CONST(50)
+#define CSI_RAW_14_L3_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L3_SHIFT)
+#define CSI_RAW_14_L3_RANGE                     _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(50)
+#define CSI_RAW_14_L3_ROW                       0
+
+#define CSI_DT_SSP_FS   0
+#define CSI_DT_SSP_FE   1
+#define CSI_DT_SSP_LS   2
+#define CSI_DT_SSP_LE   3
+#define CSI_DT_SSP_R1   4
+#define CSI_DT_SSP_R2   5
+#define CSI_DT_SSP_R3   6
+#define CSI_DT_SSP_R4   7
+#define CSI_DT_GSP_G1   8
+#define CSI_DT_GSP_G2   9
+#define CSI_DT_GSP_G3   10
+#define CSI_DT_GSP_G4   11
+#define CSI_DT_GSP_G5   12
+#define CSI_DT_GSP_G6   13
+#define CSI_DT_GSP_G7   14
+#define CSI_DT_GSP_G8   15
+#define CSI_DT_GED_NULL 16
+#define CSI_DT_GED_BLANK        17
+#define CSI_DT_GED_ED   18
+#define CSI_DT_GED_R1   19
+#define CSI_DT_GED_R2   20
+#define CSI_DT_GED_R3   21
+#define CSI_DT_GED_R4   22
+#define CSI_DT_GED_R5   23
+#define CSI_DT_YUV_420_8        24
+#define CSI_DT_YUV_420_10       25
+#define CSI_DT_YUV_420_L_8      26
+#define CSI_DT_YUV_R1   27
+#define CSI_DT_YUV_420_CSPS_8   28
+#define CSI_DT_YUV_420_CSPS_10  29
+#define CSI_DT_YUV_422_8        30
+#define CSI_DT_YUV_422_10       31
+#define CSI_DT_RGB_444  32
+#define CSI_DT_RGB_555  33
+#define CSI_DT_RGB_565  34
+#define CSI_DT_RGB_666  35
+#define CSI_DT_RGB_888  36
+#define CSI_DT_RGB_R1   37
+#define CSI_DT_RGB_R2   38
+#define CSI_DT_RGB_R3   39
+#define CSI_DT_RAW_6    40
+#define CSI_DT_RAW_7    41
+#define CSI_DT_RAW_8    42
+#define CSI_DT_RAW_10   43
+#define CSI_DT_RAW_12   44
+#define CSI_DT_RAW_14   45
+#define CSI_DT_RAW_R1   46
+#define CSI_DT_RAW_R2   47
+#define CSI_DT_UED_U1   48
+#define CSI_DT_UED_U2   49
+#define CSI_DT_UED_U3   50
+#define CSI_DT_UED_U4   51
+#define CSI_DT_UED_R1   52
+#define CSI_DT_UED_R2   53
+#define CSI_DT_UED_R3   54
+#define CSI_DT_UED_R4   55
+
+// Packet D
+#define D_SIZE 6
+
+// SSP = Synchronization Short Packet
+// Reserved
+#define D_T_SHIFT                       _MK_SHIFT_CONST(0)
+#define D_T_FIELD                       (_MK_MASK_CONST(0x3f) << D_T_SHIFT)
+#define D_T_RANGE                       _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define D_T_ROW                 0
+#define D_T_SSP_FS                      _MK_ENUM_CONST(0)    // // Frame Start
+
+#define D_T_SSP_FE                      _MK_ENUM_CONST(1)    // // Frame End
+
+#define D_T_SSP_LS                      _MK_ENUM_CONST(2)    // // Line Start
+
+#define D_T_SSP_LE                      _MK_ENUM_CONST(3)    // // Line End
+
+#define D_T_SSP_R1                      _MK_ENUM_CONST(4)    // // Reserved 1
+
+#define D_T_SSP_R2                      _MK_ENUM_CONST(5)    // // Reserved 2
+
+#define D_T_SSP_R3                      _MK_ENUM_CONST(6)    // // Reserved 3
+
+#define D_T_SSP_R4                      _MK_ENUM_CONST(7)    // // Reserved 4
+// GSP = Generic Short Packet
+
+#define D_T_GSP_G1                      _MK_ENUM_CONST(8)    // // Generic Short Packet Code 1
+
+#define D_T_GSP_G2                      _MK_ENUM_CONST(9)    // // Generic Short Packet Code 2
+
+#define D_T_GSP_G3                      _MK_ENUM_CONST(10)    // // Generic Short Packet Code 3
+
+#define D_T_GSP_G4                      _MK_ENUM_CONST(11)    // // Generic Short Packet Code 4
+
+#define D_T_GSP_G5                      _MK_ENUM_CONST(12)    // // Generic Short Packet Code 5
+
+#define D_T_GSP_G6                      _MK_ENUM_CONST(13)    // // Generic Short Packet Code 6
+
+#define D_T_GSP_G7                      _MK_ENUM_CONST(14)    // // Generic Short Packet Code 7
+
+#define D_T_GSP_G8                      _MK_ENUM_CONST(15)    // // Generic Short Packet Code 8
+// GED = Generic 8-bit Data
+
+#define D_T_GED_NULL                    _MK_ENUM_CONST(16)    // // Null 
+
+#define D_T_GED_BLANK                   _MK_ENUM_CONST(17)    // // Blanking Data 
+
+#define D_T_GED_ED                      _MK_ENUM_CONST(18)    // // Embedded 8-bit non Image Data
+
+#define D_T_GED_R1                      _MK_ENUM_CONST(19)    // // Reserved
+
+#define D_T_GED_R2                      _MK_ENUM_CONST(20)    // // Reserved
+
+#define D_T_GED_R3                      _MK_ENUM_CONST(21)    // // Reserved
+
+#define D_T_GED_R4                      _MK_ENUM_CONST(22)    // // Reserved
+
+#define D_T_GED_R5                      _MK_ENUM_CONST(23)    // // Reserved
+// YUV = YUV Image Data Types
+
+#define D_T_YUV_420_8                   _MK_ENUM_CONST(24)    // // YUV420 8-bit
+
+#define D_T_YUV_420_10                  _MK_ENUM_CONST(25)    // // YUV420 10-bit
+
+#define D_T_YUV_420_L_8                 _MK_ENUM_CONST(26)    // // Legacy YUV420 8-bit
+
+#define D_T_YUV_R1                      _MK_ENUM_CONST(27)    // // Reserved
+
+#define D_T_YUV_420_CSPS_8                      _MK_ENUM_CONST(28)    // // YUV420 8-bit (Chroma Shifted Pixel Sampling)
+
+#define D_T_YUV_420_CSPS_10                     _MK_ENUM_CONST(29)    // // YUV420 10-bit (Chroma Shifted Pixel Sampling)
+
+#define D_T_YUV_422_8                   _MK_ENUM_CONST(30)    // // YUV422 8-bit
+
+#define D_T_YUV_422_10                  _MK_ENUM_CONST(31)    // // YUV422 10-bit
+// RGB = RGB Image Data Types
+
+#define D_T_RGB_444                     _MK_ENUM_CONST(32)    // // RGB444
+
+#define D_T_RGB_555                     _MK_ENUM_CONST(33)    // // RGB555
+
+#define D_T_RGB_565                     _MK_ENUM_CONST(34)    // // RGB565
+
+#define D_T_RGB_666                     _MK_ENUM_CONST(35)    // // RGB666
+
+#define D_T_RGB_888                     _MK_ENUM_CONST(36)    // // RGB888
+
+#define D_T_RGB_R1                      _MK_ENUM_CONST(37)    // // Reserved
+
+#define D_T_RGB_R2                      _MK_ENUM_CONST(38)    // // Reserved
+
+#define D_T_RGB_R3                      _MK_ENUM_CONST(39)    // // Reserved
+// RAW Image Data Types
+
+#define D_T_RAW_6                       _MK_ENUM_CONST(40)    // // RAW6
+
+#define D_T_RAW_7                       _MK_ENUM_CONST(41)    // // RAW7
+
+#define D_T_RAW_8                       _MK_ENUM_CONST(42)    // // RAW8
+
+#define D_T_RAW_10                      _MK_ENUM_CONST(43)    // // RAW10
+
+#define D_T_RAW_12                      _MK_ENUM_CONST(44)    // // RAW12
+
+#define D_T_RAW_14                      _MK_ENUM_CONST(45)    // // RAW14
+
+#define D_T_RAW_R1                      _MK_ENUM_CONST(46)    // // Reserved
+
+#define D_T_RAW_R2                      _MK_ENUM_CONST(47)    // // Reserved
+// UED = User Defined 8-bit Data
+
+#define D_T_UED_U1                      _MK_ENUM_CONST(48)    // // User Defined 8-bit Data Type 1
+
+#define D_T_UED_U2                      _MK_ENUM_CONST(49)    // // User Defined 8-bit Data Type 2
+
+#define D_T_UED_U3                      _MK_ENUM_CONST(50)    // // User Defined 8-bit Data Type 3
+
+#define D_T_UED_U4                      _MK_ENUM_CONST(51)    // // User Defined 8-bit Data Type 4
+
+#define D_T_UED_R1                      _MK_ENUM_CONST(52)    // // Reserved
+
+#define D_T_UED_R2                      _MK_ENUM_CONST(53)    // // Reserved
+
+#define D_T_UED_R3                      _MK_ENUM_CONST(54)    // // Reserved
+
+#define D_T_UED_R4                      _MK_ENUM_CONST(55)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARVI_REGS(_op_) \
+_op_(VI_OUT_1_INCR_SYNCPT_0) \
+_op_(VI_OUT_1_INCR_SYNCPT_CNTRL_0) \
+_op_(VI_OUT_1_INCR_SYNCPT_ERROR_0) \
+_op_(VI_OUT_2_INCR_SYNCPT_0) \
+_op_(VI_OUT_2_INCR_SYNCPT_CNTRL_0) \
+_op_(VI_OUT_2_INCR_SYNCPT_ERROR_0) \
+_op_(VI_MISC_INCR_SYNCPT_0) \
+_op_(VI_MISC_INCR_SYNCPT_CNTRL_0) \
+_op_(VI_MISC_INCR_SYNCPT_ERROR_0) \
+_op_(VI_CONT_SYNCPT_OUT_1_0) \
+_op_(VI_CONT_SYNCPT_OUT_2_0) \
+_op_(VI_CONT_SYNCPT_VIP_VSYNC_0) \
+_op_(VI_CONT_SYNCPT_VI2EPP_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0) \
+_op_(VI_CTXSW_0) \
+_op_(VI_INTSTATUS_0) \
+_op_(VI_VI_INPUT_CONTROL_0) \
+_op_(VI_VI_CORE_CONTROL_0) \
+_op_(VI_VI_FIRST_OUTPUT_CONTROL_0) \
+_op_(VI_VI_SECOND_OUTPUT_CONTROL_0) \
+_op_(VI_HOST_INPUT_FRAME_SIZE_0) \
+_op_(VI_HOST_H_ACTIVE_0) \
+_op_(VI_HOST_V_ACTIVE_0) \
+_op_(VI_VIP_H_ACTIVE_0) \
+_op_(VI_VIP_V_ACTIVE_0) \
+_op_(VI_VI_PEER_CONTROL_0) \
+_op_(VI_VI_DMA_SELECT_0) \
+_op_(VI_HOST_DMA_WRITE_BUFFER_0) \
+_op_(VI_HOST_DMA_BASE_ADDRESS_0) \
+_op_(VI_HOST_DMA_WRITE_BUFFER_STATUS_0) \
+_op_(VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0) \
+_op_(VI_VB0_START_ADDRESS_FIRST_0) \
+_op_(VI_VB0_BASE_ADDRESS_FIRST_0) \
+_op_(VI_VB0_START_ADDRESS_U_0) \
+_op_(VI_VB0_BASE_ADDRESS_U_0) \
+_op_(VI_VB0_START_ADDRESS_V_0) \
+_op_(VI_VB0_BASE_ADDRESS_V_0) \
+_op_(VI_VB0_SCRATCH_ADDRESS_UV_0) \
+_op_(VI_FIRST_OUTPUT_FRAME_SIZE_0) \
+_op_(VI_VB0_COUNT_FIRST_0) \
+_op_(VI_VB0_SIZE_FIRST_0) \
+_op_(VI_VB0_BUFFER_STRIDE_FIRST_0) \
+_op_(VI_VB0_START_ADDRESS_SECOND_0) \
+_op_(VI_VB0_BASE_ADDRESS_SECOND_0) \
+_op_(VI_SECOND_OUTPUT_FRAME_SIZE_0) \
+_op_(VI_VB0_COUNT_SECOND_0) \
+_op_(VI_VB0_SIZE_SECOND_0) \
+_op_(VI_VB0_BUFFER_STRIDE_SECOND_0) \
+_op_(VI_H_LPF_CONTROL_0) \
+_op_(VI_H_DOWNSCALE_CONTROL_0) \
+_op_(VI_V_DOWNSCALE_CONTROL_0) \
+_op_(VI_CSC_Y_0) \
+_op_(VI_CSC_UV_R_0) \
+_op_(VI_CSC_UV_G_0) \
+_op_(VI_CSC_UV_B_0) \
+_op_(VI_CSC_ALPHA_0) \
+_op_(VI_HOST_VSYNC_0) \
+_op_(VI_COMMAND_0) \
+_op_(VI_HOST_FIFO_STATUS_0) \
+_op_(VI_INTERRUPT_MASK_0) \
+_op_(VI_INTERRUPT_TYPE_SELECT_0) \
+_op_(VI_INTERRUPT_POLARITY_SELECT_0) \
+_op_(VI_INTERRUPT_STATUS_0) \
+_op_(VI_VIP_INPUT_STATUS_0) \
+_op_(VI_VIDEO_BUFFER_STATUS_0) \
+_op_(VI_SYNC_OUTPUT_0) \
+_op_(VI_VVS_OUTPUT_DELAY_0) \
+_op_(VI_PWM_CONTROL_0) \
+_op_(VI_PWM_SELECT_PULSE_A_0) \
+_op_(VI_PWM_SELECT_PULSE_B_0) \
+_op_(VI_PWM_SELECT_PULSE_C_0) \
+_op_(VI_PWM_SELECT_PULSE_D_0) \
+_op_(VI_VI_DATA_INPUT_CONTROL_0) \
+_op_(VI_PIN_INPUT_ENABLE_0) \
+_op_(VI_PIN_OUTPUT_ENABLE_0) \
+_op_(VI_PIN_INVERSION_0) \
+_op_(VI_PIN_INPUT_DATA_0) \
+_op_(VI_PIN_OUTPUT_DATA_0) \
+_op_(VI_PIN_OUTPUT_SELECT_0) \
+_op_(VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0) \
+_op_(VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0) \
+_op_(VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0) \
+_op_(VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0) \
+_op_(VI_RAISE_HOST_FIRST_OUTPUT_0) \
+_op_(VI_RAISE_HOST_SECOND_OUTPUT_0) \
+_op_(VI_RAISE_EPP_0) \
+_op_(VI_CAMERA_CONTROL_0) \
+_op_(VI_VI_ENABLE_0) \
+_op_(VI_VI_ENABLE_2_0) \
+_op_(VI_VI_RAISE_0) \
+_op_(VI_Y_FIFO_WRITE_0) \
+_op_(VI_U_FIFO_WRITE_0) \
+_op_(VI_V_FIFO_WRITE_0) \
+_op_(VI_VI_MCCIF_FIFOCTRL_0) \
+_op_(VI_TIMEOUT_WCOAL_VI_0) \
+_op_(VI_MCCIF_VIRUV_HP_0) \
+_op_(VI_MCCIF_VIWSB_HP_0) \
+_op_(VI_MCCIF_VIWU_HP_0) \
+_op_(VI_MCCIF_VIWV_HP_0) \
+_op_(VI_MCCIF_VIWY_HP_0) \
+_op_(VI_CSI_PPA_RAISE_FRAME_START_0) \
+_op_(VI_CSI_PPA_RAISE_FRAME_END_0) \
+_op_(VI_CSI_PPB_RAISE_FRAME_START_0) \
+_op_(VI_CSI_PPB_RAISE_FRAME_END_0) \
+_op_(VI_CSI_PPA_H_ACTIVE_0) \
+_op_(VI_CSI_PPA_V_ACTIVE_0) \
+_op_(VI_CSI_PPB_H_ACTIVE_0) \
+_op_(VI_CSI_PPB_V_ACTIVE_0) \
+_op_(VI_ISP_H_ACTIVE_0) \
+_op_(VI_ISP_V_ACTIVE_0) \
+_op_(VI_STREAM_1_RESOURCE_DEFINE_0) \
+_op_(VI_STREAM_2_RESOURCE_DEFINE_0) \
+_op_(VI_RAISE_STREAM_1_DONE_0) \
+_op_(VI_RAISE_STREAM_2_DONE_0) \
+_op_(VI_TS_MODE_0) \
+_op_(VI_TS_CONTROL_0) \
+_op_(VI_TS_PACKET_COUNT_0) \
+_op_(VI_TS_ERROR_COUNT_0) \
+_op_(VI_TS_CPU_FLOW_CTL_0) \
+_op_(VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0) \
+_op_(VI_VB0_CHROMA_LINE_STRIDE_FIRST_0) \
+_op_(VI_EPP_LINES_PER_BUFFER_0) \
+_op_(VI_BUFFER_RELEASE_OUTPUT1_0) \
+_op_(VI_BUFFER_RELEASE_OUTPUT2_0) \
+_op_(VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0) \
+_op_(VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0) \
+_op_(VI_TERMINATE_BW_FIRST_0) \
+_op_(VI_TERMINATE_BW_SECOND_0) \
+_op_(VI_VB0_FIRST_BUFFER_ADDR_MODE_0) \
+_op_(VI_VB0_SECOND_BUFFER_ADDR_MODE_0) \
+_op_(VI_RESERVE_0_0) \
+_op_(VI_RESERVE_1_0) \
+_op_(VI_RESERVE_2_0) \
+_op_(VI_RESERVE_3_0) \
+_op_(VI_RESERVE_4_0) \
+_op_(CSI_VI_INPUT_STREAM_CONTROL_0) \
+_op_(CSI_HOST_INPUT_STREAM_CONTROL_0) \
+_op_(CSI_INPUT_STREAM_A_CONTROL_0) \
+_op_(CSI_PIXEL_STREAM_A_CONTROL0_0) \
+_op_(CSI_PIXEL_STREAM_A_CONTROL1_0) \
+_op_(CSI_PIXEL_STREAM_A_WORD_COUNT_0) \
+_op_(CSI_PIXEL_STREAM_A_GAP_0) \
+_op_(CSI_PIXEL_STREAM_PPA_COMMAND_0) \
+_op_(CSI_INPUT_STREAM_B_CONTROL_0) \
+_op_(CSI_PIXEL_STREAM_B_CONTROL0_0) \
+_op_(CSI_PIXEL_STREAM_B_CONTROL1_0) \
+_op_(CSI_PIXEL_STREAM_B_WORD_COUNT_0) \
+_op_(CSI_PIXEL_STREAM_B_GAP_0) \
+_op_(CSI_PIXEL_STREAM_PPB_COMMAND_0) \
+_op_(CSI_PHY_CIL_COMMAND_0) \
+_op_(CSI_PHY_CILA_CONTROL0_0) \
+_op_(CSI_PHY_CILB_CONTROL0_0) \
+_op_(CSI_CSI_PIXEL_PARSER_STATUS_0) \
+_op_(CSI_CSI_CIL_STATUS_0) \
+_op_(CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0) \
+_op_(CSI_CSI_CIL_INTERRUPT_MASK_0) \
+_op_(CSI_CSI_READONLY_STATUS_0) \
+_op_(CSI_ESCAPE_MODE_COMMAND_0) \
+_op_(CSI_ESCAPE_MODE_DATA_0) \
+_op_(CSI_CILA_PAD_CONFIG0_0) \
+_op_(CSI_CILA_PAD_CONFIG1_0) \
+_op_(CSI_CILB_PAD_CONFIG0_0) \
+_op_(CSI_CILB_PAD_CONFIG1_0) \
+_op_(CSI_CIL_PAD_CONFIG0_0) \
+_op_(CSI_CILA_MIPI_CAL_CONFIG_0) \
+_op_(CSI_CILB_MIPI_CAL_CONFIG_0) \
+_op_(CSI_CIL_MIPI_CAL_STATUS_0) \
+_op_(CSI_CLKEN_OVERRIDE_0) \
+_op_(CSI_DEBUG_CONTROL_0) \
+_op_(CSI_DEBUG_COUNTER_0_0) \
+_op_(CSI_DEBUG_COUNTER_1_0) \
+_op_(CSI_DEBUG_COUNTER_2_0) \
+_op_(CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0) \
+_op_(CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0) \
+_op_(CSI_DSI_MIPI_CAL_CONFIG_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_VI 0x00000000
+#define BASE_ADDRESS_CSI        0x00000200
+
+//
+// ARVI REGISTER BANKS
+//
+
+#define VI0_FIRST_REG 0x0000 // VI_OUT_1_INCR_SYNCPT_0
+#define VI0_LAST_REG 0x0002 // VI_OUT_1_INCR_SYNCPT_ERROR_0
+#define VI1_FIRST_REG 0x0008 // VI_OUT_2_INCR_SYNCPT_0
+#define VI1_LAST_REG 0x000a // VI_OUT_2_INCR_SYNCPT_ERROR_0
+#define VI2_FIRST_REG 0x0010 // VI_MISC_INCR_SYNCPT_0
+#define VI2_LAST_REG 0x0012 // VI_MISC_INCR_SYNCPT_ERROR_0
+#define VI3_FIRST_REG 0x0018 // VI_CONT_SYNCPT_OUT_1_0
+#define VI3_LAST_REG 0x0098 // VI_RESERVE_4_0
+#define CSI0_FIRST_REG 0x0200 // CSI_VI_INPUT_STREAM_CONTROL_0
+#define CSI0_LAST_REG 0x0200 // CSI_VI_INPUT_STREAM_CONTROL_0
+#define CSI1_FIRST_REG 0x0202 // CSI_HOST_INPUT_STREAM_CONTROL_0
+#define CSI1_LAST_REG 0x0202 // CSI_HOST_INPUT_STREAM_CONTROL_0
+#define CSI2_FIRST_REG 0x0204 // CSI_INPUT_STREAM_A_CONTROL_0
+#define CSI2_LAST_REG 0x0204 // CSI_INPUT_STREAM_A_CONTROL_0
+#define CSI3_FIRST_REG 0x0206 // CSI_PIXEL_STREAM_A_CONTROL0_0
+#define CSI3_LAST_REG 0x020a // CSI_PIXEL_STREAM_PPA_COMMAND_0
+#define CSI4_FIRST_REG 0x020f // CSI_INPUT_STREAM_B_CONTROL_0
+#define CSI4_LAST_REG 0x020f // CSI_INPUT_STREAM_B_CONTROL_0
+#define CSI5_FIRST_REG 0x0211 // CSI_PIXEL_STREAM_B_CONTROL0_0
+#define CSI5_LAST_REG 0x0215 // CSI_PIXEL_STREAM_PPB_COMMAND_0
+#define CSI6_FIRST_REG 0x021a // CSI_PHY_CIL_COMMAND_0
+#define CSI6_LAST_REG 0x021c // CSI_PHY_CILB_CONTROL0_0
+#define CSI7_FIRST_REG 0x021e // CSI_CSI_PIXEL_PARSER_STATUS_0
+#define CSI7_LAST_REG 0x0234 // CSI_DSI_MIPI_CAL_CONFIG_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARVI_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap15/project_relocation_table.h b/arch/arm/mach-tegra/nv/include/ap15/project_relocation_table.h
new file mode 100644
index 000000000000..0dea12fce480
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap15/project_relocation_table.h
@@ -0,0 +1,555 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef PROJECT_AP15_RELOCATION_TABLE_SPEC_INC
+#define PROJECT_AP15_RELOCATION_TABLE_SPEC_INC
+
+// ------------------------------------------------------------
+//    hw nvdevids
+// ------------------------------------------------------------
+// Memory Aperture: Internal Memory
+#define NV_DEVID_IMEM                            1
+
+// Memory Aperture: External Memory
+#define NV_DEVID_EMEM                            2
+
+// Memory Aperture: TCRAM
+#define NV_DEVID_TCRAM                           3
+
+// Memory Aperture: IRAM
+#define NV_DEVID_IRAM                            4
+
+// Memory Aperture: NOR FLASH
+#define NV_DEVID_NOR                             5
+
+// Memory Aperture: EXIO
+#define NV_DEVID_EXIO                            6
+
+// Memory Aperture: GART
+#define NV_DEVID_GART                            7
+
+// Device Aperture: Graphics Host (HOST1X)
+#define NV_DEVID_HOST1X                          8
+
+// Device Aperture: ARM PERIPH registers
+#define NV_DEVID_ARM_PERIPH                      9
+
+// Device Aperture: MSELECT
+#define NV_DEVID_MSELECT                         10
+
+// Device Aperture: memory controller
+#define NV_DEVID_MC                              11
+
+// Device Aperture: external memory controller
+#define NV_DEVID_EMC                             12
+
+// Device Aperture: video input
+#define NV_DEVID_VI                              13
+
+// Device Aperture: encoder pre-processor
+#define NV_DEVID_EPP                             14
+
+// Device Aperture: video encoder
+#define NV_DEVID_MPE                             15
+
+// Device Aperture: 3D engine
+#define NV_DEVID_GR3D                            16
+
+// Device Aperture: 2D + SBLT engine
+#define NV_DEVID_GR2D                            17
+
+// Device Aperture: Image Signal Processor
+#define NV_DEVID_ISP                             18
+
+// Device Aperture: DISPLAY
+#define NV_DEVID_DISPLAY                         19
+
+// Device Aperture: UPTAG
+#define NV_DEVID_UPTAG                           20
+
+// Device Aperture - SHR_SEM
+#define NV_DEVID_SHR_SEM                         21
+
+// Device Aperture - ARB_SEM
+#define NV_DEVID_ARB_SEM                         22
+
+// Device Aperture - ARB_PRI
+#define NV_DEVID_ARB_PRI                         23
+
+// Obsoleted for AP15
+#define NV_DEVID_PRI_INTR                        24
+
+// Obsoleted for AP15
+#define NV_DEVID_SEC_INTR                        25
+
+// Device Aperture: Timer Programmable
+#define NV_DEVID_TMR                             26
+
+// Device Aperture: Clock and Reset
+#define NV_DEVID_CAR                             27
+
+// Device Aperture: Flow control
+#define NV_DEVID_FLOW                            28
+
+// Device Aperture: Event
+#define NV_DEVID_EVENT                           29
+
+// Device Aperture: AHB DMA
+#define NV_DEVID_AHB_DMA                         30
+
+// Device Aperture: APB DMA
+#define NV_DEVID_APB_DMA                         31
+
+// Device Aperture: COP Cache Controller
+#define NV_DEVID_COP_CACHE                       32
+
+// Obsolete - use COP_CACHE
+#define NV_DEVID_CC                              32
+
+// Obsolete - use COP_CACHE
+#define NV_DEVID_SYS_REG                         32
+
+// Device Aperture: System Statistic monitor
+#define NV_DEVID_STAT                            33
+
+// Device Aperture: GPIO
+#define NV_DEVID_GPIO                            34
+
+// Device Aperture: Vector Co-Processor 2
+#define NV_DEVID_VCP                             35
+
+// Device Aperture: Arm Vectors
+#define NV_DEVID_VECTOR                          36
+
+// Device: MEM
+#define NV_DEVID_MEM                             37
+
+// Obsolete - use VDE
+#define NV_DEVID_SXE                             38
+
+// Device Aperture: video decoder
+#define NV_DEVID_VDE                             38
+
+// Obsolete - use VDE
+#define NV_DEVID_BSEV                            39
+
+// Obsolete - use VDE
+#define NV_DEVID_MBE                             40
+
+// Obsolete - use VDE
+#define NV_DEVID_PPE                             41
+
+// Obsolete - use VDE
+#define NV_DEVID_MCE                             42
+
+// Obsolete - use VDE
+#define NV_DEVID_TFE                             43
+
+// Obsolete - use VDE
+#define NV_DEVID_PPB                             44
+
+// Obsolete - use VDE
+#define NV_DEVID_VDMA                            45
+
+// Obsolete - use VDE
+#define NV_DEVID_UCQ                             46
+
+// Device Aperture: BSEA (now in AVP cluster)
+#define NV_DEVID_BSEA                            47
+
+// Obsolete - use VDE
+#define NV_DEVID_FRAMEID                         48
+
+// Device Aperture: Misc regs
+#define NV_DEVID_MISC                            49
+
+// Device Aperture: AC97
+#define NV_DEVID_AC97                            50
+
+// Device Aperture: S/P-DIF
+#define NV_DEVID_SPDIF                           51
+
+// Device Aperture: I2S
+#define NV_DEVID_I2S                             52
+
+// Device Aperture: UART
+#define NV_DEVID_UART                            53
+
+// Device Aperture: VFIR
+#define NV_DEVID_VFIR                            54
+
+// Device Aperture: NAND Flash Controller
+#define NV_DEVID_NANDCTRL                        55
+
+// Obsolete - use NANDCTRL
+#define NV_DEVID_NANDFLASH                       55
+
+// Device Aperture: HSMMC
+#define NV_DEVID_HSMMC                           56
+
+// Device Aperture: XIO
+#define NV_DEVID_XIO                             57
+
+// Device Aperture: PWFM
+#define NV_DEVID_PWFM                            58
+
+// Device Aperture: MIPI
+#define NV_DEVID_MIPI_HS                         59
+
+// Device Aperture: I2C
+#define NV_DEVID_I2C                             60
+
+// Device Aperture: TWC
+#define NV_DEVID_TWC                             61
+
+// Device Aperture: SLINK
+#define NV_DEVID_SLINK                           62
+
+// Device Aperture: SLINK4B
+#define NV_DEVID_SLINK4B                         63
+
+// Device Aperture: SPI
+#define NV_DEVID_SPI                             64
+
+// Device Aperture: DVC
+#define NV_DEVID_DVC                             65
+
+// Device Aperture: RTC
+#define NV_DEVID_RTC                             66
+
+// Device Aperture: KeyBoard Controller
+#define NV_DEVID_KBC                             67
+
+// Device Aperture: PMIF
+#define NV_DEVID_PMIF                            68
+
+// Device Aperture: FUSE
+#define NV_DEVID_FUSE                            69
+
+// Device Aperture: L2 Cache Controller
+#define NV_DEVID_CMC                             70
+
+// Device Apertuer: NOR FLASH Controller
+#define NV_DEVID_NOR_REG                         71
+
+// Device Aperture: EIDE
+#define NV_DEVID_EIDE                            72
+
+// Device Aperture: USB
+#define NV_DEVID_USB                             73
+
+// Device Aperture: SDIO
+#define NV_DEVID_SDIO                            74
+
+// Device Aperture: TVO
+#define NV_DEVID_TVO                             75
+
+// Device Aperture: DSI
+#define NV_DEVID_DSI                             76
+
+// Device Aperture: HDMI
+#define NV_DEVID_HDMI                            77
+
+// Device Aperture: Third Interrupt Controller extra registers
+#define NV_DEVID_TRI_INTR                        78
+
+// Device Aperture: Common Interrupt Controller
+#define NV_DEVID_ICTLR                           79
+
+// Non-Aperture Interrupt: DMA TX interrupts
+#define NV_DEVID_DMA_TX_INTR                     80
+
+// Non-Aperture Interrupt: DMA RX interrupts
+#define NV_DEVID_DMA_RX_INTR                     81
+
+// Non-Aperture Interrupt: SW reserved interrupt
+#define NV_DEVID_SW_INTR                         82
+
+// Non-Aperture Interrupt: CPU PMU Interrupt
+#define NV_DEVID_CPU_INTR                        83
+
+// Device Aperture: Timer Free Running MicroSecond
+#define NV_DEVID_TMRUS                           84
+
+// Device Aperture: Interrupt Controller ARB_GNT Registers
+#define NV_DEVID_ICTLR_ARBGNT                    85
+
+// Device Aperture: Interrupt Controller DMA Registers
+#define NV_DEVID_ICTLR_DRQ                       86
+
+// Device Aperture: AHB DMA Channel
+#define NV_DEVID_AHB_DMA_CH                      87
+
+// Device Aperture: APB DMA Channel
+#define NV_DEVID_APB_DMA_CH                      88
+
+// Device Aperture: AHB Arbitration Controller
+#define NV_DEVID_AHB_ARBC                        89
+
+// Obsolete - use AHB_ARBC
+#define NV_DEVID_AHB_ARB_CTRL                    89
+
+// Device Aperture: AHB/APB Debug Bus Registers
+#define NV_DEVID_AHPBDEBUG                       91
+
+// Device Aperture: Secure Boot Register
+#define NV_DEVID_SECURE_BOOT                     92
+
+// Device Aperture: SPROM
+#define NV_DEVID_SPROM                           93
+
+// Memory Aperture: AHB external memory remapping
+#define NV_DEVID_AHB_EMEM                        94
+
+// Non-Aperture Interrupt: External PMU interrupt
+#define NV_DEVID_PMU_EXT                         95
+
+// Device Aperture: AHB EMEM to MC Flush Register
+#define NV_DEVID_PPCS                            96
+
+// Device Aperture: MMU TLB registers for COP/AVP
+#define NV_DEVID_MMU_TLB                         97
+
+// Device Aperture: OVG engine
+#define NV_DEVID_VG                              98
+
+// Device Aperture: CSI
+#define NV_DEVID_CSI                             99
+
+// Device ID for COP
+#define NV_DEVID_AVP                             100
+
+// Device ID for MPCORE
+#define NV_DEVID_CPU                             101
+
+// Device Aperture: ULPI controller
+#define NV_DEVID_ULPI                            102
+
+// Device Aperture: ARM CONFIG registers
+#define NV_DEVID_ARM_CONFIG                      103
+
+// Device Aperture: ARM PL310 (L2 controller)
+#define NV_DEVID_ARM_PL310                       104
+
+// Device Aperture: PCIe
+#define NV_DEVID_PCIE                            105
+
+// Device Aperture: OWR (one wire)
+#define NV_DEVID_OWR                             106
+
+// Device Aperture: AVPUCQ
+#define NV_DEVID_AVPUCQ                          107
+
+// Device Aperture: AVPBSEA (obsolete)
+#define NV_DEVID_AVPBSEA                         108
+
+// Device Aperture: Sync NOR
+#define NV_DEVID_SNOR                            109
+
+// Device Aperture: SDMMC
+#define NV_DEVID_SDMMC                           110
+
+// Device Aperture: KFUSE
+#define NV_DEVID_KFUSE                           111
+
+// Device Aperture: CSITE
+#define NV_DEVID_CSITE                           112
+
+// Non-Aperture Interrupt: ARM Interprocessor Interrupt
+#define NV_DEVID_ARM_IPI                         113
+
+// Device Aperture: ARM Interrupts 0-31
+#define NV_DEVID_ARM_ICTLR                       114
+
+// Device Aperture: IOBIST
+#define NV_DEVID_IOBIST                          115
+
+// Device Aperture: SPEEDO
+#define NV_DEVID_SPEEDO                          116
+
+// Device Aperture: LA
+#define NV_DEVID_LA                              117
+
+// Device Aperture: VS
+#define NV_DEVID_VS                              118
+
+// Device Aperture: VCI
+#define NV_DEVID_VCI                             119
+
+// Device Aperture: APBIF
+#define NV_DEVID_APBIF                           120
+
+// Device Aperture: AHUB
+#define NV_DEVID_AHUB                            121
+
+// Device Aperture: DAM
+#define NV_DEVID_DAM                             122
+
+// ------------------------------------------------------------
+//    hw powergroups
+// ------------------------------------------------------------
+// Always On
+#define NV_POWERGROUP_AO                         0
+
+// Main
+#define NV_POWERGROUP_NPG                        1
+
+// CPU related blocks
+#define NV_POWERGROUP_CPU                        2
+
+// 3D graphics
+#define NV_POWERGROUP_TD                         3
+
+// Video encode engine blocks
+#define NV_POWERGROUP_VE                         4
+
+// PCIe
+#define NV_POWERGROUP_PCIE                       5
+
+// Video decoder
+#define NV_POWERGROUP_VDE                        6
+
+// MPEG encoder
+#define NV_POWERGROUP_MPE                        7
+
+// SW define for Power Group maximum
+#define NV_POWERGROUP_MAX                        8
+
+// non-mapped power group
+#define NV_POWERGROUP_INVALID                    0xffff
+
+// SW table for mapping power group define to register enums (NV_POWERGROUP_INVALID = no mapping)
+//  use as 'int table[NV_POWERGROUP_MAX] = { NV_POWERGROUP_ENUM_TABLE }'
+#define NV_POWERGROUP_ENUM_TABLE                 NV_POWERGROUP_INVALID, NV_POWERGROUP_INVALID, 0, 1, 2, NV_POWERGROUP_INVALID, NV_POWERGROUP_INVALID, NV_POWERGROUP_INVALID
+
+// ------------------------------------------------------------
+//    relocation table data (stored in boot rom)
+// ------------------------------------------------------------
+// relocation table pointer stored at NV_RELOCATION_TABLE_OFFSET
+#define NV_RELOCATION_TABLE_PTR_OFFSET 64
+#define NV_RELOCATION_TABLE_SIZE  472
+#define NV_RELOCATION_TABLE_INIT \
+          0x00000001, 0x00020010, 0x00000000, 0x40000000, 0x005f1010, \
+          0x00000000, 0x00000000, 0x00531010, 0x00000000, 0x00000000, \
+          0x00521010, 0x00000000, 0x00000000, 0x00040010, 0x40000000, \
+          0x00008000, 0x00040010, 0x40008000, 0x00008000, 0x00040010, \
+          0x40010000, 0x00008000, 0x00040010, 0x40018000, 0x00008000, \
+          0x00081010, 0x50000000, 0x00024000, 0x00091020, 0x50040000, \
+          0x00002000, 0x000a1020, 0x50042000, 0x00001000, 0x000f1140, \
+          0x54040000, 0x00040000, 0x00631040, 0x54080000, 0x00040000, \
+          0x000d1140, 0x54080000, 0x00040000, 0x000e1040, 0x540c0000, \
+          0x00040000, 0x00121040, 0x54100000, 0x00040000, 0x00111010, \
+          0x54140000, 0x00040000, 0x00101230, 0x54180000, 0x00040000, \
+          0x00131210, 0x54200000, 0x00040000, 0x00131210, 0x54240000, \
+          0x00040000, 0x004d1110, 0x54280000, 0x00040000, 0x004b1010, \
+          0x542c0000, 0x00040000, 0x004c1010, 0x54300000, 0x00040000, \
+          0x00070010, 0x58000000, 0x01000000, 0x00141010, 0x60000000, \
+          0x00001000, 0x00151010, 0x60001000, 0x00001000, 0x00161010, \
+          0x60002000, 0x00001000, 0x00171010, 0x60003000, 0x00001000, \
+          0x004f1010, 0x60004000, 0x00000040, 0x00551010, 0x60004040, \
+          0x000000c0, 0x004f1110, 0x60004100, 0x00000040, 0x00561010, \
+          0x60004140, 0x00000008, 0x00561110, 0x60004148, 0x00000008, \
+          0x004f1210, 0x60004200, 0x00000040, 0x001a1010, 0x60005000, \
+          0x00000008, 0x001a1010, 0x60005008, 0x00000008, 0x00541010, \
+          0x60005010, 0x00000040, 0x001a1010, 0x60005050, 0x00000008, \
+          0x001a1010, 0x60005058, 0x00000008, 0x001b1110, 0x60006000, \
+          0x00001000, 0x001c1010, 0x60007000, 0x00000014, 0x001e1110, \
+          0x60008000, 0x00001000, 0x00571010, 0x60009000, 0x00000020, \
+          0x00571010, 0x60009020, 0x00000020, 0x00571010, 0x60009040, \
+          0x00000020, 0x00571010, 0x60009060, 0x00000020, 0x001f1010, \
+          0x6000a000, 0x00001000, 0x00581010, 0x6000b000, 0x00000020, \
+          0x00581010, 0x6000b020, 0x00000020, 0x00581010, 0x6000b040, \
+          0x00000020, 0x00581010, 0x6000b060, 0x00000020, 0x00581010, \
+          0x6000b080, 0x00000020, 0x00581010, 0x6000b0a0, 0x00000020, \
+          0x00581010, 0x6000b0c0, 0x00000020, 0x00581010, 0x6000b0e0, \
+          0x00000020, 0x00581010, 0x6000b100, 0x00000020, 0x00581010, \
+          0x6000b120, 0x00000020, 0x00581010, 0x6000b140, 0x00000020, \
+          0x00581010, 0x6000b160, 0x00000020, 0x00581010, 0x6000b180, \
+          0x00000020, 0x00581010, 0x6000b1a0, 0x00000020, 0x00581010, \
+          0x6000b1c0, 0x00000020, 0x00581010, 0x6000b1e0, 0x00000020, \
+          0x00201010, 0x6000c000, 0x00000400, 0x00591010, 0x6000c004, \
+          0x0000010c, 0x005b1010, 0x6000c150, 0x000000a6, 0x005c1010, \
+          0x6000c200, 0x00000004, 0x00211010, 0x6000c400, 0x00000400, \
+          0x00222010, 0x6000d000, 0x00000880, 0x00222010, 0x6000d080, \
+          0x00000880, 0x00222010, 0x6000d100, 0x00000880, 0x00222010, \
+          0x6000d180, 0x00000880, 0x00222010, 0x6000d200, 0x00000880, \
+          0x00222010, 0x6000d280, 0x00000880, 0x00231010, 0x6000e000, \
+          0x00001000, 0x00241010, 0x6000f000, 0x00001000, 0x002f1010, \
+          0x6001a000, 0x00003b00, 0x00261110, 0x6001a000, 0x00003b00, \
+          0x00311110, 0x70000000, 0x00001000, 0x00321010, 0x70002000, \
+          0x00000200, 0x00331010, 0x70002400, 0x00000200, 0x00341010, \
+          0x70002800, 0x00000100, 0x00341010, 0x70002a00, 0x00000100, \
+          0x00351110, 0x70006000, 0x00000040, 0x00351110, 0x70006040, \
+          0x00000040, 0x00361010, 0x70006100, 0x00000100, 0x00351110, \
+          0x70006200, 0x00000100, 0x00371110, 0x70008000, 0x00000100, \
+          0x00381010, 0x70008500, 0x00000100, 0x00391010, 0x70008a00, \
+          0x00000200, 0x003a1010, 0x7000a000, 0x00000100, 0x003b1010, \
+          0x7000b000, 0x00000100, 0x003c1110, 0x7000c000, 0x00000100, \
+          0x003d1010, 0x7000c100, 0x00000100, 0x00401010, 0x7000c380, \
+          0x00000030, 0x003c1110, 0x7000c400, 0x00000100, 0x00411010, \
+          0x7000d000, 0x00000200, 0x003f1010, 0x7000d300, 0x00000100, \
+          0x003e1010, 0x7000d400, 0x00000200, 0x003e1010, 0x7000d600, \
+          0x00000200, 0x003e1010, 0x7000d800, 0x00000200, 0x00421000, \
+          0x7000e000, 0x00000100, 0x00431000, 0x7000e200, 0x00000100, \
+          0x00441000, 0x7000e400, 0x00000100, 0x00461010, 0x7000e800, \
+          0x00000200, 0x005d1010, 0x7000ec00, 0x00000100, 0x000b1010, \
+          0x7000f000, 0x00000400, 0x000c1110, 0x7000f400, 0x00000400, \
+          0x00451110, 0x7000f800, 0x00000400, 0x00050010, 0x80000000, \
+          0x10000000, 0x005e0010, 0x90000000, 0x20000000, 0x00060010, \
+          0xb0000000, 0x08000000, 0x00060010, 0xb8000000, 0x08000000, \
+          0x00481010, 0xc3000000, 0x01000000, 0x00601010, 0xc4000000, \
+          0x00010000, 0x00491110, 0xc5000000, 0x00002000, 0x004a1010, \
+          0xc8000000, 0x00000100, 0x004a1010, 0xc8000100, 0x00000100, \
+          0x00611010, 0xf000f000, 0x00001000, 0x00000000, 0x82100116, \
+          0x81e00218, 0x8210031f, 0xc2100800, 0xa2100801, 0xc2100802, \
+          0xa2100803, 0x82100b04, 0x82100d05, 0x82100e06, 0x82100f07, \
+          0x82101008, 0x82101209, 0x8210130a, 0x8210140b, 0x8210150c, \
+          0xa1c01904, 0xc1c01905, 0xc1c01906, 0xa1c01907, 0xa1c01a1d, \
+          0xc1c01a1c, 0x81e01f1e, 0x81e0201f, 0x81c02200, 0x81c02301, \
+          0x81e02509, 0x81e0260a, 0xa1e0280b, 0xc1e0280c, 0xa1c0291b, \
+          0xc1e0291d, 0xa1c02e1a, 0xc1e02e1c, 0x81e04316, 0x81e04400, \
+          0x81e04501, 0x81e04602, 0x81e04703, 0x81e04817, 0x82104917, \
+          0x81c04a19, 0x81c04d09, 0x81c04d0a, 0x81c04d0b, 0x81c04d0c, \
+          0x81c04d08, 0x81c04d11, 0x82104e10, 0x82104e18, 0x82104f11, \
+          0x81f04f00, 0x81f04f12, 0x82004f00, 0x82004f12, 0x81e0500d, \
+          0x81f05003, 0x81f05004, 0x82005003, 0x82005004, 0x81c0510d, \
+          0x81f05102, 0x81f05101, 0x82005101, 0x82005102, 0x81c05203, \
+          0x81f05206, 0x81f05205, 0x82005205, 0x82005206, 0x81e05304, \
+          0x81f05308, 0x82005308, 0x81e05405, 0x81f05409, 0x82005409, \
+          0x81e05514, 0x81f05511, 0x82005511, 0x81e0560e, 0x81f0560a, \
+          0x8200560a, 0x81c05718, 0x81c05816, 0x81c05910, 0x81e05b0f, \
+          0x81e05c06, 0x81f05c0c, 0x82005c0c, 0x81e05d08, 0x81f05d0b, \
+          0x82005d0b, 0x81e05e07, 0x81f05e07, 0x82005e07, 0x82105f14, \
+          0x81f05f0d, 0x82005f0d, 0x81e06015, 0x81e0611a, 0x81e0621b, \
+          0x82106312, 0x82106413, 0x81c06502, 0x82106615, 0x8210680f, \
+          0x82106a0d, 0x82106b0e, 0x81c07117, 0x81c07314, 0x81c0740e, \
+          0x81c0750f, 0x00000000
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arafi.h b/arch/arm/mach-tegra/nv/include/ap20/arafi.h
new file mode 100644
index 000000000000..1be73682f4fe
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arafi.h
@@ -0,0 +1,2914 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAFI_H_INC_
+#define ___ARAFI_H_INC_
+
+// Register AFI_AXI_BAR0_SZ_0  
+#define AFI_AXI_BAR0_SZ_0                       _MK_ADDR_CONST(0x0)
+#define AFI_AXI_BAR0_SZ_0_SECURE                        0x0
+#define AFI_AXI_BAR0_SZ_0_WORD_COUNT                    0x1
+#define AFI_AXI_BAR0_SZ_0_RESET_VAL                     _MK_MASK_CONST(0x40000)
+#define AFI_AXI_BAR0_SZ_0_RESET_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR0_SZ_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR0_SZ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR0_SZ_0_READ_MASK                     _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR0_SZ_0_WRITE_MASK                    _MK_MASK_CONST(0xfffff)
+//The size of the address range associated with BARi is in 4K increments.  
+//Value of 0 signifies BARi is not used.
+#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_FIELD                   (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_SHIFT)
+#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_RANGE                   19:0
+#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_WOFFSET                 0x0
+#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_DEFAULT                 _MK_MASK_CONST(0x40000)
+#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR0_SZ_0_AXI_BAR0_SIZE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AXI_BAR1_SZ_0  
+#define AFI_AXI_BAR1_SZ_0                       _MK_ADDR_CONST(0x4)
+#define AFI_AXI_BAR1_SZ_0_SECURE                        0x0
+#define AFI_AXI_BAR1_SZ_0_WORD_COUNT                    0x1
+#define AFI_AXI_BAR1_SZ_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR1_SZ_0_RESET_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR1_SZ_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR1_SZ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR1_SZ_0_READ_MASK                     _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR1_SZ_0_WRITE_MASK                    _MK_MASK_CONST(0xfffff)
+//The size of the address range associated with BARi is in 4K increments.
+//Value of 0 signifies BARi is not used.
+#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_FIELD                   (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_SHIFT)
+#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_RANGE                   19:0
+#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_WOFFSET                 0x0
+#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR1_SZ_0_AXI_BAR1_SIZE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AXI_BAR2_SZ_0  
+#define AFI_AXI_BAR2_SZ_0                       _MK_ADDR_CONST(0x8)
+#define AFI_AXI_BAR2_SZ_0_SECURE                        0x0
+#define AFI_AXI_BAR2_SZ_0_WORD_COUNT                    0x1
+#define AFI_AXI_BAR2_SZ_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR2_SZ_0_RESET_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR2_SZ_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR2_SZ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR2_SZ_0_READ_MASK                     _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR2_SZ_0_WRITE_MASK                    _MK_MASK_CONST(0xfffff)
+//The size of the address range associated with BARi is in 4K increments. 
+//Value of 0 signifies BARi is not used.
+#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_FIELD                   (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_SHIFT)
+#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_RANGE                   19:0
+#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_WOFFSET                 0x0
+#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR2_SZ_0_AXI_BAR2_SIZE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AXI_BAR3_SZ_0  
+#define AFI_AXI_BAR3_SZ_0                       _MK_ADDR_CONST(0xc)
+#define AFI_AXI_BAR3_SZ_0_SECURE                        0x0
+#define AFI_AXI_BAR3_SZ_0_WORD_COUNT                    0x1
+#define AFI_AXI_BAR3_SZ_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR3_SZ_0_RESET_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR3_SZ_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR3_SZ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR3_SZ_0_READ_MASK                     _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR3_SZ_0_WRITE_MASK                    _MK_MASK_CONST(0xfffff)
+//The size of the address range associated with BARi is in 4K increments.
+//Value of 0 signifies BARi is not used.
+#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_FIELD                   (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_SHIFT)
+#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_RANGE                   19:0
+#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_WOFFSET                 0x0
+#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR3_SZ_0_AXI_BAR3_SIZE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AXI_BAR4_SZ_0  
+#define AFI_AXI_BAR4_SZ_0                       _MK_ADDR_CONST(0x10)
+#define AFI_AXI_BAR4_SZ_0_SECURE                        0x0
+#define AFI_AXI_BAR4_SZ_0_WORD_COUNT                    0x1
+#define AFI_AXI_BAR4_SZ_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR4_SZ_0_RESET_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR4_SZ_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR4_SZ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR4_SZ_0_READ_MASK                     _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR4_SZ_0_WRITE_MASK                    _MK_MASK_CONST(0xfffff)
+//The size of the address range associated with BARi is in 4K increments.
+//Value of 0 signifies BARi is not used.
+#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_FIELD                   (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_SHIFT)
+#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_RANGE                   19:0
+#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_WOFFSET                 0x0
+#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR4_SZ_0_AXI_BAR4_SIZE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AXI_BAR5_SZ_0  
+#define AFI_AXI_BAR5_SZ_0                       _MK_ADDR_CONST(0x14)
+#define AFI_AXI_BAR5_SZ_0_SECURE                        0x0
+#define AFI_AXI_BAR5_SZ_0_WORD_COUNT                    0x1
+#define AFI_AXI_BAR5_SZ_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR5_SZ_0_RESET_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR5_SZ_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR5_SZ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR5_SZ_0_READ_MASK                     _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR5_SZ_0_WRITE_MASK                    _MK_MASK_CONST(0xfffff)
+//The size of the address range associated with BARi is in 4K increments.
+//Value of 0 signifies BARi is not used.
+#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_FIELD                   (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_SHIFT)
+#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_RANGE                   19:0
+#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_WOFFSET                 0x0
+#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_DEFAULT_MASK                    _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR5_SZ_0_AXI_BAR5_SIZE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AXI_BAR0_START_0  
+#define AFI_AXI_BAR0_START_0                    _MK_ADDR_CONST(0x18)
+#define AFI_AXI_BAR0_START_0_SECURE                     0x0
+#define AFI_AXI_BAR0_START_0_WORD_COUNT                         0x1
+#define AFI_AXI_BAR0_START_0_RESET_VAL                  _MK_MASK_CONST(0x80000000)
+#define AFI_AXI_BAR0_START_0_RESET_MASK                         _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR0_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR0_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR0_START_0_READ_MASK                  _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR0_START_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff000)
+//The start of AXI address space for BARi.  
+//The AXI target address is compared to start/size for each BAR 
+//to determine if the access is to that BAR.
+#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_SHIFT                       _MK_SHIFT_CONST(12)
+#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_FIELD                       (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR0_START_0_AXI_BAR0_START_SHIFT)
+#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_RANGE                       31:12
+#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_WOFFSET                     0x0
+#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_DEFAULT                     _MK_MASK_CONST(0x80000)
+#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR0_START_0_AXI_BAR0_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AXI_BAR1_START_0  
+#define AFI_AXI_BAR1_START_0                    _MK_ADDR_CONST(0x1c)
+#define AFI_AXI_BAR1_START_0_SECURE                     0x0
+#define AFI_AXI_BAR1_START_0_WORD_COUNT                         0x1
+#define AFI_AXI_BAR1_START_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR1_START_0_RESET_MASK                         _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR1_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR1_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR1_START_0_READ_MASK                  _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR1_START_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff000)
+//The start of AXI address space for BARi.  
+//The AXI target address is compared to start/size for each BAR 
+//to determine if the access is to that BAR.
+#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_SHIFT                       _MK_SHIFT_CONST(12)
+#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_FIELD                       (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR1_START_0_AXI_BAR1_START_SHIFT)
+#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_RANGE                       31:12
+#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_WOFFSET                     0x0
+#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR1_START_0_AXI_BAR1_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AXI_BAR2_START_0  
+#define AFI_AXI_BAR2_START_0                    _MK_ADDR_CONST(0x20)
+#define AFI_AXI_BAR2_START_0_SECURE                     0x0
+#define AFI_AXI_BAR2_START_0_WORD_COUNT                         0x1
+#define AFI_AXI_BAR2_START_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR2_START_0_RESET_MASK                         _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR2_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR2_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR2_START_0_READ_MASK                  _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR2_START_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff000)
+//The start of AXI address space for BARi.  
+//The AXI target address is compared to start/size for each BAR 
+//to determine if the access is to that BAR.
+#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_SHIFT                       _MK_SHIFT_CONST(12)
+#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_FIELD                       (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR2_START_0_AXI_BAR2_START_SHIFT)
+#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_RANGE                       31:12
+#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_WOFFSET                     0x0
+#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR2_START_0_AXI_BAR2_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AXI_BAR3_START_0  
+#define AFI_AXI_BAR3_START_0                    _MK_ADDR_CONST(0x24)
+#define AFI_AXI_BAR3_START_0_SECURE                     0x0
+#define AFI_AXI_BAR3_START_0_WORD_COUNT                         0x1
+#define AFI_AXI_BAR3_START_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR3_START_0_RESET_MASK                         _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR3_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR3_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR3_START_0_READ_MASK                  _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR3_START_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff000)
+//The start of AXI address space for BARi.  
+//The AXI target address is compared to start/size for each BAR 
+//to determine if the access is to that BAR.
+#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_SHIFT                       _MK_SHIFT_CONST(12)
+#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_FIELD                       (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR3_START_0_AXI_BAR3_START_SHIFT)
+#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_RANGE                       31:12
+#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_WOFFSET                     0x0
+#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR3_START_0_AXI_BAR3_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AXI_BAR4_START_0  
+#define AFI_AXI_BAR4_START_0                    _MK_ADDR_CONST(0x28)
+#define AFI_AXI_BAR4_START_0_SECURE                     0x0
+#define AFI_AXI_BAR4_START_0_WORD_COUNT                         0x1
+#define AFI_AXI_BAR4_START_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR4_START_0_RESET_MASK                         _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR4_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR4_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR4_START_0_READ_MASK                  _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR4_START_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff000)
+//The start of AXI address space for BARi.  
+//The AXI target address is compared to start/size for each BAR 
+//to determine if the access is to that BAR.
+#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_SHIFT                       _MK_SHIFT_CONST(12)
+#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_FIELD                       (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR4_START_0_AXI_BAR4_START_SHIFT)
+#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_RANGE                       31:12
+#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_WOFFSET                     0x0
+#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR4_START_0_AXI_BAR4_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AXI_BAR5_START_0  
+#define AFI_AXI_BAR5_START_0                    _MK_ADDR_CONST(0x2c)
+#define AFI_AXI_BAR5_START_0_SECURE                     0x0
+#define AFI_AXI_BAR5_START_0_WORD_COUNT                         0x1
+#define AFI_AXI_BAR5_START_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR5_START_0_RESET_MASK                         _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR5_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR5_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR5_START_0_READ_MASK                  _MK_MASK_CONST(0xfffff000)
+#define AFI_AXI_BAR5_START_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff000)
+//The start of AXI address space for BARi.  
+//The AXI target address is compared to start/size for each BAR 
+//to determine if the access is to that BAR.
+#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_SHIFT                       _MK_SHIFT_CONST(12)
+#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_FIELD                       (_MK_MASK_CONST(0xfffff) << AFI_AXI_BAR5_START_0_AXI_BAR5_START_SHIFT)
+#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_RANGE                       31:12
+#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_WOFFSET                     0x0
+#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
+#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AXI_BAR5_START_0_AXI_BAR5_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_FPCI_BAR0_0  
+#define AFI_FPCI_BAR0_0                 _MK_ADDR_CONST(0x30)
+#define AFI_FPCI_BAR0_0_SECURE                  0x0
+#define AFI_FPCI_BAR0_0_WORD_COUNT                      0x1
+#define AFI_FPCI_BAR0_0_RESET_VAL                       _MK_MASK_CONST(0x800001)
+#define AFI_FPCI_BAR0_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR0_0_READ_MASK                       _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR0_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff1)
+//The start of FPCI address space mapped into the BARi 
+//range of PCI memory space.  The 40-bit FPCI address is determined
+//by a a shift left 8 of the value of this register.
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_SHIFT                   _MK_SHIFT_CONST(4)
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_FIELD                   (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR0_0_FPCI_BAR0_START_SHIFT)
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_RANGE                   31:4
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_WOFFSET                 0x0
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_DEFAULT                 _MK_MASK_CONST(0x80000)
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_DEFAULT_MASK                    _MK_MASK_CONST(0xfffffff)
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Indicates if the address region is memory
+//mapped versus configuration or IO space.
+//1=memory mapped access (PW only)
+//0=IO/config access (NWP only)
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_FIELD                     (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_SHIFT)
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_RANGE                     0:0
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_WOFFSET                   0x0
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR0_0_FPCI_BAR0_ACCESS_TYPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_FPCI_BAR1_0  
+#define AFI_FPCI_BAR1_0                 _MK_ADDR_CONST(0x34)
+#define AFI_FPCI_BAR1_0_SECURE                  0x0
+#define AFI_FPCI_BAR1_0_WORD_COUNT                      0x1
+#define AFI_FPCI_BAR1_0_RESET_VAL                       _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR1_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR1_0_READ_MASK                       _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR1_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff1)
+//The start of FPCI address space mapped into the BARi 
+//range of PCI memory space.  The 40-bit FPCI address is determined
+//by a a shift left 8 of the value of this register.
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_SHIFT                   _MK_SHIFT_CONST(4)
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_FIELD                   (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR1_0_FPCI_BAR1_START_SHIFT)
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_RANGE                   31:4
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_WOFFSET                 0x0
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_DEFAULT_MASK                    _MK_MASK_CONST(0xfffffff)
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Indicates if the address region is memory
+//mapped versus configuration or IO space.
+//1=memory mapped access (PW only)
+//0=IO/config access (NWP only)
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_FIELD                     (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_SHIFT)
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_RANGE                     0:0
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_WOFFSET                   0x0
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR1_0_FPCI_BAR1_ACCESS_TYPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_FPCI_BAR2_0  
+#define AFI_FPCI_BAR2_0                 _MK_ADDR_CONST(0x38)
+#define AFI_FPCI_BAR2_0_SECURE                  0x0
+#define AFI_FPCI_BAR2_0_WORD_COUNT                      0x1
+#define AFI_FPCI_BAR2_0_RESET_VAL                       _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR2_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR2_0_READ_MASK                       _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR2_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff1)
+//The start of FPCI address space mapped into the BARi 
+//range of PCI memory space.  The 40-bit FPCI address is determined
+//by a a shift left 8 of the value of this register.
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_SHIFT                   _MK_SHIFT_CONST(4)
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_FIELD                   (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR2_0_FPCI_BAR2_START_SHIFT)
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_RANGE                   31:4
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_WOFFSET                 0x0
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_DEFAULT_MASK                    _MK_MASK_CONST(0xfffffff)
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Indicates if the address region is memory
+//mapped versus configuration or IO space.
+//1=memory mapped access (PW only)
+//0=IO/config access (NWP only)
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_FIELD                     (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_SHIFT)
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_RANGE                     0:0
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_WOFFSET                   0x0
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR2_0_FPCI_BAR2_ACCESS_TYPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_FPCI_BAR3_0  
+#define AFI_FPCI_BAR3_0                 _MK_ADDR_CONST(0x3c)
+#define AFI_FPCI_BAR3_0_SECURE                  0x0
+#define AFI_FPCI_BAR3_0_WORD_COUNT                      0x1
+#define AFI_FPCI_BAR3_0_RESET_VAL                       _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR3_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR3_0_READ_MASK                       _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR3_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff1)
+//The start of FPCI address space mapped into the BARi 
+//range of PCI memory space.  The 40-bit FPCI address is determined
+//by a a shift left 8 of the value of this register.
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_SHIFT                   _MK_SHIFT_CONST(4)
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_FIELD                   (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR3_0_FPCI_BAR3_START_SHIFT)
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_RANGE                   31:4
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_WOFFSET                 0x0
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_DEFAULT_MASK                    _MK_MASK_CONST(0xfffffff)
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Indicates if the address region is memory
+//mapped versus configuration or IO space.
+//1=memory mapped access (PW only)
+//0=IO/config access (NWP only)
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_FIELD                     (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_SHIFT)
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_RANGE                     0:0
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_WOFFSET                   0x0
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR3_0_FPCI_BAR3_ACCESS_TYPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_FPCI_BAR4_0  
+#define AFI_FPCI_BAR4_0                 _MK_ADDR_CONST(0x40)
+#define AFI_FPCI_BAR4_0_SECURE                  0x0
+#define AFI_FPCI_BAR4_0_WORD_COUNT                      0x1
+#define AFI_FPCI_BAR4_0_RESET_VAL                       _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR4_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR4_0_READ_MASK                       _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR4_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff1)
+//The start of FPCI address space mapped into the BARi 
+//range of PCI memory space.  The 40-bit FPCI address is determined
+//by a a shift left 8 of the value of this register.
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_SHIFT                   _MK_SHIFT_CONST(4)
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_FIELD                   (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR4_0_FPCI_BAR4_START_SHIFT)
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_RANGE                   31:4
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_WOFFSET                 0x0
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_DEFAULT_MASK                    _MK_MASK_CONST(0xfffffff)
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Indicates if the address region is memory
+//mapped versus configuration or IO space.
+//1=memory mapped access (PW only)
+//0=IO/config access (NWP only)
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_FIELD                     (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_SHIFT)
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_RANGE                     0:0
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_WOFFSET                   0x0
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR4_0_FPCI_BAR4_ACCESS_TYPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_FPCI_BAR5_0  
+#define AFI_FPCI_BAR5_0                 _MK_ADDR_CONST(0x44)
+#define AFI_FPCI_BAR5_0_SECURE                  0x0
+#define AFI_FPCI_BAR5_0_WORD_COUNT                      0x1
+#define AFI_FPCI_BAR5_0_RESET_VAL                       _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR5_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR5_0_READ_MASK                       _MK_MASK_CONST(0xfffffff1)
+#define AFI_FPCI_BAR5_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff1)
+//The start of FPCI address space mapped into the BARi 
+//range of PCI memory space.  The 40-bit FPCI address is determined
+//by a a shift left 8 of the value of this register.
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_SHIFT                   _MK_SHIFT_CONST(4)
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_FIELD                   (_MK_MASK_CONST(0xfffffff) << AFI_FPCI_BAR5_0_FPCI_BAR5_START_SHIFT)
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_RANGE                   31:4
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_WOFFSET                 0x0
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_DEFAULT_MASK                    _MK_MASK_CONST(0xfffffff)
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_START_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Indicates if the address region is memory
+//mapped versus configuration or IO space.
+//1=memory mapped access (PW only)
+//0=IO/config access (NWP only)
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_FIELD                     (_MK_MASK_CONST(0x1) << AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_SHIFT)
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_RANGE                     0:0
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_WOFFSET                   0x0
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_FPCI_BAR5_0_FPCI_BAR5_ACCESS_TYPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_CACHE_BAR0_SZ_0  
+#define AFI_CACHE_BAR0_SZ_0                     _MK_ADDR_CONST(0x48)
+#define AFI_CACHE_BAR0_SZ_0_SECURE                      0x0
+#define AFI_CACHE_BAR0_SZ_0_WORD_COUNT                  0x1
+#define AFI_CACHE_BAR0_SZ_0_RESET_VAL                   _MK_MASK_CONST(0x40000)
+#define AFI_CACHE_BAR0_SZ_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
+#define AFI_CACHE_BAR0_SZ_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR0_SZ_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR0_SZ_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
+#define AFI_CACHE_BAR0_SZ_0_WRITE_MASK                  _MK_MASK_CONST(0xfffff)
+//The size of the address range associated with cache BAR is in 
+//4K increments.  Value of 0 signifies BAR is not used.
+#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_SHIFT                       _MK_SHIFT_CONST(0)
+#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_FIELD                       (_MK_MASK_CONST(0xfffff) << AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_SHIFT)
+#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_RANGE                       19:0
+#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_WOFFSET                     0x0
+#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_DEFAULT                     _MK_MASK_CONST(0x40000)
+#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
+#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR0_SZ_0_CACHE_BAR0_SIZE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_CACHE_BAR0_ST_0  
+#define AFI_CACHE_BAR0_ST_0                     _MK_ADDR_CONST(0x4c)
+#define AFI_CACHE_BAR0_ST_0_SECURE                      0x0
+#define AFI_CACHE_BAR0_ST_0_WORD_COUNT                  0x1
+#define AFI_CACHE_BAR0_ST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR0_ST_0_RESET_MASK                  _MK_MASK_CONST(0xfffff000)
+#define AFI_CACHE_BAR0_ST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR0_ST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR0_ST_0_READ_MASK                   _MK_MASK_CONST(0xfffff000)
+#define AFI_CACHE_BAR0_ST_0_WRITE_MASK                  _MK_MASK_CONST(0xfffff000)
+//The start of AXI address space for CACHE BAR.  
+//The AXI initiator address is compared to start/size 
+//for CACHE BAR to determine if the access is to the BAR.
+#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_SHIFT                      _MK_SHIFT_CONST(12)
+#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_FIELD                      (_MK_MASK_CONST(0xfffff) << AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_SHIFT)
+#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_RANGE                      31:12
+#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_WOFFSET                    0x0
+#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_DEFAULT_MASK                       _MK_MASK_CONST(0xfffff)
+#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR0_ST_0_CACHE_BAR0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_CACHE_BAR1_SZ_0  
+#define AFI_CACHE_BAR1_SZ_0                     _MK_ADDR_CONST(0x50)
+#define AFI_CACHE_BAR1_SZ_0_SECURE                      0x0
+#define AFI_CACHE_BAR1_SZ_0_WORD_COUNT                  0x1
+#define AFI_CACHE_BAR1_SZ_0_RESET_VAL                   _MK_MASK_CONST(0x40000)
+#define AFI_CACHE_BAR1_SZ_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
+#define AFI_CACHE_BAR1_SZ_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR1_SZ_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR1_SZ_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
+#define AFI_CACHE_BAR1_SZ_0_WRITE_MASK                  _MK_MASK_CONST(0xfffff)
+//The size of the address range associated with cache BAR is in 
+//4K increments.  Value of 0 signifies BAR is not used.
+#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_SHIFT                       _MK_SHIFT_CONST(0)
+#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_FIELD                       (_MK_MASK_CONST(0xfffff) << AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_SHIFT)
+#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_RANGE                       19:0
+#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_WOFFSET                     0x0
+#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_DEFAULT                     _MK_MASK_CONST(0x40000)
+#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
+#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR1_SZ_0_CACHE_BAR1_SIZE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_CACHE_BAR1_ST_0  
+#define AFI_CACHE_BAR1_ST_0                     _MK_ADDR_CONST(0x54)
+#define AFI_CACHE_BAR1_ST_0_SECURE                      0x0
+#define AFI_CACHE_BAR1_ST_0_WORD_COUNT                  0x1
+#define AFI_CACHE_BAR1_ST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR1_ST_0_RESET_MASK                  _MK_MASK_CONST(0xfffff000)
+#define AFI_CACHE_BAR1_ST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR1_ST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR1_ST_0_READ_MASK                   _MK_MASK_CONST(0xfffff000)
+#define AFI_CACHE_BAR1_ST_0_WRITE_MASK                  _MK_MASK_CONST(0xfffff000)
+//The start of AXI address space for CACHE BAR.  
+//The AXI initiator address is compared to start/size 
+//for CACHE BAR to determine if the access is to the BAR.
+#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_SHIFT                      _MK_SHIFT_CONST(12)
+#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_FIELD                      (_MK_MASK_CONST(0xfffff) << AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_SHIFT)
+#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_RANGE                      31:12
+#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_WOFFSET                    0x0
+#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_DEFAULT_MASK                       _MK_MASK_CONST(0xfffff)
+#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_CACHE_BAR1_ST_0_CACHE_BAR1_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_IO_BAR_SZ_0  
+#define AFI_IO_BAR_SZ_0                 _MK_ADDR_CONST(0x58)
+#define AFI_IO_BAR_SZ_0_SECURE                  0x0
+#define AFI_IO_BAR_SZ_0_WORD_COUNT                      0x1
+#define AFI_IO_BAR_SZ_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AFI_IO_BAR_SZ_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
+#define AFI_IO_BAR_SZ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_IO_BAR_SZ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_IO_BAR_SZ_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
+#define AFI_IO_BAR_SZ_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff)
+//The size of the address range associated with IO BAR is in 
+//4K increments.  Value of 0 signifies BAR is not used.
+#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_SHIFT                       _MK_SHIFT_CONST(0)
+#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_FIELD                       (_MK_MASK_CONST(0xfffff) << AFI_IO_BAR_SZ_0_IO_BAR_SIZE_SHIFT)
+#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_RANGE                       19:0
+#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_WOFFSET                     0x0
+#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_DEFAULT_MASK                        _MK_MASK_CONST(0xfffff)
+#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_IO_BAR_SZ_0_IO_BAR_SIZE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_IO_BAR_ST_0  
+#define AFI_IO_BAR_ST_0                 _MK_ADDR_CONST(0x5c)
+#define AFI_IO_BAR_ST_0_SECURE                  0x0
+#define AFI_IO_BAR_ST_0_WORD_COUNT                      0x1
+#define AFI_IO_BAR_ST_0_RESET_VAL                       _MK_MASK_CONST(0xfc000000)
+#define AFI_IO_BAR_ST_0_RESET_MASK                      _MK_MASK_CONST(0xfffff000)
+#define AFI_IO_BAR_ST_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_IO_BAR_ST_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_IO_BAR_ST_0_READ_MASK                       _MK_MASK_CONST(0xfffff000)
+#define AFI_IO_BAR_ST_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff000)
+//The start of AXI address space for IO BAR.  
+//The upstream FPCI address starting at 0xFD_FC00_0000 up to
+//the range indicated in IO_BAR_SIZE are mapped to start/offset 
+//for IO BAR.
+#define AFI_IO_BAR_ST_0_IO_BAR_START_SHIFT                      _MK_SHIFT_CONST(12)
+#define AFI_IO_BAR_ST_0_IO_BAR_START_FIELD                      (_MK_MASK_CONST(0xfffff) << AFI_IO_BAR_ST_0_IO_BAR_START_SHIFT)
+#define AFI_IO_BAR_ST_0_IO_BAR_START_RANGE                      31:12
+#define AFI_IO_BAR_ST_0_IO_BAR_START_WOFFSET                    0x0
+#define AFI_IO_BAR_ST_0_IO_BAR_START_DEFAULT                    _MK_MASK_CONST(0xfc000)
+#define AFI_IO_BAR_ST_0_IO_BAR_START_DEFAULT_MASK                       _MK_MASK_CONST(0xfffff)
+#define AFI_IO_BAR_ST_0_IO_BAR_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_IO_BAR_ST_0_IO_BAR_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_BAR_SZ_0  
+#define AFI_MSI_BAR_SZ_0                        _MK_ADDR_CONST(0x60)
+#define AFI_MSI_BAR_SZ_0_SECURE                         0x0
+#define AFI_MSI_BAR_SZ_0_WORD_COUNT                     0x1
+#define AFI_MSI_BAR_SZ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AFI_MSI_BAR_SZ_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define AFI_MSI_BAR_SZ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AFI_MSI_BAR_SZ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_BAR_SZ_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define AFI_MSI_BAR_SZ_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+//The size of the address range associated with MSI BAR is
+//in 4K increments.  Value of 0 signifies BAR is not used.
+#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_FIELD                     (_MK_MASK_CONST(0xfffff) << AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_SHIFT)
+#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_RANGE                     19:0
+#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_WOFFSET                   0x0
+#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0xfffff)
+#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_BAR_SZ_0_MSI_BAR_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_FPCI_BAR_ST_0  
+#define AFI_MSI_FPCI_BAR_ST_0                   _MK_ADDR_CONST(0x64)
+#define AFI_MSI_FPCI_BAR_ST_0_SECURE                    0x0
+#define AFI_MSI_FPCI_BAR_ST_0_WORD_COUNT                        0x1
+#define AFI_MSI_FPCI_BAR_ST_0_RESET_VAL                         _MK_MASK_CONST(0x58540000)
+#define AFI_MSI_FPCI_BAR_ST_0_RESET_MASK                        _MK_MASK_CONST(0xfffffff0)
+#define AFI_MSI_FPCI_BAR_ST_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AFI_MSI_FPCI_BAR_ST_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_FPCI_BAR_ST_0_READ_MASK                         _MK_MASK_CONST(0xfffffff0)
+#define AFI_MSI_FPCI_BAR_ST_0_WRITE_MASK                        _MK_MASK_CONST(0xfffffff0)
+//The start of upstream FPCI address space for MSI BAR.  
+//The upstream FPCI address is compared to start/1KB range
+//for MSI BAR to determine if the access is MSI. Bits 31:4
+//of MSI BAR start correspond to UFPCI address bits 39:12.
+#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_SHIFT                  _MK_SHIFT_CONST(4)
+#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_FIELD                  (_MK_MASK_CONST(0xfffffff) << AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_SHIFT)
+#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_RANGE                  31:4
+#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_WOFFSET                        0x0
+#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_DEFAULT                        _MK_MASK_CONST(0x5854000)
+#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_DEFAULT_MASK                   _MK_MASK_CONST(0xfffffff)
+#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_MSI_FPCI_BAR_ST_0_MSI_FPCI_BAR_START_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_AXI_BAR_ST_0  
+#define AFI_MSI_AXI_BAR_ST_0                    _MK_ADDR_CONST(0x68)
+#define AFI_MSI_AXI_BAR_ST_0_SECURE                     0x0
+#define AFI_MSI_AXI_BAR_ST_0_WORD_COUNT                         0x1
+#define AFI_MSI_AXI_BAR_ST_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_MSI_AXI_BAR_ST_0_RESET_MASK                         _MK_MASK_CONST(0xfffff000)
+#define AFI_MSI_AXI_BAR_ST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_MSI_AXI_BAR_ST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_MSI_AXI_BAR_ST_0_READ_MASK                  _MK_MASK_CONST(0xfffff000)
+#define AFI_MSI_AXI_BAR_ST_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff000)
+//The start of upstream AXI address space for MSI BAR.
+//The upstream FPCI address is compared to start/1KB range
+//for MSI BAR to determine if the access is MSI. Bits 31:12
+//of MSI BAR start correspond to AXI address bits 31:12.
+#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_SHIFT                    _MK_SHIFT_CONST(12)
+#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_FIELD                    (_MK_MASK_CONST(0xfffff) << AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_SHIFT)
+#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_RANGE                    31:12
+#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_WOFFSET                  0x0
+#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_DEFAULT_MASK                     _MK_MASK_CONST(0xfffff)
+#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_MSI_AXI_BAR_ST_0_MSI_AXI_BAR_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_VEC0_0  
+#define AFI_MSI_VEC0_0                  _MK_ADDR_CONST(0x6c)
+#define AFI_MSI_VEC0_0_SECURE                   0x0
+#define AFI_MSI_VEC0_0_WORD_COUNT                       0x1
+#define AFI_MSI_VEC0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to 32 of the possible 256 MSI vectors.
+//VECTOR0 corresponds to MSI vectors 31-0.
+//Vector7 corresponds to MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the MSI vector
+//is set to 1 by hardware if the corresponding enable bit is 1.
+//The bit is set to 0 if a 1 is written to its location.
+#define AFI_MSI_VEC0_0_MSI_VECTOR0_SHIFT                        _MK_SHIFT_CONST(0)
+#define AFI_MSI_VEC0_0_MSI_VECTOR0_FIELD                        (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC0_0_MSI_VECTOR0_SHIFT)
+#define AFI_MSI_VEC0_0_MSI_VECTOR0_RANGE                        31:0
+#define AFI_MSI_VEC0_0_MSI_VECTOR0_WOFFSET                      0x0
+#define AFI_MSI_VEC0_0_MSI_VECTOR0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC0_0_MSI_VECTOR0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC0_0_MSI_VECTOR0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC0_0_MSI_VECTOR0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_VEC1_0  
+#define AFI_MSI_VEC1_0                  _MK_ADDR_CONST(0x70)
+#define AFI_MSI_VEC1_0_SECURE                   0x0
+#define AFI_MSI_VEC1_0_WORD_COUNT                       0x1
+#define AFI_MSI_VEC1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to 32 of the possible 256 MSI vectors.
+//VECTOR0 corresponds to MSI vectors 31-0.
+//Vector7 corresponds to MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the MSI vector
+//is set to 1 by hardware if the corresponding enable bit is 1.
+//The bit is set to 0 if a 1 is written to its location.
+#define AFI_MSI_VEC1_0_MSI_VECTOR1_SHIFT                        _MK_SHIFT_CONST(0)
+#define AFI_MSI_VEC1_0_MSI_VECTOR1_FIELD                        (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC1_0_MSI_VECTOR1_SHIFT)
+#define AFI_MSI_VEC1_0_MSI_VECTOR1_RANGE                        31:0
+#define AFI_MSI_VEC1_0_MSI_VECTOR1_WOFFSET                      0x0
+#define AFI_MSI_VEC1_0_MSI_VECTOR1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC1_0_MSI_VECTOR1_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC1_0_MSI_VECTOR1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC1_0_MSI_VECTOR1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_VEC2_0  
+#define AFI_MSI_VEC2_0                  _MK_ADDR_CONST(0x74)
+#define AFI_MSI_VEC2_0_SECURE                   0x0
+#define AFI_MSI_VEC2_0_WORD_COUNT                       0x1
+#define AFI_MSI_VEC2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC2_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC2_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC2_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to 32 of the possible 256 MSI vectors.
+//VECTOR0 corresponds to MSI vectors 31-0.
+//Vector7 corresponds to MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the MSI vector
+//is set to 1 by hardware if the corresponding enable bit is 1.
+//The bit is set to 0 if a 1 is written to its location.
+#define AFI_MSI_VEC2_0_MSI_VECTOR2_SHIFT                        _MK_SHIFT_CONST(0)
+#define AFI_MSI_VEC2_0_MSI_VECTOR2_FIELD                        (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC2_0_MSI_VECTOR2_SHIFT)
+#define AFI_MSI_VEC2_0_MSI_VECTOR2_RANGE                        31:0
+#define AFI_MSI_VEC2_0_MSI_VECTOR2_WOFFSET                      0x0
+#define AFI_MSI_VEC2_0_MSI_VECTOR2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC2_0_MSI_VECTOR2_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC2_0_MSI_VECTOR2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC2_0_MSI_VECTOR2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_VEC3_0  
+#define AFI_MSI_VEC3_0                  _MK_ADDR_CONST(0x78)
+#define AFI_MSI_VEC3_0_SECURE                   0x0
+#define AFI_MSI_VEC3_0_WORD_COUNT                       0x1
+#define AFI_MSI_VEC3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC3_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC3_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC3_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to 32 of the possible 256 MSI vectors.
+//VECTOR0 corresponds to MSI vectors 31-0.
+//Vector7 corresponds to MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the MSI vector
+//is set to 1 by hardware if the corresponding enable bit is 1.
+//The bit is set to 0 if a 1 is written to its location.
+#define AFI_MSI_VEC3_0_MSI_VECTOR3_SHIFT                        _MK_SHIFT_CONST(0)
+#define AFI_MSI_VEC3_0_MSI_VECTOR3_FIELD                        (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC3_0_MSI_VECTOR3_SHIFT)
+#define AFI_MSI_VEC3_0_MSI_VECTOR3_RANGE                        31:0
+#define AFI_MSI_VEC3_0_MSI_VECTOR3_WOFFSET                      0x0
+#define AFI_MSI_VEC3_0_MSI_VECTOR3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC3_0_MSI_VECTOR3_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC3_0_MSI_VECTOR3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC3_0_MSI_VECTOR3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_VEC4_0  
+#define AFI_MSI_VEC4_0                  _MK_ADDR_CONST(0x7c)
+#define AFI_MSI_VEC4_0_SECURE                   0x0
+#define AFI_MSI_VEC4_0_WORD_COUNT                       0x1
+#define AFI_MSI_VEC4_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC4_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC4_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC4_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to 32 of the possible 256 MSI vectors.
+//VECTOR0 corresponds to MSI vectors 31-0.
+//Vector7 corresponds to MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the MSI vector
+//is set to 1 by hardware if the corresponding enable bit is 1.
+//The bit is set to 0 if a 1 is written to its location.
+#define AFI_MSI_VEC4_0_MSI_VECTOR4_SHIFT                        _MK_SHIFT_CONST(0)
+#define AFI_MSI_VEC4_0_MSI_VECTOR4_FIELD                        (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC4_0_MSI_VECTOR4_SHIFT)
+#define AFI_MSI_VEC4_0_MSI_VECTOR4_RANGE                        31:0
+#define AFI_MSI_VEC4_0_MSI_VECTOR4_WOFFSET                      0x0
+#define AFI_MSI_VEC4_0_MSI_VECTOR4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC4_0_MSI_VECTOR4_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC4_0_MSI_VECTOR4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC4_0_MSI_VECTOR4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_VEC5_0  
+#define AFI_MSI_VEC5_0                  _MK_ADDR_CONST(0x80)
+#define AFI_MSI_VEC5_0_SECURE                   0x0
+#define AFI_MSI_VEC5_0_WORD_COUNT                       0x1
+#define AFI_MSI_VEC5_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC5_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC5_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC5_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC5_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC5_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to 32 of the possible 256 MSI vectors.
+//VECTOR0 corresponds to MSI vectors 31-0.
+//Vector7 corresponds to MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the MSI vector
+//is set to 1 by hardware if the corresponding enable bit is 1.
+//The bit is set to 0 if a 1 is written to its location.
+#define AFI_MSI_VEC5_0_MSI_VECTOR5_SHIFT                        _MK_SHIFT_CONST(0)
+#define AFI_MSI_VEC5_0_MSI_VECTOR5_FIELD                        (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC5_0_MSI_VECTOR5_SHIFT)
+#define AFI_MSI_VEC5_0_MSI_VECTOR5_RANGE                        31:0
+#define AFI_MSI_VEC5_0_MSI_VECTOR5_WOFFSET                      0x0
+#define AFI_MSI_VEC5_0_MSI_VECTOR5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC5_0_MSI_VECTOR5_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC5_0_MSI_VECTOR5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC5_0_MSI_VECTOR5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_VEC6_0  
+#define AFI_MSI_VEC6_0                  _MK_ADDR_CONST(0x84)
+#define AFI_MSI_VEC6_0_SECURE                   0x0
+#define AFI_MSI_VEC6_0_WORD_COUNT                       0x1
+#define AFI_MSI_VEC6_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC6_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC6_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC6_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC6_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC6_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to 32 of the possible 256 MSI vectors.
+//VECTOR0 corresponds to MSI vectors 31-0.
+//Vector7 corresponds to MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the MSI vector
+//is set to 1 by hardware if the corresponding enable bit is 1.
+//The bit is set to 0 if a 1 is written to its location.
+#define AFI_MSI_VEC6_0_MSI_VECTOR6_SHIFT                        _MK_SHIFT_CONST(0)
+#define AFI_MSI_VEC6_0_MSI_VECTOR6_FIELD                        (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC6_0_MSI_VECTOR6_SHIFT)
+#define AFI_MSI_VEC6_0_MSI_VECTOR6_RANGE                        31:0
+#define AFI_MSI_VEC6_0_MSI_VECTOR6_WOFFSET                      0x0
+#define AFI_MSI_VEC6_0_MSI_VECTOR6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC6_0_MSI_VECTOR6_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC6_0_MSI_VECTOR6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC6_0_MSI_VECTOR6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_VEC7_0  
+#define AFI_MSI_VEC7_0                  _MK_ADDR_CONST(0x88)
+#define AFI_MSI_VEC7_0_SECURE                   0x0
+#define AFI_MSI_VEC7_0_WORD_COUNT                       0x1
+#define AFI_MSI_VEC7_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC7_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC7_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC7_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC7_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC7_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to 32 of the possible 256 MSI vectors.
+//VECTOR0 corresponds to MSI vectors 31-0.
+//Vector7 corresponds to MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the MSI vector
+//is set to 1 by hardware if the corresponding enable bit is 1.
+//The bit is set to 0 if a 1 is written to its location.
+#define AFI_MSI_VEC7_0_MSI_VECTOR7_SHIFT                        _MK_SHIFT_CONST(0)
+#define AFI_MSI_VEC7_0_MSI_VECTOR7_FIELD                        (_MK_MASK_CONST(0xffffffff) << AFI_MSI_VEC7_0_MSI_VECTOR7_SHIFT)
+#define AFI_MSI_VEC7_0_MSI_VECTOR7_RANGE                        31:0
+#define AFI_MSI_VEC7_0_MSI_VECTOR7_WOFFSET                      0x0
+#define AFI_MSI_VEC7_0_MSI_VECTOR7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC7_0_MSI_VECTOR7_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_VEC7_0_MSI_VECTOR7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_MSI_VEC7_0_MSI_VECTOR7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_EN_VEC0_0  
+#define AFI_MSI_EN_VEC0_0                       _MK_ADDR_CONST(0x8c)
+#define AFI_MSI_EN_VEC0_0_SECURE                        0x0
+#define AFI_MSI_EN_VEC0_0_WORD_COUNT                    0x1
+#define AFI_MSI_EN_VEC0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC0_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to the enable bit for 32
+//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds
+//to enable bits for MSI vectors 31-0.  Vector7 corresponds 
+//to enable bits for MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the
+//MSI vector is set to 1 by hardware if the corresponding
+//enable bit is 1.
+#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_FIELD                      (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_SHIFT)
+#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_RANGE                      31:0
+#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_WOFFSET                    0x0
+#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC0_0_MSI_ENABLE_VECTOR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_EN_VEC1_0  
+#define AFI_MSI_EN_VEC1_0                       _MK_ADDR_CONST(0x90)
+#define AFI_MSI_EN_VEC1_0_SECURE                        0x0
+#define AFI_MSI_EN_VEC1_0_WORD_COUNT                    0x1
+#define AFI_MSI_EN_VEC1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to the enable bit for 32
+//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds
+//to enable bits for MSI vectors 31-0.  Vector7 corresponds 
+//to enable bits for MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the
+//MSI vector is set to 1 by hardware if the corresponding
+//enable bit is 1.
+#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_FIELD                      (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_SHIFT)
+#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_RANGE                      31:0
+#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_WOFFSET                    0x0
+#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC1_0_MSI_ENABLE_VECTOR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_EN_VEC2_0  
+#define AFI_MSI_EN_VEC2_0                       _MK_ADDR_CONST(0x94)
+#define AFI_MSI_EN_VEC2_0_SECURE                        0x0
+#define AFI_MSI_EN_VEC2_0_WORD_COUNT                    0x1
+#define AFI_MSI_EN_VEC2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC2_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC2_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC2_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to the enable bit for 32
+//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds
+//to enable bits for MSI vectors 31-0.  Vector7 corresponds 
+//to enable bits for MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the
+//MSI vector is set to 1 by hardware if the corresponding
+//enable bit is 1.
+#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_FIELD                      (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_SHIFT)
+#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_RANGE                      31:0
+#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_WOFFSET                    0x0
+#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC2_0_MSI_ENABLE_VECTOR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_EN_VEC3_0  
+#define AFI_MSI_EN_VEC3_0                       _MK_ADDR_CONST(0x98)
+#define AFI_MSI_EN_VEC3_0_SECURE                        0x0
+#define AFI_MSI_EN_VEC3_0_WORD_COUNT                    0x1
+#define AFI_MSI_EN_VEC3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC3_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC3_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC3_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to the enable bit for 32
+//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds
+//to enable bits for MSI vectors 31-0.  Vector7 corresponds 
+//to enable bits for MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the
+//MSI vector is set to 1 by hardware if the corresponding
+//enable bit is 1.
+#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_FIELD                      (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_SHIFT)
+#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_RANGE                      31:0
+#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_WOFFSET                    0x0
+#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC3_0_MSI_ENABLE_VECTOR3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_EN_VEC4_0  
+#define AFI_MSI_EN_VEC4_0                       _MK_ADDR_CONST(0x9c)
+#define AFI_MSI_EN_VEC4_0_SECURE                        0x0
+#define AFI_MSI_EN_VEC4_0_WORD_COUNT                    0x1
+#define AFI_MSI_EN_VEC4_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC4_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC4_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC4_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to the enable bit for 32
+//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds
+//to enable bits for MSI vectors 31-0.  Vector7 corresponds 
+//to enable bits for MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the
+//MSI vector is set to 1 by hardware if the corresponding
+//enable bit is 1.
+#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_FIELD                      (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_SHIFT)
+#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_RANGE                      31:0
+#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_WOFFSET                    0x0
+#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC4_0_MSI_ENABLE_VECTOR4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_EN_VEC5_0  
+#define AFI_MSI_EN_VEC5_0                       _MK_ADDR_CONST(0xa0)
+#define AFI_MSI_EN_VEC5_0_SECURE                        0x0
+#define AFI_MSI_EN_VEC5_0_WORD_COUNT                    0x1
+#define AFI_MSI_EN_VEC5_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC5_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC5_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC5_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC5_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC5_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to the enable bit for 32
+//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds
+//to enable bits for MSI vectors 31-0.  Vector7 corresponds 
+//to enable bits for MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the
+//MSI vector is set to 1 by hardware if the corresponding
+//enable bit is 1.
+#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_FIELD                      (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_SHIFT)
+#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_RANGE                      31:0
+#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_WOFFSET                    0x0
+#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC5_0_MSI_ENABLE_VECTOR5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_EN_VEC6_0  
+#define AFI_MSI_EN_VEC6_0                       _MK_ADDR_CONST(0xa4)
+#define AFI_MSI_EN_VEC6_0_SECURE                        0x0
+#define AFI_MSI_EN_VEC6_0_WORD_COUNT                    0x1
+#define AFI_MSI_EN_VEC6_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC6_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC6_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC6_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC6_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC6_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to the enable bit for 32
+//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds
+//to enable bits for MSI vectors 31-0.  Vector7 corresponds 
+//to enable bits for MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the
+//MSI vector is set to 1 by hardware if the corresponding
+//enable bit is 1.
+#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_FIELD                      (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_SHIFT)
+#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_RANGE                      31:0
+#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_WOFFSET                    0x0
+#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC6_0_MSI_ENABLE_VECTOR6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_MSI_EN_VEC7_0  
+#define AFI_MSI_EN_VEC7_0                       _MK_ADDR_CONST(0xa8)
+#define AFI_MSI_EN_VEC7_0_SECURE                        0x0
+#define AFI_MSI_EN_VEC7_0_WORD_COUNT                    0x1
+#define AFI_MSI_EN_VEC7_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC7_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC7_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC7_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC7_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC7_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+//Each vector register corresponds to the enable bit for 32
+//of the possible 256 MSI vectors. ENABLE VECTOR0 corresponds
+//to enable bits for MSI vectors 31-0.  Vector7 corresponds 
+//to enable bits for MSI vectors 255-223.
+//When an upstream MSI is sent, the bit corresponding to the
+//MSI vector is set to 1 by hardware if the corresponding
+//enable bit is 1.
+#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_FIELD                      (_MK_MASK_CONST(0xffffffff) << AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_SHIFT)
+#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_RANGE                      31:0
+#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_WOFFSET                    0x0
+#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_MSI_EN_VEC7_0_MSI_ENABLE_VECTOR7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_CONFIGURATION_0  
+#define AFI_CONFIGURATION_0                     _MK_ADDR_CONST(0xac)
+#define AFI_CONFIGURATION_0_SECURE                      0x0
+#define AFI_CONFIGURATION_0_WORD_COUNT                  0x1
+#define AFI_CONFIGURATION_0_RESET_VAL                   _MK_MASK_CONST(0x8e04)
+#define AFI_CONFIGURATION_0_RESET_MASK                  _MK_MASK_CONST(0xff3f)
+#define AFI_CONFIGURATION_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_READ_MASK                   _MK_MASK_CONST(0xff3f)
+#define AFI_CONFIGURATION_0_WRITE_MASK                  _MK_MASK_CONST(0xc03f)
+//When the PCI device block is disabled, it is completely invisible
+//on the PCI bus, i.e. it doesn't even process PCI configuration accesses.
+#define AFI_CONFIGURATION_0_EN_FPCI_SHIFT                       _MK_SHIFT_CONST(0)
+#define AFI_CONFIGURATION_0_EN_FPCI_FIELD                       (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_EN_FPCI_SHIFT)
+#define AFI_CONFIGURATION_0_EN_FPCI_RANGE                       0:0
+#define AFI_CONFIGURATION_0_EN_FPCI_WOFFSET                     0x0
+#define AFI_CONFIGURATION_0_EN_FPCI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_EN_FPCI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_EN_FPCI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_EN_FPCI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//CYA - input to downstream FPCI.
+//Allow downstream FPCI reads to pass writes.
+#define AFI_CONFIGURATION_0_DFPCI_PASSPW_SHIFT                  _MK_SHIFT_CONST(1)
+#define AFI_CONFIGURATION_0_DFPCI_PASSPW_FIELD                  (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_DFPCI_PASSPW_SHIFT)
+#define AFI_CONFIGURATION_0_DFPCI_PASSPW_RANGE                  1:1
+#define AFI_CONFIGURATION_0_DFPCI_PASSPW_WOFFSET                        0x0
+#define AFI_CONFIGURATION_0_DFPCI_PASSPW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_DFPCI_PASSPW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_DFPCI_PASSPW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_DFPCI_PASSPW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//CYA - input to downstream FPCI.
+//Allow downstream FPCI responses to pass writes
+#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_SHIFT                       _MK_SHIFT_CONST(2)
+#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_FIELD                       (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_SHIFT)
+#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_RANGE                       2:2
+#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_WOFFSET                     0x0
+#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_DFPCI_RSPPASSPW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//CYA - used for downstream FPCI.
+//Allow downstream FPCI PWs to pass NPWs.
+#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_SHIFT                       _MK_SHIFT_CONST(3)
+#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_FIELD                       (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_SHIFT)
+#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_RANGE                       3:3
+#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_WOFFSET                     0x0
+#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_DFPCI_PWPASSNPW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//CYA - used for upstream FPCI.
+//Allow upstream FPCI PWs to pass NPWs.
+#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_SHIFT                       _MK_SHIFT_CONST(4)
+#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_FIELD                       (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_SHIFT)
+#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_RANGE                       4:4
+#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_WOFFSET                     0x0
+#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_UFPCI_PWPASSNPW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//CYA - input to upstream FPCI.
+//Allow upstream FPCI reads to pass writes.
+#define AFI_CONFIGURATION_0_UFPCI_PASSPW_SHIFT                  _MK_SHIFT_CONST(5)
+#define AFI_CONFIGURATION_0_UFPCI_PASSPW_FIELD                  (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_UFPCI_PASSPW_SHIFT)
+#define AFI_CONFIGURATION_0_UFPCI_PASSPW_RANGE                  5:5
+#define AFI_CONFIGURATION_0_UFPCI_PASSPW_WOFFSET                        0x0
+#define AFI_CONFIGURATION_0_UFPCI_PASSPW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_UFPCI_PASSPW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_UFPCI_PASSPW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_UFPCI_PASSPW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//This read-only bit provides status on whether PCIe is strapped
+//as a root port or endpoint.  The value of this bit is 1b (endpoint)
+//if production mode is 0b (disabled) and memory strap_ram_code[0] is 1b.
+#define AFI_CONFIGURATION_0_ENDPT_MODE_SHIFT                    _MK_SHIFT_CONST(8)
+#define AFI_CONFIGURATION_0_ENDPT_MODE_FIELD                    (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_ENDPT_MODE_SHIFT)
+#define AFI_CONFIGURATION_0_ENDPT_MODE_RANGE                    8:8
+#define AFI_CONFIGURATION_0_ENDPT_MODE_WOFFSET                  0x0
+#define AFI_CONFIGURATION_0_ENDPT_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_ENDPT_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_ENDPT_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_ENDPT_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//This read-only bit provides status on whether MSI Vector registers
+//have any active bits valid or not
+#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_SHIFT                 _MK_SHIFT_CONST(9)
+#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_FIELD                 (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_MSI_VEC_EMPTY_SHIFT)
+#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_RANGE                 9:9
+#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_WOFFSET                       0x0
+#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_MSI_VEC_EMPTY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//This read-only bit provides status writes to AFI target.
+//A value of 1b indicates there are no outstanding writes to downstream FPCI.
+#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_SHIFT                     _MK_SHIFT_CONST(10)
+#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_FIELD                     (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_SHIFT)
+#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_RANGE                     10:10
+#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_WOFFSET                   0x0
+#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_TARGET_WRITE_IDLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//This read-only bit provides status reads to AFI target.
+//A value of 1b indicates there are no outstanding reads to downstream FPCI.
+#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_SHIFT                      _MK_SHIFT_CONST(11)
+#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_FIELD                      (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_TARGET_READ_IDLE_SHIFT)
+#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_RANGE                      11:11
+#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_WOFFSET                    0x0
+#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_TARGET_READ_IDLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//This read-only bit is 0 when a card is present in PCIE slot 0
+#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_SHIFT                        _MK_SHIFT_CONST(12)
+#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_FIELD                        (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_SHIFT)
+#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_RANGE                        12:12
+#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_WOFFSET                      0x0
+#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_PE0_PRSNT_L_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//This read-only bit is 0 when a card is present in PCIE slot 1
+#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_SHIFT                        _MK_SHIFT_CONST(13)
+#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_FIELD                        (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_SHIFT)
+#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_RANGE                        13:13
+#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_WOFFSET                      0x0
+#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_PE1_PRSNT_L_IN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//CYA - used to en(dis)able the handling of interleaved write requests on mselect
+#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_SHIFT                 _MK_SHIFT_CONST(14)
+#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_FIELD                 (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_WR_INTRLV_CYA_SHIFT)
+#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_RANGE                 14:14
+#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_WOFFSET                       0x0
+#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_WR_INTRLV_CYA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//CYA - used to en(dis)able the handling of write data ahead of requests on mselect
+#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_SHIFT                        _MK_SHIFT_CONST(15)
+#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_FIELD                        (_MK_MASK_CONST(0x1) << AFI_CONFIGURATION_0_WDATA_LEAD_CYA_SHIFT)
+#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_RANGE                        15:15
+#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_WOFFSET                      0x0
+#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_CONFIGURATION_0_WDATA_LEAD_CYA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register AFI_FPCI_ERROR_MASKS_0  
+#define AFI_FPCI_ERROR_MASKS_0                  _MK_ADDR_CONST(0xb0)
+#define AFI_FPCI_ERROR_MASKS_0_SECURE                   0x0
+#define AFI_FPCI_ERROR_MASKS_0_WORD_COUNT                       0x1
+#define AFI_FPCI_ERROR_MASKS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_FPCI_ERROR_MASKS_0_RESET_MASK                       _MK_MASK_CONST(0x7)
+#define AFI_FPCI_ERROR_MASKS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_FPCI_ERROR_MASKS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AFI_FPCI_ERROR_MASKS_0_READ_MASK                        _MK_MASK_CONST(0x7)
+#define AFI_FPCI_ERROR_MASKS_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
+//This bit allows FPCI error to be forwarded to AXI response when FPCI error response
+//indicates Target Abort. 1 = forward error, 0 = return AXI OKAY response (2'b0)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_SHIFT                     _MK_SHIFT_CONST(0)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_FIELD                     (_MK_MASK_CONST(0x1) << AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_SHIFT)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_RANGE                     0:0
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_WOFFSET                   0x0
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_TARGET_ABORT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//This bit allows FPCI error to be forwarded to AXI response when FPCI error response
+//indicates Data Error. 1 = forward error, 0 = return AXI OKAY response (2'b0)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_SHIFT                       _MK_SHIFT_CONST(1)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_FIELD                       (_MK_MASK_CONST(0x1) << AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_SHIFT)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_RANGE                       1:1
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_WOFFSET                     0x0
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_DATA_ERROR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//This bit allows FPCI error to be forwarded to AXI response when FPCI error response
+//indicates Master Abort. 1 = forward error, 0 = return AXI OKAY response (2'b0)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_SHIFT                     _MK_SHIFT_CONST(2)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_FIELD                     (_MK_MASK_CONST(0x1) << AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_SHIFT)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_RANGE                     2:2
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_WOFFSET                   0x0
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_FPCI_ERROR_MASKS_0_MASK_FPCI_MASTER_ABORT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_INTR_MASK_0  
+#define AFI_INTR_MASK_0                 _MK_ADDR_CONST(0xb4)
+#define AFI_INTR_MASK_0_SECURE                  0x0
+#define AFI_INTR_MASK_0_WORD_COUNT                      0x1
+#define AFI_INTR_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AFI_INTR_MASK_0_RESET_MASK                      _MK_MASK_CONST(0x101)
+#define AFI_INTR_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_INTR_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_INTR_MASK_0_READ_MASK                       _MK_MASK_CONST(0x101)
+#define AFI_INTR_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0x101)
+//Interrupt to MPCORE gated by mask.
+#define AFI_INTR_MASK_0_INT_MASK_SHIFT                  _MK_SHIFT_CONST(0)
+#define AFI_INTR_MASK_0_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << AFI_INTR_MASK_0_INT_MASK_SHIFT)
+#define AFI_INTR_MASK_0_INT_MASK_RANGE                  0:0
+#define AFI_INTR_MASK_0_INT_MASK_WOFFSET                        0x0
+#define AFI_INTR_MASK_0_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_INTR_MASK_0_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AFI_INTR_MASK_0_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_INTR_MASK_0_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//MSI to MPCORE gated by mask.
+#define AFI_INTR_MASK_0_MSI_MASK_SHIFT                  _MK_SHIFT_CONST(8)
+#define AFI_INTR_MASK_0_MSI_MASK_FIELD                  (_MK_MASK_CONST(0x1) << AFI_INTR_MASK_0_MSI_MASK_SHIFT)
+#define AFI_INTR_MASK_0_MSI_MASK_RANGE                  8:8
+#define AFI_INTR_MASK_0_MSI_MASK_WOFFSET                        0x0
+#define AFI_INTR_MASK_0_MSI_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_INTR_MASK_0_MSI_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AFI_INTR_MASK_0_MSI_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_INTR_MASK_0_MSI_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register AFI_INTR_CODE_0  
+#define AFI_INTR_CODE_0                 _MK_ADDR_CONST(0xb8)
+#define AFI_INTR_CODE_0_SECURE                  0x0
+#define AFI_INTR_CODE_0_WORD_COUNT                      0x1
+#define AFI_INTR_CODE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AFI_INTR_CODE_0_RESET_MASK                      _MK_MASK_CONST(0xf)
+#define AFI_INTR_CODE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_INTR_CODE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_INTR_CODE_0_READ_MASK                       _MK_MASK_CONST(0xf)
+#define AFI_INTR_CODE_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
+//Eight interrupt codes
+//If the code is 0, logging of the next interrupt is enabled
+#define AFI_INTR_CODE_0_INT_CODE_SHIFT                  _MK_SHIFT_CONST(0)
+#define AFI_INTR_CODE_0_INT_CODE_FIELD                  (_MK_MASK_CONST(0xf) << AFI_INTR_CODE_0_INT_CODE_SHIFT)
+#define AFI_INTR_CODE_0_INT_CODE_RANGE                  3:0
+#define AFI_INTR_CODE_0_INT_CODE_WOFFSET                        0x0
+#define AFI_INTR_CODE_0_INT_CODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_INTR_CODE_0_INT_CODE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define AFI_INTR_CODE_0_INT_CODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_INTR_CODE_0_INT_CODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_CLEAR                 _MK_ENUM_CONST(0)    // //Clear interrupt code
+
+#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_INI_SLVERR                    _MK_ENUM_CONST(1)    // //Interrupt code for MPCORE AXI SLVERR response to AFI
+
+#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_INI_DECERR                    _MK_ENUM_CONST(2)    // //Interrupt code for MPCORE AXI DECERR response to AFI
+
+#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_TGT_SLVERR                    _MK_ENUM_CONST(3)    // //Interrupt code for PCIE endpoint FPCI target abort or data error 
+//response to AFI
+
+#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_TGT_DECERR                    _MK_ENUM_CONST(4)    // //Interrupt code for PCIE2 FPCI master abort response to AFI
+
+#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_TGT_WRERR                     _MK_ENUM_CONST(5)    // //Interrupt code for bufferable write to non-posted write address region
+
+#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_SM_MSG                        _MK_ENUM_CONST(6)    // //Interrupt code for PCIE2 system management message
+
+#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_DFPCI_DECERR                  _MK_ENUM_CONST(7)    // //Interrupt code for PCIE2 response to downstream request when
+//downstream FPCI addresss does not fall in a claimable downstream region
+
+#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_AXI_DECERR                    _MK_ENUM_CONST(8)    // //Interrupt code for AFI response to downstream request when
+//mselect AXI addresss does not fall in any of AFI downstream BARs
+
+#define AFI_INTR_CODE_0_INT_CODE_INT_CODE_FPCI_TIMEOUT                  _MK_ENUM_CONST(9)    // //Interrupt code for FPCI Timeout
+
+
+
+// Register AFI_INTR_SIGNATURE_0  
+#define AFI_INTR_SIGNATURE_0                    _MK_ADDR_CONST(0xbc)
+#define AFI_INTR_SIGNATURE_0_SECURE                     0x0
+#define AFI_INTR_SIGNATURE_0_WORD_COUNT                         0x1
+#define AFI_INTR_SIGNATURE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_INTR_SIGNATURE_0_RESET_MASK                         _MK_MASK_CONST(0xfffffffd)
+#define AFI_INTR_SIGNATURE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_INTR_SIGNATURE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_INTR_SIGNATURE_0_READ_MASK                  _MK_MASK_CONST(0xfffffffd)
+#define AFI_INTR_SIGNATURE_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffffd)
+//Indicates direction of the AXI/FPCI transaction. 1=rd/0=wr
+//If signature type is 6 (sideband message), this field is 1.
+#define AFI_INTR_SIGNATURE_0_DIR_SHIFT                  _MK_SHIFT_CONST(0)
+#define AFI_INTR_SIGNATURE_0_DIR_FIELD                  (_MK_MASK_CONST(0x1) << AFI_INTR_SIGNATURE_0_DIR_SHIFT)
+#define AFI_INTR_SIGNATURE_0_DIR_RANGE                  0:0
+#define AFI_INTR_SIGNATURE_0_DIR_WOFFSET                        0x0
+#define AFI_INTR_SIGNATURE_0_DIR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_INTR_SIGNATURE_0_DIR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AFI_INTR_SIGNATURE_0_DIR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_INTR_SIGNATURE_0_DIR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AFI_INTR_SIGNATURE_0_DIR_WRITE                  _MK_ENUM_CONST(0)    // //Interrupt due to a write transaction
+
+#define AFI_INTR_SIGNATURE_0_DIR_READ                   _MK_ENUM_CONST(1)    // //Interrupt due to a read transaction
+
+
+//For interrupt codes 1-5/7-8, it contains address bits [31:2], 
+//either in FPCI memory space or AXI space. If interrupt code is 6,
+//the information field INT_INFO[12:0] contain sideband information 
+//{sideband unitid, 3'b0, tms02sm_msg[4:0]}.
+//For FPCI generated errors, the info contains FPCI address.
+//For AXI/AFI generated errors, the info contains AXI address.
+#define AFI_INTR_SIGNATURE_0_INT_INFO_SHIFT                     _MK_SHIFT_CONST(2)
+#define AFI_INTR_SIGNATURE_0_INT_INFO_FIELD                     (_MK_MASK_CONST(0x3fffffff) << AFI_INTR_SIGNATURE_0_INT_INFO_SHIFT)
+#define AFI_INTR_SIGNATURE_0_INT_INFO_RANGE                     31:2
+#define AFI_INTR_SIGNATURE_0_INT_INFO_WOFFSET                   0x0
+#define AFI_INTR_SIGNATURE_0_INT_INFO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_INTR_SIGNATURE_0_INT_INFO_DEFAULT_MASK                      _MK_MASK_CONST(0x3fffffff)
+#define AFI_INTR_SIGNATURE_0_INT_INFO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_INTR_SIGNATURE_0_INT_INFO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_UPPER_FPCI_ADDR_0  
+#define AFI_UPPER_FPCI_ADDR_0                   _MK_ADDR_CONST(0xc0)
+#define AFI_UPPER_FPCI_ADDR_0_SECURE                    0x0
+#define AFI_UPPER_FPCI_ADDR_0_WORD_COUNT                        0x1
+#define AFI_UPPER_FPCI_ADDR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define AFI_UPPER_FPCI_ADDR_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define AFI_UPPER_FPCI_ADDR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AFI_UPPER_FPCI_ADDR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AFI_UPPER_FPCI_ADDR_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define AFI_UPPER_FPCI_ADDR_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+//These 8 bits are the upper byte of captured FPCI address (bits[39:32])
+//when interrupt code is 3, 4 or 7.  These bits determine the region
+//in the Hypertransport Address Map that was accessed.  This map
+//is described in section 3.2.4 of the AFI IAS.
+#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_FIELD                      (_MK_MASK_CONST(0xff) << AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_SHIFT)
+#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_RANGE                      7:0
+#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_WOFFSET                    0x0
+#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_UPPER_FPCI_ADDR_0_INT_INFO_UPPER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_SM_INTR_ENABLE_0  
+#define AFI_SM_INTR_ENABLE_0                    _MK_ADDR_CONST(0xc4)
+#define AFI_SM_INTR_ENABLE_0_SECURE                     0x0
+#define AFI_SM_INTR_ENABLE_0_WORD_COUNT                         0x1
+#define AFI_SM_INTR_ENABLE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_SM_INTR_ENABLE_0_RESET_MASK                         _MK_MASK_CONST(0x7fff)
+#define AFI_SM_INTR_ENABLE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_SM_INTR_ENABLE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_SM_INTR_ENABLE_0_READ_MASK                  _MK_MASK_CONST(0x7fff)
+#define AFI_SM_INTR_ENABLE_0_WRITE_MASK                         _MK_MASK_CONST(0x7fff)
+//Each of the bits in this register correspond to enabling the
+//associated message shown in the system message table in 3.2.10
+//Enable bits for interrupt code 6 of table in section 8.1.3
+#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_SHIFT                       _MK_SHIFT_CONST(0)
+#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_FIELD                       (_MK_MASK_CONST(0x7fff) << AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_SHIFT)
+#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_RANGE                       14:0
+#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_WOFFSET                     0x0
+#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_DEFAULT_MASK                        _MK_MASK_CONST(0x7fff)
+#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_SM_INTR_ENABLE_0_ENABLE_MESSAGE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AFI_INTR_ENABLE_0  
+#define AFI_AFI_INTR_ENABLE_0                   _MK_ADDR_CONST(0xc8)
+#define AFI_AFI_INTR_ENABLE_0_SECURE                    0x0
+#define AFI_AFI_INTR_ENABLE_0_WORD_COUNT                        0x1
+#define AFI_AFI_INTR_ENABLE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define AFI_AFI_INTR_ENABLE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define AFI_AFI_INTR_ENABLE_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+//Enable bit for interrupt code 1 
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_SHIFT                       _MK_SHIFT_CONST(0)
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_FIELD                       (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_SHIFT)
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_RANGE                       0:0
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_WOFFSET                     0x0
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_SLVERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//Enable bit for interrupt code 2 
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_SHIFT                       _MK_SHIFT_CONST(1)
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_FIELD                       (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_SHIFT)
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_RANGE                       1:1
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_WOFFSET                     0x0
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_INI_DECERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//Enable bit for interrupt code 3 
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_SHIFT                       _MK_SHIFT_CONST(2)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_FIELD                       (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_SHIFT)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_RANGE                       2:2
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_WOFFSET                     0x0
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_SLVERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//Enable bit for interrupt code 4 
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_SHIFT                       _MK_SHIFT_CONST(3)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_FIELD                       (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_SHIFT)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_RANGE                       3:3
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_WOFFSET                     0x0
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_DECERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//Enable bit for interrupt code 5 
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_SHIFT                        _MK_SHIFT_CONST(4)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_FIELD                        (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_SHIFT)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_RANGE                        4:4
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_WOFFSET                      0x0
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_TGT_WRERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//Enable bit for interrupt code 7 
+#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_SHIFT                     _MK_SHIFT_CONST(5)
+#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_FIELD                     (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_SHIFT)
+#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_RANGE                     5:5
+#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_WOFFSET                   0x0
+#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_DFPCI_DECERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//Enable bit for interrupt code 8 
+#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_SHIFT                       _MK_SHIFT_CONST(6)
+#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_FIELD                       (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_SHIFT)
+#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_RANGE                       6:6
+#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_WOFFSET                     0x0
+#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_AXI_DECERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//Enable bit for interrupt code 9 
+#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_SHIFT                     _MK_SHIFT_CONST(7)
+#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_FIELD                     (_MK_MASK_CONST(0x1) << AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_SHIFT)
+#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_RANGE                     7:7
+#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_WOFFSET                   0x0
+#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_AFI_INTR_ENABLE_0_EN_FPCI_TIMEOUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_AUSER_OVERRIDE_0  
+#define AFI_AUSER_OVERRIDE_0                    _MK_ADDR_CONST(0xcc)
+#define AFI_AUSER_OVERRIDE_0_SECURE                     0x0
+#define AFI_AUSER_OVERRIDE_0_WORD_COUNT                         0x1
+#define AFI_AUSER_OVERRIDE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_AUSER_OVERRIDE_0_RESET_MASK                         _MK_MASK_CONST(0x8000001f)
+#define AFI_AUSER_OVERRIDE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_AUSER_OVERRIDE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_AUSER_OVERRIDE_0_READ_MASK                  _MK_MASK_CONST(0x8000001f)
+#define AFI_AUSER_OVERRIDE_0_WRITE_MASK                         _MK_MASK_CONST(0x8000001f)
+//Programmable value to drive on to AXI initiator AUSER fields
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_FIELD                   (_MK_MASK_CONST(0x1f) << AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_SHIFT)
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_RANGE                   4:0
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_WOFFSET                 0x0
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Enables value in override register to be driven on AXI initiator 
+//AUSER when in preproduction mode. 
+//1=drive AUSER override value (preproduction mode only)
+//0=drive AUSER normally
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_SHIFT                    _MK_SHIFT_CONST(31)
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_FIELD                    (_MK_MASK_CONST(0x1) << AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_SHIFT)
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_RANGE                    31:31
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_WOFFSET                  0x0
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_AUSER_OVERRIDE_0_AUSER_OVERRIDE_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AFI_ACACHE_OVERRIDE_0  
+#define AFI_ACACHE_OVERRIDE_0                   _MK_ADDR_CONST(0xd0)
+#define AFI_ACACHE_OVERRIDE_0_SECURE                    0x0
+#define AFI_ACACHE_OVERRIDE_0_WORD_COUNT                        0x1
+#define AFI_ACACHE_OVERRIDE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define AFI_ACACHE_OVERRIDE_0_RESET_MASK                        _MK_MASK_CONST(0x8000000f)
+#define AFI_ACACHE_OVERRIDE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AFI_ACACHE_OVERRIDE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AFI_ACACHE_OVERRIDE_0_READ_MASK                         _MK_MASK_CONST(0x8000000f)
+#define AFI_ACACHE_OVERRIDE_0_WRITE_MASK                        _MK_MASK_CONST(0x8000000f)
+//Programmable value to drive on to AXI initiator ACACHE fields
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_FIELD                 (_MK_MASK_CONST(0xf) << AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_SHIFT)
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_RANGE                 3:0
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_WOFFSET                       0x0
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//Enables value in override register to be driven on AXI initiator 
+//ACACHE when in preproduction mode. 
+//1=drive ACACHE override value (preproduction mode only)
+//0=drive ACACHE normally
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_SHIFT                  _MK_SHIFT_CONST(31)
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_FIELD                  (_MK_MASK_CONST(0x1) << AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_SHIFT)
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_RANGE                  31:31
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_WOFFSET                        0x0
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_ACACHE_OVERRIDE_0_ACACHE_OVERRIDE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register AFI_APROT_OVERRIDE_0  
+#define AFI_APROT_OVERRIDE_0                    _MK_ADDR_CONST(0xd4)
+#define AFI_APROT_OVERRIDE_0_SECURE                     0x0
+#define AFI_APROT_OVERRIDE_0_WORD_COUNT                         0x1
+#define AFI_APROT_OVERRIDE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_APROT_OVERRIDE_0_RESET_MASK                         _MK_MASK_CONST(0x80000007)
+#define AFI_APROT_OVERRIDE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_APROT_OVERRIDE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_APROT_OVERRIDE_0_READ_MASK                  _MK_MASK_CONST(0x80000007)
+#define AFI_APROT_OVERRIDE_0_WRITE_MASK                         _MK_MASK_CONST(0x80000007)
+//Programmable value to drive on to AXI initiator APROT fields
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_FIELD                   (_MK_MASK_CONST(0x7) << AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_SHIFT)
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_RANGE                   2:0
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_WOFFSET                 0x0
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Enables value in override register to be driven on AXI initiator 
+//APROT when in preproduction mode. 
+//1=drive APROT override value (preproduction mode only)
+//0=drive APROT normally
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_SHIFT                    _MK_SHIFT_CONST(31)
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_FIELD                    (_MK_MASK_CONST(0x1) << AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_SHIFT)
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_RANGE                    31:31
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_WOFFSET                  0x0
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_APROT_OVERRIDE_0_APROT_OVERRIDE_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AFI_FPCI_TIMEOUT_0  
+#define AFI_FPCI_TIMEOUT_0                      _MK_ADDR_CONST(0xd8)
+#define AFI_FPCI_TIMEOUT_0_SECURE                       0x0
+#define AFI_FPCI_TIMEOUT_0_WORD_COUNT                   0x1
+#define AFI_FPCI_TIMEOUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define AFI_FPCI_TIMEOUT_0_RESET_MASK                   _MK_MASK_CONST(0x800fffff)
+#define AFI_FPCI_TIMEOUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AFI_FPCI_TIMEOUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AFI_FPCI_TIMEOUT_0_READ_MASK                    _MK_MASK_CONST(0x800fffff)
+#define AFI_FPCI_TIMEOUT_0_WRITE_MASK                   _MK_MASK_CONST(0x800fffff)
+//SM (system management) threshold specifying how long to wait 
+//for response from FPCI before declaring it timeout
+#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_SHIFT                     _MK_SHIFT_CONST(0)
+#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_FIELD                     (_MK_MASK_CONST(0xfffff) << AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_SHIFT)
+#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_RANGE                     19:0
+#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_WOFFSET                   0x0
+#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_DEFAULT_MASK                      _MK_MASK_CONST(0xfffff)
+#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_FPCI_TIMEOUT_0_SM2ALL_FPCI_TIMEOUT_THRESH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//SM (system management) timeout enable
+#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_SHIFT                        _MK_SHIFT_CONST(31)
+#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_FIELD                        (_MK_MASK_CONST(0x1) << AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_SHIFT)
+#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_RANGE                        31:31
+#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_WOFFSET                      0x0
+#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_FPCI_TIMEOUT_0_SM2TMS0_FPCI_TIMEOUT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register AFI_IDDQ_MODE_0  
+#define AFI_IDDQ_MODE_0                 _MK_ADDR_CONST(0xdc)
+#define AFI_IDDQ_MODE_0_SECURE                  0x0
+#define AFI_IDDQ_MODE_0_WORD_COUNT                      0x1
+#define AFI_IDDQ_MODE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_0_RESET_MASK                      _MK_MASK_CONST(0x3)
+#define AFI_IDDQ_MODE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_0_READ_MASK                       _MK_MASK_CONST(0x3)
+#define AFI_IDDQ_MODE_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
+//SM (system management) to PCIE PLL assert IDDQ Mode
+#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_SHIFT                 _MK_SHIFT_CONST(0)
+#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_FIELD                 (_MK_MASK_CONST(0x1) << AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_SHIFT)
+#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_RANGE                 0:0
+#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_WOFFSET                       0x0
+#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_0_SM2PCIE_ASSERT_PEX0_PLL_IDDQ_MODE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//SM (system management) to PCIE PLL deassert IDDQ Mode
+#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_FIELD                       (_MK_MASK_CONST(0x1) << AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_SHIFT)
+#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_RANGE                       1:1
+#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_WOFFSET                     0x0
+#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_0_SM2PCIE_DEASSERT_PEX0_PLL_IDDQ_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_PLL_RESET_0  
+#define AFI_PLL_RESET_0                 _MK_ADDR_CONST(0xe0)
+#define AFI_PLL_RESET_0_SECURE                  0x0
+#define AFI_PLL_RESET_0_WORD_COUNT                      0x1
+#define AFI_PLL_RESET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_0_RESET_MASK                      _MK_MASK_CONST(0x3)
+#define AFI_PLL_RESET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_0_READ_MASK                       _MK_MASK_CONST(0x3)
+#define AFI_PLL_RESET_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
+//SM (system management) to PCIE PLL assert Reset
+#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_SHIFT                       _MK_SHIFT_CONST(0)
+#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_FIELD                       (_MK_MASK_CONST(0x1) << AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_SHIFT)
+#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_RANGE                       0:0
+#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_WOFFSET                     0x0
+#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_0_SM2PCIE_ASSERT_PEX0_PLL_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//SM (system management) to PCIE PLL deassert Reset
+#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_SHIFT                     _MK_SHIFT_CONST(1)
+#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_FIELD                     (_MK_MASK_CONST(0x1) << AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_SHIFT)
+#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_RANGE                     1:1
+#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_WOFFSET                   0x0
+#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_0_SM2PCIE_DEASSERT_PEX0_PLL_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_IDDQ_MODE_ACK_0  
+#define AFI_IDDQ_MODE_ACK_0                     _MK_ADDR_CONST(0xe4)
+#define AFI_IDDQ_MODE_ACK_0_SECURE                      0x0
+#define AFI_IDDQ_MODE_ACK_0_WORD_COUNT                  0x1
+#define AFI_IDDQ_MODE_ACK_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_ACK_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define AFI_IDDQ_MODE_ACK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_ACK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_ACK_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define AFI_IDDQ_MODE_ACK_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+//SM (system management) to PCIE PLL assert IDDQ Mode Ack
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_SHIFT                 _MK_SHIFT_CONST(0)
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_FIELD                 (_MK_MASK_CONST(0x1) << AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_SHIFT)
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_RANGE                 0:0
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_WOFFSET                       0x0
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_IDDQ_MODE_ACK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//SM (system management) to PCIE PLL deassert IDDQ Mode Ack
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_SHIFT                       _MK_SHIFT_CONST(1)
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_FIELD                       (_MK_MASK_CONST(0x1) << AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_SHIFT)
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_RANGE                       1:1
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_WOFFSET                     0x0
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_IDDQ_MODE_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_IDDQ_MODE_ACK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_PLL_RESET_ACK_0  
+#define AFI_PLL_RESET_ACK_0                     _MK_ADDR_CONST(0xe8)
+#define AFI_PLL_RESET_ACK_0_SECURE                      0x0
+#define AFI_PLL_RESET_ACK_0_WORD_COUNT                  0x1
+#define AFI_PLL_RESET_ACK_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_ACK_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define AFI_PLL_RESET_ACK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_ACK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_ACK_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define AFI_PLL_RESET_ACK_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+//SM (system management) to PCIE PLL assert Reset Ack
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_SHIFT                       _MK_SHIFT_CONST(0)
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_FIELD                       (_MK_MASK_CONST(0x1) << AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_SHIFT)
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_RANGE                       0:0
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_WOFFSET                     0x0
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_ASSERT_PEX0_PLL_RST_ACK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//SM (system management) to PCIE PLL deassert Reset Ack
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_SHIFT                     _MK_SHIFT_CONST(1)
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_FIELD                     (_MK_MASK_CONST(0x1) << AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_SHIFT)
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_RANGE                     1:1
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_WOFFSET                   0x0
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PLL_RESET_ACK_0_PCIE2SM_DEASSERT_PEX0_PLL_RST_ACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_PCIE_THROTTLE_0  
+#define AFI_PCIE_THROTTLE_0                     _MK_ADDR_CONST(0xec)
+#define AFI_PCIE_THROTTLE_0_SECURE                      0x0
+#define AFI_PCIE_THROTTLE_0_WORD_COUNT                  0x1
+#define AFI_PCIE_THROTTLE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define AFI_PCIE_THROTTLE_0_RESET_MASK                  _MK_MASK_CONST(0x8000fff7)
+#define AFI_PCIE_THROTTLE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AFI_PCIE_THROTTLE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AFI_PCIE_THROTTLE_0_READ_MASK                   _MK_MASK_CONST(0x8000fff7)
+#define AFI_PCIE_THROTTLE_0_WRITE_MASK                  _MK_MASK_CONST(0x8000fff7)
+//Override THERM MGMT duty cycle
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_FIELD                      (_MK_MASK_CONST(0x7) << AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_SHIFT)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_RANGE                      2:0
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_WOFFSET                    0x0
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_DUTY_CYCLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//Override THERM MGMT period
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_SHIFT                  _MK_SHIFT_CONST(4)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_FIELD                  (_MK_MASK_CONST(0xfff) << AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_SHIFT)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_RANGE                  15:4
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_WOFFSET                        0x0
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_PERIOD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//Override THERM MGMT 
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_FIELD                      (_MK_MASK_CONST(0x1) << AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_SHIFT)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_RANGE                      31:31
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_WOFFSET                    0x0
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_PCIE_THROTTLE_0_SM2PCIE_THROT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AFI_PME_0  
+#define AFI_PME_0                       _MK_ADDR_CONST(0xf0)
+#define AFI_PME_0_SECURE                        0x0
+#define AFI_PME_0_WORD_COUNT                    0x1
+#define AFI_PME_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_PME_0_RESET_MASK                    _MK_MASK_CONST(0x1ff1)
+#define AFI_PME_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_PME_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_PME_0_READ_MASK                     _MK_MASK_CONST(0x1ff1)
+#define AFI_PME_0_WRITE_MASK                    _MK_MASK_CONST(0x101)
+//SM (system management) to PCIE PME Turn Off
+#define AFI_PME_0_SM2TMS0C0_PME_TO_SHIFT                        _MK_SHIFT_CONST(0)
+#define AFI_PME_0_SM2TMS0C0_PME_TO_FIELD                        (_MK_MASK_CONST(0x1) << AFI_PME_0_SM2TMS0C0_PME_TO_SHIFT)
+#define AFI_PME_0_SM2TMS0C0_PME_TO_RANGE                        0:0
+#define AFI_PME_0_SM2TMS0C0_PME_TO_WOFFSET                      0x0
+#define AFI_PME_0_SM2TMS0C0_PME_TO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PME_0_SM2TMS0C0_PME_TO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_PME_0_SM2TMS0C0_PME_TO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PME_0_SM2TMS0C0_PME_TO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//PCIE Endpoint PME message
+#define AFI_PME_0_TMS0C02SM_PME_SHIFT                   _MK_SHIFT_CONST(4)
+#define AFI_PME_0_TMS0C02SM_PME_FIELD                   (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C02SM_PME_SHIFT)
+#define AFI_PME_0_TMS0C02SM_PME_RANGE                   4:4
+#define AFI_PME_0_TMS0C02SM_PME_WOFFSET                 0x0
+#define AFI_PME_0_TMS0C02SM_PME_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C02SM_PME_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_PME_0_TMS0C02SM_PME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C02SM_PME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//PCIE Endpoint PME Ack
+#define AFI_PME_0_TMS0C02SM_PME_ACK_SHIFT                       _MK_SHIFT_CONST(5)
+#define AFI_PME_0_TMS0C02SM_PME_ACK_FIELD                       (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C02SM_PME_ACK_SHIFT)
+#define AFI_PME_0_TMS0C02SM_PME_ACK_RANGE                       5:5
+#define AFI_PME_0_TMS0C02SM_PME_ACK_WOFFSET                     0x0
+#define AFI_PME_0_TMS0C02SM_PME_ACK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C02SM_PME_ACK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_PME_0_TMS0C02SM_PME_ACK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C02SM_PME_ACK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//PCIE Link Presence State
+#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_SHIFT                        _MK_SHIFT_CONST(6)
+#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_FIELD                        (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C02SM_PRESENCE_STATE_SHIFT)
+#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_RANGE                        6:6
+#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_WOFFSET                      0x0
+#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C02SM_PRESENCE_STATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//LTSSM ready for Power Down
+#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_SHIFT                    _MK_SHIFT_CONST(7)
+#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_FIELD                    (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_SHIFT)
+#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_RANGE                    7:7
+#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_WOFFSET                  0x0
+#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C02SM_LTSSM_READY_FOR_PD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//SM (system management) to PCIE PME Turn Off
+#define AFI_PME_0_SM2TMS0C1_PME_TO_SHIFT                        _MK_SHIFT_CONST(8)
+#define AFI_PME_0_SM2TMS0C1_PME_TO_FIELD                        (_MK_MASK_CONST(0x1) << AFI_PME_0_SM2TMS0C1_PME_TO_SHIFT)
+#define AFI_PME_0_SM2TMS0C1_PME_TO_RANGE                        8:8
+#define AFI_PME_0_SM2TMS0C1_PME_TO_WOFFSET                      0x0
+#define AFI_PME_0_SM2TMS0C1_PME_TO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PME_0_SM2TMS0C1_PME_TO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_PME_0_SM2TMS0C1_PME_TO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PME_0_SM2TMS0C1_PME_TO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//PCIE Endpoint PME message
+#define AFI_PME_0_TMS0C12SM_PME_SHIFT                   _MK_SHIFT_CONST(9)
+#define AFI_PME_0_TMS0C12SM_PME_FIELD                   (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C12SM_PME_SHIFT)
+#define AFI_PME_0_TMS0C12SM_PME_RANGE                   9:9
+#define AFI_PME_0_TMS0C12SM_PME_WOFFSET                 0x0
+#define AFI_PME_0_TMS0C12SM_PME_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C12SM_PME_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_PME_0_TMS0C12SM_PME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C12SM_PME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//PCIE Endpoint PME Ack
+#define AFI_PME_0_TMS0C12SM_PME_ACK_SHIFT                       _MK_SHIFT_CONST(10)
+#define AFI_PME_0_TMS0C12SM_PME_ACK_FIELD                       (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C12SM_PME_ACK_SHIFT)
+#define AFI_PME_0_TMS0C12SM_PME_ACK_RANGE                       10:10
+#define AFI_PME_0_TMS0C12SM_PME_ACK_WOFFSET                     0x0
+#define AFI_PME_0_TMS0C12SM_PME_ACK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C12SM_PME_ACK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_PME_0_TMS0C12SM_PME_ACK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C12SM_PME_ACK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//PCIE Link Presence State
+#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_SHIFT                        _MK_SHIFT_CONST(11)
+#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_FIELD                        (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C12SM_PRESENCE_STATE_SHIFT)
+#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_RANGE                        11:11
+#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_WOFFSET                      0x0
+#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C12SM_PRESENCE_STATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//LTSSM ready for Power Down
+#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_SHIFT                    _MK_SHIFT_CONST(12)
+#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_FIELD                    (_MK_MASK_CONST(0x1) << AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_SHIFT)
+#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_RANGE                    12:12
+#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_WOFFSET                  0x0
+#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PME_0_TMS0C12SM_LTSSM_READY_FOR_PD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AFI_REQ_PENDING_0  
+#define AFI_REQ_PENDING_0                       _MK_ADDR_CONST(0xf4)
+#define AFI_REQ_PENDING_0_SECURE                        0x0
+#define AFI_REQ_PENDING_0_WORD_COUNT                    0x1
+#define AFI_REQ_PENDING_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define AFI_REQ_PENDING_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define AFI_REQ_PENDING_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+//SM (system management) status that coherent request pending 
+//from PCIE to FPCI
+#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_FIELD                      (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_SHIFT)
+#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_RANGE                      0:0
+#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_WOFFSET                    0x0
+#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C02SM_COH_REQUEST_PEND_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//SM (system management) status that Non-coherent request pending 
+//from PCIE to FPCI
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_SHIFT                   _MK_SHIFT_CONST(1)
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_FIELD                   (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_SHIFT)
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_RANGE                   1:1
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_WOFFSET                 0x0
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONCOH_REQUEST_PEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//SM (system management) status that ISO request pending 
+//from PCIE to FPCI
+#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_SHIFT                   _MK_SHIFT_CONST(2)
+#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_FIELD                   (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_SHIFT)
+#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_RANGE                   2:2
+#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_WOFFSET                 0x0
+#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C02SM_ISO_PENDING_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//SM (system management) status that Non-ISO request pending 
+//from PCIE to FPCI
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_SHIFT                        _MK_SHIFT_CONST(3)
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_FIELD                        (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_SHIFT)
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_RANGE                        3:3
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_WOFFSET                      0x0
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C02SM_NONISO_PENDING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//SM (system management) status that coherent request pending 
+//from PCIE to FPCI
+#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_SHIFT                      _MK_SHIFT_CONST(4)
+#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_FIELD                      (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_SHIFT)
+#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_RANGE                      4:4
+#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_WOFFSET                    0x0
+#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C12SM_COH_REQUEST_PEND_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//SM (system management) status that Non-coherent request pending 
+//from PCIE to FPCI
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_SHIFT                   _MK_SHIFT_CONST(5)
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_FIELD                   (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_SHIFT)
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_RANGE                   5:5
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_WOFFSET                 0x0
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONCOH_REQUEST_PEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//SM (system management) status that ISO request pending 
+//from PCIE to FPCI
+#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_SHIFT                   _MK_SHIFT_CONST(6)
+#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_FIELD                   (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_SHIFT)
+#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_RANGE                   6:6
+#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_WOFFSET                 0x0
+#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C12SM_ISO_PENDING_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//SM (system management) status that Non-ISO request pending 
+//from PCIE to FPCI
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_SHIFT                        _MK_SHIFT_CONST(7)
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_FIELD                        (_MK_MASK_CONST(0x1) << AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_SHIFT)
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_RANGE                        7:7
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_WOFFSET                      0x0
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_REQ_PENDING_0_TMS0C12SM_NONISO_PENDING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register AFI_PCIE_CONFIG_0  
+#define AFI_PCIE_CONFIG_0                       _MK_ADDR_CONST(0xf8)
+#define AFI_PCIE_CONFIG_0_SECURE                        0x0
+#define AFI_PCIE_CONFIG_0_WORD_COUNT                    0x1
+#define AFI_PCIE_CONFIG_0_RESET_VAL                     _MK_MASK_CONST(0x3024)
+#define AFI_PCIE_CONFIG_0_RESET_MASK                    _MK_MASK_CONST(0xf1f1f7)
+#define AFI_PCIE_CONFIG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CONFIG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CONFIG_0_READ_MASK                     _MK_MASK_CONST(0xf1f1f7)
+#define AFI_PCIE_CONFIG_0_WRITE_MASK                    _MK_MASK_CONST(0xf1f1f7)
+//CYA to indicate PCIE slot empty.  Overrides PCIE slot present input.
+#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_SHIFT                       _MK_SHIFT_CONST(0)
+#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_FIELD                       (_MK_MASK_CONST(0x1) << AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_SHIFT)
+#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_RANGE                       0:0
+#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_WOFFSET                     0x0
+#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CONFIG_0_SM2TGIO_SLOT_EMPTY_PD_CYA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//Disable PCIE Controller 0 (default off)
+#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_SHIFT                   _MK_SHIFT_CONST(1)
+#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_FIELD                   (_MK_MASK_CONST(0x1) << AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_SHIFT)
+#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_RANGE                   1:1
+#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_WOFFSET                 0x0
+#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CONFIG_0_PCIEC0_DISABLE_DEVICE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Disable PCIE Controller 1 (default on)
+#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_SHIFT                   _MK_SHIFT_CONST(2)
+#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_FIELD                   (_MK_MASK_CONST(0x1) << AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_SHIFT)
+#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_RANGE                   2:2
+#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_WOFFSET                 0x0
+#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CONFIG_0_PCIEC1_DISABLE_DEVICE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//T0C0 Upstream FPCI Unit ID.  HyperTransport, upstream FPCI request
+#define AFI_PCIE_CONFIG_0_UNITID_T0C0_SHIFT                     _MK_SHIFT_CONST(4)
+#define AFI_PCIE_CONFIG_0_UNITID_T0C0_FIELD                     (_MK_MASK_CONST(0x1f) << AFI_PCIE_CONFIG_0_UNITID_T0C0_SHIFT)
+#define AFI_PCIE_CONFIG_0_UNITID_T0C0_RANGE                     8:4
+#define AFI_PCIE_CONFIG_0_UNITID_T0C0_WOFFSET                   0x0
+#define AFI_PCIE_CONFIG_0_UNITID_T0C0_DEFAULT                   _MK_MASK_CONST(0x2)
+#define AFI_PCIE_CONFIG_0_UNITID_T0C0_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define AFI_PCIE_CONFIG_0_UNITID_T0C0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CONFIG_0_UNITID_T0C0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//T0C1 Upstream FPCI Unit ID.  HyperTransport, upstream FPCI request
+//Downstream FPCI unit ID should remain 0.
+#define AFI_PCIE_CONFIG_0_UNITID_T0C1_SHIFT                     _MK_SHIFT_CONST(12)
+#define AFI_PCIE_CONFIG_0_UNITID_T0C1_FIELD                     (_MK_MASK_CONST(0x1f) << AFI_PCIE_CONFIG_0_UNITID_T0C1_SHIFT)
+#define AFI_PCIE_CONFIG_0_UNITID_T0C1_RANGE                     16:12
+#define AFI_PCIE_CONFIG_0_UNITID_T0C1_WOFFSET                   0x0
+#define AFI_PCIE_CONFIG_0_UNITID_T0C1_DEFAULT                   _MK_MASK_CONST(0x3)
+#define AFI_PCIE_CONFIG_0_UNITID_T0C1_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define AFI_PCIE_CONFIG_0_UNITID_T0C1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CONFIG_0_UNITID_T0C1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//SM (system management) configuration of PCIE crossbar.  
+//There are 2 possible configurations for PCIE crossbar:
+//  0  :  Single controller - T0C0 4 lanes
+//  1  :  Dual controller - T0C0 2 lanes/T0C1 2 lanes
+#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_SHIFT                     _MK_SHIFT_CONST(20)
+#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_FIELD                     (_MK_MASK_CONST(0xf) << AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_SHIFT)
+#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_RANGE                     23:20
+#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_WOFFSET                   0x0
+#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CONFIG_0_SM2TMS0_XBAR_CONFIG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_REV_ID_0  
+#define AFI_REV_ID_0                    _MK_ADDR_CONST(0xfc)
+#define AFI_REV_ID_0_SECURE                     0x0
+#define AFI_REV_ID_0_WORD_COUNT                         0x1
+#define AFI_REV_ID_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_REV_ID_0_RESET_MASK                         _MK_MASK_CONST(0x3)
+#define AFI_REV_ID_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_REV_ID_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_REV_ID_0_READ_MASK                  _MK_MASK_CONST(0x3)
+#define AFI_REV_ID_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
+//Override for PCI config revision id read-only register.  
+//This allows backdoor changes to rev ID for metal spins.
+#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_FIELD                   (_MK_MASK_CONST(0x1) << AFI_REV_ID_0_CFG_REVID_OVERRIDE_SHIFT)
+#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_RANGE                   0:0
+#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_WOFFSET                 0x0
+#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_REV_ID_0_CFG_REVID_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Write Enable for PCI backdoor rev ID override value.
+#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_SHIFT)
+#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_RANGE                       1:1
+#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_WOFFSET                     0x0
+#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_REV_ID_0_CFG_REVID_WRITE_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AFI_TOM_0  
+#define AFI_TOM_0                       _MK_ADDR_CONST(0x100)
+#define AFI_TOM_0_SECURE                        0x0
+#define AFI_TOM_0_WORD_COUNT                    0x1
+#define AFI_TOM_0_RESET_VAL                     _MK_MASK_CONST(0x3f3f003f)
+#define AFI_TOM_0_RESET_MASK                    _MK_MASK_CONST(0x3fff003f)
+#define AFI_TOM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_TOM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_TOM_0_READ_MASK                     _MK_MASK_CONST(0x3fff003f)
+#define AFI_TOM_0_WRITE_MASK                    _MK_MASK_CONST(0x3fff003f)
+//Top of Memory Limit 1.  Determines peer-to-peer range as:
+//{TOM1 :: 26'b0} to 0xFFFF_FFFF (except MSI region)
+#define AFI_TOM_0_DLDT2ALL_TOM1_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_TOM_0_DLDT2ALL_TOM1_FIELD                   (_MK_MASK_CONST(0x3f) << AFI_TOM_0_DLDT2ALL_TOM1_SHIFT)
+#define AFI_TOM_0_DLDT2ALL_TOM1_RANGE                   5:0
+#define AFI_TOM_0_DLDT2ALL_TOM1_WOFFSET                 0x0
+#define AFI_TOM_0_DLDT2ALL_TOM1_DEFAULT                 _MK_MASK_CONST(0x3f)
+#define AFI_TOM_0_DLDT2ALL_TOM1_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define AFI_TOM_0_DLDT2ALL_TOM1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_TOM_0_DLDT2ALL_TOM1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Top of Memory Limit 2.  Determines peer-to-peer range as:
+//{TOM2 :: 26'b0} to 0xFC_FFFF_FFFF
+#define AFI_TOM_0_DLDT2ALL_TOM2_SHIFT                   _MK_SHIFT_CONST(16)
+#define AFI_TOM_0_DLDT2ALL_TOM2_FIELD                   (_MK_MASK_CONST(0x3fff) << AFI_TOM_0_DLDT2ALL_TOM2_SHIFT)
+#define AFI_TOM_0_DLDT2ALL_TOM2_RANGE                   29:16
+#define AFI_TOM_0_DLDT2ALL_TOM2_WOFFSET                 0x0
+#define AFI_TOM_0_DLDT2ALL_TOM2_DEFAULT                 _MK_MASK_CONST(0x3f3f)
+#define AFI_TOM_0_DLDT2ALL_TOM2_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define AFI_TOM_0_DLDT2ALL_TOM2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_TOM_0_DLDT2ALL_TOM2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_FUSE_0  
+#define AFI_FUSE_0                      _MK_ADDR_CONST(0x104)
+#define AFI_FUSE_0_SECURE                       0x0
+#define AFI_FUSE_0_WORD_COUNT                   0x1
+#define AFI_FUSE_0_RESET_VAL                    _MK_MASK_CONST(0x336)
+#define AFI_FUSE_0_RESET_MASK                   _MK_MASK_CONST(0x777)
+#define AFI_FUSE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AFI_FUSE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AFI_FUSE_0_READ_MASK                    _MK_MASK_CONST(0x777)
+#define AFI_FUSE_0_WRITE_MASK                   _MK_MASK_CONST(0x777)
+//Enable advanced error reporting capability of PCIE.  
+//This should remain off for AP20.
+#define AFI_FUSE_0_FUSE_PCIE_AER_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define AFI_FUSE_0_FUSE_PCIE_AER_EN_FIELD                       (_MK_MASK_CONST(0x1) << AFI_FUSE_0_FUSE_PCIE_AER_EN_SHIFT)
+#define AFI_FUSE_0_FUSE_PCIE_AER_EN_RANGE                       0:0
+#define AFI_FUSE_0_FUSE_PCIE_AER_EN_WOFFSET                     0x0
+#define AFI_FUSE_0_FUSE_PCIE_AER_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_FUSE_0_FUSE_PCIE_AER_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AFI_FUSE_0_FUSE_PCIE_AER_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_FUSE_0_FUSE_PCIE_AER_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//Disable SLI capability for GPU.  This should remain on for AP20.
+#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_SHIFT                      _MK_SHIFT_CONST(1)
+#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_FIELD                      (_MK_MASK_CONST(0x1) << AFI_FUSE_0_FUSE_PCIE_SLI_DIS_SHIFT)
+#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_RANGE                      1:1
+#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_WOFFSET                    0x0
+#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_FUSE_0_FUSE_PCIE_SLI_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//Disable Gen 2 capability of PCIE.  This should remain on for AP20.
+#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_SHIFT                  _MK_SHIFT_CONST(2)
+#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_FIELD                  (_MK_MASK_CONST(0x1) << AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_SHIFT)
+#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_RANGE                  2:2
+#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_WOFFSET                        0x0
+#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_FUSE_0_FUSE_PCIE_T0_GEN2_DIS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//Configure PCIE as x1, x2, x4, x8, or x16.  
+//This should remain 3'b011 for AP20
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_SHIFT                   _MK_SHIFT_CONST(4)
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_FIELD                   (_MK_MASK_CONST(0x7) << AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_SHIFT)
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_RANGE                   6:4
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_WOFFSET                 0x0
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_DEFAULT                 _MK_MASK_CONST(0x3)
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Configure PCIE as x1, x2, x4, x8, or x16.  
+//This should remain 3'b011 for AP20
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_SHIFT                   _MK_SHIFT_CONST(8)
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_FIELD                   (_MK_MASK_CONST(0x7) << AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_SHIFT)
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_RANGE                   10:8
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_WOFFSET                 0x0
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_DEFAULT                 _MK_MASK_CONST(0x3)
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_FUSE_0_FUSE_PCIE_WIDTH_T0C1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_PMU_0  
+#define AFI_PMU_0                       _MK_ADDR_CONST(0x108)
+#define AFI_PMU_0_SECURE                        0x0
+#define AFI_PMU_0_WORD_COUNT                    0x1
+#define AFI_PMU_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_RESET_MASK                    _MK_MASK_CONST(0x1f1fff1)
+#define AFI_PMU_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_READ_MASK                     _MK_MASK_CONST(0x1f1fff1)
+#define AFI_PMU_0_WRITE_MASK                    _MK_MASK_CONST(0xff1)
+//PMU Load Indicator Enable.  
+//This is used for wall-plug applications and should remain off for AP20.
+#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_SHIFT                      _MK_SHIFT_CONST(0)
+#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_FIELD                      (_MK_MASK_CONST(0x1) << AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_SHIFT)
+#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_RANGE                      0:0
+#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_WOFFSET                    0x0
+#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_PMU2ALL_LI_UPDATE_FAST_TOG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//PMU Load Indicator Scale for T0C0
+#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_SHIFT                     _MK_SHIFT_CONST(4)
+#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_FIELD                     (_MK_MASK_CONST(0xf) << AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_SHIFT)
+#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_RANGE                     7:4
+#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_WOFFSET                   0x0
+#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_PMU2CTLR_T0_C0_LOAD_INDICATOR_SCALE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//PMU Load Indicator Scale for T0C1
+#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_SHIFT                     _MK_SHIFT_CONST(8)
+#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_FIELD                     (_MK_MASK_CONST(0xf) << AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_SHIFT)
+#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_RANGE                     11:8
+#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_WOFFSET                   0x0
+#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_PMU2CTLR_T0_C1_LOAD_INDICATOR_SCALE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//PMU Status
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_SHIFT                  _MK_SHIFT_CONST(12)
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_FIELD                  (_MK_MASK_CONST(0xf) << AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_SHIFT)
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_RANGE                  15:12
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_WOFFSET                        0x0
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//PMU toggle response from PCIE
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_SHIFT                     _MK_SHIFT_CONST(16)
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_FIELD                     (_MK_MASK_CONST(0x1) << AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_SHIFT)
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_RANGE                     16:16
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_WOFFSET                   0x0
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_CTLR_T0_C0_2PMU_TOG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//PMU Status
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_SHIFT                  _MK_SHIFT_CONST(20)
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_FIELD                  (_MK_MASK_CONST(0xf) << AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_SHIFT)
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_RANGE                  23:20
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_WOFFSET                        0x0
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//PMU toggle response from PCIE
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_SHIFT                     _MK_SHIFT_CONST(24)
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_FIELD                     (_MK_MASK_CONST(0x1) << AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_SHIFT)
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_RANGE                     24:24
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_WOFFSET                   0x0
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PMU_0_CTLR_T0_C1_2PMU_TOG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AFI_PCIE_CLK_CONFIG_STATUS_0  
+#define AFI_PCIE_CLK_CONFIG_STATUS_0                    _MK_ADDR_CONST(0x10c)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_SECURE                     0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_WORD_COUNT                         0x1
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0xff3f1f)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_READ_MASK                  _MK_MASK_CONST(0xff3f1f)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
+//Acknowledge to Select XCLK Gen2 request.  
+//This should remain low for AP20.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_SHIFT                  _MK_SHIFT_CONST(0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_FIELD                  (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_RANGE                  0:0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_WOFFSET                        0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0_RDY_XCLK_GEN2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//Acknowledge to Select T0C0 XTXCLK1X Gen2 request.  
+//This should remain low for AP20.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_SHIFT                    _MK_SHIFT_CONST(1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_FIELD                    (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_RANGE                    1:1
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_WOFFSET                  0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_RDY_XTXCLK1X_GEN2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//Acknowledge to Disable T0C0 XTXCLK1X request.  Used for clock gating.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_SHIFT                 _MK_SHIFT_CONST(2)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_FIELD                 (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_RANGE                 2:2
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_WOFFSET                       0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C0_OFF_XTXCLK1X_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//Acknowledge to Select T0C0 XTXCLK1X Gen2 request.  
+//This should remain low for AP20.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_SHIFT                    _MK_SHIFT_CONST(3)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_FIELD                    (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_RANGE                    3:3
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_WOFFSET                  0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_RDY_XTXCLK1X_GEN2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//Acknowledge to Disable T0C0 XTXCLK1X request.  Used for clock gating.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_SHIFT                 _MK_SHIFT_CONST(4)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_FIELD                 (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_RANGE                 4:4
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_WOFFSET                       0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_CLK2PCIE_TMS0C1_OFF_XTXCLK1X_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//Request to select Gen2 speed clock (500 MHz) for XCLK.  
+//This is generated when register settings for PCIE2 specify 
+//Gen2 speed clocks. This should remain low for AP20.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_SHIFT                  _MK_SHIFT_CONST(8)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_FIELD                  (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_RANGE                  8:8
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_WOFFSET                        0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_SEL_XCLK_GEN2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//Request to select Gen2 speed clock (500 MHz) for T0C0 XTXCLK1X.  
+//This is generated when register settings for PCIE2 specify 
+//Gen2 speed clocks. This should remain low for AP20.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_SHIFT                    _MK_SHIFT_CONST(9)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_FIELD                    (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_RANGE                    9:9
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_WOFFSET                  0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_SEL_XTXCLK1X_GEN2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//Request to select Gen2 speed clock (500 MHz) for T0C1 XTXCLK1X.  
+//This is generated when register settings for PCIE2 specify 
+//Gen2 speed clocks. This should remain low for AP20.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_SHIFT                    _MK_SHIFT_CONST(10)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_FIELD                    (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_RANGE                    10:10
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_WOFFSET                  0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_SEL_XTXCLK1X_GEN2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//Request to gate TMS/FPCI clocks when in low power mode.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_SHIFT                   _MK_SHIFT_CONST(11)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_FIELD                   (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_RANGE                   11:11
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_WOFFSET                 0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0_CLAMP_CLK_L1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Request to gate T0C0 XTXCLK1X when in low power mode.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_SHIFT                 _MK_SHIFT_CONST(12)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_FIELD                 (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_RANGE                 12:12
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_WOFFSET                       0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C0_DIS_XTXCLK1X_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//Request to gate T0C1 XTXCLK1X when in low power mode.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_SHIFT                 _MK_SHIFT_CONST(13)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_FIELD                 (_MK_MASK_CONST(0x1) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_RANGE                 13:13
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_WOFFSET                       0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0C1_DIS_XTXCLK1X_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//Clock select to pad macro.  For AP20, this should remain 0.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_FIELD                  (_MK_MASK_CONST(0xf) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_RANGE                  19:16
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_WOFFSET                        0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP0_PAD_MACRO_CLK_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//Clock select to pad macro.  For AP20, this should remain 0.
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_SHIFT                  _MK_SHIFT_CONST(20)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_FIELD                  (_MK_MASK_CONST(0xf) << AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_SHIFT)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_RANGE                  23:20
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_WOFFSET                        0x0
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AFI_PCIE_CLK_CONFIG_STATUS_0_PCIE2CLK_TMS0GRP1_PAD_MACRO_CLK_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register AFI_PEX0_CTRL_0  
+#define AFI_PEX0_CTRL_0                 _MK_ADDR_CONST(0x110)
+#define AFI_PEX0_CTRL_0_SECURE                  0x0
+#define AFI_PEX0_CTRL_0_WORD_COUNT                      0x1
+#define AFI_PEX0_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AFI_PEX0_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0x89)
+#define AFI_PEX0_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_PEX0_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_PEX0_CTRL_0_READ_MASK                       _MK_MASK_CONST(0x89)
+#define AFI_PEX0_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x89)
+//PEX0 external pe0_rst_l register
+#define AFI_PEX0_CTRL_0_PEX0_RST_L_SHIFT                        _MK_SHIFT_CONST(0)
+#define AFI_PEX0_CTRL_0_PEX0_RST_L_FIELD                        (_MK_MASK_CONST(0x1) << AFI_PEX0_CTRL_0_PEX0_RST_L_SHIFT)
+#define AFI_PEX0_CTRL_0_PEX0_RST_L_RANGE                        0:0
+#define AFI_PEX0_CTRL_0_PEX0_RST_L_WOFFSET                      0x0
+#define AFI_PEX0_CTRL_0_PEX0_RST_L_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PEX0_CTRL_0_PEX0_RST_L_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_PEX0_CTRL_0_PEX0_RST_L_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PEX0_CTRL_0_PEX0_RST_L_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//PEX0 enable to clkout pad
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_SHIFT                    _MK_SHIFT_CONST(3)
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_FIELD                    (_MK_MASK_CONST(0x1) << AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_SHIFT)
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_RANGE                    3:3
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_WOFFSET                  0x0
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//PEX0 refclk select 0=PLLE, 1=PHY REFCLK
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_SHIFT                   _MK_SHIFT_CONST(7)
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_FIELD                   (_MK_MASK_CONST(0x1) << AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_SHIFT)
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_RANGE                   7:7
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_WOFFSET                 0x0
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PEX0_CTRL_0_PEX0_REFCLK_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_PEX0_STATUS_0  
+#define AFI_PEX0_STATUS_0                       _MK_ADDR_CONST(0x114)
+#define AFI_PEX0_STATUS_0_SECURE                        0x0
+#define AFI_PEX0_STATUS_0_WORD_COUNT                    0x1
+#define AFI_PEX0_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_PEX0_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_PEX0_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_PEX0_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_PEX0_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_PEX0_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+//status PEX0 pe0_clkreq_l input
+#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_FIELD                   (_MK_MASK_CONST(0x1) << AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_SHIFT)
+#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_RANGE                   0:0
+#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_WOFFSET                 0x0
+#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PEX0_STATUS_0_PEX0_CLKREQ_L_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_PEX1_CTRL_0  
+#define AFI_PEX1_CTRL_0                 _MK_ADDR_CONST(0x118)
+#define AFI_PEX1_CTRL_0_SECURE                  0x0
+#define AFI_PEX1_CTRL_0_WORD_COUNT                      0x1
+#define AFI_PEX1_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AFI_PEX1_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0x89)
+#define AFI_PEX1_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_PEX1_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_PEX1_CTRL_0_READ_MASK                       _MK_MASK_CONST(0x89)
+#define AFI_PEX1_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x89)
+//PEX1 external pe1_rst_l register
+#define AFI_PEX1_CTRL_0_PEX1_RST_L_SHIFT                        _MK_SHIFT_CONST(0)
+#define AFI_PEX1_CTRL_0_PEX1_RST_L_FIELD                        (_MK_MASK_CONST(0x1) << AFI_PEX1_CTRL_0_PEX1_RST_L_SHIFT)
+#define AFI_PEX1_CTRL_0_PEX1_RST_L_RANGE                        0:0
+#define AFI_PEX1_CTRL_0_PEX1_RST_L_WOFFSET                      0x0
+#define AFI_PEX1_CTRL_0_PEX1_RST_L_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PEX1_CTRL_0_PEX1_RST_L_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AFI_PEX1_CTRL_0_PEX1_RST_L_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AFI_PEX1_CTRL_0_PEX1_RST_L_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//PEX1 enable to clkout pad
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_SHIFT                    _MK_SHIFT_CONST(3)
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_FIELD                    (_MK_MASK_CONST(0x1) << AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_SHIFT)
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_RANGE                    3:3
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_WOFFSET                  0x0
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//PEX1 refclk select 0=PLLE, 1=PHY REFCLK
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_SHIFT                   _MK_SHIFT_CONST(7)
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_FIELD                   (_MK_MASK_CONST(0x1) << AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_SHIFT)
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_RANGE                   7:7
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_WOFFSET                 0x0
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PEX1_CTRL_0_PEX1_REFCLK_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_PEX1_STATUS_0  
+#define AFI_PEX1_STATUS_0                       _MK_ADDR_CONST(0x11c)
+#define AFI_PEX1_STATUS_0_SECURE                        0x0
+#define AFI_PEX1_STATUS_0_WORD_COUNT                    0x1
+#define AFI_PEX1_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AFI_PEX1_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_PEX1_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AFI_PEX1_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AFI_PEX1_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define AFI_PEX1_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+//status PEX1 pe1_clkreq_l input
+#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_FIELD                   (_MK_MASK_CONST(0x1) << AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_SHIFT)
+#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_RANGE                   0:0
+#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_WOFFSET                 0x0
+#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_PEX1_STATUS_0_PEX1_CLKREQ_L_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_WR_SCRATCH_0  
+#define AFI_WR_SCRATCH_0                        _MK_ADDR_CONST(0x120)
+#define AFI_WR_SCRATCH_0_SECURE                         0x0
+#define AFI_WR_SCRATCH_0_WORD_COUNT                     0x1
+#define AFI_WR_SCRATCH_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AFI_WR_SCRATCH_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AFI_WR_SCRATCH_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AFI_WR_SCRATCH_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AFI_WR_SCRATCH_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AFI_WR_SCRATCH_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+//Scratch registers to write
+#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_FIELD                   (_MK_MASK_CONST(0xffffffff) << AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_SHIFT)
+#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_RANGE                   31:0
+#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_WOFFSET                 0x0
+#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_WR_SCRATCH_0_AFI_WR_SCRATCH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_RD_SCRATCH_0  
+#define AFI_RD_SCRATCH_0                        _MK_ADDR_CONST(0x124)
+#define AFI_RD_SCRATCH_0_SECURE                         0x0
+#define AFI_RD_SCRATCH_0_WORD_COUNT                     0x1
+#define AFI_RD_SCRATCH_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AFI_RD_SCRATCH_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AFI_RD_SCRATCH_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AFI_RD_SCRATCH_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AFI_RD_SCRATCH_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AFI_RD_SCRATCH_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+//Scratch registers to read 
+#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_SHIFT                   _MK_SHIFT_CONST(0)
+#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_FIELD                   (_MK_MASK_CONST(0xffffffff) << AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_SHIFT)
+#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_RANGE                   31:0
+#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_WOFFSET                 0x0
+#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AFI_RD_SCRATCH_0_AFI_RD_SCRATCH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AFI_DUMMY_REG_0  
+#define AFI_DUMMY_REG_0                 _MK_ADDR_CONST(0x128)
+#define AFI_DUMMY_REG_0_SECURE                  0x0
+#define AFI_DUMMY_REG_0_WORD_COUNT                      0x1
+#define AFI_DUMMY_REG_0_RESET_VAL                       _MK_MASK_CONST(0x1)
+#define AFI_DUMMY_REG_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_DUMMY_REG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AFI_DUMMY_REG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AFI_DUMMY_REG_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define AFI_DUMMY_REG_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+//Dummy register
+#define AFI_DUMMY_REG_0_DUMMY_SHIFT                     _MK_SHIFT_CONST(0)
+#define AFI_DUMMY_REG_0_DUMMY_FIELD                     (_MK_MASK_CONST(0x1) << AFI_DUMMY_REG_0_DUMMY_SHIFT)
+#define AFI_DUMMY_REG_0_DUMMY_RANGE                     0:0
+#define AFI_DUMMY_REG_0_DUMMY_WOFFSET                   0x0
+#define AFI_DUMMY_REG_0_DUMMY_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AFI_DUMMY_REG_0_DUMMY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AFI_DUMMY_REG_0_DUMMY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AFI_DUMMY_REG_0_DUMMY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Packet PCIE_INTINFO_ADDR
+#define PCIE_INTINFO_ADDR_SIZE 30
+
+//When interrupt code is not equal to 6, the INT_INFO field of the
+//interrupt signature register contains either the AXI or FPCI address
+//bits[31:2] of the read or write transaction causing the interrupt
+#define PCIE_INTINFO_ADDR_INTERRUPT_ADDRESS_SHIFT                       _MK_SHIFT_CONST(2)
+#define PCIE_INTINFO_ADDR_INTERRUPT_ADDRESS_FIELD                       (_MK_MASK_CONST(0x3fffffff) << PCIE_INTINFO_ADDR_INTERRUPT_ADDRESS_SHIFT)
+#define PCIE_INTINFO_ADDR_INTERRUPT_ADDRESS_RANGE                       _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(2)
+#define PCIE_INTINFO_ADDR_INTERRUPT_ADDRESS_ROW                 0
+
+
+// Packet PCIE_INTINFO_SM
+#define PCIE_INTINFO_SM_SIZE 13
+
+//Unit ID of the PCIE2 controller generating the system management message.
+//This will correspond to UNITID_T0C0 or UNITID_T0C1 of PCIE_CONFIG register.
+#define PCIE_INTINFO_SM_SM_UNIT_ID_SHIFT                        _MK_SHIFT_CONST(10)
+#define PCIE_INTINFO_SM_SM_UNIT_ID_FIELD                        (_MK_MASK_CONST(0x1f) << PCIE_INTINFO_SM_SM_UNIT_ID_SHIFT)
+#define PCIE_INTINFO_SM_SM_UNIT_ID_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(10)
+#define PCIE_INTINFO_SM_SM_UNIT_ID_ROW                  0
+
+//System management message
+#define PCIE_INTINFO_SM_SM_MESSAGE_SHIFT                        _MK_SHIFT_CONST(2)
+#define PCIE_INTINFO_SM_SM_MESSAGE_FIELD                        (_MK_MASK_CONST(0x1f) << PCIE_INTINFO_SM_SM_MESSAGE_SHIFT)
+#define PCIE_INTINFO_SM_SM_MESSAGE_RANGE                        _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(2)
+#define PCIE_INTINFO_SM_SM_MESSAGE_ROW                  0
+#define PCIE_INTINFO_SM_SM_MESSAGE_INTA_ASSERT                  _MK_ENUM_CONST(16)    // //Interrupt A Assertion
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_INTB_ASSERT                  _MK_ENUM_CONST(20)    // //Interrupt B Assertion
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_INTC_ASSERT                  _MK_ENUM_CONST(24)    // //Interrupt C Assertion
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_INTD_ASSERT                  _MK_ENUM_CONST(28)    // //Interrupt D Assertion
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_INTA_DEASSERT                        _MK_ENUM_CONST(0)    // //Interrupt A Deassertion
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_INTB_DEASSERT                        _MK_ENUM_CONST(4)    // //Interrupt B Deassertion
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_INTC_DEASSERT                        _MK_ENUM_CONST(8)    // //Interrupt C Deassertion
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_INTD_DEASSERT                        _MK_ENUM_CONST(12)    // //Interrupt D Deassertion
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_ERR_CORRECTABLE                      _MK_ENUM_CONST(1)    // //Correctable Error
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_ERR_UNCORRECTABLE_NONFATAL                   _MK_ENUM_CONST(5)    // //Un-Correctable Non-Fatal Error
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_ERR_UNCORRECTABLE_FATAL                      _MK_ENUM_CONST(9)    // //Un-Correctable Fatal Error
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_PME_ASSERT                   _MK_ENUM_CONST(2)    // //PME Assertion
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_HOTPLUG_ASSERT                       _MK_ENUM_CONST(6)    // //Hotplug Assertion
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_RP_ASSERT                    _MK_ENUM_CONST(19)    // //Root Port Assertion
+
+#define PCIE_INTINFO_SM_SM_MESSAGE_RP_DEASSERT                  _MK_ENUM_CONST(3)    // //Root Port Deassertion
+
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAFI_REGS(_op_) \
+_op_(AFI_AXI_BAR0_SZ_0) \
+_op_(AFI_AXI_BAR1_SZ_0) \
+_op_(AFI_AXI_BAR2_SZ_0) \
+_op_(AFI_AXI_BAR3_SZ_0) \
+_op_(AFI_AXI_BAR4_SZ_0) \
+_op_(AFI_AXI_BAR5_SZ_0) \
+_op_(AFI_AXI_BAR0_START_0) \
+_op_(AFI_AXI_BAR1_START_0) \
+_op_(AFI_AXI_BAR2_START_0) \
+_op_(AFI_AXI_BAR3_START_0) \
+_op_(AFI_AXI_BAR4_START_0) \
+_op_(AFI_AXI_BAR5_START_0) \
+_op_(AFI_FPCI_BAR0_0) \
+_op_(AFI_FPCI_BAR1_0) \
+_op_(AFI_FPCI_BAR2_0) \
+_op_(AFI_FPCI_BAR3_0) \
+_op_(AFI_FPCI_BAR4_0) \
+_op_(AFI_FPCI_BAR5_0) \
+_op_(AFI_CACHE_BAR0_SZ_0) \
+_op_(AFI_CACHE_BAR0_ST_0) \
+_op_(AFI_CACHE_BAR1_SZ_0) \
+_op_(AFI_CACHE_BAR1_ST_0) \
+_op_(AFI_IO_BAR_SZ_0) \
+_op_(AFI_IO_BAR_ST_0) \
+_op_(AFI_MSI_BAR_SZ_0) \
+_op_(AFI_MSI_FPCI_BAR_ST_0) \
+_op_(AFI_MSI_AXI_BAR_ST_0) \
+_op_(AFI_MSI_VEC0_0) \
+_op_(AFI_MSI_VEC1_0) \
+_op_(AFI_MSI_VEC2_0) \
+_op_(AFI_MSI_VEC3_0) \
+_op_(AFI_MSI_VEC4_0) \
+_op_(AFI_MSI_VEC5_0) \
+_op_(AFI_MSI_VEC6_0) \
+_op_(AFI_MSI_VEC7_0) \
+_op_(AFI_MSI_EN_VEC0_0) \
+_op_(AFI_MSI_EN_VEC1_0) \
+_op_(AFI_MSI_EN_VEC2_0) \
+_op_(AFI_MSI_EN_VEC3_0) \
+_op_(AFI_MSI_EN_VEC4_0) \
+_op_(AFI_MSI_EN_VEC5_0) \
+_op_(AFI_MSI_EN_VEC6_0) \
+_op_(AFI_MSI_EN_VEC7_0) \
+_op_(AFI_CONFIGURATION_0) \
+_op_(AFI_FPCI_ERROR_MASKS_0) \
+_op_(AFI_INTR_MASK_0) \
+_op_(AFI_INTR_CODE_0) \
+_op_(AFI_INTR_SIGNATURE_0) \
+_op_(AFI_UPPER_FPCI_ADDR_0) \
+_op_(AFI_SM_INTR_ENABLE_0) \
+_op_(AFI_AFI_INTR_ENABLE_0) \
+_op_(AFI_AUSER_OVERRIDE_0) \
+_op_(AFI_ACACHE_OVERRIDE_0) \
+_op_(AFI_APROT_OVERRIDE_0) \
+_op_(AFI_FPCI_TIMEOUT_0) \
+_op_(AFI_IDDQ_MODE_0) \
+_op_(AFI_PLL_RESET_0) \
+_op_(AFI_IDDQ_MODE_ACK_0) \
+_op_(AFI_PLL_RESET_ACK_0) \
+_op_(AFI_PCIE_THROTTLE_0) \
+_op_(AFI_PME_0) \
+_op_(AFI_REQ_PENDING_0) \
+_op_(AFI_PCIE_CONFIG_0) \
+_op_(AFI_REV_ID_0) \
+_op_(AFI_TOM_0) \
+_op_(AFI_FUSE_0) \
+_op_(AFI_PMU_0) \
+_op_(AFI_PCIE_CLK_CONFIG_STATUS_0) \
+_op_(AFI_PEX0_CTRL_0) \
+_op_(AFI_PEX0_STATUS_0) \
+_op_(AFI_PEX1_CTRL_0) \
+_op_(AFI_PEX1_STATUS_0) \
+_op_(AFI_WR_SCRATCH_0) \
+_op_(AFI_RD_SCRATCH_0) \
+_op_(AFI_DUMMY_REG_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_AFI        0x00000000
+
+//
+// ARAFI REGISTER BANKS
+//
+
+#define AFI0_FIRST_REG 0x0000 // AFI_AXI_BAR0_SZ_0
+#define AFI0_LAST_REG 0x0128 // AFI_DUMMY_REG_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAFI_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arahb_arbc.h b/arch/arm/mach-tegra/nv/include/ap20/arahb_arbc.h
new file mode 100644
index 000000000000..a080ae40d835
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arahb_arbc.h
@@ -0,0 +1,3739 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAHB_ARBC_H_INC_
+#define ___ARAHB_ARBC_H_INC_
+
+// Register AHB_ARBITRATION_DISABLE_0  
+#define AHB_ARBITRATION_DISABLE_0                       _MK_ADDR_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SECURE                        0x0
+#define AHB_ARBITRATION_DISABLE_0_WORD_COUNT                    0x1
+#define AHB_ARBITRATION_DISABLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_RESET_MASK                    _MK_MASK_CONST(0x801f3fff)
+#define AHB_ARBITRATION_DISABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_READ_MASK                     _MK_MASK_CONST(0x801f3fff)
+#define AHB_ARBITRATION_DISABLE_0_WRITE_MASK                    _MK_MASK_CONST(0x801f3fff)
+//  1 = disable bus parking.
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SHIFT                    _MK_SHIFT_CONST(31)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_RANGE                    31:31
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_DIS_BUS_PARK_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable SDMMC3 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_SHIFT                  _MK_SHIFT_CONST(20)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDMMC3_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_RANGE                  20:20
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC3_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable SDMMC2 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_SHIFT                  _MK_SHIFT_CONST(19)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDMMC2_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_RANGE                  19:19
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC2_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable USB2 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_USB2_SHIFT                    _MK_SHIFT_CONST(18)
+#define AHB_ARBITRATION_DISABLE_0_USB2_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_USB2_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_USB2_RANGE                    18:18
+#define AHB_ARBITRATION_DISABLE_0_USB2_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_USB2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_USB2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB2_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_USB2_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable USB3 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_USB3_SHIFT                    _MK_SHIFT_CONST(17)
+#define AHB_ARBITRATION_DISABLE_0_USB3_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_USB3_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_USB3_RANGE                    17:17
+#define AHB_ARBITRATION_DISABLE_0_USB3_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_USB3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_USB3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB3_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_USB3_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable BSEA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SHIFT                    _MK_SHIFT_CONST(16)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_BSEA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_RANGE                    16:16
+#define AHB_ARBITRATION_DISABLE_0_BSEA_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_BSEA_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable BSEV from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_BSEV_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_RANGE                    13:13
+#define AHB_ARBITRATION_DISABLE_0_BSEV_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_BSEV_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable SDMMC4 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_SHIFT                  _MK_SHIFT_CONST(12)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDMMC4_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_RANGE                  12:12
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC4_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable SNOR from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SNOR_SHIFT                    _MK_SHIFT_CONST(11)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SNOR_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_RANGE                    11:11
+#define AHB_ARBITRATION_DISABLE_0_SNOR_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_SNOR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SNOR_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable NAND from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_NAND_SHIFT                    _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_DISABLE_0_NAND_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_NAND_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_NAND_RANGE                    10:10
+#define AHB_ARBITRATION_DISABLE_0_NAND_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_NAND_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_NAND_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_NAND_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable SDMMC1 from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_SHIFT                  _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_SDMMC1_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_RANGE                  9:9
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_SDMMC1_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable XIO from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_XIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_DISABLE_0_XIO_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_XIO_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_XIO_RANGE                     8:8
+#define AHB_ARBITRATION_DISABLE_0_XIO_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_XIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_XIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_XIO_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable APB-DMA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SHIFT                  _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_APBDMA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_RANGE                  7:7
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_APBDMA_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable USB from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_USB_SHIFT                     _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_DISABLE_0_USB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_USB_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_USB_RANGE                     6:6
+#define AHB_ARBITRATION_DISABLE_0_USB_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_USB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_USB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_USB_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_USB_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable AHB-DMA from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SHIFT                  _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_AHBDMA_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_RANGE                  5:5
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_WOFFSET                        0x0
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_ENABLE                 _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_AHBDMA_DISABLE                        _MK_ENUM_CONST(1)
+
+//  1 = disable EIDE from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SHIFT                    _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_EIDE_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_RANGE                    4:4
+#define AHB_ARBITRATION_DISABLE_0_EIDE_WOFFSET                  0x0
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_ENABLE                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_EIDE_DISABLE                  _MK_ENUM_CONST(1)
+
+//  1 = disable CoreSight from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_CSITE_SHIFT                   _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_CSITE_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_RANGE                   3:3
+#define AHB_ARBITRATION_DISABLE_0_CSITE_WOFFSET                 0x0
+#define AHB_ARBITRATION_DISABLE_0_CSITE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_ENABLE                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_CSITE_DISABLE                 _MK_ENUM_CONST(1)
+
+//  1 = disable VCP from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_VCP_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_DISABLE_0_VCP_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_VCP_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_VCP_RANGE                     2:2
+#define AHB_ARBITRATION_DISABLE_0_VCP_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_VCP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_VCP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_VCP_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable COP from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_COP_SHIFT                     _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_DISABLE_0_COP_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_COP_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_COP_RANGE                     1:1
+#define AHB_ARBITRATION_DISABLE_0_COP_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_COP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_COP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_COP_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_COP_DISABLE                   _MK_ENUM_CONST(1)
+
+//  1 = disable CPU from arbitration.
+#define AHB_ARBITRATION_DISABLE_0_CPU_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_DISABLE_0_CPU_SHIFT)
+#define AHB_ARBITRATION_DISABLE_0_CPU_RANGE                     0:0
+#define AHB_ARBITRATION_DISABLE_0_CPU_WOFFSET                   0x0
+#define AHB_ARBITRATION_DISABLE_0_CPU_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_DISABLE_0_CPU_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_DISABLE_0_CPU_DISABLE                   _MK_ENUM_CONST(1)
+
+
+// Register AHB_ARBITRATION_PRIORITY_CTRL_0  ///////////////////////////////////////////////////////////////////////////////////////////////////////////////
+//
+//  The AHB arbiter implements a 2-level priority scheme.  In the 1st level, arbitration is determined between
+//  the high and low priority group according to the priority weight; the higher the weight, the higher the
+//  winning rate of the high priority group.  In the 2nd level, within each of the high/low priority group, 
+//  arbitration is determined in a round-robin fashion.
+//
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////
+#define AHB_ARBITRATION_PRIORITY_CTRL_0                 _MK_ADDR_CONST(0x4)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_SECURE                  0x0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_WORD_COUNT                      0x1
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// AHB priority weight count. This 3-bit field is  use to control 
+// the amount of attention (weight) giving to the high priority 
+// group before switching to the low priority group.
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SHIFT                       _MK_SHIFT_CONST(29)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_FIELD                       (_MK_MASK_CONST(0x7) << AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SHIFT)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_RANGE                       31:29
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_WOFFSET                     0x0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_WEIGHT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = low priority
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_FIELD                       (_MK_MASK_CONST(0x1fffffff) << AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SHIFT)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_RANGE                       28:0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_WOFFSET                     0x0
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1fffffff)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_PRIORITY_CTRL_0_AHB_PRIORITY_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_USR_PROTECT_0  
+#define AHB_ARBITRATION_USR_PROTECT_0                   _MK_ADDR_CONST(0x8)
+#define AHB_ARBITRATION_USR_PROTECT_0_SECURE                    0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_WORD_COUNT                        0x1
+#define AHB_ARBITRATION_USR_PROTECT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_RESET_MASK                        _MK_MASK_CONST(0x1ff)
+#define AHB_ARBITRATION_USR_PROTECT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_READ_MASK                         _MK_MASK_CONST(0x1ff)
+#define AHB_ARBITRATION_USR_PROTECT_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Abort on USR mode access to Cache memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SHIFT                       _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_RANGE                       8:8
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_CACHE_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to internal ROM memory  space
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_ROM_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_RANGE                 7:7
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_ROM_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to APB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SHIFT                 _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_APB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_RANGE                 6:6
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_APB_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to AHB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SHIFT                 _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_AHB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_RANGE                 5:5
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_WOFFSET                       0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_AHB_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to PPSB memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SHIFT                        _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_FIELD                        (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_RANGE                        4:4
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_WOFFSET                      0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_ABT_DIS                      _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_PPSB_ABT_EN                       _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMd memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_RANGE                       3:3
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMD_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMc memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SHIFT                       _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_RANGE                       2:2
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMC_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMb memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_RANGE                       1:1
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMB_ABT_EN                      _MK_ENUM_CONST(1)
+
+// Abort on USR mode access to iRAMa memory space
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_RANGE                       0:0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_WOFFSET                     0x0
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_USR_PROTECT_0_IRAMA_ABT_EN                      _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_AHB_MEM_0  
+#define AHB_GIZMO_AHB_MEM_0                     _MK_ADDR_CONST(0xc)
+#define AHB_GIZMO_AHB_MEM_0_SECURE                      0x0
+#define AHB_GIZMO_AHB_MEM_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_AHB_MEM_0_RESET_VAL                   _MK_MASK_CONST(0x200c1)
+#define AHB_GIZMO_AHB_MEM_0_RESET_MASK                  _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_AHB_MEM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_READ_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_AHB_MEM_0_WRITE_MASK                  _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit counter use to indicate 
+// the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SHIFT                   _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_FIELD                   (_MK_MASK_CONST(0xff) << AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_RANGE                   31:24
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_REQ_NEG_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately 
+// 1 = start the AHB write request immediately as soon as the device 
+// has put one write data in hte AHB gizmos queue. 0 = start the AHB 
+// write request only when all the  write data has transferred from 
+// the device to the AHB gizmos queue.
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_RANGE                     18:18
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Maximum 
+// allowed AHB burst size. 
+// 00 = single transfer. 
+// 01 = burst-of-4. 
+// 10 = burst-of-8 
+// 11 = burst-of-16.
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SHIFT                     _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_RANGE                     17:16
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                  _MK_ENUM_CONST(1)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                  _MK_ENUM_CONST(2)
+#define AHB_GIZMO_AHB_MEM_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                 _MK_ENUM_CONST(3)
+
+// AHB slave gizmo (memory controller)-Dont split AHB write transaction 1 = dont 
+// split AHB write transaction  ever. 0 (and enable_split=1) = allow AHB write 
+// transaction to be split.
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SHIFT                     _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_RANGE                     7:7
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_DONT_SPLIT_AHB_WR_DISABLE                   _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Accept AHB write request 
+// always. 1= always accept AHB write request without checking 
+// whether there is room in the queue to store the write data.Bypass 
+// Memory Controller AHB slave gizmo write queue. 0 = accept AHB 
+// write request only when theres  enough room in the queue to store 
+// all the write data. Memory controller AHB  slave gizmos write queue 
+// is used in this case.
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                  _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_RANGE                  6:6
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration. 1 = allow AHB master re-arbitration as 
+// soon as the device returns one read data into the gizmos queue. 0 = allow AHB master 
+// re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SHIFT                  _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_RANGE                  2:2
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENB_FAST_REARBITRATE_ENABLE                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Foce all AHB transaction to single 
+// data request transaction 1 = force to single data transaction always.  
+// 0 = dont force to single data transaction.
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SHIFT                   _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_RANGE                   1:1
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo (memory controller ) - Enable splitting AHB transaction. 
+// 1 = enable 0 = disable.
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_RANGE                  0:0
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_MEM_0_ENABLE_SPLIT_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_APB_DMA_0  
+#define AHB_GIZMO_APB_DMA_0                     _MK_ADDR_CONST(0x10)
+#define AHB_GIZMO_APB_DMA_0_SECURE                      0x0
+#define AHB_GIZMO_APB_DMA_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_APB_DMA_0_RESET_VAL                   _MK_MASK_CONST(0xa0000)
+#define AHB_GIZMO_APB_DMA_0_RESET_MASK                  _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_APB_DMA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_READ_MASK                   _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_APB_DMA_0_WRITE_MASK                  _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate 
+// the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SHIFT                   _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_FIELD                   (_MK_MASK_CONST(0xff) << AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_RANGE                   31:24
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_WOFFSET                 0x0
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_REQ_NEG_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all 
+// requested read data to be in the AHB gizmos queue before returning 
+// the data back to the IP. 0 = transfer each read data from the AHB 
+// to the IP  immediately.
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SHIFT                       _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_APB_DMA_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_RANGE                       19:19
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_WOFFSET                     0x0
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_NO_WAIT                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_RD_DATA_WAIT                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  
+// 1 = start the AHB write request immediately as soon as the device has 
+// put one write data in the AHB gizmos queue. 0 = start the AHB write 
+// request only when all the  write data has transferred from the device 
+// to the AHB gizmos queue.
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_APB_DMA_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_RANGE                     18:18
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SHIFT                     _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_RANGE                     17:16
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_WOFFSET                   0x0
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                  _MK_ENUM_CONST(1)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                  _MK_ENUM_CONST(2)
+#define AHB_GIZMO_APB_DMA_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                 _MK_ENUM_CONST(3)
+
+
+// Reserved address 20 [0x14] 
+
+// Register AHB_GIZMO_IDE_0  
+#define AHB_GIZMO_IDE_0                 _MK_ADDR_CONST(0x18)
+#define AHB_GIZMO_IDE_0_SECURE                  0x0
+#define AHB_GIZMO_IDE_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_IDE_0_RESET_VAL                       _MK_MASK_CONST(0x200bf)
+#define AHB_GIZMO_IDE_0_RESET_MASK                      _MK_MASK_CONST(0xff0f00ff)
+#define AHB_GIZMO_IDE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_READ_MASK                       _MK_MASK_CONST(0xff0f00ff)
+#define AHB_GIZMO_IDE_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f00ff)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk 
+// count between requests from  this AHB master.
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_IDE_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data 
+// to be in the AHB gizmos queue before returning the data back to the IP. 0 = transfer 
+// each read data from the AHB to the IP  immediately.
+#define AHB_GIZMO_IDE_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_IDE_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_IDE_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_IDE_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_IDE_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the 
+// AHB write request immediately as soon as the device has put one write data in the 
+// AHB gizmos queue. 0 = start the AHB write request only when all the  write data 
+// has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_IDE_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_IDE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction 
+// ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept 
+// AHB write request without checking whether there is room in the queue 
+// to store the write data. 0 = accept AHB write request only when theres  
+// enough room in the queue to store all the write data.
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo  Maximum allowed IP 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.
+// 11 = burst-of-16.
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_FIELD                  (_MK_MASK_CONST(0x3) << AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_RANGE                  5:4
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_WOFFSET                        0x0
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DEFAULT                        _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                       _MK_ENUM_CONST(1)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                       _MK_ENUM_CONST(2)
+#define AHB_GIZMO_IDE_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                      _MK_ENUM_CONST(3)
+
+// AHB slave gizmo  Start write request to device immediately.  1 = start write request on the device side as soon 
+// as the AHB master puts data into the gizmos queue. 0 = start the device write request only when the  AHB master 
+// has placed all write data into the gizmos queue.
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon 
+// as the device returns one read data into the gizmos queue.0 = allow AHB master re-arbitration 
+// only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always. 
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable, 0 = disable.
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_IDE_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_IDE_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_USB_0  
+#define AHB_GIZMO_USB_0                 _MK_ADDR_CONST(0x1c)
+#define AHB_GIZMO_USB_0_SECURE                  0x0
+#define AHB_GIZMO_USB_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_USB_0_RESET_VAL                       _MK_MASK_CONST(0x20083)
+#define AHB_GIZMO_USB_0_RESET_MASK                      _MK_MASK_CONST(0xff0f00cf)
+#define AHB_GIZMO_USB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_READ_MASK                       _MK_MASK_CONST(0xff0f00cf)
+#define AHB_GIZMO_USB_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f00cf)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_USB_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in 
+// the AHB gizmos queue before returning the data back to the IP. 0 = transfer each read data 
+// from the AHB to the IP  immediately.
+#define AHB_GIZMO_USB_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_USB_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_USB_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_USB_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_USB_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device has put one write data in the AHB gizmos 
+// queue. 0 = start the AHB write request only when all the  write data has transferred 
+// from the device to the AHB gizmos queue.
+#define AHB_GIZMO_USB_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_USB_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_USB_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8. 
+// 11 = burst-of-16.
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_USB_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction 
+// ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept 
+// AHB write request without checking whether there is room in the queue 
+// to store the write data. 0 = accept AHB write request only when theres  
+// enough room in the queue to store all the write data.
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo  Start write request to device immediately.  1 = start write request on 
+// the device side as soon as the AHB master puts data into the gizmos queue. 0 = start the 
+// device write request only when the  AHB master has placed all write data into the gizmos 
+// queue.
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_DISABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_IP_WR_REQ_IMMEDIATE_ENABLE                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon 
+// as the device returns one read data into the gizmos queue. 0 = allow AHB master 
+// re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always. 
+// 0 = dont force to single data transaction.
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_AHB_XBAR_BRIDGE_0  
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0                     _MK_ADDR_CONST(0x20)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_SECURE                      0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_WORD_COUNT                  0x1
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_RESET_VAL                   _MK_MASK_CONST(0x8d)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 
+// 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SHIFT                     _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_RANGE                     7:7
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_ENABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_DONT_SPLIT_AHB_WR_DISABLE                   _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write 
+// request without checking whether there is room in the queue to store the write 
+// data. 0 = accept AHB write request only when theres  enough room in the queue 
+// to store all the write data.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                  _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_RANGE                  6:6
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                      _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Maximum allowed IP burst 
+// size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_RANGE                      5:4
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Start write request to device immediately.  1 = start write request on the 
+// device side as soon as the AHB master puts data into the gizmos queue.  0 = start the device 
+// write request only when the  AHB master has placed all write data into the gizmos queue.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SHIFT                     _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_RANGE                     3:3
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_WOFFSET                   0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_IMMEDIATE_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as 
+// the device returns one read data into the gizmos queue.  0 = allow AHB master re-arbitration 
+// only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SHIFT                  _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_RANGE                  2:2
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENB_FAST_REARBITRATE_ENABLE                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request transaction.  
+// 1 = force to single data transaction always.  
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SHIFT                   _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_RANGE                   1:1
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_WOFFSET                 0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable 0 = disable
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_RANGE                  0:0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_WOFFSET                        0x0
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_AHB_XBAR_BRIDGE_0_ENABLE_SPLIT_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_CPU_AHB_BRIDGE_0  
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0                      _MK_ADDR_CONST(0x24)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_SECURE                       0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RESET_VAL                    _MK_MASK_CONST(0x60000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RESET_MASK                   _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_READ_MASK                    _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_WRITE_MASK                   _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in the 
+// AHB gizmos queue before returning the data back to the IP.  0 = transfer each read data from 
+// the AHB to the IP  immediately.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SHIFT                        _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_RANGE                        19:19
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_WOFFSET                      0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_NO_WAIT                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_RD_DATA_WAIT                 _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB write 
+// request immediately as soon as the device  has put one write data in the AHB gizmos queue.  
+// 0 = start the AHB write request only when all the  write data has transferred from the 
+// device to the AHB gizmos queue.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed AHB 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_CPU_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_COP_AHB_BRIDGE_0  
+#define AHB_GIZMO_COP_AHB_BRIDGE_0                      _MK_ADDR_CONST(0x28)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_SECURE                       0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RESET_VAL                    _MK_MASK_CONST(0x60000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RESET_MASK                   _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_READ_MASK                    _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_WRITE_MASK                   _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in the 
+// AHB gizmos queue before returning the data back to the IP.  0 = transfer each read data from 
+// the AHB to the IP  immediately.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SHIFT                        _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_RANGE                        19:19
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_WOFFSET                      0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_NO_WAIT                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_RD_DATA_WAIT                 _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB write 
+// request immediately as soon as the device  has put one write data in the AHB gizmos queue.  
+// 0 = start the AHB write request only when all the  write data has transferred from the 
+// device to the AHB gizmos queue.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed AHB 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_COP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_XBAR_APB_CTLR_0  
+#define AHB_GIZMO_XBAR_APB_CTLR_0                       _MK_ADDR_CONST(0x2c)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_SECURE                        0x0
+#define AHB_GIZMO_XBAR_APB_CTLR_0_WORD_COUNT                    0x1
+#define AHB_GIZMO_XBAR_APB_CTLR_0_RESET_VAL                     _MK_MASK_CONST(0x8)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_RESET_MASK                    _MK_MASK_CONST(0x38)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_READ_MASK                     _MK_MASK_CONST(0x38)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_WRITE_MASK                    _MK_MASK_CONST(0x38)
+// AHB slave gizmo - Maximum allowed IP 
+// burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(4)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_RANGE                        5:4
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_MAX_IP_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+// AHB slave gizmo - Start write request to device immediately.  1 = start write request on 
+// the device side as soon as the AHB master puts data into the gizmos queue.  0 = start 
+// the device write request only when the  AHB master has placed all write data into the 
+// gizmos queue.
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SHIFT                       _MK_SHIFT_CONST(3)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_RANGE                       3:3
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_WOFFSET                     0x0
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_DISABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XBAR_APB_CTLR_0_IMMEDIATE_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_VCP_AHB_BRIDGE_0  
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0                      _MK_ADDR_CONST(0x30)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_SECURE                       0x0
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RESET_VAL                    _MK_MASK_CONST(0x60000)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RESET_MASK                   _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_READ_MASK                    _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_WRITE_MASK                   _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read data from the AHB to the IP  immediately.
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_SHIFT                        _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_RANGE                        19:19
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_WOFFSET                      0x0
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_NO_WAIT                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_RD_DATA_WAIT                 _MK_ENUM_CONST(1)
+
+//AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device  has put one write data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_VCP_AHB_BRIDGE_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Register AHB_GIZMO_NAND_0  
+#define AHB_GIZMO_NAND_0                        _MK_ADDR_CONST(0x3c)
+#define AHB_GIZMO_NAND_0_SECURE                         0x0
+#define AHB_GIZMO_NAND_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_NAND_0_RESET_VAL                      _MK_MASK_CONST(0xa0000)
+#define AHB_GIZMO_NAND_0_RESET_MASK                     _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_NAND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_READ_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_NAND_0_WRITE_MASK                     _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_NAND_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_NAND_0_RD_DATA_SHIFT                  _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_NAND_0_RD_DATA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_NAND_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_NAND_0_RD_DATA_RANGE                  19:19
+#define AHB_GIZMO_NAND_0_RD_DATA_WOFFSET                        0x0
+#define AHB_GIZMO_NAND_0_RD_DATA_DEFAULT                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_RD_DATA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_RD_DATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_RD_DATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_RD_DATA_NO_WAIT                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_RD_DATA_WAIT                   _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_NAND_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_NAND_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_NAND_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Reserved address 64 [0x40] 
+
+// Register AHB_GIZMO_SDMMC4_0  
+#define AHB_GIZMO_SDMMC4_0                      _MK_ADDR_CONST(0x44)
+#define AHB_GIZMO_SDMMC4_0_SECURE                       0x0
+#define AHB_GIZMO_SDMMC4_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_SDMMC4_0_RESET_VAL                    _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_SDMMC4_0_RESET_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_READ_MASK                    _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC4_0_WRITE_MASK                   _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_SDMMC4_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_SHIFT                      _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_RANGE                      7:7
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_DONT_SPLIT_AHB_WR_DISABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                   _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_RANGE                   6:6
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                       _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_SHIFT                   _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_RANGE                   2:2
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_ENB_FAST_REARBITRATE_ENABLE                  _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_RANGE                    1:1
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_SHIFT                   _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_RANGE                   0:0
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC4_0_ENABLE_SPLIT_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_XIO_0  
+#define AHB_GIZMO_XIO_0                 _MK_ADDR_CONST(0x48)
+#define AHB_GIZMO_XIO_0_SECURE                  0x0
+#define AHB_GIZMO_XIO_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_XIO_0_RESET_VAL                       _MK_MASK_CONST(0x40000)
+#define AHB_GIZMO_XIO_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_XIO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_XIO_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SHIFT                       _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_FIELD                       (_MK_MASK_CONST(0xff) << AHB_GIZMO_XIO_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_RANGE                       31:24
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_WOFFSET                     0x0
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_REQ_NEG_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_XIO_0_RD_DATA_SHIFT                   _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_XIO_0_RD_DATA_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_XIO_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_XIO_0_RD_DATA_RANGE                   19:19
+#define AHB_GIZMO_XIO_0_RD_DATA_WOFFSET                 0x0
+#define AHB_GIZMO_XIO_0_RD_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_RD_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_RD_DATA_NO_WAIT                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_RD_DATA_WAIT                    _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SHIFT                 _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_XIO_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_RANGE                 18:18
+#define AHB_GIZMO_XIO_0_IMMEDIATE_WOFFSET                       0x0
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_DISABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_IMMEDIATE_ENABLE                        _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum allowed 
+// AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_FIELD                 (_MK_MASK_CONST(0x3) << AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_RANGE                 17:16
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_WOFFSET                       0x0
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                      _MK_ENUM_CONST(1)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                      _MK_ENUM_CONST(2)
+#define AHB_GIZMO_XIO_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                     _MK_ENUM_CONST(3)
+
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Register AHB_GIZMO_BSEV_0  
+#define AHB_GIZMO_BSEV_0                        _MK_ADDR_CONST(0x60)
+#define AHB_GIZMO_BSEV_0_SECURE                         0x0
+#define AHB_GIZMO_BSEV_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_BSEV_0_RESET_VAL                      _MK_MASK_CONST(0x20000)
+#define AHB_GIZMO_BSEV_0_RESET_MASK                     _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_BSEV_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_READ_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define AHB_GIZMO_BSEV_0_WRITE_MASK                     _MK_MASK_CONST(0xff0f0000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Pack all AHB read data.  1 = wait for all requested read data to be 
+// in the AHB gizmos queue before returning the data back to the IP.  0 = transfer each read 
+// data from the AHB to the IP  immediately.
+#define AHB_GIZMO_BSEV_0_RD_DATA_SHIFT                  _MK_SHIFT_CONST(19)
+#define AHB_GIZMO_BSEV_0_RD_DATA_FIELD                  (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEV_0_RD_DATA_SHIFT)
+#define AHB_GIZMO_BSEV_0_RD_DATA_RANGE                  19:19
+#define AHB_GIZMO_BSEV_0_RD_DATA_WOFFSET                        0x0
+#define AHB_GIZMO_BSEV_0_RD_DATA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEV_0_RD_DATA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_NO_WAIT                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_RD_DATA_WAIT                   _MK_ENUM_CONST(1)
+
+// AHB master gizmo (AHB-DMA) - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device  has put one write data in the AHB 
+// gizmos queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue. !!THIS SHOULD NEVER BE SET TO 
+// ENABLE!! (BSEV requires this bit to be 0) 
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEV_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.
+// 11 = burst-of-16.
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_BSEV_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register AHB_GIZMO_BSEA_0  
+#define AHB_GIZMO_BSEA_0                        _MK_ADDR_CONST(0x70)
+#define AHB_GIZMO_BSEA_0_SECURE                         0x0
+#define AHB_GIZMO_BSEA_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_BSEA_0_RESET_VAL                      _MK_MASK_CONST(0x20000)
+#define AHB_GIZMO_BSEA_0_RESET_MASK                     _MK_MASK_CONST(0xff070000)
+#define AHB_GIZMO_BSEA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_READ_MASK                      _MK_MASK_CONST(0xff070000)
+#define AHB_GIZMO_BSEA_0_WRITE_MASK                     _MK_MASK_CONST(0xff070000)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count 
+// between requests from  this AHB master.
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// AHB master gizmo - Start AHB write request immediately.  1 = start the AHB 
+// write request immediately as soon as the device puts data in the AHB gizmos 
+// queue.  0 = start the AHB write request only when all the  write data has 
+// transferred from the device to the AHB gizmos queue.  !!THIS SHOULD NEVER BE 
+// SET TO ENABLE!! (BSEV requires this bit to be 0) 
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_BSEA_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEA_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+// AHB master gizmo - Maximum 
+// allowed AHB burst size.  
+// 00 = single transfer.  
+// 01 = burst-of-4.  
+// 10 = burst-of-8.  
+// 11 = burst-of-16.
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_BSEA_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+
+// Register AHB_GIZMO_NOR_0  
+#define AHB_GIZMO_NOR_0                 _MK_ADDR_CONST(0x74)
+#define AHB_GIZMO_NOR_0_SECURE                  0x0
+#define AHB_GIZMO_NOR_0_WORD_COUNT                      0x1
+#define AHB_GIZMO_NOR_0_RESET_VAL                       _MK_MASK_CONST(0x85)
+#define AHB_GIZMO_NOR_0_RESET_MASK                      _MK_MASK_CONST(0xc7)
+#define AHB_GIZMO_NOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_READ_MASK                       _MK_MASK_CONST(0xc7)
+#define AHB_GIZMO_NOR_0_WRITE_MASK                      _MK_MASK_CONST(0xc7)
+// AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB 
+// write transaction ever. 0 (and enable_split=1) = allow AHB write  
+// transaction to be split.
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SHIFT                 _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_FIELD                 (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_RANGE                 7:7
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_WOFFSET                       0x0
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_ENABLE                        _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_DONT_SPLIT_AHB_WR_DISABLE                       _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Accept AHB write request always.  
+// 1 = always accept AHB write request without checking whether 
+// there is room in the queue to store the write data. 0 = accept 
+// AHB write request only when theres  enough room in the queue 
+// to store all the write data.
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                      _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_RANGE                      6:6
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                  _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master 
+// re-arbitration as soon as the device returns one read data into the gizmos 
+// queue.  0 = allow AHB master re-arbitration only when the  device returns all 
+// read data into the gizmos queue.
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SHIFT                      _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_RANGE                      2:2
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ENB_FAST_REARBITRATE_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Force all AHB transaction to single data request 
+// transaction.  1 = force to single data transaction always.  
+// 0 = dont force to single data  transaction.
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_FIELD                       (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_RANGE                       1:1
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_WOFFSET                     0x0
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                 _MK_ENUM_CONST(1)
+
+// AHB slave gizmo - Enable splitting AHB transactions.  1 = enable 0 = disable
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_NOR_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_RANGE                      0:0
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_WOFFSET                    0x0
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_NOR_0_ENABLE_SPLIT_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_USB2_0  
+#define AHB_GIZMO_USB2_0                        _MK_ADDR_CONST(0x78)
+#define AHB_GIZMO_USB2_0_SECURE                         0x0
+#define AHB_GIZMO_USB2_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_USB2_0_RESET_VAL                      _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_USB2_0_RESET_MASK                     _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_USB2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_READ_MASK                      _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_USB2_0_WRITE_MASK                     _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_USB2_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_USB2_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_USB2_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_USB2_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_USB2_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_SHIFT                        _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_RANGE                        7:7
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_WOFFSET                      0x0
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_ENABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_DONT_SPLIT_AHB_WR_DISABLE                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                     _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_RANGE                     6:6
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                   0x0
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                 _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_RANGE                     2:2
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_WOFFSET                   0x0
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_ENB_FAST_REARBITRATE_ENABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_SHIFT                      _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_RANGE                      1:1
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_WOFFSET                    0x0
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                        _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB2_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_RANGE                     0:0
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_WOFFSET                   0x0
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB2_0_ENABLE_SPLIT_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_USB3_0  
+#define AHB_GIZMO_USB3_0                        _MK_ADDR_CONST(0x7c)
+#define AHB_GIZMO_USB3_0_SECURE                         0x0
+#define AHB_GIZMO_USB3_0_WORD_COUNT                     0x1
+#define AHB_GIZMO_USB3_0_RESET_VAL                      _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_USB3_0_RESET_MASK                     _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_USB3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_READ_MASK                      _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_USB3_0_WRITE_MASK                     _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_SHIFT                      _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_FIELD                      (_MK_MASK_CONST(0xff) << AHB_GIZMO_USB3_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_RANGE                      31:24
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_WOFFSET                    0x0
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_REQ_NEG_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_USB3_0_IMMEDIATE_SHIFT                        _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_RANGE                        18:18
+#define AHB_GIZMO_USB3_0_IMMEDIATE_WOFFSET                      0x0
+#define AHB_GIZMO_USB3_0_IMMEDIATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_DISABLE                      _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_IMMEDIATE_ENABLE                       _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_FIELD                        (_MK_MASK_CONST(0x3) << AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_RANGE                        17:16
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_WOFFSET                      0x0
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DEFAULT                      _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                     _MK_ENUM_CONST(1)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                     _MK_ENUM_CONST(2)
+#define AHB_GIZMO_USB3_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                    _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_SHIFT                        _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_FIELD                        (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_RANGE                        7:7
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_WOFFSET                      0x0
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_ENABLE                       _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_DONT_SPLIT_AHB_WR_DISABLE                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                     _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_RANGE                     6:6
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                   0x0
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                 _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_RANGE                     2:2
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_WOFFSET                   0x0
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_ENB_FAST_REARBITRATE_ENABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_SHIFT                      _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_RANGE                      1:1
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_WOFFSET                    0x0
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                        _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_FIELD                     (_MK_MASK_CONST(0x1) << AHB_GIZMO_USB3_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_RANGE                     0:0
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_WOFFSET                   0x0
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_DEFAULT                   _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_DISABLE                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_USB3_0_ENABLE_SPLIT_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_SDMMC1_0  
+#define AHB_GIZMO_SDMMC1_0                      _MK_ADDR_CONST(0x80)
+#define AHB_GIZMO_SDMMC1_0_SECURE                       0x0
+#define AHB_GIZMO_SDMMC1_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_SDMMC1_0_RESET_VAL                    _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_SDMMC1_0_RESET_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_READ_MASK                    _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC1_0_WRITE_MASK                   _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_SDMMC1_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_SHIFT                      _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_RANGE                      7:7
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_DONT_SPLIT_AHB_WR_DISABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                   _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_RANGE                   6:6
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                       _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_SHIFT                   _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_RANGE                   2:2
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_ENB_FAST_REARBITRATE_ENABLE                  _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_RANGE                    1:1
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_SHIFT                   _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_RANGE                   0:0
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC1_0_ENABLE_SPLIT_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_SDMMC2_0  
+#define AHB_GIZMO_SDMMC2_0                      _MK_ADDR_CONST(0x84)
+#define AHB_GIZMO_SDMMC2_0_SECURE                       0x0
+#define AHB_GIZMO_SDMMC2_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_SDMMC2_0_RESET_VAL                    _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_SDMMC2_0_RESET_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_READ_MASK                    _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC2_0_WRITE_MASK                   _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_SDMMC2_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_SHIFT                      _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_RANGE                      7:7
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_DONT_SPLIT_AHB_WR_DISABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                   _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_RANGE                   6:6
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                       _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_SHIFT                   _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_RANGE                   2:2
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_ENB_FAST_REARBITRATE_ENABLE                  _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_RANGE                    1:1
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_SHIFT                   _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_RANGE                   0:0
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC2_0_ENABLE_SPLIT_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Register AHB_GIZMO_SDMMC3_0  
+#define AHB_GIZMO_SDMMC3_0                      _MK_ADDR_CONST(0x88)
+#define AHB_GIZMO_SDMMC3_0_SECURE                       0x0
+#define AHB_GIZMO_SDMMC3_0_WORD_COUNT                   0x1
+#define AHB_GIZMO_SDMMC3_0_RESET_VAL                    _MK_MASK_CONST(0x20087)
+#define AHB_GIZMO_SDMMC3_0_RESET_MASK                   _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_READ_MASK                    _MK_MASK_CONST(0xff0700c7)
+#define AHB_GIZMO_SDMMC3_0_WRITE_MASK                   _MK_MASK_CONST(0xff0700c7)
+// AHB master request negate count. This is an 8-bit  counter use to indicate the minimum number of clk count between requests from  this AHB master.
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_SHIFT                    _MK_SHIFT_CONST(24)
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_FIELD                    (_MK_MASK_CONST(0xff) << AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_RANGE                    31:24
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_REQ_NEG_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//AHB master gizmo - Start AHB write request immediately.  1 = start the AHB write request immediately as soon as the device puts data in the AHB gizmos queue.  0 = start the AHB write request only when all the  write data has transferred from the device to the AHB gizmos queue.
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_SHIFT                      _MK_SHIFT_CONST(18)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_IMMEDIATE_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_RANGE                      18:18
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_DISABLE                    _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_IMMEDIATE_ENABLE                     _MK_ENUM_CONST(1)
+
+//AHB master gizmo - Maximum allowed AHB burst size.  00 = single transfer.  01 = burst-of-4.  10 = burst-of-8.  11 = burst-of-16.
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_FIELD                      (_MK_MASK_CONST(0x3) << AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_RANGE                      17:16
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DMA_BURST_1WORDS                   _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DMA_BURST_4WORDS                   _MK_ENUM_CONST(1)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DMA_BURST_8WORDS                   _MK_ENUM_CONST(2)
+#define AHB_GIZMO_SDMMC3_0_MAX_AHB_BURSTSIZE_DMA_BURST_16WORDS                  _MK_ENUM_CONST(3)
+
+//AHB slave gizmo - Dont split AHB write transaction.  1 = dont split AHB write transaction ever. 0 (and enable_split=1) = allow AHB write  transaction to be split.
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_SHIFT                      _MK_SHIFT_CONST(7)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_FIELD                      (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_RANGE                      7:7
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_WOFFSET                    0x0
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_DEFAULT                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_DONT_SPLIT_AHB_WR_DISABLE                    _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Accept AHB write request always.  1 = always accept AHB write request without checking whether there is room in the queue to store the write data. 0 = accept AHB write request only when theres  enough room in the queue to store all the write data.
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_SHIFT                   _MK_SHIFT_CONST(6)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_RANGE                   6:6
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_CHECK                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_ACCEPT_AHB_WR_ALWAYS_ACCEPT_ON_NOCHECK                       _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable fast re-arbitration.  1 = allow AHB master re-arbitration as soon as the device returns one read data into the gizmos queue. 0 = allow AHB master re-arbitration only when the  device returns all read data into the gizmos queue.
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_SHIFT                   _MK_SHIFT_CONST(2)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_RANGE                   2:2
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_ENB_FAST_REARBITRATE_ENABLE                  _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Force all AHB transaction to single data request transaction.  1 = force to single data transaction always. 0 = dont force to single data transaction.
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_RANGE                    1:1
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_WOFFSET                  0x0
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_NOT_SINGLE_DATA                  _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_FORCE_TO_AHB_SINGLE_SINGLE_DATA                      _MK_ENUM_CONST(1)
+
+//AHB slave gizmo - Enable splitting AHB transactions.  1 = enable  0 = disable
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_SHIFT                   _MK_SHIFT_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_FIELD                   (_MK_MASK_CONST(0x1) << AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_SHIFT)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_RANGE                   0:0
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_WOFFSET                 0x0
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_DISABLE                 _MK_ENUM_CONST(0)
+#define AHB_GIZMO_SDMMC3_0_ENABLE_SPLIT_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Register AHB_AHB_MEM_PREFETCH_CFG_X_0  
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0                    _MK_ADDR_CONST(0xd8)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_SECURE                     0x0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_WORD_COUNT                         0x1
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_RESET_MASK                         _MK_MASK_CONST(0xf)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_READ_MASK                  _MK_MASK_CONST(0xf)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_WRITE_MASK                         _MK_MASK_CONST(0xf)
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_SHIFT                   _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_FIELD                   (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_RANGE                   0:0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_WOFFSET                 0x0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_SHIFT                   _MK_SHIFT_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_FIELD                   (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_RANGE                   1:1
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_WOFFSET                 0x0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_SHIFT                   _MK_SHIFT_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_FIELD                   (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_RANGE                   2:2
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_WOFFSET                 0x0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_SHIFT                   _MK_SHIFT_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_FIELD                   (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_RANGE                   3:3
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_WOFFSET                 0x0
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG_X_0_DISABLE_CHECK_SIZE_MASTER4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_XBAR_CTRL_0  
+#define AHB_ARBITRATION_XBAR_CTRL_0                     _MK_ADDR_CONST(0xdc)
+#define AHB_ARBITRATION_XBAR_CTRL_0_SECURE                      0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_WORD_COUNT                  0x1
+#define AHB_ARBITRATION_XBAR_CTRL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_RESET_MASK                  _MK_MASK_CONST(0x10003)
+#define AHB_ARBITRATION_XBAR_CTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_READ_MASK                   _MK_MASK_CONST(0x10003)
+#define AHB_ARBITRATION_XBAR_CTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x10003)
+// SW should set this bit when memory has been initialized
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_RANGE                 16:16
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_WOFFSET                       0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_NOT_DONE                      _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DONE                  _MK_ENUM_CONST(1)
+
+// By default CPU accesses to IRAMs will be held if  there are any pending requests from the AHB to the 
+// IRAMs. This is done to  avoid data coherency issues. If SW handles coherency then this can be turned  
+// off to improve performance.SW writes to modify
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SHIFT                      _MK_SHIFT_CONST(1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_RANGE                      1:1
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_WOFFSET                    0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DISABLE                    _MK_ENUM_CONST(1)
+
+// SW writes to modify
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SHIFT)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_RANGE                      0:0
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_WOFFSET                    0x0
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_ENABLE                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DISABLE                    _MK_ENUM_CONST(1)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG3_0  
+#define AHB_AHB_MEM_PREFETCH_CFG3_0                     _MK_ADDR_CONST(0xe0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SECURE                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_RESET_VAL                   _MK_MASK_CONST(0x14800800)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_WRITE_MASK                  _MK_MASK_CONST(0xffe0ffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// AHBDMA master
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x5)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDMMC1                   _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SNOR                     _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDMMC4                   _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_USB3                     _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_USB2                     _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDMMC2                   _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_SDMMC3                   _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// not used for AP-20 and beyond (last used in AP15)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 2048 cycles
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG3_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG4_0  
+#define AHB_AHB_MEM_PREFETCH_CFG4_0                     _MK_ADDR_CONST(0xe4)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SECURE                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_RESET_VAL                   _MK_MASK_CONST(0x14800800)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_WRITE_MASK                  _MK_MASK_CONST(0xffe0ffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// AHBDMA master
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x5)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDMMC1                   _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SNOR                     _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDMMC4                   _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_USB3                     _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_USB2                     _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDMMC2                   _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_SDMMC3                   _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// not used for AP-20 and beyond (last used in AP15)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 2048 cycles
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG4_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AVP_PPCS_RD_COH_STATUS_0  
+#define AHB_AVP_PPCS_RD_COH_STATUS_0                    _MK_ADDR_CONST(0xe8)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_SECURE                     0x0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WORD_COUNT                         0x1
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x10001)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SHIFT                      _MK_SHIFT_CONST(16)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_FIELD                      (_MK_MASK_CONST(0x1) << AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SHIFT)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_RANGE                      16:16
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_WOFFSET                    0x0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_RDS_OUTSTANDING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_FIELD                      (_MK_MASK_CONST(0x1) << AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SHIFT)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_RANGE                      0:0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_WOFFSET                    0x0
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_AVP_PPCS_RD_COH_STATUS_0_WRS_OUTSTANDING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG1_0  
+#define AHB_AHB_MEM_PREFETCH_CFG1_0                     _MK_ADDR_CONST(0xec)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SECURE                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_RESET_VAL                   _MK_MASK_CONST(0x14800800)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_WRITE_MASK                  _MK_MASK_CONST(0xffe0ffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// AHBDMA master
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x5)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDMMC1                   _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SNOR                     _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDMMC4                   _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_USB3                     _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_USB2                     _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDMMC2                   _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_SDMMC3                   _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// not used for AP-20 and beyond (last used in AP15)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 2048 cycles
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG1_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHB_MEM_PREFETCH_CFG2_0  
+#define AHB_AHB_MEM_PREFETCH_CFG2_0                     _MK_ADDR_CONST(0xf0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SECURE                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_WORD_COUNT                  0x1
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_RESET_VAL                   _MK_MASK_CONST(0x18800800)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_WRITE_MASK                  _MK_MASK_CONST(0xffe0ffff)
+// 1=enable 0=disable
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_RANGE                        31:31
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_WOFFSET                      0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// USB
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SHIFT                    _MK_SHIFT_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_RANGE                    30:26
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_DEFAULT                  _MK_MASK_CONST(0x6)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_CPU                      _MK_ENUM_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_COP                      _MK_ENUM_CONST(1)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_VCP                      _MK_ENUM_CONST(2)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_03                        _MK_ENUM_CONST(3)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_IDE                      _MK_ENUM_CONST(4)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_AHBDMA                   _MK_ENUM_CONST(5)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_USB                      _MK_ENUM_CONST(6)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_APBDMA                   _MK_ENUM_CONST(7)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_XIO                      _MK_ENUM_CONST(8)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDIO1                    _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDMMC1                   _MK_ENUM_CONST(9)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_NAND_FLASH                       _MK_ENUM_CONST(10)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SNOR                     _MK_ENUM_CONST(11)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_HSMMC                    _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_BSEV                     _MK_ENUM_CONST(13)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_0E                        _MK_ENUM_CONST(14)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_0F                        _MK_ENUM_CONST(15)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDMMC4                   _MK_ENUM_CONST(12)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_BSEA                     _MK_ENUM_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_USB3                     _MK_ENUM_CONST(17)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_USB2                     _MK_ENUM_CONST(18)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDIO2                    _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDMMC2                   _MK_ENUM_CONST(19)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_SDMMC3                   _MK_ENUM_CONST(20)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_15                        _MK_ENUM_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_16                        _MK_ENUM_CONST(22)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_17                        _MK_ENUM_CONST(23)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_18                        _MK_ENUM_CONST(24)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_19                        _MK_ENUM_CONST(25)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1A                        _MK_ENUM_CONST(26)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1B                        _MK_ENUM_CONST(27)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1C                        _MK_ENUM_CONST(28)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1D                        _MK_ENUM_CONST(29)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1E                        _MK_ENUM_CONST(30)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_AHB_MST_ID_UNUSED_1F                        _MK_ENUM_CONST(31)
+
+// 2^(n+4) byte boundary. any value >16 will use n=16
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SHIFT                    _MK_SHIFT_CONST(21)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_FIELD                    (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_RANGE                    25:21
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_DEFAULT                  _MK_MASK_CONST(0x4)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_ADDR_BNDRY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// not used for AP-20 and beyond (last used in AP15)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_FIELD                 (_MK_MASK_CONST(0x1f) << AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_RANGE                 20:16
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_WOFFSET                       0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_SPEC_THROTTLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_FIELD                    (_MK_MASK_CONST(0xffff) << AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SHIFT)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_RANGE                    15:0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_WOFFSET                  0x0
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_DEFAULT                  _MK_MASK_CONST(0x800)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_AHB_MEM_PREFETCH_CFG2_0_INACTIVITY_TIMEOUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register AHB_AHBSLVMEM_STATUS_0  
+#define AHB_AHBSLVMEM_STATUS_0                  _MK_ADDR_CONST(0xf4)
+#define AHB_AHBSLVMEM_STATUS_0_SECURE                   0x0
+#define AHB_AHBSLVMEM_STATUS_0_WORD_COUNT                       0x1
+#define AHB_AHBSLVMEM_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x3)
+#define AHB_AHBSLVMEM_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SHIFT                       _MK_SHIFT_CONST(1)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_FIELD                       (_MK_MASK_CONST(0x1) << AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SHIFT)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_RANGE                       1:1
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_WOFFSET                     0x0
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_PPCS_RDS_OUTSTANDING_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SHIFT                       _MK_SHIFT_CONST(0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_FIELD                       (_MK_MASK_CONST(0x1) << AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SHIFT)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_RANGE                       0:0
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_WOFFSET                     0x0
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_AHBSLVMEM_STATUS_0_GIZMO_IP_RDQUE_EMPTY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0  
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0                  _MK_ADDR_CONST(0xf8)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_SECURE                   0x0
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_WORD_COUNT                       0x1
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_RESET_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_READ_MASK                        _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_WRITE_MASK                       _MK_MASK_CONST(0x7fffffff)
+// 0 = there is no write data in the write queue from  that AHB master.
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SHIFT                      _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_FIELD                      (_MK_MASK_CONST(0x7fffffff) << AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SHIFT)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_RANGE                      30:0
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_WOFFSET                    0x0
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0_AHB_MASTER_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_CPU_ABORT_INFO_0  
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0                        _MK_ADDR_CONST(0xfc)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SECURE                         0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Abort occurred due to an iRAMa protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SHIFT                    _MK_SHIFT_CONST(15)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_RANGE                    15:15
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMA_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMb protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SHIFT                    _MK_SHIFT_CONST(14)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_RANGE                    14:14
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMB_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMc protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_RANGE                    13:13
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMC_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMd protection  violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SHIFT                    _MK_SHIFT_CONST(12)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_RANGE                    12:12
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_IRAMD_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an access to invalid iRAM  address space
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SHIFT                 _MK_SHIFT_CONST(11)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_FIELD                 (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_RANGE                 11:11
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_WOFFSET                       0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_ABT_DIS                       _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_INV_IRAM_ABT_EN                        _MK_ENUM_CONST(1)
+
+// Abort occurred due to a PPSB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SHIFT                     _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_RANGE                     10:10
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PPSB_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Abort occurred due to an APB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SHIFT                      _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_RANGE                      9:9
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_WOFFSET                    0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_APB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to an AHB protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SHIFT                      _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_RANGE                      8:8
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_WOFFSET                    0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_AHB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to a Cache protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SHIFT                    _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_RANGE                    7:7
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_CACHE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for any protection violation
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SHIFT                       _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_RANGE                       6:6
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_WOFFSET                     0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_PROTECTION_ABT_EN                      _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Misalignment (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SHIFT                    _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_RANGE                    5:5
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_ALIGN_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Bad Size (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_RANGE                  4:4
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_WOFFSET                        0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_ABT_DIS                        _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_BADSIZE_ABT_EN                 _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Write
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SHIFT                    _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_RANGE                    3:3
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_WOFFSET                  0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_WRITE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Data access
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_RANGE                     2:2
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_DATA_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Aborted transaction Request Size 00=byte,  01=hword, 10=word
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_RANGE                     1:0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_BYTE_ABT                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_HWORD_ABT                 _MK_ENUM_CONST(1)
+#define AHB_ARBITRATION_CPU_ABORT_INFO_0_SIZE_WORD_ABT                  _MK_ENUM_CONST(2)
+
+
+// Register AHB_ARBITRATION_CPU_ABORT_ADDR_0  
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0                        _MK_ADDR_CONST(0x100)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_SECURE                         0x0
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Instruction Address which caused the abort
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_FIELD                     (_MK_MASK_CONST(0xffffffff) << AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SHIFT)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_RANGE                     31:0
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_WOFFSET                   0x0
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_CPU_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register AHB_ARBITRATION_COP_ABORT_INFO_0  
+#define AHB_ARBITRATION_COP_ABORT_INFO_0                        _MK_ADDR_CONST(0x104)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SECURE                         0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_RESET_MASK                     _MK_MASK_CONST(0xe7ff)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_READ_MASK                      _MK_MASK_CONST(0xe7ff)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Abort occurred due to an iRAMa protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SHIFT                    _MK_SHIFT_CONST(15)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_RANGE                    15:15
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMA_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMb protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SHIFT                    _MK_SHIFT_CONST(14)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_RANGE                    14:14
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMB_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to an iRAMc protection  violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SHIFT                    _MK_SHIFT_CONST(13)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_RANGE                    13:13
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_IRAMC_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Abort occurred due to a PPSB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SHIFT                     _MK_SHIFT_CONST(10)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_RANGE                     10:10
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PPSB_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Abort occurred due to an APB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SHIFT                      _MK_SHIFT_CONST(9)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_RANGE                      9:9
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_WOFFSET                    0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_APB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to an AHB protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SHIFT                      _MK_SHIFT_CONST(8)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_FIELD                      (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_RANGE                      8:8
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_WOFFSET                    0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_ABT_DIS                    _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_AHB_ABT_EN                     _MK_ENUM_CONST(1)
+
+// Abort occurred due to a Cache protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SHIFT                    _MK_SHIFT_CONST(7)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_RANGE                    7:7
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_CACHE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for any protection violation
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SHIFT                       _MK_SHIFT_CONST(6)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_FIELD                       (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_RANGE                       6:6
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_WOFFSET                     0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_ABT_DIS                     _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_PROTECTION_ABT_EN                      _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Misalignment (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SHIFT                    _MK_SHIFT_CONST(5)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_RANGE                    5:5
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_ALIGN_ABT_EN                   _MK_ENUM_CONST(1)
+
+// TRUE for abort caused by Bad Size (i.e. word  access at odd byte address)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SHIFT                  _MK_SHIFT_CONST(4)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_FIELD                  (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_RANGE                  4:4
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_WOFFSET                        0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_ABT_DIS                        _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_BADSIZE_ABT_EN                 _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Write
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SHIFT                    _MK_SHIFT_CONST(3)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_RANGE                    3:3
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_WOFFSET                  0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_ABT_DIS                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_WRITE_ABT_EN                   _MK_ENUM_CONST(1)
+
+// Aborted transaction was a Data access
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SHIFT                     _MK_SHIFT_CONST(2)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_FIELD                     (_MK_MASK_CONST(0x1) << AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_RANGE                     2:2
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_ABT_DIS                   _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_DATA_ABT_EN                    _MK_ENUM_CONST(1)
+
+// Aborted transaction Request Size 00=byte,  01=hword, 10=word
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_FIELD                     (_MK_MASK_CONST(0x3) << AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_RANGE                     1:0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_BYTE_ABT                  _MK_ENUM_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_HWORD_ABT                 _MK_ENUM_CONST(1)
+#define AHB_ARBITRATION_COP_ABORT_INFO_0_SIZE_WORD_ABT                  _MK_ENUM_CONST(2)
+
+
+// Register AHB_ARBITRATION_COP_ABORT_ADDR_0  
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0                        _MK_ADDR_CONST(0x108)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_SECURE                         0x0
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_WORD_COUNT                     0x1
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Instruction Address which caused the abort
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SHIFT                     _MK_SHIFT_CONST(0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_FIELD                     (_MK_MASK_CONST(0xffffffff) << AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SHIFT)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_RANGE                     31:0
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_WOFFSET                   0x0
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_ARBITRATION_COP_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 268 [0x10c] 
+
+// Reserved address 272 [0x110] 
+
+// Reserved address 276 [0x114] 
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Reserved address 288 [0x120] 
+
+// Reserved address 292 [0x124] 
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Reserved address 320 [0x140] 
+
+// Reserved address 324 [0x144] 
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Reserved address 336 [0x150] 
+
+// Reserved address 340 [0x154] 
+
+// Reserved address 344 [0x158] 
+
+// Reserved address 348 [0x15c] 
+
+// Reserved address 352 [0x160] 
+
+// Reserved address 356 [0x164] 
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Reserved address 384 [0x180] 
+
+// Reserved address 388 [0x184] 
+
+// Reserved address 392 [0x188] 
+
+// Reserved address 396 [0x18c] 
+
+// Reserved address 400 [0x190] 
+
+// Reserved address 404 [0x194] 
+
+// Reserved address 408 [0x198] 
+
+// Reserved address 412 [0x19c] 
+
+// Reserved address 416 [0x1a0] 
+
+// Reserved address 420 [0x1a4] 
+
+// Reserved address 424 [0x1a8] 
+
+// Reserved address 428 [0x1ac] 
+
+// Reserved address 432 [0x1b0] 
+
+// Reserved address 436 [0x1b4] 
+
+// Reserved address 440 [0x1b8] 
+
+// Reserved address 444 [0x1bc] 
+
+// Reserved address 448 [0x1c0] 
+
+// Reserved address 452 [0x1c4] 
+
+// Reserved address 456 [0x1c8] 
+
+// Reserved address 460 [0x1cc] 
+
+// Reserved address 464 [0x1d0] 
+
+// Reserved address 468 [0x1d4] 
+
+// Reserved address 472 [0x1d8] 
+
+// Reserved address 476 [0x1dc] 
+
+// Reserved address 480 [0x1e0] 
+
+// Reserved address 484 [0x1e4] 
+
+// Reserved address 488 [0x1e8] 
+
+// Reserved address 492 [0x1ec] 
+
+// Reserved address 496 [0x1f0] 
+
+// Reserved address 500 [0x1f4] 
+
+// Reserved address 504 [0x1f8] 
+
+// Reserved address 508 [0x1fc] 
+
+// Reserved address 512 [0x200] 
+
+// Reserved address 516 [0x204] 
+
+// Reserved address 520 [0x208] 
+
+// Reserved address 524 [0x20c] 
+
+// Reserved address 528 [0x210] 
+
+// Reserved address 532 [0x214] 
+
+// Reserved address 536 [0x218] 
+
+// Reserved address 540 [0x21c] 
+
+// Reserved address 544 [0x220] 
+
+// Reserved address 548 [0x224] 
+
+// Reserved address 552 [0x228] 
+
+// Reserved address 556 [0x22c] 
+
+// Reserved address 560 [0x230] 
+
+// Reserved address 564 [0x234] 
+
+// Reserved address 568 [0x238] 
+
+// Register AHB_AVPC_MCCIF_FIFOCTRL_0  
+#define AHB_AVPC_MCCIF_FIFOCTRL_0                       _MK_ADDR_CONST(0x23c)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_SECURE                        0x0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_WORD_COUNT                    0x1
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_SHIFT                  _MK_SHIFT_CONST(0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_FIELD                  (_MK_MASK_CONST(0x1) << AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_SHIFT)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_RANGE                  0:0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_WOFFSET                        0x0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_INIT_ENUM                      DISABLE
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRCL_MCLE2X_ENABLE                 _MK_ENUM_CONST(1)
+
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_SHIFT                  _MK_SHIFT_CONST(1)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_FIELD                  (_MK_MASK_CONST(0x1) << AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_SHIFT)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_RANGE                  1:1
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_WOFFSET                        0x0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_INIT_ENUM                      DISABLE
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDMC_RDFAST_ENABLE                 _MK_ENUM_CONST(1)
+
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_SHIFT                  _MK_SHIFT_CONST(2)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_FIELD                  (_MK_MASK_CONST(0x1) << AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_SHIFT)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_RANGE                  2:2
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_WOFFSET                        0x0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_INIT_ENUM                      DISABLE
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_WRMC_CLLE2X_ENABLE                 _MK_ENUM_CONST(1)
+
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_SHIFT                  _MK_SHIFT_CONST(3)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_FIELD                  (_MK_MASK_CONST(0x1) << AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_SHIFT)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_RANGE                  3:3
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_WOFFSET                        0x0
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_INIT_ENUM                      DISABLE
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_DISABLE                        _MK_ENUM_CONST(0)
+#define AHB_AVPC_MCCIF_FIFOCTRL_0_AVPC_MCCIF_RDCL_RDFAST_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Reserved address 573 [0x23d] 
+
+// Reserved address 574 [0x23e] 
+
+// Reserved address 575 [0x23f] 
+
+// Register AHB_TIMEOUT_WCOAL_AVPC_0  
+#define AHB_TIMEOUT_WCOAL_AVPC_0                        _MK_ADDR_CONST(0x240)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_SECURE                         0x0
+#define AHB_TIMEOUT_WCOAL_AVPC_0_WORD_COUNT                     0x1
+#define AHB_TIMEOUT_WCOAL_AVPC_0_RESET_VAL                      _MK_MASK_CONST(0x32)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_SHIFT)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_RANGE                    7:0
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_WOFFSET                  0x0
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x32)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define AHB_TIMEOUT_WCOAL_AVPC_0_AVPCARM7W_WCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 577 [0x241] 
+
+// Reserved address 578 [0x242] 
+
+// Reserved address 579 [0x243] 
+
+// Reserved address 580 [0x244] 
+
+// Reserved address 581 [0x245] 
+
+// Reserved address 582 [0x246] 
+
+// Reserved address 583 [0x247] 
+
+// Reserved address 584 [0x248] 
+
+// Reserved address 585 [0x249] 
+
+// Reserved address 586 [0x24a] 
+
+// Reserved address 587 [0x24b] 
+
+// Reserved address 588 [0x24c] 
+
+// Reserved address 589 [0x24d] 
+
+// Reserved address 590 [0x24e] 
+
+// Reserved address 591 [0x24f] 
+
+// Reserved address 592 [0x250] 
+
+// Reserved address 593 [0x251] 
+
+// Reserved address 594 [0x252] 
+
+// Reserved address 595 [0x253] 
+
+// Reserved address 596 [0x254] 
+
+// Reserved address 597 [0x255] 
+
+// Reserved address 598 [0x256] 
+
+// Reserved address 599 [0x257] 
+
+// Reserved address 600 [0x258] 
+
+// Reserved address 601 [0x259] 
+
+// Reserved address 602 [0x25a] 
+
+// Reserved address 603 [0x25b] 
+
+// Reserved address 604 [0x25c] 
+
+// Reserved address 605 [0x25d] 
+
+// Reserved address 606 [0x25e] 
+
+// Reserved address 607 [0x25f] 
+
+// Reserved address 608 [0x260] 
+
+// Reserved address 609 [0x261] 
+
+// Reserved address 610 [0x262] 
+
+// Reserved address 611 [0x263] 
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAHB_ARBC_REGS(_op_) \
+_op_(AHB_ARBITRATION_DISABLE_0) \
+_op_(AHB_ARBITRATION_PRIORITY_CTRL_0) \
+_op_(AHB_ARBITRATION_USR_PROTECT_0) \
+_op_(AHB_GIZMO_AHB_MEM_0) \
+_op_(AHB_GIZMO_APB_DMA_0) \
+_op_(AHB_GIZMO_IDE_0) \
+_op_(AHB_GIZMO_USB_0) \
+_op_(AHB_GIZMO_AHB_XBAR_BRIDGE_0) \
+_op_(AHB_GIZMO_CPU_AHB_BRIDGE_0) \
+_op_(AHB_GIZMO_COP_AHB_BRIDGE_0) \
+_op_(AHB_GIZMO_XBAR_APB_CTLR_0) \
+_op_(AHB_GIZMO_VCP_AHB_BRIDGE_0) \
+_op_(AHB_GIZMO_NAND_0) \
+_op_(AHB_GIZMO_SDMMC4_0) \
+_op_(AHB_GIZMO_XIO_0) \
+_op_(AHB_GIZMO_BSEV_0) \
+_op_(AHB_GIZMO_BSEA_0) \
+_op_(AHB_GIZMO_NOR_0) \
+_op_(AHB_GIZMO_USB2_0) \
+_op_(AHB_GIZMO_USB3_0) \
+_op_(AHB_GIZMO_SDMMC1_0) \
+_op_(AHB_GIZMO_SDMMC2_0) \
+_op_(AHB_GIZMO_SDMMC3_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG_X_0) \
+_op_(AHB_ARBITRATION_XBAR_CTRL_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG3_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG4_0) \
+_op_(AHB_AVP_PPCS_RD_COH_STATUS_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG1_0) \
+_op_(AHB_AHB_MEM_PREFETCH_CFG2_0) \
+_op_(AHB_AHBSLVMEM_STATUS_0) \
+_op_(AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID_0) \
+_op_(AHB_ARBITRATION_CPU_ABORT_INFO_0) \
+_op_(AHB_ARBITRATION_CPU_ABORT_ADDR_0) \
+_op_(AHB_ARBITRATION_COP_ABORT_INFO_0) \
+_op_(AHB_ARBITRATION_COP_ABORT_ADDR_0) \
+_op_(AHB_AVPC_MCCIF_FIFOCTRL_0) \
+_op_(AHB_TIMEOUT_WCOAL_AVPC_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_AHB        0x00000000
+
+//
+// ARAHB_ARBC REGISTER BANKS
+//
+
+#define AHB0_FIRST_REG 0x0000 // AHB_ARBITRATION_DISABLE_0
+#define AHB0_LAST_REG 0x0010 // AHB_GIZMO_APB_DMA_0
+#define AHB1_FIRST_REG 0x0018 // AHB_GIZMO_IDE_0
+#define AHB1_LAST_REG 0x0030 // AHB_GIZMO_VCP_AHB_BRIDGE_0
+#define AHB2_FIRST_REG 0x003c // AHB_GIZMO_NAND_0
+#define AHB2_LAST_REG 0x003c // AHB_GIZMO_NAND_0
+#define AHB3_FIRST_REG 0x0044 // AHB_GIZMO_SDMMC4_0
+#define AHB3_LAST_REG 0x0048 // AHB_GIZMO_XIO_0
+#define AHB4_FIRST_REG 0x0060 // AHB_GIZMO_BSEV_0
+#define AHB4_LAST_REG 0x0060 // AHB_GIZMO_BSEV_0
+#define AHB5_FIRST_REG 0x0070 // AHB_GIZMO_BSEA_0
+#define AHB5_LAST_REG 0x0088 // AHB_GIZMO_SDMMC3_0
+#define AHB6_FIRST_REG 0x00d8 // AHB_AHB_MEM_PREFETCH_CFG_X_0
+#define AHB6_LAST_REG 0x0108 // AHB_ARBITRATION_COP_ABORT_ADDR_0
+#define AHB7_FIRST_REG 0x023c // AHB_AVPC_MCCIF_FIFOCTRL_0
+#define AHB7_LAST_REG 0x023c // AHB_AVPC_MCCIF_FIFOCTRL_0
+#define AHB8_FIRST_REG 0x0240 // AHB_TIMEOUT_WCOAL_AVPC_0
+#define AHB8_LAST_REG 0x0240 // AHB_TIMEOUT_WCOAL_AVPC_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAHB_ARBC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arapb_misc.h b/arch/arm/mach-tegra/nv/include/ap20/arapb_misc.h
new file mode 100644
index 000000000000..e1e57e96bfc6
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arapb_misc.h
@@ -0,0 +1,15362 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPB_MISC_H_INC_
+#define ___ARAPB_MISC_H_INC_
+
+// Reserved address 0 [0x0] 
+
+// Reserved address 4 [0x4] 
+
+// Register APB_MISC_PP_STRAPPING_OPT_A_0  
+#define APB_MISC_PP_STRAPPING_OPT_A_0                   _MK_ADDR_CONST(0x8)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SECURE                    0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_WORD_COUNT                        0x1
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RESET_MASK                        _MK_MASK_CONST(0x101)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_READ_MASK                         _MK_MASK_CONST(0x3fc001f1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_WRITE_MASK                        _MK_MASK_CONST(0x3fc001f1)
+// read at power-on reset time from gmi_ad[15:12] strap pads.
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_RANGE                 29:26
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// read at power-on reset time from gmi_hior strap pad
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT                  _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_RANGE                  25:25
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_WOFFSET                        0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_DISABLED                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_USB_RECOVERY_MODE_ENABLED                        _MK_ENUM_CONST(1)
+
+// read at power-on reset time from gmi_hiow strap pad
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SHIFT                   _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_RANGE                   24:24
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_IROM                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_BOOT_SRC_NOR_BOOT_NOR                     _MK_ENUM_CONST(1)
+
+// read at power-on reset time from {gmi_clk,gmi_adv_n} strap pads 00=Serial_JTAG, 01=CPU_only, 10=COP_only, 11=Serial_JTAG(same as 00 case)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT                    _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_RANGE                    23:22
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_WOFFSET                  0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_CPU                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_COP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_ARM_JTAG_SERIAL_ALT                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RANGE                   8:8
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_INIT_ENUM                       RSVD1
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RSVD1                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_MIO_WIDTH_RSVD2                   _MK_ENUM_CONST(1)
+
+// read at power-on reset time from gmi_ad[7:4] strap pads
+// In emulation (HIDREV_MAJORREV==0), this field indicates the RAM type connected.
+// For   QT (HIDREV_MINORREV==0): 0=SIM, 1=DDR, 2=DDR2, 3=LPDDR2
+// For FPGA (HIDREV_MINORREV==1): 0=SIM, 1=DDR, 2=DDR2, 3=LPDDR2
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_FIELD                    (_MK_MASK_CONST(0xf) << APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_RANGE                    7:4
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_WOFFSET                  0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_RAM_CODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SHIFT)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RANGE                   0:0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_WOFFSET                 0x0
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_INIT_ENUM                       RSVD1
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RSVD1                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_STRAPPING_OPT_A_0_NOR_WIDTH_RSVD2                   _MK_ENUM_CONST(1)
+
+
+// Reserved address 12 [0xc] 
+
+// Reserved address 16 [0x10] 
+
+// Register APB_MISC_PP_TRISTATE_REG_A_0  
+#define APB_MISC_PP_TRISTATE_REG_A_0                    _MK_ADDR_CONST(0x14)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SECURE                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_VAL                  _MK_MASK_CONST(0xc01bfff0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_RANGE                        31:31
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_OWC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_RANGE                      30:30
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_SDIO1_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_RANGE                        29:29
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_RANGE                        28:28
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GMA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCF_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_RANGE                       26:26
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCE_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT                 _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_RANGE                 25:25
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_WOFFSET                       0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_RM_TRISTATE                      _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_RANGE                        24:24
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PTA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_RANGE                        23:23
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_PMC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_RANGE                       22:22
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_RANGE                       21:21
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_KBCB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_RANGE                       20:20
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRRX_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_RANGE                       19:19
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_IRTX_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_RANGE                       18:18
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_I2CP_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_RANGE                        17:17
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPV_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_RANGE                        16:16
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_GPU_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_RANGE                        15:15
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTE_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_RANGE                        14:14
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_RANGE                        13:13
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_RANGE                        12:12
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_RANGE                        11:11
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DTA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP4_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_RANGE                       9:9
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP3_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_RANGE                       8:8
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_RANGE                       7:7
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_DAP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_RANGE                       6:6
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CSUS_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_RANGE                      5:5
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV2_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_RANGE                      4:4
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_CDEV1_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_RANGE                        3:3
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_A_0_Z_ATA_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_B_0  
+#define APB_MISC_PP_TRISTATE_REG_B_0                    _MK_ADDR_CONST(0x18)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SECURE                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_VAL                  _MK_MASK_CONST(0xffefee)
+#define APB_MISC_PP_TRISTATE_REG_B_0_RESET_MASK                         _MK_MASK_CONST(0xe6ffffef)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_READ_MASK                  _MK_MASK_CONST(0xe6ffffef)
+#define APB_MISC_PP_TRISTATE_REG_B_0_WRITE_MASK                         _MK_MASK_CONST(0xe6ffffef)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_RANGE                        31:31
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_DDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_RANGE                        30:30
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_RANGE                        29:29
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GMB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_RANGE                       26:26
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_KBCC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_RANGE                        25:25
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_ATE_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_RANGE                        23:23
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_RANGE                        22:22
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UCA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_RANGE                        21:21
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_RANGE                        20:20
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_RANGE                        19:19
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_RANGE                        18:18
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_UAA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_RANGE                       17:17
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIH_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_RANGE                       16:16
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIG_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_RANGE                       15:15
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIF_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIE_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_RANGE                       13:13
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPID_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_RANGE                       12:12
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIB_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPIA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_RANGE                       9:9
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDO_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_RANGE                       8:8
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SPDI_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_RANGE                       7:7
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXK_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_RANGE                       6:6
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXD_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_RANGE                       5:5
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXC_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_RANGE                       3:3
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SLXA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDD_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_SDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_INIT_ENUM                    NORMAL
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_B_0_Z_GME_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_C_0  
+#define APB_MISC_PP_TRISTATE_REG_C_0                    _MK_ADDR_CONST(0x1c)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SECURE                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_VAL                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT                       _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_RANGE                       31:31
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LCSN_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_RANGE                        30:30
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LDC_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_RANGE                       29:29
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSCK_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_RANGE                       28:28
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_RANGE                       27:27
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LSC0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_RANGE                        26:26
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVS_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_RANGE                        25:25
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM1_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_RANGE                        24:24
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LM0_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_RANGE                      23:23
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_WOFFSET                    0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_INIT_ENUM                  TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_HDINT_TRISTATE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_RANGE                       22:22
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_RANGE                       21:21
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LVP0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_RANGE                       20:20
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_RANGE                       19:19
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_RANGE                       18:18
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LHP0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_RANGE                       17:17
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD17_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_RANGE                       16:16
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD16_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_RANGE                       15:15
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD15_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD14_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_RANGE                       13:13
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD13_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_RANGE                       12:12
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD12_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD11_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD10_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_RANGE                        9:9
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD9_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_RANGE                        8:8
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD8_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_RANGE                        7:7
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD7_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_RANGE                        6:6
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD6_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_RANGE                        5:5
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD5_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_RANGE                        4:4
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD4_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_RANGE                        3:3
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD3_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_RANGE                        2:2
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD2_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_RANGE                        1:1
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD1_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_RANGE                        0:0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_C_0_Z_LD0_TRISTATE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_TRISTATE_REG_D_0  
+#define APB_MISC_PP_TRISTATE_REG_D_0                    _MK_ADDR_CONST(0x20)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SECURE                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_VAL                  _MK_MASK_CONST(0xf1ff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_RESET_MASK                         _MK_MASK_CONST(0xfdff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_READ_MASK                  _MK_MASK_CONST(0xfdff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_WRITE_MASK                         _MK_MASK_CONST(0xfdff)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_RANGE                        15:15
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_SDB_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_RANGE                       14:14
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_CRTP_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_RANGE                        13:13
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_UDA_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_RANGE                        12:12
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_DTF_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_RANGE                       11:11
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_GPU7_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_RANGE                       10:10
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_INIT_ENUM                   NORMAL
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_KBCD_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_RANGE                        8:8
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPP_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_RANGE                        7:7
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LHS_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_RANGE                        6:6
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_WOFFSET                      0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_INIT_ENUM                    TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LDI_TRISTATE                     _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_RANGE                       5:5
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW2_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_RANGE                       4:4
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW1_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_RANGE                       3:3
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LPW0_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_RANGE                       2:2
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDI_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_RANGE                       1:1
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSDA_TRISTATE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SHIFT)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_RANGE                       0:0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_WOFFSET                     0x0
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_INIT_ENUM                   TRISTATE
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_TRISTATE_REG_D_0_Z_LSPI_TRISTATE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_CONFIG_CTL_0  
+#define APB_MISC_PP_CONFIG_CTL_0                        _MK_ADDR_CONST(0x24)
+#define APB_MISC_PP_CONFIG_CTL_0_SECURE                         0x0
+#define APB_MISC_PP_CONFIG_CTL_0_WORD_COUNT                     0x1
+#define APB_MISC_PP_CONFIG_CTL_0_RESET_VAL                      _MK_MASK_CONST(0x40)
+#define APB_MISC_PP_CONFIG_CTL_0_RESET_MASK                     _MK_MASK_CONST(0xc0)
+#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_READ_MASK                      _MK_MASK_CONST(0xc0)
+#define APB_MISC_PP_CONFIG_CTL_0_WRITE_MASK                     _MK_MASK_CONST(0xc0)
+//  0 = Disable ; 1 = Enable RTCK Daisychaining
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_TBE_SHIFT)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_RANGE                      7:7
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_WOFFSET                    0x0
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_INIT_ENUM                  DISABLE
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_CONFIG_CTL_0_TBE_ENABLE                     _MK_ENUM_CONST(1)
+
+//  0 = Disable Debug ; 1 = Enable JTAG DBGEN
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_CONFIG_CTL_0_JTAG_SHIFT)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_RANGE                     6:6
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_WOFFSET                   0x0
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_INIT_ENUM                 ENABLE
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_CONFIG_CTL_0_JTAG_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_MISC_USB_OTG_0  
+#define APB_MISC_PP_MISC_USB_OTG_0                      _MK_ADDR_CONST(0x28)
+#define APB_MISC_PP_MISC_USB_OTG_0_SECURE                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_MISC_USB_OTG_0_RESET_VAL                    _MK_MASK_CONST(0x1000)
+#define APB_MISC_PP_MISC_USB_OTG_0_RESET_MASK                   _MK_MASK_CONST(0xc3ffffff)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_READ_MASK                    _MK_MASK_CONST(0xc3ffffff)
+#define APB_MISC_PP_MISC_USB_OTG_0_WRITE_MASK                   _MK_MASK_CONST(0xc07fff29)
+// Wake on Disconnect Enable (device mode)
+// When enabled (1), USB PHY will wakeup
+// from suspend on a disconnect event.
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_RANGE                      31:31
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_DISCON_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Wake on Connect Enable (device mode)
+// When enabled (1), USB PHY will wakeup
+// from suspend on a connect event.
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_RANGE                        30:30
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WAKE_ON_CNNT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// B_SESS_END status from USB PHY.
+// This field is the same as the field
+// B_SESS_END_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT                        _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_RANGE                        25:25
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_B_SESS_END_STS2_SET                  _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status from USB PHY.
+// This field is the same as the field
+// A_VBUS_VLD_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_RANGE                        24:24
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_VBUS_VLD_STS2_SET                  _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status from USB PHY.
+// This field is the same as the field
+// A_SESS_VLD_STS in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_RANGE                        23:23
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_A_SESS_VLD_STS2_SET                  _MK_ENUM_CONST(1)
+
+// Software_B_SESS_END status.
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This field is the same as the field
+// B_SESS_END_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_RANGE                  22:22
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled B_SESS_END.
+// Software sets this bit to drive the
+// value in  SW_B_SESS_END to the USB
+// controller
+// This field is the same as the field
+// B_SESS_END_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT                       _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_RANGE                       21:21
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_B_SESS_END_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Software_A_VBUS_VLD status.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This field is the same as the field
+// A_VBUS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_RANGE                  20:20
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in SW_A_VBUS_VLD to the USB
+// controller.
+// This field is the same as the field
+// A_VBUS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_RANGE                       19:19
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_VBUS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Software_A_SESS_VLD status.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This field is the same as the field
+// A_SESS_VLD_SW_VALUE in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_RANGE                  18:18
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_SET                    _MK_ENUM_CONST(1)
+
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in SW_A_SESS_VLD to the USB
+// controller.
+// This field is the same as the field
+// A_SESS_VLD_SW_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_RANGE                       17:17
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_A_SESS_VLD_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Suspend Set
+// Software must write a 1 to this bit to put the USB PHY in
+// suspend mode. Software should do this only after making sure that
+// the USB is indeed in suspend mode. Setting this bit will stop the
+// PHY clock. Software should write a 0 to clear it.
+// NOTE: It is required that software generate a positive pulse on this
+// bit to guarantee proper operation.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_RANGE                       16:16
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_SET_SET                 _MK_ENUM_CONST(1)
+
+// VBUS Change Interrupt Enable
+// If set, an interrupt will be generated whenever
+// A_SESS_VLD changes value. Software can read the
+// value of A_SESS_VLD from A_SESS_VLD_STS2 bit.
+// This field is the same as the field
+// A_SESS_VLD_INT_EN in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_RANGE                        15:15
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_INT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Software controlled OTG_ID.
+// If SW_OTG_ID_EN = 1, then software needs to monitor
+// actual OTG_ID bit used  as a GPIO and based on the value of OTG_ID,
+// it can set this bit.
+// This field is the same as the field
+// ID_SW_VALUE in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_RANGE                      14:14
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_SET                        _MK_ENUM_CONST(1)
+
+// Reserved
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_RANGE                 13:13
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSVD13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// ID pullup enable.
+// This field controls the internal pull-up to
+// OTG_ID pin. Software should set this to
+// 1 if using internal OTG_ID. If software
+// is using a GPIO for OTG_ID, then it
+// can write this to 0.
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_RANGE                  12:12
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_WOFFSET                        0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_ID_PU_ENABLE                 _MK_ENUM_CONST(1)
+
+//Suspend Clear
+// Software must write a 1 to this bit to bring the PHY
+// out of suspend mode. This is used when the software stops the PHY
+// clock during suspend and then wants to initiate a resume. Software
+// should also write 0 to clear it.
+// NOTE: It is required that software generate a  positive pulse on this
+// bit to guarantee proper operation.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_RANGE                       11:11
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_WOFFSET                     0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSP_CLR_SET                 _MK_ENUM_CONST(1)
+
+// Wake/resume on VBUS change change detect
+// If enabled, the USB PHY will wake up whenever a
+// change in A_SESS_VLD is detected.
+// This should be set only when USB PHY is already
+// suspended.
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_RANGE                   10:10
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_VBUS_CHG_ENABLE                  _MK_ENUM_CONST(1)
+
+// Resume/Clock valid interrupt enable
+// If this bit is enabled, interrupt is generated
+// whenever PHY clock becomes valid.
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_RANGE                 9:9
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_RSM_IE_ENABLE                        _MK_ENUM_CONST(1)
+
+// Wake on resume enable
+// If this bit is enabled, USB PHY will wakeup from
+// suspend whenever resume/reset signaling is
+// detected on USB.
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_RANGE                      8:8
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_WK_RSM_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// PHY clock valid status
+// This bit is set whenever PHY clock becomes valid.
+// It is cleared whenever PHY clock stops.
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_RANGE                        7:7
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_PCLKVLD_SET                  _MK_ENUM_CONST(1)
+
+// VBUS change detect
+// This bit is set whenever a change in A_SESS_VLD
+// is detected.
+// Software can read the status of A_SESS_VLD from 
+// A_SESS_VLD_STS2 bit.
+// This field is the same as the field
+// A_SESS_VLD_CHG_DET in register USB_PHY_VBUS_SENSORS.
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT                   _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_RANGE                   6:6
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_VBUS_CHG_DET_SET                     _MK_ENUM_CONST(1)
+
+// Loopback enable
+// Not for normal software use
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_RANGE                        5:5
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_LPBK_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Real OTG_ID status from the USB PHY.
+// This field is the same as the field
+// ID_STS in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_RANGE                 4:4
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_WOFFSET                       0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_OTG_ID_SET                   _MK_ENUM_CONST(1)
+
+// Enable Software Controlled OTG_ID
+// If using a GPIO for OTG_ID signal, then
+// software can set this to 1 and write
+// the value from the GPIO to the
+// SW_OTG_ID bit in this register.
+// This field is the same as the field
+// ID_SW_EN in register USB_PHY_VBUS_WAKEUP_ID.
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_RANGE                   3:3
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_WOFFSET                 0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SW_OTG_ID_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// USB PHY suspend status
+// This bit is set to 1 whenver USB is suspended and the PHY clock isnt  available.
+// NOTE: Software should not access any
+// registers in USB controller when this
+// bit is set.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_RANGE                      2:2
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUSPENDED_SET                        _MK_ENUM_CONST(1)
+
+// Static General purpose input coming from ID pin
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_RANGE                      1:1
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_WOFFSET                    0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_StaticGpi_SET                        _MK_ENUM_CONST(1)
+
+// Polarity of the suspend signal going to USB PHY
+// Software should not change this.
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SHIFT)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_RANGE                        0:0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_WOFFSET                      0x0
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_LOW                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_MISC_USB_OTG_0_SUS_POL_ACTIVE_HIGH                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 96 [0x60] 
+
+// Register APB_MISC_PP_USB_PHY_PARAM_0  
+#define APB_MISC_PP_USB_PHY_PARAM_0                     _MK_ADDR_CONST(0x64)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SECURE                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_RESET_MASK                  _MK_MASK_CONST(0x18)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_READ_MASK                   _MK_MASK_CONST(0x18)
+#define APB_MISC_PP_USB_PHY_PARAM_0_WRITE_MASK                  _MK_MASK_CONST(0x18)
+// Vbus_sense control
+// Controls which VBUS sensor input is driven to the controller.
+// 00: Use VBUS_WAKEUP.
+// 01: Use (A_SESS_VLD || B_SESS_VLD) output from the PHY if the PHY clock is available.
+// Otherwise, use VBUS_WAKEUP.
+// 10: Use (A_SESS_VLD || B_SESS_VLD) output from the PHY
+// 11: Use A_SESS_VLD output from the PHY
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SHIFT)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_RANGE                        4:3
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_VBUS_WAKEUP                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_AB_SESS_VLD                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_USB_PHY_PARAM_0_VS_CTL_A_SESS_VLD                   _MK_ENUM_CONST(3)
+
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register APB_MISC_PP_USB_PHY_VBUS_SENSORS_0  
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0                      _MK_ADDR_CONST(0x70)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SECURE                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_RESET_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_READ_MASK                    _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_WRITE_MASK                   _MK_MASK_CONST(0x39393939)
+// A_VBUS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(29)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_RANGE                   29:29
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This is only valid when A_VBUS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_RANGE                    28:28
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software enable.
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in A_VBUS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_RANGE                       27:27
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status.
+// This is set to 1 whenever A_VBUS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_RANGE                 26:26
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_VBUS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(25)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_RANGE                     25:25
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever A_VBUS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_RANGE                      24:24
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// A_SESS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_RANGE                   21:21
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This is only valid when A_SESS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_RANGE                    20:20
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software enable.
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in A_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_RANGE                       19:19
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status.
+// This is set to 1 whenever A_SESS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_RANGE                 18:18
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_SESS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_RANGE                     17:17
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// A_SESS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever A_SESS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_RANGE                      16:16
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// B_SESS_VLD debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_RANGE                   13:13
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_VLD status.
+// This is only valid when B_SESS_VLD_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_RANGE                    12:12
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software enable.
+// Enable Software Controlled B_SESS_VLD.
+// Software sets this bit to drive the
+// value in B_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_RANGE                       11:11
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD status.
+// This is set to 1 whenever B_SESS_VLD sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_RANGE                 10:10
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_VLD.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT                     _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_RANGE                     9:9
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_VLD interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_VLD_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_RANGE                      8:8
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// B_SESS_END debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_RANGE                   5:5
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// B_SESS_END software value
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This is only valid when B_SESS_END_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_RANGE                    4:4
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// B_SESS_END software enable.
+// Enable Software Controlled B_SESS_END
+// Software sets this bit to drive the
+// value in B_SESS_END_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_RANGE                       3:3
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_END status.
+// This is set to 1 whenever B_SESS_END sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_RANGE                 2:2
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_END change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_END.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_RANGE                     1:1
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_END interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_END_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_RANGE                      0:0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0  
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0                    _MK_ADDR_CONST(0x74)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SECURE                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WORD_COUNT                         0x1
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_VAL                  _MK_MASK_CONST(0x6000000)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_RESET_MASK                         _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_READ_MASK                  _MK_MASK_CONST(0x3f3f3f3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_WRITE_MASK                         _MK_MASK_CONST(0x3f393939)
+// HS Tx to Tx inter-packet delay counter.
+// Software should not change this.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_RANGE                    29:24
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT                  _MK_MASK_CONST(0x6)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_IP_DELAY_TX2TX_HS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// VDAT_DET debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_RANGE                   21:21
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_A                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_B                   _MK_ENUM_CONST(1)
+
+// VDAT_DET software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the VDAT_DET status.
+// This is only valid when VDAT_DET_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_RANGE                    20:20
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_UNSET                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SET                      _MK_ENUM_CONST(1)
+
+// VDAT_DET software enable.
+// Enable Software Controlled VDAT_DET.
+// Software sets this bit to drive the
+// value in VDAT_DET_SW_VALUE to the USB
+// controller
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_RANGE                       19:19
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VDAT_DET status.
+// This is set to 1 whenever VDAT_DET sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_RANGE                 18:18
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SET                   _MK_ENUM_CONST(1)
+
+// VDAT_DET change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VDAT_DET.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_RANGE                     17:17
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SET                       _MK_ENUM_CONST(1)
+
+// VDAT_DET interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever VDAT_DET_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_RANGE                      16:16
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_RANGE                        13:13
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_A                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_B                        _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the VBUS_WAKEUP status.
+// This is only valid when VBUS_WAKEUP_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_RANGE                 12:12
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SET                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP software enable.
+// Enable Software Controlled VBUS_WAKEUP.
+// Software sets this bit to drive the
+// value in VBUS_WAKEUP_SW_VALUE to the USB
+// controller.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_RANGE                    11:11
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP status.
+// This is set to 1 whenever VBUS_WAKEUP sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_RANGE                      10:10
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_WOFFSET                    0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_UNSET                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SET                        _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VBUS_WAKEUP.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_RANGE                  9:9
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SET                    _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever VBUS_WAKEUP_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_RANGE                   8:8
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// ID debounce A/B select.
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_RANGE                 5:5
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_A                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_B                 _MK_ENUM_CONST(1)
+
+// ID software value.
+// Software should write the appropriate
+// value (1/0) to set/unset the ID status.
+// This is only valid when ID_SW_EN is set.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_RANGE                  4:4
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_WOFFSET                        0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_UNSET                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SET                    _MK_ENUM_CONST(1)
+
+// ID software enable.
+// Enable Software Controlled ID.
+// Software sets this bit to drive the
+// value in ID_SW_VALUE to the USB
+// controller
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_RANGE                     3:3
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// ID status.
+// This is set to 1 whenever ID sensor
+// output is 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_RANGE                       2:2
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_WOFFSET                     0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_UNSET                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SET                 _MK_ENUM_CONST(1)
+
+// ID change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of ID.
+// software writes a 1 to clear it
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_RANGE                   1:1
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_WOFFSET                 0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_UNSET                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SET                     _MK_ENUM_CONST(1)
+
+// ID interrupt enable.
+// If this field is set to 1, an interrupt is
+// generated whenever ID_CHG_DET is set to 1.
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_RANGE                    0:0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_WOFFSET                  0x0
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0  
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0                      _MK_ADDR_CONST(0x78)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SECURE                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WORD_COUNT                   0x1
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// A_SESS_VLD alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_RANGE                 6:6
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_RANGE                 5:5
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SET                   _MK_ENUM_CONST(1)
+
+// ID alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_RANGE                     4:4
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_WOFFSET                   0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_END alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_RANGE                 3:3
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SET                   _MK_ENUM_CONST(1)
+
+// Static GPI alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_RANGE                 2:2
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SET                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SHIFT                 _MK_SHIFT_CONST(1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_RANGE                 1:1
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_WOFFSET                       0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SET                   _MK_ENUM_CONST(1)
+
+// Vbus wakeup alternate status
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_RANGE                        0:0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_WOFFSET                      0x0
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_UNSET                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SET                  _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_PP_MISC_SAVE_THE_DAY_0  
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0                 _MK_ADDR_CONST(0x7c)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SECURE                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WORD_COUNT                      0x1
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_RANGE                    31:24
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_A_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_RANGE                    23:16
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_B_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_RANGE                    15:8
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Reserved
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_FIELD                    (_MK_MASK_CONST(0xff) << APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SHIFT)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_RANGE                    7:0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_WOFFSET                  0x0
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_MISC_SAVE_THE_DAY_0_SAVE_THE_DAY_D_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_A_0  
+#define APB_MISC_PP_PIN_MUX_CTL_A_0                     _MK_ADDR_CONST(0x80)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_VAL                   _MK_MASK_CONST(0x2a22000)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RESET_MASK                  _MK_MASK_CONST(0xfff3f3ff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_READ_MASK                   _MK_MASK_CONST(0xfff3f3ff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_WRITE_MASK                  _MK_MASK_CONST(0xfff3f3ff)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_RANGE                     31:30
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_SDIO1                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_RSVD1                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_UARTE                     _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_SDIO1_SEL_UARTA                     _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_OWR                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCE_SEL_RSVD2                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_TRACE                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_KBCF_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RANGE                       25:24
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATA_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATC_SEL_SDIO4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_RANGE                       21:20
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATD_SEL_SDIO4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATB_SEL_SDIO4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RANGE                        15:14
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_WOFFSET                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_I2C                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD1                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD2                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_RM_SEL_RSVD3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_ATE_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_RANGE                       9:8
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_SPI1                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_RSVD                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_UARTD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UDA_SEL_ULPI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_RANGE                       7:6
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_IRDA                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SPDIF                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAD_SEL_SPI4                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_OWR                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_SPI2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAB_SEL_ULPI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_SPI3                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_MIPI_HS                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_UARTA                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_A_0_UAA_SEL_ULPI                        _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_B_0  
+#define APB_MISC_PP_PIN_MUX_CTL_B_0                     _MK_ADDR_CONST(0x84)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_VAL                   _MK_MASK_CONST(0xa140a)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_RESET_MASK                  _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_READ_MASK                   _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTE_SEL_SPI1                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_SDIO2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTD_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RANGE                       27:26
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTB_SEL_SPI1                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RANGE                       21:20
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_SDIO2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_DTA_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_UARTC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_PWM                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCB_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_UARTC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_UCA_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_PCIE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SPI4                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SDIO3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXK_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPI4                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SDIO3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXD_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPI4                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SDIO3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXC_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RANGE                       9:8
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_OWR                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RSVD1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RSVD2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_OWC_SEL_RSVD3                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_PCIE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SPI4                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SDIO3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_SLXA_SEL_SPI2                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RANGE                     5:4
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_HDMI                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD2                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD3                     _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_HDINT_SEL_RSVD4                     _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_UARTD                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SPI4                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMC_SEL_SFLASH                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_UARTE                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SPI3                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_B_0_GMA_SEL_SDIO4                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_C_0  
+#define APB_MISC_PP_PIN_MUX_CTL_C_0                     _MK_ADDR_CONST(0x88)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_VAL                   _MK_MASK_CONST(0xa8ca0000)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMD_SEL_SFLASH                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_IDE                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_NAND                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_GMB_SEL_GMI_INT                     _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_DAP4                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_GMI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP4_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_DAP3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP3_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_DAP2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_TWC                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP2_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_GMI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DAP1_SEL_SDIO2                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTA                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_UARTB                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_GMI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRRX_SEL_SPI4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTA                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_UARTB                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_GMI                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_IRTX_SEL_SPI4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_TRACE                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCC_SEL_EMC_TEST1_DLL                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCB_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_KBCA_SEL_EMC_TEST0_DLL                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_I2C                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_I2CP_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLC_OUT1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_PLLP_OUT3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CSUS_SEL_VI_SENSOR_CLK                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_RANGE                     5:4
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_OSC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_AHB_CLK                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_APB_CLK                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV2_SEL_PLLP_OUT4                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_RANGE                     3:2
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_OSC                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLA_OUT                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_PLLM_OUT1                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_CDEV1_SEL_AUDIO_SYNC                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_I2C2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RSVD1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RSVD2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_C_0_DDC_SEL_RSVD3                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_D_0  
+#define APB_MISC_PP_PIN_MUX_CTL_D_0                     _MK_ADDR_CONST(0x8c)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_VAL                   _MK_MASK_CONST(0xffc00022)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIA_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIB_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIC_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPID_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIE_SEL_GMI                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI1                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_SPI2                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIF_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIG_SEL_I2C                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI3                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_SPI2_ALT                   _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPIH_SEL_I2C                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_UARTA                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_PWM                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SDIO3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDD_SEL_SPI3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_PWM                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_TWC                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SDIO3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDC_SEL_SPI3                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_RANGE                       11:10
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_UARTA                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_PWM                 _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SDIO3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SDB_SEL_SPI2                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_RSVD                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_I2C                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDI_SEL_SDIO2                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SPDIF                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_RSVD                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_I2C                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_SPDO_SEL_SDIO2                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_PWM                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_UARTA                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPU_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_PCIE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GPV_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_RSVD1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_DAP5                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_D_0_GME_SEL_SDIO4                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_E_0  
+#define APB_MISC_PP_PIN_MUX_CTL_E_0                     _MK_ADDR_CONST(0x90)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVP0_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_RANGE                       29:28
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM1_SEL_CRT                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RANGE                       27:26
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_SPI3                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LM0_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_RANGE                       25:24
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LVS_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LHS_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC1_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RANGE                      19:18
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSC0_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSCK_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LDC_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LCSN_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSPI_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDA_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LSDI_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_RANGE                      5:4
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW2_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RANGE                      3:2
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RSVD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW1_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_SPI3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_E_0_LPW0_SEL_HDMI                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_F_0  
+#define APB_MISC_PP_PIN_MUX_CTL_F_0                     _MK_ADDR_CONST(0x94)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RANGE                      31:30
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD15_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD14_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD13_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RANGE                      25:24
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD12_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RANGE                      23:22
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD11_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD10_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD9_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD8_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD7_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RANGE                       13:12
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD6_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RANGE                       11:10
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD5_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RANGE                       9:8
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD4_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RANGE                       7:6
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD3_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RANGE                       5:4
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD2_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RANGE                       3:2
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD1_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RANGE                       1:0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_XIO                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_F_0_LD0_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_G_0  
+#define APB_MISC_PP_PIN_MUX_CTL_G_0                     _MK_ADDR_CONST(0x98)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_RESET_MASK                  _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_READ_MASK                   _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_WRITE_MASK                  _MK_MASK_CONST(0xfcffcfff)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RANGE                       31:30
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_I2C3                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_VI                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_DTF_SEL_RSVD4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RANGE                      29:28
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RTCK                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD1                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_GPU7_SEL_RSVD3                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_RANGE                      27:26
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_KBC                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_NAND                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_SDIO2                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_KBCD_SEL_MIO                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RANGE                       23:22
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_I2C2                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_HDMI                        _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_GMI                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PTA_SEL_RSVD3                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RANGE                      21:20
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_CRT                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RSVD2                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_CRTP_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_RANGE                       19:18
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_ON                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_PMC_SEL_PWR_INTR                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RANGE                       17:16
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LDI_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RANGE                       15:14
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_WOFFSET                     0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYA                    _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_DISPLAYB                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RSVD3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LPP_SEL_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RANGE                      11:10
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP0_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RANGE                      9:8
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LVP1_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RANGE                      7:6
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP2_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RANGE                      5:4
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RSVD3                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LHP1_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RANGE                      3:2
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD17_SEL_RSVD4                      _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RANGE                      1:0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYA                   _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_DISPLAYB                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_XIO                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_G_0_LD16_SEL_RSVD                       _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PIN_MUX_CTL_H_0  
+#define APB_MISC_PP_PIN_MUX_CTL_H_0                     _MK_ADDR_CONST(0x9c)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SECURE                      0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_WORD_COUNT                  0x1
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_RESET_MASK                  _MK_MASK_CONST(0x3fffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffff)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT                     _MK_SHIFT_CONST(21)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_RANGE                     21:21
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4M_SEL_DAP4_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_RANGE                     20:20
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3M_SEL_DAP3_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT                     _MK_SHIFT_CONST(19)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_RANGE                     19:19
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2M_SEL_DAP2_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_RANGE                     18:18
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_WOFFSET                   0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_SLAVE                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1M_SEL_DAP1_MASTER                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_RANGE                      17:16
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC3_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_RANGE                      15:14
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC2_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_RANGE                      13:12
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_WOFFSET                    0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAC1_SEL_DAP4                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RANGE                 11:9
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD                  _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP4_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RANGE                 8:6
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP3_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RANGE                 5:3
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP1                  _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP2_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SHIFT)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RANGE                 2:0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_WOFFSET                       0x0
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC1                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC2                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAC3                  _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD1                 _MK_ENUM_CONST(3)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_RSVD2                 _MK_ENUM_CONST(4)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP2                  _MK_ENUM_CONST(5)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP3                  _MK_ENUM_CONST(6)
+#define APB_MISC_PP_PIN_MUX_CTL_H_0_DAP1_CNTRL_MUX_SELECT_DAP4                  _MK_ENUM_CONST(7)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_A_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0                  _MK_ADDR_CONST(0xa0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SECURE                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_VAL                        _MK_MASK_CONST(0x215556aa)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_GPV_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTF_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RANGE                  27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTE_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RANGE                  25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RANGE                  23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RANGE                  19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_INIT_ENUM                      PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP4_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP3_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP2_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_DAP1_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RANGE                  9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATE_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RANGE                  7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RANGE                  3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RANGE                  1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_A_0_ATA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_B_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0                  _MK_ADDR_CONST(0xa4)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SECURE                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_VAL                        _MK_MASK_CONST(0x6a8865aa)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RANGE                 31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXK_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RANGE                 29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RANGE                 27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_CRTP_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RANGE                 23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SLXA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RANGE                 19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDO_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_SPDI_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_KBCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_GPU7_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_PTA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RANGE                 3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_I2CP_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RANGE                   1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_B_0_RM_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_C_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0                  _MK_ADDR_CONST(0xa8)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SECURE                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_VAL                        _MK_MASK_CONST(0xaa6655)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_RESET_MASK                       _MK_MASK_CONST(0xf3ffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_READ_MASK                        _MK_MASK_CONST(0xf3ffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_WRITE_MASK                       _MK_MASK_CONST(0xf3ffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RANGE                 31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2C_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RANGE                 29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_XM2D_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_RANGE                  25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_GME_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RANGE                 23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRRX_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT                 _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RANGE                 21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_IRTX_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RANGE                 19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIH_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RANGE                 17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIG_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIF_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPID_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RANGE                 5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_SPIA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RANGE                        3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_INIT_ENUM                    PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV2_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RANGE                        1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_INIT_ENUM                    PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_C_0_CDEV1_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_D_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0                  _MK_ADDR_CONST(0xac)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SECURE                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_VAL                        _MK_MASK_CONST(0xa1a55a8a)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_SDC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SHIFT                 _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_RANGE                 27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_DDRC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+// LC_P? for : lcd_pclk, lcd_de, lcd_hsycn, lcd_vsync, lcd_m0, lcd_m1, lcd_vp0, hdmi_int
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RANGE                 25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_INIT_ENUM                     PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_CSUS_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+// LS_P? for : lcd_sdin, lcd_sdout, lcd_wr_, lcd_cs0, lcd_dc0, lcd_sck, lcd_pwr0, lcd_pwr1, lcd_pwr2
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RANGE                   23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LC_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT                   _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RANGE                   21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_WOFFSET                 0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT                 _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_INIT_ENUM                       PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_NORMAL                  _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_DOWN                       _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_PULL_UP                 _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LS_PU_PD_RSVD                    _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RANGE                      19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD23_22_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RANGE                      17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD21_20_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RANGE                      15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_WOFFSET                    0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_INIT_ENUM                  PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_NORMAL                     _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_DOWN                  _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_PULL_UP                    _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD19_18_PU_PD_RSVD                       _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RANGE                       13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_WOFFSET                     0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_INIT_ENUM                   PULL_DOWN
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_NORMAL                      _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_DOWN                   _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_PULL_UP                     _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_LD17_0_PU_PD_RSVD                        _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RANGE                  11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RANGE                  9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UCA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RANGE                  7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RANGE                  5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RANGE                  3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RANGE                  1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_D_0_UAA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_PP_PULLUPDOWN_REG_E_0  
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0                  _MK_ADDR_CONST(0xb0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SECURE                   0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WORD_COUNT                       0x1
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_VAL                        _MK_MASK_CONST(0xa008000a)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SHIFT                  _MK_SHIFT_CONST(30)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_RANGE                  31:30
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_OWC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_RANGE                  29:28
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_INIT_ENUM                      PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_DDC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_RANGE                  27:26
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMD_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_RANGE                  25:24
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMC_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_RANGE                  23:22
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMB_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_RANGE                  21:20
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_GMA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_RANGE                        19:18
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_WOFFSET                      0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_DEFAULT                      _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_INIT_ENUM                    PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_NORMAL                       _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_PULL_DOWN                    _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_PULL_UP                      _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_SDIO1_PU_PD_RSVD                 _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_RANGE                  17:16
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_WOFFSET                        0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_INIT_ENUM                      NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_NORMAL                 _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_PULL_DOWN                      _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_PULL_UP                        _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_UDA_PU_PD_RSVD                   _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_RANGE                 15:14
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_CK32_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_RANGE                 13:12
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_RANGE                 11:10
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCD_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_RANGE                 9:8
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCC_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RANGE                 7:6
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCB_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RANGE                 5:4
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_INIT_ENUM                     NORMAL
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_PMCA_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RANGE                 3:2
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCE_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SHIFT)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RANGE                 1:0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_WOFFSET                       0x0
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT                       _MK_MASK_CONST(0x2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_INIT_ENUM                     PULL_UP
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_NORMAL                        _MK_ENUM_CONST(0)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_DOWN                     _MK_ENUM_CONST(1)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_PULL_UP                       _MK_ENUM_CONST(2)
+#define APB_MISC_PP_PULLUPDOWN_REG_E_0_KBCF_PU_PD_RSVD                  _MK_ENUM_CONST(3)
+
+
+// Register APB_MISC_ASYNC_COREPWRCONFIG_0  
+#define APB_MISC_ASYNC_COREPWRCONFIG_0                  _MK_ADDR_CONST(0x400)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SECURE                   0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_WORD_COUNT                       0x1
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_RESET_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_READ_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0x7)
+// Power is on in TDA/TDB partitions
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_RANGE                      0:0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_INIT_ENUM                  DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_TD_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Power is on in VE/MPE partitions
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_RANGE                      1:1
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_WOFFSET                    0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_INIT_ENUM                  DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_VE_COREPWR_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Power is on in CPU partition
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SHIFT)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_RANGE                     2:2
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_WOFFSET                   0x0
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_INIT_ENUM                 DISABLE
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_COREPWRCONFIG_0_CPU_COREPWR_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 1028 [0x404] 
+
+// Reserved address 1032 [0x408] 
+
+// Reserved address 1036 [0x40c] 
+
+// Register APB_MISC_ASYNC_EMCPADEN_0  
+#define APB_MISC_ASYNC_EMCPADEN_0                       _MK_ADDR_CONST(0x410)
+#define APB_MISC_ASYNC_EMCPADEN_0_SECURE                        0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_EMCPADEN_0_RESET_VAL                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_EMCPADEN_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+// outputs enable for EMC pads
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_RANGE                       0:0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_WOFFSET                     0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_OUTPUT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// inputs enable for EMC pads
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SHIFT)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_RANGE                        1:1
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_WOFFSET                      0x0
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_EMCPADEN_0_EMC_PAD_INPUT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Reserved address 1044 [0x414] 
+
+// Reserved address 1048 [0x418] 
+
+// Reserved address 1052 [0x41c] 
+
+// Reserved address 1056 [0x420] 
+
+// Reserved address 1060 [0x424] 
+
+// Reserved address 1064 [0x428] 
+
+// Register APB_MISC_ASYNC_VCLKCTRL_0  
+#define APB_MISC_ASYNC_VCLKCTRL_0                       _MK_ADDR_CONST(0x42c)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SECURE                        0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_VCLKCTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+// VCLK input enable
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SHIFT)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_RANGE                     0:0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_WOFFSET                   0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_IE_ENABLE                    _MK_ENUM_CONST(1)
+
+// VCLK invert enable
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SHIFT)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_RANGE                      1:1
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_WOFFSET                    0x0
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_VCLKCTRL_0_VCLK_PAD_INVERSION_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Reserved address 1072 [0x430] 
+
+// Reserved address 1076 [0x434] 
+
+// Register APB_MISC_ASYNC_TVDACVHSYNCCTRL_0  
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0                        _MK_ADDR_CONST(0x438)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SECURE                         0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SHIFT)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_RANGE                   1:0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_HSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SHIFT)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_RANGE                   3:2
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACVHSYNCCTRL_0_TVDAC_VSYNCDLY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_TVDACCNTL_0  
+#define APB_MISC_ASYNC_TVDACCNTL_0                      _MK_ADDR_CONST(0x43c)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SECURE                       0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_WORD_COUNT                   0x1
+#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_VAL                    _MK_MASK_CONST(0x83b)
+#define APB_MISC_ASYNC_TVDACCNTL_0_RESET_MASK                   _MK_MASK_CONST(0x1effffff)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_READ_MASK                    _MK_MASK_CONST(0x1effffff)
+#define APB_MISC_ASYNC_TVDACCNTL_0_WRITE_MASK                   _MK_MASK_CONST(0x1effffff)
+// Power down everything including the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_RANGE                       0:0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_IDDQ_ENABLE                      _MK_ENUM_CONST(1)
+
+// Power down everything except the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT                  _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_RANGE                  1:1
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_POWERDOWN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Power down everything including the band-gap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_RANGE                  2:2
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_DETECT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTR output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_RANGE                     3:3
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPR_ENABLE                    _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTG output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_RANGE                     4:4
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPG_ENABLE                    _MK_ENUM_CONST(1)
+
+// Low power (sleep) mode. SHut down OUTB output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_RANGE                     5:5
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_SLEEPB_ENABLE                    _MK_ENUM_CONST(1)
+
+// Adjust threshold voltage of comparator inside DAC
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_RANGE                    7:6
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_WOFFSET                  0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMP_TH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Turn bandgap averaging on/off
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_RANGE                        8:8
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_WOFFSET                      0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_AVG_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+// To adjust temp coeff
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_FIELD                 (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_RANGE                 11:9
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT                       _MK_MASK_CONST(0x4)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CURVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Control bits for bandgap
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_RANGE                  15:12
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_BGAP_CNTL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// For debugging. Selects internal analog output to be sent out of VREF pin
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_RANGE                      18:16
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_WOFFSET                    0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_ATEST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Reserved for additional control
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_RANGE                       23:19
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_CNTL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Enable COMPOUTR output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT                   _MK_SHIFT_CONST(25)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_RANGE                   25:25
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPR_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COMPOUTG output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT                   _MK_SHIFT_CONST(26)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_RANGE                   26:26
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPG_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COMPOUTB output
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT                   _MK_SHIFT_CONST(27)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_RANGE                   27:27
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_WOFFSET                 0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_COMPB_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Indicate load status
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SHIFT)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_RANGE                    28:28
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_WOFFSET                  0x0
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_UNLOADED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACCNTL_0_DAC_PLUG_OK_LOADED                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_TVDACSTATUS_0  
+#define APB_MISC_ASYNC_TVDACSTATUS_0                    _MK_ADDR_CONST(0x440)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SECURE                     0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_WORD_COUNT                         0x1
+#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_RESET_MASK                         _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_READ_MASK                  _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Channel R comparator output for auto-detect
+// 0 = COMPINR > threshold
+// 1 = COMPINR < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_RANGE                 0:0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Channel G comparator output for auto-detect
+// 0 = COMPING > threshold
+// 1 = COMPING < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT                 _MK_SHIFT_CONST(1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_RANGE                 1:1
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Channel B comparator output for auto-detect
+// 0 = COMPINB > threshold
+// 1 = COMPINB < threshold, or when POWERDOWN==1
+// comparison threshold = 0.325V
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SHIFT)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_RANGE                 2:2
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACSTATUS_0_DAC_COMPOUTB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_TVDACDINCONFIG_0  
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0                 _MK_ADDR_CONST(0x444)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SECURE                  0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WORD_COUNT                      0x1
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_RESET_MASK                      _MK_MASK_CONST(0xffffd37)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_READ_MASK                       _MK_MASK_CONST(0xffffd37)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_WRITE_MASK                      _MK_MASK_CONST(0xffffd37)
+// Data Input FIFO threshold
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_RANGE                       2:0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_WOFFSET                     0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT                     _MK_MASK_CONST(0x2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_FIFO_TH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// INPUT source for TVDAC
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_RANGE                        5:4
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_WOFFSET                      0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVDAC_OFF                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_TVO                  _MK_ENUM_CONST(1)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAY                      _MK_ENUM_CONST(2)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_SOURCE_DISPLAYB                     _MK_ENUM_CONST(3)
+
+// Override DAC DIN inputs
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_RANGE                  8:8
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_WOFFSET                        0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// DIN override
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_FIELD                     (_MK_MASK_CONST(0x3ff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_RANGE                     19:10
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_WOFFSET                   0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_DIN_ORIDE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// AMPIN
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT                 _MK_SHIFT_CONST(20)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_FIELD                 (_MK_MASK_CONST(0xff) << APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SHIFT)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_RANGE                 27:20
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_WOFFSET                       0x0
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_TVDACDINCONFIG_0_DAC_AMPIN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_INT_STATUS_0  // Interrupt Status
+//  This reflects status of all pending
+//  interrupts which is valid as long as
+//  the interrupt is not cleared even if the
+//  interrupt is masked. A pending interrupt
+//  can be cleared by writing a '1' to this
+//  the corresponding interrupt status bit
+//  in this register.
+//        0       rt  HGP0_INT_STATUS          // HGP0 Interrupt Status
+//                                             //  (this is cleared on write)
+//                                             //   0= interrupt not pending
+//                                             //   1= interrupt pending
+//        1       rt  HGP1_INT_STATUS          // HGP1 Interrupt Status
+//                                             //  (this is cleared on write)
+//                                             //   0= interrupt not pending
+//                                            //   1= interrupt pending
+//      2       rt  HGP2_INT_STATUS          // HGP2 Interrupt Status
+//                                          //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      4       rt  HGP4_INT_STATUS          // HGP4 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      5       rt  HGP5_INT_STATUS          // HGP5 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+//      6       rt  HGP6_INT_STATUS          // HGP6 Interrupt Status
+//                                           //  (this is cleared on write)
+//                                           //   0= interrupt not pending
+//                                           //   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0                     _MK_ADDR_CONST(0x448)
+#define APB_MISC_ASYNC_INT_STATUS_0_SECURE                      0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_WORD_COUNT                  0x1
+#define APB_MISC_ASYNC_INT_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// HGP7 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_RANGE                       7:7
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP7_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP8 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_RANGE                       8:8
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP8_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP9 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_RANGE                       9:9
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_WOFFSET                     0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP9_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HGP10 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_RANGE                      10:10
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP10_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HGP11 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_RANGE                      11:11
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP11_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HGP12 Interrupt Status
+//  (this is cleared on write)
+//   0= interrupt not pending
+//   1= interrupt pending
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SHIFT)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_RANGE                      12:12
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_WOFFSET                    0x0
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_STATUS_0_HGP12_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_ASYNC_INT_MASK_0  // Interrupt Mask
+// Setting bits in this register masked the
+//  corresponding interrupt but does not
+//  clear a pending interrupt and does not
+//  prevent a pending interrupt to be generated.
+//  Masking an interrupt also does not clear
+//  a pending interrupt status and does not
+//  a pending interrupt status to be generated.
+//      0       rw  HGP0_INT_MASK  i=0x0     // HGP0 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      1       rw  HGP1_INT_MASK  i=0x0     // HGP1 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      2       rw  HGP2_INT_MASK  i=0x0     // HGP2 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      4       rw  HGP4_INT_MASK  i=0x0     // HGP4 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      5       rw  HGP5_INT_MASK  i=0x0     // HGP5 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+//      6       rw  HGP6_INT_MASK  i=0x0     // HGP6 Interrupt Mask
+//          enum ( MASKED, NOTMASKED )       //   0= interrupt masked
+//                                           //   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0                       _MK_ADDR_CONST(0x44c)
+#define APB_MISC_ASYNC_INT_MASK_0_SECURE                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_WORD_COUNT                    0x1
+#define APB_MISC_ASYNC_INT_MASK_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_RESET_MASK                    _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_READ_MASK                     _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_RANGE                   7:7
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP7_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_RANGE                   8:8
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP8_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_RANGE                   9:9
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_MASKED                  _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP9_INT_MASK_NOTMASKED                       _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_RANGE                  10:10
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP10_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_RANGE                  11:11
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP11_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Mask   0= interrupt masked
+//   1= interrupt not masked
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SHIFT)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_RANGE                  12:12
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_MASKED                 _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_MASK_0_HGP12_INT_MASK_NOTMASKED                      _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_INT_POLARITY_0  // Interrupt Polarity
+//  These bits specify whether a pending interrupt 
+//  is generated on falling edge or on rising edge 
+//  of the corresponding input signal/event.
+//        0       rw  HGP0_INT_POLARITY  i=0x0  // HGP0 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      1       rw  HGP1_INT_POLARITY  i=0x0  // HGP1 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      2       rw  HGP2_INT_POLARITY  i=0x0  // HGP2 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      4       rw  HGP4_INT_POLARITY  i=0x0  // HGP4 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      5       rw  HGP5_INT_POLARITY  i=0x0  // HGP5 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+//      6       rw  HGP6_INT_POLARITY  i=0x0  // HGP6 Interrupt Polarity
+//      enum ( LOW, HIGH )                    //   0= falling edge interrupt
+//                                            //   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0                   _MK_ADDR_CONST(0x450)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SECURE                    0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_WORD_COUNT                        0x1
+#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_RESET_MASK                        _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_READ_MASK                         _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_POLARITY_0_WRITE_MASK                        _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_RANGE                   7:7
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP7_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_RANGE                   8:8
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP8_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_RANGE                   9:9
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP9_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_RANGE                  10:10
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP10_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_RANGE                  11:11
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP11_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Polarity   0= falling edge interrupt
+//   1= rising edge interrupt
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SHIFT)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_RANGE                  12:12
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_WOFFSET                        0x0
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_POLARITY_0_HGP12_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_ASYNC_INT_TYPE_SELECT_0  // Interrupt Type
+//  These bits specify whether an interrupt 
+//  is generated on an edge of a level type.
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0                        _MK_ADDR_CONST(0x454)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SECURE                         0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WORD_COUNT                     0x1
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_RESET_MASK                     _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_READ_MASK                      _MK_MASK_CONST(0x1f80)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_WRITE_MASK                     _MK_MASK_CONST(0x1f80)
+// HGP7 Interrupt Type   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(7)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_RANGE                    7:7
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP7_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP8 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(8)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_RANGE                    8:8
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP8_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP9 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT                    _MK_SHIFT_CONST(9)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_RANGE                    9:9
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_WOFFSET                  0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_EDGE                     _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP9_INT_TYPE_LEVEL                    _MK_ENUM_CONST(1)
+
+// HGP10 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_RANGE                   10:10
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP10_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// HGP11 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(11)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_RANGE                   11:11
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP11_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// HGP12 Interrupt Polarity   0= Edge type
+//   1= Level type
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(12)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SHIFT)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_RANGE                   12:12
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_WOFFSET                 0x0
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define APB_MISC_ASYNC_INT_TYPE_SELECT_0_HGP12_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_MODEREG_0  
+#define APB_MISC_GP_MODEREG_0                   _MK_ADDR_CONST(0x800)
+#define APB_MISC_GP_MODEREG_0_SECURE                    0x0
+#define APB_MISC_GP_MODEREG_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_MODEREG_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_READ_MASK                         _MK_MASK_CONST(0x301)
+#define APB_MISC_GP_MODEREG_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Standby pad input 1 = STANDBYN is    asserted (low  voltage),                   0 = STANDBYN is desasserted (high voltage)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_STANDBY_IE_SHIFT)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_RANGE                  0:0
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_WOFFSET                        0x0
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_DEASSERTED                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_MODEREG_0_STANDBY_IE_ASSERTED                       _MK_ENUM_CONST(1)
+
+// LP-DDR Strap option bit 0.
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SHIFT)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_RANGE                        8:8
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_WOFFSET                      0x0
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// LP-DDR Strap option bit 1.
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SHIFT)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_RANGE                        9:9
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_WOFFSET                      0x0
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_MODEREG_0_LPDDR_STRAP1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_HIDREV_0  
+#define APB_MISC_GP_HIDREV_0                    _MK_ADDR_CONST(0x804)
+#define APB_MISC_GP_HIDREV_0_SECURE                     0x0
+#define APB_MISC_GP_HIDREV_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_HIDREV_0_RESET_VAL                  _MK_MASK_CONST(0x22017)
+#define APB_MISC_GP_HIDREV_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
+#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
+#define APB_MISC_GP_HIDREV_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Chip ID family register. There maybe a new HIDFAM code
+// added for MG20 products, this is still being descided.
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_HIDFAM_SHIFT)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_RANGE                       3:0
+#define APB_MISC_GP_HIDREV_0_HIDFAM_WOFFSET                     0x0
+#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT                     _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_GPU                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD                    _MK_ENUM_CONST(1)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_BR_CHIPS                    _MK_ENUM_CONST(2)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_CRUSH                       _MK_ENUM_CONST(3)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_MCP                 _MK_ENUM_CONST(4)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_CK                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_VAIO                        _MK_ENUM_CONST(6)
+#define APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD_SOC                        _MK_ENUM_CONST(7)
+
+// Chip ID major revision (0: Emulation, 1-15: Silicon)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MAJORREV_SHIFT)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_RANGE                     7:4
+#define APB_MISC_GP_HIDREV_0_MAJORREV_WOFFSET                   0x0
+#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_EMULATION                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_HIDREV_0_MAJORREV_A01                       _MK_ENUM_CONST(1)
+
+// Chip ID
+#define APB_MISC_GP_HIDREV_0_CHIPID_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_HIDREV_0_CHIPID_FIELD                       (_MK_MASK_CONST(0xff) << APB_MISC_GP_HIDREV_0_CHIPID_SHIFT)
+#define APB_MISC_GP_HIDREV_0_CHIPID_RANGE                       15:8
+#define APB_MISC_GP_HIDREV_0_CHIPID_WOFFSET                     0x0
+#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT                     _MK_MASK_CONST(0x20)
+#define APB_MISC_GP_HIDREV_0_CHIPID_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_CHIPID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Chip ID minor revision (IF MAJORREV==0(Emulation) THEN  0: QT, 1:E388 FPGA)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SHIFT                     _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_HIDREV_0_MINORREV_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_HIDREV_0_MINORREV_SHIFT)
+#define APB_MISC_GP_HIDREV_0_MINORREV_RANGE                     19:16
+#define APB_MISC_GP_HIDREV_0_MINORREV_WOFFSET                   0x0
+#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APB_MISC_GP_HIDREV_0_MINORREV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_HIDREV_0_MINORREV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2056 [0x808] 
+
+// Reserved address 2060 [0x80c] 
+
+// Register APB_MISC_GP_ASDBGREG_0  
+#define APB_MISC_GP_ASDBGREG_0                  _MK_ADDR_CONST(0x810)
+#define APB_MISC_GP_ASDBGREG_0_SECURE                   0x0
+#define APB_MISC_GP_ASDBGREG_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_ASDBGREG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_RESET_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
+#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_READ_MASK                        _MK_MASK_CONST(0x3ff0ffdf)
+#define APB_MISC_GP_ASDBGREG_0_WRITE_MASK                       _MK_MASK_CONST(0x3ff0ffdf)
+// Enables iddq (WARNING: Will functionally kill chip)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_RANGE                    0:0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_WOFFSET                  0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_IDDQ_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enables pullup
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT                  _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_RANGE                  1:1
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_WOFFSET                        0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLUP_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enables pulldown
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_RANGE                        2:2
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PULLDOWN_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enables debug mode
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_RANGE                       3:3
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_DEBUG_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enables performance monitor mode
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_RANGE                  4:4
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_WOFFSET                        0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_PM_ENABLE_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_RANGE                        7:6
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_CLKBYP_FUNC_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_RANGE                        8:8
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T1CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_RANGE                        9:9
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T2CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT                        _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_RANGE                        10:10
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T3CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_RANGE                        11:11
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T4CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_RANGE                        12:12
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T5CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_RANGE                        13:13
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T6CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_RANGE                        14:14
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_T7CLK_ENABLE                       _MK_ENUM_CONST(1)
+
+//  Obsolete previously used with host_pad_macros (jmoskal)
+//16      rw  CFG2TMC_SW_BP_WRNCLK      i=0x0
+//    enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_RANGE                      15:15
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_SW_BP_CLK_DIV_ENABLE                     _MK_ENUM_CONST(1)
+
+// control timing characteristics for the compiled rams
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT                   _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_RANGE                   21:20
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_WOFFSET                 0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_EMAA_ENABLE                  _MK_ENUM_CONST(1)
+
+// control write timing characteristics for the compiled RAMDP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT                        _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_RANGE                        23:22
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMPDP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_RANGE                       25:24
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_PDP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMREG
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_RANGE                       27:26
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_REG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the compiled RAMSP
+// ECO 385781, add reset to RAM_SVOP_SP
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SHIFT)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_RANGE                        29:28
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG_0_CFG2TMC_RAM_SVOP_SP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2068 [0x814] 
+
+// Register APB_MISC_GP_OBSCTRL_0  
+#define APB_MISC_GP_OBSCTRL_0                   _MK_ADDR_CONST(0x818)
+#define APB_MISC_GP_OBSCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_OBSCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_OBSCTRL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_OBSCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Module-level mux select for determining which debug signals to send out
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_FIELD                 (_MK_MASK_CONST(0xffff) << APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_RANGE                 15:0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_WOFFSET                       0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Observation module select
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT                 _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_RANGE                 19:16
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_WOFFSET                       0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_PMC                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_UAVP                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CSI                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CSICIL                        _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DISPLAY                       _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DISPLAYB                      _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DSI                   _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_HDMI                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_TVO                   _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CAR                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_EMC                   _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_GR2D                  _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_HOST1X                        _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MC                    _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MSELECT                       _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_STRAT12                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FUSE                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_KFUSE                 _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CSITE                 _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_CLIP                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_IDX                   _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_SETUP                 _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_VPE                   _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ALU                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ATRAST                        _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_DWR                   _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_FDC                   _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_PSEQ                  _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_QRAST                 _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_TEX                   _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEA                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEB                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_MPEC                  _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_UVDE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_EPP                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_ISP                   _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_VI                    _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_PCIE2                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_AFI                   _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_USB                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_USB2                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_MOD_SEL_USB3                  _MK_ENUM_CONST(2)
+
+// Observation partition select
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_RANGE                        23:20
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_WOFFSET                      0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_AO                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_AVP                  _MK_ENUM_CONST(1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_DIS                  _MK_ENUM_CONST(2)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_GR                   _MK_ENUM_CONST(3)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_MPE                  _MK_ENUM_CONST(4)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_PCX                  _MK_ENUM_CONST(5)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_ST                   _MK_ENUM_CONST(6)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDA                  _MK_ENUM_CONST(7)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_TDB                  _MK_ENUM_CONST(8)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VE                   _MK_ENUM_CONST(9)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_VDE                  _MK_ENUM_CONST(10)
+#define APB_MISC_GP_OBSCTRL_0_OBS_PART_SEL_USX                  _MK_ENUM_CONST(11)
+
+// Module internal mux select
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SHIFT                     _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_FIELD                     (_MK_MASK_CONST(0x7f) << APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_RANGE                     30:24
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_WOFFSET                   0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_SIG_INT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Observation bus enable
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_OBSCTRL_0_OBS_EN_SHIFT)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_RANGE                      31:31
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_WOFFSET                    0x0
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OBSCTRL_0_OBS_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_OBSDATA_0  
+#define APB_MISC_GP_OBSDATA_0                   _MK_ADDR_CONST(0x81c)
+#define APB_MISC_GP_OBSDATA_0_SECURE                    0x0
+#define APB_MISC_GP_OBSDATA_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_OBSDATA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_OBSDATA_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Observation port data.  This should be the same data that is going out on the observation bus.
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_OBSDATA_0_OBS_DATA_SHIFT)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_RANGE                    31:0
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_WOFFSET                  0x0
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OBSDATA_0_OBS_DATA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2080 [0x820] 
+
+// Reserved address 2084 [0x824] 
+
+// Reserved address 2088 [0x828] 
+
+// Reserved address 2092 [0x82c] 
+
+// Reserved address 2096 [0x830] 
+
+// Reserved address 2100 [0x834] 
+
+// Reserved address 2104 [0x838] 
+
+// Reserved address 2108 [0x83c] 
+
+// Reserved address 2112 [0x840] 
+
+// Reserved address 2116 [0x844] 
+
+// Reserved address 2120 [0x848] 
+
+// Reserved address 2124 [0x84c] 
+
+// Reserved address 2128 [0x850] 
+
+// Reserved address 2132 [0x854] 
+
+// Register APB_MISC_GP_ASDBGREG2_0  
+#define APB_MISC_GP_ASDBGREG2_0                 _MK_ADDR_CONST(0x858)
+#define APB_MISC_GP_ASDBGREG2_0_SECURE                  0x0
+#define APB_MISC_GP_ASDBGREG2_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_ASDBGREG2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_RESET_MASK                      _MK_MASK_CONST(0x7ff80)
+#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_READ_MASK                       _MK_MASK_CONST(0x7ff80)
+#define APB_MISC_GP_ASDBGREG2_0_WRITE_MASK                      _MK_MASK_CONST(0x7ff80)
+//Enable bypass of functional clock with test clock 8
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_RANGE                       7:7
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T8CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 9
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_RANGE                       8:8
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_WOFFSET                     0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T9CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 10
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT                      _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_RANGE                      9:9
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T10CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 11
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_RANGE                      10:10
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T11CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 12
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT                      _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_RANGE                      11:11
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T12CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 13
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_RANGE                      12:12
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T13CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 14
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_RANGE                      13:13
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T14CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 15
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT                      _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_RANGE                      14:14
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T15CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 16
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_RANGE                      15:15
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T16CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 17
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_RANGE                      16:16
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T17CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of functional clock with test clock 18
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT                      _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_RANGE                      17:17
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_WOFFSET                    0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_T18CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+//Enable bypass of sync Already in NV_car
+//  18       rw  CFG2TMC_OSCFI_BYPASS     i=0x0  //Enable bypass of oscfi
+//            enum ( DISABLE, ENABLE )
+//  19       rw  CFG2TMC_OSCFI_EN         i=0x0  //Enable oscfi refclk
+//      enum ( DISABLE, ENABLE )
+//      enum ( DISABLE, ENABLE )
+//  25:21   rw  CFG2TMC_OSCFI_D           i=0x0  //
+//  31:26   rw  CFG2TMC_OSCFI_S           i=0x0  //
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SHIFT)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_RANGE                        18:18
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_WOFFSET                      0x0
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ASDBGREG2_0_CFG2TMC_SW_BP_SYNC_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APB_MISC_GP_ASDBGREG3_0  
+#define APB_MISC_GP_ASDBGREG3_0                 _MK_ADDR_CONST(0x85c)
+#define APB_MISC_GP_ASDBGREG3_0_SECURE                  0x0
+#define APB_MISC_GP_ASDBGREG3_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_ASDBGREG3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
+#define APB_MISC_GP_ASDBGREG3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
+#define APB_MISC_GP_ASDBGREG3_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff)
+// control write timing characteristics for the L1 idata and ddata rams
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SHIFT)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_RANGE                   1:0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_WOFFSET                 0x0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the L1 itag  and dtag rams 
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SHIFT                    _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SHIFT)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_RANGE                    3:2
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_WOFFSET                  0x0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L1TAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the L2 (SCU) data rams
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SHIFT)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_RANGE                   5:4
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_WOFFSET                 0x0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the L2 (SCU) tag  rams 
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SHIFT)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_RANGE                    7:6
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_WOFFSET                  0x0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_L2TAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// control write timing characteristics for the irams  
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SHIFT)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_RANGE                     9:8
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_WOFFSET                   0x0
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ASDBGREG3_0_CFG2TMC_RAM_SVOP_IRAM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_EMU_REVID_0  
+#define APB_MISC_GP_EMU_REVID_0                 _MK_ADDR_CONST(0x860)
+#define APB_MISC_GP_EMU_REVID_0_SECURE                  0x0
+#define APB_MISC_GP_EMU_REVID_0_WORD_COUNT                      0x1
+#define APB_MISC_GP_EMU_REVID_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_EMU_REVID_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// USED by emulators to indicate netlist #, 0 for silicon.
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_FIELD                   (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_NETLIST_SHIFT)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_RANGE                   15:0
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_WOFFSET                 0x0
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_NETLIST_INIT_ENUM                       NV_EMUL_NETLIST
+
+// USED by emulators to indicate patch #, 0 for silicon.
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT                     _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_FIELD                     (_MK_MASK_CONST(0xffff) << APB_MISC_GP_EMU_REVID_0_PATCH_SHIFT)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_RANGE                     31:16
+#define APB_MISC_GP_EMU_REVID_0_PATCH_WOFFSET                   0x0
+#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_EMU_REVID_0_PATCH_INIT_ENUM                 NV_EMUL_PATCH
+
+
+// Register APB_MISC_GP_TRANSACTOR_SCRATCH_0  
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0                        _MK_ADDR_CONST(0x864)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SECURE                         0x0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// used for emulation to determine test results. USE CPU specific registers below.
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_FIELD                       (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SHIFT)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_RANGE                       31:0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_WOFFSET                     0x0
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_TRANSACTOR_SCRATCH_0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AOCFG1PADCTRL_0  //        0       rw  CFG2TMC_AOCFG1_PULLD_EN i=0x0   // AOCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_AOCFG1_PULLU_EN i=0x0   // AOCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_AOCFG1PADCTRL_0                     _MK_ADDR_CONST(0x868)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// AOCFG1 data pins high speed mode enable
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// AOCFG1 data pins schmidt enable
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// AOCFG1 data pins low power mode select
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG1PADCTRL_0_CFG2TMC_AOCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AOCFG2PADCTRL_0  //        0       rw  CFG2TMC_AOCFG2_PULLD_EN i=0x0   // AOCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_AOCFG2_PULLU_EN i=0x0   // AOCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_AOCFG2PADCTRL_0                     _MK_ADDR_CONST(0x86c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// AOCFG2 data pins high speed mode enable
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// AOCFG2 data pins schmidt enable
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// AOCFG2 data pins low power mode select
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AOCFG2PADCTRL_0_CFG2TMC_AOCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_ATCFG1PADCTRL_0  //        0       rw  CFG2TMC_ATCFG1_PULLD_EN   i=0x0   // ATCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_ATCFG1_PULLU_EN   i=0x0   // ATCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ATCFG1PADCTRL_0                     _MK_ADDR_CONST(0x870)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// ATCFG1 data pins high speed mode enable
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ATCFG1 data pins schmidt enable
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// ATCFG1 data pins low power mode select
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG1PADCTRL_0_CFG2TMC_ATCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_ATCFG2PADCTRL_0  //        0       rw  CFG2TMC_ATCFG2_PULLD_EN   i=0x0   // ATCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_ATCFG2_PULLU_EN   i=0x0   // ATCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_ATCFG2PADCTRL_0                     _MK_ADDR_CONST(0x874)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// ATCFG2 data pins high speed mode enable
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ATCFG2 data pins schmidt enable
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// ATCFG2 data pins low power mode select
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_ATCFG2PADCTRL_0_CFG2TMC_ATCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CDEV1CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV1CFG_PULLD_EN   i=0x0   // CDEV1CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CDEV1CFG_PULLU_EN   i=0x0   // CDEV1CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0                   _MK_ADDR_CONST(0x878)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// CDEV1CFG data pins high speed mode enable
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CDEV1CFG data pins schmidt enable
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// CDEV1CFG data pins low power mode select
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV1CFGPADCTRL_0_CFG2TMC_CDEV1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CDEV2CFGPADCTRL_0  //        0       rw  CFG2TMC_CDEV2CFG_PULLD_EN   i=0x0   // CDEV2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CDEV2CFG_PULLU_EN   i=0x0   // CDEV2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0                   _MK_ADDR_CONST(0x87c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// CDEV2CFG data pins high speed mode enable
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CDEV2CFG data pins schmidt enable
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// CDEV2CFG data pins low power mode select
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CDEV2CFGPADCTRL_0_CFG2TMC_CDEV2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CSUSCFGPADCTRL_0  //        0       rw  CFG2TMC_CSUSCFG_PULLD_EN   i=0x0   // CSUSCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CSUSCFG_PULLU_EN   i=0x0   // CSUSCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CSUSCFGPADCTRL_0                    _MK_ADDR_CONST(0x880)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// CSUSCFG data pins high speed mode enable
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// CSUSCFG data pins schmidt enable
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// CSUSCFG data pins low power mode select
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CSUSCFGPADCTRL_0_CFG2TMC_CSUSCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP1CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP1CFG_PULLD_EN   i=0x0   // DAP1CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP1CFG_PULLU_EN   i=0x0   // DAP1CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP1CFGPADCTRL_0                    _MK_ADDR_CONST(0x884)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP1CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP1CFG data pins schmidt enable
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP1CFG data pins low power mode select
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP1CFGPADCTRL_0_CFG2TMC_DAP1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP2CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP2CFG_PULLD_EN   i=0x0   // DAP2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP2CFG_PULLU_EN   i=0x0   // DAP2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP2CFGPADCTRL_0                    _MK_ADDR_CONST(0x888)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP2CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP2CFG data pins schmidt enable
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP2CFG data pins low power mode select
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP2CFGPADCTRL_0_CFG2TMC_DAP2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP3CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP3CFG_PULLD_EN   i=0x0   // DAP3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP3CFG_PULLU_EN   i=0x0   // DAP3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP3CFGPADCTRL_0                    _MK_ADDR_CONST(0x88c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP3CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP3CFG data pins schmidt enable
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP3CFG data pins low power mode select
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP3CFGPADCTRL_0_CFG2TMC_DAP3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DAP4CFGPADCTRL_0  //        0       rw  CFG2TMC_DAP4CFG_PULLD_EN   i=0x0   // DAP4CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DAP4CFG_PULLU_EN   i=0x0   // DAP4CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DAP4CFGPADCTRL_0                    _MK_ADDR_CONST(0x890)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// DAP4CFG data pins high speed mode enable
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DAP4CFG data pins schmidt enable
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DAP4CFG data pins low power mode select
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_RANGE                 5:4
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DAP4CFGPADCTRL_0_CFG2TMC_DAP4CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DBGCFGPADCTRL_0  //        0       rw  CFG2TMC_DBGCFG_PULLD_EN   i=0x0   // DBGCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DBGCFG_PULLU_EN   i=0x0   // DBGCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DBGCFGPADCTRL_0                     _MK_ADDR_CONST(0x894)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// DBGCFG data pins high speed mode enable
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// DBGCFG data pins schmidt enable
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// DBGCFG data pins low power mode select
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DBGCFGPADCTRL_0_CFG2TMC_DBGCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_LCDCFG1PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG1_PULLD_EN   i=0x0   // LCDCFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_LCDCFG1_PULLU_EN   i=0x0   // LCDCFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_LCDCFG1PADCTRL_0                    _MK_ADDR_CONST(0x898)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// LCDCFG1 data pins high speed mode enable
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCDCFG1 data pins schmidt enable
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCDCFG1 data pins low power mode select
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_RANGE                 5:4
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG1PADCTRL_0_CFG2TMC_LCDCFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_LCDCFG2PADCTRL_0  //        0       rw  CFG2TMC_LCDCFG2_PULLD_EN   i=0x0   // LCDCFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_LCDCFG2_PULLU_EN   i=0x0   // LCDCFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_LCDCFG2PADCTRL_0                    _MK_ADDR_CONST(0x89c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+// LCDCFG2 data pins high speed mode enable
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_RANGE                       2:2
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_HSM_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// LCDCFG2 data pins schmidt enable
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// LCDCFG2 data pins low power mode select
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_RANGE                 5:4
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_WOFFSET                       0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_LPMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_RANGE                    16:12
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_RANGE                    24:20
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_RANGE                       29:28
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_RANGE                       31:30
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_LCDCFG2PADCTRL_0_CFG2TMC_LCDCFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO2CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO2CFG_PULLD_EN   i=0x0   // SDIO2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO2CFG_PULLU_EN   i=0x0   // SDIO2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO2CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO2CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO2CFG data pins low power mode select
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO2CFGPADCTRL_0_CFG2TMC_SDIO2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO3CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO3CFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO3CFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8a4)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO3CFGPADCTRL_0_CFG2TMC_SDIO3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SPICFGPADCTRL_0  //        0       rw  CFG2TMC_SPICFG_PULLD_EN   i=0x0   // SPICFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SPICFG_PULLU_EN   i=0x0   // SPICFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SPICFGPADCTRL_0                     _MK_ADDR_CONST(0x8a8)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SPICFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SPICFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SPICFG data pins high speed mode enable
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SPICFG data pins schmidt enable
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SPICFG data pins low power mode select
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SPICFGPADCTRL_0_CFG2TMC_SPICFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UAACFGPADCTRL_0  //        0       rw  CFG2TMC_UAACFG_PULLD_EN   i=0x0   // UAACFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UAACFG_PULLU_EN   i=0x0   // UAACFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UAACFGPADCTRL_0                     _MK_ADDR_CONST(0x8ac)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UAACFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UAACFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// UAACFG data pins high speed mode enable
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// UAACFG data pins schmidt enable
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// UAACFG data pins low power mode select
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UAACFGPADCTRL_0_CFG2TMC_UAACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UABCFGPADCTRL_0  //        0       rw  CFG2TMC_UABCFG_PULLD_EN   i=0x0   // UABCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UABCFG_PULLU_EN   i=0x0   // UABCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UABCFGPADCTRL_0                     _MK_ADDR_CONST(0x8b0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UABCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UABCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// UABCFG data pins high speed mode enable
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// UABCFG data pins schmidt enable
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// UABCFG data pins low power mode select
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UABCFGPADCTRL_0_CFG2TMC_UABCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UART2CFGPADCTRL_0  //        0       rw  CFG2TMC_UART2CFG_PULLD_EN   i=0x0   // UART2CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UART2CFG_PULLU_EN   i=0x0   // UART2CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UART2CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b4)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// UART2CFG data pins high speed mode enable
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// UART2CFG data pins schmidt enable
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// UART2CFG data pins low power mode select
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART2CFGPADCTRL_0_CFG2TMC_UART2CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UART3CFGPADCTRL_0  //        0       rw  CFG2TMC_UART3CFG_PULLD_EN   i=0x0   // UART3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UART3CFG_PULLU_EN   i=0x0   // UART3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UART3CFGPADCTRL_0                   _MK_ADDR_CONST(0x8b8)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// UART3CFG data pins high speed mode enable
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// UART3CFG data pins schmidt enable
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// UART3CFG data pins low power mode select
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UART3CFGPADCTRL_0_CFG2TMC_UART3CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_VICFG1PADCTRL_0  //        0       rw  CFG2TMC_VICFG1_PULLD_EN   i=0x0   // VICFG1 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_VICFG1_PULLU_EN   i=0x0   // VICFG1 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_VICFG1PADCTRL_0                     _MK_ADDR_CONST(0x8bc)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_VICFG1PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG1PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// VICFG1 data pins high speed mode enable
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VICFG1 data pins schmidt enable
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VICFG1 data pins low power mode select
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_RANGE                   5:4
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG1PADCTRL_0_CFG2TMC_VICFG1_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_VICFG2PADCTRL_0  //        0       rw  CFG2TMC_VICFG2_PULLD_EN   i=0x0   // VICFG2 pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_VICFG2_PULLU_EN   i=0x0   // VICFG2 pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_VICFG2PADCTRL_0                     _MK_ADDR_CONST(0x8c0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_VICFG2PADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_VICFG2PADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// VICFG2 data pins high speed mode enable
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// VICFG2 data pins schmidt enable
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// VICFG2 data pins low power mode select
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_RANGE                   5:4
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_VICFG2PADCTRL_0_CFG2TMC_VICFG2_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGAPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGA_PULLD_EN   i=0x0 // XM2CFGA pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGA_PULLU_EN i=0x0   // XM2CFGA pullup mode enable
+//            enum ( DISABLE, ENABLE )
+//        3       rw  CFG2TMC_XM2CFGA_RX_FT_REC_EN i=0x0   
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGAPADCTRL_0                    _MK_ADDR_CONST(0x8c4)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xffffc000)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xffffc070)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xffffc070)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xffffc070)
+// XM2CFGA data pins bypass outbound flop enable
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_RANGE                    4:4
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_BYPASS_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// XM2CFGA data pins preemp enable
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_RANGE                    5:5
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// pad clk_sel  (ma bits get this value inverted in lpddr2 mode)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_RANGE                      6:6
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_WOFFSET                    0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CLK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_RANGE                    18:14
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_RANGE                    23:19
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_RANGE                       27:24
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_RANGE                       31:28
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGCPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGC_PULLD_EN   i=0x0   // XM2CFGC pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGC_PULLU_EN   i=0x0   // XM2CFGC pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGCPADCTRL_0                    _MK_ADDR_CONST(0x8c8)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xfffffff0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xfffffff8)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xfffffff8)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffff8)
+// XM2CFGD data pins schmidt enable
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_RANGE                       8:4
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_RANGE                       13:9
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_RANGE                    18:14
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_RANGE                    23:19
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_RANGE                       27:24
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_RANGE                       31:28
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGDPADCTRL_0  //        0       rw  CFG2TMC_XM2CFGD_PULLD_EN   i=0x0   // XM2CFGD pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CFGD_PULLU_EN   i=0x0   // XM2CFGD pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CFGDPADCTRL_0                    _MK_ADDR_CONST(0x8cc)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0xfffffff0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0xfffffff8)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0xfffffff8)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xfffffff8)
+// XM2CFGD data pins schmidt enable
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_RANGE                     3:3
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_RANGE                       8:4
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_FIELD                       (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_RANGE                       13:9
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_TERM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT                    _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_RANGE                    18:14
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT                    _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_RANGE                    23:19
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_RANGE                       27:24
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_RANGE                       31:28
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_WOFFSET                     0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CLKCFGPADCTRL_0  //        0       rw  CFG2TMC_XM2CLKCFG_PULLD_EN   i=0x0   // XM2CLKCFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_XM2CLKCFG_PULLU_EN   i=0x0   // XM2CLKCFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0                  _MK_ADDR_CONST(0x8d0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SECURE                   0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_VAL                        _MK_MASK_CONST(0xffffc002)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_RESET_MASK                       _MK_MASK_CONST(0xffffc00e)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_READ_MASK                        _MK_MASK_CONST(0xffffc00e)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xffffc00e)
+// XM2 bypass outbound flop enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_RANGE                        1:1
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_BYPASS_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// preemp enable
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_RANGE                        2:2
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// XM2CLKCFG bypass drvdn/up calibration 
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SHIFT                    _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_RANGE                    3:3
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_BYPASS_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_RANGE                        18:14
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_RANGE                        23:19
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT                   _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_RANGE                   27:24
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT                   _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_RANGE                   31:28
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT                 _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2COMPPADCTRL_0  
+#define APB_MISC_GP_XM2COMPPADCTRL_0                    _MK_ADDR_CONST(0x8d4)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_SECURE                     0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_XM2COMPPADCTRL_0_RESET_VAL                  _MK_MASK_CONST(0x1f1f008)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_RESET_MASK                         _MK_MASK_CONST(0x1f1f0ff)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_READ_MASK                  _MK_MASK_CONST(0x1f1f0ff)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x1f1f0ff)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SHIFT)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_RANGE                     3:0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_WOFFSET                   0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SHIFT)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_RANGE                   4:4
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_TESTOUT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SHIFT)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_RANGE                     7:5
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_WOFFSET                   0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_BIAS_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_RANGE                        16:12
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_RANGE                        24:20
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_WOFFSET                      0x0
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_DEFAULT                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2VTTGENPADCTRL_0  
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0                  _MK_ADDR_CONST(0x8d8)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_SECURE                   0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_RESET_VAL                        _MK_MASK_CONST(0x5500)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_RESET_MASK                       _MK_MASK_CONST(0x7077701)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_READ_MASK                        _MK_MASK_CONST(0x7077703)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0x7077703)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_RANGE                    0:0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_WOFFSET                  0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// dummy pin
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_RANGE                     1:1
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_WOFFSET                   0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_RANGE                     10:8
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_WOFFSET                   0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_DEFAULT                   _MK_MASK_CONST(0x5)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_FIELD                      (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_RANGE                      14:12
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_WOFFSET                    0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_DEFAULT                    _MK_MASK_CONST(0x5)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_RANGE                        18:16
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_RANGE                        26:24
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_WOFFSET                      0x0
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_PADCTL_DFT_0  
+#define APB_MISC_GP_PADCTL_DFT_0                        _MK_ADDR_CONST(0x8dc)
+#define APB_MISC_GP_PADCTL_DFT_0_SECURE                         0x0
+#define APB_MISC_GP_PADCTL_DFT_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_PADCTL_DFT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_RESET_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_READ_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_PADCTL_DFT_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
+// Enable pin-shorting for tester mode pin-shorting
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SHIFT)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_RANGE                      0:0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_WOFFSET                    0x0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Select which pins are used for test-mode observe
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SHIFT)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_RANGE                     1:1
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_WOFFSET                   0x0
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_PADCTL_DFT_0_PINSHORT_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_SDIO1CFGPADCTRL_0  //        0       rw  CFG2TMC_SDIO1CFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_SDIO1CFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0                   _MK_ADDR_CONST(0x8e0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_SECURE                    0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_RESET_VAL                         _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_RESET_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_READ_MASK                         _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_RANGE                     2:2
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_HSM_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_RANGE                   3:3
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_WOFFSET                 0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_SCHMT_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_RANGE                       5:4
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_WOFFSET                     0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_LPMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_RANGE                  16:12
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_DEFAULT                        _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_RANGE                  24:20
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_WOFFSET                        0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_DEFAULT                        _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SHIFT                     _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_RANGE                     29:28
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_RANGE                     31:30
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_WOFFSET                   0x0
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_SDIO1CFGPADCTRL_0_CFG2TMC_SDIO1CFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGCPADCTRL2_0  
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0                   _MK_ADDR_CONST(0x8e4)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_SECURE                    0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_RESET_VAL                         _MK_MASK_CONST(0x8080042)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_RESET_MASK                        _MK_MASK_CONST(0xf0f00ff)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_READ_MASK                         _MK_MASK_CONST(0xf0f00ff)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_WRITE_MASK                        _MK_MASK_CONST(0xf0f00ff)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_RANGE                        0:0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins bypass outbound flop enable
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_RANGE                   1:1
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_BYPASS_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins preemp enable
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_RANGE                   2:2
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SHIFT                  _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_RANGE                  3:3
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SHIFT                 _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_RANGE                 4:4
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_WOFFSET                       0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SHIFT                  _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_RANGE                  5:5
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SHIFT                   _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_RANGE                   6:6
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SHIFT                  _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_RANGE                  7:7
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CLKSEL_DQS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_FIELD                    (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_RANGE                    19:16
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_WOFFSET                  0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_DEFAULT                  _MK_MASK_CONST(0x8)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SHIFT                     _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_FIELD                     (_MK_MASK_CONST(0xf) << APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SHIFT)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_RANGE                     27:24
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_WOFFSET                   0x0
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_DEFAULT                   _MK_MASK_CONST(0x8)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_XM2CFGDPADCTRL2_0  
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0                   _MK_ADDR_CONST(0x8e8)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_SECURE                    0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_RESET_VAL                         _MK_MASK_CONST(0x2)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_RESET_MASK                        _MK_MASK_CONST(0x7777000f)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_READ_MASK                         _MK_MASK_CONST(0x7777000f)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_WRITE_MASK                        _MK_MASK_CONST(0x7777000f)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_RANGE                        0:0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_WOFFSET                      0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins bypass outbound flop enable
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_RANGE                   1:1
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_BYPASS_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// XM2CFGD data pins preemp enable
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_RANGE                   2:2
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_WOFFSET                 0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SHIFT                  _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_RANGE                  3:3
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+//delay trim for byte 0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_RANGE                  18:16
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//delay trim for byte 1
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_RANGE                  22:20
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//delay trim for byte 2
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_RANGE                  26:24
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//delay trim for byte 3
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SHIFT                  _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SHIFT)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_RANGE                  30:28
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_WOFFSET                        0x0
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CRTCFGPADCTRL_0  //        0       rw  CFG2TMC_CRTCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_CRTCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_CRTCFGPADCTRL_0                     _MK_ADDR_CONST(0x8ec)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_CRTCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CRTCFGPADCTRL_0_CFG2TMC_CRTCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DDCCFGPADCTRL_0  //        0       rw  CFG2TMC_DDCCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_DDCCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_DDCCFGPADCTRL_0                     _MK_ADDR_CONST(0x8f0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_DDCCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DDCCFGPADCTRL_0_CFG2TMC_DDCCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_GMACFGPADCTRL_0  //        0       rw  CFG2TMC_GMACFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_GMACFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_GMACFGPADCTRL_0                     _MK_ADDR_CONST(0x8f4)
+#define APB_MISC_GP_GMACFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_GMACFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_GMACFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMACFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMACFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMACFGPADCTRL_0_CFG2TMC_GMACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_GMBCFGPADCTRL_0  //        0       rw  CFG2TMC_GMBCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_GMBCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_GMBCFGPADCTRL_0                     _MK_ADDR_CONST(0x8f8)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_GMBCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMBCFGPADCTRL_0_CFG2TMC_GMBCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_GMCCFGPADCTRL_0  //        0       rw  CFG2TMC_GMCCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_GMCCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_GMCCFGPADCTRL_0                     _MK_ADDR_CONST(0x8fc)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_GMCCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMCCFGPADCTRL_0_CFG2TMC_GMCCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_GMDCFGPADCTRL_0  //        0       rw  CFG2TMC_GMDCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_GMDCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_GMDCFGPADCTRL_0                     _MK_ADDR_CONST(0x900)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_GMDCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMDCFGPADCTRL_0_CFG2TMC_GMDCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_GMECFGPADCTRL_0  //        0       rw  CFG2TMC_GMECFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_GMECFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_GMECFGPADCTRL_0                     _MK_ADDR_CONST(0x904)
+#define APB_MISC_GP_GMECFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_GMECFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_GMECFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMECFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_GMECFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_GMECFGPADCTRL_0_CFG2TMC_GMECFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_OWRCFGPADCTRL_0  //        0       rw  CFG2TMC_OWRCFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_OWRCFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_OWRCFGPADCTRL_0                     _MK_ADDR_CONST(0x908)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_OWRCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_OWRCFGPADCTRL_0_CFG2TMC_OWRCFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_UADCFGPADCTRL_0  //        0       rw  CFG2TMC_UDACFG_PULLD_EN   i=0x0   // SDIO3CFG pulldown mode enable
+//            enum ( DISABLE, ENABLE )
+//        1       rw  CFG2TMC_UDACFG_PULLU_EN   i=0x0   // SDIO3CFG pullup mode enable
+//            enum ( DISABLE, ENABLE )
+#define APB_MISC_GP_UADCFGPADCTRL_0                     _MK_ADDR_CONST(0x90c)
+#define APB_MISC_GP_UADCFGPADCTRL_0_SECURE                      0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_WORD_COUNT                  0x1
+#define APB_MISC_GP_UADCFGPADCTRL_0_RESET_VAL                   _MK_MASK_CONST(0xf1612030)
+#define APB_MISC_GP_UADCFGPADCTRL_0_RESET_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UADCFGPADCTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_READ_MASK                   _MK_MASK_CONST(0xf1f1f03c)
+#define APB_MISC_GP_UADCFGPADCTRL_0_WRITE_MASK                  _MK_MASK_CONST(0xf1f1f03c)
+// SDIO3CFG data pins high speed mode enable
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_RANGE                 2:2
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_WOFFSET                       0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_HSM_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins schmidt enable
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_RANGE                       3:3
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_WOFFSET                     0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_SCHMT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// SDIO3CFG data pins low power mode select
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_RANGE                   5:4
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_WOFFSET                 0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_LPMD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_RANGE                      16:12
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_WOFFSET                    0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_DEFAULT                    _MK_MASK_CONST(0x12)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_RANGE                      24:20
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_WOFFSET                    0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_DEFAULT                    _MK_MASK_CONST(0x16)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SHIFT                 _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_RANGE                 29:28
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_WOFFSET                       0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVDN_SLWR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SHIFT)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_RANGE                 31:30
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_WOFFSET                       0x0
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_DEFAULT                       _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_UADCFGPADCTRL_0_CFG2TMC_UDACFG_CAL_DRVUP_SLWF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0  
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0                    _MK_ADDR_CONST(0x920)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SECURE                     0x0
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_WORD_COUNT                         0x1
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// used for emulation to determine test results.
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_FIELD                       (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SHIFT)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_RANGE                       31:0
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_WOFFSET                     0x0
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0_AVP_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0  
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0                   _MK_ADDR_CONST(0x924)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SECURE                    0x0
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// used for emulation to determine test results.
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SHIFT)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_RANGE                     31:0
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_WOFFSET                   0x0
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0_CPU0_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0  
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0                   _MK_ADDR_CONST(0x928)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SECURE                    0x0
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_WORD_COUNT                        0x1
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// used for emulation to determine test results.
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SHIFT)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_RANGE                     31:0
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_WOFFSET                   0x0
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0_CPU1_TRANSACTOR_SCRATCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DEV_PRESENT0_0  
+#define APB_MISC_GP_DEV_PRESENT0_0                      _MK_ADDR_CONST(0x92c)
+#define APB_MISC_GP_DEV_PRESENT0_0_SECURE                       0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_WORD_COUNT                   0x1
+#define APB_MISC_GP_DEV_PRESENT0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_DEV_PRESENT0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_RANGE                       0:0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_RANGE                     1:1
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_RANGE                     2:2
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_RANGE                     3:3
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_RANGE                     4:4
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_IRAM_D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_RANGE                        5:5
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_NOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_RANGE                      6:6
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_RANGE                      7:7
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EXIO2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_RANGE                       8:8
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GART_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SHIFT                     _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_RANGE                     9:9
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_HOST1X_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SHIFT                 _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_RANGE                 10:10
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_WOFFSET                       0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARM_PERIPH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_RANGE                    11:11
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MSELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SHIFT                 _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_RANGE                 12:12
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_WOFFSET                       0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_RANGE                        13:13
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SHIFT                 _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_RANGE                 14:14
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_WOFFSET                       0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_VI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_RANGE                        15:15
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_EPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_RANGE                        16:16
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_MPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_RANGE                       17:17
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR3D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_RANGE                       18:18
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_GR2D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_RANGE                        19:19
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SHIFT                    _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_RANGE                    20:20
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SHIFT                   _MK_SHIFT_CONST(21)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_RANGE                   21:21
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_DISPLAYB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_RANGE                      22:22
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_UPTAG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SHIFT                    _MK_SHIFT_CONST(23)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_RANGE                    23:23
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_SHR_SEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_RANGE                    24:24
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_SEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SHIFT                    _MK_SHIFT_CONST(25)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_RANGE                    25:25
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_ARB_PRI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SHIFT                       _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_RANGE                       26:26
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_RANGE                       27:27
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_RANGE                       28:28
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_RANGE                       29:29
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_TMR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_RANGE                        30:30
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_CAR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SHIFT                       _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_RANGE                       31:31
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT0_0_DEV_PRESENT_FLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DEV_PRESENT1_0  
+#define APB_MISC_GP_DEV_PRESENT1_0                      _MK_ADDR_CONST(0x930)
+#define APB_MISC_GP_DEV_PRESENT1_0_SECURE                       0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_WORD_COUNT                   0x1
+#define APB_MISC_GP_DEV_PRESENT1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_DEV_PRESENT1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_RANGE                    0:0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AHB_DMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_RANGE                    1:1
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_APB_DMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_RANGE                  2:2
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_COP_CACHE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_RANGE                       3:3
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_STAT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_RANGE                      4:4
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_RANGE                      5:5
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_RANGE                      6:6
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SHIFT                      _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_RANGE                      7:7
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SHIFT                      _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_RANGE                      8:8
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SHIFT                      _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_RANGE                      9:9
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_RANGE                      10:10
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_GPIO7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_RANGE                        11:11
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VCP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SHIFT                     _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_RANGE                     12:12
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VECTOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_RANGE                        13:13
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_RANGE                       14:14
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_BSEA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_RANGE                       15:15
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MISC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_RANGE                       16:16
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SHIFT                      _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_RANGE                      17:17
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_SPDIF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_RANGE                       18:18
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_RANGE                       19:19
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2S2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_RANGE                      20:20
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SHIFT                      _MK_SHIFT_CONST(21)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_RANGE                      21:21
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SHIFT                      _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_RANGE                      22:22
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_RANGE                      23:23
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_RANGE                      24:24
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_UARTE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SHIFT                       _MK_SHIFT_CONST(25)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_RANGE                       25:25
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_VFIR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SHIFT                   _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_RANGE                   26:26
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_NANDCTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SHIFT                      _MK_SHIFT_CONST(27)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_RANGE                      27:27
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_HSMMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_RANGE                        28:28
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_XIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SHIFT                       _MK_SHIFT_CONST(29)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_RANGE                       29:29
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_PWFM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SHIFT                    _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_RANGE                    30:30
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_MIPI_HS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_RANGE                        31:31
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT1_0_DEV_PRESENT_I2C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DEV_PRESENT2_0  
+#define APB_MISC_GP_DEV_PRESENT2_0                      _MK_ADDR_CONST(0x934)
+#define APB_MISC_GP_DEV_PRESENT2_0_SECURE                       0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_WORD_COUNT                   0x1
+#define APB_MISC_GP_DEV_PRESENT2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_DEV_PRESENT2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_RANGE                       0:0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_RANGE                       1:1
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_I2C3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_RANGE                        2:2
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TWC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_RANGE                       3:3
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_RANGE                       4:4
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_RANGE                       5:5
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_RANGE                       6:6
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SBC4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_RANGE                        7:7
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_RANGE                        8:8
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DVC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_RANGE                        9:9
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_RTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SHIFT                        _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_RANGE                        10:10
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_KBC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_RANGE                        11:11
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_RANGE                       12:12
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_FUSE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_RANGE                       13:13
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_EIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_RANGE                        14:14
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_RANGE                       15:15
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_RANGE                       16:16
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_USB3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_RANGE                        17:17
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TVO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_RANGE                        18:18
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_DSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_RANGE                       19:19
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_HDMI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_RANGE                  20:20
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SHIFT                  _MK_SHIFT_CONST(21)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_RANGE                  21:21
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_RANGE                  22:22
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TRI_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SHIFT                 _MK_SHIFT_CONST(23)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_RANGE                 23:23
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_WOFFSET                       0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_QUAD_ICTLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SHIFT                    _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_RANGE                    24:24
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SW_INTR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SHIFT                      _MK_SHIFT_CONST(25)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_RANGE                      25:25
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU0_PMU_INTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SHIFT                      _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_RANGE                      26:26
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_CPU1_PMU_INTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SHIFT                      _MK_SHIFT_CONST(27)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_RANGE                      27:27
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_TMRUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SHIFT                   _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_RANGE                   28:28
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_PRI_ICTLR_ARBGNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SHIFT                   _MK_SHIFT_CONST(29)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_RANGE                   29:29
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_TX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SHIFT                   _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_RANGE                   30:30
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_SEC_ICTLR_DRQ_RX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_RANGE                        31:31
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT2_0_DEV_PRESENT_AHB_DMA_CH0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DEV_PRESENT3_0  
+#define APB_MISC_GP_DEV_PRESENT3_0                      _MK_ADDR_CONST(0x938)
+#define APB_MISC_GP_DEV_PRESENT3_0_SECURE                       0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_WORD_COUNT                   0x1
+#define APB_MISC_GP_DEV_PRESENT3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_DEV_PRESENT3_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SHIFT                        _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_RANGE                        0:0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_RANGE                        1:1
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_RANGE                        2:2
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_DMA_CH3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SHIFT                        _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_RANGE                        3:3
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SHIFT                        _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_RANGE                        4:4
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SHIFT                        _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_RANGE                        5:5
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_RANGE                        6:6
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SHIFT                        _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_RANGE                        7:7
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SHIFT                        _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_RANGE                        8:8
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SHIFT                        _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_RANGE                        9:9
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SHIFT                        _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_RANGE                        10:10
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SHIFT                        _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_RANGE                        11:11
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_RANGE                        12:12
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_RANGE                       13:13
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_RANGE                       14:14
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_RANGE                       15:15
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SHIFT                       _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_RANGE                       16:16
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SHIFT                       _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_RANGE                       17:17
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SHIFT                       _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_RANGE                       18:18
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_APB_DMA_CH15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SHIFT                   _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_RANGE                   19:19
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_ARBC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SHIFT                  _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_RANGE                  20:20
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHPBDEBUG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_RANGE                        21:21
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SECURE_BOOT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_RANGE                   22:22
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AHB_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SHIFT                    _MK_SHIFT_CONST(23)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_RANGE                    23:23
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PMU_EXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_RANGE                       24:24
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PPCS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SHIFT                    _MK_SHIFT_CONST(25)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_RANGE                    25:25
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_WOFFSET                  0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_MMU_TLB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_RANGE                        26:26
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_CSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SHIFT                  _MK_SHIFT_CONST(27)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_RANGE                  27:27
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_ARM_PL310_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_RANGE                       28:28
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_PCIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_RANGE                        29:29
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SHIFT                     _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_RANGE                     30:30
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_AVPUCQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SHIFT                       _MK_SHIFT_CONST(31)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_RANGE                       31:31
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT3_0_DEV_PRESENT_SNOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_DEV_PRESENT4_0  
+#define APB_MISC_GP_DEV_PRESENT4_0                      _MK_ADDR_CONST(0x93c)
+#define APB_MISC_GP_DEV_PRESENT4_0_SECURE                       0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_WORD_COUNT                   0x1
+#define APB_MISC_GP_DEV_PRESENT4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_GP_DEV_PRESENT4_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_RANGE                     0:0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_RANGE                     1:1
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_RANGE                     2:2
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_RANGE                     3:3
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SDMMC4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_RANGE                      4:4
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_KFUSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SHIFT                      _MK_SHIFT_CONST(5)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_RANGE                      5:5
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_CSITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SHIFT                       _MK_SHIFT_CONST(6)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_RANGE                       6:6
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_RANGE                       7:7
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SHIFT                       _MK_SHIFT_CONST(8)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_RANGE                       8:8
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SHIFT                       _MK_SHIFT_CONST(9)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_RANGE                       9:9
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SHIFT                       _MK_SHIFT_CONST(10)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_RANGE                       10:10
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SHIFT                       _MK_SHIFT_CONST(11)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_RANGE                       11:11
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SHIFT                       _MK_SHIFT_CONST(12)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_RANGE                       12:12
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SHIFT                       _MK_SHIFT_CONST(13)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_RANGE                       13:13
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_RANGE                       14:14
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_RANGE                       15:15
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_WOFFSET                     0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_RANGE                      16:16
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SHIFT                      _MK_SHIFT_CONST(17)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_RANGE                      17:17
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_RANGE                      18:18
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SHIFT                      _MK_SHIFT_CONST(19)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_RANGE                      19:19
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SHIFT                      _MK_SHIFT_CONST(20)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_RANGE                      20:20
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SHIFT                      _MK_SHIFT_CONST(21)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_RANGE                      21:21
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_IPI15_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SHIFT                  _MK_SHIFT_CONST(22)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_RANGE                  22:22
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_WOFFSET                        0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_ARM_ICTLR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SHIFT                        _MK_SHIFT_CONST(23)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_RANGE                        23:23
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_HDMI_IOBIST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_RANGE                        24:24
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_WOFFSET                      0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_MIPI_IOBIST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SHIFT                     _MK_SHIFT_CONST(25)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_RANGE                     25:25
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X2_IOBIST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SHIFT                     _MK_SHIFT_CONST(26)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_RANGE                     26:26
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_WOFFSET                   0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_PCIE_X4_IOBIST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SHIFT                      _MK_SHIFT_CONST(27)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_RANGE                      27:27
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_WOFFSET                    0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LPDDR2_IOBIST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SHIFT                   _MK_SHIFT_CONST(28)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_RANGE                   28:28
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SHIFT                   _MK_SHIFT_CONST(29)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_RANGE                   29:29
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_WOFFSET                 0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_SPEEDO_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SHIFT)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_RANGE                 30:30
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_WOFFSET                       0x0
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_DEV_PRESENT4_0_DEV_PRESENT_LA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_ADDR_0  
+#define APB_MISC_GP_L2EMU_ADDR_0                        _MK_ADDR_CONST(0x940)
+#define APB_MISC_GP_L2EMU_ADDR_0_SECURE                         0x0
+#define APB_MISC_GP_L2EMU_ADDR_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_L2EMU_ADDR_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_READ_MASK                      _MK_MASK_CONST(0x7fff)
+#define APB_MISC_GP_L2EMU_ADDR_0_WRITE_MASK                     _MK_MASK_CONST(0x7fff)
+// 256-bit aligned cache address
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_FIELD                       (_MK_MASK_CONST(0x7fff) << APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SHIFT)
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_RANGE                       14:0
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_WOFFSET                     0x0
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_ADDR_0_L2EMU_ADDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_BE_0  
+#define APB_MISC_GP_L2EMU_BE_0                  _MK_ADDR_CONST(0x944)
+#define APB_MISC_GP_L2EMU_BE_0_SECURE                   0x0
+#define APB_MISC_GP_L2EMU_BE_0_WORD_COUNT                       0x1
+#define APB_MISC_GP_L2EMU_BE_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_BE_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_BE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_BE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_BE_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_BE_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// byte enables
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SHIFT)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_RANGE                   31:0
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_WOFFSET                 0x0
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_DEFAULT                 _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_BE_0_L2EMU_BE_INIT_ENUM                       -1
+
+
+// Register APB_MISC_GP_L2EMU_DATA0_0  
+#define APB_MISC_GP_L2EMU_DATA0_0                       _MK_ADDR_CONST(0x948)
+#define APB_MISC_GP_L2EMU_DATA0_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA0_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA0_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 0
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA0_0_L2EMU_DATA0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA1_0  
+#define APB_MISC_GP_L2EMU_DATA1_0                       _MK_ADDR_CONST(0x94c)
+#define APB_MISC_GP_L2EMU_DATA1_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA1_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 1
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA1_0_L2EMU_DATA1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA2_0  
+#define APB_MISC_GP_L2EMU_DATA2_0                       _MK_ADDR_CONST(0x950)
+#define APB_MISC_GP_L2EMU_DATA2_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA2_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA2_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 2
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA2_0_L2EMU_DATA2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA3_0  
+#define APB_MISC_GP_L2EMU_DATA3_0                       _MK_ADDR_CONST(0x954)
+#define APB_MISC_GP_L2EMU_DATA3_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA3_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA3_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 3
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA3_0_L2EMU_DATA3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA4_0  
+#define APB_MISC_GP_L2EMU_DATA4_0                       _MK_ADDR_CONST(0x958)
+#define APB_MISC_GP_L2EMU_DATA4_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA4_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA4_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA4_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 4
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA4_0_L2EMU_DATA4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA5_0  
+#define APB_MISC_GP_L2EMU_DATA5_0                       _MK_ADDR_CONST(0x95c)
+#define APB_MISC_GP_L2EMU_DATA5_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA5_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA5_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA5_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 5
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA5_0_L2EMU_DATA5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA6_0  
+#define APB_MISC_GP_L2EMU_DATA6_0                       _MK_ADDR_CONST(0x960)
+#define APB_MISC_GP_L2EMU_DATA6_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA6_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA6_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA6_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 6
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA6_0_L2EMU_DATA6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_DATA7_0  
+#define APB_MISC_GP_L2EMU_DATA7_0                       _MK_ADDR_CONST(0x964)
+#define APB_MISC_GP_L2EMU_DATA7_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_DATA7_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_DATA7_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_GP_L2EMU_DATA7_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// data word 7
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_FIELD                     (_MK_MASK_CONST(0xffffffff) << APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SHIFT)
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_RANGE                     31:0
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_DATA7_0_L2EMU_DATA7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_READ_0  
+#define APB_MISC_GP_L2EMU_READ_0                        _MK_ADDR_CONST(0x968)
+#define APB_MISC_GP_L2EMU_READ_0_SECURE                         0x0
+#define APB_MISC_GP_L2EMU_READ_0_WORD_COUNT                     0x1
+#define APB_MISC_GP_L2EMU_READ_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_L2EMU_READ_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+// trigger cache line read
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SHIFT)
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_RANGE                       0:0
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_WOFFSET                     0x0
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_READ_0_L2EMU_READ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_GP_L2EMU_WRITE_0  
+#define APB_MISC_GP_L2EMU_WRITE_0                       _MK_ADDR_CONST(0x96c)
+#define APB_MISC_GP_L2EMU_WRITE_0_SECURE                        0x0
+#define APB_MISC_GP_L2EMU_WRITE_0_WORD_COUNT                    0x1
+#define APB_MISC_GP_L2EMU_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_GP_L2EMU_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+// trigger cache line write
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SHIFT)
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_RANGE                     0:0
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_WOFFSET                   0x0
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_GP_L2EMU_WRITE_0_L2EMU_WRITE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_PLL_CFG0_0  // USB_PHY PLL Configuration Register 0
+//
+// The data sampling frequency relies on a 960MHz clock, so the goal of the PLL is to have:
+// In_Frequency*(PLL_VCOMULTBY2+1)*(PLL_NDIV/PLL_MDIV) = 960MHz
+//
+// With a 12MHz input from PLL_U, the default setting of 
+// PLL_VCOMULTBY2=1, PLL_NDIV=40 and PLL_MDIV=1 results in a correct output.
+#define APB_MISC_UTMIP_PLL_CFG0_0                       _MK_ADDR_CONST(0xa00)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SECURE                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_WORD_COUNT                    0x1
+#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_VAL                     _MK_MASK_CONST(0x280180)
+#define APB_MISC_UTMIP_PLL_CFG0_0_RESET_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_READ_MASK                     _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_WRITE_MASK                    _MK_MASK_CONST(0x7fffffff)
+// LOCK_ENABLE input of USB_PHY PLL.
+// Normally only used during test. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_RANGE                    0:0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// LOCKSEL[5:0] input of USB_PHY PLL.
+// Used in test modes only. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT                       _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_FIELD                       (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_RANGE                       6:1
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_WOFFSET                     0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VCOMULTBY2 control of the UTMIP PHY PLL.
+// Recommended setting is on. Additional divide by 2 on the 
+// VCO feedback. Which is setting the bit to 1. See cell spec.
+//
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT                    _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_RANGE                    7:7
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_WOFFSET                  0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// MDIV[7:0] input of the USB_PHY PLL. This is the predivide on the PLL. 
+// 0x0 is not allowed. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_RANGE                  15:8
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// NDIV[7:0] input of USB_PHY PLL. 
+// This is the feedback divider on the VCO feedback. 
+// 0x0 is not allowed. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT                  _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_FIELD                  (_MK_MASK_CONST(0xff) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_RANGE                  23:16
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT                        _MK_MASK_CONST(0x28)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PDIV[2:0] input of the USB_PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_RANGE                  26:24
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PDIVRST of the UTMIP PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_RANGE                       27:27
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_WOFFSET                     0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Selects which of the eight 60MHz clock phases to produce at the output 
+// of the USB PHY PLL. This is for a test mode. See cell specification.
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_FIELD                        (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_RANGE                        30:28
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_PLL_CFG1_0  // UTMIP PLL and PLLU configuration register 1
+#define APB_MISC_UTMIP_PLL_CFG1_0                       _MK_ADDR_CONST(0xa04)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SECURE                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_WORD_COUNT                    0x1
+#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_VAL                     _MK_MASK_CONST(0x182000c0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// Determines the time to wait until the output of USB_PHY PLL is considered stable. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_FIELD                   (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_RANGE                   11:0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT                 _MK_MASK_CONST(0xc0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input off. (Overrides FORCE_PLL_ACTIVE_POWERUP.)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE                        12:12
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input on. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT                  _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE                  13:13
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input off. (Overrides FORCE_PLL_ENABLE_POWERUP.)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE                        14:14
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input on. 
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT                  _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE                  15:15
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power down. (Overrides FORCE_PLLU_POWERUP.)  
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_RANGE                      16:16
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power up.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_RANGE                        17:17
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// SETUP[8:0] input of USB_PHY PLL.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_FIELD                 (_MK_MASK_CONST(0x1ff) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_RANGE                 26:18
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_WOFFSET                       0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT                       _MK_MASK_CONST(0x8)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1ff)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Controls the wait time to enable PLL_U when coming out of suspend or reset.
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE                     31:27
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_XCVR_CFG0_0  // UTMIP transceiver cell configuration register 0
+#define APB_MISC_UTMIP_XCVR_CFG0_0                      _MK_ADDR_CONST(0xa08)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SECURE                       0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x20202500)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// SETUP[3:0] input of XCVR cell. HS driver output control. 4 LSBs.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_FIELD                       (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_RANGE                       3:0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HS slew rate control. The two LSBs.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT                      _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_RANGE                      5:4
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FS slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT                      _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_RANGE                      7:6
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// LS rising slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_RANGE                     9:8
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// LS falling slew rate control.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT                     _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_RANGE                     11:10
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Internal loopback inside XCVR cell. Used for IOBIST.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT                  _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_RANGE                  12:12
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_WOFFSET                        0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Enable HS termination.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT                      _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_RANGE                      13:13
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PD input into power down. (Overrides FORCE_PD_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_RANGE                       14:14
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Force PD input into power up. 
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT                 _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_RANGE                 15:15
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_WOFFSET                       0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power down. (Overrides FORCE_PD2_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_RANGE                      16:16
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT                        _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_RANGE                        17:17
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power down. (Overrides FORCE_PDZI_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_RANGE                     18:18
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT                       _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_RANGE                       19:19
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Disconnect method on the usb transceiver pad
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SHIFT                       _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_RANGE                       20:20
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Low speed bias selection method for usb transceiver pad
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SHIFT                  _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_RANGE                  21:21
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Most significant bits of SETUP.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_FIELD                   (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_RANGE                   24:22
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_WOFFSET                 0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Most significant bits of HS_SLEW.
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SHIFT                  _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_FIELD                  (_MK_MASK_CONST(0x7f) << APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_RANGE                  31:25
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_WOFFSET                        0x0
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_DEFAULT                        _MK_MASK_CONST(0x10)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BIAS_CFG0_0  // UTMIP Bias cell configuration register 0
+#define APB_MISC_UTMIP_BIAS_CFG0_0                      _MK_ADDR_CONST(0xa0c)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SECURE                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x1ffffff)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x1ffffff)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x1ffffff)
+// HS squelch detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_RANGE                  1:0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// HS disconnect detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_RANGE                   3:2
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// HS chirp detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_FIELD                    (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_RANGE                    5:4
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SessionEnd detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_RANGE                 7:6
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Vbus detector level.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_RANGE                 9:8
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Power down bias circuit.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT                   _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_RANGE                   10:10
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Power down OTG circuit.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT                    _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_RANGE                    11:11
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Active 1.5K pullup control offset.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT                     _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_RANGE                     14:12
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_WOFFSET                   0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Active termination control offset.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT                       _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_RANGE                       17:15
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_WOFFSET                     0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0: StaticGpi = IdDig. 1: StaticGpi = GPI_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT                  _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_RANGE                  18:18
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// See GPI_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT                  _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_RANGE                  19:19
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: IdDig = IdDig. 1: IdDig = IDDIG_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_RANGE                        20:20
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_WOFFSET                      0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// See IDDIG_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_RANGE                        21:21
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_WOFFSET                      0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0: IDPD = ~IdPullup. 1: IDPD = IDPD_VAL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT                 _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_RANGE                 22:22
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// See IDPD_SEL.
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT                 _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_RANGE                 23:23
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Most significant bit of UTMIP_HSDISCON_LEVEL, bit 2
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SHIFT                       _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_RANGE                       24:24
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_WOFFSET                     0x0
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_HSRX_CFG0_0  // UTMIP High speed receive config 0 
+#define APB_MISC_UTMIP_HSRX_CFG0_0                      _MK_ADDR_CONST(0xa10)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SECURE                       0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x91653400)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Require 4 sync pattern transitions (01) instead of 3
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_RANGE                    0:0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sync pattern detection needs 3 consecutive samples instead of 4
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_RANGE                   1:1
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_WOFFSET                 0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Based on incoming edges and current sampling position, adjust phase
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT                     _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_FIELD                     (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_RANGE                     3:2
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_WOFFSET                   0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Retime the path. 
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT                   _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_FIELD                   (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_RANGE                   5:4
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_WOFFSET                 0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pass through the feedback, do not block it.
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT                    _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_RANGE                    6:6
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// When in Chirp Mode, allow chirp rx data through
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT                       _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_RANGE                       7:7
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Do not declare underrun errors
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT                 _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_RANGE                 8:8
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Do not declare overrun errors until overflow of FIFO
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_RANGE                  9:9
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Depth of elastic input store
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT                    _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_RANGE                    14:10
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_WOFFSET                  0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT                  _MK_MASK_CONST(0xd)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of cycles of idle to declare IDLE. 
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_RANGE                        19:15
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT                      _MK_MASK_CONST(0xa)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Do not strip incoming data
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT                     _MK_SHIFT_CONST(20)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_RANGE                     20:20
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_WOFFSET                   0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Limit the delay of the squelch at EOP time
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT                  _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_RANGE                  23:21
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT                        _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// The number of (edges-1) needed to move the sampling point
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_FIELD                  (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_RANGE                  27:24
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_WOFFSET                        0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Realign the inertia counters on a new packet
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT                       _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_RANGE                       28:28
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_WOFFSET                     0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Allow consecutive ups and downs on the bits, debug only, set to 0.
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_RANGE                        29:29
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Keep the stay alive pattern on active
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_FIELD                      (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_RANGE                      31:30
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_WOFFSET                    0x0
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_HSRX_CFG1_0  // UTMIP High speed receive config 1
+#define APB_MISC_UTMIP_HSRX_CFG1_0                      _MK_ADDR_CONST(0xa14)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SECURE                       0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x13)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
+// Allow Keep Alive packets 
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_RANGE                      0:0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_WOFFSET                    0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// How long to wait before start of sync launches RxActive
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_FIELD                        (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_RANGE                        5:1
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_WOFFSET                      0x0
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT                      _MK_MASK_CONST(0x9)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_FSLSRX_CFG0_0  // UTMIP full and Low speed receive config 0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0                    _MK_ADDR_CONST(0xa18)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SECURE                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WORD_COUNT                         0x1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_VAL                  _MK_MASK_CONST(0xfd548429)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Give up on packet if a long sequence of J 
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_RANGE                  0:0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 20 bits of idle should end the packet if FsLsIdleCountLimitCfg=1.
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_RANGE                    6:1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT                  _MK_MASK_CONST(0x14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Enable the reset of the state machine on extended SE0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT                   _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_RANGE                   7:7
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 4 bits of of SEO should exceed the time limit
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT                     _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_RANGE                     13:8
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT                   _MK_MASK_CONST(0x4)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Require a full sync pattern to declare the data received
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT                       _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_RANGE                       14:14
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_WOFFSET                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Limit the number of bit times a K can last
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT                      _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_RANGE                      15:15
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_WOFFSET                    0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Number of K bits in question
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_FIELD                        (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_RANGE                        21:16
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT                      _MK_MASK_CONST(0x14)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Only look for transitioning out of EOP
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT                   _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_RANGE                   22:22
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Do not allow >= dribble bits 
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_RANGE                  25:23
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x2)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Do not allow <= dribble bits
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT                  _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_FIELD                  (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_RANGE                  28:26
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT                    _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_RANGE                    29:29
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Filter SE1
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_RANGE                        30:30
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// One SE1, don't allow dribble
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT                        _MK_SHIFT_CONST(31)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_RANGE                        31:31
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_FSLSRX_CFG1_0  // UTMIP full and Low speed receive config 1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0                    _MK_ADDR_CONST(0xa1c)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SECURE                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WORD_COUNT                         0x1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_VAL                  _MK_MASK_CONST(0x2267400)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_RESET_MASK                         _MK_MASK_CONST(0x7ffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_READ_MASK                  _MK_MASK_CONST(0x7ffffff)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_WRITE_MASK                         _MK_MASK_CONST(0x7ffffff)
+// Whether full speed EOP  is determined within 3(0) or 4(1) 60MHz cycles
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_RANGE                  0:0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_WOFFSET                        0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Whether full speed uses debouncing
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT                    _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_RANGE                    1:1
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Only look for a KK pattern, instead of KJKK
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_RANGE                   2:2
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in full speed mode
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_RANGE                     3:3
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in low  speed mode
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_RANGE                     4:4
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Only for this number of 60MHz of SEO and Idle to end packet
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT                   _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_FIELD                   (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_RANGE                   10:5
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_WOFFSET                 0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT                 _MK_MASK_CONST(0x20)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of SEO clock cycles to block bit extraction
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT                     _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_FIELD                     (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_RANGE                     16:11
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT                   _MK_MASK_CONST(0xe)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Phase count on which LS bits are extracted
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT                    _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_FIELD                    (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_RANGE                    22:17
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_WOFFSET                  0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT                  _MK_MASK_CONST(0x13)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of clock cycle of LS stable
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT                       _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_FIELD                       (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_RANGE                       25:23
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_WOFFSET                     0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT                     _MK_MASK_CONST(0x4)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Assumes line state filtering table is inclusive, not exclusive
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT                        _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_RANGE                        26:26
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_WOFFSET                      0x0
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_TX_CFG0_0  // UTMIP transmit config signals 
+#define APB_MISC_UTMIP_TX_CFG0_0                        _MK_ADDR_CONST(0xa20)
+#define APB_MISC_UTMIP_TX_CFG0_0_SECURE                         0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_WORD_COUNT                     0x1
+#define APB_MISC_UTMIP_TX_CFG0_0_RESET_VAL                      _MK_MASK_CONST(0x10200)
+#define APB_MISC_UTMIP_TX_CFG0_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define APB_MISC_UTMIP_TX_CFG0_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+// Do not sent SYNC or EOP
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT                     _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_RANGE                     0:0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_WOFFSET                   0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// No encoding, static programming
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_RANGE                        1:1
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// No bit stuffing, static programming
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT                        _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_RANGE                        2:2
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 2 -- not likely, for Chirp
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT                   _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_RANGE                   3:3
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_WOFFSET                 0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 3 -- perhaps, when sending controller made packets
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_RANGE                    4:4
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SIE, not macrocell, detects LineState change to resume
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT                    _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_RANGE                    5:5
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// output enable turns on  1 cycle before
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_RANGE                  6:6
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// output enable turns off 1 cycle after
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(7)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 7:7
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Disable high speed disconnect
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_RANGE                  8:8
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Only check during EOP
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT                 _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_RANGE                 9:9
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT                      _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_FIELD                      (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_RANGE                      14:10
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_WOFFSET                    0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT                    _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_RANGE                    15:15
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_WOFFSET                  0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Allow SOP to be source of transmit error stuffing
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT                        _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_RANGE                        16:16
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_WOFFSET                      0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// output enable turns on  1/2 cycle before
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_RANGE                  17:17
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// output enable turns off 1/2 cycle after 
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_RANGE                 18:18
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                       0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// output enable sends an initial J before sync pattern
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT                      _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_RANGE                      19:19
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_WOFFSET                    0x0
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_MISC_CFG0_0  // UTMIP miscellaneous configurations
+#define APB_MISC_UTMIP_MISC_CFG0_0                      _MK_ADDR_CONST(0xa24)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SECURE                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x3e00078)
+#define APB_MISC_UTMIP_MISC_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffffff)
+// Use combinational terminations or synced through CLKXTAL
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT                       _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_RANGE                       0:0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Use free running terminations at all time
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT                        _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_RANGE                        1:1
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Ignore free running terminations, even when no clock
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT                 _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_RANGE                 2:2
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Don't use free running terminations during suspend.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_RANGE                       3:3
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Determines if all signal need to be stable to not change a config.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT                       _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_RANGE                       4:4
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Number of cycles of crystal clock of signal not changing to consider stable.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT                     _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_FIELD                     (_MK_MASK_CONST(0x7) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_RANGE                     7:5
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force DM pulldown active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_RANGE                  8:8
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DP pulldown active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT                  _MK_SHIFT_CONST(9)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_RANGE                  9:9
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DM pullup active.      
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT                  _MK_SHIFT_CONST(10)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_RANGE                  10:10
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DP pullup active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT                  _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_RANGE                  11:11
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force DM pulldown inactive. (Overrides FORCE_PULLDN_DM.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT                        _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_RANGE                        12:12
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DP pulldown inactive. (Overrides FORCE_PULLDN_DP.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT                        _MK_SHIFT_CONST(13)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_RANGE                        13:13
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DM pullup inactive. (Overrides FORCE_PULLUP_DM.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT                        _MK_SHIFT_CONST(14)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_RANGE                        14:14
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force DP pullup inactive. (Overrides FORCE_PULLUP_DP.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT                        _MK_SHIFT_CONST(15)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_RANGE                        15:15
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force HS termination active.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_RANGE                    16:16
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force HS termination inactive.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT                  _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_RANGE                  17:17
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force HS clock always on.
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT                        _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_RANGE                        18:18
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force error insertion into RX path. (Used for IOBIST.)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT                        _MK_SHIFT_CONST(19)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_FIELD                        (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RANGE                        20:19
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DISABLE                      _MK_ENUM_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_ERR                      _MK_ENUM_CONST(1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RX_ERR                       _MK_ENUM_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_RX_ERR                   _MK_ENUM_CONST(3)
+
+// Don't block changes for 4ms when going from LS to FS (should not happen)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT                        _MK_SHIFT_CONST(21)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_RANGE                        21:21
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Suspend exit requires edge or simply a value...
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT                     _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_RANGE                     22:22
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT                    _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_RANGE                    23:23
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT                  _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_RANGE                  24:24
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT                      _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_RANGE                      25:25
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_WOFFSET                    0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Use DP/DM as obs bus
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT                     _MK_SHIFT_CONST(26)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_RANGE                     26:26
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Select DP/DM obs signals
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT                 _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_RANGE                 30:27
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_MISC_CFG1_0  // UTMIP miscellaneous configurations
+#define APB_MISC_UTMIP_MISC_CFG1_0                      _MK_ADDR_CONST(0xa28)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SECURE                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x40198024)
+#define APB_MISC_UTMIP_MISC_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x7fffffff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x7fffffff)
+// Bit 0: 0: 0xa5 -> treat as KeepAlive 
+//        1: treat as regular packet 
+// Bit 1: 0: Turn on FS EOP detection
+//        1: Turn off FS EOP detection
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_FIELD                 (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_RANGE                 1:0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT                  _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_RANGE                  2:2
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT                       _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_RANGE                       3:3
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT                  _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_FIELD                  (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_RANGE                  4:4
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT                 _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_RANGE                 5:5
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// WRONG! This should be 1ms -> 0x50
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT                        _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_FIELD                        (_MK_MASK_CONST(0xfff) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_RANGE                        17:6
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_WOFFSET                      0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT                      _MK_MASK_CONST(0x600)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0xfff)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 5 us / (1/19.2MHz) = 96 / 16 = 6
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT                     _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE                     22:18
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_WOFFSET                   0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT                   _MK_MASK_CONST(0x6)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT                      _MK_SHIFT_CONST(23)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_RANGE                      23:23
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_WOFFSET                    0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT                 _MK_SHIFT_CONST(24)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_RANGE                 24:24
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT                  _MK_SHIFT_CONST(25)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_FIELD                  (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_RANGE                  26:25
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_WOFFSET                        0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: Use FS filtering on line state when XcvrSel=3
+// 1: Use LS filtering on line state when XcvrSel=3
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT                       _MK_SHIFT_CONST(27)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_RANGE                       27:27
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_WOFFSET                     0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Use neg edge sync for linestate
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT                    _MK_SHIFT_CONST(28)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_RANGE                    28:28
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_WOFFSET                  0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bypass LineState reclocking logic
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT                 _MK_SHIFT_CONST(29)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_RANGE                 29:29
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Selects whether to enable the crystal clock in the module.
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT                 _MK_SHIFT_CONST(30)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_FIELD                 (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_RANGE                 30:30
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_WOFFSET                       0x0
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_DEBOUNCE_CFG0_0  // UTMIP Avalid and Bvalid debounce
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0                  _MK_ADDR_CONST(0xa2c)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SECURE                   0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WORD_COUNT                       0x1
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// simulation value -- Used for interrupts
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_RANGE                      15:0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_WOFFSET                    0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// simulation value -- Used for interrupts
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT                      _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_FIELD                      (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_RANGE                      31:16
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_WOFFSET                    0x0
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT                    _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BAT_CHRG_CFG0_0  // UTMIP battery charger configuration
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0                  _MK_ADDR_CONST(0xa30)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SECURE                   0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WORD_COUNT                       0x1
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
+// Power down charger circuit
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT                      _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_RANGE                      0:0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_WOFFSET                    0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT                   _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_RANGE                   1:1
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_RANGE                   2:2
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT                    _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_RANGE                    3:3
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT                    _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_RANGE                    4:4
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_SPARE_CFG0_0  // Utmip spare configuration bits 
+#define APB_MISC_UTMIP_SPARE_CFG0_0                     _MK_ADDR_CONST(0xa34)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SECURE                      0x0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_WORD_COUNT                  0x1
+#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_VAL                   _MK_MASK_CONST(0xffff0000)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Spare register bits
+// 0: HS_RX_IPG_ERROR_ENABLE
+// 1: HS_RX_FLUSH_ALAP. Flush as late as possible
+// 2: HS_RX_LATE_SQUELCH. Delay Squelch by 1 CLK480 cycle.
+// 3: FUSE_SETUP_SEL. Select between regular CFG value and JTAG values for UX_SETUP
+// 31 to 4: Reserved
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_FIELD                   (_MK_MASK_CONST(0xffffffff) << APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_RANGE                   31:0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_WOFFSET                 0x0
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT                 _MK_MASK_CONST(0xffff0000)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_INIT_ENUM                       -65536
+
+
+// Register APB_MISC_UTMIP_XCVR_CFG1_0  // UTMIP transceiver cell configuration register 1
+#define APB_MISC_UTMIP_XCVR_CFG1_0                      _MK_ADDR_CONST(0xa38)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_SECURE                       0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_XCVR_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x822a)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Force PDDISC input into power down. (Overrides FORCE_PDDISC_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_RANGE                   0:0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Force PDDISC input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SHIFT                     _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_RANGE                     1:1
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PDCHRP input input into power down. (Overrides FORCE_PDCHRP_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SHIFT                   _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_FIELD                   (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_RANGE                   2:2
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_WOFFSET                 0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Force PDCHRP input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SHIFT                     _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_RANGE                     3:3
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PDDR input input into power down. (Overrides FORCE_PDDR_POWERUP.)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SHIFT                     _MK_SHIFT_CONST(4)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_RANGE                     4:4
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PDDR input into power up.
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SHIFT                       _MK_SHIFT_CONST(5)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_FIELD                       (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_RANGE                       5:5
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Encoded value to use on TCTRL when software override is enabled, 0 to 16 only
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SHIFT                     _MK_SHIFT_CONST(6)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_RANGE                     10:6
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Use a software override on TCTRL instead of automatic bias control
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SHIFT                     _MK_SHIFT_CONST(11)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_RANGE                     11:11
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Encoded value to use on RCTRL when software override is enabled, 0 to 16 only
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SHIFT                     _MK_SHIFT_CONST(12)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_FIELD                     (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_RANGE                     16:12
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Use a software override on RCTRL instead of automatic bias control
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SHIFT                     _MK_SHIFT_CONST(17)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_FIELD                     (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_RANGE                     17:17
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_WOFFSET                   0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Range adjusment on terminations.
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT                      _MK_SHIFT_CONST(18)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_RANGE                      21:18
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_WOFFSET                    0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Spare bits for usb transceiver pad ECO.
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SHIFT                       _MK_SHIFT_CONST(22)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_FIELD                       (_MK_MASK_CONST(0x3) << APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SHIFT)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_RANGE                       23:22
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_WOFFSET                     0x0
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BIAS_CFG1_0  // UTMIP Bias cell configuration register 1
+#define APB_MISC_UTMIP_BIAS_CFG1_0                      _MK_ADDR_CONST(0xa3c)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_SECURE                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_BIAS_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x2a)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3fff)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3fff)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3fff)
+// Force PDTRK input into power down. (Overrides FORCE_PDTRK_POWERUP.)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_RANGE                    0:0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force PDTRK input into power up.
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SHIFT                      _MK_SHIFT_CONST(1)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_RANGE                      1:1
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_WOFFSET                    0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force VBUS_WAKEUP input into power down.
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SHIFT                    _MK_SHIFT_CONST(2)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_RANGE                    2:2
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Control the BIAS cell power down lag. The lag should be 20us. For a Xtal clock of 13MHz it should be set a 5. 
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SHIFT                 _MK_SHIFT_CONST(3)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_FIELD                 (_MK_MASK_CONST(0x1f) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_RANGE                 7:3
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_WOFFSET                       0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_DEFAULT                       _MK_MASK_CONST(0x5)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Debouncer time scaling, factor-1 to slow down debouncing by. So 0 is 1, 1 is 2, etc.
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT                  _MK_SHIFT_CONST(8)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_FIELD                  (_MK_MASK_CONST(0x3f) << APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_RANGE                  13:8
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_WOFFSET                        0x0
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_UTMIP_BIAS_STS0_0  // UTMIP Bias cell status register 0
+#define APB_MISC_UTMIP_BIAS_STS0_0                      _MK_ADDR_CONST(0xa40)
+#define APB_MISC_UTMIP_BIAS_STS0_0_SECURE                       0x0
+#define APB_MISC_UTMIP_BIAS_STS0_0_WORD_COUNT                   0x1
+#define APB_MISC_UTMIP_BIAS_STS0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_BIAS_STS0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APB_MISC_UTMIP_BIAS_STS0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Thermal encoding output from USB bias pad. 
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_FIELD                    (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_RANGE                    15:0
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Thermal encoding output from USB bias pad. 
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SHIFT                    _MK_SHIFT_CONST(16)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_FIELD                    (_MK_MASK_CONST(0xffff) << APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SHIFT)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_RANGE                    31:16
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_WOFFSET                  0x0
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL_0  
+#define APB_MISC_DAS_DAP_CTRL_SEL_0                     _MK_ADDR_CONST(0xc00)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_SECURE                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_READ_MASK                   _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_RANGE                    31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_RANGE                      30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_RANGE                      29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_RANGE                  4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_WOFFSET                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_0_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL  
+#define APB_MISC_DAS_DAP_CTRL_SEL                       _MK_ADDR_CONST(0xc00)
+#define APB_MISC_DAS_DAP_CTRL_SEL_SECURE                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_WORD_COUNT                    0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_RESET_MASK                    _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_READ_MASK                     _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_WRITE_MASK                    _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SHIFT                      _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_RANGE                      31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_SLAVE                      _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_MS_SEL_MASTER                     _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SHIFT                        _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_RANGE                        30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_WOFFSET                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_TX                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_RX                   _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SHIFT                        _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_FIELD                        (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_RANGE                        29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_WOFFSET                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_RX                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_SDATA2_RX_TX_TX                   _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SHIFT                    _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_FIELD                    (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_RANGE                    4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAC1                     _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAC2                     _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAC3                     _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP1                     _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP2                     _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP3                     _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP4                     _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_DAP5                     _MK_ENUM_CONST(20)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL_1  
+#define APB_MISC_DAS_DAP_CTRL_SEL_1                     _MK_ADDR_CONST(0xc04)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_SECURE                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_READ_MASK                   _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_RANGE                    31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_RANGE                      30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_RANGE                      29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_RANGE                  4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_WOFFSET                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_1_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL_2  
+#define APB_MISC_DAS_DAP_CTRL_SEL_2                     _MK_ADDR_CONST(0xc08)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_SECURE                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_READ_MASK                   _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_RANGE                    31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_RANGE                      30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_RANGE                      29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_RANGE                  4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_WOFFSET                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_2_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL_3  
+#define APB_MISC_DAS_DAP_CTRL_SEL_3                     _MK_ADDR_CONST(0xc0c)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_SECURE                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_READ_MASK                   _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_RANGE                    31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_RANGE                      30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_RANGE                      29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_RANGE                  4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_WOFFSET                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_3_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)
+
+
+// Register APB_MISC_DAS_DAP_CTRL_SEL_4  
+#define APB_MISC_DAS_DAP_CTRL_SEL_4                     _MK_ADDR_CONST(0xc10)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_SECURE                      0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_RESET_MASK                  _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_READ_MASK                   _MK_MASK_CONST(0xe000001f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_WRITE_MASK                  _MK_MASK_CONST(0xe000001f)
+//This bit is programmed to put particular DAP is either in master or slave mode when two or more DAPs are in by-pass mode.
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SHIFT                    _MK_SHIFT_CONST(31)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_FIELD                    (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_RANGE                    31:31
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_WOFFSET                  0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_SLAVE                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_MS_SEL_MASTER                   _MK_ENUM_CONST(1)
+
+//To program sdata1 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SHIFT                      _MK_SHIFT_CONST(30)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_RANGE                      30:30
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_TX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA1_TX_RX_RX                 _MK_ENUM_CONST(1)
+
+//To program sdata2 in either tx or rx mode when two or more DAPs are in by-pass mode
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SHIFT                      _MK_SHIFT_CONST(29)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_FIELD                      (_MK_MASK_CONST(0x1) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_RANGE                      29:29
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_WOFFSET                    0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_RX                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_SDATA2_RX_TX_TX                 _MK_ENUM_CONST(1)
+
+//DAP selection bits to select one of the three DACs or one of the five DAPs
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_FIELD                  (_MK_MASK_CONST(0x1f) << APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SHIFT)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_RANGE                  4:0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_WOFFSET                        0x0
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAC1                   _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAC2                   _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAC3                   _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP1                   _MK_ENUM_CONST(16)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP2                   _MK_ENUM_CONST(17)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP3                   _MK_ENUM_CONST(18)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP4                   _MK_ENUM_CONST(19)
+#define APB_MISC_DAS_DAP_CTRL_SEL_4_DAP_CTRL_SEL_DAP5                   _MK_ENUM_CONST(20)
+
+
+// Reserved address 3092 [0xc14] 
+
+// Reserved address 3096 [0xc18] 
+
+// Reserved address 3100 [0xc1c] 
+
+// Reserved address 3104 [0xc20] 
+
+// Reserved address 3108 [0xc24] 
+
+// Reserved address 3112 [0xc28] 
+
+// Reserved address 3116 [0xc2c] 
+
+// Reserved address 3120 [0xc30] 
+
+// Reserved address 3124 [0xc34] 
+
+// Reserved address 3128 [0xc38] 
+
+// Reserved address 3132 [0xc3c] 
+
+// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0  
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0                   _MK_ADDR_CONST(0xc40)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_SECURE                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_WORD_COUNT                        0x1
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_RESET_MASK                        _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_READ_MASK                         _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_WRITE_MASK                        _MK_MASK_CONST(0xff00000f)
+//These bits are to control the selection of sdata2 input for DACs. 
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_RANGE                      31:28
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA2_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of sdata1 input for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_RANGE                      27:24
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_SDATA1_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of bit clock and fsync for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_RANGE                 3:0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_WOFFSET                       0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP1                  _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP2                  _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP3                  _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP4                  _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0_DAC_CLK_SEL_DAP5                  _MK_ENUM_CONST(4)
+
+
+// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL  
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL                     _MK_ADDR_CONST(0xc40)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_SECURE                      0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_WORD_COUNT                  0x1
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_RESET_MASK                  _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_READ_MASK                   _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_WRITE_MASK                  _MK_MASK_CONST(0xff00000f)
+//These bits are to control the selection of sdata2 input for DACs. 
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_RANGE                        31:28
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_WOFFSET                      0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP1                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP2                 _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP3                 _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP4                 _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_DAP5                 _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of sdata1 input for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SHIFT                        _MK_SHIFT_CONST(24)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_FIELD                        (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_RANGE                        27:24
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_WOFFSET                      0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP1                 _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP2                 _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP3                 _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP4                 _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_DAP5                 _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of bit clock and fsync for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SHIFT                   _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_FIELD                   (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_RANGE                   3:0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_WOFFSET                 0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP1                    _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP2                    _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP3                    _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP4                    _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_DAP5                    _MK_ENUM_CONST(4)
+
+
+// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1  
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1                   _MK_ADDR_CONST(0xc44)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_SECURE                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_WORD_COUNT                        0x1
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_RESET_MASK                        _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_READ_MASK                         _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_WRITE_MASK                        _MK_MASK_CONST(0xff00000f)
+//These bits are to control the selection of sdata2 input for DACs. 
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_RANGE                      31:28
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA2_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of sdata1 input for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_RANGE                      27:24
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_SDATA1_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of bit clock and fsync for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_RANGE                 3:0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_WOFFSET                       0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP1                  _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP2                  _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP3                  _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP4                  _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1_DAC_CLK_SEL_DAP5                  _MK_ENUM_CONST(4)
+
+
+// Register APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2  
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2                   _MK_ADDR_CONST(0xc48)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_SECURE                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_WORD_COUNT                        0x1
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_RESET_MASK                        _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_READ_MASK                         _MK_MASK_CONST(0xff00000f)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_WRITE_MASK                        _MK_MASK_CONST(0xff00000f)
+//These bits are to control the selection of sdata2 input for DACs. 
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_RANGE                      31:28
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA2_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of sdata1 input for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_FIELD                      (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_RANGE                      27:24
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_WOFFSET                    0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP1                       _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP2                       _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP3                       _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP4                       _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_SDATA1_SEL_DAP5                       _MK_ENUM_CONST(4)
+
+//These bits are to control the selection of bit clock and fsync for DACs.
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_FIELD                 (_MK_MASK_CONST(0xf) << APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SHIFT)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_RANGE                 3:0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_WOFFSET                       0x0
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP1                  _MK_ENUM_CONST(0)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP2                  _MK_ENUM_CONST(1)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP3                  _MK_ENUM_CONST(2)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP4                  _MK_ENUM_CONST(3)
+#define APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2_DAC_CLK_SEL_DAP5                  _MK_ENUM_CONST(4)
+
+
+// Reserved address 3148 [0xc4c] 
+
+// Reserved address 3152 [0xc50] 
+
+// Reserved address 3156 [0xc54] 
+
+// Reserved address 3160 [0xc58] 
+
+// Reserved address 3164 [0xc5c] 
+
+// Reserved address 3168 [0xc60] 
+
+// Reserved address 3172 [0xc64] 
+
+// Reserved address 3176 [0xc68] 
+
+// Reserved address 3180 [0xc6c] 
+
+// Reserved address 3184 [0xc70] 
+
+// Reserved address 3188 [0xc74] 
+
+// Reserved address 3192 [0xc78] 
+
+// Reserved address 3196 [0xc7c] 
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPB_MISC_REGS(_op_) \
+_op_(APB_MISC_PP_STRAPPING_OPT_A_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_A_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_B_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_C_0) \
+_op_(APB_MISC_PP_TRISTATE_REG_D_0) \
+_op_(APB_MISC_PP_CONFIG_CTL_0) \
+_op_(APB_MISC_PP_MISC_USB_OTG_0) \
+_op_(APB_MISC_PP_USB_PHY_PARAM_0) \
+_op_(APB_MISC_PP_USB_PHY_VBUS_SENSORS_0) \
+_op_(APB_MISC_PP_USB_PHY_VBUS_WAKEUP_ID_0) \
+_op_(APB_MISC_PP_USB_PHY_ALT_VBUS_STS_0) \
+_op_(APB_MISC_PP_MISC_SAVE_THE_DAY_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_A_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_B_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_C_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_D_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_E_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_F_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_G_0) \
+_op_(APB_MISC_PP_PIN_MUX_CTL_H_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_A_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_B_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_C_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_D_0) \
+_op_(APB_MISC_PP_PULLUPDOWN_REG_E_0) \
+_op_(APB_MISC_ASYNC_COREPWRCONFIG_0) \
+_op_(APB_MISC_ASYNC_EMCPADEN_0) \
+_op_(APB_MISC_ASYNC_VCLKCTRL_0) \
+_op_(APB_MISC_ASYNC_TVDACVHSYNCCTRL_0) \
+_op_(APB_MISC_ASYNC_TVDACCNTL_0) \
+_op_(APB_MISC_ASYNC_TVDACSTATUS_0) \
+_op_(APB_MISC_ASYNC_TVDACDINCONFIG_0) \
+_op_(APB_MISC_ASYNC_INT_STATUS_0) \
+_op_(APB_MISC_ASYNC_INT_MASK_0) \
+_op_(APB_MISC_ASYNC_INT_POLARITY_0) \
+_op_(APB_MISC_ASYNC_INT_TYPE_SELECT_0) \
+_op_(APB_MISC_GP_MODEREG_0) \
+_op_(APB_MISC_GP_HIDREV_0) \
+_op_(APB_MISC_GP_ASDBGREG_0) \
+_op_(APB_MISC_GP_OBSCTRL_0) \
+_op_(APB_MISC_GP_OBSDATA_0) \
+_op_(APB_MISC_GP_ASDBGREG2_0) \
+_op_(APB_MISC_GP_ASDBGREG3_0) \
+_op_(APB_MISC_GP_EMU_REVID_0) \
+_op_(APB_MISC_GP_TRANSACTOR_SCRATCH_0) \
+_op_(APB_MISC_GP_AOCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_AOCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_ATCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_ATCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_CDEV1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_CDEV2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_CSUSCFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DAP4CFGPADCTRL_0) \
+_op_(APB_MISC_GP_DBGCFGPADCTRL_0) \
+_op_(APB_MISC_GP_LCDCFG1PADCTRL_0) \
+_op_(APB_MISC_GP_LCDCFG2PADCTRL_0) \
+_op_(APB_MISC_GP_SDIO2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_SDIO3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_SPICFGPADCTRL_0) \
+_op_(APB_MISC_GP_UAACFGPADCTRL_0) \
+_op_(APB_MISC_GP_UABCFGPADCTRL_0) \
+_op_(APB_MISC_GP_UART2CFGPADCTRL_0) \
+_op_(APB_MISC_GP_UART3CFGPADCTRL_0) \
+_op_(APB_MISC_GP_VICFG1PADCTRL_0) \
+_op_(APB_MISC_GP_VICFG2PADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGAPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGCPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGDPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CLKCFGPADCTRL_0) \
+_op_(APB_MISC_GP_XM2COMPPADCTRL_0) \
+_op_(APB_MISC_GP_XM2VTTGENPADCTRL_0) \
+_op_(APB_MISC_GP_PADCTL_DFT_0) \
+_op_(APB_MISC_GP_SDIO1CFGPADCTRL_0) \
+_op_(APB_MISC_GP_XM2CFGCPADCTRL2_0) \
+_op_(APB_MISC_GP_XM2CFGDPADCTRL2_0) \
+_op_(APB_MISC_GP_CRTCFGPADCTRL_0) \
+_op_(APB_MISC_GP_DDCCFGPADCTRL_0) \
+_op_(APB_MISC_GP_GMACFGPADCTRL_0) \
+_op_(APB_MISC_GP_GMBCFGPADCTRL_0) \
+_op_(APB_MISC_GP_GMCCFGPADCTRL_0) \
+_op_(APB_MISC_GP_GMDCFGPADCTRL_0) \
+_op_(APB_MISC_GP_GMECFGPADCTRL_0) \
+_op_(APB_MISC_GP_OWRCFGPADCTRL_0) \
+_op_(APB_MISC_GP_UADCFGPADCTRL_0) \
+_op_(APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0) \
+_op_(APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH_0) \
+_op_(APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH_0) \
+_op_(APB_MISC_GP_DEV_PRESENT0_0) \
+_op_(APB_MISC_GP_DEV_PRESENT1_0) \
+_op_(APB_MISC_GP_DEV_PRESENT2_0) \
+_op_(APB_MISC_GP_DEV_PRESENT3_0) \
+_op_(APB_MISC_GP_DEV_PRESENT4_0) \
+_op_(APB_MISC_GP_L2EMU_ADDR_0) \
+_op_(APB_MISC_GP_L2EMU_BE_0) \
+_op_(APB_MISC_GP_L2EMU_DATA0_0) \
+_op_(APB_MISC_GP_L2EMU_DATA1_0) \
+_op_(APB_MISC_GP_L2EMU_DATA2_0) \
+_op_(APB_MISC_GP_L2EMU_DATA3_0) \
+_op_(APB_MISC_GP_L2EMU_DATA4_0) \
+_op_(APB_MISC_GP_L2EMU_DATA5_0) \
+_op_(APB_MISC_GP_L2EMU_DATA6_0) \
+_op_(APB_MISC_GP_L2EMU_DATA7_0) \
+_op_(APB_MISC_GP_L2EMU_READ_0) \
+_op_(APB_MISC_GP_L2EMU_WRITE_0) \
+_op_(APB_MISC_UTMIP_PLL_CFG0_0) \
+_op_(APB_MISC_UTMIP_PLL_CFG1_0) \
+_op_(APB_MISC_UTMIP_XCVR_CFG0_0) \
+_op_(APB_MISC_UTMIP_BIAS_CFG0_0) \
+_op_(APB_MISC_UTMIP_HSRX_CFG0_0) \
+_op_(APB_MISC_UTMIP_HSRX_CFG1_0) \
+_op_(APB_MISC_UTMIP_FSLSRX_CFG0_0) \
+_op_(APB_MISC_UTMIP_FSLSRX_CFG1_0) \
+_op_(APB_MISC_UTMIP_TX_CFG0_0) \
+_op_(APB_MISC_UTMIP_MISC_CFG0_0) \
+_op_(APB_MISC_UTMIP_MISC_CFG1_0) \
+_op_(APB_MISC_UTMIP_DEBOUNCE_CFG0_0) \
+_op_(APB_MISC_UTMIP_BAT_CHRG_CFG0_0) \
+_op_(APB_MISC_UTMIP_SPARE_CFG0_0) \
+_op_(APB_MISC_UTMIP_XCVR_CFG1_0) \
+_op_(APB_MISC_UTMIP_BIAS_CFG1_0) \
+_op_(APB_MISC_UTMIP_BIAS_STS0_0) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL_0) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL_1) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL_2) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL_3) \
+_op_(APB_MISC_DAS_DAP_CTRL_SEL_4) \
+_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0) \
+_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL) \
+_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1) \
+_op_(APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APB_MISC   0x00000000
+#define BASE_ADDRESS_APB_MISC_PP        0x00000000
+#define BASE_ADDRESS_APB_MISC_ASYNC     0x00000400
+#define BASE_ADDRESS_APB_MISC_GP        0x00000800
+#define BASE_ADDRESS_APB_MISC_UTMIP     0x00000a00
+#define BASE_ADDRESS_APB_MISC_DAS       0x00000c00
+
+//
+// ARAPB_MISC REGISTER BANKS
+//
+
+#define APB_MISC_PP0_FIRST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
+#define APB_MISC_PP0_LAST_REG 0x0008 // APB_MISC_PP_STRAPPING_OPT_A_0
+#define APB_MISC_PP1_FIRST_REG 0x0014 // APB_MISC_PP_TRISTATE_REG_A_0
+#define APB_MISC_PP1_LAST_REG 0x0028 // APB_MISC_PP_MISC_USB_OTG_0
+#define APB_MISC_PP2_FIRST_REG 0x0064 // APB_MISC_PP_USB_PHY_PARAM_0
+#define APB_MISC_PP2_LAST_REG 0x0064 // APB_MISC_PP_USB_PHY_PARAM_0
+#define APB_MISC_PP3_FIRST_REG 0x0070 // APB_MISC_PP_USB_PHY_VBUS_SENSORS_0
+#define APB_MISC_PP3_LAST_REG 0x00b0 // APB_MISC_PP_PULLUPDOWN_REG_E_0
+#define APB_MISC_ASYNC0_FIRST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
+#define APB_MISC_ASYNC0_LAST_REG 0x0400 // APB_MISC_ASYNC_COREPWRCONFIG_0
+#define APB_MISC_ASYNC1_FIRST_REG 0x0410 // APB_MISC_ASYNC_EMCPADEN_0
+#define APB_MISC_ASYNC1_LAST_REG 0x0410 // APB_MISC_ASYNC_EMCPADEN_0
+#define APB_MISC_ASYNC2_FIRST_REG 0x042c // APB_MISC_ASYNC_VCLKCTRL_0
+#define APB_MISC_ASYNC2_LAST_REG 0x042c // APB_MISC_ASYNC_VCLKCTRL_0
+#define APB_MISC_ASYNC3_FIRST_REG 0x0438 // APB_MISC_ASYNC_TVDACVHSYNCCTRL_0
+#define APB_MISC_ASYNC3_LAST_REG 0x0454 // APB_MISC_ASYNC_INT_TYPE_SELECT_0
+#define APB_MISC_GP0_FIRST_REG 0x0800 // APB_MISC_GP_MODEREG_0
+#define APB_MISC_GP0_LAST_REG 0x0804 // APB_MISC_GP_HIDREV_0
+#define APB_MISC_GP1_FIRST_REG 0x0810 // APB_MISC_GP_ASDBGREG_0
+#define APB_MISC_GP1_LAST_REG 0x0810 // APB_MISC_GP_ASDBGREG_0
+#define APB_MISC_GP2_FIRST_REG 0x0818 // APB_MISC_GP_OBSCTRL_0
+#define APB_MISC_GP2_LAST_REG 0x081c // APB_MISC_GP_OBSDATA_0
+#define APB_MISC_GP3_FIRST_REG 0x0858 // APB_MISC_GP_ASDBGREG2_0
+#define APB_MISC_GP3_LAST_REG 0x090c // APB_MISC_GP_UADCFGPADCTRL_0
+#define APB_MISC_GP4_FIRST_REG 0x0920 // APB_MISC_GP_AVP_TRANSACTOR_SCRATCH_0
+#define APB_MISC_GP4_LAST_REG 0x096c // APB_MISC_GP_L2EMU_WRITE_0
+#define APB_MISC_UTMIP0_FIRST_REG 0x0a00 // APB_MISC_UTMIP_PLL_CFG0_0
+#define APB_MISC_UTMIP0_LAST_REG 0x0a40 // APB_MISC_UTMIP_BIAS_STS0_0
+#define APB_MISC_DAS0_FIRST_REG 0x0c00 // APB_MISC_DAS_DAP_CTRL_SEL_0
+#define APB_MISC_DAS0_LAST_REG 0x0c10 // APB_MISC_DAS_DAP_CTRL_SEL_4
+#define APB_MISC_DAS1_FIRST_REG 0x0c40 // APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0
+#define APB_MISC_DAS1_LAST_REG 0x0c48 // APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPB_MISC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arapbdev_kbc.h b/arch/arm/mach-tegra/nv/include/ap20/arapbdev_kbc.h
new file mode 100644
index 000000000000..75e2804305fb
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arapbdev_kbc.h
@@ -0,0 +1,3949 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBDEV_KBC_H_INC_
+#define ___ARAPBDEV_KBC_H_INC_
+#define APBDEV_KBC_NUM_ROWS     16
+#define APBDEV_KBC_NUM_COLS     8
+#define APBDEV_KBC_MAX_ENT      8
+#define APBDEV_KBC_REG_WIDTH_BYTES      4
+#define APBDEV_KBC_FIFO_DEPTH   10
+
+// Register APBDEV_KBC_CONTROL_0  
+#define APBDEV_KBC_CONTROL_0                    _MK_ADDR_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_SECURE                     0x0
+#define APBDEV_KBC_CONTROL_0_WORD_COUNT                         0x1
+#define APBDEV_KBC_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x10000)
+#define APBDEV_KBC_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x7ffff)
+#define APBDEV_KBC_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x7ffff)
+#define APBDEV_KBC_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x7ffff)
+// Keyboard controller enable. Setting this bit will override the 
+// pins settings done in GPIO
+#define APBDEV_KBC_CONTROL_0_EN_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_CONTROL_0_EN_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_KBC_CONTROL_0_EN_SHIFT)
+#define APBDEV_KBC_CONTROL_0_EN_RANGE                   0:0
+#define APBDEV_KBC_CONTROL_0_EN_WOFFSET                 0x0
+#define APBDEV_KBC_CONTROL_0_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_CONTROL_0_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_CONTROL_0_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Key-press interrupt enable. Setting this bit will enable interrupt
+// on any key-press
+#define APBDEV_KBC_CONTROL_0_KP_INT_EN_SHIFT                    _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_CONTROL_0_KP_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_KBC_CONTROL_0_KP_INT_EN_SHIFT)
+#define APBDEV_KBC_CONTROL_0_KP_INT_EN_RANGE                    1:1
+#define APBDEV_KBC_CONTROL_0_KP_INT_EN_WOFFSET                  0x0
+#define APBDEV_KBC_CONTROL_0_KP_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_KP_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_CONTROL_0_KP_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_KP_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_KP_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_CONTROL_0_KP_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// FIFO overflow interrupt enable. Setting this bit will enable interrupt
+// on FIFO overflow
+#define APBDEV_KBC_CONTROL_0_FIFO_OVF_INT_EN_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_CONTROL_0_FIFO_OVF_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_CONTROL_0_FIFO_OVF_INT_EN_SHIFT)
+#define APBDEV_KBC_CONTROL_0_FIFO_OVF_INT_EN_RANGE                      2:2
+#define APBDEV_KBC_CONTROL_0_FIFO_OVF_INT_EN_WOFFSET                    0x0
+#define APBDEV_KBC_CONTROL_0_FIFO_OVF_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_FIFO_OVF_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_CONTROL_0_FIFO_OVF_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_FIFO_OVF_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FIFO threshold count interrupt enable. Setting this bit will enable interrupt
+// when FIFO occupancy reaches/crosses the value specified in FIFO_TH_CNT
+// 0 Disable FIFO overflow interrupt
+// 1 Enable FIFO overflow interrupt
+#define APBDEV_KBC_CONTROL_0_FIFO_CNT_INT_EN_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_CONTROL_0_FIFO_CNT_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_CONTROL_0_FIFO_CNT_INT_EN_SHIFT)
+#define APBDEV_KBC_CONTROL_0_FIFO_CNT_INT_EN_RANGE                      3:3
+#define APBDEV_KBC_CONTROL_0_FIFO_CNT_INT_EN_WOFFSET                    0x0
+#define APBDEV_KBC_CONTROL_0_FIFO_CNT_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_FIFO_CNT_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_CONTROL_0_FIFO_CNT_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_FIFO_CNT_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Debounce count. This value sets the debounce FSM associated with each KBC 
+// input pin evaluate the input transitions
+// 0 = No debounce
+// N = N KBC clocks
+#define APBDEV_KBC_CONTROL_0_DBC_CNT_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_CONTROL_0_DBC_CNT_FIELD                      (_MK_MASK_CONST(0x3ff) << APBDEV_KBC_CONTROL_0_DBC_CNT_SHIFT)
+#define APBDEV_KBC_CONTROL_0_DBC_CNT_RANGE                      13:4
+#define APBDEV_KBC_CONTROL_0_DBC_CNT_WOFFSET                    0x0
+#define APBDEV_KBC_CONTROL_0_DBC_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_DBC_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x3ff)
+#define APBDEV_KBC_CONTROL_0_DBC_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_DBC_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FIFO threshold count. Keeps the threshold FIFO ocuupancy count. If FIFO 
+// reaches/crosses that count an optional interrupt will be raised. Should
+// not be programmed as 0
+// N = Threshold occupancy count is N
+#define APBDEV_KBC_CONTROL_0_FIFO_TH_CNT_SHIFT                  _MK_SHIFT_CONST(14)
+#define APBDEV_KBC_CONTROL_0_FIFO_TH_CNT_FIELD                  (_MK_MASK_CONST(0xf) << APBDEV_KBC_CONTROL_0_FIFO_TH_CNT_SHIFT)
+#define APBDEV_KBC_CONTROL_0_FIFO_TH_CNT_RANGE                  17:14
+#define APBDEV_KBC_CONTROL_0_FIFO_TH_CNT_WOFFSET                        0x0
+#define APBDEV_KBC_CONTROL_0_FIFO_TH_CNT_DEFAULT                        _MK_MASK_CONST(0x4)
+#define APBDEV_KBC_CONTROL_0_FIFO_TH_CNT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_CONTROL_0_FIFO_TH_CNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_FIFO_TH_CNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Selects the bahavior in case of FIFO overflow 
+// 0 = Drop the new detected key-presses
+// 1 = Overwrite the new detected key-presses
+#define APBDEV_KBC_CONTROL_0_FIFO_MODE_SHIFT                    _MK_SHIFT_CONST(18)
+#define APBDEV_KBC_CONTROL_0_FIFO_MODE_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_KBC_CONTROL_0_FIFO_MODE_SHIFT)
+#define APBDEV_KBC_CONTROL_0_FIFO_MODE_RANGE                    18:18
+#define APBDEV_KBC_CONTROL_0_FIFO_MODE_WOFFSET                  0x0
+#define APBDEV_KBC_CONTROL_0_FIFO_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_FIFO_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_CONTROL_0_FIFO_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_CONTROL_0_FIFO_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_INT_0  
+#define APBDEV_KBC_INT_0                        _MK_ADDR_CONST(0x4)
+#define APBDEV_KBC_INT_0_SECURE                         0x0
+#define APBDEV_KBC_INT_0_WORD_COUNT                     0x1
+#define APBDEV_KBC_INT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_INT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_INT_0_WRITE_MASK                     _MK_MASK_CONST(0x7)
+// Key-press intrrupt status. Writing '1' to this bit will clear the 
+// interrupt
+// 0 Key-press interrupt de-asserted
+// 1 Key-press interrupt asserted (read)
+// 1 Clear key-press interrupt (write)
+#define APBDEV_KBC_INT_0_KP_INT_STATUS_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_INT_0_KP_INT_STATUS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_KBC_INT_0_KP_INT_STATUS_SHIFT)
+#define APBDEV_KBC_INT_0_KP_INT_STATUS_RANGE                    0:0
+#define APBDEV_KBC_INT_0_KP_INT_STATUS_WOFFSET                  0x0
+#define APBDEV_KBC_INT_0_KP_INT_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_KP_INT_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_INT_0_KP_INT_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_KP_INT_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// FIFO overflow intrrupt status. Writing '1' to this bit will clear the 
+// interrupt
+// 0 FIFO overflow intrrupt de-asserted
+// 1 FIFO overflow intrrupt asserted (read)
+// 1 Clear FIFO overflow intrrupt (write)
+#define APBDEV_KBC_INT_0_FIFO_OVF_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_INT_0_FIFO_OVF_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_INT_0_FIFO_OVF_INT_STATUS_SHIFT)
+#define APBDEV_KBC_INT_0_FIFO_OVF_INT_STATUS_RANGE                      1:1
+#define APBDEV_KBC_INT_0_FIFO_OVF_INT_STATUS_WOFFSET                    0x0
+#define APBDEV_KBC_INT_0_FIFO_OVF_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_FIFO_OVF_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_INT_0_FIFO_OVF_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_FIFO_OVF_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FIFO thershold count intrrupt status. Writing '1' to this bit will clear the 
+// interrupt
+// 0 FIFO thershold count intrrupt de-asserted
+// 1 FIFO thershold count intrrupt asserted (read)
+// 1 Clear FIFO overflow intrrupt (write)
+#define APBDEV_KBC_INT_0_FIFO_CNT_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_INT_0_FIFO_CNT_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_INT_0_FIFO_CNT_INT_STATUS_SHIFT)
+#define APBDEV_KBC_INT_0_FIFO_CNT_INT_STATUS_RANGE                      2:2
+#define APBDEV_KBC_INT_0_FIFO_CNT_INT_STATUS_WOFFSET                    0x0
+#define APBDEV_KBC_INT_0_FIFO_CNT_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_FIFO_CNT_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_INT_0_FIFO_CNT_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_FIFO_CNT_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// KBC status. Read only. 
+// 0 = WuKP (Wake-up on key-press) interrupt mode
+// 1 = CP (Continuous polling) mode
+#define APBDEV_KBC_INT_0_KBC_ST_STATUS_SHIFT                    _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_INT_0_KBC_ST_STATUS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_KBC_INT_0_KBC_ST_STATUS_SHIFT)
+#define APBDEV_KBC_INT_0_KBC_ST_STATUS_RANGE                    3:3
+#define APBDEV_KBC_INT_0_KBC_ST_STATUS_WOFFSET                  0x0
+#define APBDEV_KBC_INT_0_KBC_ST_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_KBC_ST_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_INT_0_KBC_ST_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_KBC_ST_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// FIFO occupancy count. Shows the number of unread registers. Read only.
+#define APBDEV_KBC_INT_0_AV_FIFO_CNT_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_INT_0_AV_FIFO_CNT_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_INT_0_AV_FIFO_CNT_SHIFT)
+#define APBDEV_KBC_INT_0_AV_FIFO_CNT_RANGE                      7:4
+#define APBDEV_KBC_INT_0_AV_FIFO_CNT_WOFFSET                    0x0
+#define APBDEV_KBC_INT_0_AV_FIFO_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_AV_FIFO_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_INT_0_AV_FIFO_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INT_0_AV_FIFO_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_ROW_CFG0_0  
+#define APBDEV_KBC_ROW_CFG0_0                   _MK_ADDR_CONST(0x8)
+#define APBDEV_KBC_ROW_CFG0_0_SECURE                    0x0
+#define APBDEV_KBC_ROW_CFG0_0_WORD_COUNT                        0x1
+#define APBDEV_KBC_ROW_CFG0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_RESET_MASK                        _MK_MASK_CONST(0x3fffffff)
+#define APBDEV_KBC_ROW_CFG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_READ_MASK                         _MK_MASK_CONST(0x3fffffff)
+#define APBDEV_KBC_ROW_CFG0_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffffff)
+// Indicates whether GPIO pin# 0 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 0 in column configuration
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_EN_RANGE                       0:0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_EN_WOFFSET                     0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 0 to row number. Valid only if GPIO_0_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_NUM_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_NUM_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_NUM_RANGE                      4:1
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_0_ROW_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 1 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 1 in column configuration
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_EN_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_EN_RANGE                       5:5
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_EN_WOFFSET                     0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 1 to row number. Valid only if GPIO_1_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_NUM_SHIFT                      _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_NUM_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_NUM_RANGE                      9:6
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_1_ROW_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 2 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 2 in column configuration
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_EN_SHIFT                       _MK_SHIFT_CONST(10)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_EN_RANGE                       10:10
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_EN_WOFFSET                     0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 2 to row number. Valid only if GPIO_2_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_NUM_SHIFT                      _MK_SHIFT_CONST(11)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_NUM_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_NUM_RANGE                      14:11
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_2_ROW_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 3 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 3 in column configuration
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_EN_SHIFT                       _MK_SHIFT_CONST(15)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_EN_RANGE                       15:15
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_EN_WOFFSET                     0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 3 to row number. Valid only if GPIO_3_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_NUM_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_NUM_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_NUM_RANGE                      19:16
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_3_ROW_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 4 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 4 in column configuration
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_EN_SHIFT                       _MK_SHIFT_CONST(20)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_EN_RANGE                       20:20
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_EN_WOFFSET                     0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 4 to row number. Valid only if GPIO_4_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_NUM_SHIFT                      _MK_SHIFT_CONST(21)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_NUM_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_NUM_RANGE                      24:21
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_4_ROW_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 5 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 5 in column configuration
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_EN_SHIFT                       _MK_SHIFT_CONST(25)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_EN_RANGE                       25:25
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_EN_WOFFSET                     0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 5 to row number. Valid only if GPIO_5_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_NUM_SHIFT                      _MK_SHIFT_CONST(26)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_NUM_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_NUM_RANGE                      29:26
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG0_0_GPIO_5_ROW_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_ROW_CFG1_0  
+#define APBDEV_KBC_ROW_CFG1_0                   _MK_ADDR_CONST(0xc)
+#define APBDEV_KBC_ROW_CFG1_0_SECURE                    0x0
+#define APBDEV_KBC_ROW_CFG1_0_WORD_COUNT                        0x1
+#define APBDEV_KBC_ROW_CFG1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_RESET_MASK                        _MK_MASK_CONST(0x3fffffff)
+#define APBDEV_KBC_ROW_CFG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_READ_MASK                         _MK_MASK_CONST(0x3fffffff)
+#define APBDEV_KBC_ROW_CFG1_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffffff)
+// Indicates whether GPIO pin# 6 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 6 in column configuration
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_EN_RANGE                       0:0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_EN_WOFFSET                     0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 6 to row number. Valid only if GPIO_6_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_NUM_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_NUM_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_NUM_RANGE                      4:1
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_6_ROW_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 7 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 7 in column configuration
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_EN_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_EN_RANGE                       5:5
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_EN_WOFFSET                     0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 7 to row number. Valid only if GPIO_7_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_NUM_SHIFT                      _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_NUM_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_NUM_RANGE                      9:6
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_7_ROW_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 8 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 8 in column configuration
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_EN_SHIFT                       _MK_SHIFT_CONST(10)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_EN_RANGE                       10:10
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_EN_WOFFSET                     0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 8 to row number. Valid only if GPIO_8_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_NUM_SHIFT                      _MK_SHIFT_CONST(11)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_NUM_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_NUM_RANGE                      14:11
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_8_ROW_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 9 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 9 in column configuration
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_EN_SHIFT                       _MK_SHIFT_CONST(15)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_EN_RANGE                       15:15
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_EN_WOFFSET                     0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 9 to row number. Valid only if GPIO_9_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_NUM_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_NUM_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_NUM_RANGE                      19:16
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_9_ROW_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 10 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 10 in column configuration
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_EN_SHIFT                      _MK_SHIFT_CONST(20)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_EN_RANGE                      20:20
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 10 to row number. Valid only if GPIO_10_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_NUM_RANGE                     24:21
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_10_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 11 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 11 in column configuration
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_EN_SHIFT                      _MK_SHIFT_CONST(25)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_EN_RANGE                      25:25
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 11 to row number. Valid only if GPIO_11_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(26)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_NUM_RANGE                     29:26
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG1_0_GPIO_11_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_ROW_CFG2_0  
+#define APBDEV_KBC_ROW_CFG2_0                   _MK_ADDR_CONST(0x10)
+#define APBDEV_KBC_ROW_CFG2_0_SECURE                    0x0
+#define APBDEV_KBC_ROW_CFG2_0_WORD_COUNT                        0x1
+#define APBDEV_KBC_ROW_CFG2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_RESET_MASK                        _MK_MASK_CONST(0x3fffffff)
+#define APBDEV_KBC_ROW_CFG2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_READ_MASK                         _MK_MASK_CONST(0x3fffffff)
+#define APBDEV_KBC_ROW_CFG2_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffffff)
+// Indicates whether GPIO pin# 12 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 12 in column configuration
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_EN_RANGE                      0:0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 12 to row number. Valid only if GPIO_12_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_NUM_RANGE                     4:1
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_12_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 13 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 13 in column configuration
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_EN_SHIFT                      _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_EN_RANGE                      5:5
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 13 to row number. Valid only if GPIO_13_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_NUM_RANGE                     9:6
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_13_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 14 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 14 in column configuration
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_EN_SHIFT                      _MK_SHIFT_CONST(10)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_EN_RANGE                      10:10
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 14 to row number. Valid only if GPIO_14_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(11)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_NUM_RANGE                     14:11
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_14_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 15 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 15 in column configuration
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_EN_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_EN_RANGE                      15:15
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 15 to row number. Valid only if GPIO_15_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_NUM_RANGE                     19:16
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_15_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 16 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 16 in column configuration
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_EN_SHIFT                      _MK_SHIFT_CONST(20)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_EN_RANGE                      20:20
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 16 to row number. Valid only if GPIO_16_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_NUM_RANGE                     24:21
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_16_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 17 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 17 in column configuration
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_EN_SHIFT                      _MK_SHIFT_CONST(25)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_EN_RANGE                      25:25
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 17 to row number. Valid only if GPIO_17_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(26)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_NUM_RANGE                     29:26
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG2_0_GPIO_17_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_ROW_CFG3_0  
+#define APBDEV_KBC_ROW_CFG3_0                   _MK_ADDR_CONST(0x14)
+#define APBDEV_KBC_ROW_CFG3_0_SECURE                    0x0
+#define APBDEV_KBC_ROW_CFG3_0_WORD_COUNT                        0x1
+#define APBDEV_KBC_ROW_CFG3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_RESET_MASK                        _MK_MASK_CONST(0x3fffffff)
+#define APBDEV_KBC_ROW_CFG3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_READ_MASK                         _MK_MASK_CONST(0x3fffffff)
+#define APBDEV_KBC_ROW_CFG3_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffffff)
+// Indicates whether GPIO pin# 18 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 18 in column configuration
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_EN_RANGE                      0:0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 18 to row number. Valid only if GPIO_18_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_NUM_RANGE                     4:1
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_18_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 19 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 19 in column configuration
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_EN_SHIFT                      _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_EN_RANGE                      5:5
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 19 to row number. Valid only if GPIO_19_ROW_EN is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_NUM_RANGE                     9:6
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_19_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 20 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 20 in column configuration
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_EN_SHIFT                      _MK_SHIFT_CONST(10)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_EN_RANGE                      10:10
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 20 to row number. Valid only if GPIO_20 is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(11)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_NUM_RANGE                     14:11
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_20_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 21 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 21 in column configuration
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_EN_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_EN_RANGE                      15:15
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 21 to row number. Valid only if GPIO_21 is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_NUM_RANGE                     19:16
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_21_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 22 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 22 in column configuration
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_EN_SHIFT                      _MK_SHIFT_CONST(20)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_EN_RANGE                      20:20
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 22 to row number. Valid only if GPIO_21 is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_NUM_RANGE                     24:21
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_22_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 23 is mapped to any row of keypad matrix. This bit 
+// overrides any setting done for pin# 23 in column configuration
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_EN_SHIFT                      _MK_SHIFT_CONST(25)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_EN_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_EN_RANGE                      25:25
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_EN_WOFFSET                    0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 23 to row number. Valid only if GPIO_21 is set. 
+// Indicates row number
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_NUM_SHIFT                     _MK_SHIFT_CONST(26)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_NUM_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_NUM_SHIFT)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_NUM_RANGE                     29:26
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW_CFG3_0_GPIO_23_ROW_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_COL_CFG0_0  
+#define APBDEV_KBC_COL_CFG0_0                   _MK_ADDR_CONST(0x18)
+#define APBDEV_KBC_COL_CFG0_0_SECURE                    0x0
+#define APBDEV_KBC_COL_CFG0_0_WORD_COUNT                        0x1
+#define APBDEV_KBC_COL_CFG0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_KBC_COL_CFG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_KBC_COL_CFG0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Indicates whether GPIO pin# 0 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_0_ROW_EN in ROW_CFG0 is set to 0.
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_EN_RANGE                       0:0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_EN_WOFFSET                     0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 0 to column number. Valid only if GPIO_0_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_NUM_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_NUM_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_NUM_RANGE                      3:1
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_0_COL_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 1 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_1_ROW_EN in ROW_CFG0 is set to 0.
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_EN_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_EN_RANGE                       4:4
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_EN_WOFFSET                     0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 1 to column number. Valid only if GPIO_1_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_NUM_SHIFT                      _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_NUM_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_NUM_RANGE                      7:5
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_1_COL_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 2 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_2_ROW_EN in ROW_CFG0 is set to 0.
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_EN_SHIFT                       _MK_SHIFT_CONST(8)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_EN_RANGE                       8:8
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_EN_WOFFSET                     0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 2 to column number. Valid only if GPIO_2_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_NUM_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_NUM_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_NUM_RANGE                      11:9
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_2_COL_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 3 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_3_ROW_EN in ROW_CFG0 is set to 0.
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_EN_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_EN_RANGE                       12:12
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_EN_WOFFSET                     0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 3 to column number. Valid only if GPIO_3_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_NUM_SHIFT                      _MK_SHIFT_CONST(13)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_NUM_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_NUM_RANGE                      15:13
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_3_COL_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 4 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_4_ROW_EN in ROW_CFG0 is set to 0.
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_EN_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_EN_RANGE                       16:16
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_EN_WOFFSET                     0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 4 to column number. Valid only if GPIO_4_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_NUM_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_NUM_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_NUM_RANGE                      19:17
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_4_COL_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 5 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_5_ROW_EN in ROW_CFG0 is set to 0.
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_EN_SHIFT                       _MK_SHIFT_CONST(20)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_EN_RANGE                       20:20
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_EN_WOFFSET                     0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 5 to column number. Valid only if GPIO_5_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_NUM_SHIFT                      _MK_SHIFT_CONST(21)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_NUM_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_NUM_RANGE                      23:21
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_5_COL_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 6 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_6_ROW_EN in ROW_CFG1 is set to 0.
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_EN_SHIFT                       _MK_SHIFT_CONST(24)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_EN_RANGE                       24:24
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_EN_WOFFSET                     0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 6 to column number. Valid only if GPIO_6_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_NUM_SHIFT                      _MK_SHIFT_CONST(25)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_NUM_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_NUM_RANGE                      27:25
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_6_COL_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 7 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_7_ROW_EN in ROW_CFG1 is set to 0.
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_EN_SHIFT                       _MK_SHIFT_CONST(28)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_EN_RANGE                       28:28
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_EN_WOFFSET                     0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 7 to column number. Valid only if GPIO_7_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_NUM_SHIFT                      _MK_SHIFT_CONST(29)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_NUM_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_NUM_RANGE                      31:29
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG0_0_GPIO_7_COL_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_COL_CFG1_0  
+#define APBDEV_KBC_COL_CFG1_0                   _MK_ADDR_CONST(0x1c)
+#define APBDEV_KBC_COL_CFG1_0_SECURE                    0x0
+#define APBDEV_KBC_COL_CFG1_0_WORD_COUNT                        0x1
+#define APBDEV_KBC_COL_CFG1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_KBC_COL_CFG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_KBC_COL_CFG1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Indicates whether GPIO pin# 8 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_8_ROW_EN in ROW_CFG1 is set to 0.
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_EN_RANGE                       0:0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_EN_WOFFSET                     0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 8 to column number. Valid only if GPIO_8_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_NUM_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_NUM_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_NUM_RANGE                      3:1
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_8_COL_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 9 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_9_ROW_EN in ROW_CFG1 is set to 0.
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_EN_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_EN_RANGE                       4:4
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_EN_WOFFSET                     0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_EN_NOT_MAPPED                  _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_EN_MAPPED                      _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 9 to column number. Valid only if GPIO_9_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_NUM_SHIFT                      _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_NUM_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_NUM_RANGE                      7:5
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_NUM_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_9_COL_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 10 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_10_ROW_EN in ROW_CFG1 is set to 0.
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_EN_RANGE                      8:8
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 10 to column number. Valid only if GPIO_10_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_NUM_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_NUM_RANGE                     11:9
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_10_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 11 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_11_ROW_EN in ROW_CFG1 is set to 0.
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_EN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_EN_RANGE                      12:12
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 11 to column number. Valid only if GPIO_11_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_NUM_SHIFT                     _MK_SHIFT_CONST(13)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_NUM_RANGE                     15:13
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_11_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 12 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_12_ROW_EN in ROW_CFG2 is set to 0.
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_EN_RANGE                      16:16
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 12 to column number. Valid only if GPIO_12_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_NUM_SHIFT                     _MK_SHIFT_CONST(17)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_NUM_RANGE                     19:17
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_12_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 13 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_13_ROW_EN in ROW_CFG2 is set to 0.
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_EN_SHIFT                      _MK_SHIFT_CONST(20)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_EN_RANGE                      20:20
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 13 to column number. Valid only if GPIO_13_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_NUM_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_NUM_RANGE                     23:21
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_13_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 14 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_14_ROW_EN in ROW_CFG2 is set to 0.
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_EN_SHIFT                      _MK_SHIFT_CONST(24)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_EN_RANGE                      24:24
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 14 to column number. Valid only if GPIO_14_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_NUM_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_NUM_RANGE                     27:25
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_14_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 15 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_15_ROW_EN in ROW_CFG2 is set to 0.
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_EN_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_EN_RANGE                      28:28
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 15 to column number. Valid only if GPIO_15_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_NUM_SHIFT                     _MK_SHIFT_CONST(29)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_NUM_RANGE                     31:29
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG1_0_GPIO_15_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_COL_CFG2_0  
+#define APBDEV_KBC_COL_CFG2_0                   _MK_ADDR_CONST(0x20)
+#define APBDEV_KBC_COL_CFG2_0_SECURE                    0x0
+#define APBDEV_KBC_COL_CFG2_0_WORD_COUNT                        0x1
+#define APBDEV_KBC_COL_CFG2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_KBC_COL_CFG2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_KBC_COL_CFG2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Indicates whether GPIO pin# 16 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_16_ROW_EN in ROW_CFG2 is set to 0.
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_EN_RANGE                      0:0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 16 to column number. Valid only if GPIO_16_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_NUM_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_NUM_RANGE                     3:1
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_16_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 17 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_17_ROW_EN in ROW_CFG2 is set to 0.
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_EN_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_EN_RANGE                      4:4
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 17 to column number. Valid only if GPIO_17_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_NUM_SHIFT                     _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_NUM_RANGE                     7:5
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_17_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 18 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_18_ROW_EN in ROW_CFG3 is set to 0.
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_EN_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_EN_RANGE                      8:8
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 18 to column number. Valid only if GPIO_18_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_NUM_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_NUM_RANGE                     11:9
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_18_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 19 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_19_ROW_EN in ROW_CFG3 is set to 0.
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_EN_SHIFT                      _MK_SHIFT_CONST(12)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_EN_RANGE                      12:12
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 19 to column number. Valid only if GPIO_19_COL_EN is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_NUM_SHIFT                     _MK_SHIFT_CONST(13)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_NUM_RANGE                     15:13
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_19_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 20 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_20 in ROW_CFG3 is set to 0.
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_EN_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_EN_RANGE                      16:16
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 20 to column number. Valid only if GPIO_20 is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_NUM_SHIFT                     _MK_SHIFT_CONST(17)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_NUM_RANGE                     19:17
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_20_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 21 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_21 in ROW_CFG3 is set to 0.
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_EN_SHIFT                      _MK_SHIFT_CONST(20)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_EN_RANGE                      20:20
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 21 to column number. Valid only if GPIO_21 is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_NUM_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_NUM_RANGE                     23:21
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_21_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 22 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_22 in ROW_CFG3 is set to 0.
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_EN_SHIFT                      _MK_SHIFT_CONST(24)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_EN_RANGE                      24:24
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 22 to column number. Valid only if GPIO_22 is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_NUM_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_NUM_RANGE                     27:25
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_22_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates whether GPIO pin# 23 is mapped to any column of keypad matrix. This bit 
+// should be set to '1' only when GPIO_22 in ROW_CFG3 is set to 0.
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_EN_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_EN_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_EN_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_EN_RANGE                      28:28
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_EN_WOFFSET                    0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_EN_NOT_MAPPED                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_EN_MAPPED                     _MK_ENUM_CONST(1)
+
+// Mapping of GPIO pin# 23 to column number. Valid only if GPIO_23 is set. 
+// Indicates row number
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_NUM_SHIFT                     _MK_SHIFT_CONST(29)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_NUM_FIELD                     (_MK_MASK_CONST(0x7) << APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_NUM_SHIFT)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_NUM_RANGE                     31:29
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_NUM_WOFFSET                   0x0
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_NUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_NUM_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_NUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_COL_CFG2_0_GPIO_23_COL_NUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_TO_CNT_0  
+#define APBDEV_KBC_TO_CNT_0                     _MK_ADDR_CONST(0x24)
+#define APBDEV_KBC_TO_CNT_0_SECURE                      0x0
+#define APBDEV_KBC_TO_CNT_0_WORD_COUNT                  0x1
+#define APBDEV_KBC_TO_CNT_0_RESET_VAL                   _MK_MASK_CONST(0x27100)
+#define APBDEV_KBC_TO_CNT_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
+#define APBDEV_KBC_TO_CNT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_TO_CNT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_TO_CNT_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
+#define APBDEV_KBC_TO_CNT_0_WRITE_MASK                  _MK_MASK_CONST(0xfffff)
+// Time-out count value. The default value is 5 seconds. The value should be  
+// calculated for a 32 KHz clock.
+#define APBDEV_KBC_TO_CNT_0_TO_CNT_VAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_TO_CNT_0_TO_CNT_VAL_FIELD                    (_MK_MASK_CONST(0xfffff) << APBDEV_KBC_TO_CNT_0_TO_CNT_VAL_SHIFT)
+#define APBDEV_KBC_TO_CNT_0_TO_CNT_VAL_RANGE                    19:0
+#define APBDEV_KBC_TO_CNT_0_TO_CNT_VAL_WOFFSET                  0x0
+#define APBDEV_KBC_TO_CNT_0_TO_CNT_VAL_DEFAULT                  _MK_MASK_CONST(0x27100)
+#define APBDEV_KBC_TO_CNT_0_TO_CNT_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0xfffff)
+#define APBDEV_KBC_TO_CNT_0_TO_CNT_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_TO_CNT_0_TO_CNT_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_INIT_DLY_0  
+#define APBDEV_KBC_INIT_DLY_0                   _MK_ADDR_CONST(0x28)
+#define APBDEV_KBC_INIT_DLY_0_SECURE                    0x0
+#define APBDEV_KBC_INIT_DLY_0_WORD_COUNT                        0x1
+#define APBDEV_KBC_INIT_DLY_0_RESET_VAL                         _MK_MASK_CONST(0x400)
+#define APBDEV_KBC_INIT_DLY_0_RESET_MASK                        _MK_MASK_CONST(0xfffff)
+#define APBDEV_KBC_INIT_DLY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INIT_DLY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INIT_DLY_0_READ_MASK                         _MK_MASK_CONST(0xfffff)
+#define APBDEV_KBC_INIT_DLY_0_WRITE_MASK                        _MK_MASK_CONST(0xfffff)
+// Initial delay value. The default value is 32.25 milliseconds. The value should be  
+// calculated for a 32 KHz clock.
+#define APBDEV_KBC_INIT_DLY_0_INIT_DLY_VAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_INIT_DLY_0_INIT_DLY_VAL_FIELD                        (_MK_MASK_CONST(0xfffff) << APBDEV_KBC_INIT_DLY_0_INIT_DLY_VAL_SHIFT)
+#define APBDEV_KBC_INIT_DLY_0_INIT_DLY_VAL_RANGE                        19:0
+#define APBDEV_KBC_INIT_DLY_0_INIT_DLY_VAL_WOFFSET                      0x0
+#define APBDEV_KBC_INIT_DLY_0_INIT_DLY_VAL_DEFAULT                      _MK_MASK_CONST(0x400)
+#define APBDEV_KBC_INIT_DLY_0_INIT_DLY_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0xfffff)
+#define APBDEV_KBC_INIT_DLY_0_INIT_DLY_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_INIT_DLY_0_INIT_DLY_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_RPT_DLY_0  
+#define APBDEV_KBC_RPT_DLY_0                    _MK_ADDR_CONST(0x2c)
+#define APBDEV_KBC_RPT_DLY_0_SECURE                     0x0
+#define APBDEV_KBC_RPT_DLY_0_WORD_COUNT                         0x1
+#define APBDEV_KBC_RPT_DLY_0_RESET_VAL                  _MK_MASK_CONST(0x400)
+#define APBDEV_KBC_RPT_DLY_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
+#define APBDEV_KBC_RPT_DLY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_RPT_DLY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_RPT_DLY_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
+#define APBDEV_KBC_RPT_DLY_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff)
+//  delay value. The default value is 32.25 milliseconds. The value should be  
+// calculated for a 32 KHz clock.
+#define APBDEV_KBC_RPT_DLY_0_RPT_DLY_VAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_RPT_DLY_0_RPT_DLY_VAL_FIELD                  (_MK_MASK_CONST(0xfffff) << APBDEV_KBC_RPT_DLY_0_RPT_DLY_VAL_SHIFT)
+#define APBDEV_KBC_RPT_DLY_0_RPT_DLY_VAL_RANGE                  19:0
+#define APBDEV_KBC_RPT_DLY_0_RPT_DLY_VAL_WOFFSET                        0x0
+#define APBDEV_KBC_RPT_DLY_0_RPT_DLY_VAL_DEFAULT                        _MK_MASK_CONST(0x400)
+#define APBDEV_KBC_RPT_DLY_0_RPT_DLY_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
+#define APBDEV_KBC_RPT_DLY_0_RPT_DLY_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_RPT_DLY_0_RPT_DLY_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_KP_ENT0_0  
+#define APBDEV_KBC_KP_ENT0_0                    _MK_ADDR_CONST(0x30)
+#define APBDEV_KBC_KP_ENT0_0_SECURE                     0x0
+#define APBDEV_KBC_KP_ENT0_0_WORD_COUNT                         0x1
+#define APBDEV_KBC_KP_ENT0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_KBC_KP_ENT0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_KBC_KP_ENT0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Column number for first key.  
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT0_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT0_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT0_RANGE                      2:0
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT0_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT0_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Row number for first key.  
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT0_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT0_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT0_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT0_RANGE                      6:3
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT0_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT0_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether first entry is valid or not
+// 0x0 Entry not valid  
+// 0x1 Valid entry  
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT0_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT0_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT0_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT0_RANGE                  7:7
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT0_WOFFSET                        0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Column number for second key.  
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT1_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT1_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT1_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT1_RANGE                      10:8
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT1_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT1_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Row number for second key.  
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT1_SHIFT                      _MK_SHIFT_CONST(11)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT1_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT1_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT1_RANGE                      14:11
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT1_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT1_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether second entry is valid or not
+// 0x0 Entry not valid  
+// 0x1 Valid entry  
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT1_SHIFT                  _MK_SHIFT_CONST(15)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT1_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT1_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT1_RANGE                  15:15
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT1_WOFFSET                        0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Column number for third key.  
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT2_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT2_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT2_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT2_RANGE                      18:16
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT2_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT2_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Row number for third key.  
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT2_SHIFT                      _MK_SHIFT_CONST(19)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT2_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT2_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT2_RANGE                      22:19
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT2_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT2_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether third entry is valid or not
+// 0x0 Entry not valid  
+// 0x1 Valid entry  
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT2_SHIFT                  _MK_SHIFT_CONST(23)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT2_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT2_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT2_RANGE                  23:23
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT2_WOFFSET                        0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Column number for fourth key.  
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT3_SHIFT                      _MK_SHIFT_CONST(24)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT3_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT3_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT3_RANGE                      26:24
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT3_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT3_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_COL_NUM_ENT3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Row number for fourth key.  
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT3_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT3_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT3_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT3_RANGE                      30:27
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT3_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT3_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_ROW_NUM_ENT3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether fourth entry is valid or not
+// 0x0 Entry not valid  
+// 0x1 Valid entry  
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT3_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT3_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT3_SHIFT)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT3_RANGE                  31:31
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT3_WOFFSET                        0x0
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT0_0_KP_NEW_ENT3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_KP_ENT1_0  
+#define APBDEV_KBC_KP_ENT1_0                    _MK_ADDR_CONST(0x34)
+#define APBDEV_KBC_KP_ENT1_0_SECURE                     0x0
+#define APBDEV_KBC_KP_ENT1_0_WORD_COUNT                         0x1
+#define APBDEV_KBC_KP_ENT1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_KBC_KP_ENT1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_KBC_KP_ENT1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Column number for fifth key.  
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT4_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT4_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT4_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT4_RANGE                      2:0
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT4_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT4_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Row number for fifth key.  
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT4_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT4_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT4_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT4_RANGE                      6:3
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT4_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT4_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether fifth entry is valid or not
+// 0x0 Entry not valid  
+// 0x1 Valid entry  
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT4_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT4_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT4_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT4_RANGE                  7:7
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT4_WOFFSET                        0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Column number for sixth key.  
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT5_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT5_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT5_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT5_RANGE                      10:8
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT5_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT5_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Row number for sixth key.  
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT5_SHIFT                      _MK_SHIFT_CONST(11)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT5_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT5_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT5_RANGE                      14:11
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT5_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT5_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether sixth entry is valid or not
+// 0x0 Entry not valid  
+// 0x1 Valid entry  
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT5_SHIFT                  _MK_SHIFT_CONST(15)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT5_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT5_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT5_RANGE                  15:15
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT5_WOFFSET                        0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Column number for seventh key.  
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT6_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT6_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT6_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT6_RANGE                      18:16
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT6_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT6_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Row number for seventh key.  
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT6_SHIFT                      _MK_SHIFT_CONST(19)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT6_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT6_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT6_RANGE                      22:19
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT6_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT6_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether seventh entry is valid or not
+// 0x0 Entry not valid  
+// 0x1 Valid entry
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT6_SHIFT                  _MK_SHIFT_CONST(23)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT6_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT6_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT6_RANGE                  23:23
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT6_WOFFSET                        0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Column number for eight key.  
+// 0x0 = Column number 0
+// 0x7 = Column number 7
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT7_SHIFT                      _MK_SHIFT_CONST(24)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT7_FIELD                      (_MK_MASK_CONST(0x7) << APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT7_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT7_RANGE                      26:24
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT7_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT7_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_COL_NUM_ENT7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Row number for eight key.  
+// 0x0 = Row number 0
+// 0xF = Row number 15
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT7_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT7_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT7_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT7_RANGE                      30:27
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT7_WOFFSET                    0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT7_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_ROW_NUM_ENT7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Indicates whether eight entry is valid or not
+// 0x0 Entry not valid  
+// 0x1 Valid entry            
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT7_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT7_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT7_SHIFT)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT7_RANGE                  31:31
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT7_WOFFSET                        0x0
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_KP_ENT1_0_KP_NEW_ENT7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_KBC_ROW0_MASK_0  
+#define APBDEV_KBC_ROW0_MASK_0                  _MK_ADDR_CONST(0x38)
+#define APBDEV_KBC_ROW0_MASK_0_SECURE                   0x0
+#define APBDEV_KBC_ROW0_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_KBC_ROW0_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW0_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW0_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// Disable row0 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL0_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL0_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL0_MASK_ENABLE_RANGE                  0:0
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL0_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL0_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL0_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL0_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL0_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL0_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL0_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row0 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL1_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL1_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL1_MASK_ENABLE_RANGE                  1:1
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL1_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL1_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL1_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL1_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL1_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL1_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL1_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row0 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL2_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL2_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL2_MASK_ENABLE_RANGE                  2:2
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL2_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL2_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL2_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL2_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL2_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL2_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL2_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row0 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL3_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL3_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL3_MASK_ENABLE_RANGE                  3:3
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL3_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL3_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL3_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL3_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL3_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL3_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL3_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row0 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL4_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL4_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL4_MASK_ENABLE_RANGE                  4:4
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL4_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL4_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL4_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL4_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL4_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL4_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL4_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row0 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL5_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL5_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL5_MASK_ENABLE_RANGE                  5:5
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL5_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL5_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL5_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL5_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL5_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL5_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL5_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row0 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL6_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL6_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL6_MASK_ENABLE_RANGE                  6:6
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL6_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL6_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL6_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL6_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL6_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL6_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL6_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row0 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL7_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL7_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL7_MASK_ENABLE_RANGE                  7:7
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL7_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL7_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL7_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL7_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL7_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL7_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW0_MASK_0_KBC_ROW0_COL7_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW1_MASK_0  
+#define APBDEV_KBC_ROW1_MASK_0                  _MK_ADDR_CONST(0x3c)
+#define APBDEV_KBC_ROW1_MASK_0_SECURE                   0x0
+#define APBDEV_KBC_ROW1_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_KBC_ROW1_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW1_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW1_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// Disable row1 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL0_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL0_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL0_MASK_ENABLE_RANGE                  0:0
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL0_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL0_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL0_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL0_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL0_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL0_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL0_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row1 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL1_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL1_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL1_MASK_ENABLE_RANGE                  1:1
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL1_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL1_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL1_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL1_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL1_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL1_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL1_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row1 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL2_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL2_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL2_MASK_ENABLE_RANGE                  2:2
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL2_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL2_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL2_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL2_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL2_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL2_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL2_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row1 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL3_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL3_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL3_MASK_ENABLE_RANGE                  3:3
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL3_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL3_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL3_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL3_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL3_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL3_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL3_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row1 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL4_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL4_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL4_MASK_ENABLE_RANGE                  4:4
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL4_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL4_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL4_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL4_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL4_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL4_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL4_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row1 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL5_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL5_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL5_MASK_ENABLE_RANGE                  5:5
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL5_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL5_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL5_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL5_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL5_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL5_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL5_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row1 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL6_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL6_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL6_MASK_ENABLE_RANGE                  6:6
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL6_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL6_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL6_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL6_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL6_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL6_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL6_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row1 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL7_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL7_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL7_MASK_ENABLE_RANGE                  7:7
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL7_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL7_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL7_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL7_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL7_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL7_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW1_MASK_0_KBC_ROW1_COL7_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW2_MASK_0  
+#define APBDEV_KBC_ROW2_MASK_0                  _MK_ADDR_CONST(0x40)
+#define APBDEV_KBC_ROW2_MASK_0_SECURE                   0x0
+#define APBDEV_KBC_ROW2_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_KBC_ROW2_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW2_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW2_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// Disable row2 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL0_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL0_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL0_MASK_ENABLE_RANGE                  0:0
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL0_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL0_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL0_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL0_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL0_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL0_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL0_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row2 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL1_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL1_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL1_MASK_ENABLE_RANGE                  1:1
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL1_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL1_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL1_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL1_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL1_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL1_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL1_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row2 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL2_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL2_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL2_MASK_ENABLE_RANGE                  2:2
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL2_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL2_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL2_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL2_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL2_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL2_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL2_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row2 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL3_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL3_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL3_MASK_ENABLE_RANGE                  3:3
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL3_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL3_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL3_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL3_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL3_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL3_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL3_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row2 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL4_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL4_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL4_MASK_ENABLE_RANGE                  4:4
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL4_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL4_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL4_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL4_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL4_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL4_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL4_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row2 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL5_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL5_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL5_MASK_ENABLE_RANGE                  5:5
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL5_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL5_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL5_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL5_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL5_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL5_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL5_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row2 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL6_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL6_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL6_MASK_ENABLE_RANGE                  6:6
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL6_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL6_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL6_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL6_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL6_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL6_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL6_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row2 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL7_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL7_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL7_MASK_ENABLE_RANGE                  7:7
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL7_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL7_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL7_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL7_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL7_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL7_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW2_MASK_0_KBC_ROW2_COL7_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW3_MASK_0  
+#define APBDEV_KBC_ROW3_MASK_0                  _MK_ADDR_CONST(0x44)
+#define APBDEV_KBC_ROW3_MASK_0_SECURE                   0x0
+#define APBDEV_KBC_ROW3_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_KBC_ROW3_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW3_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW3_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// Disable row3 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL0_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL0_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL0_MASK_ENABLE_RANGE                  0:0
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL0_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL0_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL0_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL0_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL0_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL0_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL0_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row3 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL1_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL1_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL1_MASK_ENABLE_RANGE                  1:1
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL1_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL1_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL1_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL1_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL1_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL1_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL1_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row3 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL2_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL2_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL2_MASK_ENABLE_RANGE                  2:2
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL2_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL2_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL2_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL2_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL2_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL2_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL2_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row3 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL3_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL3_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL3_MASK_ENABLE_RANGE                  3:3
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL3_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL3_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL3_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL3_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL3_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL3_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL3_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row3 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL4_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL4_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL4_MASK_ENABLE_RANGE                  4:4
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL4_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL4_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL4_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL4_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL4_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL4_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL4_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row3 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL5_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL5_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL5_MASK_ENABLE_RANGE                  5:5
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL5_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL5_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL5_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL5_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL5_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL5_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL5_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row3 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL6_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL6_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL6_MASK_ENABLE_RANGE                  6:6
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL6_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL6_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL6_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL6_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL6_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL6_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL6_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row3 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL7_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL7_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL7_MASK_ENABLE_RANGE                  7:7
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL7_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL7_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL7_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL7_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL7_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL7_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW3_MASK_0_KBC_ROW3_COL7_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW4_MASK_0  
+#define APBDEV_KBC_ROW4_MASK_0                  _MK_ADDR_CONST(0x48)
+#define APBDEV_KBC_ROW4_MASK_0_SECURE                   0x0
+#define APBDEV_KBC_ROW4_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_KBC_ROW4_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW4_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW4_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// Disable row4 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL0_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL0_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL0_MASK_ENABLE_RANGE                  0:0
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL0_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL0_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL0_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL0_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL0_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL0_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL0_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row4 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL1_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL1_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL1_MASK_ENABLE_RANGE                  1:1
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL1_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL1_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL1_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL1_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL1_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL1_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL1_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row4 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL2_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL2_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL2_MASK_ENABLE_RANGE                  2:2
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL2_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL2_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL2_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL2_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL2_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL2_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL2_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row4 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL3_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL3_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL3_MASK_ENABLE_RANGE                  3:3
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL3_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL3_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL3_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL3_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL3_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL3_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL3_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row4 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL4_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL4_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL4_MASK_ENABLE_RANGE                  4:4
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL4_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL4_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL4_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL4_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL4_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL4_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL4_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row4 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL5_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL5_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL5_MASK_ENABLE_RANGE                  5:5
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL5_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL5_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL5_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL5_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL5_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL5_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL5_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row4 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL6_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL6_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL6_MASK_ENABLE_RANGE                  6:6
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL6_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL6_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL6_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL6_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL6_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL6_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL6_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row4 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL7_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL7_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL7_MASK_ENABLE_RANGE                  7:7
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL7_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL7_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL7_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL7_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL7_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL7_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW4_MASK_0_KBC_ROW4_COL7_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW5_MASK_0  
+#define APBDEV_KBC_ROW5_MASK_0                  _MK_ADDR_CONST(0x4c)
+#define APBDEV_KBC_ROW5_MASK_0_SECURE                   0x0
+#define APBDEV_KBC_ROW5_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_KBC_ROW5_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW5_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW5_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// Disable row5 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL0_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL0_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL0_MASK_ENABLE_RANGE                  0:0
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL0_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL0_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL0_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL0_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL0_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL0_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL0_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row5 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL1_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL1_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL1_MASK_ENABLE_RANGE                  1:1
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL1_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL1_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL1_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL1_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL1_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL1_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL1_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row5 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL2_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL2_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL2_MASK_ENABLE_RANGE                  2:2
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL2_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL2_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL2_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL2_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL2_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL2_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL2_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row5 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL3_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL3_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL3_MASK_ENABLE_RANGE                  3:3
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL3_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL3_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL3_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL3_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL3_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL3_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL3_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row5 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL4_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL4_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL4_MASK_ENABLE_RANGE                  4:4
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL4_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL4_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL4_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL4_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL4_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL4_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL4_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row5 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL5_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL5_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL5_MASK_ENABLE_RANGE                  5:5
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL5_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL5_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL5_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL5_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL5_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL5_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL5_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row5 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL6_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL6_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL6_MASK_ENABLE_RANGE                  6:6
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL6_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL6_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL6_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL6_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL6_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL6_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL6_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row5 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL7_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL7_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL7_MASK_ENABLE_RANGE                  7:7
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL7_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL7_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL7_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL7_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL7_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL7_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW5_MASK_0_KBC_ROW5_COL7_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW6_MASK_0  
+#define APBDEV_KBC_ROW6_MASK_0                  _MK_ADDR_CONST(0x50)
+#define APBDEV_KBC_ROW6_MASK_0_SECURE                   0x0
+#define APBDEV_KBC_ROW6_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_KBC_ROW6_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW6_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW6_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// Disable row6 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL0_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL0_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL0_MASK_ENABLE_RANGE                  0:0
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL0_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL0_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL0_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL0_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL0_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL0_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL0_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row6 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL1_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL1_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL1_MASK_ENABLE_RANGE                  1:1
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL1_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL1_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL1_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL1_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL1_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL1_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL1_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row6 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL2_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL2_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL2_MASK_ENABLE_RANGE                  2:2
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL2_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL2_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL2_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL2_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL2_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL2_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL2_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row6 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL3_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL3_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL3_MASK_ENABLE_RANGE                  3:3
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL3_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL3_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL3_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL3_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL3_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL3_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL3_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row6 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL4_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL4_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL4_MASK_ENABLE_RANGE                  4:4
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL4_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL4_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL4_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL4_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL4_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL4_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL4_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row6 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL5_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL5_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL5_MASK_ENABLE_RANGE                  5:5
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL5_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL5_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL5_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL5_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL5_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL5_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL5_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row6 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL6_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL6_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL6_MASK_ENABLE_RANGE                  6:6
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL6_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL6_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL6_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL6_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL6_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL6_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL6_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row6 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL7_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL7_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL7_MASK_ENABLE_RANGE                  7:7
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL7_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL7_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL7_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL7_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL7_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL7_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW6_MASK_0_KBC_ROW6_COL7_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW7_MASK_0  
+#define APBDEV_KBC_ROW7_MASK_0                  _MK_ADDR_CONST(0x54)
+#define APBDEV_KBC_ROW7_MASK_0_SECURE                   0x0
+#define APBDEV_KBC_ROW7_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_KBC_ROW7_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW7_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW7_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// Disable row7 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL0_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL0_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL0_MASK_ENABLE_RANGE                  0:0
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL0_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL0_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL0_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL0_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL0_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL0_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL0_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row7 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL1_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL1_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL1_MASK_ENABLE_RANGE                  1:1
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL1_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL1_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL1_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL1_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL1_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL1_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL1_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row7 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL2_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL2_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL2_MASK_ENABLE_RANGE                  2:2
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL2_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL2_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL2_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL2_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL2_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL2_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL2_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row7 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL3_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL3_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL3_MASK_ENABLE_RANGE                  3:3
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL3_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL3_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL3_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL3_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL3_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL3_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL3_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row7 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL4_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL4_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL4_MASK_ENABLE_RANGE                  4:4
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL4_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL4_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL4_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL4_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL4_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL4_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL4_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row7 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL5_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL5_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL5_MASK_ENABLE_RANGE                  5:5
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL5_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL5_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL5_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL5_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL5_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL5_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL5_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row7 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL6_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL6_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL6_MASK_ENABLE_RANGE                  6:6
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL6_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL6_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL6_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL6_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL6_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL6_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL6_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row7 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL7_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL7_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL7_MASK_ENABLE_RANGE                  7:7
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL7_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL7_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL7_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL7_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL7_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL7_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW7_MASK_0_KBC_ROW7_COL7_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW8_MASK_0  
+#define APBDEV_KBC_ROW8_MASK_0                  _MK_ADDR_CONST(0x58)
+#define APBDEV_KBC_ROW8_MASK_0_SECURE                   0x0
+#define APBDEV_KBC_ROW8_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_KBC_ROW8_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW8_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW8_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// Disable row8 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL0_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL0_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL0_MASK_ENABLE_RANGE                  0:0
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL0_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL0_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL0_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL0_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL0_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL0_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL0_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row8 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL1_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL1_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL1_MASK_ENABLE_RANGE                  1:1
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL1_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL1_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL1_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL1_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL1_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL1_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL1_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row8 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL2_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL2_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL2_MASK_ENABLE_RANGE                  2:2
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL2_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL2_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL2_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL2_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL2_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL2_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL2_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row8 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL3_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL3_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL3_MASK_ENABLE_RANGE                  3:3
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL3_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL3_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL3_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL3_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL3_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL3_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL3_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row8 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL4_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL4_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL4_MASK_ENABLE_RANGE                  4:4
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL4_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL4_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL4_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL4_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL4_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL4_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL4_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row8 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL5_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL5_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL5_MASK_ENABLE_RANGE                  5:5
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL5_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL5_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL5_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL5_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL5_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL5_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL5_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row8 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL6_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL6_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL6_MASK_ENABLE_RANGE                  6:6
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL6_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL6_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL6_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL6_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL6_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL6_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL6_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row8 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL7_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL7_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL7_MASK_ENABLE_RANGE                  7:7
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL7_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL7_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL7_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL7_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL7_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL7_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW8_MASK_0_KBC_ROW8_COL7_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW9_MASK_0  
+#define APBDEV_KBC_ROW9_MASK_0                  _MK_ADDR_CONST(0x5c)
+#define APBDEV_KBC_ROW9_MASK_0_SECURE                   0x0
+#define APBDEV_KBC_ROW9_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_KBC_ROW9_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW9_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW9_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// Disable row9 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL0_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL0_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL0_MASK_ENABLE_RANGE                  0:0
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL0_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL0_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL0_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL0_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL0_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL0_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL0_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row9 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL1_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL1_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL1_MASK_ENABLE_RANGE                  1:1
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL1_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL1_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL1_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL1_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL1_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL1_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL1_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row9 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL2_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL2_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL2_MASK_ENABLE_RANGE                  2:2
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL2_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL2_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL2_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL2_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL2_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL2_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL2_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row9 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL3_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL3_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL3_MASK_ENABLE_RANGE                  3:3
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL3_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL3_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL3_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL3_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL3_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL3_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL3_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row9 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL4_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL4_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL4_MASK_ENABLE_RANGE                  4:4
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL4_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL4_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL4_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL4_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL4_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL4_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL4_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row9 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL5_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL5_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL5_MASK_ENABLE_RANGE                  5:5
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL5_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL5_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL5_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL5_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL5_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL5_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL5_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row9 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL6_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL6_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL6_MASK_ENABLE_RANGE                  6:6
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL6_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL6_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL6_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL6_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL6_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL6_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL6_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+// Disable row9 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL7_MASK_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL7_MASK_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL7_MASK_ENABLE_RANGE                  7:7
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL7_MASK_ENABLE_WOFFSET                        0x0
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL7_MASK_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL7_MASK_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL7_MASK_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL7_MASK_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL7_MASK_ENABLE_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW9_MASK_0_KBC_ROW9_COL7_MASK_ENABLE_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW10_MASK_0  
+#define APBDEV_KBC_ROW10_MASK_0                 _MK_ADDR_CONST(0x60)
+#define APBDEV_KBC_ROW10_MASK_0_SECURE                  0x0
+#define APBDEV_KBC_ROW10_MASK_0_WORD_COUNT                      0x1
+#define APBDEV_KBC_ROW10_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW10_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW10_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+// Disable row10 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL0_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL0_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL0_MASK_ENABLE_RANGE                        0:0
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL0_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL0_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL0_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL0_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL0_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL0_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL0_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row10 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL1_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL1_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL1_MASK_ENABLE_RANGE                        1:1
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL1_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL1_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL1_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL1_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL1_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL1_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL1_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row10 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL2_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL2_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL2_MASK_ENABLE_RANGE                        2:2
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL2_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL2_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL2_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL2_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL2_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL2_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL2_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row10 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL3_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL3_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL3_MASK_ENABLE_RANGE                        3:3
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL3_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL3_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL3_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL3_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL3_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL3_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL3_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row10 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL4_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL4_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL4_MASK_ENABLE_RANGE                        4:4
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL4_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL4_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL4_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL4_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL4_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL4_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL4_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row10 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL5_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL5_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL5_MASK_ENABLE_RANGE                        5:5
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL5_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL5_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL5_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL5_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL5_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL5_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL5_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row10 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL6_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL6_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL6_MASK_ENABLE_RANGE                        6:6
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL6_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL6_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL6_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL6_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL6_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL6_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL6_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row10 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL7_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL7_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL7_MASK_ENABLE_RANGE                        7:7
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL7_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL7_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL7_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL7_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL7_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL7_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW10_MASK_0_KBC_ROW10_COL7_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW11_MASK_0  
+#define APBDEV_KBC_ROW11_MASK_0                 _MK_ADDR_CONST(0x64)
+#define APBDEV_KBC_ROW11_MASK_0_SECURE                  0x0
+#define APBDEV_KBC_ROW11_MASK_0_WORD_COUNT                      0x1
+#define APBDEV_KBC_ROW11_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW11_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW11_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+// Disable row11 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL0_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL0_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL0_MASK_ENABLE_RANGE                        0:0
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL0_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL0_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL0_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL0_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL0_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL0_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL0_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row11 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL1_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL1_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL1_MASK_ENABLE_RANGE                        1:1
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL1_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL1_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL1_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL1_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL1_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL1_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL1_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row11 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL2_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL2_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL2_MASK_ENABLE_RANGE                        2:2
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL2_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL2_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL2_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL2_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL2_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL2_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL2_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row11 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL3_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL3_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL3_MASK_ENABLE_RANGE                        3:3
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL3_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL3_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL3_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL3_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL3_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL3_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL3_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row11 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL4_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL4_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL4_MASK_ENABLE_RANGE                        4:4
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL4_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL4_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL4_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL4_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL4_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL4_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL4_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row11 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL5_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL5_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL5_MASK_ENABLE_RANGE                        5:5
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL5_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL5_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL5_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL5_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL5_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL5_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL5_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row11 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL6_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL6_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL6_MASK_ENABLE_RANGE                        6:6
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL6_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL6_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL6_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL6_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL6_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL6_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL6_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row11 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL7_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL7_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL7_MASK_ENABLE_RANGE                        7:7
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL7_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL7_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL7_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL7_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL7_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL7_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW11_MASK_0_KBC_ROW11_COL7_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW12_MASK_0  
+#define APBDEV_KBC_ROW12_MASK_0                 _MK_ADDR_CONST(0x68)
+#define APBDEV_KBC_ROW12_MASK_0_SECURE                  0x0
+#define APBDEV_KBC_ROW12_MASK_0_WORD_COUNT                      0x1
+#define APBDEV_KBC_ROW12_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW12_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW12_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+// Disable row12 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL0_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL0_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL0_MASK_ENABLE_RANGE                        0:0
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL0_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL0_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL0_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL0_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL0_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL0_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL0_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row12 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL1_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL1_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL1_MASK_ENABLE_RANGE                        1:1
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL1_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL1_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL1_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL1_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL1_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL1_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL1_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row12 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL2_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL2_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL2_MASK_ENABLE_RANGE                        2:2
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL2_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL2_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL2_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL2_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL2_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL2_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL2_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row12 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL3_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL3_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL3_MASK_ENABLE_RANGE                        3:3
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL3_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL3_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL3_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL3_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL3_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL3_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL3_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row12 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL4_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL4_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL4_MASK_ENABLE_RANGE                        4:4
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL4_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL4_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL4_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL4_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL4_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL4_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL4_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row12 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL5_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL5_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL5_MASK_ENABLE_RANGE                        5:5
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL5_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL5_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL5_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL5_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL5_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL5_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL5_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row12 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL6_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL6_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL6_MASK_ENABLE_RANGE                        6:6
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL6_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL6_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL6_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL6_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL6_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL6_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL6_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row12 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL7_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL7_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL7_MASK_ENABLE_RANGE                        7:7
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL7_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL7_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL7_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL7_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL7_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL7_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW12_MASK_0_KBC_ROW12_COL7_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW13_MASK_0  
+#define APBDEV_KBC_ROW13_MASK_0                 _MK_ADDR_CONST(0x6c)
+#define APBDEV_KBC_ROW13_MASK_0_SECURE                  0x0
+#define APBDEV_KBC_ROW13_MASK_0_WORD_COUNT                      0x1
+#define APBDEV_KBC_ROW13_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW13_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW13_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+// Disable row13 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL0_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL0_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL0_MASK_ENABLE_RANGE                        0:0
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL0_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL0_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL0_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL0_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL0_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL0_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL0_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row13 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL1_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL1_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL1_MASK_ENABLE_RANGE                        1:1
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL1_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL1_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL1_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL1_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL1_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL1_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL1_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row13 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL2_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL2_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL2_MASK_ENABLE_RANGE                        2:2
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL2_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL2_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL2_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL2_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL2_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL2_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL2_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row13 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL3_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL3_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL3_MASK_ENABLE_RANGE                        3:3
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL3_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL3_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL3_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL3_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL3_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL3_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL3_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row13 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL4_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL4_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL4_MASK_ENABLE_RANGE                        4:4
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL4_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL4_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL4_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL4_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL4_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL4_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL4_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row13 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL5_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL5_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL5_MASK_ENABLE_RANGE                        5:5
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL5_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL5_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL5_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL5_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL5_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL5_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL5_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row13 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL6_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL6_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL6_MASK_ENABLE_RANGE                        6:6
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL6_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL6_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL6_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL6_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL6_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL6_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL6_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row13 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL7_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL7_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL7_MASK_ENABLE_RANGE                        7:7
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL7_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL7_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL7_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL7_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL7_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL7_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW13_MASK_0_KBC_ROW13_COL7_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW14_MASK_0  
+#define APBDEV_KBC_ROW14_MASK_0                 _MK_ADDR_CONST(0x70)
+#define APBDEV_KBC_ROW14_MASK_0_SECURE                  0x0
+#define APBDEV_KBC_ROW14_MASK_0_WORD_COUNT                      0x1
+#define APBDEV_KBC_ROW14_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW14_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW14_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+// Disable row14 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL0_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL0_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL0_MASK_ENABLE_RANGE                        0:0
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL0_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL0_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL0_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL0_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL0_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL0_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL0_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row14 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL1_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL1_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL1_MASK_ENABLE_RANGE                        1:1
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL1_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL1_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL1_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL1_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL1_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL1_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL1_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row14 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL2_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL2_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL2_MASK_ENABLE_RANGE                        2:2
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL2_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL2_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL2_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL2_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL2_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL2_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL2_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row14 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL3_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL3_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL3_MASK_ENABLE_RANGE                        3:3
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL3_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL3_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL3_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL3_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL3_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL3_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL3_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row14 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL4_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL4_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL4_MASK_ENABLE_RANGE                        4:4
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL4_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL4_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL4_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL4_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL4_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL4_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL4_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row14 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL5_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL5_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL5_MASK_ENABLE_RANGE                        5:5
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL5_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL5_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL5_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL5_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL5_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL5_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL5_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row14 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL6_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL6_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL6_MASK_ENABLE_RANGE                        6:6
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL6_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL6_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL6_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL6_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL6_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL6_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL6_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row14 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL7_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL7_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL7_MASK_ENABLE_RANGE                        7:7
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL7_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL7_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL7_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL7_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL7_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL7_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW14_MASK_0_KBC_ROW14_COL7_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_KBC_ROW15_MASK_0  
+#define APBDEV_KBC_ROW15_MASK_0                 _MK_ADDR_CONST(0x74)
+#define APBDEV_KBC_ROW15_MASK_0_SECURE                  0x0
+#define APBDEV_KBC_ROW15_MASK_0_WORD_COUNT                      0x1
+#define APBDEV_KBC_ROW15_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW15_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define APBDEV_KBC_ROW15_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+// Disable row15 col0 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL0_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL0_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL0_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL0_MASK_ENABLE_RANGE                        0:0
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL0_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL0_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL0_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL0_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL0_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL0_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL0_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row15 col1 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL1_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL1_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL1_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL1_MASK_ENABLE_RANGE                        1:1
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL1_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL1_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL1_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL1_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL1_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL1_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL1_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row15 col2 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL2_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL2_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL2_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL2_MASK_ENABLE_RANGE                        2:2
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL2_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL2_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL2_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL2_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL2_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL2_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL2_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row15 col3 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL3_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL3_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL3_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL3_MASK_ENABLE_RANGE                        3:3
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL3_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL3_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL3_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL3_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL3_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL3_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL3_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row15 col4 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL4_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL4_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL4_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL4_MASK_ENABLE_RANGE                        4:4
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL4_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL4_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL4_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL4_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL4_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL4_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL4_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row15 col5 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL5_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(5)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL5_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL5_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL5_MASK_ENABLE_RANGE                        5:5
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL5_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL5_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL5_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL5_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL5_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL5_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL5_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row15 col6 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL6_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(6)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL6_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL6_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL6_MASK_ENABLE_RANGE                        6:6
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL6_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL6_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL6_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL6_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL6_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL6_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL6_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+// Disable row15 col7 when system is in suspend/deep sleep mode
+// 1 Disable row/col pair
+// 0 Enable row/col pair
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL7_MASK_ENABLE_SHIFT                        _MK_SHIFT_CONST(7)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL7_MASK_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL7_MASK_ENABLE_SHIFT)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL7_MASK_ENABLE_RANGE                        7:7
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL7_MASK_ENABLE_WOFFSET                      0x0
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL7_MASK_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL7_MASK_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL7_MASK_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL7_MASK_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL7_MASK_ENABLE_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_KBC_ROW15_MASK_0_KBC_ROW15_COL7_MASK_ENABLE_DISABLE                      _MK_ENUM_CONST(1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBDEV_KBC_REGS(_op_) \
+_op_(APBDEV_KBC_CONTROL_0) \
+_op_(APBDEV_KBC_INT_0) \
+_op_(APBDEV_KBC_ROW_CFG0_0) \
+_op_(APBDEV_KBC_ROW_CFG1_0) \
+_op_(APBDEV_KBC_ROW_CFG2_0) \
+_op_(APBDEV_KBC_ROW_CFG3_0) \
+_op_(APBDEV_KBC_COL_CFG0_0) \
+_op_(APBDEV_KBC_COL_CFG1_0) \
+_op_(APBDEV_KBC_COL_CFG2_0) \
+_op_(APBDEV_KBC_TO_CNT_0) \
+_op_(APBDEV_KBC_INIT_DLY_0) \
+_op_(APBDEV_KBC_RPT_DLY_0) \
+_op_(APBDEV_KBC_KP_ENT0_0) \
+_op_(APBDEV_KBC_KP_ENT1_0) \
+_op_(APBDEV_KBC_ROW0_MASK_0) \
+_op_(APBDEV_KBC_ROW1_MASK_0) \
+_op_(APBDEV_KBC_ROW2_MASK_0) \
+_op_(APBDEV_KBC_ROW3_MASK_0) \
+_op_(APBDEV_KBC_ROW4_MASK_0) \
+_op_(APBDEV_KBC_ROW5_MASK_0) \
+_op_(APBDEV_KBC_ROW6_MASK_0) \
+_op_(APBDEV_KBC_ROW7_MASK_0) \
+_op_(APBDEV_KBC_ROW8_MASK_0) \
+_op_(APBDEV_KBC_ROW9_MASK_0) \
+_op_(APBDEV_KBC_ROW10_MASK_0) \
+_op_(APBDEV_KBC_ROW11_MASK_0) \
+_op_(APBDEV_KBC_ROW12_MASK_0) \
+_op_(APBDEV_KBC_ROW13_MASK_0) \
+_op_(APBDEV_KBC_ROW14_MASK_0) \
+_op_(APBDEV_KBC_ROW15_MASK_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDEV_KBC 0x00000000
+
+//
+// ARAPBDEV_KBC REGISTER BANKS
+//
+
+#define APBDEV_KBC0_FIRST_REG 0x0000 // APBDEV_KBC_CONTROL_0
+#define APBDEV_KBC0_LAST_REG 0x0074 // APBDEV_KBC_ROW15_MASK_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBDEV_KBC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arapbdma.h b/arch/arm/mach-tegra/nv/include/ap20/arapbdma.h
new file mode 100644
index 000000000000..2a475f7e9981
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arapbdma.h
@@ -0,0 +1,2666 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBDMA_H_INC_
+#define ___ARAPBDMA_H_INC_
+
+// Register APBDMA_COMMAND_0  
+#define APBDMA_COMMAND_0                        _MK_ADDR_CONST(0x0)
+#define APBDMA_COMMAND_0_SECURE                         0x0
+#define APBDMA_COMMAND_0_WORD_COUNT                     0x1
+#define APBDMA_COMMAND_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_RESET_MASK                     _MK_MASK_CONST(0x80000000)
+#define APBDMA_COMMAND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_READ_MASK                      _MK_MASK_CONST(0x80000000)
+#define APBDMA_COMMAND_0_WRITE_MASK                     _MK_MASK_CONST(0x80000000)
+// Enables Global APB-DMA  
+#define APBDMA_COMMAND_0_GEN_SHIFT                      _MK_SHIFT_CONST(31)
+#define APBDMA_COMMAND_0_GEN_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_COMMAND_0_GEN_SHIFT)
+#define APBDMA_COMMAND_0_GEN_RANGE                      31:31
+#define APBDMA_COMMAND_0_GEN_WOFFSET                    0x0
+#define APBDMA_COMMAND_0_GEN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_COMMAND_0_GEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_COMMAND_0_GEN_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMA_COMMAND_0_GEN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_STATUS_0  
+#define APBDMA_STATUS_0                 _MK_ADDR_CONST(0x4)
+#define APBDMA_STATUS_0_SECURE                  0x0
+#define APBDMA_STATUS_0_WORD_COUNT                      0x1
+#define APBDMA_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDMA_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDMA_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// DMA channel15  status 
+#define APBDMA_STATUS_0_BSY_15_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMA_STATUS_0_BSY_15_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_15_SHIFT)
+#define APBDMA_STATUS_0_BSY_15_RANGE                    31:31
+#define APBDMA_STATUS_0_BSY_15_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_15_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_15_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_15_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel14  status
+#define APBDMA_STATUS_0_BSY_14_SHIFT                    _MK_SHIFT_CONST(30)
+#define APBDMA_STATUS_0_BSY_14_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_14_SHIFT)
+#define APBDMA_STATUS_0_BSY_14_RANGE                    30:30
+#define APBDMA_STATUS_0_BSY_14_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_14_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_14_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_14_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel13  status 
+#define APBDMA_STATUS_0_BSY_13_SHIFT                    _MK_SHIFT_CONST(29)
+#define APBDMA_STATUS_0_BSY_13_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_13_SHIFT)
+#define APBDMA_STATUS_0_BSY_13_RANGE                    29:29
+#define APBDMA_STATUS_0_BSY_13_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_13_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_13_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_13_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel12  status 
+#define APBDMA_STATUS_0_BSY_12_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMA_STATUS_0_BSY_12_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_12_SHIFT)
+#define APBDMA_STATUS_0_BSY_12_RANGE                    28:28
+#define APBDMA_STATUS_0_BSY_12_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_12_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_12_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_12_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel11  status 
+#define APBDMA_STATUS_0_BSY_11_SHIFT                    _MK_SHIFT_CONST(27)
+#define APBDMA_STATUS_0_BSY_11_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_11_SHIFT)
+#define APBDMA_STATUS_0_BSY_11_RANGE                    27:27
+#define APBDMA_STATUS_0_BSY_11_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_11_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_11_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_11_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel10  status
+#define APBDMA_STATUS_0_BSY_10_SHIFT                    _MK_SHIFT_CONST(26)
+#define APBDMA_STATUS_0_BSY_10_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_10_SHIFT)
+#define APBDMA_STATUS_0_BSY_10_RANGE                    26:26
+#define APBDMA_STATUS_0_BSY_10_WOFFSET                  0x0
+#define APBDMA_STATUS_0_BSY_10_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_10_NOT_BUSY                 _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_10_BUSY                     _MK_ENUM_CONST(1)
+
+// DMA channel9  status 
+#define APBDMA_STATUS_0_BSY_9_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDMA_STATUS_0_BSY_9_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_9_SHIFT)
+#define APBDMA_STATUS_0_BSY_9_RANGE                     25:25
+#define APBDMA_STATUS_0_BSY_9_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_9_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_9_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_9_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel8  status 
+#define APBDMA_STATUS_0_BSY_8_SHIFT                     _MK_SHIFT_CONST(24)
+#define APBDMA_STATUS_0_BSY_8_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_8_SHIFT)
+#define APBDMA_STATUS_0_BSY_8_RANGE                     24:24
+#define APBDMA_STATUS_0_BSY_8_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_8_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_8_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_8_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel7  status 
+#define APBDMA_STATUS_0_BSY_7_SHIFT                     _MK_SHIFT_CONST(23)
+#define APBDMA_STATUS_0_BSY_7_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_7_SHIFT)
+#define APBDMA_STATUS_0_BSY_7_RANGE                     23:23
+#define APBDMA_STATUS_0_BSY_7_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_7_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_7_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel6  status 
+#define APBDMA_STATUS_0_BSY_6_SHIFT                     _MK_SHIFT_CONST(22)
+#define APBDMA_STATUS_0_BSY_6_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_6_SHIFT)
+#define APBDMA_STATUS_0_BSY_6_RANGE                     22:22
+#define APBDMA_STATUS_0_BSY_6_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_6_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_6_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel5  status 
+#define APBDMA_STATUS_0_BSY_5_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDMA_STATUS_0_BSY_5_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_5_SHIFT)
+#define APBDMA_STATUS_0_BSY_5_RANGE                     21:21
+#define APBDMA_STATUS_0_BSY_5_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_5_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_5_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel4  status 
+#define APBDMA_STATUS_0_BSY_4_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_STATUS_0_BSY_4_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_4_SHIFT)
+#define APBDMA_STATUS_0_BSY_4_RANGE                     20:20
+#define APBDMA_STATUS_0_BSY_4_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_4_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_4_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel3  status 
+#define APBDMA_STATUS_0_BSY_3_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_STATUS_0_BSY_3_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_3_SHIFT)
+#define APBDMA_STATUS_0_BSY_3_RANGE                     19:19
+#define APBDMA_STATUS_0_BSY_3_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_3_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_3_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel2  status 
+#define APBDMA_STATUS_0_BSY_2_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDMA_STATUS_0_BSY_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_2_SHIFT)
+#define APBDMA_STATUS_0_BSY_2_RANGE                     18:18
+#define APBDMA_STATUS_0_BSY_2_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_2_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_2_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel1  status 
+#define APBDMA_STATUS_0_BSY_1_SHIFT                     _MK_SHIFT_CONST(17)
+#define APBDMA_STATUS_0_BSY_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_1_SHIFT)
+#define APBDMA_STATUS_0_BSY_1_RANGE                     17:17
+#define APBDMA_STATUS_0_BSY_1_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_1_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_1_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel0  status 
+#define APBDMA_STATUS_0_BSY_0_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMA_STATUS_0_BSY_0_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_BSY_0_SHIFT)
+#define APBDMA_STATUS_0_BSY_0_RANGE                     16:16
+#define APBDMA_STATUS_0_BSY_0_WOFFSET                   0x0
+#define APBDMA_STATUS_0_BSY_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_BSY_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_BSY_0_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_BSY_0_BUSY                      _MK_ENUM_CONST(1)
+
+// DMA channel15 Interrupt Status
+#define APBDMA_STATUS_0_ISE_EOC_15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_STATUS_0_ISE_EOC_15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_15_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_15_RANGE                        15:15
+#define APBDMA_STATUS_0_ISE_EOC_15_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_15_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_15_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel14 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_STATUS_0_ISE_EOC_14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_14_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_14_RANGE                        14:14
+#define APBDMA_STATUS_0_ISE_EOC_14_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_14_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_14_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel13 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_STATUS_0_ISE_EOC_13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_13_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_13_RANGE                        13:13
+#define APBDMA_STATUS_0_ISE_EOC_13_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_13_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_13_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel12 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_STATUS_0_ISE_EOC_12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_12_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_12_RANGE                        12:12
+#define APBDMA_STATUS_0_ISE_EOC_12_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_12_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_12_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel11 Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_STATUS_0_ISE_EOC_11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_11_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_11_RANGE                        11:11
+#define APBDMA_STATUS_0_ISE_EOC_11_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_11_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_11_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel10 Interrupt Status
+#define APBDMA_STATUS_0_ISE_EOC_10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_STATUS_0_ISE_EOC_10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_10_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_10_RANGE                        10:10
+#define APBDMA_STATUS_0_ISE_EOC_10_WOFFSET                      0x0
+#define APBDMA_STATUS_0_ISE_EOC_10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_10_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_10_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DMA channel9  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_STATUS_0_ISE_EOC_9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_9_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_9_RANGE                 9:9
+#define APBDMA_STATUS_0_ISE_EOC_9_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_9_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_9_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel8  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_STATUS_0_ISE_EOC_8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_8_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_8_RANGE                 8:8
+#define APBDMA_STATUS_0_ISE_EOC_8_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_8_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_8_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel7  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_STATUS_0_ISE_EOC_7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_7_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_7_RANGE                 7:7
+#define APBDMA_STATUS_0_ISE_EOC_7_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_7_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_7_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel6  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_STATUS_0_ISE_EOC_6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_6_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_6_RANGE                 6:6
+#define APBDMA_STATUS_0_ISE_EOC_6_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_6_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_6_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel5  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_STATUS_0_ISE_EOC_5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_5_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_5_RANGE                 5:5
+#define APBDMA_STATUS_0_ISE_EOC_5_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_5_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_5_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel4  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_STATUS_0_ISE_EOC_4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_4_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_4_RANGE                 4:4
+#define APBDMA_STATUS_0_ISE_EOC_4_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_4_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_4_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel3  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_STATUS_0_ISE_EOC_3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_3_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_3_RANGE                 3:3
+#define APBDMA_STATUS_0_ISE_EOC_3_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_3_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_3_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel2  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_STATUS_0_ISE_EOC_2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_2_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_2_RANGE                 2:2
+#define APBDMA_STATUS_0_ISE_EOC_2_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_2_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_2_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel1  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_STATUS_0_ISE_EOC_1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_1_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_1_RANGE                 1:1
+#define APBDMA_STATUS_0_ISE_EOC_1_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_1_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_1_ACTIVE                        _MK_ENUM_CONST(1)
+
+// DMA channel0  Interrupt Status 
+#define APBDMA_STATUS_0_ISE_EOC_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_STATUS_0_ISE_EOC_0_SHIFT)
+#define APBDMA_STATUS_0_ISE_EOC_0_RANGE                 0:0
+#define APBDMA_STATUS_0_ISE_EOC_0_WOFFSET                       0x0
+#define APBDMA_STATUS_0_ISE_EOC_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_STATUS_0_ISE_EOC_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_STATUS_0_ISE_EOC_0_NOT_ACTIVE                    _MK_ENUM_CONST(0)
+#define APBDMA_STATUS_0_ISE_EOC_0_ACTIVE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_REQUESTORS_TX_0  
+#define APBDMA_REQUESTORS_TX_0                  _MK_ADDR_CONST(0x8)
+#define APBDMA_REQUESTORS_TX_0_SECURE                   0x0
+#define APBDMA_REQUESTORS_TX_0_WORD_COUNT                       0x1
+#define APBDMA_REQUESTORS_TX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_RESET_MASK                       _MK_MASK_CONST(0x3ffffff)
+#define APBDMA_REQUESTORS_TX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_READ_MASK                        _MK_MASK_CONST(0x3ffffff)
+#define APBDMA_REQUESTORS_TX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// OWR-I2C
+#define APBDMA_REQUESTORS_TX_0_OWR_SHIFT                        _MK_SHIFT_CONST(25)
+#define APBDMA_REQUESTORS_TX_0_OWR_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_OWR_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_OWR_RANGE                        25:25
+#define APBDMA_REQUESTORS_TX_0_OWR_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_TX_0_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_OWR_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_OWR_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DVC-I2C
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_SHIFT                    _MK_SHIFT_CONST(24)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_DVC_I2C_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_RANGE                    24:24
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_DVC_I2C_ACTIVE                   _MK_ENUM_CONST(1)
+
+// I2C3 
+#define APBDMA_REQUESTORS_TX_0_I2C_3_SHIFT                      _MK_SHIFT_CONST(23)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2C_3_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_RANGE                      23:23
+#define APBDMA_REQUESTORS_TX_0_I2C_3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2C_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2C_3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2C2 
+#define APBDMA_REQUESTORS_TX_0_I2C_2_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2C_2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_RANGE                      22:22
+#define APBDMA_REQUESTORS_TX_0_I2C_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2C_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2C_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2C1 
+#define APBDMA_REQUESTORS_TX_0_I2C_1_SHIFT                      _MK_SHIFT_CONST(21)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2C_1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_RANGE                      21:21
+#define APBDMA_REQUESTORS_TX_0_I2C_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2C_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2C_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// UARTE 
+#define APBDMA_REQUESTORS_TX_0_UART_E_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_REQUESTORS_TX_0_UART_E_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_E_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_E_RANGE                     20:20
+#define APBDMA_REQUESTORS_TX_0_UART_E_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_E_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_E_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_E_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_E_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_E_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_E_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UARTD 
+#define APBDMA_REQUESTORS_TX_0_UART_D_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_REQUESTORS_TX_0_UART_D_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_D_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_D_RANGE                     19:19
+#define APBDMA_REQUESTORS_TX_0_UART_D_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_D_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_D_ACTIVE                    _MK_ENUM_CONST(1)
+
+// SLINK 2B-4
+#define APBDMA_REQUESTORS_TX_0_SL2B4_SHIFT                      _MK_SHIFT_CONST(18)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B4_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_RANGE                      18:18
+#define APBDMA_REQUESTORS_TX_0_SL2B4_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B4_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-3
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B3_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_RANGE                      17:17
+#define APBDMA_REQUESTORS_TX_0_SL2B3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-2
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_RANGE                      16:16
+#define APBDMA_REQUESTORS_TX_0_SL2B2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-1
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SL2B1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_RANGE                      15:15
+#define APBDMA_REQUESTORS_TX_0_SL2B1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SL2B1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SL2B1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 4B
+#define APBDMA_REQUESTORS_TX_0_RSVD_SHIFT                       _MK_SHIFT_CONST(14)
+#define APBDMA_REQUESTORS_TX_0_RSVD_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_RSVD_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_RSVD_RANGE                       14:14
+#define APBDMA_REQUESTORS_TX_0_RSVD_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_RSVD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_RSVD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_RSVD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_RSVD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_RSVD_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_RSVD_ACTIVE                      _MK_ENUM_CONST(1)
+
+// ACModem
+#define APBDMA_REQUESTORS_TX_0_ACModem_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_REQUESTORS_TX_0_ACModem_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_ACModem_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_ACModem_RANGE                    13:13
+#define APBDMA_REQUESTORS_TX_0_ACModem_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_TX_0_ACModem_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_ACModem_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_ACModem_ACTIVE                   _MK_ENUM_CONST(1)
+
+// AC97
+#define APBDMA_REQUESTORS_TX_0_AC97_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDMA_REQUESTORS_TX_0_AC97_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_AC97_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_AC97_RANGE                       12:12
+#define APBDMA_REQUESTORS_TX_0_AC97_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_AC97_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_AC97_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPI Controller
+#define APBDMA_REQUESTORS_TX_0_SPI_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_REQUESTORS_TX_0_SPI_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SPI_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SPI_RANGE                        11:11
+#define APBDMA_REQUESTORS_TX_0_SPI_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_TX_0_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPI_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SPI_ACTIVE                       _MK_ENUM_CONST(1)
+
+// UART C
+#define APBDMA_REQUESTORS_TX_0_UART_C_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDMA_REQUESTORS_TX_0_UART_C_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_C_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_C_RANGE                     10:10
+#define APBDMA_REQUESTORS_TX_0_UART_C_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_C_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_C_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART B (VFIR)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_REQUESTORS_TX_0_UART_B_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_B_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_B_RANGE                     9:9
+#define APBDMA_REQUESTORS_TX_0_UART_B_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_B_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART A
+#define APBDMA_REQUESTORS_TX_0_UART_A_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_REQUESTORS_TX_0_UART_A_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UART_A_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UART_A_RANGE                     8:8
+#define APBDMA_REQUESTORS_TX_0_UART_A_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_UART_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UART_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UART_A_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Tx Output FIFO1 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S2_1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_RANGE                     7:7
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_1_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Tx Output FIFO2 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S2_2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_RANGE                     6:6
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S2_2_ACTIVE                    _MK_ENUM_CONST(1)
+
+// MIPI Rx Input FIFO.
+#define APBDMA_REQUESTORS_TX_0_MIPI_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDMA_REQUESTORS_TX_0_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_MIPI_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_MIPI_RANGE                       5:5
+#define APBDMA_REQUESTORS_TX_0_MIPI_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// EBU USR Output (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_UI_I_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDMA_REQUESTORS_TX_0_UI_I_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_UI_I_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_UI_I_RANGE                       4:4
+#define APBDMA_REQUESTORS_TX_0_UI_I_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_TX_0_UI_I_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_UI_I_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_UI_I_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPDIF Output FIFO (Rx) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_SPD_I_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_RANGE                      3:3
+#define APBDMA_REQUESTORS_TX_0_SPD_I_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_SPD_I_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_SPD_I_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2S Tx Output FIFO1 (Record) (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S_1_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_RANGE                      2:2
+#define APBDMA_REQUESTORS_TX_0_I2S_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2S_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2S Tx Output FIFO2 (Play) (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_I2S_2_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_RANGE                      1:1
+#define APBDMA_REQUESTORS_TX_0_I2S_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_TX_0_I2S_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_I2S_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// Enables counter request.
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_TX_0_CNTR_REQ_SHIFT)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_RANGE                   0:0
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_WOFFSET                 0x0
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_TX_0_CNTR_REQ_ACTIVE                  _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_REQUESTORS_RX_0  
+#define APBDMA_REQUESTORS_RX_0                  _MK_ADDR_CONST(0xc)
+#define APBDMA_REQUESTORS_RX_0_SECURE                   0x0
+#define APBDMA_REQUESTORS_RX_0_WORD_COUNT                       0x1
+#define APBDMA_REQUESTORS_RX_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_RESET_MASK                       _MK_MASK_CONST(0x3ffbfff)
+#define APBDMA_REQUESTORS_RX_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_READ_MASK                        _MK_MASK_CONST(0x3ffffff)
+#define APBDMA_REQUESTORS_RX_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// OWR-I2C
+#define APBDMA_REQUESTORS_RX_0_OWR_SHIFT                        _MK_SHIFT_CONST(25)
+#define APBDMA_REQUESTORS_RX_0_OWR_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_OWR_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_OWR_RANGE                        25:25
+#define APBDMA_REQUESTORS_RX_0_OWR_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_RX_0_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_OWR_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_OWR_ACTIVE                       _MK_ENUM_CONST(1)
+
+// DVC-I2C
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_SHIFT                    _MK_SHIFT_CONST(24)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_DVC_I2C_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_RANGE                    24:24
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_DVC_I2C_ACTIVE                   _MK_ENUM_CONST(1)
+
+// I2C3 
+#define APBDMA_REQUESTORS_RX_0_I2C_3_SHIFT                      _MK_SHIFT_CONST(23)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2C_3_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_RANGE                      23:23
+#define APBDMA_REQUESTORS_RX_0_I2C_3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2C_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2C_3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2C2 
+#define APBDMA_REQUESTORS_RX_0_I2C_2_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2C_2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_RANGE                      22:22
+#define APBDMA_REQUESTORS_RX_0_I2C_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2C_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2C_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// I2C1 
+#define APBDMA_REQUESTORS_RX_0_I2C_1_SHIFT                      _MK_SHIFT_CONST(21)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2C_1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_RANGE                      21:21
+#define APBDMA_REQUESTORS_RX_0_I2C_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2C_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2C_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+// UARTE 
+#define APBDMA_REQUESTORS_RX_0_UART_E_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_REQUESTORS_RX_0_UART_E_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_E_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_E_RANGE                     20:20
+#define APBDMA_REQUESTORS_RX_0_UART_E_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_E_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_E_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_E_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_E_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_E_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_E_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UARTD 
+#define APBDMA_REQUESTORS_RX_0_UART_D_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_REQUESTORS_RX_0_UART_D_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_D_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_D_RANGE                     19:19
+#define APBDMA_REQUESTORS_RX_0_UART_D_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_D_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_D_ACTIVE                    _MK_ENUM_CONST(1)
+
+// SLINK 2B-4
+#define APBDMA_REQUESTORS_RX_0_SL2B4_SHIFT                      _MK_SHIFT_CONST(18)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B4_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_RANGE                      18:18
+#define APBDMA_REQUESTORS_RX_0_SL2B4_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B4_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-3
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B3_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_RANGE                      17:17
+#define APBDMA_REQUESTORS_RX_0_SL2B3_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B3_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-2
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_RANGE                      16:16
+#define APBDMA_REQUESTORS_RX_0_SL2B2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B2_ACTIVE                     _MK_ENUM_CONST(1)
+
+// SLINK 2B-1
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SL2B1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_RANGE                      15:15
+#define APBDMA_REQUESTORS_RX_0_SL2B1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SL2B1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SL2B1_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define APBDMA_REQUESTORS_RX_0_RSVD_SHIFT                       _MK_SHIFT_CONST(14)
+#define APBDMA_REQUESTORS_RX_0_RSVD_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_RSVD_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_RSVD_RANGE                       14:14
+#define APBDMA_REQUESTORS_RX_0_RSVD_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_RSVD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_RSVD_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_RSVD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_RSVD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// ACModem
+#define APBDMA_REQUESTORS_RX_0_ACModem_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_REQUESTORS_RX_0_ACModem_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_ACModem_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_ACModem_RANGE                    13:13
+#define APBDMA_REQUESTORS_RX_0_ACModem_WOFFSET                  0x0
+#define APBDMA_REQUESTORS_RX_0_ACModem_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_ACModem_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_ACModem_ACTIVE                   _MK_ENUM_CONST(1)
+
+// AC97
+#define APBDMA_REQUESTORS_RX_0_AC97_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDMA_REQUESTORS_RX_0_AC97_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_AC97_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_AC97_RANGE                       12:12
+#define APBDMA_REQUESTORS_RX_0_AC97_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_AC97_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_AC97_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPI Controller
+#define APBDMA_REQUESTORS_RX_0_SPI_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_REQUESTORS_RX_0_SPI_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SPI_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SPI_RANGE                        11:11
+#define APBDMA_REQUESTORS_RX_0_SPI_WOFFSET                      0x0
+#define APBDMA_REQUESTORS_RX_0_SPI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SPI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPI_NOT_ACTIVE                   _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SPI_ACTIVE                       _MK_ENUM_CONST(1)
+
+// UART C
+#define APBDMA_REQUESTORS_RX_0_UART_C_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDMA_REQUESTORS_RX_0_UART_C_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_C_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_C_RANGE                     10:10
+#define APBDMA_REQUESTORS_RX_0_UART_C_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_C_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_C_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART B (VFIR)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_REQUESTORS_RX_0_UART_B_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_B_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_B_RANGE                     9:9
+#define APBDMA_REQUESTORS_RX_0_UART_B_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_B_ACTIVE                    _MK_ENUM_CONST(1)
+
+// UART A
+#define APBDMA_REQUESTORS_RX_0_UART_A_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_REQUESTORS_RX_0_UART_A_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UART_A_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UART_A_RANGE                     8:8
+#define APBDMA_REQUESTORS_RX_0_UART_A_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_UART_A_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UART_A_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UART_A_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Rx Input FIFO2 (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S2_2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_RANGE                     7:7
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_2_ACTIVE                    _MK_ENUM_CONST(1)
+
+// I2S2 Rx Input FIFO1 (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S2_1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_RANGE                     6:6
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_WOFFSET                   0x0
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_NOT_ACTIVE                        _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S2_1_ACTIVE                    _MK_ENUM_CONST(1)
+
+// MIPI Rx Input FIFO.
+#define APBDMA_REQUESTORS_RX_0_MIPI_SHIFT                       _MK_SHIFT_CONST(5)
+#define APBDMA_REQUESTORS_RX_0_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_MIPI_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_MIPI_RANGE                       5:5
+#define APBDMA_REQUESTORS_RX_0_MIPI_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// EBU+SPDIF USR Input (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_UI_I_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDMA_REQUESTORS_RX_0_UI_I_FIELD                       (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_UI_I_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_UI_I_RANGE                       4:4
+#define APBDMA_REQUESTORS_RX_0_UI_I_WOFFSET                     0x0
+#define APBDMA_REQUESTORS_RX_0_UI_I_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_UI_I_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_NOT_ACTIVE                  _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_UI_I_ACTIVE                      _MK_ENUM_CONST(1)
+
+// SPDIF Input FIFO (Rx) (Peripheral initiated DMA request) 1 = Activate DMA transfer 0 = NOP
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_SPD_I_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_RANGE                      3:3
+#define APBDMA_REQUESTORS_RX_0_SPD_I_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_SPD_I_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_SPD_I_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  I2S Rx Input FIFO2 (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S_2_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_RANGE                      2:2
+#define APBDMA_REQUESTORS_RX_0_I2S_2_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2S_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S_2_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  I2S Rx Input FIFO1 (Peripheral initiated DMA request) 1 = Activate DMA transfer0 = NOP
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_FIELD                      (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_I2S_1_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_RANGE                      1:1
+#define APBDMA_REQUESTORS_RX_0_I2S_1_WOFFSET                    0x0
+#define APBDMA_REQUESTORS_RX_0_I2S_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_NOT_ACTIVE                 _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_I2S_1_ACTIVE                     _MK_ENUM_CONST(1)
+
+//  indicates Enabled counter request or not 
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_REQUESTORS_RX_0_CNTR_REQ_SHIFT)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_RANGE                   0:0
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_WOFFSET                 0x0
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_REQUESTORS_RX_0_CNTR_REQ_ACTIVE                  _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_CNTRL_REG_0  
+#define APBDMA_CNTRL_REG_0                      _MK_ADDR_CONST(0x10)
+#define APBDMA_CNTRL_REG_0_SECURE                       0x0
+#define APBDMA_CNTRL_REG_0_WORD_COUNT                   0x1
+#define APBDMA_CNTRL_REG_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APBDMA_CNTRL_REG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define APBDMA_CNTRL_REG_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Enable the channel15 count
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH15_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_RANGE                    31:31
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH15_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel14 count
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH14_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_RANGE                    30:30
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH14_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel13 count
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SHIFT                    _MK_SHIFT_CONST(29)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH13_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_RANGE                    29:29
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH13_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel12 count
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH12_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_RANGE                    28:28
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH12_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel11 count
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SHIFT                    _MK_SHIFT_CONST(27)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH11_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_RANGE                    27:27
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH11_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel10 count
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SHIFT                    _MK_SHIFT_CONST(26)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH10_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_RANGE                    26:26
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH10_CNT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable the channel9 count
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH9_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_RANGE                     25:25
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH9_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel8 count
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SHIFT                     _MK_SHIFT_CONST(24)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH8_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_RANGE                     24:24
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH8_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel7 count
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SHIFT                     _MK_SHIFT_CONST(23)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH7_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_RANGE                     23:23
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH7_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel6 count
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SHIFT                     _MK_SHIFT_CONST(22)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH6_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_RANGE                     22:22
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH6_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel5 count
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SHIFT                     _MK_SHIFT_CONST(21)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH5_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_RANGE                     21:21
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH5_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel4 count
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SHIFT                     _MK_SHIFT_CONST(20)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH4_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_RANGE                     20:20
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH4_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel3 count
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH3_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_RANGE                     19:19
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH3_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel2 count
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH2_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_RANGE                     18:18
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH2_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel1 count
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SHIFT                     _MK_SHIFT_CONST(17)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH1_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_RANGE                     17:17
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH1_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable the channel0 count
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_CNTRL_REG_0_CH0_CNT_EN_SHIFT)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_RANGE                     16:16
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_WOFFSET                   0x0
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_CNTRL_REG_0_CH0_CNT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// DMA COUNT Value.
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_FIELD                    (_MK_MASK_CONST(0xffff) << APBDMA_CNTRL_REG_0_COUNT_VALUE_SHIFT)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_RANGE                    15:0
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_WOFFSET                  0x0
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_CNTRL_REG_0_COUNT_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDMA_IRQ_STA_CPU_0  
+#define APBDMA_IRQ_STA_CPU_0                    _MK_ADDR_CONST(0x14)
+#define APBDMA_IRQ_STA_CPU_0_SECURE                     0x0
+#define APBDMA_IRQ_STA_CPU_0_WORD_COUNT                         0x1
+#define APBDMA_IRQ_STA_CPU_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_CPU_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_CPU_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Gathers all the after-masking CPU directed IRQ status bits from channel15 
+#define APBDMA_IRQ_STA_CPU_0_CH15_SHIFT                 _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_STA_CPU_0_CH15_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH15_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH15_RANGE                 15:15
+#define APBDMA_IRQ_STA_CPU_0_CH15_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH15_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel14 
+#define APBDMA_IRQ_STA_CPU_0_CH14_SHIFT                 _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_STA_CPU_0_CH14_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH14_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH14_RANGE                 14:14
+#define APBDMA_IRQ_STA_CPU_0_CH14_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH14_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel13 
+#define APBDMA_IRQ_STA_CPU_0_CH13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_STA_CPU_0_CH13_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH13_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH13_RANGE                 13:13
+#define APBDMA_IRQ_STA_CPU_0_CH13_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH13_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel12 
+#define APBDMA_IRQ_STA_CPU_0_CH12_SHIFT                 _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_STA_CPU_0_CH12_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH12_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH12_RANGE                 12:12
+#define APBDMA_IRQ_STA_CPU_0_CH12_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH12_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel11 
+#define APBDMA_IRQ_STA_CPU_0_CH11_SHIFT                 _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_STA_CPU_0_CH11_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH11_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH11_RANGE                 11:11
+#define APBDMA_IRQ_STA_CPU_0_CH11_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH11_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel10 
+#define APBDMA_IRQ_STA_CPU_0_CH10_SHIFT                 _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_STA_CPU_0_CH10_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH10_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH10_RANGE                 10:10
+#define APBDMA_IRQ_STA_CPU_0_CH10_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_CPU_0_CH10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH10_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel9 
+#define APBDMA_IRQ_STA_CPU_0_CH9_SHIFT                  _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_STA_CPU_0_CH9_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH9_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH9_RANGE                  9:9
+#define APBDMA_IRQ_STA_CPU_0_CH9_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH9_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel8 
+#define APBDMA_IRQ_STA_CPU_0_CH8_SHIFT                  _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_STA_CPU_0_CH8_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH8_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH8_RANGE                  8:8
+#define APBDMA_IRQ_STA_CPU_0_CH8_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH8_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel7 
+#define APBDMA_IRQ_STA_CPU_0_CH7_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_STA_CPU_0_CH7_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH7_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH7_RANGE                  7:7
+#define APBDMA_IRQ_STA_CPU_0_CH7_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH7_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel6 
+#define APBDMA_IRQ_STA_CPU_0_CH6_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_STA_CPU_0_CH6_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH6_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH6_RANGE                  6:6
+#define APBDMA_IRQ_STA_CPU_0_CH6_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH6_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel5 
+#define APBDMA_IRQ_STA_CPU_0_CH5_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_STA_CPU_0_CH5_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH5_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH5_RANGE                  5:5
+#define APBDMA_IRQ_STA_CPU_0_CH5_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH5_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel4 
+#define APBDMA_IRQ_STA_CPU_0_CH4_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_STA_CPU_0_CH4_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH4_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH4_RANGE                  4:4
+#define APBDMA_IRQ_STA_CPU_0_CH4_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH4_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel3 
+#define APBDMA_IRQ_STA_CPU_0_CH3_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_STA_CPU_0_CH3_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH3_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH3_RANGE                  3:3
+#define APBDMA_IRQ_STA_CPU_0_CH3_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH3_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel2 
+#define APBDMA_IRQ_STA_CPU_0_CH2_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_STA_CPU_0_CH2_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH2_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH2_RANGE                  2:2
+#define APBDMA_IRQ_STA_CPU_0_CH2_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel1 
+#define APBDMA_IRQ_STA_CPU_0_CH1_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_STA_CPU_0_CH1_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH1_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH1_RANGE                  1:1
+#define APBDMA_IRQ_STA_CPU_0_CH1_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking CPU directed IRQ status bits from channel0 
+#define APBDMA_IRQ_STA_CPU_0_CH0_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_CPU_0_CH0_SHIFT)
+#define APBDMA_IRQ_STA_CPU_0_CH0_RANGE                  0:0
+#define APBDMA_IRQ_STA_CPU_0_CH0_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_CPU_0_CH0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_CPU_0_CH0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_CPU_0_CH0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_STA_COP_0  
+#define APBDMA_IRQ_STA_COP_0                    _MK_ADDR_CONST(0x18)
+#define APBDMA_IRQ_STA_COP_0_SECURE                     0x0
+#define APBDMA_IRQ_STA_COP_0_WORD_COUNT                         0x1
+#define APBDMA_IRQ_STA_COP_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_COP_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_STA_COP_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Gathers all the after-masking COP directed IRQ status bits from channel15 
+#define APBDMA_IRQ_STA_COP_0_CH15_SHIFT                 _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_STA_COP_0_CH15_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH15_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH15_RANGE                 15:15
+#define APBDMA_IRQ_STA_COP_0_CH15_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH15_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH15_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel14 
+#define APBDMA_IRQ_STA_COP_0_CH14_SHIFT                 _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_STA_COP_0_CH14_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH14_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH14_RANGE                 14:14
+#define APBDMA_IRQ_STA_COP_0_CH14_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH14_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH14_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel13 
+#define APBDMA_IRQ_STA_COP_0_CH13_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_STA_COP_0_CH13_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH13_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH13_RANGE                 13:13
+#define APBDMA_IRQ_STA_COP_0_CH13_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH13_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH13_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel12 
+#define APBDMA_IRQ_STA_COP_0_CH12_SHIFT                 _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_STA_COP_0_CH12_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH12_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH12_RANGE                 12:12
+#define APBDMA_IRQ_STA_COP_0_CH12_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH12_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH12_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel11 
+#define APBDMA_IRQ_STA_COP_0_CH11_SHIFT                 _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_STA_COP_0_CH11_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH11_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH11_RANGE                 11:11
+#define APBDMA_IRQ_STA_COP_0_CH11_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH11_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH11_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel10 
+#define APBDMA_IRQ_STA_COP_0_CH10_SHIFT                 _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_STA_COP_0_CH10_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH10_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH10_RANGE                 10:10
+#define APBDMA_IRQ_STA_COP_0_CH10_WOFFSET                       0x0
+#define APBDMA_IRQ_STA_COP_0_CH10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH10_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH10_ENABLE                        _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel9 
+#define APBDMA_IRQ_STA_COP_0_CH9_SHIFT                  _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_STA_COP_0_CH9_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH9_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH9_RANGE                  9:9
+#define APBDMA_IRQ_STA_COP_0_CH9_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH9_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH9_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel8 
+#define APBDMA_IRQ_STA_COP_0_CH8_SHIFT                  _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_STA_COP_0_CH8_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH8_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH8_RANGE                  8:8
+#define APBDMA_IRQ_STA_COP_0_CH8_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH8_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH8_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel7 
+#define APBDMA_IRQ_STA_COP_0_CH7_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_STA_COP_0_CH7_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH7_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH7_RANGE                  7:7
+#define APBDMA_IRQ_STA_COP_0_CH7_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH7_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH7_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel6 
+#define APBDMA_IRQ_STA_COP_0_CH6_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_STA_COP_0_CH6_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH6_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH6_RANGE                  6:6
+#define APBDMA_IRQ_STA_COP_0_CH6_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH6_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH6_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel5 
+#define APBDMA_IRQ_STA_COP_0_CH5_SHIFT                  _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_STA_COP_0_CH5_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH5_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH5_RANGE                  5:5
+#define APBDMA_IRQ_STA_COP_0_CH5_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH5_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH5_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel4 
+#define APBDMA_IRQ_STA_COP_0_CH4_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_STA_COP_0_CH4_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH4_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH4_RANGE                  4:4
+#define APBDMA_IRQ_STA_COP_0_CH4_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH4_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH4_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel3 
+#define APBDMA_IRQ_STA_COP_0_CH3_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_STA_COP_0_CH3_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH3_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH3_RANGE                  3:3
+#define APBDMA_IRQ_STA_COP_0_CH3_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH3_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH3_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel2 
+#define APBDMA_IRQ_STA_COP_0_CH2_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_STA_COP_0_CH2_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH2_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH2_RANGE                  2:2
+#define APBDMA_IRQ_STA_COP_0_CH2_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH2_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel1 
+#define APBDMA_IRQ_STA_COP_0_CH1_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_STA_COP_0_CH1_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH1_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH1_RANGE                  1:1
+#define APBDMA_IRQ_STA_COP_0_CH1_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH1_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Gathers all the after-masking COP directed IRQ status bits from channel0 
+#define APBDMA_IRQ_STA_COP_0_CH0_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH0_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_IRQ_STA_COP_0_CH0_SHIFT)
+#define APBDMA_IRQ_STA_COP_0_CH0_RANGE                  0:0
+#define APBDMA_IRQ_STA_COP_0_CH0_WOFFSET                        0x0
+#define APBDMA_IRQ_STA_COP_0_CH0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_STA_COP_0_CH0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_STA_COP_0_CH0_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_STA_COP_0_CH0_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_0  
+#define APBDMA_IRQ_MASK_0                       _MK_ADDR_CONST(0x1c)
+#define APBDMA_IRQ_MASK_0_SECURE                        0x0
+#define APBDMA_IRQ_MASK_0_WORD_COUNT                    0x1
+#define APBDMA_IRQ_MASK_0_RESET_VAL                     _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Each bit allows the associated channel15 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH15_SHIFT                    _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_0_CH15_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH15_RANGE                    15:15
+#define APBDMA_IRQ_MASK_0_CH15_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH15_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH15_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH15_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel14 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH14_SHIFT                    _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_0_CH14_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH14_RANGE                    14:14
+#define APBDMA_IRQ_MASK_0_CH14_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH14_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH14_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH14_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel13 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH13_SHIFT                    _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_0_CH13_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH13_RANGE                    13:13
+#define APBDMA_IRQ_MASK_0_CH13_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH13_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH13_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH13_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel12 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH12_SHIFT                    _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_0_CH12_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH12_RANGE                    12:12
+#define APBDMA_IRQ_MASK_0_CH12_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH12_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH12_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH12_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel11 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH11_SHIFT                    _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_0_CH11_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH11_RANGE                    11:11
+#define APBDMA_IRQ_MASK_0_CH11_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH11_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH11_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH11_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel10 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH10_SHIFT                    _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_0_CH10_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH10_RANGE                    10:10
+#define APBDMA_IRQ_MASK_0_CH10_WOFFSET                  0x0
+#define APBDMA_IRQ_MASK_0_CH10_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH10_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH10_ENABLE                   _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel9 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH9_SHIFT                     _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_0_CH9_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH9_RANGE                     9:9
+#define APBDMA_IRQ_MASK_0_CH9_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH9_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH9_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH9_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel8 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH8_SHIFT                     _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_0_CH8_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH8_RANGE                     8:8
+#define APBDMA_IRQ_MASK_0_CH8_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH8_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH8_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH8_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel7 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH7_SHIFT                     _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_0_CH7_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH7_RANGE                     7:7
+#define APBDMA_IRQ_MASK_0_CH7_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH7_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH7_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH7_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel6 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH6_SHIFT                     _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_0_CH6_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH6_RANGE                     6:6
+#define APBDMA_IRQ_MASK_0_CH6_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH6_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH6_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH6_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel5 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH5_SHIFT                     _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_0_CH5_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH5_RANGE                     5:5
+#define APBDMA_IRQ_MASK_0_CH5_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH5_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH5_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH5_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel4 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH4_SHIFT                     _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_0_CH4_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH4_RANGE                     4:4
+#define APBDMA_IRQ_MASK_0_CH4_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH4_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH4_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH4_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel3 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH3_SHIFT                     _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_0_CH3_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH3_RANGE                     3:3
+#define APBDMA_IRQ_MASK_0_CH3_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH3_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH3_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH3_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel2 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH2_SHIFT                     _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_0_CH2_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH2_RANGE                     2:2
+#define APBDMA_IRQ_MASK_0_CH2_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH2_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH2_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH2_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel1 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH1_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_0_CH1_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH1_RANGE                     1:1
+#define APBDMA_IRQ_MASK_0_CH1_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH1_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH1_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH1_ENABLE                    _MK_ENUM_CONST(1)
+
+// Each bit allows the associated channel0 IRQ to propagate when '1' 
+#define APBDMA_IRQ_MASK_0_CH0_SHIFT                     _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH0_FIELD                     (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_0_CH0_RANGE                     0:0
+#define APBDMA_IRQ_MASK_0_CH0_WOFFSET                   0x0
+#define APBDMA_IRQ_MASK_0_CH0_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_0_CH0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_0_CH0_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_0_CH0_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_SET_0  
+#define APBDMA_IRQ_MASK_SET_0                   _MK_ADDR_CONST(0x20)
+#define APBDMA_IRQ_MASK_SET_0_SECURE                    0x0
+#define APBDMA_IRQ_MASK_SET_0_WORD_COUNT                        0x1
+#define APBDMA_IRQ_MASK_SET_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_SET_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_READ_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_SET_0_CH15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH15_RANGE                        15:15
+#define APBDMA_IRQ_MASK_SET_0_CH15_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH15_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_SET_0_CH14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH14_RANGE                        14:14
+#define APBDMA_IRQ_MASK_SET_0_CH14_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH14_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_SET_0_CH13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH13_RANGE                        13:13
+#define APBDMA_IRQ_MASK_SET_0_CH13_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH13_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_SET_0_CH12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH12_RANGE                        12:12
+#define APBDMA_IRQ_MASK_SET_0_CH12_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH12_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_SET_0_CH11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH11_RANGE                        11:11
+#define APBDMA_IRQ_MASK_SET_0_CH11_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH11_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_SET_0_CH10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH10_RANGE                        10:10
+#define APBDMA_IRQ_MASK_SET_0_CH10_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_SET_0_CH10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH10_ENABLE                       _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_SET_0_CH9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH9_RANGE                 9:9
+#define APBDMA_IRQ_MASK_SET_0_CH9_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH9_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_SET_0_CH8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH8_RANGE                 8:8
+#define APBDMA_IRQ_MASK_SET_0_CH8_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH8_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_SET_0_CH7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH7_RANGE                 7:7
+#define APBDMA_IRQ_MASK_SET_0_CH7_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH7_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_SET_0_CH6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH6_RANGE                 6:6
+#define APBDMA_IRQ_MASK_SET_0_CH6_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH6_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_SET_0_CH5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH5_RANGE                 5:5
+#define APBDMA_IRQ_MASK_SET_0_CH5_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH5_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_SET_0_CH4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH4_RANGE                 4:4
+#define APBDMA_IRQ_MASK_SET_0_CH4_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH4_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_SET_0_CH3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH3_RANGE                 3:3
+#define APBDMA_IRQ_MASK_SET_0_CH3_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH3_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_SET_0_CH2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH2_RANGE                 2:2
+#define APBDMA_IRQ_MASK_SET_0_CH2_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_SET_0_CH1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH1_RANGE                 1:1
+#define APBDMA_IRQ_MASK_SET_0_CH1_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Sets the Mask Register
+#define APBDMA_IRQ_MASK_SET_0_CH0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_SET_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_SET_0_CH0_RANGE                 0:0
+#define APBDMA_IRQ_MASK_SET_0_CH0_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_SET_0_CH0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_SET_0_CH0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_SET_0_CH0_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_IRQ_MASK_CLR_0  
+#define APBDMA_IRQ_MASK_CLR_0                   _MK_ADDR_CONST(0x24)
+#define APBDMA_IRQ_MASK_CLR_0_SECURE                    0x0
+#define APBDMA_IRQ_MASK_CLR_0_WORD_COUNT                        0x1
+#define APBDMA_IRQ_MASK_CLR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDMA_IRQ_MASK_CLR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_READ_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SHIFT                        _MK_SHIFT_CONST(15)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH15_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_RANGE                        15:15
+#define APBDMA_IRQ_MASK_CLR_0_CH15_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH15_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH14_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_RANGE                        14:14
+#define APBDMA_IRQ_MASK_CLR_0_CH14_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH14_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SHIFT                        _MK_SHIFT_CONST(13)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH13_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_RANGE                        13:13
+#define APBDMA_IRQ_MASK_CLR_0_CH13_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH13_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SHIFT                        _MK_SHIFT_CONST(12)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH12_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_RANGE                        12:12
+#define APBDMA_IRQ_MASK_CLR_0_CH12_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH12_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SHIFT                        _MK_SHIFT_CONST(11)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH11_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_RANGE                        11:11
+#define APBDMA_IRQ_MASK_CLR_0_CH11_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH11_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_FIELD                        (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH10_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_RANGE                        10:10
+#define APBDMA_IRQ_MASK_CLR_0_CH10_WOFFSET                      0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH10_ENABLE                       _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SHIFT                 _MK_SHIFT_CONST(9)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH9_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_RANGE                 9:9
+#define APBDMA_IRQ_MASK_CLR_0_CH9_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH9_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH8_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_RANGE                 8:8
+#define APBDMA_IRQ_MASK_CLR_0_CH8_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH8_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SHIFT                 _MK_SHIFT_CONST(7)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH7_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_RANGE                 7:7
+#define APBDMA_IRQ_MASK_CLR_0_CH7_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH7_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SHIFT                 _MK_SHIFT_CONST(6)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH6_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_RANGE                 6:6
+#define APBDMA_IRQ_MASK_CLR_0_CH6_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH6_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SHIFT                 _MK_SHIFT_CONST(5)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH5_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_RANGE                 5:5
+#define APBDMA_IRQ_MASK_CLR_0_CH5_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH5_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SHIFT                 _MK_SHIFT_CONST(4)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH4_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_RANGE                 4:4
+#define APBDMA_IRQ_MASK_CLR_0_CH4_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH4_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SHIFT                 _MK_SHIFT_CONST(3)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH3_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_RANGE                 3:3
+#define APBDMA_IRQ_MASK_CLR_0_CH3_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH3_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH2_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_RANGE                 2:2
+#define APBDMA_IRQ_MASK_CLR_0_CH2_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH1_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_RANGE                 1:1
+#define APBDMA_IRQ_MASK_CLR_0_CH1_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Clears the Mask Register
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_FIELD                 (_MK_MASK_CONST(0x1) << APBDMA_IRQ_MASK_CLR_0_CH0_SHIFT)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_RANGE                 0:0
+#define APBDMA_IRQ_MASK_CLR_0_CH0_WOFFSET                       0x0
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMA_IRQ_MASK_CLR_0_CH0_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDMA_TRIG_REG_0  
+#define APBDMA_TRIG_REG_0                       _MK_ADDR_CONST(0x28)
+#define APBDMA_TRIG_REG_0_SECURE                        0x0
+#define APBDMA_TRIG_REG_0_WORD_COUNT                    0x1
+#define APBDMA_TRIG_REG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffe)
+#define APBDMA_TRIG_REG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_READ_MASK                     _MK_MASK_CONST(0x1fffffe)
+#define APBDMA_TRIG_REG_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// EOC-15 Initiated DMA Request after transfer completion 
+#define APBDMA_TRIG_REG_0_APB_15_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMA_TRIG_REG_0_APB_15_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_15_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_15_RANGE                  24:24
+#define APBDMA_TRIG_REG_0_APB_15_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_15_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_15_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-14 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_14_SHIFT                  _MK_SHIFT_CONST(23)
+#define APBDMA_TRIG_REG_0_APB_14_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_14_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_14_RANGE                  23:23
+#define APBDMA_TRIG_REG_0_APB_14_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_14_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_14_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-13 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_13_SHIFT                  _MK_SHIFT_CONST(22)
+#define APBDMA_TRIG_REG_0_APB_13_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_13_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_13_RANGE                  22:22
+#define APBDMA_TRIG_REG_0_APB_13_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_13_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_13_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-12 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_12_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMA_TRIG_REG_0_APB_12_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_12_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_12_RANGE                  21:21
+#define APBDMA_TRIG_REG_0_APB_12_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_12_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_12_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-11 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_11_SHIFT                  _MK_SHIFT_CONST(20)
+#define APBDMA_TRIG_REG_0_APB_11_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_11_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_11_RANGE                  20:20
+#define APBDMA_TRIG_REG_0_APB_11_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_11_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_11_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-10 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_10_SHIFT                  _MK_SHIFT_CONST(19)
+#define APBDMA_TRIG_REG_0_APB_10_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_10_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_10_RANGE                  19:19
+#define APBDMA_TRIG_REG_0_APB_10_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_APB_10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_10_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_10_ACTIVE                 _MK_ENUM_CONST(1)
+
+// EOC-9 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_9_SHIFT                   _MK_SHIFT_CONST(18)
+#define APBDMA_TRIG_REG_0_APB_9_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_9_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_9_RANGE                   18:18
+#define APBDMA_TRIG_REG_0_APB_9_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_9_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_9_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_9_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_9_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-8 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_8_SHIFT                   _MK_SHIFT_CONST(17)
+#define APBDMA_TRIG_REG_0_APB_8_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_8_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_8_RANGE                   17:17
+#define APBDMA_TRIG_REG_0_APB_8_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_8_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_8_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_8_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_8_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-7 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_7_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDMA_TRIG_REG_0_APB_7_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_7_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_7_RANGE                   16:16
+#define APBDMA_TRIG_REG_0_APB_7_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_7_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_7_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-6 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_6_SHIFT                   _MK_SHIFT_CONST(15)
+#define APBDMA_TRIG_REG_0_APB_6_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_6_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_6_RANGE                   15:15
+#define APBDMA_TRIG_REG_0_APB_6_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_6_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_6_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-5 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_5_SHIFT                   _MK_SHIFT_CONST(14)
+#define APBDMA_TRIG_REG_0_APB_5_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_5_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_5_RANGE                   14:14
+#define APBDMA_TRIG_REG_0_APB_5_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_5_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_5_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-4 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_4_SHIFT                   _MK_SHIFT_CONST(13)
+#define APBDMA_TRIG_REG_0_APB_4_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_4_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_4_RANGE                   13:13
+#define APBDMA_TRIG_REG_0_APB_4_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_4_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_4_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-3 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_3_SHIFT                   _MK_SHIFT_CONST(12)
+#define APBDMA_TRIG_REG_0_APB_3_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_3_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_3_RANGE                   12:12
+#define APBDMA_TRIG_REG_0_APB_3_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_3_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_3_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-2 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_2_SHIFT                   _MK_SHIFT_CONST(11)
+#define APBDMA_TRIG_REG_0_APB_2_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_2_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_2_RANGE                   11:11
+#define APBDMA_TRIG_REG_0_APB_2_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_2_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_2_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-1 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_1_SHIFT                   _MK_SHIFT_CONST(10)
+#define APBDMA_TRIG_REG_0_APB_1_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_1_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_1_RANGE                   10:10
+#define APBDMA_TRIG_REG_0_APB_1_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_1_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_1_ACTIVE                  _MK_ENUM_CONST(1)
+
+// EOC-0 Initiated DMA Request after transfer completion
+#define APBDMA_TRIG_REG_0_APB_0_SHIFT                   _MK_SHIFT_CONST(9)
+#define APBDMA_TRIG_REG_0_APB_0_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_APB_0_SHIFT)
+#define APBDMA_TRIG_REG_0_APB_0_RANGE                   9:9
+#define APBDMA_TRIG_REG_0_APB_0_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_APB_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_APB_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_APB_0_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_APB_0_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Trigger select from Timer (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_TMR2_SHIFT                    _MK_SHIFT_CONST(8)
+#define APBDMA_TRIG_REG_0_TMR2_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_TMR2_SHIFT)
+#define APBDMA_TRIG_REG_0_TMR2_RANGE                    8:8
+#define APBDMA_TRIG_REG_0_TMR2_WOFFSET                  0x0
+#define APBDMA_TRIG_REG_0_TMR2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_TMR2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR2_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_TMR2_ACTIVE                   _MK_ENUM_CONST(1)
+
+// Trigger select from Timer (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_TMR1_SHIFT                    _MK_SHIFT_CONST(7)
+#define APBDMA_TRIG_REG_0_TMR1_FIELD                    (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_TMR1_SHIFT)
+#define APBDMA_TRIG_REG_0_TMR1_RANGE                    7:7
+#define APBDMA_TRIG_REG_0_TMR1_WOFFSET                  0x0
+#define APBDMA_TRIG_REG_0_TMR1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_TMR1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_TMR1_NOT_ACTIVE                       _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_TMR1_ACTIVE                   _MK_ENUM_CONST(1)
+
+// XRQ.B (GPIOB) (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_XRQ_B_SHIFT                   _MK_SHIFT_CONST(6)
+#define APBDMA_TRIG_REG_0_XRQ_B_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_XRQ_B_SHIFT)
+#define APBDMA_TRIG_REG_0_XRQ_B_RANGE                   6:6
+#define APBDMA_TRIG_REG_0_XRQ_B_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_XRQ_B_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_XRQ_B_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_B_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_XRQ_B_ACTIVE                  _MK_ENUM_CONST(1)
+
+// XRQ.A (GPIOA) (Hardware initiated DMA request) 
+#define APBDMA_TRIG_REG_0_XRQ_A_SHIFT                   _MK_SHIFT_CONST(5)
+#define APBDMA_TRIG_REG_0_XRQ_A_FIELD                   (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_XRQ_A_SHIFT)
+#define APBDMA_TRIG_REG_0_XRQ_A_RANGE                   5:5
+#define APBDMA_TRIG_REG_0_XRQ_A_WOFFSET                 0x0
+#define APBDMA_TRIG_REG_0_XRQ_A_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_XRQ_A_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_XRQ_A_NOT_ACTIVE                      _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_XRQ_A_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request
+#define APBDMA_TRIG_REG_0_SMP_27_SHIFT                  _MK_SHIFT_CONST(4)
+#define APBDMA_TRIG_REG_0_SMP_27_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_27_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_27_RANGE                  4:4
+#define APBDMA_TRIG_REG_0_SMP_27_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_27_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_27_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_27_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_26_SHIFT                  _MK_SHIFT_CONST(3)
+#define APBDMA_TRIG_REG_0_SMP_26_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_26_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_26_RANGE                  3:3
+#define APBDMA_TRIG_REG_0_SMP_26_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_26_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_26_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_26_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_25_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMA_TRIG_REG_0_SMP_25_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_25_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_25_RANGE                  2:2
+#define APBDMA_TRIG_REG_0_SMP_25_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_25_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_25_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_25_ACTIVE                 _MK_ENUM_CONST(1)
+
+// Semaphore requests SW initiated DMA request 
+#define APBDMA_TRIG_REG_0_SMP_24_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDMA_TRIG_REG_0_SMP_24_FIELD                  (_MK_MASK_CONST(0x1) << APBDMA_TRIG_REG_0_SMP_24_SHIFT)
+#define APBDMA_TRIG_REG_0_SMP_24_RANGE                  1:1
+#define APBDMA_TRIG_REG_0_SMP_24_WOFFSET                        0x0
+#define APBDMA_TRIG_REG_0_SMP_24_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMA_TRIG_REG_0_SMP_24_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMA_TRIG_REG_0_SMP_24_NOT_ACTIVE                     _MK_ENUM_CONST(0)
+#define APBDMA_TRIG_REG_0_SMP_24_ACTIVE                 _MK_ENUM_CONST(1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBDMA_REGS(_op_) \
+_op_(APBDMA_COMMAND_0) \
+_op_(APBDMA_STATUS_0) \
+_op_(APBDMA_REQUESTORS_TX_0) \
+_op_(APBDMA_REQUESTORS_RX_0) \
+_op_(APBDMA_CNTRL_REG_0) \
+_op_(APBDMA_IRQ_STA_CPU_0) \
+_op_(APBDMA_IRQ_STA_COP_0) \
+_op_(APBDMA_IRQ_MASK_0) \
+_op_(APBDMA_IRQ_MASK_SET_0) \
+_op_(APBDMA_IRQ_MASK_CLR_0) \
+_op_(APBDMA_TRIG_REG_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDMA     0x00000000
+
+//
+// ARAPBDMA REGISTER BANKS
+//
+
+#define APBDMA0_FIRST_REG 0x0000 // APBDMA_COMMAND_0
+#define APBDMA0_LAST_REG 0x0028 // APBDMA_TRIG_REG_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBDMA_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arapbdmachan.h b/arch/arm/mach-tegra/nv/include/ap20/arapbdmachan.h
new file mode 100644
index 000000000000..12092fabf195
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arapbdmachan.h
@@ -0,0 +1,7087 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBDMACHAN_H_INC_
+#define ___ARAPBDMACHAN_H_INC_
+
+// Register APBDMACHAN_CHANNEL_0_CSR_0  
+#define APBDMACHAN_CHANNEL_0_CSR_0                      _MK_ADDR_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_0_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+//DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_0_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_0_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_STA_0  
+#define APBDMACHAN_CHANNEL_0_STA_0                      _MK_ADDR_CONST(0x4)
+#define APBDMACHAN_CHANNEL_0_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_0_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_0_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_0_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag                                    
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 8 [0x8] 
+
+// Reserved address 12 [0xc] 
+
+// Register APBDMACHAN_CHANNEL_0_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0                  _MK_ADDR_CONST(0x10)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0                  _MK_ADDR_CONST(0x14)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_0_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0                  _MK_ADDR_CONST(0x18)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus:APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_0_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0                  _MK_ADDR_CONST(0x1c)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_0_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_1_CSR_0  
+#define APBDMACHAN_CHANNEL_1_CSR_0                      _MK_ADDR_CONST(0x20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_1_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_1_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_1_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_STA_0  
+#define APBDMACHAN_CHANNEL_1_STA_0                      _MK_ADDR_CONST(0x24)
+#define APBDMACHAN_CHANNEL_1_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_1_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_1_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_1_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Register APBDMACHAN_CHANNEL_1_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0                  _MK_ADDR_CONST(0x30)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0                  _MK_ADDR_CONST(0x34)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_1_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0                  _MK_ADDR_CONST(0x38)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_1_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0                  _MK_ADDR_CONST(0x3c)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_1_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_2_CSR_0  
+#define APBDMACHAN_CHANNEL_2_CSR_0                      _MK_ADDR_CONST(0x40)
+#define APBDMACHAN_CHANNEL_2_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_2_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_2_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_2_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_STA_0  
+#define APBDMACHAN_CHANNEL_2_STA_0                      _MK_ADDR_CONST(0x44)
+#define APBDMACHAN_CHANNEL_2_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_2_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_2_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_2_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Register APBDMACHAN_CHANNEL_2_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0                  _MK_ADDR_CONST(0x50)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0                  _MK_ADDR_CONST(0x54)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+// 0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_2_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0                  _MK_ADDR_CONST(0x58)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_2_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0                  _MK_ADDR_CONST(0x5c)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_2_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_3_CSR_0  
+#define APBDMACHAN_CHANNEL_3_CSR_0                      _MK_ADDR_CONST(0x60)
+#define APBDMACHAN_CHANNEL_3_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_3_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_3_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_3_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_STA_0  
+#define APBDMACHAN_CHANNEL_3_STA_0                      _MK_ADDR_CONST(0x64)
+#define APBDMACHAN_CHANNEL_3_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_3_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_3_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_3_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Register APBDMACHAN_CHANNEL_3_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0                  _MK_ADDR_CONST(0x70)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0                  _MK_ADDR_CONST(0x74)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff070000)
+//  0 = send interrupt to COP                                            
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_3_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0                  _MK_ADDR_CONST(0x78)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_3_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0                  _MK_ADDR_CONST(0x7c)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_3_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_4_CSR_0  
+#define APBDMACHAN_CHANNEL_4_CSR_0                      _MK_ADDR_CONST(0x80)
+#define APBDMACHAN_CHANNEL_4_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_4_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_4_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_4_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_STA_0  
+#define APBDMACHAN_CHANNEL_4_STA_0                      _MK_ADDR_CONST(0x84)
+#define APBDMACHAN_CHANNEL_4_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_4_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_4_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_4_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicates whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Register APBDMACHAN_CHANNEL_4_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0                  _MK_ADDR_CONST(0x90)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0                  _MK_ADDR_CONST(0x94)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_4_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0                  _MK_ADDR_CONST(0x98)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_4_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0                  _MK_ADDR_CONST(0x9c)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_4_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_5_CSR_0  
+#define APBDMACHAN_CHANNEL_5_CSR_0                      _MK_ADDR_CONST(0xa0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_5_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_5_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_5_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_STA_0  
+#define APBDMACHAN_CHANNEL_5_STA_0                      _MK_ADDR_CONST(0xa4)
+#define APBDMACHAN_CHANNEL_5_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_5_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_5_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_5_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Register APBDMACHAN_CHANNEL_5_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0                  _MK_ADDR_CONST(0xb0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0                  _MK_ADDR_CONST(0xb4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_5_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0                  _MK_ADDR_CONST(0xb8)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_5_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0                  _MK_ADDR_CONST(0xbc)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_5_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_6_CSR_0  
+#define APBDMACHAN_CHANNEL_6_CSR_0                      _MK_ADDR_CONST(0xc0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_6_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_6_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_6_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_STA_0  
+#define APBDMACHAN_CHANNEL_6_STA_0                      _MK_ADDR_CONST(0xc4)
+#define APBDMACHAN_CHANNEL_6_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_6_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_6_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_6_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status active or not
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Register APBDMACHAN_CHANNEL_6_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0                  _MK_ADDR_CONST(0xd0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0                  _MK_ADDR_CONST(0xd4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_6_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0                  _MK_ADDR_CONST(0xd8)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_6_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0                  _MK_ADDR_CONST(0xdc)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_6_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_7_CSR_0  
+#define APBDMACHAN_CHANNEL_7_CSR_0                      _MK_ADDR_CONST(0xe0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_7_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_7_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_7_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_STA_0  
+#define APBDMACHAN_CHANNEL_7_STA_0                      _MK_ADDR_CONST(0xe4)
+#define APBDMACHAN_CHANNEL_7_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_7_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_7_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_7_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate whether DMA Channel Status Active or not 
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Register APBDMACHAN_CHANNEL_7_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0                  _MK_ADDR_CONST(0xf0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0                  _MK_ADDR_CONST(0xf4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_7_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0                  _MK_ADDR_CONST(0xf8)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_7_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0                  _MK_ADDR_CONST(0xfc)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_7_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_8_CSR_0  
+#define APBDMACHAN_CHANNEL_8_CSR_0                      _MK_ADDR_CONST(0x100)
+#define APBDMACHAN_CHANNEL_8_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_8_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_8_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_8_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_STA_0  
+#define APBDMACHAN_CHANNEL_8_STA_0                      _MK_ADDR_CONST(0x104)
+#define APBDMACHAN_CHANNEL_8_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_8_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_8_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_8_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activate or not
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 264 [0x108] 
+
+// Reserved address 268 [0x10c] 
+
+// Register APBDMACHAN_CHANNEL_8_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0                  _MK_ADDR_CONST(0x110)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0                  _MK_ADDR_CONST(0x114)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_8_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0                  _MK_ADDR_CONST(0x118)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_8_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0                  _MK_ADDR_CONST(0x11c)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_8_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_9_CSR_0  
+#define APBDMACHAN_CHANNEL_9_CSR_0                      _MK_ADDR_CONST(0x120)
+#define APBDMACHAN_CHANNEL_9_CSR_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_9_CSR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_RESET_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_CSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_READ_MASK                    _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SHIFT                 _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_RANGE                 30:30
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_IE_EOC_ENABLE                        _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_HOLD_ENABLE                  _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SHIFT                    _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_RANGE                    28:28
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_AHB_WRITE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_DIR_AHB_READ                 _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SHIFT                   _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_RANGE                   27:27
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_MULTIPLE_BLOCK                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_ONCE_SINGLE_BLOCK                    _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SHIFT                       _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_RANGE                       26:22
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_NA1                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP24                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP25                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP26                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_SMP27                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_XRQ_A                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_XRQ_B                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_TMR1                        _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_TMR2                        _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_0                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_1                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_2                       _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_3                       _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_4                       _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_5                       _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_6                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_7                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_8                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_9                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_10                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_11                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_12                      _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_13                      _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_14                      _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_9_CSR_0_TRIG_SEL_APB_15                      _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SHIFT                   _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_RANGE                   21:21
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_FLOW_ENABLE                  _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_FIELD                        (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_RANGE                        20:16
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_CNTR_REQ                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S_2                        _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S_1                        _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SPD_I                        _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UI_I                 _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_MIPI                 _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S2_2                       _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2S2_1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_A                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_B                       _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_C                       _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SPI                  _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_AC97                 _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_ACModem                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL4B                 _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B1                        _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B2                        _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B3                        _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_SL2B4                        _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_D                       _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_UART_E                       _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2C                  _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2C2                 _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_I2C3                 _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_DVC_I2C                      _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_OWR                  _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA26                 _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA27                 _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA28                 _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA29                 _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA30                 _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_9_CSR_0_REQ_SEL_NA31                 _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_CSR_0_WCOUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_STA_0  
+#define APBDMACHAN_CHANNEL_9_STA_0                      _MK_ADDR_CONST(0x124)
+#define APBDMACHAN_CHANNEL_9_STA_0_SECURE                       0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_WORD_COUNT                   0x1
+#define APBDMACHAN_CHANNEL_9_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_RESET_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_9_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_READ_MASK                    _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_9_STA_0_WRITE_MASK                   _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activate or not
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_RANGE                    31:31
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_WAIT                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_BSY_ACTIVE                   _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_NO_INTR                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_ISE_EOC_INTR                 _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SHIFT                   _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_RANGE                   29:29
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_NO_HALT                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_HALT_HALT                    _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SHIFT                  _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_RANGE                  28:28
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_PING_INTR_STA                  _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_STA_0_PING_PONG_STA_PONG_INTR_STA                  _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_STA_0_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Register APBDMACHAN_CHANNEL_9_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0                  _MK_ADDR_CONST(0x130)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_FIELD                   (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_RANGE                   31:2
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0                  _MK_ADDR_CONST(0x134)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_CPU                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_INTR_ENB_COP                     _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+//When enabled the data going to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SHIFT                  _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_FIELD                  (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_RANGE                  26:24
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                       _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                       _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                       _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SHIFT                    _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_FIELD                    (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RANGE                    19:19
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                     _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_FIELD                       (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_RANGE                       18:16
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_NO_WRAP                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_9_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0                  _MK_ADDR_CONST(0x138)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffc)
+//APB-DMA Starting address for APB Bus: APB Base address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_FIELD                   (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_RANGE                   15:2
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_9_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0                  _MK_ADDR_CONST(0x13c)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_SECURE                   0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_WORD_COUNT                       0x1
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_RESET_VAL                        _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_RESET_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_READ_MASK                        _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_WRITE_MASK                       _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_RANGE                      30:28
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                      _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SHIFT                      _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_RANGE                      27:27
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_DISBALE                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_DATA_SWAP_ENABLE                     _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                     _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                     _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                     _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                     _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                    _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                    _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_9_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_10_CSR_0  
+#define APBDMACHAN_CHANNEL_10_CSR_0                     _MK_ADDR_CONST(0x140)
+#define APBDMACHAN_CHANNEL_10_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_10_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_10_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_10_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_STA_0  
+#define APBDMACHAN_CHANNEL_10_STA_0                     _MK_ADDR_CONST(0x144)
+#define APBDMACHAN_CHANNEL_10_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_10_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_10_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_10_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+// Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Register APBDMACHAN_CHANNEL_10_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0                 _MK_ADDR_CONST(0x150)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0                 _MK_ADDR_CONST(0x154)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_10_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0                 _MK_ADDR_CONST(0x158)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_10_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0                 _MK_ADDR_CONST(0x15c)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_10_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_11_CSR_0  
+#define APBDMACHAN_CHANNEL_11_CSR_0                     _MK_ADDR_CONST(0x160)
+#define APBDMACHAN_CHANNEL_11_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_11_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_11_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_11_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_STA_0  
+#define APBDMACHAN_CHANNEL_11_STA_0                     _MK_ADDR_CONST(0x164)
+#define APBDMACHAN_CHANNEL_11_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_11_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_11_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_11_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or waiting
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Register APBDMACHAN_CHANNEL_11_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0                 _MK_ADDR_CONST(0x170)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0                 _MK_ADDR_CONST(0x174)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff070000)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff070000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// when enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_11_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0                 _MK_ADDR_CONST(0x178)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base  address: Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_11_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0                 _MK_ADDR_CONST(0x17c)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_11_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_12_CSR_0  
+#define APBDMACHAN_CHANNEL_12_CSR_0                     _MK_ADDR_CONST(0x180)
+#define APBDMACHAN_CHANNEL_12_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_12_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_12_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_12_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_STA_0  
+#define APBDMACHAN_CHANNEL_12_STA_0                     _MK_ADDR_CONST(0x184)
+#define APBDMACHAN_CHANNEL_12_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_12_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_12_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_12_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 392 [0x188] 
+
+// Reserved address 396 [0x18c] 
+
+// Register APBDMACHAN_CHANNEL_12_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0                 _MK_ADDR_CONST(0x190)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0                 _MK_ADDR_CONST(0x194)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_12_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0                 _MK_ADDR_CONST(0x198)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_12_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0                 _MK_ADDR_CONST(0x19c)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_12_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_13_CSR_0  
+#define APBDMACHAN_CHANNEL_13_CSR_0                     _MK_ADDR_CONST(0x1a0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_13_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_13_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_13_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_STA_0  
+#define APBDMACHAN_CHANNEL_13_STA_0                     _MK_ADDR_CONST(0x1a4)
+#define APBDMACHAN_CHANNEL_13_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_13_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_13_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_13_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 424 [0x1a8] 
+
+// Reserved address 428 [0x1ac] 
+
+// Register APBDMACHAN_CHANNEL_13_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0                 _MK_ADDR_CONST(0x1b0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0                 _MK_ADDR_CONST(0x1b4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_13_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0                 _MK_ADDR_CONST(0x1b8)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_13_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0                 _MK_ADDR_CONST(0x1bc)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_13_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_14_CSR_0  
+#define APBDMACHAN_CHANNEL_14_CSR_0                     _MK_ADDR_CONST(0x1c0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_14_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_14_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_14_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_STA_0  
+#define APBDMACHAN_CHANNEL_14_STA_0                     _MK_ADDR_CONST(0x1c4)
+#define APBDMACHAN_CHANNEL_14_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_14_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_14_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_14_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 456 [0x1c8] 
+
+// Reserved address 460 [0x1cc] 
+
+// Register APBDMACHAN_CHANNEL_14_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0                 _MK_ADDR_CONST(0x1d0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0                 _MK_ADDR_CONST(0x1d4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_14_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0                 _MK_ADDR_CONST(0x1d8)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_14_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0                 _MK_ADDR_CONST(0x1dc)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_14_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_15_CSR_0  
+#define APBDMACHAN_CHANNEL_15_CSR_0                     _MK_ADDR_CONST(0x1e0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_15_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_READ_MASK                   _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xfffffffc)
+// Enables DMA channel transfer 
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Interrupts when DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SHIFT                        _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_FIELD                        (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_RANGE                        30:30
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_IE_EOC_ENABLE                       _MK_ENUM_CONST(1)
+
+// Holds this Processor until DMA Block Transfer Completes 
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_HOLD_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA Transfer Direction 1 = AHB read to APB write 0 = APB read to AHB write
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SHIFT                   _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_DIR_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_RANGE                   28:28
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_AHB_WRITE                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_DIR_AHB_READ                        _MK_ENUM_CONST(1)
+
+// Run Once or Run Multiple Mode (Allow Retriggering of this Channel) 1 = Run for One Block Transfer 0 = Run for Multiple Block Transfer
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SHIFT                  _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_RANGE                  27:27
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_MULTIPLE_BLOCK                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_ONCE_SINGLE_BLOCK                   _MK_ENUM_CONST(1)
+
+// Enable on Non-Zero Value
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_FIELD                      (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_RANGE                      26:22
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_NA1                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP24                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP25                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP26                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_SMP27                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_XRQ_A                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_XRQ_B                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_TMR1                       _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_TMR2                       _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_0                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_1                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_2                      _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_3                      _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_4                      _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_5                      _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_6                      _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_7                      _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_8                      _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_9                      _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_10                     _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_11                     _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_12                     _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_13                     _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_14                     _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_15_CSR_0_TRIG_SEL_APB_15                     _MK_ENUM_CONST(24)
+
+// Flow Control Enable (Synchronize Burst Transfers) 1 = Link to DRQ source 0 = Independent of DRQ request
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SHIFT                  _MK_SHIFT_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_RANGE                  21:21
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_FLOW_ENABLE                 _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_FIELD                       (_MK_MASK_CONST(0x1f) << APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_RANGE                       20:16
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_CNTR_REQ                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S_2                       _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S_1                       _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SPD_I                       _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UI_I                        _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_MIPI                        _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S2_2                      _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2S2_1                      _MK_ENUM_CONST(7)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_A                      _MK_ENUM_CONST(8)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_B                      _MK_ENUM_CONST(9)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_C                      _MK_ENUM_CONST(10)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SPI                 _MK_ENUM_CONST(11)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_AC97                        _MK_ENUM_CONST(12)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_ACModem                     _MK_ENUM_CONST(13)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL4B                        _MK_ENUM_CONST(14)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B1                       _MK_ENUM_CONST(15)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B2                       _MK_ENUM_CONST(16)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B3                       _MK_ENUM_CONST(17)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_SL2B4                       _MK_ENUM_CONST(18)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_D                      _MK_ENUM_CONST(19)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_UART_E                      _MK_ENUM_CONST(20)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2C                 _MK_ENUM_CONST(21)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2C2                        _MK_ENUM_CONST(22)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_I2C3                        _MK_ENUM_CONST(23)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_DVC_I2C                     _MK_ENUM_CONST(24)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_OWR                 _MK_ENUM_CONST(25)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA26                        _MK_ENUM_CONST(26)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA27                        _MK_ENUM_CONST(27)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA28                        _MK_ENUM_CONST(28)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA29                        _MK_ENUM_CONST(29)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA30                        _MK_ENUM_CONST(30)
+#define APBDMACHAN_CHANNEL_15_CSR_0_REQ_SEL_NA31                        _MK_ENUM_CONST(31)
+
+// Number of 32bit word cycles
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_FIELD                        (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_RANGE                        15:2
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_WOFFSET                      0x0
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_CSR_0_WCOUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_STA_0  
+#define APBDMACHAN_CHANNEL_15_STA_0                     _MK_ADDR_CONST(0x1e4)
+#define APBDMACHAN_CHANNEL_15_STA_0_SECURE                      0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_WORD_COUNT                  0x1
+#define APBDMACHAN_CHANNEL_15_STA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_RESET_MASK                  _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_15_STA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_READ_MASK                   _MK_MASK_CONST(0xf000fffc)
+#define APBDMACHAN_CHANNEL_15_STA_0_WRITE_MASK                  _MK_MASK_CONST(0x40000000)
+// indicate DMA Channel Status activated or not 
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SHIFT                   _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_BSY_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_RANGE                   31:31
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_WAIT                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_BSY_ACTIVE                  _MK_ENUM_CONST(1)
+
+//  Write '1' to clear the flag
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SHIFT                       _MK_SHIFT_CONST(30)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_FIELD                       (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_RANGE                       30:30
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_WOFFSET                     0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_NO_INTR                     _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_ISE_EOC_INTR                        _MK_ENUM_CONST(1)
+
+// Holding Status of Processor 
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SHIFT                  _MK_SHIFT_CONST(29)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_HALT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_RANGE                  29:29
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_NO_HALT                        _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_HALT_HALT                   _MK_ENUM_CONST(1)
+
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SHIFT                 _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_FIELD                 (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_RANGE                 28:28
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_PING_INTR_STA                 _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_STA_0_PING_PONG_STA_PONG_INTR_STA                 _MK_ENUM_CONST(1)
+
+// Current 32bit word cycles Flags set /cleared by HW
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_STA_0_COUNT_SHIFT)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_RANGE                 15:2
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_STA_0_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 488 [0x1e8] 
+
+// Reserved address 492 [0x1ec] 
+
+// Register APBDMACHAN_CHANNEL_15_AHB_PTR_0  
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0                 _MK_ADDR_CONST(0x1f0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffc)
+// APB-DMA Starting Address for AHB Bus: SW writes to  modify
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_FIELD                  (_MK_MASK_CONST(0x3fffffff) << APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_RANGE                  31:2
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_PTR_0_AHB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_AHB_SEQ_0  
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0                 _MK_ADDR_CONST(0x1f4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20000000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0xff0f0000)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0xff0f0000)
+//  0 = send interrupt to COP
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_FIELD                  (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_RANGE                  31:31
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_CPU                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_INTR_ENB_COP                    _MK_ENUM_CONST(0)
+
+// AHB Bus Width 0 = 8 bit Bus (RSVD) 1 = 16 bit Bus (RSVD) 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD)4 = 128 bit Bus (RSVD)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to AHB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+// AHB Burst Size DMA Burst Length (encoded) 4 = 1 Word (1x32bits) 5 = 4 Words (4x32bits)else = 8 Words (8x32bits) default
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SHIFT                 _MK_SHIFT_CONST(24)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_FIELD                 (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_RANGE                 26:24
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_WOFFSET                       0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_1WORDS                      _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_4WORDS                      _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_AHB_BURST_DMA_BURST_8WORDS                      _MK_ENUM_CONST(6)
+
+// 2X Double Buffering Mode (For Run-Multiple Mode with No Wrap Operations) 1 = Reload Base Address for 2X blocks (reload every other time) 0 = Reload Base Address for 1X blocks  (def) (reload each time)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_FIELD                   (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RANGE                   19:19
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_WOFFSET                 0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_1X_BLOCKS                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_DBL_BUF_RELOAD_FOR_2X_BLOCKS                    _MK_ENUM_CONST(1)
+
+// AHB Address Wrap: AHB Address wrap-around window 0=No Wrap (default) 5=Wrap on 512 word window 1=Wrap on 32 word window 6=Wrap on 1024 word window 2=Wrap on 64 word window 7=Wrap on 2048 word window 3=Wrap on 128 word window 4=Wrap on 256 word window
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_FIELD                      (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_RANGE                      18:16
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WOFFSET                    0x0
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_NO_WRAP                    _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_0N_32WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_64WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_128WORDS                   _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_256WORDS                   _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_512WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_1024WORDS                  _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_AHB_SEQ_0_WRAP_WRAP_ON_2048WORDS                  _MK_ENUM_CONST(7)
+
+
+// Register APBDMACHAN_CHANNEL_15_APB_PTR_0  
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0                 _MK_ADDR_CONST(0x1f8)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_RESET_MASK                      _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_READ_MASK                       _MK_MASK_CONST(0xfffc)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_WRITE_MASK                      _MK_MASK_CONST(0xfffc)
+// APB-DMA Starting address for APB Bus: APB Base address:Upper 16 bits are fixed at 0x7000:XXXX
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SHIFT                  _MK_SHIFT_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_FIELD                  (_MK_MASK_CONST(0x3fff) << APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_RANGE                  15:2
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_WOFFSET                        0x0
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_PTR_0_APB_BASE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDMACHAN_CHANNEL_15_APB_SEQ_0  
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0                 _MK_ADDR_CONST(0x1fc)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_SECURE                  0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_WORD_COUNT                      0x1
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_RESET_VAL                       _MK_MASK_CONST(0x20010000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_RESET_MASK                      _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_READ_MASK                       _MK_MASK_CONST(0x78070000)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_WRITE_MASK                      _MK_MASK_CONST(0x78070000)
+// 0 = 8 bit Bus 1 = 16 bit Bus 2 = 32 bit Bus (Def) 3 = 64 bit Bus (RSVD) 4 = 128 bit BUS (RSVD)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_RANGE                     30:28
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT                   _MK_MASK_CONST(0x2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_8                       _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_16                      _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_32                      _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_64                      _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_BUS_WIDTH_BUS_WIDTH_128                     _MK_ENUM_CONST(4)
+
+// When enabled the data going  to APB gets swapped as [31:0] --> {[7:0], [15:8], [23:16], [31:24] }.
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SHIFT                     _MK_SHIFT_CONST(27)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_RANGE                     27:27
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_DATA_SWAP_ENABLE                    _MK_ENUM_CONST(1)
+
+//APB Address Wrap-around Window 0 = No Wrap 1 = Wrap on 1 Word Window (def) 2 = Wrap on 2 Word Window 3 = Wrap on 4 Word Window 4 = Wrap on 8 Word Window 5 = Wrap on 16 Word Window 6 = Wrap on 32 Word Window 7 = Wrap on 64 Word Window (rsvd)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_FIELD                     (_MK_MASK_CONST(0x7) << APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SHIFT)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_RANGE                     18:16
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WOFFSET                   0x0
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_NO_WRAP                   _MK_ENUM_CONST(0)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_0N_1WORDS                    _MK_ENUM_CONST(1)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_2WORDS                    _MK_ENUM_CONST(2)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_4WORDS                    _MK_ENUM_CONST(3)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_8WORDS                    _MK_ENUM_CONST(4)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_16WORDS                   _MK_ENUM_CONST(5)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_32WORDS                   _MK_ENUM_CONST(6)
+#define APBDMACHAN_CHANNEL_15_APB_SEQ_0_APB_ADDR_WRAP_WRAP_ON_64WORDS                   _MK_ENUM_CONST(7)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBDMACHAN_REGS(_op_) \
+_op_(APBDMACHAN_CHANNEL_0_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_0_STA_0) \
+_op_(APBDMACHAN_CHANNEL_0_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_0_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_0_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_0_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_1_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_1_STA_0) \
+_op_(APBDMACHAN_CHANNEL_1_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_1_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_1_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_1_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_2_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_2_STA_0) \
+_op_(APBDMACHAN_CHANNEL_2_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_2_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_2_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_2_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_3_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_3_STA_0) \
+_op_(APBDMACHAN_CHANNEL_3_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_3_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_3_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_3_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_4_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_4_STA_0) \
+_op_(APBDMACHAN_CHANNEL_4_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_4_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_4_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_4_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_5_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_5_STA_0) \
+_op_(APBDMACHAN_CHANNEL_5_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_5_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_5_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_5_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_6_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_6_STA_0) \
+_op_(APBDMACHAN_CHANNEL_6_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_6_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_6_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_6_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_7_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_7_STA_0) \
+_op_(APBDMACHAN_CHANNEL_7_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_7_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_7_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_7_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_8_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_8_STA_0) \
+_op_(APBDMACHAN_CHANNEL_8_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_8_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_8_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_8_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_9_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_9_STA_0) \
+_op_(APBDMACHAN_CHANNEL_9_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_9_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_9_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_9_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_10_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_10_STA_0) \
+_op_(APBDMACHAN_CHANNEL_10_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_10_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_10_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_10_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_11_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_11_STA_0) \
+_op_(APBDMACHAN_CHANNEL_11_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_11_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_11_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_11_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_12_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_12_STA_0) \
+_op_(APBDMACHAN_CHANNEL_12_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_12_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_12_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_12_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_13_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_13_STA_0) \
+_op_(APBDMACHAN_CHANNEL_13_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_13_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_13_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_13_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_14_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_14_STA_0) \
+_op_(APBDMACHAN_CHANNEL_14_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_14_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_14_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_14_APB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_15_CSR_0) \
+_op_(APBDMACHAN_CHANNEL_15_STA_0) \
+_op_(APBDMACHAN_CHANNEL_15_AHB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_15_AHB_SEQ_0) \
+_op_(APBDMACHAN_CHANNEL_15_APB_PTR_0) \
+_op_(APBDMACHAN_CHANNEL_15_APB_SEQ_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDMACHAN 0x00000000
+
+//
+// ARAPBDMACHAN REGISTER BANKS
+//
+
+#define APBDMACHAN0_FIRST_REG 0x0000 // APBDMACHAN_CHANNEL_0_CSR_0
+#define APBDMACHAN0_LAST_REG 0x0004 // APBDMACHAN_CHANNEL_0_STA_0
+#define APBDMACHAN1_FIRST_REG 0x0010 // APBDMACHAN_CHANNEL_0_AHB_PTR_0
+#define APBDMACHAN1_LAST_REG 0x0024 // APBDMACHAN_CHANNEL_1_STA_0
+#define APBDMACHAN2_FIRST_REG 0x0030 // APBDMACHAN_CHANNEL_1_AHB_PTR_0
+#define APBDMACHAN2_LAST_REG 0x0044 // APBDMACHAN_CHANNEL_2_STA_0
+#define APBDMACHAN3_FIRST_REG 0x0050 // APBDMACHAN_CHANNEL_2_AHB_PTR_0
+#define APBDMACHAN3_LAST_REG 0x0064 // APBDMACHAN_CHANNEL_3_STA_0
+#define APBDMACHAN4_FIRST_REG 0x0070 // APBDMACHAN_CHANNEL_3_AHB_PTR_0
+#define APBDMACHAN4_LAST_REG 0x0084 // APBDMACHAN_CHANNEL_4_STA_0
+#define APBDMACHAN5_FIRST_REG 0x0090 // APBDMACHAN_CHANNEL_4_AHB_PTR_0
+#define APBDMACHAN5_LAST_REG 0x00a4 // APBDMACHAN_CHANNEL_5_STA_0
+#define APBDMACHAN6_FIRST_REG 0x00b0 // APBDMACHAN_CHANNEL_5_AHB_PTR_0
+#define APBDMACHAN6_LAST_REG 0x00c4 // APBDMACHAN_CHANNEL_6_STA_0
+#define APBDMACHAN7_FIRST_REG 0x00d0 // APBDMACHAN_CHANNEL_6_AHB_PTR_0
+#define APBDMACHAN7_LAST_REG 0x00e4 // APBDMACHAN_CHANNEL_7_STA_0
+#define APBDMACHAN8_FIRST_REG 0x00f0 // APBDMACHAN_CHANNEL_7_AHB_PTR_0
+#define APBDMACHAN8_LAST_REG 0x0104 // APBDMACHAN_CHANNEL_8_STA_0
+#define APBDMACHAN9_FIRST_REG 0x0110 // APBDMACHAN_CHANNEL_8_AHB_PTR_0
+#define APBDMACHAN9_LAST_REG 0x0124 // APBDMACHAN_CHANNEL_9_STA_0
+#define APBDMACHAN10_FIRST_REG 0x0130 // APBDMACHAN_CHANNEL_9_AHB_PTR_0
+#define APBDMACHAN10_LAST_REG 0x0144 // APBDMACHAN_CHANNEL_10_STA_0
+#define APBDMACHAN11_FIRST_REG 0x0150 // APBDMACHAN_CHANNEL_10_AHB_PTR_0
+#define APBDMACHAN11_LAST_REG 0x0164 // APBDMACHAN_CHANNEL_11_STA_0
+#define APBDMACHAN12_FIRST_REG 0x0170 // APBDMACHAN_CHANNEL_11_AHB_PTR_0
+#define APBDMACHAN12_LAST_REG 0x0184 // APBDMACHAN_CHANNEL_12_STA_0
+#define APBDMACHAN13_FIRST_REG 0x0190 // APBDMACHAN_CHANNEL_12_AHB_PTR_0
+#define APBDMACHAN13_LAST_REG 0x01a4 // APBDMACHAN_CHANNEL_13_STA_0
+#define APBDMACHAN14_FIRST_REG 0x01b0 // APBDMACHAN_CHANNEL_13_AHB_PTR_0
+#define APBDMACHAN14_LAST_REG 0x01c4 // APBDMACHAN_CHANNEL_14_STA_0
+#define APBDMACHAN15_FIRST_REG 0x01d0 // APBDMACHAN_CHANNEL_14_AHB_PTR_0
+#define APBDMACHAN15_LAST_REG 0x01e4 // APBDMACHAN_CHANNEL_15_STA_0
+#define APBDMACHAN16_FIRST_REG 0x01f0 // APBDMACHAN_CHANNEL_15_AHB_PTR_0
+#define APBDMACHAN16_LAST_REG 0x01fc // APBDMACHAN_CHANNEL_15_APB_SEQ_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBDMACHAN_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arapbpm.h b/arch/arm/mach-tegra/nv/include/ap20/arapbpm.h
new file mode 100644
index 000000000000..6725a85fe701
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arapbpm.h
@@ -0,0 +1,3602 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARAPBPM_H_INC_
+#define ___ARAPBPM_H_INC_
+
+// Register APBDEV_PMC_CNTRL_0  
+#define APBDEV_PMC_CNTRL_0                      _MK_ADDR_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SECURE                       0x0
+#define APBDEV_PMC_CNTRL_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_CNTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RESET_MASK                   _MK_MASK_CONST(0x7ffff)
+#define APBDEV_PMC_CNTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_READ_MASK                    _MK_MASK_CONST(0x7ffff)
+#define APBDEV_PMC_CNTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x7ffff)
+// Disable 32KHz clock to KBC 
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_RANGE                    0:0
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_CLK_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// Disable  32KHz clock to RTC                          
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SHIFT                    _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_RANGE                    1:1
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_RTC_CLK_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// Software reset to RTC
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_RTC_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_RANGE                        2:2
+#define APBDEV_PMC_CNTRL_0_RTC_RST_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_RTC_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Software reset to KBC  
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_KBC_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_RANGE                        3:3
+#define APBDEV_PMC_CNTRL_0_KBC_RST_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_KBC_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset to CAR - generates 2 clock cycle  pulse. 
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_MAIN_RST_SHIFT)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_RANGE                       4:4
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_WOFFSET                     0x0
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_MAIN_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enables latching wakeup events - stops latching   on transition from 1 to 0(sequence - set to 1,set to 0) 
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SHIFT                   _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SHIFT)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_RANGE                   5:5
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_WOFFSET                 0x0
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_LATCHWAKE_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Disable  detecting glitch on wakeup event- in default operation glitches are ignored on wakeup lines. if this bit is set to 1, glitch (event shorter than half 32khz clock, will be causing wakeup from lp0
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_RANGE                  6:6
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_WOFFSET                        0x0
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_GLITCHDET_DIS_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enables blinking counter and blink output -works only if BLINK field in DPD_PADS_ORIDE is set to 1
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SHIFT                       _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_BLINK_EN_SHIFT)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_RANGE                       7:7
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_WOFFSET                     0x0
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_BLINK_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Inverts power request polarity
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SHIFT                        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_RANGE                        8:8
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_NORMAL                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_POLARITY_INVERT                       _MK_ENUM_CONST(1)
+
+// Power request output enable. resets to tristate
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRREQ_OE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_RANGE                      9:9
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_WOFFSET                    0x0
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRREQ_OE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Inverts system clock enable polarity 
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SHIFT                        _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_RANGE                        10:10
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_NORMAL                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_POLARITY_INVERT                       _MK_ENUM_CONST(1)
+
+// Enables output of system enable clock - works only if SYS_CLK field in DPD_PADS_ORIDE is set to 1. resets to tristate
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SHIFT                      _MK_SHIFT_CONST(11)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SYSCLK_OE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_RANGE                      11:11
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_WOFFSET                    0x0
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SYSCLK_OE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Disable  power gating - global override, will override function of PWRGATE_TOGGLE register. all partitions will stay enabled. 
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SHIFT                    _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SHIFT)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_RANGE                    12:12
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_WOFFSET                  0x0
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_PWRGATE_DIS_ENABLE                   _MK_ENUM_CONST(1)
+
+// AO intitlized  purely sftw diagnostic and interpretation
+#define APBDEV_PMC_CNTRL_0_AOINIT_SHIFT                 _MK_SHIFT_CONST(13)
+#define APBDEV_PMC_CNTRL_0_AOINIT_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_AOINIT_SHIFT)
+#define APBDEV_PMC_CNTRL_0_AOINIT_RANGE                 13:13
+#define APBDEV_PMC_CNTRL_0_AOINIT_WOFFSET                       0x0
+#define APBDEV_PMC_CNTRL_0_AOINIT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_AOINIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_NOTDONE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_AOINIT_DONE                  _MK_ENUM_CONST(1)
+
+// when set causes side effect of entering lp0 after powering down cpu
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SHIFT                        _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SHIFT)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_RANGE                        14:14
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_WOFFSET                      0x0
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_SIDE_EFFECT_LP0_ENABLE                       _MK_ENUM_CONST(1)
+
+// Inverts power request polarity
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SHIFT                     _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_RANGE                     15:15
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_WOFFSET                   0x0
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_NORMAL                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_POLARITY_INVERT                    _MK_ENUM_CONST(1)
+
+// Power request output enable. resets to tristate
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_RANGE                   16:16
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_WOFFSET                 0x0
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_CPUPWRREQ_OE_ENABLE                  _MK_ENUM_CONST(1)
+
+// Inverts INTR polarity
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_SHIFT                  _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_INTR_POLARITY_SHIFT)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_RANGE                  17:17
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_WOFFSET                        0x0
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_INTR_POLARITY_ENABLE                 _MK_ENUM_CONST(1)
+
+// Fuse override
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SHIFT                  _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SHIFT)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_RANGE                  18:18
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_WOFFSET                        0x0
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CNTRL_0_FUSE_OVERRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SEC_DISABLE_0  
+#define APBDEV_PMC_SEC_DISABLE_0                        _MK_ADDR_CONST(0x4)
+#define APBDEV_PMC_SEC_DISABLE_0_SECURE                         0x0
+#define APBDEV_PMC_SEC_DISABLE_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_SEC_DISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_SEC_DISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+// disable write to secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_WRITE_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_RANGE                    0:0
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_WOFFSET                  0x0
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_WRITE_ON                       _MK_ENUM_CONST(1)
+
+// disable read  from  secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_READ_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_RANGE                     1:1
+#define APBDEV_PMC_SEC_DISABLE_0_READ_WOFFSET                   0x0
+#define APBDEV_PMC_SEC_DISABLE_0_READ_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_OFF                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_READ_ON                        _MK_ENUM_CONST(1)
+
+// disable write to bondout secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_BWRITE_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_RANGE                   2:2
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_WOFFSET                 0x0
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_BWRITE_ON                      _MK_ENUM_CONST(1)
+
+// disable read  from bondout secure registers
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_SHIFT                    _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_SEC_DISABLE_0_BREAD_SHIFT)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_RANGE                    3:3
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_WOFFSET                  0x0
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SEC_DISABLE_0_BREAD_ON                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PMC_SWRST_0  
+#define APBDEV_PMC_PMC_SWRST_0                  _MK_ADDR_CONST(0x8)
+#define APBDEV_PMC_PMC_SWRST_0_SECURE                   0x0
+#define APBDEV_PMC_PMC_SWRST_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PMC_SWRST_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+//software reset to pmc only
+#define APBDEV_PMC_PMC_SWRST_0_RST_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_PMC_SWRST_0_RST_SHIFT)
+#define APBDEV_PMC_PMC_SWRST_0_RST_RANGE                        0:0
+#define APBDEV_PMC_PMC_SWRST_0_RST_WOFFSET                      0x0
+#define APBDEV_PMC_PMC_SWRST_0_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PMC_SWRST_0_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PMC_SWRST_0_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_MASK_0  
+#define APBDEV_PMC_WAKE_MASK_0                  _MK_ADDR_CONST(0xc)
+#define APBDEV_PMC_WAKE_MASK_0_SECURE                   0x0
+#define APBDEV_PMC_WAKE_MASK_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_WAKE_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// pin  0-15  wake enable      
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_FIELD                      (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_MASK_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RANGE                      15:0
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_ENABLE                     _MK_ENUM_CONST(1)
+
+// RTC  wake enable                
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SHIFT                        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_RANGE                        16:16
+#define APBDEV_PMC_WAKE_MASK_0_RTC_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_RTC_ENABLE                       _MK_ENUM_CONST(1)
+
+// KBC  wake  enable                
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SHIFT                        _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_RANGE                        17:17
+#define APBDEV_PMC_WAKE_MASK_0_KBC_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_KBC_ENABLE                       _MK_ENUM_CONST(1)
+
+// PWR_INT wake enable               
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SHIFT                    _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_RANGE                    18:18
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_PWR_INT_ENABLE                   _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SHIFT                  _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_FIELD                  (_MK_MASK_CONST(0xf) << APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_RANGE                  22:19
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_ACTIVE_LOW                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_USB_EVENT_ACTIVE_HIGH                    _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SHIFT                  _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_FIELD                  (_MK_MASK_CONST(0xff) << APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_RANGE                  30:23
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_DISABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_EVENT_RES_ENABLE                 _MK_ENUM_CONST(1)
+
+// external reset wake enable
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SHIFT                    _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_MASK_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_RANGE                    31:31
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_DISABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_MASK_0_RESET_N_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_LVL_0  
+#define APBDEV_PMC_WAKE_LVL_0                   _MK_ADDR_CONST(0x10)
+#define APBDEV_PMC_WAKE_LVL_0_SECURE                    0x0
+#define APBDEV_PMC_WAKE_LVL_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_WAKE_LVL_0_RESET_VAL                         _MK_MASK_CONST(0x7f9fffff)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_LVL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_LVL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// pin 0-15 wake  level       
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_FIELD                       (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_LVL_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RANGE                       15:0
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_WOFFSET                     0x0
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_DEFAULT                     _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_ACTIVE_LOW                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_ACTIVE_HIGH                 _MK_ENUM_CONST(1)
+
+// RTC  wake  level               
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SHIFT                 _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_RANGE                 16:16
+#define APBDEV_PMC_WAKE_LVL_0_RTC_WOFFSET                       0x0
+#define APBDEV_PMC_WAKE_LVL_0_RTC_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_ACTIVE_LOW                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_RTC_ACTIVE_HIGH                   _MK_ENUM_CONST(1)
+
+// KBC  wake level                
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SHIFT                 _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_RANGE                 17:17
+#define APBDEV_PMC_WAKE_LVL_0_KBC_WOFFSET                       0x0
+#define APBDEV_PMC_WAKE_LVL_0_KBC_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_ACTIVE_LOW                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_KBC_ACTIVE_HIGH                   _MK_ENUM_CONST(1)
+
+// power interrupt - now pernamently tied to  bit 18            
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SHIFT                     _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_RANGE                     18:18
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_WOFFSET                   0x0
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_ACTIVE_LOW                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_PWR_INT_ACTIVE_HIGH                       _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SHIFT                   _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_FIELD                   (_MK_MASK_CONST(0xf) << APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_RANGE                   22:19
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_WOFFSET                 0x0
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_DEFAULT                 _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_ACTIVE_LOW                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_USB_EVENT_ACTIVE_HIGH                     _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SHIFT                   _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_RANGE                   30:23
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_WOFFSET                 0x0
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_DEFAULT                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_ACTIVE_LOW                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_EVENT_RES_ACTIVE_HIGH                     _MK_ENUM_CONST(1)
+
+// external reset wake level (low active!)              
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SHIFT                     _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_LVL_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_RANGE                     31:31
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_WOFFSET                   0x0
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_ACTIVE_LOW                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_LVL_0_RESET_N_ACTIVE_HIGH                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_WAKE_STATUS_0  
+#define APBDEV_PMC_WAKE_STATUS_0                        _MK_ADDR_CONST(0x14)
+#define APBDEV_PMC_WAKE_STATUS_0_SECURE                         0x0
+#define APBDEV_PMC_WAKE_STATUS_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_WAKE_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// pin 0-15 wake    
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_FIELD                    (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_STATUS_0_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RANGE                    15:0
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_WOFFSET                  0x0
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_NOT_SET                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_SET                      _MK_ENUM_CONST(1)
+
+// RTC wake                
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_RTC_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_RANGE                      16:16
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_NOT_SET                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_RTC_SET                        _MK_ENUM_CONST(1)
+
+// KBC wake              
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_KBC_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_RANGE                      17:17
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_WOFFSET                    0x0
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_NOT_SET                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_KBC_SET                        _MK_ENUM_CONST(1)
+
+// power interrupt            
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SHIFT                  _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_RANGE                  18:18
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_NOT_SET                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_PWR_INT_SET                    _MK_ENUM_CONST(1)
+
+// USB wake events
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SHIFT                        _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_FIELD                        (_MK_MASK_CONST(0xf) << APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_RANGE                        22:19
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_NOT_SET                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_USB_EVENT_SET                  _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SHIFT                        _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_FIELD                        (_MK_MASK_CONST(0xff) << APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_RANGE                        30:23
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_WOFFSET                      0x0
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_NOT_SET                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_EVENT_RES_SET                  _MK_ENUM_CONST(1)
+
+// external reset            
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SHIFT                  _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_WAKE_STATUS_0_RESET_N_SHIFT)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_RANGE                  31:31
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_WOFFSET                        0x0
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_NOT_SET                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_WAKE_STATUS_0_RESET_N_SET                    _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SW_WAKE_STATUS_0  
+#define APBDEV_PMC_SW_WAKE_STATUS_0                     _MK_ADDR_CONST(0x18)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_SECURE                      0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// pin 0-15 wake    
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_FIELD                 (_MK_MASK_CONST(0xffff) << APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RANGE                 15:0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_WOFFSET                       0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_ENABLE                        _MK_ENUM_CONST(1)
+
+// RTC wake                
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_RANGE                   16:16
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_WOFFSET                 0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RTC_ENABLE                  _MK_ENUM_CONST(1)
+
+// KBC wake              
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SHIFT                   _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_RANGE                   17:17
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_WOFFSET                 0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_KBC_ENABLE                  _MK_ENUM_CONST(1)
+
+// power interrupt            
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SHIFT                       _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_RANGE                       18:18
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_WOFFSET                     0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_NOT_SET                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_PWR_INT_SET                 _MK_ENUM_CONST(1)
+
+// USB wake events
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SHIFT                     _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_FIELD                     (_MK_MASK_CONST(0xf) << APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_RANGE                     22:19
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_WOFFSET                   0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_NOT_SET                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_USB_EVENT_SET                       _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SHIFT                     _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_FIELD                     (_MK_MASK_CONST(0xff) << APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_RANGE                     30:23
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_WOFFSET                   0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_NOT_SET                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_EVENT_RES_SET                       _MK_ENUM_CONST(1)
+
+// external reset            
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SHIFT                       _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SHIFT)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_RANGE                       31:31
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_WOFFSET                     0x0
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_NOT_SET                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_SW_WAKE_STATUS_0_RESET_N_SET                 _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_PADS_ORIDE_0  
+#define APBDEV_PMC_DPD_PADS_ORIDE_0                     _MK_ADDR_CONST(0x1c)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SECURE                      0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_RESET_VAL                   _MK_MASK_CONST(0x200000)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_RESET_MASK                  _MK_MASK_CONST(0x3ffffff)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_READ_MASK                   _MK_MASK_CONST(0x3ffffff)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x3ffffff)
+//override dpd idle state with column 0 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_RANGE                      0:0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL0_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 1 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_RANGE                      1:1
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL1_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 2 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_RANGE                      2:2
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL2_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 3 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_RANGE                      3:3
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL3_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 4 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_RANGE                      4:4
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL4_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 5 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SHIFT                      _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_RANGE                      5:5
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL5_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 6 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SHIFT                      _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_RANGE                      6:6
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL6_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 7 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SHIFT                      _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_RANGE                      7:7
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL7_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 8 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_RANGE                      8:8
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL8_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 9 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_RANGE                      9:9
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL9_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 10 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SHIFT                     _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_RANGE                     10:10
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL10_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 11 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SHIFT                     _MK_SHIFT_CONST(11)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_RANGE                     11:11
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL11_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with column 12 output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SHIFT                     _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_RANGE                     12:12
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_COL12_ENABLE                    _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 0  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SHIFT                      _MK_SHIFT_CONST(13)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_RANGE                      13:13
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW0_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 1  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SHIFT                      _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_RANGE                      14:14
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW1_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 2  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_RANGE                      15:15
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW2_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 3  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_RANGE                      16:16
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW3_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 4  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SHIFT                      _MK_SHIFT_CONST(17)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_RANGE                      17:17
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW4_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 5  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SHIFT                      _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_RANGE                      18:18
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW5_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 6  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SHIFT                      _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_RANGE                      19:19
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW6_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with blink ouptut
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SHIFT                 _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_RANGE                 20:20
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_WOFFSET                       0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_BLINK_ENABLE                        _MK_ENUM_CONST(1)
+
+//override dpd idle state with column with sys_clk_request output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT                       _MK_SHIFT_CONST(21)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_RANGE                       21:21
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_WOFFSET                     0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_SYS_CLK_ENABLE                      _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 7  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SHIFT                      _MK_SHIFT_CONST(22)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_RANGE                      22:22
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW7_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 8  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SHIFT                      _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_RANGE                      23:23
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW8_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 9  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SHIFT                      _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_RANGE                      24:24
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_WOFFSET                    0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW9_ENABLE                     _MK_ENUM_CONST(1)
+
+//override dpd idle state with row 10  output
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SHIFT                     _MK_SHIFT_CONST(25)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SHIFT)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_RANGE                     25:25
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_WOFFSET                   0x0
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_PADS_ORIDE_0_KBC_ROW10_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_SAMPLE_0  
+#define APBDEV_PMC_DPD_SAMPLE_0                 _MK_ADDR_CONST(0x20)
+#define APBDEV_PMC_DPD_SAMPLE_0_SECURE                  0x0
+#define APBDEV_PMC_DPD_SAMPLE_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_DPD_SAMPLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+// will set sampling of pads value
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_SAMPLE_0_ON_SHIFT)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_RANGE                        0:0
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_WOFFSET                      0x0
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_SAMPLE_0_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DPD_ENABLE_0  
+#define APBDEV_PMC_DPD_ENABLE_0                 _MK_ADDR_CONST(0x24)
+#define APBDEV_PMC_DPD_ENABLE_0_SECURE                  0x0
+#define APBDEV_PMC_DPD_ENABLE_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_DPD_ENABLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+// will set sampling of pads value
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_DPD_ENABLE_0_ON_SHIFT)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_RANGE                        0:0
+#define APBDEV_PMC_DPD_ENABLE_0_ON_WOFFSET                      0x0
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DPD_ENABLE_0_ON_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGATE_TIMER_OFF_0  
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0                  _MK_ADDR_CONST(0x28)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SECURE                   0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RESET_VAL                        _MK_MASK_CONST(0xeca97531)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// timer value for rail 0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_RANGE                      3:0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 1
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_RANGE                      7:4
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_DEFAULT                    _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 2
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SHIFT                      _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_RANGE                      11:8
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_DEFAULT                    _MK_MASK_CONST(0x5)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 3
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SHIFT                      _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_RANGE                      15:12
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_DEFAULT                    _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 4
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SHIFT                      _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_RANGE                      19:16
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_DEFAULT                    _MK_MASK_CONST(0x9)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 5
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SHIFT                      _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_RANGE                      23:20
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_DEFAULT                    _MK_MASK_CONST(0xa)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 6
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SHIFT                      _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_RANGE                      27:24
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_DEFAULT                    _MK_MASK_CONST(0xc)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// timer value for rail 7
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SHIFT                      _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_FIELD                      (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_RANGE                      31:28
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_WOFFSET                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_DEFAULT                    _MK_MASK_CONST(0xe)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_OFF_0_RAIL7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PWRGATE_TIMER_ON_0  
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0                   _MK_ADDR_CONST(0x2c)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_SECURE                    0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RESET_VAL                         _MK_MASK_CONST(0xeca97531)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// timer value for rail 0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_RANGE                       3:0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 1
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_RANGE                       7:4
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_DEFAULT                     _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 2
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SHIFT                       _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_RANGE                       11:8
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_DEFAULT                     _MK_MASK_CONST(0x5)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 3
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SHIFT                       _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_RANGE                       15:12
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_DEFAULT                     _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 4
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SHIFT                       _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_RANGE                       19:16
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_DEFAULT                     _MK_MASK_CONST(0x9)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 5
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SHIFT                       _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_RANGE                       23:20
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_DEFAULT                     _MK_MASK_CONST(0xa)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 6
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SHIFT                       _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_RANGE                       27:24
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_DEFAULT                     _MK_MASK_CONST(0xc)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// timer value for rail 7
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SHIFT                       _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_FIELD                       (_MK_MASK_CONST(0xf) << APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SHIFT)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_RANGE                       31:28
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_WOFFSET                     0x0
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_DEFAULT                     _MK_MASK_CONST(0xe)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TIMER_ON_0_RAIL7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PWRGATE_TOGGLE_0  
+#define APBDEV_PMC_PWRGATE_TOGGLE_0                     _MK_ADDR_CONST(0x30)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_SECURE                      0x0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_RESET_MASK                  _MK_MASK_CONST(0x107)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_READ_MASK                   _MK_MASK_CONST(0x107)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_WRITE_MASK                  _MK_MASK_CONST(0x107)
+//id of partition to be toggled 
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_FIELD                        (_MK_MASK_CONST(0x7) << APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SHIFT)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_RANGE                        2:0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_WOFFSET                      0x0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_CP                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_TD                   _MK_ENUM_CONST(1)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_VE                   _MK_ENUM_CONST(2)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_VDE                  _MK_ENUM_CONST(4)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_PCX                  _MK_ENUM_CONST(3)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_L2C                  _MK_ENUM_CONST(5)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_PARTID_MPE                  _MK_ENUM_CONST(6)
+
+//start power down/up
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SHIFT                 _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_TOGGLE_0_START_SHIFT)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_RANGE                 8:8
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_WOFFSET                       0x0
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_DISABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_TOGGLE_0_START_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_REMOVE_CLAMPING_CMD_0  
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0                        _MK_ADDR_CONST(0x34)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SECURE                         0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_RESET_MASK                     _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_READ_MASK                      _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_WRITE_MASK                     _MK_MASK_CONST(0x7f)
+//remove clamping to CPU
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_RANGE                      0:0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_CPU_ENABLE                     _MK_ENUM_CONST(1)
+
+//remove clamping to TD
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SHIFT                       _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_RANGE                       1:1
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_WOFFSET                     0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_TD_ENABLE                      _MK_ENUM_CONST(1)
+
+//remove clamping to VE
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SHIFT                       _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_RANGE                       2:2
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_WOFFSET                     0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VE_ENABLE                      _MK_ENUM_CONST(1)
+
+//remove clamping to VDE
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SHIFT                      _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_RANGE                      3:3
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_VDE_ENABLE                     _MK_ENUM_CONST(1)
+
+//remove clamping to PCX
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SHIFT                      _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_RANGE                      4:4
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_PCX_ENABLE                     _MK_ENUM_CONST(1)
+
+//remove clamping to L2_CACHE
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SHIFT                      _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_RANGE                      5:5
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_L2C_ENABLE                     _MK_ENUM_CONST(1)
+
+//remove clamping to MPE_CACHE
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SHIFT                      _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SHIFT)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_RANGE                      6:6
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_WOFFSET                    0x0
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_REMOVE_CLAMPING_CMD_0_MPE_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGATE_STATUS_0  
+#define APBDEV_PMC_PWRGATE_STATUS_0                     _MK_ADDR_CONST(0x38)
+#define APBDEV_PMC_PWRGATE_STATUS_0_SECURE                      0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_PWRGATE_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGATE_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGATE_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGATE_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+//status of CPU partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_CPU_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_RANGE                   0:0
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_CPU_ON                      _MK_ENUM_CONST(1)
+
+//status of TD  Partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SHIFT                    _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_TD_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_RANGE                    1:1
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_WOFFSET                  0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_TD_ON                       _MK_ENUM_CONST(1)
+
+//status of VE  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SHIFT                    _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_VE_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_RANGE                    2:2
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_WOFFSET                  0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_OFF                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VE_ON                       _MK_ENUM_CONST(1)
+
+//status of VDE  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_SHIFT                   _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_VDE_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_RANGE                   4:4
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_VDE_ON                      _MK_ENUM_CONST(1)
+
+//status of PCX  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_SHIFT                   _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_PCX_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_RANGE                   3:3
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_PCX_ON                      _MK_ENUM_CONST(1)
+
+//status of L2C  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_SHIFT                   _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_L2C_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_RANGE                   5:5
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_L2C_ON                      _MK_ENUM_CONST(1)
+
+//status of MPE  partition
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_SHIFT                   _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWRGATE_STATUS_0_MPE_SHIFT)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_RANGE                   6:6
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_OFF                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWRGATE_STATUS_0_MPE_ON                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWRGOOD_TIMER_0  
+#define APBDEV_PMC_PWRGOOD_TIMER_0                      _MK_ADDR_CONST(0x3c)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_SECURE                       0x0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_PWRGOOD_TIMER_0_RESET_VAL                    _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_READ_MASK                    _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_WRITE_MASK                   _MK_MASK_CONST(0xffff)
+// pmu timer * 32
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_FIELD                        (_MK_MASK_CONST(0xff) << APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SHIFT)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_RANGE                        7:0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_WOFFSET                      0x0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_DEFAULT                      _MK_MASK_CONST(0x7f)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_PMU_TIM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// xtal timer * 32
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SHIFT                   _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SHIFT)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_RANGE                   15:8
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_WOFFSET                 0x0
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWRGOOD_TIMER_0_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BLINK_TIMER_0  
+#define APBDEV_PMC_BLINK_TIMER_0                        _MK_ADDR_CONST(0x40)
+#define APBDEV_PMC_BLINK_TIMER_0_SECURE                         0x0
+#define APBDEV_PMC_BLINK_TIMER_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_BLINK_TIMER_0_RESET_VAL                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BLINK_TIMER_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// time on 
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_FIELD                  (_MK_MASK_CONST(0x7fff) << APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_RANGE                  14:0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_WOFFSET                        0x0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_DEFAULT                        _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x7fff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// if 0 32khz clock 
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SHIFT                      _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_RANGE                      15:15
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_WOFFSET                    0x0
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// time off         
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SHIFT                 _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_FIELD                 (_MK_MASK_CONST(0xffff) << APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SHIFT)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_RANGE                 31:16
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_WOFFSET                       0x0
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_DEFAULT                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_NO_IOPOWER_0  
+#define APBDEV_PMC_NO_IOPOWER_0                 _MK_ADDR_CONST(0x44)
+#define APBDEV_PMC_NO_IOPOWER_0_SECURE                  0x0
+#define APBDEV_PMC_NO_IOPOWER_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_NO_IOPOWER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
+#define APBDEV_PMC_NO_IOPOWER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
+#define APBDEV_PMC_NO_IOPOWER_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff)
+//rail ao IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_SYS_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_RANGE                       0:0
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_SYS_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail at3 IOs 
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_SHIFT                      _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_NAND_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_RANGE                      1:1
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_WOFFSET                    0x0
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_NAND_ENABLE                     _MK_ENUM_CONST(1)
+
+//rail dbg IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_UART_SHIFT                      _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_UART_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_RANGE                      2:2
+#define APBDEV_PMC_NO_IOPOWER_0_UART_WOFFSET                    0x0
+#define APBDEV_PMC_NO_IOPOWER_0_UART_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_UART_ENABLE                     _MK_ENUM_CONST(1)
+
+//rail dlcd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_BB_SHIFT                        _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_BB_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_RANGE                        3:3
+#define APBDEV_PMC_NO_IOPOWER_0_BB_WOFFSET                      0x0
+#define APBDEV_PMC_NO_IOPOWER_0_BB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_BB_ENABLE                       _MK_ENUM_CONST(1)
+
+//rail dvi IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_VI_SHIFT                        _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_VI_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_RANGE                        4:4
+#define APBDEV_PMC_NO_IOPOWER_0_VI_WOFFSET                      0x0
+#define APBDEV_PMC_NO_IOPOWER_0_VI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_VI_ENABLE                       _MK_ENUM_CONST(1)
+
+//rail i2s IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_SHIFT                     _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_AUDIO_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_RANGE                     5:5
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_WOFFSET                   0x0
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_DISABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_AUDIO_ENABLE                    _MK_ENUM_CONST(1)
+
+//rail lcd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SHIFT                       _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_LCD_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_RANGE                       6:6
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_LCD_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail mem IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SHIFT                       _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_MEM_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_RANGE                       7:7
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_WOFFSET                     0x0
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_DISABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_MEM_ENABLE                      _MK_ENUM_CONST(1)
+
+//rail sd IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SHIFT                        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_SD_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_RANGE                        8:8
+#define APBDEV_PMC_NO_IOPOWER_0_SD_WOFFSET                      0x0
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_DISABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_SD_ENABLE                       _MK_ENUM_CONST(1)
+
+//rail mipi IOs   
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SHIFT                      _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_NO_IOPOWER_0_MIPI_SHIFT)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_RANGE                      9:9
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_WOFFSET                    0x0
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_DISABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_NO_IOPOWER_0_MIPI_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWR_DET_0  
+#define APBDEV_PMC_PWR_DET_0                    _MK_ADDR_CONST(0x48)
+#define APBDEV_PMC_PWR_DET_0_SECURE                     0x0
+#define APBDEV_PMC_PWR_DET_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_PWR_DET_0_RESET_VAL                  _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_RESET_MASK                         _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
+//rail ao IOs   
+#define APBDEV_PMC_PWR_DET_0_SYS_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_SYS_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_SYS_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_SYS_RANGE                  0:0
+#define APBDEV_PMC_PWR_DET_0_SYS_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_SYS_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SYS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SYS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SYS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SYS_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_SYS_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail at3 IOs 
+#define APBDEV_PMC_PWR_DET_0_NAND_SHIFT                 _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PWR_DET_0_NAND_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_NAND_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_NAND_RANGE                 1:1
+#define APBDEV_PMC_PWR_DET_0_NAND_WOFFSET                       0x0
+#define APBDEV_PMC_PWR_DET_0_NAND_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_NAND_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_NAND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_NAND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_NAND_ENABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_NAND_DISABLE                       _MK_ENUM_CONST(1)
+
+//rail dbg IOs   
+#define APBDEV_PMC_PWR_DET_0_UART_SHIFT                 _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PWR_DET_0_UART_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_UART_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_UART_RANGE                 2:2
+#define APBDEV_PMC_PWR_DET_0_UART_WOFFSET                       0x0
+#define APBDEV_PMC_PWR_DET_0_UART_DEFAULT                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_UART_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_UART_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_UART_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_UART_ENABLE                        _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_UART_DISABLE                       _MK_ENUM_CONST(1)
+
+//rail dlcd IOs   
+#define APBDEV_PMC_PWR_DET_0_BB_SHIFT                   _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_PWR_DET_0_BB_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_BB_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_BB_RANGE                   3:3
+#define APBDEV_PMC_PWR_DET_0_BB_WOFFSET                 0x0
+#define APBDEV_PMC_PWR_DET_0_BB_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_BB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_BB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_BB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_BB_ENABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_BB_DISABLE                 _MK_ENUM_CONST(1)
+
+//rail dvi IOs   
+#define APBDEV_PMC_PWR_DET_0_VI_SHIFT                   _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWR_DET_0_VI_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_VI_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_VI_RANGE                   4:4
+#define APBDEV_PMC_PWR_DET_0_VI_WOFFSET                 0x0
+#define APBDEV_PMC_PWR_DET_0_VI_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_VI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_VI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_VI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_VI_ENABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_VI_DISABLE                 _MK_ENUM_CONST(1)
+
+//rail i2s IOs   
+#define APBDEV_PMC_PWR_DET_0_AUDIO_SHIFT                        _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_AUDIO_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_RANGE                        5:5
+#define APBDEV_PMC_PWR_DET_0_AUDIO_WOFFSET                      0x0
+#define APBDEV_PMC_PWR_DET_0_AUDIO_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_AUDIO_DISABLE                      _MK_ENUM_CONST(1)
+
+//rail lcd IOs   
+#define APBDEV_PMC_PWR_DET_0_LCD_SHIFT                  _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_PWR_DET_0_LCD_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_LCD_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_LCD_RANGE                  6:6
+#define APBDEV_PMC_PWR_DET_0_LCD_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_LCD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_LCD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_LCD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_LCD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_LCD_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_LCD_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail mem IOs   
+#define APBDEV_PMC_PWR_DET_0_MEM_SHIFT                  _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_PWR_DET_0_MEM_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_MEM_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_MEM_RANGE                  7:7
+#define APBDEV_PMC_PWR_DET_0_MEM_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_0_MEM_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_MEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_MEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_MEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_MEM_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_MEM_DISABLE                        _MK_ENUM_CONST(1)
+
+//rail sd IOs   
+#define APBDEV_PMC_PWR_DET_0_SD_SHIFT                   _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWR_DET_0_SD_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_0_SD_SHIFT)
+#define APBDEV_PMC_PWR_DET_0_SD_RANGE                   8:8
+#define APBDEV_PMC_PWR_DET_0_SD_WOFFSET                 0x0
+#define APBDEV_PMC_PWR_DET_0_SD_DEFAULT                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_0_SD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_0_SD_ENABLE                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_0_SD_DISABLE                 _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PWR_DET_LATCH_0  
+#define APBDEV_PMC_PWR_DET_LATCH_0                      _MK_ADDR_CONST(0x4c)
+#define APBDEV_PMC_PWR_DET_LATCH_0_SECURE                       0x0
+#define APBDEV_PMC_PWR_DET_LATCH_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_PWR_DET_LATCH_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+//power detect latch, latches value as long set to 1  
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SHIFT)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_RANGE                  0:0
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_WOFFSET                        0x0
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_ENABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_LATCH_0_LATCH_DISABLE                        _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_SCRATCH0_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH0_0                   _MK_ADDR_CONST(0x50)
+#define APBDEV_PMC_SCRATCH0_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH0_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH0_0_SCRATCH0_SHIFT)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH0_0_SCRATCH0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH1_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH1_0                   _MK_ADDR_CONST(0x54)
+#define APBDEV_PMC_SCRATCH1_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH1_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH1_0_SCRATCH1_SHIFT)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH1_0_SCRATCH1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH2_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH2_0                   _MK_ADDR_CONST(0x58)
+#define APBDEV_PMC_SCRATCH2_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH2_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH2_0_SCRATCH2_SHIFT)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH2_0_SCRATCH2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH3_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH3_0                   _MK_ADDR_CONST(0x5c)
+#define APBDEV_PMC_SCRATCH3_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH3_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH3_0_SCRATCH3_SHIFT)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH3_0_SCRATCH3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH4_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH4_0                   _MK_ADDR_CONST(0x60)
+#define APBDEV_PMC_SCRATCH4_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH4_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH4_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH4_0_SCRATCH4_SHIFT)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH4_0_SCRATCH4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH5_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH5_0                   _MK_ADDR_CONST(0x64)
+#define APBDEV_PMC_SCRATCH5_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH5_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH5_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH5_0_SCRATCH5_SHIFT)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH5_0_SCRATCH5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH6_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH6_0                   _MK_ADDR_CONST(0x68)
+#define APBDEV_PMC_SCRATCH6_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH6_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH6_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH6_0_SCRATCH6_SHIFT)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH6_0_SCRATCH6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH7_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH7_0                   _MK_ADDR_CONST(0x6c)
+#define APBDEV_PMC_SCRATCH7_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH7_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH7_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH7_0_SCRATCH7_SHIFT)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH7_0_SCRATCH7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH8_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH8_0                   _MK_ADDR_CONST(0x70)
+#define APBDEV_PMC_SCRATCH8_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH8_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH8_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH8_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH8_0_SCRATCH8_SHIFT)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH8_0_SCRATCH8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH9_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH9_0                   _MK_ADDR_CONST(0x74)
+#define APBDEV_PMC_SCRATCH9_0_SECURE                    0x0
+#define APBDEV_PMC_SCRATCH9_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_SCRATCH9_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH9_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_FIELD                    (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH9_0_SCRATCH9_SHIFT)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_RANGE                    31:0
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_WOFFSET                  0x0
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH9_0_SCRATCH9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH10_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH10_0                  _MK_ADDR_CONST(0x78)
+#define APBDEV_PMC_SCRATCH10_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH10_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH10_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH10_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH10_0_SCRATCH10_SHIFT)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH10_0_SCRATCH10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH11_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH11_0                  _MK_ADDR_CONST(0x7c)
+#define APBDEV_PMC_SCRATCH11_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH11_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH11_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH11_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH11_0_SCRATCH11_SHIFT)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH11_0_SCRATCH11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH12_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH12_0                  _MK_ADDR_CONST(0x80)
+#define APBDEV_PMC_SCRATCH12_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH12_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH12_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH12_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH12_0_SCRATCH12_SHIFT)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH12_0_SCRATCH12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH13_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH13_0                  _MK_ADDR_CONST(0x84)
+#define APBDEV_PMC_SCRATCH13_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH13_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH13_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH13_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH13_0_SCRATCH13_SHIFT)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH13_0_SCRATCH13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH14_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH14_0                  _MK_ADDR_CONST(0x88)
+#define APBDEV_PMC_SCRATCH14_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH14_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH14_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH14_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH14_0_SCRATCH14_SHIFT)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH14_0_SCRATCH14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH15_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH15_0                  _MK_ADDR_CONST(0x8c)
+#define APBDEV_PMC_SCRATCH15_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH15_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH15_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH15_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH15_0_SCRATCH15_SHIFT)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH15_0_SCRATCH15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH16_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH16_0                  _MK_ADDR_CONST(0x90)
+#define APBDEV_PMC_SCRATCH16_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH16_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH16_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH16_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH16_0_SCRATCH16_SHIFT)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH16_0_SCRATCH16_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH17_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH17_0                  _MK_ADDR_CONST(0x94)
+#define APBDEV_PMC_SCRATCH17_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH17_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH17_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH17_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH17_0_SCRATCH17_SHIFT)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH17_0_SCRATCH17_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH18_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH18_0                  _MK_ADDR_CONST(0x98)
+#define APBDEV_PMC_SCRATCH18_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH18_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH18_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH18_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH18_0_SCRATCH18_SHIFT)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH18_0_SCRATCH18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH19_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH19_0                  _MK_ADDR_CONST(0x9c)
+#define APBDEV_PMC_SCRATCH19_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH19_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH19_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH19_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH19_0_SCRATCH19_SHIFT)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH19_0_SCRATCH19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH20_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH20_0                  _MK_ADDR_CONST(0xa0)
+#define APBDEV_PMC_SCRATCH20_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH20_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH20_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH20_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH20_0_SCRATCH20_SHIFT)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH20_0_SCRATCH20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH21_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH21_0                  _MK_ADDR_CONST(0xa4)
+#define APBDEV_PMC_SCRATCH21_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH21_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH21_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH21_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH21_0_SCRATCH21_SHIFT)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH21_0_SCRATCH21_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH22_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH22_0                  _MK_ADDR_CONST(0xa8)
+#define APBDEV_PMC_SCRATCH22_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH22_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH22_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH22_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH22_0_SCRATCH22_SHIFT)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH22_0_SCRATCH22_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH23_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH23_0                  _MK_ADDR_CONST(0xac)
+#define APBDEV_PMC_SCRATCH23_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH23_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH23_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH23_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH23_0_SCRATCH23_SHIFT)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH23_0_SCRATCH23_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH0_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH0_0                    _MK_ADDR_CONST(0xb0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH0_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH0_0_SECURE_SCRATCH0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH1_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH1_0                    _MK_ADDR_CONST(0xb4)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH1_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH1_0_SECURE_SCRATCH1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH2_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH2_0                    _MK_ADDR_CONST(0xb8)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH2_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH2_0_SECURE_SCRATCH2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH3_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH3_0                    _MK_ADDR_CONST(0xbc)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH3_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH3_0_SECURE_SCRATCH3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH4_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH4_0                    _MK_ADDR_CONST(0xc0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH4_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH4_0_SECURE_SCRATCH4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SECURE_SCRATCH5_0  // Secure scratch register
+#define APBDEV_PMC_SECURE_SCRATCH5_0                    _MK_ADDR_CONST(0xc4)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE                     0x0
+#define APBDEV_PMC_SECURE_SCRATCH5_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_SECURE_SCRATCH5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SHIFT)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_RANGE                      31:0
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_WOFFSET                    0x0
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SECURE_SCRATCH5_0_SECURE_SCRATCH5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_CPUPWRGOOD_TIMER_0  
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0                   _MK_ADDR_CONST(0xc8)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_SECURE                    0x0
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_RESET_VAL                         _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// timer data
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SHIFT)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_RANGE                        31:0
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_WOFFSET                      0x0
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_DEFAULT                      _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWRGOOD_TIMER_0_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_CPUPWROFF_TIMER_0  
+#define APBDEV_PMC_CPUPWROFF_TIMER_0                    _MK_ADDR_CONST(0xcc)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_SECURE                     0x0
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_RESET_VAL                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// timer data
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_FIELD                 (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SHIFT)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_RANGE                 31:0
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_WOFFSET                       0x0
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_DEFAULT                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CPUPWROFF_TIMER_0_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PG_MASK_0  
+#define APBDEV_PMC_PG_MASK_0                    _MK_ADDR_CONST(0xd0)
+#define APBDEV_PMC_PG_MASK_0_SECURE                     0x0
+#define APBDEV_PMC_PG_MASK_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_PG_MASK_0_RESET_VAL                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PG_MASK_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PG_MASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_PG_MASK_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Mask TD rail
+#define APBDEV_PMC_PG_MASK_0_TD_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PG_MASK_0_TD_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_PG_MASK_0_TD_SHIFT)
+#define APBDEV_PMC_PG_MASK_0_TD_RANGE                   7:0
+#define APBDEV_PMC_PG_MASK_0_TD_WOFFSET                 0x0
+#define APBDEV_PMC_PG_MASK_0_TD_DEFAULT                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_TD_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_TD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_TD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Mask VE rail
+#define APBDEV_PMC_PG_MASK_0_VE_SHIFT                   _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PG_MASK_0_VE_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_PG_MASK_0_VE_SHIFT)
+#define APBDEV_PMC_PG_MASK_0_VE_RANGE                   15:8
+#define APBDEV_PMC_PG_MASK_0_VE_WOFFSET                 0x0
+#define APBDEV_PMC_PG_MASK_0_VE_DEFAULT                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_VE_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_VE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_VE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Mask VDE rail
+#define APBDEV_PMC_PG_MASK_0_VD_SHIFT                   _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_PG_MASK_0_VD_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_PG_MASK_0_VD_SHIFT)
+#define APBDEV_PMC_PG_MASK_0_VD_RANGE                   23:16
+#define APBDEV_PMC_PG_MASK_0_VD_WOFFSET                 0x0
+#define APBDEV_PMC_PG_MASK_0_VD_DEFAULT                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_VD_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_VD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_VD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Mask PCX rail
+#define APBDEV_PMC_PG_MASK_0_PX_SHIFT                   _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_PG_MASK_0_PX_FIELD                   (_MK_MASK_CONST(0xff) << APBDEV_PMC_PG_MASK_0_PX_SHIFT)
+#define APBDEV_PMC_PG_MASK_0_PX_RANGE                   31:24
+#define APBDEV_PMC_PG_MASK_0_PX_WOFFSET                 0x0
+#define APBDEV_PMC_PG_MASK_0_PX_DEFAULT                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_PX_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_0_PX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_0_PX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PG_MASK_1_0  
+#define APBDEV_PMC_PG_MASK_1_0                  _MK_ADDR_CONST(0xd4)
+#define APBDEV_PMC_PG_MASK_1_0_SECURE                   0x0
+#define APBDEV_PMC_PG_MASK_1_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PG_MASK_1_0_RESET_VAL                        _MK_MASK_CONST(0xff01)
+#define APBDEV_PMC_PG_MASK_1_0_RESET_MASK                       _MK_MASK_CONST(0xff01)
+#define APBDEV_PMC_PG_MASK_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_1_0_READ_MASK                        _MK_MASK_CONST(0xff01)
+#define APBDEV_PMC_PG_MASK_1_0_WRITE_MASK                       _MK_MASK_CONST(0xff01)
+// MASK L2C rail
+#define APBDEV_PMC_PG_MASK_1_0_L2C_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PG_MASK_1_0_L2C_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_PG_MASK_1_0_L2C_SHIFT)
+#define APBDEV_PMC_PG_MASK_1_0_L2C_RANGE                        0:0
+#define APBDEV_PMC_PG_MASK_1_0_L2C_WOFFSET                      0x0
+#define APBDEV_PMC_PG_MASK_1_0_L2C_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PG_MASK_1_0_L2C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PG_MASK_1_0_L2C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_1_0_L2C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// MASK MPE rail
+#define APBDEV_PMC_PG_MASK_1_0_MPE_SHIFT                        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PG_MASK_1_0_MPE_FIELD                        (_MK_MASK_CONST(0xff) << APBDEV_PMC_PG_MASK_1_0_MPE_SHIFT)
+#define APBDEV_PMC_PG_MASK_1_0_MPE_RANGE                        15:8
+#define APBDEV_PMC_PG_MASK_1_0_MPE_WOFFSET                      0x0
+#define APBDEV_PMC_PG_MASK_1_0_MPE_DEFAULT                      _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_1_0_MPE_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define APBDEV_PMC_PG_MASK_1_0_MPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PG_MASK_1_0_MPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_AUTO_WAKE_LVL_0  
+#define APBDEV_PMC_AUTO_WAKE_LVL_0                      _MK_ADDR_CONST(0xd8)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SECURE                       0x0
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+//Causes PMC to sample the wake pads
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SHIFT                   _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_FIELD                   (_MK_MASK_CONST(0x1) << APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SHIFT)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_RANGE                   0:0
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_WOFFSET                 0x0
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_DISABLE                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_0_SMPL_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_AUTO_WAKE_LVL_MASK_0  
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0                 _MK_ADDR_CONST(0xdc)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_SECURE                  0x0
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_FIELD                     (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SHIFT)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_RANGE                     31:0
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_WOFFSET                   0x0
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_AUTO_WAKE_LVL_MASK_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_WAKE_DELAY_0  
+#define APBDEV_PMC_WAKE_DELAY_0                 _MK_ADDR_CONST(0xe0)
+#define APBDEV_PMC_WAKE_DELAY_0_SECURE                  0x0
+#define APBDEV_PMC_WAKE_DELAY_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_WAKE_DELAY_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_DELAY_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_DELAY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_DELAY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_DELAY_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_DELAY_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_FIELD                     (_MK_MASK_CONST(0xffff) << APBDEV_PMC_WAKE_DELAY_0_VALUE_SHIFT)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_RANGE                     15:0
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_WOFFSET                   0x0
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_WAKE_DELAY_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_PWR_DET_VAL_0  
+#define APBDEV_PMC_PWR_DET_VAL_0                        _MK_ADDR_CONST(0xe4)
+#define APBDEV_PMC_PWR_DET_VAL_0_SECURE                         0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_WORD_COUNT                     0x1
+#define APBDEV_PMC_PWR_DET_VAL_0_RESET_VAL                      _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_VAL_0_RESET_MASK                     _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_VAL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_READ_MASK                      _MK_MASK_CONST(0x1ff)
+#define APBDEV_PMC_PWR_DET_VAL_0_WRITE_MASK                     _MK_MASK_CONST(0x1ff)
+//rail ao IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_SYS_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_RANGE                      0:0
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_WOFFSET                    0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_ENABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SYS_DISABLE                    _MK_ENUM_CONST(1)
+
+//rail at3 IOs 
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_SHIFT                     _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_NAND_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_RANGE                     1:1
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_WOFFSET                   0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_ENABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_NAND_DISABLE                   _MK_ENUM_CONST(1)
+
+//rail dbg IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_SHIFT                     _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_FIELD                     (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_UART_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_RANGE                     2:2
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_WOFFSET                   0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_DEFAULT                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_ENABLE                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_UART_DISABLE                   _MK_ENUM_CONST(1)
+
+//rail dlcd IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_SHIFT                       _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_BB_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_RANGE                       3:3
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_WOFFSET                     0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_ENABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_BB_DISABLE                     _MK_ENUM_CONST(1)
+
+//rail dvi IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_SHIFT                       _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_VI_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_RANGE                       4:4
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_WOFFSET                     0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_ENABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_VI_DISABLE                     _MK_ENUM_CONST(1)
+
+//rail i2s IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SHIFT                    _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_RANGE                    5:5
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_WOFFSET                  0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_DEFAULT                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_ENABLE                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_AUDIO_DISABLE                  _MK_ENUM_CONST(1)
+
+//rail lcd IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_SHIFT                      _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_LCD_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_RANGE                      6:6
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_WOFFSET                    0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_ENABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_LCD_DISABLE                    _MK_ENUM_CONST(1)
+
+//rail mem IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_SHIFT                      _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_FIELD                      (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_MEM_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_RANGE                      7:7
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_WOFFSET                    0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_DEFAULT                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_ENABLE                     _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_MEM_DISABLE                    _MK_ENUM_CONST(1)
+
+//rail sd IOs   
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_SHIFT                       _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_PWR_DET_VAL_0_SD_SHIFT)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_RANGE                       8:8
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_WOFFSET                     0x0
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_DEFAULT                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_ENABLE                      _MK_ENUM_CONST(0)
+#define APBDEV_PMC_PWR_DET_VAL_0_SD_DISABLE                     _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_DDR_PWR_0  
+#define APBDEV_PMC_DDR_PWR_0                    _MK_ADDR_CONST(0xe8)
+#define APBDEV_PMC_DDR_PWR_0_SECURE                     0x0
+#define APBDEV_PMC_DDR_PWR_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_DDR_PWR_0_RESET_VAL                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DDR_PWR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DDR_PWR_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_VAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_DDR_PWR_0_VAL_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_DDR_PWR_0_VAL_SHIFT)
+#define APBDEV_PMC_DDR_PWR_0_VAL_RANGE                  0:0
+#define APBDEV_PMC_DDR_PWR_0_VAL_WOFFSET                        0x0
+#define APBDEV_PMC_DDR_PWR_0_VAL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_DDR_PWR_0_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DDR_PWR_0_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_DDR_PWR_0_VAL_E_12V                  _MK_ENUM_CONST(0)
+#define APBDEV_PMC_DDR_PWR_0_VAL_E_18V                  _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_USB_DEBOUNCE_DEL_0  
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0                   _MK_ADDR_CONST(0xec)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_SECURE                    0x0
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_WORD_COUNT                        0x1
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_FIELD                 (_MK_MASK_CONST(0xffff) << APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SHIFT)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_RANGE                 15:0
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_WOFFSET                       0x0
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_DEBOUNCE_DEL_0_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_USB_AO_0  
+#define APBDEV_PMC_USB_AO_0                     _MK_ADDR_CONST(0xf0)
+#define APBDEV_PMC_USB_AO_0_SECURE                      0x0
+#define APBDEV_PMC_USB_AO_0_WORD_COUNT                  0x1
+#define APBDEV_PMC_USB_AO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_USB_AO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_USB_AO_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_FIELD                      (_MK_MASK_CONST(0x3) << APBDEV_PMC_USB_AO_0_UB_ID_PD_SHIFT)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_RANGE                      1:0
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_WOFFSET                    0x0
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_UB_ID_PD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SHIFT                        _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_FIELD                        (_MK_MASK_CONST(0x3) << APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SHIFT)
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_RANGE                        3:2
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_WOFFSET                      0x0
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_USB_AO_0_VBUS_WAKEUP_PD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_CRYPTO_OP_0  
+#define APBDEV_PMC_CRYPTO_OP_0                  _MK_ADDR_CONST(0xf4)
+#define APBDEV_PMC_CRYPTO_OP_0_SECURE                   0x0
+#define APBDEV_PMC_CRYPTO_OP_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_CRYPTO_OP_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CRYPTO_OP_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CRYPTO_OP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CRYPTO_OP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CRYPTO_OP_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CRYPTO_OP_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+//Disabled by default
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_CRYPTO_OP_0_VAL_SHIFT)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_RANGE                        0:0
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_WOFFSET                      0x0
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_ENABLE                       _MK_ENUM_CONST(0)
+#define APBDEV_PMC_CRYPTO_OP_0_VAL_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_PLLP_WB0_OVERRIDE_0  
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0                  _MK_ADDR_CONST(0xf8)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_SECURE                   0x0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_FIELD                        (_MK_MASK_CONST(0xf) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SHIFT)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_RANGE                        3:0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_WOFFSET                      0x0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 1 = override CAR PLLP setting, 0 = no override.
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SHIFT)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_RANGE                    0:0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_WOFFSET                  0x0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OVERRIDE_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = enable PLLP, 0 = disable PLLP.
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SHIFT)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_RANGE                        1:1
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_WOFFSET                      0x0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_PLLP_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 00 = 13MHz, 01 = 19.2MHz, 10 = 12MHz, 11 = 26MHz.
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SHIFT                   _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_FIELD                   (_MK_MASK_CONST(0x3) << APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SHIFT)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_RANGE                   3:2
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_WOFFSET                 0x0
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_PLLP_WB0_OVERRIDE_0_OSC_FREQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH24_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH24_0                  _MK_ADDR_CONST(0xfc)
+#define APBDEV_PMC_SCRATCH24_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH24_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH24_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH24_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH24_0_SCRATCH24_SHIFT)
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH24_0_SCRATCH24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH25_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH25_0                  _MK_ADDR_CONST(0x100)
+#define APBDEV_PMC_SCRATCH25_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH25_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH25_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH25_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH25_0_SCRATCH25_SHIFT)
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH25_0_SCRATCH25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH26_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH26_0                  _MK_ADDR_CONST(0x104)
+#define APBDEV_PMC_SCRATCH26_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH26_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH26_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH26_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH26_0_SCRATCH26_SHIFT)
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH26_0_SCRATCH26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH27_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH27_0                  _MK_ADDR_CONST(0x108)
+#define APBDEV_PMC_SCRATCH27_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH27_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH27_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH27_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH27_0_SCRATCH27_SHIFT)
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH27_0_SCRATCH27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH28_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH28_0                  _MK_ADDR_CONST(0x10c)
+#define APBDEV_PMC_SCRATCH28_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH28_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH28_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH28_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH28_0_SCRATCH28_SHIFT)
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH28_0_SCRATCH28_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH29_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH29_0                  _MK_ADDR_CONST(0x110)
+#define APBDEV_PMC_SCRATCH29_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH29_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH29_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH29_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH29_0_SCRATCH29_SHIFT)
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH29_0_SCRATCH29_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH30_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH30_0                  _MK_ADDR_CONST(0x114)
+#define APBDEV_PMC_SCRATCH30_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH30_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH30_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH30_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH30_0_SCRATCH30_SHIFT)
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH30_0_SCRATCH30_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH31_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH31_0                  _MK_ADDR_CONST(0x118)
+#define APBDEV_PMC_SCRATCH31_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH31_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH31_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH31_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH31_0_SCRATCH31_SHIFT)
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH31_0_SCRATCH31_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH32_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH32_0                  _MK_ADDR_CONST(0x11c)
+#define APBDEV_PMC_SCRATCH32_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH32_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH32_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH32_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH32_0_SCRATCH32_SHIFT)
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH32_0_SCRATCH32_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH33_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH33_0                  _MK_ADDR_CONST(0x120)
+#define APBDEV_PMC_SCRATCH33_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH33_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH33_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH33_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH33_0_SCRATCH33_SHIFT)
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH33_0_SCRATCH33_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH34_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH34_0                  _MK_ADDR_CONST(0x124)
+#define APBDEV_PMC_SCRATCH34_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH34_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH34_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH34_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH34_0_SCRATCH34_SHIFT)
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH34_0_SCRATCH34_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH35_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH35_0                  _MK_ADDR_CONST(0x128)
+#define APBDEV_PMC_SCRATCH35_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH35_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH35_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH35_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH35_0_SCRATCH35_SHIFT)
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH35_0_SCRATCH35_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH36_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH36_0                  _MK_ADDR_CONST(0x12c)
+#define APBDEV_PMC_SCRATCH36_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH36_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH36_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH36_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH36_0_SCRATCH36_SHIFT)
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH36_0_SCRATCH36_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH37_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH37_0                  _MK_ADDR_CONST(0x130)
+#define APBDEV_PMC_SCRATCH37_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH37_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH37_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH37_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH37_0_SCRATCH37_SHIFT)
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH37_0_SCRATCH37_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH38_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH38_0                  _MK_ADDR_CONST(0x134)
+#define APBDEV_PMC_SCRATCH38_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH38_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH38_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH38_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH38_0_SCRATCH38_SHIFT)
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH38_0_SCRATCH38_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH39_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH39_0                  _MK_ADDR_CONST(0x138)
+#define APBDEV_PMC_SCRATCH39_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH39_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH39_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH39_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH39_0_SCRATCH39_SHIFT)
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH39_0_SCRATCH39_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH40_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH40_0                  _MK_ADDR_CONST(0x13c)
+#define APBDEV_PMC_SCRATCH40_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH40_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH40_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH40_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH40_0_SCRATCH40_SHIFT)
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH40_0_SCRATCH40_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH41_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH41_0                  _MK_ADDR_CONST(0x140)
+#define APBDEV_PMC_SCRATCH41_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH41_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH41_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH41_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH41_0_SCRATCH41_SHIFT)
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH41_0_SCRATCH41_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SCRATCH42_0  // Scratch register 
+#define APBDEV_PMC_SCRATCH42_0                  _MK_ADDR_CONST(0x144)
+#define APBDEV_PMC_SCRATCH42_0_SECURE                   0x0
+#define APBDEV_PMC_SCRATCH42_0_WORD_COUNT                       0x1
+#define APBDEV_PMC_SCRATCH42_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_SCRATCH42_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// General purpose register storage         
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_SHIFT                  _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_FIELD                  (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_SCRATCH42_0_SCRATCH42_SHIFT)
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_RANGE                  31:0
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_WOFFSET                        0x0
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SCRATCH42_0_SCRATCH42_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BONDOUT_MIRROR0_0  // Secure scratch register
+#define APBDEV_PMC_BONDOUT_MIRROR0_0                    _MK_ADDR_CONST(0x148)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_SECURE                     0x0
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SHIFT)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_RANGE                      31:0
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_WOFFSET                    0x0
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR0_0_BONDOUT_MIRROR0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BONDOUT_MIRROR1_0  // Secure scratch register
+#define APBDEV_PMC_BONDOUT_MIRROR1_0                    _MK_ADDR_CONST(0x14c)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_SECURE                     0x0
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SHIFT)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_RANGE                      31:0
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_WOFFSET                    0x0
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR1_0_BONDOUT_MIRROR1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BONDOUT_MIRROR2_0  // Secure scratch register
+#define APBDEV_PMC_BONDOUT_MIRROR2_0                    _MK_ADDR_CONST(0x150)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_SECURE                     0x0
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_WORD_COUNT                         0x1
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SHIFT                      _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_FIELD                      (_MK_MASK_CONST(0xffffffff) << APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SHIFT)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_RANGE                      31:0
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_WOFFSET                    0x0
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR2_0_BONDOUT_MIRROR2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_SYS_33V_EN_0  
+#define APBDEV_PMC_SYS_33V_EN_0                 _MK_ADDR_CONST(0x154)
+#define APBDEV_PMC_SYS_33V_EN_0_SECURE                  0x0
+#define APBDEV_PMC_SYS_33V_EN_0_WORD_COUNT                      0x1
+#define APBDEV_PMC_SYS_33V_EN_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SYS_33V_EN_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SYS_33V_EN_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SYS_33V_EN_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SYS_33V_EN_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SYS_33V_EN_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+// 1 - 3.3v, 0 - 1.8v
+#define APBDEV_PMC_SYS_33V_EN_0_val_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SYS_33V_EN_0_val_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_SYS_33V_EN_0_val_SHIFT)
+#define APBDEV_PMC_SYS_33V_EN_0_val_RANGE                       0:0
+#define APBDEV_PMC_SYS_33V_EN_0_val_WOFFSET                     0x0
+#define APBDEV_PMC_SYS_33V_EN_0_val_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SYS_33V_EN_0_val_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_SYS_33V_EN_0_val_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_SYS_33V_EN_0_val_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0  
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0                      _MK_ADDR_CONST(0x158)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_SECURE                       0x0
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_WORD_COUNT                   0x1
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_RESET_MASK                   _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_READ_MASK                    _MK_MASK_CONST(0x3)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
+// disable write to bondout secure registers
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SHIFT                 _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_FIELD                 (_MK_MASK_CONST(0x1) << APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SHIFT)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_RANGE                 0:0
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_WOFFSET                       0x0
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_OFF                   _MK_ENUM_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BWRITE_ON                    _MK_ENUM_CONST(1)
+
+// disable read  from bondout secure registers
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SHIFT                  _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_FIELD                  (_MK_MASK_CONST(0x1) << APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SHIFT)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_RANGE                  1:1
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_WOFFSET                        0x0
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_OFF                    _MK_ENUM_CONST(0)
+#define APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0_BREAD_ON                     _MK_ENUM_CONST(1)
+
+
+// Register APBDEV_PMC_GATE_0  
+#define APBDEV_PMC_GATE_0                       _MK_ADDR_CONST(0x15c)
+#define APBDEV_PMC_GATE_0_SECURE                        0x0
+#define APBDEV_PMC_GATE_0_WORD_COUNT                    0x1
+#define APBDEV_PMC_GATE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_GATE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_GATE_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_GATE_0_GATE_WAKE_SHIFT)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_RANGE                       0:0
+#define APBDEV_PMC_GATE_0_GATE_WAKE_WOFFSET                     0x0
+#define APBDEV_PMC_GATE_0_GATE_WAKE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_OFF                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_GATE_0_GATE_WAKE_ON                  _MK_ENUM_CONST(1)
+
+#define APBDEV_PMC_GATE_0_GATE_DBNS_SHIFT                       _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_FIELD                       (_MK_MASK_CONST(0x1) << APBDEV_PMC_GATE_0_GATE_DBNS_SHIFT)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_RANGE                       0:0
+#define APBDEV_PMC_GATE_0_GATE_DBNS_WOFFSET                     0x0
+#define APBDEV_PMC_GATE_0_GATE_DBNS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_OFF                 _MK_ENUM_CONST(0)
+#define APBDEV_PMC_GATE_0_GATE_DBNS_ON                  _MK_ENUM_CONST(1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPBPM_REGS(_op_) \
+_op_(APBDEV_PMC_CNTRL_0) \
+_op_(APBDEV_PMC_SEC_DISABLE_0) \
+_op_(APBDEV_PMC_PMC_SWRST_0) \
+_op_(APBDEV_PMC_WAKE_MASK_0) \
+_op_(APBDEV_PMC_WAKE_LVL_0) \
+_op_(APBDEV_PMC_WAKE_STATUS_0) \
+_op_(APBDEV_PMC_SW_WAKE_STATUS_0) \
+_op_(APBDEV_PMC_DPD_PADS_ORIDE_0) \
+_op_(APBDEV_PMC_DPD_SAMPLE_0) \
+_op_(APBDEV_PMC_DPD_ENABLE_0) \
+_op_(APBDEV_PMC_PWRGATE_TIMER_OFF_0) \
+_op_(APBDEV_PMC_PWRGATE_TIMER_ON_0) \
+_op_(APBDEV_PMC_PWRGATE_TOGGLE_0) \
+_op_(APBDEV_PMC_REMOVE_CLAMPING_CMD_0) \
+_op_(APBDEV_PMC_PWRGATE_STATUS_0) \
+_op_(APBDEV_PMC_PWRGOOD_TIMER_0) \
+_op_(APBDEV_PMC_BLINK_TIMER_0) \
+_op_(APBDEV_PMC_NO_IOPOWER_0) \
+_op_(APBDEV_PMC_PWR_DET_0) \
+_op_(APBDEV_PMC_PWR_DET_LATCH_0) \
+_op_(APBDEV_PMC_SCRATCH0_0) \
+_op_(APBDEV_PMC_SCRATCH1_0) \
+_op_(APBDEV_PMC_SCRATCH2_0) \
+_op_(APBDEV_PMC_SCRATCH3_0) \
+_op_(APBDEV_PMC_SCRATCH4_0) \
+_op_(APBDEV_PMC_SCRATCH5_0) \
+_op_(APBDEV_PMC_SCRATCH6_0) \
+_op_(APBDEV_PMC_SCRATCH7_0) \
+_op_(APBDEV_PMC_SCRATCH8_0) \
+_op_(APBDEV_PMC_SCRATCH9_0) \
+_op_(APBDEV_PMC_SCRATCH10_0) \
+_op_(APBDEV_PMC_SCRATCH11_0) \
+_op_(APBDEV_PMC_SCRATCH12_0) \
+_op_(APBDEV_PMC_SCRATCH13_0) \
+_op_(APBDEV_PMC_SCRATCH14_0) \
+_op_(APBDEV_PMC_SCRATCH15_0) \
+_op_(APBDEV_PMC_SCRATCH16_0) \
+_op_(APBDEV_PMC_SCRATCH17_0) \
+_op_(APBDEV_PMC_SCRATCH18_0) \
+_op_(APBDEV_PMC_SCRATCH19_0) \
+_op_(APBDEV_PMC_SCRATCH20_0) \
+_op_(APBDEV_PMC_SCRATCH21_0) \
+_op_(APBDEV_PMC_SCRATCH22_0) \
+_op_(APBDEV_PMC_SCRATCH23_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH0_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH1_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH2_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH3_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH4_0) \
+_op_(APBDEV_PMC_SECURE_SCRATCH5_0) \
+_op_(APBDEV_PMC_CPUPWRGOOD_TIMER_0) \
+_op_(APBDEV_PMC_CPUPWROFF_TIMER_0) \
+_op_(APBDEV_PMC_PG_MASK_0) \
+_op_(APBDEV_PMC_PG_MASK_1_0) \
+_op_(APBDEV_PMC_AUTO_WAKE_LVL_0) \
+_op_(APBDEV_PMC_AUTO_WAKE_LVL_MASK_0) \
+_op_(APBDEV_PMC_WAKE_DELAY_0) \
+_op_(APBDEV_PMC_PWR_DET_VAL_0) \
+_op_(APBDEV_PMC_DDR_PWR_0) \
+_op_(APBDEV_PMC_USB_DEBOUNCE_DEL_0) \
+_op_(APBDEV_PMC_USB_AO_0) \
+_op_(APBDEV_PMC_CRYPTO_OP_0) \
+_op_(APBDEV_PMC_PLLP_WB0_OVERRIDE_0) \
+_op_(APBDEV_PMC_SCRATCH24_0) \
+_op_(APBDEV_PMC_SCRATCH25_0) \
+_op_(APBDEV_PMC_SCRATCH26_0) \
+_op_(APBDEV_PMC_SCRATCH27_0) \
+_op_(APBDEV_PMC_SCRATCH28_0) \
+_op_(APBDEV_PMC_SCRATCH29_0) \
+_op_(APBDEV_PMC_SCRATCH30_0) \
+_op_(APBDEV_PMC_SCRATCH31_0) \
+_op_(APBDEV_PMC_SCRATCH32_0) \
+_op_(APBDEV_PMC_SCRATCH33_0) \
+_op_(APBDEV_PMC_SCRATCH34_0) \
+_op_(APBDEV_PMC_SCRATCH35_0) \
+_op_(APBDEV_PMC_SCRATCH36_0) \
+_op_(APBDEV_PMC_SCRATCH37_0) \
+_op_(APBDEV_PMC_SCRATCH38_0) \
+_op_(APBDEV_PMC_SCRATCH39_0) \
+_op_(APBDEV_PMC_SCRATCH40_0) \
+_op_(APBDEV_PMC_SCRATCH41_0) \
+_op_(APBDEV_PMC_SCRATCH42_0) \
+_op_(APBDEV_PMC_BONDOUT_MIRROR0_0) \
+_op_(APBDEV_PMC_BONDOUT_MIRROR1_0) \
+_op_(APBDEV_PMC_BONDOUT_MIRROR2_0) \
+_op_(APBDEV_PMC_SYS_33V_EN_0) \
+_op_(APBDEV_PMC_BONDOUT_MIRROR_ACCESS_0) \
+_op_(APBDEV_PMC_GATE_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APBDEV_PMC 0x00000000
+
+//
+// ARAPBPM REGISTER BANKS
+//
+
+#define APBDEV_PMC0_FIRST_REG 0x0000 // APBDEV_PMC_CNTRL_0
+#define APBDEV_PMC0_LAST_REG 0x015c // APBDEV_PMC_GATE_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARAPBPM_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arclk_rst.h b/arch/arm/mach-tegra/nv/include/ap20/arclk_rst.h
new file mode 100644
index 000000000000..fbcc898df117
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arclk_rst.h
@@ -0,0 +1,12976 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARCLK_RST_H_INC_
+#define ___ARCLK_RST_H_INC_
+
+// Register CLK_RST_CONTROLLER_RST_SOURCE_0  
+#define CLK_RST_CONTROLLER_RST_SOURCE_0                 _MK_ADDR_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_RESET_MASK                      _MK_MASK_CONST(0x3f37)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_READ_MASK                       _MK_MASK_CONST(0x3f37)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WRITE_MASK                      _MK_MASK_CONST(0x37)
+// System reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SHIFT                   _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_RANGE                   13:13
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_SYS_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// System reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// COP reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_COP_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// COP reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_RANGE                   10:10
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CPU reset by SW (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_SWR_CPU_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CPU reset by watch dog timer (RO)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_STA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Enable Watch Dog Timer (Dead Man Timer)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Watch Dog Timer Select
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_RANGE                   4:4
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_INIT_ENUM                       TIMER1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_TIMER1                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SEL_TIMER2                  _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for system.
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SHIFT                    _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_RANGE                    2:2
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_SYS_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for COP
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_COP_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable Watch Dog Timer reset for CPU
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SHIFT)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_SOURCE_0_WDT_CPU_RST_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEVICES_L_0  
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0                      _MK_ADDR_CONST(0x4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_RESET_VAL                    _MK_MASK_CONST(0x3ffffec9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_RESET_MASK                   _MK_MASK_CONST(0xbfffffff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_READ_MASK                    _MK_MASK_CONST(0xbfffffff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_WRITE_MASK                   _MK_MASK_CONST(0xbfffffff)
+// Reset COP cache controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_RANGE                 31:31
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CACHE2_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset vector co-processor.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VCP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset HOST1X.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_RANGE                 28:28
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_HOST1X_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset DISP1 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_RANGE                  27:27
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP1_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset DISP2 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_RANGE                  26:26
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_DISP2_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset IDE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_IDE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset 3D controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_RANGE                     24:24
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_3D_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset ISP controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_RANGE                    23:23
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_ISP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset USB controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_USBD_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset 2D graphics engine controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_RANGE                     21:21
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_2D_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset VI controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_RANGE                     20:20
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_VI_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset EPP controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_RANGE                    19:19
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_EPP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset I2S 2 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset Pulse Width Modulator
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_PWM_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset Three Wire Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TWC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset SDMMC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_SHIFT                 _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_RANGE                 15:15
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC4_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset SDMMC1 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_SHIFT                 _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_RANGE                 14:14
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC1_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset NAND flash controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_RANGE                        13:13
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_INIT_ENUM                    ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_NDFLASH_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset I2C1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2C1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset I2S 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_I2S1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SPDIF Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_RANGE                  10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SPDIF_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset SDMMC2 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_SHIFT                 _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_RANGE                 9:9
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_SDMMC2_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset GPIO Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_GPIO_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_RANGE                  7:7
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTB_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset UARTA Controller 
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_RANGE                  6:6
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_UARTA_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset Timer Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TMR_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset RTC Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_RTC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset AC97 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_AC97_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Write 1 to pulse System Reset Signal. HW clears  this bit
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SHIFT                       _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_RANGE                       2:2
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_TRIG_SYS_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Write 1 to force COP Reset Signal. SW needs to  clear this bit when done.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_COP_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Write 1 to force CPU Reset Signal. SW needs to  clear this bit when done.
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_L_0_SWR_CPU_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEVICES_H_0  
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0                      _MK_ADDR_CONST(0x8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_RESET_VAL                    _MK_MASK_CONST(0xfefffb77)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// Reset BSEV controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_RANGE                   31:31
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEV_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset BSEA controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_RANGE                   30:30
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_BSEA_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset VDE & BSEV controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_VDE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset MPE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MPE_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset USB3 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_RANGE                   27:27
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB3_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset USB2 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_SHIFT                   _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_RANGE                   26:26
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_USB2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset EMC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_EMC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset UART C Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_RANGE                  23:23
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_UARTC_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset I2C 2 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_I2C2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset TVDAC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_RANGE                  21:21
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVDAC_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset CSI controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_RANGE                    20:20
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_CSI_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset HDMI
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_RANGE                   19:19
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_HDMI_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset MIPI base-band controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MIPI_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset TVO/CVE controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_TVO_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset DSI controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DSI_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset DVC-I2C Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_RANGE                        15:15
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_INIT_ENUM                    ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_DVC_I2C_RST_ENABLE                       _MK_ENUM_CONST(1)
+
+// Reset SBC 3 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_RANGE                   14:14
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC3_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset XIO controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_RANGE                    13:13
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_XIO_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset SBC 2 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC2_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SPI 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SPI1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_RANGE                    10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_NOR_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_RANGE                   10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SNOR_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SBC 1 Controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_SBC1_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset KFuse controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_RANGE                  8:8
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KFUSE_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset Fuse controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_RANGE                   7:7
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_FUSE_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset PMC controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_RANGE                    6:6
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_PMC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset statistic monitor
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_INIT_ENUM                   ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_STAT_MON_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Reset Keyboard controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_KBC_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset APB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_RANGE                 2:2
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_APBDMA_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset AHB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_RANGE                 1:1
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_AHBDMA_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset MC.
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_H_0_SWR_MEM_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEVICES_U_0  
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0                      _MK_ADDR_CONST(0xc)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_RESET_VAL                    _MK_MASK_CONST(0x15ff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_RESET_MASK                   _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_READ_MASK                    _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff)
+// Reset LA logic.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_RANGE                     12:12
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_LA_RST_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset AVPUCQ logic.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_SHIFT                 _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_RANGE                 11:11
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AVPUCQ_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset PCIEXCLK logic.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_RANGE                       10:10
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_INIT_ENUM                   ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIEXCLK_RST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Reset Coresight controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_RANGE                  9:9
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_CSITE_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset AFI controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_RANGE                    8:8
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_AFI_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset OWR controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_RANGE                    7:7
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_OWR_RST_ENABLE                   _MK_ENUM_CONST(1)
+
+// Reset PCIE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_SHIFT                   _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_RANGE                   6:6
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_PCIE_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset SDMMC3 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_RANGE                 5:5
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SDMMC3_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reset SBC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_RANGE                   4:4
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SBC4_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset I2C3 controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_I2C3_RST_ENABLE                  _MK_ENUM_CONST(1)
+
+// Reset UARTE controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_RANGE                  2:2
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTE_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset UARTD controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_SHIFT                  _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_RANGE                  1:1
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_UARTD_RST_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reset SPEEDO controller.
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_RANGE                 0:0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEVICES_U_0_SWR_SPEEDO_RST_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0  
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0                      _MK_ADDR_CONST(0x10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_RESET_VAL                    _MK_MASK_CONST(0x80000130)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_RESET_MASK                   _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_READ_MASK                    _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_WRITE_MASK                   _MK_MASK_CONST(0xbffffff9)
+// Enable clock to COP cache controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_RANGE                 31:31
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CACHE2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to vector co-processor.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_RANGE                    29:29
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VCP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to HOST1X.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_RANGE                 28:28
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_HOST1X_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to DISP1 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_RANGE                  27:27
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP1_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to DISP2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_DISP2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to IDE controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_RANGE                    25:25
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_IDE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to 3D controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_RANGE                     24:24
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_3D_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to ISP controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_RANGE                    23:23
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_ISP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to USB controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_RANGE                   22:22
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_USBD_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to 2D graphics engine.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_RANGE                     21:21
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_2D_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to VI controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_RANGE                     20:20
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_VI_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to EPP controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_RANGE                    19:19
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_EPP_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to I2S 2 controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_RANGE                   18:18
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_RANGE                    17:17
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_PWM_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_RANGE                    16:16
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TWC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to SDMMC4 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_SHIFT                 _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_RANGE                 15:15
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC4_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to SDMMC1 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_SHIFT                 _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_RANGE                 14:14
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to NAND flash controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_RANGE                        13:13
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_NDFLASH_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable clock to I2C1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_RANGE                   12:12
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2C1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to I2S1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_RANGE                   11:11
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_I2S1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SPDIF Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_RANGE                  10:10
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SPDIF_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to SDMMC2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_SHIFT                 _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_RANGE                 9:9
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_SDMMC2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to GPIO Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_RANGE                   8:8
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_GPIO_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_RANGE                  7:7
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTB_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to UARTA Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_RANGE                  6:6
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_UARTA_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to Timer Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_RANGE                    5:5
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_TMR_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to RTC Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_RANGE                    4:4
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_RTC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to AC97 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_RANGE                   3:3
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_AC97_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to CPU.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_RANGE                    0:0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0_CLK_ENB_CPU_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0  
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0                      _MK_ADDR_CONST(0x14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_RESET_VAL                    _MK_MASK_CONST(0x480)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// Enable clock to BSEV Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_RANGE                   31:31
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEV_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to BSEA Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_RANGE                   30:30
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_BSEA_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to VDE Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_RANGE                    29:29
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_VDE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to MPE controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MPE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to USB3 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_RANGE                   27:27
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB3_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to USB2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_SHIFT                   _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_RANGE                   26:26
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_USB2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to EMC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_RANGE                    25:25
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_EMC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to UART-C Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_UARTC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to I2C2 controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_RANGE                   22:22
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_I2C2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to TVDAC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_RANGE                  21:21
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVDAC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to CSI controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_RANGE                    20:20
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_CSI_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to HDMI
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_RANGE                   19:19
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_HDMI_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to MIPI base-band controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_RANGE                   18:18
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MIPI_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to TVO/CVE controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_RANGE                    17:17
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_TVO_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to DSI controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_RANGE                    16:16
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DSI_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to DVC-I2C Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_RANGE                        15:15
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_DVC_I2C_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 3 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_RANGE                   14:14
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC3_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to XIO Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_RANGE                    13:13
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_XIO_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 2 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_RANGE                   12:12
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC2_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SPI 1 Controller
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_RANGE                   11:11
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SPI1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_RANGE                    10:10
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_NOR_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_RANGE                   10:10
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SNOR_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SBC 1 Controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_RANGE                   9:9
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_SBC1_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to KFUSE controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_RANGE                  8:8
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KFUSE_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to FUSE controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_RANGE                   7:7
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_FUSE_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to PMC controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_RANGE                    6:6
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_PMC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to statistic monitor.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_RANGE                       5:5
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_STAT_MON_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable clock to keyboard controller.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_RANGE                    4:4
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_KBC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to APB-DMA.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_RANGE                 2:2
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_APBDMA_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to AHB-DMA.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_RANGE                 1:1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_AHBDMA_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to MC/EMC.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_RANGE                    0:0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0_CLK_ENB_MEM_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0  
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0                      _MK_ADDR_CONST(0x18)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_RESET_VAL                    _MK_MASK_CONST(0x7f00a00)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_RESET_MASK                   _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_READ_MASK                    _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_WRITE_MASK                   _MK_MASK_CONST(0x77f01bff)
+// Enable clock to DEV1 pad.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_RANGE                       30:30
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV1_OUT_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable clock to DEV2 pad.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_RANGE                       29:29
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_DEV2_OUT_ENABLE                      _MK_ENUM_CONST(1)
+
+// Enable clock to SUS pad.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_RANGE                        28:28
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SUS_OUT_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable CLK_M clk doubler.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_SHIFT                      _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_RANGE                      26:26
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_INIT_ENUM                  ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_DISABLE                    _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_M_DOUBLER_ENB_ENABLE                     _MK_ENUM_CONST(1)
+
+// Enable audio sync clk doubler.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_SHIFT                   _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_RANGE                   25:25
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_INIT_ENUM                       ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_SYNC_CLK_DOUBLER_ENB_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable COP cache ram clk.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_RANGE                  24:24
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CRAM2_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable IRAMD clk.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMD_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable IRAMC clk.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_SHIFT                  _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_RANGE                  22:22
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMC_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_RANGE                  21:21
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMB_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_RANGE                  20:20
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_IRAMA_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to LA.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_RANGE                     12:12
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_INIT_ENUM                 DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_LA_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable clock to AVPUCQ.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_SHIFT                 _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_RANGE                 11:11
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_INIT_ENUM                     ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AVPUCQ_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to Coresight.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_RANGE                  9:9
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_INIT_ENUM                      ENABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_CSITE_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to AFI.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_RANGE                    8:8
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_AFI_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to OWR.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_RANGE                    7:7
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_OWR_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable clock to PCIE.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_SHIFT                   _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_RANGE                   6:6
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_PCIE_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to SDMMC3.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_RANGE                 5:5
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SDMMC3_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable clock to SBC4.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_RANGE                   4:4
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SBC4_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to I2C3.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_RANGE                   3:3
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_INIT_ENUM                       DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_I2C3_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable clock to UARTE.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_RANGE                  2:2
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTE_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to UARTD.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_SHIFT                  _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_RANGE                  1:1
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_UARTD_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable clock to SPEEDO.
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_RANGE                 0:0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_INIT_ENUM                     DISABLE
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_DISABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0_CLK_ENB_SPEEDO_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Reserved address 28 [0x1c] 
+
+// Register CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0  
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0                  _MK_ADDR_CONST(0x20)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_RESET_VAL                        _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_RESET_MASK                       _MK_MASK_CONST(0xff00ffff)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_READ_MASK                        _MK_MASK_CONST(0xff00ffff)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_WRITE_MASK                       _MK_MASK_CONST(0xff00ffff)
+// 0000=32KHz Clock source; 
+// 0001=IDLE Clock Source;
+// 001X=Run clock source; 
+// 01XX=IRQ Clock Source;
+// 1XXX=FIQ Clock Source
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_RANGE                  31:28
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_STDBY                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_IDLE                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_RUN                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_IRQ                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_STATE_FIQ                    _MK_ENUM_CONST(8)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_RANGE                  27:27
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_RANGE                  25:25
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_COP_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_RANGE                  24:24
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CPU_AUTO_CWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0000 = clk_m,
+//  0001 = pllC_out0,
+//  0010 = clk_s,
+//  0011 = pllM_out0,
+//  0100 = pllP_out0,
+//  0101 = pllP_out4,
+//  0110 = pllP_out3,
+//  0111 = clk_d,
+//  1xxx = PLLX_out0,
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_RANGE                 15:12
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_FIQ_SOURCE_PLLX_OUT0                     _MK_ENUM_CONST(8)
+
+//  Same definitions as CWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_RANGE                 11:8
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IRQ_SOURCE_PLLX_OUT0                     _MK_ENUM_CONST(8)
+
+//  Same definitions as CWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_RANGE                 7:4
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKS                  _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLM_OUT0                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT0                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_CLKD                  _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_RUN_SOURCE_PLLX_OUT0                     _MK_ENUM_CONST(8)
+
+//  Same definitions as CWAKEUP_FIQ
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_RANGE                        3:0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKM                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLC_OUT0                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKS                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLM_OUT0                    _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT0                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT4                    _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLP_OUT3                    _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_CLKD                 _MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0_CWAKEUP_IDLE_SOURCE_PLLX_OUT0                    _MK_ENUM_CONST(8)
+
+
+// Register CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0  
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0                 _MK_ADDR_CONST(0x24)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_RESET_MASK                      _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_READ_MASK                       _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_WRITE_MASK                      _MK_MASK_CONST(0x8f00ffff)
+//  0 = disable divider.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_RANGE                    31:31
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_RANGE                       27:27
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_RANGE                       26:26
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_RANGE                       25:25
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_COP_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_RANGE                       24:24
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_RANGE                       15:8
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_RANGE                        7:0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0_SUPER_CDIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0  
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0                  _MK_ADDR_CONST(0x28)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_RESET_VAL                        _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_RESET_MASK                       _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_READ_MASK                        _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_WRITE_MASK                       _MK_MASK_CONST(0xff007777)
+// 0000=32KHz Clock source; 
+// 0001=IDLE Clock Source;
+// 001X=Run clock source; 
+// 01XX=IRQ Clock Source;
+// 1XXX=FIQ Clock Source
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_RANGE                  31:28
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_STDBY                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_IDLE                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_RUN                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_IRQ                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SYS_STATE_FIQ                    _MK_ENUM_CONST(8)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_RANGE                  27:27
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_RANGE                  26:26
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_FIQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_RANGE                  25:25
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_COP_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_RANGE                  24:24
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_CPU_AUTO_SWAKEUP_FROM_IRQ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  000 = clk_m,
+//  001 = pllC_out1,
+//  010 = pllP_out4,
+//  011 = pllP_out3,
+//  100 = pllP_out2,
+//  101 = clk_d,
+//  110 = clk_s,
+//  111 = pllM_out1,
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_RANGE                 14:12
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_FIQ_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_RANGE                 10:8
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IRQ_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_FIELD                 (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_RANGE                 6:4
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKM                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLC_OUT1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT4                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT3                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLP_OUT2                     _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKD                  _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_CLKS                  _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_RUN_SOURCE_PLLM_OUT1                     _MK_ENUM_CONST(7)
+
+//  Same definitions as SWAKEUP_FIQ_SOURCE
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_FIELD                        (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SHIFT)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_RANGE                        2:0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKM                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLC_OUT1                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT4                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT3                    _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLP_OUT2                    _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKD                 _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_CLKS                 _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0_SWAKEUP_IDLE_SOURCE_PLLM_OUT1                    _MK_ENUM_CONST(7)
+
+
+// Register CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0  
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0                 _MK_ADDR_CONST(0x2c)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_RESET_MASK                      _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_READ_MASK                       _MK_MASK_CONST(0x8f00ffff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_WRITE_MASK                      _MK_MASK_CONST(0x8f00ffff)
+//  0 = disable divider.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SHIFT                    _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_RANGE                    31:31
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_ENB_ENABLE                   _MK_ENUM_CONST(1)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_RANGE                       27:27
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable FIQ, disable FIQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_RANGE                       26:26
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_FIQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_RANGE                       25:25
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_COP_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = enable IRQ, disable IRQ.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_RANGE                       24:24
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIS_FROM_CPU_IRQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_RANGE                       15:8
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVIDEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Actual value = n + 1.
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_RANGE                        7:0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0_SUPER_SDIV_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0  
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0                    _MK_ADDR_CONST(0x30)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_RESET_MASK                         _MK_MASK_CONST(0xbb)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_READ_MASK                  _MK_MASK_CONST(0xbb)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_WRITE_MASK                         _MK_MASK_CONST(0xbb)
+//  0=enable HCLK, 1=disable HCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_RANGE                     7:7
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_HCLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1/(n+1) of SCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SHIFT                     _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_RANGE                     5:4
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_AHB_RATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  0=enable PCLK, 1=disable PCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT                     _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_RANGE                     3:3
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_PCLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1/(n+1) of HCLK.
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_RANGE                     1:0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0_APB_RATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PROG_DLY_CLK_0  
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0                       _MK_ADDR_CONST(0x34)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_RESET_VAL                     _MK_MASK_CONST(0x7700)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_RESET_MASK                    _MK_MASK_CONST(0xff00)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_READ_MASK                     _MK_MASK_CONST(0xff00)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_WRITE_MASK                    _MK_MASK_CONST(0xff00)
+// 16 Taps of selectable delay for CLK_M clk doubler
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SHIFT                        _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_RANGE                        15:12
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_DEFAULT                      _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_CLK_D_DELCLK_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 16 Taps of selectable delay for SYNC_CLK clk doubler
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_FIELD                     (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_RANGE                     11:8
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_DEFAULT                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PROG_DLY_CLK_0_SYNC_CLK_DELCLK_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0  
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0                        _MK_ADDR_CONST(0x38)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SECURE                         0x0
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_RESET_MASK                     _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_WRITE_MASK                     _MK_MASK_CONST(0x1f)
+//  0 = Enable AUDIO SYNC CLK
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_SHIFT                     _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_RANGE                     4:4
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_DIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 0000 = SPDIFIN recovered bit clock.
+// 0001 = I2S1 bit clock.
+// 0010 = I2S2 bit clock.
+// 0011 = AC97 bit clock.
+// 0100 = pllA_out0.
+// 0101 = external audio clock (dap_mclk2).
+// 0110 = external audio clock (dap_mclk1).
+// 0111 = external vimclk (vimclk).
+// 1xxx = reserved
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_FIELD                    (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SHIFT)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_RANGE                    3:0
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_SPDIFIN                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_I2S1                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_I2S2                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_AC97                     _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_PLLA_OUT0                        _MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_EXT_AUDIO_CLK2                   _MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_EXT_AUDIO_CLK1                   _MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0_SYNC_CLK_RATE_EXT_VIMCLK                       _MK_ENUM_CONST(7)
+
+
+// Reserved address 60 [0x3c] 
+
+// Register CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0  
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0                        _MK_ADDR_CONST(0x40)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_SECURE                         0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_RESET_MASK                     _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_READ_MASK                      _MK_MASK_CONST(0xff007777)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_WRITE_MASK                     _MK_MASK_CONST(0xff007777)
+// 0000=no skip.
+// 0001=skip base on IDLE Clock skip rate;
+// 001X=skip base on Run clock skip rate; 
+// 01XX=skip base on IRQ Clock skip rate;
+// 1XXX=skip base on FIQ Clock skip rate
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SHIFT                       _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_FIELD                       (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_RANGE                       31:28
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_RANGE                    27:27
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SHIFT                    _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_RANGE                    26:26
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on COP IRQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_RANGE                    25:25
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_COP_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = NOP ; 1=Burst on CPU IRQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_RANGE                    24:24
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_ENB_FROM_CPU_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  skip n/16 clock.
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SHIFT                    _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_RANGE                    14:12
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_FIQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_RANGE                    10:8
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IRQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_FIELD                    (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_RANGE                    6:4
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_RUN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  Same definitions as COP_CLK_SKIP_RATE_FIQ
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SHIFT)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_RANGE                   2:0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0_COP_CLK_SKIP_RATE_IDLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_MASK_ARM_0  
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0                       _MK_ADDR_CONST(0x44)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RESET_MASK                    _MK_MASK_CONST(0x80030003)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_READ_MASK                     _MK_MASK_CONST(0x80030003)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_WRITE_MASK                    _MK_MASK_CONST(0x30003)
+//  1 = ARM11 AXI pipe is flushed.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_RANGE                  31:31
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_AXI_FLUSH_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = reset CPU0 when flow control assert halt.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SHIFT                      _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_RANGE                      17:17
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_RST_CPU0_WHEN_HALT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  1 = HW will stop clock to CPU when halt, 0 = no clock stop.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT                       _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_RANGE                       16:16
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_CPU_HALT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  00 = no clock masking.
+//  01 = u2_nwait_r.
+//  10 = u2_nwait_r.
+//  11 = no clock masking.
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_FIELD                    (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_RANGE                    1:0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_MASK_ARM_0_CLK_MASK_COP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_MISC_CLK_ENB_0  
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0                       _MK_ADDR_CONST(0x48)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_RESET_MASK                    _MK_MASK_CONST(0x10f00000)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_READ_MASK                     _MK_MASK_CONST(0x10f00000)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_WRITE_MASK                    _MK_MASK_CONST(0x10f00000)
+// 1 = VISIBLE, 0 = NOT VISIBLE.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_RANGE                 28:28
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_CFG_ALL_VISIBLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 00 = osc, 01 = osc/2, 10 = osc/4, 11 = osc/8.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SHIFT                        _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_RANGE                        23:22
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV1_OSC_DIV_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 00 = osc, 01 = osc/2, 10 = osc/4, 11 = osc/8.
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SHIFT                        _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_RANGE                        21:20
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_DEV2_OSC_DIV_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0  
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0                      _MK_ADDR_CONST(0x4c)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_RESET_VAL                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_RESET_MASK                   _MK_MASK_CONST(0x303)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_READ_MASK                    _MK_MASK_CONST(0x303)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_WRITE_MASK                   _MK_MASK_CONST(0x303)
+// Clock divider ratio for the cpu bridge devices
+// connected to CPU/L2-cache.
+//   00 = div-by-1.
+//   01 = div-by-2.
+//   10 = div-by-3.
+//   11 = div-by-4.
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_FIELD                      (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_RANGE                      1:0
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_DEFAULT                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU_BRIDGE_CLKDIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = CPU0 clock stop, 0 = CPU0 clock run.
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_RANGE                   8:8
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU0_CLK_STP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = CPU1 clock stop, 0 = CPU1 clock run.
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_RANGE                   9:9
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0_CPU1_CLK_STP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_OSC_CTRL_0  
+#define CLK_RST_CONTROLLER_OSC_CTRL_0                   _MK_ADDR_CONST(0x50)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_VAL                         _MK_MASK_CONST(0x3f1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_RESET_MASK                        _MK_MASK_CONST(0xfff1f3f3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_READ_MASK                         _MK_MASK_CONST(0xfff1f3f3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_WRITE_MASK                        _MK_MASK_CONST(0xfff1f3f3)
+// 00 = 13MHz, 01 = 19.2MHz, 10 = 12MHz, 11 = 26MHz.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT                    _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_FIELD                    (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_RANGE                    31:30
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// PLL reference clock divide.  00 = /1, 01 = /2, 10 = /4, 11 = reserve.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_RANGE                 29:28
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_PLL_REF_DIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Crystal oscillator spare register control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_RANGE                 27:20
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSCFI_SPARE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Crystal oscillator duty cycle control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT                        _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_FIELD                        (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_RANGE                        16:12
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XODS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator drive strength control.
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_FIELD                        (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_RANGE                        9:4
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT                      _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator bypass enable (1 = enable bypass).
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SHIFT                        _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_RANGE                        1:1
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOBP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Crystal oscillator enable (1 = enable).
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_RANGE                 0:0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_XOE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLL_LFSR_0  
+#define CLK_RST_CONTROLLER_PLL_LFSR_0                   _MK_ADDR_CONST(0x54)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Random number generated from PLL linear feedback shift register.
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_FIELD                 (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_RANGE                 15:0
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLL_LFSR_0_RND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_0  
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0                       _MK_ADDR_CONST(0x58)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_RESET_MASK                    _MK_MASK_CONST(0x8000000f)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_READ_MASK                     _MK_MASK_CONST(0x8000000f)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_WRITE_MASK                    _MK_MASK_CONST(0x8000000f)
+// 0 = default, 1 = enable osc frequency detect. 
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_RANGE                       31:31
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_INIT_ENUM                   DISABLE
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_DISABLE                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_OSC_FREQ_DET_TRIG_ENABLE                      _MK_ENUM_CONST(1)
+
+// Indicate the # of 32KHz clock period as window in n+1 scheme.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_RANGE                 3:0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_0_REF_CLK_WIN_CFG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0  
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0                        _MK_ADDR_CONST(0x5c)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SECURE                         0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// 0 = not busy, 1 = busy.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_RANGE                        31:31
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// indicate the number of osc count within the 32KHz clock reference window.
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_FIELD                 (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SHIFT)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_RANGE                 15:0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0_OSC_FREQ_DET_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0  
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0                   _MK_ADDR_CONST(0x60)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_RESET_MASK                        _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_READ_MASK                         _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_WRITE_MASK                        _MK_MASK_CONST(0x3ff)
+// PTO counter reset.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SHIFT                 _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_RANGE                 9:9
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// enable PTO counter.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_RANGE                  8:8
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_CNT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PLL PTO source select.
+// 0000 = PLLX PTO div-2.
+// 0001 = PLLC PTO div-2.
+// 0010 = PLLM PTO div-2.
+// 0011 = PLLP PTO div-2.
+// 0100 = PLLA PTO div-2.
+// 0101 = PLLU PTO div-2.
+// 0110 = PLLD PTO div-2.
+// 0111 = PLLE PTO div-2.
+// 1000 = PLLS PTO div-2.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_SRC_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Indicate the # of 32KHz clock period as window in n+1 scheme.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_RANGE                 3:0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0_PTO_REF_CLK_WIN_CFG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0  
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0                 _MK_ADDR_CONST(0x64)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x8000ffff)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// 0 = not busy, 1 = busy.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_BUSY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// indicate the number of PTO clock count within the 32KHz clock reference window.
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_FIELD                       (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SHIFT)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_RANGE                       15:0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0_PTO_CLK_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLE_SS_CNTL_0  
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0                       _MK_ADDR_CONST(0x68)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_RESET_VAL                     _MK_MASK_CONST(0x5e00)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// interpolator bias current. 
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_RANGE                        31:30
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTEGOFFSET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Triangle generator increment interval control.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SHIFT                        _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_FIELD                        (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_RANGE                        29:24
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINCINTRV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Triangle generator increment control.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SHIFT                     _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_RANGE                     23:16
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 0 gives down spread, 1 gives up-spread.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SHIFT                  _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_RANGE                  15:15
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCINVERT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 gives control to SSCINVERT, 1 enables center spread.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SHIFT                  _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_RANGE                  14:14
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCCENTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bypass from pulse density modulator. Normally set to zero.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SHIFT                  _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_RANGE                  13:13
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCPDMBYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 enables spreading, 1 disables spreading.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_RANGE                     12:12
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCBYP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Interpolator reset. 0=normal operation  1=resets SS machine.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SHIFT                       _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_RANGE                       11:11
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_INTERP_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// When set feedback clock bypasses interpolator. Default value is zero.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_RANGE                  10:10
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_BYPASS_SS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Enables reference current for external devices like PLL_DIFFCLKBUF_CML.
+// Overrides IDDQ and ENABLE for bandgap.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_SHIFT                    _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_RANGE                    9:9
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_EN_IREF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Spread limit control.
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_FIELD                     (_MK_MASK_CONST(0x1ff) << CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_RANGE                     8:0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_SS_CNTL_0_PLLE_SSCMAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 108 [0x6c] 
+
+// Register CLK_RST_CONTROLLER_BOND_OUT_L_0  
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0                 _MK_ADDR_CONST(0x70)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_RESET_MASK                      _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_READ_MASK                       _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_WRITE_MASK                      _MK_MASK_CONST(0xbffffff9)
+// Bond out COP cache controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_RANGE                   31:31
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CACHE2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out vector co-processor.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SHIFT                      _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_RANGE                      29:29
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VCP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out HOST1X.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_RANGE                   28:28
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_HOST1X_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out DISP1 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_RANGE                    27:27
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out DISP2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SHIFT                    _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_RANGE                    26:26
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_DISP2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IDE controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SHIFT                      _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_RANGE                      25:25
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_IDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out 3D controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_RANGE                       24:24
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_3D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out ISP controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_RANGE                      23:23
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_ISP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out USB controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SHIFT                     _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_RANGE                     22:22
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_USBD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out 2D graphics engine.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SHIFT                       _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_RANGE                       21:21
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_2D_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out VI controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SHIFT                       _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_RANGE                       20:20
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_VI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out EPP controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SHIFT                      _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_RANGE                      19:19
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_EPP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out I2S 2 controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SHIFT                     _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_RANGE                     18:18
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SHIFT                      _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_RANGE                      17:17
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_PWM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_RANGE                      16:16
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TWC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out SDMMC4 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_SHIFT                   _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_RANGE                   15:15
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out SDMMC1 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_RANGE                   14:14
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out NAND flash controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SHIFT                  _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_RANGE                  13:13
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_NDFLASH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bond out I2C1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_RANGE                     12:12
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2C1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out I2S1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_RANGE                     11:11
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_I2S1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SPDIF Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_RANGE                    10:10
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SPDIF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out SDMMC2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_RANGE                   9:9
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_SDMMC2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out GPIO Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_RANGE                     8:8
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_GPIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_RANGE                    7:7
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out UARTA Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_RANGE                    6:6
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_UARTA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out Timer Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SHIFT                      _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_RANGE                      5:5
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_TMR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out RTC Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SHIFT                      _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_RANGE                      4:4
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_RTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out AC97 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SHIFT                     _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_RANGE                     3:3
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_AC97_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out CPU.
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_RANGE                      0:0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_L_0_BOND_OUT_CPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_BOND_OUT_H_0  
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0                 _MK_ADDR_CONST(0x74)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_RESET_MASK                      _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_READ_MASK                       _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_WRITE_MASK                      _MK_MASK_CONST(0xfefffff7)
+// Bond out BSEV Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SHIFT                     _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_RANGE                     31:31
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out BSEA Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_RANGE                     30:30
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_BSEA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out VDE Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SHIFT                      _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_RANGE                      29:29
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_VDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out MPE controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SHIFT                      _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_RANGE                      28:28
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MPE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out USB3 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_SHIFT                     _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_RANGE                     27:27
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out USB2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_SHIFT                     _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_RANGE                     26:26
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_USB2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out EMC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SHIFT                      _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_RANGE                      25:25
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_EMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out UART-C Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_RANGE                    23:23
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_UARTC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out I2C2 controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SHIFT                     _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_RANGE                     22:22
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_I2C2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out TVDAC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SHIFT                    _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_RANGE                    21:21
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVDAC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out CSI controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SHIFT                      _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_RANGE                      20:20
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_CSI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out HDMI
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SHIFT                     _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_RANGE                     19:19
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_HDMI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out MIPI base-band controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SHIFT                     _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_RANGE                     18:18
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MIPI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out TVO/CVE controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SHIFT                      _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_RANGE                      17:17
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_TVO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out DSI controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_RANGE                      16:16
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DSI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out DVC-I2C Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SHIFT                  _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_RANGE                  15:15
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_DVC_I2C_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bond out SBC 3 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SHIFT                     _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_RANGE                     14:14
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out XIO Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SHIFT                      _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_RANGE                      13:13
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_XIO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out SBC 2 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_RANGE                     12:12
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SPI 1 Controller
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_RANGE                     11:11
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SPI1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out NOR Flash Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SHIFT                      _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_RANGE                      10:10
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_NOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out NOR Flash Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_SHIFT                     _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_RANGE                     10:10
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SNOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SBC 1 Controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SHIFT                     _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_RANGE                     9:9
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_SBC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out KFUSE controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_RANGE                    8:8
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KFUSE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out FUSE controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_RANGE                     7:7
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_FUSE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out PMC controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SHIFT                      _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_RANGE                      6:6
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_PMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out statistic monitor.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_RANGE                 5:5
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_STAT_MON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Bond out keyboard controller.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SHIFT                      _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_RANGE                      4:4
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_KBC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out APB-DMA.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SHIFT                   _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_RANGE                   2:2
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_APBDMA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out AHB-DMA.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SHIFT                   _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_RANGE                   1:1
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_AHBDMA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out MC/EMC.
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_RANGE                      0:0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_H_0_BOND_OUT_MEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_BOND_OUT_U_0  
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0                 _MK_ADDR_CONST(0x78)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_RESET_MASK                      _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_READ_MASK                       _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_WRITE_MASK                      _MK_MASK_CONST(0x77f01bff)
+// Bond out DEV1_OUT.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_RANGE                 30:30
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV1_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Bond out DEV2_OUT.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_SHIFT                 _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_RANGE                 29:29
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_DEV2_OUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Bond out SUS_OUT.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_RANGE                  28:28
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SUS_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Bond out CLK_M_DOUBLER.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_SHIFT                    _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_RANGE                    26:26
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CLK_M_DOUBLER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out SYNC_CLK_DOUBLER.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_SHIFT                 _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_RANGE                 25:25
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SYNC_CLK_DOUBLER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Bond out CRAM2.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_RANGE                    24:24
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CRAM2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IRAMD.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_RANGE                    23:23
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IRAMC.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_SHIFT                    _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_RANGE                    22:22
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IRAMB.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_SHIFT                    _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_RANGE                    21:21
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out IRAMA.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_RANGE                    20:20
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_IRAMA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out LA.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_SHIFT                       _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_RANGE                       12:12
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_LA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Bond out AVPUCQ.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_RANGE                   11:11
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AVPUCQ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out CSITE.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_SHIFT                    _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_RANGE                    9:9
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_CSITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out AFI.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_SHIFT                      _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_RANGE                      8:8
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_AFI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out OWR.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_SHIFT                      _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_RANGE                      7:7
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_OWR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bond out PCIE.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_SHIFT                     _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_RANGE                     6:6
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_PCIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out SDMMC3.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_RANGE                   5:5
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SDMMC3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Bond out SBC4.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_SHIFT                     _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_RANGE                     4:4
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SBC4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out I2C3.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_SHIFT                     _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_RANGE                     3:3
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_I2C3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Bond out UARTE.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_SHIFT                    _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_RANGE                    2:2
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out UARTD.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_RANGE                    1:1
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_UARTD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Bond out SPEEDO.
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_SHIFT)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_RANGE                   0:0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_BOND_OUT_U_0_BOND_OUT_SPEEDO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 124 [0x7c] 
+
+// Register CLK_RST_CONTROLLER_PLLC_BASE_0  
+#define CLK_RST_CONTROLLER_PLLC_BASE_0                  _MK_ADDR_CONST(0x80)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_BASE_0_PLLC_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLC_OUT_0  
+#define CLK_RST_CONTROLLER_PLLC_OUT_0                   _MK_ADDR_CONST(0x84)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLC_OUT1 divider from base PLLC (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  PLLC_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLC_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_OUT_0_PLLC_OUT1_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 136 [0x88] 
+
+// Register CLK_RST_CONTROLLER_PLLC_MISC_0  
+#define CLK_RST_CONTROLLER_PLLC_MISC_0                  _MK_ADDR_CONST(0x8c)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+//  1 = invert PLLC_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLC_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLC test output select.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLC DCCON control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLC charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLC loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLC VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLC_MISC_0_PLLC_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLM_BASE_0  
+#define CLK_RST_CONTROLLER_PLLM_BASE_0                  _MK_ADDR_CONST(0x90)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_BASE_0_PLLM_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLM_OUT_0  
+#define CLK_RST_CONTROLLER_PLLM_OUT_0                   _MK_ADDR_CONST(0x94)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLM_OUT1 divider from base PLLM (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  PLLM_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLM_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_OUT_0_PLLM_OUT1_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 152 [0x98] 
+
+// Register CLK_RST_CONTROLLER_PLLM_MISC_0  
+#define CLK_RST_CONTROLLER_PLLM_MISC_0                  _MK_ADDR_CONST(0x9c)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xcfd7ffff)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_READ_MASK                        _MK_MASK_CONST(0xcfd7ffff)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xcfd7ffff)
+//  1 = invert PLLM_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLM_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLM setup.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_SHIFT                 _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_RANGE                 27:24
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLM test output select.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLM DCCON control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLM charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLM loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLM VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLM_MISC_0_PLLM_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_BASE_0  
+#define CLK_RST_CONTROLLER_PLLP_BASE_0                  _MK_ADDR_CONST(0xa0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xf873ff1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_READ_MASK                        _MK_MASK_CONST(0xf873ff1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xf073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = disallow base override , 1 = allow base override.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_RANGE                  28:28
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_BASE_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0_PLLP_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_OUTA_0  
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0                  _MK_ADDR_CONST(0xa4)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_VAL                        _MK_MASK_CONST(0x30003)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_RESET_MASK                       _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_READ_MASK                        _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_WRITE_MASK                       _MK_MASK_CONST(0xff07ff07)
+//  PLLP_OUT2 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_RANGE                    31:24
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT2 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_RANGE                  18:18
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT2 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_RANGE                    17:17
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT2 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT                     _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RANGE                     16:16
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT2_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_RANGE                    15:8
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT1 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_RANGE                  2:2
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT1 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RANGE                     0:0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTA_0_PLLP_OUT1_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_OUTB_0  
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0                  _MK_ADDR_CONST(0xa8)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_RESET_VAL                        _MK_MASK_CONST(0x30003)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_RESET_MASK                       _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_READ_MASK                        _MK_MASK_CONST(0xff07ff07)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_WRITE_MASK                       _MK_MASK_CONST(0xff07ff07)
+//  PLLP_OUT4 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SHIFT                    _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_RANGE                    31:24
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT4 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_RANGE                  18:18
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT4 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_RANGE                    17:17
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT4 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT                     _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RANGE                     16:16
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT4_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider from base PLLP (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_RANGE                    15:8
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RATIO_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  0 = disallow PLLP_OUT3 ratio override, 1 = enable override.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_RANGE                  2:2
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_INIT_ENUM                      DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_DISABLE                        _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_OVRRIDE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_RANGE                    1:1
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_INIT_ENUM                        ENABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_CLKEN_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLLP_OUT3 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RANGE                     0:0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_INIT_ENUM                 RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_ENABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_OUTB_0_PLLP_OUT3_RSTN_RESET_DISABLE                     _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_PLLP_MISC_0  
+#define CLK_RST_CONTROLLER_PLLP_MISC_0                  _MK_ADDR_CONST(0xac)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffd7ffff)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffd7ffff)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffd7ffff)
+//  1 = invert PLLP_OUT4 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT3 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT2 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SHIFT                  _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_RANGE                  29:29
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = invert PLLP_OUT1 clock.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SHIFT                  _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_RANGE                  28:28
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT4 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT4_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT3 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_RANGE                  26:26
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT3_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT2 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_RANGE                  25:25
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT2_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLP_OUT1 divider.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_RANGE                  24:24
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_OUT1_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLP test output select.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLP DCCON control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLP charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLP loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLP VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLP_MISC_0_PLLP_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLA_BASE_0  
+#define CLK_RST_CONTROLLER_PLLA_BASE_0                  _MK_ADDR_CONST(0xb0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_BASE_0_PLLA_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLA_OUT_0  
+#define CLK_RST_CONTROLLER_PLLA_OUT_0                   _MK_ADDR_CONST(0xb4)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_VAL                         _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_RESET_MASK                        _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_READ_MASK                         _MK_MASK_CONST(0xff03)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_WRITE_MASK                        _MK_MASK_CONST(0xff03)
+//  PLLA_OUT0 divider from base PLLA (lsb denote 0.5x).
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT                     _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_RANGE                     15:8
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RATIO_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLA_OUT0 divider clk enable.  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_INIT_ENUM                 ENABLE
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_DISABLE                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_CLKEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  PLLA_OUT0 divider reset.  0 = reset, 1 = not reset.
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RANGE                      0:0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_INIT_ENUM                  RESET_DISABLE
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_ENABLE                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_OUT_0_PLLA_OUT0_RSTN_RESET_DISABLE                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 184 [0xb8] 
+
+// Register CLK_RST_CONTROLLER_PLLA_MISC_0  
+#define CLK_RST_CONTROLLER_PLLA_MISC_0                  _MK_ADDR_CONST(0xbc)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc0d7ffff)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc0d7ffff)
+//  1 = invert PLLA_OUT0 clock.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_RANGE                  31:31
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_INV_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  1 = bypass PLLA_OUT0 divider.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_RANGE                  30:30
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_OUT0_DIV_BYP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Base PLLA test output select.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLA DCCON control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLA charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLA loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLA VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLA_MISC_0_PLLA_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLU_BASE_0  
+#define CLK_RST_CONTROLLER_PLLU_BASE_0                  _MK_ADDR_CONST(0xc0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe9f3ff1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe9f3ff1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe1f3ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.  This bit is use only when PLLU_OVERRIDE bit is set.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 = FO_[ICUSB,HSIC,USB] controlled by USB controllers, 1 = controlled by PLLU_CLKENABLEs.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_SHIFT                      _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_RANGE                      24:24
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_OVERRIDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  FO_ICUSB output enable.  This bit is use only when PLLU_OVERRIDE bit is set.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_SHIFT                       _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_RANGE                       23:23
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_ICUSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  FO_HSIC output enable.  This bit is use only when PLLU_OVERRIDE bit is set.
+//  Otherwise, USB controllers will control this automatically.  
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_SHIFT                        _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_RANGE                        22:22
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_HSIC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  FO_USB output enable.  This bit is use only when PLLU_OVERRIDE bit is set.
+//  Otherwise, USB controllers will control this automatically.  
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_SHIFT                 _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_RANGE                 21:21
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_CLKENABLE_USB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  0 = post-div of 2, 1 = post-div of 1.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_SHIFT                      _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_RANGE                      20:20
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_VCO_FREQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_BASE_0_PLLU_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Register CLK_RST_CONTROLLER_PLLU_MISC_0  
+#define CLK_RST_CONTROLLER_PLLU_MISC_0                  _MK_ADDR_CONST(0xcc)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_RESET_MASK                       _MK_MASK_CONST(0x3843ffff)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_READ_MASK                        _MK_MASK_CONST(0x3843ffff)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0x3843ffff)
+//  Base PLLU test output select.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_RANGE                   29:27
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_RANGE                   22:22
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLU charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLU loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLU VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLU_MISC_0_PLLU_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLD_BASE_0  
+#define CLK_RST_CONTROLLER_PLLD_BASE_0                  _MK_ADDR_CONST(0xd0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_BASE_0_PLLD_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Register CLK_RST_CONTROLLER_PLLD_MISC_0  
+#define CLK_RST_CONTROLLER_PLLD_MISC_0                  _MK_ADDR_CONST(0xdc)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//  1 = 5-125MHz, 0 = 40-1000MHz.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_RANGE                       31:31
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_FO_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = disable, 1 = normal operation.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_RANGE                     30:30
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CLKENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Base PLLD test output select.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_RANGE                   29:27
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  load pulse position adjust.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SHIFT                       _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_FIELD                       (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_RANGE                       26:24
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOADADJ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  0 = normal operation, 1 = reset.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SHIFT                       _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_RANGE                       23:23
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DIV_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_RANGE                   22:22
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_RANGE                      21:16
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLD DCCON control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_RANGE                 15:12
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLD VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLD_MISC_0_PLLD_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLX_BASE_0  
+#define CLK_RST_CONTROLLER_PLLX_BASE_0                  _MK_ADDR_CONST(0xe0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x10c)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff1f)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff1f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_FIELD                  (_MK_MASK_CONST(0x1f) << CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_RANGE                  4:0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_DEFAULT                        _MK_MASK_CONST(0xc)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_BASE_0_PLLX_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLX_MISC_0  
+#define CLK_RST_CONTROLLER_PLLX_MISC_0                  _MK_ADDR_CONST(0xe4)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100100)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xfd7ffff)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_READ_MASK                        _MK_MASK_CONST(0xfd7ffff)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xfd7ffff)
+//  Base PLLX setup.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_SHIFT                 _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_RANGE                 27:24
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLX test output select.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLX DCCON control.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_RANGE                 20:20
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_DCCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLX charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLX loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLX VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLX_MISC_0_PLLX_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLE_BASE_0  
+#define CLK_RST_CONTROLLER_PLLE_BASE_0                  _MK_ADDR_CONST(0xe8)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_RESET_VAL                        _MK_MASK_CONST(0xd18c801)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+//  Enable CML pdivider. 0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_SHIFT                    _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_RANGE                    31:31
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_INIT_ENUM                        DISABLE
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_DISABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_CML_ENABLE                   _MK_ENUM_CONST(1)
+
+//  PLL enable. 0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  Forces PLL_LOCK to 1.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_RANGE                 29:29
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_LOCK_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  0 gives vcoclk/4, 1 gives vcoclk/2 clock to the interpolator logic. Normally set to zero.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_RANGE                        28:28
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_FDIV4B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  divider control for CLOCKOUT_CML/CLOCKOUTB_CML.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_FIELD                     (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_RANGE                     27:24
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_DEFAULT                   _MK_MASK_CONST(0xd)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_CML_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Base PLLE setup[19:18].
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_RANGE                       23:22
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_EXT_SETUP_19_18_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  post divider for CLOCKOUT and SYNC_CLOCKOUT.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_SHIFT                 _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_FIELD                 (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_RANGE                 21:16
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_DEFAULT                       _MK_MASK_CONST(0x18)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_PLDIV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  feedback divider.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_FIELD                  (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_RANGE                  15:8
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_DEFAULT                        _MK_MASK_CONST(0xc8)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_NDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  input divider.
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_FIELD                  (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_RANGE                  7:0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_BASE_0_PLLE_MDIV_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLE_MISC_0  
+#define CLK_RST_CONTROLLER_PLLE_MISC_0                  _MK_ADDR_CONST(0xec)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xffff07ff)
+//  Base PLLE setup[15:0].
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SHIFT                 _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_FIELD                 (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_RANGE                 31:16
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  When read, this is PLL_READY status: 1 = PLL finish training, 0 = PLL not finish training.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_SHIFT                     _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_RANGE                     15:15
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PLL_READY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Process monitor debug output.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_RANGE                   14:12
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_MON_TESTOUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SHIFT                  _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_RANGE                  11:11
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_RANGE                       10:10
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_RANGE                   9:9
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  Bypass PLL (similar to PTO control of other PLL).
+//  0 = PTO always 0 if PLLE_ENABLE=0 (SYN_CLOCKOUT=0), 
+//  0 = PTO = PLLE CLOCKIN if PLLE_ENABLE=1,
+//  1 = PTO = PLLE FO (SYN_CLOCKOUT=VCOCLOCK/PLDIV).
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_RANGE                   8:8
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLE charge pump gain control.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SHIFT                   _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_RANGE                   7:6
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KCP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  Base PLLE loop filter resistor control.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_RANGE                 5:4
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_LFRES_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLE setup[17:16].
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_SHIFT                       _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_RANGE                       3:2
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_EXT_SETUP_17_16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  Base PLLE sync mode (leave it at 0).
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_RANGE                     1:1
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_SYNC_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  Base PLLE VCO gain.
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SHIFT)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_RANGE                  0:0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLE_MISC_0_PLLE_KVCO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLS_BASE_0  
+#define CLK_RST_CONTROLLER_PLLS_BASE_0                  _MK_ADDR_CONST(0xf0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_RESET_VAL                        _MK_MASK_CONST(0x101)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_RESET_MASK                       _MK_MASK_CONST(0xe873ff0f)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_READ_MASK                        _MK_MASK_CONST(0xe873ff0f)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_WRITE_MASK                       _MK_MASK_CONST(0xe073ff0f)
+//  0 = no bypass, 1 = bypass.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_SHIFT                        _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_RANGE                        31:31
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_BYPASS_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = disable, 1 = enable.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_RANGE                        30:30
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+
+//  0 = enable reference clk, 1 = disable reference clk.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_RANGE                       29:29
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_INIT_ENUM                   REF_ENABLE
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_REF_ENABLE                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_REF_DIS_REF_DISABLE                 _MK_ENUM_CONST(1)
+
+//  0 = not lock, 1 = lock.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_RANGE                  27:27
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_LOCK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  0 = post divider (2^n).
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_SHIFT                  _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_FIELD                  (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_RANGE                  22:20
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL feedback divider.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_FIELD                  (_MK_MASK_CONST(0x3ff) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_RANGE                  17:8
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  PLL input divider.
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_SHIFT                  _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_RANGE                  3:0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_BASE_0_PLLS_DIVM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_PLLS_MISC_0  
+#define CLK_RST_CONTROLLER_PLLS_MISC_0                  _MK_ADDR_CONST(0xf4)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_RESET_VAL                        _MK_MASK_CONST(0x100)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_RESET_MASK                       _MK_MASK_CONST(0xc7ffff)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_READ_MASK                        _MK_MASK_CONST(0xc7ffff)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_WRITE_MASK                       _MK_MASK_CONST(0xc7ffff)
+//  Base PLLS test output select.
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_RANGE                   23:22
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_PTS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  1 = enable, 0 = disable. 
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_RANGE                   18:18
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_DISABLE                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+//  lock select.
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_FIELD                      (_MK_MASK_CONST(0x3f) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_RANGE                      17:12
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LOCK_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Base PLLS charge pump setup control.
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_SHIFT                 _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_RANGE                 11:8
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_CPCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLS loop filter setup control.
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_FIELD                 (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_RANGE                 7:4
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_LFCON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  Base PLLS VCO range setup control.
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_FIELD                        (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_SHIFT)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_RANGE                        3:0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_PLLS_MISC_0_PLLS_VCOCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0  
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0                 _MK_ADDR_CONST(0xf8)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_RESET_MASK                      _MK_MASK_CONST(0xfffffffe)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_READ_MASK                       _MK_MASK_CONST(0xfffffffe)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffffe)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SHIFT                  _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_RANGE                  31:31
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_TVDAC_CLK_OVR_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_RANGE                   30:30
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_PPCS_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_RANGE                   29:29
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEA_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_RANGE                   28:28
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_BSEV_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_RANGE                    27:27
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VDE_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_RANGE                        26:26
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_VPECLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_RANGE                        25:25
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_TEXCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_RANGE                      24:24
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_SETUPCLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_RANGE                      23:23
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_QRASTCLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_RANGE                       22:22
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_PSEQCLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_RANGE                        21:21
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_IDXCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_RANGE                        20:20
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_FDCCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_RANGE                        19:19
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_DWRCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_RANGE                       18:18
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_CLIPCLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_RANGE                     17:17
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ATRASTCLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_RANGE                        16:16
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR3D_ALUCLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_RANGE                     15:15
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_VI_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_RANGE                    14:14
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPE_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_RANGE                 13:13
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MPCORE_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_RANGE                     12:12
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_MC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_RANGE                    11:11
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_KBC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_RANGE                 10:10
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RIF_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_RANGE                        9:9
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_RDMA_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_RANGE                   8:8
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_INTFC_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_RANGE                     7:7
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SHIFT                        _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_RANGE                        6:6
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_HC_CDMA_CLK_OVR_ON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_RANGE                   5:5
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_GR2D_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_RANGE                    4:4
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EPP_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_RANGE                    3:3
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_EMC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_RANGE                    2:2
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DCB_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_RANGE                     1:1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0_DC_CLK_OVR_ON_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0  
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0                 _MK_ADDR_CONST(0xfc)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RESET_MASK                      _MK_MASK_CONST(0x3fff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_READ_MASK                       _MK_MASK_CONST(0x3fff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_WRITE_MASK                      _MK_MASK_CONST(0x3fff)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_RANGE                   13:13
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB1_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_RANGE                   12:12
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB3_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_RANGE                   11:11
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_AVPC_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_RANGE                   10:10
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_USB2_CLK_OVR_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_RANGE                       9:9
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEC_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_RANGE                       8:8
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEB_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_RANGE                       7:7
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_REGS_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_RANGE                       6:6
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MPEA_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_RANGE                       5:5
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_PMEM_CLK_OVR_ON_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_RANGE                 4:4
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_IB_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SHIFT                      _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_RANGE                      3:3
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_MEMRD_CLK_OVR_ON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_RANGE                 2:2
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_MPE_RC_CLK_OVR_ON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_RANGE                    1:1
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_CSI_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SHIFT)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_RANGE                    0:0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0_RTC_CLK_OVR_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0                    _MK_ADDR_CONST(0x100)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_VAL                  _MK_MASK_CONST(0xd0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_RESET_MASK                         _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_READ_MASK                  _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_WRITE_MASK                         _MK_MASK_CONST(0xd00000ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_SYNC_CLK_X2                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// 1 = enable I2S1 master clock, disable I2S1 master clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0_I2S1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0                    _MK_ADDR_CONST(0x104)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_VAL                  _MK_MASK_CONST(0xd0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_RESET_MASK                         _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_READ_MASK                  _MK_MASK_CONST(0xd00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_WRITE_MASK                         _MK_MASK_CONST(0xd00000ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLA_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_SYNC_CLK_X2                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// 1 = enable I2S2 master clock, disable I2S2 master clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_MASTER_CLKEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0_I2S2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0                       _MK_ADDR_CONST(0x108)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_RESET_VAL                     _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_RESET_MASK                    _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_READ_MASK                     _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_WRITE_MASK                    _MK_MASK_CONST(0xc00000ff)
+//  00 = pllA_out0
+//  01 = audio SYNC_CLK x 2
+//  10 = pllP_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_RANGE                        31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_DEFAULT                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_INIT_ENUM                    CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_PLLA_OUT0                    _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_SYNC_CLK_X2                  _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_PLLP_OUT0                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_SRC_CLK_M                        _MK_ENUM_CONST(3)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_RANGE                    7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0_SPDIFOUT_CLK_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0                        _MK_ADDR_CONST(0x10c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SECURE                         0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_WORD_COUNT                     0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_RESET_MASK                     _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_READ_MASK                      _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_WRITE_MASK                     _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = 1'b0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_FIELD                  (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_RANGE                  31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_INIT_ENUM                      PLLP_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_PLLP_OUT0                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_PLLC_OUT0                      _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_SRC_PLLM_OUT0                      _MK_ENUM_CONST(2)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_FIELD                      (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_RANGE                      7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0_SPDIFIN_CLK_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0                     _MK_ADDR_CONST(0x110)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_RESET_VAL                   _MK_MASK_CONST(0x30000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_RESET_MASK                  _MK_MASK_CONST(0x700000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_READ_MASK                   _MK_MASK_CONST(0x700000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_WRITE_MASK                  _MK_MASK_CONST(0x700000ff)
+//  000 = pllP_out0
+//  001 = pllC_out0
+//  010 = audio SYNC_CLK x 2
+//  011 = clk_m
+//  100 = clk_s
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x7) << CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_RANGE                   30:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_SYNC_CLK_X2                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_SRC_CLK_S                   _MK_ENUM_CONST(4)
+
+//  N  = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0_PWM_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0                    _MK_ADDR_CONST(0x114)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0                    _MK_ADDR_CONST(0x118)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0_SBC2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0                    _MK_ADDR_CONST(0x11c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0_SBC3_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0                     _MK_ADDR_CONST(0x120)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0_XIO_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0                    _MK_ADDR_CONST(0x124)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_RESET_MASK                         _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_READ_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_WRITE_MASK                         _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_RANGE                     15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0                 _MK_ADDR_CONST(0x128)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_RESET_VAL                       _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_RESET_MASK                      _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_READ_MASK                       _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_WRITE_MASK                      _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_RANGE                       15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0_DVC_I2C_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0                     _MK_ADDR_CONST(0x12c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0_TWC_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Reserved address 304 [0x130] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0                    _MK_ADDR_CONST(0x134)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0_SBC1_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0                   _MK_ADDR_CONST(0x138)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0_DISP1_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0                   _MK_ADDR_CONST(0x13c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0_DISP2_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0                     _MK_ADDR_CONST(0x140)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLD_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0_CVE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0                     _MK_ADDR_CONST(0x144)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0_IDE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0                      _MK_ADDR_CONST(0x148)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_RESET_MASK                   _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_READ_MASK                    _MK_MASK_CONST(0xc30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_WRITE_MASK                   _MK_MASK_CONST(0xc30000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_INIT_ENUM                 PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SRC_PLLA_OUT0                 _MK_ENUM_CONST(3)
+
+// 0 = pd2vi_clk, 1 = vi_sensor_clk.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT                  _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_RANGE                  25:25
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_PD2VI_CLK_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0 = select internal clock, 1 = select external clock (pd2vi_clk).
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_RANGE                     24:24
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INIT_ENUM                 INTERNAL
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_INTERNAL                  _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_SEL_EXTERNAL                  _MK_ENUM_CONST(1)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_0_VI_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 332 [0x14c] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0                  _MK_ADDR_CONST(0x150)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_RESET_MASK                       _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_READ_MASK                        _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_WRITE_MASK                       _MK_MASK_CONST(0xc08f00ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_INIT_ENUM                 CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_SRC_CLK_M                     _MK_ENUM_CONST(3)
+
+// 1 = use internal feedback clock.
+// 0 = use external feedback clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 16-tap of internal feedback clock delay.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_SHIFT                  _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_RANGE                  19:16
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_INT_FB_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0_SDMMC1_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0                  _MK_ADDR_CONST(0x154)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_RESET_MASK                       _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_READ_MASK                        _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_WRITE_MASK                       _MK_MASK_CONST(0xc08f00ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_INIT_ENUM                 CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_SRC_CLK_M                     _MK_ENUM_CONST(3)
+
+// 1 = use internal feedback clock.
+// 0 = use external feedback clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 16-tap of internal feedback clock delay.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_SHIFT                  _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_RANGE                  19:16
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_INT_FB_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0_SDMMC2_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0                     _MK_ADDR_CONST(0x158)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_RESET_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_READ_MASK                   _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_WRITE_MASK                  _MK_MASK_CONST(0xc000ffff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+//  if all 0's, this idle divisor field will not be use.
+//  for non-zero values, when host1x is idle, this field will be use
+//  instead of G3D_CLK_DIVISOR.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_SHIFT                      _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_FIELD                      (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_RANGE                      15:8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_IDLE_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0_G3D_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0                     _MK_ADDR_CONST(0x15c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_RESET_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_READ_MASK                   _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_WRITE_MASK                  _MK_MASK_CONST(0xc000ffff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+//  if all 0's, this idle divisor field will not be use.
+//  for non-zero values, when host1x is idle, this field will be use
+//  instead of G2D_CLK_DIVISOR.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_SHIFT                      _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_FIELD                      (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_RANGE                      15:8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_IDLE_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0_G2D_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0                 _MK_ADDR_CONST(0x160)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_SECURE                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_WORD_COUNT                      0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_RESET_VAL                       _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_RESET_MASK                      _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_READ_MASK                       _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_WRITE_MASK                      _MK_MASK_CONST(0xc00000ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0_NDFLASH_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0                  _MK_ADDR_CONST(0x164)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_RESET_MASK                       _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_READ_MASK                        _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_WRITE_MASK                       _MK_MASK_CONST(0xc08f00ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_INIT_ENUM                 CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_SRC_CLK_M                     _MK_ENUM_CONST(3)
+
+// 1 = use internal feedback clock.
+// 0 = use external feedback clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 16-tap of internal feedback clock delay.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_SHIFT                  _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_RANGE                  19:16
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_INT_FB_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0_SDMMC4_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0                    _MK_ADDR_CONST(0x168)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+// 00 = pllP_out0
+// 01 = pllC_out0
+// 10 = pllM_out0
+// 11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+// N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0_VFIR_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0                     _MK_ADDR_CONST(0x16c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_INIT_ENUM                       PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0_EPP_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0                     _MK_ADDR_CONST(0x170)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_INIT_ENUM                       PLLM_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_SRC_PLLA_OUT0                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0_MPE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0                    _MK_ADDR_CONST(0x174)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0_MIPI_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0                   _MK_ADDR_CONST(0x178)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0                   _MK_ADDR_CONST(0x17c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0                  _MK_ADDR_CONST(0x180)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_RESET_MASK                       _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_READ_MASK                        _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_WRITE_MASK                       _MK_MASK_CONST(0xc000ffff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_INIT_ENUM                 PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_SRC_PLLA_OUT0                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+//  if all 0's, this idle divisor field will not be use.
+//  for non-zero values, when host1x is idle, this field will be use
+//  instead of HOST1X_CLK_DIVISOR.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_SHIFT                        _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_FIELD                        (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_RANGE                        15:8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_IDLE_DIVISOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0_HOST1X_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 388 [0x184] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0                     _MK_ADDR_CONST(0x188)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLD_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0_TVO_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0                    _MK_ADDR_CONST(0x18c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLD_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0_HDMI_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 400 [0x190] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0                   _MK_ADDR_CONST(0x194)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllD_out0
+//  10 = pllC_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLD_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0_TVDAC_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0                    _MK_ADDR_CONST(0x198)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_RESET_MASK                         _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_READ_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_WRITE_MASK                         _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_RANGE                     15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0                     _MK_ADDR_CONST(0x19c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_RESET_MASK                  _MK_MASK_CONST(0xe30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_READ_MASK                   _MK_MASK_CONST(0xe30000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_WRITE_MASK                  _MK_MASK_CONST(0xe30000ff)
+// 00 = pllM_out0
+// 01 = pllC_out0
+// 10 = pllP_out0
+// 11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT                        _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_FIELD                        (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_RANGE                        31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_INIT_ENUM                    CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLM_OUT0                    _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLC_OUT0                    _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_PLLP_OUT0                    _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_SRC_CLK_M                        _MK_ENUM_CONST(3)
+
+// 1 = use un-divided PllM_out0 as clock source.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_RANGE                   29:29
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_USE_PLLM_UD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  1 = enable EMC 2X clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_ENB_ENABLE                       _MK_ENUM_CONST(1)
+
+//  1 = enable EMC 1X clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SHIFT                        _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_RANGE                        24:24
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_INIT_ENUM                    DISABLE
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_DISABLE                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_1X_CLK_ENB_ENABLE                       _MK_ENUM_CONST(1)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_FIELD                    (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_RANGE                    7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0_EMC_2X_CLK_DIVISOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0                   _MK_ADDR_CONST(0x1a0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Reserved address 420 [0x1a4] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0                       _MK_ADDR_CONST(0x1a8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_SECURE                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_WORD_COUNT                    0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_RESET_MASK                    _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_READ_MASK                     _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_WRITE_MASK                    _MK_MASK_CONST(0xc00000ff)
+//  00 = pllM_out0
+//  01 = pllC_out0
+//  10 = pllP_out0
+//  11 = pllA_out0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_INIT_ENUM                   PLLM_OUT0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_SRC_PLLA_OUT0                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0_VI_SENSOR_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 428 [0x1ac] 
+
+// Reserved address 432 [0x1b0] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0                    _MK_ADDR_CONST(0x1b4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_RESET_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_READ_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_WRITE_MASK                         _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_RANGE                     7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0_SBC4_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0                    _MK_ADDR_CONST(0x1b8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SECURE                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_WORD_COUNT                         0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_RESET_VAL                  _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_RESET_MASK                         _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_READ_MASK                  _MK_MASK_CONST(0xc000ffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_WRITE_MASK                         _MK_MASK_CONST(0xc000ffff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SHIFT                 _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_FIELD                 (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_RANGE                 31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_DEFAULT                       _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_INIT_ENUM                     CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PLLP_OUT0                     _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PLLC_OUT0                     _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PLLM_OUT0                     _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_CLK_M                 _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 1.0x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_FIELD                     (_MK_MASK_CONST(0xffff) << CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_RANGE                     15:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0                  _MK_ADDR_CONST(0x1bc)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_RESET_MASK                       _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_READ_MASK                        _MK_MASK_CONST(0xc08f00ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_WRITE_MASK                       _MK_MASK_CONST(0xc08f00ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_INIT_ENUM                 CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_SRC_CLK_M                     _MK_ENUM_CONST(3)
+
+// 1 = use internal feedback clock.
+// 0 = use external feedback clock.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_RANGE                  23:23
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 16-tap of internal feedback clock delay.
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_SHIFT                  _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_FIELD                  (_MK_MASK_CONST(0xf) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_RANGE                  19:16
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_INT_FB_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0_SDMMC3_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0                   _MK_ADDR_CONST(0x1c0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0_UARTD_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0                   _MK_ADDR_CONST(0x1c4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_RESET_MASK                        _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_READ_MASK                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_WRITE_MASK                        _MK_MASK_CONST(0xc0000000)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0_UARTE_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0                     _MK_ADDR_CONST(0x1c8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0_VDE_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0                     _MK_ADDR_CONST(0x1cc)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0_OWR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0                     _MK_ADDR_CONST(0x1d0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_RESET_VAL                   _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_RESET_MASK                  _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_READ_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_WRITE_MASK                  _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_RANGE                   31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_INIT_ENUM                       CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_PLLP_OUT0                       _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_PLLC_OUT0                       _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_PLLM_OUT0                       _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_SRC_CLK_M                   _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_FIELD                       (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_RANGE                       7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_NOR_CLK_DIVISOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_SHIFT                  _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_FIELD                  (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_RANGE                  31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_DEFAULT                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_INIT_ENUM                      CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_PLLP_OUT0                      _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_PLLC_OUT0                      _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_PLLM_OUT0                      _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_SRC_CLK_M                  _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_FIELD                      (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_RANGE                      7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0_SNOR_CLK_DIVISOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0                   _MK_ADDR_CONST(0x1d4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SECURE                    0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_WORD_COUNT                        0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_RESET_VAL                         _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_RESET_MASK                        _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_READ_MASK                         _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_WRITE_MASK                        _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_FIELD                       (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_RANGE                       31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_DEFAULT                     _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_INIT_ENUM                   CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLP_OUT0                   _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLC_OUT0                   _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_PLLM_OUT0                   _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_SRC_CLK_M                       _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_FIELD                   (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_RANGE                   7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0_CSITE_CLK_DIVISOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 472 [0x1d8] 
+
+// Reserved address 476 [0x1dc] 
+
+// Reserved address 480 [0x1e0] 
+
+// Reserved address 484 [0x1e4] 
+
+// Reserved address 488 [0x1e8] 
+
+// Reserved address 492 [0x1ec] 
+
+// Reserved address 496 [0x1f0] 
+
+// Reserved address 500 [0x1f4] 
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_LA_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0                      _MK_ADDR_CONST(0x1f8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_RESET_VAL                    _MK_MASK_CONST(0xc0000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_RESET_MASK                   _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_READ_MASK                    _MK_MASK_CONST(0xc00000ff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_WRITE_MASK                   _MK_MASK_CONST(0xc00000ff)
+//  00 = pllP_out0
+//  01 = pllC_out0
+//  10 = pllM_out0
+//  11 = clk_m
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SHIFT                     _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_FIELD                     (_MK_MASK_CONST(0x3) << CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_RANGE                     31:30
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_DEFAULT                   _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_INIT_ENUM                 CLK_M
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLP_OUT0                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLC_OUT0                 _MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_PLLM_OUT0                 _MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_SRC_CLK_M                     _MK_ENUM_CONST(3)
+
+//  N = Divide by (n+1) (lsb denote 0.5x)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_FIELD                 (_MK_MASK_CONST(0xff) << CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_RANGE                 7:0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_LA_0_LA_CLK_DIVISOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0  
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0                     _MK_ADDR_CONST(0x1fc)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_SECURE                      0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_WORD_COUNT                  0x1
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_RESET_MASK                  _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_READ_MASK                   _MK_MASK_CONST(0x10000000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_WRITE_MASK                  _MK_MASK_CONST(0x10000000)
+//  0 = external oscillator
+//  1 = internal PLL_S
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_SHIFT                   _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_RANGE                   28:28
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_INIT_ENUM                       EXT_OSC
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_EXT_OSC                 _MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0_OSC_CLK_SRC_INT_PLLS_OUT                    _MK_ENUM_CONST(1)
+
+
+// Register CLK_RST_CONTROLLER_LOCK_BOND_OUT_0  
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0                      _MK_ADDR_CONST(0x200)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+// 1 = lock all BOND_OUT_[L,H,U] registers.
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SHIFT)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_RANGE                      0:0
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_LOCK_BOND_OUT_0_LOCK_BOND_OUT_REG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 516 [0x204] 
+
+// Reserved address 520 [0x208] 
+
+// Reserved address 524 [0x20c] 
+
+// Reserved address 528 [0x210] 
+
+// Reserved address 532 [0x214] 
+
+// Reserved address 536 [0x218] 
+
+// Reserved address 540 [0x21c] 
+
+// Reserved address 544 [0x220] 
+
+// Reserved address 548 [0x224] 
+
+// Reserved address 552 [0x228] 
+
+// Reserved address 556 [0x22c] 
+
+// Reserved address 560 [0x230] 
+
+// Reserved address 564 [0x234] 
+
+// Reserved address 568 [0x238] 
+
+// Reserved address 572 [0x23c] 
+
+// Reserved address 576 [0x240] 
+
+// Reserved address 580 [0x244] 
+
+// Reserved address 584 [0x248] 
+
+// Reserved address 588 [0x24c] 
+
+// Reserved address 592 [0x250] 
+
+// Reserved address 596 [0x254] 
+
+// Reserved address 600 [0x258] 
+
+// Reserved address 604 [0x25c] 
+
+// Reserved address 608 [0x260] 
+
+// Reserved address 612 [0x264] 
+
+// Reserved address 616 [0x268] 
+
+// Reserved address 620 [0x26c] 
+
+// Reserved address 624 [0x270] 
+
+// Reserved address 628 [0x274] 
+
+// Reserved address 632 [0x278] 
+
+// Reserved address 636 [0x27c] 
+
+// Reserved address 640 [0x280] 
+
+// Reserved address 644 [0x284] 
+
+// Reserved address 648 [0x288] 
+
+// Reserved address 652 [0x28c] 
+
+// Reserved address 656 [0x290] 
+
+// Reserved address 660 [0x294] 
+
+// Reserved address 664 [0x298] 
+
+// Reserved address 668 [0x29c] 
+
+// Reserved address 672 [0x2a0] 
+
+// Reserved address 676 [0x2a4] 
+
+// Reserved address 680 [0x2a8] 
+
+// Reserved address 684 [0x2ac] 
+
+// Reserved address 688 [0x2b0] 
+
+// Reserved address 692 [0x2b4] 
+
+// Reserved address 696 [0x2b8] 
+
+// Reserved address 700 [0x2bc] 
+
+// Reserved address 704 [0x2c0] 
+
+// Reserved address 708 [0x2c4] 
+
+// Reserved address 712 [0x2c8] 
+
+// Reserved address 716 [0x2cc] 
+
+// Reserved address 720 [0x2d0] 
+
+// Reserved address 724 [0x2d4] 
+
+// Reserved address 728 [0x2d8] 
+
+// Reserved address 732 [0x2dc] 
+
+// Reserved address 736 [0x2e0] 
+
+// Reserved address 740 [0x2e4] 
+
+// Reserved address 744 [0x2e8] 
+
+// Reserved address 748 [0x2ec] 
+
+// Reserved address 752 [0x2f0] 
+
+// Reserved address 756 [0x2f4] 
+
+// Reserved address 760 [0x2f8] 
+
+// Reserved address 764 [0x2fc] 
+
+// Register CLK_RST_CONTROLLER_RST_DEV_L_SET_0  
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0                      _MK_ADDR_CONST(0x300)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_RESET_VAL                    _MK_MASK_CONST(0x3ffffec9)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_RESET_MASK                   _MK_MASK_CONST(0xbfffffff)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_READ_MASK                    _MK_MASK_CONST(0xbfffffff)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xbfffffff)
+// set reset COP cache controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_RANGE                 31:31
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CACHE2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset vector co-processor.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VCP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset HOST1X.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_RANGE                 28:28
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_HOST1X_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset DISP1 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_RANGE                  27:27
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset DISP2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_RANGE                  26:26
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_DISP2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset IDE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_IDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset 3D controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_RANGE                     24:24
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_3D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set reset ISP controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_RANGE                    23:23
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_ISP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset USB controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_USBD_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset 2D graphics engine controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_RANGE                     21:21
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_2D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set reset VI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_RANGE                     20:20
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_VI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set reset EPP controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_RANGE                    19:19
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_EPP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset I2S 2 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset Pulse Width Modulator
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_PWM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset Three Wire Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TWC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset SDMMC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_SHIFT                 _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_RANGE                 15:15
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC4_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset SDMMC1 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_SHIFT                 _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_RANGE                 14:14
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC1_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset NAND flash controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_RANGE                        13:13
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_NDFLASH_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set reset I2C1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2C1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset I2S 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_I2S1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset SPDIF Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_RANGE                  10:10
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SPDIF_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset SDMMC2 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_SHIFT                 _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_RANGE                 9:9
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_SDMMC2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset GPIO Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_GPIO_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_RANGE                  7:7
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset UARTA Controller 
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_RANGE                  6:6
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_UARTA_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset Timer Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TMR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset RTC Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_RTC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset AC97 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_AC97_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Write 1 to pulse System Reset Signal.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_SHIFT                       _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_RANGE                       2:2
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_TRIG_SYS_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set reset COP.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_COP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset CPU.
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_SET_0_SET_CPU_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEV_L_CLR_0  
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0                      _MK_ADDR_CONST(0x304)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x3ffffec9)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_RESET_MASK                   _MK_MASK_CONST(0xbffffffb)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_READ_MASK                    _MK_MASK_CONST(0xbffffffb)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xbffffffb)
+// clear reset COP cache controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_SHIFT                 _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_RANGE                 31:31
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CACHE2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset vector co-processor.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VCP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset HOST1X.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_SHIFT                 _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_RANGE                 28:28
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_HOST1X_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset DISP1 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_SHIFT                  _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_RANGE                  27:27
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP1_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset DISP2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_RANGE                  26:26
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_DISP2_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset IDE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_IDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset 3D controlelr.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_SHIFT                     _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_RANGE                     24:24
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_3D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear reset ISP controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_SHIFT                    _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_RANGE                    23:23
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_ISP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset USB controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_USBD_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset 2D graphics engine controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_SHIFT                     _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_RANGE                     21:21
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_2D_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear reset VI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_SHIFT                     _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_RANGE                     20:20
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_VI_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear reset EPP controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_SHIFT                    _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_RANGE                    19:19
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_EPP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset I2S 2 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset Pulse Width Modulator
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_PWM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset Three Wire Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TWC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset SDMMC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_SHIFT                 _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_RANGE                 15:15
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC4_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset SDMMC1 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_SHIFT                 _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_RANGE                 14:14
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC1_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset NAND flash controller.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_RANGE                        13:13
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_NDFLASH_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear reset I2C1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2C1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset I2S 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_I2S1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset SPDIF Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_SHIFT                  _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_RANGE                  10:10
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SPDIF_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset SDMMC2 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_SHIFT                 _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_RANGE                 9:9
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_SDMMC2_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset GPIO Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_SHIFT                   _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_RANGE                   8:8
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_GPIO_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_SHIFT                  _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_RANGE                  7:7
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTB_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset UARTA Controller 
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_SHIFT                  _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_RANGE                  6:6
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_UARTA_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset Timer Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_SHIFT                    _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_RANGE                    5:5
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_TMR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset RTC Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_RTC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset AC97 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_AC97_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset COP.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_SHIFT                    _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_RANGE                    1:1
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_COP_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset CPU.
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_L_CLR_0_CLR_CPU_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEV_H_SET_0  
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0                      _MK_ADDR_CONST(0x308)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_RESET_VAL                    _MK_MASK_CONST(0xfefffb77)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// set reset BSEV controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_RANGE                   31:31
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEV_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset BSEA controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_RANGE                   30:30
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_BSEA_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset VDE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_VDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset MPE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MPE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset USB3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_RANGE                   27:27
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset USB2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_SHIFT                   _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_RANGE                   26:26
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_USB2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset EMC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_EMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset UART C Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_RANGE                  23:23
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_UARTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset I2C 2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_I2C2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset TVDAC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_RANGE                  21:21
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVDAC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset CSI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_RANGE                    20:20
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_CSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset HDMI
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_RANGE                   19:19
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_HDMI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset MIPI base-band controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MIPI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset TVO/CVE controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_TVO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset DSI controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset DVC-I2C Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_RANGE                        15:15
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_DVC_I2C_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set reset SBC 3 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_RANGE                   14:14
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset XIO controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_RANGE                    13:13
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_XIO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset SBC 2 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset SPI 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SPI1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_RANGE                    10:10
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_NOR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_RANGE                   10:10
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SNOR_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset SBC 1 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_SBC1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset KFuse controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_RANGE                  8:8
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KFUSE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset Fuse controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_RANGE                   7:7
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_FUSE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset PMC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_RANGE                    6:6
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_PMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset statistic monitor
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_STAT_MON_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set reset Keyboard controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_KBC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset APB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_RANGE                 2:2
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_APBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset AHB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_RANGE                 1:1
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_AHBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset MC.
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_SET_0_SET_MEM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEV_H_CLR_0  
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0                      _MK_ADDR_CONST(0x30c)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_RESET_VAL                    _MK_MASK_CONST(0xfefffb77)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// clear reset BSEV controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_SHIFT                   _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_RANGE                   31:31
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEV_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset BSEA controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_RANGE                   30:30
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_BSEA_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset VDE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_SHIFT                    _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_RANGE                    29:29
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_VDE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset MPE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MPE_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset USB3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_SHIFT                   _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_RANGE                   27:27
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset USB2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_SHIFT                   _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_RANGE                   26:26
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_USB2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset EMC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_SHIFT                    _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_RANGE                    25:25
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_EMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset UART C Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_SHIFT                  _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_RANGE                  23:23
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_UARTC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset I2C 2 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_SHIFT                   _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_RANGE                   22:22
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_I2C2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset TVDAC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_SHIFT                  _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_RANGE                  21:21
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVDAC_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset CSI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_SHIFT                    _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_RANGE                    20:20
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_CSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset HDMI
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_SHIFT                   _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_RANGE                   19:19
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_HDMI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset MIPI base-band controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_SHIFT                   _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_RANGE                   18:18
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MIPI_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset TVO/CVE controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_SHIFT                    _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_RANGE                    17:17
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_TVO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset DSI controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_SHIFT                    _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_RANGE                    16:16
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DSI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset DVC-I2C Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_SHIFT                        _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_RANGE                        15:15
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_DVC_I2C_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear reset SBC 3 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_SHIFT                   _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_RANGE                   14:14
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset XIO controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_RANGE                    13:13
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_XIO_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset SBC 2 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_SHIFT                   _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_RANGE                   12:12
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC2_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset SPI 1 Controller
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_SHIFT                   _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_RANGE                   11:11
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SPI1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_SHIFT                    _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_RANGE                    10:10
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_NOR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset NOR Flash Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_SHIFT                   _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_RANGE                   10:10
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SNOR_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset SBC 1 Controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_SHIFT                   _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_RANGE                   9:9
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_SBC1_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset KFuse controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_SHIFT                  _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_RANGE                  8:8
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KFUSE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset Fuse controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_SHIFT                   _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_RANGE                   7:7
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_FUSE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset PMC controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_SHIFT                    _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_RANGE                    6:6
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_PMC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset statistic monitor
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_STAT_MON_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear reset Keyboard controller.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_SHIFT                    _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_RANGE                    4:4
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_KBC_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset APB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_SHIFT                 _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_RANGE                 2:2
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_APBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset AHB-DMA.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_SHIFT                 _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_RANGE                 1:1
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_AHBDMA_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset MC.
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_SHIFT                    _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_RANGE                    0:0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR_0_CLR_MEM_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEV_U_SET_0  
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0                      _MK_ADDR_CONST(0x310)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_RESET_VAL                    _MK_MASK_CONST(0x15ff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_RESET_MASK                   _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_READ_MASK                    _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff)
+// set reset LA logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_RANGE                     12:12
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_LA_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set reset AVPUCQ logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_SHIFT                 _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_RANGE                 11:11
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AVPUCQ_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset PCIEXCLK logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_RANGE                       10:10
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIEXCLK_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set reset CSITE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_RANGE                  9:9
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_CSITE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset AFI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_RANGE                    8:8
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_AFI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset OWR controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_RANGE                    7:7
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_OWR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set reset PCIE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_SHIFT                   _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_RANGE                   6:6
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_PCIE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset SDMMC3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_RANGE                 5:5
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SDMMC3_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set reset SBC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_RANGE                   4:4
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SBC4_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset I2C3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_I2C3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set reset UARTE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_RANGE                  2:2
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset UARTD controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_SHIFT                  _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_RANGE                  1:1
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_UARTD_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set reset SPEEDO controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_RANGE                 0:0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_SET_0_SET_SPEEDO_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_DEV_U_CLR_0  
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0                      _MK_ADDR_CONST(0x314)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x15ff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_READ_MASK                    _MK_MASK_CONST(0x1fff)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff)
+// clear reset LA logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_SHIFT                     _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_RANGE                     12:12
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_LA_RST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear reset AVPUCQ logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_SHIFT                 _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_RANGE                 11:11
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AVPUCQ_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset PCIEXCLK logic.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_RANGE                       10:10
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIEXCLK_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear reset CSITE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_SHIFT                  _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_RANGE                  9:9
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_CSITE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset AFI controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_SHIFT                    _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_RANGE                    8:8
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_AFI_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset OWR controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_SHIFT                    _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_RANGE                    7:7
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_DEFAULT                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_OWR_RST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear reset PCIE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_SHIFT                   _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_RANGE                   6:6
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_PCIE_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset SDMMC3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_SHIFT                 _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_RANGE                 5:5
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SDMMC3_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear reset SBC4 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_SHIFT                   _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_RANGE                   4:4
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SBC4_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset I2C3 controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_SHIFT                   _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_RANGE                   3:3
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_I2C3_RST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear reset UARTE controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_SHIFT                  _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_RANGE                  2:2
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTE_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset UARTD controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_SHIFT                  _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_RANGE                  1:1
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_UARTD_RST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear reset SPEEDO controller.
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_SHIFT                 _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_SHIFT)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_RANGE                 0:0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_DEFAULT                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_DEV_U_CLR_0_CLR_SPEEDO_RST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 792 [0x318] 
+
+// Reserved address 796 [0x31c] 
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_L_SET_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0                      _MK_ADDR_CONST(0x320)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_RESET_VAL                    _MK_MASK_CONST(0x80000130)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_RESET_MASK                   _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_READ_MASK                    _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xbffffff9)
+// set enable clock to COP cache controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_SHIFT                     _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_RANGE                     31:31
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CACHE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to vector co-processor.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_SHIFT                        _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_RANGE                        29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VCP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to HOST1X.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_SHIFT                     _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_RANGE                     28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_HOST1X_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to DISP1 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_SHIFT                      _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_RANGE                      27:27
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to DISP2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_SHIFT                      _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_RANGE                      26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_DISP2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to IDE controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_IDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to 3D controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_SHIFT                 _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_RANGE                 24:24
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_3D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set enable clock to ISP controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_SHIFT                        _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_RANGE                        23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to USB controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_RANGE                       22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_USBD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to 2D graphics engine.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_SHIFT                 _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_RANGE                 21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_2D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set enable clock to VI controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_RANGE                 20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_VI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set enable clock to EPP controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_SHIFT                        _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_RANGE                        19:19
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_EPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to I2S 2 controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_RANGE                       18:18
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_SHIFT                        _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_RANGE                        17:17
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_PWM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_RANGE                        16:16
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TWC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to SDMMC4 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_SHIFT                     _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_RANGE                     15:15
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to SDMMC1 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_SHIFT                     _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_RANGE                     14:14
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to NAND flash controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_RANGE                    13:13
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_NDFLASH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set enable clock to I2C1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_SHIFT                       _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_RANGE                       12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2C1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to I2S1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_SHIFT                       _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_RANGE                       11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_I2S1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to SPDIF Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_SHIFT                      _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_RANGE                      10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SPDIF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to SDMMC2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_SHIFT                     _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_RANGE                     9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_SDMMC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to GPIO Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_RANGE                       8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_GPIO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_SHIFT                      _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_RANGE                      7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to UARTA Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_SHIFT                      _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_RANGE                      6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_UARTA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to Timer Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_SHIFT                        _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_RANGE                        5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_TMR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to RTC Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_RANGE                        4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_RTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to AC97 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_SHIFT                       _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_RANGE                       3:3
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to CPU.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_RANGE                        0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_SET_0_SET_CLK_ENB_CPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0                      _MK_ADDR_CONST(0x324)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x80000130)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_RESET_MASK                   _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_READ_MASK                    _MK_MASK_CONST(0xbffffff9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xbffffff9)
+// clear enable clock to COP cache controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_SHIFT                     _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_RANGE                     31:31
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CACHE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to vector co-processor.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_SHIFT                        _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_RANGE                        29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VCP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to HOST1X.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_SHIFT                     _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_RANGE                     28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_HOST1X_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to DISP1 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_SHIFT                      _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_RANGE                      27:27
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to DISP2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_SHIFT                      _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_RANGE                      26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_DISP2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to IDE controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_IDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to 3D controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_SHIFT                 _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_RANGE                 24:24
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_3D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear enable clock to ISP controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_SHIFT                        _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_RANGE                        23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to USB controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_RANGE                       22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_USBD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to 2D graphics engine.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_SHIFT                 _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_RANGE                 21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_2D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear enable clock to VI controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_SHIFT                 _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_RANGE                 20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_VI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear enable clock to EPP controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_SHIFT                        _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_RANGE                        19:19
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_EPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to I2S 2 controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_RANGE                       18:18
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to PWM (Pulse Width Modulator)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_SHIFT                        _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_RANGE                        17:17
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_PWM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to 3-Wire Interface Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_RANGE                        16:16
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TWC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to SDMMC4 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_SHIFT                     _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_RANGE                     15:15
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to SDMMC1 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_SHIFT                     _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_RANGE                     14:14
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to NAND flash controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_SHIFT                    _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_RANGE                    13:13
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_NDFLASH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear enable clock to I2C1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_SHIFT                       _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_RANGE                       12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2C1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to I2S1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_SHIFT                       _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_RANGE                       11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_I2S1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to SPDIF Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_SHIFT                      _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_RANGE                      10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SPDIF_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to SDMMC2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_SHIFT                     _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_RANGE                     9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_SDMMC2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to GPIO Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_RANGE                       8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_GPIO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to UARTB/VFIR Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_SHIFT                      _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_RANGE                      7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to UARTA Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_SHIFT                      _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_RANGE                      6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_UARTA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to Timer Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_SHIFT                        _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_RANGE                        5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_TMR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to RTC Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_RANGE                        4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_RTC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to AC97 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_SHIFT                       _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_RANGE                       3:3
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_AC97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to CPU.
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_RANGE                        0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0_CLR_CLK_ENB_CPU_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_H_SET_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0                      _MK_ADDR_CONST(0x328)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_RESET_VAL                    _MK_MASK_CONST(0x400)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// set enable clock to BSEV Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_RANGE                       31:31
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to BSEA Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_RANGE                       30:30
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_BSEA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to VDE Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_SHIFT                        _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_RANGE                        29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_VDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to MPE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_RANGE                        28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to USB3 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_RANGE                       27:27
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to USB2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_RANGE                       26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_USB2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to EMC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_EMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to UART-C Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_RANGE                      23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_UARTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to I2C2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_RANGE                       22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_I2C2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to TVDAC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_SHIFT                      _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_RANGE                      21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVDAC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to CSI controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_SHIFT                        _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_RANGE                        20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_CSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to HDMI
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_SHIFT                       _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_RANGE                       19:19
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_HDMI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to MIPI base-band controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_RANGE                       18:18
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to TVO/CVE controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_SHIFT                        _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_RANGE                        17:17
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_TVO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to DSI controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_RANGE                        16:16
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to DVC-I2C Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_SHIFT                    _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_RANGE                    15:15
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_DVC_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set enable clock to SBC 3 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_SHIFT                       _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_RANGE                       14:14
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to XIO Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_RANGE                        13:13
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_XIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to SBC 2 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_SHIFT                       _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_RANGE                       12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to SPI 1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_SHIFT                       _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_RANGE                       11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SPI1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_SHIFT                        _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_RANGE                        10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_NOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_RANGE                       10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SNOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to SBC 1 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_RANGE                       9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_SBC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to KFUSE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_SHIFT                      _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_RANGE                      8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KFUSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to FUSE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_SHIFT                       _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_RANGE                       7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_FUSE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to PMC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_SHIFT                        _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_RANGE                        6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to statistic monitor.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_RANGE                   5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_STAT_MON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set enable clock to keyboard controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_RANGE                        4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_KBC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to APB-DMA.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_SHIFT                     _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_RANGE                     2:2
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_APBDMA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to AHB-DMA.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_RANGE                     1:1
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_AHBDMA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to MC/EMC.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_RANGE                        0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_SET_0_SET_CLK_ENB_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0                      _MK_ADDR_CONST(0x32c)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x400)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_RESET_MASK                   _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_READ_MASK                    _MK_MASK_CONST(0xfefffff7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0xfefffff7)
+// clear enable clock to BSEV Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_SHIFT                       _MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_RANGE                       31:31
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to BSEA Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_SHIFT                       _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_RANGE                       30:30
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_BSEA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to VDE Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_SHIFT                        _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_RANGE                        29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_VDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to MPE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_SHIFT                        _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_RANGE                        28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to USB3 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_SHIFT                       _MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_RANGE                       27:27
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to USB2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_SHIFT                       _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_RANGE                       26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_USB2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to EMC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_SHIFT                        _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_RANGE                        25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_EMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to UART-C Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_RANGE                      23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_UARTC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to I2C2 controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_SHIFT                       _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_RANGE                       22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_I2C2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to TVDAC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_SHIFT                      _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_RANGE                      21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVDAC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to CSI controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_SHIFT                        _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_RANGE                        20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_CSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to HDMI
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_SHIFT                       _MK_SHIFT_CONST(19)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_RANGE                       19:19
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_HDMI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to MIPI base-band controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_SHIFT                       _MK_SHIFT_CONST(18)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_RANGE                       18:18
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MIPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to TVO/CVE controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_SHIFT                        _MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_RANGE                        17:17
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_TVO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to DSI controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_SHIFT                        _MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_RANGE                        16:16
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DSI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to DVC-I2C Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_SHIFT                    _MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_RANGE                    15:15
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_DVC_I2C_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear enable clock to SBC 3 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_SHIFT                       _MK_SHIFT_CONST(14)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_RANGE                       14:14
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to XIO Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_SHIFT                        _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_RANGE                        13:13
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_XIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to SBC 2 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_SHIFT                       _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_RANGE                       12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to SPI 1 Controller
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_SHIFT                       _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_RANGE                       11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SPI1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_SHIFT                        _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_RANGE                        10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_DEFAULT                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_NOR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to NOR Flash Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_SHIFT                       _MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_RANGE                       10:10
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SNOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to SBC 1 Controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_RANGE                       9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_SBC1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to KFUSE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_SHIFT                      _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_RANGE                      8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KFUSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to FUSE controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_SHIFT                       _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_RANGE                       7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_FUSE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to PMC controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_SHIFT                        _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_RANGE                        6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_PMC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to statistic monitor.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_SHIFT                   _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_RANGE                   5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_STAT_MON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear enable clock to keyboard controller.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_SHIFT                        _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_RANGE                        4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_KBC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to APB-DMA.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_SHIFT                     _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_RANGE                     2:2
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_APBDMA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to AHB-DMA.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_SHIFT                     _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_RANGE                     1:1
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_AHBDMA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to MC/EMC.
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_SHIFT                        _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_RANGE                        0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0_CLR_CLK_ENB_MEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_U_SET_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0                      _MK_ADDR_CONST(0x330)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_RESET_VAL                    _MK_MASK_CONST(0x7f00a00)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_RESET_MASK                   _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_READ_MASK                    _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_WRITE_MASK                   _MK_MASK_CONST(0x77f01bff)
+// set enable clock to DEV1 pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_RANGE                   30:30
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV1_OUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set enable clock to DEV2 pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_RANGE                   29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_DEV2_OUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// set enable clock to SUS pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SUS_OUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set enable CLK_M clk doubler.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_M_DOUBLER_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set enable audio sync clk doubler.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_RANGE                       25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable COP cache ram clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_SHIFT                      _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_RANGE                      24:24
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CRAM2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable IRAMD clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_RANGE                      23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable IRAMC clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_SHIFT                      _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_RANGE                      22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_SHIFT                      _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_RANGE                      21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_SHIFT                      _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_RANGE                      20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_IRAMA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to LA.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_RANGE                 12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_LA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// set enable clock to AVPUCQ.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_RANGE                     11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AVPUCQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to CSITE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_SHIFT                      _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_RANGE                      9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_CSITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to AFI.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_SHIFT                        _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_RANGE                        8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_AFI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to OWR.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_SHIFT                        _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_RANGE                        7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// set enable clock to PCIE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_SHIFT                       _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_RANGE                       6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_PCIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to SDMMC3.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_SHIFT                     _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_RANGE                     5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// set enable clock to SBC4.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_SHIFT                       _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_RANGE                       4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SBC4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to I2C3.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_SHIFT                       _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_RANGE                       3:3
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_I2C3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// set enable clock to UARTE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_SHIFT                      _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_RANGE                      2:2
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to UARTD.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_SHIFT                      _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_RANGE                      1:1
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_UARTD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set enable clock to SPEEDO.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_RANGE                     0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_SET_0_SET_CLK_ENB_SPEEDO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0  
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0                      _MK_ADDR_CONST(0x334)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_SECURE                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_WORD_COUNT                   0x1
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_RESET_VAL                    _MK_MASK_CONST(0x7f00a00)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_RESET_MASK                   _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_READ_MASK                    _MK_MASK_CONST(0x77f01bff)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_WRITE_MASK                   _MK_MASK_CONST(0x77f01bff)
+// clear enable clock to DEV1 pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_SHIFT                   _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_RANGE                   30:30
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV1_OUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear enable clock to DEV2 pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_SHIFT                   _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_FIELD                   (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_RANGE                   29:29
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_WOFFSET                 0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_DEV2_OUT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// clear enable clock to SUS pad.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_RANGE                    28:28
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SUS_OUT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// clear enable CLK_M clk doubler.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_SHIFT                  _MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_FIELD                  (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_RANGE                  26:26
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_WOFFSET                        0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_M_DOUBLER_ENB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// clear enable audio sync clk doubler.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_SHIFT                       _MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_RANGE                       25:25
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_SYNC_CLK_DOUBLER_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable COP cache ram clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_SHIFT                      _MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_RANGE                      24:24
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CRAM2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable IRAMD clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_SHIFT                      _MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_RANGE                      23:23
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable IRAMC clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_SHIFT                      _MK_SHIFT_CONST(22)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_RANGE                      22:22
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_SHIFT                      _MK_SHIFT_CONST(21)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_RANGE                      21:21
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable IRAMB clk.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_SHIFT                      _MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_RANGE                      20:20
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_IRAMA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to LA.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_SHIFT                 _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_FIELD                 (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_RANGE                 12:12
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_WOFFSET                       0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_LA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// clear enable clock to AVPUCQ.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_SHIFT                     _MK_SHIFT_CONST(11)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_RANGE                     11:11
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_DEFAULT                   _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AVPUCQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to CSITE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_SHIFT                      _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_RANGE                      9:9
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_CSITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to AFI.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_SHIFT                        _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_RANGE                        8:8
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_AFI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to OWR.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_SHIFT                        _MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_FIELD                        (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_RANGE                        7:7
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_WOFFSET                      0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_OWR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// clear enable clock to PCIE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_SHIFT                       _MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_RANGE                       6:6
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_PCIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to SDMMC3.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_SHIFT                     _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_RANGE                     5:5
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SDMMC3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// clear enable clock to SBC4.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_SHIFT                       _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_RANGE                       4:4
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SBC4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to I2C3.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_SHIFT                       _MK_SHIFT_CONST(3)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_RANGE                       3:3
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_I2C3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// clear enable clock to UARTE.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_SHIFT                      _MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_RANGE                      2:2
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to UARTD.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_SHIFT                      _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_RANGE                      1:1
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_UARTD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// clear enable clock to SPEEDO.
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_SHIFT                     _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_FIELD                     (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_SHIFT)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_RANGE                     0:0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_WOFFSET                   0x0
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0_CLR_CLK_ENB_SPEEDO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 824 [0x338] 
+
+// Reserved address 828 [0x33c] 
+
+// Register CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0  
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0                  _MK_ADDR_CONST(0x340)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_RESET_VAL                        _MK_MASK_CONST(0x2222)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_RESET_MASK                       _MK_MASK_CONST(0x70003333)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_READ_MASK                        _MK_MASK_CONST(0x70003333)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x70003333)
+// 1 = assert nPRESETDBG to the coresight.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_SHIFT                      _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_RANGE                      30:30
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PRESETDBG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = assert nSCURESET to the SCU.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_RANGE                       29:29
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_SCURESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = assert nPERIPHRESET to the CPU.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_PERIPHRESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = assert nDBGRESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_SHIFT                      _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_RANGE                      13:13
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = assert nDBGRESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_RANGE                      12:12
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DBGRESET0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = assert nWDRESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_RANGE                       9:9
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = assert nWDRESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_RANGE                       8:8
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_WDRESET0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = assert nDERESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = assert nDERESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_SHIFT                       _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_RANGE                       4:4
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_DERESET0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = assert nCPURESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_SHIFT                      _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_RANGE                      1:1
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = assert nCPURESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_RANGE                      0:0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0_SET_CPURESET0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0  
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0                  _MK_ADDR_CONST(0x344)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_SECURE                   0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_WORD_COUNT                       0x1
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_RESET_VAL                        _MK_MASK_CONST(0x2222)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_RESET_MASK                       _MK_MASK_CONST(0x70003333)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_READ_MASK                        _MK_MASK_CONST(0x70003333)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_WRITE_MASK                       _MK_MASK_CONST(0x70003333)
+// 1 = deasesrt nPRESETDBG to the coresight.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_SHIFT                      _MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_RANGE                      30:30
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PRESETDBG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nSCURESET to the SCU.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_SHIFT                       _MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_RANGE                       29:29
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_SCURESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nPERIPHRESET to the CPU's interrupt/timer.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_SHIFT                    _MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_FIELD                    (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_RANGE                    28:28
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_WOFFSET                  0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_PERIPHRESET_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nDBGRESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_SHIFT                      _MK_SHIFT_CONST(13)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_RANGE                      13:13
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nDBGRESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_SHIFT                      _MK_SHIFT_CONST(12)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_RANGE                      12:12
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DBGRESET0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nWDRESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_SHIFT                       _MK_SHIFT_CONST(9)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_RANGE                       9:9
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nWDRESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_SHIFT                       _MK_SHIFT_CONST(8)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_RANGE                       8:8
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_WDRESET0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nDERESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_SHIFT                       _MK_SHIFT_CONST(5)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_RANGE                       5:5
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_DEFAULT                     _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nDERESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_SHIFT                       _MK_SHIFT_CONST(4)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_FIELD                       (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_RANGE                       4:4
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_WOFFSET                     0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_DERESET0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nCPURESET to CPU1.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_SHIFT                      _MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_RANGE                      1:1
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = deasesrt nCPURESET to CPU0.
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_SHIFT                      _MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_FIELD                      (_MK_MASK_CONST(0x1) << CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_SHIFT)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_RANGE                      0:0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_WOFFSET                    0x0
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0_CLR_CPURESET0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 840 [0x348] 
+
+// Reserved address 844 [0x34c] 
+
+//
+// REGISTER LIST
+//
+#define LIST_ARCLK_RST_REGS(_op_) \
+_op_(CLK_RST_CONTROLLER_RST_SOURCE_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEVICES_L_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEVICES_H_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEVICES_U_0) \
+_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0) \
+_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0) \
+_op_(CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0) \
+_op_(CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER_0) \
+_op_(CLK_RST_CONTROLLER_SCLK_BURST_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE_0) \
+_op_(CLK_RST_CONTROLLER_PROG_DLY_CLK_0) \
+_op_(CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0) \
+_op_(CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0) \
+_op_(CLK_RST_CONTROLLER_CLK_MASK_ARM_0) \
+_op_(CLK_RST_CONTROLLER_MISC_CLK_ENB_0) \
+_op_(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0) \
+_op_(CLK_RST_CONTROLLER_OSC_CTRL_0) \
+_op_(CLK_RST_CONTROLLER_PLL_LFSR_0) \
+_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_0) \
+_op_(CLK_RST_CONTROLLER_OSC_FREQ_DET_STATUS_0) \
+_op_(CLK_RST_CONTROLLER_PTO_CLK_CNT_CNTL_0) \
+_op_(CLK_RST_CONTROLLER_PTO_CLK_CNT_STATUS_0) \
+_op_(CLK_RST_CONTROLLER_PLLE_SS_CNTL_0) \
+_op_(CLK_RST_CONTROLLER_BOND_OUT_L_0) \
+_op_(CLK_RST_CONTROLLER_BOND_OUT_H_0) \
+_op_(CLK_RST_CONTROLLER_BOND_OUT_U_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLC_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLM_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_OUTA_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_OUTB_0) \
+_op_(CLK_RST_CONTROLLER_PLLP_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_OUT_0) \
+_op_(CLK_RST_CONTROLLER_PLLA_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLU_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLU_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLD_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLD_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLX_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLX_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLE_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLE_MISC_0) \
+_op_(CLK_RST_CONTROLLER_PLLS_BASE_0) \
+_op_(CLK_RST_CONTROLLER_PLLS_MISC_0) \
+_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA_0) \
+_op_(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2S2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_IN_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_PWM_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC3_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_XIO_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DVC_I2C_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_DISP2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CVE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_IDE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_G3D_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_G2D_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NDFLASH_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VFIR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EPP_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MPE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_MIPI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTD_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_UARTE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_VDE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_OWR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_NOR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_LA_0) \
+_op_(CLK_RST_CONTROLLER_CLK_SOURCE_OSC_0) \
+_op_(CLK_RST_CONTROLLER_LOCK_BOND_OUT_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_L_SET_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_L_CLR_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_H_SET_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_H_CLR_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_U_SET_0) \
+_op_(CLK_RST_CONTROLLER_RST_DEV_U_CLR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_L_SET_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_L_CLR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_H_SET_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_H_CLR_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_U_SET_0) \
+_op_(CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0) \
+_op_(CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0) \
+_op_(CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_CLK_RST_CONTROLLER 0x00000000
+
+//
+// ARCLK_RST REGISTER BANKS
+//
+
+#define CLK_RST_CONTROLLER0_FIRST_REG 0x0000 // CLK_RST_CONTROLLER_RST_SOURCE_0
+#define CLK_RST_CONTROLLER0_LAST_REG 0x0018 // CLK_RST_CONTROLLER_CLK_OUT_ENB_U_0
+#define CLK_RST_CONTROLLER1_FIRST_REG 0x0020 // CLK_RST_CONTROLLER_CCLK_BURST_POLICY_0
+#define CLK_RST_CONTROLLER1_LAST_REG 0x0038 // CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_RATE_0
+#define CLK_RST_CONTROLLER2_FIRST_REG 0x0040 // CLK_RST_CONTROLLER_COP_CLK_SKIP_POLICY_0
+#define CLK_RST_CONTROLLER2_LAST_REG 0x0068 // CLK_RST_CONTROLLER_PLLE_SS_CNTL_0
+#define CLK_RST_CONTROLLER3_FIRST_REG 0x0070 // CLK_RST_CONTROLLER_BOND_OUT_L_0
+#define CLK_RST_CONTROLLER3_LAST_REG 0x0078 // CLK_RST_CONTROLLER_BOND_OUT_U_0
+#define CLK_RST_CONTROLLER4_FIRST_REG 0x0080 // CLK_RST_CONTROLLER_PLLC_BASE_0
+#define CLK_RST_CONTROLLER4_LAST_REG 0x0084 // CLK_RST_CONTROLLER_PLLC_OUT_0
+#define CLK_RST_CONTROLLER5_FIRST_REG 0x008c // CLK_RST_CONTROLLER_PLLC_MISC_0
+#define CLK_RST_CONTROLLER5_LAST_REG 0x0094 // CLK_RST_CONTROLLER_PLLM_OUT_0
+#define CLK_RST_CONTROLLER6_FIRST_REG 0x009c // CLK_RST_CONTROLLER_PLLM_MISC_0
+#define CLK_RST_CONTROLLER6_LAST_REG 0x00b4 // CLK_RST_CONTROLLER_PLLA_OUT_0
+#define CLK_RST_CONTROLLER7_FIRST_REG 0x00bc // CLK_RST_CONTROLLER_PLLA_MISC_0
+#define CLK_RST_CONTROLLER7_LAST_REG 0x00c0 // CLK_RST_CONTROLLER_PLLU_BASE_0
+#define CLK_RST_CONTROLLER8_FIRST_REG 0x00cc // CLK_RST_CONTROLLER_PLLU_MISC_0
+#define CLK_RST_CONTROLLER8_LAST_REG 0x00d0 // CLK_RST_CONTROLLER_PLLD_BASE_0
+#define CLK_RST_CONTROLLER9_FIRST_REG 0x00dc // CLK_RST_CONTROLLER_PLLD_MISC_0
+#define CLK_RST_CONTROLLER9_LAST_REG 0x012c // CLK_RST_CONTROLLER_CLK_SOURCE_TWC_0
+#define CLK_RST_CONTROLLER10_FIRST_REG 0x0134 // CLK_RST_CONTROLLER_CLK_SOURCE_SBC1_0
+#define CLK_RST_CONTROLLER10_LAST_REG 0x0148 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_0
+#define CLK_RST_CONTROLLER11_FIRST_REG 0x0150 // CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1_0
+#define CLK_RST_CONTROLLER11_LAST_REG 0x0180 // CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X_0
+#define CLK_RST_CONTROLLER12_FIRST_REG 0x0188 // CLK_RST_CONTROLLER_CLK_SOURCE_TVO_0
+#define CLK_RST_CONTROLLER12_LAST_REG 0x018c // CLK_RST_CONTROLLER_CLK_SOURCE_HDMI_0
+#define CLK_RST_CONTROLLER13_FIRST_REG 0x0194 // CLK_RST_CONTROLLER_CLK_SOURCE_TVDAC_0
+#define CLK_RST_CONTROLLER13_LAST_REG 0x01a0 // CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0
+#define CLK_RST_CONTROLLER14_FIRST_REG 0x01a8 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0
+#define CLK_RST_CONTROLLER14_LAST_REG 0x01a8 // CLK_RST_CONTROLLER_CLK_SOURCE_VI_SENSOR_0
+#define CLK_RST_CONTROLLER15_FIRST_REG 0x01b4 // CLK_RST_CONTROLLER_CLK_SOURCE_SBC4_0
+#define CLK_RST_CONTROLLER15_LAST_REG 0x01d4 // CLK_RST_CONTROLLER_CLK_SOURCE_CSITE_0
+#define CLK_RST_CONTROLLER16_FIRST_REG 0x01f8 // CLK_RST_CONTROLLER_CLK_SOURCE_LA_0
+#define CLK_RST_CONTROLLER16_LAST_REG 0x0200 // CLK_RST_CONTROLLER_LOCK_BOND_OUT_0
+#define CLK_RST_CONTROLLER17_FIRST_REG 0x0300 // CLK_RST_CONTROLLER_RST_DEV_L_SET_0
+#define CLK_RST_CONTROLLER17_LAST_REG 0x0314 // CLK_RST_CONTROLLER_RST_DEV_U_CLR_0
+#define CLK_RST_CONTROLLER18_FIRST_REG 0x0320 // CLK_RST_CONTROLLER_CLK_ENB_L_SET_0
+#define CLK_RST_CONTROLLER18_LAST_REG 0x0334 // CLK_RST_CONTROLLER_CLK_ENB_U_CLR_0
+#define CLK_RST_CONTROLLER19_FIRST_REG 0x0340 // CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET_0
+#define CLK_RST_CONTROLLER19_LAST_REG 0x0344 // CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARCLK_RST_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/ardvc.h b/arch/arm/mach-tegra/nv/include/ap20/ardvc.h
new file mode 100644
index 000000000000..6d9d5486d725
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/ardvc.h
@@ -0,0 +1,5536 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARDVC_H_INC_
+#define ___ARDVC_H_INC_
+
+// Register DVC_CTRL_REG1_0  
+#define DVC_CTRL_REG1_0                 _MK_ADDR_CONST(0x0)
+#define DVC_CTRL_REG1_0_SECURE                  0x0
+#define DVC_CTRL_REG1_0_WORD_COUNT                      0x1
+#define DVC_CTRL_REG1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_CTRL_REG1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define DVC_CTRL_REG1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+//Number of ref_clks to wait for PMU voltage change  request to take effect
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_SHIFT                      _MK_SHIFT_CONST(11)
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_FIELD                      (_MK_MASK_CONST(0x1fffff) << DVC_CTRL_REG1_0_PMU_WAIT_CNT_SHIFT)
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_RANGE                      31:11
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_WOFFSET                    0x0
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x1fffff)
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_PMU_WAIT_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//Enable Interrupt  0: disable (default), 1:Enable
+#define DVC_CTRL_REG1_0_INTR_EN_SHIFT                   _MK_SHIFT_CONST(10)
+#define DVC_CTRL_REG1_0_INTR_EN_FIELD                   (_MK_MASK_CONST(0x1) << DVC_CTRL_REG1_0_INTR_EN_SHIFT)
+#define DVC_CTRL_REG1_0_INTR_EN_RANGE                   10:10
+#define DVC_CTRL_REG1_0_INTR_EN_WOFFSET                 0x0
+#define DVC_CTRL_REG1_0_INTR_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_INTR_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG1_0_INTR_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_INTR_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_INTR_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG1_0_INTR_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// 0:not present , 1:present
+#define DVC_CTRL_REG1_0_EXT_PMU_SHIFT                   _MK_SHIFT_CONST(9)
+#define DVC_CTRL_REG1_0_EXT_PMU_FIELD                   (_MK_MASK_CONST(0x1) << DVC_CTRL_REG1_0_EXT_PMU_SHIFT)
+#define DVC_CTRL_REG1_0_EXT_PMU_RANGE                   9:9
+#define DVC_CTRL_REG1_0_EXT_PMU_WOFFSET                 0x0
+#define DVC_CTRL_REG1_0_EXT_PMU_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_EXT_PMU_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG1_0_EXT_PMU_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_EXT_PMU_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_EXT_PMU_NOT_PRESENT                     _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG1_0_EXT_PMU_PRESENT                 _MK_ENUM_CONST(1)
+
+// Number of iterations to adjust the voltage
+#define DVC_CTRL_REG1_0_NUM_ITER_SHIFT                  _MK_SHIFT_CONST(2)
+#define DVC_CTRL_REG1_0_NUM_ITER_FIELD                  (_MK_MASK_CONST(0x7f) << DVC_CTRL_REG1_0_NUM_ITER_SHIFT)
+#define DVC_CTRL_REG1_0_NUM_ITER_RANGE                  8:2
+#define DVC_CTRL_REG1_0_NUM_ITER_WOFFSET                        0x0
+#define DVC_CTRL_REG1_0_NUM_ITER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_NUM_ITER_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define DVC_CTRL_REG1_0_NUM_ITER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_NUM_ITER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: disable(default) , 1: Fixed Voltage adjust  mode , 2: Continuous mode
+#define DVC_CTRL_REG1_0_MODE_SHIFT                      _MK_SHIFT_CONST(0)
+#define DVC_CTRL_REG1_0_MODE_FIELD                      (_MK_MASK_CONST(0x3) << DVC_CTRL_REG1_0_MODE_SHIFT)
+#define DVC_CTRL_REG1_0_MODE_RANGE                      1:0
+#define DVC_CTRL_REG1_0_MODE_WOFFSET                    0x0
+#define DVC_CTRL_REG1_0_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define DVC_CTRL_REG1_0_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG1_0_MODE_DISABLE                    _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG1_0_MODE_FIX_MODE                   _MK_ENUM_CONST(1)
+#define DVC_CTRL_REG1_0_MODE_CONT_MODE                  _MK_ENUM_CONST(2)
+
+
+// Register DVC_CTRL_REG2_0  
+#define DVC_CTRL_REG2_0                 _MK_ADDR_CONST(0x4)
+#define DVC_CTRL_REG2_0_SECURE                  0x0
+#define DVC_CTRL_REG2_0_WORD_COUNT                      0x1
+#define DVC_CTRL_REG2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_CTRL_REG2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define DVC_CTRL_REG2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Wakeup timer, in terms of number of ref clocks, for voltage adjustment process.
+#define DVC_CTRL_REG2_0_TIMER_CNT_SHIFT                 _MK_SHIFT_CONST(9)
+#define DVC_CTRL_REG2_0_TIMER_CNT_FIELD                 (_MK_MASK_CONST(0x7fffff) << DVC_CTRL_REG2_0_TIMER_CNT_SHIFT)
+#define DVC_CTRL_REG2_0_TIMER_CNT_RANGE                 31:9
+#define DVC_CTRL_REG2_0_TIMER_CNT_WOFFSET                       0x0
+#define DVC_CTRL_REG2_0_TIMER_CNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_TIMER_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0x7fffff)
+#define DVC_CTRL_REG2_0_TIMER_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_TIMER_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// The period in terms of number of ref clks, during  which perf counter is incremented.
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_SHIFT                       _MK_SHIFT_CONST(2)
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_FIELD                       (_MK_MASK_CONST(0x7f) << DVC_CTRL_REG2_0_ROSC_SA_CNT_SHIFT)
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_RANGE                       8:2
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_WOFFSET                     0x0
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_ROSC_SA_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Number of ref clocks to wait for the ring oscillator  settle.
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_SHIFT                    _MK_SHIFT_CONST(0)
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_FIELD                    (_MK_MASK_CONST(0x3) << DVC_CTRL_REG2_0_ROSC_START_DEL_SHIFT)
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_RANGE                    1:0
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_WOFFSET                  0x0
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG2_0_ROSC_START_DEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register DVC_CTRL_REG3_0  
+#define DVC_CTRL_REG3_0                 _MK_ADDR_CONST(0x8)
+#define DVC_CTRL_REG3_0_SECURE                  0x0
+#define DVC_CTRL_REG3_0_WORD_COUNT                      0x1
+#define DVC_CTRL_REG3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_RESET_MASK                      _MK_MASK_CONST(0xf7ffc3ff)
+#define DVC_CTRL_REG3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_READ_MASK                       _MK_MASK_CONST(0xf7ffc3ff)
+#define DVC_CTRL_REG3_0_WRITE_MASK                      _MK_MASK_CONST(0xf7ffc3ff)
+// Status bit which s/w should write to let DVC know that PMU has been programmed. DVC will then clear this bit.
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_SHIFT                  _MK_SHIFT_CONST(31)
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_FIELD                  (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_SHIFT)
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_RANGE                  31:31
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_WOFFSET                        0x0
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_SW_PROG_PMU_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Enable I2C intr which is triggered after I2C transfer is done.
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_SHIFT                  _MK_SHIFT_CONST(30)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_FIELD                  (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_SHIFT)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_RANGE                  30:30
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_WOFFSET                        0x0
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_I2C_DONE_INTR_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// PMU voltage program ready intr enable
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_SHIFT                    _MK_SHIFT_CONST(29)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_FIELD                    (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_SHIFT)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_RANGE                    29:29
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_WOFFSET                  0x0
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_PMU_VOLT_READY_INTR_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Enable for target performance adjustment done interrupt.
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_SHIFT                     _MK_SHIFT_CONST(28)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_FIELD                     (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_SHIFT)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_RANGE                     28:28
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_WOFFSET                   0x0
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_TGT_PERF_DONE_INTR_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Select either hardware or software to program the PMU via I2C.
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_SHIFT                    _MK_SHIFT_CONST(26)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_FIELD                    (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_I2C_HW_SW_PROG_SHIFT)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_RANGE                    26:26
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_WOFFSET                  0x0
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_HW                       _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_I2C_HW_SW_PROG_SW                       _MK_ENUM_CONST(1)
+
+// Enable Wakeup timer.
+#define DVC_CTRL_REG3_0_TIMER_EN_SHIFT                  _MK_SHIFT_CONST(25)
+#define DVC_CTRL_REG3_0_TIMER_EN_FIELD                  (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_TIMER_EN_SHIFT)
+#define DVC_CTRL_REG3_0_TIMER_EN_RANGE                  25:25
+#define DVC_CTRL_REG3_0_TIMER_EN_WOFFSET                        0x0
+#define DVC_CTRL_REG3_0_TIMER_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TIMER_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_TIMER_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TIMER_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TIMER_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_TIMER_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Number of decrement requests, after an increment  request, to wait for, before voltage change is applied.
+#define DVC_CTRL_REG3_0_HYST_CNTR_SHIFT                 _MK_SHIFT_CONST(22)
+#define DVC_CTRL_REG3_0_HYST_CNTR_FIELD                 (_MK_MASK_CONST(0x7) << DVC_CTRL_REG3_0_HYST_CNTR_SHIFT)
+#define DVC_CTRL_REG3_0_HYST_CNTR_RANGE                 24:22
+#define DVC_CTRL_REG3_0_HYST_CNTR_WOFFSET                       0x0
+#define DVC_CTRL_REG3_0_HYST_CNTR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_HYST_CNTR_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define DVC_CTRL_REG3_0_HYST_CNTR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_HYST_CNTR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Self clearing bit that if set causes one  performance monitor sample to be taken 
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_SHIFT                        _MK_SHIFT_CONST(21)
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_FIELD                        (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_TRIG_PM_SA_SHIFT)
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_RANGE                        21:21
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_WOFFSET                      0x0
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_TRIG_PM_SA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Select 1 of 32 path of ring oscillator adder
+#define DVC_CTRL_REG3_0_MUX_SEL_SHIFT                   _MK_SHIFT_CONST(16)
+#define DVC_CTRL_REG3_0_MUX_SEL_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_CTRL_REG3_0_MUX_SEL_SHIFT)
+#define DVC_CTRL_REG3_0_MUX_SEL_RANGE                   20:16
+#define DVC_CTRL_REG3_0_MUX_SEL_WOFFSET                 0x0
+#define DVC_CTRL_REG3_0_MUX_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_MUX_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_CTRL_REG3_0_MUX_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_MUX_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 0:not long path , 1:select long path for clk
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_SHIFT                      _MK_SHIFT_CONST(15)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_FIELD                      (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_LONG_PATH_EN_SHIFT)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_RANGE                      15:15
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_WOFFSET                    0x0
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_LONG_PATH_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Select between adder ring oscillator (0) and speedo ring oscillator (1).
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_FIELD                      (_MK_MASK_CONST(0x1) << DVC_CTRL_REG3_0_RING_OSC_SEL_SHIFT)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_RANGE                      14:14
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_WOFFSET                    0x0
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_OLD                        _MK_ENUM_CONST(0)
+#define DVC_CTRL_REG3_0_RING_OSC_SEL_NEW                        _MK_ENUM_CONST(1)
+
+// (actual perf-target perf)>threshold, voltage  tuning is done if enabled
+#define DVC_CTRL_REG3_0_VA_TH_H_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_CTRL_REG3_0_VA_TH_H_FIELD                   (_MK_MASK_CONST(0x3ff) << DVC_CTRL_REG3_0_VA_TH_H_SHIFT)
+#define DVC_CTRL_REG3_0_VA_TH_H_RANGE                   9:0
+#define DVC_CTRL_REG3_0_VA_TH_H_WOFFSET                 0x0
+#define DVC_CTRL_REG3_0_VA_TH_H_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_VA_TH_H_DEFAULT_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_CTRL_REG3_0_VA_TH_H_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_CTRL_REG3_0_VA_TH_H_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register DVC_STATUS_REG_0  
+#define DVC_STATUS_REG_0                        _MK_ADDR_CONST(0xc)
+#define DVC_STATUS_REG_0_SECURE                         0x0
+#define DVC_STATUS_REG_0_WORD_COUNT                     0x1
+#define DVC_STATUS_REG_0_RESET_VAL                      _MK_MASK_CONST(0x60000)
+#define DVC_STATUS_REG_0_RESET_MASK                     _MK_MASK_CONST(0x7fffffff)
+#define DVC_STATUS_REG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_READ_MASK                      _MK_MASK_CONST(0x7fffffff)
+#define DVC_STATUS_REG_0_WRITE_MASK                     _MK_MASK_CONST(0x7fffffff)
+// Interrupt to indicate I2C transfer is done
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_SHIFT                    _MK_SHIFT_CONST(30)
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_FIELD                    (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_I2C_DONE_INTR_SHIFT)
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_RANGE                    30:30
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_WOFFSET                  0x0
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_DONE_INTR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Interrupt indicating that voltage adjustment value is ready and can be programmed to PMU via I2C by software.
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_SHIFT                      _MK_SHIFT_CONST(29)
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_FIELD                      (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_SHIFT)
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_RANGE                      29:29
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_WOFFSET                    0x0
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_PMU_VOLT_READY_INTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Interrupt to firmware to indicate voltage change has been completed.
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_SHIFT                       _MK_SHIFT_CONST(28)
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_FIELD                       (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_SHIFT)
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_RANGE                       28:28
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_WOFFSET                     0x0
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_TGT_PERF_DONE_INTR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// DVC/PMU is busy adjusting voltage.
+#define DVC_STATUS_REG_0_BUSY_SHIFT                     _MK_SHIFT_CONST(27)
+#define DVC_STATUS_REG_0_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_BUSY_SHIFT)
+#define DVC_STATUS_REG_0_BUSY_RANGE                     27:27
+#define DVC_STATUS_REG_0_BUSY_WOFFSET                   0x0
+#define DVC_STATUS_REG_0_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Carry output from the adder of the new ring oscillator
+#define DVC_STATUS_REG_0_CARRY_OUT_SHIFT                        _MK_SHIFT_CONST(26)
+#define DVC_STATUS_REG_0_CARRY_OUT_FIELD                        (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_CARRY_OUT_SHIFT)
+#define DVC_STATUS_REG_0_CARRY_OUT_RANGE                        26:26
+#define DVC_STATUS_REG_0_CARRY_OUT_WOFFSET                      0x0
+#define DVC_STATUS_REG_0_CARRY_OUT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_CARRY_OUT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_CARRY_OUT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_CARRY_OUT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// I2C Status bits 
+#define DVC_STATUS_REG_0_I2C_STATUS_SHIFT                       _MK_SHIFT_CONST(22)
+#define DVC_STATUS_REG_0_I2C_STATUS_FIELD                       (_MK_MASK_CONST(0xf) << DVC_STATUS_REG_0_I2C_STATUS_SHIFT)
+#define DVC_STATUS_REG_0_I2C_STATUS_RANGE                       25:22
+#define DVC_STATUS_REG_0_I2C_STATUS_WOFFSET                     0x0
+#define DVC_STATUS_REG_0_I2C_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define DVC_STATUS_REG_0_I2C_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Indicates error for I2C master in data transfer
+#define DVC_STATUS_REG_0_I2C_ERROR_SHIFT                        _MK_SHIFT_CONST(21)
+#define DVC_STATUS_REG_0_I2C_ERROR_FIELD                        (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_I2C_ERROR_SHIFT)
+#define DVC_STATUS_REG_0_I2C_ERROR_RANGE                        21:21
+#define DVC_STATUS_REG_0_I2C_ERROR_WOFFSET                      0x0
+#define DVC_STATUS_REG_0_I2C_ERROR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_ERROR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_I2C_ERROR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_I2C_ERROR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Measured performance count less than target performance count condition detected.
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_SHIFT                  _MK_SHIFT_CONST(20)
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_FIELD                  (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_TGT_PM_UNDERRUN_SHIFT)
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_RANGE                  20:20
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_WOFFSET                        0x0
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_TGT_PM_UNDERRUN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Voltage adjustment exceeds the limit
+#define DVC_STATUS_REG_0_VADJ_ERR_SHIFT                 _MK_SHIFT_CONST(19)
+#define DVC_STATUS_REG_0_VADJ_ERR_FIELD                 (_MK_MASK_CONST(0x1) << DVC_STATUS_REG_0_VADJ_ERR_SHIFT)
+#define DVC_STATUS_REG_0_VADJ_ERR_RANGE                 19:19
+#define DVC_STATUS_REG_0_VADJ_ERR_WOFFSET                       0x0
+#define DVC_STATUS_REG_0_VADJ_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_VADJ_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define DVC_STATUS_REG_0_VADJ_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_VADJ_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Value of the voltage that has been applied.
+#define DVC_STATUS_REG_0_CURR_VOLT_SHIFT                        _MK_SHIFT_CONST(14)
+#define DVC_STATUS_REG_0_CURR_VOLT_FIELD                        (_MK_MASK_CONST(0x1f) << DVC_STATUS_REG_0_CURR_VOLT_SHIFT)
+#define DVC_STATUS_REG_0_CURR_VOLT_RANGE                        18:14
+#define DVC_STATUS_REG_0_CURR_VOLT_WOFFSET                      0x0
+#define DVC_STATUS_REG_0_CURR_VOLT_DEFAULT                      _MK_MASK_CONST(0x18)
+#define DVC_STATUS_REG_0_CURR_VOLT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define DVC_STATUS_REG_0_CURR_VOLT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_CURR_VOLT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Performance monitor sample value for the last sample
+#define DVC_STATUS_REG_0_PMON_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
+#define DVC_STATUS_REG_0_PMON_VALUE_FIELD                       (_MK_MASK_CONST(0x3fff) << DVC_STATUS_REG_0_PMON_VALUE_SHIFT)
+#define DVC_STATUS_REG_0_PMON_VALUE_RANGE                       13:0
+#define DVC_STATUS_REG_0_PMON_VALUE_WOFFSET                     0x0
+#define DVC_STATUS_REG_0_PMON_VALUE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_PMON_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0x3fff)
+#define DVC_STATUS_REG_0_PMON_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_STATUS_REG_0_PMON_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_CTRL_REG_0  
+#define DVC_I2C_CTRL_REG_0                      _MK_ADDR_CONST(0x10)
+#define DVC_I2C_CTRL_REG_0_SECURE                       0x0
+#define DVC_I2C_CTRL_REG_0_WORD_COUNT                   0x1
+#define DVC_I2C_CTRL_REG_0_RESET_VAL                    _MK_MASK_CONST(0x14514000)
+#define DVC_I2C_CTRL_REG_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CTRL_REG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CTRL_REG_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// 1 or 2 or 3 Commands for writing to PMU-I2C slave.
+// 000=>  1 cmd vsel1 only to core
+// 001=>  2 cmd's vsel1 & vsel2 to the core & AO
+// 010=>  3 cmd's vsel1 & vsel2 & vsel3 to the core, AO and CPU
+// 011=> NA
+// 100 => 2 cmd's vsel1 to the core, vsel2 is S/W controlled
+// 101 & 110 = > NA
+// 111 => 3 cmd's vsel1 to the core , vsel2 & vsel3 are S/W controlled
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_SHIFT                      _MK_SHIFT_CONST(29)
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_FIELD                      (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_MULTI_CMD_SHIFT)
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_RANGE                      31:29
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_WOFFSET                    0x0
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_MULTI_CMD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Size of vsel3 to match with PMU
+#define DVC_I2C_CTRL_REG_0_SIZE3_SHIFT                  _MK_SHIFT_CONST(26)
+#define DVC_I2C_CTRL_REG_0_SIZE3_FIELD                  (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SIZE3_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SIZE3_RANGE                  28:26
+#define DVC_I2C_CTRL_REG_0_SIZE3_WOFFSET                        0x0
+#define DVC_I2C_CTRL_REG_0_SIZE3_DEFAULT                        _MK_MASK_CONST(0x5)
+#define DVC_I2C_CTRL_REG_0_SIZE3_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SIZE3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SIZE3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Shift vsel3 to match with PMU
+#define DVC_I2C_CTRL_REG_0_SHIFT3_SHIFT                 _MK_SHIFT_CONST(23)
+#define DVC_I2C_CTRL_REG_0_SHIFT3_FIELD                 (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SHIFT3_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SHIFT3_RANGE                 25:23
+#define DVC_I2C_CTRL_REG_0_SHIFT3_WOFFSET                       0x0
+#define DVC_I2C_CTRL_REG_0_SHIFT3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT3_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SHIFT3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Size of vsel2 to match with PMU
+#define DVC_I2C_CTRL_REG_0_SIZE2_SHIFT                  _MK_SHIFT_CONST(20)
+#define DVC_I2C_CTRL_REG_0_SIZE2_FIELD                  (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SIZE2_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SIZE2_RANGE                  22:20
+#define DVC_I2C_CTRL_REG_0_SIZE2_WOFFSET                        0x0
+#define DVC_I2C_CTRL_REG_0_SIZE2_DEFAULT                        _MK_MASK_CONST(0x5)
+#define DVC_I2C_CTRL_REG_0_SIZE2_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SIZE2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SIZE2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Shift vsel2 to match with PMU
+#define DVC_I2C_CTRL_REG_0_SHIFT2_SHIFT                 _MK_SHIFT_CONST(17)
+#define DVC_I2C_CTRL_REG_0_SHIFT2_FIELD                 (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SHIFT2_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SHIFT2_RANGE                 19:17
+#define DVC_I2C_CTRL_REG_0_SHIFT2_WOFFSET                       0x0
+#define DVC_I2C_CTRL_REG_0_SHIFT2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT2_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SHIFT2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Size of vsel to match with PMU
+#define DVC_I2C_CTRL_REG_0_SIZE1_SHIFT                  _MK_SHIFT_CONST(14)
+#define DVC_I2C_CTRL_REG_0_SIZE1_FIELD                  (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SIZE1_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SIZE1_RANGE                  16:14
+#define DVC_I2C_CTRL_REG_0_SIZE1_WOFFSET                        0x0
+#define DVC_I2C_CTRL_REG_0_SIZE1_DEFAULT                        _MK_MASK_CONST(0x5)
+#define DVC_I2C_CTRL_REG_0_SIZE1_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SIZE1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SIZE1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Shift vsel to match with PMU
+#define DVC_I2C_CTRL_REG_0_SHIFT1_SHIFT                 _MK_SHIFT_CONST(11)
+#define DVC_I2C_CTRL_REG_0_SHIFT1_FIELD                 (_MK_MASK_CONST(0x7) << DVC_I2C_CTRL_REG_0_SHIFT1_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SHIFT1_RANGE                 13:11
+#define DVC_I2C_CTRL_REG_0_SHIFT1_WOFFSET                       0x0
+#define DVC_I2C_CTRL_REG_0_SHIFT1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT1_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define DVC_I2C_CTRL_REG_0_SHIFT1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SHIFT1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 7 bit or 10 bit addressing
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_SHIFT                        _MK_SHIFT_CONST(10)
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_FIELD                        (_MK_MASK_CONST(0x1) << DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_SHIFT)
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_RANGE                        10:10
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_WOFFSET                      0x0
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_ADDR_7BIT_10BIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// External slave ID Address
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_SHIFT                       _MK_SHIFT_CONST(0)
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_FIELD                       (_MK_MASK_CONST(0x3ff) << DVC_I2C_CTRL_REG_0_SLAVE_ID_SHIFT)
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_RANGE                       9:0
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_WOFFSET                     0x0
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CTRL_REG_0_SLAVE_ID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_ADDR_DATA_REG_0  
+#define DVC_I2C_ADDR_DATA_REG_0                 _MK_ADDR_CONST(0x14)
+#define DVC_I2C_ADDR_DATA_REG_0_SECURE                  0x0
+#define DVC_I2C_ADDR_DATA_REG_0_WORD_COUNT                      0x1
+#define DVC_I2C_ADDR_DATA_REG_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_ADDR_DATA_REG_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_ADDR_DATA_REG_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Optional second data
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_SHIFT                     _MK_SHIFT_CONST(24)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_FIELD                     (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_0_DATA2_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_RANGE                     31:24
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_WOFFSET                   0x0
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Optional second addr
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_SHIFT                     _MK_SHIFT_CONST(16)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_FIELD                     (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_0_ADDR2_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_RANGE                     23:16
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_WOFFSET                   0x0
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Default data
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_SHIFT                     _MK_SHIFT_CONST(8)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_FIELD                     (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_0_DATA1_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_RANGE                     15:8
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_WOFFSET                   0x0
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_DATA1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Addr for voltage sel
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_SHIFT                     _MK_SHIFT_CONST(0)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_FIELD                     (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_0_ADDR1_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_RANGE                     7:0
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_WOFFSET                   0x0
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_0_ADDR1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register DVC_RING_OSC_ADDER_IN1_0  
+#define DVC_RING_OSC_ADDER_IN1_0                        _MK_ADDR_CONST(0x18)
+#define DVC_RING_OSC_ADDER_IN1_0_SECURE                         0x0
+#define DVC_RING_OSC_ADDER_IN1_0_WORD_COUNT                     0x1
+#define DVC_RING_OSC_ADDER_IN1_0_RESET_VAL                      _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN1_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN1_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN1_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Ring osc adder input1
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_SHIFT                        _MK_SHIFT_CONST(0)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_FIELD                        (_MK_MASK_CONST(0xffffffff) << DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_SHIFT)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_RANGE                        31:0
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_WOFFSET                      0x0
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_DEFAULT                      _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN1_0_ADDER_IN1_INIT_ENUM                    -1
+
+
+// Register DVC_RING_OSC_ADDER_IN2_0  
+#define DVC_RING_OSC_ADDER_IN2_0                        _MK_ADDR_CONST(0x1c)
+#define DVC_RING_OSC_ADDER_IN2_0_SECURE                         0x0
+#define DVC_RING_OSC_ADDER_IN2_0_WORD_COUNT                     0x1
+#define DVC_RING_OSC_ADDER_IN2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN2_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN2_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN2_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Ring osc adder input2
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_SHIFT                        _MK_SHIFT_CONST(0)
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_FIELD                        (_MK_MASK_CONST(0xffffffff) << DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_SHIFT)
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_RANGE                        31:0
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_WOFFSET                      0x0
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_RING_OSC_ADDER_IN2_0_ADDER_IN2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register DVC_REQ_REGISTER_0  
+#define DVC_REQ_REGISTER_0                      _MK_ADDR_CONST(0x20)
+#define DVC_REQ_REGISTER_0_SECURE                       0x0
+#define DVC_REQ_REGISTER_0_WORD_COUNT                   0x1
+#define DVC_REQ_REGISTER_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define DVC_REQ_REGISTER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define DVC_REQ_REGISTER_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+// Self clearing bit , which firmware can use to trigger DVC voltage change
+#define DVC_REQ_REGISTER_0_REQ_VLD_SHIFT                        _MK_SHIFT_CONST(6)
+#define DVC_REQ_REGISTER_0_REQ_VLD_FIELD                        (_MK_MASK_CONST(0x1) << DVC_REQ_REGISTER_0_REQ_VLD_SHIFT)
+#define DVC_REQ_REGISTER_0_REQ_VLD_RANGE                        6:6
+#define DVC_REQ_REGISTER_0_REQ_VLD_WOFFSET                      0x0
+#define DVC_REQ_REGISTER_0_REQ_VLD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_REQ_VLD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_REQ_REGISTER_0_REQ_VLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_REQ_VLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_REQ_VLD_INVALID                      _MK_ENUM_CONST(0)
+#define DVC_REQ_REGISTER_0_REQ_VLD_VALID                        _MK_ENUM_CONST(1)
+
+// firmware target performance
+#define DVC_REQ_REGISTER_0_NORM_FREQ_SHIFT                      _MK_SHIFT_CONST(0)
+#define DVC_REQ_REGISTER_0_NORM_FREQ_FIELD                      (_MK_MASK_CONST(0x3f) << DVC_REQ_REGISTER_0_NORM_FREQ_SHIFT)
+#define DVC_REQ_REGISTER_0_NORM_FREQ_RANGE                      5:0
+#define DVC_REQ_REGISTER_0_NORM_FREQ_WOFFSET                    0x0
+#define DVC_REQ_REGISTER_0_NORM_FREQ_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_NORM_FREQ_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define DVC_REQ_REGISTER_0_NORM_FREQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_REQ_REGISTER_0_NORM_FREQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_ADDR_DATA_REG_3_0  
+#define DVC_I2C_ADDR_DATA_REG_3_0                       _MK_ADDR_CONST(0x24)
+#define DVC_I2C_ADDR_DATA_REG_3_0_SECURE                        0x0
+#define DVC_I2C_ADDR_DATA_REG_3_0_WORD_COUNT                    0x1
+#define DVC_I2C_ADDR_DATA_REG_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define DVC_I2C_ADDR_DATA_REG_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define DVC_I2C_ADDR_DATA_REG_3_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
+//Default Data
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_SHIFT                   _MK_SHIFT_CONST(8)
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_FIELD                   (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_3_0_DATA3_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_RANGE                   15:8
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_WOFFSET                 0x0
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_DATA3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Addr For Volatge sel 3
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_FIELD                   (_MK_MASK_CONST(0xff) << DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_SHIFT)
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_RANGE                   7:0
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_WOFFSET                 0x0
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_ADDR_DATA_REG_3_0_ADDR3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Register DVC_I2C_CNFG_0  
+#define DVC_I2C_CNFG_0                  _MK_ADDR_CONST(0x40)
+#define DVC_I2C_CNFG_0_SECURE                   0x0
+#define DVC_I2C_CNFG_0_WORD_COUNT                       0x1
+#define DVC_I2C_CNFG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_RESET_MASK                       _MK_MASK_CONST(0x7fff)
+#define DVC_I2C_CNFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_READ_MASK                        _MK_MASK_CONST(0x7fff)
+#define DVC_I2C_CNFG_0_WRITE_MASK                       _MK_MASK_CONST(0x7fff)
+// Debounce period for sda and scl lines
+// 0 = No debounce
+// 1 = 2T
+// 2  = 4T
+// 3 =  6T etc
+// where T is the period of the fix PLL 
+//clk source coming to i2c.
+//Maximum debounce period programmable is 
+//14T.A debounce period of >50ns is desirable
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT                       _MK_SHIFT_CONST(12)
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_FIELD                       (_MK_MASK_CONST(0x7) << DVC_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT)
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_RANGE                       14:12
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_WOFFSET                     0x0
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Write 1 to enable new master fsm
+// 0 = old fsm
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT                     _MK_SHIFT_CONST(11)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_FIELD                     (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_RANGE                     11:11
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_WOFFSET                   0x0
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_DISABLE                   _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_NEW_MASTER_FSM_ENABLE                    _MK_ENUM_CONST(1)
+
+// Write 1 to initiate transfer in packet mode.
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_SHIFT                     _MK_SHIFT_CONST(10)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_FIELD                     (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_PACKET_MODE_EN_SHIFT)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_RANGE                     10:10
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_WOFFSET                   0x0
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_NOP                       _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_PACKET_MODE_EN_GO                        _MK_ENUM_CONST(1)
+
+// Writing a 1 causes the master to initiate the
+// transaction in normal mode. Values of other  bits are not
+// affected when this bit is 1,Cleared by 
+// hardware.  Other bits of the register are
+// masked for writes when this bit is programmed
+// to one.hence,firware should first configure
+// all other registrs and  bits [8:0] of 
+// I2C_CNFG register before the bit
+// I2C_CNFG[9] is programmed to Zero.
+#define DVC_I2C_CNFG_0_SEND_SHIFT                       _MK_SHIFT_CONST(9)
+#define DVC_I2C_CNFG_0_SEND_FIELD                       (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_SEND_SHIFT)
+#define DVC_I2C_CNFG_0_SEND_RANGE                       9:9
+#define DVC_I2C_CNFG_0_SEND_WOFFSET                     0x0
+#define DVC_I2C_CNFG_0_SEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SEND_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_SEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SEND_NOP                 _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_SEND_GO                  _MK_ENUM_CONST(1)
+
+// Enable mode to handle devices that do not generate ACK. 
+// 1 - dont look for an ack at the end of the Enable
+#define DVC_I2C_CNFG_0_NOACK_SHIFT                      _MK_SHIFT_CONST(8)
+#define DVC_I2C_CNFG_0_NOACK_FIELD                      (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_NOACK_SHIFT)
+#define DVC_I2C_CNFG_0_NOACK_RANGE                      8:8
+#define DVC_I2C_CNFG_0_NOACK_WOFFSET                    0x0
+#define DVC_I2C_CNFG_0_NOACK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NOACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_NOACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NOACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_NOACK_DISABLE                    _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_NOACK_ENABLE                     _MK_ENUM_CONST(1)
+
+// Read/Write Command for Slave 2:
+// 1 -  Read Transaction; 0 -  write Transaction.
+// For a 7-bit slave address,this bit must match
+// with the LSB of address byte for slave 2.
+// Valid only when  bit-4 of this register is 
+// set
+#define DVC_I2C_CNFG_0_CMD2_SHIFT                       _MK_SHIFT_CONST(7)
+#define DVC_I2C_CNFG_0_CMD2_FIELD                       (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_CMD2_SHIFT)
+#define DVC_I2C_CNFG_0_CMD2_RANGE                       7:7
+#define DVC_I2C_CNFG_0_CMD2_WOFFSET                     0x0
+#define DVC_I2C_CNFG_0_CMD2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_CMD2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD2_DISABLE                     _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_CMD2_ENABLE                      _MK_ENUM_CONST(1)
+
+// Read/Write Command for Slave 1: 
+// 1 - Read Transaction; 0 -  write Transaction.
+// Command for Slave 1: For a 7-bit slave address
+// this bit must match with the LSB of address 
+// byte for slave1.
+#define DVC_I2C_CNFG_0_CMD1_SHIFT                       _MK_SHIFT_CONST(6)
+#define DVC_I2C_CNFG_0_CMD1_FIELD                       (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_CMD1_SHIFT)
+#define DVC_I2C_CNFG_0_CMD1_RANGE                       6:6
+#define DVC_I2C_CNFG_0_CMD1_WOFFSET                     0x0
+#define DVC_I2C_CNFG_0_CMD1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_CMD1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_CMD1_DISABLE                     _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_CMD1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  1 = Yes, a Start byte needs to be  sent.
+#define DVC_I2C_CNFG_0_START_SHIFT                      _MK_SHIFT_CONST(5)
+#define DVC_I2C_CNFG_0_START_FIELD                      (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_START_SHIFT)
+#define DVC_I2C_CNFG_0_START_RANGE                      5:5
+#define DVC_I2C_CNFG_0_START_WOFFSET                    0x0
+#define DVC_I2C_CNFG_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_START_DISABLE                    _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_START_ENABLE                     _MK_ENUM_CONST(1)
+
+//  1 - Enables a two slave transaction ;
+//  0 = No command for Slave 2 present.
+#define DVC_I2C_CNFG_0_SLV2_SHIFT                       _MK_SHIFT_CONST(4)
+#define DVC_I2C_CNFG_0_SLV2_FIELD                       (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_SLV2_SHIFT)
+#define DVC_I2C_CNFG_0_SLV2_RANGE                       4:4
+#define DVC_I2C_CNFG_0_SLV2_WOFFSET                     0x0
+#define DVC_I2C_CNFG_0_SLV2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SLV2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_SLV2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SLV2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_SLV2_DISABLE                     _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_SLV2_ENABLE                      _MK_ENUM_CONST(1)
+
+// The Number of bytes to be transmitted per
+// transaction 000= 1byte ... 111 = 8bytes;
+// In a two slave transaction number of bytes
+// should be programmed less than 011.
+#define DVC_I2C_CNFG_0_LENGTH_SHIFT                     _MK_SHIFT_CONST(1)
+#define DVC_I2C_CNFG_0_LENGTH_FIELD                     (_MK_MASK_CONST(0x7) << DVC_I2C_CNFG_0_LENGTH_SHIFT)
+#define DVC_I2C_CNFG_0_LENGTH_RANGE                     3:1
+#define DVC_I2C_CNFG_0_LENGTH_WOFFSET                   0x0
+#define DVC_I2C_CNFG_0_LENGTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_LENGTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define DVC_I2C_CNFG_0_LENGTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_LENGTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Address mode defines whether a 7-bit or a 
+// 10-bit slave address is programmed. 1 = 10-bit
+// device address 0  = 7-bit device address  
+#define DVC_I2C_CNFG_0_A_MOD_SHIFT                      _MK_SHIFT_CONST(0)
+#define DVC_I2C_CNFG_0_A_MOD_FIELD                      (_MK_MASK_CONST(0x1) << DVC_I2C_CNFG_0_A_MOD_SHIFT)
+#define DVC_I2C_CNFG_0_A_MOD_RANGE                      0:0
+#define DVC_I2C_CNFG_0_A_MOD_WOFFSET                    0x0
+#define DVC_I2C_CNFG_0_A_MOD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_A_MOD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_I2C_CNFG_0_A_MOD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_A_MOD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CNFG_0_A_MOD_SEVEN_BIT_DEVICE_ADDRESS                   _MK_ENUM_CONST(0)
+#define DVC_I2C_CNFG_0_A_MOD_TEN_BIT_DEVICE_ADDRESS                     _MK_ENUM_CONST(1)
+
+
+// Register DVC_I2C_CMD_ADDR0_0  
+#define DVC_I2C_CMD_ADDR0_0                     _MK_ADDR_CONST(0x44)
+#define DVC_I2C_CMD_ADDR0_0_SECURE                      0x0
+#define DVC_I2C_CMD_ADDR0_0_WORD_COUNT                  0x1
+#define DVC_I2C_CMD_ADDR0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR0_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR0_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR0_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+// In case of 7-Bit mode address is written in the 
+// I2C_CMD_ADDR0[7:1] and I2C_CMD_ADDR0[0] indicates the
+// read/write transaction.I2C_CMD_ADDR0[0] bit must match 
+// with the I2C_CNFG[6].
+// In case of 10-Bit mode addess is written in 
+// I2C_CMD_ADDR0[9:0] and I2C_CNFG[6]  indicates the 
+// read/write transaction. 
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_FIELD                 (_MK_MASK_CONST(0x3ff) << DVC_I2C_CMD_ADDR0_0_ADDR0_SHIFT)
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_RANGE                 9:0
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_WOFFSET                       0x0
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_CMD_ADDR1_0  
+#define DVC_I2C_CMD_ADDR1_0                     _MK_ADDR_CONST(0x48)
+#define DVC_I2C_CMD_ADDR1_0_SECURE                      0x0
+#define DVC_I2C_CMD_ADDR1_0_WORD_COUNT                  0x1
+#define DVC_I2C_CMD_ADDR1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR1_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR1_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR1_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+// In case of 7-Bit mode address is written in the 
+// I2C_CMD_ADDR0[7:1] and I2C_CMD_ADDR0[0] indicates the 
+// read/write transaction.I2C_CMD_ADDR0[0] bit must match
+// with the I2C_CNFG[7].        
+// In case of 10-Bit mode addess is written in 
+// I2C_CMD_ADDR0[9:0] and I2C_CNFG[7] indicates the 
+// read/write transaction. 
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_FIELD                 (_MK_MASK_CONST(0x3ff) << DVC_I2C_CMD_ADDR1_0_ADDR1_SHIFT)
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_RANGE                 9:0
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_WOFFSET                       0x0
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_CMD_DATA1_0  
+#define DVC_I2C_CMD_DATA1_0                     _MK_ADDR_CONST(0x4c)
+#define DVC_I2C_CMD_DATA1_0_SECURE                      0x0
+#define DVC_I2C_CMD_DATA1_0_WORD_COUNT                  0x1
+#define DVC_I2C_CMD_DATA1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CMD_DATA1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CMD_DATA1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Fourth data byte to be sent/received
+#define DVC_I2C_CMD_DATA1_0_DATA4_SHIFT                 _MK_SHIFT_CONST(24)
+#define DVC_I2C_CMD_DATA1_0_DATA4_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA1_0_DATA4_SHIFT)
+#define DVC_I2C_CMD_DATA1_0_DATA4_RANGE                 31:24
+#define DVC_I2C_CMD_DATA1_0_DATA4_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA1_0_DATA4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Third data byte to be sent/received
+#define DVC_I2C_CMD_DATA1_0_DATA3_SHIFT                 _MK_SHIFT_CONST(16)
+#define DVC_I2C_CMD_DATA1_0_DATA3_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA1_0_DATA3_SHIFT)
+#define DVC_I2C_CMD_DATA1_0_DATA3_RANGE                 23:16
+#define DVC_I2C_CMD_DATA1_0_DATA3_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA1_0_DATA3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Second data byte to be sent/received
+#define DVC_I2C_CMD_DATA1_0_DATA2_SHIFT                 _MK_SHIFT_CONST(8)
+#define DVC_I2C_CMD_DATA1_0_DATA2_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA1_0_DATA2_SHIFT)
+#define DVC_I2C_CMD_DATA1_0_DATA2_RANGE                 15:8
+#define DVC_I2C_CMD_DATA1_0_DATA2_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA1_0_DATA2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This register contains the first data byte to be  sent/received.
+#define DVC_I2C_CMD_DATA1_0_DATA1_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_I2C_CMD_DATA1_0_DATA1_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA1_0_DATA1_SHIFT)
+#define DVC_I2C_CMD_DATA1_0_DATA1_RANGE                 7:0
+#define DVC_I2C_CMD_DATA1_0_DATA1_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA1_0_DATA1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_CMD_DATA2_0  
+#define DVC_I2C_CMD_DATA2_0                     _MK_ADDR_CONST(0x50)
+#define DVC_I2C_CMD_DATA2_0_SECURE                      0x0
+#define DVC_I2C_CMD_DATA2_0_WORD_COUNT                  0x1
+#define DVC_I2C_CMD_DATA2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CMD_DATA2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_CMD_DATA2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Eighth data byte to be sent/received
+#define DVC_I2C_CMD_DATA2_0_DATA8_SHIFT                 _MK_SHIFT_CONST(24)
+#define DVC_I2C_CMD_DATA2_0_DATA8_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA2_0_DATA8_SHIFT)
+#define DVC_I2C_CMD_DATA2_0_DATA8_RANGE                 31:24
+#define DVC_I2C_CMD_DATA2_0_DATA8_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA2_0_DATA8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA8_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Seventh data byte to be sent/received
+#define DVC_I2C_CMD_DATA2_0_DATA7_SHIFT                 _MK_SHIFT_CONST(16)
+#define DVC_I2C_CMD_DATA2_0_DATA7_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA2_0_DATA7_SHIFT)
+#define DVC_I2C_CMD_DATA2_0_DATA7_RANGE                 23:16
+#define DVC_I2C_CMD_DATA2_0_DATA7_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA2_0_DATA7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA7_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sixth data byte to be sent/received
+#define DVC_I2C_CMD_DATA2_0_DATA6_SHIFT                 _MK_SHIFT_CONST(8)
+#define DVC_I2C_CMD_DATA2_0_DATA6_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA2_0_DATA6_SHIFT)
+#define DVC_I2C_CMD_DATA2_0_DATA6_RANGE                 15:8
+#define DVC_I2C_CMD_DATA2_0_DATA6_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA2_0_DATA6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This register contains the Fifth data byte to be  sent/received.
+#define DVC_I2C_CMD_DATA2_0_DATA5_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_I2C_CMD_DATA2_0_DATA5_FIELD                 (_MK_MASK_CONST(0xff) << DVC_I2C_CMD_DATA2_0_DATA5_SHIFT)
+#define DVC_I2C_CMD_DATA2_0_DATA5_RANGE                 7:0
+#define DVC_I2C_CMD_DATA2_0_DATA5_WOFFSET                       0x0
+#define DVC_I2C_CMD_DATA2_0_DATA5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define DVC_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Register DVC_I2C_STATUS_0  
+#define DVC_I2C_STATUS_0                        _MK_ADDR_CONST(0x5c)
+#define DVC_I2C_STATUS_0_SECURE                         0x0
+#define DVC_I2C_STATUS_0_WORD_COUNT                     0x1
+#define DVC_I2C_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x1ff)
+#define DVC_I2C_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x1ff)
+#define DVC_I2C_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+//  1 = Busy.
+#define DVC_I2C_STATUS_0_BUSY_SHIFT                     _MK_SHIFT_CONST(8)
+#define DVC_I2C_STATUS_0_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << DVC_I2C_STATUS_0_BUSY_SHIFT)
+#define DVC_I2C_STATUS_0_BUSY_RANGE                     8:8
+#define DVC_I2C_STATUS_0_BUSY_WOFFSET                   0x0
+#define DVC_I2C_STATUS_0_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_I2C_STATUS_0_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_BUSY_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define DVC_I2C_STATUS_0_BUSY_BUSY                      _MK_ENUM_CONST(1)
+
+// Transaction for Slave2 for x byte failed. x is 'h0 to 'ha.
+// all others invalid 
+#define DVC_I2C_STATUS_0_CMD2_STAT_SHIFT                        _MK_SHIFT_CONST(4)
+#define DVC_I2C_STATUS_0_CMD2_STAT_FIELD                        (_MK_MASK_CONST(0xf) << DVC_I2C_STATUS_0_CMD2_STAT_SHIFT)
+#define DVC_I2C_STATUS_0_CMD2_STAT_RANGE                        7:4
+#define DVC_I2C_STATUS_0_CMD2_STAT_WOFFSET                      0x0
+#define DVC_I2C_STATUS_0_CMD2_STAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD2_STAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_XFER_SUCCESSFUL                  _MK_ENUM_CONST(0)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE1                  _MK_ENUM_CONST(1)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE2                  _MK_ENUM_CONST(2)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE3                  _MK_ENUM_CONST(3)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE4                  _MK_ENUM_CONST(4)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE5                  _MK_ENUM_CONST(5)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE6                  _MK_ENUM_CONST(6)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE7                  _MK_ENUM_CONST(7)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE8                  _MK_ENUM_CONST(8)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE9                  _MK_ENUM_CONST(9)
+#define DVC_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE10                 _MK_ENUM_CONST(10)
+
+// Transaction for Slave1 for x byte failed. x is 'h0 to 'ha.
+// all others invalid
+#define DVC_I2C_STATUS_0_CMD1_STAT_SHIFT                        _MK_SHIFT_CONST(0)
+#define DVC_I2C_STATUS_0_CMD1_STAT_FIELD                        (_MK_MASK_CONST(0xf) << DVC_I2C_STATUS_0_CMD1_STAT_SHIFT)
+#define DVC_I2C_STATUS_0_CMD1_STAT_RANGE                        3:0
+#define DVC_I2C_STATUS_0_CMD1_STAT_WOFFSET                      0x0
+#define DVC_I2C_STATUS_0_CMD1_STAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD1_STAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_XFER_SUCCESSFUL                  _MK_ENUM_CONST(0)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE1                  _MK_ENUM_CONST(1)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE2                  _MK_ENUM_CONST(2)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE3                  _MK_ENUM_CONST(3)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE4                  _MK_ENUM_CONST(4)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE5                  _MK_ENUM_CONST(5)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE6                  _MK_ENUM_CONST(6)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE7                  _MK_ENUM_CONST(7)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE8                  _MK_ENUM_CONST(8)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE9                  _MK_ENUM_CONST(9)
+#define DVC_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE10                 _MK_ENUM_CONST(10)
+
+
+// Packet I2C_IO_PACKET_HEADER_0
+#define I2C_IO_PACKET_HEADER_0_SIZE 32
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT                        _MK_SHIFT_CONST(30)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_FIELD                        (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT                      _MK_SHIFT_CONST(28)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_FIELD                      (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_RANGE                      _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(28)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_ROW                        0
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_ONE                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_TWO                        _MK_ENUM_CONST(1)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_THREE                      _MK_ENUM_CONST(2)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_FOUR                       _MK_ENUM_CONST(3)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT                        _MK_SHIFT_CONST(24)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_FIELD                        (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_RANGE                        _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PKTID_SHIFT                      _MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_PKTID_FIELD                      (_MK_MASK_CONST(0xff) << I2C_IO_PACKET_HEADER_0_PKTID_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PKTID_RANGE                      _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_PKTID_ROW                        0
+
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT                      _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_FIELD                      (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_RANGE                      _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_ROW                        0
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C1                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C2                       _MK_ENUM_CONST(1)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C3                       _MK_ENUM_CONST(2)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_DVC_I2C                    _MK_ENUM_CONST(3)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT                        _MK_SHIFT_CONST(8)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_FIELD                        (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT                   _MK_SHIFT_CONST(4)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_FIELD                   (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RANGE                   _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(4)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_ROW                     0
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RESERVED                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_I2C                     _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT                        _MK_SHIFT_CONST(3)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_FIELD                        (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_FIELD                    (_MK_MASK_CONST(0x7) << I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_ROW                      0
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT                        _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_FIELD                        (_MK_MASK_CONST(0xfffff) << I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_ROW                  1
+
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT                        _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_FIELD                        (_MK_MASK_CONST(0xfff) << I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_ROW                  1
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT                        _MK_SHIFT_CONST(23)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_FIELD                        (_MK_MASK_CONST(0x1ff) << I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(23)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT                    _MK_SHIFT_CONST(22)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_RANGE                    _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT                    _MK_SHIFT_CONST(21)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_RANGE                    _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT                    _MK_SHIFT_CONST(20)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_RANGE                    _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_READ_SHIFT                       _MK_SHIFT_CONST(19)
+#define I2C_IO_PACKET_HEADER_0_READ_FIELD                       (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_READ_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_READ_RANGE                       _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
+#define I2C_IO_PACKET_HEADER_0_READ_ROW                 2
+#define I2C_IO_PACKET_HEADER_0_READ_WRITE                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_READ_READ                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT                  _MK_SHIFT_CONST(18)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_FIELD                  (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_RANGE                  _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_ROW                    2
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SEVEN_BIT                      _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_TEN_BIT                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_IE_SHIFT                 _MK_SHIFT_CONST(17)
+#define I2C_IO_PACKET_HEADER_0_IE_FIELD                 (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_IE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_IE_RANGE                 _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
+#define I2C_IO_PACKET_HEADER_0_IE_ROW                   2
+#define I2C_IO_PACKET_HEADER_0_IE_DISABLE                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_IE_ENABLE                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT                       _MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_FIELD                       (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_RANGE                       _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_ROW                 2
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_STOP                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_REPEAT_START                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_SHIFT                        _MK_SHIFT_CONST(15)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_FIELD                        (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_RESERVED2_1_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT                     _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_FIELD                     (_MK_MASK_CONST(0x7) << I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_ROW                       2
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT                        _MK_SHIFT_CONST(10)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_FIELD                        (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_FIELD                 (_MK_MASK_CONST(0x3ff) << I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_RANGE                 _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_ROW                   2
+
+
+// Register DVC_I2C_TX_PACKET_FIFO_0  
+#define DVC_I2C_TX_PACKET_FIFO_0                        _MK_ADDR_CONST(0x60)
+#define DVC_I2C_TX_PACKET_FIFO_0_SECURE                         0x0
+#define DVC_I2C_TX_PACKET_FIFO_0_WORD_COUNT                     0x1
+#define DVC_I2C_TX_PACKET_FIFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_TX_PACKET_FIFO_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_TX_PACKET_FIFO_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_TX_PACKET_FIFO_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+//SW writes packets into this register  
+//A packet may contain generic
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT                        _MK_SHIFT_CONST(0)
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_FIELD                        (_MK_MASK_CONST(0xffffffff) << DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT)
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_RANGE                        31:0
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_WOFFSET                      0x0
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register DVC_I2C_RX_FIFO_0  
+#define DVC_I2C_RX_FIFO_0                       _MK_ADDR_CONST(0x64)
+#define DVC_I2C_RX_FIFO_0_SECURE                        0x0
+#define DVC_I2C_RX_FIFO_0_WORD_COUNT                    0x1
+#define DVC_I2C_RX_FIFO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define DVC_I2C_RX_FIFO_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_RX_FIFO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_RX_FIFO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_RX_FIFO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_RX_FIFO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+//SW Reads data from this register,causes pop  
+#define DVC_I2C_RX_FIFO_0_RD_DATA_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_I2C_RX_FIFO_0_RD_DATA_FIELD                 (_MK_MASK_CONST(0xffffffff) << DVC_I2C_RX_FIFO_0_RD_DATA_SHIFT)
+#define DVC_I2C_RX_FIFO_0_RD_DATA_RANGE                 31:0
+#define DVC_I2C_RX_FIFO_0_RD_DATA_WOFFSET                       0x0
+#define DVC_I2C_RX_FIFO_0_RD_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_I2C_RX_FIFO_0_RD_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define DVC_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register DVC_PACKET_TRANSFER_STATUS_0  
+#define DVC_PACKET_TRANSFER_STATUS_0                    _MK_ADDR_CONST(0x68)
+#define DVC_PACKET_TRANSFER_STATUS_0_SECURE                     0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_WORD_COUNT                         0x1
+#define DVC_PACKET_TRANSFER_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x1ffffff)
+#define DVC_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1ffffff)
+#define DVC_PACKET_TRANSFER_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+//The packet transfer for which last packet is set has been
+//completed       
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT                    _MK_SHIFT_CONST(24)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_FIELD                    (_MK_MASK_CONST(0x1) << DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_RANGE                    24:24
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_WOFFSET                  0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_UNSET                    _MK_ENUM_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SET                      _MK_ENUM_CONST(1)
+
+//The current packet id for which the transaction is 
+//happening on the bus
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT                      _MK_SHIFT_CONST(16)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_FIELD                      (_MK_MASK_CONST(0xff) << DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_RANGE                      23:16
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_WOFFSET                    0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//The number of bytes transferred in the current packet 
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT                     _MK_SHIFT_CONST(4)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_FIELD                     (_MK_MASK_CONST(0xfff) << DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_RANGE                     15:4
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_WOFFSET                   0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//No ack recieved for the addr byte
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT                       _MK_SHIFT_CONST(3)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_FIELD                       (_MK_MASK_CONST(0x1) << DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_RANGE                       3:3
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_WOFFSET                     0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_UNSET                       _MK_ENUM_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SET                 _MK_ENUM_CONST(1)
+
+//No ack recieved for the data byte
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT                       _MK_SHIFT_CONST(2)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_FIELD                       (_MK_MASK_CONST(0x1) << DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_RANGE                       2:2
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_WOFFSET                     0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_UNSET                       _MK_ENUM_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SET                 _MK_ENUM_CONST(1)
+
+//Arbitration lost for the current byte
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT                     _MK_SHIFT_CONST(1)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_FIELD                     (_MK_MASK_CONST(0x1) << DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_RANGE                     1:1
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_WOFFSET                   0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_UNSET                     _MK_ENUM_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_ARB_LOST_SET                       _MK_ENUM_CONST(1)
+
+//1 = Controller is busy
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT                      _MK_SHIFT_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_FIELD                      (_MK_MASK_CONST(0x1) << DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_RANGE                      0:0
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_WOFFSET                    0x0
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_UNSET                      _MK_ENUM_CONST(0)
+#define DVC_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SET                        _MK_ENUM_CONST(1)
+
+
+// Register DVC_FIFO_CONTROL_0  
+#define DVC_FIFO_CONTROL_0                      _MK_ADDR_CONST(0x6c)
+#define DVC_FIFO_CONTROL_0_SECURE                       0x0
+#define DVC_FIFO_CONTROL_0_WORD_COUNT                   0x1
+#define DVC_FIFO_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define DVC_FIFO_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define DVC_FIFO_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+//Transmit fifo trigger level 
+//000 = 1 word,  Dma trigger is asserted when 
+//at least one word empty in the fifo 
+//010 = 2 word,  Dma trigger is asserted when 
+//at least 2 words empty in the fifo 
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_FIELD                   (_MK_MASK_CONST(0x7) << DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_RANGE                   7:5
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_WOFFSET                 0x0
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Receive fifo trigger level 
+//000 = 1 word  Dma trigger is asserted when 
+//at least one word full in the fifo 
+//010 = 2 word  Dma trigger is asserted when 
+//at least 2 word full in the fifo 
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT                   _MK_SHIFT_CONST(2)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_FIELD                   (_MK_MASK_CONST(0x7) << DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_RANGE                   4:2
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_WOFFSET                 0x0
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//1= flush the tx fifo,cleared after fifo is flushed
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT                  _MK_SHIFT_CONST(1)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_FIELD                  (_MK_MASK_CONST(0x1) << DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_RANGE                  1:1
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_WOFFSET                        0x0
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_UNSET                  _MK_ENUM_CONST(0)
+#define DVC_FIFO_CONTROL_0_TX_FIFO_FLUSH_SET                    _MK_ENUM_CONST(1)
+
+//1= flush the rx fifo,cleared after fifo is flushed 
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_FIELD                  (_MK_MASK_CONST(0x1) << DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_RANGE                  0:0
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_WOFFSET                        0x0
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_UNSET                  _MK_ENUM_CONST(0)
+#define DVC_FIFO_CONTROL_0_RX_FIFO_FLUSH_SET                    _MK_ENUM_CONST(1)
+
+
+// Register DVC_FIFO_STATUS_0  
+#define DVC_FIFO_STATUS_0                       _MK_ADDR_CONST(0x70)
+#define DVC_FIFO_STATUS_0_SECURE                        0x0
+#define DVC_FIFO_STATUS_0_WORD_COUNT                    0x1
+#define DVC_FIFO_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define DVC_FIFO_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define DVC_FIFO_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+//The number of slots that can be written to the tx fifo
+//0000 = tx_fifo full
+//0001 = 1 slot empty 
+//0010 = 2 slots empty 
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT                       _MK_SHIFT_CONST(4)
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_FIELD                       (_MK_MASK_CONST(0xf) << DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT)
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_RANGE                       7:4
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_WOFFSET                     0x0
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//The number of slots to be read from  the rx fifo
+//0000 = rx_fifo empty
+//0001 = 1 slot  full
+//0010 = 2 slots  full
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_FIELD                        (_MK_MASK_CONST(0xf) << DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT)
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_RANGE                        3:0
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_WOFFSET                      0x0
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register DVC_INTERRUPT_MASK_REGISTER_0  
+#define DVC_INTERRUPT_MASK_REGISTER_0                   _MK_ADDR_CONST(0x74)
+#define DVC_INTERRUPT_MASK_REGISTER_0_SECURE                    0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_WORD_COUNT                        0x1
+#define DVC_INTERRUPT_MASK_REGISTER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define DVC_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define DVC_INTERRUPT_MASK_REGISTER_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT                    _MK_SHIFT_CONST(6)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_RANGE                    6:6
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_WOFFSET                  0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT                    _MK_SHIFT_CONST(5)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_RANGE                    5:5
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_WOFFSET                  0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT                    _MK_SHIFT_CONST(4)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_RANGE                    4:4
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_WOFFSET                  0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT                        _MK_SHIFT_CONST(3)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_RANGE                        3:3
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_WOFFSET                      0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_FIELD                     (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_RANGE                     2:2
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_WOFFSET                   0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT                       _MK_SHIFT_CONST(1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_RANGE                       1:1
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_RANGE                       0:0
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register DVC_INTERRUPT_STATUS_REGISTER_0  //This register indicates the status bit for which the interrupt is set.If set,Write 1 to clear it
+//However TFIFO_DATA_REQ,RFIFO_DATA_REQ fields depend on the fifo trigger levels and cannot be cleared.
+#define DVC_INTERRUPT_STATUS_REGISTER_0                 _MK_ADDR_CONST(0x78)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_SECURE                  0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_WORD_COUNT                      0x1
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+//A packet has been transferred succesfully.
+//TRANSFER_PKT_ID filed can be used to know the 
+//current byte under transfer.This bit can be
+//masked by the IE field in the i2c specific header
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT                      _MK_SHIFT_CONST(7)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_FIELD                      (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_RANGE                      7:7
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_WOFFSET                    0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_UNSET                      _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SET                        _MK_ENUM_CONST(1)
+
+//All the packets transferred succesfully
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT                 _MK_SHIFT_CONST(6)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_FIELD                 (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_RANGE                 6:6
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_WOFFSET                       0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_UNSET                 _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SET                   _MK_ENUM_CONST(1)
+
+//Tx fifo overflow
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_FIELD                 (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_RANGE                 5:5
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_WOFFSET                       0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_UNSET                 _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SET                   _MK_ENUM_CONST(1)
+
+//rx fifo underflow
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT                 _MK_SHIFT_CONST(4)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_FIELD                 (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_RANGE                 4:4
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_WOFFSET                       0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_UNSET                 _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SET                   _MK_ENUM_CONST(1)
+
+//No ACK from slave
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT                     _MK_SHIFT_CONST(3)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_FIELD                     (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_RANGE                     3:3
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_WOFFSET                   0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_UNSET                     _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_NOACK_SET                       _MK_ENUM_CONST(1)
+
+//Arbitration lost
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT                  _MK_SHIFT_CONST(2)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_FIELD                  (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_RANGE                  2:2
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_WOFFSET                        0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_UNSET                  _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SET                    _MK_ENUM_CONST(1)
+
+//Tx fifo data req
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT                    _MK_SHIFT_CONST(1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_FIELD                    (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_RANGE                    1:1
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_WOFFSET                  0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_UNSET                    _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SET                      _MK_ENUM_CONST(1)
+
+//rx fifo data req
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT                    _MK_SHIFT_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_FIELD                    (_MK_MASK_CONST(0x1) << DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_RANGE                    0:0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_WOFFSET                  0x0
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_UNSET                    _MK_ENUM_CONST(0)
+#define DVC_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SET                      _MK_ENUM_CONST(1)
+
+
+// Register DVC_I2C_CLK_DIVISOR_REGISTER_0  
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0                  _MK_ADDR_CONST(0x7c)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_SECURE                   0x0
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_WORD_COUNT                       0x1
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//N= divide by n+1
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT                     _MK_SHIFT_CONST(0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_FIELD                     (_MK_MASK_CONST(0xffff) << DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_RANGE                     15:0
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_WOFFSET                   0x0
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_0  
+#define DVC_VSEL_MAP_LUT_0                      _MK_ADDR_CONST(0x80)
+#define DVC_VSEL_MAP_LUT_0_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_0_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_0_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_0_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_0_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_0_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_0_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_0_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_0_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_0_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_0_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_0_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_0_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_0_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_0_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_0_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_0_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_0_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT  
+#define DVC_VSEL_MAP_LUT                        _MK_ADDR_CONST(0x80)
+#define DVC_VSEL_MAP_LUT_SECURE                         0x0
+#define DVC_VSEL_MAP_LUT_WORD_COUNT                     0x1
+#define DVC_VSEL_MAP_LUT_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_RESET_MASK                     _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_READ_MASK                      _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_WRITE_MASK                     _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_VSEL3_SHIFT                    _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_VSEL3_FIELD                    (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_VSEL3_RANGE                    9:5
+#define DVC_VSEL_MAP_LUT_VSEL3_WOFFSET                  0x0
+#define DVC_VSEL_MAP_LUT_VSEL3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_VSEL3_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_VSEL3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_VSEL3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_VSEL2_SHIFT                    _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_VSEL2_FIELD                    (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_VSEL2_RANGE                    4:0
+#define DVC_VSEL_MAP_LUT_VSEL2_WOFFSET                  0x0
+#define DVC_VSEL_MAP_LUT_VSEL2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_VSEL2_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_VSEL2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_VSEL2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_1  
+#define DVC_VSEL_MAP_LUT_1                      _MK_ADDR_CONST(0x84)
+#define DVC_VSEL_MAP_LUT_1_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_1_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_1_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_1_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_1_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_1_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_1_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_1_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_1_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_1_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_1_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_1_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_1_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_1_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_1_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_1_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_1_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_1_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_1_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_2  
+#define DVC_VSEL_MAP_LUT_2                      _MK_ADDR_CONST(0x88)
+#define DVC_VSEL_MAP_LUT_2_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_2_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_2_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_2_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_2_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_2_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_2_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_2_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_2_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_2_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_2_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_2_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_2_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_2_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_2_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_2_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_2_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_2_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_2_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_3  
+#define DVC_VSEL_MAP_LUT_3                      _MK_ADDR_CONST(0x8c)
+#define DVC_VSEL_MAP_LUT_3_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_3_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_3_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_3_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_3_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_3_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_3_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_3_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_3_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_3_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_3_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_3_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_3_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_3_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_3_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_3_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_3_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_3_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_3_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_4  
+#define DVC_VSEL_MAP_LUT_4                      _MK_ADDR_CONST(0x90)
+#define DVC_VSEL_MAP_LUT_4_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_4_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_4_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_4_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_4_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_4_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_4_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_4_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_4_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_4_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_4_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_4_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_4_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_4_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_4_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_4_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_4_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_4_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_4_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_4_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_5  
+#define DVC_VSEL_MAP_LUT_5                      _MK_ADDR_CONST(0x94)
+#define DVC_VSEL_MAP_LUT_5_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_5_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_5_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_5_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_5_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_5_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_5_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_5_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_5_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_5_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_5_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_5_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_5_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_5_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_5_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_5_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_5_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_5_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_5_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_5_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_6  
+#define DVC_VSEL_MAP_LUT_6                      _MK_ADDR_CONST(0x98)
+#define DVC_VSEL_MAP_LUT_6_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_6_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_6_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_6_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_6_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_6_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_6_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_6_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_6_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_6_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_6_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_6_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_6_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_6_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_6_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_6_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_6_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_6_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_6_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_6_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_7  
+#define DVC_VSEL_MAP_LUT_7                      _MK_ADDR_CONST(0x9c)
+#define DVC_VSEL_MAP_LUT_7_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_7_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_7_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_7_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_7_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_7_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_7_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_7_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_7_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_7_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_7_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_7_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_7_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_7_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_7_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_7_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_7_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_7_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_7_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_7_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_8  
+#define DVC_VSEL_MAP_LUT_8                      _MK_ADDR_CONST(0xa0)
+#define DVC_VSEL_MAP_LUT_8_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_8_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_8_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_8_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_8_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_8_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_8_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_8_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_8_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_8_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_8_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_8_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_8_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_8_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_8_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_8_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_8_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_8_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_8_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_8_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_9  
+#define DVC_VSEL_MAP_LUT_9                      _MK_ADDR_CONST(0xa4)
+#define DVC_VSEL_MAP_LUT_9_SECURE                       0x0
+#define DVC_VSEL_MAP_LUT_9_WORD_COUNT                   0x1
+#define DVC_VSEL_MAP_LUT_9_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_9_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_9_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_9_VSEL3_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_9_VSEL3_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_9_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_9_VSEL3_RANGE                  9:5
+#define DVC_VSEL_MAP_LUT_9_VSEL3_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_9_VSEL3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_VSEL3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_9_VSEL3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_VSEL3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_9_VSEL2_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_9_VSEL2_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_9_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_9_VSEL2_RANGE                  4:0
+#define DVC_VSEL_MAP_LUT_9_VSEL2_WOFFSET                        0x0
+#define DVC_VSEL_MAP_LUT_9_VSEL2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_VSEL2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_9_VSEL2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_9_VSEL2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_10  
+#define DVC_VSEL_MAP_LUT_10                     _MK_ADDR_CONST(0xa8)
+#define DVC_VSEL_MAP_LUT_10_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_10_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_10_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_10_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_10_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_10_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_10_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_10_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_10_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_10_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_10_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_10_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_10_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_10_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_10_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_10_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_10_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_10_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_10_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_10_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_11  
+#define DVC_VSEL_MAP_LUT_11                     _MK_ADDR_CONST(0xac)
+#define DVC_VSEL_MAP_LUT_11_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_11_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_11_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_11_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_11_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_11_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_11_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_11_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_11_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_11_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_11_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_11_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_11_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_11_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_11_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_11_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_11_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_11_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_11_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_11_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_12  
+#define DVC_VSEL_MAP_LUT_12                     _MK_ADDR_CONST(0xb0)
+#define DVC_VSEL_MAP_LUT_12_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_12_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_12_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_12_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_12_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_12_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_12_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_12_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_12_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_12_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_12_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_12_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_12_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_12_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_12_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_12_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_12_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_12_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_12_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_12_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_13  
+#define DVC_VSEL_MAP_LUT_13                     _MK_ADDR_CONST(0xb4)
+#define DVC_VSEL_MAP_LUT_13_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_13_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_13_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_13_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_13_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_13_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_13_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_13_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_13_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_13_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_13_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_13_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_13_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_13_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_13_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_13_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_13_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_13_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_13_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_13_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_14  
+#define DVC_VSEL_MAP_LUT_14                     _MK_ADDR_CONST(0xb8)
+#define DVC_VSEL_MAP_LUT_14_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_14_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_14_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_14_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_14_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_14_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_14_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_14_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_14_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_14_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_14_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_14_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_14_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_14_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_14_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_14_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_14_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_14_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_14_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_14_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_15  
+#define DVC_VSEL_MAP_LUT_15                     _MK_ADDR_CONST(0xbc)
+#define DVC_VSEL_MAP_LUT_15_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_15_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_15_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_15_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_15_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_15_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_15_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_15_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_15_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_15_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_15_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_15_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_15_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_15_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_15_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_15_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_15_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_15_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_15_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_15_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_16  
+#define DVC_VSEL_MAP_LUT_16                     _MK_ADDR_CONST(0xc0)
+#define DVC_VSEL_MAP_LUT_16_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_16_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_16_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_16_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_16_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_16_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_16_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_16_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_16_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_16_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_16_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_16_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_16_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_16_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_16_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_16_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_16_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_16_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_16_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_16_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_17  
+#define DVC_VSEL_MAP_LUT_17                     _MK_ADDR_CONST(0xc4)
+#define DVC_VSEL_MAP_LUT_17_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_17_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_17_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_17_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_17_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_17_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_17_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_17_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_17_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_17_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_17_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_17_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_17_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_17_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_17_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_17_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_17_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_17_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_17_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_17_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_18  
+#define DVC_VSEL_MAP_LUT_18                     _MK_ADDR_CONST(0xc8)
+#define DVC_VSEL_MAP_LUT_18_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_18_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_18_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_18_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_18_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_18_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_18_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_18_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_18_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_18_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_18_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_18_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_18_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_18_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_18_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_18_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_18_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_18_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_18_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_18_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_19  
+#define DVC_VSEL_MAP_LUT_19                     _MK_ADDR_CONST(0xcc)
+#define DVC_VSEL_MAP_LUT_19_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_19_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_19_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_19_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_19_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_19_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_19_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_19_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_19_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_19_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_19_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_19_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_19_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_19_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_19_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_19_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_19_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_19_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_19_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_19_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_20  
+#define DVC_VSEL_MAP_LUT_20                     _MK_ADDR_CONST(0xd0)
+#define DVC_VSEL_MAP_LUT_20_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_20_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_20_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_20_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_20_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_20_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_20_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_20_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_20_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_20_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_20_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_20_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_20_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_20_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_20_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_20_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_20_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_20_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_20_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_20_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_21  
+#define DVC_VSEL_MAP_LUT_21                     _MK_ADDR_CONST(0xd4)
+#define DVC_VSEL_MAP_LUT_21_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_21_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_21_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_21_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_21_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_21_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_21_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_21_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_21_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_21_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_21_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_21_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_21_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_21_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_21_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_21_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_21_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_21_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_21_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_21_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_22  
+#define DVC_VSEL_MAP_LUT_22                     _MK_ADDR_CONST(0xd8)
+#define DVC_VSEL_MAP_LUT_22_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_22_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_22_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_22_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_22_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_22_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_22_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_22_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_22_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_22_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_22_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_22_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_22_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_22_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_22_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_22_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_22_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_22_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_22_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_22_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_23  
+#define DVC_VSEL_MAP_LUT_23                     _MK_ADDR_CONST(0xdc)
+#define DVC_VSEL_MAP_LUT_23_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_23_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_23_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_23_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_23_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_23_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_23_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_23_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_23_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_23_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_23_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_23_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_23_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_23_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_23_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_23_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_23_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_23_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_23_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_23_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_24  
+#define DVC_VSEL_MAP_LUT_24                     _MK_ADDR_CONST(0xe0)
+#define DVC_VSEL_MAP_LUT_24_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_24_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_24_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_24_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_24_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_24_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_24_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_24_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_24_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_24_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_24_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_24_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_24_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_24_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_24_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_24_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_24_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_24_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_24_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_24_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_25  
+#define DVC_VSEL_MAP_LUT_25                     _MK_ADDR_CONST(0xe4)
+#define DVC_VSEL_MAP_LUT_25_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_25_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_25_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_25_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_25_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_25_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_25_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_25_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_25_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_25_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_25_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_25_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_25_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_25_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_25_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_25_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_25_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_25_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_25_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_25_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_26  
+#define DVC_VSEL_MAP_LUT_26                     _MK_ADDR_CONST(0xe8)
+#define DVC_VSEL_MAP_LUT_26_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_26_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_26_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_26_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_26_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_26_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_26_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_26_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_26_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_26_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_26_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_26_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_26_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_26_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_26_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_26_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_26_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_26_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_26_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_26_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_27  
+#define DVC_VSEL_MAP_LUT_27                     _MK_ADDR_CONST(0xec)
+#define DVC_VSEL_MAP_LUT_27_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_27_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_27_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_27_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_27_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_27_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_27_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_27_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_27_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_27_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_27_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_27_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_27_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_27_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_27_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_27_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_27_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_27_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_27_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_27_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_28  
+#define DVC_VSEL_MAP_LUT_28                     _MK_ADDR_CONST(0xf0)
+#define DVC_VSEL_MAP_LUT_28_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_28_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_28_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_28_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_28_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_28_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_28_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_28_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_28_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_28_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_28_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_28_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_28_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_28_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_28_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_28_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_28_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_28_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_28_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_28_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_29  
+#define DVC_VSEL_MAP_LUT_29                     _MK_ADDR_CONST(0xf4)
+#define DVC_VSEL_MAP_LUT_29_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_29_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_29_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_29_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_29_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_29_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_29_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_29_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_29_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_29_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_29_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_29_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_29_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_29_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_29_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_29_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_29_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_29_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_29_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_29_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_30  
+#define DVC_VSEL_MAP_LUT_30                     _MK_ADDR_CONST(0xf8)
+#define DVC_VSEL_MAP_LUT_30_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_30_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_30_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_30_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_30_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_30_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_30_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_30_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_30_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_30_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_30_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_30_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_30_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_30_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_30_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_30_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_30_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_30_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_30_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_30_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VSEL_MAP_LUT_31  
+#define DVC_VSEL_MAP_LUT_31                     _MK_ADDR_CONST(0xfc)
+#define DVC_VSEL_MAP_LUT_31_SECURE                      0x0
+#define DVC_VSEL_MAP_LUT_31_WORD_COUNT                  0x1
+#define DVC_VSEL_MAP_LUT_31_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_31_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define DVC_VSEL_MAP_LUT_31_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+//VSEL3 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_31_VSEL3_SHIFT                 _MK_SHIFT_CONST(5)
+#define DVC_VSEL_MAP_LUT_31_VSEL3_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_31_VSEL3_SHIFT)
+#define DVC_VSEL_MAP_LUT_31_VSEL3_RANGE                 9:5
+#define DVC_VSEL_MAP_LUT_31_VSEL3_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_31_VSEL3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_VSEL3_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_31_VSEL3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_VSEL3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//VSEL2 Corresponding to VSEL1
+#define DVC_VSEL_MAP_LUT_31_VSEL2_SHIFT                 _MK_SHIFT_CONST(0)
+#define DVC_VSEL_MAP_LUT_31_VSEL2_FIELD                 (_MK_MASK_CONST(0x1f) << DVC_VSEL_MAP_LUT_31_VSEL2_SHIFT)
+#define DVC_VSEL_MAP_LUT_31_VSEL2_RANGE                 4:0
+#define DVC_VSEL_MAP_LUT_31_VSEL2_WOFFSET                       0x0
+#define DVC_VSEL_MAP_LUT_31_VSEL2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_VSEL2_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define DVC_VSEL_MAP_LUT_31_VSEL2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VSEL_MAP_LUT_31_VSEL2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_0  
+#define DVC_VLUT_0                      _MK_ADDR_CONST(0x100)
+#define DVC_VLUT_0_SECURE                       0x0
+#define DVC_VLUT_0_WORD_COUNT                   0x1
+#define DVC_VLUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_0_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_0_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_0_PMCNT_SHIFT)
+#define DVC_VLUT_0_PMCNT_RANGE                  23:10
+#define DVC_VLUT_0_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_0_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_0_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_0_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_0_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_0_VMIN_SHIFT)
+#define DVC_VLUT_0_VMIN_RANGE                   9:5
+#define DVC_VLUT_0_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_0_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_0_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_0_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_0_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_0_VMAX_SHIFT)
+#define DVC_VLUT_0_VMAX_RANGE                   4:0
+#define DVC_VLUT_0_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_0_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_0_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_0_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT  
+#define DVC_VLUT                        _MK_ADDR_CONST(0x100)
+#define DVC_VLUT_SECURE                         0x0
+#define DVC_VLUT_WORD_COUNT                     0x1
+#define DVC_VLUT_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_RESET_MASK                     _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define DVC_VLUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_READ_MASK                      _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_WRITE_MASK                     _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_PMCNT_SHIFT                    _MK_SHIFT_CONST(10)
+#define DVC_VLUT_PMCNT_FIELD                    (_MK_MASK_CONST(0x3fff) << DVC_VLUT_PMCNT_SHIFT)
+#define DVC_VLUT_PMCNT_RANGE                    23:10
+#define DVC_VLUT_PMCNT_WOFFSET                  0x0
+#define DVC_VLUT_PMCNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define DVC_VLUT_PMCNT_DEFAULT_MASK                     _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_PMCNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_PMCNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_VMIN_SHIFT                     _MK_SHIFT_CONST(5)
+#define DVC_VLUT_VMIN_FIELD                     (_MK_MASK_CONST(0x1f) << DVC_VLUT_VMIN_SHIFT)
+#define DVC_VLUT_VMIN_RANGE                     9:5
+#define DVC_VLUT_VMIN_WOFFSET                   0x0
+#define DVC_VLUT_VMIN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_VMIN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_VMIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_VMIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_VMAX_SHIFT                     _MK_SHIFT_CONST(0)
+#define DVC_VLUT_VMAX_FIELD                     (_MK_MASK_CONST(0x1f) << DVC_VLUT_VMAX_SHIFT)
+#define DVC_VLUT_VMAX_RANGE                     4:0
+#define DVC_VLUT_VMAX_WOFFSET                   0x0
+#define DVC_VLUT_VMAX_DEFAULT                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_VMAX_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_VMAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_VMAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_1  
+#define DVC_VLUT_1                      _MK_ADDR_CONST(0x104)
+#define DVC_VLUT_1_SECURE                       0x0
+#define DVC_VLUT_1_WORD_COUNT                   0x1
+#define DVC_VLUT_1_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_1_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_1_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_1_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_1_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_1_PMCNT_SHIFT)
+#define DVC_VLUT_1_PMCNT_RANGE                  23:10
+#define DVC_VLUT_1_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_1_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_1_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_1_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_1_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_1_VMIN_SHIFT)
+#define DVC_VLUT_1_VMIN_RANGE                   9:5
+#define DVC_VLUT_1_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_1_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_1_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_1_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_1_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_1_VMAX_SHIFT)
+#define DVC_VLUT_1_VMAX_RANGE                   4:0
+#define DVC_VLUT_1_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_1_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_1_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_1_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_2  
+#define DVC_VLUT_2                      _MK_ADDR_CONST(0x108)
+#define DVC_VLUT_2_SECURE                       0x0
+#define DVC_VLUT_2_WORD_COUNT                   0x1
+#define DVC_VLUT_2_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_2_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_2_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_2_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_2_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_2_PMCNT_SHIFT)
+#define DVC_VLUT_2_PMCNT_RANGE                  23:10
+#define DVC_VLUT_2_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_2_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_2_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_2_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_2_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_2_VMIN_SHIFT)
+#define DVC_VLUT_2_VMIN_RANGE                   9:5
+#define DVC_VLUT_2_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_2_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_2_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_2_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_2_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_2_VMAX_SHIFT)
+#define DVC_VLUT_2_VMAX_RANGE                   4:0
+#define DVC_VLUT_2_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_2_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_2_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_2_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_3  
+#define DVC_VLUT_3                      _MK_ADDR_CONST(0x10c)
+#define DVC_VLUT_3_SECURE                       0x0
+#define DVC_VLUT_3_WORD_COUNT                   0x1
+#define DVC_VLUT_3_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_3_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_3_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_3_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_3_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_3_PMCNT_SHIFT)
+#define DVC_VLUT_3_PMCNT_RANGE                  23:10
+#define DVC_VLUT_3_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_3_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_3_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_3_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_3_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_3_VMIN_SHIFT)
+#define DVC_VLUT_3_VMIN_RANGE                   9:5
+#define DVC_VLUT_3_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_3_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_3_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_3_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_3_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_3_VMAX_SHIFT)
+#define DVC_VLUT_3_VMAX_RANGE                   4:0
+#define DVC_VLUT_3_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_3_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_3_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_3_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_4  
+#define DVC_VLUT_4                      _MK_ADDR_CONST(0x110)
+#define DVC_VLUT_4_SECURE                       0x0
+#define DVC_VLUT_4_WORD_COUNT                   0x1
+#define DVC_VLUT_4_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_4_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_4_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_4_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_4_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_4_PMCNT_SHIFT)
+#define DVC_VLUT_4_PMCNT_RANGE                  23:10
+#define DVC_VLUT_4_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_4_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_4_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_4_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_4_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_4_VMIN_SHIFT)
+#define DVC_VLUT_4_VMIN_RANGE                   9:5
+#define DVC_VLUT_4_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_4_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_4_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_4_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_4_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_4_VMAX_SHIFT)
+#define DVC_VLUT_4_VMAX_RANGE                   4:0
+#define DVC_VLUT_4_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_4_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_4_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_4_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_5  
+#define DVC_VLUT_5                      _MK_ADDR_CONST(0x114)
+#define DVC_VLUT_5_SECURE                       0x0
+#define DVC_VLUT_5_WORD_COUNT                   0x1
+#define DVC_VLUT_5_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_5_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_5_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_5_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_5_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_5_PMCNT_SHIFT)
+#define DVC_VLUT_5_PMCNT_RANGE                  23:10
+#define DVC_VLUT_5_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_5_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_5_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_5_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_5_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_5_VMIN_SHIFT)
+#define DVC_VLUT_5_VMIN_RANGE                   9:5
+#define DVC_VLUT_5_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_5_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_5_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_5_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_5_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_5_VMAX_SHIFT)
+#define DVC_VLUT_5_VMAX_RANGE                   4:0
+#define DVC_VLUT_5_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_5_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_5_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_5_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_6  
+#define DVC_VLUT_6                      _MK_ADDR_CONST(0x118)
+#define DVC_VLUT_6_SECURE                       0x0
+#define DVC_VLUT_6_WORD_COUNT                   0x1
+#define DVC_VLUT_6_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_6_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_6_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_6_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_6_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_6_PMCNT_SHIFT)
+#define DVC_VLUT_6_PMCNT_RANGE                  23:10
+#define DVC_VLUT_6_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_6_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_6_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_6_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_6_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_6_VMIN_SHIFT)
+#define DVC_VLUT_6_VMIN_RANGE                   9:5
+#define DVC_VLUT_6_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_6_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_6_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_6_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_6_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_6_VMAX_SHIFT)
+#define DVC_VLUT_6_VMAX_RANGE                   4:0
+#define DVC_VLUT_6_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_6_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_6_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_6_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_7  
+#define DVC_VLUT_7                      _MK_ADDR_CONST(0x11c)
+#define DVC_VLUT_7_SECURE                       0x0
+#define DVC_VLUT_7_WORD_COUNT                   0x1
+#define DVC_VLUT_7_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_7_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_7_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_7_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_7_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_7_PMCNT_SHIFT)
+#define DVC_VLUT_7_PMCNT_RANGE                  23:10
+#define DVC_VLUT_7_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_7_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_7_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_7_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_7_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_7_VMIN_SHIFT)
+#define DVC_VLUT_7_VMIN_RANGE                   9:5
+#define DVC_VLUT_7_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_7_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_7_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_7_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_7_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_7_VMAX_SHIFT)
+#define DVC_VLUT_7_VMAX_RANGE                   4:0
+#define DVC_VLUT_7_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_7_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_7_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_7_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_8  
+#define DVC_VLUT_8                      _MK_ADDR_CONST(0x120)
+#define DVC_VLUT_8_SECURE                       0x0
+#define DVC_VLUT_8_WORD_COUNT                   0x1
+#define DVC_VLUT_8_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_8_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_8_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_8_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_8_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_8_PMCNT_SHIFT)
+#define DVC_VLUT_8_PMCNT_RANGE                  23:10
+#define DVC_VLUT_8_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_8_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_8_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_8_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_8_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_8_VMIN_SHIFT)
+#define DVC_VLUT_8_VMIN_RANGE                   9:5
+#define DVC_VLUT_8_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_8_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_8_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_8_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_8_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_8_VMAX_SHIFT)
+#define DVC_VLUT_8_VMAX_RANGE                   4:0
+#define DVC_VLUT_8_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_8_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_8_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_8_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_9  
+#define DVC_VLUT_9                      _MK_ADDR_CONST(0x124)
+#define DVC_VLUT_9_SECURE                       0x0
+#define DVC_VLUT_9_WORD_COUNT                   0x1
+#define DVC_VLUT_9_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_9_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_9_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_9_PMCNT_SHIFT                  _MK_SHIFT_CONST(10)
+#define DVC_VLUT_9_PMCNT_FIELD                  (_MK_MASK_CONST(0x3fff) << DVC_VLUT_9_PMCNT_SHIFT)
+#define DVC_VLUT_9_PMCNT_RANGE                  23:10
+#define DVC_VLUT_9_PMCNT_WOFFSET                        0x0
+#define DVC_VLUT_9_PMCNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_PMCNT_DEFAULT_MASK                   _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_9_PMCNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_PMCNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_9_VMIN_SHIFT                   _MK_SHIFT_CONST(5)
+#define DVC_VLUT_9_VMIN_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_9_VMIN_SHIFT)
+#define DVC_VLUT_9_VMIN_RANGE                   9:5
+#define DVC_VLUT_9_VMIN_WOFFSET                 0x0
+#define DVC_VLUT_9_VMIN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_VMIN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_9_VMIN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_VMIN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_9_VMAX_SHIFT                   _MK_SHIFT_CONST(0)
+#define DVC_VLUT_9_VMAX_FIELD                   (_MK_MASK_CONST(0x1f) << DVC_VLUT_9_VMAX_SHIFT)
+#define DVC_VLUT_9_VMAX_RANGE                   4:0
+#define DVC_VLUT_9_VMAX_WOFFSET                 0x0
+#define DVC_VLUT_9_VMAX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_VMAX_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_9_VMAX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_9_VMAX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_10  
+#define DVC_VLUT_10                     _MK_ADDR_CONST(0x128)
+#define DVC_VLUT_10_SECURE                      0x0
+#define DVC_VLUT_10_WORD_COUNT                  0x1
+#define DVC_VLUT_10_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_10_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_10_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_10_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_10_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_10_PMCNT_SHIFT)
+#define DVC_VLUT_10_PMCNT_RANGE                 23:10
+#define DVC_VLUT_10_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_10_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_10_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_10_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_10_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_10_VMIN_SHIFT)
+#define DVC_VLUT_10_VMIN_RANGE                  9:5
+#define DVC_VLUT_10_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_10_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_10_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_10_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_10_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_10_VMAX_SHIFT)
+#define DVC_VLUT_10_VMAX_RANGE                  4:0
+#define DVC_VLUT_10_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_10_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_10_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_10_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_11  
+#define DVC_VLUT_11                     _MK_ADDR_CONST(0x12c)
+#define DVC_VLUT_11_SECURE                      0x0
+#define DVC_VLUT_11_WORD_COUNT                  0x1
+#define DVC_VLUT_11_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_11_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_11_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_11_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_11_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_11_PMCNT_SHIFT)
+#define DVC_VLUT_11_PMCNT_RANGE                 23:10
+#define DVC_VLUT_11_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_11_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_11_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_11_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_11_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_11_VMIN_SHIFT)
+#define DVC_VLUT_11_VMIN_RANGE                  9:5
+#define DVC_VLUT_11_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_11_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_11_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_11_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_11_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_11_VMAX_SHIFT)
+#define DVC_VLUT_11_VMAX_RANGE                  4:0
+#define DVC_VLUT_11_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_11_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_11_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_11_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_12  
+#define DVC_VLUT_12                     _MK_ADDR_CONST(0x130)
+#define DVC_VLUT_12_SECURE                      0x0
+#define DVC_VLUT_12_WORD_COUNT                  0x1
+#define DVC_VLUT_12_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_12_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_12_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_12_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_12_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_12_PMCNT_SHIFT)
+#define DVC_VLUT_12_PMCNT_RANGE                 23:10
+#define DVC_VLUT_12_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_12_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_12_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_12_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_12_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_12_VMIN_SHIFT)
+#define DVC_VLUT_12_VMIN_RANGE                  9:5
+#define DVC_VLUT_12_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_12_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_12_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_12_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_12_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_12_VMAX_SHIFT)
+#define DVC_VLUT_12_VMAX_RANGE                  4:0
+#define DVC_VLUT_12_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_12_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_12_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_12_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_13  
+#define DVC_VLUT_13                     _MK_ADDR_CONST(0x134)
+#define DVC_VLUT_13_SECURE                      0x0
+#define DVC_VLUT_13_WORD_COUNT                  0x1
+#define DVC_VLUT_13_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_13_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_13_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_13_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_13_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_13_PMCNT_SHIFT)
+#define DVC_VLUT_13_PMCNT_RANGE                 23:10
+#define DVC_VLUT_13_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_13_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_13_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_13_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_13_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_13_VMIN_SHIFT)
+#define DVC_VLUT_13_VMIN_RANGE                  9:5
+#define DVC_VLUT_13_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_13_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_13_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_13_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_13_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_13_VMAX_SHIFT)
+#define DVC_VLUT_13_VMAX_RANGE                  4:0
+#define DVC_VLUT_13_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_13_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_13_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_13_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_14  
+#define DVC_VLUT_14                     _MK_ADDR_CONST(0x138)
+#define DVC_VLUT_14_SECURE                      0x0
+#define DVC_VLUT_14_WORD_COUNT                  0x1
+#define DVC_VLUT_14_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_14_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_14_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_14_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_14_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_14_PMCNT_SHIFT)
+#define DVC_VLUT_14_PMCNT_RANGE                 23:10
+#define DVC_VLUT_14_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_14_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_14_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_14_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_14_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_14_VMIN_SHIFT)
+#define DVC_VLUT_14_VMIN_RANGE                  9:5
+#define DVC_VLUT_14_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_14_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_14_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_14_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_14_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_14_VMAX_SHIFT)
+#define DVC_VLUT_14_VMAX_RANGE                  4:0
+#define DVC_VLUT_14_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_14_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_14_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_14_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_15  
+#define DVC_VLUT_15                     _MK_ADDR_CONST(0x13c)
+#define DVC_VLUT_15_SECURE                      0x0
+#define DVC_VLUT_15_WORD_COUNT                  0x1
+#define DVC_VLUT_15_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_15_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_15_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_15_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_15_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_15_PMCNT_SHIFT)
+#define DVC_VLUT_15_PMCNT_RANGE                 23:10
+#define DVC_VLUT_15_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_15_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_15_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_15_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_15_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_15_VMIN_SHIFT)
+#define DVC_VLUT_15_VMIN_RANGE                  9:5
+#define DVC_VLUT_15_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_15_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_15_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_15_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_15_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_15_VMAX_SHIFT)
+#define DVC_VLUT_15_VMAX_RANGE                  4:0
+#define DVC_VLUT_15_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_15_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_15_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_15_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_16  
+#define DVC_VLUT_16                     _MK_ADDR_CONST(0x140)
+#define DVC_VLUT_16_SECURE                      0x0
+#define DVC_VLUT_16_WORD_COUNT                  0x1
+#define DVC_VLUT_16_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_16_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_16_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_16_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_16_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_16_PMCNT_SHIFT)
+#define DVC_VLUT_16_PMCNT_RANGE                 23:10
+#define DVC_VLUT_16_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_16_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_16_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_16_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_16_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_16_VMIN_SHIFT)
+#define DVC_VLUT_16_VMIN_RANGE                  9:5
+#define DVC_VLUT_16_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_16_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_16_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_16_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_16_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_16_VMAX_SHIFT)
+#define DVC_VLUT_16_VMAX_RANGE                  4:0
+#define DVC_VLUT_16_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_16_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_16_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_16_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_17  
+#define DVC_VLUT_17                     _MK_ADDR_CONST(0x144)
+#define DVC_VLUT_17_SECURE                      0x0
+#define DVC_VLUT_17_WORD_COUNT                  0x1
+#define DVC_VLUT_17_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_17_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_17_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_17_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_17_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_17_PMCNT_SHIFT)
+#define DVC_VLUT_17_PMCNT_RANGE                 23:10
+#define DVC_VLUT_17_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_17_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_17_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_17_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_17_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_17_VMIN_SHIFT)
+#define DVC_VLUT_17_VMIN_RANGE                  9:5
+#define DVC_VLUT_17_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_17_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_17_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_17_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_17_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_17_VMAX_SHIFT)
+#define DVC_VLUT_17_VMAX_RANGE                  4:0
+#define DVC_VLUT_17_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_17_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_17_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_17_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_18  
+#define DVC_VLUT_18                     _MK_ADDR_CONST(0x148)
+#define DVC_VLUT_18_SECURE                      0x0
+#define DVC_VLUT_18_WORD_COUNT                  0x1
+#define DVC_VLUT_18_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_18_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_18_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_18_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_18_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_18_PMCNT_SHIFT)
+#define DVC_VLUT_18_PMCNT_RANGE                 23:10
+#define DVC_VLUT_18_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_18_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_18_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_18_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_18_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_18_VMIN_SHIFT)
+#define DVC_VLUT_18_VMIN_RANGE                  9:5
+#define DVC_VLUT_18_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_18_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_18_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_18_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_18_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_18_VMAX_SHIFT)
+#define DVC_VLUT_18_VMAX_RANGE                  4:0
+#define DVC_VLUT_18_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_18_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_18_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_18_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_19  
+#define DVC_VLUT_19                     _MK_ADDR_CONST(0x14c)
+#define DVC_VLUT_19_SECURE                      0x0
+#define DVC_VLUT_19_WORD_COUNT                  0x1
+#define DVC_VLUT_19_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_19_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_19_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_19_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_19_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_19_PMCNT_SHIFT)
+#define DVC_VLUT_19_PMCNT_RANGE                 23:10
+#define DVC_VLUT_19_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_19_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_19_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_19_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_19_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_19_VMIN_SHIFT)
+#define DVC_VLUT_19_VMIN_RANGE                  9:5
+#define DVC_VLUT_19_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_19_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_19_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_19_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_19_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_19_VMAX_SHIFT)
+#define DVC_VLUT_19_VMAX_RANGE                  4:0
+#define DVC_VLUT_19_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_19_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_19_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_19_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_20  
+#define DVC_VLUT_20                     _MK_ADDR_CONST(0x150)
+#define DVC_VLUT_20_SECURE                      0x0
+#define DVC_VLUT_20_WORD_COUNT                  0x1
+#define DVC_VLUT_20_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_20_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_20_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_20_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_20_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_20_PMCNT_SHIFT)
+#define DVC_VLUT_20_PMCNT_RANGE                 23:10
+#define DVC_VLUT_20_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_20_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_20_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_20_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_20_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_20_VMIN_SHIFT)
+#define DVC_VLUT_20_VMIN_RANGE                  9:5
+#define DVC_VLUT_20_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_20_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_20_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_20_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_20_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_20_VMAX_SHIFT)
+#define DVC_VLUT_20_VMAX_RANGE                  4:0
+#define DVC_VLUT_20_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_20_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_20_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_20_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_21  
+#define DVC_VLUT_21                     _MK_ADDR_CONST(0x154)
+#define DVC_VLUT_21_SECURE                      0x0
+#define DVC_VLUT_21_WORD_COUNT                  0x1
+#define DVC_VLUT_21_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_21_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_21_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_21_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_21_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_21_PMCNT_SHIFT)
+#define DVC_VLUT_21_PMCNT_RANGE                 23:10
+#define DVC_VLUT_21_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_21_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_21_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_21_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_21_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_21_VMIN_SHIFT)
+#define DVC_VLUT_21_VMIN_RANGE                  9:5
+#define DVC_VLUT_21_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_21_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_21_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_21_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_21_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_21_VMAX_SHIFT)
+#define DVC_VLUT_21_VMAX_RANGE                  4:0
+#define DVC_VLUT_21_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_21_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_21_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_21_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_22  
+#define DVC_VLUT_22                     _MK_ADDR_CONST(0x158)
+#define DVC_VLUT_22_SECURE                      0x0
+#define DVC_VLUT_22_WORD_COUNT                  0x1
+#define DVC_VLUT_22_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_22_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_22_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_22_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_22_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_22_PMCNT_SHIFT)
+#define DVC_VLUT_22_PMCNT_RANGE                 23:10
+#define DVC_VLUT_22_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_22_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_22_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_22_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_22_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_22_VMIN_SHIFT)
+#define DVC_VLUT_22_VMIN_RANGE                  9:5
+#define DVC_VLUT_22_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_22_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_22_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_22_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_22_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_22_VMAX_SHIFT)
+#define DVC_VLUT_22_VMAX_RANGE                  4:0
+#define DVC_VLUT_22_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_22_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_22_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_22_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_23  
+#define DVC_VLUT_23                     _MK_ADDR_CONST(0x15c)
+#define DVC_VLUT_23_SECURE                      0x0
+#define DVC_VLUT_23_WORD_COUNT                  0x1
+#define DVC_VLUT_23_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_23_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_23_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_23_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_23_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_23_PMCNT_SHIFT)
+#define DVC_VLUT_23_PMCNT_RANGE                 23:10
+#define DVC_VLUT_23_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_23_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_23_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_23_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_23_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_23_VMIN_SHIFT)
+#define DVC_VLUT_23_VMIN_RANGE                  9:5
+#define DVC_VLUT_23_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_23_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_23_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_23_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_23_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_23_VMAX_SHIFT)
+#define DVC_VLUT_23_VMAX_RANGE                  4:0
+#define DVC_VLUT_23_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_23_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_23_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_23_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_24  
+#define DVC_VLUT_24                     _MK_ADDR_CONST(0x160)
+#define DVC_VLUT_24_SECURE                      0x0
+#define DVC_VLUT_24_WORD_COUNT                  0x1
+#define DVC_VLUT_24_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_24_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_24_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_24_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_24_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_24_PMCNT_SHIFT)
+#define DVC_VLUT_24_PMCNT_RANGE                 23:10
+#define DVC_VLUT_24_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_24_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_24_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_24_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_24_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_24_VMIN_SHIFT)
+#define DVC_VLUT_24_VMIN_RANGE                  9:5
+#define DVC_VLUT_24_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_24_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_24_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_24_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_24_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_24_VMAX_SHIFT)
+#define DVC_VLUT_24_VMAX_RANGE                  4:0
+#define DVC_VLUT_24_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_24_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_24_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_24_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_25  
+#define DVC_VLUT_25                     _MK_ADDR_CONST(0x164)
+#define DVC_VLUT_25_SECURE                      0x0
+#define DVC_VLUT_25_WORD_COUNT                  0x1
+#define DVC_VLUT_25_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_25_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_25_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_25_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_25_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_25_PMCNT_SHIFT)
+#define DVC_VLUT_25_PMCNT_RANGE                 23:10
+#define DVC_VLUT_25_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_25_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_25_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_25_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_25_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_25_VMIN_SHIFT)
+#define DVC_VLUT_25_VMIN_RANGE                  9:5
+#define DVC_VLUT_25_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_25_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_25_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_25_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_25_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_25_VMAX_SHIFT)
+#define DVC_VLUT_25_VMAX_RANGE                  4:0
+#define DVC_VLUT_25_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_25_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_25_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_25_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_26  
+#define DVC_VLUT_26                     _MK_ADDR_CONST(0x168)
+#define DVC_VLUT_26_SECURE                      0x0
+#define DVC_VLUT_26_WORD_COUNT                  0x1
+#define DVC_VLUT_26_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_26_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_26_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_26_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_26_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_26_PMCNT_SHIFT)
+#define DVC_VLUT_26_PMCNT_RANGE                 23:10
+#define DVC_VLUT_26_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_26_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_26_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_26_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_26_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_26_VMIN_SHIFT)
+#define DVC_VLUT_26_VMIN_RANGE                  9:5
+#define DVC_VLUT_26_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_26_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_26_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_26_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_26_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_26_VMAX_SHIFT)
+#define DVC_VLUT_26_VMAX_RANGE                  4:0
+#define DVC_VLUT_26_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_26_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_26_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_26_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_27  
+#define DVC_VLUT_27                     _MK_ADDR_CONST(0x16c)
+#define DVC_VLUT_27_SECURE                      0x0
+#define DVC_VLUT_27_WORD_COUNT                  0x1
+#define DVC_VLUT_27_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_27_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_27_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_27_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_27_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_27_PMCNT_SHIFT)
+#define DVC_VLUT_27_PMCNT_RANGE                 23:10
+#define DVC_VLUT_27_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_27_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_27_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_27_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_27_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_27_VMIN_SHIFT)
+#define DVC_VLUT_27_VMIN_RANGE                  9:5
+#define DVC_VLUT_27_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_27_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_27_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_27_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_27_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_27_VMAX_SHIFT)
+#define DVC_VLUT_27_VMAX_RANGE                  4:0
+#define DVC_VLUT_27_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_27_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_27_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_27_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_28  
+#define DVC_VLUT_28                     _MK_ADDR_CONST(0x170)
+#define DVC_VLUT_28_SECURE                      0x0
+#define DVC_VLUT_28_WORD_COUNT                  0x1
+#define DVC_VLUT_28_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_28_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_28_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_28_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_28_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_28_PMCNT_SHIFT)
+#define DVC_VLUT_28_PMCNT_RANGE                 23:10
+#define DVC_VLUT_28_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_28_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_28_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_28_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_28_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_28_VMIN_SHIFT)
+#define DVC_VLUT_28_VMIN_RANGE                  9:5
+#define DVC_VLUT_28_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_28_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_28_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_28_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_28_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_28_VMAX_SHIFT)
+#define DVC_VLUT_28_VMAX_RANGE                  4:0
+#define DVC_VLUT_28_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_28_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_28_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_28_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_29  
+#define DVC_VLUT_29                     _MK_ADDR_CONST(0x174)
+#define DVC_VLUT_29_SECURE                      0x0
+#define DVC_VLUT_29_WORD_COUNT                  0x1
+#define DVC_VLUT_29_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_29_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_29_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_29_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_29_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_29_PMCNT_SHIFT)
+#define DVC_VLUT_29_PMCNT_RANGE                 23:10
+#define DVC_VLUT_29_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_29_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_29_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_29_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_29_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_29_VMIN_SHIFT)
+#define DVC_VLUT_29_VMIN_RANGE                  9:5
+#define DVC_VLUT_29_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_29_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_29_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_29_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_29_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_29_VMAX_SHIFT)
+#define DVC_VLUT_29_VMAX_RANGE                  4:0
+#define DVC_VLUT_29_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_29_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_29_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_29_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_30  
+#define DVC_VLUT_30                     _MK_ADDR_CONST(0x178)
+#define DVC_VLUT_30_SECURE                      0x0
+#define DVC_VLUT_30_WORD_COUNT                  0x1
+#define DVC_VLUT_30_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_30_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_30_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_30_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_30_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_30_PMCNT_SHIFT)
+#define DVC_VLUT_30_PMCNT_RANGE                 23:10
+#define DVC_VLUT_30_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_30_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_30_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_30_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_30_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_30_VMIN_SHIFT)
+#define DVC_VLUT_30_VMIN_RANGE                  9:5
+#define DVC_VLUT_30_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_30_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_30_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_30_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_30_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_30_VMAX_SHIFT)
+#define DVC_VLUT_30_VMAX_RANGE                  4:0
+#define DVC_VLUT_30_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_30_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_30_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_30_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_31  
+#define DVC_VLUT_31                     _MK_ADDR_CONST(0x17c)
+#define DVC_VLUT_31_SECURE                      0x0
+#define DVC_VLUT_31_WORD_COUNT                  0x1
+#define DVC_VLUT_31_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_31_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_31_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_31_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_31_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_31_PMCNT_SHIFT)
+#define DVC_VLUT_31_PMCNT_RANGE                 23:10
+#define DVC_VLUT_31_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_31_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_31_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_31_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_31_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_31_VMIN_SHIFT)
+#define DVC_VLUT_31_VMIN_RANGE                  9:5
+#define DVC_VLUT_31_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_31_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_31_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_31_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_31_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_31_VMAX_SHIFT)
+#define DVC_VLUT_31_VMAX_RANGE                  4:0
+#define DVC_VLUT_31_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_31_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_31_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_31_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_32  
+#define DVC_VLUT_32                     _MK_ADDR_CONST(0x180)
+#define DVC_VLUT_32_SECURE                      0x0
+#define DVC_VLUT_32_WORD_COUNT                  0x1
+#define DVC_VLUT_32_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_32_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_32_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_32_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_32_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_32_PMCNT_SHIFT)
+#define DVC_VLUT_32_PMCNT_RANGE                 23:10
+#define DVC_VLUT_32_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_32_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_32_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_32_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_32_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_32_VMIN_SHIFT)
+#define DVC_VLUT_32_VMIN_RANGE                  9:5
+#define DVC_VLUT_32_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_32_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_32_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_32_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_32_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_32_VMAX_SHIFT)
+#define DVC_VLUT_32_VMAX_RANGE                  4:0
+#define DVC_VLUT_32_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_32_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_32_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_32_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_33  
+#define DVC_VLUT_33                     _MK_ADDR_CONST(0x184)
+#define DVC_VLUT_33_SECURE                      0x0
+#define DVC_VLUT_33_WORD_COUNT                  0x1
+#define DVC_VLUT_33_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_33_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_33_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_33_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_33_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_33_PMCNT_SHIFT)
+#define DVC_VLUT_33_PMCNT_RANGE                 23:10
+#define DVC_VLUT_33_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_33_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_33_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_33_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_33_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_33_VMIN_SHIFT)
+#define DVC_VLUT_33_VMIN_RANGE                  9:5
+#define DVC_VLUT_33_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_33_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_33_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_33_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_33_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_33_VMAX_SHIFT)
+#define DVC_VLUT_33_VMAX_RANGE                  4:0
+#define DVC_VLUT_33_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_33_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_33_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_33_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_34  
+#define DVC_VLUT_34                     _MK_ADDR_CONST(0x188)
+#define DVC_VLUT_34_SECURE                      0x0
+#define DVC_VLUT_34_WORD_COUNT                  0x1
+#define DVC_VLUT_34_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_34_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_34_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_34_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_34_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_34_PMCNT_SHIFT)
+#define DVC_VLUT_34_PMCNT_RANGE                 23:10
+#define DVC_VLUT_34_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_34_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_34_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_34_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_34_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_34_VMIN_SHIFT)
+#define DVC_VLUT_34_VMIN_RANGE                  9:5
+#define DVC_VLUT_34_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_34_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_34_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_34_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_34_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_34_VMAX_SHIFT)
+#define DVC_VLUT_34_VMAX_RANGE                  4:0
+#define DVC_VLUT_34_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_34_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_34_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_34_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_35  
+#define DVC_VLUT_35                     _MK_ADDR_CONST(0x18c)
+#define DVC_VLUT_35_SECURE                      0x0
+#define DVC_VLUT_35_WORD_COUNT                  0x1
+#define DVC_VLUT_35_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_35_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_35_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_35_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_35_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_35_PMCNT_SHIFT)
+#define DVC_VLUT_35_PMCNT_RANGE                 23:10
+#define DVC_VLUT_35_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_35_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_35_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_35_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_35_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_35_VMIN_SHIFT)
+#define DVC_VLUT_35_VMIN_RANGE                  9:5
+#define DVC_VLUT_35_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_35_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_35_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_35_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_35_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_35_VMAX_SHIFT)
+#define DVC_VLUT_35_VMAX_RANGE                  4:0
+#define DVC_VLUT_35_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_35_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_35_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_35_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_36  
+#define DVC_VLUT_36                     _MK_ADDR_CONST(0x190)
+#define DVC_VLUT_36_SECURE                      0x0
+#define DVC_VLUT_36_WORD_COUNT                  0x1
+#define DVC_VLUT_36_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_36_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_36_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_36_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_36_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_36_PMCNT_SHIFT)
+#define DVC_VLUT_36_PMCNT_RANGE                 23:10
+#define DVC_VLUT_36_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_36_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_36_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_36_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_36_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_36_VMIN_SHIFT)
+#define DVC_VLUT_36_VMIN_RANGE                  9:5
+#define DVC_VLUT_36_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_36_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_36_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_36_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_36_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_36_VMAX_SHIFT)
+#define DVC_VLUT_36_VMAX_RANGE                  4:0
+#define DVC_VLUT_36_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_36_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_36_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_36_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_37  
+#define DVC_VLUT_37                     _MK_ADDR_CONST(0x194)
+#define DVC_VLUT_37_SECURE                      0x0
+#define DVC_VLUT_37_WORD_COUNT                  0x1
+#define DVC_VLUT_37_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_37_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_37_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_37_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_37_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_37_PMCNT_SHIFT)
+#define DVC_VLUT_37_PMCNT_RANGE                 23:10
+#define DVC_VLUT_37_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_37_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_37_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_37_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_37_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_37_VMIN_SHIFT)
+#define DVC_VLUT_37_VMIN_RANGE                  9:5
+#define DVC_VLUT_37_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_37_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_37_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_37_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_37_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_37_VMAX_SHIFT)
+#define DVC_VLUT_37_VMAX_RANGE                  4:0
+#define DVC_VLUT_37_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_37_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_37_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_37_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_38  
+#define DVC_VLUT_38                     _MK_ADDR_CONST(0x198)
+#define DVC_VLUT_38_SECURE                      0x0
+#define DVC_VLUT_38_WORD_COUNT                  0x1
+#define DVC_VLUT_38_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_38_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_38_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_38_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_38_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_38_PMCNT_SHIFT)
+#define DVC_VLUT_38_PMCNT_RANGE                 23:10
+#define DVC_VLUT_38_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_38_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_38_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_38_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_38_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_38_VMIN_SHIFT)
+#define DVC_VLUT_38_VMIN_RANGE                  9:5
+#define DVC_VLUT_38_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_38_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_38_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_38_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_38_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_38_VMAX_SHIFT)
+#define DVC_VLUT_38_VMAX_RANGE                  4:0
+#define DVC_VLUT_38_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_38_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_38_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_38_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_39  
+#define DVC_VLUT_39                     _MK_ADDR_CONST(0x19c)
+#define DVC_VLUT_39_SECURE                      0x0
+#define DVC_VLUT_39_WORD_COUNT                  0x1
+#define DVC_VLUT_39_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_39_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_39_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_39_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_39_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_39_PMCNT_SHIFT)
+#define DVC_VLUT_39_PMCNT_RANGE                 23:10
+#define DVC_VLUT_39_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_39_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_39_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_39_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_39_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_39_VMIN_SHIFT)
+#define DVC_VLUT_39_VMIN_RANGE                  9:5
+#define DVC_VLUT_39_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_39_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_39_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_39_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_39_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_39_VMAX_SHIFT)
+#define DVC_VLUT_39_VMAX_RANGE                  4:0
+#define DVC_VLUT_39_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_39_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_39_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_39_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_40  
+#define DVC_VLUT_40                     _MK_ADDR_CONST(0x1a0)
+#define DVC_VLUT_40_SECURE                      0x0
+#define DVC_VLUT_40_WORD_COUNT                  0x1
+#define DVC_VLUT_40_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_40_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_40_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_40_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_40_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_40_PMCNT_SHIFT)
+#define DVC_VLUT_40_PMCNT_RANGE                 23:10
+#define DVC_VLUT_40_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_40_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_40_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_40_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_40_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_40_VMIN_SHIFT)
+#define DVC_VLUT_40_VMIN_RANGE                  9:5
+#define DVC_VLUT_40_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_40_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_40_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_40_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_40_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_40_VMAX_SHIFT)
+#define DVC_VLUT_40_VMAX_RANGE                  4:0
+#define DVC_VLUT_40_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_40_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_40_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_40_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_41  
+#define DVC_VLUT_41                     _MK_ADDR_CONST(0x1a4)
+#define DVC_VLUT_41_SECURE                      0x0
+#define DVC_VLUT_41_WORD_COUNT                  0x1
+#define DVC_VLUT_41_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_41_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_41_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_41_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_41_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_41_PMCNT_SHIFT)
+#define DVC_VLUT_41_PMCNT_RANGE                 23:10
+#define DVC_VLUT_41_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_41_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_41_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_41_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_41_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_41_VMIN_SHIFT)
+#define DVC_VLUT_41_VMIN_RANGE                  9:5
+#define DVC_VLUT_41_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_41_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_41_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_41_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_41_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_41_VMAX_SHIFT)
+#define DVC_VLUT_41_VMAX_RANGE                  4:0
+#define DVC_VLUT_41_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_41_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_41_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_41_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_42  
+#define DVC_VLUT_42                     _MK_ADDR_CONST(0x1a8)
+#define DVC_VLUT_42_SECURE                      0x0
+#define DVC_VLUT_42_WORD_COUNT                  0x1
+#define DVC_VLUT_42_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_42_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_42_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_42_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_42_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_42_PMCNT_SHIFT)
+#define DVC_VLUT_42_PMCNT_RANGE                 23:10
+#define DVC_VLUT_42_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_42_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_42_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_42_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_42_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_42_VMIN_SHIFT)
+#define DVC_VLUT_42_VMIN_RANGE                  9:5
+#define DVC_VLUT_42_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_42_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_42_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_42_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_42_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_42_VMAX_SHIFT)
+#define DVC_VLUT_42_VMAX_RANGE                  4:0
+#define DVC_VLUT_42_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_42_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_42_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_42_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_43  
+#define DVC_VLUT_43                     _MK_ADDR_CONST(0x1ac)
+#define DVC_VLUT_43_SECURE                      0x0
+#define DVC_VLUT_43_WORD_COUNT                  0x1
+#define DVC_VLUT_43_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_43_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_43_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_43_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_43_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_43_PMCNT_SHIFT)
+#define DVC_VLUT_43_PMCNT_RANGE                 23:10
+#define DVC_VLUT_43_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_43_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_43_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_43_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_43_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_43_VMIN_SHIFT)
+#define DVC_VLUT_43_VMIN_RANGE                  9:5
+#define DVC_VLUT_43_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_43_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_43_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_43_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_43_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_43_VMAX_SHIFT)
+#define DVC_VLUT_43_VMAX_RANGE                  4:0
+#define DVC_VLUT_43_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_43_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_43_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_43_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_44  
+#define DVC_VLUT_44                     _MK_ADDR_CONST(0x1b0)
+#define DVC_VLUT_44_SECURE                      0x0
+#define DVC_VLUT_44_WORD_COUNT                  0x1
+#define DVC_VLUT_44_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_44_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_44_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_44_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_44_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_44_PMCNT_SHIFT)
+#define DVC_VLUT_44_PMCNT_RANGE                 23:10
+#define DVC_VLUT_44_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_44_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_44_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_44_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_44_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_44_VMIN_SHIFT)
+#define DVC_VLUT_44_VMIN_RANGE                  9:5
+#define DVC_VLUT_44_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_44_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_44_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_44_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_44_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_44_VMAX_SHIFT)
+#define DVC_VLUT_44_VMAX_RANGE                  4:0
+#define DVC_VLUT_44_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_44_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_44_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_44_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_45  
+#define DVC_VLUT_45                     _MK_ADDR_CONST(0x1b4)
+#define DVC_VLUT_45_SECURE                      0x0
+#define DVC_VLUT_45_WORD_COUNT                  0x1
+#define DVC_VLUT_45_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_45_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_45_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_45_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_45_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_45_PMCNT_SHIFT)
+#define DVC_VLUT_45_PMCNT_RANGE                 23:10
+#define DVC_VLUT_45_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_45_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_45_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_45_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_45_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_45_VMIN_SHIFT)
+#define DVC_VLUT_45_VMIN_RANGE                  9:5
+#define DVC_VLUT_45_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_45_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_45_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_45_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_45_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_45_VMAX_SHIFT)
+#define DVC_VLUT_45_VMAX_RANGE                  4:0
+#define DVC_VLUT_45_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_45_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_45_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_45_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_46  
+#define DVC_VLUT_46                     _MK_ADDR_CONST(0x1b8)
+#define DVC_VLUT_46_SECURE                      0x0
+#define DVC_VLUT_46_WORD_COUNT                  0x1
+#define DVC_VLUT_46_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_46_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_46_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_46_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_46_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_46_PMCNT_SHIFT)
+#define DVC_VLUT_46_PMCNT_RANGE                 23:10
+#define DVC_VLUT_46_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_46_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_46_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_46_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_46_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_46_VMIN_SHIFT)
+#define DVC_VLUT_46_VMIN_RANGE                  9:5
+#define DVC_VLUT_46_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_46_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_46_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_46_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_46_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_46_VMAX_SHIFT)
+#define DVC_VLUT_46_VMAX_RANGE                  4:0
+#define DVC_VLUT_46_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_46_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_46_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_46_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_47  
+#define DVC_VLUT_47                     _MK_ADDR_CONST(0x1bc)
+#define DVC_VLUT_47_SECURE                      0x0
+#define DVC_VLUT_47_WORD_COUNT                  0x1
+#define DVC_VLUT_47_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_47_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_47_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_47_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_47_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_47_PMCNT_SHIFT)
+#define DVC_VLUT_47_PMCNT_RANGE                 23:10
+#define DVC_VLUT_47_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_47_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_47_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_47_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_47_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_47_VMIN_SHIFT)
+#define DVC_VLUT_47_VMIN_RANGE                  9:5
+#define DVC_VLUT_47_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_47_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_47_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_47_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_47_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_47_VMAX_SHIFT)
+#define DVC_VLUT_47_VMAX_RANGE                  4:0
+#define DVC_VLUT_47_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_47_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_47_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_47_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_48  
+#define DVC_VLUT_48                     _MK_ADDR_CONST(0x1c0)
+#define DVC_VLUT_48_SECURE                      0x0
+#define DVC_VLUT_48_WORD_COUNT                  0x1
+#define DVC_VLUT_48_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_48_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_48_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_48_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_48_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_48_PMCNT_SHIFT)
+#define DVC_VLUT_48_PMCNT_RANGE                 23:10
+#define DVC_VLUT_48_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_48_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_48_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_48_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_48_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_48_VMIN_SHIFT)
+#define DVC_VLUT_48_VMIN_RANGE                  9:5
+#define DVC_VLUT_48_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_48_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_48_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_48_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_48_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_48_VMAX_SHIFT)
+#define DVC_VLUT_48_VMAX_RANGE                  4:0
+#define DVC_VLUT_48_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_48_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_48_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_48_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_49  
+#define DVC_VLUT_49                     _MK_ADDR_CONST(0x1c4)
+#define DVC_VLUT_49_SECURE                      0x0
+#define DVC_VLUT_49_WORD_COUNT                  0x1
+#define DVC_VLUT_49_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_49_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_49_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_49_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_49_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_49_PMCNT_SHIFT)
+#define DVC_VLUT_49_PMCNT_RANGE                 23:10
+#define DVC_VLUT_49_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_49_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_49_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_49_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_49_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_49_VMIN_SHIFT)
+#define DVC_VLUT_49_VMIN_RANGE                  9:5
+#define DVC_VLUT_49_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_49_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_49_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_49_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_49_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_49_VMAX_SHIFT)
+#define DVC_VLUT_49_VMAX_RANGE                  4:0
+#define DVC_VLUT_49_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_49_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_49_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_49_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_50  
+#define DVC_VLUT_50                     _MK_ADDR_CONST(0x1c8)
+#define DVC_VLUT_50_SECURE                      0x0
+#define DVC_VLUT_50_WORD_COUNT                  0x1
+#define DVC_VLUT_50_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_50_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_50_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_50_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_50_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_50_PMCNT_SHIFT)
+#define DVC_VLUT_50_PMCNT_RANGE                 23:10
+#define DVC_VLUT_50_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_50_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_50_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_50_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_50_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_50_VMIN_SHIFT)
+#define DVC_VLUT_50_VMIN_RANGE                  9:5
+#define DVC_VLUT_50_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_50_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_50_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_50_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_50_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_50_VMAX_SHIFT)
+#define DVC_VLUT_50_VMAX_RANGE                  4:0
+#define DVC_VLUT_50_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_50_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_50_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_50_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_51  
+#define DVC_VLUT_51                     _MK_ADDR_CONST(0x1cc)
+#define DVC_VLUT_51_SECURE                      0x0
+#define DVC_VLUT_51_WORD_COUNT                  0x1
+#define DVC_VLUT_51_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_51_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_51_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_51_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_51_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_51_PMCNT_SHIFT)
+#define DVC_VLUT_51_PMCNT_RANGE                 23:10
+#define DVC_VLUT_51_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_51_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_51_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_51_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_51_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_51_VMIN_SHIFT)
+#define DVC_VLUT_51_VMIN_RANGE                  9:5
+#define DVC_VLUT_51_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_51_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_51_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_51_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_51_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_51_VMAX_SHIFT)
+#define DVC_VLUT_51_VMAX_RANGE                  4:0
+#define DVC_VLUT_51_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_51_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_51_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_51_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_52  
+#define DVC_VLUT_52                     _MK_ADDR_CONST(0x1d0)
+#define DVC_VLUT_52_SECURE                      0x0
+#define DVC_VLUT_52_WORD_COUNT                  0x1
+#define DVC_VLUT_52_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_52_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_52_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_52_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_52_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_52_PMCNT_SHIFT)
+#define DVC_VLUT_52_PMCNT_RANGE                 23:10
+#define DVC_VLUT_52_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_52_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_52_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_52_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_52_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_52_VMIN_SHIFT)
+#define DVC_VLUT_52_VMIN_RANGE                  9:5
+#define DVC_VLUT_52_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_52_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_52_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_52_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_52_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_52_VMAX_SHIFT)
+#define DVC_VLUT_52_VMAX_RANGE                  4:0
+#define DVC_VLUT_52_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_52_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_52_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_52_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_53  
+#define DVC_VLUT_53                     _MK_ADDR_CONST(0x1d4)
+#define DVC_VLUT_53_SECURE                      0x0
+#define DVC_VLUT_53_WORD_COUNT                  0x1
+#define DVC_VLUT_53_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_53_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_53_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_53_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_53_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_53_PMCNT_SHIFT)
+#define DVC_VLUT_53_PMCNT_RANGE                 23:10
+#define DVC_VLUT_53_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_53_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_53_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_53_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_53_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_53_VMIN_SHIFT)
+#define DVC_VLUT_53_VMIN_RANGE                  9:5
+#define DVC_VLUT_53_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_53_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_53_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_53_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_53_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_53_VMAX_SHIFT)
+#define DVC_VLUT_53_VMAX_RANGE                  4:0
+#define DVC_VLUT_53_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_53_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_53_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_53_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_54  
+#define DVC_VLUT_54                     _MK_ADDR_CONST(0x1d8)
+#define DVC_VLUT_54_SECURE                      0x0
+#define DVC_VLUT_54_WORD_COUNT                  0x1
+#define DVC_VLUT_54_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_54_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_54_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_54_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_54_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_54_PMCNT_SHIFT)
+#define DVC_VLUT_54_PMCNT_RANGE                 23:10
+#define DVC_VLUT_54_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_54_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_54_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_54_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_54_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_54_VMIN_SHIFT)
+#define DVC_VLUT_54_VMIN_RANGE                  9:5
+#define DVC_VLUT_54_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_54_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_54_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_54_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_54_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_54_VMAX_SHIFT)
+#define DVC_VLUT_54_VMAX_RANGE                  4:0
+#define DVC_VLUT_54_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_54_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_54_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_54_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_55  
+#define DVC_VLUT_55                     _MK_ADDR_CONST(0x1dc)
+#define DVC_VLUT_55_SECURE                      0x0
+#define DVC_VLUT_55_WORD_COUNT                  0x1
+#define DVC_VLUT_55_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_55_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_55_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_55_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_55_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_55_PMCNT_SHIFT)
+#define DVC_VLUT_55_PMCNT_RANGE                 23:10
+#define DVC_VLUT_55_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_55_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_55_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_55_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_55_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_55_VMIN_SHIFT)
+#define DVC_VLUT_55_VMIN_RANGE                  9:5
+#define DVC_VLUT_55_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_55_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_55_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_55_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_55_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_55_VMAX_SHIFT)
+#define DVC_VLUT_55_VMAX_RANGE                  4:0
+#define DVC_VLUT_55_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_55_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_55_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_55_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_56  
+#define DVC_VLUT_56                     _MK_ADDR_CONST(0x1e0)
+#define DVC_VLUT_56_SECURE                      0x0
+#define DVC_VLUT_56_WORD_COUNT                  0x1
+#define DVC_VLUT_56_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_56_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_56_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_56_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_56_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_56_PMCNT_SHIFT)
+#define DVC_VLUT_56_PMCNT_RANGE                 23:10
+#define DVC_VLUT_56_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_56_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_56_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_56_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_56_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_56_VMIN_SHIFT)
+#define DVC_VLUT_56_VMIN_RANGE                  9:5
+#define DVC_VLUT_56_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_56_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_56_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_56_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_56_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_56_VMAX_SHIFT)
+#define DVC_VLUT_56_VMAX_RANGE                  4:0
+#define DVC_VLUT_56_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_56_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_56_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_56_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_57  
+#define DVC_VLUT_57                     _MK_ADDR_CONST(0x1e4)
+#define DVC_VLUT_57_SECURE                      0x0
+#define DVC_VLUT_57_WORD_COUNT                  0x1
+#define DVC_VLUT_57_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_57_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_57_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_57_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_57_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_57_PMCNT_SHIFT)
+#define DVC_VLUT_57_PMCNT_RANGE                 23:10
+#define DVC_VLUT_57_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_57_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_57_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_57_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_57_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_57_VMIN_SHIFT)
+#define DVC_VLUT_57_VMIN_RANGE                  9:5
+#define DVC_VLUT_57_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_57_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_57_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_57_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_57_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_57_VMAX_SHIFT)
+#define DVC_VLUT_57_VMAX_RANGE                  4:0
+#define DVC_VLUT_57_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_57_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_57_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_57_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_58  
+#define DVC_VLUT_58                     _MK_ADDR_CONST(0x1e8)
+#define DVC_VLUT_58_SECURE                      0x0
+#define DVC_VLUT_58_WORD_COUNT                  0x1
+#define DVC_VLUT_58_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_58_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_58_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_58_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_58_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_58_PMCNT_SHIFT)
+#define DVC_VLUT_58_PMCNT_RANGE                 23:10
+#define DVC_VLUT_58_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_58_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_58_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_58_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_58_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_58_VMIN_SHIFT)
+#define DVC_VLUT_58_VMIN_RANGE                  9:5
+#define DVC_VLUT_58_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_58_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_58_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_58_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_58_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_58_VMAX_SHIFT)
+#define DVC_VLUT_58_VMAX_RANGE                  4:0
+#define DVC_VLUT_58_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_58_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_58_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_58_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_59  
+#define DVC_VLUT_59                     _MK_ADDR_CONST(0x1ec)
+#define DVC_VLUT_59_SECURE                      0x0
+#define DVC_VLUT_59_WORD_COUNT                  0x1
+#define DVC_VLUT_59_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_59_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_59_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_59_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_59_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_59_PMCNT_SHIFT)
+#define DVC_VLUT_59_PMCNT_RANGE                 23:10
+#define DVC_VLUT_59_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_59_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_59_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_59_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_59_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_59_VMIN_SHIFT)
+#define DVC_VLUT_59_VMIN_RANGE                  9:5
+#define DVC_VLUT_59_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_59_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_59_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_59_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_59_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_59_VMAX_SHIFT)
+#define DVC_VLUT_59_VMAX_RANGE                  4:0
+#define DVC_VLUT_59_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_59_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_59_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_59_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_60  
+#define DVC_VLUT_60                     _MK_ADDR_CONST(0x1f0)
+#define DVC_VLUT_60_SECURE                      0x0
+#define DVC_VLUT_60_WORD_COUNT                  0x1
+#define DVC_VLUT_60_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_60_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_60_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_60_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_60_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_60_PMCNT_SHIFT)
+#define DVC_VLUT_60_PMCNT_RANGE                 23:10
+#define DVC_VLUT_60_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_60_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_60_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_60_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_60_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_60_VMIN_SHIFT)
+#define DVC_VLUT_60_VMIN_RANGE                  9:5
+#define DVC_VLUT_60_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_60_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_60_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_60_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_60_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_60_VMAX_SHIFT)
+#define DVC_VLUT_60_VMAX_RANGE                  4:0
+#define DVC_VLUT_60_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_60_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_60_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_60_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_61  
+#define DVC_VLUT_61                     _MK_ADDR_CONST(0x1f4)
+#define DVC_VLUT_61_SECURE                      0x0
+#define DVC_VLUT_61_WORD_COUNT                  0x1
+#define DVC_VLUT_61_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_61_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_61_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_61_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_61_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_61_PMCNT_SHIFT)
+#define DVC_VLUT_61_PMCNT_RANGE                 23:10
+#define DVC_VLUT_61_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_61_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_61_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_61_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_61_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_61_VMIN_SHIFT)
+#define DVC_VLUT_61_VMIN_RANGE                  9:5
+#define DVC_VLUT_61_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_61_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_61_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_61_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_61_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_61_VMAX_SHIFT)
+#define DVC_VLUT_61_VMAX_RANGE                  4:0
+#define DVC_VLUT_61_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_61_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_61_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_61_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_62  
+#define DVC_VLUT_62                     _MK_ADDR_CONST(0x1f8)
+#define DVC_VLUT_62_SECURE                      0x0
+#define DVC_VLUT_62_WORD_COUNT                  0x1
+#define DVC_VLUT_62_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_62_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_62_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_62_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_62_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_62_PMCNT_SHIFT)
+#define DVC_VLUT_62_PMCNT_RANGE                 23:10
+#define DVC_VLUT_62_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_62_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_62_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_62_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_62_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_62_VMIN_SHIFT)
+#define DVC_VLUT_62_VMIN_RANGE                  9:5
+#define DVC_VLUT_62_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_62_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_62_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_62_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_62_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_62_VMAX_SHIFT)
+#define DVC_VLUT_62_VMAX_RANGE                  4:0
+#define DVC_VLUT_62_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_62_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_62_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_62_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Ram DVC_VLUT_63  
+#define DVC_VLUT_63                     _MK_ADDR_CONST(0x1fc)
+#define DVC_VLUT_63_SECURE                      0x0
+#define DVC_VLUT_63_WORD_COUNT                  0x1
+#define DVC_VLUT_63_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_63_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define DVC_VLUT_63_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+// Target performance count
+#define DVC_VLUT_63_PMCNT_SHIFT                 _MK_SHIFT_CONST(10)
+#define DVC_VLUT_63_PMCNT_FIELD                 (_MK_MASK_CONST(0x3fff) << DVC_VLUT_63_PMCNT_SHIFT)
+#define DVC_VLUT_63_PMCNT_RANGE                 23:10
+#define DVC_VLUT_63_PMCNT_WOFFSET                       0x0
+#define DVC_VLUT_63_PMCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_PMCNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define DVC_VLUT_63_PMCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_PMCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minimum voltage selection value for a given  frequency
+#define DVC_VLUT_63_VMIN_SHIFT                  _MK_SHIFT_CONST(5)
+#define DVC_VLUT_63_VMIN_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_63_VMIN_SHIFT)
+#define DVC_VLUT_63_VMIN_RANGE                  9:5
+#define DVC_VLUT_63_VMIN_WOFFSET                        0x0
+#define DVC_VLUT_63_VMIN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_VMIN_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_63_VMIN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_VMIN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum voltage selection value for a given  frequency
+#define DVC_VLUT_63_VMAX_SHIFT                  _MK_SHIFT_CONST(0)
+#define DVC_VLUT_63_VMAX_FIELD                  (_MK_MASK_CONST(0x1f) << DVC_VLUT_63_VMAX_SHIFT)
+#define DVC_VLUT_63_VMAX_RANGE                  4:0
+#define DVC_VLUT_63_VMAX_WOFFSET                        0x0
+#define DVC_VLUT_63_VMAX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_VMAX_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define DVC_VLUT_63_VMAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define DVC_VLUT_63_VMAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARDVC_REGS(_op_) \
+_op_(DVC_CTRL_REG1_0) \
+_op_(DVC_CTRL_REG2_0) \
+_op_(DVC_CTRL_REG3_0) \
+_op_(DVC_STATUS_REG_0) \
+_op_(DVC_I2C_CTRL_REG_0) \
+_op_(DVC_I2C_ADDR_DATA_REG_0) \
+_op_(DVC_RING_OSC_ADDER_IN1_0) \
+_op_(DVC_RING_OSC_ADDER_IN2_0) \
+_op_(DVC_REQ_REGISTER_0) \
+_op_(DVC_I2C_ADDR_DATA_REG_3_0) \
+_op_(DVC_I2C_CNFG_0) \
+_op_(DVC_I2C_CMD_ADDR0_0) \
+_op_(DVC_I2C_CMD_ADDR1_0) \
+_op_(DVC_I2C_CMD_DATA1_0) \
+_op_(DVC_I2C_CMD_DATA2_0) \
+_op_(DVC_I2C_STATUS_0) \
+_op_(DVC_I2C_TX_PACKET_FIFO_0) \
+_op_(DVC_I2C_RX_FIFO_0) \
+_op_(DVC_PACKET_TRANSFER_STATUS_0) \
+_op_(DVC_FIFO_CONTROL_0) \
+_op_(DVC_FIFO_STATUS_0) \
+_op_(DVC_INTERRUPT_MASK_REGISTER_0) \
+_op_(DVC_INTERRUPT_STATUS_REGISTER_0) \
+_op_(DVC_I2C_CLK_DIVISOR_REGISTER_0) \
+_op_(DVC_VSEL_MAP_LUT_0) \
+_op_(DVC_VSEL_MAP_LUT) \
+_op_(DVC_VSEL_MAP_LUT_1) \
+_op_(DVC_VSEL_MAP_LUT_2) \
+_op_(DVC_VSEL_MAP_LUT_3) \
+_op_(DVC_VSEL_MAP_LUT_4) \
+_op_(DVC_VSEL_MAP_LUT_5) \
+_op_(DVC_VSEL_MAP_LUT_6) \
+_op_(DVC_VSEL_MAP_LUT_7) \
+_op_(DVC_VSEL_MAP_LUT_8) \
+_op_(DVC_VSEL_MAP_LUT_9) \
+_op_(DVC_VSEL_MAP_LUT_10) \
+_op_(DVC_VSEL_MAP_LUT_11) \
+_op_(DVC_VSEL_MAP_LUT_12) \
+_op_(DVC_VSEL_MAP_LUT_13) \
+_op_(DVC_VSEL_MAP_LUT_14) \
+_op_(DVC_VSEL_MAP_LUT_15) \
+_op_(DVC_VSEL_MAP_LUT_16) \
+_op_(DVC_VSEL_MAP_LUT_17) \
+_op_(DVC_VSEL_MAP_LUT_18) \
+_op_(DVC_VSEL_MAP_LUT_19) \
+_op_(DVC_VSEL_MAP_LUT_20) \
+_op_(DVC_VSEL_MAP_LUT_21) \
+_op_(DVC_VSEL_MAP_LUT_22) \
+_op_(DVC_VSEL_MAP_LUT_23) \
+_op_(DVC_VSEL_MAP_LUT_24) \
+_op_(DVC_VSEL_MAP_LUT_25) \
+_op_(DVC_VSEL_MAP_LUT_26) \
+_op_(DVC_VSEL_MAP_LUT_27) \
+_op_(DVC_VSEL_MAP_LUT_28) \
+_op_(DVC_VSEL_MAP_LUT_29) \
+_op_(DVC_VSEL_MAP_LUT_30) \
+_op_(DVC_VSEL_MAP_LUT_31) \
+_op_(DVC_VLUT_0) \
+_op_(DVC_VLUT) \
+_op_(DVC_VLUT_1) \
+_op_(DVC_VLUT_2) \
+_op_(DVC_VLUT_3) \
+_op_(DVC_VLUT_4) \
+_op_(DVC_VLUT_5) \
+_op_(DVC_VLUT_6) \
+_op_(DVC_VLUT_7) \
+_op_(DVC_VLUT_8) \
+_op_(DVC_VLUT_9) \
+_op_(DVC_VLUT_10) \
+_op_(DVC_VLUT_11) \
+_op_(DVC_VLUT_12) \
+_op_(DVC_VLUT_13) \
+_op_(DVC_VLUT_14) \
+_op_(DVC_VLUT_15) \
+_op_(DVC_VLUT_16) \
+_op_(DVC_VLUT_17) \
+_op_(DVC_VLUT_18) \
+_op_(DVC_VLUT_19) \
+_op_(DVC_VLUT_20) \
+_op_(DVC_VLUT_21) \
+_op_(DVC_VLUT_22) \
+_op_(DVC_VLUT_23) \
+_op_(DVC_VLUT_24) \
+_op_(DVC_VLUT_25) \
+_op_(DVC_VLUT_26) \
+_op_(DVC_VLUT_27) \
+_op_(DVC_VLUT_28) \
+_op_(DVC_VLUT_29) \
+_op_(DVC_VLUT_30) \
+_op_(DVC_VLUT_31) \
+_op_(DVC_VLUT_32) \
+_op_(DVC_VLUT_33) \
+_op_(DVC_VLUT_34) \
+_op_(DVC_VLUT_35) \
+_op_(DVC_VLUT_36) \
+_op_(DVC_VLUT_37) \
+_op_(DVC_VLUT_38) \
+_op_(DVC_VLUT_39) \
+_op_(DVC_VLUT_40) \
+_op_(DVC_VLUT_41) \
+_op_(DVC_VLUT_42) \
+_op_(DVC_VLUT_43) \
+_op_(DVC_VLUT_44) \
+_op_(DVC_VLUT_45) \
+_op_(DVC_VLUT_46) \
+_op_(DVC_VLUT_47) \
+_op_(DVC_VLUT_48) \
+_op_(DVC_VLUT_49) \
+_op_(DVC_VLUT_50) \
+_op_(DVC_VLUT_51) \
+_op_(DVC_VLUT_52) \
+_op_(DVC_VLUT_53) \
+_op_(DVC_VLUT_54) \
+_op_(DVC_VLUT_55) \
+_op_(DVC_VLUT_56) \
+_op_(DVC_VLUT_57) \
+_op_(DVC_VLUT_58) \
+_op_(DVC_VLUT_59) \
+_op_(DVC_VLUT_60) \
+_op_(DVC_VLUT_61) \
+_op_(DVC_VLUT_62) \
+_op_(DVC_VLUT_63)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_DVC        0x00000000
+
+//
+// ARDVC REGISTER BANKS
+//
+
+#define DVC0_FIRST_REG 0x0000 // DVC_CTRL_REG1_0
+#define DVC0_LAST_REG 0x0024 // DVC_I2C_ADDR_DATA_REG_3_0
+#define DVC1_FIRST_REG 0x0040 // DVC_I2C_CNFG_0
+#define DVC1_LAST_REG 0x0050 // DVC_I2C_CMD_DATA2_0
+#define DVC2_FIRST_REG 0x005c // DVC_I2C_STATUS_0
+#define DVC2_LAST_REG 0x01fc // DVC_VLUT_63
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARDVC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/aremc.h b/arch/arm/mach-tegra/nv/include/ap20/aremc.h
new file mode 100644
index 000000000000..cc6d52b2e045
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/aremc.h
@@ -0,0 +1,7271 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___AREMC_H_INC_
+#define ___AREMC_H_INC_
+#define EMC_FBIO_DATA_MAX       31
+#define EMC_FBIO_DATA_WIDTH     32
+#define EMC_FBIO_DOE_MAX        3
+#define EMC_FBIO_DOE_WIDTH      4
+#define MAX_EMC_TIMING_WDV      15
+
+// Register EMC_INTSTATUS_0  // Interrupt Status Register.
+#define EMC_INTSTATUS_0                 _MK_ADDR_CONST(0x0)
+#define EMC_INTSTATUS_0_SECURE                  0x0
+#define EMC_INTSTATUS_0_WORD_COUNT                      0x1
+#define EMC_INTSTATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_RESET_MASK                      _MK_MASK_CONST(0x38)
+#define EMC_INTSTATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_READ_MASK                       _MK_MASK_CONST(0x38)
+#define EMC_INTSTATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x38)
+// Refresh request overflow timeout.
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_SHIFT                      _MK_SHIFT_CONST(3)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_FIELD                      (_MK_MASK_CONST(0x1) << EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_SHIFT)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_RANGE                      3:3
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_WOFFSET                    0x0
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_INIT_ENUM                  CLEAR
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_CLEAR                      _MK_ENUM_CONST(0)
+#define EMC_INTSTATUS_0_REFRESH_OVERFLOW_INT_SET                        _MK_ENUM_CONST(1)
+
+// CAR/EMC clock-change handshake complete.
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_SHIFT                    _MK_SHIFT_CONST(4)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_FIELD                    (_MK_MASK_CONST(0x1) << EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_SHIFT)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_RANGE                    4:4
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_WOFFSET                  0x0
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_INIT_ENUM                        CLEAR
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_CLEAR                    _MK_ENUM_CONST(0)
+#define EMC_INTSTATUS_0_CLKCHANGE_COMPLETE_INT_SET                      _MK_ENUM_CONST(1)
+
+// LPDDR2 MRR data is available to be read.
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_SHIFT                     _MK_SHIFT_CONST(5)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_FIELD                     (_MK_MASK_CONST(0x1) << EMC_INTSTATUS_0_MRR_DIVLD_INT_SHIFT)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_RANGE                     5:5
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_WOFFSET                   0x0
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_INIT_ENUM                 CLEAR
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_CLEAR                     _MK_ENUM_CONST(0)
+#define EMC_INTSTATUS_0_MRR_DIVLD_INT_SET                       _MK_ENUM_CONST(1)
+
+
+// Register EMC_INTMASK_0  // Interrupt Mask Register. 
+#define EMC_INTMASK_0                   _MK_ADDR_CONST(0x4)
+#define EMC_INTMASK_0_SECURE                    0x0
+#define EMC_INTMASK_0_WORD_COUNT                        0x1
+#define EMC_INTMASK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_RESET_MASK                        _MK_MASK_CONST(0x38)
+#define EMC_INTMASK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_READ_MASK                         _MK_MASK_CONST(0x38)
+#define EMC_INTMASK_0_WRITE_MASK                        _MK_MASK_CONST(0x38)
+// Mask for refresh request overflow timeout.
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_SHIFT                    _MK_SHIFT_CONST(3)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_FIELD                    (_MK_MASK_CONST(0x1) << EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_SHIFT)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_RANGE                    3:3
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_WOFFSET                  0x0
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_INIT_ENUM                        MASKED
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_MASKED                   _MK_ENUM_CONST(0)
+#define EMC_INTMASK_0_REFRESH_OVERFLOW_INTMASK_UNMASKED                 _MK_ENUM_CONST(1)
+
+// Mask for CAR/EMC clock-change handshake complete.
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_SHIFT                  _MK_SHIFT_CONST(4)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_FIELD                  (_MK_MASK_CONST(0x1) << EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_SHIFT)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_RANGE                  4:4
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_WOFFSET                        0x0
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_INIT_ENUM                      MASKED
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_MASKED                 _MK_ENUM_CONST(0)
+#define EMC_INTMASK_0_CLKCHANGE_COMPLETE_INTMASK_UNMASKED                       _MK_ENUM_CONST(1)
+
+// Mask for MRR data available.
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_SHIFT                   _MK_SHIFT_CONST(5)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_FIELD                   (_MK_MASK_CONST(0x1) << EMC_INTMASK_0_MRR_DIVLD_INTMASK_SHIFT)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_RANGE                   5:5
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_WOFFSET                 0x0
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_INIT_ENUM                       MASKED
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_MASKED                  _MK_ENUM_CONST(0)
+#define EMC_INTMASK_0_MRR_DIVLD_INTMASK_UNMASKED                        _MK_ENUM_CONST(1)
+
+
+// Register EMC_DBG_0  // Debug Register
+#define EMC_DBG_0                       _MK_ADDR_CONST(0x8)
+#define EMC_DBG_0_SECURE                        0x0
+#define EMC_DBG_0_WORD_COUNT                    0x1
+#define EMC_DBG_0_RESET_VAL                     _MK_MASK_CONST(0x1000400)
+#define EMC_DBG_0_RESET_MASK                    _MK_MASK_CONST(0x1000637)
+#define EMC_DBG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MASK                     _MK_MASK_CONST(0x1000637)
+#define EMC_DBG_0_WRITE_MASK                    _MK_MASK_CONST(0x1000637)
+// controls whether reads to the configuration registers are done from the assembly or active state.
+#define EMC_DBG_0_READ_MUX_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DBG_0_READ_MUX_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_READ_MUX_SHIFT)
+#define EMC_DBG_0_READ_MUX_RANGE                        0:0
+#define EMC_DBG_0_READ_MUX_WOFFSET                      0x0
+#define EMC_DBG_0_READ_MUX_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_READ_MUX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_MUX_INIT_ENUM                    ACTIVE
+#define EMC_DBG_0_READ_MUX_ACTIVE                       _MK_ENUM_CONST(0)
+#define EMC_DBG_0_READ_MUX_ASSEMBLY                     _MK_ENUM_CONST(1)
+
+// controls whether writes to the configuration registers are done from the assembly or active state.
+#define EMC_DBG_0_WRITE_MUX_SHIFT                       _MK_SHIFT_CONST(1)
+#define EMC_DBG_0_WRITE_MUX_FIELD                       (_MK_MASK_CONST(0x1) << EMC_DBG_0_WRITE_MUX_SHIFT)
+#define EMC_DBG_0_WRITE_MUX_RANGE                       1:1
+#define EMC_DBG_0_WRITE_MUX_WOFFSET                     0x0
+#define EMC_DBG_0_WRITE_MUX_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_WRITE_MUX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_WRITE_MUX_INIT_ENUM                   ASSEMBLY
+#define EMC_DBG_0_WRITE_MUX_ASSEMBLY                    _MK_ENUM_CONST(0)
+#define EMC_DBG_0_WRITE_MUX_ACTIVE                      _MK_ENUM_CONST(1)
+
+// causes the active state to get updated with the assembly state immediately upon writing the TIMING_CONTROL register.
+#define EMC_DBG_0_FORCE_UPDATE_SHIFT                    _MK_SHIFT_CONST(2)
+#define EMC_DBG_0_FORCE_UPDATE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DBG_0_FORCE_UPDATE_SHIFT)
+#define EMC_DBG_0_FORCE_UPDATE_RANGE                    2:2
+#define EMC_DBG_0_FORCE_UPDATE_WOFFSET                  0x0
+#define EMC_DBG_0_FORCE_UPDATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_FORCE_UPDATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_FORCE_UPDATE_INIT_ENUM                        DISABLED
+#define EMC_DBG_0_FORCE_UPDATE_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_FORCE_UPDATE_ENABLED                  _MK_ENUM_CONST(1)
+
+// should be set to MRS_256 when a non-mobile DRAM is used because they require a 200 cycle
+// delay between the DLL reset and any read commands.
+#define EMC_DBG_0_MRS_WAIT_SHIFT                        _MK_SHIFT_CONST(4)
+#define EMC_DBG_0_MRS_WAIT_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_MRS_WAIT_SHIFT)
+#define EMC_DBG_0_MRS_WAIT_RANGE                        4:4
+#define EMC_DBG_0_MRS_WAIT_WOFFSET                      0x0
+#define EMC_DBG_0_MRS_WAIT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_MRS_WAIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_MRS_WAIT_INIT_ENUM                    MRS_2
+#define EMC_DBG_0_MRS_WAIT_MRS_2                        _MK_ENUM_CONST(0)
+#define EMC_DBG_0_MRS_WAIT_MRS_256                      _MK_ENUM_CONST(1)
+
+// specifies whether or not to periodic reset the FBIO read-data fifo during normal operation.
+// The periodic resets can be used for graceful recovery from an intermittent failure condition;
+// only the initial reset is absolutely required.
+#define EMC_DBG_0_PERIODIC_QRST_SHIFT                   _MK_SHIFT_CONST(5)
+#define EMC_DBG_0_PERIODIC_QRST_FIELD                   (_MK_MASK_CONST(0x1) << EMC_DBG_0_PERIODIC_QRST_SHIFT)
+#define EMC_DBG_0_PERIODIC_QRST_RANGE                   5:5
+#define EMC_DBG_0_PERIODIC_QRST_WOFFSET                 0x0
+#define EMC_DBG_0_PERIODIC_QRST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_PERIODIC_QRST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_PERIODIC_QRST_INIT_ENUM                       DISABLED
+#define EMC_DBG_0_PERIODIC_QRST_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_DBG_0_PERIODIC_QRST_ENABLED                 _MK_ENUM_CONST(1)
+
+// controls whether the dqm signals during reads are managed for power (not relevant for DDR).
+// If set to MANAGED, EMC only turns them on when necessary.  If set to ALWAYS_ON, the dqm signals are
+// enabled during non-write operation.
+#define EMC_DBG_0_READ_DQM_CTRL_SHIFT                   _MK_SHIFT_CONST(9)
+#define EMC_DBG_0_READ_DQM_CTRL_FIELD                   (_MK_MASK_CONST(0x1) << EMC_DBG_0_READ_DQM_CTRL_SHIFT)
+#define EMC_DBG_0_READ_DQM_CTRL_RANGE                   9:9
+#define EMC_DBG_0_READ_DQM_CTRL_WOFFSET                 0x0
+#define EMC_DBG_0_READ_DQM_CTRL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_READ_DQM_CTRL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_READ_DQM_CTRL_INIT_ENUM                       MANAGED
+#define EMC_DBG_0_READ_DQM_CTRL_MANAGED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_READ_DQM_CTRL_ALWAYS_ON                       _MK_ENUM_CONST(1)
+
+// determines whether the busy signal from the auto-precharge cancellation (APC) fifo
+// is allowed to stall requests to the EMC.
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SHIFT                        _MK_SHIFT_CONST(10)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DBG_0_AP_REQ_BUSY_CTRL_SHIFT)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_RANGE                        10:10
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_WOFFSET                      0x0
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_INIT_ENUM                    ENABLED
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_DISABLED                     _MK_ENUM_CONST(0)
+#define EMC_DBG_0_AP_REQ_BUSY_CTRL_ENABLED                      _MK_ENUM_CONST(1)
+
+// determines the priority of cfg accesses to the DRAM.  Setting this register to ENABLED
+// gives DRAM config cycles (refresh, mrs, emrs, etc.) higher priority over real time requestors.
+// The DISABLED setting gives the real time requestors higher priority than DRAM config cycles.
+// Do not program to DISABLED unless for debugging.
+#define EMC_DBG_0_CFG_PRIORITY_SHIFT                    _MK_SHIFT_CONST(24)
+#define EMC_DBG_0_CFG_PRIORITY_FIELD                    (_MK_MASK_CONST(0x1) << EMC_DBG_0_CFG_PRIORITY_SHIFT)
+#define EMC_DBG_0_CFG_PRIORITY_RANGE                    24:24
+#define EMC_DBG_0_CFG_PRIORITY_WOFFSET                  0x0
+#define EMC_DBG_0_CFG_PRIORITY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_CFG_PRIORITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_DBG_0_CFG_PRIORITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_CFG_PRIORITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DBG_0_CFG_PRIORITY_INIT_ENUM                        ENABLED
+#define EMC_DBG_0_CFG_PRIORITY_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_DBG_0_CFG_PRIORITY_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_CFG_0  // Configuration Register
+#define EMC_CFG_0                       _MK_ADDR_CONST(0xc)
+#define EMC_CFG_0_SECURE                        0x0
+#define EMC_CFG_0_WORD_COUNT                    0x1
+#define EMC_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x300ff00)
+#define EMC_CFG_0_RESET_MASK                    _MK_MASK_CONST(0xe301ff01)
+#define EMC_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_READ_MASK                     _MK_MASK_CONST(0xe301ff01)
+#define EMC_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0xe301ff01)
+// preemptively closes all of the banks after the EMC has been idle for PRE_IDLE_CYCLES cycles and
+// there are banks open. PRE_IDLE_EN can be enabled if violating tRAS max is an issue.
+#define EMC_CFG_0_PRE_IDLE_EN_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_CFG_0_PRE_IDLE_EN_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_PRE_IDLE_EN_SHIFT)
+#define EMC_CFG_0_PRE_IDLE_EN_RANGE                     0:0
+#define EMC_CFG_0_PRE_IDLE_EN_WOFFSET                   0x0
+#define EMC_CFG_0_PRE_IDLE_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_PRE_IDLE_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_EN_INIT_ENUM                 DISABLED
+#define EMC_CFG_0_PRE_IDLE_EN_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_PRE_IDLE_EN_ENABLED                   _MK_ENUM_CONST(1)
+
+// cycles after which an idle bank may be closed. Note that 0 is an illegal setting for PRE_IDLE_CYCLES.
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_FIELD                 (_MK_MASK_CONST(0xff) << EMC_CFG_0_PRE_IDLE_CYCLES_SHIFT)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_RANGE                 15:8
+#define EMC_CFG_0_PRE_IDLE_CYCLES_WOFFSET                       0x0
+#define EMC_CFG_0_PRE_IDLE_CYCLES_DEFAULT                       _MK_MASK_CONST(0xff)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_PRE_IDLE_CYCLES_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// used to try to clear the auto-precharge bit on the previous request if the next request
+// is on the same page.  The previous request has to be in reach for this to happen.
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SHIFT)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_RANGE                     16:16
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_WOFFSET                   0x0
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_INIT_ENUM                 DISABLED
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_CLEAR_AP_PREV_SPREQ_ENABLED                   _MK_ENUM_CONST(1)
+
+// enable auto-precharge in the EMC for reads. This bits, when set to DISABLE, will override the settings in the MC
+// register. Otherwise, they permit clients to make auto-precharge requests as specified by the Memory Controller.
+#define EMC_CFG_0_AUTO_PRE_RD_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_CFG_0_AUTO_PRE_RD_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_AUTO_PRE_RD_SHIFT)
+#define EMC_CFG_0_AUTO_PRE_RD_RANGE                     24:24
+#define EMC_CFG_0_AUTO_PRE_RD_WOFFSET                   0x0
+#define EMC_CFG_0_AUTO_PRE_RD_DEFAULT                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_RD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_RD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_RD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_RD_INIT_ENUM                 ENABLED
+#define EMC_CFG_0_AUTO_PRE_RD_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_AUTO_PRE_RD_ENABLED                   _MK_ENUM_CONST(1)
+
+// enable auto-precharge in the EMC for writes. This bits, when set to DISABLE, will override the settings in the MC
+// register. Otherwise, they permit clients to make auto-precharge requests as specified by the Memory Controller.
+#define EMC_CFG_0_AUTO_PRE_WR_SHIFT                     _MK_SHIFT_CONST(25)
+#define EMC_CFG_0_AUTO_PRE_WR_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_0_AUTO_PRE_WR_SHIFT)
+#define EMC_CFG_0_AUTO_PRE_WR_RANGE                     25:25
+#define EMC_CFG_0_AUTO_PRE_WR_WOFFSET                   0x0
+#define EMC_CFG_0_AUTO_PRE_WR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_WR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_AUTO_PRE_WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_AUTO_PRE_WR_INIT_ENUM                 ENABLED
+#define EMC_CFG_0_AUTO_PRE_WR_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_0_AUTO_PRE_WR_ENABLED                   _MK_ENUM_CONST(1)
+
+// allows the DRAM controller to perform opportunistic active powerdown control using the CKE
+// pin on the DRAM. The behavior of the powerdown control logic is controlled by the PDEX2* and *2PDEN
+// registers. The value of DRAM_ACPD should only be changed when CKE is low, e.g., during software-controlled
+// self-refresh or before DRAM initialization.
+// If enabling ACPD, you should ALWAYS enable DRAM_CLKSTOP_PDSR_ONLY.
+// Not doing so will result in sub-optimal power-down & clockstop performance.  The powerdown conditions are
+// met within a couple of cycles after the clock has stopped, so the clock must be restarted & minimum clock
+// timings met before powerdown can be issued and clock restopped.
+#define EMC_CFG_0_DRAM_ACPD_SHIFT                       _MK_SHIFT_CONST(29)
+#define EMC_CFG_0_DRAM_ACPD_FIELD                       (_MK_MASK_CONST(0x1) << EMC_CFG_0_DRAM_ACPD_SHIFT)
+#define EMC_CFG_0_DRAM_ACPD_RANGE                       29:29
+#define EMC_CFG_0_DRAM_ACPD_WOFFSET                     0x0
+#define EMC_CFG_0_DRAM_ACPD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_DRAM_ACPD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_ACPD_INIT_ENUM                   NO_POWERDOWN
+#define EMC_CFG_0_DRAM_ACPD_NO_POWERDOWN                        _MK_ENUM_CONST(0)
+#define EMC_CFG_0_DRAM_ACPD_ACTIVE_POWERDOWN                    _MK_ENUM_CONST(1)
+
+// clockstop (if enabled) only allowed to happen if CKE=0 (for all CKE bits associated w/ clock)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_SHIFT                  _MK_SHIFT_CONST(30)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_FIELD                  (_MK_MASK_CONST(0x1) << EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_SHIFT)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_RANGE                  30:30
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_WOFFSET                        0x0
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_INIT_ENUM                      DISABLED
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_DISABLED                       _MK_ENUM_CONST(0)
+#define EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_ENABLED                        _MK_ENUM_CONST(1)
+
+// allows the DRAM controller to turn off the clock to the DRAM when it is safe to do so
+// (no operations are ongoing, and tRFC, tMRS, tRP, etc. have all been satisfied).
+#define EMC_CFG_0_DRAM_CLKSTOP_SHIFT                    _MK_SHIFT_CONST(31)
+#define EMC_CFG_0_DRAM_CLKSTOP_FIELD                    (_MK_MASK_CONST(0x1) << EMC_CFG_0_DRAM_CLKSTOP_SHIFT)
+#define EMC_CFG_0_DRAM_CLKSTOP_RANGE                    31:31
+#define EMC_CFG_0_DRAM_CLKSTOP_WOFFSET                  0x0
+#define EMC_CFG_0_DRAM_CLKSTOP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_CFG_0_DRAM_CLKSTOP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_0_DRAM_CLKSTOP_INIT_ENUM                        DISABLED
+#define EMC_CFG_0_DRAM_CLKSTOP_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_CFG_0_DRAM_CLKSTOP_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register EMC_ADR_CFG_0  // External memory address config Register
+#define EMC_ADR_CFG_0                   _MK_ADDR_CONST(0x10)
+#define EMC_ADR_CFG_0_SECURE                    0x0
+#define EMC_ADR_CFG_0_WORD_COUNT                        0x1
+#define EMC_ADR_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x40202)
+#define EMC_ADR_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x30f0307)
+#define EMC_ADR_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_READ_MASK                         _MK_MASK_CONST(0x30f0307)
+#define EMC_ADR_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x30f0307)
+// width of column address of the attached SDRAM device.
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_FIELD                       (_MK_MASK_CONST(0x7) << EMC_ADR_CFG_0_EMEM_COLWIDTH_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_RANGE                       2:0
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_WOFFSET                     0x0
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT                     _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_INIT_ENUM                   W9
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W7                  _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W8                  _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W9                  _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W10                 _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_0_EMEM_COLWIDTH_W11                 _MK_ENUM_CONST(4)
+
+// width of bank address of the attached SDRAM device.
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_FIELD                      (_MK_MASK_CONST(0x3) << EMC_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_RANGE                      9:8
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_WOFFSET                    0x0
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT                    _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_INIT_ENUM                  W2
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W1                 _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W2                 _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_BANKWIDTH_W3                 _MK_ENUM_CONST(3)
+
+// size of the attached SDRAM device used to generate width of row address.
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SHIFT                        _MK_SHIFT_CONST(16)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_FIELD                        (_MK_MASK_CONST(0xf) << EMC_ADR_CFG_0_EMEM_DEVSIZE_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_RANGE                        19:16
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_WOFFSET                      0x0
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT                      _MK_MASK_CONST(0x4)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_INIT_ENUM                    D64MB
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D4MB                 _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D8MB                 _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D16MB                        _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D32MB                        _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D64MB                        _MK_ENUM_CONST(4)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D128MB                       _MK_ENUM_CONST(5)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D256MB                       _MK_ENUM_CONST(6)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D512MB                       _MK_ENUM_CONST(7)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D1024MB                      _MK_ENUM_CONST(8)
+#define EMC_ADR_CFG_0_EMEM_DEVSIZE_D1GB                 _MK_ENUM_CONST(8)
+
+// the number of attached devices.
+// If more than one device is attached, the DEVSIZE, COLWIDTH, and BANKWIDTH configurations for the second device
+// will be defined by the fields in ADR_CFG_1, while the fields in ADR_CFG will only apply to the first device.
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_FIELD                 (_MK_MASK_CONST(0x3) << EMC_ADR_CFG_0_EMEM_NUMDEV_SHIFT)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_RANGE                 25:24
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_WOFFSET                       0x0
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_INIT_ENUM                     N1
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_N1                    _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_0_EMEM_NUMDEV_N2                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_ADR_CFG_1_0  // External memory address config Register, Device[1]
+#define EMC_ADR_CFG_1_0                 _MK_ADDR_CONST(0x14)
+#define EMC_ADR_CFG_1_0_SECURE                  0x0
+#define EMC_ADR_CFG_1_0_WORD_COUNT                      0x1
+#define EMC_ADR_CFG_1_0_RESET_VAL                       _MK_MASK_CONST(0x40202)
+#define EMC_ADR_CFG_1_0_RESET_MASK                      _MK_MASK_CONST(0xf0307)
+#define EMC_ADR_CFG_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_READ_MASK                       _MK_MASK_CONST(0xf0307)
+#define EMC_ADR_CFG_1_0_WRITE_MASK                      _MK_MASK_CONST(0xf0307)
+// width of column address of the attached SDRAM device.
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_FIELD                    (_MK_MASK_CONST(0x7) << EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_SHIFT)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_RANGE                    2:0
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_WOFFSET                  0x0
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_DEFAULT                  _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_INIT_ENUM                        W9
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_W7                       _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_W8                       _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_W9                       _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_W10                      _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_W11                      _MK_ENUM_CONST(4)
+
+// width of bank address of the attached SDRAM device.
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_FIELD                   (_MK_MASK_CONST(0x3) << EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_SHIFT)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_RANGE                   9:8
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_WOFFSET                 0x0
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_DEFAULT                 _MK_MASK_CONST(0x2)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_INIT_ENUM                       W2
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_W1                      _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_W2                      _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_W3                      _MK_ENUM_CONST(3)
+
+// size of the attached SDRAM device used to generate width of row address.
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_FIELD                     (_MK_MASK_CONST(0xf) << EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_SHIFT)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_RANGE                     19:16
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_WOFFSET                   0x0
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_DEFAULT                   _MK_MASK_CONST(0x4)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_INIT_ENUM                 D64MB
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D4MB                      _MK_ENUM_CONST(0)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D8MB                      _MK_ENUM_CONST(1)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D16MB                     _MK_ENUM_CONST(2)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D32MB                     _MK_ENUM_CONST(3)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D64MB                     _MK_ENUM_CONST(4)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D128MB                    _MK_ENUM_CONST(5)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D256MB                    _MK_ENUM_CONST(6)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D512MB                    _MK_ENUM_CONST(7)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D1024MB                   _MK_ENUM_CONST(8)
+#define EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_D1GB                      _MK_ENUM_CONST(8)
+
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+
+// Register EMC_REFCTRL_0  // Refresh Control Register
+#define EMC_REFCTRL_0                   _MK_ADDR_CONST(0x20)
+#define EMC_REFCTRL_0_SECURE                    0x0
+#define EMC_REFCTRL_0_WORD_COUNT                        0x1
+#define EMC_REFCTRL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_RESET_MASK                        _MK_MASK_CONST(0x80000003)
+#define EMC_REFCTRL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_READ_MASK                         _MK_MASK_CONST(0x80000003)
+#define EMC_REFCTRL_0_WRITE_MASK                        _MK_MASK_CONST(0x80000003)
+// disables refresh to individual attached device (1 bit per dram chip-select).
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_FIELD                      (_MK_MASK_CONST(0x3) << EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_SHIFT)
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_RANGE                      1:0
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_WOFFSET                    0x0
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_DEVICE_REFRESH_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// enable refresh controller. 
+#define EMC_REFCTRL_0_REF_VALID_SHIFT                   _MK_SHIFT_CONST(31)
+#define EMC_REFCTRL_0_REF_VALID_FIELD                   (_MK_MASK_CONST(0x1) << EMC_REFCTRL_0_REF_VALID_SHIFT)
+#define EMC_REFCTRL_0_REF_VALID_RANGE                   31:31
+#define EMC_REFCTRL_0_REF_VALID_WOFFSET                 0x0
+#define EMC_REFCTRL_0_REF_VALID_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_REFCTRL_0_REF_VALID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_REFCTRL_0_REF_VALID_INIT_ENUM                       DISABLED
+#define EMC_REFCTRL_0_REF_VALID_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_REFCTRL_0_REF_VALID_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register EMC_PIN_0  // Controls state of selected DRAM pins
+#define EMC_PIN_0                       _MK_ADDR_CONST(0x24)
+#define EMC_PIN_0_SECURE                        0x0
+#define EMC_PIN_0_WORD_COUNT                    0x1
+#define EMC_PIN_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_RESET_MASK                    _MK_MASK_CONST(0x11)
+#define EMC_PIN_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_READ_MASK                     _MK_MASK_CONST(0x11)
+#define EMC_PIN_0_WRITE_MASK                    _MK_MASK_CONST(0x11)
+// selects the level of the CKE pin.
+// This can be used to place the DRAM in power down state.  PIN_CKE value is applied all CKE pins.
+#define EMC_PIN_0_PIN_CKE_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_PIN_0_PIN_CKE_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PIN_0_PIN_CKE_SHIFT)
+#define EMC_PIN_0_PIN_CKE_RANGE                 0:0
+#define EMC_PIN_0_PIN_CKE_WOFFSET                       0x0
+#define EMC_PIN_0_PIN_CKE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PIN_0_PIN_CKE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_CKE_INIT_ENUM                     POWERDOWN
+#define EMC_PIN_0_PIN_CKE_POWERDOWN                     _MK_ENUM_CONST(0)
+#define EMC_PIN_0_PIN_CKE_NORMAL                        _MK_ENUM_CONST(1)
+
+// is used to always mask DRAM writes.
+// This pin should only be used for initialization.  Certain DRAM vendors (e.g., Samsung),
+// require the DQM to be high during initialization.  The register value should be set to NORMAL
+// after the initialization sequence.
+#define EMC_PIN_0_PIN_DQM_SHIFT                 _MK_SHIFT_CONST(4)
+#define EMC_PIN_0_PIN_DQM_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PIN_0_PIN_DQM_SHIFT)
+#define EMC_PIN_0_PIN_DQM_RANGE                 4:4
+#define EMC_PIN_0_PIN_DQM_WOFFSET                       0x0
+#define EMC_PIN_0_PIN_DQM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PIN_0_PIN_DQM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PIN_0_PIN_DQM_INIT_ENUM                     NORMAL
+#define EMC_PIN_0_PIN_DQM_NORMAL                        _MK_ENUM_CONST(0)
+#define EMC_PIN_0_PIN_DQM_INACTIVE                      _MK_ENUM_CONST(1)
+
+
+// Register EMC_TIMING_CONTROL_0  // Triggers an update of the timing-related registers
+#define EMC_TIMING_CONTROL_0                    _MK_ADDR_CONST(0x28)
+#define EMC_TIMING_CONTROL_0_SECURE                     0x0
+#define EMC_TIMING_CONTROL_0_WORD_COUNT                         0x1
+#define EMC_TIMING_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_TIMING_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_FIELD                        (_MK_MASK_CONST(0x1) << EMC_TIMING_CONTROL_0_TIMING_UPDATE_SHIFT)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_RANGE                        0:0
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_WOFFSET                      0x0
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_TIMING_CONTROL_0_TIMING_UPDATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RC_0  // DRAM timing parameter
+#define EMC_RC_0                        _MK_ADDR_CONST(0x2c)
+#define EMC_RC_0_SECURE                         0x0
+#define EMC_RC_0_WORD_COUNT                     0x1
+#define EMC_RC_0_RESET_VAL                      _MK_MASK_CONST(0x3f)
+#define EMC_RC_0_RESET_MASK                     _MK_MASK_CONST(0x3f)
+#define EMC_RC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_RC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_RC_0_READ_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_RC_0_WRITE_MASK                     _MK_MASK_CONST(0x3f)
+// specifies the row cycle time.
+// This is the minimum number of cycles between activate commands to the same bank.
+#define EMC_RC_0_RC_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_RC_0_RC_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_RC_0_RC_SHIFT)
+#define EMC_RC_0_RC_RANGE                       5:0
+#define EMC_RC_0_RC_WOFFSET                     0x0
+#define EMC_RC_0_RC_DEFAULT                     _MK_MASK_CONST(0x3f)
+#define EMC_RC_0_RC_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_RC_0_RC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_RC_0_RC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RFC_0  // DRAM timing parameter
+#define EMC_RFC_0                       _MK_ADDR_CONST(0x30)
+#define EMC_RFC_0_SECURE                        0x0
+#define EMC_RFC_0_WORD_COUNT                    0x1
+#define EMC_RFC_0_RESET_VAL                     _MK_MASK_CONST(0x3f)
+#define EMC_RFC_0_RESET_MASK                    _MK_MASK_CONST(0x1ff)
+#define EMC_RFC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_RFC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_RFC_0_READ_MASK                     _MK_MASK_CONST(0x1ff)
+#define EMC_RFC_0_WRITE_MASK                    _MK_MASK_CONST(0x1ff)
+// specifies the auto refresh cycle time.
+// This is the minimum number of cycles between an auto refresh command and a subsequent auto refresh
+// or activate command.
+#define EMC_RFC_0_RFC_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_RFC_0_RFC_FIELD                     (_MK_MASK_CONST(0x1ff) << EMC_RFC_0_RFC_SHIFT)
+#define EMC_RFC_0_RFC_RANGE                     8:0
+#define EMC_RFC_0_RFC_WOFFSET                   0x0
+#define EMC_RFC_0_RFC_DEFAULT                   _MK_MASK_CONST(0x3f)
+#define EMC_RFC_0_RFC_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
+#define EMC_RFC_0_RFC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_RFC_0_RFC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RAS_0  // DRAM timing parameter
+#define EMC_RAS_0                       _MK_ADDR_CONST(0x34)
+#define EMC_RAS_0_SECURE                        0x0
+#define EMC_RAS_0_WORD_COUNT                    0x1
+#define EMC_RAS_0_RESET_VAL                     _MK_MASK_CONST(0x3f)
+#define EMC_RAS_0_RESET_MASK                    _MK_MASK_CONST(0x3f)
+#define EMC_RAS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_RAS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_RAS_0_READ_MASK                     _MK_MASK_CONST(0x3f)
+#define EMC_RAS_0_WRITE_MASK                    _MK_MASK_CONST(0x3f)
+// specifies the row active time. 
+// This is the minimum number of cycles between an activate command and a precharge command to the same bank.
+#define EMC_RAS_0_RAS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_RAS_0_RAS_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_RAS_0_RAS_SHIFT)
+#define EMC_RAS_0_RAS_RANGE                     5:0
+#define EMC_RAS_0_RAS_WOFFSET                   0x0
+#define EMC_RAS_0_RAS_DEFAULT                   _MK_MASK_CONST(0x3f)
+#define EMC_RAS_0_RAS_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_RAS_0_RAS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_RAS_0_RAS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RP_0  // DRAM timing parameter
+#define EMC_RP_0                        _MK_ADDR_CONST(0x38)
+#define EMC_RP_0_SECURE                         0x0
+#define EMC_RP_0_WORD_COUNT                     0x1
+#define EMC_RP_0_RESET_VAL                      _MK_MASK_CONST(0x3f)
+#define EMC_RP_0_RESET_MASK                     _MK_MASK_CONST(0x3f)
+#define EMC_RP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_RP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_RP_0_READ_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_RP_0_WRITE_MASK                     _MK_MASK_CONST(0x3f)
+// specifies the row precharge time.
+// This is the minimum number of cycles between a precharge command and an activate command to the same bank.
+#define EMC_RP_0_RP_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_RP_0_RP_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_RP_0_RP_SHIFT)
+#define EMC_RP_0_RP_RANGE                       5:0
+#define EMC_RP_0_RP_WOFFSET                     0x0
+#define EMC_RP_0_RP_DEFAULT                     _MK_MASK_CONST(0x3f)
+#define EMC_RP_0_RP_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_RP_0_RP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_RP_0_RP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_R2W_0  // DRAM timing parameter
+#define EMC_R2W_0                       _MK_ADDR_CONST(0x3c)
+#define EMC_R2W_0_SECURE                        0x0
+#define EMC_R2W_0_WORD_COUNT                    0x1
+#define EMC_R2W_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define EMC_R2W_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_R2W_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_R2W_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_R2W_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_R2W_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+// specifies the minimum number of cycles from any read command to any write command,
+// irrespective of bank.  This parameter guarantees the read->write turn-around time on the bus.
+// Set to ((CL+1)-WL + R2W_bus_turnaround_clks). If ODT is enabled,  set to ((CL+1)-WL + R2W_bus_turnaround_clks + 1)).
+// Largest programming value is 29
+#define EMC_R2W_0_R2W_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_R2W_0_R2W_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_R2W_0_R2W_SHIFT)
+#define EMC_R2W_0_R2W_RANGE                     4:0
+#define EMC_R2W_0_R2W_WOFFSET                   0x0
+#define EMC_R2W_0_R2W_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_R2W_0_R2W_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_R2W_0_R2W_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_R2W_0_R2W_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_W2R_0  // DRAM timing parameter
+#define EMC_W2R_0                       _MK_ADDR_CONST(0x40)
+#define EMC_W2R_0_SECURE                        0x0
+#define EMC_W2R_0_WORD_COUNT                    0x1
+#define EMC_W2R_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define EMC_W2R_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_W2R_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_W2R_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_W2R_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_W2R_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+// specifies the minimum number of cycles from a write command to a read command,
+// irrespective of bank. Set to ((WL+1) + tWTR).
+// Largest programming value is 29
+#define EMC_W2R_0_W2R_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_W2R_0_W2R_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_W2R_0_W2R_SHIFT)
+#define EMC_W2R_0_W2R_RANGE                     4:0
+#define EMC_W2R_0_W2R_WOFFSET                   0x0
+#define EMC_W2R_0_W2R_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_W2R_0_W2R_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_W2R_0_W2R_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_W2R_0_W2R_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_R2P_0  // DRAM timing parameter
+#define EMC_R2P_0                       _MK_ADDR_CONST(0x44)
+#define EMC_R2P_0_SECURE                        0x0
+#define EMC_R2P_0_WORD_COUNT                    0x1
+#define EMC_R2P_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define EMC_R2P_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_R2P_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_R2P_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_R2P_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_R2P_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+// specifies the minimum number of cycles from a read command to
+// a precharge command for the same bank.  Set to 1 clock.
+#define EMC_R2P_0_R2P_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_R2P_0_R2P_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_R2P_0_R2P_SHIFT)
+#define EMC_R2P_0_R2P_RANGE                     4:0
+#define EMC_R2P_0_R2P_WOFFSET                   0x0
+#define EMC_R2P_0_R2P_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_R2P_0_R2P_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_R2P_0_R2P_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_R2P_0_R2P_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_W2P_0  // DRAM timing parameter
+#define EMC_W2P_0                       _MK_ADDR_CONST(0x48)
+#define EMC_W2P_0_SECURE                        0x0
+#define EMC_W2P_0_WORD_COUNT                    0x1
+#define EMC_W2P_0_RESET_VAL                     _MK_MASK_CONST(0x1f)
+#define EMC_W2P_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_W2P_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_W2P_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_W2P_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_W2P_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+// specifies the minimum number of cycles from a write command to
+// a precharge command for the same bank. Set to ((WL+1) + tWR).
+#define EMC_W2P_0_W2P_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_W2P_0_W2P_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_W2P_0_W2P_SHIFT)
+#define EMC_W2P_0_W2P_RANGE                     4:0
+#define EMC_W2P_0_W2P_WOFFSET                   0x0
+#define EMC_W2P_0_W2P_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_W2P_0_W2P_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_W2P_0_W2P_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_W2P_0_W2P_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RD_RCD_0  // DRAM timing parameter
+#define EMC_RD_RCD_0                    _MK_ADDR_CONST(0x4c)
+#define EMC_RD_RCD_0_SECURE                     0x0
+#define EMC_RD_RCD_0_WORD_COUNT                         0x1
+#define EMC_RD_RCD_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define EMC_RD_RCD_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
+#define EMC_RD_RCD_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_RD_RCD_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_RD_RCD_0_READ_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_RD_RCD_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
+// specifies the ras to cas delay.
+// RD_RCD is the minimum number of cycles between an activate command and a read command to the same bank.
+#define EMC_RD_RCD_0_RD_RCD_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_RD_RCD_0_RD_RCD_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_RD_RCD_0_RD_RCD_SHIFT)
+#define EMC_RD_RCD_0_RD_RCD_RANGE                       5:0
+#define EMC_RD_RCD_0_RD_RCD_WOFFSET                     0x0
+#define EMC_RD_RCD_0_RD_RCD_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define EMC_RD_RCD_0_RD_RCD_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_RD_RCD_0_RD_RCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_RD_RCD_0_RD_RCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_WR_RCD_0  // DRAM timing parameter
+#define EMC_WR_RCD_0                    _MK_ADDR_CONST(0x50)
+#define EMC_WR_RCD_0_SECURE                     0x0
+#define EMC_WR_RCD_0_WORD_COUNT                         0x1
+#define EMC_WR_RCD_0_RESET_VAL                  _MK_MASK_CONST(0x1f)
+#define EMC_WR_RCD_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
+#define EMC_WR_RCD_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_WR_RCD_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_WR_RCD_0_READ_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_WR_RCD_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
+// minimum number of cycles between an activate command and a
+// write command to the same bank.
+#define EMC_WR_RCD_0_WR_RCD_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_WR_RCD_0_WR_RCD_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_WR_RCD_0_WR_RCD_SHIFT)
+#define EMC_WR_RCD_0_WR_RCD_RANGE                       5:0
+#define EMC_WR_RCD_0_WR_RCD_WOFFSET                     0x0
+#define EMC_WR_RCD_0_WR_RCD_DEFAULT                     _MK_MASK_CONST(0x1f)
+#define EMC_WR_RCD_0_WR_RCD_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_WR_RCD_0_WR_RCD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_WR_RCD_0_WR_RCD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RRD_0  // DRAM timing parameter
+#define EMC_RRD_0                       _MK_ADDR_CONST(0x54)
+#define EMC_RRD_0_SECURE                        0x0
+#define EMC_RRD_0_WORD_COUNT                    0x1
+#define EMC_RRD_0_RESET_VAL                     _MK_MASK_CONST(0xf)
+#define EMC_RRD_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_RRD_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_RRD_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_RRD_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_RRD_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+// specifies the Bank X Act to Bank Y Act command delay.
+#define EMC_RRD_0_RRD_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_RRD_0_RRD_FIELD                     (_MK_MASK_CONST(0xf) << EMC_RRD_0_RRD_SHIFT)
+#define EMC_RRD_0_RRD_RANGE                     3:0
+#define EMC_RRD_0_RRD_WOFFSET                   0x0
+#define EMC_RRD_0_RRD_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_RRD_0_RRD_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_RRD_0_RRD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_RRD_0_RRD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_REXT_0  // DRAM timing parameter
+#define EMC_REXT_0                      _MK_ADDR_CONST(0x58)
+#define EMC_REXT_0_SECURE                       0x0
+#define EMC_REXT_0_WORD_COUNT                   0x1
+#define EMC_REXT_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define EMC_REXT_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_REXT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_REXT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_REXT_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_REXT_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+// specifies the read to read delay for reads when 
+// multiple physical devices are present.
+#define EMC_REXT_0_REXT_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_REXT_0_REXT_FIELD                   (_MK_MASK_CONST(0xf) << EMC_REXT_0_REXT_SHIFT)
+#define EMC_REXT_0_REXT_RANGE                   3:0
+#define EMC_REXT_0_REXT_WOFFSET                 0x0
+#define EMC_REXT_0_REXT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define EMC_REXT_0_REXT_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_REXT_0_REXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_REXT_0_REXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_WDV_0  // DRAM timing parameter
+#define EMC_WDV_0                       _MK_ADDR_CONST(0x5c)
+#define EMC_WDV_0_SECURE                        0x0
+#define EMC_WDV_0_WORD_COUNT                    0x1
+#define EMC_WDV_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_WDV_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_WDV_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+// the number of cycles to post (delay) write data from being asserted
+// to the rams. Set to 0 for DDR1 operation. For DDR1, the delay obtained is the programmed value + 1.
+#define EMC_WDV_0_WDV_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_WDV_0_WDV_FIELD                     (_MK_MASK_CONST(0xf) << EMC_WDV_0_WDV_SHIFT)
+#define EMC_WDV_0_WDV_RANGE                     3:0
+#define EMC_WDV_0_WDV_WOFFSET                   0x0
+#define EMC_WDV_0_WDV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_WDV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_WDV_0_WDV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_WDV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_WDV_0_WDV_MAX                       _MK_ENUM_CONST(15)
+
+
+// Register EMC_QUSE_0  // DRAM timing parameter
+#define EMC_QUSE_0                      _MK_ADDR_CONST(0x60)
+#define EMC_QUSE_0_SECURE                       0x0
+#define EMC_QUSE_0_WORD_COUNT                   0x1
+#define EMC_QUSE_0_RESET_VAL                    _MK_MASK_CONST(0x2)
+#define EMC_QUSE_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_QUSE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_QUSE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_QUSE_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+// tells the chip when to look for read return data.
+#define EMC_QUSE_0_QUSE_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_QUSE_0_QUSE_FIELD                   (_MK_MASK_CONST(0xf) << EMC_QUSE_0_QUSE_SHIFT)
+#define EMC_QUSE_0_QUSE_RANGE                   3:0
+#define EMC_QUSE_0_QUSE_WOFFSET                 0x0
+#define EMC_QUSE_0_QUSE_DEFAULT                 _MK_MASK_CONST(0x2)
+#define EMC_QUSE_0_QUSE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_QUSE_0_QUSE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_0_QUSE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QRST_0  // DRAM timing parameter
+#define EMC_QRST_0                      _MK_ADDR_CONST(0x64)
+#define EMC_QRST_0_SECURE                       0x0
+#define EMC_QRST_0_WORD_COUNT                   0x1
+#define EMC_QRST_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define EMC_QRST_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_QRST_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_QRST_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_QRST_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_QRST_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+// time from expiration of QSAFE until reset is issued
+#define EMC_QRST_0_QRST_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_QRST_0_QRST_FIELD                   (_MK_MASK_CONST(0xf) << EMC_QRST_0_QRST_SHIFT)
+#define EMC_QRST_0_QRST_RANGE                   3:0
+#define EMC_QRST_0_QRST_WOFFSET                 0x0
+#define EMC_QRST_0_QRST_DEFAULT                 _MK_MASK_CONST(0x1)
+#define EMC_QRST_0_QRST_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_QRST_0_QRST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_QRST_0_QRST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QSAFE_0  // DRAM timing parameter
+#define EMC_QSAFE_0                     _MK_ADDR_CONST(0x68)
+#define EMC_QSAFE_0_SECURE                      0x0
+#define EMC_QSAFE_0_WORD_COUNT                  0x1
+#define EMC_QSAFE_0_RESET_VAL                   _MK_MASK_CONST(0x7)
+#define EMC_QSAFE_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define EMC_QSAFE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_QSAFE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_QSAFE_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_QSAFE_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+// time from a read command to when it is safe to issue a QRST (delayed by the QRST parameter).
+#define EMC_QSAFE_0_QSAFE_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_QSAFE_0_QSAFE_FIELD                 (_MK_MASK_CONST(0xf) << EMC_QSAFE_0_QSAFE_SHIFT)
+#define EMC_QSAFE_0_QSAFE_RANGE                 3:0
+#define EMC_QSAFE_0_QSAFE_WOFFSET                       0x0
+#define EMC_QSAFE_0_QSAFE_DEFAULT                       _MK_MASK_CONST(0x7)
+#define EMC_QSAFE_0_QSAFE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define EMC_QSAFE_0_QSAFE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_QSAFE_0_QSAFE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RDV_0  // DRAM timing parameter
+#define EMC_RDV_0                       _MK_ADDR_CONST(0x6c)
+#define EMC_RDV_0_SECURE                        0x0
+#define EMC_RDV_0_WORD_COUNT                    0x1
+#define EMC_RDV_0_RESET_VAL                     _MK_MASK_CONST(0x8)
+#define EMC_RDV_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_RDV_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_RDV_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_RDV_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_RDV_0_WRITE_MASK                    _MK_MASK_CONST(0x1f)
+// time from read command to latching the read data from the pad macros.
+#define EMC_RDV_0_RDV_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_RDV_0_RDV_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_RDV_0_RDV_SHIFT)
+#define EMC_RDV_0_RDV_RANGE                     4:0
+#define EMC_RDV_0_RDV_WOFFSET                   0x0
+#define EMC_RDV_0_RDV_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_RDV_0_RDV_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_RDV_0_RDV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_RDV_0_RDV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_RDV_0_RDV_MAX                       _MK_ENUM_CONST(15)
+
+
+// Register EMC_REFRESH_0  // DRAM timing parameter
+#define EMC_REFRESH_0                   _MK_ADDR_CONST(0x70)
+#define EMC_REFRESH_0_SECURE                    0x0
+#define EMC_REFRESH_0_WORD_COUNT                        0x1
+#define EMC_REFRESH_0_RESET_VAL                         _MK_MASK_CONST(0x1f)
+#define EMC_REFRESH_0_RESET_MASK                        _MK_MASK_CONST(0x1f)
+#define EMC_REFRESH_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define EMC_REFRESH_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+#define EMC_REFRESH_0_REFRESH_LO_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_REFRESH_0_REFRESH_LO_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_REFRESH_0_REFRESH_LO_SHIFT)
+#define EMC_REFRESH_0_REFRESH_LO_RANGE                  4:0
+#define EMC_REFRESH_0_REFRESH_LO_WOFFSET                        0x0
+#define EMC_REFRESH_0_REFRESH_LO_DEFAULT                        _MK_MASK_CONST(0x1f)
+#define EMC_REFRESH_0_REFRESH_LO_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_REFRESH_0_REFRESH_LO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_REFRESH_LO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_REFRESH_LO_INIT_ENUM                      MAX
+#define EMC_REFRESH_0_REFRESH_LO_MAX                    _MK_ENUM_CONST(31)
+
+// specifies the interval between refresh requests.
+#define EMC_REFRESH_0_REFRESH_SHIFT                     _MK_SHIFT_CONST(5)
+#define EMC_REFRESH_0_REFRESH_FIELD                     (_MK_MASK_CONST(0x7ff) << EMC_REFRESH_0_REFRESH_SHIFT)
+#define EMC_REFRESH_0_REFRESH_RANGE                     15:5
+#define EMC_REFRESH_0_REFRESH_WOFFSET                   0x0
+#define EMC_REFRESH_0_REFRESH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_REFRESH_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_REFRESH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_REFRESH_0_REFRESH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_BURST_REFRESH_NUM_0  // DRAM timing parameter
+#define EMC_BURST_REFRESH_NUM_0                 _MK_ADDR_CONST(0x74)
+#define EMC_BURST_REFRESH_NUM_0_SECURE                  0x0
+#define EMC_BURST_REFRESH_NUM_0_WORD_COUNT                      0x1
+#define EMC_BURST_REFRESH_NUM_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_RESET_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_BURST_REFRESH_NUM_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_READ_MASK                       _MK_MASK_CONST(0xf)
+#define EMC_BURST_REFRESH_NUM_0_WRITE_MASK                      _MK_MASK_CONST(0xf)
+// specify the refresh burst count.
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_FIELD                 (_MK_MASK_CONST(0xf) << EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_SHIFT)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_RANGE                 3:0
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_WOFFSET                       0x0
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_INIT_ENUM                     BR1
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR1                   _MK_ENUM_CONST(0)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR2                   _MK_ENUM_CONST(1)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR4                   _MK_ENUM_CONST(2)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR8                   _MK_ENUM_CONST(3)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR16                  _MK_ENUM_CONST(4)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR32                  _MK_ENUM_CONST(5)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR64                  _MK_ENUM_CONST(6)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR128                 _MK_ENUM_CONST(7)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR256                 _MK_ENUM_CONST(8)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_BR512                 _MK_ENUM_CONST(9)
+#define EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_MAX                   _MK_ENUM_CONST(9)
+
+
+// Register EMC_PDEX2WR_0  // DRAM timing parameter
+#define EMC_PDEX2WR_0                   _MK_ADDR_CONST(0x78)
+#define EMC_PDEX2WR_0_SECURE                    0x0
+#define EMC_PDEX2WR_0_WORD_COUNT                        0x1
+#define EMC_PDEX2WR_0_RESET_VAL                         _MK_MASK_CONST(0xe)
+#define EMC_PDEX2WR_0_RESET_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_PDEX2WR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_PDEX2WR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_PDEX2WR_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define EMC_PDEX2WR_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+// specify the timing delay from exit of powerdown mode to a write command.
+// Largest allowed value is 14
+#define EMC_PDEX2WR_0_PDEX2WR_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_PDEX2WR_0_PDEX2WR_FIELD                     (_MK_MASK_CONST(0xf) << EMC_PDEX2WR_0_PDEX2WR_SHIFT)
+#define EMC_PDEX2WR_0_PDEX2WR_RANGE                     3:0
+#define EMC_PDEX2WR_0_PDEX2WR_WOFFSET                   0x0
+#define EMC_PDEX2WR_0_PDEX2WR_DEFAULT                   _MK_MASK_CONST(0xe)
+#define EMC_PDEX2WR_0_PDEX2WR_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_PDEX2WR_0_PDEX2WR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_PDEX2WR_0_PDEX2WR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_PDEX2RD_0  // DRAM timing parameter
+#define EMC_PDEX2RD_0                   _MK_ADDR_CONST(0x7c)
+#define EMC_PDEX2RD_0_SECURE                    0x0
+#define EMC_PDEX2RD_0_WORD_COUNT                        0x1
+#define EMC_PDEX2RD_0_RESET_VAL                         _MK_MASK_CONST(0xe)
+#define EMC_PDEX2RD_0_RESET_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_PDEX2RD_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_PDEX2RD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_PDEX2RD_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define EMC_PDEX2RD_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+// specify the timing delay from exit of powerdown mode to a read command.
+// Largest allowed value is 14
+#define EMC_PDEX2RD_0_PDEX2RD_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_PDEX2RD_0_PDEX2RD_FIELD                     (_MK_MASK_CONST(0xf) << EMC_PDEX2RD_0_PDEX2RD_SHIFT)
+#define EMC_PDEX2RD_0_PDEX2RD_RANGE                     3:0
+#define EMC_PDEX2RD_0_PDEX2RD_WOFFSET                   0x0
+#define EMC_PDEX2RD_0_PDEX2RD_DEFAULT                   _MK_MASK_CONST(0xe)
+#define EMC_PDEX2RD_0_PDEX2RD_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_PDEX2RD_0_PDEX2RD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_PDEX2RD_0_PDEX2RD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_PCHG2PDEN_0  // DRAM timing parameter
+#define EMC_PCHG2PDEN_0                 _MK_ADDR_CONST(0x80)
+#define EMC_PCHG2PDEN_0_SECURE                  0x0
+#define EMC_PCHG2PDEN_0_WORD_COUNT                      0x1
+#define EMC_PCHG2PDEN_0_RESET_VAL                       _MK_MASK_CONST(0xf)
+#define EMC_PCHG2PDEN_0_RESET_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_PCHG2PDEN_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_PCHG2PDEN_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_PCHG2PDEN_0_READ_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_PCHG2PDEN_0_WRITE_MASK                      _MK_MASK_CONST(0x1f)
+//  specify the timing delay from a precharge command to powerdown entry.
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_PCHG2PDEN_0_PCHG2PDEN_SHIFT)
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_RANGE                 4:0
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_WOFFSET                       0x0
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_DEFAULT                       _MK_MASK_CONST(0xf)
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PCHG2PDEN_0_PCHG2PDEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_ACT2PDEN_0  // DRAM timing parameter
+#define EMC_ACT2PDEN_0                  _MK_ADDR_CONST(0x84)
+#define EMC_ACT2PDEN_0_SECURE                   0x0
+#define EMC_ACT2PDEN_0_WORD_COUNT                       0x1
+#define EMC_ACT2PDEN_0_RESET_VAL                        _MK_MASK_CONST(0xf)
+#define EMC_ACT2PDEN_0_RESET_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_ACT2PDEN_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_ACT2PDEN_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_ACT2PDEN_0_READ_MASK                        _MK_MASK_CONST(0x1f)
+#define EMC_ACT2PDEN_0_WRITE_MASK                       _MK_MASK_CONST(0x1f)
+// specify the timing delay from an activate, mrs or emrs command to powerdown entry.
+#define EMC_ACT2PDEN_0_ACT2PDEN_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_ACT2PDEN_0_ACT2PDEN_FIELD                   (_MK_MASK_CONST(0x1f) << EMC_ACT2PDEN_0_ACT2PDEN_SHIFT)
+#define EMC_ACT2PDEN_0_ACT2PDEN_RANGE                   4:0
+#define EMC_ACT2PDEN_0_ACT2PDEN_WOFFSET                 0x0
+#define EMC_ACT2PDEN_0_ACT2PDEN_DEFAULT                 _MK_MASK_CONST(0xf)
+#define EMC_ACT2PDEN_0_ACT2PDEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_ACT2PDEN_0_ACT2PDEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_ACT2PDEN_0_ACT2PDEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AR2PDEN_0  // DRAM timing parameter
+#define EMC_AR2PDEN_0                   _MK_ADDR_CONST(0x88)
+#define EMC_AR2PDEN_0_SECURE                    0x0
+#define EMC_AR2PDEN_0_WORD_COUNT                        0x1
+#define EMC_AR2PDEN_0_RESET_VAL                         _MK_MASK_CONST(0x1f)
+#define EMC_AR2PDEN_0_RESET_MASK                        _MK_MASK_CONST(0x1f)
+#define EMC_AR2PDEN_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_AR2PDEN_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AR2PDEN_0_READ_MASK                         _MK_MASK_CONST(0x1f)
+#define EMC_AR2PDEN_0_WRITE_MASK                        _MK_MASK_CONST(0x1f)
+// specify the timing delay from an autorefresh command to powerdown entry.
+#define EMC_AR2PDEN_0_AR2PDEN_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_AR2PDEN_0_AR2PDEN_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_AR2PDEN_0_AR2PDEN_SHIFT)
+#define EMC_AR2PDEN_0_AR2PDEN_RANGE                     4:0
+#define EMC_AR2PDEN_0_AR2PDEN_WOFFSET                   0x0
+#define EMC_AR2PDEN_0_AR2PDEN_DEFAULT                   _MK_MASK_CONST(0x1f)
+#define EMC_AR2PDEN_0_AR2PDEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define EMC_AR2PDEN_0_AR2PDEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AR2PDEN_0_AR2PDEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_RW2PDEN_0  // DRAM timing parameter
+#define EMC_RW2PDEN_0                   _MK_ADDR_CONST(0x8c)
+#define EMC_RW2PDEN_0_SECURE                    0x0
+#define EMC_RW2PDEN_0_WORD_COUNT                        0x1
+#define EMC_RW2PDEN_0_RESET_VAL                         _MK_MASK_CONST(0xf)
+#define EMC_RW2PDEN_0_RESET_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_RW2PDEN_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_RW2PDEN_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_RW2PDEN_0_READ_MASK                         _MK_MASK_CONST(0x3f)
+#define EMC_RW2PDEN_0_WRITE_MASK                        _MK_MASK_CONST(0x3f)
+// specify the timing delay from a read/write command to powerdown entry.
+//  Auto-precharge timing must be taken into account when programming this field (affects lpddr & lpddr2/ddr2 differently).
+#define EMC_RW2PDEN_0_RW2PDEN_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_RW2PDEN_0_RW2PDEN_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_RW2PDEN_0_RW2PDEN_SHIFT)
+#define EMC_RW2PDEN_0_RW2PDEN_RANGE                     5:0
+#define EMC_RW2PDEN_0_RW2PDEN_WOFFSET                   0x0
+#define EMC_RW2PDEN_0_RW2PDEN_DEFAULT                   _MK_MASK_CONST(0xf)
+#define EMC_RW2PDEN_0_RW2PDEN_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_RW2PDEN_0_RW2PDEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_RW2PDEN_0_RW2PDEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TXSR_0  // DRAM timing parameter
+#define EMC_TXSR_0                      _MK_ADDR_CONST(0x90)
+#define EMC_TXSR_0_SECURE                       0x0
+#define EMC_TXSR_0_WORD_COUNT                   0x1
+#define EMC_TXSR_0_RESET_VAL                    _MK_MASK_CONST(0x7ff)
+#define EMC_TXSR_0_RESET_MASK                   _MK_MASK_CONST(0xfff)
+#define EMC_TXSR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_TXSR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_TXSR_0_READ_MASK                    _MK_MASK_CONST(0xfff)
+#define EMC_TXSR_0_WRITE_MASK                   _MK_MASK_CONST(0xfff)
+// cycles between self-refresh exit & first DRAM command
+// Largest allowed value is 0xffe
+#define EMC_TXSR_0_TXSR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_TXSR_0_TXSR_FIELD                   (_MK_MASK_CONST(0xfff) << EMC_TXSR_0_TXSR_SHIFT)
+#define EMC_TXSR_0_TXSR_RANGE                   11:0
+#define EMC_TXSR_0_TXSR_WOFFSET                 0x0
+#define EMC_TXSR_0_TXSR_DEFAULT                 _MK_MASK_CONST(0x7ff)
+#define EMC_TXSR_0_TXSR_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define EMC_TXSR_0_TXSR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TXSR_0_TXSR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TCKE_0  // DRAM timing parameter
+#define EMC_TCKE_0                      _MK_ADDR_CONST(0x94)
+#define EMC_TCKE_0_SECURE                       0x0
+#define EMC_TCKE_0_WORD_COUNT                   0x1
+#define EMC_TCKE_0_RESET_VAL                    _MK_MASK_CONST(0xe)
+#define EMC_TCKE_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_TCKE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_TCKE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_TCKE_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_TCKE_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+// specify minimum CKE pulse width.
+#define EMC_TCKE_0_TCKE_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_TCKE_0_TCKE_FIELD                   (_MK_MASK_CONST(0xf) << EMC_TCKE_0_TCKE_SHIFT)
+#define EMC_TCKE_0_TCKE_RANGE                   3:0
+#define EMC_TCKE_0_TCKE_WOFFSET                 0x0
+#define EMC_TCKE_0_TCKE_DEFAULT                 _MK_MASK_CONST(0xe)
+#define EMC_TCKE_0_TCKE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_TCKE_0_TCKE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TCKE_0_TCKE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TFAW_0  // DRAM timing parameter
+#define EMC_TFAW_0                      _MK_ADDR_CONST(0x98)
+#define EMC_TFAW_0_SECURE                       0x0
+#define EMC_TFAW_0_WORD_COUNT                   0x1
+#define EMC_TFAW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_TFAW_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
+#define EMC_TFAW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_TFAW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_TFAW_0_READ_MASK                    _MK_MASK_CONST(0x3f)
+#define EMC_TFAW_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
+// specify the width of the FAW (four-activate window) for 8-bank devices.
+// Set to 0 to disable this timing check. Only 4 activates may occur withing the rolling window. 
+#define EMC_TFAW_0_TFAW_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_TFAW_0_TFAW_FIELD                   (_MK_MASK_CONST(0x3f) << EMC_TFAW_0_TFAW_SHIFT)
+#define EMC_TFAW_0_TFAW_RANGE                   5:0
+#define EMC_TFAW_0_TFAW_WOFFSET                 0x0
+#define EMC_TFAW_0_TFAW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_TFAW_0_TFAW_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define EMC_TFAW_0_TFAW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TFAW_0_TFAW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TRPAB_0  // DRAM timing parameter
+#define EMC_TRPAB_0                     _MK_ADDR_CONST(0x9c)
+#define EMC_TRPAB_0_SECURE                      0x0
+#define EMC_TRPAB_0_WORD_COUNT                  0x1
+#define EMC_TRPAB_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_TRPAB_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_TRPAB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_TRPAB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_TRPAB_0_READ_MASK                   _MK_MASK_CONST(0x3f)
+#define EMC_TRPAB_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
+// specify precharge-all tRP allowance for 8-bank devices.
+// Setting this field to 0 will cause EMC to use TRP.TRP for precharge-all.
+#define EMC_TRPAB_0_TRPAB_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_TRPAB_0_TRPAB_FIELD                 (_MK_MASK_CONST(0x3f) << EMC_TRPAB_0_TRPAB_SHIFT)
+#define EMC_TRPAB_0_TRPAB_RANGE                 5:0
+#define EMC_TRPAB_0_TRPAB_WOFFSET                       0x0
+#define EMC_TRPAB_0_TRPAB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_TRPAB_0_TRPAB_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_TRPAB_0_TRPAB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_TRPAB_0_TRPAB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TCLKSTABLE_0  // DRAM timing parameter
+#define EMC_TCLKSTABLE_0                        _MK_ADDR_CONST(0xa0)
+#define EMC_TCLKSTABLE_0_SECURE                         0x0
+#define EMC_TCLKSTABLE_0_WORD_COUNT                     0x1
+#define EMC_TCLKSTABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTABLE_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTABLE_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTABLE_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+// specify minimum number of cycles of a stable clock period
+// prior to exiting powerdown or self-refresh modes.
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_FIELD                       (_MK_MASK_CONST(0xf) << EMC_TCLKSTABLE_0_TCLKSTABLE_SHIFT)
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_RANGE                       3:0
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_WOFFSET                     0x0
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTABLE_0_TCLKSTABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TCLKSTOP_0  // DRAM timing parameter
+#define EMC_TCLKSTOP_0                  _MK_ADDR_CONST(0xa4)
+#define EMC_TCLKSTOP_0_SECURE                   0x0
+#define EMC_TCLKSTOP_0_WORD_COUNT                       0x1
+#define EMC_TCLKSTOP_0_RESET_VAL                        _MK_MASK_CONST(0x2)
+#define EMC_TCLKSTOP_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTOP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTOP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTOP_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTOP_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+// delay from last command to stopping the external clock to DRAM devices.
+#define EMC_TCLKSTOP_0_TCLKSTOP_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_TCLKSTOP_0_TCLKSTOP_FIELD                   (_MK_MASK_CONST(0xf) << EMC_TCLKSTOP_0_TCLKSTOP_SHIFT)
+#define EMC_TCLKSTOP_0_TCLKSTOP_RANGE                   3:0
+#define EMC_TCLKSTOP_0_TCLKSTOP_WOFFSET                 0x0
+#define EMC_TCLKSTOP_0_TCLKSTOP_DEFAULT                 _MK_MASK_CONST(0x2)
+#define EMC_TCLKSTOP_0_TCLKSTOP_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_TCLKSTOP_0_TCLKSTOP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_TCLKSTOP_0_TCLKSTOP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_TREFBW_0  // DRAM timing parameter
+#define EMC_TREFBW_0                    _MK_ADDR_CONST(0xa8)
+#define EMC_TREFBW_0_SECURE                     0x0
+#define EMC_TREFBW_0_WORD_COUNT                         0x1
+#define EMC_TREFBW_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_TREFBW_0_RESET_MASK                         _MK_MASK_CONST(0x3fff)
+#define EMC_TREFBW_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_TREFBW_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_TREFBW_0_READ_MASK                  _MK_MASK_CONST(0x3fff)
+#define EMC_TREFBW_0_WRITE_MASK                         _MK_MASK_CONST(0x3fff)
+// specify the width of the burst-refresh window.
+// If set to a non-zero value, only 8 refreshes will occur in this rolling window.
+// Set to 0 to disable this timing check. 
+#define EMC_TREFBW_0_TREFBW_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_TREFBW_0_TREFBW_FIELD                       (_MK_MASK_CONST(0x3fff) << EMC_TREFBW_0_TREFBW_SHIFT)
+#define EMC_TREFBW_0_TREFBW_RANGE                       13:0
+#define EMC_TREFBW_0_TREFBW_WOFFSET                     0x0
+#define EMC_TREFBW_0_TREFBW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_TREFBW_0_TREFBW_DEFAULT_MASK                        _MK_MASK_CONST(0x3fff)
+#define EMC_TREFBW_0_TREFBW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_TREFBW_0_TREFBW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_QUSE_EXTRA_0  
+#define EMC_QUSE_EXTRA_0                        _MK_ADDR_CONST(0xac)
+#define EMC_QUSE_EXTRA_0_SECURE                         0x0
+#define EMC_QUSE_EXTRA_0_WORD_COUNT                     0x1
+#define EMC_QUSE_EXTRA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_QUSE_EXTRA_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_QUSE_EXTRA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_QUSE_EXTRA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_QUSE_EXTRA_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define EMC_QUSE_EXTRA_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_FIELD                       (_MK_MASK_CONST(0xf) << EMC_QUSE_EXTRA_0_QUSE_EXTRA_SHIFT)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_RANGE                       3:0
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_WOFFSET                     0x0
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_QUSE_EXTRA_0_QUSE_EXTRA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_ODT_WRITE_0  
+#define EMC_ODT_WRITE_0                 _MK_ADDR_CONST(0xb0)
+#define EMC_ODT_WRITE_0_SECURE                  0x0
+#define EMC_ODT_WRITE_0_WORD_COUNT                      0x1
+#define EMC_ODT_WRITE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_RESET_MASK                      _MK_MASK_CONST(0xc0000007)
+#define EMC_ODT_WRITE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_READ_MASK                       _MK_MASK_CONST(0xc0000007)
+#define EMC_ODT_WRITE_0_WRITE_MASK                      _MK_MASK_CONST(0xc0000007)
+// Set this field = ABS ( WL - ceiling(tAOND) - 2 ).
+// The valid programming range is 0 <= ODT_WR_DELAY <= 2 if ODT_B4_WRITE=0, 0 <= ODT_WR_DELAY <= 1 if ODT_B4_WRITE=1
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_FIELD                      (_MK_MASK_CONST(0x7) << EMC_ODT_WRITE_0_ODT_WR_DELAY_SHIFT)
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_RANGE                      2:0
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_WOFFSET                    0x0
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ODT_WR_DELAY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// If this field == 1, ODT is turned on ODT_WR_DELAY cycles prior to dram WRITE command.
+// If this field == 0, ODT is turned on ODT_WR_DELAY cycles after dram WRITE command.
+// Set ODT_B4_WRITE to 1 if ( WL - ceiling(tAOND) - 2 ) < 0.
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_SHIFT                      _MK_SHIFT_CONST(30)
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_ODT_WRITE_0_ODT_B4_WRITE_SHIFT)
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_RANGE                      30:30
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_WOFFSET                    0x0
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ODT_B4_WRITE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// enables ODT to be turned on prior to issuing write to DRAM.
+// If ENABLE_ODT_DURING_WRITE = 1 and DISABLE_ODT_DURING_READ = 0, ODT will always be enabled after 1st write.
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_SHIFT                   _MK_SHIFT_CONST(31)
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_SHIFT)
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_RANGE                   31:31
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_WOFFSET                 0x0
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_ODT_READ_0  
+#define EMC_ODT_READ_0                  _MK_ADDR_CONST(0xb4)
+#define EMC_ODT_READ_0_SECURE                   0x0
+#define EMC_ODT_READ_0_WORD_COUNT                       0x1
+#define EMC_ODT_READ_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_RESET_MASK                       _MK_MASK_CONST(0xc0000007)
+#define EMC_ODT_READ_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_READ_MASK                        _MK_MASK_CONST(0xc0000007)
+#define EMC_ODT_READ_0_WRITE_MASK                       _MK_MASK_CONST(0xc0000007)
+// Set this field = ABS ( RL - ceiling(tAOFD) - 2 ).
+// The valid programming range is 0 <= ODT_RD_DELAY <= 2 if ODT_B4_READ=0, 0 <= ODT_RD_DELAY <= 1 if ODT_B4_READ=1
+#define EMC_ODT_READ_0_ODT_RD_DELAY_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_ODT_READ_0_ODT_RD_DELAY_FIELD                       (_MK_MASK_CONST(0x7) << EMC_ODT_READ_0_ODT_RD_DELAY_SHIFT)
+#define EMC_ODT_READ_0_ODT_RD_DELAY_RANGE                       2:0
+#define EMC_ODT_READ_0_ODT_RD_DELAY_WOFFSET                     0x0
+#define EMC_ODT_READ_0_ODT_RD_DELAY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_ODT_RD_DELAY_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define EMC_ODT_READ_0_ODT_RD_DELAY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_ODT_RD_DELAY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// If this field == 1, ODT is turned off ODT_RD_DELAY cycles prior to dram READ command.
+// If this field == 0, ODT is turned off ODT_RD_DELAY cycles after dram READ command.
+// Set ODT_B4_READ to 1 if ( RL - ceiling(tAOFD) - 2 ) < 0.
+#define EMC_ODT_READ_0_ODT_B4_READ_SHIFT                        _MK_SHIFT_CONST(30)
+#define EMC_ODT_READ_0_ODT_B4_READ_FIELD                        (_MK_MASK_CONST(0x1) << EMC_ODT_READ_0_ODT_B4_READ_SHIFT)
+#define EMC_ODT_READ_0_ODT_B4_READ_RANGE                        30:30
+#define EMC_ODT_READ_0_ODT_B4_READ_WOFFSET                      0x0
+#define EMC_ODT_READ_0_ODT_B4_READ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_ODT_B4_READ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_ODT_READ_0_ODT_B4_READ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_ODT_B4_READ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// enables ODT to be turned off prior to issuing read to DRAM.
+// If this field == 0, ODT state will not be changed for reads. 
+// If this field == 1, Turn off ODT prior to READ command
+//   (has no effect if ODT ENABLE_ODT_DURING_WRITE == 0, as ODT will always be disabled). 
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_SHIFT                    _MK_SHIFT_CONST(31)
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_FIELD                    (_MK_MASK_CONST(0x1) << EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_SHIFT)
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_RANGE                    31:31
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_WOFFSET                  0x0
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Register EMC_MRS_0  // Command trigger: MRS
+#define EMC_MRS_0                       _MK_ADDR_CONST(0xcc)
+#define EMC_MRS_0_SECURE                        0x0
+#define EMC_MRS_0_WORD_COUNT                    0x1
+#define EMC_MRS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_READ_MASK                     _MK_MASK_CONST(0xc0303fff)
+#define EMC_MRS_0_WRITE_MASK                    _MK_MASK_CONST(0xc0303fff)
+// mode-register data to be written. 
+#define EMC_MRS_0_MRS_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_MRS_0_MRS_ADR_FIELD                 (_MK_MASK_CONST(0x3fff) << EMC_MRS_0_MRS_ADR_SHIFT)
+#define EMC_MRS_0_MRS_ADR_RANGE                 13:0
+#define EMC_MRS_0_MRS_ADR_WOFFSET                       0x0
+#define EMC_MRS_0_MRS_ADR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_ADR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Set to 0x0 for MRS.
+#define EMC_MRS_0_MRS_BA_SHIFT                  _MK_SHIFT_CONST(20)
+#define EMC_MRS_0_MRS_BA_FIELD                  (_MK_MASK_CONST(0x3) << EMC_MRS_0_MRS_BA_SHIFT)
+#define EMC_MRS_0_MRS_BA_RANGE                  21:20
+#define EMC_MRS_0_MRS_BA_WOFFSET                        0x0
+#define EMC_MRS_0_MRS_BA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_BA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// active low chip-select, 0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for only dev1.
+#define EMC_MRS_0_MRS_DEV_SELECTN_SHIFT                 _MK_SHIFT_CONST(30)
+#define EMC_MRS_0_MRS_DEV_SELECTN_FIELD                 (_MK_MASK_CONST(0x3) << EMC_MRS_0_MRS_DEV_SELECTN_SHIFT)
+#define EMC_MRS_0_MRS_DEV_SELECTN_RANGE                 31:30
+#define EMC_MRS_0_MRS_DEV_SELECTN_WOFFSET                       0x0
+#define EMC_MRS_0_MRS_DEV_SELECTN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_DEV_SELECTN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_DEV_SELECTN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_MRS_0_MRS_DEV_SELECTN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_EMRS_0  // Command trigger: EMRS
+#define EMC_EMRS_0                      _MK_ADDR_CONST(0xd0)
+#define EMC_EMRS_0_SECURE                       0x0
+#define EMC_EMRS_0_WORD_COUNT                   0x1
+#define EMC_EMRS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_READ_MASK                    _MK_MASK_CONST(0xc0303fff)
+#define EMC_EMRS_0_WRITE_MASK                   _MK_MASK_CONST(0xc0303fff)
+// mode-register data to be written. 
+#define EMC_EMRS_0_EMRS_ADR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_EMRS_0_EMRS_ADR_FIELD                       (_MK_MASK_CONST(0x3fff) << EMC_EMRS_0_EMRS_ADR_SHIFT)
+#define EMC_EMRS_0_EMRS_ADR_RANGE                       13:0
+#define EMC_EMRS_0_EMRS_ADR_WOFFSET                     0x0
+#define EMC_EMRS_0_EMRS_ADR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_ADR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Set to 0x1 for EMRS (and where applicable, 0x2 for EMRS2, and 0x3 for EMRS3).
+#define EMC_EMRS_0_EMRS_BA_SHIFT                        _MK_SHIFT_CONST(20)
+#define EMC_EMRS_0_EMRS_BA_FIELD                        (_MK_MASK_CONST(0x3) << EMC_EMRS_0_EMRS_BA_SHIFT)
+#define EMC_EMRS_0_EMRS_BA_RANGE                        21:20
+#define EMC_EMRS_0_EMRS_BA_WOFFSET                      0x0
+#define EMC_EMRS_0_EMRS_BA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_BA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// active low chip-select, 0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for only dev1.
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_SHIFT                       _MK_SHIFT_CONST(30)
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_FIELD                       (_MK_MASK_CONST(0x3) << EMC_EMRS_0_EMRS_DEV_SELECTN_SHIFT)
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_RANGE                       31:30
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_WOFFSET                     0x0
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_EMRS_0_EMRS_DEV_SELECTN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_REF_0  // Command trigger: Refresh
+#define EMC_REF_0                       _MK_ADDR_CONST(0xd4)
+#define EMC_REF_0_SECURE                        0x0
+#define EMC_REF_0_WORD_COUNT                    0x1
+#define EMC_REF_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_REF_0_RESET_MASK                    _MK_MASK_CONST(0xff01)
+#define EMC_REF_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_REF_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_READ_MASK                     _MK_MASK_CONST(0xff01)
+#define EMC_REF_0_WRITE_MASK                    _MK_MASK_CONST(0xff01)
+// causes the hardware to perform a REFRESH to all DRAM banks.
+#define EMC_REF_0_REF_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_REF_0_REF_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_REF_0_REF_CMD_SHIFT)
+#define EMC_REF_0_REF_CMD_RANGE                 0:0
+#define EMC_REF_0_REF_CMD_WOFFSET                       0x0
+#define EMC_REF_0_REF_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_REF_0_REF_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// perform (REF_NUM + 1) refresh cycles.
+#define EMC_REF_0_REF_NUM_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_REF_0_REF_NUM_FIELD                 (_MK_MASK_CONST(0xff) << EMC_REF_0_REF_NUM_SHIFT)
+#define EMC_REF_0_REF_NUM_RANGE                 15:8
+#define EMC_REF_0_REF_NUM_WOFFSET                       0x0
+#define EMC_REF_0_REF_NUM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_NUM_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_REF_0_REF_NUM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_REF_0_REF_NUM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_PRE_0  // Command trigger: Precharge-All
+#define EMC_PRE_0                       _MK_ADDR_CONST(0xd8)
+#define EMC_PRE_0_SECURE                        0x0
+#define EMC_PRE_0_WORD_COUNT                    0x1
+#define EMC_PRE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_READ_MASK                     _MK_MASK_CONST(0xc0000001)
+#define EMC_PRE_0_WRITE_MASK                    _MK_MASK_CONST(0xc0000001)
+// causes the hardware to perform a PRECHARGE to all DRAM banks.
+#define EMC_PRE_0_PRE_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_PRE_0_PRE_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_PRE_0_PRE_CMD_SHIFT)
+#define EMC_PRE_0_PRE_CMD_RANGE                 0:0
+#define EMC_PRE_0_PRE_CMD_WOFFSET                       0x0
+#define EMC_PRE_0_PRE_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_PRE_0_PRE_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// active low chip-select, 0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for only dev1.
+#define EMC_PRE_0_PRE_DEV_SELECTN_SHIFT                 _MK_SHIFT_CONST(30)
+#define EMC_PRE_0_PRE_DEV_SELECTN_FIELD                 (_MK_MASK_CONST(0x3) << EMC_PRE_0_PRE_DEV_SELECTN_SHIFT)
+#define EMC_PRE_0_PRE_DEV_SELECTN_RANGE                 31:30
+#define EMC_PRE_0_PRE_DEV_SELECTN_WOFFSET                       0x0
+#define EMC_PRE_0_PRE_DEV_SELECTN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_DEV_SELECTN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_DEV_SELECTN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_PRE_0_PRE_DEV_SELECTN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_NOP_0  // Command trigger: NOP
+#define EMC_NOP_0                       _MK_ADDR_CONST(0xdc)
+#define EMC_NOP_0_SECURE                        0x0
+#define EMC_NOP_0_WORD_COUNT                    0x1
+#define EMC_NOP_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+// causes the hardware to perform a NOP to all DRAM banks.
+#define EMC_NOP_0_NOP_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_NOP_0_NOP_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_NOP_0_NOP_CMD_SHIFT)
+#define EMC_NOP_0_NOP_CMD_RANGE                 0:0
+#define EMC_NOP_0_NOP_CMD_WOFFSET                       0x0
+#define EMC_NOP_0_NOP_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_NOP_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_NOP_0_NOP_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_NOP_0_NOP_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_SELF_REF_0  // Command trigger: SELF REFRESH
+#define EMC_SELF_REF_0                  _MK_ADDR_CONST(0xe0)
+#define EMC_SELF_REF_0_SECURE                   0x0
+#define EMC_SELF_REF_0_WORD_COUNT                       0x1
+#define EMC_SELF_REF_0_RESET_VAL                        _MK_MASK_CONST(0xc0000000)
+#define EMC_SELF_REF_0_RESET_MASK                       _MK_MASK_CONST(0xc0000001)
+#define EMC_SELF_REF_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_READ_MASK                        _MK_MASK_CONST(0xc0000001)
+#define EMC_SELF_REF_0_WRITE_MASK                       _MK_MASK_CONST(0xc0000001)
+// causes the hardware to issue a SELF_REFRESH command. While CMD:ENABLED, the CKE pin is held deasserted. The CMD:ENABLED state will override the PIN:CKE setting.
+// The DRAM will ignore all accesses until CMD:DISABLED.
+#define EMC_SELF_REF_0_SELF_REF_CMD_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_FIELD                       (_MK_MASK_CONST(0x1) << EMC_SELF_REF_0_SELF_REF_CMD_SHIFT)
+#define EMC_SELF_REF_0_SELF_REF_CMD_RANGE                       0:0
+#define EMC_SELF_REF_0_SELF_REF_CMD_WOFFSET                     0x0
+#define EMC_SELF_REF_0_SELF_REF_CMD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_SELF_REF_0_SELF_REF_CMD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_INIT_ENUM                   DISABLED
+#define EMC_SELF_REF_0_SELF_REF_CMD_DISABLED                    _MK_ENUM_CONST(0)
+#define EMC_SELF_REF_0_SELF_REF_CMD_ENABLED                     _MK_ENUM_CONST(1)
+
+// active low chip-select, 0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for only dev1, 0x3 for neither device.
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_SHIFT                   _MK_SHIFT_CONST(30)
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_FIELD                   (_MK_MASK_CONST(0x3) << EMC_SELF_REF_0_SREF_DEV_SELECTN_SHIFT)
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_RANGE                   31:30
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_WOFFSET                 0x0
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_DEFAULT                 _MK_MASK_CONST(0x3)
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_SELF_REF_0_SREF_DEV_SELECTN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DPD_0  // Command trigger: Deep Power Down
+#define EMC_DPD_0                       _MK_ADDR_CONST(0xe4)
+#define EMC_DPD_0_SECURE                        0x0
+#define EMC_DPD_0_WORD_COUNT                    0x1
+#define EMC_DPD_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_READ_MASK                     _MK_MASK_CONST(0xc0000001)
+#define EMC_DPD_0_WRITE_MASK                    _MK_MASK_CONST(0xc0000001)
+// causes the hardware to issue the deep power down command (Burst Terminate w/ cke low). While in DPD mode, the DRAM will not maintain data integrity.
+// While CMD:ENABLED, the CKE pin is held deasserted. The CMD:ENABLED state will override the PIN:CKE setting.
+// The DRAM will ignore all accesses until CMD:DISABLED.
+#define EMC_DPD_0_DPD_CMD_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_DPD_0_DPD_CMD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DPD_0_DPD_CMD_SHIFT)
+#define EMC_DPD_0_DPD_CMD_RANGE                 0:0
+#define EMC_DPD_0_DPD_CMD_WOFFSET                       0x0
+#define EMC_DPD_0_DPD_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_DPD_0_DPD_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_CMD_INIT_ENUM                     DISABLED
+#define EMC_DPD_0_DPD_CMD_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_DPD_0_DPD_CMD_ENABLED                       _MK_ENUM_CONST(1)
+
+// active low chip-select, 0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for only dev1.
+#define EMC_DPD_0_DPD_DEV_SELECTN_SHIFT                 _MK_SHIFT_CONST(30)
+#define EMC_DPD_0_DPD_DEV_SELECTN_FIELD                 (_MK_MASK_CONST(0x3) << EMC_DPD_0_DPD_DEV_SELECTN_SHIFT)
+#define EMC_DPD_0_DPD_DEV_SELECTN_RANGE                 31:30
+#define EMC_DPD_0_DPD_DEV_SELECTN_WOFFSET                       0x0
+#define EMC_DPD_0_DPD_DEV_SELECTN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_DEV_SELECTN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_DEV_SELECTN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DPD_0_DPD_DEV_SELECTN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_MRW_0  // Command trigger: MRW
+#define EMC_MRW_0                       _MK_ADDR_CONST(0xe8)
+#define EMC_MRW_0_SECURE                        0x0
+#define EMC_MRW_0_WORD_COUNT                    0x1
+#define EMC_MRW_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_READ_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_WRITE_MASK                    _MK_MASK_CONST(0xc0ff00ff)
+// data to be written
+#define EMC_MRW_0_MRW_OP_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_MRW_0_MRW_OP_FIELD                  (_MK_MASK_CONST(0xff) << EMC_MRW_0_MRW_OP_SHIFT)
+#define EMC_MRW_0_MRW_OP_RANGE                  7:0
+#define EMC_MRW_0_MRW_OP_WOFFSET                        0x0
+#define EMC_MRW_0_MRW_OP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_OP_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_OP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_OP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// register address
+#define EMC_MRW_0_MRW_MA_SHIFT                  _MK_SHIFT_CONST(16)
+#define EMC_MRW_0_MRW_MA_FIELD                  (_MK_MASK_CONST(0xff) << EMC_MRW_0_MRW_MA_SHIFT)
+#define EMC_MRW_0_MRW_MA_RANGE                  23:16
+#define EMC_MRW_0_MRW_MA_WOFFSET                        0x0
+#define EMC_MRW_0_MRW_MA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_MA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_MA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_MA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// active-low chip-select,  0x0 applies command to both devices, 0x2 to for only dev0, 0x1 for dev1.
+#define EMC_MRW_0_MRW_DEV_SELECTN_SHIFT                 _MK_SHIFT_CONST(30)
+#define EMC_MRW_0_MRW_DEV_SELECTN_FIELD                 (_MK_MASK_CONST(0x3) << EMC_MRW_0_MRW_DEV_SELECTN_SHIFT)
+#define EMC_MRW_0_MRW_DEV_SELECTN_RANGE                 31:30
+#define EMC_MRW_0_MRW_DEV_SELECTN_WOFFSET                       0x0
+#define EMC_MRW_0_MRW_DEV_SELECTN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_DEV_SELECTN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_DEV_SELECTN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_MRW_0_MRW_DEV_SELECTN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_MRR_0  // Command trigger: MRR
+#define EMC_MRR_0                       _MK_ADDR_CONST(0xec)
+#define EMC_MRR_0_SECURE                        0x0
+#define EMC_MRR_0_WORD_COUNT                    0x1
+#define EMC_MRR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define EMC_MRR_0_WRITE_MASK                    _MK_MASK_CONST(0xc0ff0000)
+// data returned
+#define EMC_MRR_0_MRR_DATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_MRR_0_MRR_DATA_FIELD                        (_MK_MASK_CONST(0xffff) << EMC_MRR_0_MRR_DATA_SHIFT)
+#define EMC_MRR_0_MRR_DATA_RANGE                        15:0
+#define EMC_MRR_0_MRR_DATA_WOFFSET                      0x0
+#define EMC_MRR_0_MRR_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// register address
+#define EMC_MRR_0_MRR_MA_SHIFT                  _MK_SHIFT_CONST(16)
+#define EMC_MRR_0_MRR_MA_FIELD                  (_MK_MASK_CONST(0xff) << EMC_MRR_0_MRR_MA_SHIFT)
+#define EMC_MRR_0_MRR_MA_RANGE                  23:16
+#define EMC_MRR_0_MRR_MA_WOFFSET                        0x0
+#define EMC_MRR_0_MRR_MA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_MA_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_MA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_MA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// active-low chip-select, choose which device to send the command to. (enum for safety).
+#define EMC_MRR_0_MRR_DEV_SELECTN_SHIFT                 _MK_SHIFT_CONST(30)
+#define EMC_MRR_0_MRR_DEV_SELECTN_FIELD                 (_MK_MASK_CONST(0x3) << EMC_MRR_0_MRR_DEV_SELECTN_SHIFT)
+#define EMC_MRR_0_MRR_DEV_SELECTN_RANGE                 31:30
+#define EMC_MRR_0_MRR_DEV_SELECTN_WOFFSET                       0x0
+#define EMC_MRR_0_MRR_DEV_SELECTN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DEV_SELECTN_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DEV_SELECTN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DEV_SELECTN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_MRR_0_MRR_DEV_SELECTN_ILLEGAL                       _MK_ENUM_CONST(0)
+#define EMC_MRR_0_MRR_DEV_SELECTN_DEV1                  _MK_ENUM_CONST(1)
+#define EMC_MRR_0_MRR_DEV_SELECTN_DEV0                  _MK_ENUM_CONST(2)
+#define EMC_MRR_0_MRR_DEV_SELECTN_RESERVED                      _MK_ENUM_CONST(3)
+
+
+// Register EMC_CMDQ_0  // Command Queue Depth register
+#define EMC_CMDQ_0                      _MK_ADDR_CONST(0xf0)
+#define EMC_CMDQ_0_SECURE                       0x0
+#define EMC_CMDQ_0_WORD_COUNT                   0x1
+#define EMC_CMDQ_0_RESET_VAL                    _MK_MASK_CONST(0x10004408)
+#define EMC_CMDQ_0_RESET_MASK                   _MK_MASK_CONST(0x1f00771f)
+#define EMC_CMDQ_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_READ_MASK                    _MK_MASK_CONST(0x1f00771f)
+#define EMC_CMDQ_0_WRITE_MASK                   _MK_MASK_CONST(0x1f00771f)
+#define EMC_CMDQ_0_RW_DEPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_CMDQ_0_RW_DEPTH_FIELD                       (_MK_MASK_CONST(0x1f) << EMC_CMDQ_0_RW_DEPTH_SHIFT)
+#define EMC_CMDQ_0_RW_DEPTH_RANGE                       4:0
+#define EMC_CMDQ_0_RW_DEPTH_WOFFSET                     0x0
+#define EMC_CMDQ_0_RW_DEPTH_DEFAULT                     _MK_MASK_CONST(0x8)
+#define EMC_CMDQ_0_RW_DEPTH_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define EMC_CMDQ_0_RW_DEPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_RW_DEPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_CMDQ_0_ACT_DEPTH_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_CMDQ_0_ACT_DEPTH_FIELD                      (_MK_MASK_CONST(0x7) << EMC_CMDQ_0_ACT_DEPTH_SHIFT)
+#define EMC_CMDQ_0_ACT_DEPTH_RANGE                      10:8
+#define EMC_CMDQ_0_ACT_DEPTH_WOFFSET                    0x0
+#define EMC_CMDQ_0_ACT_DEPTH_DEFAULT                    _MK_MASK_CONST(0x4)
+#define EMC_CMDQ_0_ACT_DEPTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_CMDQ_0_ACT_DEPTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_ACT_DEPTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_CMDQ_0_PRE_DEPTH_SHIFT                      _MK_SHIFT_CONST(12)
+#define EMC_CMDQ_0_PRE_DEPTH_FIELD                      (_MK_MASK_CONST(0x7) << EMC_CMDQ_0_PRE_DEPTH_SHIFT)
+#define EMC_CMDQ_0_PRE_DEPTH_RANGE                      14:12
+#define EMC_CMDQ_0_PRE_DEPTH_WOFFSET                    0x0
+#define EMC_CMDQ_0_PRE_DEPTH_DEFAULT                    _MK_MASK_CONST(0x4)
+#define EMC_CMDQ_0_PRE_DEPTH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_CMDQ_0_PRE_DEPTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_PRE_DEPTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_CMDQ_0_RW_WD_DEPTH_SHIFT                    _MK_SHIFT_CONST(24)
+#define EMC_CMDQ_0_RW_WD_DEPTH_FIELD                    (_MK_MASK_CONST(0x1f) << EMC_CMDQ_0_RW_WD_DEPTH_SHIFT)
+#define EMC_CMDQ_0_RW_WD_DEPTH_RANGE                    28:24
+#define EMC_CMDQ_0_RW_WD_DEPTH_WOFFSET                  0x0
+#define EMC_CMDQ_0_RW_WD_DEPTH_DEFAULT                  _MK_MASK_CONST(0x10)
+#define EMC_CMDQ_0_RW_WD_DEPTH_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define EMC_CMDQ_0_RW_WD_DEPTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CMDQ_0_RW_WD_DEPTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_CFG1_0  // FBIO configuration register
+#define EMC_FBIO_CFG1_0                 _MK_ADDR_CONST(0xf4)
+#define EMC_FBIO_CFG1_0_SECURE                  0x0
+#define EMC_FBIO_CFG1_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_RESET_MASK                      _MK_MASK_CONST(0x10000)
+#define EMC_FBIO_CFG1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_READ_MASK                       _MK_MASK_CONST(0x10000)
+#define EMC_FBIO_CFG1_0_WRITE_MASK                      _MK_MASK_CONST(0x10000)
+// determines whether the output enable is the same width as data (DEN_EARLY=0) or 1/2 bit time wider on either end (DEN_EARLY=1).
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_FIELD                     (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SHIFT)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_RANGE                     16:16
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_WOFFSET                   0x0
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_INIT_ENUM                 DISABLE
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DISABLE                   _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG1_0_CFG_DEN_EARLY_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_FBIO_DQSIB_DLY_0  // FBIO configuration register
+#define EMC_FBIO_DQSIB_DLY_0                    _MK_ADDR_CONST(0xf8)
+#define EMC_FBIO_DQSIB_DLY_0_SECURE                     0x0
+#define EMC_FBIO_DQSIB_DLY_0_WORD_COUNT                         0x1
+#define EMC_FBIO_DQSIB_DLY_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_DQSIB_DLY_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_RANGE                 7:0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_RANGE                 15:8
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_RANGE                 23:16
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_RANGE                 31:24
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_DQSIB_DLY_MSB_0  // FBIO configuration register
+#define EMC_FBIO_DQSIB_DLY_MSB_0                        _MK_ADDR_CONST(0xfc)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_SECURE                         0x0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_WORD_COUNT                     0x1
+#define EMC_FBIO_DQSIB_DLY_MSB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_FIELD                 (_MK_MASK_CONST(0x3) << EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_RANGE                 1:0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_FIELD                 (_MK_MASK_CONST(0x3) << EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_RANGE                 9:8
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_FIELD                 (_MK_MASK_CONST(0x3) << EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_RANGE                 17:16
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_FIELD                 (_MK_MASK_CONST(0x3) << EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_SHIFT)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_RANGE                 25:24
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_WOFFSET                       0x0
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_SPARE_0  // FBIO spare register
+#define EMC_FBIO_SPARE_0                        _MK_ADDR_CONST(0x100)
+#define EMC_FBIO_SPARE_0_SECURE                         0x0
+#define EMC_FBIO_SPARE_0_WORD_COUNT                     0x1
+#define EMC_FBIO_SPARE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SHIFT)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_RANGE                   31:0
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WOFFSET                 0x0
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_CFG5_0  // FBIO configuration Register 
+#define EMC_FBIO_CFG5_0                 _MK_ADDR_CONST(0x104)
+#define EMC_FBIO_CFG5_0_SECURE                  0x0
+#define EMC_FBIO_CFG5_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG5_0_RESET_VAL                       _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_RESET_MASK                      _MK_MASK_CONST(0x793)
+#define EMC_FBIO_CFG5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_READ_MASK                       _MK_MASK_CONST(0x793)
+#define EMC_FBIO_CFG5_0_WRITE_MASK                      _MK_MASK_CONST(0x793)
+// specifies which DRAM protocol to use for the attached device(s).
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_FIELD                 (_MK_MASK_CONST(0x3) << EMC_FBIO_CFG5_0_DRAM_TYPE_SHIFT)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_RANGE                 1:0
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_WOFFSET                       0x0
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_INIT_ENUM                     DDR1
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_RESERVED                      _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DDR1                  _MK_ENUM_CONST(1)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2                        _MK_ENUM_CONST(2)
+#define EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2                  _MK_ENUM_CONST(3)
+
+//  specifies whether the DRAM data-bus is 16-bits or 32-bits wide.
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SHIFT                        _MK_SHIFT_CONST(4)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_FIELD                        (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DRAM_WIDTH_SHIFT)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_RANGE                        4:4
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_WOFFSET                      0x0
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_INIT_ENUM                    X32
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_X32                  _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DRAM_WIDTH_X16                  _MK_ENUM_CONST(1)
+
+// enables differential signalling on dqs strobes (lpddr2/ddr2 options)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_SHIFT                  _MK_SHIFT_CONST(7)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_FIELD                  (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_SHIFT)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_RANGE                  7:7
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_WOFFSET                        0x0
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_INIT_ENUM                      DISABLED
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_DISABLED                       _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_ENABLED                        _MK_ENUM_CONST(1)
+
+// enables CTT_TERMINATION mode in pads (ddr2 support)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_FIELD                   (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_CTT_TERMINATION_SHIFT)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_RANGE                   8:8
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_WOFFSET                 0x0
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_INIT_ENUM                       DISABLED
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_CTT_TERMINATION_ENABLED                 _MK_ENUM_CONST(1)
+
+// enables pulldowns on dqs lines (and pullups on DQS_N if DIFFERENTIAL_DQS).
+#define EMC_FBIO_CFG5_0_DQS_PULLD_SHIFT                 _MK_SHIFT_CONST(9)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_FIELD                 (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DQS_PULLD_SHIFT)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_RANGE                 9:9
+#define EMC_FBIO_CFG5_0_DQS_PULLD_WOFFSET                       0x0
+#define EMC_FBIO_CFG5_0_DQS_PULLD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_INIT_ENUM                     DISABLED
+#define EMC_FBIO_CFG5_0_DQS_PULLD_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DQS_PULLD_ENABLED                       _MK_ENUM_CONST(1)
+
+// disables reads/writes to a device until the precharge command has been issued by the dram internally.
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_SHIFT                        _MK_SHIFT_CONST(10)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_FIELD                        (_MK_MASK_CONST(0x1) << EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_SHIFT)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_RANGE                        10:10
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_WOFFSET                      0x0
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_INIT_ENUM                    DISABLED
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_DISABLED                     _MK_ENUM_CONST(0)
+#define EMC_FBIO_CFG5_0_DISABLE_CONCURRENT_AUTOPRE_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Register EMC_FBIO_WRPTR_EQ_2_0  // FBIO wrptr register
+#define EMC_FBIO_WRPTR_EQ_2_0                   _MK_ADDR_CONST(0x108)
+#define EMC_FBIO_WRPTR_EQ_2_0_SECURE                    0x0
+#define EMC_FBIO_WRPTR_EQ_2_0_WORD_COUNT                        0x1
+#define EMC_FBIO_WRPTR_EQ_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define EMC_FBIO_WRPTR_EQ_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_FIELD                       (_MK_MASK_CONST(0xf) << EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SHIFT)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_RANGE                       3:0
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_WOFFSET                     0x0
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_WRPTR_EQ_2_0_FB_WRPTR_EQ_2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_QUSE_DLY_0  // FBIO configuration register
+#define EMC_FBIO_QUSE_DLY_0                     _MK_ADDR_CONST(0x10c)
+#define EMC_FBIO_QUSE_DLY_0_SECURE                      0x0
+#define EMC_FBIO_QUSE_DLY_0_WORD_COUNT                  0x1
+#define EMC_FBIO_QUSE_DLY_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_QUSE_DLY_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_RANGE                   7:0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_RANGE                   15:8
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_RANGE                   23:16
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SHIFT)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_RANGE                   31:24
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_QUSE_DLY_MSB_0  // FBIO configuration register
+#define EMC_FBIO_QUSE_DLY_MSB_0                 _MK_ADDR_CONST(0x110)
+#define EMC_FBIO_QUSE_DLY_MSB_0_SECURE                  0x0
+#define EMC_FBIO_QUSE_DLY_MSB_0_WORD_COUNT                      0x1
+#define EMC_FBIO_QUSE_DLY_MSB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_QUSE_DLY_MSB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_QUSE_DLY_MSB_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_FIELD                   (_MK_MASK_CONST(0x3) << EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_SHIFT)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_RANGE                   1:0
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_FIELD                   (_MK_MASK_CONST(0x3) << EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_SHIFT)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_RANGE                   9:8
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_FIELD                   (_MK_MASK_CONST(0x3) << EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_SHIFT)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_RANGE                   17:16
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_FIELD                   (_MK_MASK_CONST(0x3) << EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_SHIFT)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_RANGE                   25:24
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_WOFFSET                 0x0
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_FBIO_CFG6_0  // FBIO configuration register   
+#define EMC_FBIO_CFG6_0                 _MK_ADDR_CONST(0x114)
+#define EMC_FBIO_CFG6_0_SECURE                  0x0
+#define EMC_FBIO_CFG6_0_WORD_COUNT                      0x1
+#define EMC_FBIO_CFG6_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define EMC_FBIO_CFG6_0_RESET_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_READ_MASK                       _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_WRITE_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_FIELD                     (_MK_MASK_CONST(0x7) << EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SHIFT)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_RANGE                     2:0
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_WOFFSET                   0x0
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_DEFAULT                   _MK_MASK_CONST(0x2)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Register EMC_DQS_TRIMMER_RD0_0  
+#define EMC_DQS_TRIMMER_RD0_0                   _MK_ADDR_CONST(0x120)
+#define EMC_DQS_TRIMMER_RD0_0_SECURE                    0x0
+#define EMC_DQS_TRIMMER_RD0_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_READ_MASK                         _MK_MASK_CONST(0x3ff03ff)
+#define EMC_DQS_TRIMMER_RD0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_FIELD                        (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_RANGE                        9:0
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_WOFFSET                      0x0
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_QUSE_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_FIELD                 (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SHIFT)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_RANGE                 25:16
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD0_0_DQS_CURRENT_TRIM_VAL_BYTE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD1_0  
+#define EMC_DQS_TRIMMER_RD1_0                   _MK_ADDR_CONST(0x124)
+#define EMC_DQS_TRIMMER_RD1_0_SECURE                    0x0
+#define EMC_DQS_TRIMMER_RD1_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_READ_MASK                         _MK_MASK_CONST(0x3ff03ff)
+#define EMC_DQS_TRIMMER_RD1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_FIELD                        (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_RANGE                        9:0
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_WOFFSET                      0x0
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_QUSE_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_FIELD                 (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SHIFT)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_RANGE                 25:16
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD1_0_DQS_CURRENT_TRIM_VAL_BYTE_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD2_0  
+#define EMC_DQS_TRIMMER_RD2_0                   _MK_ADDR_CONST(0x128)
+#define EMC_DQS_TRIMMER_RD2_0_SECURE                    0x0
+#define EMC_DQS_TRIMMER_RD2_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_READ_MASK                         _MK_MASK_CONST(0x3ff03ff)
+#define EMC_DQS_TRIMMER_RD2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_FIELD                        (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_RANGE                        9:0
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_WOFFSET                      0x0
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_QUSE_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_FIELD                 (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SHIFT)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_RANGE                 25:16
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD2_0_DQS_CURRENT_TRIM_VAL_BYTE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DQS_TRIMMER_RD3_0  
+#define EMC_DQS_TRIMMER_RD3_0                   _MK_ADDR_CONST(0x12c)
+#define EMC_DQS_TRIMMER_RD3_0_SECURE                    0x0
+#define EMC_DQS_TRIMMER_RD3_0_WORD_COUNT                        0x1
+#define EMC_DQS_TRIMMER_RD3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_READ_MASK                         _MK_MASK_CONST(0x3ff03ff)
+#define EMC_DQS_TRIMMER_RD3_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_FIELD                        (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_RANGE                        9:0
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_WOFFSET                      0x0
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_QUSE_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_FIELD                 (_MK_MASK_CONST(0x3ff) << EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SHIFT)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_RANGE                 25:16
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_WOFFSET                       0x0
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DQS_TRIMMER_RD3_0_DQS_CURRENT_TRIM_VAL_BYTE_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Register EMC_CLKEN_OVERRIDE_0  
+#define EMC_CLKEN_OVERRIDE_0                    _MK_ADDR_CONST(0x140)
+#define EMC_CLKEN_OVERRIDE_0_SECURE                     0x0
+#define EMC_CLKEN_OVERRIDE_0_WORD_COUNT                         0x1
+#define EMC_CLKEN_OVERRIDE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RESET_MASK                         _MK_MASK_CONST(0x7f)
+#define EMC_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_READ_MASK                  _MK_MASK_CONST(0x7f)
+#define EMC_CLKEN_OVERRIDE_0_WRITE_MASK                         _MK_MASK_CONST(0x7f)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_RANGE                        0:0
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_WOFFSET                      0x0
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_ARB_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SHIFT                       _MK_SHIFT_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_FIELD                       (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_RANGE                       1:1
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_WOFFSET                     0x0
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_INIT_ENUM                   CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_CLK_GATED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_CLK_ALWAYS_ON                       _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DISABLE                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_ENABLE                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_DISABLED                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_CMDQ_CLKEN_OVR_ENABLED                     _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SHIFT                      _MK_SHIFT_CONST(2)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_RANGE                      2:2
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_WOFFSET                    0x0
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_INIT_ENUM                  CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_CLK_GATED                  _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_CLK_ALWAYS_ON                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DISABLE                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_ENABLE                     _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_DRAMC_CLKEN_OVR_ENABLED                    _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(3)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_RANGE                 3:3
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_WOFFSET                       0x0
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_RR_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(4)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_RANGE                 4:4
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_WOFFSET                       0x0
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LL_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(5)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_RANGE                    5:5
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_WOFFSET                  0x0
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_DISABLE                  _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_ENABLE                   _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_LLSTATS_CLKEN_OVR_ENABLED                  _MK_ENUM_CONST(1)
+
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SHIFT                      _MK_SHIFT_CONST(6)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SHIFT)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_RANGE                      6:6
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_WOFFSET                    0x0
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_INIT_ENUM                  CLK_GATED
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_CLK_GATED                  _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_CLK_ALWAYS_ON                      _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DISABLE                    _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_ENABLE                     _MK_ENUM_CONST(1)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CLKEN_OVERRIDE_0_STATS_CLKEN_OVR_ENABLED                    _MK_ENUM_CONST(1)
+
+#define NV_MC_EMEM_DFIFO_DEPTH  4
+#define NV_MC_IMEM_DFIFO_DEPTH  5
+#define NV_MC_EMEM_APFIFO_DEPTH 5
+#define NV_MC_ARB_EMEM_REGLEVEL 3
+#define NV_MC_EMEM_REQ_ID_WIDEREQ       8
+#define NV_MC_EMEM_RDI_ID_WIDERDI       8
+#define NV_MC_EMEM_REQ_ID_ILLEGALACC    7
+#define NV_MC_EMEM_RDI_ID_ILLEGALACC    7
+#define NV_MC_EMEM_REQ_ID_LLRAWDECR     6
+#define NV_MC_EMEM_RDI_ID_LLRAWDECR     6
+#define NV_MC_EMEM_REQ_ID_APCIGNORE     5
+#define NV_MC_EMEM_RDI_ID_APCIGNORE     5
+
+// Packet MC2EMC
+#define MC2EMC_SIZE 186
+
+#define MC2EMC_WDO_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_SHIFT)
+#define MC2EMC_WDO_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_ROW                  0
+
+#define MC2EMC_WDO_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_0_SHIFT)
+#define MC2EMC_WDO_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_ROW                        0
+
+#define MC2EMC_WDO_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_1_SHIFT)
+#define MC2EMC_WDO_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_ROW                        0
+
+#define MC2EMC_WDO_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_2_SHIFT)
+#define MC2EMC_WDO_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_ROW                        0
+
+#define MC2EMC_WDO_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_3_SHIFT)
+#define MC2EMC_WDO_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_ROW                        0
+
+#define MC2EMC_BE_SHIFT                 _MK_SHIFT_CONST(128)
+#define MC2EMC_BE_FIELD                 (_MK_MASK_CONST(0xffff) << MC2EMC_BE_SHIFT)
+#define MC2EMC_BE_RANGE                 _MK_SHIFT_CONST(143):_MK_SHIFT_CONST(128)
+#define MC2EMC_BE_ROW                   0
+
+#define MC2EMC_ADR_SHIFT                        _MK_SHIFT_CONST(144)
+#define MC2EMC_ADR_FIELD                        (_MK_MASK_CONST(0x3ffffff) << MC2EMC_ADR_SHIFT)
+#define MC2EMC_ADR_RANGE                        _MK_SHIFT_CONST(169):_MK_SHIFT_CONST(144)
+#define MC2EMC_ADR_ROW                  0
+
+#define MC2EMC_REQ_ID_SHIFT                     _MK_SHIFT_CONST(170)
+#define MC2EMC_REQ_ID_FIELD                     (_MK_MASK_CONST(0x1ff) << MC2EMC_REQ_ID_SHIFT)
+#define MC2EMC_REQ_ID_RANGE                     _MK_SHIFT_CONST(178):_MK_SHIFT_CONST(170)
+#define MC2EMC_REQ_ID_ROW                       0
+
+#define MC2EMC_AP_SHIFT                 _MK_SHIFT_CONST(179)
+#define MC2EMC_AP_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_AP_SHIFT)
+#define MC2EMC_AP_RANGE                 _MK_SHIFT_CONST(179):_MK_SHIFT_CONST(179)
+#define MC2EMC_AP_ROW                   0
+
+#define MC2EMC_WE_SHIFT                 _MK_SHIFT_CONST(180)
+#define MC2EMC_WE_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_WE_SHIFT)
+#define MC2EMC_WE_RANGE                 _MK_SHIFT_CONST(180):_MK_SHIFT_CONST(180)
+#define MC2EMC_WE_ROW                   0
+
+#define MC2EMC_TAG_SHIFT                        _MK_SHIFT_CONST(181)
+#define MC2EMC_TAG_FIELD                        (_MK_MASK_CONST(0x1f) << MC2EMC_TAG_SHIFT)
+#define MC2EMC_TAG_RANGE                        _MK_SHIFT_CONST(185):_MK_SHIFT_CONST(181)
+#define MC2EMC_TAG_ROW                  0
+
+
+// Packet MC2EMC_APC
+#define MC2EMC_APC_SIZE 3
+
+#define MC2EMC_APC_CLR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_FIELD                    (_MK_MASK_CONST(0x1) << MC2EMC_APC_CLR_SHIFT)
+#define MC2EMC_APC_CLR_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_ROW                      0
+
+#define MC2EMC_APC_BANK_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_FIELD                   (_MK_MASK_CONST(0x3) << MC2EMC_APC_BANK_SHIFT)
+#define MC2EMC_APC_BANK_RANGE                   _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_ROW                     0
+
+
+// Packet EMC2MC
+#define EMC2MC_SIZE 137
+
+#define EMC2MC_RDI_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_SHIFT)
+#define EMC2MC_RDI_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_ROW                  0
+
+#define EMC2MC_RDI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_0_SHIFT)
+#define EMC2MC_RDI_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_ROW                        0
+
+#define EMC2MC_RDI_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_1_SHIFT)
+#define EMC2MC_RDI_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_ROW                        0
+
+#define EMC2MC_RDI_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_2_SHIFT)
+#define EMC2MC_RDI_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_ROW                        0
+
+#define EMC2MC_RDI_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_3_SHIFT)
+#define EMC2MC_RDI_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_ROW                        0
+
+#define EMC2MC_RDI_ID_SHIFT                     _MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_FIELD                     (_MK_MASK_CONST(0x1ff) << EMC2MC_RDI_ID_SHIFT)
+#define EMC2MC_RDI_ID_RANGE                     _MK_SHIFT_CONST(136):_MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_ROW                       0
+
+
+// Packet MC2EMC_LL
+#define MC2EMC_LL_SIZE 33
+
+#define MC2EMC_LL_ADR_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ADR_FIELD                     (_MK_MASK_CONST(0x7ffffff) << MC2EMC_LL_ADR_SHIFT)
+#define MC2EMC_LL_ADR_RANGE                     _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ADR_ROW                       0
+
+#define MC2EMC_LL_TAG_SHIFT                     _MK_SHIFT_CONST(27)
+#define MC2EMC_LL_TAG_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_TAG_SHIFT)
+#define MC2EMC_LL_TAG_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(27)
+#define MC2EMC_LL_TAG_ROW                       0
+
+#define MC2EMC_LL_DOUBLEREQ_SHIFT                       _MK_SHIFT_CONST(32)
+#define MC2EMC_LL_DOUBLEREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC2EMC_LL_DOUBLEREQ_SHIFT)
+#define MC2EMC_LL_DOUBLEREQ_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define MC2EMC_LL_DOUBLEREQ_ROW                 0
+
+
+// Packet EMC2MC_LL
+#define EMC2MC_LL_SIZE 64
+
+#define EMC2MC_LL_RDI_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_FIELD                     (_MK_MASK_CONST(0xffffffff) << EMC2MC_LL_RDI_SHIFT)
+#define EMC2MC_LL_RDI_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_ROW                       0
+
+
+// Packet MC2EMC_LL_CRITINFO
+#define MC2EMC_LL_CRITINFO_SIZE 11
+
+#define MC2EMC_LL_CRITINFO_HP_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_CRITINFO_HP_SHIFT)
+#define MC2EMC_LL_CRITINFO_HP_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_ROW                       0
+
+#define MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_FIELD                        (_MK_MASK_CONST(0x3f) << MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_RANGE                        _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_ROW                  0
+
+
+// Packet MC2EMC_LL_ARBINFO
+#define MC2EMC_LL_ARBINFO_SIZE 2
+
+#define MC2EMC_LL_ARBINFO_BANK_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_ARBINFO_BANK_SHIFT)
+#define MC2EMC_LL_ARBINFO_BANK_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_ROW                      0
+
+
+// Packet CMC2MC_AXI_A
+#define CMC2MC_AXI_A_SIZE 63
+
+#define CMC2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_A_AADDR_SHIFT)
+#define CMC2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_ROW                  0
+
+#define CMC2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_A_AID_SHIFT)
+#define CMC2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_ROW                    0
+
+#define CMC2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define CMC2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ALEN_SHIFT)
+#define CMC2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define CMC2MC_AXI_A_ALEN_ROW                   0
+#define CMC2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define CMC2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define CMC2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define CMC2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define CMC2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_ASIZE_SHIFT)
+#define CMC2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ASIZE_ROW                  0
+#define CMC2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define CMC2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define CMC2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ABURST_SHIFT)
+#define CMC2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define CMC2MC_AXI_A_ABURST_ROW                 0
+#define CMC2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define CMC2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ALOCK_SHIFT)
+#define CMC2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define CMC2MC_AXI_A_ALOCK_ROW                  0
+#define CMC2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define CMC2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ACACHE_SHIFT)
+#define CMC2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define CMC2MC_AXI_A_ACACHE_ROW                 0
+#define CMC2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define CMC2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_APROT_SHIFT)
+#define CMC2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define CMC2MC_AXI_A_APROT_ROW                  0
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet CMC2MC_AXI_W
+#define CMC2MC_AXI_W_SIZE 86
+
+#define CMC2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_W_WDATA_SHIFT)
+#define CMC2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_ROW                  0
+
+#define CMC2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_W_WID_SHIFT)
+#define CMC2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_ROW                    0
+
+#define CMC2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WSTRB_SHIFT)
+#define CMC2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(84):_MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_W_WSTRB_ROW                  0
+
+#define CMC2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(85)
+#define CMC2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_W_WLAST_SHIFT)
+#define CMC2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(85):_MK_SHIFT_CONST(85)
+#define CMC2MC_AXI_W_WLAST_ROW                  0
+#define CMC2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet CMC2MC_AXI_B
+#define CMC2MC_AXI_B_SIZE 15
+
+#define CMC2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_B_BID_SHIFT)
+#define CMC2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_ROW                    0
+
+#define CMC2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(13)
+#define CMC2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_B_BRESP_SHIFT)
+#define CMC2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define CMC2MC_AXI_B_BRESP_ROW                  0
+#define CMC2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet CMC2MC_AXI_R
+#define CMC2MC_AXI_R_SIZE 80
+
+#define CMC2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_R_RDATA_SHIFT)
+#define CMC2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_ROW                  0
+
+#define CMC2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_R_RID_SHIFT)
+#define CMC2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_ROW                    0
+
+#define CMC2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_R_RRESP_SHIFT)
+#define CMC2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(78):_MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_R_RRESP_ROW                  0
+#define CMC2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(79)
+#define CMC2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_R_RLAST_SHIFT)
+#define CMC2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(79)
+#define CMC2MC_AXI_R_RLAST_ROW                  0
+#define CMC2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_A
+#define MSELECT2MC_AXI_A_SIZE 63
+
+#define MSELECT2MC_AXI_A_AADDR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_A_AADDR_SHIFT)
+#define MSELECT2MC_AXI_A_AADDR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_ROW                      0
+
+#define MSELECT2MC_AXI_A_AID_SHIFT                      _MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_A_AID_SHIFT)
+#define MSELECT2MC_AXI_A_AID_RANGE                      _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_ROW                        0
+
+#define MSELECT2MC_AXI_A_ALEN_SHIFT                     _MK_SHIFT_CONST(45)
+#define MSELECT2MC_AXI_A_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ALEN_SHIFT)
+#define MSELECT2MC_AXI_A_ALEN_RANGE                     _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define MSELECT2MC_AXI_A_ALEN_ROW                       0
+#define MSELECT2MC_AXI_A_ALEN_ONEDATA                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALEN_TWODATA                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALEN_THREEDATA                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALEN_FOURDATA                  _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ALEN_FIVEDATA                  _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ALEN_SIXDATA                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ALEN_SEVENDATA                 _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ALEN_EIGHTDATA                 _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ALEN_NINEDATA                  _MK_ENUM_CONST(8)
+#define MSELECT2MC_AXI_A_ALEN_TENDATA                   _MK_ENUM_CONST(9)
+#define MSELECT2MC_AXI_A_ALEN_ELEVENDATA                        _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ALEN_TWELVEDATA                        _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ALEN_THIRTEENDATA                      _MK_ENUM_CONST(12)
+#define MSELECT2MC_AXI_A_ALEN_FOURTEENDATA                      _MK_ENUM_CONST(13)
+#define MSELECT2MC_AXI_A_ALEN_FIFTHTEENDATA                     _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ALEN_SIXTEENDATA                       _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_ASIZE_SHIFT                    _MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_ASIZE_SHIFT)
+#define MSELECT2MC_AXI_A_ASIZE_RANGE                    _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ASIZE_ROW                      0
+#define MSELECT2MC_AXI_A_ASIZE_ONEBYTE                  _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ASIZE_TWOBYTES                 _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ASIZE_FOURBYTES                        _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ASIZE_EIGHTBYTES                       _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTEENBYTES                     _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ASIZE_THIRTYTWOBYTES                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTYFOURBYTES                   _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                       _MK_ENUM_CONST(7)
+
+#define MSELECT2MC_AXI_A_ABURST_SHIFT                   _MK_SHIFT_CONST(52)
+#define MSELECT2MC_AXI_A_ABURST_FIELD                   (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ABURST_SHIFT)
+#define MSELECT2MC_AXI_A_ABURST_RANGE                   _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define MSELECT2MC_AXI_A_ABURST_ROW                     0
+#define MSELECT2MC_AXI_A_ABURST_FIXED                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ABURST_INCR                    _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ABURST_WRAP                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ABURST_RSVD                    _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ALOCK_SHIFT                    _MK_SHIFT_CONST(54)
+#define MSELECT2MC_AXI_A_ALOCK_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ALOCK_SHIFT)
+#define MSELECT2MC_AXI_A_ALOCK_RANGE                    _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define MSELECT2MC_AXI_A_ALOCK_ROW                      0
+#define MSELECT2MC_AXI_A_ALOCK_NORMAL                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALOCK_EXCLUSIVE                        _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALOCK_LOCKED                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALOCK_RSVD                     _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ACACHE_SHIFT                   _MK_SHIFT_CONST(56)
+#define MSELECT2MC_AXI_A_ACACHE_FIELD                   (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ACACHE_SHIFT)
+#define MSELECT2MC_AXI_A_ACACHE_RANGE                   _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define MSELECT2MC_AXI_A_ACACHE_ROW                     0
+#define MSELECT2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                      _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ACACHE_BUFFERABLE                      _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                      _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                       _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                   _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                      _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                       _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                  _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_APROT_SHIFT                    _MK_SHIFT_CONST(60)
+#define MSELECT2MC_AXI_A_APROT_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_APROT_SHIFT)
+#define MSELECT2MC_AXI_A_APROT_RANGE                    _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define MSELECT2MC_AXI_A_APROT_ROW                      0
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_NORMAL                       _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_NORMAL                       _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(7)
+
+
+// Packet MSELECT2MC_AXI_W
+#define MSELECT2MC_AXI_W_SIZE 86
+
+#define MSELECT2MC_AXI_W_WDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_W_WDATA_SHIFT)
+#define MSELECT2MC_AXI_W_WDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_ROW                      0
+
+#define MSELECT2MC_AXI_W_WID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_W_WID_SHIFT)
+#define MSELECT2MC_AXI_W_WID_RANGE                      _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_ROW                        0
+
+#define MSELECT2MC_AXI_W_WSTRB_SHIFT                    _MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_W_WSTRB_FIELD                    (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WSTRB_SHIFT)
+#define MSELECT2MC_AXI_W_WSTRB_RANGE                    _MK_SHIFT_CONST(84):_MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_W_WSTRB_ROW                      0
+
+#define MSELECT2MC_AXI_W_WLAST_SHIFT                    _MK_SHIFT_CONST(85)
+#define MSELECT2MC_AXI_W_WLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_W_WLAST_SHIFT)
+#define MSELECT2MC_AXI_W_WLAST_RANGE                    _MK_SHIFT_CONST(85):_MK_SHIFT_CONST(85)
+#define MSELECT2MC_AXI_W_WLAST_ROW                      0
+#define MSELECT2MC_AXI_W_WLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_W_WLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_B
+#define MSELECT2MC_AXI_B_SIZE 15
+
+#define MSELECT2MC_AXI_B_BID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_B_BID_SHIFT)
+#define MSELECT2MC_AXI_B_BID_RANGE                      _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_ROW                        0
+
+#define MSELECT2MC_AXI_B_BRESP_SHIFT                    _MK_SHIFT_CONST(13)
+#define MSELECT2MC_AXI_B_BRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_B_BRESP_SHIFT)
+#define MSELECT2MC_AXI_B_BRESP_RANGE                    _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define MSELECT2MC_AXI_B_BRESP_ROW                      0
+#define MSELECT2MC_AXI_B_BRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_B_BRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_B_BRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_B_BRESP_DECERR                   _MK_ENUM_CONST(3)
+
+
+// Packet MSELECT2MC_AXI_R
+#define MSELECT2MC_AXI_R_SIZE 80
+
+#define MSELECT2MC_AXI_R_RDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_R_RDATA_SHIFT)
+#define MSELECT2MC_AXI_R_RDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_ROW                      0
+
+#define MSELECT2MC_AXI_R_RID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_R_RID_SHIFT)
+#define MSELECT2MC_AXI_R_RID_RANGE                      _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_ROW                        0
+
+#define MSELECT2MC_AXI_R_RRESP_SHIFT                    _MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_R_RRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_R_RRESP_SHIFT)
+#define MSELECT2MC_AXI_R_RRESP_RANGE                    _MK_SHIFT_CONST(78):_MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_R_RRESP_ROW                      0
+#define MSELECT2MC_AXI_R_RRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_R_RRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_R_RRESP_DECERR                   _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_R_RLAST_SHIFT                    _MK_SHIFT_CONST(79)
+#define MSELECT2MC_AXI_R_RLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_R_RLAST_SHIFT)
+#define MSELECT2MC_AXI_R_RLAST_RANGE                    _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(79)
+#define MSELECT2MC_AXI_R_RLAST_ROW                      0
+#define MSELECT2MC_AXI_R_RLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_A
+#define AXI2MC_AXI_A_SIZE 63
+
+#define AXI2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_A_AADDR_SHIFT)
+#define AXI2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_ROW                  0
+
+#define AXI2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_A_AID_SHIFT)
+#define AXI2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_ROW                    0
+
+#define AXI2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define AXI2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ALEN_SHIFT)
+#define AXI2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define AXI2MC_AXI_A_ALEN_ROW                   0
+#define AXI2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define AXI2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define AXI2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define AXI2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define AXI2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_ASIZE_SHIFT)
+#define AXI2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ASIZE_ROW                  0
+#define AXI2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define AXI2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define AXI2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ABURST_SHIFT)
+#define AXI2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define AXI2MC_AXI_A_ABURST_ROW                 0
+#define AXI2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define AXI2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ALOCK_SHIFT)
+#define AXI2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define AXI2MC_AXI_A_ALOCK_ROW                  0
+#define AXI2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define AXI2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ACACHE_SHIFT)
+#define AXI2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define AXI2MC_AXI_A_ACACHE_ROW                 0
+#define AXI2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define AXI2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_APROT_SHIFT)
+#define AXI2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define AXI2MC_AXI_A_APROT_ROW                  0
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet AXI2MC_AXI_W
+#define AXI2MC_AXI_W_SIZE 302
+
+#define AXI2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WDATA_SHIFT)
+#define AXI2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_ROW                  0
+
+#define AXI2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_W_WID_SHIFT)
+#define AXI2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(268):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_ROW                    0
+
+#define AXI2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WSTRB_SHIFT)
+#define AXI2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(300):_MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_W_WSTRB_ROW                  0
+
+#define AXI2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(301)
+#define AXI2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_W_WLAST_SHIFT)
+#define AXI2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(301):_MK_SHIFT_CONST(301)
+#define AXI2MC_AXI_W_WLAST_ROW                  0
+#define AXI2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_B
+#define AXI2MC_AXI_B_SIZE 15
+
+#define AXI2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_B_BID_SHIFT)
+#define AXI2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_ROW                    0
+
+#define AXI2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(13)
+#define AXI2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_B_BRESP_SHIFT)
+#define AXI2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define AXI2MC_AXI_B_BRESP_ROW                  0
+#define AXI2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet AXI2MC_AXI_R
+#define AXI2MC_AXI_R_SIZE 272
+
+#define AXI2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_R_RDATA_SHIFT)
+#define AXI2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_ROW                  0
+
+#define AXI2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_R_RID_SHIFT)
+#define AXI2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(268):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_ROW                    0
+
+#define AXI2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_R_RRESP_SHIFT)
+#define AXI2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(270):_MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_R_RRESP_ROW                  0
+#define AXI2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(271)
+#define AXI2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_R_RLAST_SHIFT)
+#define AXI2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(271):_MK_SHIFT_CONST(271)
+#define AXI2MC_AXI_R_RLAST_ROW                  0
+#define AXI2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MC_AXI_RWREQ
+#define MC_AXI_RWREQ_SIZE 112
+
+#define MC_AXI_RWREQ_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_AADDR_SHIFT)
+#define MC_AXI_RWREQ_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_ROW                  0
+
+#define MC_AXI_RWREQ_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << MC_AXI_RWREQ_AID_SHIFT)
+#define MC_AXI_RWREQ_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_ROW                    0
+
+#define MC_AXI_RWREQ_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define MC_AXI_RWREQ_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define MC_AXI_RWREQ_ALEN_ROW                   0
+
+#define MC_AXI_RWREQ_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ASIZE_ROW                  2
+
+#define MC_AXI_RWREQ_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define MC_AXI_RWREQ_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ABURST_SHIFT)
+#define MC_AXI_RWREQ_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define MC_AXI_RWREQ_ABURST_ROW                 0
+#define MC_AXI_RWREQ_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define MC_AXI_RWREQ_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define MC_AXI_RWREQ_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define MC_AXI_RWREQ_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define MC_AXI_RWREQ_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define MC_AXI_RWREQ_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ALOCK_SHIFT)
+#define MC_AXI_RWREQ_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define MC_AXI_RWREQ_ALOCK_ROW                  0
+
+#define MC_AXI_RWREQ_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define MC_AXI_RWREQ_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACACHE_SHIFT)
+#define MC_AXI_RWREQ_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define MC_AXI_RWREQ_ACACHE_ROW                 0
+
+#define MC_AXI_RWREQ_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_APROT_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_APROT_SHIFT)
+#define MC_AXI_RWREQ_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_APROT_ROW                  0
+
+#define MC_AXI_RWREQ_ASB_SHIFT                  _MK_SHIFT_CONST(63)
+#define MC_AXI_RWREQ_ASB_FIELD                  (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ASB_SHIFT)
+#define MC_AXI_RWREQ_ASB_RANGE                  _MK_SHIFT_CONST(64):_MK_SHIFT_CONST(63)
+#define MC_AXI_RWREQ_ASB_ROW                    0
+
+#define MC_AXI_RWREQ_ARW_SHIFT                  _MK_SHIFT_CONST(65)
+#define MC_AXI_RWREQ_ARW_FIELD                  (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ARW_SHIFT)
+#define MC_AXI_RWREQ_ARW_RANGE                  _MK_SHIFT_CONST(65):_MK_SHIFT_CONST(65)
+#define MC_AXI_RWREQ_ARW_ROW                    0
+
+#define MC_AXI_RWREQ_ACT_AADDR_SHIFT                    _MK_SHIFT_CONST(66)
+#define MC_AXI_RWREQ_ACT_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_ACT_AADDR_SHIFT)
+#define MC_AXI_RWREQ_ACT_AADDR_RANGE                    _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(66)
+#define MC_AXI_RWREQ_ACT_AADDR_ROW                      0
+
+#define MC_AXI_RWREQ_ACT_ALEN_SHIFT                     _MK_SHIFT_CONST(98)
+#define MC_AXI_RWREQ_ACT_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACT_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ACT_ALEN_RANGE                     _MK_SHIFT_CONST(101):_MK_SHIFT_CONST(98)
+#define MC_AXI_RWREQ_ACT_ALEN_ROW                       0
+
+#define MC_AXI_RWREQ_ACT_ASIZE_SHIFT                    _MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_ACT_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ACT_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ACT_ASIZE_RANGE                    _MK_SHIFT_CONST(104):_MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_ACT_ASIZE_ROW                      0
+
+#define MC_AXI_RWREQ_DOUBLEREQ_SHIFT                    _MK_SHIFT_CONST(105)
+#define MC_AXI_RWREQ_DOUBLEREQ_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_DOUBLEREQ_SHIFT)
+#define MC_AXI_RWREQ_DOUBLEREQ_RANGE                    _MK_SHIFT_CONST(105):_MK_SHIFT_CONST(105)
+#define MC_AXI_RWREQ_DOUBLEREQ_ROW                      0
+
+#define MC_AXI_RWREQ_ILLEGALACC_SHIFT                   _MK_SHIFT_CONST(106)
+#define MC_AXI_RWREQ_ILLEGALACC_FIELD                   (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ILLEGALACC_SHIFT)
+#define MC_AXI_RWREQ_ILLEGALACC_RANGE                   _MK_SHIFT_CONST(106):_MK_SHIFT_CONST(106)
+#define MC_AXI_RWREQ_ILLEGALACC_ROW                     0
+
+#define MC_AXI_RWREQ_TAG_SHIFT                  _MK_SHIFT_CONST(107)
+#define MC_AXI_RWREQ_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << MC_AXI_RWREQ_TAG_SHIFT)
+#define MC_AXI_RWREQ_TAG_RANGE                  _MK_SHIFT_CONST(111):_MK_SHIFT_CONST(107)
+#define MC_AXI_RWREQ_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_RESET
+#define CSR_C2MC_RESET_SIZE 1
+
+#define CSR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_RESET_RSTN_SHIFT)
+#define CSR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSR_C2MC_REQ
+#define CSR_C2MC_REQ_SIZE 32
+
+#define CSR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_REQ_ADR_SHIFT)
+#define CSR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_ROW                    0
+
+
+// Packet CSR_C2MC_SIZE
+#define CSR_C2MC_SIZE_SIZE 1
+
+#define CSR_C2MC_SIZE_SIZE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSR_C2MC_SIZE_SIZE_FIELD                        (_MK_MASK_CONST(0x1) << CSR_C2MC_SIZE_SIZE_SHIFT)
+#define CSR_C2MC_SIZE_SIZE_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_SIZE_SIZE_ROW                  0
+
+
+// Packet CSR_C2MC_SECURE
+#define CSR_C2MC_SECURE_SIZE 1
+
+#define CSR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CSR_C2MC_SECURE_SECURE_SHIFT)
+#define CSR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CSR_C2MC_TAG
+#define CSR_C2MC_TAG_SIZE 5
+
+#define CSR_C2MC_TAG_TAG_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TAG_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << CSR_C2MC_TAG_TAG_SHIFT)
+#define CSR_C2MC_TAG_TAG_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TAG_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_BP_REQ
+#define CSR_C2MC_BP_REQ_SIZE 48
+
+#define CSR_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSR_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSR_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSR_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSR_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_ROW                       0
+
+
+// Packet CSR_C2MC_ADRXY
+#define CSR_C2MC_ADRXY_SIZE 30
+
+#define CSR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSR_C2MC_ADRXY_OFFX_SHIFT)
+#define CSR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSR_C2MC_ADRXY_OFFY_SHIFT)
+#define CSR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSR_C2MC_TILE
+#define CSR_C2MC_TILE_SIZE 33
+
+#define CSR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_TILE_LINADR_SHIFT)
+#define CSR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_ROW                        0
+
+#define CSR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_TILE_TMODE_SHIFT)
+#define CSR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_ROW                 0
+#define CSR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSR_C2MC_RDI
+#define CSR_C2MC_RDI_SIZE 256
+
+#define CSR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_RDI_RDI_SHIFT)
+#define CSR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CSR_C2MC_HP
+#define CSR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CSR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_HP_HPTH_SHIFT)
+#define CSR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CSR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CSR_C2MC_HP_HPTM_SHIFT)
+#define CSR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CSR_C2MC_HYST
+#define CSR_C2MC_HYST_SIZE 32
+
+#define CSR_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CSR_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CSR_C2MC_HYST_DHYST_TM_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSR_C2MC_HYST_DHYST_TM_FIELD                    (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_DHYST_TM_SHIFT)
+#define CSR_C2MC_HYST_DHYST_TM_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSR_C2MC_HYST_DHYST_TM_ROW                      0
+
+#define CSR_C2MC_HYST_DHYST_TH_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSR_C2MC_HYST_DHYST_TH_FIELD                    (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_DHYST_TH_SHIFT)
+#define CSR_C2MC_HYST_DHYST_TH_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_HYST_DHYST_TH_ROW                      0
+
+#define CSR_C2MC_HYST_HYST_TM_SHIFT                     _MK_SHIFT_CONST(24)
+#define CSR_C2MC_HYST_HYST_TM_FIELD                     (_MK_MASK_CONST(0xf) << CSR_C2MC_HYST_HYST_TM_SHIFT)
+#define CSR_C2MC_HYST_HYST_TM_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define CSR_C2MC_HYST_HYST_TM_ROW                       0
+
+#define CSR_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CSR_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CSR_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CSR_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CSR_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CSR_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CSR_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CSR_C2MC_HYST_HYST_EN_SHIFT)
+#define CSR_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CSR_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CSW_C2MC_RESET
+#define CSW_C2MC_RESET_SIZE 1
+
+#define CSW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_RESET_RSTN_SHIFT)
+#define CSW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSW_C2MC_REQ
+#define CSW_C2MC_REQ_SIZE 321
+
+#define CSW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_ADR_SHIFT)
+#define CSW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_ROW                    0
+
+#define CSW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_BE_SHIFT)
+#define CSW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_ROW                     0
+
+#define CSW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_WDO_SHIFT)
+#define CSW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_ROW                    0
+
+#define CSW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_REQ_TAG_SHIFT)
+#define CSW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CSW_C2MC_SECURE
+#define CSW_C2MC_SECURE_SIZE 1
+
+#define CSW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CSW_C2MC_SECURE_SECURE_SHIFT)
+#define CSW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CSW_C2MC_BP_REQ
+#define CSW_C2MC_BP_REQ_SIZE 337
+
+#define CSW_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSW_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSW_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSW_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSW_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_ROW                       0
+
+#define CSW_C2MC_BP_REQ_BE_SHIFT                        _MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BE_SHIFT)
+#define CSW_C2MC_BP_REQ_BE_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_ROW                  0
+
+#define CSW_C2MC_BP_REQ_WDO_SHIFT                       _MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_FIELD                       (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_WDO_SHIFT)
+#define CSW_C2MC_BP_REQ_WDO_RANGE                       _MK_SHIFT_CONST(335):_MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_ROW                 0
+
+#define CSW_C2MC_BP_REQ_TAG_SHIFT                       _MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_BP_REQ_TAG_SHIFT)
+#define CSW_C2MC_BP_REQ_TAG_RANGE                       _MK_SHIFT_CONST(336):_MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_ROW                 0
+
+
+// Packet CSW_C2MC_ADRXY
+#define CSW_C2MC_ADRXY_SIZE 30
+
+#define CSW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSW_C2MC_ADRXY_OFFX_SHIFT)
+#define CSW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSW_C2MC_ADRXY_OFFY_SHIFT)
+#define CSW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSW_C2MC_TILE
+#define CSW_C2MC_TILE_SIZE 33
+
+#define CSW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_TILE_LINADR_SHIFT)
+#define CSW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_ROW                        0
+
+#define CSW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_TILE_TMODE_SHIFT)
+#define CSW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_ROW                 0
+#define CSW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSW_C2MC_XDI
+#define CSW_C2MC_XDI_SIZE 32
+
+// sometimes fake data
+#define CSW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_XDI_XDI_SHIFT)
+#define CSW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CSW_C2MC_HP
+#define CSW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CSW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HP_HPTH_SHIFT)
+#define CSW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CSW_C2MC_WCOAL
+#define CSW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CSW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CSW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CSW_C2MC_HYST
+#define CSW_C2MC_HYST_SIZE 32
+
+// hysteresis control register
+#define CSW_C2MC_HYST_HYST_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HYST_HYST_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HYST_HYST_SHIFT)
+#define CSW_C2MC_HYST_HYST_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HYST_HYST_ROW                  0
+
+
+// Packet CBR_C2MC_RESET
+#define CBR_C2MC_RESET_SIZE 1
+
+#define CBR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RESET_RSTN_SHIFT)
+#define CBR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBR_C2MC_REQP
+#define CBR_C2MC_REQP_SIZE 263
+
+#define CBR_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADR_SHIFT)
+#define CBR_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_ROW                   0
+
+#define CBR_C2MC_REQP_ADRU_SHIFT                        _MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRU_SHIFT)
+#define CBR_C2MC_REQP_ADRU_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_ROW                  0
+
+#define CBR_C2MC_REQP_ADRV_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRV_SHIFT)
+#define CBR_C2MC_REQP_ADRV_RANGE                        _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_ROW                  0
+
+#define CBR_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LS_SHIFT)
+#define CBR_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_ROW                    0
+
+#define CBR_C2MC_REQP_LSUV_SHIFT                        _MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LSUV_SHIFT)
+#define CBR_C2MC_REQP_LSUV_RANGE                        _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_ROW                  0
+
+#define CBR_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_HS_SHIFT)
+#define CBR_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(191):_MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_ROW                    0
+
+#define CBR_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_VS_SHIFT)
+#define CBR_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(223):_MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_ROW                    0
+
+#define CBR_C2MC_REQP_DL_SHIFT                  _MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_DL_SHIFT)
+#define CBR_C2MC_REQP_DL_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_ROW                    0
+
+#define CBR_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_HD_SHIFT)
+#define CBR_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_ROW                    0
+
+#define CBR_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VD_SHIFT)
+#define CBR_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(257):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_ROW                    0
+
+#define CBR_C2MC_REQP_VX2_SHIFT                 _MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VX2_SHIFT)
+#define CBR_C2MC_REQP_VX2_RANGE                 _MK_SHIFT_CONST(258):_MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_ROW                   0
+
+#define CBR_C2MC_REQP_LP_SHIFT                  _MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_LP_SHIFT)
+#define CBR_C2MC_REQP_LP_RANGE                  _MK_SHIFT_CONST(259):_MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_ROW                    0
+
+#define CBR_C2MC_REQP_YUV_SHIFT                 _MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_REQP_YUV_SHIFT)
+#define CBR_C2MC_REQP_YUV_RANGE                 _MK_SHIFT_CONST(262):_MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_ROW                   0
+
+
+// Packet CBR_C2MC_SECURE
+#define CBR_C2MC_SECURE_SIZE 1
+
+#define CBR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_SECURE_SECURE_SHIFT)
+#define CBR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CBR_C2MC_ADRXY
+#define CBR_C2MC_ADRXY_SIZE 44
+
+#define CBR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_ADRXY_OFFX_SHIFT)
+#define CBR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFY_SHIFT)
+#define CBR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFYUV_SHIFT                     _MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_FIELD                     (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFYUV_SHIFT)
+#define CBR_C2MC_ADRXY_OFFYUV_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_ROW                       0
+
+
+// Packet CBR_C2MC_TILE
+#define CBR_C2MC_TILE_SIZE 98
+
+#define CBR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADR_SHIFT)
+#define CBR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_ROW                        0
+
+#define CBR_C2MC_TILE_LINADRU_SHIFT                     _MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRU_SHIFT)
+#define CBR_C2MC_TILE_LINADRU_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_ROW                       0
+
+#define CBR_C2MC_TILE_LINADRV_SHIFT                     _MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRV_SHIFT)
+#define CBR_C2MC_TILE_LINADRV_RANGE                     _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_ROW                       0
+
+#define CBR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODE_SHIFT)
+#define CBR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_ROW                 0
+#define CBR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+#define CBR_C2MC_TILE_TMODEUV_SHIFT                     _MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODEUV_SHIFT)
+#define CBR_C2MC_TILE_TMODEUV_RANGE                     _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_ROW                       0
+#define CBR_C2MC_TILE_TMODEUV_LINEAR                    _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODEUV_TILED                     _MK_ENUM_CONST(1)
+
+
+// Packet CBR_C2MC_RDYP
+#define CBR_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBR_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_RDYP_RDYP_SHIFT)
+#define CBR_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBR_C2MC_OUTSTD
+#define CBR_C2MC_OUTSTD_SIZE 1
+
+#define CBR_C2MC_OUTSTD_OUTSTD_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_OUTSTD_OUTSTD_SHIFT)
+#define CBR_C2MC_OUTSTD_OUTSTD_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_ROW                      0
+
+
+// Packet CBR_C2MC_STOP
+#define CBR_C2MC_STOP_SIZE 1
+
+#define CBR_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_STOP_STOP_SHIFT)
+#define CBR_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBR_C2MC_RDI
+#define CBR_C2MC_RDI_SIZE 262
+
+#define CBR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_RDI_RDI_SHIFT)
+#define CBR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_ROW                    0
+
+#define CBR_C2MC_RDI_RDILST_SHIFT                       _MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RDI_RDILST_SHIFT)
+#define CBR_C2MC_RDI_RDILST_RANGE                       _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_ROW                 0
+
+#define CBR_C2MC_RDI_RDINB_SHIFT                        _MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_FIELD                        (_MK_MASK_CONST(0x1f) << CBR_C2MC_RDI_RDINB_SHIFT)
+#define CBR_C2MC_RDI_RDINB_RANGE                        _MK_SHIFT_CONST(261):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_ROW                  0
+
+
+// Packet CBR_C2MC_DOREQ
+#define CBR_C2MC_DOREQ_SIZE 64
+
+#define CBR_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_ADR_SHIFT)
+#define CBR_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBR_C2MC_DOREQ_LS_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_LS_SHIFT)
+#define CBR_C2MC_DOREQ_LS_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_ROW                   0
+
+
+// Packet CBR_C2MC_HP
+#define CBR_C2MC_HP_SIZE 71
+
+// high-priority threshold
+#define CBR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_HP_HPTH_SHIFT)
+#define CBR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CBR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CBR_C2MC_HP_HPTM_SHIFT)
+#define CBR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_ROW                    0
+
+// suppression - start of frame
+#define CBR_C2MC_HP_HPSOF_SHIFT                 _MK_SHIFT_CONST(38)
+#define CBR_C2MC_HP_HPSOF_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_HP_HPSOF_SHIFT)
+#define CBR_C2MC_HP_HPSOF_RANGE                 _MK_SHIFT_CONST(38):_MK_SHIFT_CONST(38)
+#define CBR_C2MC_HP_HPSOF_ROW                   0
+
+// suppression - cycles per word
+#define CBR_C2MC_HP_HPCPW_SHIFT                 _MK_SHIFT_CONST(39)
+#define CBR_C2MC_HP_HPCPW_FIELD                 (_MK_MASK_CONST(0xffff) << CBR_C2MC_HP_HPCPW_SHIFT)
+#define CBR_C2MC_HP_HPCPW_RANGE                 _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(39)
+#define CBR_C2MC_HP_HPCPW_ROW                   0
+
+// suppression - words per line
+#define CBR_C2MC_HP_HPCBNPW_SHIFT                       _MK_SHIFT_CONST(55)
+#define CBR_C2MC_HP_HPCBNPW_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_HP_HPCBNPW_SHIFT)
+#define CBR_C2MC_HP_HPCBNPW_RANGE                       _MK_SHIFT_CONST(70):_MK_SHIFT_CONST(55)
+#define CBR_C2MC_HP_HPCBNPW_ROW                 0
+
+
+// Packet CBR_C2MC_HYST
+#define CBR_C2MC_HYST_SIZE 32
+
+#define CBR_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CBR_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CBR_C2MC_HYST_DHYST_TM_SHIFT                    _MK_SHIFT_CONST(8)
+#define CBR_C2MC_HYST_DHYST_TM_FIELD                    (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_DHYST_TM_SHIFT)
+#define CBR_C2MC_HYST_DHYST_TM_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CBR_C2MC_HYST_DHYST_TM_ROW                      0
+
+#define CBR_C2MC_HYST_DHYST_TH_SHIFT                    _MK_SHIFT_CONST(16)
+#define CBR_C2MC_HYST_DHYST_TH_FIELD                    (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_DHYST_TH_SHIFT)
+#define CBR_C2MC_HYST_DHYST_TH_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_HYST_DHYST_TH_ROW                      0
+
+#define CBR_C2MC_HYST_HYST_TM_SHIFT                     _MK_SHIFT_CONST(24)
+#define CBR_C2MC_HYST_HYST_TM_FIELD                     (_MK_MASK_CONST(0xf) << CBR_C2MC_HYST_HYST_TM_SHIFT)
+#define CBR_C2MC_HYST_HYST_TM_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define CBR_C2MC_HYST_HYST_TM_ROW                       0
+
+#define CBR_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CBR_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CBR_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CBR_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CBR_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CBR_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_HYST_HYST_EN_SHIFT)
+#define CBR_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CBR_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CBW_C2MC_RESET
+#define CBW_C2MC_RESET_SIZE 1
+
+#define CBW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_RESET_RSTN_SHIFT)
+#define CBW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBW_C2MC_REQP
+#define CBW_C2MC_REQP_SIZE 134
+
+#define CBW_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_ADR_SHIFT)
+#define CBW_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_ROW                   0
+
+#define CBW_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_LS_SHIFT)
+#define CBW_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_ROW                    0
+
+#define CBW_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_HS_SHIFT)
+#define CBW_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_ROW                    0
+
+#define CBW_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_VS_SHIFT)
+#define CBW_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_ROW                    0
+
+#define CBW_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_HD_SHIFT)
+#define CBW_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(128):_MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_ROW                    0
+
+#define CBW_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_VD_SHIFT)
+#define CBW_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(129):_MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_ROW                    0
+
+#define CBW_C2MC_REQP_BPP_SHIFT                 _MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_FIELD                 (_MK_MASK_CONST(0x3) << CBW_C2MC_REQP_BPP_SHIFT)
+#define CBW_C2MC_REQP_BPP_RANGE                 _MK_SHIFT_CONST(131):_MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_ROW                   0
+
+#define CBW_C2MC_REQP_XY_SHIFT                  _MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_XY_SHIFT)
+#define CBW_C2MC_REQP_XY_RANGE                  _MK_SHIFT_CONST(132):_MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_ROW                    0
+
+#define CBW_C2MC_REQP_PK_SHIFT                  _MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_PK_SHIFT)
+#define CBW_C2MC_REQP_PK_RANGE                  _MK_SHIFT_CONST(133):_MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_ROW                    0
+
+
+// Packet CBW_C2MC_SECURE
+#define CBW_C2MC_SECURE_SIZE 1
+
+#define CBW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CBW_C2MC_SECURE_SECURE_SHIFT)
+#define CBW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CBW_C2MC_ADRXY
+#define CBW_C2MC_ADRXY_SIZE 30
+
+#define CBW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBW_C2MC_ADRXY_OFFX_SHIFT)
+#define CBW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBW_C2MC_ADRXY_OFFY_SHIFT)
+#define CBW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CBW_C2MC_TILE
+#define CBW_C2MC_TILE_SIZE 33
+
+#define CBW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_TILE_LINADR_SHIFT)
+#define CBW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_ROW                        0
+
+#define CBW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_TILE_TMODE_SHIFT)
+#define CBW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_ROW                 0
+#define CBW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CBW_C2MC_RDYP
+#define CBW_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBW_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_RDYP_RDYP_SHIFT)
+#define CBW_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBW_C2MC_STOP
+#define CBW_C2MC_STOP_SIZE 1
+
+#define CBW_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_STOP_STOP_SHIFT)
+#define CBW_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBW_C2MC_XDI
+#define CBW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CBW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_XDI_XDI_SHIFT)
+#define CBW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CBW_C2MC_DOREQ
+#define CBW_C2MC_DOREQ_SIZE 321
+
+#define CBW_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_ADR_SHIFT)
+#define CBW_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBW_C2MC_DOREQ_BE_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_BE_SHIFT)
+#define CBW_C2MC_DOREQ_BE_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_ROW                   0
+
+#define CBW_C2MC_DOREQ_WDO_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_WDO_SHIFT)
+#define CBW_C2MC_DOREQ_WDO_RANGE                        _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_ROW                  0
+
+#define CBW_C2MC_DOREQ_TAG_SHIFT                        _MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_DOREQ_TAG_SHIFT)
+#define CBW_C2MC_DOREQ_TAG_RANGE                        _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_ROW                  0
+
+
+// Packet CBW_C2MC_HP
+#define CBW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CBW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_HP_HPTH_SHIFT)
+#define CBW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CBW_C2MC_WCOAL
+#define CBW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CBW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CBW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CBW_C2MC_HYST
+#define CBW_C2MC_HYST_SIZE 32
+
+#define CBW_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xfff) << CBW_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CBW_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CBW_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CBW_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CBW_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CBW_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CBW_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CBW_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CBW_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CBW_C2MC_HYST_HYST_EN_SHIFT)
+#define CBW_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CBW_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CCR_C2MC_RESET
+#define CCR_C2MC_RESET_SIZE 1
+
+#define CCR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCR_C2MC_RESET_RSTN_SHIFT)
+#define CCR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCR_C2MC_REQ
+#define CCR_C2MC_REQ_SIZE 101
+
+#define CCR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_ADR_SHIFT)
+#define CCR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_ROW                    0
+
+#define CCR_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_LS_SHIFT)
+#define CCR_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCR_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_HINC_SHIFT)
+#define CCR_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_ROW                   0
+
+#define CCR_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCR_C2MC_REQ_ACMD_SHIFT)
+#define CCR_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_ROW                   0
+
+#define CCR_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_LN_SHIFT)
+#define CCR_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_ROW                     0
+
+#define CCR_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_HD_SHIFT)
+#define CCR_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_ROW                     0
+
+#define CCR_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_VD_SHIFT)
+#define CCR_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_ROW                     0
+
+
+// Packet CCR_C2MC_SECURE
+#define CCR_C2MC_SECURE_SIZE 1
+
+#define CCR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CCR_C2MC_SECURE_SECURE_SHIFT)
+#define CCR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CCR_C2MC_RDI
+#define CCR_C2MC_RDI_SIZE 256
+
+#define CCR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_RDI_RDI_SHIFT)
+#define CCR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CCR_C2MC_HP
+#define CCR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CCR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HP_HPTH_SHIFT)
+#define CCR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CCR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CCR_C2MC_HP_HPTM_SHIFT)
+#define CCR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CCR_C2MC_HYST
+#define CCR_C2MC_HYST_SIZE 32
+
+// hysteresis control register
+#define CCR_C2MC_HYST_HYST_SHIFT                        _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HYST_HYST_FIELD                        (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HYST_HYST_SHIFT)
+#define CCR_C2MC_HYST_HYST_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HYST_HYST_ROW                  0
+
+
+// Packet CCW_C2MC_RESET
+#define CCW_C2MC_RESET_SIZE 1
+
+#define CCW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_RESET_RSTN_SHIFT)
+#define CCW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCW_C2MC_REQ
+#define CCW_C2MC_REQ_SIZE 417
+
+#define CCW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_ADR_SHIFT)
+#define CCW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_ROW                    0
+
+#define CCW_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_LS_SHIFT)
+#define CCW_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCW_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_HINC_SHIFT)
+#define CCW_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_ROW                   0
+
+#define CCW_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_ACMD_SHIFT)
+#define CCW_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_ROW                   0
+
+#define CCW_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_LN_SHIFT)
+#define CCW_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_ROW                     0
+
+#define CCW_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_HD_SHIFT)
+#define CCW_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_ROW                     0
+
+#define CCW_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_VD_SHIFT)
+#define CCW_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_ROW                     0
+
+#define CCW_C2MC_REQ_BPP_SHIFT                  _MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_FIELD                  (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_BPP_SHIFT)
+#define CCW_C2MC_REQ_BPP_RANGE                  _MK_SHIFT_CONST(102):_MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_ROW                    0
+
+#define CCW_C2MC_REQ_XY_SHIFT                   _MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_XY_SHIFT)
+#define CCW_C2MC_REQ_XY_RANGE                   _MK_SHIFT_CONST(103):_MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_ROW                     0
+
+#define CCW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_BE_SHIFT)
+#define CCW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_ROW                     0
+
+#define CCW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_WDO_SHIFT)
+#define CCW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(415):_MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_ROW                    0
+
+#define CCW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_TAG_SHIFT)
+#define CCW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(416):_MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CCW_C2MC_SECURE
+#define CCW_C2MC_SECURE_SIZE 1
+
+#define CCW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CCW_C2MC_SECURE_SECURE_SHIFT)
+#define CCW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CCW_C2MC_ADRXY
+#define CCW_C2MC_ADRXY_SIZE 30
+
+#define CCW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CCW_C2MC_ADRXY_OFFX_SHIFT)
+#define CCW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CCW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CCW_C2MC_ADRXY_OFFY_SHIFT)
+#define CCW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CCW_C2MC_TILE
+#define CCW_C2MC_TILE_SIZE 33
+
+#define CCW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_TILE_LINADR_SHIFT)
+#define CCW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_ROW                        0
+
+#define CCW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_TILE_TMODE_SHIFT)
+#define CCW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_ROW                 0
+#define CCW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CCW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CCW_C2MC_XDI
+#define CCW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CCW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_XDI_XDI_SHIFT)
+#define CCW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CCW_C2MC_HP
+#define CCW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CCW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_HP_HPTH_SHIFT)
+#define CCW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CCW_C2MC_WCOAL
+#define CCW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CCW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CCW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CCW_C2MC_HYST
+#define CCW_C2MC_HYST_SIZE 32
+
+#define CCW_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xfff) << CCW_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CCW_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CCW_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CCW_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CCW_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CCW_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CCW_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CCW_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CCW_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CCW_C2MC_HYST_HYST_EN_SHIFT)
+#define CCW_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CCW_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet SC_MCCIF_ASYNC
+#define SC_MCCIF_ASYNC_SIZE 4
+
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT                        _MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT                        _MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_RANGE                        _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT                        _MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT                        _MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_ROW                  0
+
+
+// Register EMC_LL_ARB_CONFIG_0  // LOW-LATENCY arbiter configuration
+#define EMC_LL_ARB_CONFIG_0                     _MK_ADDR_CONST(0x144)
+#define EMC_LL_ARB_CONFIG_0_SECURE                      0x0
+#define EMC_LL_ARB_CONFIG_0_WORD_COUNT                  0x1
+#define EMC_LL_ARB_CONFIG_0_RESET_VAL                   _MK_MASK_CONST(0x2003)
+#define EMC_LL_ARB_CONFIG_0_RESET_MASK                  _MK_MASK_CONST(0x3f00f10f)
+#define EMC_LL_ARB_CONFIG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_READ_MASK                   _MK_MASK_CONST(0x3f00f10f)
+#define EMC_LL_ARB_CONFIG_0_WRITE_MASK                  _MK_MASK_CONST(0x3f00f10f)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_FIELD                   (_MK_MASK_CONST(0xf) << EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_RANGE                   3:0
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_WOFFSET                 0x0
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_DEFAULT                 _MK_MASK_CONST(0x3)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_DIE_OFF_EXP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_FIELD                     (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_RANGE                     8:8
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_WOFFSET                   0x0
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_INIT_ENUM                 DISABLED
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_LL_ARB_CONFIG_0_ALLOW_IDLE_INSERT_ENABLED                   _MK_ENUM_CONST(1)
+
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SHIFT                  _MK_SHIFT_CONST(12)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_FIELD                  (_MK_MASK_CONST(0xf) << EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_RANGE                  15:12
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_WOFFSET                        0x0
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_DEFAULT                        _MK_MASK_CONST(0x2)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_MAX_LL_GREED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// set to one to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_SHIFT                    _MK_SHIFT_CONST(24)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_RANGE                    24:24
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_WOFFSET                  0x0
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set to one to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_SHIFT                      _MK_SHIFT_CONST(25)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_RANGE                      25:25
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_WOFFSET                    0x0
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_GREED_DIFF_BANK_AFTER_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set to one to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_SHIFT                    _MK_SHIFT_CONST(26)
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_RANGE                    26:26
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_WOFFSET                  0x0
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_FORCE_INSERT_WR_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set to one to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_SHIFT                    _MK_SHIFT_CONST(27)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_RANGE                    27:27
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_WOFFSET                  0x0
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_BEFORE_DISABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// set to one to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_SHIFT                      _MK_SHIFT_CONST(28)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_RANGE                      28:28
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_WOFFSET                    0x0
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_TOGGLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// set to zero to get AP15 behavior
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_SHIFT                      _MK_SHIFT_CONST(29)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_FIELD                      (_MK_MASK_CONST(0x1) << EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_SHIFT)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_RANGE                      29:29
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_WOFFSET                    0x0
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_LL_ARB_CONFIG_0_LL_INSERT_DIFF_BANK_AFTER_REMOVE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MIN_CRITICAL_HP_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MIN_CRITICAL_HP_0                 _MK_ADDR_CONST(0x148)
+#define EMC_T_MIN_CRITICAL_HP_0_SECURE                  0x0
+#define EMC_T_MIN_CRITICAL_HP_0_WORD_COUNT                      0x1
+#define EMC_T_MIN_CRITICAL_HP_0_RESET_VAL                       _MK_MASK_CONST(0xa080600)
+#define EMC_T_MIN_CRITICAL_HP_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_RANGE                   7:0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_RANGE                   15:8
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_DEFAULT                 _MK_MASK_CONST(0x6)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_RANGE                   23:16
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_DEFAULT                 _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SHIFT)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_RANGE                   31:24
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_WOFFSET                 0x0
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_DEFAULT                 _MK_MASK_CONST(0xa)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_HP_0_T_MIN_CRIT_HP_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MIN_CRITICAL_TIMEOUT_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0                    _MK_ADDR_CONST(0x14c)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_SECURE                     0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_WORD_COUNT                         0x1
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_RESET_VAL                  _MK_MASK_CONST(0xa080600)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_RANGE                 7:0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_RANGE                 15:8
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_DEFAULT                       _MK_MASK_CONST(0x6)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_RANGE                 23:16
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_DEFAULT                       _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SHIFT)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_RANGE                 31:24
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_WOFFSET                       0x0
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_DEFAULT                       _MK_MASK_CONST(0xa)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_CRITICAL_TIMEOUT_0_T_MIN_CRIT_TIMEOUT_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MIN_LOAD_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MIN_LOAD_0                        _MK_ADDR_CONST(0x150)
+#define EMC_T_MIN_LOAD_0_SECURE                         0x0
+#define EMC_T_MIN_LOAD_0_WORD_COUNT                     0x1
+#define EMC_T_MIN_LOAD_0_RESET_VAL                      _MK_MASK_CONST(0x8040200)
+#define EMC_T_MIN_LOAD_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_RANGE                     7:0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_RANGE                     15:8
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_DEFAULT                   _MK_MASK_CONST(0x2)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_RANGE                     23:16
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_DEFAULT                   _MK_MASK_CONST(0x4)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SHIFT)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_RANGE                     31:24
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_WOFFSET                   0x0
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MIN_LOAD_0_T_MIN_LOAD_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_CRITICAL_HP_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MAX_CRITICAL_HP_0                 _MK_ADDR_CONST(0x154)
+#define EMC_T_MAX_CRITICAL_HP_0_SECURE                  0x0
+#define EMC_T_MAX_CRITICAL_HP_0_WORD_COUNT                      0x1
+#define EMC_T_MAX_CRITICAL_HP_0_RESET_VAL                       _MK_MASK_CONST(0xb0a0901)
+#define EMC_T_MAX_CRITICAL_HP_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_RANGE                   7:0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_DEFAULT                 _MK_MASK_CONST(0x1)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_RANGE                   15:8
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_DEFAULT                 _MK_MASK_CONST(0x9)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_RANGE                   23:16
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_DEFAULT                 _MK_MASK_CONST(0xa)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SHIFT                   _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_FIELD                   (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SHIFT)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_RANGE                   31:24
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_WOFFSET                 0x0
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_DEFAULT                 _MK_MASK_CONST(0xb)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_HP_0_T_MAX_CRIT_HP_3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_CRITICAL_TIMEOUT_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0                    _MK_ADDR_CONST(0x158)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_SECURE                     0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_WORD_COUNT                         0x1
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_RESET_VAL                  _MK_MASK_CONST(0xb0a0901)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_RANGE                 7:0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_DEFAULT                       _MK_MASK_CONST(0x1)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SHIFT                 _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_RANGE                 15:8
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_DEFAULT                       _MK_MASK_CONST(0x9)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_RANGE                 23:16
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_DEFAULT                       _MK_MASK_CONST(0xa)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_FIELD                 (_MK_MASK_CONST(0xff) << EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SHIFT)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_RANGE                 31:24
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_WOFFSET                       0x0
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_DEFAULT                       _MK_MASK_CONST(0xb)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_CRITICAL_TIMEOUT_0_T_MAX_CRIT_TIMEOUT_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_T_MAX_LOAD_0  // LOW-LATENCY arbiter configuration
+#define EMC_T_MAX_LOAD_0                        _MK_ADDR_CONST(0x15c)
+#define EMC_T_MAX_LOAD_0_SECURE                         0x0
+#define EMC_T_MAX_LOAD_0_WORD_COUNT                     0x1
+#define EMC_T_MAX_LOAD_0_RESET_VAL                      _MK_MASK_CONST(0x20100804)
+#define EMC_T_MAX_LOAD_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_RANGE                     7:0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_DEFAULT                   _MK_MASK_CONST(0x4)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_RANGE                     15:8
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_DEFAULT                   _MK_MASK_CONST(0x8)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SHIFT                     _MK_SHIFT_CONST(16)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_RANGE                     23:16
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_DEFAULT                   _MK_MASK_CONST(0x10)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SHIFT                     _MK_SHIFT_CONST(24)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_FIELD                     (_MK_MASK_CONST(0xff) << EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SHIFT)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_RANGE                     31:24
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_WOFFSET                   0x0
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_DEFAULT                   _MK_MASK_CONST(0x20)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_T_MAX_LOAD_0_T_MAX_LOAD_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_CONTROL_0  
+#define EMC_STAT_CONTROL_0                      _MK_ADDR_CONST(0x160)
+#define EMC_STAT_CONTROL_0_SECURE                       0x0
+#define EMC_STAT_CONTROL_0_WORD_COUNT                   0x1
+#define EMC_STAT_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x30307)
+#define EMC_STAT_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x30307)
+#define EMC_STAT_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x30307)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_FIELD                    (_MK_MASK_CONST(0x7) << EMC_STAT_CONTROL_0_LLMC_GATHER_SHIFT)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_RANGE                    2:0
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_WOFFSET                  0x0
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_INIT_ENUM                        RST
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_RST                      _MK_ENUM_CONST(0)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_CLEAR                    _MK_ENUM_CONST(1)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_DISABLE                  _MK_ENUM_CONST(2)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_ENABLE                   _MK_ENUM_CONST(3)
+#define EMC_STAT_CONTROL_0_LLMC_GATHER_SLAVE_TO_MC                      _MK_ENUM_CONST(4)
+
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_FIELD                     (_MK_MASK_CONST(0x3) << EMC_STAT_CONTROL_0_PWR_GATHER_SHIFT)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_RANGE                     9:8
+#define EMC_STAT_CONTROL_0_PWR_GATHER_WOFFSET                   0x0
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_INIT_ENUM                 RST
+#define EMC_STAT_CONTROL_0_PWR_GATHER_RST                       _MK_ENUM_CONST(0)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_CLEAR                     _MK_ENUM_CONST(1)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_DISABLE                   _MK_ENUM_CONST(2)
+#define EMC_STAT_CONTROL_0_PWR_GATHER_ENABLE                    _MK_ENUM_CONST(3)
+
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_SHIFT                    _MK_SHIFT_CONST(16)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_FIELD                    (_MK_MASK_CONST(0x3) << EMC_STAT_CONTROL_0_DRAM_GATHER_SHIFT)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_RANGE                    17:16
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_WOFFSET                  0x0
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_INIT_ENUM                        RST
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_RST                      _MK_ENUM_CONST(0)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_CLEAR                    _MK_ENUM_CONST(1)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_DISABLE                  _MK_ENUM_CONST(2)
+#define EMC_STAT_CONTROL_0_DRAM_GATHER_ENABLE                   _MK_ENUM_CONST(3)
+
+
+// Register EMC_STAT_STATUS_0  
+#define EMC_STAT_STATUS_0                       _MK_ADDR_CONST(0x164)
+#define EMC_STAT_STATUS_0_SECURE                        0x0
+#define EMC_STAT_STATUS_0_WORD_COUNT                    0x1
+#define EMC_STAT_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x10101)
+#define EMC_STAT_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << EMC_STAT_STATUS_0_LLMC_LIMIT_SHIFT)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_RANGE                      0:0
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_WOFFSET                    0x0
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_LLMC_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SHIFT                       _MK_SHIFT_CONST(8)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_FIELD                       (_MK_MASK_CONST(0x1) << EMC_STAT_STATUS_0_PWR_LIMIT_SHIFT)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_RANGE                       8:8
+#define EMC_STAT_STATUS_0_PWR_LIMIT_WOFFSET                     0x0
+#define EMC_STAT_STATUS_0_PWR_LIMIT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_PWR_LIMIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_SHIFT                      _MK_SHIFT_CONST(16)
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << EMC_STAT_STATUS_0_DRAM_LIMIT_SHIFT)
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_RANGE                      16:16
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_WOFFSET                    0x0
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_STATUS_0_DRAM_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_LLMC_ADDR_LOW_0  
+#define EMC_STAT_LLMC_ADDR_LOW_0                        _MK_ADDR_CONST(0x168)
+#define EMC_STAT_LLMC_ADDR_LOW_0_SECURE                         0x0
+#define EMC_STAT_LLMC_ADDR_LOW_0_WORD_COUNT                     0x1
+#define EMC_STAT_LLMC_ADDR_LOW_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_RESET_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_READ_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_WRITE_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SHIFT                    _MK_SHIFT_CONST(4)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_FIELD                    (_MK_MASK_CONST(0x3ffffff) << EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SHIFT)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_RANGE                    29:4
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_WOFFSET                  0x0
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_DEFAULT_MASK                     _MK_MASK_CONST(0x3ffffff)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_LOW_0_LLMC_ADDR_LOW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_LLMC_ADDR_HIGH_0  
+#define EMC_STAT_LLMC_ADDR_HIGH_0                       _MK_ADDR_CONST(0x16c)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_SECURE                        0x0
+#define EMC_STAT_LLMC_ADDR_HIGH_0_WORD_COUNT                    0x1
+#define EMC_STAT_LLMC_ADDR_HIGH_0_RESET_VAL                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_RESET_MASK                    _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_READ_MASK                     _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_WRITE_MASK                    _MK_MASK_CONST(0x3ffffff0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SHIFT                  _MK_SHIFT_CONST(4)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_FIELD                  (_MK_MASK_CONST(0x3ffffff) << EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SHIFT)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_RANGE                  29:4
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_WOFFSET                        0x0
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_DEFAULT                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_DEFAULT_MASK                   _MK_MASK_CONST(0x3ffffff)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_ADDR_HIGH_0_LLMC_ADDR_HIGH_INIT_ENUM                      -1
+
+
+// Register EMC_STAT_LLMC_CLOCK_LIMIT_0  
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0                     _MK_ADDR_CONST(0x170)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_SECURE                      0x0
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_WORD_COUNT                  0x1
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_RESET_VAL                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SHIFT)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_RANGE                      31:0
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_WOFFSET                    0x0
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_DEFAULT                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCK_LIMIT_0_LLMC_CLOCK_LIMIT_INIT_ENUM                  -1
+
+
+// Register EMC_STAT_LLMC_CLOCKS_0  
+#define EMC_STAT_LLMC_CLOCKS_0                  _MK_ADDR_CONST(0x174)
+#define EMC_STAT_LLMC_CLOCKS_0_SECURE                   0x0
+#define EMC_STAT_LLMC_CLOCKS_0_WORD_COUNT                       0x1
+#define EMC_STAT_LLMC_CLOCKS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CLOCKS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SHIFT)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_RANGE                        31:0
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_WOFFSET                      0x0
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CLOCKS_0_LLMC_CLOCKS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Packet AREMC_STAT_CONTROL
+#define AREMC_STAT_CONTROL_SIZE 28
+
+#define AREMC_STAT_CONTROL_MODE_SHIFT                   _MK_SHIFT_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_FIELD                   (_MK_MASK_CONST(0x3) << AREMC_STAT_CONTROL_MODE_SHIFT)
+#define AREMC_STAT_CONTROL_MODE_RANGE                   _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_ROW                     0
+#define AREMC_STAT_CONTROL_MODE_BANDWIDTH                       _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_MODE_LATENCY_AVG                     _MK_ENUM_CONST(1)
+#define AREMC_STAT_CONTROL_MODE_LATENCY_HISTO                   _MK_ENUM_CONST(2)
+
+#define AREMC_STAT_CONTROL_SKIP_SHIFT                   _MK_SHIFT_CONST(4)
+#define AREMC_STAT_CONTROL_SKIP_FIELD                   (_MK_MASK_CONST(0x7) << AREMC_STAT_CONTROL_SKIP_SHIFT)
+#define AREMC_STAT_CONTROL_SKIP_RANGE                   _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(4)
+#define AREMC_STAT_CONTROL_SKIP_ROW                     0
+
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT                    _MK_SHIFT_CONST(8)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_CLIENT_TYPE_SHIFT)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_RANGE                    _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_ROW                      0
+#define AREMC_STAT_CONTROL_CLIENT_TYPE_MPCORER                  _MK_ENUM_CONST(0)
+
+#define AREMC_STAT_CONTROL_EVENT_SHIFT                  _MK_SHIFT_CONST(16)
+#define AREMC_STAT_CONTROL_EVENT_FIELD                  (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_EVENT_SHIFT)
+#define AREMC_STAT_CONTROL_EVENT_RANGE                  _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
+#define AREMC_STAT_CONTROL_EVENT_ROW                    0
+#define AREMC_STAT_CONTROL_EVENT_QUALIFIED                      _MK_ENUM_CONST(0)
+
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT                  _MK_SHIFT_CONST(26)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_FIELD                  (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_FILTER_CLIENT_SHIFT)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_RANGE                  _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_ROW                    0
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_DISABLE                        _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_FILTER_CLIENT_ENABLE                 _MK_ENUM_CONST(1)
+
+#define AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT                    _MK_SHIFT_CONST(27)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_FIELD                    (_MK_MASK_CONST(0x1) << AREMC_STAT_CONTROL_FILTER_ADDR_SHIFT)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_RANGE                    _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_ROW                      0
+#define AREMC_STAT_CONTROL_FILTER_ADDR_DISABLE                  _MK_ENUM_CONST(0)
+#define AREMC_STAT_CONTROL_FILTER_ADDR_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register EMC_STAT_LLMC_CONTROL_0_0  
+#define EMC_STAT_LLMC_CONTROL_0_0                       _MK_ADDR_CONST(0x178)
+#define EMC_STAT_LLMC_CONTROL_0_0_SECURE                        0x0
+#define EMC_STAT_LLMC_CONTROL_0_0_WORD_COUNT                    0x1
+#define EMC_STAT_LLMC_CONTROL_0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_FIELD                  (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SHIFT)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_RANGE                  31:0
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_WOFFSET                        0x0
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_CONTROL_0_0_LLMC_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 380 [0x17c] 
+
+// Packet AREMC_STAT_HIST_LIMIT
+#define AREMC_STAT_HIST_LIMIT_SIZE 32
+
+#define AREMC_STAT_HIST_LIMIT_LOW_SHIFT                 _MK_SHIFT_CONST(0)
+#define AREMC_STAT_HIST_LIMIT_LOW_FIELD                 (_MK_MASK_CONST(0xffff) << AREMC_STAT_HIST_LIMIT_LOW_SHIFT)
+#define AREMC_STAT_HIST_LIMIT_LOW_RANGE                 _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define AREMC_STAT_HIST_LIMIT_LOW_ROW                   0
+
+#define AREMC_STAT_HIST_LIMIT_HIGH_SHIFT                        _MK_SHIFT_CONST(16)
+#define AREMC_STAT_HIST_LIMIT_HIGH_FIELD                        (_MK_MASK_CONST(0xffff) << AREMC_STAT_HIST_LIMIT_HIGH_SHIFT)
+#define AREMC_STAT_HIST_LIMIT_HIGH_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define AREMC_STAT_HIST_LIMIT_HIGH_ROW                  0
+
+
+// Register EMC_STAT_LLMC_HIST_LIMIT_0_0  
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0                    _MK_ADDR_CONST(0x180)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_SECURE                     0x0
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_WORD_COUNT                         0x1
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_RESET_VAL                  _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_FIELD                    (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SHIFT)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_RANGE                    31:0
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_WOFFSET                  0x0
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_DEFAULT                  _MK_MASK_CONST(0xffff0000)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_LIMIT_0_0_LLMC_HIST_LIMIT_0_INIT_ENUM                        -65536
+
+
+// Reserved address 388 [0x184] 
+
+// Register EMC_STAT_LLMC_COUNT_0_0  
+#define EMC_STAT_LLMC_COUNT_0_0                 _MK_ADDR_CONST(0x188)
+#define EMC_STAT_LLMC_COUNT_0_0_SECURE                  0x0
+#define EMC_STAT_LLMC_COUNT_0_0_WORD_COUNT                      0x1
+#define EMC_STAT_LLMC_COUNT_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_COUNT_0_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SHIFT)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_RANGE                      31:0
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_WOFFSET                    0x0
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_COUNT_0_0_LLMC_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 396 [0x18c] 
+
+// Register EMC_STAT_LLMC_HIST_0_0  
+#define EMC_STAT_LLMC_HIST_0_0                  _MK_ADDR_CONST(0x190)
+#define EMC_STAT_LLMC_HIST_0_0_SECURE                   0x0
+#define EMC_STAT_LLMC_HIST_0_0_WORD_COUNT                       0x1
+#define EMC_STAT_LLMC_HIST_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_LLMC_HIST_0_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SHIFT)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_RANGE                        31:0
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_WOFFSET                      0x0
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_LLMC_HIST_0_0_LLMC_HIST_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 404 [0x194] 
+
+// Register EMC_STAT_PWR_CLOCK_LIMIT_0  
+#define EMC_STAT_PWR_CLOCK_LIMIT_0                      _MK_ADDR_CONST(0x198)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_SECURE                       0x0
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_WORD_COUNT                   0x1
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_RESET_VAL                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SHIFT)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_RANGE                        31:0
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_WOFFSET                      0x0
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_DEFAULT                      _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCK_LIMIT_0_PWR_CLOCK_LIMIT_INIT_ENUM                    -1
+
+
+// Register EMC_STAT_PWR_CLOCKS_0  
+#define EMC_STAT_PWR_CLOCKS_0                   _MK_ADDR_CONST(0x19c)
+#define EMC_STAT_PWR_CLOCKS_0_SECURE                    0x0
+#define EMC_STAT_PWR_CLOCKS_0_WORD_COUNT                        0x1
+#define EMC_STAT_PWR_CLOCKS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_CLOCKS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_FIELD                  (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SHIFT)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_RANGE                  31:0
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_WOFFSET                        0x0
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_CLOCKS_0_PWR_CLOCKS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_PWR_COUNT_0  
+#define EMC_STAT_PWR_COUNT_0                    _MK_ADDR_CONST(0x1a0)
+#define EMC_STAT_PWR_COUNT_0_SECURE                     0x0
+#define EMC_STAT_PWR_COUNT_0_WORD_COUNT                         0x1
+#define EMC_STAT_PWR_COUNT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_PWR_COUNT_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_FIELD                    (_MK_MASK_CONST(0xffffffff) << EMC_STAT_PWR_COUNT_0_PWR_COUNT_SHIFT)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_RANGE                    31:0
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_WOFFSET                  0x0
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_PWR_COUNT_0_PWR_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_CLOCK_LIMIT_LO_0  
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0                  _MK_ADDR_CONST(0x1a4)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_SECURE                   0x0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_WORD_COUNT                       0x1
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_RESET_VAL                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_SHIFT)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_RANGE                        31:0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_WOFFSET                      0x0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_DEFAULT                      _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_LO_0_DRAM_CLOCK_LIMIT_LO_INIT_ENUM                    -1
+
+
+// Register EMC_STAT_DRAM_CLOCK_LIMIT_HI_0  
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0                  _MK_ADDR_CONST(0x1a8)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_SECURE                   0x0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_WORD_COUNT                       0x1
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_RESET_VAL                        _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_FIELD                        (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_SHIFT)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_RANGE                        7:0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_WOFFSET                      0x0
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_DEFAULT                      _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCK_LIMIT_HI_0_DRAM_CLOCK_LIMIT_HI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_CLOCKS_LO_0  
+#define EMC_STAT_DRAM_CLOCKS_LO_0                       _MK_ADDR_CONST(0x1ac)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_CLOCKS_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_CLOCKS_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_FIELD                  (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_SHIFT)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_RANGE                  31:0
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_WOFFSET                        0x0
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_LO_0_DRAM_CLOCKS_LO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_CLOCKS_HI_0  
+#define EMC_STAT_DRAM_CLOCKS_HI_0                       _MK_ADDR_CONST(0x1b0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_CLOCKS_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_CLOCKS_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_FIELD                  (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_SHIFT)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_RANGE                  7:0
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_WOFFSET                        0x0
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_CLOCKS_HI_0_DRAM_CLOCKS_HI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0                    _MK_ADDR_CONST(0x1b4)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0_DEV0_ACTIVATE_CNT_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0                    _MK_ADDR_CONST(0x1b8)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0_DEV0_ACTIVATE_CNT_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_READ_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0                        _MK_ADDR_CONST(0x1bc)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_SECURE                         0x0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_WORD_COUNT                     0x1
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_LO_0_DEV0_READ_CNT_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_READ_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0                        _MK_ADDR_CONST(0x1c0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_SECURE                         0x0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_WORD_COUNT                     0x1
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_READ_CNT_HI_0_DEV0_READ_CNT_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0                       _MK_ADDR_CONST(0x1c4)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0_DEV0_WRITE_CNT_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0                       _MK_ADDR_CONST(0x1c8)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0_DEV0_WRITE_CNT_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_REF_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0                 _MK_ADDR_CONST(0x1cc)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_LO_0_DEV0_REF_CNT_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_REF_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0                 _MK_ADDR_CONST(0x1d0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_REF_CNT_HI_0_DEV0_REF_CNT_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0                       _MK_ADDR_CONST(0x1d4)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0                       _MK_ADDR_CONST(0x1d8)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0                       _MK_ADDR_CONST(0x1dc)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0                       _MK_ADDR_CONST(0x1e0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0  
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0                    _MK_ADDR_CONST(0x1e4)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0_DEV0_CKE_EQ1_CLKS_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0  
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0                    _MK_ADDR_CONST(0x1e8)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0_DEV0_CKE_EQ1_CLKS_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0                 _MK_ADDR_CONST(0x1ec)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0_DEV0_EXTCLKS_CKE_EQ1_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0                 _MK_ADDR_CONST(0x1f0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0_DEV0_EXTCLKS_CKE_EQ1_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0                 _MK_ADDR_CONST(0x1f4)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0_DEV0_EXTCLKS_CKE_EQ0_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0                 _MK_ADDR_CONST(0x1f8)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0_DEV0_EXTCLKS_CKE_EQ0_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0                    _MK_ADDR_CONST(0x1fc)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0_DEV1_ACTIVATE_CNT_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0                    _MK_ADDR_CONST(0x200)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0_DEV1_ACTIVATE_CNT_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_READ_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0                        _MK_ADDR_CONST(0x204)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_SECURE                         0x0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_WORD_COUNT                     0x1
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_LO_0_DEV1_READ_CNT_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_READ_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0                        _MK_ADDR_CONST(0x208)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_SECURE                         0x0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_WORD_COUNT                     0x1
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_READ_CNT_HI_0_DEV1_READ_CNT_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0                       _MK_ADDR_CONST(0x20c)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0_DEV1_WRITE_CNT_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0                       _MK_ADDR_CONST(0x210)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0_DEV1_WRITE_CNT_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_REF_CNT_LO_0  
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0                 _MK_ADDR_CONST(0x214)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_LO_0_DEV1_REF_CNT_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_REF_CNT_HI_0  
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0                 _MK_ADDR_CONST(0x218)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_REF_CNT_HI_0_DEV1_REF_CNT_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0                       _MK_ADDR_CONST(0x21c)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0                       _MK_ADDR_CONST(0x220)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0                       _MK_ADDR_CONST(0x224)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_FIELD                       (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_RANGE                       31:0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0                       _MK_ADDR_CONST(0x228)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SECURE                        0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_WORD_COUNT                    0x1
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_FIELD                       (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_RANGE                       7:0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_WOFFSET                     0x0
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0  
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0                    _MK_ADDR_CONST(0x22c)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_FIELD                 (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_RANGE                 31:0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0_DEV1_CKE_EQ1_CLKS_LO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0  
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0                    _MK_ADDR_CONST(0x230)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_SECURE                     0x0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_WORD_COUNT                         0x1
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_FIELD                 (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_RANGE                 7:0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_WOFFSET                       0x0
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0_DEV1_CKE_EQ1_CLKS_HI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0                 _MK_ADDR_CONST(0x234)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0_DEV1_EXTCLKS_CKE_EQ1_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0                 _MK_ADDR_CONST(0x238)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0_DEV1_EXTCLKS_CKE_EQ1_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0                 _MK_ADDR_CONST(0x23c)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0_DEV1_EXTCLKS_CKE_EQ0_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0                 _MK_ADDR_CONST(0x240)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0_DEV1_EXTCLKS_CKE_EQ0_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0                 _MK_ADDR_CONST(0x244)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0                 _MK_ADDR_CONST(0x248)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0                 _MK_ADDR_CONST(0x24c)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0                 _MK_ADDR_CONST(0x250)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0  
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0                 _MK_ADDR_CONST(0x254)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0  
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0                 _MK_ADDR_CONST(0x258)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0  
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0                 _MK_ADDR_CONST(0x25c)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_FIELD                   (_MK_MASK_CONST(0xffffffff) << EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_SHIFT)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_RANGE                   31:0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0  
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0                 _MK_ADDR_CONST(0x260)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SECURE                  0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_WORD_COUNT                      0x1
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT                   _MK_SHIFT_CONST(0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_FIELD                   (_MK_MASK_CONST(0xff) << EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_SHIFT)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_RANGE                   7:0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_WOFFSET                 0x0
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 612 [0x264] 
+
+// Reserved address 616 [0x268] 
+
+// Reserved address 620 [0x26c] 
+
+// Reserved address 624 [0x270] 
+
+// Reserved address 628 [0x274] 
+
+// Reserved address 632 [0x278] 
+
+// Reserved address 636 [0x27c] 
+
+// Reserved address 640 [0x280] 
+
+// Reserved address 644 [0x284] 
+
+// Reserved address 648 [0x288] 
+
+// Reserved address 652 [0x28c] 
+
+// Reserved address 656 [0x290] 
+
+// Reserved address 660 [0x294] 
+
+// Reserved address 664 [0x298] 
+
+// Reserved address 668 [0x29c] 
+
+// Reserved address 672 [0x2a0] 
+
+// Register EMC_AUTO_CAL_CONFIG_0  // Auto-calibration settings for EMC pads
+#define EMC_AUTO_CAL_CONFIG_0                   _MK_ADDR_CONST(0x2a4)
+#define EMC_AUTO_CAL_CONFIG_0_SECURE                    0x0
+#define EMC_AUTO_CAL_CONFIG_0_WORD_COUNT                        0x1
+#define EMC_AUTO_CAL_CONFIG_0_RESET_VAL                         _MK_MASK_CONST(0xa60000)
+#define EMC_AUTO_CAL_CONFIG_0_RESET_MASK                        _MK_MASK_CONST(0xf3ff1f1f)
+#define EMC_AUTO_CAL_CONFIG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_READ_MASK                         _MK_MASK_CONST(0xf3ff1f1f)
+#define EMC_AUTO_CAL_CONFIG_0_WRITE_MASK                        _MK_MASK_CONST(0x73ff1f1f)
+// 2's complement offset for pull-up value
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_RANGE                  4:0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_WOFFSET                        0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 2's complement offset for pull-down value
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT                  _MK_SHIFT_CONST(8)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_FIELD                  (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_RANGE                  12:8
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_WOFFSET                        0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Auto Cal calibration step interval (in emc clocks)
+// - the default is set for 1.0us calibration step at 166MHz
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT                       _MK_SHIFT_CONST(16)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_FIELD                       (_MK_MASK_CONST(0x3ff) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_RANGE                       25:16
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_WOFFSET                     0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT                     _MK_MASK_CONST(0xa6)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 0 (Normal operation) pad DRVDN/UP_SLWR/F tied to AUTO_CAL output
+//                      DRDVDN/UP_SLWR/F[3:0] = AUTO_CAL_PULLDOWN/UP[4:1]
+// 1 (override) use CFG2TMC_*_DRVDN/UP_SLWR/F pins to control pad slew inputs
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_SHIFT                        _MK_SHIFT_CONST(28)
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_FIELD                        (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_RANGE                        28:28
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_WOFFSET                      0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTOCAL_SLW_OVERRIDE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 1 (normal operation): use EMC generated pullup/dn (override or autocal) 0 (disabled): use cfg2tmc_xm2* register settings for pullup/dn
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SHIFT                     _MK_SHIFT_CONST(29)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_FIELD                     (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_RANGE                     29:29
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_WOFFSET                   0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_INIT_ENUM                 DISABLED
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_ENABLED                   _MK_ENUM_CONST(1)
+
+// 0 (normal operation): use AUTO_CAL_PU/PD_OFFSET as an offset 
+//                       to the calibration tate machine setting
+// 1 (override)        : use AUTO_CAL_PU/PD_OFFSET register 
+//                       values directly
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT                   _MK_SHIFT_CONST(30)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_RANGE                   30:30
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_WOFFSET                 0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Writing a one to this bit starts the calibration state
+// machine.  This bit must be set even if the override is
+// set in order to latch in the override value.
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT                      _MK_SHIFT_CONST(31)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_FIELD                      (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SHIFT)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_RANGE                      31:31
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_WOFFSET                    0x0
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AUTO_CAL_INTERVAL_0  // EMC pad calibration interval
+#define EMC_AUTO_CAL_INTERVAL_0                 _MK_ADDR_CONST(0x2a8)
+#define EMC_AUTO_CAL_INTERVAL_0_SECURE                  0x0
+#define EMC_AUTO_CAL_INTERVAL_0_WORD_COUNT                      0x1
+#define EMC_AUTO_CAL_INTERVAL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_RESET_MASK                      _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_READ_MASK                       _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_WRITE_MASK                      _MK_MASK_CONST(0xfffffff)
+// 0: do calibration once
+// Otherwise, auto-calibration occurs at intervals equivalent
+// to the programmed number of cycles.
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_FIELD                 (_MK_MASK_CONST(0xfffffff) << EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_RANGE                 27:0
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_WOFFSET                       0x0
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xfffffff)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_AUTO_CAL_STATUS_0  // EMC pad calibration status
+#define EMC_AUTO_CAL_STATUS_0                   _MK_ADDR_CONST(0x2ac)
+#define EMC_AUTO_CAL_STATUS_0_SECURE                    0x0
+#define EMC_AUTO_CAL_STATUS_0_WORD_COUNT                        0x1
+#define EMC_AUTO_CAL_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x9f1f1f1f)
+#define EMC_AUTO_CAL_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Pullup code generated by auto-calibration
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_FIELD                     (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_RANGE                     4:0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_WOFFSET                   0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pulldown code generated by auto-calibration
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_FIELD                   (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_RANGE                   12:8
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_WOFFSET                 0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pullup code sent to pads
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT                 _MK_SHIFT_CONST(16)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_FIELD                 (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_RANGE                 20:16
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_WOFFSET                       0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLUP_ADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Pulldown code sent to pads
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT                       _MK_SHIFT_CONST(24)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_FIELD                       (_MK_MASK_CONST(0x1f) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_RANGE                       28:24
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_WOFFSET                     0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_PULLDOWN_ADJ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// One when auto calibrate is active
+// - valid only after auto calibrate sequence has 
+// completed (EMC_CAL_ACTIVE == 0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT                     _MK_SHIFT_CONST(31)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_FIELD                     (_MK_MASK_CONST(0x1) << EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SHIFT)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_RANGE                     31:31
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_WOFFSET                   0x0
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_AUTO_CAL_STATUS_0_AUTO_CAL_ACTIVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EMC_REQ_CTRL_0  // Request status/control
+#define EMC_REQ_CTRL_0                  _MK_ADDR_CONST(0x2b0)
+#define EMC_REQ_CTRL_0_SECURE                   0x0
+#define EMC_REQ_CTRL_0_WORD_COUNT                       0x1
+#define EMC_REQ_CTRL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_RESET_MASK                       _MK_MASK_CONST(0x3)
+#define EMC_REQ_CTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_READ_MASK                        _MK_MASK_CONST(0x3)
+#define EMC_REQ_CTRL_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
+// Stall incoming read transactions (1st non-LL read will stall all transactions)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_FIELD                    (_MK_MASK_CONST(0x1) << EMC_REQ_CTRL_0_STALL_ALL_READS_SHIFT)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_RANGE                    0:0
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_WOFFSET                  0x0
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_STALL_ALL_READS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Stall incoming write transactions
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_SHIFT                   _MK_SHIFT_CONST(1)
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_FIELD                   (_MK_MASK_CONST(0x1) << EMC_REQ_CTRL_0_STALL_ALL_WRITES_SHIFT)
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_RANGE                   1:1
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_WOFFSET                 0x0
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_REQ_CTRL_0_STALL_ALL_WRITES_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register EMC_EMC_STATUS_0  // EMC state-machine status
+#define EMC_EMC_STATUS_0                        _MK_ADDR_CONST(0x2b4)
+#define EMC_EMC_STATUS_0_SECURE                         0x0
+#define EMC_EMC_STATUS_0_WORD_COUNT                     0x1
+#define EMC_EMC_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x1f3337)
+#define EMC_EMC_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Request fifo is empty
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_FIELD                       (_MK_MASK_CONST(0x1) << EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_SHIFT)
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_RANGE                       0:0
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_WOFFSET                     0x0
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_REQ_FIFO_EMPTY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// LL Request fifo is empty
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_SHIFT                    _MK_SHIFT_CONST(1)
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_FIELD                    (_MK_MASK_CONST(0x1) << EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_SHIFT)
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_RANGE                    1:1
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_WOFFSET                  0x0
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_EMC_LL_REQ_FIFO_EMPTY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// All non-stalled requests have completed 
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_SHIFT                      _MK_SHIFT_CONST(2)
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_FIELD                      (_MK_MASK_CONST(0x1) << EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_SHIFT)
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_RANGE                      2:2
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_WOFFSET                    0x0
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_NO_OUTSTANDING_TRANSACTIONS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// dev[n] has entered powerdown state (incoming req's will awaken if not stalled)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(4)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x3) << EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_SHIFT)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_RANGE                        5:4
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_WOFFSET                      0x0
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// dev[n] has been put into self-refresh (will remain until SR exit cmd).
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_SHIFT                     _MK_SHIFT_CONST(8)
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_FIELD                     (_MK_MASK_CONST(0x3) << EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_SHIFT)
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_RANGE                     9:8
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_WOFFSET                   0x0
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_SELF_REFRESH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// dev[n] has been put into deep powerdown state
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_SHIFT                      _MK_SHIFT_CONST(12)
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_FIELD                      (_MK_MASK_CONST(0x3) << EMC_EMC_STATUS_0_DRAM_IN_DPD_SHIFT)
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_RANGE                      13:12
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_WOFFSET                    0x0
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_DRAM_IN_DPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// mrr fifospace available
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_FIELD                   (_MK_MASK_CONST(0xf) << EMC_EMC_STATUS_0_MRR_FIFO_SPACE_SHIFT)
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_RANGE                   19:16
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_WOFFSET                 0x0
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_FIFO_SPACE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// mrr data available for reading
+#define EMC_EMC_STATUS_0_MRR_DIVLD_SHIFT                        _MK_SHIFT_CONST(20)
+#define EMC_EMC_STATUS_0_MRR_DIVLD_FIELD                        (_MK_MASK_CONST(0x1) << EMC_EMC_STATUS_0_MRR_DIVLD_SHIFT)
+#define EMC_EMC_STATUS_0_MRR_DIVLD_RANGE                        20:20
+#define EMC_EMC_STATUS_0_MRR_DIVLD_WOFFSET                      0x0
+#define EMC_EMC_STATUS_0_MRR_DIVLD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_DIVLD_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_DIVLD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_EMC_STATUS_0_MRR_DIVLD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_CFG_2_0  // EMC Configuration
+#define EMC_CFG_2_0                     _MK_ADDR_CONST(0x2b8)
+#define EMC_CFG_2_0_SECURE                      0x0
+#define EMC_CFG_2_0_WORD_COUNT                  0x1
+#define EMC_CFG_2_0_RESET_VAL                   _MK_MASK_CONST(0x3)
+#define EMC_CFG_2_0_RESET_MASK                  _MK_MASK_CONST(0x80330707)
+#define EMC_CFG_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_READ_MASK                   _MK_MASK_CONST(0x80330707)
+#define EMC_CFG_2_0_WRITE_MASK                  _MK_MASK_CONST(0x80330707)
+// allows EMC and CAR to handshake on PLL divider/source changes.
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_SHIFT)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_RANGE                  0:0
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_WOFFSET                        0x0
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_INIT_ENUM                      ENABLED
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// Forces dram into power-down during CLKCHANGE.
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_SHIFT                   _MK_SHIFT_CONST(1)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_SHIFT)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_RANGE                   1:1
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_WOFFSET                 0x0
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_INIT_ENUM                       ENABLED
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// Forces dram into self-refresh during CLKCHANGE.   Takes precedent over CLKCHANGE_PD_ENABLE if both are set.
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_SHIFT                   _MK_SHIFT_CONST(2)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_SHIFT)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_RANGE                   2:2
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_WOFFSET                 0x0
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_INIT_ENUM                       DISABLED
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// Remaps address/command pins for LPDDR_POP ball-out otherwise    uses standard LPDDR2 pin configuration.
+#define EMC_CFG_2_0_PIN_CONFIG_SHIFT                    _MK_SHIFT_CONST(8)
+#define EMC_CFG_2_0_PIN_CONFIG_FIELD                    (_MK_MASK_CONST(0x3) << EMC_CFG_2_0_PIN_CONFIG_SHIFT)
+#define EMC_CFG_2_0_PIN_CONFIG_RANGE                    9:8
+#define EMC_CFG_2_0_PIN_CONFIG_WOFFSET                  0x0
+#define EMC_CFG_2_0_PIN_CONFIG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_PIN_CONFIG_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define EMC_CFG_2_0_PIN_CONFIG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_PIN_CONFIG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_PIN_CONFIG_INIT_ENUM                        LPDDR2
+#define EMC_CFG_2_0_PIN_CONFIG_LPDDR2                   _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_PIN_CONFIG_LPDDR_POP                        _MK_ENUM_CONST(1)
+#define EMC_CFG_2_0_PIN_CONFIG_RESERVED                 _MK_ENUM_CONST(2)
+
+// Used to select source for DRAM clock.  If enabled, xm2_addr_mclk pins   instead of xm2_mclk.  the former is located adjacent to addr pins used
+//   in lpddr2 (for lower clk to addr skew).  If disabled, xm2_addr_mclk will
+//   be disabled & xm2_mclk will output DRAM clock (required for LPDDR_POP).
+#define EMC_CFG_2_0_USE_ADDR_CLK_SHIFT                  _MK_SHIFT_CONST(10)
+#define EMC_CFG_2_0_USE_ADDR_CLK_FIELD                  (_MK_MASK_CONST(0x1) << EMC_CFG_2_0_USE_ADDR_CLK_SHIFT)
+#define EMC_CFG_2_0_USE_ADDR_CLK_RANGE                  10:10
+#define EMC_CFG_2_0_USE_ADDR_CLK_WOFFSET                        0x0
+#define EMC_CFG_2_0_USE_ADDR_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_USE_ADDR_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_USE_ADDR_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_USE_ADDR_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_USE_ADDR_CLK_INIT_ENUM                      DISABLED
+#define EMC_CFG_2_0_USE_ADDR_CLK_DISABLED                       _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_USE_ADDR_CLK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Indicates which AP bytelane is connected to DRAM byte 0 (over which MRR data is returned).
+#define EMC_CFG_2_0_MRR_BYTESEL_SHIFT                   _MK_SHIFT_CONST(16)
+#define EMC_CFG_2_0_MRR_BYTESEL_FIELD                   (_MK_MASK_CONST(0x3) << EMC_CFG_2_0_MRR_BYTESEL_SHIFT)
+#define EMC_CFG_2_0_MRR_BYTESEL_RANGE                   17:16
+#define EMC_CFG_2_0_MRR_BYTESEL_WOFFSET                 0x0
+#define EMC_CFG_2_0_MRR_BYTESEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_MRR_BYTESEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define EMC_CFG_2_0_MRR_BYTESEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_MRR_BYTESEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// If using 2 X16 DRAM on a single CS to form 32-bit wide data,
+//   indicates which bytelane 2nd DRAM's byte 0 is connected to.
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_SHIFT                       _MK_SHIFT_CONST(20)
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_FIELD                       (_MK_MASK_CONST(0x3) << EMC_CFG_2_0_MRR_BYTESEL_X16_SHIFT)
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_RANGE                       21:20
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_WOFFSET                     0x0
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_MRR_BYTESEL_X16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// CYA bit, gives priority to activates over precharges,  determining which    (precharge/activate) is processed first if both are pending and unblocked.
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_SHIFT                      _MK_SHIFT_CONST(31)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CFG_2_0_DRAMC_PRE_B4_ACT_SHIFT)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_RANGE                      31:31
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_WOFFSET                    0x0
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_INIT_ENUM                  DISABLED
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CFG_2_0_DRAMC_PRE_B4_ACT_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register EMC_CFG_DIG_DLL_0  // Configure Digital DLL
+#define EMC_CFG_DIG_DLL_0                       _MK_ADDR_CONST(0x2bc)
+#define EMC_CFG_DIG_DLL_0_SECURE                        0x0
+#define EMC_CFG_DIG_DLL_0_WORD_COUNT                    0x1
+#define EMC_CFG_DIG_DLL_0_RESET_VAL                     _MK_MASK_CONST(0x57)
+#define EMC_CFG_DIG_DLL_0_RESET_MASK                    _MK_MASK_CONST(0x7bff0fff)
+#define EMC_CFG_DIG_DLL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_READ_MASK                     _MK_MASK_CONST(0xfbff0fff)
+#define EMC_CFG_DIG_DLL_0_WRITE_MASK                    _MK_MASK_CONST(0x3bff0fff)
+// Enable digital DLL's.
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLL_EN_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_RANGE                      0:0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_WOFFSET                    0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_INIT_ENUM                  ENABLED
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_EN_ENABLED                    _MK_ENUM_CONST(1)
+
+// Enable DL trimmer cells (embedded in pads).
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_SHIFT                      _MK_SHIFT_CONST(1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_RANGE                      1:1
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_WOFFSET                    0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_INIT_ENUM                  ENABLED
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_ENABLED                    _MK_ENUM_CONST(1)
+
+// Override DLL's DLI output w/ OVERRIDE_VAL (still uses mult/offset).
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_FIELD                     (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_RANGE                     2:2
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_WOFFSET                   0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_INIT_ENUM                 ENABLED
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_DISABLED                  _MK_ENUM_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_ENABLED                   _MK_ENUM_CONST(1)
+
+// Turn off upper DLL & use lower dll output to drive all trimmers.
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_SHIFT                      _MK_SHIFT_CONST(3)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_FIELD                      (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_RANGE                      3:3
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_WOFFSET                    0x0
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_INIT_ENUM                  DISABLED
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_DISABLED                   _MK_ENUM_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_ENABLED                    _MK_ENUM_CONST(1)
+
+// Set trimmer values directly for each byte via    FBIO_QUSE_DLY/FBIO_DQS_DLY & FBIO_QUSE_DLY_MSB/FBIO_DQS_DLY_MSB.
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(4)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_FIELD                    (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_RANGE                    4:4
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_WOFFSET                  0x0
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_INIT_ENUM                        ENABLED
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_DISABLED                 _MK_ENUM_CONST(0)
+#define EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_ENABLED                  _MK_ENUM_CONST(1)
+
+// Enable DLL for use w/ lowspeed EMCCLK operation (<200MHz).
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_SHIFT                        _MK_SHIFT_CONST(5)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_FIELD                        (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_RANGE                        5:5
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_WOFFSET                      0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Controls how frequently DLL runs, as follows
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_SHIFT                    _MK_SHIFT_CONST(6)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_FIELD                    (_MK_MASK_CONST(0x3) << EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RANGE                    7:6
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_WOFFSET                  0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_INIT_ENUM                        RUN_TIL_LOCK
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RUN_CONTINUOUS                   _MK_ENUM_CONST(0)    // // DLL will run continuously (only disabled during reads).  This option will consume the most power.
+
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RUN_TIL_LOCK                     _MK_ENUM_CONST(1)    // // after DLL_RESET is set, DLL will run until it has locked, then be disabled
+
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RUN_PERIODIC                     _MK_ENUM_CONST(2)    // // DLL will be re-enabled w/ each refresh to make sure LOCK is maintained
+
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RESERVED                 _MK_ENUM_CONST(3)
+
+// DLL Loop filter control (2^(udset+3)).
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_FIELD                   (_MK_MASK_CONST(0xf) << EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_RANGE                   11:8
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_WOFFSET                 0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Value to use in place of DLI output if CFG_DLL_OVERRIDE_EN is set.
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_SHIFT                    _MK_SHIFT_CONST(16)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_FIELD                    (_MK_MASK_CONST(0x3ff) << EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_RANGE                    25:16
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_WOFFSET                  0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3ff)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CYA bit -- disable override of DLL logic when DLL_ALM is set
+//     (otherwise overrides DLI to 0x3FF).
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_SHIFT                   _MK_SHIFT_CONST(27)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_FIELD                   (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_RANGE                   27:27
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_WOFFSET                 0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_ALARM_DISABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// CYA in case DLL has problems locking. DLL will be treated as locked 
+//     after LIMIT emcclk cycles. Counter is reset w/ DLL_RESET (from above) 
+//     or w/ each periodic update (if using RUN_PERIODIC).  Settings are:
+//       00:  LIMIT = 2^12
+//       01:  LIMIT = 2^15
+//       10:  LIMIT = 2^16
+//       11:  LIMIT = 2^16 + 2^17
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_SHIFT                      _MK_SHIFT_CONST(28)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_FIELD                      (_MK_MASK_CONST(0x3) << EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_RANGE                      29:28
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_WOFFSET                    0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Writing 1 to this register will send reset pulse to DLL's on next shadow
+//     update.  Must reset DLL's when changing clock frequency by factor >= 2
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_SHIFT                       _MK_SHIFT_CONST(30)
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_FIELD                       (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_DLL_RESET_SHIFT)
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_RANGE                       30:30
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_WOFFSET                     0x0
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_DLL_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Writing 1 to this register causes override_val to be used in place of
+// DLL output until DLL_LOCK is obtained.  Takes effect on next shadow update.
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_SHIFT                 _MK_SHIFT_CONST(31)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_SHIFT)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_RANGE                 31:31
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_WOFFSET                       0x0
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_DIG_DLL_0_CFG_DLL_USE_OVERRIDE_UNTIL_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DLL_XFORM_DQS_0  // Configure Digital DLL
+#define EMC_DLL_XFORM_DQS_0                     _MK_ADDR_CONST(0x2c0)
+#define EMC_DLL_XFORM_DQS_0_SECURE                      0x0
+#define EMC_DLL_XFORM_DQS_0_WORD_COUNT                  0x1
+#define EMC_DLL_XFORM_DQS_0_RESET_VAL                   _MK_MASK_CONST(0x10)
+#define EMC_DLL_XFORM_DQS_0_RESET_MASK                  _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_DQS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_DQS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_DQS_0_READ_MASK                   _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_DQS_0_WRITE_MASK                  _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_FIELD                        (_MK_MASK_CONST(0x1f) << EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_SHIFT)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_RANGE                        4:0
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_WOFFSET                      0x0
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_DEFAULT                      _MK_MASK_CONST(0x10)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_SHIFT                        _MK_SHIFT_CONST(8)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_FIELD                        (_MK_MASK_CONST(0x7fff) << EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_SHIFT)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_RANGE                        22:8
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_WOFFSET                      0x0
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_DEFAULT_MASK                 _MK_MASK_CONST(0x7fff)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DLL_XFORM_QUSE_0  // Configure Digital DLL
+#define EMC_DLL_XFORM_QUSE_0                    _MK_ADDR_CONST(0x2c4)
+#define EMC_DLL_XFORM_QUSE_0_SECURE                     0x0
+#define EMC_DLL_XFORM_QUSE_0_WORD_COUNT                         0x1
+#define EMC_DLL_XFORM_QUSE_0_RESET_VAL                  _MK_MASK_CONST(0x8)
+#define EMC_DLL_XFORM_QUSE_0_RESET_MASK                         _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_QUSE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_QUSE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_QUSE_0_READ_MASK                  _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_QUSE_0_WRITE_MASK                         _MK_MASK_CONST(0x7fff1f)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_FIELD                      (_MK_MASK_CONST(0x1f) << EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_SHIFT)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_RANGE                      4:0
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_WOFFSET                    0x0
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_DEFAULT                    _MK_MASK_CONST(0x8)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_SHIFT                      _MK_SHIFT_CONST(8)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_FIELD                      (_MK_MASK_CONST(0x7fff) << EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_SHIFT)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_RANGE                      22:8
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_WOFFSET                    0x0
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_DEFAULT_MASK                       _MK_MASK_CONST(0x7fff)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DIG_DLL_UPPER_STATUS_0  // Digital DLL Status
+#define EMC_DIG_DLL_UPPER_STATUS_0                      _MK_ADDR_CONST(0x2c8)
+#define EMC_DIG_DLL_UPPER_STATUS_0_SECURE                       0x0
+#define EMC_DIG_DLL_UPPER_STATUS_0_WORD_COUNT                   0x1
+#define EMC_DIG_DLL_UPPER_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_READ_MASK                    _MK_MASK_CONST(0xe3ff)
+#define EMC_DIG_DLL_UPPER_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_FIELD                  (_MK_MASK_CONST(0x3ff) << EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_SHIFT)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_RANGE                  9:0
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_WOFFSET                        0x0
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_SHIFT                 _MK_SHIFT_CONST(13)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_SHIFT)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_RANGE                 13:13
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_WOFFSET                       0x0
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_TIMEOUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_SHIFT                        _MK_SHIFT_CONST(14)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_SHIFT)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_RANGE                        14:14
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_WOFFSET                      0x0
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_ALARM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_SHIFT                 _MK_SHIFT_CONST(15)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_SHIFT)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_RANGE                 15:15
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_WOFFSET                       0x0
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_UPPER_STATUS_0_DLL_UPPER_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_DIG_DLL_LOWER_STATUS_0  // Digital DLL Status
+#define EMC_DIG_DLL_LOWER_STATUS_0                      _MK_ADDR_CONST(0x2cc)
+#define EMC_DIG_DLL_LOWER_STATUS_0_SECURE                       0x0
+#define EMC_DIG_DLL_LOWER_STATUS_0_WORD_COUNT                   0x1
+#define EMC_DIG_DLL_LOWER_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_READ_MASK                    _MK_MASK_CONST(0xe3ff)
+#define EMC_DIG_DLL_LOWER_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_SHIFT                  _MK_SHIFT_CONST(0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_FIELD                  (_MK_MASK_CONST(0x3ff) << EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_SHIFT)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_RANGE                  9:0
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_WOFFSET                        0x0
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_OUT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_SHIFT                 _MK_SHIFT_CONST(13)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_SHIFT)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_RANGE                 13:13
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_WOFFSET                       0x0
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_TIMEOUT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_SHIFT                        _MK_SHIFT_CONST(14)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_FIELD                        (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_SHIFT)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_RANGE                        14:14
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_WOFFSET                      0x0
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_ALARM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_SHIFT                 _MK_SHIFT_CONST(15)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_FIELD                 (_MK_MASK_CONST(0x1) << EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_SHIFT)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_RANGE                 15:15
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_WOFFSET                       0x0
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_DIG_DLL_LOWER_STATUS_0_DLL_LOWER_LOCK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_CFG_CLKTRIM_0_0  // Configures m4clk trimmers
+#define EMC_CFG_CLKTRIM_0_0                     _MK_ADDR_CONST(0x2d0)
+#define EMC_CFG_CLKTRIM_0_0_SECURE                      0x0
+#define EMC_CFG_CLKTRIM_0_0_WORD_COUNT                  0x1
+#define EMC_CFG_CLKTRIM_0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_0_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_RANGE                     5:0
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_WOFFSET                   0x0
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_MAX                       _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_SHIFT                     _MK_SHIFT_CONST(6)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_RANGE                     11:6
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_WOFFSET                   0x0
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_MAX                       _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_SHIFT                     _MK_SHIFT_CONST(12)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_RANGE                     17:12
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_WOFFSET                   0x0
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_MAX                       _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_SHIFT                     _MK_SHIFT_CONST(18)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_FIELD                     (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_RANGE                     23:18
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_WOFFSET                   0x0
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_MAX                       _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_SHIFT                 _MK_SHIFT_CONST(24)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_FIELD                 (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_RANGE                 29:24
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_WOFFSET                       0x0
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_MAX                   _MK_ENUM_CONST(47)
+
+
+// Register EMC_CFG_CLKTRIM_1_0  // Configures m4clk trimmers
+#define EMC_CFG_CLKTRIM_1_0                     _MK_ADDR_CONST(0x2d4)
+#define EMC_CFG_CLKTRIM_1_0_SECURE                      0x0
+#define EMC_CFG_CLKTRIM_1_0_WORD_COUNT                  0x1
+#define EMC_CFG_CLKTRIM_1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_1_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_FIELD                      (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_RANGE                      5:0
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_WOFFSET                    0x0
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_MAX                        _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_SHIFT                      _MK_SHIFT_CONST(6)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_FIELD                      (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_RANGE                      11:6
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_WOFFSET                    0x0
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_MAX                        _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_SHIFT                      _MK_SHIFT_CONST(12)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_FIELD                      (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_RANGE                      17:12
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_WOFFSET                    0x0
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_MAX                        _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_SHIFT                      _MK_SHIFT_CONST(18)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_FIELD                      (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_RANGE                      23:18
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_WOFFSET                    0x0
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_MAX                        _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_SHIFT                      _MK_SHIFT_CONST(24)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_FIELD                      (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_RANGE                      29:24
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_WOFFSET                    0x0
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_MAX                        _MK_ENUM_CONST(47)
+
+
+// Register EMC_CFG_CLKTRIM_2_0  // Configures m4clk trimmers
+#define EMC_CFG_CLKTRIM_2_0                     _MK_ADDR_CONST(0x2d8)
+#define EMC_CFG_CLKTRIM_2_0_SECURE                      0x0
+#define EMC_CFG_CLKTRIM_2_0_WORD_COUNT                  0x1
+#define EMC_CFG_CLKTRIM_2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_RESET_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_READ_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_2_0_WRITE_MASK                  _MK_MASK_CONST(0x3fffffff)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_SHIFT                       _MK_SHIFT_CONST(0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_RANGE                       5:0
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_WOFFSET                     0x0
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_MAX                 _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_SHIFT                       _MK_SHIFT_CONST(6)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_RANGE                       11:6
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_WOFFSET                     0x0
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_MAX                 _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_SHIFT                       _MK_SHIFT_CONST(12)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_RANGE                       17:12
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_WOFFSET                     0x0
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_MAX                 _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_SHIFT                       _MK_SHIFT_CONST(18)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_RANGE                       23:18
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_WOFFSET                     0x0
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_MAX                 _MK_ENUM_CONST(47)
+
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_SHIFT                       _MK_SHIFT_CONST(24)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_FIELD                       (_MK_MASK_CONST(0x3f) << EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_SHIFT)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_RANGE                       29:24
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_WOFFSET                     0x0
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_MAX                 _MK_ENUM_CONST(47)
+
+
+// Register EMC_CTT_TERM_CTRL_0  // Configure CTT termination output drive strength
+#define EMC_CTT_TERM_CTRL_0                     _MK_ADDR_CONST(0x2dc)
+#define EMC_CTT_TERM_CTRL_0_SECURE                      0x0
+#define EMC_CTT_TERM_CTRL_0_WORD_COUNT                  0x1
+#define EMC_CTT_TERM_CTRL_0_RESET_VAL                   _MK_MASK_CONST(0x802)
+#define EMC_CTT_TERM_CTRL_0_RESET_MASK                  _MK_MASK_CONST(0x80001f07)
+#define EMC_CTT_TERM_CTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_READ_MASK                   _MK_MASK_CONST(0x9f0f9f07)
+#define EMC_CTT_TERM_CTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x80001f07)
+// 
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_SHIFT                    _MK_SHIFT_CONST(0)
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_FIELD                    (_MK_MASK_CONST(0x7) << EMC_CTT_TERM_CTRL_0_TERM_SLOPE_SHIFT)
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_RANGE                    2:0
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_WOFFSET                  0x0
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_DEFAULT                  _MK_MASK_CONST(0x2)
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_SLOPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_SHIFT                   _MK_SHIFT_CONST(8)
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_FIELD                   (_MK_MASK_CONST(0x1f) << EMC_CTT_TERM_CTRL_0_TERM_OFFSET_SHIFT)
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_RANGE                   12:8
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_WOFFSET                 0x0
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_DEFAULT                 _MK_MASK_CONST(0x8)
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_SHIFT                    _MK_SHIFT_CONST(15)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_FIELD                    (_MK_MASK_CONST(0x1f) << EMC_CTT_TERM_CTRL_0_TERM_DRVDN_SHIFT)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_RANGE                    19:15
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_WOFFSET                  0x0
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_SHIFT                    _MK_SHIFT_CONST(24)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_FIELD                    (_MK_MASK_CONST(0x1f) << EMC_CTT_TERM_CTRL_0_TERM_DRVUP_SHIFT)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_RANGE                    28:24
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_WOFFSET                  0x0
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_DRVUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_SHIFT                 _MK_SHIFT_CONST(31)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_FIELD                 (_MK_MASK_CONST(0x1) << EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_SHIFT)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_RANGE                 31:31
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_WOFFSET                       0x0
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_INIT_ENUM                     DISABLED
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_DISABLED                      _MK_ENUM_CONST(0)
+#define EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register EMC_ZCAL_REF_CNT_0  // Configure ZQ Calibration
+#define EMC_ZCAL_REF_CNT_0                      _MK_ADDR_CONST(0x2e0)
+#define EMC_ZCAL_REF_CNT_0_SECURE                       0x0
+#define EMC_ZCAL_REF_CNT_0_WORD_COUNT                   0x1
+#define EMC_ZCAL_REF_CNT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_REF_CNT_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define EMC_ZCAL_REF_CNT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_REF_CNT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_REF_CNT_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define EMC_ZCAL_REF_CNT_0_WRITE_MASK                   _MK_MASK_CONST(0xffffff)
+// Number of refreshes to wait between issuance of ZCAL_MRW_CMD.  If 0, ZCAL is disabled and internal counter will be reset.
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_FIELD                      (_MK_MASK_CONST(0xffffff) << EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_SHIFT)
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_RANGE                      23:0
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_WOFFSET                    0x0
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xffffff)
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register EMC_ZCAL_WAIT_CNT_0  // Configure ZQ Calibration
+#define EMC_ZCAL_WAIT_CNT_0                     _MK_ADDR_CONST(0x2e4)
+#define EMC_ZCAL_WAIT_CNT_0_SECURE                      0x0
+#define EMC_ZCAL_WAIT_CNT_0_WORD_COUNT                  0x1
+#define EMC_ZCAL_WAIT_CNT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_WAIT_CNT_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_ZCAL_WAIT_CNT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_WAIT_CNT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_WAIT_CNT_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define EMC_ZCAL_WAIT_CNT_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+// Number of emc clocks to wait before issuing any commands after sending ZCAL_MRW_CMD.
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_FIELD                 (_MK_MASK_CONST(0xff) << EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_SHIFT)
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_RANGE                 7:0
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_WOFFSET                       0x0
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EMC_ZCAL_MRW_CMD_0  // Configure ZQ Calibration
+#define EMC_ZCAL_MRW_CMD_0                      _MK_ADDR_CONST(0x2e8)
+#define EMC_ZCAL_MRW_CMD_0_SECURE                       0x0
+#define EMC_ZCAL_MRW_CMD_0_WORD_COUNT                   0x1
+#define EMC_ZCAL_MRW_CMD_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_WRITE_MASK                   _MK_MASK_CONST(0xc0ff00ff)
+// MRW OP field to be sent after ZCAL_REF_CNT
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_FIELD                      (_MK_MASK_CONST(0xff) << EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_SHIFT)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_RANGE                      7:0
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_WOFFSET                    0x0
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// MRW MA field to be sent after ZCAL_REF_CNT
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_SHIFT                      _MK_SHIFT_CONST(16)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_FIELD                      (_MK_MASK_CONST(0xff) << EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_SHIFT)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_RANGE                      23:16
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_WOFFSET                    0x0
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// active-low chip-select, 0x0 applies command to both devices (will happen 1 at a time), 0x2 to for only dev0, 0x1 for dev1.
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_SHIFT                     _MK_SHIFT_CONST(30)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_FIELD                     (_MK_MASK_CONST(0x3) << EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_SHIFT)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_RANGE                     31:30
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_WOFFSET                   0x0
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EMC_ZCAL_MRW_CMD_0_ZQ_MRW_DEV_SELECTN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_AREMC_REGS(_op_) \
+_op_(EMC_INTSTATUS_0) \
+_op_(EMC_INTMASK_0) \
+_op_(EMC_DBG_0) \
+_op_(EMC_CFG_0) \
+_op_(EMC_ADR_CFG_0) \
+_op_(EMC_ADR_CFG_1_0) \
+_op_(EMC_REFCTRL_0) \
+_op_(EMC_PIN_0) \
+_op_(EMC_TIMING_CONTROL_0) \
+_op_(EMC_RC_0) \
+_op_(EMC_RFC_0) \
+_op_(EMC_RAS_0) \
+_op_(EMC_RP_0) \
+_op_(EMC_R2W_0) \
+_op_(EMC_W2R_0) \
+_op_(EMC_R2P_0) \
+_op_(EMC_W2P_0) \
+_op_(EMC_RD_RCD_0) \
+_op_(EMC_WR_RCD_0) \
+_op_(EMC_RRD_0) \
+_op_(EMC_REXT_0) \
+_op_(EMC_WDV_0) \
+_op_(EMC_QUSE_0) \
+_op_(EMC_QRST_0) \
+_op_(EMC_QSAFE_0) \
+_op_(EMC_RDV_0) \
+_op_(EMC_REFRESH_0) \
+_op_(EMC_BURST_REFRESH_NUM_0) \
+_op_(EMC_PDEX2WR_0) \
+_op_(EMC_PDEX2RD_0) \
+_op_(EMC_PCHG2PDEN_0) \
+_op_(EMC_ACT2PDEN_0) \
+_op_(EMC_AR2PDEN_0) \
+_op_(EMC_RW2PDEN_0) \
+_op_(EMC_TXSR_0) \
+_op_(EMC_TCKE_0) \
+_op_(EMC_TFAW_0) \
+_op_(EMC_TRPAB_0) \
+_op_(EMC_TCLKSTABLE_0) \
+_op_(EMC_TCLKSTOP_0) \
+_op_(EMC_TREFBW_0) \
+_op_(EMC_QUSE_EXTRA_0) \
+_op_(EMC_ODT_WRITE_0) \
+_op_(EMC_ODT_READ_0) \
+_op_(EMC_MRS_0) \
+_op_(EMC_EMRS_0) \
+_op_(EMC_REF_0) \
+_op_(EMC_PRE_0) \
+_op_(EMC_NOP_0) \
+_op_(EMC_SELF_REF_0) \
+_op_(EMC_DPD_0) \
+_op_(EMC_MRW_0) \
+_op_(EMC_MRR_0) \
+_op_(EMC_CMDQ_0) \
+_op_(EMC_FBIO_CFG1_0) \
+_op_(EMC_FBIO_DQSIB_DLY_0) \
+_op_(EMC_FBIO_DQSIB_DLY_MSB_0) \
+_op_(EMC_FBIO_SPARE_0) \
+_op_(EMC_FBIO_CFG5_0) \
+_op_(EMC_FBIO_WRPTR_EQ_2_0) \
+_op_(EMC_FBIO_QUSE_DLY_0) \
+_op_(EMC_FBIO_QUSE_DLY_MSB_0) \
+_op_(EMC_FBIO_CFG6_0) \
+_op_(EMC_DQS_TRIMMER_RD0_0) \
+_op_(EMC_DQS_TRIMMER_RD1_0) \
+_op_(EMC_DQS_TRIMMER_RD2_0) \
+_op_(EMC_DQS_TRIMMER_RD3_0) \
+_op_(EMC_CLKEN_OVERRIDE_0) \
+_op_(EMC_LL_ARB_CONFIG_0) \
+_op_(EMC_T_MIN_CRITICAL_HP_0) \
+_op_(EMC_T_MIN_CRITICAL_TIMEOUT_0) \
+_op_(EMC_T_MIN_LOAD_0) \
+_op_(EMC_T_MAX_CRITICAL_HP_0) \
+_op_(EMC_T_MAX_CRITICAL_TIMEOUT_0) \
+_op_(EMC_T_MAX_LOAD_0) \
+_op_(EMC_STAT_CONTROL_0) \
+_op_(EMC_STAT_STATUS_0) \
+_op_(EMC_STAT_LLMC_ADDR_LOW_0) \
+_op_(EMC_STAT_LLMC_ADDR_HIGH_0) \
+_op_(EMC_STAT_LLMC_CLOCK_LIMIT_0) \
+_op_(EMC_STAT_LLMC_CLOCKS_0) \
+_op_(EMC_STAT_LLMC_CONTROL_0_0) \
+_op_(EMC_STAT_LLMC_HIST_LIMIT_0_0) \
+_op_(EMC_STAT_LLMC_COUNT_0_0) \
+_op_(EMC_STAT_LLMC_HIST_0_0) \
+_op_(EMC_STAT_PWR_CLOCK_LIMIT_0) \
+_op_(EMC_STAT_PWR_CLOCKS_0) \
+_op_(EMC_STAT_PWR_COUNT_0) \
+_op_(EMC_STAT_DRAM_CLOCK_LIMIT_LO_0) \
+_op_(EMC_STAT_DRAM_CLOCK_LIMIT_HI_0) \
+_op_(EMC_STAT_DRAM_CLOCKS_LO_0) \
+_op_(EMC_STAT_DRAM_CLOCKS_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_ACTIVATE_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_READ_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_READ_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_WRITE_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_WRITE_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_REF_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_REF_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_CKE_EQ1_CLKS_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_EXTCLKS_CKE_EQ0_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_ACTIVATE_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_READ_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_READ_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_WRITE_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_WRITE_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_REF_CNT_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_REF_CNT_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_CUMM_BANKS_ACTIVE_CKE_EQ0_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_CKE_EQ1_CLKS_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_EXTCLKS_CKE_EQ0_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV0_NO_BANKS_ACTIVE_CKE_EQ0_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ1_HI_0) \
+_op_(EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_LO_0) \
+_op_(EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0) \
+_op_(EMC_AUTO_CAL_CONFIG_0) \
+_op_(EMC_AUTO_CAL_INTERVAL_0) \
+_op_(EMC_AUTO_CAL_STATUS_0) \
+_op_(EMC_REQ_CTRL_0) \
+_op_(EMC_EMC_STATUS_0) \
+_op_(EMC_CFG_2_0) \
+_op_(EMC_CFG_DIG_DLL_0) \
+_op_(EMC_DLL_XFORM_DQS_0) \
+_op_(EMC_DLL_XFORM_QUSE_0) \
+_op_(EMC_DIG_DLL_UPPER_STATUS_0) \
+_op_(EMC_DIG_DLL_LOWER_STATUS_0) \
+_op_(EMC_CFG_CLKTRIM_0_0) \
+_op_(EMC_CFG_CLKTRIM_1_0) \
+_op_(EMC_CFG_CLKTRIM_2_0) \
+_op_(EMC_CTT_TERM_CTRL_0) \
+_op_(EMC_ZCAL_REF_CNT_0) \
+_op_(EMC_ZCAL_WAIT_CNT_0) \
+_op_(EMC_ZCAL_MRW_CMD_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_EMC        0x00000000
+
+//
+// AREMC REGISTER BANKS
+//
+
+#define EMC0_FIRST_REG 0x0000 // EMC_INTSTATUS_0
+#define EMC0_LAST_REG 0x0014 // EMC_ADR_CFG_1_0
+#define EMC1_FIRST_REG 0x0020 // EMC_REFCTRL_0
+#define EMC1_LAST_REG 0x00b4 // EMC_ODT_READ_0
+#define EMC2_FIRST_REG 0x00cc // EMC_MRS_0
+#define EMC2_LAST_REG 0x0114 // EMC_FBIO_CFG6_0
+#define EMC3_FIRST_REG 0x0120 // EMC_DQS_TRIMMER_RD0_0
+#define EMC3_LAST_REG 0x012c // EMC_DQS_TRIMMER_RD3_0
+#define EMC4_FIRST_REG 0x0140 // EMC_CLKEN_OVERRIDE_0
+#define EMC4_LAST_REG 0x0178 // EMC_STAT_LLMC_CONTROL_0_0
+#define EMC5_FIRST_REG 0x0180 // EMC_STAT_LLMC_HIST_LIMIT_0_0
+#define EMC5_LAST_REG 0x0180 // EMC_STAT_LLMC_HIST_LIMIT_0_0
+#define EMC6_FIRST_REG 0x0188 // EMC_STAT_LLMC_COUNT_0_0
+#define EMC6_LAST_REG 0x0188 // EMC_STAT_LLMC_COUNT_0_0
+#define EMC7_FIRST_REG 0x0190 // EMC_STAT_LLMC_HIST_0_0
+#define EMC7_LAST_REG 0x0190 // EMC_STAT_LLMC_HIST_0_0
+#define EMC8_FIRST_REG 0x0198 // EMC_STAT_PWR_CLOCK_LIMIT_0
+#define EMC8_LAST_REG 0x0260 // EMC_STAT_DRAM_DEV1_NO_BANKS_ACTIVE_CKE_EQ0_HI_0
+#define EMC9_FIRST_REG 0x02a4 // EMC_AUTO_CAL_CONFIG_0
+#define EMC9_LAST_REG 0x02e8 // EMC_ZCAL_MRW_CMD_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___AREMC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arevp.h b/arch/arm/mach-tegra/nv/include/ap20/arevp.h
new file mode 100644
index 000000000000..433991e2b2e0
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arevp.h
@@ -0,0 +1,2481 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___AREVP_H_INC_
+#define ___AREVP_H_INC_
+
+// Register EVP_RESET_VECTOR_0  
+#define EVP_RESET_VECTOR_0                      _MK_ADDR_CONST(0x0)
+#define EVP_RESET_VECTOR_0_SECURE                       0x0
+#define EVP_RESET_VECTOR_0_WORD_COUNT                   0x1
+#define EVP_RESET_VECTOR_0_RESET_VAL                    _MK_MASK_CONST(0xfff00000)
+#define EVP_RESET_VECTOR_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_RESET_VECTOR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EVP_RESET_VECTOR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EVP_RESET_VECTOR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_RESET_VECTOR_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// RESET Exception Vector Pointer 
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_RESET_VECTOR_0_RESET_VECTOR_SHIFT)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_RANGE                   31:0
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_WOFFSET                 0x0
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_DEFAULT                 _MK_MASK_CONST(0xfff00000)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_RESET_VECTOR_0_RESET_VECTOR_INIT_ENUM                       -1048576
+
+
+// Register EVP_UNDEF_VECTOR_0  
+#define EVP_UNDEF_VECTOR_0                      _MK_ADDR_CONST(0x4)
+#define EVP_UNDEF_VECTOR_0_SECURE                       0x0
+#define EVP_UNDEF_VECTOR_0_WORD_COUNT                   0x1
+#define EVP_UNDEF_VECTOR_0_RESET_VAL                    _MK_MASK_CONST(0xfff00004)
+#define EVP_UNDEF_VECTOR_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_UNDEF_VECTOR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define EVP_UNDEF_VECTOR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define EVP_UNDEF_VECTOR_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_UNDEF_VECTOR_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Undefined Exception Vector Pointer
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SHIFT)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_RANGE                   31:0
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_WOFFSET                 0x0
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_DEFAULT                 _MK_MASK_CONST(0xfff00004)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_UNDEF_VECTOR_0_UNDEF_VECTOR_INIT_ENUM                       -1048572
+
+
+// Register EVP_SWI_VECTOR_0  
+#define EVP_SWI_VECTOR_0                        _MK_ADDR_CONST(0x8)
+#define EVP_SWI_VECTOR_0_SECURE                         0x0
+#define EVP_SWI_VECTOR_0_WORD_COUNT                     0x1
+#define EVP_SWI_VECTOR_0_RESET_VAL                      _MK_MASK_CONST(0xfff00008)
+#define EVP_SWI_VECTOR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_SWI_VECTOR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EVP_SWI_VECTOR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EVP_SWI_VECTOR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_SWI_VECTOR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Software Interrupt Vector Pointer
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_SWI_VECTOR_0_SWI_VECTOR_SHIFT)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_RANGE                       31:0
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_WOFFSET                     0x0
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_DEFAULT                     _MK_MASK_CONST(0xfff00008)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_SWI_VECTOR_0_SWI_VECTOR_INIT_ENUM                   -1048568
+
+
+// Register EVP_PREFETCH_ABORT_VECTOR_0  
+#define EVP_PREFETCH_ABORT_VECTOR_0                     _MK_ADDR_CONST(0xc)
+#define EVP_PREFETCH_ABORT_VECTOR_0_SECURE                      0x0
+#define EVP_PREFETCH_ABORT_VECTOR_0_WORD_COUNT                  0x1
+#define EVP_PREFETCH_ABORT_VECTOR_0_RESET_VAL                   _MK_MASK_CONST(0xfff0000c)
+#define EVP_PREFETCH_ABORT_VECTOR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PREFETCH_ABORT_VECTOR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PREFETCH_ABORT_VECTOR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Code Prefetch ABORT Vector Pointer 
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SHIFT                      _MK_SHIFT_CONST(0)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_FIELD                      (_MK_MASK_CONST(0xffffffff) << EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SHIFT)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_RANGE                      31:0
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_WOFFSET                    0x0
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_DEFAULT                    _MK_MASK_CONST(0xfff0000c)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_PREFETCH_ABORT_VECTOR_0_PRE_ABORT_VECTOR_INIT_ENUM                  -1048564
+
+
+// Register EVP_DATA_ABORT_VECTOR_0  
+#define EVP_DATA_ABORT_VECTOR_0                 _MK_ADDR_CONST(0x10)
+#define EVP_DATA_ABORT_VECTOR_0_SECURE                  0x0
+#define EVP_DATA_ABORT_VECTOR_0_WORD_COUNT                      0x1
+#define EVP_DATA_ABORT_VECTOR_0_RESET_VAL                       _MK_MASK_CONST(0xfff00010)
+#define EVP_DATA_ABORT_VECTOR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_DATA_ABORT_VECTOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_DATA_ABORT_VECTOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_DATA_ABORT_VECTOR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_DATA_ABORT_VECTOR_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// Data ABORT Vector Pointer
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SHIFT)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_RANGE                 31:0
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_WOFFSET                       0x0
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_DEFAULT                       _MK_MASK_CONST(0xfff00010)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_DATA_ABORT_VECTOR_0_DATA_ABORT_VECTOR_INIT_ENUM                     -1048560
+
+
+// Register EVP_RSVD_VECTOR_0  
+#define EVP_RSVD_VECTOR_0                       _MK_ADDR_CONST(0x14)
+#define EVP_RSVD_VECTOR_0_SECURE                        0x0
+#define EVP_RSVD_VECTOR_0_WORD_COUNT                    0x1
+#define EVP_RSVD_VECTOR_0_RESET_VAL                     _MK_MASK_CONST(0xfff00014)
+#define EVP_RSVD_VECTOR_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_RSVD_VECTOR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_RSVD_VECTOR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_RSVD_VECTOR_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_RSVD_VECTOR_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Reserved Exception Vector Pointer
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_RSVD_VECTOR_0_RSVD_VECTOR_SHIFT)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_RANGE                     31:0
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_WOFFSET                   0x0
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_DEFAULT                   _MK_MASK_CONST(0xfff00014)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_RSVD_VECTOR_0_RSVD_VECTOR_INIT_ENUM                 -1048556
+
+
+// Register EVP_IRQ_VECTOR_0  
+#define EVP_IRQ_VECTOR_0                        _MK_ADDR_CONST(0x18)
+#define EVP_IRQ_VECTOR_0_SECURE                         0x0
+#define EVP_IRQ_VECTOR_0_WORD_COUNT                     0x1
+#define EVP_IRQ_VECTOR_0_RESET_VAL                      _MK_MASK_CONST(0xfff00018)
+#define EVP_IRQ_VECTOR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_VECTOR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EVP_IRQ_VECTOR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EVP_IRQ_VECTOR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_VECTOR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// IRQ Vector Pointer 
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_IRQ_VECTOR_0_IRQ_VECTOR_SHIFT)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_RANGE                       31:0
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_WOFFSET                     0x0
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xfff00018)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_IRQ_VECTOR_0_IRQ_VECTOR_INIT_ENUM                   -1048552
+
+
+// Register EVP_FIQ_VECTOR_0  
+#define EVP_FIQ_VECTOR_0                        _MK_ADDR_CONST(0x1c)
+#define EVP_FIQ_VECTOR_0_SECURE                         0x0
+#define EVP_FIQ_VECTOR_0_WORD_COUNT                     0x1
+#define EVP_FIQ_VECTOR_0_RESET_VAL                      _MK_MASK_CONST(0xfff00000)
+#define EVP_FIQ_VECTOR_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_VECTOR_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define EVP_FIQ_VECTOR_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define EVP_FIQ_VECTOR_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_VECTOR_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// FIQ Vector Pointer 
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_FIQ_VECTOR_0_FIQ_VECTOR_SHIFT)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_RANGE                       31:0
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_WOFFSET                     0x0
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xfff00000)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_FIQ_VECTOR_0_FIQ_VECTOR_INIT_ENUM                   -1048576
+
+
+// Register EVP_IRQ_STS_0  
+#define EVP_IRQ_STS_0                   _MK_ADDR_CONST(0x20)
+#define EVP_IRQ_STS_0_SECURE                    0x0
+#define EVP_IRQ_STS_0_WORD_COUNT                        0x1
+#define EVP_IRQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_IRQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_IRQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_IRQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// FFS (from lsb) IRQ index  (0x80 indicates no active IRQ)
+#define EVP_IRQ_STS_0_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_IRQ_STS_0_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_IRQ_STS_0_IRQ_STS_SHIFT)
+#define EVP_IRQ_STS_0_IRQ_STS_RANGE                     31:0
+#define EVP_IRQ_STS_0_IRQ_STS_WOFFSET                   0x0
+#define EVP_IRQ_STS_0_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_IRQ_STS_0_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_IRQ_STS_0_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_IRQ_STS_0_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_STS_0  
+#define EVP_PRI_IRQ_STS_0                       _MK_ADDR_CONST(0x24)
+#define EVP_PRI_IRQ_STS_0_SECURE                        0x0
+#define EVP_PRI_IRQ_STS_0_WORD_COUNT                    0x1
+#define EVP_PRI_IRQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Current highest priority active IRQ (0x80 indicates no active priority IRQ)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SHIFT)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_RANGE                     31:0
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_WOFFSET                   0x0
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_STS_0_PRI_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_FIQ_STS_0  
+#define EVP_FIQ_STS_0                   _MK_ADDR_CONST(0x28)
+#define EVP_FIQ_STS_0_SECURE                    0x0
+#define EVP_FIQ_STS_0_WORD_COUNT                        0x1
+#define EVP_FIQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_FIQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_FIQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_FIQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// FFS (from lsb) FIQ index (0x80 indicates no active FIQ)
+#define EVP_FIQ_STS_0_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_FIQ_STS_0_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_FIQ_STS_0_FIQ_STS_SHIFT)
+#define EVP_FIQ_STS_0_FIQ_STS_RANGE                     31:0
+#define EVP_FIQ_STS_0_FIQ_STS_WOFFSET                   0x0
+#define EVP_FIQ_STS_0_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_FIQ_STS_0_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_FIQ_STS_0_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_FIQ_STS_0_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_STS_0  
+#define EVP_PRI_FIQ_STS_0                       _MK_ADDR_CONST(0x2c)
+#define EVP_PRI_FIQ_STS_0_SECURE                        0x0
+#define EVP_PRI_FIQ_STS_0_WORD_COUNT                    0x1
+#define EVP_PRI_FIQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Current highest priority active FIQ (0x80 indicates no active priority FIQ)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SHIFT)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_RANGE                     31:0
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_WOFFSET                   0x0
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_STS_0_PRI_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_0_0  
+#define EVP_PRI_IRQ_NUM_0_0                     _MK_ADDR_CONST(0x40)
+#define EVP_PRI_IRQ_NUM_0_0_SECURE                      0x0
+#define EVP_PRI_IRQ_NUM_0_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_0_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT)
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_0_0  
+#define EVP_PRI_IRQ_VEC_0_0                     _MK_ADDR_CONST(0x44)
+#define EVP_PRI_IRQ_VEC_0_0_SECURE                      0x0
+#define EVP_PRI_IRQ_VEC_0_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_0_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT)
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_1_0  
+#define EVP_PRI_IRQ_NUM_1_0                     _MK_ADDR_CONST(0x48)
+#define EVP_PRI_IRQ_NUM_1_0_SECURE                      0x0
+#define EVP_PRI_IRQ_NUM_1_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_1_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT)
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_1_0  
+#define EVP_PRI_IRQ_VEC_1_0                     _MK_ADDR_CONST(0x4c)
+#define EVP_PRI_IRQ_VEC_1_0_SECURE                      0x0
+#define EVP_PRI_IRQ_VEC_1_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_1_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT)
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_2_0  
+#define EVP_PRI_IRQ_NUM_2_0                     _MK_ADDR_CONST(0x50)
+#define EVP_PRI_IRQ_NUM_2_0_SECURE                      0x0
+#define EVP_PRI_IRQ_NUM_2_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_2_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT)
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_2_0  
+#define EVP_PRI_IRQ_VEC_2_0                     _MK_ADDR_CONST(0x54)
+#define EVP_PRI_IRQ_VEC_2_0_SECURE                      0x0
+#define EVP_PRI_IRQ_VEC_2_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_2_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT)
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_3_0  
+#define EVP_PRI_IRQ_NUM_3_0                     _MK_ADDR_CONST(0x58)
+#define EVP_PRI_IRQ_NUM_3_0_SECURE                      0x0
+#define EVP_PRI_IRQ_NUM_3_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_3_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT)
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_3_0  
+#define EVP_PRI_IRQ_VEC_3_0                     _MK_ADDR_CONST(0x5c)
+#define EVP_PRI_IRQ_VEC_3_0_SECURE                      0x0
+#define EVP_PRI_IRQ_VEC_3_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_3_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT)
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_4_0  
+#define EVP_PRI_IRQ_NUM_4_0                     _MK_ADDR_CONST(0x60)
+#define EVP_PRI_IRQ_NUM_4_0_SECURE                      0x0
+#define EVP_PRI_IRQ_NUM_4_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_4_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_4_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_4_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_4_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT)
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_4_0  
+#define EVP_PRI_IRQ_VEC_4_0                     _MK_ADDR_CONST(0x64)
+#define EVP_PRI_IRQ_VEC_4_0_SECURE                      0x0
+#define EVP_PRI_IRQ_VEC_4_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_4_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_4_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_4_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_4_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT)
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_5_0  
+#define EVP_PRI_IRQ_NUM_5_0                     _MK_ADDR_CONST(0x68)
+#define EVP_PRI_IRQ_NUM_5_0_SECURE                      0x0
+#define EVP_PRI_IRQ_NUM_5_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_5_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_5_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_5_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_5_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_5_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_5_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT)
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_5_0  
+#define EVP_PRI_IRQ_VEC_5_0                     _MK_ADDR_CONST(0x6c)
+#define EVP_PRI_IRQ_VEC_5_0_SECURE                      0x0
+#define EVP_PRI_IRQ_VEC_5_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_5_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_5_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_5_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_5_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_5_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_5_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT)
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_6_0  
+#define EVP_PRI_IRQ_NUM_6_0                     _MK_ADDR_CONST(0x70)
+#define EVP_PRI_IRQ_NUM_6_0_SECURE                      0x0
+#define EVP_PRI_IRQ_NUM_6_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_6_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_6_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_6_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_6_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_6_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_6_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT)
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_6_0  
+#define EVP_PRI_IRQ_VEC_6_0                     _MK_ADDR_CONST(0x74)
+#define EVP_PRI_IRQ_VEC_6_0_SECURE                      0x0
+#define EVP_PRI_IRQ_VEC_6_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_6_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_6_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_6_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_6_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_6_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_6_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT)
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_NUM_7_0  
+#define EVP_PRI_IRQ_NUM_7_0                     _MK_ADDR_CONST(0x78)
+#define EVP_PRI_IRQ_NUM_7_0_SECURE                      0x0
+#define EVP_PRI_IRQ_NUM_7_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_NUM_7_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_7_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_7_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_7_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_7_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_7_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT)
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_RANGE                 31:0
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_WOFFSET                       0x0
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_IRQ_VEC_7_0  
+#define EVP_PRI_IRQ_VEC_7_0                     _MK_ADDR_CONST(0x7c)
+#define EVP_PRI_IRQ_VEC_7_0_SECURE                      0x0
+#define EVP_PRI_IRQ_VEC_7_0_WORD_COUNT                  0x1
+#define EVP_PRI_IRQ_VEC_7_0_RESET_VAL                   _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_7_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_7_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_7_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_7_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_7_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT)
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_RANGE                 31:0
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_WOFFSET                       0x0
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT                       _MK_MASK_CONST(0x40000018)
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_NUM_0_0  
+#define EVP_PRI_FIQ_NUM_0_0                     _MK_ADDR_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_0_0_SECURE                      0x0
+#define EVP_PRI_FIQ_NUM_0_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_NUM_0_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT)
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_RANGE                 31:0
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_WOFFSET                       0x0
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_VEC_0_0  
+#define EVP_PRI_FIQ_VEC_0_0                     _MK_ADDR_CONST(0x84)
+#define EVP_PRI_FIQ_VEC_0_0_SECURE                      0x0
+#define EVP_PRI_FIQ_VEC_0_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_VEC_0_0_RESET_VAL                   _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_0_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT)
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_RANGE                 31:0
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_WOFFSET                       0x0
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT                       _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_NUM_1_0  
+#define EVP_PRI_FIQ_NUM_1_0                     _MK_ADDR_CONST(0x88)
+#define EVP_PRI_FIQ_NUM_1_0_SECURE                      0x0
+#define EVP_PRI_FIQ_NUM_1_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_NUM_1_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT)
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_RANGE                 31:0
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_WOFFSET                       0x0
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_VEC_1_0  
+#define EVP_PRI_FIQ_VEC_1_0                     _MK_ADDR_CONST(0x8c)
+#define EVP_PRI_FIQ_VEC_1_0_SECURE                      0x0
+#define EVP_PRI_FIQ_VEC_1_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_VEC_1_0_RESET_VAL                   _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_1_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT)
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_RANGE                 31:0
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_WOFFSET                       0x0
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT                       _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_NUM_2_0  
+#define EVP_PRI_FIQ_NUM_2_0                     _MK_ADDR_CONST(0x90)
+#define EVP_PRI_FIQ_NUM_2_0_SECURE                      0x0
+#define EVP_PRI_FIQ_NUM_2_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_NUM_2_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT)
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_RANGE                 31:0
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_WOFFSET                       0x0
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_VEC_2_0  
+#define EVP_PRI_FIQ_VEC_2_0                     _MK_ADDR_CONST(0x94)
+#define EVP_PRI_FIQ_VEC_2_0_SECURE                      0x0
+#define EVP_PRI_FIQ_VEC_2_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_VEC_2_0_RESET_VAL                   _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_2_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT)
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_RANGE                 31:0
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_WOFFSET                       0x0
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT                       _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_NUM_3_0  
+#define EVP_PRI_FIQ_NUM_3_0                     _MK_ADDR_CONST(0x98)
+#define EVP_PRI_FIQ_NUM_3_0_SECURE                      0x0
+#define EVP_PRI_FIQ_NUM_3_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_NUM_3_0_RESET_VAL                   _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number for the Interrupt associated with this entry
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT)
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_RANGE                 31:0
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_WOFFSET                       0x0
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT                       _MK_MASK_CONST(0x80)
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_PRI_FIQ_VEC_3_0  
+#define EVP_PRI_FIQ_VEC_3_0                     _MK_ADDR_CONST(0x9c)
+#define EVP_PRI_FIQ_VEC_3_0_SECURE                      0x0
+#define EVP_PRI_FIQ_VEC_3_0_WORD_COUNT                  0x1
+#define EVP_PRI_FIQ_VEC_3_0_RESET_VAL                   _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_3_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT)
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_RANGE                 31:0
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_WOFFSET                       0x0
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT                       _MK_MASK_CONST(0x4000001c)
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_RESET_VECTOR_0  
+#define EVP_CPU_RESET_VECTOR_0                  _MK_ADDR_CONST(0x100)
+#define EVP_CPU_RESET_VECTOR_0_SECURE                   0x0
+#define EVP_CPU_RESET_VECTOR_0_WORD_COUNT                       0x1
+#define EVP_CPU_RESET_VECTOR_0_RESET_VAL                        _MK_MASK_CONST(0xfff00000)
+#define EVP_CPU_RESET_VECTOR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RESET_VECTOR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_RESET_VECTOR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_RESET_VECTOR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RESET_VECTOR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// RESET Exception Vector Pointer 
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SHIFT)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_RANGE                   31:0
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_WOFFSET                 0x0
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_DEFAULT                 _MK_MASK_CONST(0xfff00000)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_CPU_RESET_VECTOR_0_CPU_RESET_VECTOR_INIT_ENUM                       -1048576
+
+
+// Register EVP_CPU_UNDEF_VECTOR_0  
+#define EVP_CPU_UNDEF_VECTOR_0                  _MK_ADDR_CONST(0x104)
+#define EVP_CPU_UNDEF_VECTOR_0_SECURE                   0x0
+#define EVP_CPU_UNDEF_VECTOR_0_WORD_COUNT                       0x1
+#define EVP_CPU_UNDEF_VECTOR_0_RESET_VAL                        _MK_MASK_CONST(0xfff00004)
+#define EVP_CPU_UNDEF_VECTOR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_UNDEF_VECTOR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_UNDEF_VECTOR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_UNDEF_VECTOR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_UNDEF_VECTOR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// Undefined Exception Vector Pointer
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SHIFT)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_RANGE                   31:0
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_WOFFSET                 0x0
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_DEFAULT                 _MK_MASK_CONST(0xfff00004)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_CPU_UNDEF_VECTOR_0_CPU_UNDEF_VECTOR_INIT_ENUM                       -1048572
+
+
+// Register EVP_CPU_SWI_VECTOR_0  
+#define EVP_CPU_SWI_VECTOR_0                    _MK_ADDR_CONST(0x108)
+#define EVP_CPU_SWI_VECTOR_0_SECURE                     0x0
+#define EVP_CPU_SWI_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_CPU_SWI_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xfff00008)
+#define EVP_CPU_SWI_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_SWI_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_SWI_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_SWI_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_SWI_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Software Interrupt Vector Pointer
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SHIFT)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_RANGE                       31:0
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_WOFFSET                     0x0
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_DEFAULT                     _MK_MASK_CONST(0xfff00008)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_SWI_VECTOR_0_CPU_SWI_VECTOR_INIT_ENUM                   -1048568
+
+
+// Register EVP_CPU_PREFETCH_ABORT_VECTOR_0  
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0                 _MK_ADDR_CONST(0x10c)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_SECURE                  0x0
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_WORD_COUNT                      0x1
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_RESET_VAL                       _MK_MASK_CONST(0xfff0000c)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Code Prefetch ABORT Vector Pointer 
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_SHIFT                      _MK_SHIFT_CONST(0)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_FIELD                      (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_SHIFT)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_RANGE                      31:0
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_WOFFSET                    0x0
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_DEFAULT                    _MK_MASK_CONST(0xfff0000c)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_PREFETCH_ABORT_VECTOR_0_CPU_PRE_ABORT_VECTOR_INIT_ENUM                  -1048564
+
+
+// Register EVP_CPU_DATA_ABORT_VECTOR_0  
+#define EVP_CPU_DATA_ABORT_VECTOR_0                     _MK_ADDR_CONST(0x110)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_SECURE                      0x0
+#define EVP_CPU_DATA_ABORT_VECTOR_0_WORD_COUNT                  0x1
+#define EVP_CPU_DATA_ABORT_VECTOR_0_RESET_VAL                   _MK_MASK_CONST(0xfff00010)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Data ABORT Vector Pointer
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_SHIFT)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_RANGE                 31:0
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_WOFFSET                       0x0
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_DEFAULT                       _MK_MASK_CONST(0xfff00010)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_CPU_DATA_ABORT_VECTOR_0_CPU_DATA_ABORT_VECTOR_INIT_ENUM                     -1048560
+
+
+// Register EVP_CPU_RSVD_VECTOR_0  
+#define EVP_CPU_RSVD_VECTOR_0                   _MK_ADDR_CONST(0x114)
+#define EVP_CPU_RSVD_VECTOR_0_SECURE                    0x0
+#define EVP_CPU_RSVD_VECTOR_0_WORD_COUNT                        0x1
+#define EVP_CPU_RSVD_VECTOR_0_RESET_VAL                         _MK_MASK_CONST(0xfff00014)
+#define EVP_CPU_RSVD_VECTOR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RSVD_VECTOR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_RSVD_VECTOR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_RSVD_VECTOR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RSVD_VECTOR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Reserved Exception Vector Pointer
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SHIFT)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_RANGE                     31:0
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_WOFFSET                   0x0
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_DEFAULT                   _MK_MASK_CONST(0xfff00014)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_RSVD_VECTOR_0_CPU_RSVD_VECTOR_INIT_ENUM                 -1048556
+
+
+// Register EVP_CPU_IRQ_VECTOR_0  
+#define EVP_CPU_IRQ_VECTOR_0                    _MK_ADDR_CONST(0x118)
+#define EVP_CPU_IRQ_VECTOR_0_SECURE                     0x0
+#define EVP_CPU_IRQ_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_CPU_IRQ_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xfff00018)
+#define EVP_CPU_IRQ_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// IRQ Vector Pointer 
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SHIFT)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_RANGE                       31:0
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_WOFFSET                     0x0
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xfff00018)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_VECTOR_0_CPU_IRQ_VECTOR_INIT_ENUM                   -1048552
+
+
+// Register EVP_CPU_FIQ_VECTOR_0  
+#define EVP_CPU_FIQ_VECTOR_0                    _MK_ADDR_CONST(0x11c)
+#define EVP_CPU_FIQ_VECTOR_0_SECURE                     0x0
+#define EVP_CPU_FIQ_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_CPU_FIQ_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xfff0001c)
+#define EVP_CPU_FIQ_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// FIQ Vector Pointer 
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SHIFT)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_RANGE                       31:0
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_WOFFSET                     0x0
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xfff0001c)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_VECTOR_0_CPU_FIQ_VECTOR_INIT_ENUM                   -1048548
+
+
+// Register EVP_CPU_IRQ_STS_0  
+#define EVP_CPU_IRQ_STS_0                       _MK_ADDR_CONST(0x120)
+#define EVP_CPU_IRQ_STS_0_SECURE                        0x0
+#define EVP_CPU_IRQ_STS_0_WORD_COUNT                    0x1
+#define EVP_CPU_IRQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_CPU_IRQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// FFS (from lsb) IRQ index  (0x80 indicates no active IRQ)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SHIFT)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_RANGE                     31:0
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_WOFFSET                   0x0
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_IRQ_STS_0_CPU_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_STS_0  
+#define EVP_CPU_PRI_IRQ_STS_0                   _MK_ADDR_CONST(0x124)
+#define EVP_CPU_PRI_IRQ_STS_0_SECURE                    0x0
+#define EVP_CPU_PRI_IRQ_STS_0_WORD_COUNT                        0x1
+#define EVP_CPU_PRI_IRQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Current highest priority active IRQ (0x80 indicates no active priority IRQ)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SHIFT)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_STS_0_CPU_PRI_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_FIQ_STS_0  
+#define EVP_CPU_FIQ_STS_0                       _MK_ADDR_CONST(0x128)
+#define EVP_CPU_FIQ_STS_0_SECURE                        0x0
+#define EVP_CPU_FIQ_STS_0_WORD_COUNT                    0x1
+#define EVP_CPU_FIQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_CPU_FIQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// FFS (from lsb) FIQ index (0x80 indicates no active FIQ)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SHIFT)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_RANGE                     31:0
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_WOFFSET                   0x0
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_FIQ_STS_0_CPU_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_STS_0  
+#define EVP_CPU_PRI_FIQ_STS_0                   _MK_ADDR_CONST(0x12c)
+#define EVP_CPU_PRI_FIQ_STS_0_SECURE                    0x0
+#define EVP_CPU_PRI_FIQ_STS_0_WORD_COUNT                        0x1
+#define EVP_CPU_PRI_FIQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Current highest priority active FIQ (0x80 indicates no active priority FIQ)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SHIFT)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_STS_0_CPU_PRI_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_0_0  
+#define EVP_CPU_PRI_IRQ_NUM_0_0                 _MK_ADDR_CONST(0x140)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_NUM_0_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_0_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_0_0  
+#define EVP_CPU_PRI_IRQ_VEC_0_0                 _MK_ADDR_CONST(0x144)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_VEC_0_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_0_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_1_0  
+#define EVP_CPU_PRI_IRQ_NUM_1_0                 _MK_ADDR_CONST(0x148)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_NUM_1_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_1_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_1_0  
+#define EVP_CPU_PRI_IRQ_VEC_1_0                 _MK_ADDR_CONST(0x14c)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_VEC_1_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_1_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_2_0  
+#define EVP_CPU_PRI_IRQ_NUM_2_0                 _MK_ADDR_CONST(0x150)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_NUM_2_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_2_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_2_0  
+#define EVP_CPU_PRI_IRQ_VEC_2_0                 _MK_ADDR_CONST(0x154)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_VEC_2_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_2_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_3_0  
+#define EVP_CPU_PRI_IRQ_NUM_3_0                 _MK_ADDR_CONST(0x158)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_NUM_3_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_3_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_3_0  
+#define EVP_CPU_PRI_IRQ_VEC_3_0                 _MK_ADDR_CONST(0x15c)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_VEC_3_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_3_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_4_0  
+#define EVP_CPU_PRI_IRQ_NUM_4_0                 _MK_ADDR_CONST(0x160)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_NUM_4_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_4_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_4_0  
+#define EVP_CPU_PRI_IRQ_VEC_4_0                 _MK_ADDR_CONST(0x164)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_VEC_4_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_4_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_5_0  
+#define EVP_CPU_PRI_IRQ_NUM_5_0                 _MK_ADDR_CONST(0x168)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_NUM_5_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_5_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_5_0  
+#define EVP_CPU_PRI_IRQ_VEC_5_0                 _MK_ADDR_CONST(0x16c)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_VEC_5_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_5_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_6_0  
+#define EVP_CPU_PRI_IRQ_NUM_6_0                 _MK_ADDR_CONST(0x170)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_NUM_6_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_6_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_6_0  
+#define EVP_CPU_PRI_IRQ_VEC_6_0                 _MK_ADDR_CONST(0x174)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_VEC_6_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_6_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_NUM_7_0  
+#define EVP_CPU_PRI_IRQ_NUM_7_0                 _MK_ADDR_CONST(0x178)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_NUM_7_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_NUM_7_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_IRQ_VEC_7_0  
+#define EVP_CPU_PRI_IRQ_VEC_7_0                 _MK_ADDR_CONST(0x17c)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_SECURE                  0x0
+#define EVP_CPU_PRI_IRQ_VEC_7_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_IRQ_VEC_7_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_RANGE                     31:0
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_WOFFSET                   0x0
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_NUM_0_0  
+#define EVP_CPU_PRI_FIQ_NUM_0_0                 _MK_ADDR_CONST(0x180)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_SECURE                  0x0
+#define EVP_CPU_PRI_FIQ_NUM_0_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_NUM_0_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_VEC_0_0  
+#define EVP_CPU_PRI_FIQ_VEC_0_0                 _MK_ADDR_CONST(0x184)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_SECURE                  0x0
+#define EVP_CPU_PRI_FIQ_VEC_0_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_VEC_0_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_NUM_1_0  
+#define EVP_CPU_PRI_FIQ_NUM_1_0                 _MK_ADDR_CONST(0x188)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_SECURE                  0x0
+#define EVP_CPU_PRI_FIQ_NUM_1_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_NUM_1_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_VEC_1_0  
+#define EVP_CPU_PRI_FIQ_VEC_1_0                 _MK_ADDR_CONST(0x18c)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_SECURE                  0x0
+#define EVP_CPU_PRI_FIQ_VEC_1_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_VEC_1_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_NUM_2_0  
+#define EVP_CPU_PRI_FIQ_NUM_2_0                 _MK_ADDR_CONST(0x190)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_SECURE                  0x0
+#define EVP_CPU_PRI_FIQ_NUM_2_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_NUM_2_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_VEC_2_0  
+#define EVP_CPU_PRI_FIQ_VEC_2_0                 _MK_ADDR_CONST(0x194)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_SECURE                  0x0
+#define EVP_CPU_PRI_FIQ_VEC_2_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_VEC_2_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_NUM_3_0  
+#define EVP_CPU_PRI_FIQ_NUM_3_0                 _MK_ADDR_CONST(0x198)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_SECURE                  0x0
+#define EVP_CPU_PRI_FIQ_NUM_3_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_NUM_3_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_CPU_PRI_FIQ_VEC_3_0  
+#define EVP_CPU_PRI_FIQ_VEC_3_0                 _MK_ADDR_CONST(0x19c)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_SECURE                  0x0
+#define EVP_CPU_PRI_FIQ_VEC_3_0_WORD_COUNT                      0x1
+#define EVP_CPU_PRI_FIQ_VEC_3_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_RANGE                     31:0
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_WOFFSET                   0x0
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_CPU_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_RESET_VECTOR_0  
+#define EVP_COP_RESET_VECTOR_0                  _MK_ADDR_CONST(0x200)
+#define EVP_COP_RESET_VECTOR_0_SECURE                   0x0
+#define EVP_COP_RESET_VECTOR_0_WORD_COUNT                       0x1
+#define EVP_COP_RESET_VECTOR_0_RESET_VAL                        _MK_MASK_CONST(0xfff00000)
+#define EVP_COP_RESET_VECTOR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RESET_VECTOR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EVP_COP_RESET_VECTOR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EVP_COP_RESET_VECTOR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RESET_VECTOR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// RESET Exception Vector Pointer 
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SHIFT)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_RANGE                   31:0
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_WOFFSET                 0x0
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_DEFAULT                 _MK_MASK_CONST(0xfff00000)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_COP_RESET_VECTOR_0_COP_RESET_VECTOR_INIT_ENUM                       -1048576
+
+
+// Register EVP_COP_UNDEF_VECTOR_0  
+#define EVP_COP_UNDEF_VECTOR_0                  _MK_ADDR_CONST(0x204)
+#define EVP_COP_UNDEF_VECTOR_0_SECURE                   0x0
+#define EVP_COP_UNDEF_VECTOR_0_WORD_COUNT                       0x1
+#define EVP_COP_UNDEF_VECTOR_0_RESET_VAL                        _MK_MASK_CONST(0xfff00004)
+#define EVP_COP_UNDEF_VECTOR_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_UNDEF_VECTOR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define EVP_COP_UNDEF_VECTOR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define EVP_COP_UNDEF_VECTOR_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_UNDEF_VECTOR_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// Undefined Exception Vector Pointer
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_FIELD                   (_MK_MASK_CONST(0xffffffff) << EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SHIFT)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_RANGE                   31:0
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_WOFFSET                 0x0
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_DEFAULT                 _MK_MASK_CONST(0xfff00004)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define EVP_COP_UNDEF_VECTOR_0_COP_UNDEF_VECTOR_INIT_ENUM                       -1048572
+
+
+// Register EVP_COP_SWI_VECTOR_0  
+#define EVP_COP_SWI_VECTOR_0                    _MK_ADDR_CONST(0x208)
+#define EVP_COP_SWI_VECTOR_0_SECURE                     0x0
+#define EVP_COP_SWI_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_COP_SWI_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xfff00008)
+#define EVP_COP_SWI_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_SWI_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_COP_SWI_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_COP_SWI_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_SWI_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Software Interrupt Vector Pointer
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SHIFT)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_RANGE                       31:0
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_WOFFSET                     0x0
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_DEFAULT                     _MK_MASK_CONST(0xfff00008)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_COP_SWI_VECTOR_0_COP_SWI_VECTOR_INIT_ENUM                   -1048568
+
+
+// Register EVP_COP_PREFETCH_ABORT_VECTOR_0  
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0                 _MK_ADDR_CONST(0x20c)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_SECURE                  0x0
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_WORD_COUNT                      0x1
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_RESET_VAL                       _MK_MASK_CONST(0xfff0000c)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Code Prefetch ABORT Vector Pointer 
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_SHIFT                      _MK_SHIFT_CONST(0)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_FIELD                      (_MK_MASK_CONST(0xffffffff) << EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_SHIFT)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_RANGE                      31:0
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_WOFFSET                    0x0
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_DEFAULT                    _MK_MASK_CONST(0xfff0000c)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_COP_PREFETCH_ABORT_VECTOR_0_COP_PRE_ABORT_VECTOR_INIT_ENUM                  -1048564
+
+
+// Register EVP_COP_DATA_ABORT_VECTOR_0  
+#define EVP_COP_DATA_ABORT_VECTOR_0                     _MK_ADDR_CONST(0x210)
+#define EVP_COP_DATA_ABORT_VECTOR_0_SECURE                      0x0
+#define EVP_COP_DATA_ABORT_VECTOR_0_WORD_COUNT                  0x1
+#define EVP_COP_DATA_ABORT_VECTOR_0_RESET_VAL                   _MK_MASK_CONST(0xfff00010)
+#define EVP_COP_DATA_ABORT_VECTOR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_DATA_ABORT_VECTOR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define EVP_COP_DATA_ABORT_VECTOR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_COP_DATA_ABORT_VECTOR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_DATA_ABORT_VECTOR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Data ABORT Vector Pointer
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_FIELD                 (_MK_MASK_CONST(0xffffffff) << EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_SHIFT)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_RANGE                 31:0
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_WOFFSET                       0x0
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_DEFAULT                       _MK_MASK_CONST(0xfff00010)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_COP_DATA_ABORT_VECTOR_0_COP_DATA_ABORT_VECTOR_INIT_ENUM                     -1048560
+
+
+// Register EVP_COP_RSVD_VECTOR_0  
+#define EVP_COP_RSVD_VECTOR_0                   _MK_ADDR_CONST(0x214)
+#define EVP_COP_RSVD_VECTOR_0_SECURE                    0x0
+#define EVP_COP_RSVD_VECTOR_0_WORD_COUNT                        0x1
+#define EVP_COP_RSVD_VECTOR_0_RESET_VAL                         _MK_MASK_CONST(0xfff00014)
+#define EVP_COP_RSVD_VECTOR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RSVD_VECTOR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_COP_RSVD_VECTOR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_COP_RSVD_VECTOR_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RSVD_VECTOR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Reserved Exception Vector Pointer
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SHIFT)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_RANGE                     31:0
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_WOFFSET                   0x0
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_DEFAULT                   _MK_MASK_CONST(0xfff00014)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_COP_RSVD_VECTOR_0_COP_RSVD_VECTOR_INIT_ENUM                 -1048556
+
+
+// Register EVP_COP_IRQ_VECTOR_0  
+#define EVP_COP_IRQ_VECTOR_0                    _MK_ADDR_CONST(0x218)
+#define EVP_COP_IRQ_VECTOR_0_SECURE                     0x0
+#define EVP_COP_IRQ_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_COP_IRQ_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xfff00018)
+#define EVP_COP_IRQ_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// IRQ Vector Pointer 
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SHIFT)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_RANGE                       31:0
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_WOFFSET                     0x0
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xfff00018)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_VECTOR_0_COP_IRQ_VECTOR_INIT_ENUM                   -1048552
+
+
+// Register EVP_COP_FIQ_VECTOR_0  
+#define EVP_COP_FIQ_VECTOR_0                    _MK_ADDR_CONST(0x21c)
+#define EVP_COP_FIQ_VECTOR_0_SECURE                     0x0
+#define EVP_COP_FIQ_VECTOR_0_WORD_COUNT                         0x1
+#define EVP_COP_FIQ_VECTOR_0_RESET_VAL                  _MK_MASK_CONST(0xfff0001c)
+#define EVP_COP_FIQ_VECTOR_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_VECTOR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_VECTOR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_VECTOR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_VECTOR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// FIQ Vector Pointer 
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_FIELD                       (_MK_MASK_CONST(0xffffffff) << EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SHIFT)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_RANGE                       31:0
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_WOFFSET                     0x0
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_DEFAULT                     _MK_MASK_CONST(0xfff0001c)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_VECTOR_0_COP_FIQ_VECTOR_INIT_ENUM                   -1048548
+
+
+// Register EVP_COP_IRQ_STS_0  
+#define EVP_COP_IRQ_STS_0                       _MK_ADDR_CONST(0x220)
+#define EVP_COP_IRQ_STS_0_SECURE                        0x0
+#define EVP_COP_IRQ_STS_0_WORD_COUNT                    0x1
+#define EVP_COP_IRQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_COP_IRQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// FFS (from lsb) IRQ index  (0x80 indicates no active IRQ)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_IRQ_STS_0_COP_IRQ_STS_SHIFT)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_RANGE                     31:0
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_WOFFSET                   0x0
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_IRQ_STS_0_COP_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_STS_0  
+#define EVP_COP_PRI_IRQ_STS_0                   _MK_ADDR_CONST(0x224)
+#define EVP_COP_PRI_IRQ_STS_0_SECURE                    0x0
+#define EVP_COP_PRI_IRQ_STS_0_WORD_COUNT                        0x1
+#define EVP_COP_PRI_IRQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Current highest priority active IRQ (0x80 indicates no active priority IRQ)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SHIFT)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_STS_0_COP_PRI_IRQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_FIQ_STS_0  
+#define EVP_COP_FIQ_STS_0                       _MK_ADDR_CONST(0x228)
+#define EVP_COP_FIQ_STS_0_SECURE                        0x0
+#define EVP_COP_FIQ_STS_0_WORD_COUNT                    0x1
+#define EVP_COP_FIQ_STS_0_RESET_VAL                     _MK_MASK_CONST(0x80)
+#define EVP_COP_FIQ_STS_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_STS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_STS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_STS_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_STS_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// FFS (from lsb) FIQ index (0x80 indicates no active FIQ)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_FIQ_STS_0_COP_FIQ_STS_SHIFT)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_RANGE                     31:0
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_WOFFSET                   0x0
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_FIQ_STS_0_COP_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_STS_0  
+#define EVP_COP_PRI_FIQ_STS_0                   _MK_ADDR_CONST(0x22c)
+#define EVP_COP_PRI_FIQ_STS_0_SECURE                    0x0
+#define EVP_COP_PRI_FIQ_STS_0_WORD_COUNT                        0x1
+#define EVP_COP_PRI_FIQ_STS_0_RESET_VAL                         _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_STS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_STS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_STS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_STS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_STS_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Current highest priority active FIQ (0x80 indicates no active priority FIQ)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SHIFT)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_STS_0_COP_PRI_FIQ_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_0_0  
+#define EVP_COP_PRI_IRQ_NUM_0_0                 _MK_ADDR_CONST(0x240)
+#define EVP_COP_PRI_IRQ_NUM_0_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_NUM_0_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_0_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_0_0_PRI_IRQ_NUM_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_0_0  
+#define EVP_COP_PRI_IRQ_VEC_0_0                 _MK_ADDR_CONST(0x244)
+#define EVP_COP_PRI_IRQ_VEC_0_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_VEC_0_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_0_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_0_0_PRI_IRQ_VEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_1_0  
+#define EVP_COP_PRI_IRQ_NUM_1_0                 _MK_ADDR_CONST(0x248)
+#define EVP_COP_PRI_IRQ_NUM_1_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_NUM_1_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_1_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_1_0_PRI_IRQ_NUM_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_1_0  
+#define EVP_COP_PRI_IRQ_VEC_1_0                 _MK_ADDR_CONST(0x24c)
+#define EVP_COP_PRI_IRQ_VEC_1_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_VEC_1_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_1_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_1_0_PRI_IRQ_VEC_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_2_0  
+#define EVP_COP_PRI_IRQ_NUM_2_0                 _MK_ADDR_CONST(0x250)
+#define EVP_COP_PRI_IRQ_NUM_2_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_NUM_2_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_2_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_2_0_PRI_IRQ_NUM_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_2_0  
+#define EVP_COP_PRI_IRQ_VEC_2_0                 _MK_ADDR_CONST(0x254)
+#define EVP_COP_PRI_IRQ_VEC_2_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_VEC_2_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_2_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_2_0_PRI_IRQ_VEC_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_3_0  
+#define EVP_COP_PRI_IRQ_NUM_3_0                 _MK_ADDR_CONST(0x258)
+#define EVP_COP_PRI_IRQ_NUM_3_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_NUM_3_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_3_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_3_0_PRI_IRQ_NUM_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_3_0  
+#define EVP_COP_PRI_IRQ_VEC_3_0                 _MK_ADDR_CONST(0x25c)
+#define EVP_COP_PRI_IRQ_VEC_3_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_VEC_3_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_3_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_3_0_PRI_IRQ_VEC_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_4_0  
+#define EVP_COP_PRI_IRQ_NUM_4_0                 _MK_ADDR_CONST(0x260)
+#define EVP_COP_PRI_IRQ_NUM_4_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_NUM_4_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_4_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_4_0_PRI_IRQ_NUM_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_4_0  
+#define EVP_COP_PRI_IRQ_VEC_4_0                 _MK_ADDR_CONST(0x264)
+#define EVP_COP_PRI_IRQ_VEC_4_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_VEC_4_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_4_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_4_0_PRI_IRQ_VEC_4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_5_0  
+#define EVP_COP_PRI_IRQ_NUM_5_0                 _MK_ADDR_CONST(0x268)
+#define EVP_COP_PRI_IRQ_NUM_5_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_NUM_5_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_5_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_5_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_5_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_5_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_5_0_PRI_IRQ_NUM_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_5_0  
+#define EVP_COP_PRI_IRQ_VEC_5_0                 _MK_ADDR_CONST(0x26c)
+#define EVP_COP_PRI_IRQ_VEC_5_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_VEC_5_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_5_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_5_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_5_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_5_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_5_0_PRI_IRQ_VEC_5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_6_0  
+#define EVP_COP_PRI_IRQ_NUM_6_0                 _MK_ADDR_CONST(0x270)
+#define EVP_COP_PRI_IRQ_NUM_6_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_NUM_6_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_6_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_6_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_6_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_6_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_6_0_PRI_IRQ_NUM_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_6_0  
+#define EVP_COP_PRI_IRQ_VEC_6_0                 _MK_ADDR_CONST(0x274)
+#define EVP_COP_PRI_IRQ_VEC_6_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_VEC_6_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_6_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_6_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_6_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_6_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_6_0_PRI_IRQ_VEC_6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_NUM_7_0  
+#define EVP_COP_PRI_IRQ_NUM_7_0                 _MK_ADDR_CONST(0x278)
+#define EVP_COP_PRI_IRQ_NUM_7_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_NUM_7_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_NUM_7_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_7_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_7_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_7_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SHIFT)
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_NUM_7_0_PRI_IRQ_NUM_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_IRQ_VEC_7_0  
+#define EVP_COP_PRI_IRQ_VEC_7_0                 _MK_ADDR_CONST(0x27c)
+#define EVP_COP_PRI_IRQ_VEC_7_0_SECURE                  0x0
+#define EVP_COP_PRI_IRQ_VEC_7_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_IRQ_VEC_7_0_RESET_VAL                       _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_7_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_7_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_7_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SHIFT)
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_RANGE                     31:0
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_WOFFSET                   0x0
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT                   _MK_MASK_CONST(0x40000018)
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_IRQ_VEC_7_0_PRI_IRQ_VEC_7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_NUM_0_0  
+#define EVP_COP_PRI_FIQ_NUM_0_0                 _MK_ADDR_CONST(0x280)
+#define EVP_COP_PRI_FIQ_NUM_0_0_SECURE                  0x0
+#define EVP_COP_PRI_FIQ_NUM_0_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_NUM_0_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SHIFT)
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_0_0_PRI_FIQ_NUM_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_VEC_0_0  
+#define EVP_COP_PRI_FIQ_VEC_0_0                 _MK_ADDR_CONST(0x284)
+#define EVP_COP_PRI_FIQ_VEC_0_0_SECURE                  0x0
+#define EVP_COP_PRI_FIQ_VEC_0_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_VEC_0_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SHIFT)
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_0_0_PRI_FIQ_VEC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_NUM_1_0  
+#define EVP_COP_PRI_FIQ_NUM_1_0                 _MK_ADDR_CONST(0x288)
+#define EVP_COP_PRI_FIQ_NUM_1_0_SECURE                  0x0
+#define EVP_COP_PRI_FIQ_NUM_1_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_NUM_1_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SHIFT)
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_1_0_PRI_FIQ_NUM_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_VEC_1_0  
+#define EVP_COP_PRI_FIQ_VEC_1_0                 _MK_ADDR_CONST(0x28c)
+#define EVP_COP_PRI_FIQ_VEC_1_0_SECURE                  0x0
+#define EVP_COP_PRI_FIQ_VEC_1_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_VEC_1_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SHIFT)
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_1_0_PRI_FIQ_VEC_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_NUM_2_0  
+#define EVP_COP_PRI_FIQ_NUM_2_0                 _MK_ADDR_CONST(0x290)
+#define EVP_COP_PRI_FIQ_NUM_2_0_SECURE                  0x0
+#define EVP_COP_PRI_FIQ_NUM_2_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_NUM_2_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SHIFT)
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_2_0_PRI_FIQ_NUM_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_VEC_2_0  
+#define EVP_COP_PRI_FIQ_VEC_2_0                 _MK_ADDR_CONST(0x294)
+#define EVP_COP_PRI_FIQ_VEC_2_0_SECURE                  0x0
+#define EVP_COP_PRI_FIQ_VEC_2_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_VEC_2_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SHIFT)
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_2_0_PRI_FIQ_VEC_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_NUM_3_0  
+#define EVP_COP_PRI_FIQ_NUM_3_0                 _MK_ADDR_CONST(0x298)
+#define EVP_COP_PRI_FIQ_NUM_3_0_SECURE                  0x0
+#define EVP_COP_PRI_FIQ_NUM_3_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_NUM_3_0_RESET_VAL                       _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Number for the Interrupt associated with this entry
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SHIFT)
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT                   _MK_MASK_CONST(0x80)
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_NUM_3_0_PRI_FIQ_NUM_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register EVP_COP_PRI_FIQ_VEC_3_0  
+#define EVP_COP_PRI_FIQ_VEC_3_0                 _MK_ADDR_CONST(0x29c)
+#define EVP_COP_PRI_FIQ_VEC_3_0_SECURE                  0x0
+#define EVP_COP_PRI_FIQ_VEC_3_0_WORD_COUNT                      0x1
+#define EVP_COP_PRI_FIQ_VEC_3_0_RESET_VAL                       _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Pointer to the interrupt handler for the above interrupt 
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_FIELD                     (_MK_MASK_CONST(0xffffffff) << EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SHIFT)
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_RANGE                     31:0
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_WOFFSET                   0x0
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT                   _MK_MASK_CONST(0x4000001c)
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define EVP_COP_PRI_FIQ_VEC_3_0_PRI_FIQ_VEC_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_AREVP_REGS(_op_) \
+_op_(EVP_RESET_VECTOR_0) \
+_op_(EVP_UNDEF_VECTOR_0) \
+_op_(EVP_SWI_VECTOR_0) \
+_op_(EVP_PREFETCH_ABORT_VECTOR_0) \
+_op_(EVP_DATA_ABORT_VECTOR_0) \
+_op_(EVP_RSVD_VECTOR_0) \
+_op_(EVP_IRQ_VECTOR_0) \
+_op_(EVP_FIQ_VECTOR_0) \
+_op_(EVP_IRQ_STS_0) \
+_op_(EVP_PRI_IRQ_STS_0) \
+_op_(EVP_FIQ_STS_0) \
+_op_(EVP_PRI_FIQ_STS_0) \
+_op_(EVP_PRI_IRQ_NUM_0_0) \
+_op_(EVP_PRI_IRQ_VEC_0_0) \
+_op_(EVP_PRI_IRQ_NUM_1_0) \
+_op_(EVP_PRI_IRQ_VEC_1_0) \
+_op_(EVP_PRI_IRQ_NUM_2_0) \
+_op_(EVP_PRI_IRQ_VEC_2_0) \
+_op_(EVP_PRI_IRQ_NUM_3_0) \
+_op_(EVP_PRI_IRQ_VEC_3_0) \
+_op_(EVP_PRI_IRQ_NUM_4_0) \
+_op_(EVP_PRI_IRQ_VEC_4_0) \
+_op_(EVP_PRI_IRQ_NUM_5_0) \
+_op_(EVP_PRI_IRQ_VEC_5_0) \
+_op_(EVP_PRI_IRQ_NUM_6_0) \
+_op_(EVP_PRI_IRQ_VEC_6_0) \
+_op_(EVP_PRI_IRQ_NUM_7_0) \
+_op_(EVP_PRI_IRQ_VEC_7_0) \
+_op_(EVP_PRI_FIQ_NUM_0_0) \
+_op_(EVP_PRI_FIQ_VEC_0_0) \
+_op_(EVP_PRI_FIQ_NUM_1_0) \
+_op_(EVP_PRI_FIQ_VEC_1_0) \
+_op_(EVP_PRI_FIQ_NUM_2_0) \
+_op_(EVP_PRI_FIQ_VEC_2_0) \
+_op_(EVP_PRI_FIQ_NUM_3_0) \
+_op_(EVP_PRI_FIQ_VEC_3_0) \
+_op_(EVP_CPU_RESET_VECTOR_0) \
+_op_(EVP_CPU_UNDEF_VECTOR_0) \
+_op_(EVP_CPU_SWI_VECTOR_0) \
+_op_(EVP_CPU_PREFETCH_ABORT_VECTOR_0) \
+_op_(EVP_CPU_DATA_ABORT_VECTOR_0) \
+_op_(EVP_CPU_RSVD_VECTOR_0) \
+_op_(EVP_CPU_IRQ_VECTOR_0) \
+_op_(EVP_CPU_FIQ_VECTOR_0) \
+_op_(EVP_CPU_IRQ_STS_0) \
+_op_(EVP_CPU_PRI_IRQ_STS_0) \
+_op_(EVP_CPU_FIQ_STS_0) \
+_op_(EVP_CPU_PRI_FIQ_STS_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_0_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_0_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_1_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_1_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_2_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_2_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_3_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_3_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_4_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_4_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_5_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_5_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_6_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_6_0) \
+_op_(EVP_CPU_PRI_IRQ_NUM_7_0) \
+_op_(EVP_CPU_PRI_IRQ_VEC_7_0) \
+_op_(EVP_CPU_PRI_FIQ_NUM_0_0) \
+_op_(EVP_CPU_PRI_FIQ_VEC_0_0) \
+_op_(EVP_CPU_PRI_FIQ_NUM_1_0) \
+_op_(EVP_CPU_PRI_FIQ_VEC_1_0) \
+_op_(EVP_CPU_PRI_FIQ_NUM_2_0) \
+_op_(EVP_CPU_PRI_FIQ_VEC_2_0) \
+_op_(EVP_CPU_PRI_FIQ_NUM_3_0) \
+_op_(EVP_CPU_PRI_FIQ_VEC_3_0) \
+_op_(EVP_COP_RESET_VECTOR_0) \
+_op_(EVP_COP_UNDEF_VECTOR_0) \
+_op_(EVP_COP_SWI_VECTOR_0) \
+_op_(EVP_COP_PREFETCH_ABORT_VECTOR_0) \
+_op_(EVP_COP_DATA_ABORT_VECTOR_0) \
+_op_(EVP_COP_RSVD_VECTOR_0) \
+_op_(EVP_COP_IRQ_VECTOR_0) \
+_op_(EVP_COP_FIQ_VECTOR_0) \
+_op_(EVP_COP_IRQ_STS_0) \
+_op_(EVP_COP_PRI_IRQ_STS_0) \
+_op_(EVP_COP_FIQ_STS_0) \
+_op_(EVP_COP_PRI_FIQ_STS_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_0_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_0_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_1_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_1_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_2_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_2_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_3_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_3_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_4_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_4_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_5_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_5_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_6_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_6_0) \
+_op_(EVP_COP_PRI_IRQ_NUM_7_0) \
+_op_(EVP_COP_PRI_IRQ_VEC_7_0) \
+_op_(EVP_COP_PRI_FIQ_NUM_0_0) \
+_op_(EVP_COP_PRI_FIQ_VEC_0_0) \
+_op_(EVP_COP_PRI_FIQ_NUM_1_0) \
+_op_(EVP_COP_PRI_FIQ_VEC_1_0) \
+_op_(EVP_COP_PRI_FIQ_NUM_2_0) \
+_op_(EVP_COP_PRI_FIQ_VEC_2_0) \
+_op_(EVP_COP_PRI_FIQ_NUM_3_0) \
+_op_(EVP_COP_PRI_FIQ_VEC_3_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_EVP        0x00000000
+
+//
+// AREVP REGISTER BANKS
+//
+
+#define EVP0_FIRST_REG 0x0000 // EVP_RESET_VECTOR_0
+#define EVP0_LAST_REG 0x002c // EVP_PRI_FIQ_STS_0
+#define EVP1_FIRST_REG 0x0040 // EVP_PRI_IRQ_NUM_0_0
+#define EVP1_LAST_REG 0x009c // EVP_PRI_FIQ_VEC_3_0
+#define EVP2_FIRST_REG 0x0100 // EVP_CPU_RESET_VECTOR_0
+#define EVP2_LAST_REG 0x012c // EVP_CPU_PRI_FIQ_STS_0
+#define EVP3_FIRST_REG 0x0140 // EVP_CPU_PRI_IRQ_NUM_0_0
+#define EVP3_LAST_REG 0x019c // EVP_CPU_PRI_FIQ_VEC_3_0
+#define EVP4_FIRST_REG 0x0200 // EVP_COP_RESET_VECTOR_0
+#define EVP4_LAST_REG 0x022c // EVP_COP_PRI_FIQ_STS_0
+#define EVP5_FIRST_REG 0x0240 // EVP_COP_PRI_IRQ_NUM_0_0
+#define EVP5_LAST_REG 0x029c // EVP_COP_PRI_FIQ_VEC_3_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___AREVP_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arfic_dist.h b/arch/arm/mach-tegra/nv/include/ap20/arfic_dist.h
new file mode 100644
index 000000000000..19bde0644a5e
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arfic_dist.h
@@ -0,0 +1,18238 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARFIC_DIST_H_INC_
+#define ___ARFIC_DIST_H_INC_
+
+// Register FIC_DIST_DISTRIBUTOR_ENABLE_0  
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0                   _MK_ADDR_CONST(0x1000)
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_SECURE                    0x0
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_WORD_COUNT                        0x1
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_RESET_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_READ_MASK                         _MK_MASK_CONST(0x1)
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
+// Controls if the Distributor responds to changes in the
+// status of its interrupt inputs, SPI or PPI
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_INTERRUPT_IN_ENABLE_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_INTERRUPT_IN_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_DISTRIBUTOR_ENABLE_0_INTERRUPT_IN_ENABLE_SHIFT)
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_INTERRUPT_IN_ENABLE_RANGE                 0:0
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_INTERRUPT_IN_ENABLE_WOFFSET                       0x0
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_INTERRUPT_IN_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_INTERRUPT_IN_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_INTERRUPT_IN_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_ENABLE_0_INTERRUPT_IN_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_IC_TYPE_0  
+#define FIC_DIST_IC_TYPE_0                      _MK_ADDR_CONST(0x1004)
+#define FIC_DIST_IC_TYPE_0_SECURE                       0x0
+#define FIC_DIST_IC_TYPE_0_WORD_COUNT                   0x1
+#define FIC_DIST_IC_TYPE_0_RESET_VAL                    _MK_MASK_CONST(0x424)
+#define FIC_DIST_IC_TYPE_0_RESET_MASK                   _MK_MASK_CONST(0xfcff)
+#define FIC_DIST_IC_TYPE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_IC_TYPE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_IC_TYPE_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_IC_TYPE_0_WRITE_MASK                   _MK_MASK_CONST(0xfcff)
+// Indicates the number of INTIDs provided
+#define FIC_DIST_IC_TYPE_0_IT_LINES_NUMBER_SHIFT                        _MK_SHIFT_CONST(0)
+#define FIC_DIST_IC_TYPE_0_IT_LINES_NUMBER_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_IC_TYPE_0_IT_LINES_NUMBER_SHIFT)
+#define FIC_DIST_IC_TYPE_0_IT_LINES_NUMBER_RANGE                        4:0
+#define FIC_DIST_IC_TYPE_0_IT_LINES_NUMBER_WOFFSET                      0x0
+#define FIC_DIST_IC_TYPE_0_IT_LINES_NUMBER_DEFAULT                      _MK_MASK_CONST(0x4)
+#define FIC_DIST_IC_TYPE_0_IT_LINES_NUMBER_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_IC_TYPE_0_IT_LINES_NUMBER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_IC_TYPE_0_IT_LINES_NUMBER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Indicates the number of CPUs in the system
+#define FIC_DIST_IC_TYPE_0_CPU_NUMBER_SHIFT                     _MK_SHIFT_CONST(5)
+#define FIC_DIST_IC_TYPE_0_CPU_NUMBER_FIELD                     (_MK_MASK_CONST(0x7) << FIC_DIST_IC_TYPE_0_CPU_NUMBER_SHIFT)
+#define FIC_DIST_IC_TYPE_0_CPU_NUMBER_RANGE                     7:5
+#define FIC_DIST_IC_TYPE_0_CPU_NUMBER_WOFFSET                   0x0
+#define FIC_DIST_IC_TYPE_0_CPU_NUMBER_DEFAULT                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_IC_TYPE_0_CPU_NUMBER_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define FIC_DIST_IC_TYPE_0_CPU_NUMBER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_IC_TYPE_0_CPU_NUMBER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates the number of security domains in the system
+#define FIC_DIST_IC_TYPE_0_DOMAINS_SHIFT                        _MK_SHIFT_CONST(10)
+#define FIC_DIST_IC_TYPE_0_DOMAINS_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_IC_TYPE_0_DOMAINS_SHIFT)
+#define FIC_DIST_IC_TYPE_0_DOMAINS_RANGE                        10:10
+#define FIC_DIST_IC_TYPE_0_DOMAINS_WOFFSET                      0x0
+#define FIC_DIST_IC_TYPE_0_DOMAINS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_IC_TYPE_0_DOMAINS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_IC_TYPE_0_DOMAINS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_IC_TYPE_0_DOMAINS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Indicates the number of Lockable SPI
+#define FIC_DIST_IC_TYPE_0_LSPI_SHIFT                   _MK_SHIFT_CONST(11)
+#define FIC_DIST_IC_TYPE_0_LSPI_FIELD                   (_MK_MASK_CONST(0x1f) << FIC_DIST_IC_TYPE_0_LSPI_SHIFT)
+#define FIC_DIST_IC_TYPE_0_LSPI_RANGE                   15:11
+#define FIC_DIST_IC_TYPE_0_LSPI_WOFFSET                 0x0
+#define FIC_DIST_IC_TYPE_0_LSPI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_IC_TYPE_0_LSPI_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define FIC_DIST_IC_TYPE_0_LSPI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_IC_TYPE_0_LSPI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_DISTRIBUTOR_IDENT_0  
+#define FIC_DIST_DISTRIBUTOR_IDENT_0                    _MK_ADDR_CONST(0x1008)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_SECURE                     0x0
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_WORD_COUNT                         0x1
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_RESET_VAL                  _MK_MASK_CONST(0x100043b)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_READ_MASK                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTOR_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTOR_FIELD                  (_MK_MASK_CONST(0xfff) << FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTOR_SHIFT)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTOR_RANGE                  11:0
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTOR_WOFFSET                        0x0
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTOR_DEFAULT                        _MK_MASK_CONST(0x43b)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTOR_DEFAULT_MASK                   _MK_MASK_CONST(0xfff)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_REVISION_NUMBER_SHIFT                      _MK_SHIFT_CONST(12)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_REVISION_NUMBER_FIELD                      (_MK_MASK_CONST(0xfff) << FIC_DIST_DISTRIBUTOR_IDENT_0_REVISION_NUMBER_SHIFT)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_REVISION_NUMBER_RANGE                      23:12
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_REVISION_NUMBER_WOFFSET                    0x0
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_REVISION_NUMBER_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_REVISION_NUMBER_DEFAULT_MASK                       _MK_MASK_CONST(0xfff)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_REVISION_NUMBER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_REVISION_NUMBER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTATION_DEFINED_SHIFT                       _MK_SHIFT_CONST(24)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTATION_DEFINED_FIELD                       (_MK_MASK_CONST(0xff) << FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTATION_DEFINED_SHIFT)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTATION_DEFINED_RANGE                       31:24
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTATION_DEFINED_WOFFSET                     0x0
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTATION_DEFINED_DEFAULT                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTATION_DEFINED_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTATION_DEFINED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_DISTRIBUTOR_IDENT_0_IMPLEMENTATION_DEFINED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Reserved address 4108 [0x100c] 
+
+// Reserved address 4112 [0x1010] 
+
+// Reserved address 4116 [0x1014] 
+
+// Reserved address 4120 [0x1018] 
+
+// Reserved address 4124 [0x101c] 
+
+// Reserved address 4128 [0x1020] 
+
+// Reserved address 4132 [0x1024] 
+
+// Reserved address 4136 [0x1028] 
+
+// Reserved address 4140 [0x102c] 
+
+// Reserved address 4144 [0x1030] 
+
+// Reserved address 4148 [0x1034] 
+
+// Reserved address 4152 [0x1038] 
+
+// Reserved address 4156 [0x103c] 
+
+// Reserved address 4160 [0x1040] 
+
+// Reserved address 4164 [0x1044] 
+
+// Reserved address 4168 [0x1048] 
+
+// Reserved address 4172 [0x104c] 
+
+// Reserved address 4176 [0x1050] 
+
+// Reserved address 4180 [0x1054] 
+
+// Reserved address 4184 [0x1058] 
+
+// Reserved address 4188 [0x105c] 
+
+// Reserved address 4192 [0x1060] 
+
+// Reserved address 4196 [0x1064] 
+
+// Reserved address 4200 [0x1068] 
+
+// Reserved address 4204 [0x106c] 
+
+// Reserved address 4208 [0x1070] 
+
+// Reserved address 4212 [0x1074] 
+
+// Reserved address 4216 [0x1078] 
+
+// Reserved address 4220 [0x107c] 
+
+// Register FIC_DIST_INTERRUPT_SECURITY_0_0  
+#define FIC_DIST_INTERRUPT_SECURITY_0_0                 _MK_ADDR_CONST(0x1080)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_SECURE                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_WORD_COUNT                      0x1
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_RESET_MASK                      _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_READ_MASK                       _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_WRITE_MASK                      _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_0_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_0_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_0_RANGE                      0:0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_0_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_1_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_1_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_1_RANGE                      1:1
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_1_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_2_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_2_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_2_RANGE                      2:2
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_2_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_3_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_3_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_3_RANGE                      3:3
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_3_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_4_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_4_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_4_RANGE                      4:4
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_4_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_5_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_5_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_5_RANGE                      5:5
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_5_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_6_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_6_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_6_RANGE                      6:6
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_6_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_7_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_7_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_7_RANGE                      7:7
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_7_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_8_SHIFT                      _MK_SHIFT_CONST(8)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_8_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_8_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_8_RANGE                      8:8
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_8_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_9_SHIFT                      _MK_SHIFT_CONST(9)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_9_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_9_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_9_RANGE                      9:9
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_9_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_10_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_10_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_10_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_10_RANGE                     10:10
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_10_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_11_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_11_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_11_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_11_RANGE                     11:11
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_11_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_12_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_12_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_12_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_12_RANGE                     12:12
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_12_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_12_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_12_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_13_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_13_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_13_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_13_RANGE                     13:13
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_13_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_13_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_13_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_13_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_13_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_14_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_14_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_14_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_14_RANGE                     14:14
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_14_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_14_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_14_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_14_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_14_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_15_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_15_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_15_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_15_RANGE                     15:15
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_15_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_15_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_15_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_15_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_STI_15_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_4_SHIFT                      _MK_SHIFT_CONST(27)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_4_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_4_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_4_RANGE                      27:27
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_4_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_0_SHIFT                      _MK_SHIFT_CONST(28)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_0_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_0_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_0_RANGE                      28:28
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_0_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_1_SHIFT                      _MK_SHIFT_CONST(29)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_1_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_1_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_1_RANGE                      29:29
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_1_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_2_SHIFT                      _MK_SHIFT_CONST(30)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_2_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_2_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_2_RANGE                      30:30
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_2_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_3_SHIFT                      _MK_SHIFT_CONST(31)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_3_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_3_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_3_RANGE                      31:31
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_3_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_0_0_INT_NS_PPI_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INTERRUPT_SECURITY_1_0  
+#define FIC_DIST_INTERRUPT_SECURITY_1_0                 _MK_ADDR_CONST(0x1084)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_SECURE                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_WORD_COUNT                      0x1
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_0_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_0_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_0_RANGE                      0:0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_0_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_1_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_1_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_1_RANGE                      1:1
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_1_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_2_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_2_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_2_RANGE                      2:2
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_2_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_3_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_3_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_3_RANGE                      3:3
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_3_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_4_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_4_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_4_RANGE                      4:4
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_4_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_5_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_5_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_5_RANGE                      5:5
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_5_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_6_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_6_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_6_RANGE                      6:6
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_6_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_7_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_7_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_7_RANGE                      7:7
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_7_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_8_SHIFT                      _MK_SHIFT_CONST(8)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_8_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_8_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_8_RANGE                      8:8
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_8_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_9_SHIFT                      _MK_SHIFT_CONST(9)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_9_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_9_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_9_RANGE                      9:9
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_9_WOFFSET                    0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_10_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_10_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_10_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_10_RANGE                     10:10
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_10_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_11_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_11_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_11_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_11_RANGE                     11:11
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_11_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_12_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_12_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_12_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_12_RANGE                     12:12
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_12_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_12_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_12_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_13_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_13_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_13_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_13_RANGE                     13:13
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_13_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_13_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_13_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_13_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_13_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_14_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_14_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_14_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_14_RANGE                     14:14
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_14_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_14_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_14_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_14_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_14_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_15_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_15_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_15_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_15_RANGE                     15:15
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_15_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_15_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_15_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_15_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_15_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_16_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_16_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_16_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_16_RANGE                     16:16
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_16_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_16_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_16_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_16_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_16_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_17_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_17_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_17_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_17_RANGE                     17:17
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_17_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_17_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_17_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_17_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_17_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_18_SHIFT                     _MK_SHIFT_CONST(18)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_18_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_18_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_18_RANGE                     18:18
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_18_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_18_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_18_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_18_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_18_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_19_SHIFT                     _MK_SHIFT_CONST(19)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_19_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_19_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_19_RANGE                     19:19
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_19_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_19_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_19_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_19_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_19_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_20_SHIFT                     _MK_SHIFT_CONST(20)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_20_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_20_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_20_RANGE                     20:20
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_20_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_20_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_20_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_20_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_20_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_21_SHIFT                     _MK_SHIFT_CONST(21)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_21_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_21_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_21_RANGE                     21:21
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_21_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_21_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_21_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_21_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_21_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_22_SHIFT                     _MK_SHIFT_CONST(22)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_22_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_22_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_22_RANGE                     22:22
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_22_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_22_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_22_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_22_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_22_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_23_SHIFT                     _MK_SHIFT_CONST(23)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_23_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_23_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_23_RANGE                     23:23
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_23_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_23_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_23_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_23_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_23_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_24_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_24_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_24_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_24_RANGE                     24:24
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_24_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_24_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_24_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_24_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_24_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_25_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_25_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_25_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_25_RANGE                     25:25
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_25_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_25_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_25_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_25_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_25_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_26_SHIFT                     _MK_SHIFT_CONST(26)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_26_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_26_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_26_RANGE                     26:26
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_26_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_26_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_26_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_26_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_26_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_27_SHIFT                     _MK_SHIFT_CONST(27)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_27_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_27_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_27_RANGE                     27:27
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_27_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_27_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_27_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_27_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_27_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_28_SHIFT                     _MK_SHIFT_CONST(28)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_28_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_28_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_28_RANGE                     28:28
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_28_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_28_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_28_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_28_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_28_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_29_SHIFT                     _MK_SHIFT_CONST(29)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_29_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_29_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_29_RANGE                     29:29
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_29_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_29_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_29_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_29_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_29_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_30_SHIFT                     _MK_SHIFT_CONST(30)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_30_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_30_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_30_RANGE                     30:30
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_30_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_30_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_30_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_30_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_30_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_31_SHIFT                     _MK_SHIFT_CONST(31)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_31_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_31_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_31_RANGE                     31:31
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_31_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_31_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_31_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_31_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_1_0_INT_NS_SPI_31_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INTERRUPT_SECURITY_2_0  
+#define FIC_DIST_INTERRUPT_SECURITY_2_0                 _MK_ADDR_CONST(0x1088)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_SECURE                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_WORD_COUNT                      0x1
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_32_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_32_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_32_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_32_RANGE                     0:0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_32_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_32_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_32_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_32_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_32_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_33_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_33_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_33_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_33_RANGE                     1:1
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_33_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_33_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_33_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_33_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_33_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_34_SHIFT                     _MK_SHIFT_CONST(2)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_34_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_34_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_34_RANGE                     2:2
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_34_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_34_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_34_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_34_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_34_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_35_SHIFT                     _MK_SHIFT_CONST(3)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_35_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_35_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_35_RANGE                     3:3
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_35_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_35_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_35_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_35_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_35_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_36_SHIFT                     _MK_SHIFT_CONST(4)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_36_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_36_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_36_RANGE                     4:4
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_36_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_36_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_36_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_36_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_36_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_37_SHIFT                     _MK_SHIFT_CONST(5)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_37_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_37_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_37_RANGE                     5:5
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_37_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_37_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_37_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_37_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_37_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_38_SHIFT                     _MK_SHIFT_CONST(6)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_38_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_38_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_38_RANGE                     6:6
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_38_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_38_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_38_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_38_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_38_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_39_SHIFT                     _MK_SHIFT_CONST(7)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_39_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_39_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_39_RANGE                     7:7
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_39_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_39_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_39_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_39_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_39_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_40_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_40_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_40_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_40_RANGE                     8:8
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_40_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_40_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_40_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_40_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_40_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_41_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_41_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_41_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_41_RANGE                     9:9
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_41_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_41_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_41_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_41_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_41_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_42_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_42_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_42_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_42_RANGE                     10:10
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_42_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_42_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_42_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_42_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_42_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_43_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_43_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_43_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_43_RANGE                     11:11
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_43_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_43_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_43_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_43_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_43_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_44_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_44_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_44_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_44_RANGE                     12:12
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_44_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_44_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_44_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_44_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_44_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_45_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_45_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_45_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_45_RANGE                     13:13
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_45_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_45_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_45_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_45_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_45_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_46_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_46_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_46_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_46_RANGE                     14:14
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_46_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_46_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_46_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_46_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_46_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_47_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_47_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_47_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_47_RANGE                     15:15
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_47_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_47_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_47_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_47_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_47_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_48_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_48_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_48_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_48_RANGE                     16:16
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_48_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_48_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_48_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_48_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_48_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_49_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_49_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_49_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_49_RANGE                     17:17
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_49_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_49_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_49_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_49_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_49_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_50_SHIFT                     _MK_SHIFT_CONST(18)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_50_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_50_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_50_RANGE                     18:18
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_50_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_50_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_50_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_50_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_50_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_51_SHIFT                     _MK_SHIFT_CONST(19)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_51_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_51_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_51_RANGE                     19:19
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_51_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_51_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_51_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_51_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_51_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_52_SHIFT                     _MK_SHIFT_CONST(20)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_52_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_52_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_52_RANGE                     20:20
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_52_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_52_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_52_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_52_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_52_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_53_SHIFT                     _MK_SHIFT_CONST(21)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_53_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_53_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_53_RANGE                     21:21
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_53_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_53_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_53_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_53_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_53_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_54_SHIFT                     _MK_SHIFT_CONST(22)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_54_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_54_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_54_RANGE                     22:22
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_54_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_54_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_54_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_54_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_54_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_55_SHIFT                     _MK_SHIFT_CONST(23)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_55_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_55_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_55_RANGE                     23:23
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_55_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_55_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_55_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_55_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_55_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_56_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_56_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_56_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_56_RANGE                     24:24
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_56_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_56_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_56_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_56_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_56_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_57_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_57_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_57_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_57_RANGE                     25:25
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_57_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_57_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_57_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_57_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_57_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_58_SHIFT                     _MK_SHIFT_CONST(26)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_58_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_58_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_58_RANGE                     26:26
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_58_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_58_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_58_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_58_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_58_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_59_SHIFT                     _MK_SHIFT_CONST(27)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_59_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_59_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_59_RANGE                     27:27
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_59_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_59_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_59_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_59_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_59_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_60_SHIFT                     _MK_SHIFT_CONST(28)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_60_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_60_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_60_RANGE                     28:28
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_60_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_60_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_60_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_60_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_60_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_61_SHIFT                     _MK_SHIFT_CONST(29)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_61_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_61_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_61_RANGE                     29:29
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_61_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_61_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_61_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_61_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_61_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_62_SHIFT                     _MK_SHIFT_CONST(30)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_62_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_62_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_62_RANGE                     30:30
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_62_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_62_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_62_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_62_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_62_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_63_SHIFT                     _MK_SHIFT_CONST(31)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_63_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_63_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_63_RANGE                     31:31
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_63_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_63_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_63_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_63_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_2_0_INT_NS_SPI_63_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INTERRUPT_SECURITY_3_0  
+#define FIC_DIST_INTERRUPT_SECURITY_3_0                 _MK_ADDR_CONST(0x108c)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_SECURE                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_WORD_COUNT                      0x1
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_64_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_64_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_64_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_64_RANGE                     0:0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_64_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_64_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_64_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_64_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_64_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_65_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_65_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_65_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_65_RANGE                     1:1
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_65_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_65_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_65_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_65_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_65_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_66_SHIFT                     _MK_SHIFT_CONST(2)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_66_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_66_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_66_RANGE                     2:2
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_66_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_66_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_66_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_66_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_66_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_67_SHIFT                     _MK_SHIFT_CONST(3)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_67_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_67_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_67_RANGE                     3:3
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_67_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_67_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_67_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_67_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_67_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_68_SHIFT                     _MK_SHIFT_CONST(4)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_68_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_68_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_68_RANGE                     4:4
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_68_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_68_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_68_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_68_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_68_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_69_SHIFT                     _MK_SHIFT_CONST(5)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_69_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_69_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_69_RANGE                     5:5
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_69_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_69_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_69_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_69_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_69_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_70_SHIFT                     _MK_SHIFT_CONST(6)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_70_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_70_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_70_RANGE                     6:6
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_70_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_70_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_70_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_70_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_70_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_71_SHIFT                     _MK_SHIFT_CONST(7)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_71_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_71_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_71_RANGE                     7:7
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_71_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_71_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_71_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_71_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_71_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_72_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_72_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_72_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_72_RANGE                     8:8
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_72_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_72_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_72_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_72_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_72_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_73_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_73_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_73_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_73_RANGE                     9:9
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_73_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_73_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_73_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_73_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_73_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_74_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_74_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_74_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_74_RANGE                     10:10
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_74_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_74_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_74_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_74_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_74_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_75_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_75_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_75_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_75_RANGE                     11:11
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_75_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_75_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_75_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_75_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_75_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_76_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_76_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_76_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_76_RANGE                     12:12
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_76_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_76_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_76_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_76_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_76_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_77_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_77_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_77_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_77_RANGE                     13:13
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_77_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_77_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_77_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_77_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_77_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_78_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_78_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_78_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_78_RANGE                     14:14
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_78_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_78_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_78_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_78_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_78_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_79_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_79_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_79_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_79_RANGE                     15:15
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_79_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_79_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_79_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_79_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_79_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_80_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_80_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_80_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_80_RANGE                     16:16
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_80_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_80_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_80_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_80_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_80_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_81_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_81_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_81_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_81_RANGE                     17:17
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_81_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_81_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_81_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_81_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_81_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_82_SHIFT                     _MK_SHIFT_CONST(18)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_82_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_82_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_82_RANGE                     18:18
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_82_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_82_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_82_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_82_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_82_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_83_SHIFT                     _MK_SHIFT_CONST(19)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_83_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_83_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_83_RANGE                     19:19
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_83_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_83_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_83_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_83_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_83_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_84_SHIFT                     _MK_SHIFT_CONST(20)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_84_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_84_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_84_RANGE                     20:20
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_84_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_84_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_84_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_84_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_84_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_85_SHIFT                     _MK_SHIFT_CONST(21)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_85_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_85_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_85_RANGE                     21:21
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_85_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_85_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_85_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_85_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_85_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_86_SHIFT                     _MK_SHIFT_CONST(22)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_86_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_86_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_86_RANGE                     22:22
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_86_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_86_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_86_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_86_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_86_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_87_SHIFT                     _MK_SHIFT_CONST(23)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_87_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_87_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_87_RANGE                     23:23
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_87_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_87_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_87_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_87_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_87_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_88_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_88_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_88_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_88_RANGE                     24:24
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_88_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_88_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_88_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_88_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_88_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_89_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_89_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_89_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_89_RANGE                     25:25
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_89_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_89_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_89_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_89_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_89_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_90_SHIFT                     _MK_SHIFT_CONST(26)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_90_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_90_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_90_RANGE                     26:26
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_90_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_90_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_90_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_90_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_90_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_91_SHIFT                     _MK_SHIFT_CONST(27)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_91_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_91_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_91_RANGE                     27:27
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_91_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_91_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_91_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_91_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_91_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_92_SHIFT                     _MK_SHIFT_CONST(28)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_92_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_92_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_92_RANGE                     28:28
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_92_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_92_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_92_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_92_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_92_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_93_SHIFT                     _MK_SHIFT_CONST(29)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_93_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_93_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_93_RANGE                     29:29
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_93_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_93_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_93_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_93_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_93_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_94_SHIFT                     _MK_SHIFT_CONST(30)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_94_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_94_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_94_RANGE                     30:30
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_94_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_94_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_94_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_94_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_94_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_95_SHIFT                     _MK_SHIFT_CONST(31)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_95_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_95_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_95_RANGE                     31:31
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_95_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_95_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_95_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_95_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_3_0_INT_NS_SPI_95_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INTERRUPT_SECURITY_4_0  
+#define FIC_DIST_INTERRUPT_SECURITY_4_0                 _MK_ADDR_CONST(0x1090)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_SECURE                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_WORD_COUNT                      0x1
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_96_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_96_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_96_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_96_RANGE                     0:0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_96_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_96_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_96_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_96_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_96_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_97_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_97_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_97_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_97_RANGE                     1:1
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_97_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_97_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_97_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_97_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_97_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_98_SHIFT                     _MK_SHIFT_CONST(2)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_98_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_98_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_98_RANGE                     2:2
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_98_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_98_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_98_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_98_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_98_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_99_SHIFT                     _MK_SHIFT_CONST(3)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_99_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_99_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_99_RANGE                     3:3
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_99_WOFFSET                   0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_99_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_99_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_99_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_99_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_100_SHIFT                    _MK_SHIFT_CONST(4)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_100_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_100_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_100_RANGE                    4:4
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_100_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_100_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_100_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_100_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_100_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_101_SHIFT                    _MK_SHIFT_CONST(5)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_101_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_101_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_101_RANGE                    5:5
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_101_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_101_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_101_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_101_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_101_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_102_SHIFT                    _MK_SHIFT_CONST(6)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_102_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_102_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_102_RANGE                    6:6
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_102_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_102_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_102_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_102_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_102_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_103_SHIFT                    _MK_SHIFT_CONST(7)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_103_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_103_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_103_RANGE                    7:7
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_103_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_103_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_103_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_103_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_103_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_104_SHIFT                    _MK_SHIFT_CONST(8)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_104_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_104_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_104_RANGE                    8:8
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_104_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_104_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_104_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_104_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_104_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_105_SHIFT                    _MK_SHIFT_CONST(9)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_105_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_105_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_105_RANGE                    9:9
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_105_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_105_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_105_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_105_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_105_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_106_SHIFT                    _MK_SHIFT_CONST(10)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_106_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_106_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_106_RANGE                    10:10
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_106_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_106_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_106_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_106_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_106_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_107_SHIFT                    _MK_SHIFT_CONST(11)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_107_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_107_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_107_RANGE                    11:11
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_107_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_107_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_107_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_107_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_107_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_108_SHIFT                    _MK_SHIFT_CONST(12)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_108_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_108_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_108_RANGE                    12:12
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_108_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_108_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_108_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_108_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_108_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_109_SHIFT                    _MK_SHIFT_CONST(13)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_109_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_109_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_109_RANGE                    13:13
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_109_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_109_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_109_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_109_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_109_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_110_SHIFT                    _MK_SHIFT_CONST(14)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_110_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_110_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_110_RANGE                    14:14
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_110_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_110_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_110_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_110_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_110_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_111_SHIFT                    _MK_SHIFT_CONST(15)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_111_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_111_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_111_RANGE                    15:15
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_111_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_111_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_111_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_111_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_111_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_112_SHIFT                    _MK_SHIFT_CONST(16)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_112_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_112_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_112_RANGE                    16:16
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_112_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_112_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_112_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_112_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_112_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_113_SHIFT                    _MK_SHIFT_CONST(17)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_113_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_113_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_113_RANGE                    17:17
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_113_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_113_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_113_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_113_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_113_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_114_SHIFT                    _MK_SHIFT_CONST(18)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_114_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_114_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_114_RANGE                    18:18
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_114_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_114_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_114_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_114_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_114_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_115_SHIFT                    _MK_SHIFT_CONST(19)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_115_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_115_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_115_RANGE                    19:19
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_115_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_115_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_115_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_115_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_115_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_116_SHIFT                    _MK_SHIFT_CONST(20)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_116_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_116_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_116_RANGE                    20:20
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_116_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_116_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_116_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_116_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_116_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_117_SHIFT                    _MK_SHIFT_CONST(21)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_117_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_117_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_117_RANGE                    21:21
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_117_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_117_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_117_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_117_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_117_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_118_SHIFT                    _MK_SHIFT_CONST(22)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_118_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_118_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_118_RANGE                    22:22
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_118_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_118_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_118_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_118_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_118_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_119_SHIFT                    _MK_SHIFT_CONST(23)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_119_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_119_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_119_RANGE                    23:23
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_119_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_119_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_119_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_119_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_119_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_120_SHIFT                    _MK_SHIFT_CONST(24)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_120_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_120_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_120_RANGE                    24:24
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_120_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_120_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_120_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_120_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_120_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_121_SHIFT                    _MK_SHIFT_CONST(25)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_121_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_121_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_121_RANGE                    25:25
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_121_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_121_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_121_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_121_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_121_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_122_SHIFT                    _MK_SHIFT_CONST(26)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_122_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_122_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_122_RANGE                    26:26
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_122_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_122_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_122_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_122_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_122_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_123_SHIFT                    _MK_SHIFT_CONST(27)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_123_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_123_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_123_RANGE                    27:27
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_123_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_123_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_123_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_123_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_123_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_124_SHIFT                    _MK_SHIFT_CONST(28)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_124_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_124_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_124_RANGE                    28:28
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_124_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_124_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_124_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_124_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_124_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_125_SHIFT                    _MK_SHIFT_CONST(29)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_125_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_125_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_125_RANGE                    29:29
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_125_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_125_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_125_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_125_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_125_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_126_SHIFT                    _MK_SHIFT_CONST(30)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_126_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_126_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_126_RANGE                    30:30
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_126_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_126_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_126_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_126_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_126_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_127_SHIFT                    _MK_SHIFT_CONST(31)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_127_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_127_SHIFT)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_127_RANGE                    31:31
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_127_WOFFSET                  0x0
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_127_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_127_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_127_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INTERRUPT_SECURITY_4_0_INT_NS_SPI_127_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 4244 [0x1094] 
+
+// Reserved address 4248 [0x1098] 
+
+// Reserved address 4252 [0x109c] 
+
+// Reserved address 4256 [0x10a0] 
+
+// Reserved address 4260 [0x10a4] 
+
+// Reserved address 4264 [0x10a8] 
+
+// Reserved address 4268 [0x10ac] 
+
+// Reserved address 4272 [0x10b0] 
+
+// Reserved address 4276 [0x10b4] 
+
+// Reserved address 4280 [0x10b8] 
+
+// Reserved address 4284 [0x10bc] 
+
+// Reserved address 4288 [0x10c0] 
+
+// Reserved address 4292 [0x10c4] 
+
+// Reserved address 4296 [0x10c8] 
+
+// Reserved address 4300 [0x10cc] 
+
+// Reserved address 4304 [0x10d0] 
+
+// Reserved address 4308 [0x10d4] 
+
+// Reserved address 4312 [0x10d8] 
+
+// Reserved address 4316 [0x10dc] 
+
+// Reserved address 4320 [0x10e0] 
+
+// Reserved address 4324 [0x10e4] 
+
+// Reserved address 4328 [0x10e8] 
+
+// Reserved address 4332 [0x10ec] 
+
+// Reserved address 4336 [0x10f0] 
+
+// Reserved address 4340 [0x10f4] 
+
+// Reserved address 4344 [0x10f8] 
+
+// Reserved address 4348 [0x10fc] 
+
+// Register FIC_DIST_ENABLE_SET_0_0  
+#define FIC_DIST_ENABLE_SET_0_0                 _MK_ADDR_CONST(0x1100)
+#define FIC_DIST_ENABLE_SET_0_0_SECURE                  0x0
+#define FIC_DIST_ENABLE_SET_0_0_WORD_COUNT                      0x1
+#define FIC_DIST_ENABLE_SET_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_RESET_MASK                      _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_ENABLE_SET_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_READ_MASK                       _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_ENABLE_SET_0_0_WRITE_MASK                      _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_0_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_0_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_0_RANGE                      0:0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_0_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_1_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_1_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_1_RANGE                      1:1
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_1_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_2_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_2_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_2_RANGE                      2:2
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_2_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_3_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_3_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_3_RANGE                      3:3
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_3_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_4_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_4_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_4_RANGE                      4:4
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_4_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_5_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_5_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_5_RANGE                      5:5
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_5_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_6_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_6_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_6_RANGE                      6:6
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_6_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_7_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_7_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_7_RANGE                      7:7
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_7_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_8_SHIFT                      _MK_SHIFT_CONST(8)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_8_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_8_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_8_RANGE                      8:8
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_8_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_9_SHIFT                      _MK_SHIFT_CONST(9)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_9_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_9_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_9_RANGE                      9:9
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_9_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_10_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_10_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_10_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_10_RANGE                     10:10
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_10_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_11_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_11_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_11_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_11_RANGE                     11:11
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_11_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_12_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_12_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_12_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_12_RANGE                     12:12
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_12_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_12_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_12_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_13_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_13_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_13_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_13_RANGE                     13:13
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_13_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_13_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_13_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_13_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_13_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_14_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_14_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_14_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_14_RANGE                     14:14
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_14_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_14_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_14_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_14_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_14_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_15_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_15_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_15_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_15_RANGE                     15:15
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_15_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_15_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_15_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_15_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_STI_15_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_4_SHIFT                      _MK_SHIFT_CONST(27)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_4_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_4_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_4_RANGE                      27:27
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_4_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_0_SHIFT                      _MK_SHIFT_CONST(28)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_0_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_0_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_0_RANGE                      28:28
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_0_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_1_SHIFT                      _MK_SHIFT_CONST(29)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_1_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_1_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_1_RANGE                      29:29
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_1_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_2_SHIFT                      _MK_SHIFT_CONST(30)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_2_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_2_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_2_RANGE                      30:30
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_2_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_3_SHIFT                      _MK_SHIFT_CONST(31)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_3_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_3_SHIFT)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_3_RANGE                      31:31
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_3_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_0_0_EN_SET_PPI_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ENABLE_SET_1_0  
+#define FIC_DIST_ENABLE_SET_1_0                 _MK_ADDR_CONST(0x1104)
+#define FIC_DIST_ENABLE_SET_1_0_SECURE                  0x0
+#define FIC_DIST_ENABLE_SET_1_0_WORD_COUNT                      0x1
+#define FIC_DIST_ENABLE_SET_1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_0_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_0_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_0_RANGE                      0:0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_0_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_1_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_1_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_1_RANGE                      1:1
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_1_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_2_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_2_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_2_RANGE                      2:2
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_2_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_3_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_3_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_3_RANGE                      3:3
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_3_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_4_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_4_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_4_RANGE                      4:4
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_4_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_5_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_5_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_5_RANGE                      5:5
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_5_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_6_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_6_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_6_RANGE                      6:6
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_6_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_7_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_7_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_7_RANGE                      7:7
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_7_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_8_SHIFT                      _MK_SHIFT_CONST(8)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_8_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_8_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_8_RANGE                      8:8
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_8_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_9_SHIFT                      _MK_SHIFT_CONST(9)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_9_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_9_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_9_RANGE                      9:9
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_9_WOFFSET                    0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_10_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_10_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_10_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_10_RANGE                     10:10
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_10_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_11_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_11_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_11_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_11_RANGE                     11:11
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_11_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_12_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_12_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_12_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_12_RANGE                     12:12
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_12_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_12_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_12_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_13_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_13_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_13_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_13_RANGE                     13:13
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_13_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_13_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_13_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_13_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_13_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_14_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_14_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_14_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_14_RANGE                     14:14
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_14_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_14_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_14_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_14_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_14_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_15_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_15_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_15_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_15_RANGE                     15:15
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_15_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_15_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_15_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_15_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_15_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_16_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_16_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_16_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_16_RANGE                     16:16
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_16_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_16_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_16_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_16_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_16_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_17_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_17_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_17_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_17_RANGE                     17:17
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_17_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_17_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_17_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_17_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_17_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_18_SHIFT                     _MK_SHIFT_CONST(18)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_18_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_18_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_18_RANGE                     18:18
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_18_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_18_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_18_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_18_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_18_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_19_SHIFT                     _MK_SHIFT_CONST(19)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_19_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_19_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_19_RANGE                     19:19
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_19_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_19_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_19_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_19_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_19_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_20_SHIFT                     _MK_SHIFT_CONST(20)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_20_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_20_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_20_RANGE                     20:20
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_20_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_20_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_20_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_20_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_20_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_21_SHIFT                     _MK_SHIFT_CONST(21)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_21_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_21_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_21_RANGE                     21:21
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_21_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_21_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_21_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_21_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_21_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_22_SHIFT                     _MK_SHIFT_CONST(22)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_22_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_22_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_22_RANGE                     22:22
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_22_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_22_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_22_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_22_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_22_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_23_SHIFT                     _MK_SHIFT_CONST(23)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_23_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_23_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_23_RANGE                     23:23
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_23_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_23_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_23_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_23_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_23_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_24_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_24_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_24_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_24_RANGE                     24:24
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_24_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_24_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_24_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_24_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_24_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_25_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_25_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_25_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_25_RANGE                     25:25
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_25_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_25_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_25_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_25_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_25_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_26_SHIFT                     _MK_SHIFT_CONST(26)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_26_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_26_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_26_RANGE                     26:26
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_26_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_26_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_26_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_26_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_26_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_27_SHIFT                     _MK_SHIFT_CONST(27)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_27_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_27_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_27_RANGE                     27:27
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_27_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_27_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_27_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_27_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_27_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_28_SHIFT                     _MK_SHIFT_CONST(28)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_28_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_28_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_28_RANGE                     28:28
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_28_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_28_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_28_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_28_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_28_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_29_SHIFT                     _MK_SHIFT_CONST(29)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_29_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_29_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_29_RANGE                     29:29
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_29_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_29_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_29_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_29_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_29_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_30_SHIFT                     _MK_SHIFT_CONST(30)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_30_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_30_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_30_RANGE                     30:30
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_30_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_30_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_30_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_30_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_30_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_31_SHIFT                     _MK_SHIFT_CONST(31)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_31_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_31_SHIFT)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_31_RANGE                     31:31
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_31_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_31_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_31_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_31_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_1_0_EN_SET_SPI_31_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ENABLE_SET_2_0  
+#define FIC_DIST_ENABLE_SET_2_0                 _MK_ADDR_CONST(0x1108)
+#define FIC_DIST_ENABLE_SET_2_0_SECURE                  0x0
+#define FIC_DIST_ENABLE_SET_2_0_WORD_COUNT                      0x1
+#define FIC_DIST_ENABLE_SET_2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_32_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_32_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_32_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_32_RANGE                     0:0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_32_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_32_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_32_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_32_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_32_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_33_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_33_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_33_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_33_RANGE                     1:1
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_33_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_33_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_33_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_33_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_33_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_34_SHIFT                     _MK_SHIFT_CONST(2)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_34_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_34_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_34_RANGE                     2:2
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_34_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_34_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_34_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_34_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_34_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_35_SHIFT                     _MK_SHIFT_CONST(3)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_35_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_35_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_35_RANGE                     3:3
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_35_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_35_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_35_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_35_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_35_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_36_SHIFT                     _MK_SHIFT_CONST(4)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_36_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_36_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_36_RANGE                     4:4
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_36_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_36_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_36_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_36_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_36_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_37_SHIFT                     _MK_SHIFT_CONST(5)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_37_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_37_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_37_RANGE                     5:5
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_37_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_37_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_37_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_37_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_37_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_38_SHIFT                     _MK_SHIFT_CONST(6)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_38_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_38_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_38_RANGE                     6:6
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_38_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_38_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_38_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_38_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_38_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_39_SHIFT                     _MK_SHIFT_CONST(7)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_39_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_39_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_39_RANGE                     7:7
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_39_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_39_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_39_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_39_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_39_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_40_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_40_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_40_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_40_RANGE                     8:8
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_40_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_40_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_40_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_40_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_40_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_41_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_41_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_41_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_41_RANGE                     9:9
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_41_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_41_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_41_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_41_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_41_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_42_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_42_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_42_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_42_RANGE                     10:10
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_42_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_42_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_42_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_42_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_42_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_43_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_43_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_43_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_43_RANGE                     11:11
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_43_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_43_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_43_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_43_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_43_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_44_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_44_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_44_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_44_RANGE                     12:12
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_44_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_44_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_44_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_44_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_44_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_45_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_45_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_45_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_45_RANGE                     13:13
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_45_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_45_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_45_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_45_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_45_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_46_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_46_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_46_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_46_RANGE                     14:14
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_46_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_46_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_46_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_46_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_46_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_47_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_47_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_47_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_47_RANGE                     15:15
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_47_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_47_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_47_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_47_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_47_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_48_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_48_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_48_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_48_RANGE                     16:16
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_48_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_48_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_48_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_48_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_48_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_49_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_49_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_49_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_49_RANGE                     17:17
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_49_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_49_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_49_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_49_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_49_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_50_SHIFT                     _MK_SHIFT_CONST(18)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_50_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_50_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_50_RANGE                     18:18
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_50_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_50_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_50_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_50_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_50_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_51_SHIFT                     _MK_SHIFT_CONST(19)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_51_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_51_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_51_RANGE                     19:19
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_51_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_51_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_51_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_51_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_51_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_52_SHIFT                     _MK_SHIFT_CONST(20)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_52_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_52_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_52_RANGE                     20:20
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_52_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_52_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_52_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_52_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_52_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_53_SHIFT                     _MK_SHIFT_CONST(21)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_53_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_53_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_53_RANGE                     21:21
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_53_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_53_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_53_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_53_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_53_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_54_SHIFT                     _MK_SHIFT_CONST(22)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_54_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_54_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_54_RANGE                     22:22
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_54_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_54_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_54_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_54_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_54_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_55_SHIFT                     _MK_SHIFT_CONST(23)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_55_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_55_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_55_RANGE                     23:23
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_55_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_55_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_55_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_55_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_55_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_56_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_56_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_56_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_56_RANGE                     24:24
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_56_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_56_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_56_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_56_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_56_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_57_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_57_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_57_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_57_RANGE                     25:25
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_57_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_57_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_57_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_57_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_57_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_58_SHIFT                     _MK_SHIFT_CONST(26)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_58_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_58_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_58_RANGE                     26:26
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_58_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_58_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_58_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_58_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_58_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_59_SHIFT                     _MK_SHIFT_CONST(27)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_59_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_59_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_59_RANGE                     27:27
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_59_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_59_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_59_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_59_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_59_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_60_SHIFT                     _MK_SHIFT_CONST(28)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_60_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_60_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_60_RANGE                     28:28
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_60_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_60_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_60_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_60_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_60_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_61_SHIFT                     _MK_SHIFT_CONST(29)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_61_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_61_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_61_RANGE                     29:29
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_61_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_61_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_61_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_61_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_61_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_62_SHIFT                     _MK_SHIFT_CONST(30)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_62_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_62_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_62_RANGE                     30:30
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_62_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_62_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_62_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_62_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_62_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_63_SHIFT                     _MK_SHIFT_CONST(31)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_63_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_63_SHIFT)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_63_RANGE                     31:31
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_63_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_63_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_63_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_63_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_2_0_EN_SET_SPI_63_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ENABLE_SET_3_0  
+#define FIC_DIST_ENABLE_SET_3_0                 _MK_ADDR_CONST(0x110c)
+#define FIC_DIST_ENABLE_SET_3_0_SECURE                  0x0
+#define FIC_DIST_ENABLE_SET_3_0_WORD_COUNT                      0x1
+#define FIC_DIST_ENABLE_SET_3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_64_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_64_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_64_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_64_RANGE                     0:0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_64_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_64_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_64_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_64_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_64_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_65_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_65_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_65_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_65_RANGE                     1:1
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_65_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_65_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_65_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_65_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_65_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_66_SHIFT                     _MK_SHIFT_CONST(2)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_66_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_66_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_66_RANGE                     2:2
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_66_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_66_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_66_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_66_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_66_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_67_SHIFT                     _MK_SHIFT_CONST(3)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_67_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_67_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_67_RANGE                     3:3
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_67_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_67_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_67_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_67_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_67_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_68_SHIFT                     _MK_SHIFT_CONST(4)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_68_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_68_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_68_RANGE                     4:4
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_68_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_68_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_68_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_68_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_68_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_69_SHIFT                     _MK_SHIFT_CONST(5)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_69_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_69_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_69_RANGE                     5:5
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_69_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_69_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_69_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_69_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_69_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_70_SHIFT                     _MK_SHIFT_CONST(6)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_70_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_70_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_70_RANGE                     6:6
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_70_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_70_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_70_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_70_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_70_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_71_SHIFT                     _MK_SHIFT_CONST(7)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_71_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_71_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_71_RANGE                     7:7
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_71_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_71_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_71_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_71_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_71_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_72_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_72_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_72_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_72_RANGE                     8:8
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_72_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_72_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_72_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_72_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_72_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_73_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_73_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_73_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_73_RANGE                     9:9
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_73_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_73_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_73_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_73_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_73_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_74_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_74_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_74_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_74_RANGE                     10:10
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_74_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_74_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_74_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_74_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_74_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_75_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_75_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_75_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_75_RANGE                     11:11
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_75_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_75_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_75_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_75_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_75_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_76_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_76_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_76_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_76_RANGE                     12:12
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_76_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_76_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_76_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_76_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_76_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_77_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_77_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_77_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_77_RANGE                     13:13
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_77_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_77_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_77_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_77_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_77_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_78_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_78_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_78_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_78_RANGE                     14:14
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_78_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_78_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_78_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_78_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_78_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_79_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_79_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_79_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_79_RANGE                     15:15
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_79_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_79_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_79_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_79_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_79_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_80_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_80_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_80_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_80_RANGE                     16:16
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_80_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_80_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_80_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_80_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_80_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_81_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_81_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_81_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_81_RANGE                     17:17
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_81_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_81_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_81_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_81_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_81_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_82_SHIFT                     _MK_SHIFT_CONST(18)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_82_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_82_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_82_RANGE                     18:18
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_82_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_82_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_82_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_82_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_82_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_83_SHIFT                     _MK_SHIFT_CONST(19)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_83_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_83_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_83_RANGE                     19:19
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_83_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_83_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_83_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_83_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_83_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_84_SHIFT                     _MK_SHIFT_CONST(20)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_84_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_84_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_84_RANGE                     20:20
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_84_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_84_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_84_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_84_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_84_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_85_SHIFT                     _MK_SHIFT_CONST(21)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_85_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_85_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_85_RANGE                     21:21
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_85_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_85_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_85_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_85_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_85_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_86_SHIFT                     _MK_SHIFT_CONST(22)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_86_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_86_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_86_RANGE                     22:22
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_86_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_86_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_86_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_86_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_86_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_87_SHIFT                     _MK_SHIFT_CONST(23)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_87_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_87_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_87_RANGE                     23:23
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_87_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_87_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_87_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_87_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_87_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_88_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_88_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_88_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_88_RANGE                     24:24
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_88_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_88_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_88_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_88_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_88_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_89_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_89_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_89_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_89_RANGE                     25:25
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_89_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_89_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_89_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_89_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_89_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_90_SHIFT                     _MK_SHIFT_CONST(26)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_90_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_90_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_90_RANGE                     26:26
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_90_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_90_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_90_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_90_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_90_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_91_SHIFT                     _MK_SHIFT_CONST(27)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_91_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_91_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_91_RANGE                     27:27
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_91_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_91_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_91_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_91_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_91_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_92_SHIFT                     _MK_SHIFT_CONST(28)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_92_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_92_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_92_RANGE                     28:28
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_92_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_92_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_92_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_92_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_92_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_93_SHIFT                     _MK_SHIFT_CONST(29)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_93_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_93_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_93_RANGE                     29:29
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_93_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_93_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_93_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_93_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_93_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_94_SHIFT                     _MK_SHIFT_CONST(30)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_94_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_94_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_94_RANGE                     30:30
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_94_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_94_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_94_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_94_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_94_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_95_SHIFT                     _MK_SHIFT_CONST(31)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_95_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_95_SHIFT)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_95_RANGE                     31:31
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_95_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_95_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_95_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_95_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_3_0_EN_SET_SPI_95_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ENABLE_SET_4_0  
+#define FIC_DIST_ENABLE_SET_4_0                 _MK_ADDR_CONST(0x1110)
+#define FIC_DIST_ENABLE_SET_4_0_SECURE                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_WORD_COUNT                      0x1
+#define FIC_DIST_ENABLE_SET_4_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_96_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_96_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_96_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_96_RANGE                     0:0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_96_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_96_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_96_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_96_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_96_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_97_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_97_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_97_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_97_RANGE                     1:1
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_97_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_97_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_97_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_97_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_97_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_98_SHIFT                     _MK_SHIFT_CONST(2)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_98_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_98_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_98_RANGE                     2:2
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_98_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_98_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_98_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_98_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_98_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_99_SHIFT                     _MK_SHIFT_CONST(3)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_99_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_99_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_99_RANGE                     3:3
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_99_WOFFSET                   0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_99_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_99_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_99_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_99_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_100_SHIFT                    _MK_SHIFT_CONST(4)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_100_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_100_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_100_RANGE                    4:4
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_100_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_100_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_100_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_100_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_100_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_101_SHIFT                    _MK_SHIFT_CONST(5)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_101_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_101_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_101_RANGE                    5:5
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_101_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_101_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_101_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_101_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_101_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_102_SHIFT                    _MK_SHIFT_CONST(6)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_102_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_102_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_102_RANGE                    6:6
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_102_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_102_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_102_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_102_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_102_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_103_SHIFT                    _MK_SHIFT_CONST(7)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_103_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_103_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_103_RANGE                    7:7
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_103_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_103_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_103_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_103_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_103_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_104_SHIFT                    _MK_SHIFT_CONST(8)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_104_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_104_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_104_RANGE                    8:8
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_104_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_104_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_104_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_104_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_104_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_105_SHIFT                    _MK_SHIFT_CONST(9)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_105_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_105_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_105_RANGE                    9:9
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_105_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_105_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_105_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_105_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_105_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_106_SHIFT                    _MK_SHIFT_CONST(10)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_106_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_106_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_106_RANGE                    10:10
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_106_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_106_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_106_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_106_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_106_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_107_SHIFT                    _MK_SHIFT_CONST(11)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_107_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_107_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_107_RANGE                    11:11
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_107_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_107_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_107_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_107_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_107_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_108_SHIFT                    _MK_SHIFT_CONST(12)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_108_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_108_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_108_RANGE                    12:12
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_108_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_108_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_108_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_108_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_108_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_109_SHIFT                    _MK_SHIFT_CONST(13)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_109_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_109_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_109_RANGE                    13:13
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_109_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_109_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_109_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_109_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_109_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_110_SHIFT                    _MK_SHIFT_CONST(14)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_110_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_110_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_110_RANGE                    14:14
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_110_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_110_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_110_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_110_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_110_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_111_SHIFT                    _MK_SHIFT_CONST(15)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_111_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_111_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_111_RANGE                    15:15
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_111_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_111_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_111_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_111_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_111_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_112_SHIFT                    _MK_SHIFT_CONST(16)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_112_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_112_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_112_RANGE                    16:16
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_112_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_112_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_112_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_112_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_112_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_113_SHIFT                    _MK_SHIFT_CONST(17)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_113_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_113_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_113_RANGE                    17:17
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_113_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_113_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_113_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_113_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_113_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_114_SHIFT                    _MK_SHIFT_CONST(18)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_114_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_114_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_114_RANGE                    18:18
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_114_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_114_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_114_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_114_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_114_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_115_SHIFT                    _MK_SHIFT_CONST(19)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_115_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_115_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_115_RANGE                    19:19
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_115_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_115_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_115_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_115_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_115_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_116_SHIFT                    _MK_SHIFT_CONST(20)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_116_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_116_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_116_RANGE                    20:20
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_116_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_116_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_116_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_116_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_116_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_117_SHIFT                    _MK_SHIFT_CONST(21)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_117_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_117_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_117_RANGE                    21:21
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_117_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_117_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_117_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_117_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_117_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_118_SHIFT                    _MK_SHIFT_CONST(22)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_118_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_118_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_118_RANGE                    22:22
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_118_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_118_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_118_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_118_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_118_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_119_SHIFT                    _MK_SHIFT_CONST(23)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_119_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_119_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_119_RANGE                    23:23
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_119_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_119_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_119_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_119_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_119_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_120_SHIFT                    _MK_SHIFT_CONST(24)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_120_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_120_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_120_RANGE                    24:24
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_120_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_120_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_120_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_120_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_120_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_121_SHIFT                    _MK_SHIFT_CONST(25)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_121_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_121_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_121_RANGE                    25:25
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_121_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_121_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_121_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_121_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_121_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_122_SHIFT                    _MK_SHIFT_CONST(26)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_122_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_122_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_122_RANGE                    26:26
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_122_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_122_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_122_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_122_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_122_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_123_SHIFT                    _MK_SHIFT_CONST(27)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_123_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_123_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_123_RANGE                    27:27
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_123_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_123_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_123_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_123_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_123_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_124_SHIFT                    _MK_SHIFT_CONST(28)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_124_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_124_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_124_RANGE                    28:28
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_124_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_124_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_124_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_124_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_124_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_125_SHIFT                    _MK_SHIFT_CONST(29)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_125_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_125_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_125_RANGE                    29:29
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_125_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_125_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_125_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_125_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_125_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_126_SHIFT                    _MK_SHIFT_CONST(30)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_126_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_126_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_126_RANGE                    30:30
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_126_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_126_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_126_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_126_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_126_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_127_SHIFT                    _MK_SHIFT_CONST(31)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_127_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_127_SHIFT)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_127_RANGE                    31:31
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_127_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_127_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_127_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_127_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_SET_4_0_EN_SET_SPI_127_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 4372 [0x1114] 
+
+// Reserved address 4376 [0x1118] 
+
+// Reserved address 4380 [0x111c] 
+
+// Reserved address 4384 [0x1120] 
+
+// Reserved address 4388 [0x1124] 
+
+// Reserved address 4392 [0x1128] 
+
+// Reserved address 4396 [0x112c] 
+
+// Reserved address 4400 [0x1130] 
+
+// Reserved address 4404 [0x1134] 
+
+// Reserved address 4408 [0x1138] 
+
+// Reserved address 4412 [0x113c] 
+
+// Reserved address 4416 [0x1140] 
+
+// Reserved address 4420 [0x1144] 
+
+// Reserved address 4424 [0x1148] 
+
+// Reserved address 4428 [0x114c] 
+
+// Reserved address 4432 [0x1150] 
+
+// Reserved address 4436 [0x1154] 
+
+// Reserved address 4440 [0x1158] 
+
+// Reserved address 4444 [0x115c] 
+
+// Reserved address 4448 [0x1160] 
+
+// Reserved address 4452 [0x1164] 
+
+// Reserved address 4456 [0x1168] 
+
+// Reserved address 4460 [0x116c] 
+
+// Reserved address 4464 [0x1170] 
+
+// Reserved address 4468 [0x1174] 
+
+// Reserved address 4472 [0x1178] 
+
+// Reserved address 4476 [0x117c] 
+
+// Register FIC_DIST_ENABLE_CLEAR_0_0  
+#define FIC_DIST_ENABLE_CLEAR_0_0                       _MK_ADDR_CONST(0x1180)
+#define FIC_DIST_ENABLE_CLEAR_0_0_SECURE                        0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_WORD_COUNT                    0x1
+#define FIC_DIST_ENABLE_CLEAR_0_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_RESET_MASK                    _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_ENABLE_CLEAR_0_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_READ_MASK                     _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_ENABLE_CLEAR_0_0_WRITE_MASK                    _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_0_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_0_RANGE                    0:0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_0_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_1_SHIFT                    _MK_SHIFT_CONST(1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_1_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_1_RANGE                    1:1
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_1_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_2_SHIFT                    _MK_SHIFT_CONST(2)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_2_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_2_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_2_RANGE                    2:2
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_2_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_3_SHIFT                    _MK_SHIFT_CONST(3)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_3_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_3_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_3_RANGE                    3:3
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_3_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_4_SHIFT                    _MK_SHIFT_CONST(4)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_4_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_4_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_4_RANGE                    4:4
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_4_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_5_SHIFT                    _MK_SHIFT_CONST(5)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_5_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_5_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_5_RANGE                    5:5
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_5_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_6_SHIFT                    _MK_SHIFT_CONST(6)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_6_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_6_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_6_RANGE                    6:6
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_6_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_7_SHIFT                    _MK_SHIFT_CONST(7)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_7_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_7_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_7_RANGE                    7:7
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_7_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_8_SHIFT                    _MK_SHIFT_CONST(8)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_8_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_8_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_8_RANGE                    8:8
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_8_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_9_SHIFT                    _MK_SHIFT_CONST(9)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_9_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_9_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_9_RANGE                    9:9
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_9_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_10_SHIFT                   _MK_SHIFT_CONST(10)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_10_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_10_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_10_RANGE                   10:10
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_10_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_10_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_10_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_10_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_10_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_11_SHIFT                   _MK_SHIFT_CONST(11)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_11_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_11_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_11_RANGE                   11:11
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_11_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_11_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_11_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_11_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_11_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_12_SHIFT                   _MK_SHIFT_CONST(12)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_12_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_12_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_12_RANGE                   12:12
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_12_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_12_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_12_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_12_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_12_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_13_SHIFT                   _MK_SHIFT_CONST(13)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_13_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_13_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_13_RANGE                   13:13
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_13_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_13_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_13_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_13_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_13_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_14_SHIFT                   _MK_SHIFT_CONST(14)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_14_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_14_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_14_RANGE                   14:14
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_14_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_14_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_14_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_14_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_14_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_15_SHIFT                   _MK_SHIFT_CONST(15)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_15_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_15_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_15_RANGE                   15:15
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_15_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_15_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_15_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_15_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_STI_15_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_4_SHIFT                    _MK_SHIFT_CONST(27)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_4_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_4_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_4_RANGE                    27:27
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_4_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_0_SHIFT                    _MK_SHIFT_CONST(28)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_0_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_0_RANGE                    28:28
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_0_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_1_SHIFT                    _MK_SHIFT_CONST(29)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_1_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_1_RANGE                    29:29
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_1_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_2_SHIFT                    _MK_SHIFT_CONST(30)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_2_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_2_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_2_RANGE                    30:30
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_2_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_3_SHIFT                    _MK_SHIFT_CONST(31)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_3_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_3_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_3_RANGE                    31:31
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_3_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_0_0_EN_CLR_PPI_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ENABLE_CLEAR_1_0  
+#define FIC_DIST_ENABLE_CLEAR_1_0                       _MK_ADDR_CONST(0x1184)
+#define FIC_DIST_ENABLE_CLEAR_1_0_SECURE                        0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_WORD_COUNT                    0x1
+#define FIC_DIST_ENABLE_CLEAR_1_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_1_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_0_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_0_RANGE                    0:0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_0_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_1_SHIFT                    _MK_SHIFT_CONST(1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_1_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_1_RANGE                    1:1
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_1_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_2_SHIFT                    _MK_SHIFT_CONST(2)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_2_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_2_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_2_RANGE                    2:2
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_2_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_3_SHIFT                    _MK_SHIFT_CONST(3)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_3_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_3_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_3_RANGE                    3:3
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_3_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_4_SHIFT                    _MK_SHIFT_CONST(4)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_4_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_4_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_4_RANGE                    4:4
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_4_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_5_SHIFT                    _MK_SHIFT_CONST(5)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_5_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_5_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_5_RANGE                    5:5
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_5_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_6_SHIFT                    _MK_SHIFT_CONST(6)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_6_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_6_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_6_RANGE                    6:6
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_6_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_7_SHIFT                    _MK_SHIFT_CONST(7)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_7_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_7_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_7_RANGE                    7:7
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_7_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_8_SHIFT                    _MK_SHIFT_CONST(8)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_8_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_8_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_8_RANGE                    8:8
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_8_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_9_SHIFT                    _MK_SHIFT_CONST(9)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_9_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_9_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_9_RANGE                    9:9
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_9_WOFFSET                  0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_10_SHIFT                   _MK_SHIFT_CONST(10)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_10_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_10_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_10_RANGE                   10:10
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_10_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_10_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_10_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_10_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_10_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_11_SHIFT                   _MK_SHIFT_CONST(11)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_11_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_11_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_11_RANGE                   11:11
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_11_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_11_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_11_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_11_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_11_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_12_SHIFT                   _MK_SHIFT_CONST(12)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_12_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_12_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_12_RANGE                   12:12
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_12_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_12_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_12_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_12_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_12_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_13_SHIFT                   _MK_SHIFT_CONST(13)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_13_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_13_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_13_RANGE                   13:13
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_13_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_13_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_13_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_13_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_13_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_14_SHIFT                   _MK_SHIFT_CONST(14)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_14_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_14_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_14_RANGE                   14:14
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_14_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_14_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_14_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_14_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_14_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_15_SHIFT                   _MK_SHIFT_CONST(15)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_15_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_15_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_15_RANGE                   15:15
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_15_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_15_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_15_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_15_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_15_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_16_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_16_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_16_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_16_RANGE                   16:16
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_16_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_16_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_16_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_16_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_16_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_17_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_17_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_17_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_17_RANGE                   17:17
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_17_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_17_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_17_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_17_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_17_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_18_SHIFT                   _MK_SHIFT_CONST(18)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_18_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_18_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_18_RANGE                   18:18
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_18_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_18_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_18_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_18_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_18_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_19_SHIFT                   _MK_SHIFT_CONST(19)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_19_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_19_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_19_RANGE                   19:19
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_19_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_19_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_19_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_19_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_19_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_20_SHIFT                   _MK_SHIFT_CONST(20)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_20_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_20_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_20_RANGE                   20:20
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_20_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_20_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_20_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_20_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_20_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_21_SHIFT                   _MK_SHIFT_CONST(21)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_21_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_21_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_21_RANGE                   21:21
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_21_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_21_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_21_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_21_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_21_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_22_SHIFT                   _MK_SHIFT_CONST(22)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_22_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_22_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_22_RANGE                   22:22
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_22_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_22_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_22_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_22_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_22_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_23_SHIFT                   _MK_SHIFT_CONST(23)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_23_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_23_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_23_RANGE                   23:23
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_23_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_23_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_23_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_23_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_23_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_24_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_24_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_24_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_24_RANGE                   24:24
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_24_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_24_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_24_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_24_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_24_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_25_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_25_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_25_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_25_RANGE                   25:25
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_25_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_25_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_25_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_25_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_25_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_26_SHIFT                   _MK_SHIFT_CONST(26)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_26_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_26_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_26_RANGE                   26:26
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_26_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_26_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_26_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_26_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_26_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_27_SHIFT                   _MK_SHIFT_CONST(27)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_27_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_27_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_27_RANGE                   27:27
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_27_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_27_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_27_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_27_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_27_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_28_SHIFT                   _MK_SHIFT_CONST(28)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_28_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_28_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_28_RANGE                   28:28
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_28_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_28_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_28_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_28_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_28_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_29_SHIFT                   _MK_SHIFT_CONST(29)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_29_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_29_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_29_RANGE                   29:29
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_29_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_29_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_29_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_29_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_29_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_30_SHIFT                   _MK_SHIFT_CONST(30)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_30_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_30_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_30_RANGE                   30:30
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_30_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_30_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_30_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_30_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_30_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_31_SHIFT                   _MK_SHIFT_CONST(31)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_31_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_31_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_31_RANGE                   31:31
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_31_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_31_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_31_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_31_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_1_0_EN_CLR_SPI_31_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ENABLE_CLEAR_2_0  
+#define FIC_DIST_ENABLE_CLEAR_2_0                       _MK_ADDR_CONST(0x1188)
+#define FIC_DIST_ENABLE_CLEAR_2_0_SECURE                        0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_WORD_COUNT                    0x1
+#define FIC_DIST_ENABLE_CLEAR_2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_2_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_32_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_32_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_32_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_32_RANGE                   0:0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_32_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_32_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_32_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_32_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_32_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_33_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_33_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_33_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_33_RANGE                   1:1
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_33_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_33_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_33_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_33_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_33_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_34_SHIFT                   _MK_SHIFT_CONST(2)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_34_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_34_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_34_RANGE                   2:2
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_34_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_34_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_34_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_34_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_34_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_35_SHIFT                   _MK_SHIFT_CONST(3)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_35_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_35_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_35_RANGE                   3:3
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_35_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_35_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_35_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_35_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_35_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_36_SHIFT                   _MK_SHIFT_CONST(4)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_36_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_36_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_36_RANGE                   4:4
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_36_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_36_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_36_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_36_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_36_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_37_SHIFT                   _MK_SHIFT_CONST(5)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_37_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_37_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_37_RANGE                   5:5
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_37_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_37_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_37_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_37_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_37_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_38_SHIFT                   _MK_SHIFT_CONST(6)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_38_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_38_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_38_RANGE                   6:6
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_38_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_38_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_38_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_38_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_38_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_39_SHIFT                   _MK_SHIFT_CONST(7)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_39_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_39_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_39_RANGE                   7:7
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_39_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_39_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_39_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_39_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_39_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_40_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_40_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_40_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_40_RANGE                   8:8
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_40_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_40_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_40_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_40_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_40_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_41_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_41_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_41_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_41_RANGE                   9:9
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_41_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_41_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_41_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_41_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_41_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_42_SHIFT                   _MK_SHIFT_CONST(10)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_42_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_42_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_42_RANGE                   10:10
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_42_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_42_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_42_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_42_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_42_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_43_SHIFT                   _MK_SHIFT_CONST(11)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_43_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_43_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_43_RANGE                   11:11
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_43_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_43_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_43_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_43_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_43_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_44_SHIFT                   _MK_SHIFT_CONST(12)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_44_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_44_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_44_RANGE                   12:12
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_44_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_44_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_44_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_44_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_44_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_45_SHIFT                   _MK_SHIFT_CONST(13)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_45_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_45_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_45_RANGE                   13:13
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_45_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_45_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_45_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_45_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_45_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_46_SHIFT                   _MK_SHIFT_CONST(14)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_46_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_46_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_46_RANGE                   14:14
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_46_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_46_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_46_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_46_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_46_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_47_SHIFT                   _MK_SHIFT_CONST(15)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_47_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_47_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_47_RANGE                   15:15
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_47_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_47_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_47_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_47_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_47_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_48_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_48_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_48_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_48_RANGE                   16:16
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_48_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_48_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_48_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_48_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_48_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_49_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_49_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_49_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_49_RANGE                   17:17
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_49_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_49_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_49_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_49_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_49_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_50_SHIFT                   _MK_SHIFT_CONST(18)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_50_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_50_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_50_RANGE                   18:18
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_50_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_50_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_50_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_50_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_50_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_51_SHIFT                   _MK_SHIFT_CONST(19)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_51_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_51_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_51_RANGE                   19:19
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_51_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_51_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_51_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_51_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_51_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_52_SHIFT                   _MK_SHIFT_CONST(20)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_52_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_52_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_52_RANGE                   20:20
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_52_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_52_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_52_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_52_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_52_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_53_SHIFT                   _MK_SHIFT_CONST(21)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_53_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_53_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_53_RANGE                   21:21
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_53_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_53_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_53_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_53_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_53_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_54_SHIFT                   _MK_SHIFT_CONST(22)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_54_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_54_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_54_RANGE                   22:22
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_54_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_54_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_54_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_54_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_54_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_55_SHIFT                   _MK_SHIFT_CONST(23)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_55_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_55_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_55_RANGE                   23:23
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_55_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_55_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_55_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_55_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_55_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_56_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_56_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_56_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_56_RANGE                   24:24
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_56_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_56_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_56_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_56_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_56_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_57_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_57_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_57_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_57_RANGE                   25:25
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_57_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_57_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_57_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_57_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_57_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_58_SHIFT                   _MK_SHIFT_CONST(26)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_58_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_58_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_58_RANGE                   26:26
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_58_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_58_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_58_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_58_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_58_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_59_SHIFT                   _MK_SHIFT_CONST(27)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_59_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_59_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_59_RANGE                   27:27
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_59_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_59_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_59_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_59_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_59_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_60_SHIFT                   _MK_SHIFT_CONST(28)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_60_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_60_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_60_RANGE                   28:28
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_60_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_60_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_60_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_60_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_60_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_61_SHIFT                   _MK_SHIFT_CONST(29)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_61_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_61_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_61_RANGE                   29:29
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_61_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_61_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_61_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_61_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_61_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_62_SHIFT                   _MK_SHIFT_CONST(30)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_62_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_62_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_62_RANGE                   30:30
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_62_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_62_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_62_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_62_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_62_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_63_SHIFT                   _MK_SHIFT_CONST(31)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_63_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_63_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_63_RANGE                   31:31
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_63_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_63_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_63_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_63_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_2_0_EN_CLR_SPI_63_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ENABLE_CLEAR_3_0  
+#define FIC_DIST_ENABLE_CLEAR_3_0                       _MK_ADDR_CONST(0x118c)
+#define FIC_DIST_ENABLE_CLEAR_3_0_SECURE                        0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_WORD_COUNT                    0x1
+#define FIC_DIST_ENABLE_CLEAR_3_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_3_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_3_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_64_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_64_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_64_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_64_RANGE                   0:0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_64_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_64_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_64_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_64_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_64_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_65_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_65_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_65_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_65_RANGE                   1:1
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_65_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_65_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_65_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_65_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_65_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_66_SHIFT                   _MK_SHIFT_CONST(2)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_66_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_66_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_66_RANGE                   2:2
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_66_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_66_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_66_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_66_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_66_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_67_SHIFT                   _MK_SHIFT_CONST(3)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_67_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_67_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_67_RANGE                   3:3
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_67_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_67_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_67_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_67_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_67_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_68_SHIFT                   _MK_SHIFT_CONST(4)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_68_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_68_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_68_RANGE                   4:4
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_68_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_68_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_68_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_68_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_68_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_69_SHIFT                   _MK_SHIFT_CONST(5)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_69_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_69_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_69_RANGE                   5:5
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_69_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_69_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_69_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_69_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_69_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_70_SHIFT                   _MK_SHIFT_CONST(6)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_70_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_70_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_70_RANGE                   6:6
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_70_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_70_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_70_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_70_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_70_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_71_SHIFT                   _MK_SHIFT_CONST(7)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_71_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_71_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_71_RANGE                   7:7
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_71_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_71_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_71_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_71_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_71_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_72_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_72_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_72_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_72_RANGE                   8:8
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_72_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_72_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_72_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_72_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_72_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_73_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_73_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_73_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_73_RANGE                   9:9
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_73_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_73_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_73_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_73_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_73_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_74_SHIFT                   _MK_SHIFT_CONST(10)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_74_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_74_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_74_RANGE                   10:10
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_74_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_74_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_74_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_74_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_74_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_75_SHIFT                   _MK_SHIFT_CONST(11)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_75_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_75_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_75_RANGE                   11:11
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_75_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_75_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_75_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_75_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_75_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_76_SHIFT                   _MK_SHIFT_CONST(12)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_76_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_76_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_76_RANGE                   12:12
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_76_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_76_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_76_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_76_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_76_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_77_SHIFT                   _MK_SHIFT_CONST(13)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_77_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_77_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_77_RANGE                   13:13
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_77_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_77_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_77_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_77_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_77_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_78_SHIFT                   _MK_SHIFT_CONST(14)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_78_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_78_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_78_RANGE                   14:14
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_78_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_78_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_78_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_78_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_78_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_79_SHIFT                   _MK_SHIFT_CONST(15)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_79_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_79_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_79_RANGE                   15:15
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_79_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_79_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_79_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_79_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_79_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_80_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_80_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_80_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_80_RANGE                   16:16
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_80_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_80_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_80_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_80_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_80_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_81_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_81_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_81_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_81_RANGE                   17:17
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_81_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_81_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_81_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_81_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_81_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_82_SHIFT                   _MK_SHIFT_CONST(18)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_82_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_82_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_82_RANGE                   18:18
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_82_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_82_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_82_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_82_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_82_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_83_SHIFT                   _MK_SHIFT_CONST(19)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_83_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_83_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_83_RANGE                   19:19
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_83_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_83_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_83_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_83_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_83_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_84_SHIFT                   _MK_SHIFT_CONST(20)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_84_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_84_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_84_RANGE                   20:20
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_84_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_84_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_84_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_84_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_84_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_85_SHIFT                   _MK_SHIFT_CONST(21)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_85_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_85_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_85_RANGE                   21:21
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_85_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_85_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_85_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_85_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_85_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_86_SHIFT                   _MK_SHIFT_CONST(22)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_86_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_86_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_86_RANGE                   22:22
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_86_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_86_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_86_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_86_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_86_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_87_SHIFT                   _MK_SHIFT_CONST(23)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_87_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_87_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_87_RANGE                   23:23
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_87_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_87_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_87_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_87_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_87_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_88_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_88_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_88_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_88_RANGE                   24:24
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_88_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_88_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_88_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_88_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_88_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_89_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_89_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_89_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_89_RANGE                   25:25
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_89_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_89_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_89_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_89_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_89_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_90_SHIFT                   _MK_SHIFT_CONST(26)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_90_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_90_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_90_RANGE                   26:26
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_90_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_90_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_90_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_90_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_90_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_91_SHIFT                   _MK_SHIFT_CONST(27)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_91_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_91_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_91_RANGE                   27:27
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_91_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_91_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_91_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_91_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_91_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_92_SHIFT                   _MK_SHIFT_CONST(28)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_92_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_92_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_92_RANGE                   28:28
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_92_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_92_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_92_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_92_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_92_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_93_SHIFT                   _MK_SHIFT_CONST(29)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_93_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_93_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_93_RANGE                   29:29
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_93_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_93_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_93_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_93_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_93_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_94_SHIFT                   _MK_SHIFT_CONST(30)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_94_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_94_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_94_RANGE                   30:30
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_94_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_94_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_94_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_94_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_94_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_95_SHIFT                   _MK_SHIFT_CONST(31)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_95_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_95_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_95_RANGE                   31:31
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_95_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_95_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_95_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_95_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_3_0_EN_CLR_SPI_95_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ENABLE_CLEAR_4_0  
+#define FIC_DIST_ENABLE_CLEAR_4_0                       _MK_ADDR_CONST(0x1190)
+#define FIC_DIST_ENABLE_CLEAR_4_0_SECURE                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_WORD_COUNT                    0x1
+#define FIC_DIST_ENABLE_CLEAR_4_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_4_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_4_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_96_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_96_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_96_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_96_RANGE                   0:0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_96_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_96_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_96_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_96_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_96_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_97_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_97_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_97_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_97_RANGE                   1:1
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_97_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_97_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_97_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_97_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_97_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_98_SHIFT                   _MK_SHIFT_CONST(2)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_98_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_98_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_98_RANGE                   2:2
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_98_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_98_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_98_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_98_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_98_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_99_SHIFT                   _MK_SHIFT_CONST(3)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_99_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_99_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_99_RANGE                   3:3
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_99_WOFFSET                 0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_99_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_99_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_99_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_99_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_100_SHIFT                  _MK_SHIFT_CONST(4)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_100_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_100_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_100_RANGE                  4:4
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_100_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_100_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_100_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_100_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_100_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_101_SHIFT                  _MK_SHIFT_CONST(5)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_101_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_101_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_101_RANGE                  5:5
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_101_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_101_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_101_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_101_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_101_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_102_SHIFT                  _MK_SHIFT_CONST(6)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_102_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_102_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_102_RANGE                  6:6
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_102_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_102_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_102_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_102_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_102_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_103_SHIFT                  _MK_SHIFT_CONST(7)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_103_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_103_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_103_RANGE                  7:7
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_103_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_103_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_103_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_103_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_103_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_104_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_104_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_104_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_104_RANGE                  8:8
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_104_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_104_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_104_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_104_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_104_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_105_SHIFT                  _MK_SHIFT_CONST(9)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_105_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_105_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_105_RANGE                  9:9
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_105_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_105_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_105_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_105_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_105_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_106_SHIFT                  _MK_SHIFT_CONST(10)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_106_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_106_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_106_RANGE                  10:10
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_106_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_106_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_106_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_106_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_106_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_107_SHIFT                  _MK_SHIFT_CONST(11)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_107_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_107_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_107_RANGE                  11:11
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_107_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_107_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_107_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_107_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_107_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_108_SHIFT                  _MK_SHIFT_CONST(12)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_108_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_108_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_108_RANGE                  12:12
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_108_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_108_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_108_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_108_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_108_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_109_SHIFT                  _MK_SHIFT_CONST(13)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_109_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_109_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_109_RANGE                  13:13
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_109_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_109_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_109_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_109_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_109_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_110_SHIFT                  _MK_SHIFT_CONST(14)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_110_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_110_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_110_RANGE                  14:14
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_110_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_110_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_110_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_110_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_110_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_111_SHIFT                  _MK_SHIFT_CONST(15)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_111_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_111_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_111_RANGE                  15:15
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_111_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_111_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_111_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_111_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_111_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_112_SHIFT                  _MK_SHIFT_CONST(16)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_112_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_112_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_112_RANGE                  16:16
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_112_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_112_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_112_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_112_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_112_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_113_SHIFT                  _MK_SHIFT_CONST(17)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_113_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_113_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_113_RANGE                  17:17
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_113_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_113_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_113_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_113_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_113_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_114_SHIFT                  _MK_SHIFT_CONST(18)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_114_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_114_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_114_RANGE                  18:18
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_114_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_114_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_114_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_114_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_114_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_115_SHIFT                  _MK_SHIFT_CONST(19)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_115_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_115_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_115_RANGE                  19:19
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_115_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_115_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_115_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_115_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_115_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_116_SHIFT                  _MK_SHIFT_CONST(20)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_116_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_116_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_116_RANGE                  20:20
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_116_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_116_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_116_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_116_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_116_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_117_SHIFT                  _MK_SHIFT_CONST(21)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_117_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_117_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_117_RANGE                  21:21
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_117_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_117_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_117_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_117_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_117_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_118_SHIFT                  _MK_SHIFT_CONST(22)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_118_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_118_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_118_RANGE                  22:22
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_118_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_118_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_118_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_118_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_118_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_119_SHIFT                  _MK_SHIFT_CONST(23)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_119_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_119_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_119_RANGE                  23:23
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_119_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_119_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_119_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_119_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_119_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_120_SHIFT                  _MK_SHIFT_CONST(24)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_120_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_120_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_120_RANGE                  24:24
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_120_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_120_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_120_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_120_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_120_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_121_SHIFT                  _MK_SHIFT_CONST(25)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_121_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_121_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_121_RANGE                  25:25
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_121_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_121_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_121_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_121_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_121_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_122_SHIFT                  _MK_SHIFT_CONST(26)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_122_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_122_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_122_RANGE                  26:26
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_122_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_122_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_122_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_122_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_122_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_123_SHIFT                  _MK_SHIFT_CONST(27)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_123_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_123_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_123_RANGE                  27:27
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_123_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_123_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_123_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_123_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_123_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_124_SHIFT                  _MK_SHIFT_CONST(28)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_124_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_124_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_124_RANGE                  28:28
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_124_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_124_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_124_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_124_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_124_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_125_SHIFT                  _MK_SHIFT_CONST(29)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_125_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_125_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_125_RANGE                  29:29
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_125_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_125_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_125_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_125_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_125_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_126_SHIFT                  _MK_SHIFT_CONST(30)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_126_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_126_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_126_RANGE                  30:30
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_126_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_126_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_126_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_126_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_126_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_127_SHIFT                  _MK_SHIFT_CONST(31)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_127_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_127_SHIFT)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_127_RANGE                  31:31
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_127_WOFFSET                        0x0
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_127_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_127_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_127_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ENABLE_CLEAR_4_0_EN_CLR_SPI_127_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 4500 [0x1194] 
+
+// Reserved address 4504 [0x1198] 
+
+// Reserved address 4508 [0x119c] 
+
+// Reserved address 4512 [0x11a0] 
+
+// Reserved address 4516 [0x11a4] 
+
+// Reserved address 4520 [0x11a8] 
+
+// Reserved address 4524 [0x11ac] 
+
+// Reserved address 4528 [0x11b0] 
+
+// Reserved address 4532 [0x11b4] 
+
+// Reserved address 4536 [0x11b8] 
+
+// Reserved address 4540 [0x11bc] 
+
+// Reserved address 4544 [0x11c0] 
+
+// Reserved address 4548 [0x11c4] 
+
+// Reserved address 4552 [0x11c8] 
+
+// Reserved address 4556 [0x11cc] 
+
+// Reserved address 4560 [0x11d0] 
+
+// Reserved address 4564 [0x11d4] 
+
+// Reserved address 4568 [0x11d8] 
+
+// Reserved address 4572 [0x11dc] 
+
+// Reserved address 4576 [0x11e0] 
+
+// Reserved address 4580 [0x11e4] 
+
+// Reserved address 4584 [0x11e8] 
+
+// Reserved address 4588 [0x11ec] 
+
+// Reserved address 4592 [0x11f0] 
+
+// Reserved address 4596 [0x11f4] 
+
+// Reserved address 4600 [0x11f8] 
+
+// Reserved address 4604 [0x11fc] 
+
+// Register FIC_DIST_PENDING_SET_0_0  
+#define FIC_DIST_PENDING_SET_0_0                        _MK_ADDR_CONST(0x1200)
+#define FIC_DIST_PENDING_SET_0_0_SECURE                         0x0
+#define FIC_DIST_PENDING_SET_0_0_WORD_COUNT                     0x1
+#define FIC_DIST_PENDING_SET_0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_RESET_MASK                     _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_PENDING_SET_0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_READ_MASK                      _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_PENDING_SET_0_0_WRITE_MASK                     _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_0_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_0_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_0_RANGE                        0:0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_0_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_1_SHIFT                        _MK_SHIFT_CONST(1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_1_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_1_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_1_RANGE                        1:1
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_1_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_2_SHIFT                        _MK_SHIFT_CONST(2)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_2_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_2_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_2_RANGE                        2:2
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_2_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_3_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_3_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_3_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_3_RANGE                        3:3
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_3_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_4_SHIFT                        _MK_SHIFT_CONST(4)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_4_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_4_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_4_RANGE                        4:4
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_4_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_5_SHIFT                        _MK_SHIFT_CONST(5)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_5_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_5_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_5_RANGE                        5:5
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_5_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_6_SHIFT                        _MK_SHIFT_CONST(6)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_6_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_6_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_6_RANGE                        6:6
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_6_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_7_SHIFT                        _MK_SHIFT_CONST(7)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_7_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_7_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_7_RANGE                        7:7
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_7_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_8_SHIFT                        _MK_SHIFT_CONST(8)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_8_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_8_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_8_RANGE                        8:8
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_8_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_9_SHIFT                        _MK_SHIFT_CONST(9)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_9_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_9_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_9_RANGE                        9:9
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_9_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_10_SHIFT                       _MK_SHIFT_CONST(10)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_10_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_10_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_10_RANGE                       10:10
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_10_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_11_SHIFT                       _MK_SHIFT_CONST(11)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_11_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_11_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_11_RANGE                       11:11
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_11_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_12_SHIFT                       _MK_SHIFT_CONST(12)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_12_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_12_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_12_RANGE                       12:12
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_12_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_13_SHIFT                       _MK_SHIFT_CONST(13)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_13_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_13_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_13_RANGE                       13:13
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_13_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_14_SHIFT                       _MK_SHIFT_CONST(14)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_14_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_14_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_14_RANGE                       14:14
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_14_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_15_SHIFT                       _MK_SHIFT_CONST(15)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_15_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_15_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_15_RANGE                       15:15
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_15_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_STI_15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_4_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_4_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_4_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_4_RANGE                        27:27
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_4_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_0_SHIFT                        _MK_SHIFT_CONST(28)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_0_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_0_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_0_RANGE                        28:28
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_0_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_1_SHIFT                        _MK_SHIFT_CONST(29)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_1_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_1_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_1_RANGE                        29:29
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_1_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_2_SHIFT                        _MK_SHIFT_CONST(30)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_2_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_2_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_2_RANGE                        30:30
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_2_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_3_SHIFT                        _MK_SHIFT_CONST(31)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_3_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_3_SHIFT)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_3_RANGE                        31:31
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_3_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_0_0_PENDING_SET_PPI_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PENDING_SET_1_0  
+#define FIC_DIST_PENDING_SET_1_0                        _MK_ADDR_CONST(0x1204)
+#define FIC_DIST_PENDING_SET_1_0_SECURE                         0x0
+#define FIC_DIST_PENDING_SET_1_0_WORD_COUNT                     0x1
+#define FIC_DIST_PENDING_SET_1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_1_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_0_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_0_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_0_RANGE                        0:0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_0_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_1_SHIFT                        _MK_SHIFT_CONST(1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_1_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_1_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_1_RANGE                        1:1
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_1_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_2_SHIFT                        _MK_SHIFT_CONST(2)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_2_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_2_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_2_RANGE                        2:2
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_2_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_3_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_3_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_3_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_3_RANGE                        3:3
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_3_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_4_SHIFT                        _MK_SHIFT_CONST(4)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_4_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_4_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_4_RANGE                        4:4
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_4_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_5_SHIFT                        _MK_SHIFT_CONST(5)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_5_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_5_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_5_RANGE                        5:5
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_5_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_6_SHIFT                        _MK_SHIFT_CONST(6)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_6_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_6_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_6_RANGE                        6:6
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_6_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_7_SHIFT                        _MK_SHIFT_CONST(7)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_7_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_7_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_7_RANGE                        7:7
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_7_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_8_SHIFT                        _MK_SHIFT_CONST(8)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_8_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_8_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_8_RANGE                        8:8
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_8_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_9_SHIFT                        _MK_SHIFT_CONST(9)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_9_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_9_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_9_RANGE                        9:9
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_9_WOFFSET                      0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_10_SHIFT                       _MK_SHIFT_CONST(10)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_10_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_10_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_10_RANGE                       10:10
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_10_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_11_SHIFT                       _MK_SHIFT_CONST(11)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_11_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_11_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_11_RANGE                       11:11
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_11_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_12_SHIFT                       _MK_SHIFT_CONST(12)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_12_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_12_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_12_RANGE                       12:12
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_12_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_13_SHIFT                       _MK_SHIFT_CONST(13)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_13_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_13_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_13_RANGE                       13:13
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_13_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_14_SHIFT                       _MK_SHIFT_CONST(14)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_14_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_14_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_14_RANGE                       14:14
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_14_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_15_SHIFT                       _MK_SHIFT_CONST(15)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_15_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_15_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_15_RANGE                       15:15
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_15_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_16_SHIFT                       _MK_SHIFT_CONST(16)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_16_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_16_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_16_RANGE                       16:16
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_16_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_16_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_16_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_16_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_16_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_17_SHIFT                       _MK_SHIFT_CONST(17)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_17_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_17_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_17_RANGE                       17:17
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_17_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_17_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_17_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_17_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_17_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_18_SHIFT                       _MK_SHIFT_CONST(18)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_18_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_18_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_18_RANGE                       18:18
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_18_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_18_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_18_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_18_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_18_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_19_SHIFT                       _MK_SHIFT_CONST(19)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_19_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_19_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_19_RANGE                       19:19
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_19_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_19_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_19_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_19_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_19_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_20_SHIFT                       _MK_SHIFT_CONST(20)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_20_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_20_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_20_RANGE                       20:20
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_20_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_20_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_20_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_20_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_20_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_21_SHIFT                       _MK_SHIFT_CONST(21)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_21_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_21_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_21_RANGE                       21:21
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_21_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_21_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_21_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_21_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_21_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_22_SHIFT                       _MK_SHIFT_CONST(22)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_22_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_22_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_22_RANGE                       22:22
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_22_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_22_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_22_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_22_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_22_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_23_SHIFT                       _MK_SHIFT_CONST(23)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_23_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_23_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_23_RANGE                       23:23
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_23_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_23_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_23_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_23_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_23_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_24_SHIFT                       _MK_SHIFT_CONST(24)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_24_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_24_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_24_RANGE                       24:24
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_24_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_24_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_24_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_24_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_24_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_25_SHIFT                       _MK_SHIFT_CONST(25)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_25_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_25_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_25_RANGE                       25:25
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_25_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_25_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_25_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_25_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_25_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_26_SHIFT                       _MK_SHIFT_CONST(26)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_26_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_26_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_26_RANGE                       26:26
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_26_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_26_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_26_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_26_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_26_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_27_SHIFT                       _MK_SHIFT_CONST(27)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_27_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_27_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_27_RANGE                       27:27
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_27_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_27_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_27_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_27_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_27_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_28_SHIFT                       _MK_SHIFT_CONST(28)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_28_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_28_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_28_RANGE                       28:28
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_28_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_28_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_28_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_28_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_28_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_29_SHIFT                       _MK_SHIFT_CONST(29)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_29_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_29_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_29_RANGE                       29:29
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_29_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_29_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_29_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_29_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_29_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_30_SHIFT                       _MK_SHIFT_CONST(30)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_30_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_30_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_30_RANGE                       30:30
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_30_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_30_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_30_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_30_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_30_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_31_SHIFT                       _MK_SHIFT_CONST(31)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_31_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_31_SHIFT)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_31_RANGE                       31:31
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_31_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_31_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_31_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_31_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_1_0_PENDING_SET_SPI_31_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PENDING_SET_2_0  
+#define FIC_DIST_PENDING_SET_2_0                        _MK_ADDR_CONST(0x1208)
+#define FIC_DIST_PENDING_SET_2_0_SECURE                         0x0
+#define FIC_DIST_PENDING_SET_2_0_WORD_COUNT                     0x1
+#define FIC_DIST_PENDING_SET_2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_2_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_32_SHIFT                       _MK_SHIFT_CONST(0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_32_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_32_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_32_RANGE                       0:0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_32_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_32_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_32_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_32_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_32_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_33_SHIFT                       _MK_SHIFT_CONST(1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_33_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_33_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_33_RANGE                       1:1
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_33_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_33_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_33_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_33_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_33_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_34_SHIFT                       _MK_SHIFT_CONST(2)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_34_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_34_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_34_RANGE                       2:2
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_34_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_34_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_34_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_34_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_34_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_35_SHIFT                       _MK_SHIFT_CONST(3)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_35_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_35_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_35_RANGE                       3:3
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_35_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_35_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_35_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_35_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_35_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_36_SHIFT                       _MK_SHIFT_CONST(4)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_36_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_36_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_36_RANGE                       4:4
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_36_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_36_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_36_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_36_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_36_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_37_SHIFT                       _MK_SHIFT_CONST(5)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_37_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_37_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_37_RANGE                       5:5
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_37_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_37_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_37_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_37_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_37_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_38_SHIFT                       _MK_SHIFT_CONST(6)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_38_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_38_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_38_RANGE                       6:6
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_38_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_38_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_38_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_38_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_38_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_39_SHIFT                       _MK_SHIFT_CONST(7)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_39_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_39_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_39_RANGE                       7:7
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_39_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_39_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_39_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_39_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_39_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_40_SHIFT                       _MK_SHIFT_CONST(8)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_40_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_40_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_40_RANGE                       8:8
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_40_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_40_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_40_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_40_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_40_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_41_SHIFT                       _MK_SHIFT_CONST(9)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_41_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_41_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_41_RANGE                       9:9
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_41_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_41_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_41_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_41_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_41_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_42_SHIFT                       _MK_SHIFT_CONST(10)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_42_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_42_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_42_RANGE                       10:10
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_42_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_42_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_42_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_42_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_42_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_43_SHIFT                       _MK_SHIFT_CONST(11)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_43_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_43_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_43_RANGE                       11:11
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_43_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_43_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_43_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_43_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_43_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_44_SHIFT                       _MK_SHIFT_CONST(12)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_44_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_44_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_44_RANGE                       12:12
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_44_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_44_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_44_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_44_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_44_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_45_SHIFT                       _MK_SHIFT_CONST(13)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_45_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_45_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_45_RANGE                       13:13
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_45_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_45_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_45_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_45_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_45_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_46_SHIFT                       _MK_SHIFT_CONST(14)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_46_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_46_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_46_RANGE                       14:14
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_46_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_46_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_46_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_46_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_46_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_47_SHIFT                       _MK_SHIFT_CONST(15)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_47_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_47_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_47_RANGE                       15:15
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_47_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_47_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_47_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_47_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_47_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_48_SHIFT                       _MK_SHIFT_CONST(16)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_48_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_48_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_48_RANGE                       16:16
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_48_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_48_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_48_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_48_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_48_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_49_SHIFT                       _MK_SHIFT_CONST(17)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_49_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_49_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_49_RANGE                       17:17
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_49_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_49_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_49_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_49_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_49_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_50_SHIFT                       _MK_SHIFT_CONST(18)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_50_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_50_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_50_RANGE                       18:18
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_50_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_50_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_50_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_50_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_50_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_51_SHIFT                       _MK_SHIFT_CONST(19)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_51_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_51_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_51_RANGE                       19:19
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_51_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_51_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_51_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_51_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_51_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_52_SHIFT                       _MK_SHIFT_CONST(20)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_52_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_52_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_52_RANGE                       20:20
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_52_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_52_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_52_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_52_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_52_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_53_SHIFT                       _MK_SHIFT_CONST(21)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_53_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_53_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_53_RANGE                       21:21
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_53_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_53_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_53_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_53_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_53_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_54_SHIFT                       _MK_SHIFT_CONST(22)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_54_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_54_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_54_RANGE                       22:22
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_54_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_54_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_54_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_54_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_54_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_55_SHIFT                       _MK_SHIFT_CONST(23)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_55_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_55_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_55_RANGE                       23:23
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_55_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_55_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_55_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_55_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_55_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_56_SHIFT                       _MK_SHIFT_CONST(24)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_56_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_56_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_56_RANGE                       24:24
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_56_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_56_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_56_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_56_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_56_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_57_SHIFT                       _MK_SHIFT_CONST(25)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_57_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_57_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_57_RANGE                       25:25
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_57_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_57_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_57_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_57_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_57_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_58_SHIFT                       _MK_SHIFT_CONST(26)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_58_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_58_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_58_RANGE                       26:26
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_58_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_58_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_58_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_58_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_58_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_59_SHIFT                       _MK_SHIFT_CONST(27)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_59_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_59_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_59_RANGE                       27:27
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_59_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_59_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_59_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_59_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_59_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_60_SHIFT                       _MK_SHIFT_CONST(28)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_60_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_60_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_60_RANGE                       28:28
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_60_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_60_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_60_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_60_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_60_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_61_SHIFT                       _MK_SHIFT_CONST(29)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_61_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_61_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_61_RANGE                       29:29
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_61_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_61_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_61_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_61_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_61_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_62_SHIFT                       _MK_SHIFT_CONST(30)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_62_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_62_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_62_RANGE                       30:30
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_62_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_62_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_62_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_62_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_62_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_63_SHIFT                       _MK_SHIFT_CONST(31)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_63_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_63_SHIFT)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_63_RANGE                       31:31
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_63_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_63_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_63_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_63_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_2_0_PENDING_SET_SPI_63_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PENDING_SET_3_0  
+#define FIC_DIST_PENDING_SET_3_0                        _MK_ADDR_CONST(0x120c)
+#define FIC_DIST_PENDING_SET_3_0_SECURE                         0x0
+#define FIC_DIST_PENDING_SET_3_0_WORD_COUNT                     0x1
+#define FIC_DIST_PENDING_SET_3_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_3_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_64_SHIFT                       _MK_SHIFT_CONST(0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_64_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_64_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_64_RANGE                       0:0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_64_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_64_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_64_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_64_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_64_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_65_SHIFT                       _MK_SHIFT_CONST(1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_65_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_65_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_65_RANGE                       1:1
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_65_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_65_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_65_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_65_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_65_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_66_SHIFT                       _MK_SHIFT_CONST(2)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_66_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_66_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_66_RANGE                       2:2
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_66_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_66_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_66_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_66_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_66_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_67_SHIFT                       _MK_SHIFT_CONST(3)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_67_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_67_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_67_RANGE                       3:3
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_67_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_67_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_67_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_67_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_67_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_68_SHIFT                       _MK_SHIFT_CONST(4)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_68_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_68_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_68_RANGE                       4:4
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_68_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_68_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_68_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_68_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_68_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_69_SHIFT                       _MK_SHIFT_CONST(5)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_69_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_69_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_69_RANGE                       5:5
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_69_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_69_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_69_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_69_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_69_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_70_SHIFT                       _MK_SHIFT_CONST(6)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_70_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_70_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_70_RANGE                       6:6
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_70_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_70_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_70_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_70_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_70_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_71_SHIFT                       _MK_SHIFT_CONST(7)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_71_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_71_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_71_RANGE                       7:7
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_71_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_71_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_71_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_71_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_71_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_72_SHIFT                       _MK_SHIFT_CONST(8)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_72_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_72_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_72_RANGE                       8:8
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_72_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_72_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_72_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_72_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_72_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_73_SHIFT                       _MK_SHIFT_CONST(9)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_73_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_73_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_73_RANGE                       9:9
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_73_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_73_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_73_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_73_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_73_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_74_SHIFT                       _MK_SHIFT_CONST(10)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_74_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_74_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_74_RANGE                       10:10
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_74_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_74_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_74_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_74_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_74_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_75_SHIFT                       _MK_SHIFT_CONST(11)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_75_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_75_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_75_RANGE                       11:11
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_75_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_75_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_75_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_75_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_75_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_76_SHIFT                       _MK_SHIFT_CONST(12)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_76_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_76_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_76_RANGE                       12:12
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_76_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_76_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_76_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_76_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_76_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_77_SHIFT                       _MK_SHIFT_CONST(13)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_77_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_77_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_77_RANGE                       13:13
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_77_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_77_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_77_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_77_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_77_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_78_SHIFT                       _MK_SHIFT_CONST(14)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_78_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_78_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_78_RANGE                       14:14
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_78_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_78_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_78_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_78_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_78_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_79_SHIFT                       _MK_SHIFT_CONST(15)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_79_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_79_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_79_RANGE                       15:15
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_79_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_79_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_79_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_79_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_79_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_80_SHIFT                       _MK_SHIFT_CONST(16)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_80_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_80_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_80_RANGE                       16:16
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_80_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_80_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_80_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_80_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_80_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_81_SHIFT                       _MK_SHIFT_CONST(17)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_81_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_81_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_81_RANGE                       17:17
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_81_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_81_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_81_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_81_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_81_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_82_SHIFT                       _MK_SHIFT_CONST(18)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_82_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_82_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_82_RANGE                       18:18
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_82_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_82_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_82_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_82_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_82_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_83_SHIFT                       _MK_SHIFT_CONST(19)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_83_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_83_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_83_RANGE                       19:19
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_83_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_83_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_83_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_83_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_83_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_84_SHIFT                       _MK_SHIFT_CONST(20)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_84_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_84_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_84_RANGE                       20:20
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_84_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_84_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_84_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_84_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_84_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_85_SHIFT                       _MK_SHIFT_CONST(21)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_85_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_85_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_85_RANGE                       21:21
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_85_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_85_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_85_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_85_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_85_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_86_SHIFT                       _MK_SHIFT_CONST(22)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_86_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_86_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_86_RANGE                       22:22
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_86_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_86_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_86_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_86_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_86_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_87_SHIFT                       _MK_SHIFT_CONST(23)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_87_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_87_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_87_RANGE                       23:23
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_87_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_87_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_87_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_87_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_87_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_88_SHIFT                       _MK_SHIFT_CONST(24)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_88_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_88_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_88_RANGE                       24:24
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_88_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_88_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_88_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_88_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_88_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_89_SHIFT                       _MK_SHIFT_CONST(25)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_89_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_89_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_89_RANGE                       25:25
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_89_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_89_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_89_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_89_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_89_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_90_SHIFT                       _MK_SHIFT_CONST(26)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_90_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_90_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_90_RANGE                       26:26
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_90_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_90_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_90_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_90_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_90_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_91_SHIFT                       _MK_SHIFT_CONST(27)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_91_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_91_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_91_RANGE                       27:27
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_91_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_91_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_91_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_91_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_91_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_92_SHIFT                       _MK_SHIFT_CONST(28)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_92_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_92_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_92_RANGE                       28:28
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_92_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_92_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_92_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_92_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_92_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_93_SHIFT                       _MK_SHIFT_CONST(29)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_93_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_93_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_93_RANGE                       29:29
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_93_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_93_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_93_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_93_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_93_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_94_SHIFT                       _MK_SHIFT_CONST(30)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_94_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_94_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_94_RANGE                       30:30
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_94_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_94_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_94_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_94_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_94_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_95_SHIFT                       _MK_SHIFT_CONST(31)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_95_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_95_SHIFT)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_95_RANGE                       31:31
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_95_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_95_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_95_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_95_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_3_0_PENDING_SET_SPI_95_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PENDING_SET_4_0  
+#define FIC_DIST_PENDING_SET_4_0                        _MK_ADDR_CONST(0x1210)
+#define FIC_DIST_PENDING_SET_4_0_SECURE                         0x0
+#define FIC_DIST_PENDING_SET_4_0_WORD_COUNT                     0x1
+#define FIC_DIST_PENDING_SET_4_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_4_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_4_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_96_SHIFT                       _MK_SHIFT_CONST(0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_96_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_96_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_96_RANGE                       0:0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_96_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_96_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_96_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_96_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_96_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_97_SHIFT                       _MK_SHIFT_CONST(1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_97_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_97_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_97_RANGE                       1:1
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_97_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_97_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_97_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_97_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_97_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_98_SHIFT                       _MK_SHIFT_CONST(2)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_98_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_98_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_98_RANGE                       2:2
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_98_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_98_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_98_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_98_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_98_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_99_SHIFT                       _MK_SHIFT_CONST(3)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_99_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_99_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_99_RANGE                       3:3
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_99_WOFFSET                     0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_99_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_99_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_99_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_99_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_100_SHIFT                      _MK_SHIFT_CONST(4)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_100_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_100_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_100_RANGE                      4:4
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_100_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_100_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_100_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_100_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_100_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_101_SHIFT                      _MK_SHIFT_CONST(5)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_101_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_101_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_101_RANGE                      5:5
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_101_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_101_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_101_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_101_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_101_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_102_SHIFT                      _MK_SHIFT_CONST(6)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_102_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_102_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_102_RANGE                      6:6
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_102_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_102_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_102_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_102_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_102_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_103_SHIFT                      _MK_SHIFT_CONST(7)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_103_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_103_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_103_RANGE                      7:7
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_103_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_103_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_103_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_103_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_103_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_104_SHIFT                      _MK_SHIFT_CONST(8)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_104_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_104_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_104_RANGE                      8:8
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_104_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_104_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_104_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_104_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_104_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_105_SHIFT                      _MK_SHIFT_CONST(9)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_105_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_105_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_105_RANGE                      9:9
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_105_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_105_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_105_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_105_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_105_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_106_SHIFT                      _MK_SHIFT_CONST(10)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_106_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_106_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_106_RANGE                      10:10
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_106_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_106_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_106_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_106_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_106_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_107_SHIFT                      _MK_SHIFT_CONST(11)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_107_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_107_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_107_RANGE                      11:11
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_107_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_107_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_107_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_107_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_107_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_108_SHIFT                      _MK_SHIFT_CONST(12)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_108_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_108_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_108_RANGE                      12:12
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_108_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_108_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_108_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_108_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_108_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_109_SHIFT                      _MK_SHIFT_CONST(13)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_109_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_109_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_109_RANGE                      13:13
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_109_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_109_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_109_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_109_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_109_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_110_SHIFT                      _MK_SHIFT_CONST(14)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_110_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_110_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_110_RANGE                      14:14
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_110_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_110_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_110_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_110_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_110_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_111_SHIFT                      _MK_SHIFT_CONST(15)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_111_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_111_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_111_RANGE                      15:15
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_111_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_111_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_111_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_111_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_111_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_112_SHIFT                      _MK_SHIFT_CONST(16)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_112_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_112_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_112_RANGE                      16:16
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_112_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_112_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_112_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_112_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_112_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_113_SHIFT                      _MK_SHIFT_CONST(17)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_113_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_113_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_113_RANGE                      17:17
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_113_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_113_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_113_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_113_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_113_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_114_SHIFT                      _MK_SHIFT_CONST(18)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_114_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_114_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_114_RANGE                      18:18
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_114_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_114_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_114_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_114_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_114_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_115_SHIFT                      _MK_SHIFT_CONST(19)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_115_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_115_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_115_RANGE                      19:19
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_115_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_115_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_115_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_115_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_115_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_116_SHIFT                      _MK_SHIFT_CONST(20)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_116_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_116_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_116_RANGE                      20:20
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_116_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_116_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_116_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_116_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_116_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_117_SHIFT                      _MK_SHIFT_CONST(21)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_117_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_117_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_117_RANGE                      21:21
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_117_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_117_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_117_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_117_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_117_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_118_SHIFT                      _MK_SHIFT_CONST(22)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_118_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_118_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_118_RANGE                      22:22
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_118_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_118_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_118_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_118_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_118_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_119_SHIFT                      _MK_SHIFT_CONST(23)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_119_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_119_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_119_RANGE                      23:23
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_119_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_119_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_119_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_119_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_119_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_120_SHIFT                      _MK_SHIFT_CONST(24)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_120_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_120_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_120_RANGE                      24:24
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_120_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_120_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_120_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_120_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_120_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_121_SHIFT                      _MK_SHIFT_CONST(25)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_121_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_121_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_121_RANGE                      25:25
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_121_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_121_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_121_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_121_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_121_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_122_SHIFT                      _MK_SHIFT_CONST(26)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_122_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_122_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_122_RANGE                      26:26
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_122_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_122_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_122_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_122_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_122_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_123_SHIFT                      _MK_SHIFT_CONST(27)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_123_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_123_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_123_RANGE                      27:27
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_123_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_123_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_123_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_123_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_123_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_124_SHIFT                      _MK_SHIFT_CONST(28)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_124_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_124_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_124_RANGE                      28:28
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_124_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_124_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_124_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_124_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_124_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_125_SHIFT                      _MK_SHIFT_CONST(29)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_125_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_125_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_125_RANGE                      29:29
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_125_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_125_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_125_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_125_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_125_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_126_SHIFT                      _MK_SHIFT_CONST(30)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_126_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_126_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_126_RANGE                      30:30
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_126_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_126_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_126_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_126_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_126_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_127_SHIFT                      _MK_SHIFT_CONST(31)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_127_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_127_SHIFT)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_127_RANGE                      31:31
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_127_WOFFSET                    0x0
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_127_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_127_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_127_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_SET_4_0_PENDING_SET_SPI_127_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 4628 [0x1214] 
+
+// Reserved address 4632 [0x1218] 
+
+// Reserved address 4636 [0x121c] 
+
+// Reserved address 4640 [0x1220] 
+
+// Reserved address 4644 [0x1224] 
+
+// Reserved address 4648 [0x1228] 
+
+// Reserved address 4652 [0x122c] 
+
+// Reserved address 4656 [0x1230] 
+
+// Reserved address 4660 [0x1234] 
+
+// Reserved address 4664 [0x1238] 
+
+// Reserved address 4668 [0x123c] 
+
+// Reserved address 4672 [0x1240] 
+
+// Reserved address 4676 [0x1244] 
+
+// Reserved address 4680 [0x1248] 
+
+// Reserved address 4684 [0x124c] 
+
+// Reserved address 4688 [0x1250] 
+
+// Reserved address 4692 [0x1254] 
+
+// Reserved address 4696 [0x1258] 
+
+// Reserved address 4700 [0x125c] 
+
+// Reserved address 4704 [0x1260] 
+
+// Reserved address 4708 [0x1264] 
+
+// Reserved address 4712 [0x1268] 
+
+// Reserved address 4716 [0x126c] 
+
+// Reserved address 4720 [0x1270] 
+
+// Reserved address 4724 [0x1274] 
+
+// Reserved address 4728 [0x1278] 
+
+// Reserved address 4732 [0x127c] 
+
+// Register FIC_DIST_PENDING_CLEAR_0_0  
+#define FIC_DIST_PENDING_CLEAR_0_0                      _MK_ADDR_CONST(0x1280)
+#define FIC_DIST_PENDING_CLEAR_0_0_SECURE                       0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_WORD_COUNT                   0x1
+#define FIC_DIST_PENDING_CLEAR_0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_RESET_MASK                   _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_PENDING_CLEAR_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_READ_MASK                    _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_PENDING_CLEAR_0_0_WRITE_MASK                   _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_0_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_0_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_0_RANGE                      0:0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_0_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_1_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_1_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_1_RANGE                      1:1
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_1_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_2_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_2_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_2_RANGE                      2:2
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_2_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_3_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_3_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_3_RANGE                      3:3
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_3_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_4_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_4_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_4_RANGE                      4:4
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_4_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_5_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_5_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_5_RANGE                      5:5
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_5_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_6_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_6_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_6_RANGE                      6:6
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_6_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_7_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_7_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_7_RANGE                      7:7
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_7_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_8_SHIFT                      _MK_SHIFT_CONST(8)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_8_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_8_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_8_RANGE                      8:8
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_8_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_9_SHIFT                      _MK_SHIFT_CONST(9)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_9_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_9_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_9_RANGE                      9:9
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_9_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_10_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_10_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_10_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_10_RANGE                     10:10
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_10_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_11_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_11_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_11_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_11_RANGE                     11:11
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_11_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_12_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_12_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_12_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_12_RANGE                     12:12
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_12_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_12_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_12_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_13_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_13_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_13_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_13_RANGE                     13:13
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_13_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_13_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_13_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_13_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_13_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_14_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_14_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_14_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_14_RANGE                     14:14
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_14_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_14_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_14_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_14_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_14_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_15_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_15_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_15_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_15_RANGE                     15:15
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_15_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_15_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_15_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_15_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_STI_15_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_4_SHIFT                      _MK_SHIFT_CONST(27)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_4_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_4_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_4_RANGE                      27:27
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_4_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_0_SHIFT                      _MK_SHIFT_CONST(28)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_0_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_0_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_0_RANGE                      28:28
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_0_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_1_SHIFT                      _MK_SHIFT_CONST(29)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_1_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_1_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_1_RANGE                      29:29
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_1_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_2_SHIFT                      _MK_SHIFT_CONST(30)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_2_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_2_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_2_RANGE                      30:30
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_2_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_3_SHIFT                      _MK_SHIFT_CONST(31)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_3_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_3_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_3_RANGE                      31:31
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_3_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_0_0_PENDING_CLR_PPI_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PENDING_CLEAR_1_0  
+#define FIC_DIST_PENDING_CLEAR_1_0                      _MK_ADDR_CONST(0x1284)
+#define FIC_DIST_PENDING_CLEAR_1_0_SECURE                       0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_WORD_COUNT                   0x1
+#define FIC_DIST_PENDING_CLEAR_1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_0_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_0_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_0_RANGE                      0:0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_0_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_1_SHIFT                      _MK_SHIFT_CONST(1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_1_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_1_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_1_RANGE                      1:1
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_1_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_2_SHIFT                      _MK_SHIFT_CONST(2)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_2_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_2_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_2_RANGE                      2:2
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_2_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_3_SHIFT                      _MK_SHIFT_CONST(3)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_3_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_3_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_3_RANGE                      3:3
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_3_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_4_SHIFT                      _MK_SHIFT_CONST(4)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_4_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_4_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_4_RANGE                      4:4
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_4_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_5_SHIFT                      _MK_SHIFT_CONST(5)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_5_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_5_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_5_RANGE                      5:5
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_5_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_6_SHIFT                      _MK_SHIFT_CONST(6)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_6_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_6_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_6_RANGE                      6:6
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_6_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_7_SHIFT                      _MK_SHIFT_CONST(7)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_7_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_7_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_7_RANGE                      7:7
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_7_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_8_SHIFT                      _MK_SHIFT_CONST(8)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_8_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_8_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_8_RANGE                      8:8
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_8_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_9_SHIFT                      _MK_SHIFT_CONST(9)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_9_FIELD                      (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_9_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_9_RANGE                      9:9
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_9_WOFFSET                    0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_10_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_10_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_10_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_10_RANGE                     10:10
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_10_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_11_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_11_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_11_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_11_RANGE                     11:11
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_11_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_12_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_12_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_12_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_12_RANGE                     12:12
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_12_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_12_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_12_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_12_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_12_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_13_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_13_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_13_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_13_RANGE                     13:13
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_13_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_13_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_13_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_13_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_13_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_14_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_14_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_14_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_14_RANGE                     14:14
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_14_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_14_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_14_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_14_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_14_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_15_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_15_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_15_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_15_RANGE                     15:15
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_15_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_15_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_15_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_15_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_15_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_16_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_16_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_16_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_16_RANGE                     16:16
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_16_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_16_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_16_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_16_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_16_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_17_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_17_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_17_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_17_RANGE                     17:17
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_17_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_17_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_17_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_17_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_17_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_18_SHIFT                     _MK_SHIFT_CONST(18)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_18_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_18_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_18_RANGE                     18:18
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_18_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_18_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_18_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_18_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_18_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_19_SHIFT                     _MK_SHIFT_CONST(19)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_19_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_19_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_19_RANGE                     19:19
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_19_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_19_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_19_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_19_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_19_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_20_SHIFT                     _MK_SHIFT_CONST(20)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_20_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_20_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_20_RANGE                     20:20
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_20_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_20_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_20_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_20_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_20_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_21_SHIFT                     _MK_SHIFT_CONST(21)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_21_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_21_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_21_RANGE                     21:21
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_21_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_21_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_21_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_21_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_21_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_22_SHIFT                     _MK_SHIFT_CONST(22)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_22_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_22_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_22_RANGE                     22:22
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_22_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_22_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_22_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_22_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_22_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_23_SHIFT                     _MK_SHIFT_CONST(23)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_23_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_23_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_23_RANGE                     23:23
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_23_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_23_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_23_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_23_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_23_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_24_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_24_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_24_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_24_RANGE                     24:24
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_24_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_24_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_24_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_24_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_24_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_25_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_25_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_25_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_25_RANGE                     25:25
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_25_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_25_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_25_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_25_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_25_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_26_SHIFT                     _MK_SHIFT_CONST(26)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_26_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_26_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_26_RANGE                     26:26
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_26_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_26_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_26_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_26_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_26_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_27_SHIFT                     _MK_SHIFT_CONST(27)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_27_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_27_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_27_RANGE                     27:27
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_27_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_27_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_27_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_27_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_27_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_28_SHIFT                     _MK_SHIFT_CONST(28)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_28_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_28_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_28_RANGE                     28:28
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_28_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_28_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_28_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_28_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_28_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_29_SHIFT                     _MK_SHIFT_CONST(29)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_29_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_29_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_29_RANGE                     29:29
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_29_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_29_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_29_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_29_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_29_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_30_SHIFT                     _MK_SHIFT_CONST(30)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_30_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_30_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_30_RANGE                     30:30
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_30_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_30_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_30_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_30_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_30_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_31_SHIFT                     _MK_SHIFT_CONST(31)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_31_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_31_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_31_RANGE                     31:31
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_31_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_31_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_31_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_31_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_1_0_PENDING_CLR_SPI_31_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PENDING_CLEAR_2_0  
+#define FIC_DIST_PENDING_CLEAR_2_0                      _MK_ADDR_CONST(0x1288)
+#define FIC_DIST_PENDING_CLEAR_2_0_SECURE                       0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_WORD_COUNT                   0x1
+#define FIC_DIST_PENDING_CLEAR_2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_32_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_32_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_32_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_32_RANGE                     0:0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_32_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_32_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_32_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_32_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_32_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_33_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_33_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_33_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_33_RANGE                     1:1
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_33_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_33_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_33_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_33_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_33_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_34_SHIFT                     _MK_SHIFT_CONST(2)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_34_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_34_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_34_RANGE                     2:2
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_34_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_34_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_34_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_34_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_34_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_35_SHIFT                     _MK_SHIFT_CONST(3)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_35_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_35_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_35_RANGE                     3:3
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_35_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_35_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_35_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_35_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_35_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_36_SHIFT                     _MK_SHIFT_CONST(4)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_36_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_36_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_36_RANGE                     4:4
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_36_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_36_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_36_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_36_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_36_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_37_SHIFT                     _MK_SHIFT_CONST(5)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_37_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_37_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_37_RANGE                     5:5
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_37_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_37_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_37_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_37_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_37_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_38_SHIFT                     _MK_SHIFT_CONST(6)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_38_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_38_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_38_RANGE                     6:6
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_38_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_38_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_38_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_38_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_38_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_39_SHIFT                     _MK_SHIFT_CONST(7)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_39_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_39_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_39_RANGE                     7:7
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_39_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_39_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_39_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_39_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_39_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_40_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_40_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_40_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_40_RANGE                     8:8
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_40_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_40_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_40_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_40_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_40_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_41_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_41_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_41_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_41_RANGE                     9:9
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_41_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_41_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_41_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_41_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_41_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_42_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_42_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_42_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_42_RANGE                     10:10
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_42_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_42_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_42_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_42_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_42_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_43_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_43_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_43_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_43_RANGE                     11:11
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_43_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_43_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_43_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_43_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_43_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_44_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_44_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_44_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_44_RANGE                     12:12
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_44_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_44_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_44_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_44_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_44_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_45_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_45_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_45_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_45_RANGE                     13:13
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_45_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_45_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_45_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_45_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_45_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_46_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_46_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_46_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_46_RANGE                     14:14
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_46_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_46_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_46_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_46_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_46_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_47_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_47_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_47_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_47_RANGE                     15:15
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_47_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_47_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_47_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_47_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_47_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_48_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_48_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_48_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_48_RANGE                     16:16
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_48_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_48_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_48_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_48_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_48_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_49_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_49_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_49_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_49_RANGE                     17:17
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_49_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_49_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_49_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_49_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_49_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_50_SHIFT                     _MK_SHIFT_CONST(18)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_50_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_50_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_50_RANGE                     18:18
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_50_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_50_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_50_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_50_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_50_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_51_SHIFT                     _MK_SHIFT_CONST(19)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_51_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_51_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_51_RANGE                     19:19
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_51_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_51_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_51_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_51_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_51_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_52_SHIFT                     _MK_SHIFT_CONST(20)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_52_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_52_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_52_RANGE                     20:20
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_52_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_52_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_52_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_52_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_52_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_53_SHIFT                     _MK_SHIFT_CONST(21)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_53_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_53_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_53_RANGE                     21:21
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_53_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_53_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_53_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_53_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_53_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_54_SHIFT                     _MK_SHIFT_CONST(22)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_54_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_54_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_54_RANGE                     22:22
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_54_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_54_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_54_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_54_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_54_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_55_SHIFT                     _MK_SHIFT_CONST(23)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_55_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_55_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_55_RANGE                     23:23
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_55_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_55_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_55_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_55_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_55_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_56_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_56_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_56_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_56_RANGE                     24:24
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_56_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_56_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_56_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_56_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_56_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_57_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_57_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_57_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_57_RANGE                     25:25
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_57_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_57_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_57_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_57_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_57_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_58_SHIFT                     _MK_SHIFT_CONST(26)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_58_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_58_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_58_RANGE                     26:26
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_58_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_58_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_58_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_58_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_58_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_59_SHIFT                     _MK_SHIFT_CONST(27)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_59_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_59_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_59_RANGE                     27:27
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_59_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_59_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_59_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_59_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_59_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_60_SHIFT                     _MK_SHIFT_CONST(28)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_60_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_60_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_60_RANGE                     28:28
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_60_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_60_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_60_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_60_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_60_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_61_SHIFT                     _MK_SHIFT_CONST(29)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_61_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_61_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_61_RANGE                     29:29
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_61_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_61_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_61_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_61_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_61_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_62_SHIFT                     _MK_SHIFT_CONST(30)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_62_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_62_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_62_RANGE                     30:30
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_62_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_62_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_62_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_62_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_62_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_63_SHIFT                     _MK_SHIFT_CONST(31)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_63_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_63_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_63_RANGE                     31:31
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_63_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_63_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_63_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_63_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_2_0_PENDING_CLR_SPI_63_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PENDING_CLEAR_3_0  
+#define FIC_DIST_PENDING_CLEAR_3_0                      _MK_ADDR_CONST(0x128c)
+#define FIC_DIST_PENDING_CLEAR_3_0_SECURE                       0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_WORD_COUNT                   0x1
+#define FIC_DIST_PENDING_CLEAR_3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_3_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_64_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_64_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_64_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_64_RANGE                     0:0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_64_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_64_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_64_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_64_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_64_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_65_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_65_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_65_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_65_RANGE                     1:1
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_65_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_65_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_65_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_65_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_65_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_66_SHIFT                     _MK_SHIFT_CONST(2)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_66_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_66_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_66_RANGE                     2:2
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_66_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_66_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_66_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_66_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_66_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_67_SHIFT                     _MK_SHIFT_CONST(3)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_67_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_67_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_67_RANGE                     3:3
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_67_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_67_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_67_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_67_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_67_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_68_SHIFT                     _MK_SHIFT_CONST(4)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_68_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_68_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_68_RANGE                     4:4
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_68_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_68_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_68_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_68_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_68_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_69_SHIFT                     _MK_SHIFT_CONST(5)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_69_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_69_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_69_RANGE                     5:5
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_69_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_69_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_69_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_69_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_69_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_70_SHIFT                     _MK_SHIFT_CONST(6)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_70_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_70_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_70_RANGE                     6:6
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_70_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_70_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_70_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_70_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_70_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_71_SHIFT                     _MK_SHIFT_CONST(7)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_71_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_71_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_71_RANGE                     7:7
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_71_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_71_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_71_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_71_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_71_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_72_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_72_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_72_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_72_RANGE                     8:8
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_72_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_72_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_72_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_72_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_72_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_73_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_73_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_73_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_73_RANGE                     9:9
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_73_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_73_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_73_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_73_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_73_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_74_SHIFT                     _MK_SHIFT_CONST(10)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_74_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_74_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_74_RANGE                     10:10
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_74_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_74_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_74_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_74_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_74_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_75_SHIFT                     _MK_SHIFT_CONST(11)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_75_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_75_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_75_RANGE                     11:11
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_75_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_75_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_75_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_75_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_75_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_76_SHIFT                     _MK_SHIFT_CONST(12)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_76_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_76_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_76_RANGE                     12:12
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_76_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_76_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_76_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_76_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_76_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_77_SHIFT                     _MK_SHIFT_CONST(13)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_77_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_77_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_77_RANGE                     13:13
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_77_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_77_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_77_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_77_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_77_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_78_SHIFT                     _MK_SHIFT_CONST(14)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_78_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_78_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_78_RANGE                     14:14
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_78_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_78_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_78_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_78_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_78_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_79_SHIFT                     _MK_SHIFT_CONST(15)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_79_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_79_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_79_RANGE                     15:15
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_79_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_79_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_79_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_79_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_79_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_80_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_80_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_80_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_80_RANGE                     16:16
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_80_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_80_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_80_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_80_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_80_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_81_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_81_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_81_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_81_RANGE                     17:17
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_81_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_81_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_81_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_81_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_81_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_82_SHIFT                     _MK_SHIFT_CONST(18)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_82_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_82_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_82_RANGE                     18:18
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_82_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_82_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_82_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_82_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_82_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_83_SHIFT                     _MK_SHIFT_CONST(19)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_83_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_83_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_83_RANGE                     19:19
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_83_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_83_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_83_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_83_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_83_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_84_SHIFT                     _MK_SHIFT_CONST(20)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_84_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_84_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_84_RANGE                     20:20
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_84_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_84_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_84_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_84_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_84_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_85_SHIFT                     _MK_SHIFT_CONST(21)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_85_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_85_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_85_RANGE                     21:21
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_85_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_85_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_85_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_85_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_85_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_86_SHIFT                     _MK_SHIFT_CONST(22)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_86_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_86_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_86_RANGE                     22:22
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_86_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_86_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_86_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_86_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_86_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_87_SHIFT                     _MK_SHIFT_CONST(23)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_87_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_87_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_87_RANGE                     23:23
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_87_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_87_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_87_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_87_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_87_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_88_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_88_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_88_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_88_RANGE                     24:24
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_88_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_88_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_88_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_88_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_88_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_89_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_89_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_89_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_89_RANGE                     25:25
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_89_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_89_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_89_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_89_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_89_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_90_SHIFT                     _MK_SHIFT_CONST(26)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_90_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_90_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_90_RANGE                     26:26
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_90_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_90_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_90_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_90_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_90_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_91_SHIFT                     _MK_SHIFT_CONST(27)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_91_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_91_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_91_RANGE                     27:27
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_91_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_91_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_91_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_91_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_91_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_92_SHIFT                     _MK_SHIFT_CONST(28)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_92_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_92_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_92_RANGE                     28:28
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_92_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_92_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_92_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_92_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_92_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_93_SHIFT                     _MK_SHIFT_CONST(29)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_93_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_93_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_93_RANGE                     29:29
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_93_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_93_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_93_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_93_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_93_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_94_SHIFT                     _MK_SHIFT_CONST(30)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_94_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_94_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_94_RANGE                     30:30
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_94_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_94_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_94_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_94_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_94_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_95_SHIFT                     _MK_SHIFT_CONST(31)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_95_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_95_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_95_RANGE                     31:31
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_95_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_95_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_95_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_95_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_3_0_PENDING_CLR_SPI_95_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PENDING_CLEAR_4_0  
+#define FIC_DIST_PENDING_CLEAR_4_0                      _MK_ADDR_CONST(0x1290)
+#define FIC_DIST_PENDING_CLEAR_4_0_SECURE                       0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_WORD_COUNT                   0x1
+#define FIC_DIST_PENDING_CLEAR_4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_4_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_96_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_96_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_96_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_96_RANGE                     0:0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_96_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_96_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_96_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_96_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_96_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_97_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_97_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_97_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_97_RANGE                     1:1
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_97_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_97_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_97_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_97_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_97_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_98_SHIFT                     _MK_SHIFT_CONST(2)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_98_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_98_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_98_RANGE                     2:2
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_98_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_98_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_98_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_98_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_98_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_99_SHIFT                     _MK_SHIFT_CONST(3)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_99_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_99_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_99_RANGE                     3:3
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_99_WOFFSET                   0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_99_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_99_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_99_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_99_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_100_SHIFT                    _MK_SHIFT_CONST(4)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_100_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_100_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_100_RANGE                    4:4
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_100_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_100_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_100_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_100_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_100_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_101_SHIFT                    _MK_SHIFT_CONST(5)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_101_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_101_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_101_RANGE                    5:5
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_101_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_101_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_101_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_101_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_101_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_102_SHIFT                    _MK_SHIFT_CONST(6)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_102_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_102_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_102_RANGE                    6:6
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_102_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_102_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_102_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_102_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_102_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_103_SHIFT                    _MK_SHIFT_CONST(7)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_103_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_103_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_103_RANGE                    7:7
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_103_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_103_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_103_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_103_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_103_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_104_SHIFT                    _MK_SHIFT_CONST(8)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_104_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_104_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_104_RANGE                    8:8
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_104_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_104_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_104_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_104_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_104_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_105_SHIFT                    _MK_SHIFT_CONST(9)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_105_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_105_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_105_RANGE                    9:9
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_105_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_105_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_105_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_105_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_105_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_106_SHIFT                    _MK_SHIFT_CONST(10)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_106_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_106_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_106_RANGE                    10:10
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_106_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_106_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_106_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_106_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_106_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_107_SHIFT                    _MK_SHIFT_CONST(11)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_107_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_107_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_107_RANGE                    11:11
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_107_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_107_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_107_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_107_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_107_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_108_SHIFT                    _MK_SHIFT_CONST(12)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_108_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_108_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_108_RANGE                    12:12
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_108_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_108_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_108_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_108_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_108_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_109_SHIFT                    _MK_SHIFT_CONST(13)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_109_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_109_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_109_RANGE                    13:13
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_109_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_109_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_109_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_109_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_109_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_110_SHIFT                    _MK_SHIFT_CONST(14)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_110_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_110_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_110_RANGE                    14:14
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_110_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_110_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_110_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_110_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_110_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_111_SHIFT                    _MK_SHIFT_CONST(15)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_111_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_111_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_111_RANGE                    15:15
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_111_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_111_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_111_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_111_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_111_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_112_SHIFT                    _MK_SHIFT_CONST(16)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_112_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_112_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_112_RANGE                    16:16
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_112_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_112_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_112_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_112_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_112_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_113_SHIFT                    _MK_SHIFT_CONST(17)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_113_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_113_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_113_RANGE                    17:17
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_113_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_113_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_113_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_113_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_113_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_114_SHIFT                    _MK_SHIFT_CONST(18)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_114_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_114_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_114_RANGE                    18:18
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_114_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_114_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_114_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_114_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_114_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_115_SHIFT                    _MK_SHIFT_CONST(19)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_115_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_115_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_115_RANGE                    19:19
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_115_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_115_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_115_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_115_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_115_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_116_SHIFT                    _MK_SHIFT_CONST(20)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_116_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_116_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_116_RANGE                    20:20
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_116_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_116_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_116_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_116_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_116_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_117_SHIFT                    _MK_SHIFT_CONST(21)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_117_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_117_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_117_RANGE                    21:21
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_117_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_117_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_117_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_117_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_117_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_118_SHIFT                    _MK_SHIFT_CONST(22)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_118_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_118_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_118_RANGE                    22:22
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_118_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_118_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_118_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_118_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_118_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_119_SHIFT                    _MK_SHIFT_CONST(23)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_119_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_119_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_119_RANGE                    23:23
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_119_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_119_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_119_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_119_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_119_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_120_SHIFT                    _MK_SHIFT_CONST(24)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_120_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_120_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_120_RANGE                    24:24
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_120_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_120_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_120_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_120_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_120_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_121_SHIFT                    _MK_SHIFT_CONST(25)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_121_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_121_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_121_RANGE                    25:25
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_121_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_121_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_121_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_121_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_121_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_122_SHIFT                    _MK_SHIFT_CONST(26)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_122_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_122_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_122_RANGE                    26:26
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_122_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_122_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_122_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_122_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_122_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_123_SHIFT                    _MK_SHIFT_CONST(27)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_123_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_123_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_123_RANGE                    27:27
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_123_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_123_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_123_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_123_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_123_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_124_SHIFT                    _MK_SHIFT_CONST(28)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_124_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_124_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_124_RANGE                    28:28
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_124_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_124_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_124_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_124_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_124_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_125_SHIFT                    _MK_SHIFT_CONST(29)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_125_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_125_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_125_RANGE                    29:29
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_125_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_125_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_125_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_125_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_125_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_126_SHIFT                    _MK_SHIFT_CONST(30)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_126_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_126_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_126_RANGE                    30:30
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_126_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_126_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_126_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_126_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_126_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_127_SHIFT                    _MK_SHIFT_CONST(31)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_127_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_127_SHIFT)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_127_RANGE                    31:31
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_127_WOFFSET                  0x0
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_127_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_127_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_127_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PENDING_CLEAR_4_0_PENDING_CLR_SPI_127_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 4756 [0x1294] 
+
+// Reserved address 4760 [0x1298] 
+
+// Reserved address 4764 [0x129c] 
+
+// Reserved address 4768 [0x12a0] 
+
+// Reserved address 4772 [0x12a4] 
+
+// Reserved address 4776 [0x12a8] 
+
+// Reserved address 4780 [0x12ac] 
+
+// Reserved address 4784 [0x12b0] 
+
+// Reserved address 4788 [0x12b4] 
+
+// Reserved address 4792 [0x12b8] 
+
+// Reserved address 4796 [0x12bc] 
+
+// Reserved address 4800 [0x12c0] 
+
+// Reserved address 4804 [0x12c4] 
+
+// Reserved address 4808 [0x12c8] 
+
+// Reserved address 4812 [0x12cc] 
+
+// Reserved address 4816 [0x12d0] 
+
+// Reserved address 4820 [0x12d4] 
+
+// Reserved address 4824 [0x12d8] 
+
+// Reserved address 4828 [0x12dc] 
+
+// Reserved address 4832 [0x12e0] 
+
+// Reserved address 4836 [0x12e4] 
+
+// Reserved address 4840 [0x12e8] 
+
+// Reserved address 4844 [0x12ec] 
+
+// Reserved address 4848 [0x12f0] 
+
+// Reserved address 4852 [0x12f4] 
+
+// Reserved address 4856 [0x12f8] 
+
+// Reserved address 4860 [0x12fc] 
+
+// Register FIC_DIST_ACTIVE_STATUS_0_0  
+#define FIC_DIST_ACTIVE_STATUS_0_0                      _MK_ADDR_CONST(0x1300)
+#define FIC_DIST_ACTIVE_STATUS_0_0_SECURE                       0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_WORD_COUNT                   0x1
+#define FIC_DIST_ACTIVE_STATUS_0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_RESET_MASK                   _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_ACTIVE_STATUS_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_READ_MASK                    _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_ACTIVE_STATUS_0_0_WRITE_MASK                   _MK_MASK_CONST(0xf800ffff)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_0_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_0_RANGE                    0:0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_0_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_1_SHIFT                    _MK_SHIFT_CONST(1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_1_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_1_RANGE                    1:1
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_1_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_2_SHIFT                    _MK_SHIFT_CONST(2)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_2_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_2_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_2_RANGE                    2:2
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_2_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_3_SHIFT                    _MK_SHIFT_CONST(3)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_3_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_3_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_3_RANGE                    3:3
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_3_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_4_SHIFT                    _MK_SHIFT_CONST(4)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_4_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_4_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_4_RANGE                    4:4
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_4_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_5_SHIFT                    _MK_SHIFT_CONST(5)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_5_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_5_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_5_RANGE                    5:5
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_5_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_6_SHIFT                    _MK_SHIFT_CONST(6)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_6_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_6_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_6_RANGE                    6:6
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_6_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_7_SHIFT                    _MK_SHIFT_CONST(7)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_7_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_7_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_7_RANGE                    7:7
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_7_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_8_SHIFT                    _MK_SHIFT_CONST(8)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_8_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_8_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_8_RANGE                    8:8
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_8_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_9_SHIFT                    _MK_SHIFT_CONST(9)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_9_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_9_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_9_RANGE                    9:9
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_9_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_10_SHIFT                   _MK_SHIFT_CONST(10)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_10_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_10_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_10_RANGE                   10:10
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_10_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_10_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_10_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_10_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_10_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_11_SHIFT                   _MK_SHIFT_CONST(11)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_11_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_11_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_11_RANGE                   11:11
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_11_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_11_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_11_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_11_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_11_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_12_SHIFT                   _MK_SHIFT_CONST(12)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_12_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_12_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_12_RANGE                   12:12
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_12_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_12_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_12_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_12_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_12_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_13_SHIFT                   _MK_SHIFT_CONST(13)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_13_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_13_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_13_RANGE                   13:13
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_13_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_13_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_13_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_13_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_13_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_14_SHIFT                   _MK_SHIFT_CONST(14)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_14_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_14_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_14_RANGE                   14:14
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_14_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_14_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_14_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_14_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_14_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_15_SHIFT                   _MK_SHIFT_CONST(15)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_15_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_15_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_15_RANGE                   15:15
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_15_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_15_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_15_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_15_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_STI_15_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_4_SHIFT                    _MK_SHIFT_CONST(27)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_4_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_4_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_4_RANGE                    27:27
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_4_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_0_SHIFT                    _MK_SHIFT_CONST(28)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_0_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_0_RANGE                    28:28
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_0_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_1_SHIFT                    _MK_SHIFT_CONST(29)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_1_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_1_RANGE                    29:29
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_1_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_2_SHIFT                    _MK_SHIFT_CONST(30)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_2_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_2_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_2_RANGE                    30:30
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_2_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_3_SHIFT                    _MK_SHIFT_CONST(31)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_3_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_3_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_3_RANGE                    31:31
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_3_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_0_0_ACTIVE_STATUS_PPI_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ACTIVE_STATUS_1_0  
+#define FIC_DIST_ACTIVE_STATUS_1_0                      _MK_ADDR_CONST(0x1304)
+#define FIC_DIST_ACTIVE_STATUS_1_0_SECURE                       0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_WORD_COUNT                   0x1
+#define FIC_DIST_ACTIVE_STATUS_1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_0_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_0_RANGE                    0:0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_0_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_1_SHIFT                    _MK_SHIFT_CONST(1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_1_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_1_RANGE                    1:1
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_1_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_2_SHIFT                    _MK_SHIFT_CONST(2)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_2_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_2_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_2_RANGE                    2:2
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_2_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_3_SHIFT                    _MK_SHIFT_CONST(3)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_3_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_3_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_3_RANGE                    3:3
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_3_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_4_SHIFT                    _MK_SHIFT_CONST(4)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_4_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_4_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_4_RANGE                    4:4
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_4_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_5_SHIFT                    _MK_SHIFT_CONST(5)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_5_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_5_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_5_RANGE                    5:5
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_5_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_6_SHIFT                    _MK_SHIFT_CONST(6)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_6_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_6_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_6_RANGE                    6:6
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_6_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_7_SHIFT                    _MK_SHIFT_CONST(7)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_7_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_7_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_7_RANGE                    7:7
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_7_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_8_SHIFT                    _MK_SHIFT_CONST(8)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_8_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_8_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_8_RANGE                    8:8
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_8_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_9_SHIFT                    _MK_SHIFT_CONST(9)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_9_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_9_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_9_RANGE                    9:9
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_9_WOFFSET                  0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_10_SHIFT                   _MK_SHIFT_CONST(10)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_10_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_10_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_10_RANGE                   10:10
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_10_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_10_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_10_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_10_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_10_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_11_SHIFT                   _MK_SHIFT_CONST(11)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_11_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_11_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_11_RANGE                   11:11
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_11_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_11_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_11_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_11_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_11_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_12_SHIFT                   _MK_SHIFT_CONST(12)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_12_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_12_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_12_RANGE                   12:12
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_12_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_12_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_12_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_12_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_12_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_13_SHIFT                   _MK_SHIFT_CONST(13)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_13_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_13_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_13_RANGE                   13:13
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_13_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_13_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_13_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_13_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_13_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_14_SHIFT                   _MK_SHIFT_CONST(14)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_14_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_14_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_14_RANGE                   14:14
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_14_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_14_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_14_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_14_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_14_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_15_SHIFT                   _MK_SHIFT_CONST(15)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_15_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_15_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_15_RANGE                   15:15
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_15_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_15_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_15_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_15_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_15_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_16_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_16_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_16_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_16_RANGE                   16:16
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_16_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_16_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_16_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_16_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_16_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_17_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_17_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_17_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_17_RANGE                   17:17
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_17_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_17_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_17_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_17_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_17_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_18_SHIFT                   _MK_SHIFT_CONST(18)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_18_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_18_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_18_RANGE                   18:18
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_18_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_18_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_18_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_18_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_18_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_19_SHIFT                   _MK_SHIFT_CONST(19)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_19_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_19_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_19_RANGE                   19:19
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_19_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_19_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_19_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_19_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_19_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_20_SHIFT                   _MK_SHIFT_CONST(20)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_20_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_20_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_20_RANGE                   20:20
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_20_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_20_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_20_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_20_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_20_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_21_SHIFT                   _MK_SHIFT_CONST(21)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_21_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_21_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_21_RANGE                   21:21
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_21_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_21_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_21_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_21_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_21_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_22_SHIFT                   _MK_SHIFT_CONST(22)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_22_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_22_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_22_RANGE                   22:22
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_22_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_22_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_22_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_22_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_22_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_23_SHIFT                   _MK_SHIFT_CONST(23)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_23_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_23_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_23_RANGE                   23:23
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_23_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_23_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_23_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_23_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_23_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_24_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_24_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_24_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_24_RANGE                   24:24
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_24_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_24_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_24_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_24_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_24_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_25_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_25_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_25_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_25_RANGE                   25:25
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_25_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_25_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_25_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_25_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_25_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_26_SHIFT                   _MK_SHIFT_CONST(26)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_26_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_26_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_26_RANGE                   26:26
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_26_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_26_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_26_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_26_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_26_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_27_SHIFT                   _MK_SHIFT_CONST(27)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_27_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_27_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_27_RANGE                   27:27
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_27_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_27_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_27_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_27_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_27_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_28_SHIFT                   _MK_SHIFT_CONST(28)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_28_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_28_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_28_RANGE                   28:28
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_28_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_28_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_28_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_28_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_28_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_29_SHIFT                   _MK_SHIFT_CONST(29)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_29_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_29_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_29_RANGE                   29:29
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_29_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_29_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_29_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_29_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_29_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_30_SHIFT                   _MK_SHIFT_CONST(30)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_30_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_30_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_30_RANGE                   30:30
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_30_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_30_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_30_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_30_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_30_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_31_SHIFT                   _MK_SHIFT_CONST(31)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_31_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_31_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_31_RANGE                   31:31
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_31_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_31_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_31_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_31_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_1_0_ACTIVE_STATUS_SPI_31_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ACTIVE_STATUS_2_0  
+#define FIC_DIST_ACTIVE_STATUS_2_0                      _MK_ADDR_CONST(0x1308)
+#define FIC_DIST_ACTIVE_STATUS_2_0_SECURE                       0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_WORD_COUNT                   0x1
+#define FIC_DIST_ACTIVE_STATUS_2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_2_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_32_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_32_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_32_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_32_RANGE                   0:0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_32_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_32_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_32_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_32_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_32_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_33_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_33_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_33_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_33_RANGE                   1:1
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_33_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_33_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_33_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_33_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_33_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_34_SHIFT                   _MK_SHIFT_CONST(2)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_34_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_34_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_34_RANGE                   2:2
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_34_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_34_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_34_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_34_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_34_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_35_SHIFT                   _MK_SHIFT_CONST(3)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_35_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_35_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_35_RANGE                   3:3
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_35_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_35_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_35_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_35_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_35_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_36_SHIFT                   _MK_SHIFT_CONST(4)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_36_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_36_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_36_RANGE                   4:4
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_36_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_36_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_36_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_36_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_36_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_37_SHIFT                   _MK_SHIFT_CONST(5)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_37_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_37_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_37_RANGE                   5:5
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_37_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_37_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_37_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_37_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_37_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_38_SHIFT                   _MK_SHIFT_CONST(6)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_38_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_38_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_38_RANGE                   6:6
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_38_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_38_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_38_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_38_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_38_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_39_SHIFT                   _MK_SHIFT_CONST(7)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_39_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_39_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_39_RANGE                   7:7
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_39_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_39_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_39_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_39_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_39_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_40_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_40_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_40_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_40_RANGE                   8:8
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_40_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_40_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_40_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_40_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_40_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_41_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_41_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_41_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_41_RANGE                   9:9
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_41_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_41_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_41_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_41_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_41_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_42_SHIFT                   _MK_SHIFT_CONST(10)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_42_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_42_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_42_RANGE                   10:10
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_42_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_42_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_42_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_42_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_42_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_43_SHIFT                   _MK_SHIFT_CONST(11)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_43_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_43_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_43_RANGE                   11:11
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_43_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_43_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_43_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_43_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_43_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_44_SHIFT                   _MK_SHIFT_CONST(12)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_44_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_44_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_44_RANGE                   12:12
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_44_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_44_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_44_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_44_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_44_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_45_SHIFT                   _MK_SHIFT_CONST(13)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_45_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_45_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_45_RANGE                   13:13
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_45_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_45_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_45_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_45_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_45_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_46_SHIFT                   _MK_SHIFT_CONST(14)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_46_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_46_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_46_RANGE                   14:14
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_46_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_46_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_46_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_46_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_46_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_47_SHIFT                   _MK_SHIFT_CONST(15)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_47_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_47_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_47_RANGE                   15:15
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_47_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_47_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_47_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_47_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_47_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_48_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_48_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_48_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_48_RANGE                   16:16
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_48_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_48_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_48_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_48_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_48_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_49_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_49_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_49_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_49_RANGE                   17:17
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_49_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_49_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_49_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_49_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_49_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_50_SHIFT                   _MK_SHIFT_CONST(18)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_50_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_50_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_50_RANGE                   18:18
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_50_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_50_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_50_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_50_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_50_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_51_SHIFT                   _MK_SHIFT_CONST(19)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_51_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_51_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_51_RANGE                   19:19
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_51_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_51_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_51_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_51_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_51_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_52_SHIFT                   _MK_SHIFT_CONST(20)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_52_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_52_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_52_RANGE                   20:20
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_52_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_52_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_52_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_52_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_52_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_53_SHIFT                   _MK_SHIFT_CONST(21)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_53_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_53_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_53_RANGE                   21:21
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_53_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_53_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_53_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_53_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_53_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_54_SHIFT                   _MK_SHIFT_CONST(22)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_54_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_54_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_54_RANGE                   22:22
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_54_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_54_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_54_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_54_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_54_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_55_SHIFT                   _MK_SHIFT_CONST(23)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_55_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_55_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_55_RANGE                   23:23
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_55_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_55_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_55_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_55_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_55_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_56_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_56_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_56_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_56_RANGE                   24:24
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_56_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_56_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_56_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_56_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_56_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_57_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_57_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_57_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_57_RANGE                   25:25
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_57_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_57_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_57_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_57_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_57_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_58_SHIFT                   _MK_SHIFT_CONST(26)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_58_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_58_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_58_RANGE                   26:26
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_58_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_58_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_58_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_58_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_58_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_59_SHIFT                   _MK_SHIFT_CONST(27)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_59_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_59_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_59_RANGE                   27:27
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_59_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_59_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_59_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_59_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_59_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_60_SHIFT                   _MK_SHIFT_CONST(28)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_60_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_60_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_60_RANGE                   28:28
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_60_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_60_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_60_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_60_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_60_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_61_SHIFT                   _MK_SHIFT_CONST(29)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_61_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_61_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_61_RANGE                   29:29
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_61_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_61_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_61_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_61_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_61_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_62_SHIFT                   _MK_SHIFT_CONST(30)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_62_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_62_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_62_RANGE                   30:30
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_62_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_62_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_62_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_62_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_62_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_63_SHIFT                   _MK_SHIFT_CONST(31)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_63_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_63_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_63_RANGE                   31:31
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_63_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_63_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_63_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_63_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_2_0_ACTIVE_STATUS_SPI_63_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ACTIVE_STATUS_3_0  
+#define FIC_DIST_ACTIVE_STATUS_3_0                      _MK_ADDR_CONST(0x130c)
+#define FIC_DIST_ACTIVE_STATUS_3_0_SECURE                       0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_WORD_COUNT                   0x1
+#define FIC_DIST_ACTIVE_STATUS_3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_3_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_64_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_64_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_64_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_64_RANGE                   0:0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_64_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_64_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_64_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_64_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_64_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_65_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_65_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_65_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_65_RANGE                   1:1
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_65_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_65_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_65_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_65_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_65_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_66_SHIFT                   _MK_SHIFT_CONST(2)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_66_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_66_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_66_RANGE                   2:2
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_66_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_66_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_66_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_66_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_66_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_67_SHIFT                   _MK_SHIFT_CONST(3)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_67_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_67_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_67_RANGE                   3:3
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_67_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_67_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_67_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_67_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_67_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_68_SHIFT                   _MK_SHIFT_CONST(4)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_68_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_68_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_68_RANGE                   4:4
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_68_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_68_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_68_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_68_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_68_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_69_SHIFT                   _MK_SHIFT_CONST(5)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_69_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_69_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_69_RANGE                   5:5
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_69_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_69_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_69_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_69_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_69_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_70_SHIFT                   _MK_SHIFT_CONST(6)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_70_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_70_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_70_RANGE                   6:6
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_70_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_70_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_70_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_70_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_70_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_71_SHIFT                   _MK_SHIFT_CONST(7)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_71_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_71_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_71_RANGE                   7:7
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_71_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_71_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_71_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_71_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_71_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_72_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_72_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_72_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_72_RANGE                   8:8
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_72_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_72_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_72_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_72_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_72_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_73_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_73_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_73_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_73_RANGE                   9:9
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_73_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_73_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_73_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_73_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_73_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_74_SHIFT                   _MK_SHIFT_CONST(10)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_74_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_74_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_74_RANGE                   10:10
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_74_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_74_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_74_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_74_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_74_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_75_SHIFT                   _MK_SHIFT_CONST(11)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_75_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_75_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_75_RANGE                   11:11
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_75_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_75_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_75_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_75_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_75_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_76_SHIFT                   _MK_SHIFT_CONST(12)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_76_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_76_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_76_RANGE                   12:12
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_76_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_76_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_76_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_76_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_76_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_77_SHIFT                   _MK_SHIFT_CONST(13)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_77_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_77_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_77_RANGE                   13:13
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_77_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_77_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_77_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_77_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_77_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_78_SHIFT                   _MK_SHIFT_CONST(14)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_78_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_78_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_78_RANGE                   14:14
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_78_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_78_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_78_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_78_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_78_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_79_SHIFT                   _MK_SHIFT_CONST(15)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_79_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_79_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_79_RANGE                   15:15
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_79_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_79_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_79_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_79_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_79_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_80_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_80_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_80_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_80_RANGE                   16:16
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_80_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_80_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_80_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_80_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_80_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_81_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_81_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_81_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_81_RANGE                   17:17
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_81_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_81_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_81_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_81_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_81_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_82_SHIFT                   _MK_SHIFT_CONST(18)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_82_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_82_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_82_RANGE                   18:18
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_82_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_82_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_82_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_82_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_82_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_83_SHIFT                   _MK_SHIFT_CONST(19)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_83_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_83_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_83_RANGE                   19:19
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_83_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_83_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_83_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_83_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_83_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_84_SHIFT                   _MK_SHIFT_CONST(20)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_84_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_84_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_84_RANGE                   20:20
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_84_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_84_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_84_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_84_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_84_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_85_SHIFT                   _MK_SHIFT_CONST(21)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_85_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_85_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_85_RANGE                   21:21
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_85_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_85_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_85_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_85_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_85_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_86_SHIFT                   _MK_SHIFT_CONST(22)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_86_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_86_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_86_RANGE                   22:22
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_86_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_86_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_86_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_86_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_86_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_87_SHIFT                   _MK_SHIFT_CONST(23)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_87_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_87_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_87_RANGE                   23:23
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_87_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_87_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_87_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_87_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_87_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_88_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_88_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_88_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_88_RANGE                   24:24
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_88_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_88_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_88_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_88_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_88_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_89_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_89_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_89_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_89_RANGE                   25:25
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_89_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_89_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_89_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_89_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_89_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_90_SHIFT                   _MK_SHIFT_CONST(26)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_90_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_90_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_90_RANGE                   26:26
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_90_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_90_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_90_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_90_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_90_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_91_SHIFT                   _MK_SHIFT_CONST(27)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_91_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_91_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_91_RANGE                   27:27
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_91_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_91_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_91_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_91_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_91_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_92_SHIFT                   _MK_SHIFT_CONST(28)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_92_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_92_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_92_RANGE                   28:28
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_92_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_92_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_92_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_92_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_92_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_93_SHIFT                   _MK_SHIFT_CONST(29)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_93_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_93_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_93_RANGE                   29:29
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_93_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_93_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_93_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_93_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_93_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_94_SHIFT                   _MK_SHIFT_CONST(30)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_94_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_94_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_94_RANGE                   30:30
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_94_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_94_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_94_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_94_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_94_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_95_SHIFT                   _MK_SHIFT_CONST(31)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_95_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_95_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_95_RANGE                   31:31
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_95_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_95_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_95_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_95_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_3_0_ACTIVE_STATUS_SPI_95_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_ACTIVE_STATUS_4_0  
+#define FIC_DIST_ACTIVE_STATUS_4_0                      _MK_ADDR_CONST(0x1310)
+#define FIC_DIST_ACTIVE_STATUS_4_0_SECURE                       0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_WORD_COUNT                   0x1
+#define FIC_DIST_ACTIVE_STATUS_4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_4_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_96_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_96_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_96_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_96_RANGE                   0:0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_96_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_96_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_96_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_96_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_96_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_97_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_97_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_97_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_97_RANGE                   1:1
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_97_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_97_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_97_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_97_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_97_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_98_SHIFT                   _MK_SHIFT_CONST(2)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_98_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_98_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_98_RANGE                   2:2
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_98_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_98_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_98_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_98_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_98_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_99_SHIFT                   _MK_SHIFT_CONST(3)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_99_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_99_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_99_RANGE                   3:3
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_99_WOFFSET                 0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_99_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_99_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_99_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_99_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_100_SHIFT                  _MK_SHIFT_CONST(4)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_100_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_100_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_100_RANGE                  4:4
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_100_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_100_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_100_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_100_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_100_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_101_SHIFT                  _MK_SHIFT_CONST(5)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_101_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_101_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_101_RANGE                  5:5
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_101_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_101_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_101_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_101_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_101_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_102_SHIFT                  _MK_SHIFT_CONST(6)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_102_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_102_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_102_RANGE                  6:6
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_102_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_102_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_102_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_102_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_102_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_103_SHIFT                  _MK_SHIFT_CONST(7)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_103_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_103_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_103_RANGE                  7:7
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_103_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_103_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_103_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_103_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_103_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_104_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_104_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_104_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_104_RANGE                  8:8
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_104_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_104_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_104_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_104_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_104_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_105_SHIFT                  _MK_SHIFT_CONST(9)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_105_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_105_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_105_RANGE                  9:9
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_105_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_105_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_105_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_105_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_105_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_106_SHIFT                  _MK_SHIFT_CONST(10)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_106_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_106_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_106_RANGE                  10:10
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_106_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_106_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_106_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_106_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_106_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_107_SHIFT                  _MK_SHIFT_CONST(11)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_107_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_107_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_107_RANGE                  11:11
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_107_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_107_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_107_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_107_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_107_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_108_SHIFT                  _MK_SHIFT_CONST(12)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_108_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_108_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_108_RANGE                  12:12
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_108_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_108_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_108_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_108_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_108_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_109_SHIFT                  _MK_SHIFT_CONST(13)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_109_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_109_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_109_RANGE                  13:13
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_109_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_109_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_109_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_109_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_109_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_110_SHIFT                  _MK_SHIFT_CONST(14)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_110_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_110_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_110_RANGE                  14:14
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_110_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_110_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_110_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_110_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_110_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_111_SHIFT                  _MK_SHIFT_CONST(15)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_111_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_111_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_111_RANGE                  15:15
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_111_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_111_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_111_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_111_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_111_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_112_SHIFT                  _MK_SHIFT_CONST(16)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_112_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_112_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_112_RANGE                  16:16
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_112_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_112_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_112_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_112_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_112_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_113_SHIFT                  _MK_SHIFT_CONST(17)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_113_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_113_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_113_RANGE                  17:17
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_113_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_113_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_113_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_113_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_113_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_114_SHIFT                  _MK_SHIFT_CONST(18)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_114_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_114_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_114_RANGE                  18:18
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_114_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_114_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_114_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_114_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_114_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_115_SHIFT                  _MK_SHIFT_CONST(19)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_115_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_115_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_115_RANGE                  19:19
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_115_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_115_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_115_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_115_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_115_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_116_SHIFT                  _MK_SHIFT_CONST(20)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_116_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_116_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_116_RANGE                  20:20
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_116_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_116_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_116_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_116_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_116_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_117_SHIFT                  _MK_SHIFT_CONST(21)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_117_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_117_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_117_RANGE                  21:21
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_117_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_117_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_117_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_117_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_117_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_118_SHIFT                  _MK_SHIFT_CONST(22)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_118_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_118_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_118_RANGE                  22:22
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_118_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_118_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_118_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_118_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_118_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_119_SHIFT                  _MK_SHIFT_CONST(23)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_119_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_119_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_119_RANGE                  23:23
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_119_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_119_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_119_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_119_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_119_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_120_SHIFT                  _MK_SHIFT_CONST(24)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_120_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_120_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_120_RANGE                  24:24
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_120_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_120_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_120_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_120_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_120_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_121_SHIFT                  _MK_SHIFT_CONST(25)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_121_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_121_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_121_RANGE                  25:25
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_121_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_121_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_121_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_121_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_121_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_122_SHIFT                  _MK_SHIFT_CONST(26)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_122_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_122_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_122_RANGE                  26:26
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_122_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_122_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_122_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_122_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_122_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_123_SHIFT                  _MK_SHIFT_CONST(27)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_123_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_123_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_123_RANGE                  27:27
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_123_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_123_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_123_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_123_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_123_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_124_SHIFT                  _MK_SHIFT_CONST(28)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_124_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_124_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_124_RANGE                  28:28
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_124_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_124_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_124_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_124_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_124_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_125_SHIFT                  _MK_SHIFT_CONST(29)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_125_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_125_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_125_RANGE                  29:29
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_125_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_125_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_125_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_125_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_125_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_126_SHIFT                  _MK_SHIFT_CONST(30)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_126_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_126_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_126_RANGE                  30:30
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_126_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_126_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_126_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_126_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_126_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_127_SHIFT                  _MK_SHIFT_CONST(31)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_127_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_127_SHIFT)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_127_RANGE                  31:31
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_127_WOFFSET                        0x0
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_127_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_127_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_127_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_ACTIVE_STATUS_4_0_ACTIVE_STATUS_SPI_127_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 4884 [0x1314] 
+
+// Reserved address 4888 [0x1318] 
+
+// Reserved address 4892 [0x131c] 
+
+// Reserved address 4896 [0x1320] 
+
+// Reserved address 4900 [0x1324] 
+
+// Reserved address 4904 [0x1328] 
+
+// Reserved address 4908 [0x132c] 
+
+// Reserved address 4912 [0x1330] 
+
+// Reserved address 4916 [0x1334] 
+
+// Reserved address 4920 [0x1338] 
+
+// Reserved address 4924 [0x133c] 
+
+// Reserved address 4928 [0x1340] 
+
+// Reserved address 4932 [0x1344] 
+
+// Reserved address 4936 [0x1348] 
+
+// Reserved address 4940 [0x134c] 
+
+// Reserved address 4944 [0x1350] 
+
+// Reserved address 4948 [0x1354] 
+
+// Reserved address 4952 [0x1358] 
+
+// Reserved address 4956 [0x135c] 
+
+// Reserved address 4960 [0x1360] 
+
+// Reserved address 4964 [0x1364] 
+
+// Reserved address 4968 [0x1368] 
+
+// Reserved address 4972 [0x136c] 
+
+// Reserved address 4976 [0x1370] 
+
+// Reserved address 4980 [0x1374] 
+
+// Reserved address 4984 [0x1378] 
+
+// Reserved address 4988 [0x137c] 
+
+// Reserved address 4992 [0x1380] 
+
+// Reserved address 4996 [0x1384] 
+
+// Reserved address 5000 [0x1388] 
+
+// Reserved address 5004 [0x138c] 
+
+// Reserved address 5008 [0x1390] 
+
+// Reserved address 5012 [0x1394] 
+
+// Reserved address 5016 [0x1398] 
+
+// Reserved address 5020 [0x139c] 
+
+// Reserved address 5024 [0x13a0] 
+
+// Reserved address 5028 [0x13a4] 
+
+// Reserved address 5032 [0x13a8] 
+
+// Reserved address 5036 [0x13ac] 
+
+// Reserved address 5040 [0x13b0] 
+
+// Reserved address 5044 [0x13b4] 
+
+// Reserved address 5048 [0x13b8] 
+
+// Reserved address 5052 [0x13bc] 
+
+// Reserved address 5056 [0x13c0] 
+
+// Reserved address 5060 [0x13c4] 
+
+// Reserved address 5064 [0x13c8] 
+
+// Reserved address 5068 [0x13cc] 
+
+// Reserved address 5072 [0x13d0] 
+
+// Reserved address 5076 [0x13d4] 
+
+// Reserved address 5080 [0x13d8] 
+
+// Reserved address 5084 [0x13dc] 
+
+// Reserved address 5088 [0x13e0] 
+
+// Reserved address 5092 [0x13e4] 
+
+// Reserved address 5096 [0x13e8] 
+
+// Reserved address 5100 [0x13ec] 
+
+// Reserved address 5104 [0x13f0] 
+
+// Reserved address 5108 [0x13f4] 
+
+// Reserved address 5112 [0x13f8] 
+
+// Reserved address 5116 [0x13fc] 
+
+// Register FIC_DIST_PRIORITY_LEVEL_0_0  
+#define FIC_DIST_PRIORITY_LEVEL_0_0                     _MK_ADDR_CONST(0x1400)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_SECURE                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_0_0_WORD_COUNT                  0x1
+#define FIC_DIST_PRIORITY_LEVEL_0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_RESET_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_READ_MASK                   _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_WRITE_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_0_SHIFT                  _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_0_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_0_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_0_RANGE                  7:3
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_0_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_1_SHIFT                  _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_1_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_1_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_1_RANGE                  15:11
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_1_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_2_SHIFT                  _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_2_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_2_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_2_RANGE                  23:19
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_2_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_3_SHIFT                  _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_3_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_3_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_3_RANGE                  31:27
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_3_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_0_0_PRIORITY_LEVEL_STI_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_1_0  
+#define FIC_DIST_PRIORITY_LEVEL_1_0                     _MK_ADDR_CONST(0x1404)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_SECURE                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_1_0_WORD_COUNT                  0x1
+#define FIC_DIST_PRIORITY_LEVEL_1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_RESET_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_READ_MASK                   _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_WRITE_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_4_SHIFT                  _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_4_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_4_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_4_RANGE                  7:3
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_4_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_5_SHIFT                  _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_5_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_5_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_5_RANGE                  15:11
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_5_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_6_SHIFT                  _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_6_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_6_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_6_RANGE                  23:19
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_6_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_7_SHIFT                  _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_7_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_7_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_7_RANGE                  31:27
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_7_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_1_0_PRIORITY_LEVEL_STI_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_2_0  
+#define FIC_DIST_PRIORITY_LEVEL_2_0                     _MK_ADDR_CONST(0x1408)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_SECURE                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_2_0_WORD_COUNT                  0x1
+#define FIC_DIST_PRIORITY_LEVEL_2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_RESET_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_READ_MASK                   _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_WRITE_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_8_SHIFT                  _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_8_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_8_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_8_RANGE                  7:3
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_8_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_8_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_9_SHIFT                  _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_9_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_9_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_9_RANGE                  15:11
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_9_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_9_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_10_SHIFT                 _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_10_FIELD                 (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_10_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_10_RANGE                 23:19
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_10_WOFFSET                       0x0
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_10_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_11_SHIFT                 _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_11_FIELD                 (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_11_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_11_RANGE                 31:27
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_11_WOFFSET                       0x0
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_11_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_2_0_PRIORITY_LEVEL_STI_11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_3_0  
+#define FIC_DIST_PRIORITY_LEVEL_3_0                     _MK_ADDR_CONST(0x140c)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_SECURE                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_3_0_WORD_COUNT                  0x1
+#define FIC_DIST_PRIORITY_LEVEL_3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_RESET_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_READ_MASK                   _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_WRITE_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_12_SHIFT                 _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_12_FIELD                 (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_12_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_12_RANGE                 7:3
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_12_WOFFSET                       0x0
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_12_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_13_SHIFT                 _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_13_FIELD                 (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_13_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_13_RANGE                 15:11
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_13_WOFFSET                       0x0
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_13_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_14_SHIFT                 _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_14_FIELD                 (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_14_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_14_RANGE                 23:19
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_14_WOFFSET                       0x0
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_14_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_15_SHIFT                 _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_15_FIELD                 (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_15_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_15_RANGE                 31:27
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_15_WOFFSET                       0x0
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_15_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_3_0_PRIORITY_LEVEL_STI_15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 5136 [0x1410] 
+
+// Reserved address 5140 [0x1414] 
+
+// Register FIC_DIST_PRIORITY_LEVEL_6_0  
+#define FIC_DIST_PRIORITY_LEVEL_6_0                     _MK_ADDR_CONST(0x1418)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_SECURE                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_6_0_WORD_COUNT                  0x1
+#define FIC_DIST_PRIORITY_LEVEL_6_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_RESET_MASK                  _MK_MASK_CONST(0xf8000000)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_READ_MASK                   _MK_MASK_CONST(0xf8000000)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_WRITE_MASK                  _MK_MASK_CONST(0xf8000000)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_PRIORITY_LEVEL_PPI_4_SHIFT                  _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_PRIORITY_LEVEL_PPI_4_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_6_0_PRIORITY_LEVEL_PPI_4_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_PRIORITY_LEVEL_PPI_4_RANGE                  31:27
+#define FIC_DIST_PRIORITY_LEVEL_6_0_PRIORITY_LEVEL_PPI_4_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_6_0_PRIORITY_LEVEL_PPI_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_PRIORITY_LEVEL_PPI_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_PRIORITY_LEVEL_PPI_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_6_0_PRIORITY_LEVEL_PPI_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_7_0  
+#define FIC_DIST_PRIORITY_LEVEL_7_0                     _MK_ADDR_CONST(0x141c)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_SECURE                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_7_0_WORD_COUNT                  0x1
+#define FIC_DIST_PRIORITY_LEVEL_7_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_RESET_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_READ_MASK                   _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_WRITE_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_0_SHIFT                  _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_0_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_0_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_0_RANGE                  7:3
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_0_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_1_SHIFT                  _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_1_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_1_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_1_RANGE                  15:11
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_1_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_2_SHIFT                  _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_2_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_2_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_2_RANGE                  23:19
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_2_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_3_SHIFT                  _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_3_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_3_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_3_RANGE                  31:27
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_3_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_7_0_PRIORITY_LEVEL_PPI_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_8_0  
+#define FIC_DIST_PRIORITY_LEVEL_8_0                     _MK_ADDR_CONST(0x1420)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_SECURE                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_8_0_WORD_COUNT                  0x1
+#define FIC_DIST_PRIORITY_LEVEL_8_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_RESET_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_READ_MASK                   _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_WRITE_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_0_SHIFT                  _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_0_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_0_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_0_RANGE                  7:3
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_0_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_1_SHIFT                  _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_1_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_1_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_1_RANGE                  15:11
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_1_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_2_SHIFT                  _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_2_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_2_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_2_RANGE                  23:19
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_2_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_3_SHIFT                  _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_3_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_3_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_3_RANGE                  31:27
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_3_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_8_0_PRIORITY_LEVEL_SPI_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_9_0  
+#define FIC_DIST_PRIORITY_LEVEL_9_0                     _MK_ADDR_CONST(0x1424)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_SECURE                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_9_0_WORD_COUNT                  0x1
+#define FIC_DIST_PRIORITY_LEVEL_9_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_RESET_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_READ_MASK                   _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_WRITE_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_4_SHIFT                  _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_4_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_4_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_4_RANGE                  7:3
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_4_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_5_SHIFT                  _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_5_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_5_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_5_RANGE                  15:11
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_5_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_6_SHIFT                  _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_6_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_6_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_6_RANGE                  23:19
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_6_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_7_SHIFT                  _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_7_FIELD                  (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_7_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_7_RANGE                  31:27
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_7_WOFFSET                        0x0
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_9_0_PRIORITY_LEVEL_SPI_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_10_0  
+#define FIC_DIST_PRIORITY_LEVEL_10_0                    _MK_ADDR_CONST(0x1428)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_10_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_10_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_8_SHIFT                 _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_8_FIELD                 (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_8_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_8_RANGE                 7:3
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_8_WOFFSET                       0x0
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_8_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_9_SHIFT                 _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_9_FIELD                 (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_9_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_9_RANGE                 15:11
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_9_WOFFSET                       0x0
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_9_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_10_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_10_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_10_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_10_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_10_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_10_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_11_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_11_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_11_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_11_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_11_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_11_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_10_0_PRIORITY_LEVEL_SPI_11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_11_0  
+#define FIC_DIST_PRIORITY_LEVEL_11_0                    _MK_ADDR_CONST(0x142c)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_11_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_11_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_12_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_12_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_12_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_12_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_12_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_12_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_13_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_13_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_13_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_13_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_13_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_13_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_14_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_14_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_14_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_14_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_14_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_14_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_15_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_15_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_15_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_15_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_15_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_15_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_11_0_PRIORITY_LEVEL_SPI_15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_12_0  
+#define FIC_DIST_PRIORITY_LEVEL_12_0                    _MK_ADDR_CONST(0x1430)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_12_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_12_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_16_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_16_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_16_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_16_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_16_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_16_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_16_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_16_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_16_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_17_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_17_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_17_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_17_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_17_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_17_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_17_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_17_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_17_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_18_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_18_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_18_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_18_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_18_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_18_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_18_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_18_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_18_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_19_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_19_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_19_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_19_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_19_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_19_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_19_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_19_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_12_0_PRIORITY_LEVEL_SPI_19_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_13_0  
+#define FIC_DIST_PRIORITY_LEVEL_13_0                    _MK_ADDR_CONST(0x1434)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_13_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_13_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_20_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_20_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_20_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_20_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_20_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_20_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_20_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_20_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_20_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_21_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_21_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_21_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_21_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_21_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_21_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_21_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_21_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_21_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_22_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_22_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_22_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_22_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_22_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_22_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_22_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_22_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_22_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_23_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_23_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_23_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_23_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_23_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_23_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_23_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_23_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_13_0_PRIORITY_LEVEL_SPI_23_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_14_0  
+#define FIC_DIST_PRIORITY_LEVEL_14_0                    _MK_ADDR_CONST(0x1438)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_14_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_14_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_24_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_24_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_24_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_24_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_24_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_24_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_24_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_24_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_24_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_25_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_25_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_25_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_25_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_25_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_25_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_25_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_25_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_25_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_26_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_26_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_26_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_26_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_26_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_26_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_26_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_26_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_26_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_27_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_27_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_27_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_27_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_27_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_27_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_27_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_27_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_14_0_PRIORITY_LEVEL_SPI_27_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_15_0  
+#define FIC_DIST_PRIORITY_LEVEL_15_0                    _MK_ADDR_CONST(0x143c)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_15_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_15_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_28_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_28_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_28_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_28_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_28_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_28_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_28_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_28_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_28_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_29_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_29_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_29_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_29_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_29_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_29_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_29_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_29_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_29_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_30_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_30_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_30_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_30_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_30_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_30_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_30_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_30_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_30_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_31_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_31_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_31_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_31_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_31_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_31_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_31_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_31_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_15_0_PRIORITY_LEVEL_SPI_31_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_16_0  
+#define FIC_DIST_PRIORITY_LEVEL_16_0                    _MK_ADDR_CONST(0x1440)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_16_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_16_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_32_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_32_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_32_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_32_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_32_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_32_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_32_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_32_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_32_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_33_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_33_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_33_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_33_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_33_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_33_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_33_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_33_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_33_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_34_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_34_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_34_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_34_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_34_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_34_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_34_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_34_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_34_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_35_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_35_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_35_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_35_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_35_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_35_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_35_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_35_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_16_0_PRIORITY_LEVEL_SPI_35_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_17_0  
+#define FIC_DIST_PRIORITY_LEVEL_17_0                    _MK_ADDR_CONST(0x1444)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_17_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_17_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_36_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_36_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_36_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_36_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_36_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_36_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_36_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_36_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_36_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_37_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_37_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_37_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_37_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_37_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_37_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_37_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_37_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_37_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_38_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_38_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_38_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_38_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_38_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_38_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_38_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_38_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_38_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_39_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_39_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_39_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_39_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_39_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_39_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_39_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_39_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_17_0_PRIORITY_LEVEL_SPI_39_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_18_0  
+#define FIC_DIST_PRIORITY_LEVEL_18_0                    _MK_ADDR_CONST(0x1448)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_18_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_18_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_40_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_40_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_40_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_40_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_40_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_40_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_40_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_40_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_40_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_41_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_41_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_41_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_41_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_41_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_41_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_41_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_41_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_41_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_42_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_42_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_42_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_42_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_42_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_42_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_42_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_42_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_42_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_43_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_43_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_43_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_43_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_43_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_43_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_43_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_43_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_18_0_PRIORITY_LEVEL_SPI_43_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_19_0  
+#define FIC_DIST_PRIORITY_LEVEL_19_0                    _MK_ADDR_CONST(0x144c)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_19_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_19_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_44_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_44_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_44_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_44_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_44_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_44_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_44_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_44_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_44_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_45_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_45_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_45_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_45_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_45_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_45_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_45_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_45_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_45_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_46_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_46_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_46_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_46_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_46_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_46_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_46_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_46_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_46_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_47_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_47_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_47_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_47_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_47_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_47_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_47_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_47_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_19_0_PRIORITY_LEVEL_SPI_47_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_20_0  
+#define FIC_DIST_PRIORITY_LEVEL_20_0                    _MK_ADDR_CONST(0x1450)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_20_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_20_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_48_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_48_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_48_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_48_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_48_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_48_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_48_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_48_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_48_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_49_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_49_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_49_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_49_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_49_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_49_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_49_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_49_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_49_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_50_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_50_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_50_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_50_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_50_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_50_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_50_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_50_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_50_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_51_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_51_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_51_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_51_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_51_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_51_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_51_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_51_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_20_0_PRIORITY_LEVEL_SPI_51_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_21_0  
+#define FIC_DIST_PRIORITY_LEVEL_21_0                    _MK_ADDR_CONST(0x1454)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_21_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_21_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_52_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_52_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_52_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_52_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_52_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_52_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_52_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_52_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_52_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_53_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_53_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_53_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_53_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_53_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_53_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_53_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_53_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_53_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_54_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_54_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_54_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_54_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_54_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_54_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_54_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_54_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_54_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_55_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_55_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_55_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_55_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_55_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_55_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_55_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_55_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_21_0_PRIORITY_LEVEL_SPI_55_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_22_0  
+#define FIC_DIST_PRIORITY_LEVEL_22_0                    _MK_ADDR_CONST(0x1458)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_22_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_22_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_56_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_56_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_56_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_56_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_56_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_56_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_56_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_56_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_56_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_57_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_57_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_57_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_57_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_57_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_57_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_57_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_57_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_57_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_58_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_58_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_58_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_58_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_58_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_58_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_58_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_58_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_58_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_59_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_59_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_59_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_59_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_59_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_59_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_59_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_59_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_22_0_PRIORITY_LEVEL_SPI_59_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_23_0  
+#define FIC_DIST_PRIORITY_LEVEL_23_0                    _MK_ADDR_CONST(0x145c)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_23_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_23_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_60_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_60_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_60_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_60_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_60_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_60_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_60_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_60_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_60_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_61_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_61_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_61_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_61_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_61_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_61_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_61_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_61_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_61_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_62_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_62_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_62_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_62_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_62_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_62_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_62_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_62_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_62_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_63_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_63_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_63_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_63_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_63_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_63_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_63_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_63_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_23_0_PRIORITY_LEVEL_SPI_63_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_24_0  
+#define FIC_DIST_PRIORITY_LEVEL_24_0                    _MK_ADDR_CONST(0x1460)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_24_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_24_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_64_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_64_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_64_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_64_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_64_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_64_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_64_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_64_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_64_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_65_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_65_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_65_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_65_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_65_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_65_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_65_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_65_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_65_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_66_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_66_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_66_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_66_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_66_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_66_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_66_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_66_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_66_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_67_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_67_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_67_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_67_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_67_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_67_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_67_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_67_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_24_0_PRIORITY_LEVEL_SPI_67_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_25_0  
+#define FIC_DIST_PRIORITY_LEVEL_25_0                    _MK_ADDR_CONST(0x1464)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_25_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_25_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_68_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_68_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_68_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_68_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_68_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_68_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_68_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_68_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_68_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_69_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_69_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_69_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_69_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_69_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_69_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_69_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_69_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_69_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_70_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_70_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_70_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_70_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_70_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_70_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_70_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_70_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_70_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_71_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_71_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_71_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_71_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_71_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_71_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_71_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_71_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_25_0_PRIORITY_LEVEL_SPI_71_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_26_0  
+#define FIC_DIST_PRIORITY_LEVEL_26_0                    _MK_ADDR_CONST(0x1468)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_26_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_26_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_72_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_72_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_72_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_72_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_72_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_72_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_72_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_72_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_72_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_73_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_73_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_73_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_73_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_73_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_73_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_73_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_73_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_73_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_74_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_74_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_74_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_74_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_74_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_74_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_74_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_74_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_74_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_75_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_75_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_75_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_75_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_75_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_75_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_75_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_75_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_26_0_PRIORITY_LEVEL_SPI_75_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_27_0  
+#define FIC_DIST_PRIORITY_LEVEL_27_0                    _MK_ADDR_CONST(0x146c)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_27_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_27_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_76_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_76_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_76_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_76_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_76_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_76_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_76_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_76_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_76_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_77_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_77_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_77_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_77_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_77_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_77_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_77_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_77_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_77_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_78_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_78_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_78_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_78_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_78_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_78_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_78_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_78_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_78_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_79_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_79_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_79_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_79_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_79_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_79_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_79_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_79_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_27_0_PRIORITY_LEVEL_SPI_79_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_28_0  
+#define FIC_DIST_PRIORITY_LEVEL_28_0                    _MK_ADDR_CONST(0x1470)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_28_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_28_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_80_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_80_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_80_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_80_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_80_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_80_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_80_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_80_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_80_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_81_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_81_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_81_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_81_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_81_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_81_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_81_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_81_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_81_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_82_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_82_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_82_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_82_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_82_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_82_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_82_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_82_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_82_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_83_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_83_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_83_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_83_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_83_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_83_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_83_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_83_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_28_0_PRIORITY_LEVEL_SPI_83_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_29_0  
+#define FIC_DIST_PRIORITY_LEVEL_29_0                    _MK_ADDR_CONST(0x1474)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_29_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_29_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_84_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_84_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_84_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_84_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_84_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_84_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_84_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_84_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_84_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_85_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_85_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_85_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_85_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_85_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_85_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_85_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_85_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_85_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_86_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_86_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_86_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_86_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_86_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_86_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_86_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_86_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_86_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_87_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_87_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_87_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_87_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_87_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_87_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_87_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_87_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_29_0_PRIORITY_LEVEL_SPI_87_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_30_0  
+#define FIC_DIST_PRIORITY_LEVEL_30_0                    _MK_ADDR_CONST(0x1478)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_30_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_30_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_88_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_88_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_88_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_88_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_88_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_88_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_88_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_88_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_88_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_89_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_89_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_89_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_89_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_89_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_89_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_89_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_89_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_89_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_90_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_90_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_90_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_90_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_90_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_90_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_90_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_90_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_90_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_91_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_91_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_91_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_91_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_91_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_91_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_91_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_91_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_30_0_PRIORITY_LEVEL_SPI_91_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_31_0  
+#define FIC_DIST_PRIORITY_LEVEL_31_0                    _MK_ADDR_CONST(0x147c)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_31_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_31_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_92_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_92_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_92_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_92_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_92_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_92_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_92_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_92_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_92_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_93_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_93_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_93_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_93_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_93_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_93_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_93_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_93_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_93_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_94_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_94_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_94_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_94_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_94_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_94_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_94_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_94_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_94_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_95_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_95_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_95_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_95_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_95_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_95_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_95_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_95_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_31_0_PRIORITY_LEVEL_SPI_95_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_32_0  
+#define FIC_DIST_PRIORITY_LEVEL_32_0                    _MK_ADDR_CONST(0x1480)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_32_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_32_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_96_SHIFT                        _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_96_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_96_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_96_RANGE                        7:3
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_96_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_96_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_96_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_96_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_96_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_97_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_97_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_97_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_97_RANGE                        15:11
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_97_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_97_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_97_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_97_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_97_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_98_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_98_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_98_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_98_RANGE                        23:19
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_98_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_98_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_98_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_98_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_98_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_99_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_99_FIELD                        (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_99_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_99_RANGE                        31:27
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_99_WOFFSET                      0x0
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_99_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_99_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_99_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_32_0_PRIORITY_LEVEL_SPI_99_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_33_0  
+#define FIC_DIST_PRIORITY_LEVEL_33_0                    _MK_ADDR_CONST(0x1484)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_33_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_33_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_100_SHIFT                       _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_100_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_100_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_100_RANGE                       7:3
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_100_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_100_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_100_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_100_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_100_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_101_SHIFT                       _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_101_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_101_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_101_RANGE                       15:11
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_101_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_101_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_101_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_101_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_101_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_102_SHIFT                       _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_102_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_102_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_102_RANGE                       23:19
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_102_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_102_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_102_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_102_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_102_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_103_SHIFT                       _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_103_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_103_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_103_RANGE                       31:27
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_103_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_103_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_103_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_103_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_33_0_PRIORITY_LEVEL_SPI_103_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_34_0  
+#define FIC_DIST_PRIORITY_LEVEL_34_0                    _MK_ADDR_CONST(0x1488)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_34_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_34_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_104_SHIFT                       _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_104_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_104_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_104_RANGE                       7:3
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_104_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_104_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_104_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_104_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_104_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_105_SHIFT                       _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_105_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_105_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_105_RANGE                       15:11
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_105_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_105_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_105_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_105_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_105_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_106_SHIFT                       _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_106_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_106_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_106_RANGE                       23:19
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_106_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_106_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_106_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_106_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_106_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_107_SHIFT                       _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_107_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_107_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_107_RANGE                       31:27
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_107_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_107_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_107_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_107_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_34_0_PRIORITY_LEVEL_SPI_107_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_35_0  
+#define FIC_DIST_PRIORITY_LEVEL_35_0                    _MK_ADDR_CONST(0x148c)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_35_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_35_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_108_SHIFT                       _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_108_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_108_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_108_RANGE                       7:3
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_108_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_108_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_108_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_108_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_108_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_109_SHIFT                       _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_109_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_109_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_109_RANGE                       15:11
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_109_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_109_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_109_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_109_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_109_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_110_SHIFT                       _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_110_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_110_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_110_RANGE                       23:19
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_110_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_110_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_110_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_110_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_110_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_111_SHIFT                       _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_111_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_111_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_111_RANGE                       31:27
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_111_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_111_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_111_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_111_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_35_0_PRIORITY_LEVEL_SPI_111_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_36_0  
+#define FIC_DIST_PRIORITY_LEVEL_36_0                    _MK_ADDR_CONST(0x1490)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_36_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_36_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_112_SHIFT                       _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_112_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_112_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_112_RANGE                       7:3
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_112_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_112_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_112_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_112_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_112_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_113_SHIFT                       _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_113_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_113_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_113_RANGE                       15:11
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_113_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_113_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_113_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_113_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_113_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_114_SHIFT                       _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_114_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_114_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_114_RANGE                       23:19
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_114_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_114_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_114_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_114_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_114_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_115_SHIFT                       _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_115_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_115_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_115_RANGE                       31:27
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_115_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_115_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_115_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_115_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_36_0_PRIORITY_LEVEL_SPI_115_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_37_0  
+#define FIC_DIST_PRIORITY_LEVEL_37_0                    _MK_ADDR_CONST(0x1494)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_37_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_37_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_116_SHIFT                       _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_116_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_116_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_116_RANGE                       7:3
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_116_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_116_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_116_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_116_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_116_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_117_SHIFT                       _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_117_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_117_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_117_RANGE                       15:11
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_117_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_117_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_117_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_117_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_117_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_118_SHIFT                       _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_118_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_118_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_118_RANGE                       23:19
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_118_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_118_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_118_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_118_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_118_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_119_SHIFT                       _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_119_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_119_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_119_RANGE                       31:27
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_119_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_119_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_119_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_119_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_37_0_PRIORITY_LEVEL_SPI_119_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_38_0  
+#define FIC_DIST_PRIORITY_LEVEL_38_0                    _MK_ADDR_CONST(0x1498)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_38_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_38_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_120_SHIFT                       _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_120_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_120_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_120_RANGE                       7:3
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_120_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_120_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_120_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_120_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_120_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_121_SHIFT                       _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_121_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_121_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_121_RANGE                       15:11
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_121_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_121_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_121_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_121_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_121_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_122_SHIFT                       _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_122_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_122_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_122_RANGE                       23:19
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_122_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_122_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_122_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_122_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_122_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_123_SHIFT                       _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_123_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_123_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_123_RANGE                       31:27
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_123_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_123_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_123_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_123_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_38_0_PRIORITY_LEVEL_SPI_123_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIORITY_LEVEL_39_0  
+#define FIC_DIST_PRIORITY_LEVEL_39_0                    _MK_ADDR_CONST(0x149c)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_SECURE                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_39_0_WORD_COUNT                         0x1
+#define FIC_DIST_PRIORITY_LEVEL_39_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_RESET_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_READ_MASK                  _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_WRITE_MASK                         _MK_MASK_CONST(0xf8f8f8f8)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_124_SHIFT                       _MK_SHIFT_CONST(3)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_124_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_124_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_124_RANGE                       7:3
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_124_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_124_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_124_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_124_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_124_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_125_SHIFT                       _MK_SHIFT_CONST(11)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_125_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_125_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_125_RANGE                       15:11
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_125_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_125_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_125_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_125_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_125_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_126_SHIFT                       _MK_SHIFT_CONST(19)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_126_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_126_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_126_RANGE                       23:19
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_126_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_126_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_126_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_126_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_126_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_127_SHIFT                       _MK_SHIFT_CONST(27)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_127_FIELD                       (_MK_MASK_CONST(0x1f) << FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_127_SHIFT)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_127_RANGE                       31:27
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_127_WOFFSET                     0x0
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_127_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_127_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_127_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIORITY_LEVEL_39_0_PRIORITY_LEVEL_SPI_127_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Reserved address 5280 [0x14a0] 
+
+// Reserved address 5284 [0x14a4] 
+
+// Reserved address 5288 [0x14a8] 
+
+// Reserved address 5292 [0x14ac] 
+
+// Reserved address 5296 [0x14b0] 
+
+// Reserved address 5300 [0x14b4] 
+
+// Reserved address 5304 [0x14b8] 
+
+// Reserved address 5308 [0x14bc] 
+
+// Reserved address 5312 [0x14c0] 
+
+// Reserved address 5316 [0x14c4] 
+
+// Reserved address 5320 [0x14c8] 
+
+// Reserved address 5324 [0x14cc] 
+
+// Reserved address 5328 [0x14d0] 
+
+// Reserved address 5332 [0x14d4] 
+
+// Reserved address 5336 [0x14d8] 
+
+// Reserved address 5340 [0x14dc] 
+
+// Reserved address 5344 [0x14e0] 
+
+// Reserved address 5348 [0x14e4] 
+
+// Reserved address 5352 [0x14e8] 
+
+// Reserved address 5356 [0x14ec] 
+
+// Reserved address 5360 [0x14f0] 
+
+// Reserved address 5364 [0x14f4] 
+
+// Reserved address 5368 [0x14f8] 
+
+// Reserved address 5372 [0x14fc] 
+
+// Reserved address 5376 [0x1500] 
+
+// Reserved address 5380 [0x1504] 
+
+// Reserved address 5384 [0x1508] 
+
+// Reserved address 5388 [0x150c] 
+
+// Reserved address 5392 [0x1510] 
+
+// Reserved address 5396 [0x1514] 
+
+// Reserved address 5400 [0x1518] 
+
+// Reserved address 5404 [0x151c] 
+
+// Reserved address 5408 [0x1520] 
+
+// Reserved address 5412 [0x1524] 
+
+// Reserved address 5416 [0x1528] 
+
+// Reserved address 5420 [0x152c] 
+
+// Reserved address 5424 [0x1530] 
+
+// Reserved address 5428 [0x1534] 
+
+// Reserved address 5432 [0x1538] 
+
+// Reserved address 5436 [0x153c] 
+
+// Reserved address 5440 [0x1540] 
+
+// Reserved address 5444 [0x1544] 
+
+// Reserved address 5448 [0x1548] 
+
+// Reserved address 5452 [0x154c] 
+
+// Reserved address 5456 [0x1550] 
+
+// Reserved address 5460 [0x1554] 
+
+// Reserved address 5464 [0x1558] 
+
+// Reserved address 5468 [0x155c] 
+
+// Reserved address 5472 [0x1560] 
+
+// Reserved address 5476 [0x1564] 
+
+// Reserved address 5480 [0x1568] 
+
+// Reserved address 5484 [0x156c] 
+
+// Reserved address 5488 [0x1570] 
+
+// Reserved address 5492 [0x1574] 
+
+// Reserved address 5496 [0x1578] 
+
+// Reserved address 5500 [0x157c] 
+
+// Reserved address 5504 [0x1580] 
+
+// Reserved address 5508 [0x1584] 
+
+// Reserved address 5512 [0x1588] 
+
+// Reserved address 5516 [0x158c] 
+
+// Reserved address 5520 [0x1590] 
+
+// Reserved address 5524 [0x1594] 
+
+// Reserved address 5528 [0x1598] 
+
+// Reserved address 5532 [0x159c] 
+
+// Reserved address 5536 [0x15a0] 
+
+// Reserved address 5540 [0x15a4] 
+
+// Reserved address 5544 [0x15a8] 
+
+// Reserved address 5548 [0x15ac] 
+
+// Reserved address 5552 [0x15b0] 
+
+// Reserved address 5556 [0x15b4] 
+
+// Reserved address 5560 [0x15b8] 
+
+// Reserved address 5564 [0x15bc] 
+
+// Reserved address 5568 [0x15c0] 
+
+// Reserved address 5572 [0x15c4] 
+
+// Reserved address 5576 [0x15c8] 
+
+// Reserved address 5580 [0x15cc] 
+
+// Reserved address 5584 [0x15d0] 
+
+// Reserved address 5588 [0x15d4] 
+
+// Reserved address 5592 [0x15d8] 
+
+// Reserved address 5596 [0x15dc] 
+
+// Reserved address 5600 [0x15e0] 
+
+// Reserved address 5604 [0x15e4] 
+
+// Reserved address 5608 [0x15e8] 
+
+// Reserved address 5612 [0x15ec] 
+
+// Reserved address 5616 [0x15f0] 
+
+// Reserved address 5620 [0x15f4] 
+
+// Reserved address 5624 [0x15f8] 
+
+// Reserved address 5628 [0x15fc] 
+
+// Reserved address 5632 [0x1600] 
+
+// Reserved address 5636 [0x1604] 
+
+// Reserved address 5640 [0x1608] 
+
+// Reserved address 5644 [0x160c] 
+
+// Reserved address 5648 [0x1610] 
+
+// Reserved address 5652 [0x1614] 
+
+// Reserved address 5656 [0x1618] 
+
+// Reserved address 5660 [0x161c] 
+
+// Reserved address 5664 [0x1620] 
+
+// Reserved address 5668 [0x1624] 
+
+// Reserved address 5672 [0x1628] 
+
+// Reserved address 5676 [0x162c] 
+
+// Reserved address 5680 [0x1630] 
+
+// Reserved address 5684 [0x1634] 
+
+// Reserved address 5688 [0x1638] 
+
+// Reserved address 5692 [0x163c] 
+
+// Reserved address 5696 [0x1640] 
+
+// Reserved address 5700 [0x1644] 
+
+// Reserved address 5704 [0x1648] 
+
+// Reserved address 5708 [0x164c] 
+
+// Reserved address 5712 [0x1650] 
+
+// Reserved address 5716 [0x1654] 
+
+// Reserved address 5720 [0x1658] 
+
+// Reserved address 5724 [0x165c] 
+
+// Reserved address 5728 [0x1660] 
+
+// Reserved address 5732 [0x1664] 
+
+// Reserved address 5736 [0x1668] 
+
+// Reserved address 5740 [0x166c] 
+
+// Reserved address 5744 [0x1670] 
+
+// Reserved address 5748 [0x1674] 
+
+// Reserved address 5752 [0x1678] 
+
+// Reserved address 5756 [0x167c] 
+
+// Reserved address 5760 [0x1680] 
+
+// Reserved address 5764 [0x1684] 
+
+// Reserved address 5768 [0x1688] 
+
+// Reserved address 5772 [0x168c] 
+
+// Reserved address 5776 [0x1690] 
+
+// Reserved address 5780 [0x1694] 
+
+// Reserved address 5784 [0x1698] 
+
+// Reserved address 5788 [0x169c] 
+
+// Reserved address 5792 [0x16a0] 
+
+// Reserved address 5796 [0x16a4] 
+
+// Reserved address 5800 [0x16a8] 
+
+// Reserved address 5804 [0x16ac] 
+
+// Reserved address 5808 [0x16b0] 
+
+// Reserved address 5812 [0x16b4] 
+
+// Reserved address 5816 [0x16b8] 
+
+// Reserved address 5820 [0x16bc] 
+
+// Reserved address 5824 [0x16c0] 
+
+// Reserved address 5828 [0x16c4] 
+
+// Reserved address 5832 [0x16c8] 
+
+// Reserved address 5836 [0x16cc] 
+
+// Reserved address 5840 [0x16d0] 
+
+// Reserved address 5844 [0x16d4] 
+
+// Reserved address 5848 [0x16d8] 
+
+// Reserved address 5852 [0x16dc] 
+
+// Reserved address 5856 [0x16e0] 
+
+// Reserved address 5860 [0x16e4] 
+
+// Reserved address 5864 [0x16e8] 
+
+// Reserved address 5868 [0x16ec] 
+
+// Reserved address 5872 [0x16f0] 
+
+// Reserved address 5876 [0x16f4] 
+
+// Reserved address 5880 [0x16f8] 
+
+// Reserved address 5884 [0x16fc] 
+
+// Reserved address 5888 [0x1700] 
+
+// Reserved address 5892 [0x1704] 
+
+// Reserved address 5896 [0x1708] 
+
+// Reserved address 5900 [0x170c] 
+
+// Reserved address 5904 [0x1710] 
+
+// Reserved address 5908 [0x1714] 
+
+// Reserved address 5912 [0x1718] 
+
+// Reserved address 5916 [0x171c] 
+
+// Reserved address 5920 [0x1720] 
+
+// Reserved address 5924 [0x1724] 
+
+// Reserved address 5928 [0x1728] 
+
+// Reserved address 5932 [0x172c] 
+
+// Reserved address 5936 [0x1730] 
+
+// Reserved address 5940 [0x1734] 
+
+// Reserved address 5944 [0x1738] 
+
+// Reserved address 5948 [0x173c] 
+
+// Reserved address 5952 [0x1740] 
+
+// Reserved address 5956 [0x1744] 
+
+// Reserved address 5960 [0x1748] 
+
+// Reserved address 5964 [0x174c] 
+
+// Reserved address 5968 [0x1750] 
+
+// Reserved address 5972 [0x1754] 
+
+// Reserved address 5976 [0x1758] 
+
+// Reserved address 5980 [0x175c] 
+
+// Reserved address 5984 [0x1760] 
+
+// Reserved address 5988 [0x1764] 
+
+// Reserved address 5992 [0x1768] 
+
+// Reserved address 5996 [0x176c] 
+
+// Reserved address 6000 [0x1770] 
+
+// Reserved address 6004 [0x1774] 
+
+// Reserved address 6008 [0x1778] 
+
+// Reserved address 6012 [0x177c] 
+
+// Reserved address 6016 [0x1780] 
+
+// Reserved address 6020 [0x1784] 
+
+// Reserved address 6024 [0x1788] 
+
+// Reserved address 6028 [0x178c] 
+
+// Reserved address 6032 [0x1790] 
+
+// Reserved address 6036 [0x1794] 
+
+// Reserved address 6040 [0x1798] 
+
+// Reserved address 6044 [0x179c] 
+
+// Reserved address 6048 [0x17a0] 
+
+// Reserved address 6052 [0x17a4] 
+
+// Reserved address 6056 [0x17a8] 
+
+// Reserved address 6060 [0x17ac] 
+
+// Reserved address 6064 [0x17b0] 
+
+// Reserved address 6068 [0x17b4] 
+
+// Reserved address 6072 [0x17b8] 
+
+// Reserved address 6076 [0x17bc] 
+
+// Reserved address 6080 [0x17c0] 
+
+// Reserved address 6084 [0x17c4] 
+
+// Reserved address 6088 [0x17c8] 
+
+// Reserved address 6092 [0x17cc] 
+
+// Reserved address 6096 [0x17d0] 
+
+// Reserved address 6100 [0x17d4] 
+
+// Reserved address 6104 [0x17d8] 
+
+// Reserved address 6108 [0x17dc] 
+
+// Reserved address 6112 [0x17e0] 
+
+// Reserved address 6116 [0x17e4] 
+
+// Reserved address 6120 [0x17e8] 
+
+// Reserved address 6124 [0x17ec] 
+
+// Reserved address 6128 [0x17f0] 
+
+// Reserved address 6132 [0x17f4] 
+
+// Reserved address 6136 [0x17f8] 
+
+// Reserved address 6140 [0x17fc] 
+
+// Register FIC_DIST_SPI_TARGET_0_0  
+#define FIC_DIST_SPI_TARGET_0_0                 _MK_ADDR_CONST(0x1800)
+#define FIC_DIST_SPI_TARGET_0_0_SECURE                  0x0
+#define FIC_DIST_SPI_TARGET_0_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_TARGET_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_0_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU0_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU0_RANGE                     0:0
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU1_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU1_RANGE                     1:1
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_0_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU0_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU0_RANGE                     8:8
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU1_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU1_RANGE                     9:9
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_1_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU0_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU0_RANGE                     16:16
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU1_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU1_RANGE                     17:17
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_2_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU0_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU0_RANGE                     24:24
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU1_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU1_RANGE                     25:25
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_0_0_SPI_TARGET_STI_3_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_1_0  
+#define FIC_DIST_SPI_TARGET_1_0                 _MK_ADDR_CONST(0x1804)
+#define FIC_DIST_SPI_TARGET_1_0_SECURE                  0x0
+#define FIC_DIST_SPI_TARGET_1_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_TARGET_1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_1_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU0_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU0_RANGE                     0:0
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU1_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU1_RANGE                     1:1
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_4_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU0_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU0_RANGE                     8:8
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU1_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU1_RANGE                     9:9
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_5_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU0_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU0_RANGE                     16:16
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU1_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU1_RANGE                     17:17
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_6_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU0_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU0_RANGE                     24:24
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU1_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU1_RANGE                     25:25
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_1_0_SPI_TARGET_STI_7_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_2_0  
+#define FIC_DIST_SPI_TARGET_2_0                 _MK_ADDR_CONST(0x1808)
+#define FIC_DIST_SPI_TARGET_2_0_SECURE                  0x0
+#define FIC_DIST_SPI_TARGET_2_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_TARGET_2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_2_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU0_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU0_RANGE                     0:0
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU1_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU1_RANGE                     1:1
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_8_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU0_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU0_RANGE                     8:8
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU1_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU1_RANGE                     9:9
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_9_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU0_SHIFT                    _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU0_RANGE                    16:16
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU1_SHIFT                    _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU1_RANGE                    17:17
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_10_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU0_SHIFT                    _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU0_RANGE                    24:24
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU1_SHIFT                    _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU1_RANGE                    25:25
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_2_0_SPI_TARGET_STI_11_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_3_0  
+#define FIC_DIST_SPI_TARGET_3_0                 _MK_ADDR_CONST(0x180c)
+#define FIC_DIST_SPI_TARGET_3_0_SECURE                  0x0
+#define FIC_DIST_SPI_TARGET_3_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_TARGET_3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_3_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU0_RANGE                    0:0
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU1_SHIFT                    _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU1_RANGE                    1:1
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_12_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU0_SHIFT                    _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU0_RANGE                    8:8
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU1_SHIFT                    _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU1_RANGE                    9:9
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_13_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU0_SHIFT                    _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU0_RANGE                    16:16
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU1_SHIFT                    _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU1_RANGE                    17:17
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_14_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU0_SHIFT                    _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU0_RANGE                    24:24
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU1_SHIFT                    _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU1_RANGE                    25:25
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_3_0_SPI_TARGET_STI_15_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 6160 [0x1810] 
+
+// Reserved address 6164 [0x1814] 
+
+// Reserved address 6168 [0x1818] 
+
+// Reserved address 6172 [0x181c] 
+
+// Register FIC_DIST_SPI_TARGET_4_0  
+#define FIC_DIST_SPI_TARGET_4_0                 _MK_ADDR_CONST(0x1820)
+#define FIC_DIST_SPI_TARGET_4_0_SECURE                  0x0
+#define FIC_DIST_SPI_TARGET_4_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_TARGET_4_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_4_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU0_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU0_RANGE                     0:0
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU1_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU1_RANGE                     1:1
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_0_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU0_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU0_RANGE                     8:8
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU1_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU1_RANGE                     9:9
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_1_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU0_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU0_RANGE                     16:16
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU1_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU1_RANGE                     17:17
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_2_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU0_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU0_RANGE                     24:24
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU1_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU1_RANGE                     25:25
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_4_0_SPI_TARGET_SPI_3_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_5_0  
+#define FIC_DIST_SPI_TARGET_5_0                 _MK_ADDR_CONST(0x1824)
+#define FIC_DIST_SPI_TARGET_5_0_SECURE                  0x0
+#define FIC_DIST_SPI_TARGET_5_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_TARGET_5_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_5_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU0_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU0_RANGE                     0:0
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU1_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU1_RANGE                     1:1
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_4_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU0_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU0_RANGE                     8:8
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU1_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU1_RANGE                     9:9
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_5_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU0_SHIFT                     _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU0_RANGE                     16:16
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU1_SHIFT                     _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU1_RANGE                     17:17
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_6_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU0_SHIFT                     _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU0_RANGE                     24:24
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU1_SHIFT                     _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU1_RANGE                     25:25
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_5_0_SPI_TARGET_SPI_7_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_6_0  
+#define FIC_DIST_SPI_TARGET_6_0                 _MK_ADDR_CONST(0x1828)
+#define FIC_DIST_SPI_TARGET_6_0_SECURE                  0x0
+#define FIC_DIST_SPI_TARGET_6_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_TARGET_6_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_6_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU0_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU0_RANGE                     0:0
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU1_SHIFT                     _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU1_RANGE                     1:1
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_8_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU0_SHIFT                     _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU0_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU0_RANGE                     8:8
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU0_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU1_SHIFT                     _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU1_FIELD                     (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU1_RANGE                     9:9
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU1_WOFFSET                   0x0
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_9_CPU1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU0_SHIFT                    _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU0_RANGE                    16:16
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU1_SHIFT                    _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU1_RANGE                    17:17
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_10_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU0_SHIFT                    _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU0_RANGE                    24:24
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU1_SHIFT                    _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU1_RANGE                    25:25
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_6_0_SPI_TARGET_SPI_11_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_7_0  
+#define FIC_DIST_SPI_TARGET_7_0                 _MK_ADDR_CONST(0x182c)
+#define FIC_DIST_SPI_TARGET_7_0_SECURE                  0x0
+#define FIC_DIST_SPI_TARGET_7_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_TARGET_7_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_7_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU0_RANGE                    0:0
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU1_SHIFT                    _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU1_RANGE                    1:1
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_12_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU0_SHIFT                    _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU0_RANGE                    8:8
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU1_SHIFT                    _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU1_RANGE                    9:9
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_13_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU0_SHIFT                    _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU0_RANGE                    16:16
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU1_SHIFT                    _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU1_RANGE                    17:17
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_14_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU0_SHIFT                    _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU0_RANGE                    24:24
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU1_SHIFT                    _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU1_RANGE                    25:25
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_7_0_SPI_TARGET_SPI_15_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_8_0  
+#define FIC_DIST_SPI_TARGET_8_0                 _MK_ADDR_CONST(0x1830)
+#define FIC_DIST_SPI_TARGET_8_0_SECURE                  0x0
+#define FIC_DIST_SPI_TARGET_8_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_TARGET_8_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_8_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_8_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU0_RANGE                    0:0
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU1_SHIFT                    _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU1_RANGE                    1:1
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_16_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU0_SHIFT                    _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU0_RANGE                    8:8
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU1_SHIFT                    _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU1_RANGE                    9:9
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_17_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU0_SHIFT                    _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU0_RANGE                    16:16
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU1_SHIFT                    _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU1_RANGE                    17:17
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_18_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU0_SHIFT                    _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU0_RANGE                    24:24
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU1_SHIFT                    _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU1_RANGE                    25:25
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_8_0_SPI_TARGET_SPI_19_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_9_0  
+#define FIC_DIST_SPI_TARGET_9_0                 _MK_ADDR_CONST(0x1834)
+#define FIC_DIST_SPI_TARGET_9_0_SECURE                  0x0
+#define FIC_DIST_SPI_TARGET_9_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_TARGET_9_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_RESET_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_9_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_READ_MASK                       _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_9_0_WRITE_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU0_RANGE                    0:0
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU1_SHIFT                    _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU1_RANGE                    1:1
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_20_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU0_SHIFT                    _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU0_RANGE                    8:8
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU1_SHIFT                    _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU1_RANGE                    9:9
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_21_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU0_SHIFT                    _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU0_RANGE                    16:16
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU1_SHIFT                    _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU1_RANGE                    17:17
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_22_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU0_SHIFT                    _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU0_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU0_RANGE                    24:24
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU0_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU1_SHIFT                    _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU1_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU1_RANGE                    25:25
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU1_WOFFSET                  0x0
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_9_0_SPI_TARGET_SPI_23_CPU1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_10_0  
+#define FIC_DIST_SPI_TARGET_10_0                        _MK_ADDR_CONST(0x1838)
+#define FIC_DIST_SPI_TARGET_10_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_10_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_10_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_10_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_10_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_24_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_25_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_26_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_10_0_SPI_TARGET_SPI_27_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_11_0  
+#define FIC_DIST_SPI_TARGET_11_0                        _MK_ADDR_CONST(0x183c)
+#define FIC_DIST_SPI_TARGET_11_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_11_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_11_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_11_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_11_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_28_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_29_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_30_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_11_0_SPI_TARGET_SPI_31_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_12_0  
+#define FIC_DIST_SPI_TARGET_12_0                        _MK_ADDR_CONST(0x1840)
+#define FIC_DIST_SPI_TARGET_12_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_12_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_12_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_12_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_12_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_32_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_33_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_34_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_12_0_SPI_TARGET_SPI_35_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_13_0  
+#define FIC_DIST_SPI_TARGET_13_0                        _MK_ADDR_CONST(0x1844)
+#define FIC_DIST_SPI_TARGET_13_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_13_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_13_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_13_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_13_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_36_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_37_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_38_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_13_0_SPI_TARGET_SPI_39_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_14_0  
+#define FIC_DIST_SPI_TARGET_14_0                        _MK_ADDR_CONST(0x1848)
+#define FIC_DIST_SPI_TARGET_14_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_14_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_14_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_14_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_14_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_40_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_41_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_42_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_14_0_SPI_TARGET_SPI_43_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_15_0  
+#define FIC_DIST_SPI_TARGET_15_0                        _MK_ADDR_CONST(0x184c)
+#define FIC_DIST_SPI_TARGET_15_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_15_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_15_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_15_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_15_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_44_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_45_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_46_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_15_0_SPI_TARGET_SPI_47_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_16_0  
+#define FIC_DIST_SPI_TARGET_16_0                        _MK_ADDR_CONST(0x1850)
+#define FIC_DIST_SPI_TARGET_16_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_16_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_16_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_16_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_16_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_48_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_49_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_50_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_16_0_SPI_TARGET_SPI_51_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_17_0  
+#define FIC_DIST_SPI_TARGET_17_0                        _MK_ADDR_CONST(0x1854)
+#define FIC_DIST_SPI_TARGET_17_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_17_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_17_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_17_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_17_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_52_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_53_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_54_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_17_0_SPI_TARGET_SPI_55_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_18_0  
+#define FIC_DIST_SPI_TARGET_18_0                        _MK_ADDR_CONST(0x1858)
+#define FIC_DIST_SPI_TARGET_18_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_18_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_18_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_18_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_18_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_56_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_57_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_58_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_18_0_SPI_TARGET_SPI_59_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_19_0  
+#define FIC_DIST_SPI_TARGET_19_0                        _MK_ADDR_CONST(0x185c)
+#define FIC_DIST_SPI_TARGET_19_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_19_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_19_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_19_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_19_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_60_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_61_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_62_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_19_0_SPI_TARGET_SPI_63_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_20_0  
+#define FIC_DIST_SPI_TARGET_20_0                        _MK_ADDR_CONST(0x1860)
+#define FIC_DIST_SPI_TARGET_20_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_20_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_20_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_20_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_20_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_64_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_65_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_66_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_20_0_SPI_TARGET_SPI_67_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_21_0  
+#define FIC_DIST_SPI_TARGET_21_0                        _MK_ADDR_CONST(0x1864)
+#define FIC_DIST_SPI_TARGET_21_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_21_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_21_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_21_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_21_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_68_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_69_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_70_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_21_0_SPI_TARGET_SPI_71_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_22_0  
+#define FIC_DIST_SPI_TARGET_22_0                        _MK_ADDR_CONST(0x1868)
+#define FIC_DIST_SPI_TARGET_22_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_22_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_22_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_22_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_22_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_72_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_73_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_74_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_22_0_SPI_TARGET_SPI_75_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_23_0  
+#define FIC_DIST_SPI_TARGET_23_0                        _MK_ADDR_CONST(0x186c)
+#define FIC_DIST_SPI_TARGET_23_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_23_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_23_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_23_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_23_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_76_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_77_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_78_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_23_0_SPI_TARGET_SPI_79_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_24_0  
+#define FIC_DIST_SPI_TARGET_24_0                        _MK_ADDR_CONST(0x1870)
+#define FIC_DIST_SPI_TARGET_24_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_24_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_24_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_24_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_24_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_80_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_81_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_82_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_24_0_SPI_TARGET_SPI_83_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_25_0  
+#define FIC_DIST_SPI_TARGET_25_0                        _MK_ADDR_CONST(0x1874)
+#define FIC_DIST_SPI_TARGET_25_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_25_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_25_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_25_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_25_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_84_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_85_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_86_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_25_0_SPI_TARGET_SPI_87_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_26_0  
+#define FIC_DIST_SPI_TARGET_26_0                        _MK_ADDR_CONST(0x1878)
+#define FIC_DIST_SPI_TARGET_26_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_26_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_26_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_26_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_26_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_88_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_89_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_90_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_26_0_SPI_TARGET_SPI_91_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_27_0  
+#define FIC_DIST_SPI_TARGET_27_0                        _MK_ADDR_CONST(0x187c)
+#define FIC_DIST_SPI_TARGET_27_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_27_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_27_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_27_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_27_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_92_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_93_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_94_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_27_0_SPI_TARGET_SPI_95_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_28_0  
+#define FIC_DIST_SPI_TARGET_28_0                        _MK_ADDR_CONST(0x1880)
+#define FIC_DIST_SPI_TARGET_28_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_28_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_28_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_28_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_28_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU0_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU0_RANGE                   0:0
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU1_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU1_RANGE                   1:1
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_96_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU0_SHIFT                   _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU0_RANGE                   8:8
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU1_SHIFT                   _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU1_RANGE                   9:9
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_97_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU0_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU0_RANGE                   16:16
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU1_SHIFT                   _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU1_RANGE                   17:17
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_98_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU0_SHIFT                   _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU0_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU0_RANGE                   24:24
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU0_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU1_SHIFT                   _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU1_FIELD                   (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU1_RANGE                   25:25
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU1_WOFFSET                 0x0
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_28_0_SPI_TARGET_SPI_99_CPU1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_29_0  
+#define FIC_DIST_SPI_TARGET_29_0                        _MK_ADDR_CONST(0x1884)
+#define FIC_DIST_SPI_TARGET_29_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_29_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_29_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_29_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_29_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU0_RANGE                  0:0
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU1_SHIFT                  _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU1_RANGE                  1:1
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_100_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU0_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU0_RANGE                  8:8
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU1_SHIFT                  _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU1_RANGE                  9:9
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_101_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU0_SHIFT                  _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU0_RANGE                  16:16
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU1_SHIFT                  _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU1_RANGE                  17:17
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_102_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU0_SHIFT                  _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU0_RANGE                  24:24
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU1_SHIFT                  _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU1_RANGE                  25:25
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_29_0_SPI_TARGET_SPI_103_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_30_0  
+#define FIC_DIST_SPI_TARGET_30_0                        _MK_ADDR_CONST(0x1888)
+#define FIC_DIST_SPI_TARGET_30_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_30_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_30_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_30_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_30_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU0_RANGE                  0:0
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU1_SHIFT                  _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU1_RANGE                  1:1
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_104_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU0_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU0_RANGE                  8:8
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU1_SHIFT                  _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU1_RANGE                  9:9
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_105_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU0_SHIFT                  _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU0_RANGE                  16:16
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU1_SHIFT                  _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU1_RANGE                  17:17
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_106_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU0_SHIFT                  _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU0_RANGE                  24:24
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU1_SHIFT                  _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU1_RANGE                  25:25
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_30_0_SPI_TARGET_SPI_107_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_31_0  
+#define FIC_DIST_SPI_TARGET_31_0                        _MK_ADDR_CONST(0x188c)
+#define FIC_DIST_SPI_TARGET_31_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_31_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_31_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_31_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_31_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU0_RANGE                  0:0
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU1_SHIFT                  _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU1_RANGE                  1:1
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_108_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU0_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU0_RANGE                  8:8
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU1_SHIFT                  _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU1_RANGE                  9:9
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_109_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU0_SHIFT                  _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU0_RANGE                  16:16
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU1_SHIFT                  _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU1_RANGE                  17:17
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_110_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU0_SHIFT                  _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU0_RANGE                  24:24
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU1_SHIFT                  _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU1_RANGE                  25:25
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_31_0_SPI_TARGET_SPI_111_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_32_0  
+#define FIC_DIST_SPI_TARGET_32_0                        _MK_ADDR_CONST(0x1890)
+#define FIC_DIST_SPI_TARGET_32_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_32_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_32_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_32_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_32_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU0_RANGE                  0:0
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU1_SHIFT                  _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU1_RANGE                  1:1
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_112_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU0_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU0_RANGE                  8:8
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU1_SHIFT                  _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU1_RANGE                  9:9
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_113_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU0_SHIFT                  _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU0_RANGE                  16:16
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU1_SHIFT                  _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU1_RANGE                  17:17
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_114_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU0_SHIFT                  _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU0_RANGE                  24:24
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU1_SHIFT                  _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU1_RANGE                  25:25
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_32_0_SPI_TARGET_SPI_115_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_33_0  
+#define FIC_DIST_SPI_TARGET_33_0                        _MK_ADDR_CONST(0x1894)
+#define FIC_DIST_SPI_TARGET_33_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_33_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_33_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_33_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_33_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU0_RANGE                  0:0
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU1_SHIFT                  _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU1_RANGE                  1:1
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_116_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU0_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU0_RANGE                  8:8
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU1_SHIFT                  _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU1_RANGE                  9:9
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_117_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU0_SHIFT                  _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU0_RANGE                  16:16
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU1_SHIFT                  _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU1_RANGE                  17:17
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_118_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU0_SHIFT                  _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU0_RANGE                  24:24
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU1_SHIFT                  _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU1_RANGE                  25:25
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_33_0_SPI_TARGET_SPI_119_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_34_0  
+#define FIC_DIST_SPI_TARGET_34_0                        _MK_ADDR_CONST(0x1898)
+#define FIC_DIST_SPI_TARGET_34_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_34_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_34_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_34_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_34_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU0_RANGE                  0:0
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU1_SHIFT                  _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU1_RANGE                  1:1
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_120_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU0_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU0_RANGE                  8:8
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU1_SHIFT                  _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU1_RANGE                  9:9
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_121_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU0_SHIFT                  _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU0_RANGE                  16:16
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU1_SHIFT                  _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU1_RANGE                  17:17
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_122_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU0_SHIFT                  _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU0_RANGE                  24:24
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU1_SHIFT                  _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU1_RANGE                  25:25
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_34_0_SPI_TARGET_SPI_123_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_TARGET_35_0  
+#define FIC_DIST_SPI_TARGET_35_0                        _MK_ADDR_CONST(0x189c)
+#define FIC_DIST_SPI_TARGET_35_0_SECURE                         0x0
+#define FIC_DIST_SPI_TARGET_35_0_WORD_COUNT                     0x1
+#define FIC_DIST_SPI_TARGET_35_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_RESET_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_35_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_READ_MASK                      _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_35_0_WRITE_MASK                     _MK_MASK_CONST(0x3030303)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU0_RANGE                  0:0
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU1_SHIFT                  _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU1_RANGE                  1:1
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_124_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU0_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU0_RANGE                  8:8
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU1_SHIFT                  _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU1_RANGE                  9:9
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_125_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU0_SHIFT                  _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU0_RANGE                  16:16
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU1_SHIFT                  _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU1_RANGE                  17:17
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_126_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU0_SHIFT                  _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU0_SHIFT)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU0_RANGE                  24:24
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU0_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU1_SHIFT                  _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU1_SHIFT)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU1_RANGE                  25:25
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU1_WOFFSET                        0x0
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_TARGET_35_0_SPI_TARGET_SPI_127_CPU1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 6304 [0x18a0] 
+
+// Reserved address 6308 [0x18a4] 
+
+// Reserved address 6312 [0x18a8] 
+
+// Reserved address 6316 [0x18ac] 
+
+// Reserved address 6320 [0x18b0] 
+
+// Reserved address 6324 [0x18b4] 
+
+// Reserved address 6328 [0x18b8] 
+
+// Reserved address 6332 [0x18bc] 
+
+// Reserved address 6336 [0x18c0] 
+
+// Reserved address 6340 [0x18c4] 
+
+// Reserved address 6344 [0x18c8] 
+
+// Reserved address 6348 [0x18cc] 
+
+// Reserved address 6352 [0x18d0] 
+
+// Reserved address 6356 [0x18d4] 
+
+// Reserved address 6360 [0x18d8] 
+
+// Reserved address 6364 [0x18dc] 
+
+// Reserved address 6368 [0x18e0] 
+
+// Reserved address 6372 [0x18e4] 
+
+// Reserved address 6376 [0x18e8] 
+
+// Reserved address 6380 [0x18ec] 
+
+// Reserved address 6384 [0x18f0] 
+
+// Reserved address 6388 [0x18f4] 
+
+// Reserved address 6392 [0x18f8] 
+
+// Reserved address 6396 [0x18fc] 
+
+// Reserved address 6400 [0x1900] 
+
+// Reserved address 6404 [0x1904] 
+
+// Reserved address 6408 [0x1908] 
+
+// Reserved address 6412 [0x190c] 
+
+// Reserved address 6416 [0x1910] 
+
+// Reserved address 6420 [0x1914] 
+
+// Reserved address 6424 [0x1918] 
+
+// Reserved address 6428 [0x191c] 
+
+// Reserved address 6432 [0x1920] 
+
+// Reserved address 6436 [0x1924] 
+
+// Reserved address 6440 [0x1928] 
+
+// Reserved address 6444 [0x192c] 
+
+// Reserved address 6448 [0x1930] 
+
+// Reserved address 6452 [0x1934] 
+
+// Reserved address 6456 [0x1938] 
+
+// Reserved address 6460 [0x193c] 
+
+// Reserved address 6464 [0x1940] 
+
+// Reserved address 6468 [0x1944] 
+
+// Reserved address 6472 [0x1948] 
+
+// Reserved address 6476 [0x194c] 
+
+// Reserved address 6480 [0x1950] 
+
+// Reserved address 6484 [0x1954] 
+
+// Reserved address 6488 [0x1958] 
+
+// Reserved address 6492 [0x195c] 
+
+// Reserved address 6496 [0x1960] 
+
+// Reserved address 6500 [0x1964] 
+
+// Reserved address 6504 [0x1968] 
+
+// Reserved address 6508 [0x196c] 
+
+// Reserved address 6512 [0x1970] 
+
+// Reserved address 6516 [0x1974] 
+
+// Reserved address 6520 [0x1978] 
+
+// Reserved address 6524 [0x197c] 
+
+// Reserved address 6528 [0x1980] 
+
+// Reserved address 6532 [0x1984] 
+
+// Reserved address 6536 [0x1988] 
+
+// Reserved address 6540 [0x198c] 
+
+// Reserved address 6544 [0x1990] 
+
+// Reserved address 6548 [0x1994] 
+
+// Reserved address 6552 [0x1998] 
+
+// Reserved address 6556 [0x199c] 
+
+// Reserved address 6560 [0x19a0] 
+
+// Reserved address 6564 [0x19a4] 
+
+// Reserved address 6568 [0x19a8] 
+
+// Reserved address 6572 [0x19ac] 
+
+// Reserved address 6576 [0x19b0] 
+
+// Reserved address 6580 [0x19b4] 
+
+// Reserved address 6584 [0x19b8] 
+
+// Reserved address 6588 [0x19bc] 
+
+// Reserved address 6592 [0x19c0] 
+
+// Reserved address 6596 [0x19c4] 
+
+// Reserved address 6600 [0x19c8] 
+
+// Reserved address 6604 [0x19cc] 
+
+// Reserved address 6608 [0x19d0] 
+
+// Reserved address 6612 [0x19d4] 
+
+// Reserved address 6616 [0x19d8] 
+
+// Reserved address 6620 [0x19dc] 
+
+// Reserved address 6624 [0x19e0] 
+
+// Reserved address 6628 [0x19e4] 
+
+// Reserved address 6632 [0x19e8] 
+
+// Reserved address 6636 [0x19ec] 
+
+// Reserved address 6640 [0x19f0] 
+
+// Reserved address 6644 [0x19f4] 
+
+// Reserved address 6648 [0x19f8] 
+
+// Reserved address 6652 [0x19fc] 
+
+// Reserved address 6656 [0x1a00] 
+
+// Reserved address 6660 [0x1a04] 
+
+// Reserved address 6664 [0x1a08] 
+
+// Reserved address 6668 [0x1a0c] 
+
+// Reserved address 6672 [0x1a10] 
+
+// Reserved address 6676 [0x1a14] 
+
+// Reserved address 6680 [0x1a18] 
+
+// Reserved address 6684 [0x1a1c] 
+
+// Reserved address 6688 [0x1a20] 
+
+// Reserved address 6692 [0x1a24] 
+
+// Reserved address 6696 [0x1a28] 
+
+// Reserved address 6700 [0x1a2c] 
+
+// Reserved address 6704 [0x1a30] 
+
+// Reserved address 6708 [0x1a34] 
+
+// Reserved address 6712 [0x1a38] 
+
+// Reserved address 6716 [0x1a3c] 
+
+// Reserved address 6720 [0x1a40] 
+
+// Reserved address 6724 [0x1a44] 
+
+// Reserved address 6728 [0x1a48] 
+
+// Reserved address 6732 [0x1a4c] 
+
+// Reserved address 6736 [0x1a50] 
+
+// Reserved address 6740 [0x1a54] 
+
+// Reserved address 6744 [0x1a58] 
+
+// Reserved address 6748 [0x1a5c] 
+
+// Reserved address 6752 [0x1a60] 
+
+// Reserved address 6756 [0x1a64] 
+
+// Reserved address 6760 [0x1a68] 
+
+// Reserved address 6764 [0x1a6c] 
+
+// Reserved address 6768 [0x1a70] 
+
+// Reserved address 6772 [0x1a74] 
+
+// Reserved address 6776 [0x1a78] 
+
+// Reserved address 6780 [0x1a7c] 
+
+// Reserved address 6784 [0x1a80] 
+
+// Reserved address 6788 [0x1a84] 
+
+// Reserved address 6792 [0x1a88] 
+
+// Reserved address 6796 [0x1a8c] 
+
+// Reserved address 6800 [0x1a90] 
+
+// Reserved address 6804 [0x1a94] 
+
+// Reserved address 6808 [0x1a98] 
+
+// Reserved address 6812 [0x1a9c] 
+
+// Reserved address 6816 [0x1aa0] 
+
+// Reserved address 6820 [0x1aa4] 
+
+// Reserved address 6824 [0x1aa8] 
+
+// Reserved address 6828 [0x1aac] 
+
+// Reserved address 6832 [0x1ab0] 
+
+// Reserved address 6836 [0x1ab4] 
+
+// Reserved address 6840 [0x1ab8] 
+
+// Reserved address 6844 [0x1abc] 
+
+// Reserved address 6848 [0x1ac0] 
+
+// Reserved address 6852 [0x1ac4] 
+
+// Reserved address 6856 [0x1ac8] 
+
+// Reserved address 6860 [0x1acc] 
+
+// Reserved address 6864 [0x1ad0] 
+
+// Reserved address 6868 [0x1ad4] 
+
+// Reserved address 6872 [0x1ad8] 
+
+// Reserved address 6876 [0x1adc] 
+
+// Reserved address 6880 [0x1ae0] 
+
+// Reserved address 6884 [0x1ae4] 
+
+// Reserved address 6888 [0x1ae8] 
+
+// Reserved address 6892 [0x1aec] 
+
+// Reserved address 6896 [0x1af0] 
+
+// Reserved address 6900 [0x1af4] 
+
+// Reserved address 6904 [0x1af8] 
+
+// Reserved address 6908 [0x1afc] 
+
+// Reserved address 6912 [0x1b00] 
+
+// Reserved address 6916 [0x1b04] 
+
+// Reserved address 6920 [0x1b08] 
+
+// Reserved address 6924 [0x1b0c] 
+
+// Reserved address 6928 [0x1b10] 
+
+// Reserved address 6932 [0x1b14] 
+
+// Reserved address 6936 [0x1b18] 
+
+// Reserved address 6940 [0x1b1c] 
+
+// Reserved address 6944 [0x1b20] 
+
+// Reserved address 6948 [0x1b24] 
+
+// Reserved address 6952 [0x1b28] 
+
+// Reserved address 6956 [0x1b2c] 
+
+// Reserved address 6960 [0x1b30] 
+
+// Reserved address 6964 [0x1b34] 
+
+// Reserved address 6968 [0x1b38] 
+
+// Reserved address 6972 [0x1b3c] 
+
+// Reserved address 6976 [0x1b40] 
+
+// Reserved address 6980 [0x1b44] 
+
+// Reserved address 6984 [0x1b48] 
+
+// Reserved address 6988 [0x1b4c] 
+
+// Reserved address 6992 [0x1b50] 
+
+// Reserved address 6996 [0x1b54] 
+
+// Reserved address 7000 [0x1b58] 
+
+// Reserved address 7004 [0x1b5c] 
+
+// Reserved address 7008 [0x1b60] 
+
+// Reserved address 7012 [0x1b64] 
+
+// Reserved address 7016 [0x1b68] 
+
+// Reserved address 7020 [0x1b6c] 
+
+// Reserved address 7024 [0x1b70] 
+
+// Reserved address 7028 [0x1b74] 
+
+// Reserved address 7032 [0x1b78] 
+
+// Reserved address 7036 [0x1b7c] 
+
+// Reserved address 7040 [0x1b80] 
+
+// Reserved address 7044 [0x1b84] 
+
+// Reserved address 7048 [0x1b88] 
+
+// Reserved address 7052 [0x1b8c] 
+
+// Reserved address 7056 [0x1b90] 
+
+// Reserved address 7060 [0x1b94] 
+
+// Reserved address 7064 [0x1b98] 
+
+// Reserved address 7068 [0x1b9c] 
+
+// Reserved address 7072 [0x1ba0] 
+
+// Reserved address 7076 [0x1ba4] 
+
+// Reserved address 7080 [0x1ba8] 
+
+// Reserved address 7084 [0x1bac] 
+
+// Reserved address 7088 [0x1bb0] 
+
+// Reserved address 7092 [0x1bb4] 
+
+// Reserved address 7096 [0x1bb8] 
+
+// Reserved address 7100 [0x1bbc] 
+
+// Reserved address 7104 [0x1bc0] 
+
+// Reserved address 7108 [0x1bc4] 
+
+// Reserved address 7112 [0x1bc8] 
+
+// Reserved address 7116 [0x1bcc] 
+
+// Reserved address 7120 [0x1bd0] 
+
+// Reserved address 7124 [0x1bd4] 
+
+// Reserved address 7128 [0x1bd8] 
+
+// Reserved address 7132 [0x1bdc] 
+
+// Reserved address 7136 [0x1be0] 
+
+// Reserved address 7140 [0x1be4] 
+
+// Reserved address 7144 [0x1be8] 
+
+// Reserved address 7148 [0x1bec] 
+
+// Reserved address 7152 [0x1bf0] 
+
+// Reserved address 7156 [0x1bf4] 
+
+// Reserved address 7160 [0x1bf8] 
+
+// Reserved address 7164 [0x1bfc] 
+
+// Register FIC_DIST_INT_CONFIG_0_0  
+#define FIC_DIST_INT_CONFIG_0_0                 _MK_ADDR_CONST(0x1c00)
+#define FIC_DIST_INT_CONFIG_0_0_SECURE                  0x0
+#define FIC_DIST_INT_CONFIG_0_0_WORD_COUNT                      0x1
+#define FIC_DIST_INT_CONFIG_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_0_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_0_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_0_RANGE                  1:0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_0_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_1_SHIFT                  _MK_SHIFT_CONST(2)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_1_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_1_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_1_RANGE                  3:2
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_1_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_1_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_2_SHIFT                  _MK_SHIFT_CONST(4)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_2_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_2_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_2_RANGE                  5:4
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_2_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_2_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_3_SHIFT                  _MK_SHIFT_CONST(6)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_3_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_3_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_3_RANGE                  7:6
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_3_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_3_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_4_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_4_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_4_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_4_RANGE                  9:8
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_4_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_4_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_5_SHIFT                  _MK_SHIFT_CONST(10)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_5_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_5_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_5_RANGE                  11:10
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_5_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_5_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_6_SHIFT                  _MK_SHIFT_CONST(12)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_6_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_6_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_6_RANGE                  13:12
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_6_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_6_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_7_SHIFT                  _MK_SHIFT_CONST(14)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_7_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_7_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_7_RANGE                  15:14
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_7_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_7_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_8_SHIFT                  _MK_SHIFT_CONST(16)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_8_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_8_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_8_RANGE                  17:16
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_8_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_8_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_9_SHIFT                  _MK_SHIFT_CONST(18)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_9_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_9_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_9_RANGE                  19:18
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_9_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_9_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_10_SHIFT                 _MK_SHIFT_CONST(20)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_10_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_10_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_10_RANGE                 21:20
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_10_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_10_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_11_SHIFT                 _MK_SHIFT_CONST(22)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_11_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_11_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_11_RANGE                 23:22
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_11_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_11_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_12_SHIFT                 _MK_SHIFT_CONST(24)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_12_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_12_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_12_RANGE                 25:24
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_12_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_12_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_13_SHIFT                 _MK_SHIFT_CONST(26)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_13_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_13_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_13_RANGE                 27:26
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_13_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_13_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_14_SHIFT                 _MK_SHIFT_CONST(28)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_14_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_14_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_14_RANGE                 29:28
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_14_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_14_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_15_SHIFT                 _MK_SHIFT_CONST(30)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_15_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_15_SHIFT)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_15_RANGE                 31:30
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_15_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_15_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_0_0_INT_CONFIG_STI_15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INT_CONFIG_1_0  
+#define FIC_DIST_INT_CONFIG_1_0                 _MK_ADDR_CONST(0x1c04)
+#define FIC_DIST_INT_CONFIG_1_0_SECURE                  0x0
+#define FIC_DIST_INT_CONFIG_1_0_WORD_COUNT                      0x1
+#define FIC_DIST_INT_CONFIG_1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_RESET_MASK                      _MK_MASK_CONST(0xffc00000)
+#define FIC_DIST_INT_CONFIG_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_READ_MASK                       _MK_MASK_CONST(0xffc00000)
+#define FIC_DIST_INT_CONFIG_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffc00000)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_4_SHIFT                  _MK_SHIFT_CONST(22)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_4_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_4_SHIFT)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_4_RANGE                  23:22
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_4_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_4_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_0_SHIFT                  _MK_SHIFT_CONST(24)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_0_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_0_SHIFT)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_0_RANGE                  25:24
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_0_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_1_SHIFT                  _MK_SHIFT_CONST(26)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_1_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_1_SHIFT)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_1_RANGE                  27:26
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_1_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_1_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_2_SHIFT                  _MK_SHIFT_CONST(28)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_2_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_2_SHIFT)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_2_RANGE                  29:28
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_2_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_2_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_3_SHIFT                  _MK_SHIFT_CONST(30)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_3_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_3_SHIFT)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_3_RANGE                  31:30
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_3_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_3_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_1_0_INT_CONFIG_PPI_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INT_CONFIG_2_0  
+#define FIC_DIST_INT_CONFIG_2_0                 _MK_ADDR_CONST(0x1c08)
+#define FIC_DIST_INT_CONFIG_2_0_SECURE                  0x0
+#define FIC_DIST_INT_CONFIG_2_0_WORD_COUNT                      0x1
+#define FIC_DIST_INT_CONFIG_2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_0_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_0_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_0_RANGE                  1:0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_0_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_0_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_1_SHIFT                  _MK_SHIFT_CONST(2)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_1_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_1_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_1_RANGE                  3:2
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_1_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_1_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_2_SHIFT                  _MK_SHIFT_CONST(4)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_2_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_2_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_2_RANGE                  5:4
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_2_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_2_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_3_SHIFT                  _MK_SHIFT_CONST(6)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_3_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_3_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_3_RANGE                  7:6
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_3_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_3_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_4_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_4_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_4_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_4_RANGE                  9:8
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_4_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_4_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_5_SHIFT                  _MK_SHIFT_CONST(10)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_5_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_5_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_5_RANGE                  11:10
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_5_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_5_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_6_SHIFT                  _MK_SHIFT_CONST(12)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_6_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_6_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_6_RANGE                  13:12
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_6_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_6_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_7_SHIFT                  _MK_SHIFT_CONST(14)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_7_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_7_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_7_RANGE                  15:14
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_7_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_7_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_8_SHIFT                  _MK_SHIFT_CONST(16)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_8_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_8_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_8_RANGE                  17:16
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_8_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_8_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_9_SHIFT                  _MK_SHIFT_CONST(18)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_9_FIELD                  (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_9_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_9_RANGE                  19:18
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_9_WOFFSET                        0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_9_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_10_SHIFT                 _MK_SHIFT_CONST(20)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_10_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_10_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_10_RANGE                 21:20
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_10_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_10_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_11_SHIFT                 _MK_SHIFT_CONST(22)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_11_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_11_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_11_RANGE                 23:22
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_11_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_11_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_12_SHIFT                 _MK_SHIFT_CONST(24)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_12_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_12_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_12_RANGE                 25:24
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_12_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_12_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_13_SHIFT                 _MK_SHIFT_CONST(26)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_13_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_13_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_13_RANGE                 27:26
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_13_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_13_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_14_SHIFT                 _MK_SHIFT_CONST(28)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_14_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_14_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_14_RANGE                 29:28
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_14_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_14_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_15_SHIFT                 _MK_SHIFT_CONST(30)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_15_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_15_SHIFT)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_15_RANGE                 31:30
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_15_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_15_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_2_0_INT_CONFIG_SPI_15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INT_CONFIG_3_0  
+#define FIC_DIST_INT_CONFIG_3_0                 _MK_ADDR_CONST(0x1c0c)
+#define FIC_DIST_INT_CONFIG_3_0_SECURE                  0x0
+#define FIC_DIST_INT_CONFIG_3_0_WORD_COUNT                      0x1
+#define FIC_DIST_INT_CONFIG_3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_16_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_16_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_16_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_16_RANGE                 1:0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_16_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_16_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_16_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_16_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_16_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_17_SHIFT                 _MK_SHIFT_CONST(2)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_17_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_17_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_17_RANGE                 3:2
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_17_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_17_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_17_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_17_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_17_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_18_SHIFT                 _MK_SHIFT_CONST(4)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_18_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_18_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_18_RANGE                 5:4
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_18_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_18_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_18_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_18_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_18_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_19_SHIFT                 _MK_SHIFT_CONST(6)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_19_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_19_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_19_RANGE                 7:6
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_19_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_19_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_19_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_19_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_19_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_20_SHIFT                 _MK_SHIFT_CONST(8)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_20_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_20_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_20_RANGE                 9:8
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_20_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_20_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_20_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_20_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_20_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_21_SHIFT                 _MK_SHIFT_CONST(10)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_21_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_21_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_21_RANGE                 11:10
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_21_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_21_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_21_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_21_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_21_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_22_SHIFT                 _MK_SHIFT_CONST(12)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_22_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_22_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_22_RANGE                 13:12
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_22_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_22_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_22_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_22_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_22_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_23_SHIFT                 _MK_SHIFT_CONST(14)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_23_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_23_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_23_RANGE                 15:14
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_23_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_23_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_23_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_23_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_23_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_24_SHIFT                 _MK_SHIFT_CONST(16)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_24_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_24_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_24_RANGE                 17:16
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_24_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_24_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_24_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_24_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_24_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_25_SHIFT                 _MK_SHIFT_CONST(18)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_25_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_25_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_25_RANGE                 19:18
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_25_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_25_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_25_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_25_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_25_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_26_SHIFT                 _MK_SHIFT_CONST(20)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_26_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_26_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_26_RANGE                 21:20
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_26_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_26_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_26_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_26_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_26_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_27_SHIFT                 _MK_SHIFT_CONST(22)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_27_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_27_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_27_RANGE                 23:22
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_27_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_27_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_27_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_27_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_27_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_28_SHIFT                 _MK_SHIFT_CONST(24)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_28_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_28_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_28_RANGE                 25:24
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_28_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_28_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_28_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_28_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_28_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_29_SHIFT                 _MK_SHIFT_CONST(26)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_29_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_29_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_29_RANGE                 27:26
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_29_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_29_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_29_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_29_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_29_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_30_SHIFT                 _MK_SHIFT_CONST(28)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_30_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_30_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_30_RANGE                 29:28
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_30_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_30_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_30_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_30_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_30_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_31_SHIFT                 _MK_SHIFT_CONST(30)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_31_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_31_SHIFT)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_31_RANGE                 31:30
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_31_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_31_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_31_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_31_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_3_0_INT_CONFIG_SPI_31_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INT_CONFIG_4_0  
+#define FIC_DIST_INT_CONFIG_4_0                 _MK_ADDR_CONST(0x1c10)
+#define FIC_DIST_INT_CONFIG_4_0_SECURE                  0x0
+#define FIC_DIST_INT_CONFIG_4_0_WORD_COUNT                      0x1
+#define FIC_DIST_INT_CONFIG_4_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_32_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_32_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_32_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_32_RANGE                 1:0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_32_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_32_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_32_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_32_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_32_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_33_SHIFT                 _MK_SHIFT_CONST(2)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_33_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_33_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_33_RANGE                 3:2
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_33_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_33_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_33_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_33_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_33_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_34_SHIFT                 _MK_SHIFT_CONST(4)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_34_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_34_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_34_RANGE                 5:4
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_34_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_34_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_34_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_34_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_34_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_35_SHIFT                 _MK_SHIFT_CONST(6)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_35_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_35_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_35_RANGE                 7:6
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_35_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_35_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_35_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_35_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_35_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_36_SHIFT                 _MK_SHIFT_CONST(8)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_36_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_36_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_36_RANGE                 9:8
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_36_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_36_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_36_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_36_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_36_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_37_SHIFT                 _MK_SHIFT_CONST(10)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_37_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_37_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_37_RANGE                 11:10
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_37_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_37_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_37_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_37_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_37_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_38_SHIFT                 _MK_SHIFT_CONST(12)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_38_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_38_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_38_RANGE                 13:12
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_38_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_38_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_38_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_38_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_38_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_39_SHIFT                 _MK_SHIFT_CONST(14)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_39_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_39_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_39_RANGE                 15:14
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_39_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_39_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_39_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_39_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_39_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_40_SHIFT                 _MK_SHIFT_CONST(16)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_40_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_40_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_40_RANGE                 17:16
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_40_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_40_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_40_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_40_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_40_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_41_SHIFT                 _MK_SHIFT_CONST(18)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_41_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_41_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_41_RANGE                 19:18
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_41_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_41_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_41_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_41_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_41_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_42_SHIFT                 _MK_SHIFT_CONST(20)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_42_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_42_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_42_RANGE                 21:20
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_42_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_42_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_42_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_42_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_42_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_43_SHIFT                 _MK_SHIFT_CONST(22)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_43_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_43_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_43_RANGE                 23:22
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_43_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_43_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_43_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_43_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_43_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_44_SHIFT                 _MK_SHIFT_CONST(24)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_44_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_44_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_44_RANGE                 25:24
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_44_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_44_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_44_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_44_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_44_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_45_SHIFT                 _MK_SHIFT_CONST(26)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_45_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_45_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_45_RANGE                 27:26
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_45_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_45_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_45_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_45_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_45_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_46_SHIFT                 _MK_SHIFT_CONST(28)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_46_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_46_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_46_RANGE                 29:28
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_46_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_46_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_46_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_46_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_46_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_47_SHIFT                 _MK_SHIFT_CONST(30)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_47_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_47_SHIFT)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_47_RANGE                 31:30
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_47_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_47_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_47_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_47_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_4_0_INT_CONFIG_SPI_47_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INT_CONFIG_5_0  
+#define FIC_DIST_INT_CONFIG_5_0                 _MK_ADDR_CONST(0x1c14)
+#define FIC_DIST_INT_CONFIG_5_0_SECURE                  0x0
+#define FIC_DIST_INT_CONFIG_5_0_WORD_COUNT                      0x1
+#define FIC_DIST_INT_CONFIG_5_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_5_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_48_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_48_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_48_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_48_RANGE                 1:0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_48_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_48_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_48_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_48_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_48_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_49_SHIFT                 _MK_SHIFT_CONST(2)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_49_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_49_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_49_RANGE                 3:2
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_49_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_49_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_49_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_49_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_49_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_50_SHIFT                 _MK_SHIFT_CONST(4)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_50_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_50_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_50_RANGE                 5:4
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_50_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_50_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_50_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_50_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_50_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_51_SHIFT                 _MK_SHIFT_CONST(6)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_51_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_51_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_51_RANGE                 7:6
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_51_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_51_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_51_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_51_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_51_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_52_SHIFT                 _MK_SHIFT_CONST(8)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_52_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_52_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_52_RANGE                 9:8
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_52_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_52_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_52_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_52_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_52_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_53_SHIFT                 _MK_SHIFT_CONST(10)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_53_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_53_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_53_RANGE                 11:10
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_53_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_53_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_53_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_53_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_53_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_54_SHIFT                 _MK_SHIFT_CONST(12)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_54_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_54_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_54_RANGE                 13:12
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_54_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_54_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_54_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_54_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_54_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_55_SHIFT                 _MK_SHIFT_CONST(14)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_55_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_55_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_55_RANGE                 15:14
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_55_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_55_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_55_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_55_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_55_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_56_SHIFT                 _MK_SHIFT_CONST(16)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_56_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_56_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_56_RANGE                 17:16
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_56_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_56_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_56_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_56_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_56_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_57_SHIFT                 _MK_SHIFT_CONST(18)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_57_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_57_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_57_RANGE                 19:18
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_57_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_57_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_57_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_57_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_57_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_58_SHIFT                 _MK_SHIFT_CONST(20)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_58_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_58_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_58_RANGE                 21:20
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_58_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_58_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_58_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_58_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_58_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_59_SHIFT                 _MK_SHIFT_CONST(22)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_59_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_59_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_59_RANGE                 23:22
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_59_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_59_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_59_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_59_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_59_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_60_SHIFT                 _MK_SHIFT_CONST(24)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_60_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_60_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_60_RANGE                 25:24
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_60_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_60_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_60_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_60_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_60_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_61_SHIFT                 _MK_SHIFT_CONST(26)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_61_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_61_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_61_RANGE                 27:26
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_61_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_61_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_61_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_61_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_61_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_62_SHIFT                 _MK_SHIFT_CONST(28)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_62_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_62_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_62_RANGE                 29:28
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_62_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_62_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_62_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_62_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_62_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_63_SHIFT                 _MK_SHIFT_CONST(30)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_63_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_63_SHIFT)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_63_RANGE                 31:30
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_63_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_63_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_63_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_63_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_5_0_INT_CONFIG_SPI_63_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INT_CONFIG_6_0  
+#define FIC_DIST_INT_CONFIG_6_0                 _MK_ADDR_CONST(0x1c18)
+#define FIC_DIST_INT_CONFIG_6_0_SECURE                  0x0
+#define FIC_DIST_INT_CONFIG_6_0_WORD_COUNT                      0x1
+#define FIC_DIST_INT_CONFIG_6_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_6_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_64_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_64_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_64_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_64_RANGE                 1:0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_64_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_64_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_64_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_64_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_64_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_65_SHIFT                 _MK_SHIFT_CONST(2)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_65_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_65_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_65_RANGE                 3:2
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_65_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_65_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_65_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_65_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_65_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_66_SHIFT                 _MK_SHIFT_CONST(4)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_66_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_66_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_66_RANGE                 5:4
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_66_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_66_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_66_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_66_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_66_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_67_SHIFT                 _MK_SHIFT_CONST(6)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_67_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_67_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_67_RANGE                 7:6
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_67_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_67_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_67_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_67_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_67_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_68_SHIFT                 _MK_SHIFT_CONST(8)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_68_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_68_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_68_RANGE                 9:8
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_68_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_68_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_68_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_68_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_68_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_69_SHIFT                 _MK_SHIFT_CONST(10)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_69_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_69_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_69_RANGE                 11:10
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_69_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_69_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_69_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_69_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_69_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_70_SHIFT                 _MK_SHIFT_CONST(12)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_70_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_70_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_70_RANGE                 13:12
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_70_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_70_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_70_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_70_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_70_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_71_SHIFT                 _MK_SHIFT_CONST(14)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_71_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_71_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_71_RANGE                 15:14
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_71_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_71_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_71_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_71_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_71_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_72_SHIFT                 _MK_SHIFT_CONST(16)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_72_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_72_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_72_RANGE                 17:16
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_72_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_72_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_72_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_72_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_72_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_73_SHIFT                 _MK_SHIFT_CONST(18)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_73_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_73_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_73_RANGE                 19:18
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_73_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_73_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_73_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_73_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_73_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_74_SHIFT                 _MK_SHIFT_CONST(20)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_74_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_74_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_74_RANGE                 21:20
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_74_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_74_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_74_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_74_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_74_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_75_SHIFT                 _MK_SHIFT_CONST(22)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_75_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_75_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_75_RANGE                 23:22
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_75_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_75_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_75_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_75_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_75_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_76_SHIFT                 _MK_SHIFT_CONST(24)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_76_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_76_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_76_RANGE                 25:24
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_76_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_76_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_76_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_76_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_76_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_77_SHIFT                 _MK_SHIFT_CONST(26)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_77_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_77_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_77_RANGE                 27:26
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_77_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_77_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_77_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_77_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_77_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_78_SHIFT                 _MK_SHIFT_CONST(28)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_78_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_78_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_78_RANGE                 29:28
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_78_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_78_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_78_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_78_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_78_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_79_SHIFT                 _MK_SHIFT_CONST(30)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_79_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_79_SHIFT)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_79_RANGE                 31:30
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_79_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_79_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_79_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_79_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_6_0_INT_CONFIG_SPI_79_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INT_CONFIG_7_0  
+#define FIC_DIST_INT_CONFIG_7_0                 _MK_ADDR_CONST(0x1c1c)
+#define FIC_DIST_INT_CONFIG_7_0_SECURE                  0x0
+#define FIC_DIST_INT_CONFIG_7_0_WORD_COUNT                      0x1
+#define FIC_DIST_INT_CONFIG_7_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_7_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_80_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_80_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_80_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_80_RANGE                 1:0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_80_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_80_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_80_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_80_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_80_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_81_SHIFT                 _MK_SHIFT_CONST(2)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_81_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_81_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_81_RANGE                 3:2
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_81_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_81_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_81_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_81_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_81_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_82_SHIFT                 _MK_SHIFT_CONST(4)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_82_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_82_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_82_RANGE                 5:4
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_82_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_82_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_82_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_82_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_82_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_83_SHIFT                 _MK_SHIFT_CONST(6)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_83_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_83_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_83_RANGE                 7:6
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_83_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_83_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_83_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_83_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_83_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_84_SHIFT                 _MK_SHIFT_CONST(8)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_84_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_84_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_84_RANGE                 9:8
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_84_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_84_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_84_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_84_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_84_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_85_SHIFT                 _MK_SHIFT_CONST(10)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_85_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_85_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_85_RANGE                 11:10
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_85_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_85_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_85_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_85_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_85_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_86_SHIFT                 _MK_SHIFT_CONST(12)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_86_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_86_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_86_RANGE                 13:12
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_86_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_86_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_86_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_86_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_86_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_87_SHIFT                 _MK_SHIFT_CONST(14)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_87_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_87_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_87_RANGE                 15:14
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_87_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_87_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_87_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_87_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_87_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_88_SHIFT                 _MK_SHIFT_CONST(16)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_88_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_88_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_88_RANGE                 17:16
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_88_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_88_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_88_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_88_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_88_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_89_SHIFT                 _MK_SHIFT_CONST(18)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_89_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_89_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_89_RANGE                 19:18
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_89_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_89_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_89_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_89_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_89_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_90_SHIFT                 _MK_SHIFT_CONST(20)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_90_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_90_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_90_RANGE                 21:20
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_90_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_90_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_90_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_90_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_90_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_91_SHIFT                 _MK_SHIFT_CONST(22)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_91_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_91_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_91_RANGE                 23:22
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_91_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_91_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_91_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_91_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_91_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_92_SHIFT                 _MK_SHIFT_CONST(24)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_92_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_92_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_92_RANGE                 25:24
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_92_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_92_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_92_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_92_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_92_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_93_SHIFT                 _MK_SHIFT_CONST(26)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_93_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_93_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_93_RANGE                 27:26
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_93_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_93_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_93_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_93_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_93_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_94_SHIFT                 _MK_SHIFT_CONST(28)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_94_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_94_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_94_RANGE                 29:28
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_94_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_94_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_94_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_94_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_94_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_95_SHIFT                 _MK_SHIFT_CONST(30)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_95_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_95_SHIFT)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_95_RANGE                 31:30
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_95_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_95_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_95_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_95_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_7_0_INT_CONFIG_SPI_95_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INT_CONFIG_8_0  
+#define FIC_DIST_INT_CONFIG_8_0                 _MK_ADDR_CONST(0x1c20)
+#define FIC_DIST_INT_CONFIG_8_0_SECURE                  0x0
+#define FIC_DIST_INT_CONFIG_8_0_WORD_COUNT                      0x1
+#define FIC_DIST_INT_CONFIG_8_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_8_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_8_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_96_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_96_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_96_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_96_RANGE                 1:0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_96_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_96_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_96_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_96_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_96_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_97_SHIFT                 _MK_SHIFT_CONST(2)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_97_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_97_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_97_RANGE                 3:2
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_97_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_97_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_97_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_97_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_97_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_98_SHIFT                 _MK_SHIFT_CONST(4)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_98_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_98_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_98_RANGE                 5:4
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_98_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_98_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_98_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_98_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_98_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_99_SHIFT                 _MK_SHIFT_CONST(6)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_99_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_99_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_99_RANGE                 7:6
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_99_WOFFSET                       0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_99_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_99_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_99_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_99_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_100_SHIFT                        _MK_SHIFT_CONST(8)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_100_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_100_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_100_RANGE                        9:8
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_100_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_100_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_100_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_100_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_100_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_101_SHIFT                        _MK_SHIFT_CONST(10)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_101_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_101_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_101_RANGE                        11:10
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_101_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_101_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_101_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_101_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_101_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_102_SHIFT                        _MK_SHIFT_CONST(12)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_102_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_102_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_102_RANGE                        13:12
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_102_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_102_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_102_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_102_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_102_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_103_SHIFT                        _MK_SHIFT_CONST(14)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_103_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_103_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_103_RANGE                        15:14
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_103_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_103_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_103_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_103_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_103_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_104_SHIFT                        _MK_SHIFT_CONST(16)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_104_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_104_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_104_RANGE                        17:16
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_104_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_104_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_104_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_104_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_104_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_105_SHIFT                        _MK_SHIFT_CONST(18)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_105_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_105_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_105_RANGE                        19:18
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_105_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_105_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_105_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_105_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_105_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_106_SHIFT                        _MK_SHIFT_CONST(20)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_106_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_106_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_106_RANGE                        21:20
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_106_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_106_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_106_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_106_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_106_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_107_SHIFT                        _MK_SHIFT_CONST(22)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_107_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_107_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_107_RANGE                        23:22
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_107_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_107_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_107_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_107_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_107_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_108_SHIFT                        _MK_SHIFT_CONST(24)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_108_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_108_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_108_RANGE                        25:24
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_108_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_108_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_108_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_108_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_108_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_109_SHIFT                        _MK_SHIFT_CONST(26)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_109_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_109_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_109_RANGE                        27:26
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_109_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_109_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_109_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_109_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_109_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_110_SHIFT                        _MK_SHIFT_CONST(28)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_110_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_110_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_110_RANGE                        29:28
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_110_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_110_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_110_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_110_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_110_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_111_SHIFT                        _MK_SHIFT_CONST(30)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_111_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_111_SHIFT)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_111_RANGE                        31:30
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_111_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_111_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_111_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_111_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_8_0_INT_CONFIG_SPI_111_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_INT_CONFIG_9_0  
+#define FIC_DIST_INT_CONFIG_9_0                 _MK_ADDR_CONST(0x1c24)
+#define FIC_DIST_INT_CONFIG_9_0_SECURE                  0x0
+#define FIC_DIST_INT_CONFIG_9_0_WORD_COUNT                      0x1
+#define FIC_DIST_INT_CONFIG_9_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_9_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_9_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_112_SHIFT                        _MK_SHIFT_CONST(0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_112_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_112_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_112_RANGE                        1:0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_112_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_112_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_112_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_112_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_112_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_113_SHIFT                        _MK_SHIFT_CONST(2)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_113_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_113_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_113_RANGE                        3:2
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_113_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_113_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_113_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_113_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_113_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_114_SHIFT                        _MK_SHIFT_CONST(4)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_114_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_114_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_114_RANGE                        5:4
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_114_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_114_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_114_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_114_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_114_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_115_SHIFT                        _MK_SHIFT_CONST(6)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_115_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_115_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_115_RANGE                        7:6
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_115_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_115_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_115_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_115_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_115_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_116_SHIFT                        _MK_SHIFT_CONST(8)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_116_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_116_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_116_RANGE                        9:8
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_116_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_116_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_116_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_116_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_116_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_117_SHIFT                        _MK_SHIFT_CONST(10)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_117_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_117_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_117_RANGE                        11:10
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_117_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_117_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_117_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_117_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_117_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_118_SHIFT                        _MK_SHIFT_CONST(12)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_118_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_118_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_118_RANGE                        13:12
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_118_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_118_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_118_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_118_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_118_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_119_SHIFT                        _MK_SHIFT_CONST(14)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_119_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_119_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_119_RANGE                        15:14
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_119_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_119_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_119_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_119_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_119_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_120_SHIFT                        _MK_SHIFT_CONST(16)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_120_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_120_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_120_RANGE                        17:16
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_120_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_120_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_120_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_120_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_120_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_121_SHIFT                        _MK_SHIFT_CONST(18)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_121_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_121_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_121_RANGE                        19:18
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_121_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_121_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_121_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_121_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_121_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_122_SHIFT                        _MK_SHIFT_CONST(20)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_122_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_122_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_122_RANGE                        21:20
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_122_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_122_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_122_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_122_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_122_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_123_SHIFT                        _MK_SHIFT_CONST(22)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_123_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_123_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_123_RANGE                        23:22
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_123_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_123_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_123_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_123_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_123_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_124_SHIFT                        _MK_SHIFT_CONST(24)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_124_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_124_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_124_RANGE                        25:24
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_124_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_124_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_124_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_124_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_124_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_125_SHIFT                        _MK_SHIFT_CONST(26)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_125_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_125_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_125_RANGE                        27:26
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_125_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_125_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_125_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_125_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_125_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_126_SHIFT                        _MK_SHIFT_CONST(28)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_126_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_126_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_126_RANGE                        29:28
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_126_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_126_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_126_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_126_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_126_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_127_SHIFT                        _MK_SHIFT_CONST(30)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_127_FIELD                        (_MK_MASK_CONST(0x3) << FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_127_SHIFT)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_127_RANGE                        31:30
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_127_WOFFSET                      0x0
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_127_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_127_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_127_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_INT_CONFIG_9_0_INT_CONFIG_SPI_127_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 7208 [0x1c28] 
+
+// Reserved address 7212 [0x1c2c] 
+
+// Reserved address 7216 [0x1c30] 
+
+// Reserved address 7220 [0x1c34] 
+
+// Reserved address 7224 [0x1c38] 
+
+// Reserved address 7228 [0x1c3c] 
+
+// Reserved address 7232 [0x1c40] 
+
+// Reserved address 7236 [0x1c44] 
+
+// Reserved address 7240 [0x1c48] 
+
+// Reserved address 7244 [0x1c4c] 
+
+// Reserved address 7248 [0x1c50] 
+
+// Reserved address 7252 [0x1c54] 
+
+// Reserved address 7256 [0x1c58] 
+
+// Reserved address 7260 [0x1c5c] 
+
+// Reserved address 7264 [0x1c60] 
+
+// Reserved address 7268 [0x1c64] 
+
+// Reserved address 7272 [0x1c68] 
+
+// Reserved address 7276 [0x1c6c] 
+
+// Reserved address 7280 [0x1c70] 
+
+// Reserved address 7284 [0x1c74] 
+
+// Reserved address 7288 [0x1c78] 
+
+// Reserved address 7292 [0x1c7c] 
+
+// Reserved address 7296 [0x1c80] 
+
+// Reserved address 7300 [0x1c84] 
+
+// Reserved address 7304 [0x1c88] 
+
+// Reserved address 7308 [0x1c8c] 
+
+// Reserved address 7312 [0x1c90] 
+
+// Reserved address 7316 [0x1c94] 
+
+// Reserved address 7320 [0x1c98] 
+
+// Reserved address 7324 [0x1c9c] 
+
+// Reserved address 7328 [0x1ca0] 
+
+// Reserved address 7332 [0x1ca4] 
+
+// Reserved address 7336 [0x1ca8] 
+
+// Reserved address 7340 [0x1cac] 
+
+// Reserved address 7344 [0x1cb0] 
+
+// Reserved address 7348 [0x1cb4] 
+
+// Reserved address 7352 [0x1cb8] 
+
+// Reserved address 7356 [0x1cbc] 
+
+// Reserved address 7360 [0x1cc0] 
+
+// Reserved address 7364 [0x1cc4] 
+
+// Reserved address 7368 [0x1cc8] 
+
+// Reserved address 7372 [0x1ccc] 
+
+// Reserved address 7376 [0x1cd0] 
+
+// Reserved address 7380 [0x1cd4] 
+
+// Reserved address 7384 [0x1cd8] 
+
+// Reserved address 7388 [0x1cdc] 
+
+// Reserved address 7392 [0x1ce0] 
+
+// Reserved address 7396 [0x1ce4] 
+
+// Reserved address 7400 [0x1ce8] 
+
+// Reserved address 7404 [0x1cec] 
+
+// Reserved address 7408 [0x1cf0] 
+
+// Reserved address 7412 [0x1cf4] 
+
+// Reserved address 7416 [0x1cf8] 
+
+// Reserved address 7420 [0x1cfc] 
+
+// Register FIC_DIST_PPI_STATUS_0  // Each bit provides the status of a PPI interrupt
+#define FIC_DIST_PPI_STATUS_0                   _MK_ADDR_CONST(0x1d00)
+#define FIC_DIST_PPI_STATUS_0_SECURE                    0x0
+#define FIC_DIST_PPI_STATUS_0_WORD_COUNT                        0x1
+#define FIC_DIST_PPI_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0xf800)
+#define FIC_DIST_PPI_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xf800)
+#define FIC_DIST_PPI_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_4_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_4_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PPI_STATUS_0_PPI_STATUS_4_SHIFT)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_4_RANGE                        11:11
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_4_WOFFSET                      0x0
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_0_SHIFT                        _MK_SHIFT_CONST(12)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_0_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PPI_STATUS_0_PPI_STATUS_0_SHIFT)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_0_RANGE                        12:12
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_0_WOFFSET                      0x0
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_1_SHIFT                        _MK_SHIFT_CONST(13)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_1_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PPI_STATUS_0_PPI_STATUS_1_SHIFT)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_1_RANGE                        13:13
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_1_WOFFSET                      0x0
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_2_SHIFT                        _MK_SHIFT_CONST(14)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_2_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PPI_STATUS_0_PPI_STATUS_2_SHIFT)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_2_RANGE                        14:14
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_2_WOFFSET                      0x0
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_3_SHIFT                        _MK_SHIFT_CONST(15)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_3_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_PPI_STATUS_0_PPI_STATUS_3_SHIFT)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_3_RANGE                        15:15
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_3_WOFFSET                      0x0
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PPI_STATUS_0_PPI_STATUS_3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_STATUS_1_0  
+#define FIC_DIST_SPI_STATUS_1_0                 _MK_ADDR_CONST(0x1d04)
+#define FIC_DIST_SPI_STATUS_1_0_SECURE                  0x0
+#define FIC_DIST_SPI_STATUS_1_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_STATUS_1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_0_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_0_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_0_RANGE                  0:0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_0_WOFFSET                        0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_1_SHIFT                  _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_1_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_1_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_1_RANGE                  1:1
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_1_WOFFSET                        0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_2_SHIFT                  _MK_SHIFT_CONST(2)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_2_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_2_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_2_RANGE                  2:2
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_2_WOFFSET                        0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_3_SHIFT                  _MK_SHIFT_CONST(3)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_3_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_3_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_3_RANGE                  3:3
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_3_WOFFSET                        0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_4_SHIFT                  _MK_SHIFT_CONST(4)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_4_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_4_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_4_RANGE                  4:4
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_4_WOFFSET                        0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_5_SHIFT                  _MK_SHIFT_CONST(5)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_5_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_5_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_5_RANGE                  5:5
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_5_WOFFSET                        0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_6_SHIFT                  _MK_SHIFT_CONST(6)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_6_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_6_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_6_RANGE                  6:6
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_6_WOFFSET                        0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_7_SHIFT                  _MK_SHIFT_CONST(7)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_7_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_7_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_7_RANGE                  7:7
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_7_WOFFSET                        0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_8_SHIFT                  _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_8_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_8_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_8_RANGE                  8:8
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_8_WOFFSET                        0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_9_SHIFT                  _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_9_FIELD                  (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_9_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_9_RANGE                  9:9
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_9_WOFFSET                        0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_10_SHIFT                 _MK_SHIFT_CONST(10)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_10_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_10_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_10_RANGE                 10:10
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_10_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_11_SHIFT                 _MK_SHIFT_CONST(11)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_11_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_11_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_11_RANGE                 11:11
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_11_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_12_SHIFT                 _MK_SHIFT_CONST(12)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_12_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_12_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_12_RANGE                 12:12
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_12_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_13_SHIFT                 _MK_SHIFT_CONST(13)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_13_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_13_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_13_RANGE                 13:13
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_13_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_14_SHIFT                 _MK_SHIFT_CONST(14)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_14_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_14_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_14_RANGE                 14:14
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_14_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_15_SHIFT                 _MK_SHIFT_CONST(15)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_15_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_15_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_15_RANGE                 15:15
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_15_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_16_SHIFT                 _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_16_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_16_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_16_RANGE                 16:16
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_16_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_16_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_16_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_16_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_16_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_17_SHIFT                 _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_17_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_17_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_17_RANGE                 17:17
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_17_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_17_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_17_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_17_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_17_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_18_SHIFT                 _MK_SHIFT_CONST(18)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_18_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_18_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_18_RANGE                 18:18
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_18_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_18_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_18_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_18_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_18_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_19_SHIFT                 _MK_SHIFT_CONST(19)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_19_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_19_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_19_RANGE                 19:19
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_19_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_19_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_19_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_19_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_19_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_20_SHIFT                 _MK_SHIFT_CONST(20)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_20_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_20_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_20_RANGE                 20:20
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_20_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_20_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_20_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_20_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_20_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_21_SHIFT                 _MK_SHIFT_CONST(21)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_21_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_21_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_21_RANGE                 21:21
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_21_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_21_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_21_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_21_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_21_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_22_SHIFT                 _MK_SHIFT_CONST(22)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_22_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_22_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_22_RANGE                 22:22
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_22_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_22_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_22_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_22_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_22_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_23_SHIFT                 _MK_SHIFT_CONST(23)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_23_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_23_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_23_RANGE                 23:23
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_23_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_23_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_23_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_23_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_23_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_24_SHIFT                 _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_24_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_24_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_24_RANGE                 24:24
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_24_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_24_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_24_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_24_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_24_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_25_SHIFT                 _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_25_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_25_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_25_RANGE                 25:25
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_25_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_25_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_25_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_25_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_25_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_26_SHIFT                 _MK_SHIFT_CONST(26)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_26_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_26_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_26_RANGE                 26:26
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_26_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_26_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_26_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_26_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_26_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_27_SHIFT                 _MK_SHIFT_CONST(27)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_27_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_27_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_27_RANGE                 27:27
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_27_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_27_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_27_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_27_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_27_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_28_SHIFT                 _MK_SHIFT_CONST(28)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_28_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_28_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_28_RANGE                 28:28
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_28_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_28_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_28_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_28_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_28_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_29_SHIFT                 _MK_SHIFT_CONST(29)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_29_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_29_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_29_RANGE                 29:29
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_29_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_29_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_29_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_29_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_29_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_30_SHIFT                 _MK_SHIFT_CONST(30)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_30_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_30_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_30_RANGE                 30:30
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_30_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_30_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_30_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_30_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_30_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_31_SHIFT                 _MK_SHIFT_CONST(31)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_31_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_31_SHIFT)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_31_RANGE                 31:31
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_31_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_31_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_31_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_31_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_1_0_SPI_STATUS_SPI_31_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_STATUS_2_0  
+#define FIC_DIST_SPI_STATUS_2_0                 _MK_ADDR_CONST(0x1d08)
+#define FIC_DIST_SPI_STATUS_2_0_SECURE                  0x0
+#define FIC_DIST_SPI_STATUS_2_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_STATUS_2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_32_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_32_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_32_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_32_RANGE                 0:0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_32_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_32_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_32_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_32_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_32_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_33_SHIFT                 _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_33_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_33_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_33_RANGE                 1:1
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_33_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_33_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_33_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_33_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_33_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_34_SHIFT                 _MK_SHIFT_CONST(2)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_34_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_34_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_34_RANGE                 2:2
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_34_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_34_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_34_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_34_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_34_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_35_SHIFT                 _MK_SHIFT_CONST(3)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_35_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_35_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_35_RANGE                 3:3
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_35_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_35_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_35_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_35_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_35_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_36_SHIFT                 _MK_SHIFT_CONST(4)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_36_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_36_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_36_RANGE                 4:4
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_36_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_36_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_36_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_36_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_36_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_37_SHIFT                 _MK_SHIFT_CONST(5)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_37_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_37_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_37_RANGE                 5:5
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_37_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_37_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_37_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_37_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_37_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_38_SHIFT                 _MK_SHIFT_CONST(6)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_38_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_38_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_38_RANGE                 6:6
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_38_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_38_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_38_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_38_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_38_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_39_SHIFT                 _MK_SHIFT_CONST(7)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_39_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_39_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_39_RANGE                 7:7
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_39_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_39_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_39_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_39_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_39_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_40_SHIFT                 _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_40_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_40_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_40_RANGE                 8:8
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_40_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_40_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_40_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_40_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_40_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_41_SHIFT                 _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_41_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_41_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_41_RANGE                 9:9
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_41_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_41_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_41_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_41_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_41_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_42_SHIFT                 _MK_SHIFT_CONST(10)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_42_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_42_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_42_RANGE                 10:10
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_42_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_42_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_42_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_42_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_42_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_43_SHIFT                 _MK_SHIFT_CONST(11)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_43_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_43_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_43_RANGE                 11:11
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_43_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_43_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_43_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_43_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_43_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_44_SHIFT                 _MK_SHIFT_CONST(12)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_44_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_44_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_44_RANGE                 12:12
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_44_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_44_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_44_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_44_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_44_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_45_SHIFT                 _MK_SHIFT_CONST(13)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_45_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_45_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_45_RANGE                 13:13
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_45_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_45_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_45_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_45_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_45_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_46_SHIFT                 _MK_SHIFT_CONST(14)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_46_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_46_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_46_RANGE                 14:14
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_46_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_46_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_46_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_46_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_46_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_47_SHIFT                 _MK_SHIFT_CONST(15)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_47_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_47_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_47_RANGE                 15:15
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_47_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_47_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_47_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_47_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_47_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_48_SHIFT                 _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_48_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_48_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_48_RANGE                 16:16
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_48_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_48_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_48_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_48_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_48_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_49_SHIFT                 _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_49_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_49_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_49_RANGE                 17:17
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_49_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_49_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_49_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_49_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_49_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_50_SHIFT                 _MK_SHIFT_CONST(18)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_50_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_50_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_50_RANGE                 18:18
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_50_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_50_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_50_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_50_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_50_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_51_SHIFT                 _MK_SHIFT_CONST(19)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_51_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_51_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_51_RANGE                 19:19
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_51_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_51_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_51_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_51_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_51_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_52_SHIFT                 _MK_SHIFT_CONST(20)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_52_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_52_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_52_RANGE                 20:20
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_52_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_52_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_52_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_52_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_52_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_53_SHIFT                 _MK_SHIFT_CONST(21)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_53_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_53_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_53_RANGE                 21:21
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_53_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_53_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_53_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_53_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_53_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_54_SHIFT                 _MK_SHIFT_CONST(22)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_54_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_54_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_54_RANGE                 22:22
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_54_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_54_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_54_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_54_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_54_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_55_SHIFT                 _MK_SHIFT_CONST(23)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_55_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_55_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_55_RANGE                 23:23
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_55_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_55_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_55_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_55_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_55_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_56_SHIFT                 _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_56_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_56_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_56_RANGE                 24:24
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_56_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_56_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_56_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_56_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_56_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_57_SHIFT                 _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_57_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_57_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_57_RANGE                 25:25
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_57_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_57_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_57_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_57_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_57_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_58_SHIFT                 _MK_SHIFT_CONST(26)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_58_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_58_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_58_RANGE                 26:26
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_58_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_58_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_58_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_58_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_58_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_59_SHIFT                 _MK_SHIFT_CONST(27)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_59_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_59_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_59_RANGE                 27:27
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_59_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_59_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_59_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_59_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_59_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_60_SHIFT                 _MK_SHIFT_CONST(28)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_60_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_60_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_60_RANGE                 28:28
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_60_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_60_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_60_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_60_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_60_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_61_SHIFT                 _MK_SHIFT_CONST(29)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_61_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_61_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_61_RANGE                 29:29
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_61_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_61_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_61_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_61_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_61_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_62_SHIFT                 _MK_SHIFT_CONST(30)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_62_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_62_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_62_RANGE                 30:30
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_62_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_62_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_62_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_62_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_62_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_63_SHIFT                 _MK_SHIFT_CONST(31)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_63_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_63_SHIFT)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_63_RANGE                 31:31
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_63_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_63_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_63_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_63_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_2_0_SPI_STATUS_SPI_63_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_STATUS_3_0  
+#define FIC_DIST_SPI_STATUS_3_0                 _MK_ADDR_CONST(0x1d0c)
+#define FIC_DIST_SPI_STATUS_3_0_SECURE                  0x0
+#define FIC_DIST_SPI_STATUS_3_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_STATUS_3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_64_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_64_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_64_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_64_RANGE                 0:0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_64_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_64_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_64_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_64_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_64_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_65_SHIFT                 _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_65_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_65_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_65_RANGE                 1:1
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_65_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_65_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_65_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_65_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_65_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_66_SHIFT                 _MK_SHIFT_CONST(2)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_66_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_66_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_66_RANGE                 2:2
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_66_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_66_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_66_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_66_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_66_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_67_SHIFT                 _MK_SHIFT_CONST(3)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_67_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_67_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_67_RANGE                 3:3
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_67_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_67_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_67_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_67_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_67_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_68_SHIFT                 _MK_SHIFT_CONST(4)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_68_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_68_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_68_RANGE                 4:4
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_68_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_68_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_68_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_68_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_68_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_69_SHIFT                 _MK_SHIFT_CONST(5)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_69_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_69_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_69_RANGE                 5:5
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_69_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_69_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_69_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_69_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_69_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_70_SHIFT                 _MK_SHIFT_CONST(6)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_70_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_70_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_70_RANGE                 6:6
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_70_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_70_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_70_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_70_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_70_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_71_SHIFT                 _MK_SHIFT_CONST(7)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_71_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_71_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_71_RANGE                 7:7
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_71_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_71_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_71_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_71_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_71_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_72_SHIFT                 _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_72_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_72_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_72_RANGE                 8:8
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_72_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_72_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_72_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_72_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_72_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_73_SHIFT                 _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_73_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_73_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_73_RANGE                 9:9
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_73_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_73_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_73_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_73_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_73_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_74_SHIFT                 _MK_SHIFT_CONST(10)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_74_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_74_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_74_RANGE                 10:10
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_74_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_74_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_74_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_74_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_74_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_75_SHIFT                 _MK_SHIFT_CONST(11)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_75_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_75_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_75_RANGE                 11:11
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_75_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_75_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_75_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_75_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_75_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_76_SHIFT                 _MK_SHIFT_CONST(12)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_76_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_76_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_76_RANGE                 12:12
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_76_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_76_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_76_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_76_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_76_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_77_SHIFT                 _MK_SHIFT_CONST(13)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_77_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_77_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_77_RANGE                 13:13
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_77_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_77_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_77_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_77_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_77_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_78_SHIFT                 _MK_SHIFT_CONST(14)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_78_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_78_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_78_RANGE                 14:14
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_78_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_78_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_78_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_78_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_78_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_79_SHIFT                 _MK_SHIFT_CONST(15)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_79_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_79_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_79_RANGE                 15:15
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_79_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_79_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_79_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_79_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_79_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_80_SHIFT                 _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_80_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_80_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_80_RANGE                 16:16
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_80_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_80_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_80_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_80_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_80_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_81_SHIFT                 _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_81_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_81_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_81_RANGE                 17:17
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_81_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_81_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_81_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_81_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_81_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_82_SHIFT                 _MK_SHIFT_CONST(18)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_82_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_82_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_82_RANGE                 18:18
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_82_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_82_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_82_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_82_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_82_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_83_SHIFT                 _MK_SHIFT_CONST(19)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_83_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_83_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_83_RANGE                 19:19
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_83_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_83_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_83_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_83_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_83_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_84_SHIFT                 _MK_SHIFT_CONST(20)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_84_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_84_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_84_RANGE                 20:20
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_84_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_84_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_84_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_84_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_84_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_85_SHIFT                 _MK_SHIFT_CONST(21)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_85_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_85_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_85_RANGE                 21:21
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_85_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_85_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_85_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_85_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_85_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_86_SHIFT                 _MK_SHIFT_CONST(22)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_86_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_86_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_86_RANGE                 22:22
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_86_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_86_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_86_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_86_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_86_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_87_SHIFT                 _MK_SHIFT_CONST(23)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_87_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_87_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_87_RANGE                 23:23
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_87_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_87_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_87_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_87_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_87_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_88_SHIFT                 _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_88_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_88_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_88_RANGE                 24:24
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_88_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_88_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_88_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_88_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_88_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_89_SHIFT                 _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_89_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_89_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_89_RANGE                 25:25
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_89_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_89_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_89_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_89_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_89_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_90_SHIFT                 _MK_SHIFT_CONST(26)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_90_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_90_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_90_RANGE                 26:26
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_90_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_90_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_90_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_90_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_90_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_91_SHIFT                 _MK_SHIFT_CONST(27)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_91_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_91_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_91_RANGE                 27:27
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_91_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_91_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_91_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_91_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_91_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_92_SHIFT                 _MK_SHIFT_CONST(28)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_92_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_92_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_92_RANGE                 28:28
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_92_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_92_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_92_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_92_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_92_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_93_SHIFT                 _MK_SHIFT_CONST(29)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_93_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_93_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_93_RANGE                 29:29
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_93_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_93_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_93_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_93_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_93_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_94_SHIFT                 _MK_SHIFT_CONST(30)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_94_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_94_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_94_RANGE                 30:30
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_94_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_94_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_94_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_94_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_94_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_95_SHIFT                 _MK_SHIFT_CONST(31)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_95_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_95_SHIFT)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_95_RANGE                 31:31
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_95_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_95_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_95_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_95_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_3_0_SPI_STATUS_SPI_95_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_SPI_STATUS_4_0  
+#define FIC_DIST_SPI_STATUS_4_0                 _MK_ADDR_CONST(0x1d10)
+#define FIC_DIST_SPI_STATUS_4_0_SECURE                  0x0
+#define FIC_DIST_SPI_STATUS_4_0_WORD_COUNT                      0x1
+#define FIC_DIST_SPI_STATUS_4_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_96_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_96_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_96_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_96_RANGE                 0:0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_96_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_96_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_96_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_96_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_96_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_97_SHIFT                 _MK_SHIFT_CONST(1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_97_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_97_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_97_RANGE                 1:1
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_97_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_97_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_97_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_97_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_97_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_98_SHIFT                 _MK_SHIFT_CONST(2)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_98_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_98_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_98_RANGE                 2:2
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_98_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_98_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_98_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_98_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_98_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_99_SHIFT                 _MK_SHIFT_CONST(3)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_99_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_99_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_99_RANGE                 3:3
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_99_WOFFSET                       0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_99_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_99_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_99_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_99_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_100_SHIFT                        _MK_SHIFT_CONST(4)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_100_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_100_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_100_RANGE                        4:4
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_100_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_100_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_100_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_100_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_100_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_101_SHIFT                        _MK_SHIFT_CONST(5)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_101_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_101_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_101_RANGE                        5:5
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_101_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_101_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_101_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_101_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_101_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_102_SHIFT                        _MK_SHIFT_CONST(6)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_102_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_102_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_102_RANGE                        6:6
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_102_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_102_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_102_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_102_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_102_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_103_SHIFT                        _MK_SHIFT_CONST(7)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_103_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_103_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_103_RANGE                        7:7
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_103_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_103_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_103_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_103_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_103_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_104_SHIFT                        _MK_SHIFT_CONST(8)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_104_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_104_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_104_RANGE                        8:8
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_104_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_104_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_104_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_104_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_104_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_105_SHIFT                        _MK_SHIFT_CONST(9)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_105_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_105_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_105_RANGE                        9:9
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_105_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_105_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_105_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_105_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_105_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_106_SHIFT                        _MK_SHIFT_CONST(10)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_106_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_106_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_106_RANGE                        10:10
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_106_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_106_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_106_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_106_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_106_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_107_SHIFT                        _MK_SHIFT_CONST(11)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_107_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_107_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_107_RANGE                        11:11
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_107_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_107_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_107_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_107_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_107_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_108_SHIFT                        _MK_SHIFT_CONST(12)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_108_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_108_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_108_RANGE                        12:12
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_108_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_108_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_108_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_108_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_108_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_109_SHIFT                        _MK_SHIFT_CONST(13)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_109_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_109_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_109_RANGE                        13:13
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_109_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_109_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_109_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_109_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_109_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_110_SHIFT                        _MK_SHIFT_CONST(14)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_110_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_110_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_110_RANGE                        14:14
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_110_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_110_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_110_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_110_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_110_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_111_SHIFT                        _MK_SHIFT_CONST(15)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_111_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_111_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_111_RANGE                        15:15
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_111_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_111_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_111_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_111_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_111_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_112_SHIFT                        _MK_SHIFT_CONST(16)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_112_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_112_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_112_RANGE                        16:16
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_112_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_112_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_112_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_112_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_112_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_113_SHIFT                        _MK_SHIFT_CONST(17)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_113_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_113_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_113_RANGE                        17:17
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_113_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_113_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_113_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_113_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_113_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_114_SHIFT                        _MK_SHIFT_CONST(18)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_114_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_114_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_114_RANGE                        18:18
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_114_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_114_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_114_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_114_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_114_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_115_SHIFT                        _MK_SHIFT_CONST(19)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_115_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_115_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_115_RANGE                        19:19
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_115_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_115_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_115_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_115_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_115_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_116_SHIFT                        _MK_SHIFT_CONST(20)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_116_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_116_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_116_RANGE                        20:20
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_116_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_116_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_116_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_116_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_116_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_117_SHIFT                        _MK_SHIFT_CONST(21)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_117_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_117_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_117_RANGE                        21:21
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_117_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_117_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_117_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_117_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_117_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_118_SHIFT                        _MK_SHIFT_CONST(22)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_118_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_118_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_118_RANGE                        22:22
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_118_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_118_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_118_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_118_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_118_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_119_SHIFT                        _MK_SHIFT_CONST(23)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_119_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_119_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_119_RANGE                        23:23
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_119_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_119_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_119_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_119_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_119_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_120_SHIFT                        _MK_SHIFT_CONST(24)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_120_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_120_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_120_RANGE                        24:24
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_120_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_120_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_120_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_120_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_120_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_121_SHIFT                        _MK_SHIFT_CONST(25)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_121_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_121_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_121_RANGE                        25:25
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_121_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_121_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_121_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_121_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_121_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_122_SHIFT                        _MK_SHIFT_CONST(26)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_122_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_122_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_122_RANGE                        26:26
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_122_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_122_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_122_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_122_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_122_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_123_SHIFT                        _MK_SHIFT_CONST(27)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_123_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_123_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_123_RANGE                        27:27
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_123_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_123_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_123_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_123_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_123_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_124_SHIFT                        _MK_SHIFT_CONST(28)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_124_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_124_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_124_RANGE                        28:28
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_124_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_124_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_124_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_124_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_124_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_125_SHIFT                        _MK_SHIFT_CONST(29)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_125_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_125_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_125_RANGE                        29:29
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_125_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_125_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_125_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_125_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_125_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_126_SHIFT                        _MK_SHIFT_CONST(30)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_126_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_126_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_126_RANGE                        30:30
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_126_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_126_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_126_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_126_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_126_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_127_SHIFT                        _MK_SHIFT_CONST(31)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_127_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_127_SHIFT)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_127_RANGE                        31:31
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_127_WOFFSET                      0x0
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_127_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_127_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_127_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_SPI_STATUS_4_0_SPI_STATUS_SPI_127_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 7444 [0x1d14] 
+
+// Reserved address 7448 [0x1d18] 
+
+// Reserved address 7452 [0x1d1c] 
+
+// Reserved address 7456 [0x1d20] 
+
+// Reserved address 7460 [0x1d24] 
+
+// Reserved address 7464 [0x1d28] 
+
+// Reserved address 7468 [0x1d2c] 
+
+// Reserved address 7472 [0x1d30] 
+
+// Reserved address 7476 [0x1d34] 
+
+// Reserved address 7480 [0x1d38] 
+
+// Reserved address 7484 [0x1d3c] 
+
+// Reserved address 7488 [0x1d40] 
+
+// Reserved address 7492 [0x1d44] 
+
+// Reserved address 7496 [0x1d48] 
+
+// Reserved address 7500 [0x1d4c] 
+
+// Reserved address 7504 [0x1d50] 
+
+// Reserved address 7508 [0x1d54] 
+
+// Reserved address 7512 [0x1d58] 
+
+// Reserved address 7516 [0x1d5c] 
+
+// Reserved address 7520 [0x1d60] 
+
+// Reserved address 7524 [0x1d64] 
+
+// Reserved address 7528 [0x1d68] 
+
+// Reserved address 7532 [0x1d6c] 
+
+// Reserved address 7536 [0x1d70] 
+
+// Reserved address 7540 [0x1d74] 
+
+// Reserved address 7544 [0x1d78] 
+
+// Reserved address 7548 [0x1d7c] 
+
+// Reserved address 7552 [0x1d80] 
+
+// Reserved address 7556 [0x1d84] 
+
+// Reserved address 7560 [0x1d88] 
+
+// Reserved address 7564 [0x1d8c] 
+
+// Reserved address 7568 [0x1d90] 
+
+// Reserved address 7572 [0x1d94] 
+
+// Reserved address 7576 [0x1d98] 
+
+// Reserved address 7580 [0x1d9c] 
+
+// Reserved address 7584 [0x1da0] 
+
+// Reserved address 7588 [0x1da4] 
+
+// Reserved address 7592 [0x1da8] 
+
+// Reserved address 7596 [0x1dac] 
+
+// Reserved address 7600 [0x1db0] 
+
+// Reserved address 7604 [0x1db4] 
+
+// Reserved address 7608 [0x1db8] 
+
+// Reserved address 7612 [0x1dbc] 
+
+// Reserved address 7616 [0x1dc0] 
+
+// Reserved address 7620 [0x1dc4] 
+
+// Reserved address 7624 [0x1dc8] 
+
+// Reserved address 7628 [0x1dcc] 
+
+// Reserved address 7632 [0x1dd0] 
+
+// Reserved address 7636 [0x1dd4] 
+
+// Reserved address 7640 [0x1dd8] 
+
+// Reserved address 7644 [0x1ddc] 
+
+// Reserved address 7648 [0x1de0] 
+
+// Reserved address 7652 [0x1de4] 
+
+// Reserved address 7656 [0x1de8] 
+
+// Reserved address 7660 [0x1dec] 
+
+// Reserved address 7664 [0x1df0] 
+
+// Reserved address 7668 [0x1df4] 
+
+// Reserved address 7672 [0x1df8] 
+
+// Reserved address 7676 [0x1dfc] 
+
+// Reserved address 7680 [0x1e00] 
+
+// Reserved address 7684 [0x1e04] 
+
+// Reserved address 7688 [0x1e08] 
+
+// Reserved address 7692 [0x1e0c] 
+
+// Reserved address 7696 [0x1e10] 
+
+// Reserved address 7700 [0x1e14] 
+
+// Reserved address 7704 [0x1e18] 
+
+// Reserved address 7708 [0x1e1c] 
+
+// Reserved address 7712 [0x1e20] 
+
+// Reserved address 7716 [0x1e24] 
+
+// Reserved address 7720 [0x1e28] 
+
+// Reserved address 7724 [0x1e2c] 
+
+// Reserved address 7728 [0x1e30] 
+
+// Reserved address 7732 [0x1e34] 
+
+// Reserved address 7736 [0x1e38] 
+
+// Reserved address 7740 [0x1e3c] 
+
+// Reserved address 7744 [0x1e40] 
+
+// Reserved address 7748 [0x1e44] 
+
+// Reserved address 7752 [0x1e48] 
+
+// Reserved address 7756 [0x1e4c] 
+
+// Reserved address 7760 [0x1e50] 
+
+// Reserved address 7764 [0x1e54] 
+
+// Reserved address 7768 [0x1e58] 
+
+// Reserved address 7772 [0x1e5c] 
+
+// Reserved address 7776 [0x1e60] 
+
+// Reserved address 7780 [0x1e64] 
+
+// Reserved address 7784 [0x1e68] 
+
+// Reserved address 7788 [0x1e6c] 
+
+// Reserved address 7792 [0x1e70] 
+
+// Reserved address 7796 [0x1e74] 
+
+// Reserved address 7800 [0x1e78] 
+
+// Reserved address 7804 [0x1e7c] 
+
+// Reserved address 7808 [0x1e80] 
+
+// Reserved address 7812 [0x1e84] 
+
+// Reserved address 7816 [0x1e88] 
+
+// Reserved address 7820 [0x1e8c] 
+
+// Reserved address 7824 [0x1e90] 
+
+// Reserved address 7828 [0x1e94] 
+
+// Reserved address 7832 [0x1e98] 
+
+// Reserved address 7836 [0x1e9c] 
+
+// Reserved address 7840 [0x1ea0] 
+
+// Reserved address 7844 [0x1ea4] 
+
+// Reserved address 7848 [0x1ea8] 
+
+// Reserved address 7852 [0x1eac] 
+
+// Reserved address 7856 [0x1eb0] 
+
+// Reserved address 7860 [0x1eb4] 
+
+// Reserved address 7864 [0x1eb8] 
+
+// Reserved address 7868 [0x1ebc] 
+
+// Reserved address 7872 [0x1ec0] 
+
+// Reserved address 7876 [0x1ec4] 
+
+// Reserved address 7880 [0x1ec8] 
+
+// Reserved address 7884 [0x1ecc] 
+
+// Reserved address 7888 [0x1ed0] 
+
+// Reserved address 7892 [0x1ed4] 
+
+// Reserved address 7896 [0x1ed8] 
+
+// Reserved address 7900 [0x1edc] 
+
+// Reserved address 7904 [0x1ee0] 
+
+// Reserved address 7908 [0x1ee4] 
+
+// Reserved address 7912 [0x1ee8] 
+
+// Reserved address 7916 [0x1eec] 
+
+// Reserved address 7920 [0x1ef0] 
+
+// Reserved address 7924 [0x1ef4] 
+
+// Reserved address 7928 [0x1ef8] 
+
+// Reserved address 7932 [0x1efc] 
+
+// Register FIC_DIST_STI_TRIGGER_0  // Controls the issuing of software interrupts.
+#define FIC_DIST_STI_TRIGGER_0                  _MK_ADDR_CONST(0x1f00)
+#define FIC_DIST_STI_TRIGGER_0_SECURE                   0x0
+#define FIC_DIST_STI_TRIGGER_0_WORD_COUNT                       0x1
+#define FIC_DIST_STI_TRIGGER_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_RESET_MASK                       _MK_MASK_CONST(0x303800f)
+#define FIC_DIST_STI_TRIGGER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_READ_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_WRITE_MASK                       _MK_MASK_CONST(0x303800f)
+#define FIC_DIST_STI_TRIGGER_0_STI_INTID_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_DIST_STI_TRIGGER_0_STI_INTID_FIELD                  (_MK_MASK_CONST(0xf) << FIC_DIST_STI_TRIGGER_0_STI_INTID_SHIFT)
+#define FIC_DIST_STI_TRIGGER_0_STI_INTID_RANGE                  3:0
+#define FIC_DIST_STI_TRIGGER_0_STI_INTID_WOFFSET                        0x0
+#define FIC_DIST_STI_TRIGGER_0_STI_INTID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_STI_INTID_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define FIC_DIST_STI_TRIGGER_0_STI_INTID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_STI_INTID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_STI_TRIGGER_0_SATT_SHIFT                       _MK_SHIFT_CONST(15)
+#define FIC_DIST_STI_TRIGGER_0_SATT_FIELD                       (_MK_MASK_CONST(0x1) << FIC_DIST_STI_TRIGGER_0_SATT_SHIFT)
+#define FIC_DIST_STI_TRIGGER_0_SATT_RANGE                       15:15
+#define FIC_DIST_STI_TRIGGER_0_SATT_WOFFSET                     0x0
+#define FIC_DIST_STI_TRIGGER_0_SATT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_SATT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FIC_DIST_STI_TRIGGER_0_SATT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_SATT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU0_SHIFT                        _MK_SHIFT_CONST(16)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU0_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_STI_TRIGGER_0_TARGET_CPU0_SHIFT)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU0_RANGE                        16:16
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU0_WOFFSET                      0x0
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU1_SHIFT                        _MK_SHIFT_CONST(17)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU1_FIELD                        (_MK_MASK_CONST(0x1) << FIC_DIST_STI_TRIGGER_0_TARGET_CPU1_SHIFT)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU1_RANGE                        17:17
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU1_WOFFSET                      0x0
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_CPU1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_SHIFT                 _MK_SHIFT_CONST(24)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_FIELD                 (_MK_MASK_CONST(0x3) << FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_SHIFT)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_RANGE                 25:24
+#define FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_WOFFSET                       0x0
+#define FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_SPECIFIC_CPU                  _MK_ENUM_CONST(0)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_ALL_BUT_SELF                  _MK_ENUM_CONST(1)
+#define FIC_DIST_STI_TRIGGER_0_TARGET_LIST_FILTER_SELF                  _MK_ENUM_CONST(2)
+
+
+// Reserved address 7940 [0x1f04] 
+
+// Reserved address 7944 [0x1f08] 
+
+// Reserved address 7948 [0x1f0c] 
+
+// Reserved address 7952 [0x1f10] 
+
+// Reserved address 7956 [0x1f14] 
+
+// Reserved address 7960 [0x1f18] 
+
+// Reserved address 7964 [0x1f1c] 
+
+// Reserved address 7968 [0x1f20] 
+
+// Reserved address 7972 [0x1f24] 
+
+// Reserved address 7976 [0x1f28] 
+
+// Reserved address 7980 [0x1f2c] 
+
+// Reserved address 7984 [0x1f30] 
+
+// Reserved address 7988 [0x1f34] 
+
+// Reserved address 7992 [0x1f38] 
+
+// Reserved address 7996 [0x1f3c] 
+
+// Reserved address 8000 [0x1f40] 
+
+// Reserved address 8004 [0x1f44] 
+
+// Reserved address 8008 [0x1f48] 
+
+// Reserved address 8012 [0x1f4c] 
+
+// Reserved address 8016 [0x1f50] 
+
+// Reserved address 8020 [0x1f54] 
+
+// Reserved address 8024 [0x1f58] 
+
+// Reserved address 8028 [0x1f5c] 
+
+// Reserved address 8032 [0x1f60] 
+
+// Reserved address 8036 [0x1f64] 
+
+// Reserved address 8040 [0x1f68] 
+
+// Reserved address 8044 [0x1f6c] 
+
+// Reserved address 8048 [0x1f70] 
+
+// Reserved address 8052 [0x1f74] 
+
+// Reserved address 8056 [0x1f78] 
+
+// Reserved address 8060 [0x1f7c] 
+
+// Reserved address 8064 [0x1f80] 
+
+// Reserved address 8068 [0x1f84] 
+
+// Reserved address 8072 [0x1f88] 
+
+// Reserved address 8076 [0x1f8c] 
+
+// Reserved address 8080 [0x1f90] 
+
+// Reserved address 8084 [0x1f94] 
+
+// Reserved address 8088 [0x1f98] 
+
+// Reserved address 8092 [0x1f9c] 
+
+// Reserved address 8096 [0x1fa0] 
+
+// Reserved address 8100 [0x1fa4] 
+
+// Reserved address 8104 [0x1fa8] 
+
+// Reserved address 8108 [0x1fac] 
+
+// Reserved address 8112 [0x1fb0] 
+
+// Reserved address 8116 [0x1fb4] 
+
+// Reserved address 8120 [0x1fb8] 
+
+// Reserved address 8124 [0x1fbc] 
+
+// Reserved address 8128 [0x1fc0] 
+
+// Reserved address 8132 [0x1fc4] 
+
+// Reserved address 8136 [0x1fc8] 
+
+// Reserved address 8140 [0x1fcc] 
+
+// Register FIC_DIST_PERIPH_ID_0_0  
+#define FIC_DIST_PERIPH_ID_0_0                  _MK_ADDR_CONST(0x1fd0)
+#define FIC_DIST_PERIPH_ID_0_0_SECURE                   0x0
+#define FIC_DIST_PERIPH_ID_0_0_WORD_COUNT                       0x1
+#define FIC_DIST_PERIPH_ID_0_0_RESET_VAL                        _MK_MASK_CONST(0x90)
+#define FIC_DIST_PERIPH_ID_0_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define FIC_DIST_PERIPH_ID_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_0_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define FIC_DIST_PERIPH_ID_0_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_0_0_PART_NUMBER_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FIC_DIST_PERIPH_ID_0_0_PART_NUMBER_0_FIELD                      (_MK_MASK_CONST(0xff) << FIC_DIST_PERIPH_ID_0_0_PART_NUMBER_0_SHIFT)
+#define FIC_DIST_PERIPH_ID_0_0_PART_NUMBER_0_RANGE                      7:0
+#define FIC_DIST_PERIPH_ID_0_0_PART_NUMBER_0_WOFFSET                    0x0
+#define FIC_DIST_PERIPH_ID_0_0_PART_NUMBER_0_DEFAULT                    _MK_MASK_CONST(0x90)
+#define FIC_DIST_PERIPH_ID_0_0_PART_NUMBER_0_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FIC_DIST_PERIPH_ID_0_0_PART_NUMBER_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_0_0_PART_NUMBER_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PERIPH_ID_1_0  
+#define FIC_DIST_PERIPH_ID_1_0                  _MK_ADDR_CONST(0x1fd4)
+#define FIC_DIST_PERIPH_ID_1_0_SECURE                   0x0
+#define FIC_DIST_PERIPH_ID_1_0_WORD_COUNT                       0x1
+#define FIC_DIST_PERIPH_ID_1_0_RESET_VAL                        _MK_MASK_CONST(0xb3)
+#define FIC_DIST_PERIPH_ID_1_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define FIC_DIST_PERIPH_ID_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_1_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define FIC_DIST_PERIPH_ID_1_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_1_0_PART_NUMBER_1_SHIFT                      _MK_SHIFT_CONST(0)
+#define FIC_DIST_PERIPH_ID_1_0_PART_NUMBER_1_FIELD                      (_MK_MASK_CONST(0xf) << FIC_DIST_PERIPH_ID_1_0_PART_NUMBER_1_SHIFT)
+#define FIC_DIST_PERIPH_ID_1_0_PART_NUMBER_1_RANGE                      3:0
+#define FIC_DIST_PERIPH_ID_1_0_PART_NUMBER_1_WOFFSET                    0x0
+#define FIC_DIST_PERIPH_ID_1_0_PART_NUMBER_1_DEFAULT                    _MK_MASK_CONST(0x3)
+#define FIC_DIST_PERIPH_ID_1_0_PART_NUMBER_1_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define FIC_DIST_PERIPH_ID_1_0_PART_NUMBER_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_1_0_PART_NUMBER_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PERIPH_ID_1_0_JEP106_ID_3_0_SHIFT                      _MK_SHIFT_CONST(4)
+#define FIC_DIST_PERIPH_ID_1_0_JEP106_ID_3_0_FIELD                      (_MK_MASK_CONST(0xf) << FIC_DIST_PERIPH_ID_1_0_JEP106_ID_3_0_SHIFT)
+#define FIC_DIST_PERIPH_ID_1_0_JEP106_ID_3_0_RANGE                      7:4
+#define FIC_DIST_PERIPH_ID_1_0_JEP106_ID_3_0_WOFFSET                    0x0
+#define FIC_DIST_PERIPH_ID_1_0_JEP106_ID_3_0_DEFAULT                    _MK_MASK_CONST(0xb)
+#define FIC_DIST_PERIPH_ID_1_0_JEP106_ID_3_0_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define FIC_DIST_PERIPH_ID_1_0_JEP106_ID_3_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_1_0_JEP106_ID_3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PERIPH_ID_2_0  
+#define FIC_DIST_PERIPH_ID_2_0                  _MK_ADDR_CONST(0x1fd8)
+#define FIC_DIST_PERIPH_ID_2_0_SECURE                   0x0
+#define FIC_DIST_PERIPH_ID_2_0_WORD_COUNT                       0x1
+#define FIC_DIST_PERIPH_ID_2_0_RESET_VAL                        _MK_MASK_CONST(0xb)
+#define FIC_DIST_PERIPH_ID_2_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define FIC_DIST_PERIPH_ID_2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_2_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define FIC_DIST_PERIPH_ID_2_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_2_0_JEP106_ID_6_4_SHIFT                      _MK_SHIFT_CONST(0)
+#define FIC_DIST_PERIPH_ID_2_0_JEP106_ID_6_4_FIELD                      (_MK_MASK_CONST(0x7) << FIC_DIST_PERIPH_ID_2_0_JEP106_ID_6_4_SHIFT)
+#define FIC_DIST_PERIPH_ID_2_0_JEP106_ID_6_4_RANGE                      2:0
+#define FIC_DIST_PERIPH_ID_2_0_JEP106_ID_6_4_WOFFSET                    0x0
+#define FIC_DIST_PERIPH_ID_2_0_JEP106_ID_6_4_DEFAULT                    _MK_MASK_CONST(0x3)
+#define FIC_DIST_PERIPH_ID_2_0_JEP106_ID_6_4_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define FIC_DIST_PERIPH_ID_2_0_JEP106_ID_6_4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_2_0_JEP106_ID_6_4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PERIPH_ID_2_0_JEDEC_USED_SHIFT                 _MK_SHIFT_CONST(3)
+#define FIC_DIST_PERIPH_ID_2_0_JEDEC_USED_FIELD                 (_MK_MASK_CONST(0x1) << FIC_DIST_PERIPH_ID_2_0_JEDEC_USED_SHIFT)
+#define FIC_DIST_PERIPH_ID_2_0_JEDEC_USED_RANGE                 3:3
+#define FIC_DIST_PERIPH_ID_2_0_JEDEC_USED_WOFFSET                       0x0
+#define FIC_DIST_PERIPH_ID_2_0_JEDEC_USED_DEFAULT                       _MK_MASK_CONST(0x1)
+#define FIC_DIST_PERIPH_ID_2_0_JEDEC_USED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FIC_DIST_PERIPH_ID_2_0_JEDEC_USED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_2_0_JEDEC_USED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PERIPH_ID_2_0_REVISION_SHIFT                   _MK_SHIFT_CONST(4)
+#define FIC_DIST_PERIPH_ID_2_0_REVISION_FIELD                   (_MK_MASK_CONST(0xf) << FIC_DIST_PERIPH_ID_2_0_REVISION_SHIFT)
+#define FIC_DIST_PERIPH_ID_2_0_REVISION_RANGE                   7:4
+#define FIC_DIST_PERIPH_ID_2_0_REVISION_WOFFSET                 0x0
+#define FIC_DIST_PERIPH_ID_2_0_REVISION_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_2_0_REVISION_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define FIC_DIST_PERIPH_ID_2_0_REVISION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_2_0_REVISION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PERIPH_ID_3_0  
+#define FIC_DIST_PERIPH_ID_3_0                  _MK_ADDR_CONST(0x1fdc)
+#define FIC_DIST_PERIPH_ID_3_0_SECURE                   0x0
+#define FIC_DIST_PERIPH_ID_3_0_WORD_COUNT                       0x1
+#define FIC_DIST_PERIPH_ID_3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_3_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define FIC_DIST_PERIPH_ID_3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_3_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define FIC_DIST_PERIPH_ID_3_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_3_0_MOD_NUMBER_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_PERIPH_ID_3_0_MOD_NUMBER_FIELD                 (_MK_MASK_CONST(0x7) << FIC_DIST_PERIPH_ID_3_0_MOD_NUMBER_SHIFT)
+#define FIC_DIST_PERIPH_ID_3_0_MOD_NUMBER_RANGE                 2:0
+#define FIC_DIST_PERIPH_ID_3_0_MOD_NUMBER_WOFFSET                       0x0
+#define FIC_DIST_PERIPH_ID_3_0_MOD_NUMBER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_3_0_MOD_NUMBER_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define FIC_DIST_PERIPH_ID_3_0_MOD_NUMBER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_3_0_MOD_NUMBER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PERIPH_ID_3_0_REV_AND_SHIFT                    _MK_SHIFT_CONST(3)
+#define FIC_DIST_PERIPH_ID_3_0_REV_AND_FIELD                    (_MK_MASK_CONST(0x1) << FIC_DIST_PERIPH_ID_3_0_REV_AND_SHIFT)
+#define FIC_DIST_PERIPH_ID_3_0_REV_AND_RANGE                    3:3
+#define FIC_DIST_PERIPH_ID_3_0_REV_AND_WOFFSET                  0x0
+#define FIC_DIST_PERIPH_ID_3_0_REV_AND_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_3_0_REV_AND_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_DIST_PERIPH_ID_3_0_REV_AND_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_3_0_REV_AND_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PERIPH_ID_4_0  
+#define FIC_DIST_PERIPH_ID_4_0                  _MK_ADDR_CONST(0x1fe0)
+#define FIC_DIST_PERIPH_ID_4_0_SECURE                   0x0
+#define FIC_DIST_PERIPH_ID_4_0_WORD_COUNT                       0x1
+#define FIC_DIST_PERIPH_ID_4_0_RESET_VAL                        _MK_MASK_CONST(0x4)
+#define FIC_DIST_PERIPH_ID_4_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define FIC_DIST_PERIPH_ID_4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_4_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define FIC_DIST_PERIPH_ID_4_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_4_0_JEP106_C_CODE_SHIFT                      _MK_SHIFT_CONST(0)
+#define FIC_DIST_PERIPH_ID_4_0_JEP106_C_CODE_FIELD                      (_MK_MASK_CONST(0xf) << FIC_DIST_PERIPH_ID_4_0_JEP106_C_CODE_SHIFT)
+#define FIC_DIST_PERIPH_ID_4_0_JEP106_C_CODE_RANGE                      3:0
+#define FIC_DIST_PERIPH_ID_4_0_JEP106_C_CODE_WOFFSET                    0x0
+#define FIC_DIST_PERIPH_ID_4_0_JEP106_C_CODE_DEFAULT                    _MK_MASK_CONST(0x4)
+#define FIC_DIST_PERIPH_ID_4_0_JEP106_C_CODE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define FIC_DIST_PERIPH_ID_4_0_JEP106_C_CODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_4_0_JEP106_C_CODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FIC_DIST_PERIPH_ID_4_0_COUNT_4KB_SHIFT                  _MK_SHIFT_CONST(4)
+#define FIC_DIST_PERIPH_ID_4_0_COUNT_4KB_FIELD                  (_MK_MASK_CONST(0xf) << FIC_DIST_PERIPH_ID_4_0_COUNT_4KB_SHIFT)
+#define FIC_DIST_PERIPH_ID_4_0_COUNT_4KB_RANGE                  7:4
+#define FIC_DIST_PERIPH_ID_4_0_COUNT_4KB_WOFFSET                        0x0
+#define FIC_DIST_PERIPH_ID_4_0_COUNT_4KB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_4_0_COUNT_4KB_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define FIC_DIST_PERIPH_ID_4_0_COUNT_4KB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_DIST_PERIPH_ID_4_0_COUNT_4KB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 8164 [0x1fe4] 
+
+// Reserved address 8168 [0x1fe8] 
+
+// Reserved address 8172 [0x1fec] 
+
+// Register FIC_DIST_PRIME_CELL_ID_0_0  
+#define FIC_DIST_PRIME_CELL_ID_0_0                      _MK_ADDR_CONST(0x1ff0)
+#define FIC_DIST_PRIME_CELL_ID_0_0_SECURE                       0x0
+#define FIC_DIST_PRIME_CELL_ID_0_0_WORD_COUNT                   0x1
+#define FIC_DIST_PRIME_CELL_ID_0_0_RESET_VAL                    _MK_MASK_CONST(0xd)
+#define FIC_DIST_PRIME_CELL_ID_0_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_0_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_0_0_COMPONENT_ID_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_PRIME_CELL_ID_0_0_COMPONENT_ID_0_FIELD                 (_MK_MASK_CONST(0xff) << FIC_DIST_PRIME_CELL_ID_0_0_COMPONENT_ID_0_SHIFT)
+#define FIC_DIST_PRIME_CELL_ID_0_0_COMPONENT_ID_0_RANGE                 7:0
+#define FIC_DIST_PRIME_CELL_ID_0_0_COMPONENT_ID_0_WOFFSET                       0x0
+#define FIC_DIST_PRIME_CELL_ID_0_0_COMPONENT_ID_0_DEFAULT                       _MK_MASK_CONST(0xd)
+#define FIC_DIST_PRIME_CELL_ID_0_0_COMPONENT_ID_0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_0_0_COMPONENT_ID_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_0_0_COMPONENT_ID_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIME_CELL_ID_1_0  
+#define FIC_DIST_PRIME_CELL_ID_1_0                      _MK_ADDR_CONST(0x1ff4)
+#define FIC_DIST_PRIME_CELL_ID_1_0_SECURE                       0x0
+#define FIC_DIST_PRIME_CELL_ID_1_0_WORD_COUNT                   0x1
+#define FIC_DIST_PRIME_CELL_ID_1_0_RESET_VAL                    _MK_MASK_CONST(0xf0)
+#define FIC_DIST_PRIME_CELL_ID_1_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_1_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_1_0_COMPONENT_ID_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_PRIME_CELL_ID_1_0_COMPONENT_ID_1_FIELD                 (_MK_MASK_CONST(0xff) << FIC_DIST_PRIME_CELL_ID_1_0_COMPONENT_ID_1_SHIFT)
+#define FIC_DIST_PRIME_CELL_ID_1_0_COMPONENT_ID_1_RANGE                 7:0
+#define FIC_DIST_PRIME_CELL_ID_1_0_COMPONENT_ID_1_WOFFSET                       0x0
+#define FIC_DIST_PRIME_CELL_ID_1_0_COMPONENT_ID_1_DEFAULT                       _MK_MASK_CONST(0xf0)
+#define FIC_DIST_PRIME_CELL_ID_1_0_COMPONENT_ID_1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_1_0_COMPONENT_ID_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_1_0_COMPONENT_ID_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIME_CELL_ID_2_0  
+#define FIC_DIST_PRIME_CELL_ID_2_0                      _MK_ADDR_CONST(0x1ff8)
+#define FIC_DIST_PRIME_CELL_ID_2_0_SECURE                       0x0
+#define FIC_DIST_PRIME_CELL_ID_2_0_WORD_COUNT                   0x1
+#define FIC_DIST_PRIME_CELL_ID_2_0_RESET_VAL                    _MK_MASK_CONST(0x5)
+#define FIC_DIST_PRIME_CELL_ID_2_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_2_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_2_0_COMPONENT_ID_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_PRIME_CELL_ID_2_0_COMPONENT_ID_2_FIELD                 (_MK_MASK_CONST(0xff) << FIC_DIST_PRIME_CELL_ID_2_0_COMPONENT_ID_2_SHIFT)
+#define FIC_DIST_PRIME_CELL_ID_2_0_COMPONENT_ID_2_RANGE                 7:0
+#define FIC_DIST_PRIME_CELL_ID_2_0_COMPONENT_ID_2_WOFFSET                       0x0
+#define FIC_DIST_PRIME_CELL_ID_2_0_COMPONENT_ID_2_DEFAULT                       _MK_MASK_CONST(0x5)
+#define FIC_DIST_PRIME_CELL_ID_2_0_COMPONENT_ID_2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_2_0_COMPONENT_ID_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_2_0_COMPONENT_ID_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_DIST_PRIME_CELL_ID_3_0  
+#define FIC_DIST_PRIME_CELL_ID_3_0                      _MK_ADDR_CONST(0x1ffc)
+#define FIC_DIST_PRIME_CELL_ID_3_0_SECURE                       0x0
+#define FIC_DIST_PRIME_CELL_ID_3_0_WORD_COUNT                   0x1
+#define FIC_DIST_PRIME_CELL_ID_3_0_RESET_VAL                    _MK_MASK_CONST(0xb1)
+#define FIC_DIST_PRIME_CELL_ID_3_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_3_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_3_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_3_0_COMPONENT_ID_3_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_DIST_PRIME_CELL_ID_3_0_COMPONENT_ID_3_FIELD                 (_MK_MASK_CONST(0xff) << FIC_DIST_PRIME_CELL_ID_3_0_COMPONENT_ID_3_SHIFT)
+#define FIC_DIST_PRIME_CELL_ID_3_0_COMPONENT_ID_3_RANGE                 7:0
+#define FIC_DIST_PRIME_CELL_ID_3_0_COMPONENT_ID_3_WOFFSET                       0x0
+#define FIC_DIST_PRIME_CELL_ID_3_0_COMPONENT_ID_3_DEFAULT                       _MK_MASK_CONST(0xb1)
+#define FIC_DIST_PRIME_CELL_ID_3_0_COMPONENT_ID_3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FIC_DIST_PRIME_CELL_ID_3_0_COMPONENT_ID_3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_DIST_PRIME_CELL_ID_3_0_COMPONENT_ID_3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARFIC_DIST_REGS(_op_) \
+_op_(FIC_DIST_DISTRIBUTOR_ENABLE_0) \
+_op_(FIC_DIST_IC_TYPE_0) \
+_op_(FIC_DIST_DISTRIBUTOR_IDENT_0) \
+_op_(FIC_DIST_INTERRUPT_SECURITY_0_0) \
+_op_(FIC_DIST_INTERRUPT_SECURITY_1_0) \
+_op_(FIC_DIST_INTERRUPT_SECURITY_2_0) \
+_op_(FIC_DIST_INTERRUPT_SECURITY_3_0) \
+_op_(FIC_DIST_INTERRUPT_SECURITY_4_0) \
+_op_(FIC_DIST_ENABLE_SET_0_0) \
+_op_(FIC_DIST_ENABLE_SET_1_0) \
+_op_(FIC_DIST_ENABLE_SET_2_0) \
+_op_(FIC_DIST_ENABLE_SET_3_0) \
+_op_(FIC_DIST_ENABLE_SET_4_0) \
+_op_(FIC_DIST_ENABLE_CLEAR_0_0) \
+_op_(FIC_DIST_ENABLE_CLEAR_1_0) \
+_op_(FIC_DIST_ENABLE_CLEAR_2_0) \
+_op_(FIC_DIST_ENABLE_CLEAR_3_0) \
+_op_(FIC_DIST_ENABLE_CLEAR_4_0) \
+_op_(FIC_DIST_PENDING_SET_0_0) \
+_op_(FIC_DIST_PENDING_SET_1_0) \
+_op_(FIC_DIST_PENDING_SET_2_0) \
+_op_(FIC_DIST_PENDING_SET_3_0) \
+_op_(FIC_DIST_PENDING_SET_4_0) \
+_op_(FIC_DIST_PENDING_CLEAR_0_0) \
+_op_(FIC_DIST_PENDING_CLEAR_1_0) \
+_op_(FIC_DIST_PENDING_CLEAR_2_0) \
+_op_(FIC_DIST_PENDING_CLEAR_3_0) \
+_op_(FIC_DIST_PENDING_CLEAR_4_0) \
+_op_(FIC_DIST_ACTIVE_STATUS_0_0) \
+_op_(FIC_DIST_ACTIVE_STATUS_1_0) \
+_op_(FIC_DIST_ACTIVE_STATUS_2_0) \
+_op_(FIC_DIST_ACTIVE_STATUS_3_0) \
+_op_(FIC_DIST_ACTIVE_STATUS_4_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_0_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_1_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_2_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_3_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_6_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_7_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_8_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_9_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_10_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_11_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_12_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_13_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_14_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_15_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_16_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_17_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_18_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_19_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_20_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_21_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_22_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_23_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_24_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_25_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_26_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_27_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_28_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_29_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_30_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_31_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_32_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_33_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_34_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_35_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_36_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_37_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_38_0) \
+_op_(FIC_DIST_PRIORITY_LEVEL_39_0) \
+_op_(FIC_DIST_SPI_TARGET_0_0) \
+_op_(FIC_DIST_SPI_TARGET_1_0) \
+_op_(FIC_DIST_SPI_TARGET_2_0) \
+_op_(FIC_DIST_SPI_TARGET_3_0) \
+_op_(FIC_DIST_SPI_TARGET_4_0) \
+_op_(FIC_DIST_SPI_TARGET_5_0) \
+_op_(FIC_DIST_SPI_TARGET_6_0) \
+_op_(FIC_DIST_SPI_TARGET_7_0) \
+_op_(FIC_DIST_SPI_TARGET_8_0) \
+_op_(FIC_DIST_SPI_TARGET_9_0) \
+_op_(FIC_DIST_SPI_TARGET_10_0) \
+_op_(FIC_DIST_SPI_TARGET_11_0) \
+_op_(FIC_DIST_SPI_TARGET_12_0) \
+_op_(FIC_DIST_SPI_TARGET_13_0) \
+_op_(FIC_DIST_SPI_TARGET_14_0) \
+_op_(FIC_DIST_SPI_TARGET_15_0) \
+_op_(FIC_DIST_SPI_TARGET_16_0) \
+_op_(FIC_DIST_SPI_TARGET_17_0) \
+_op_(FIC_DIST_SPI_TARGET_18_0) \
+_op_(FIC_DIST_SPI_TARGET_19_0) \
+_op_(FIC_DIST_SPI_TARGET_20_0) \
+_op_(FIC_DIST_SPI_TARGET_21_0) \
+_op_(FIC_DIST_SPI_TARGET_22_0) \
+_op_(FIC_DIST_SPI_TARGET_23_0) \
+_op_(FIC_DIST_SPI_TARGET_24_0) \
+_op_(FIC_DIST_SPI_TARGET_25_0) \
+_op_(FIC_DIST_SPI_TARGET_26_0) \
+_op_(FIC_DIST_SPI_TARGET_27_0) \
+_op_(FIC_DIST_SPI_TARGET_28_0) \
+_op_(FIC_DIST_SPI_TARGET_29_0) \
+_op_(FIC_DIST_SPI_TARGET_30_0) \
+_op_(FIC_DIST_SPI_TARGET_31_0) \
+_op_(FIC_DIST_SPI_TARGET_32_0) \
+_op_(FIC_DIST_SPI_TARGET_33_0) \
+_op_(FIC_DIST_SPI_TARGET_34_0) \
+_op_(FIC_DIST_SPI_TARGET_35_0) \
+_op_(FIC_DIST_INT_CONFIG_0_0) \
+_op_(FIC_DIST_INT_CONFIG_1_0) \
+_op_(FIC_DIST_INT_CONFIG_2_0) \
+_op_(FIC_DIST_INT_CONFIG_3_0) \
+_op_(FIC_DIST_INT_CONFIG_4_0) \
+_op_(FIC_DIST_INT_CONFIG_5_0) \
+_op_(FIC_DIST_INT_CONFIG_6_0) \
+_op_(FIC_DIST_INT_CONFIG_7_0) \
+_op_(FIC_DIST_INT_CONFIG_8_0) \
+_op_(FIC_DIST_INT_CONFIG_9_0) \
+_op_(FIC_DIST_PPI_STATUS_0) \
+_op_(FIC_DIST_SPI_STATUS_1_0) \
+_op_(FIC_DIST_SPI_STATUS_2_0) \
+_op_(FIC_DIST_SPI_STATUS_3_0) \
+_op_(FIC_DIST_SPI_STATUS_4_0) \
+_op_(FIC_DIST_STI_TRIGGER_0) \
+_op_(FIC_DIST_PERIPH_ID_0_0) \
+_op_(FIC_DIST_PERIPH_ID_1_0) \
+_op_(FIC_DIST_PERIPH_ID_2_0) \
+_op_(FIC_DIST_PERIPH_ID_3_0) \
+_op_(FIC_DIST_PERIPH_ID_4_0) \
+_op_(FIC_DIST_PRIME_CELL_ID_0_0) \
+_op_(FIC_DIST_PRIME_CELL_ID_1_0) \
+_op_(FIC_DIST_PRIME_CELL_ID_2_0) \
+_op_(FIC_DIST_PRIME_CELL_ID_3_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_FIC_DIST   0x00001000
+
+//
+// ARFIC_DIST REGISTER BANKS
+//
+
+#define FIC_DIST0_FIRST_REG 0x1000 // FIC_DIST_DISTRIBUTOR_ENABLE_0
+#define FIC_DIST0_LAST_REG 0x1008 // FIC_DIST_DISTRIBUTOR_IDENT_0
+#define FIC_DIST1_FIRST_REG 0x1080 // FIC_DIST_INTERRUPT_SECURITY_0_0
+#define FIC_DIST1_LAST_REG 0x1090 // FIC_DIST_INTERRUPT_SECURITY_4_0
+#define FIC_DIST2_FIRST_REG 0x1100 // FIC_DIST_ENABLE_SET_0_0
+#define FIC_DIST2_LAST_REG 0x1110 // FIC_DIST_ENABLE_SET_4_0
+#define FIC_DIST3_FIRST_REG 0x1180 // FIC_DIST_ENABLE_CLEAR_0_0
+#define FIC_DIST3_LAST_REG 0x1190 // FIC_DIST_ENABLE_CLEAR_4_0
+#define FIC_DIST4_FIRST_REG 0x1200 // FIC_DIST_PENDING_SET_0_0
+#define FIC_DIST4_LAST_REG 0x1210 // FIC_DIST_PENDING_SET_4_0
+#define FIC_DIST5_FIRST_REG 0x1280 // FIC_DIST_PENDING_CLEAR_0_0
+#define FIC_DIST5_LAST_REG 0x1290 // FIC_DIST_PENDING_CLEAR_4_0
+#define FIC_DIST6_FIRST_REG 0x1300 // FIC_DIST_ACTIVE_STATUS_0_0
+#define FIC_DIST6_LAST_REG 0x1310 // FIC_DIST_ACTIVE_STATUS_4_0
+#define FIC_DIST7_FIRST_REG 0x1400 // FIC_DIST_PRIORITY_LEVEL_0_0
+#define FIC_DIST7_LAST_REG 0x140c // FIC_DIST_PRIORITY_LEVEL_3_0
+#define FIC_DIST8_FIRST_REG 0x1418 // FIC_DIST_PRIORITY_LEVEL_6_0
+#define FIC_DIST8_LAST_REG 0x149c // FIC_DIST_PRIORITY_LEVEL_39_0
+#define FIC_DIST9_FIRST_REG 0x1800 // FIC_DIST_SPI_TARGET_0_0
+#define FIC_DIST9_LAST_REG 0x180c // FIC_DIST_SPI_TARGET_3_0
+#define FIC_DIST10_FIRST_REG 0x1820 // FIC_DIST_SPI_TARGET_4_0
+#define FIC_DIST10_LAST_REG 0x189c // FIC_DIST_SPI_TARGET_35_0
+#define FIC_DIST11_FIRST_REG 0x1c00 // FIC_DIST_INT_CONFIG_0_0
+#define FIC_DIST11_LAST_REG 0x1c24 // FIC_DIST_INT_CONFIG_9_0
+#define FIC_DIST12_FIRST_REG 0x1d00 // FIC_DIST_PPI_STATUS_0
+#define FIC_DIST12_LAST_REG 0x1d10 // FIC_DIST_SPI_STATUS_4_0
+#define FIC_DIST13_FIRST_REG 0x1f00 // FIC_DIST_STI_TRIGGER_0
+#define FIC_DIST13_LAST_REG 0x1f00 // FIC_DIST_STI_TRIGGER_0
+#define FIC_DIST14_FIRST_REG 0x1fd0 // FIC_DIST_PERIPH_ID_0_0
+#define FIC_DIST14_LAST_REG 0x1fe0 // FIC_DIST_PERIPH_ID_4_0
+#define FIC_DIST15_FIRST_REG 0x1ff0 // FIC_DIST_PRIME_CELL_ID_0_0
+#define FIC_DIST15_LAST_REG 0x1ffc // FIC_DIST_PRIME_CELL_ID_3_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARFIC_DIST_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arfic_proc_if.h b/arch/arm/mach-tegra/nv/include/ap20/arfic_proc_if.h
new file mode 100644
index 000000000000..e1367952c33d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arfic_proc_if.h
@@ -0,0 +1,442 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARFIC_PROC_IF_H_INC_
+#define ___ARFIC_PROC_IF_H_INC_
+
+// Register FIC_PROC_IF_CONTROL_0  
+#define FIC_PROC_IF_CONTROL_0                   _MK_ADDR_CONST(0x100)
+#define FIC_PROC_IF_CONTROL_0_SECURE                    0x0
+#define FIC_PROC_IF_CONTROL_0_WORD_COUNT                        0x1
+#define FIC_PROC_IF_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x1f)
+#define FIC_PROC_IF_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x1f)
+#define FIC_PROC_IF_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x1f)
+// Secure enable for the Cortex-A9 processor interface
+#define FIC_PROC_IF_CONTROL_0_ENABLE_S_SHIFT                    _MK_SHIFT_CONST(0)
+#define FIC_PROC_IF_CONTROL_0_ENABLE_S_FIELD                    (_MK_MASK_CONST(0x1) << FIC_PROC_IF_CONTROL_0_ENABLE_S_SHIFT)
+#define FIC_PROC_IF_CONTROL_0_ENABLE_S_RANGE                    0:0
+#define FIC_PROC_IF_CONTROL_0_ENABLE_S_WOFFSET                  0x0
+#define FIC_PROC_IF_CONTROL_0_ENABLE_S_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_ENABLE_S_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FIC_PROC_IF_CONTROL_0_ENABLE_S_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_ENABLE_S_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Non-secure enable for the Cortex-A9 processor interface
+#define FIC_PROC_IF_CONTROL_0_ENABLE_NS_SHIFT                   _MK_SHIFT_CONST(1)
+#define FIC_PROC_IF_CONTROL_0_ENABLE_NS_FIELD                   (_MK_MASK_CONST(0x1) << FIC_PROC_IF_CONTROL_0_ENABLE_NS_SHIFT)
+#define FIC_PROC_IF_CONTROL_0_ENABLE_NS_RANGE                   1:1
+#define FIC_PROC_IF_CONTROL_0_ENABLE_NS_WOFFSET                 0x0
+#define FIC_PROC_IF_CONTROL_0_ENABLE_NS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_ENABLE_NS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FIC_PROC_IF_CONTROL_0_ENABLE_NS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_ENABLE_NS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// When a Cortex-A9 processor performs a secure read of
+// the int_ack Register and the highest
+// priority interrupt is non-secure, this bit controls
+// the acknowledge response as follows:
+// 0 = The Cortex-A9 processor interface returns an INTID
+// value of 1022 and the interrupt remains Pending.
+// 1 = The Cortex-A9 processor interface returns the INTID
+// value of the non-secure interrupt and
+// acknowledges the interrupt. The interrupt changes state
+// to Active, or Active-and-pending.
+// When a Cortex-A9 processor performs a secure write to
+// the EOI Register to signal the completion
+// of a non-secure interrupt, this bit controls if the
+// Interrupt Controller clears the interrupt as follows:
+// 0 = the Interrupt Controller ignores the write and the
+// interrupt remains Active, or
+// Active-and-pending
+// 1 = the Interrupt Controller changes the interrupt
+// status to Inactive, or Pending.
+#define FIC_PROC_IF_CONTROL_0_ACK_CTL_SHIFT                     _MK_SHIFT_CONST(2)
+#define FIC_PROC_IF_CONTROL_0_ACK_CTL_FIELD                     (_MK_MASK_CONST(0x1) << FIC_PROC_IF_CONTROL_0_ACK_CTL_SHIFT)
+#define FIC_PROC_IF_CONTROL_0_ACK_CTL_RANGE                     2:2
+#define FIC_PROC_IF_CONTROL_0_ACK_CTL_WOFFSET                   0x0
+#define FIC_PROC_IF_CONTROL_0_ACK_CTL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_ACK_CTL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FIC_PROC_IF_CONTROL_0_ACK_CTL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_ACK_CTL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Enables the Cortex-A9 processor interface to send
+// secure interrupts using the nFIQ signal.
+#define FIC_PROC_IF_CONTROL_0_FIQ_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define FIC_PROC_IF_CONTROL_0_FIQ_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << FIC_PROC_IF_CONTROL_0_FIQ_ENABLE_SHIFT)
+#define FIC_PROC_IF_CONTROL_0_FIQ_ENABLE_RANGE                  3:3
+#define FIC_PROC_IF_CONTROL_0_FIQ_ENABLE_WOFFSET                        0x0
+#define FIC_PROC_IF_CONTROL_0_FIQ_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_FIQ_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FIC_PROC_IF_CONTROL_0_FIQ_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_FIQ_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Controls which Binary Pointer Register the Cortex-A9
+// processor interface uses when it performs
+// a pre-emptive calculation. The options are:
+// 0 = secure interrupts use the bin_pt_s Register and
+// non-secure interrupts use the bin_pt_ns Register
+// 1 = secure read and writes access the secure binary
+// point register directly. Non-secure writes are
+// ignored, and non-secure reads return the value in the
+// secure binary point register plus 1, with the
+// addition saturating at a value of 7.
+#define FIC_PROC_IF_CONTROL_0_SBPR_SHIFT                        _MK_SHIFT_CONST(4)
+#define FIC_PROC_IF_CONTROL_0_SBPR_FIELD                        (_MK_MASK_CONST(0x1) << FIC_PROC_IF_CONTROL_0_SBPR_SHIFT)
+#define FIC_PROC_IF_CONTROL_0_SBPR_RANGE                        4:4
+#define FIC_PROC_IF_CONTROL_0_SBPR_WOFFSET                      0x0
+#define FIC_PROC_IF_CONTROL_0_SBPR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_SBPR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FIC_PROC_IF_CONTROL_0_SBPR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CONTROL_0_SBPR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_PROC_IF_PRIORITY_MASK_0  
+#define FIC_PROC_IF_PRIORITY_MASK_0                     _MK_ADDR_CONST(0x104)
+#define FIC_PROC_IF_PRIORITY_MASK_0_SECURE                      0x0
+#define FIC_PROC_IF_PRIORITY_MASK_0_WORD_COUNT                  0x1
+#define FIC_PROC_IF_PRIORITY_MASK_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_PRIORITY_MASK_0_RESET_MASK                  _MK_MASK_CONST(0xf8)
+#define FIC_PROC_IF_PRIORITY_MASK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_PRIORITY_MASK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_PRIORITY_MASK_0_READ_MASK                   _MK_MASK_CONST(0xf8)
+#define FIC_PROC_IF_PRIORITY_MASK_0_WRITE_MASK                  _MK_MASK_CONST(0xf8)
+// Configures the priorty mask level for the Cortex-A9 processor.
+#define FIC_PROC_IF_PRIORITY_MASK_0_PRIORITY_SHIFT                      _MK_SHIFT_CONST(3)
+#define FIC_PROC_IF_PRIORITY_MASK_0_PRIORITY_FIELD                      (_MK_MASK_CONST(0x1f) << FIC_PROC_IF_PRIORITY_MASK_0_PRIORITY_SHIFT)
+#define FIC_PROC_IF_PRIORITY_MASK_0_PRIORITY_RANGE                      7:3
+#define FIC_PROC_IF_PRIORITY_MASK_0_PRIORITY_WOFFSET                    0x0
+#define FIC_PROC_IF_PRIORITY_MASK_0_PRIORITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_PRIORITY_MASK_0_PRIORITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define FIC_PROC_IF_PRIORITY_MASK_0_PRIORITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_PRIORITY_MASK_0_PRIORITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FIC_PROC_IF_BIN_PT_0  
+#define FIC_PROC_IF_BIN_PT_0                    _MK_ADDR_CONST(0x108)
+#define FIC_PROC_IF_BIN_PT_0_SECURE                     0x0
+#define FIC_PROC_IF_BIN_PT_0_WORD_COUNT                         0x1
+#define FIC_PROC_IF_BIN_PT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_BIN_PT_0_RESET_MASK                         _MK_MASK_CONST(0x7)
+#define FIC_PROC_IF_BIN_PT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_BIN_PT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_BIN_PT_0_READ_MASK                  _MK_MASK_CONST(0x7)
+#define FIC_PROC_IF_BIN_PT_0_WRITE_MASK                         _MK_MASK_CONST(0x7)
+// Configures the value of the binary point mask.
+#define FIC_PROC_IF_BIN_PT_0_BINARY_POINT_SHIFT                 _MK_SHIFT_CONST(0)
+#define FIC_PROC_IF_BIN_PT_0_BINARY_POINT_FIELD                 (_MK_MASK_CONST(0x7) << FIC_PROC_IF_BIN_PT_0_BINARY_POINT_SHIFT)
+#define FIC_PROC_IF_BIN_PT_0_BINARY_POINT_RANGE                 2:0
+#define FIC_PROC_IF_BIN_PT_0_BINARY_POINT_WOFFSET                       0x0
+#define FIC_PROC_IF_BIN_PT_0_BINARY_POINT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_BIN_PT_0_BINARY_POINT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define FIC_PROC_IF_BIN_PT_0_BINARY_POINT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_BIN_PT_0_BINARY_POINT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FIC_PROC_IF_INT_ACK_0  
+#define FIC_PROC_IF_INT_ACK_0                   _MK_ADDR_CONST(0x10c)
+#define FIC_PROC_IF_INT_ACK_0_SECURE                    0x0
+#define FIC_PROC_IF_INT_ACK_0_WORD_COUNT                        0x1
+#define FIC_PROC_IF_INT_ACK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_INT_ACK_0_RESET_MASK                        _MK_MASK_CONST(0x1fff)
+#define FIC_PROC_IF_INT_ACK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_INT_ACK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_INT_ACK_0_READ_MASK                         _MK_MASK_CONST(0x1fff)
+#define FIC_PROC_IF_INT_ACK_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Returns the INTID of the interrupt that requries
+// servicing by the Cortex-A9 processor    :
+// 15-0 = STI[15:0]
+// 31-16 = PPI[15:0]
+// 255-32 = SPI[223:0]
+// 1020 = reserved
+// 1021 = reserved
+// 1022 = the highest priority interrutp that requires
+//        servicing is non-secure
+// 1023 = no outstanding interrupts
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_SHIFT                   _MK_SHIFT_CONST(0)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_FIELD                   (_MK_MASK_CONST(0x3ff) << FIC_PROC_IF_INT_ACK_0_ACK_INTID_SHIFT)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_RANGE                   9:0
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_WOFFSET                 0x0
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_DEFAULT_MASK                    _MK_MASK_CONST(0x3ff)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_STI_LOW                 _MK_ENUM_CONST(0)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_STI_HIGH                        _MK_ENUM_CONST(15)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_PPI_LOW                 _MK_ENUM_CONST(16)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_PPI_HIGH                        _MK_ENUM_CONST(31)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_SPI_LOW                 _MK_ENUM_CONST(32)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_SPI_HIGH                        _MK_ENUM_CONST(160)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_HIGHEST_PRI_NONSECURE                   _MK_ENUM_CONST(1022)
+#define FIC_PROC_IF_INT_ACK_0_ACK_INTID_NO_OUTSTANDING_INTR                     _MK_ENUM_CONST(1023)
+
+// Returns the CPUID of the Cortex-A9 processor that
+// requested the software interrupt
+#define FIC_PROC_IF_INT_ACK_0_ACK_SOURCE_CPUID_SHIFT                    _MK_SHIFT_CONST(10)
+#define FIC_PROC_IF_INT_ACK_0_ACK_SOURCE_CPUID_FIELD                    (_MK_MASK_CONST(0x7) << FIC_PROC_IF_INT_ACK_0_ACK_SOURCE_CPUID_SHIFT)
+#define FIC_PROC_IF_INT_ACK_0_ACK_SOURCE_CPUID_RANGE                    12:10
+#define FIC_PROC_IF_INT_ACK_0_ACK_SOURCE_CPUID_WOFFSET                  0x0
+#define FIC_PROC_IF_INT_ACK_0_ACK_SOURCE_CPUID_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_INT_ACK_0_ACK_SOURCE_CPUID_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define FIC_PROC_IF_INT_ACK_0_ACK_SOURCE_CPUID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_INT_ACK_0_ACK_SOURCE_CPUID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FIC_PROC_IF_EOI_0  
+#define FIC_PROC_IF_EOI_0                       _MK_ADDR_CONST(0x110)
+#define FIC_PROC_IF_EOI_0_SECURE                        0x0
+#define FIC_PROC_IF_EOI_0_WORD_COUNT                    0x1
+#define FIC_PROC_IF_EOI_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_EOI_0_RESET_MASK                    _MK_MASK_CONST(0x1fff)
+#define FIC_PROC_IF_EOI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_EOI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_EOI_0_READ_MASK                     _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_EOI_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff)
+// After the Cortex-A9 processor completes its interrupt
+// service routine, it sets this field to the
+// INTID of the interrupt that it serviced:
+// 15-0 = STI[15:0]
+// 31-16 = PPI[15:0]
+// 255-32 = SPI[223:0]
+// 1023-1020 = reserved
+#define FIC_PROC_IF_EOI_0_EOI_INTID_SHIFT                       _MK_SHIFT_CONST(0)
+#define FIC_PROC_IF_EOI_0_EOI_INTID_FIELD                       (_MK_MASK_CONST(0x3ff) << FIC_PROC_IF_EOI_0_EOI_INTID_SHIFT)
+#define FIC_PROC_IF_EOI_0_EOI_INTID_RANGE                       9:0
+#define FIC_PROC_IF_EOI_0_EOI_INTID_WOFFSET                     0x0
+#define FIC_PROC_IF_EOI_0_EOI_INTID_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_EOI_0_EOI_INTID_DEFAULT_MASK                        _MK_MASK_CONST(0x3ff)
+#define FIC_PROC_IF_EOI_0_EOI_INTID_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_EOI_0_EOI_INTID_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// After the Cortex-A9 processor completes the interrupt
+// service routine for an STI, it sets this to the source
+// CPUID of the STI that it serviced
+#define FIC_PROC_IF_EOI_0_EOI_SOURCE_CPUID_SHIFT                        _MK_SHIFT_CONST(10)
+#define FIC_PROC_IF_EOI_0_EOI_SOURCE_CPUID_FIELD                        (_MK_MASK_CONST(0x7) << FIC_PROC_IF_EOI_0_EOI_SOURCE_CPUID_SHIFT)
+#define FIC_PROC_IF_EOI_0_EOI_SOURCE_CPUID_RANGE                        12:10
+#define FIC_PROC_IF_EOI_0_EOI_SOURCE_CPUID_WOFFSET                      0x0
+#define FIC_PROC_IF_EOI_0_EOI_SOURCE_CPUID_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_EOI_0_EOI_SOURCE_CPUID_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define FIC_PROC_IF_EOI_0_EOI_SOURCE_CPUID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_EOI_0_EOI_SOURCE_CPUID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FIC_PROC_IF_RUN_PRIORITY_0  
+#define FIC_PROC_IF_RUN_PRIORITY_0                      _MK_ADDR_CONST(0x114)
+#define FIC_PROC_IF_RUN_PRIORITY_0_SECURE                       0x0
+#define FIC_PROC_IF_RUN_PRIORITY_0_WORD_COUNT                   0x1
+#define FIC_PROC_IF_RUN_PRIORITY_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_RUN_PRIORITY_0_RESET_MASK                   _MK_MASK_CONST(0xf0)
+#define FIC_PROC_IF_RUN_PRIORITY_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_RUN_PRIORITY_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_RUN_PRIORITY_0_READ_MASK                    _MK_MASK_CONST(0xf0)
+#define FIC_PROC_IF_RUN_PRIORITY_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Returns the priority level of the highest priority
+// interrupt that is running on the Cortex-A9 processor
+#define FIC_PROC_IF_RUN_PRIORITY_0_RUN_PRIORITY_SHIFT                   _MK_SHIFT_CONST(4)
+#define FIC_PROC_IF_RUN_PRIORITY_0_RUN_PRIORITY_FIELD                   (_MK_MASK_CONST(0xf) << FIC_PROC_IF_RUN_PRIORITY_0_RUN_PRIORITY_SHIFT)
+#define FIC_PROC_IF_RUN_PRIORITY_0_RUN_PRIORITY_RANGE                   7:4
+#define FIC_PROC_IF_RUN_PRIORITY_0_RUN_PRIORITY_WOFFSET                 0x0
+#define FIC_PROC_IF_RUN_PRIORITY_0_RUN_PRIORITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_RUN_PRIORITY_0_RUN_PRIORITY_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define FIC_PROC_IF_RUN_PRIORITY_0_RUN_PRIORITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_RUN_PRIORITY_0_RUN_PRIORITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_PROC_IF_HI_PEND_0  
+#define FIC_PROC_IF_HI_PEND_0                   _MK_ADDR_CONST(0x118)
+#define FIC_PROC_IF_HI_PEND_0_SECURE                    0x0
+#define FIC_PROC_IF_HI_PEND_0_WORD_COUNT                        0x1
+#define FIC_PROC_IF_HI_PEND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_HI_PEND_0_RESET_MASK                        _MK_MASK_CONST(0x1fff)
+#define FIC_PROC_IF_HI_PEND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_HI_PEND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_HI_PEND_0_READ_MASK                         _MK_MASK_CONST(0x1fff)
+#define FIC_PROC_IF_HI_PEND_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Returns the INTID of the highest priority pending interrupt
+// 15-0 = STI[15:0]
+// 31-16 = PPI[15:0]
+// 255-32 = SPI[223:0]
+// 1020 = reserved
+// 1021 = reserved
+// 1022 = the highest priority interrupT that requires
+//        servicing is non-secure
+// 1023 = no outstanding interrupts
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_SHIFT                  _MK_SHIFT_CONST(0)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_FIELD                  (_MK_MASK_CONST(0x3ff) << FIC_PROC_IF_HI_PEND_0_PEND_INTID_SHIFT)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_RANGE                  9:0
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_WOFFSET                        0x0
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_STI_LOW                        _MK_ENUM_CONST(0)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_STI_HIGH                       _MK_ENUM_CONST(15)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_PPI_LOW                        _MK_ENUM_CONST(16)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_PPI_HIGH                       _MK_ENUM_CONST(31)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_SPI_LOW                        _MK_ENUM_CONST(32)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_SPI_HIGH                       _MK_ENUM_CONST(160)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_HIGHEST_PRI_NONSECURE                  _MK_ENUM_CONST(1022)
+#define FIC_PROC_IF_HI_PEND_0_PEND_INTID_NO_OUTSTANDING_INTR                    _MK_ENUM_CONST(1023)
+
+// Returns the CPUID of the Cortex-A9 processor that is
+// requesting the software interrupt
+#define FIC_PROC_IF_HI_PEND_0_PEND_SOURCE_CPUID_SHIFT                   _MK_SHIFT_CONST(10)
+#define FIC_PROC_IF_HI_PEND_0_PEND_SOURCE_CPUID_FIELD                   (_MK_MASK_CONST(0x7) << FIC_PROC_IF_HI_PEND_0_PEND_SOURCE_CPUID_SHIFT)
+#define FIC_PROC_IF_HI_PEND_0_PEND_SOURCE_CPUID_RANGE                   12:10
+#define FIC_PROC_IF_HI_PEND_0_PEND_SOURCE_CPUID_WOFFSET                 0x0
+#define FIC_PROC_IF_HI_PEND_0_PEND_SOURCE_CPUID_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_HI_PEND_0_PEND_SOURCE_CPUID_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define FIC_PROC_IF_HI_PEND_0_PEND_SOURCE_CPUID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_HI_PEND_0_PEND_SOURCE_CPUID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FIC_PROC_IF_ALIAS_BIN_PT_NS_0  
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0                   _MK_ADDR_CONST(0x11c)
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_SECURE                    0x0
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_WORD_COUNT                        0x1
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_RESET_MASK                        _MK_MASK_CONST(0x7)
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_READ_MASK                         _MK_MASK_CONST(0x7)
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
+// Alias of the BIN_PT_NS regiter. Only accessible in secure mode
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_BINARY_POINT_NS_SHIFT                     _MK_SHIFT_CONST(0)
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_BINARY_POINT_NS_FIELD                     (_MK_MASK_CONST(0x7) << FIC_PROC_IF_ALIAS_BIN_PT_NS_0_BINARY_POINT_NS_SHIFT)
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_BINARY_POINT_NS_RANGE                     2:0
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_BINARY_POINT_NS_WOFFSET                   0x0
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_BINARY_POINT_NS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_BINARY_POINT_NS_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_BINARY_POINT_NS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_ALIAS_BIN_PT_NS_0_BINARY_POINT_NS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FIC_PROC_IF_CPU_IF_IDENT_0  
+#define FIC_PROC_IF_CPU_IF_IDENT_0                      _MK_ADDR_CONST(0x120)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_SECURE                       0x0
+#define FIC_PROC_IF_CPU_IF_IDENT_0_WORD_COUNT                   0x1
+#define FIC_PROC_IF_CPU_IF_IDENT_0_RESET_VAL                    _MK_MASK_CONST(0x3901043b)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Returns the JEP106 code of the company that implemented
+// the Cortex-A9 processor interface RTL.
+#define FIC_PROC_IF_CPU_IF_IDENT_0_IMPLEMENTOR_SHIFT                    _MK_SHIFT_CONST(0)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_IMPLEMENTOR_FIELD                    (_MK_MASK_CONST(0xfff) << FIC_PROC_IF_CPU_IF_IDENT_0_IMPLEMENTOR_SHIFT)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_IMPLEMENTOR_RANGE                    11:0
+#define FIC_PROC_IF_CPU_IF_IDENT_0_IMPLEMENTOR_WOFFSET                  0x0
+#define FIC_PROC_IF_CPU_IF_IDENT_0_IMPLEMENTOR_DEFAULT                  _MK_MASK_CONST(0x43b)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_IMPLEMENTOR_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_IMPLEMENTOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_IMPLEMENTOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Returns the revision number of the Interrupt Controller
+#define FIC_PROC_IF_CPU_IF_IDENT_0_REVISION_NUMBER_SHIFT                        _MK_SHIFT_CONST(12)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_REVISION_NUMBER_FIELD                        (_MK_MASK_CONST(0xf) << FIC_PROC_IF_CPU_IF_IDENT_0_REVISION_NUMBER_SHIFT)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_REVISION_NUMBER_RANGE                        15:12
+#define FIC_PROC_IF_CPU_IF_IDENT_0_REVISION_NUMBER_WOFFSET                      0x0
+#define FIC_PROC_IF_CPU_IF_IDENT_0_REVISION_NUMBER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_REVISION_NUMBER_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_REVISION_NUMBER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_REVISION_NUMBER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Identifies the architecture version
+#define FIC_PROC_IF_CPU_IF_IDENT_0_ARCHITECTURE_VERSION_SHIFT                   _MK_SHIFT_CONST(16)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_ARCHITECTURE_VERSION_FIELD                   (_MK_MASK_CONST(0xf) << FIC_PROC_IF_CPU_IF_IDENT_0_ARCHITECTURE_VERSION_SHIFT)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_ARCHITECTURE_VERSION_RANGE                   19:16
+#define FIC_PROC_IF_CPU_IF_IDENT_0_ARCHITECTURE_VERSION_WOFFSET                 0x0
+#define FIC_PROC_IF_CPU_IF_IDENT_0_ARCHITECTURE_VERSION_DEFAULT                 _MK_MASK_CONST(0x1)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_ARCHITECTURE_VERSION_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_ARCHITECTURE_VERSION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_ARCHITECTURE_VERSION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Identifies the peripheral
+#define FIC_PROC_IF_CPU_IF_IDENT_0_PART_NUMBER_SHIFT                    _MK_SHIFT_CONST(20)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_PART_NUMBER_FIELD                    (_MK_MASK_CONST(0xfff) << FIC_PROC_IF_CPU_IF_IDENT_0_PART_NUMBER_SHIFT)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_PART_NUMBER_RANGE                    31:20
+#define FIC_PROC_IF_CPU_IF_IDENT_0_PART_NUMBER_WOFFSET                  0x0
+#define FIC_PROC_IF_CPU_IF_IDENT_0_PART_NUMBER_DEFAULT                  _MK_MASK_CONST(0x390)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_PART_NUMBER_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_PART_NUMBER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FIC_PROC_IF_CPU_IF_IDENT_0_PART_NUMBER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARFIC_PROC_IF_REGS(_op_) \
+_op_(FIC_PROC_IF_CONTROL_0) \
+_op_(FIC_PROC_IF_PRIORITY_MASK_0) \
+_op_(FIC_PROC_IF_BIN_PT_0) \
+_op_(FIC_PROC_IF_INT_ACK_0) \
+_op_(FIC_PROC_IF_EOI_0) \
+_op_(FIC_PROC_IF_RUN_PRIORITY_0) \
+_op_(FIC_PROC_IF_HI_PEND_0) \
+_op_(FIC_PROC_IF_ALIAS_BIN_PT_NS_0) \
+_op_(FIC_PROC_IF_CPU_IF_IDENT_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_FIC_PROC_IF        0x00000100
+
+//
+// ARFIC_PROC_IF REGISTER BANKS
+//
+
+#define FIC_PROC_IF0_FIRST_REG 0x0100 // FIC_PROC_IF_CONTROL_0
+#define FIC_PROC_IF0_LAST_REG 0x0120 // FIC_PROC_IF_CPU_IF_IDENT_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARFIC_PROC_IF_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arflow_ctlr.h b/arch/arm/mach-tegra/nv/include/ap20/arflow_ctlr.h
new file mode 100644
index 000000000000..f44910bfdaba
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arflow_ctlr.h
@@ -0,0 +1,1096 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARFLOW_CTLR_H_INC_
+#define ___ARFLOW_CTLR_H_INC_
+
+// Register FLOW_CTLR_HALT_CPU_EVENTS_0  
+#define FLOW_CTLR_HALT_CPU_EVENTS_0                     _MK_ADDR_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SECURE                      0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_WORD_COUNT                  0x1
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SHIFT                  _MK_SHIFT_CONST(29)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FIELD                  (_MK_MASK_CONST(0x7) << FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_RANGE                  31:29
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_NONE                 _MK_ENUM_CONST(0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_RUN_AND_INT                  _MK_ENUM_CONST(1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_WAITEVENT                    _MK_ENUM_CONST(2)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_WAITEVENT_AND_INT                    _MK_ENUM_CONST(3)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ                       _MK_ENUM_CONST(4)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ_AND_INT                       _MK_ENUM_CONST(5)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ                     _MK_ENUM_CONST(6)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP                 _MK_ENUM_CONST(2)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_AND_INT                 _MK_ENUM_CONST(3)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT                       _MK_ENUM_CONST(4)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT_AND_INT                       _MK_ENUM_CONST(5)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MODE_FLOW_MODE_STOP_OR_INT                  _MK_ENUM_CONST(6)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SHIFT                  _MK_SHIFT_CONST(28)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_RANGE                  28:28
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_JTAG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SHIFT                  _MK_SHIFT_CONST(27)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_RANGE                  27:27
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SCLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SHIFT                  _MK_SHIFT_CONST(26)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_RANGE                  26:26
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X32K_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SHIFT                  _MK_SHIFT_CONST(25)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_RANGE                  25:25
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_uSEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SHIFT                  _MK_SHIFT_CONST(24)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_RANGE                  24:24
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_MSEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SHIFT                   _MK_SHIFT_CONST(23)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_RANGE                   23:23
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SEC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SHIFT                 _MK_SHIFT_CONST(22)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_RANGE                 22:22
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_X_RDY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SHIFT                 _MK_SHIFT_CONST(21)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_RANGE                 21:21
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP31_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SHIFT                 _MK_SHIFT_CONST(20)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_RANGE                 20:20
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_SMP30_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SHIFT                 _MK_SHIFT_CONST(19)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_RANGE                 19:19
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SHIFT                 _MK_SHIFT_CONST(18)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_RANGE                 18:18
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_C_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SHIFT                 _MK_SHIFT_CONST(17)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_RANGE                 17:17
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SHIFT                 _MK_SHIFT_CONST(16)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_RANGE                 16:16
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_XRQ_A_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SHIFT                   _MK_SHIFT_CONST(15)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_RANGE                   15:15
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SHIFT                   _MK_SHIFT_CONST(14)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_RANGE                   14:14
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_OBF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SHIFT                   _MK_SHIFT_CONST(13)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_RANGE                   13:13
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SHIFT                   _MK_SHIFT_CONST(12)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_RANGE                   12:12
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IBF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SHIFT                 _MK_SHIFT_CONST(11)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_RANGE                 11:11
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SHIFT                 _MK_SHIFT_CONST(10)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_RANGE                 10:10
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_IRQ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SHIFT                 _MK_SHIFT_CONST(9)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_RANGE                 9:9
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SHIFT                 _MK_SHIFT_CONST(8)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_RANGE                 8:8
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_FIQ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_FIELD                  (_MK_MASK_CONST(0xff) << FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SHIFT)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_RANGE                  7:0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU_EVENTS_0_ZERO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FLOW_CTLR_HALT_COP_EVENTS_0  
+#define FLOW_CTLR_HALT_COP_EVENTS_0                     _MK_ADDR_CONST(0x4)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SECURE                      0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_WORD_COUNT                  0x1
+#define FLOW_CTLR_HALT_COP_EVENTS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SHIFT                  _MK_SHIFT_CONST(29)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FIELD                  (_MK_MASK_CONST(0x7) << FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_RANGE                  31:29
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_NONE                 _MK_ENUM_CONST(0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_RUN_AND_INT                  _MK_ENUM_CONST(1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_WAITEVENT                    _MK_ENUM_CONST(2)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_WAITEVENT_AND_INT                    _MK_ENUM_CONST(3)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ                       _MK_ENUM_CONST(4)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ_AND_INT                       _MK_ENUM_CONST(5)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ                     _MK_ENUM_CONST(6)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP                 _MK_ENUM_CONST(2)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_AND_INT                 _MK_ENUM_CONST(3)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT                       _MK_ENUM_CONST(4)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT_AND_INT                       _MK_ENUM_CONST(5)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MODE_FLOW_MODE_STOP_OR_INT                  _MK_ENUM_CONST(6)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SHIFT                  _MK_SHIFT_CONST(28)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_RANGE                  28:28
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_JTAG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SHIFT                  _MK_SHIFT_CONST(27)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_RANGE                  27:27
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SCLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SHIFT                  _MK_SHIFT_CONST(26)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_RANGE                  26:26
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X32K_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SHIFT                  _MK_SHIFT_CONST(25)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_RANGE                  25:25
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_uSEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SHIFT                  _MK_SHIFT_CONST(24)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_RANGE                  24:24
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_MSEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SHIFT                   _MK_SHIFT_CONST(23)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_RANGE                   23:23
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SEC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SHIFT                 _MK_SHIFT_CONST(22)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_RANGE                 22:22
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_X_RDY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SHIFT                 _MK_SHIFT_CONST(21)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_RANGE                 21:21
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP31_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SHIFT                 _MK_SHIFT_CONST(20)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_RANGE                 20:20
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_SMP30_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SHIFT                 _MK_SHIFT_CONST(19)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_RANGE                 19:19
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_D_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SHIFT                 _MK_SHIFT_CONST(18)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_RANGE                 18:18
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_C_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SHIFT                 _MK_SHIFT_CONST(17)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_RANGE                 17:17
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SHIFT                 _MK_SHIFT_CONST(16)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_RANGE                 16:16
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_XRQ_A_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SHIFT                   _MK_SHIFT_CONST(15)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_RANGE                   15:15
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SHIFT                   _MK_SHIFT_CONST(14)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_RANGE                   14:14
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_OBF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SHIFT                   _MK_SHIFT_CONST(13)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_RANGE                   13:13
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SHIFT                   _MK_SHIFT_CONST(12)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_RANGE                   12:12
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_WOFFSET                 0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IBF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SHIFT                 _MK_SHIFT_CONST(11)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_RANGE                 11:11
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SHIFT                 _MK_SHIFT_CONST(10)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_RANGE                 10:10
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_IRQ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SHIFT                 _MK_SHIFT_CONST(9)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_RANGE                 9:9
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SHIFT                 _MK_SHIFT_CONST(8)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_RANGE                 8:8
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_FIQ_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_FIELD                  (_MK_MASK_CONST(0xff) << FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SHIFT)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_RANGE                  7:0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_COP_EVENTS_0_ZERO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FLOW_CTLR_CPU_CSR_0  
+#define FLOW_CTLR_CPU_CSR_0                     _MK_ADDR_CONST(0x8)
+#define FLOW_CTLR_CPU_CSR_0_SECURE                      0x0
+#define FLOW_CTLR_CPU_CSR_0_WORD_COUNT                  0x1
+#define FLOW_CTLR_CPU_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_RESET_MASK                  _MK_MASK_CONST(0xffbc033)
+#define FLOW_CTLR_CPU_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_READ_MASK                   _MK_MASK_CONST(0xffbc033)
+#define FLOW_CTLR_CPU_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0xc033)
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_SHIFT                     _MK_SHIFT_CONST(24)
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_FIELD                     (_MK_MASK_CONST(0xf) << FLOW_CTLR_CPU_CSR_0_PWR_STATE_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_RANGE                     27:24
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_WOFFSET                   0x0
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_PWR_STATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SHIFT                    _MK_SHIFT_CONST(23)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_FIELD                    (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_RANGE                    23:23
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_WOFFSET                  0x0
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_EVENT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_HALT_SHIFT                  _MK_SHIFT_CONST(22)
+#define FLOW_CTLR_CPU_CSR_0_HALT_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_HALT_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_HALT_RANGE                  22:22
+#define FLOW_CTLR_CPU_CSR_0_HALT_WOFFSET                        0x0
+#define FLOW_CTLR_CPU_CSR_0_HALT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_HALT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_HALT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_HALT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_SHIFT                       _MK_SHIFT_CONST(21)
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_FIELD                       (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_P2F_ACK_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_RANGE                       21:21
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_WOFFSET                     0x0
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_P2F_ACK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SHIFT                     _MK_SHIFT_CONST(20)
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_FIELD                     (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_RANGE                     20:20
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_WOFFSET                   0x0
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2P_PWRUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_SHIFT                       _MK_SHIFT_CONST(19)
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_FIELD                       (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_F2P_REQ_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_RANGE                       19:19
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_WOFFSET                     0x0
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2P_REQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SHIFT                        _MK_SHIFT_CONST(17)
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_RANGE                        17:17
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_WOFFSET                      0x0
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_F2C_MPCORE_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SHIFT                   _MK_SHIFT_CONST(16)
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_RANGE                   16:16
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_WOFFSET                 0x0
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_PWR_OFF_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SHIFT                     _MK_SHIFT_CONST(15)
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_FIELD                     (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_RANGE                     15:15
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_WOFFSET                   0x0
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_INTR_FLAG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_SHIFT                    _MK_SHIFT_CONST(14)
+#define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_FIELD                    (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_RANGE                    14:14
+#define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_WOFFSET                  0x0
+#define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_EVENT_FLAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_SHIFT                       _MK_SHIFT_CONST(4)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_FIELD                       (_MK_MASK_CONST(0x3) << FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_RANGE                       5:4
+#define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_WOFFSET                     0x0
+#define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_WAIT_WFE_BITMAP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_RANGE                  1:1
+#define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_WOFFSET                        0x0
+#define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_EVENT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU_CSR_0_ENABLE_SHIFT)
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_RANGE                        0:0
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_WOFFSET                      0x0
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU_CSR_0_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FLOW_CTLR_COP_CSR_0  
+#define FLOW_CTLR_COP_CSR_0                     _MK_ADDR_CONST(0xc)
+#define FLOW_CTLR_COP_CSR_0_SECURE                      0x0
+#define FLOW_CTLR_COP_CSR_0_WORD_COUNT                  0x1
+#define FLOW_CTLR_COP_CSR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_RESET_MASK                  _MK_MASK_CONST(0x8000)
+#define FLOW_CTLR_COP_CSR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_READ_MASK                   _MK_MASK_CONST(0x8000)
+#define FLOW_CTLR_COP_CSR_0_WRITE_MASK                  _MK_MASK_CONST(0x8000)
+// TRUE when Interrupt is Active -- Write-1-to-Clear
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_SHIFT                     _MK_SHIFT_CONST(15)
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_FIELD                     (_MK_MASK_CONST(0x1) << FLOW_CTLR_COP_CSR_0_INTR_FLAG_SHIFT)
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_RANGE                     15:15
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_WOFFSET                   0x0
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_COP_CSR_0_INTR_FLAG_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FLOW_CTLR_XRQ_EVENTS_0  
+#define FLOW_CTLR_XRQ_EVENTS_0                  _MK_ADDR_CONST(0x10)
+#define FLOW_CTLR_XRQ_EVENTS_0_SECURE                   0x0
+#define FLOW_CTLR_XRQ_EVENTS_0_WORD_COUNT                       0x1
+#define FLOW_CTLR_XRQ_EVENTS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_XRQ_EVENTS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_XRQ_EVENTS_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// Setting a bit to 1 enables event triggering for  the corresponding bit in GPIO port D. The assertion level is determined by  GPIO_INT.LVL.D. If more than one XRQ.D bit is set, the events are ORed  together. The resultant event is enabled by setting the XRQ.D bit in the  HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SHIFT                      _MK_SHIFT_CONST(24)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_FIELD                      (_MK_MASK_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SHIFT)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_RANGE                      31:24
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_WOFFSET                    0x0
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_D7_XRQ_D0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Setting a bit to 1 enables event triggering for  the corresponding bit in GPIO port C. The assertion level is determined by  GPIO_INT.LVL.C. If more than one XRQ.C bit is set, the events are ORed  together. The resultant event is enabled by setting the XRQ.C bit in the  HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SHIFT                      _MK_SHIFT_CONST(16)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_FIELD                      (_MK_MASK_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SHIFT)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_RANGE                      23:16
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_WOFFSET                    0x0
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_C7_XRQ_C0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Setting a bit to 1 enables event triggering for  the corresponding bit in GPIO port B. The assertion level is determined by  GPIO_INT.LVL.B. If more than one XRQ.B bit is set, the events are ORed  together. The resultant event is enabled by setting the XRQ.B bit in the  HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SHIFT                      _MK_SHIFT_CONST(8)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_FIELD                      (_MK_MASK_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SHIFT)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_RANGE                      15:8
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_WOFFSET                    0x0
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_B7_XRQ_B0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Setting a bit to 1 enables event triggering for  the corresponding bit in GPIO port A. The assertion level is determined by  GPIO_INT.LVL.A. If more than one XRQ.A bit is set, the events are ORed  together. The resultant event is enabled by setting the XRQ.A bit in the  HALT_CPU.EVENTS or HALT_COP.EVENTS registers.
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SHIFT                      _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_FIELD                      (_MK_MASK_CONST(0xff) << FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SHIFT)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_RANGE                      7:0
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_WOFFSET                    0x0
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_XRQ_EVENTS_0_XRQ_A7_XRQ_A0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FLOW_CTLR_HALT_CPU1_EVENTS_0  
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0                    _MK_ADDR_CONST(0x14)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SECURE                     0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_WORD_COUNT                         0x1
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_SHIFT                 _MK_SHIFT_CONST(29)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FIELD                 (_MK_MASK_CONST(0x7) << FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_RANGE                 31:29
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_NONE                        _MK_ENUM_CONST(0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_RUN_AND_INT                 _MK_ENUM_CONST(1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_WAITEVENT                   _MK_ENUM_CONST(2)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_WAITEVENT_AND_INT                   _MK_ENUM_CONST(3)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ                      _MK_ENUM_CONST(4)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_IRQ_AND_INT                      _MK_ENUM_CONST(5)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_EVENT_AND_IRQ                    _MK_ENUM_CONST(6)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP                        _MK_ENUM_CONST(2)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_AND_INT                        _MK_ENUM_CONST(3)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT                      _MK_ENUM_CONST(4)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_UNTIL_INT_AND_INT                      _MK_ENUM_CONST(5)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MODE_FLOW_MODE_STOP_OR_INT                 _MK_ENUM_CONST(6)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_SHIFT                 _MK_SHIFT_CONST(28)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_RANGE                 28:28
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_JTAG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_SHIFT                 _MK_SHIFT_CONST(27)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_RANGE                 27:27
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SCLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_SHIFT                 _MK_SHIFT_CONST(26)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_RANGE                 26:26
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X32K_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_SHIFT                 _MK_SHIFT_CONST(25)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_RANGE                 25:25
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_uSEC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_SHIFT                 _MK_SHIFT_CONST(24)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_RANGE                 24:24
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_MSEC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_SHIFT                  _MK_SHIFT_CONST(23)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_RANGE                  23:23
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SEC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_SHIFT                        _MK_SHIFT_CONST(22)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_RANGE                        22:22
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_WOFFSET                      0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_X_RDY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_SHIFT                        _MK_SHIFT_CONST(21)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_RANGE                        21:21
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_WOFFSET                      0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP31_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_SHIFT                        _MK_SHIFT_CONST(20)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_RANGE                        20:20
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_WOFFSET                      0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_SMP30_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_SHIFT                        _MK_SHIFT_CONST(19)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_RANGE                        19:19
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_WOFFSET                      0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_D_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_SHIFT                        _MK_SHIFT_CONST(18)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_RANGE                        18:18
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_WOFFSET                      0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_SHIFT                        _MK_SHIFT_CONST(17)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_RANGE                        17:17
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_WOFFSET                      0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_B_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_SHIFT                        _MK_SHIFT_CONST(16)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_RANGE                        16:16
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_WOFFSET                      0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_XRQ_A_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_SHIFT                  _MK_SHIFT_CONST(15)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_RANGE                  15:15
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_SHIFT                  _MK_SHIFT_CONST(14)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_RANGE                  14:14
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_OBF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_SHIFT                  _MK_SHIFT_CONST(13)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_RANGE                  13:13
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_SHIFT                  _MK_SHIFT_CONST(12)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_RANGE                  12:12
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_WOFFSET                        0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IBF_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_SHIFT                        _MK_SHIFT_CONST(11)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_RANGE                        11:11
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_WOFFSET                      0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_SHIFT                        _MK_SHIFT_CONST(10)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_RANGE                        10:10
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_WOFFSET                      0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_IRQ_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_SHIFT                        _MK_SHIFT_CONST(9)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_RANGE                        9:9
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_WOFFSET                      0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_SHIFT                        _MK_SHIFT_CONST(8)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_FIELD                        (_MK_MASK_CONST(0x1) << FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_RANGE                        8:8
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_WOFFSET                      0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_FIQ_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_SHIFT                 _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_FIELD                 (_MK_MASK_CONST(0xff) << FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_SHIFT)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_RANGE                 7:0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_WOFFSET                       0x0
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_HALT_CPU1_EVENTS_0_ZERO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FLOW_CTLR_CPU1_CSR_0  
+#define FLOW_CTLR_CPU1_CSR_0                    _MK_ADDR_CONST(0x18)
+#define FLOW_CTLR_CPU1_CSR_0_SECURE                     0x0
+#define FLOW_CTLR_CPU1_CSR_0_WORD_COUNT                         0x1
+#define FLOW_CTLR_CPU1_CSR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_RESET_MASK                         _MK_MASK_CONST(0xffbc033)
+#define FLOW_CTLR_CPU1_CSR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_READ_MASK                  _MK_MASK_CONST(0xffbc033)
+#define FLOW_CTLR_CPU1_CSR_0_WRITE_MASK                         _MK_MASK_CONST(0xc033)
+#define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_SHIFT                    _MK_SHIFT_CONST(24)
+#define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_FIELD                    (_MK_MASK_CONST(0xf) << FLOW_CTLR_CPU1_CSR_0_PWR_STATE_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_RANGE                    27:24
+#define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_WOFFSET                  0x0
+#define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_PWR_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_SHIFT                   _MK_SHIFT_CONST(23)
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_RANGE                   23:23
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_WOFFSET                 0x0
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_EVENT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_HALT_SHIFT                 _MK_SHIFT_CONST(22)
+#define FLOW_CTLR_CPU1_CSR_0_HALT_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_HALT_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_HALT_RANGE                 22:22
+#define FLOW_CTLR_CPU1_CSR_0_HALT_WOFFSET                       0x0
+#define FLOW_CTLR_CPU1_CSR_0_HALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_HALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU1_CSR_0_HALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_HALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_SHIFT                      _MK_SHIFT_CONST(21)
+#define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_FIELD                      (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_P2F_ACK_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_RANGE                      21:21
+#define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_WOFFSET                    0x0
+#define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_P2F_ACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_SHIFT                    _MK_SHIFT_CONST(20)
+#define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_FIELD                    (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_RANGE                    20:20
+#define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_WOFFSET                  0x0
+#define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_F2P_PWRUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_SHIFT                      _MK_SHIFT_CONST(19)
+#define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_FIELD                      (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_F2P_REQ_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_RANGE                      19:19
+#define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_WOFFSET                    0x0
+#define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_F2P_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_SHIFT                       _MK_SHIFT_CONST(17)
+#define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_FIELD                       (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_RANGE                       17:17
+#define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_WOFFSET                     0x0
+#define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_F2C_MPCORE_RST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_SHIFT                  _MK_SHIFT_CONST(16)
+#define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_FIELD                  (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_RANGE                  16:16
+#define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_WOFFSET                        0x0
+#define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_PWR_OFF_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_SHIFT                    _MK_SHIFT_CONST(15)
+#define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_FIELD                    (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_RANGE                    15:15
+#define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_WOFFSET                  0x0
+#define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_INTR_FLAG_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_SHIFT                   _MK_SHIFT_CONST(14)
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_FIELD                   (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_RANGE                   14:14
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_WOFFSET                 0x0
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_FLAG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_SHIFT                      _MK_SHIFT_CONST(4)
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_FIELD                      (_MK_MASK_CONST(0x3) << FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_RANGE                      5:4
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_WOFFSET                    0x0
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_WAIT_WFE_BITMAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_SHIFT                 _MK_SHIFT_CONST(1)
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_RANGE                 1:1
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_WOFFSET                       0x0
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_EVENT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FLOW_CTLR_CPU1_CSR_0_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
+#define FLOW_CTLR_CPU1_CSR_0_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << FLOW_CTLR_CPU1_CSR_0_ENABLE_SHIFT)
+#define FLOW_CTLR_CPU1_CSR_0_ENABLE_RANGE                       0:0
+#define FLOW_CTLR_CPU1_CSR_0_ENABLE_WOFFSET                     0x0
+#define FLOW_CTLR_CPU1_CSR_0_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FLOW_CTLR_CPU1_CSR_0_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FLOW_CTLR_CPU1_CSR_0_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARFLOW_CTLR_REGS(_op_) \
+_op_(FLOW_CTLR_HALT_CPU_EVENTS_0) \
+_op_(FLOW_CTLR_HALT_COP_EVENTS_0) \
+_op_(FLOW_CTLR_CPU_CSR_0) \
+_op_(FLOW_CTLR_COP_CSR_0) \
+_op_(FLOW_CTLR_XRQ_EVENTS_0) \
+_op_(FLOW_CTLR_HALT_CPU1_EVENTS_0) \
+_op_(FLOW_CTLR_CPU1_CSR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_FLOW_CTLR  0x00000000
+
+//
+// ARFLOW_CTLR REGISTER BANKS
+//
+
+#define FLOW_CTLR0_FIRST_REG 0x0000 // FLOW_CTLR_HALT_CPU_EVENTS_0
+#define FLOW_CTLR0_LAST_REG 0x0018 // FLOW_CTLR_CPU1_CSR_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARFLOW_CTLR_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arfuse.h b/arch/arm/mach-tegra/nv/include/ap20/arfuse.h
new file mode 100644
index 000000000000..51f4a4a0f080
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arfuse.h
@@ -0,0 +1,2899 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARFUSE_H_INC_
+#define ___ARFUSE_H_INC_
+
+// Register FUSE_FUSECTRL_0  
+#define FUSE_FUSECTRL_0                 _MK_ADDR_CONST(0x0)
+#define FUSE_FUSECTRL_0_SECURE                  0x0
+#define FUSE_FUSECTRL_0_WORD_COUNT                      0x1
+#define FUSE_FUSECTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_RESET_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_READ_MASK                       _MK_MASK_CONST(0xc00f0000)
+#define FUSE_FUSECTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_FIELD                      (_MK_MASK_CONST(0x3) << FUSE_FUSECTRL_0_FUSECTRL_CMD_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_RANGE                      1:0
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_WOFFSET                    0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_INIT_ENUM                  IDLE
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_IDLE                       _MK_ENUM_CONST(0)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_READ                       _MK_ENUM_CONST(1)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_WRITE                      _MK_ENUM_CONST(2)
+#define FUSE_FUSECTRL_0_FUSECTRL_CMD_SENSE_CTRL                 _MK_ENUM_CONST(3)
+
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SHIFT                    _MK_SHIFT_CONST(16)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_FUSECTRL_0_FUSECTRL_STATE_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_RANGE                    19:16
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_WOFFSET                  0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_RESET                      _MK_ENUM_CONST(0)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_POST_RESET                 _MK_ENUM_CONST(1)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_LOAD_ROW0                  _MK_ENUM_CONST(2)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_LOAD_ROW1                  _MK_ENUM_CONST(3)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_IDLE                       _MK_ENUM_CONST(4)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_READ_SETUP                 _MK_ENUM_CONST(5)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_READ_STROBE                        _MK_ENUM_CONST(6)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_SAMPLE_FUSES                       _MK_ENUM_CONST(7)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_READ_HOLD                  _MK_ENUM_CONST(8)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_SETUP                        _MK_ENUM_CONST(9)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_ADDR_SETUP                   _MK_ENUM_CONST(10)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_PROGRAM                      _MK_ENUM_CONST(11)
+#define FUSE_FUSECTRL_0_FUSECTRL_STATE_STATE_WRITE_ADDR_HOLD                    _MK_ENUM_CONST(12)
+
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SHIFT                  _MK_SHIFT_CONST(30)
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_RANGE                  30:30
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_WOFFSET                        0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_FUSE_SENSE_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_SHIFT                     _MK_SHIFT_CONST(31)
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_SHIFT)
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_RANGE                     31:31
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_WOFFSET                   0x0
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSECTRL_0_FUSECTRL_RAMREPAIR_SHIFT_DONE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEADDR_0  
+#define FUSE_FUSEADDR_0                 _MK_ADDR_CONST(0x4)
+#define FUSE_FUSEADDR_0_SECURE                  0x0
+#define FUSE_FUSEADDR_0_WORD_COUNT                      0x1
+#define FUSE_FUSEADDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEADDR_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSEADDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSEADDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEADDR_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_FUSEADDR_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_FIELD                   (_MK_MASK_CONST(0xff) << FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SHIFT)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_RANGE                   7:0
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_WOFFSET                 0x0
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEADDR_0_FUSEADDR_VLDFLD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSERDATA_0  
+#define FUSE_FUSERDATA_0                        _MK_ADDR_CONST(0x8)
+#define FUSE_FUSERDATA_0_SECURE                         0x0
+#define FUSE_FUSERDATA_0_WORD_COUNT                     0x1
+#define FUSE_FUSERDATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSERDATA_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << FUSE_FUSERDATA_0_FUSERDATA_DATA_SHIFT)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_RANGE                   31:0
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_WOFFSET                 0x0
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSERDATA_0_FUSERDATA_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEWDATA_0  
+#define FUSE_FUSEWDATA_0                        _MK_ADDR_CONST(0xc)
+#define FUSE_FUSEWDATA_0_SECURE                         0x0
+#define FUSE_FUSEWDATA_0_WORD_COUNT                     0x1
+#define FUSE_FUSEWDATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWDATA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_READ_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_FIELD                   (_MK_MASK_CONST(0xffffffff) << FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SHIFT)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_RANGE                   31:0
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_WOFFSET                 0x0
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSEWDATA_0_FUSEWDATA_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME_RD1_0  
+#define FUSE_FUSETIME_RD1_0                     _MK_ADDR_CONST(0x10)
+#define FUSE_FUSETIME_RD1_0_SECURE                      0x0
+#define FUSE_FUSETIME_RD1_0_WORD_COUNT                  0x1
+#define FUSE_FUSETIME_RD1_0_RESET_VAL                   _MK_MASK_CONST(0x10201)
+#define FUSE_FUSETIME_RD1_0_RESET_MASK                  _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_RD1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD1_0_READ_MASK                   _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_RD1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SHIFT                 _MK_SHIFT_CONST(0)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_FIELD                 (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SHIFT)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_RANGE                 7:0
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_WOFFSET                       0x0
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_DEFAULT                       _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_MAX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SHIFT                     _MK_SHIFT_CONST(8)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_FIELD                     (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SHIFT)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_RANGE                     15:8
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_WOFFSET                   0x0
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_DEFAULT                   _MK_MASK_CONST(0x2)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_TSUR_FUSEOUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SHIFT                  _MK_SHIFT_CONST(16)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_FIELD                  (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SHIFT)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_RANGE                  23:16
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_WOFFSET                        0x0
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_DEFAULT                        _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD1_0_FUSETIME_RD1_THR_MAX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME_RD2_0  
+#define FUSE_FUSETIME_RD2_0                     _MK_ADDR_CONST(0x14)
+#define FUSE_FUSETIME_RD2_0_SECURE                      0x0
+#define FUSE_FUSETIME_RD2_0_WORD_COUNT                  0x1
+#define FUSE_FUSETIME_RD2_0_RESET_VAL                   _MK_MASK_CONST(0x3)
+#define FUSE_FUSETIME_RD2_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_RD2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD2_0_READ_MASK                   _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_RD2_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_FIELD                        (_MK_MASK_CONST(0xffff) << FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SHIFT)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_RANGE                        15:0
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_WOFFSET                      0x0
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_DEFAULT                      _MK_MASK_CONST(0x3)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_RD2_0_FUSETIME_RD2_TWIDTH_RD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME_PGM1_0  
+#define FUSE_FUSETIME_PGM1_0                    _MK_ADDR_CONST(0x18)
+#define FUSE_FUSETIME_PGM1_0_SECURE                     0x0
+#define FUSE_FUSETIME_PGM1_0_WORD_COUNT                         0x1
+#define FUSE_FUSETIME_PGM1_0_RESET_VAL                  _MK_MASK_CONST(0x101a0)
+#define FUSE_FUSETIME_PGM1_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_PGM1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM1_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_PGM1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffff)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SHIFT)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_RANGE                       7:0
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_WOFFSET                     0x0
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_DEFAULT                     _MK_MASK_CONST(0xa0)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_MAX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SHIFT                      _MK_SHIFT_CONST(8)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_FIELD                      (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SHIFT)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_RANGE                      15:8
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_WOFFSET                    0x0
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_DEFAULT                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_TSUP_ADDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SHIFT                       _MK_SHIFT_CONST(16)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_FIELD                       (_MK_MASK_CONST(0xff) << FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SHIFT)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_RANGE                       23:16
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_WOFFSET                     0x0
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_DEFAULT                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM1_0_FUSETIME_PGM1_THP_ADDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSETIME_PGM2_0  
+#define FUSE_FUSETIME_PGM2_0                    _MK_ADDR_CONST(0x1c)
+#define FUSE_FUSETIME_PGM2_0_SECURE                     0x0
+#define FUSE_FUSETIME_PGM2_0_WORD_COUNT                         0x1
+#define FUSE_FUSETIME_PGM2_0_RESET_VAL                  _MK_MASK_CONST(0x104)
+#define FUSE_FUSETIME_PGM2_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_PGM2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM2_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_PGM2_0_WRITE_MASK                         _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_FIELD                     (_MK_MASK_CONST(0xffff) << FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SHIFT)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_RANGE                     15:0
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_WOFFSET                   0x0
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_DEFAULT                   _MK_MASK_CONST(0x104)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSETIME_PGM2_0_FUSETIME_PGM2_TWIDTH_PGM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIV2INTFC_START_0  
+#define FUSE_PRIV2INTFC_START_0                 _MK_ADDR_CONST(0x20)
+#define FUSE_PRIV2INTFC_START_0_SECURE                  0x0
+#define FUSE_PRIV2INTFC_START_0_WORD_COUNT                      0x1
+#define FUSE_PRIV2INTFC_START_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_RESET_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_PRIV2INTFC_START_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_READ_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SHIFT)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_RANGE                     0:0
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_WOFFSET                   0x0
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_START_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_SHIFT                 _MK_SHIFT_CONST(1)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_FIELD                 (_MK_MASK_CONST(0x1) << FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_SHIFT)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_RANGE                 1:1
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_WOFFSET                       0x0
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_PRIV2INTFC_START_0_PRIV2INTFC_SKIP_RAMREPAIR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_FUSEBYPASS_0  
+#define FUSE_FUSEBYPASS_0                       _MK_ADDR_CONST(0x24)
+#define FUSE_FUSEBYPASS_0_SECURE                        0x0
+#define FUSE_FUSEBYPASS_0_WORD_COUNT                    0x1
+#define FUSE_FUSEBYPASS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SHIFT)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_RANGE                  0:0
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_WOFFSET                        0x0
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_INIT_ENUM                      DISABLED
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DISABLED                       _MK_ENUM_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_ENABLED                        _MK_ENUM_CONST(1)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_DISABLE                        _MK_ENUM_CONST(0)
+#define FUSE_FUSEBYPASS_0_FUSEBYPASS_VAL_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register FUSE_PRIVATEKEYDISABLE_0  
+#define FUSE_PRIVATEKEYDISABLE_0                        _MK_ADDR_CONST(0x28)
+#define FUSE_PRIVATEKEYDISABLE_0_SECURE                         0x0
+#define FUSE_PRIVATEKEYDISABLE_0_WORD_COUNT                     0x1
+#define FUSE_PRIVATEKEYDISABLE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SHIFT)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_RANGE                    0:0
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_WOFFSET                  0x0
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_INIT_ENUM                        KEY_VISIBLE
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_KEY_VISIBLE                      _MK_ENUM_CONST(0)
+#define FUSE_PRIVATEKEYDISABLE_0_PRIVATEKEYDISABLE_VAL_KEY_INVISIBLE                    _MK_ENUM_CONST(1)
+
+
+// Register FUSE_DISABLEREGPROGRAM_0  
+#define FUSE_DISABLEREGPROGRAM_0                        _MK_ADDR_CONST(0x2c)
+#define FUSE_DISABLEREGPROGRAM_0_SECURE                         0x0
+#define FUSE_DISABLEREGPROGRAM_0_WORD_COUNT                     0x1
+#define FUSE_DISABLEREGPROGRAM_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_DISABLEREGPROGRAM_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define FUSE_DISABLEREGPROGRAM_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SHIFT)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_RANGE                    0:0
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_WOFFSET                  0x0
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_INIT_ENUM                        DISABLED
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DISABLED                 _MK_ENUM_CONST(0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_ENABLED                  _MK_ENUM_CONST(1)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_DISABLE                  _MK_ENUM_CONST(0)
+#define FUSE_DISABLEREGPROGRAM_0_DISABLEREGPROGRAM_VAL_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register FUSE_WRITE_ACCESS_SW_0  
+#define FUSE_WRITE_ACCESS_SW_0                  _MK_ADDR_CONST(0x30)
+#define FUSE_WRITE_ACCESS_SW_0_SECURE                   0x0
+#define FUSE_WRITE_ACCESS_SW_0_WORD_COUNT                       0x1
+#define FUSE_WRITE_ACCESS_SW_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define FUSE_WRITE_ACCESS_SW_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_WRITE_ACCESS_SW_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_READ_MASK                        _MK_MASK_CONST(0x10001)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_MASK                       _MK_MASK_CONST(0x10001)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SHIFT                       _MK_SHIFT_CONST(0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_FIELD                       (_MK_MASK_CONST(0x1) << FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SHIFT)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_RANGE                       0:0
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_WOFFSET                     0x0
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_DEFAULT                     _MK_MASK_CONST(0x1)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_INIT_ENUM                   READONLY
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_READWRITE                   _MK_ENUM_CONST(0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_CTRL_READONLY                    _MK_ENUM_CONST(1)
+
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SHIFT                     _MK_SHIFT_CONST(16)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SHIFT)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_RANGE                     16:16
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_WOFFSET                   0x0
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_NOWRITE                   _MK_ENUM_CONST(0)
+#define FUSE_WRITE_ACCESS_SW_0_WRITE_ACCESS_SW_STATUS_WRITE                     _MK_ENUM_CONST(1)
+
+
+// Register FUSE_PWR_GOOD_SW_0  
+#define FUSE_PWR_GOOD_SW_0                      _MK_ADDR_CONST(0x34)
+#define FUSE_PWR_GOOD_SW_0_SECURE                       0x0
+#define FUSE_PWR_GOOD_SW_0_WORD_COUNT                   0x1
+#define FUSE_PWR_GOOD_SW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PWR_GOOD_SW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_PWR_GOOD_SW_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_SHIFT)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_RANGE                        0:0
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_WOFFSET                      0x0
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_INIT_ENUM                    PWR_GOOD_NOT_OK
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_PWR_GOOD_NOT_OK                      _MK_ENUM_CONST(0)
+#define FUSE_PWR_GOOD_SW_0_PWR_GOOD_SW_VAL_PWR_GOOD_OK                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Register FUSE_REG_REF_CTRL_0  
+#define FUSE_REG_REF_CTRL_0                     _MK_ADDR_CONST(0x48)
+#define FUSE_REG_REF_CTRL_0_SECURE                      0x0
+#define FUSE_REG_REF_CTRL_0_WORD_COUNT                  0x1
+#define FUSE_REG_REF_CTRL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_REG_REF_CTRL_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_REG_REF_CTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_REG_REF_CTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_REG_REF_CTRL_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_REG_REF_CTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_FIELD                     (_MK_MASK_CONST(0x3) << FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_SHIFT)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_RANGE                     1:0
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_WOFFSET                   0x0
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_REG_REF_CTRL_0_REG_REF_CTRL_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_REG_BIAS_CTRL_0  
+#define FUSE_REG_BIAS_CTRL_0                    _MK_ADDR_CONST(0x4c)
+#define FUSE_REG_BIAS_CTRL_0_SECURE                     0x0
+#define FUSE_REG_BIAS_CTRL_0_WORD_COUNT                         0x1
+#define FUSE_REG_BIAS_CTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_REG_BIAS_CTRL_0_RESET_MASK                         _MK_MASK_CONST(0x3)
+#define FUSE_REG_BIAS_CTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_REG_BIAS_CTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_REG_BIAS_CTRL_0_READ_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_REG_BIAS_CTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_SHIFT                   _MK_SHIFT_CONST(0)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_FIELD                   (_MK_MASK_CONST(0x3) << FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_SHIFT)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_RANGE                   1:0
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_WOFFSET                 0x0
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_REG_BIAS_CTRL_0_REG_BIAS_CTRL_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY0_NONZERO_0  
+#define FUSE_PRIVATE_KEY0_NONZERO_0                     _MK_ADDR_CONST(0x50)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY0_NONZERO_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY0_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SHIFT)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_RANGE                     0:0
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_WOFFSET                   0x0
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_NONZERO_0_PRIVATE_KEY0_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY1_NONZERO_0  
+#define FUSE_PRIVATE_KEY1_NONZERO_0                     _MK_ADDR_CONST(0x54)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY1_NONZERO_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY1_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SHIFT)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_RANGE                     0:0
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_WOFFSET                   0x0
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_NONZERO_0_PRIVATE_KEY1_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY2_NONZERO_0  
+#define FUSE_PRIVATE_KEY2_NONZERO_0                     _MK_ADDR_CONST(0x58)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY2_NONZERO_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY2_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SHIFT)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_RANGE                     0:0
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_WOFFSET                   0x0
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_NONZERO_0_PRIVATE_KEY2_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY3_NONZERO_0  
+#define FUSE_PRIVATE_KEY3_NONZERO_0                     _MK_ADDR_CONST(0x5c)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY3_NONZERO_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY3_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SHIFT)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_RANGE                     0:0
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_WOFFSET                   0x0
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_NONZERO_0_PRIVATE_KEY3_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY4_NONZERO_0  
+#define FUSE_PRIVATE_KEY4_NONZERO_0                     _MK_ADDR_CONST(0x60)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY4_NONZERO_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY4_NONZERO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_FIELD                     (_MK_MASK_CONST(0x1) << FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_SHIFT)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_RANGE                     0:0
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_WOFFSET                   0x0
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_NONZERO_0_PRIVATE_KEY4_NONZERO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Reserved address 112 [0x70] 
+
+// Reserved address 116 [0x74] 
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Reserved address 240 [0xf0] 
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register FUSE_PRODUCTION_MODE_0  
+#define FUSE_PRODUCTION_MODE_0                  _MK_ADDR_CONST(0x100)
+#define FUSE_PRODUCTION_MODE_0_SECURE                   0x0
+#define FUSE_PRODUCTION_MODE_0_WORD_COUNT                       0x1
+#define FUSE_PRODUCTION_MODE_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SHIFT)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_RANGE                    0:0
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_WOFFSET                  0x0
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_PRODUCTION_MODE_0_PRODUCTION_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_VALID_0  
+#define FUSE_JTAG_SECUREID_VALID_0                      _MK_ADDR_CONST(0x104)
+#define FUSE_JTAG_SECUREID_VALID_0_SECURE                       0x0
+#define FUSE_JTAG_SECUREID_VALID_0_WORD_COUNT                   0x1
+#define FUSE_JTAG_SECUREID_VALID_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SHIFT)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_RANGE                    0:0
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_VALID_0_JTAG_SECUREID_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_0_0  
+#define FUSE_JTAG_SECUREID_0_0                  _MK_ADDR_CONST(0x108)
+#define FUSE_JTAG_SECUREID_0_0_SECURE                   0x0
+#define FUSE_JTAG_SECUREID_0_0_WORD_COUNT                       0x1
+#define FUSE_JTAG_SECUREID_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SHIFT)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_RANGE                    31:0
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_0_0_JTAG_SECUREID_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_JTAG_SECUREID_1_0  
+#define FUSE_JTAG_SECUREID_1_0                  _MK_ADDR_CONST(0x10c)
+#define FUSE_JTAG_SECUREID_1_0_SECURE                   0x0
+#define FUSE_JTAG_SECUREID_1_0_WORD_COUNT                       0x1
+#define FUSE_JTAG_SECUREID_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_FIELD                    (_MK_MASK_CONST(0xffffffff) << FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SHIFT)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_RANGE                    31:0
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_WOFFSET                  0x0
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_JTAG_SECUREID_1_0_JTAG_SECUREID_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SKU_INFO_0  
+#define FUSE_SKU_INFO_0                 _MK_ADDR_CONST(0x110)
+#define FUSE_SKU_INFO_0_SECURE                  0x0
+#define FUSE_SKU_INFO_0_WORD_COUNT                      0x1
+#define FUSE_SKU_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_SKU_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SKU_INFO_0_SKU_INFO_FIELD                  (_MK_MASK_CONST(0xff) << FUSE_SKU_INFO_0_SKU_INFO_SHIFT)
+#define FUSE_SKU_INFO_0_SKU_INFO_RANGE                  7:0
+#define FUSE_SKU_INFO_0_SKU_INFO_WOFFSET                        0x0
+#define FUSE_SKU_INFO_0_SKU_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SKU_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_SKU_INFO_0_SKU_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SKU_INFO_0_SKU_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PROCESS_CALIB_0  
+#define FUSE_PROCESS_CALIB_0                    _MK_ADDR_CONST(0x114)
+#define FUSE_PROCESS_CALIB_0_SECURE                     0x0
+#define FUSE_PROCESS_CALIB_0_WORD_COUNT                         0x1
+#define FUSE_PROCESS_CALIB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_RESET_MASK                         _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_READ_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_WRITE_MASK                         _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_FIELD                        (_MK_MASK_CONST(0x3) << FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SHIFT)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_RANGE                        1:0
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_WOFFSET                      0x0
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_PROCESS_CALIB_0_PROCESS_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_IO_CALIB_0  
+#define FUSE_IO_CALIB_0                 _MK_ADDR_CONST(0x118)
+#define FUSE_IO_CALIB_0_SECURE                  0x0
+#define FUSE_IO_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_IO_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_IO_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_IO_CALIB_0_IO_CALIB_FIELD                  (_MK_MASK_CONST(0x3ff) << FUSE_IO_CALIB_0_IO_CALIB_SHIFT)
+#define FUSE_IO_CALIB_0_IO_CALIB_RANGE                  9:0
+#define FUSE_IO_CALIB_0_IO_CALIB_WOFFSET                        0x0
+#define FUSE_IO_CALIB_0_IO_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_IO_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3ff)
+#define FUSE_IO_CALIB_0_IO_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_IO_CALIB_0_IO_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_CRT_CALIB_0  
+#define FUSE_DAC_CRT_CALIB_0                    _MK_ADDR_CONST(0x11c)
+#define FUSE_DAC_CRT_CALIB_0_SECURE                     0x0
+#define FUSE_DAC_CRT_CALIB_0_WORD_COUNT                         0x1
+#define FUSE_DAC_CRT_CALIB_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_FIELD                        (_MK_MASK_CONST(0xff) << FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SHIFT)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_RANGE                        7:0
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_WOFFSET                      0x0
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_CRT_CALIB_0_DAC_CRT_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_HDTV_CALIB_0  
+#define FUSE_DAC_HDTV_CALIB_0                   _MK_ADDR_CONST(0x120)
+#define FUSE_DAC_HDTV_CALIB_0_SECURE                    0x0
+#define FUSE_DAC_HDTV_CALIB_0_WORD_COUNT                        0x1
+#define FUSE_DAC_HDTV_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_FIELD                      (_MK_MASK_CONST(0xff) << FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SHIFT)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_RANGE                      7:0
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_WOFFSET                    0x0
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_DAC_HDTV_CALIB_0_DAC_HDTV_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_DAC_SDTV_CALIB_0  
+#define FUSE_DAC_SDTV_CALIB_0                   _MK_ADDR_CONST(0x124)
+#define FUSE_DAC_SDTV_CALIB_0_SECURE                    0x0
+#define FUSE_DAC_SDTV_CALIB_0_WORD_COUNT                        0x1
+#define FUSE_DAC_SDTV_CALIB_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_FIELD                      (_MK_MASK_CONST(0xff) << FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SHIFT)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_RANGE                      7:0
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_WOFFSET                    0x0
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_DAC_SDTV_CALIB_0_DAC_SDTV_CALIB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Reserved address 320 [0x140] 
+
+// Reserved address 324 [0x144] 
+
+// Register FUSE_FA_0  
+#define FUSE_FA_0                       _MK_ADDR_CONST(0x148)
+#define FUSE_FA_0_SECURE                        0x0
+#define FUSE_FA_0_WORD_COUNT                    0x1
+#define FUSE_FA_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_RESET_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_READ_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_WRITE_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_FA_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_FA_0_FA_FIELD                      (_MK_MASK_CONST(0x1) << FUSE_FA_0_FA_SHIFT)
+#define FUSE_FA_0_FA_RANGE                      0:0
+#define FUSE_FA_0_FA_WOFFSET                    0x0
+#define FUSE_FA_0_FA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_FA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_FA_0_FA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_FA_0_FA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_PRODUCTION_0  
+#define FUSE_RESERVED_PRODUCTION_0                      _MK_ADDR_CONST(0x14c)
+#define FUSE_RESERVED_PRODUCTION_0_SECURE                       0x0
+#define FUSE_RESERVED_PRODUCTION_0_WORD_COUNT                   0x1
+#define FUSE_RESERVED_PRODUCTION_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESET_MASK                   _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_READ_MASK                    _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_WRITE_MASK                   _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_FIELD                    (_MK_MASK_CONST(0xf) << FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SHIFT)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_RANGE                    3:0
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_WOFFSET                  0x0
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_PRODUCTION_0_RESERVED_PRODUCTION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE0_CALIB_0  
+#define FUSE_HDMI_LANE0_CALIB_0                 _MK_ADDR_CONST(0x150)
+#define FUSE_HDMI_LANE0_CALIB_0_SECURE                  0x0
+#define FUSE_HDMI_LANE0_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE0_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SHIFT)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE0_CALIB_0_HDMI_LANE0_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE1_CALIB_0  
+#define FUSE_HDMI_LANE1_CALIB_0                 _MK_ADDR_CONST(0x154)
+#define FUSE_HDMI_LANE1_CALIB_0_SECURE                  0x0
+#define FUSE_HDMI_LANE1_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE1_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SHIFT)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE1_CALIB_0_HDMI_LANE1_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE2_CALIB_0  
+#define FUSE_HDMI_LANE2_CALIB_0                 _MK_ADDR_CONST(0x158)
+#define FUSE_HDMI_LANE2_CALIB_0_SECURE                  0x0
+#define FUSE_HDMI_LANE2_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE2_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SHIFT)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE2_CALIB_0_HDMI_LANE2_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_HDMI_LANE3_CALIB_0  
+#define FUSE_HDMI_LANE3_CALIB_0                 _MK_ADDR_CONST(0x15c)
+#define FUSE_HDMI_LANE3_CALIB_0_SECURE                  0x0
+#define FUSE_HDMI_LANE3_CALIB_0_WORD_COUNT                      0x1
+#define FUSE_HDMI_LANE3_CALIB_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_FIELD                  (_MK_MASK_CONST(0x3f) << FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SHIFT)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_RANGE                  5:0
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_WOFFSET                        0x0
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_HDMI_LANE3_CALIB_0_HDMI_LANE3_CALIB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 352 [0x160] 
+
+// Reserved address 356 [0x164] 
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Reserved address 384 [0x180] 
+
+// Reserved address 388 [0x184] 
+
+// Reserved address 392 [0x188] 
+
+// Reserved address 396 [0x18c] 
+
+// Reserved address 400 [0x190] 
+
+// Reserved address 404 [0x194] 
+
+// Reserved address 408 [0x198] 
+
+// Reserved address 412 [0x19c] 
+
+// Register FUSE_SECURITY_MODE_0  
+#define FUSE_SECURITY_MODE_0                    _MK_ADDR_CONST(0x1a0)
+#define FUSE_SECURITY_MODE_0_SECURE                     0x0
+#define FUSE_SECURITY_MODE_0_WORD_COUNT                         0x1
+#define FUSE_SECURITY_MODE_0_RESET_VAL                  _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_SECURITY_MODE_0_SECURITY_MODE_SHIFT)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_RANGE                        0:0
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_WOFFSET                      0x0
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_SECURITY_MODE_0_SECURITY_MODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY0_0  
+#define FUSE_PRIVATE_KEY0_0                     _MK_ADDR_CONST(0x1a4)
+#define FUSE_PRIVATE_KEY0_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY0_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SHIFT)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_RANGE                  31:0
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY0_0_PRIVATE_KEY0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY1_0  
+#define FUSE_PRIVATE_KEY1_0                     _MK_ADDR_CONST(0x1a8)
+#define FUSE_PRIVATE_KEY1_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY1_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SHIFT)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_RANGE                  31:0
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY1_0_PRIVATE_KEY1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY2_0  
+#define FUSE_PRIVATE_KEY2_0                     _MK_ADDR_CONST(0x1ac)
+#define FUSE_PRIVATE_KEY2_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY2_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SHIFT)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_RANGE                  31:0
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY2_0_PRIVATE_KEY2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY3_0  
+#define FUSE_PRIVATE_KEY3_0                     _MK_ADDR_CONST(0x1b0)
+#define FUSE_PRIVATE_KEY3_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY3_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY3_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SHIFT)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_RANGE                  31:0
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY3_0_PRIVATE_KEY3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PRIVATE_KEY4_0  
+#define FUSE_PRIVATE_KEY4_0                     _MK_ADDR_CONST(0x1b4)
+#define FUSE_PRIVATE_KEY4_0_SECURE                      0x0
+#define FUSE_PRIVATE_KEY4_0_WORD_COUNT                  0x1
+#define FUSE_PRIVATE_KEY4_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_FIELD                  (_MK_MASK_CONST(0xffffffff) << FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SHIFT)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_RANGE                  31:0
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_WOFFSET                        0x0
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PRIVATE_KEY4_0_PRIVATE_KEY4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_ARM_DEBUG_DIS_0  
+#define FUSE_ARM_DEBUG_DIS_0                    _MK_ADDR_CONST(0x1b8)
+#define FUSE_ARM_DEBUG_DIS_0_SECURE                     0x0
+#define FUSE_ARM_DEBUG_DIS_0_WORD_COUNT                         0x1
+#define FUSE_ARM_DEBUG_DIS_0_RESET_VAL                  _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_DIS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_DIS_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_WRITE_MASK                         _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_FIELD                        (_MK_MASK_CONST(0x1) << FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_SHIFT)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_RANGE                        0:0
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_WOFFSET                      0x0
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_DEFAULT                      _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_DIS_0_ARM_DEBUG_DIS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_BOOT_DEVICE_INFO_0  
+#define FUSE_BOOT_DEVICE_INFO_0                 _MK_ADDR_CONST(0x1bc)
+#define FUSE_BOOT_DEVICE_INFO_0_SECURE                  0x0
+#define FUSE_BOOT_DEVICE_INFO_0_WORD_COUNT                      0x1
+#define FUSE_BOOT_DEVICE_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define FUSE_BOOT_DEVICE_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define FUSE_BOOT_DEVICE_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_FIELD                  (_MK_MASK_CONST(0xffff) << FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SHIFT)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_RANGE                  15:0
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_WOFFSET                        0x0
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_BOOT_DEVICE_INFO_0_BOOT_DEVICE_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_SW_0  
+#define FUSE_RESERVED_SW_0                      _MK_ADDR_CONST(0x1c0)
+#define FUSE_RESERVED_SW_0_SECURE                       0x0
+#define FUSE_RESERVED_SW_0_WORD_COUNT                   0x1
+#define FUSE_RESERVED_SW_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_FIELD                    (_MK_MASK_CONST(0xff) << FUSE_RESERVED_SW_0_RESERVED_SW_SHIFT)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_RANGE                    7:0
+#define FUSE_RESERVED_SW_0_RESERVED_SW_WOFFSET                  0x0
+#define FUSE_RESERVED_SW_0_RESERVED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_SW_0_RESERVED_SW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_ARM_DEBUG_CONTROL_0  
+#define FUSE_ARM_DEBUG_CONTROL_0                        _MK_ADDR_CONST(0x1c4)
+#define FUSE_ARM_DEBUG_CONTROL_0_SECURE                         0x0
+#define FUSE_ARM_DEBUG_CONTROL_0_WORD_COUNT                     0x1
+#define FUSE_ARM_DEBUG_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_ARM_DEBUG_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define FUSE_ARM_DEBUG_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_FIELD                        (_MK_MASK_CONST(0xf) << FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_SHIFT)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_RANGE                        3:0
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_WOFFSET                      0x0
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_ARM_DEBUG_CONTROL_0_ARM_DEBUG_CONTROL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM0_0  
+#define FUSE_RESERVED_ODM0_0                    _MK_ADDR_CONST(0x1c8)
+#define FUSE_RESERVED_ODM0_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM0_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM0_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM0_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SHIFT)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_RANGE                        31:0
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM0_0_RESERVED_ODM0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM1_0  
+#define FUSE_RESERVED_ODM1_0                    _MK_ADDR_CONST(0x1cc)
+#define FUSE_RESERVED_ODM1_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM1_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM1_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM1_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SHIFT)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_RANGE                        31:0
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM1_0_RESERVED_ODM1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM2_0  
+#define FUSE_RESERVED_ODM2_0                    _MK_ADDR_CONST(0x1d0)
+#define FUSE_RESERVED_ODM2_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM2_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM2_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM2_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM2_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SHIFT)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_RANGE                        31:0
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM2_0_RESERVED_ODM2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM3_0  
+#define FUSE_RESERVED_ODM3_0                    _MK_ADDR_CONST(0x1d4)
+#define FUSE_RESERVED_ODM3_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM3_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM3_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM3_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM3_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SHIFT)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_RANGE                        31:0
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM3_0_RESERVED_ODM3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM4_0  
+#define FUSE_RESERVED_ODM4_0                    _MK_ADDR_CONST(0x1d8)
+#define FUSE_RESERVED_ODM4_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM4_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM4_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM4_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM4_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SHIFT)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_RANGE                        31:0
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM4_0_RESERVED_ODM4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM5_0  
+#define FUSE_RESERVED_ODM5_0                    _MK_ADDR_CONST(0x1dc)
+#define FUSE_RESERVED_ODM5_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM5_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM5_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM5_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM5_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SHIFT)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_RANGE                        31:0
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM5_0_RESERVED_ODM5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM6_0  
+#define FUSE_RESERVED_ODM6_0                    _MK_ADDR_CONST(0x1e0)
+#define FUSE_RESERVED_ODM6_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM6_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM6_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM6_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM6_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SHIFT)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_RANGE                        31:0
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM6_0_RESERVED_ODM6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_RESERVED_ODM7_0  
+#define FUSE_RESERVED_ODM7_0                    _MK_ADDR_CONST(0x1e4)
+#define FUSE_RESERVED_ODM7_0_SECURE                     0x0
+#define FUSE_RESERVED_ODM7_0_WORD_COUNT                         0x1
+#define FUSE_RESERVED_ODM7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM7_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM7_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM7_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_FIELD                        (_MK_MASK_CONST(0xffffffff) << FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SHIFT)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_RANGE                        31:0
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_WOFFSET                      0x0
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_RESERVED_ODM7_0_RESERVED_ODM7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_OBS_DIS_0  
+#define FUSE_OBS_DIS_0                  _MK_ADDR_CONST(0x1e8)
+#define FUSE_OBS_DIS_0_SECURE                   0x0
+#define FUSE_OBS_DIS_0_WORD_COUNT                       0x1
+#define FUSE_OBS_DIS_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_OBS_DIS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_OBS_DIS_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_OBS_DIS_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_OBS_DIS_0_OBS_DIS_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_OBS_DIS_0_OBS_DIS_SHIFT)
+#define FUSE_OBS_DIS_0_OBS_DIS_RANGE                    0:0
+#define FUSE_OBS_DIS_0_OBS_DIS_WOFFSET                  0x0
+#define FUSE_OBS_DIS_0_OBS_DIS_DEFAULT                  _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_OBS_DIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_OBS_DIS_0_OBS_DIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_OBS_DIS_0_OBS_DIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_NOR_INFO_0  
+#define FUSE_NOR_INFO_0                 _MK_ADDR_CONST(0x1ec)
+#define FUSE_NOR_INFO_0_SECURE                  0x0
+#define FUSE_NOR_INFO_0_WORD_COUNT                      0x1
+#define FUSE_NOR_INFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_NOR_INFO_0_RESET_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_NOR_INFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define FUSE_NOR_INFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define FUSE_NOR_INFO_0_READ_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_NOR_INFO_0_WRITE_MASK                      _MK_MASK_CONST(0x3)
+#define FUSE_NOR_INFO_0_NOR_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_NOR_INFO_0_NOR_INFO_FIELD                  (_MK_MASK_CONST(0x3) << FUSE_NOR_INFO_0_NOR_INFO_SHIFT)
+#define FUSE_NOR_INFO_0_NOR_INFO_RANGE                  1:0
+#define FUSE_NOR_INFO_0_NOR_INFO_WOFFSET                        0x0
+#define FUSE_NOR_INFO_0_NOR_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_NOR_INFO_0_NOR_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_NOR_INFO_0_NOR_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_NOR_INFO_0_NOR_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_USB_CALIB_0  
+#define FUSE_USB_CALIB_0                        _MK_ADDR_CONST(0x1f0)
+#define FUSE_USB_CALIB_0_SECURE                         0x0
+#define FUSE_USB_CALIB_0_WORD_COUNT                     0x1
+#define FUSE_USB_CALIB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_USB_CALIB_0_RESET_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_USB_CALIB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define FUSE_USB_CALIB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define FUSE_USB_CALIB_0_READ_MASK                      _MK_MASK_CONST(0x7f)
+#define FUSE_USB_CALIB_0_WRITE_MASK                     _MK_MASK_CONST(0x7f)
+#define FUSE_USB_CALIB_0_USB_CALIB_SHIFT                        _MK_SHIFT_CONST(0)
+#define FUSE_USB_CALIB_0_USB_CALIB_FIELD                        (_MK_MASK_CONST(0x7f) << FUSE_USB_CALIB_0_USB_CALIB_SHIFT)
+#define FUSE_USB_CALIB_0_USB_CALIB_RANGE                        6:0
+#define FUSE_USB_CALIB_0_USB_CALIB_WOFFSET                      0x0
+#define FUSE_USB_CALIB_0_USB_CALIB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define FUSE_USB_CALIB_0_USB_CALIB_DEFAULT_MASK                 _MK_MASK_CONST(0x7f)
+#define FUSE_USB_CALIB_0_USB_CALIB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define FUSE_USB_CALIB_0_USB_CALIB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 500 [0x1f4] 
+
+// Register FUSE_KFUSE_PRIVKEY_CTRL_0  
+#define FUSE_KFUSE_PRIVKEY_CTRL_0                       _MK_ADDR_CONST(0x1f8)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_SECURE                        0x0
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_WORD_COUNT                    0x1
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SHIFT                      _MK_SHIFT_CONST(0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_FIELD                      (_MK_MASK_CONST(0x3) << FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SHIFT)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_RANGE                      1:0
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_WOFFSET                    0x0
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define FUSE_KFUSE_PRIVKEY_CTRL_0_KFUSE_PRIVKEY_CTRL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_PACKAGE_INFO_0  
+#define FUSE_PACKAGE_INFO_0                     _MK_ADDR_CONST(0x1fc)
+#define FUSE_PACKAGE_INFO_0_SECURE                      0x0
+#define FUSE_PACKAGE_INFO_0_WORD_COUNT                  0x1
+#define FUSE_PACKAGE_INFO_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_PACKAGE_INFO_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_PACKAGE_INFO_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_PACKAGE_INFO_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_PACKAGE_INFO_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_PACKAGE_INFO_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_FIELD                  (_MK_MASK_CONST(0x3) << FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SHIFT)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_RANGE                  1:0
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_WOFFSET                        0x0
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_PACKAGE_INFO_0_PACKAGE_INFO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_0_0  
+#define FUSE_SPARE_BIT_0_0                      _MK_ADDR_CONST(0x200)
+#define FUSE_SPARE_BIT_0_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_0_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SHIFT)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_RANGE                    0:0
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_0_0_SPARE_BIT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_1_0  
+#define FUSE_SPARE_BIT_1_0                      _MK_ADDR_CONST(0x204)
+#define FUSE_SPARE_BIT_1_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_1_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SHIFT)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_RANGE                    0:0
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_1_0_SPARE_BIT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_2_0  
+#define FUSE_SPARE_BIT_2_0                      _MK_ADDR_CONST(0x208)
+#define FUSE_SPARE_BIT_2_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_2_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SHIFT)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_RANGE                    0:0
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_2_0_SPARE_BIT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_3_0  
+#define FUSE_SPARE_BIT_3_0                      _MK_ADDR_CONST(0x20c)
+#define FUSE_SPARE_BIT_3_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_3_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SHIFT)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_RANGE                    0:0
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_3_0_SPARE_BIT_3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_4_0  
+#define FUSE_SPARE_BIT_4_0                      _MK_ADDR_CONST(0x210)
+#define FUSE_SPARE_BIT_4_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_4_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SHIFT)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_RANGE                    0:0
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_4_0_SPARE_BIT_4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_5_0  
+#define FUSE_SPARE_BIT_5_0                      _MK_ADDR_CONST(0x214)
+#define FUSE_SPARE_BIT_5_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_5_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SHIFT)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_RANGE                    0:0
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_5_0_SPARE_BIT_5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_6_0  
+#define FUSE_SPARE_BIT_6_0                      _MK_ADDR_CONST(0x218)
+#define FUSE_SPARE_BIT_6_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_6_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_6_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SHIFT)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_RANGE                    0:0
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_6_0_SPARE_BIT_6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_7_0  
+#define FUSE_SPARE_BIT_7_0                      _MK_ADDR_CONST(0x21c)
+#define FUSE_SPARE_BIT_7_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_7_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_7_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SHIFT)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_RANGE                    0:0
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_7_0_SPARE_BIT_7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_8_0  
+#define FUSE_SPARE_BIT_8_0                      _MK_ADDR_CONST(0x220)
+#define FUSE_SPARE_BIT_8_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_8_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_8_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SHIFT)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_RANGE                    0:0
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_8_0_SPARE_BIT_8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_9_0  
+#define FUSE_SPARE_BIT_9_0                      _MK_ADDR_CONST(0x224)
+#define FUSE_SPARE_BIT_9_0_SECURE                       0x0
+#define FUSE_SPARE_BIT_9_0_WORD_COUNT                   0x1
+#define FUSE_SPARE_BIT_9_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SHIFT                    _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_FIELD                    (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SHIFT)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_RANGE                    0:0
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_WOFFSET                  0x0
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_9_0_SPARE_BIT_9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_10_0  
+#define FUSE_SPARE_BIT_10_0                     _MK_ADDR_CONST(0x228)
+#define FUSE_SPARE_BIT_10_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_10_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_10_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SHIFT)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_RANGE                  0:0
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_10_0_SPARE_BIT_10_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_11_0  
+#define FUSE_SPARE_BIT_11_0                     _MK_ADDR_CONST(0x22c)
+#define FUSE_SPARE_BIT_11_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_11_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_11_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SHIFT)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_RANGE                  0:0
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_11_0_SPARE_BIT_11_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_12_0  
+#define FUSE_SPARE_BIT_12_0                     _MK_ADDR_CONST(0x230)
+#define FUSE_SPARE_BIT_12_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_12_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_12_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SHIFT)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_RANGE                  0:0
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_12_0_SPARE_BIT_12_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_13_0  
+#define FUSE_SPARE_BIT_13_0                     _MK_ADDR_CONST(0x234)
+#define FUSE_SPARE_BIT_13_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_13_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_13_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SHIFT)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_RANGE                  0:0
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_13_0_SPARE_BIT_13_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_14_0  
+#define FUSE_SPARE_BIT_14_0                     _MK_ADDR_CONST(0x238)
+#define FUSE_SPARE_BIT_14_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_14_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_14_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SHIFT)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_RANGE                  0:0
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_14_0_SPARE_BIT_14_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_15_0  
+#define FUSE_SPARE_BIT_15_0                     _MK_ADDR_CONST(0x23c)
+#define FUSE_SPARE_BIT_15_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_15_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_15_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SHIFT)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_RANGE                  0:0
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_15_0_SPARE_BIT_15_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_16_0  
+#define FUSE_SPARE_BIT_16_0                     _MK_ADDR_CONST(0x240)
+#define FUSE_SPARE_BIT_16_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_16_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_16_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_16_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_16_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SHIFT)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_RANGE                  0:0
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_16_0_SPARE_BIT_16_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_17_0  
+#define FUSE_SPARE_BIT_17_0                     _MK_ADDR_CONST(0x244)
+#define FUSE_SPARE_BIT_17_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_17_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_17_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_17_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_17_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SHIFT)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_RANGE                  0:0
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_17_0_SPARE_BIT_17_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_18_0  
+#define FUSE_SPARE_BIT_18_0                     _MK_ADDR_CONST(0x248)
+#define FUSE_SPARE_BIT_18_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_18_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_18_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_18_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_18_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SHIFT)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_RANGE                  0:0
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_18_0_SPARE_BIT_18_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_19_0  
+#define FUSE_SPARE_BIT_19_0                     _MK_ADDR_CONST(0x24c)
+#define FUSE_SPARE_BIT_19_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_19_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_19_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_19_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_19_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SHIFT)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_RANGE                  0:0
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_19_0_SPARE_BIT_19_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_20_0  
+#define FUSE_SPARE_BIT_20_0                     _MK_ADDR_CONST(0x250)
+#define FUSE_SPARE_BIT_20_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_20_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_20_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_20_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_20_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SHIFT)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_RANGE                  0:0
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_20_0_SPARE_BIT_20_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_21_0  
+#define FUSE_SPARE_BIT_21_0                     _MK_ADDR_CONST(0x254)
+#define FUSE_SPARE_BIT_21_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_21_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_21_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_21_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_21_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SHIFT)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_RANGE                  0:0
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_21_0_SPARE_BIT_21_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_22_0  
+#define FUSE_SPARE_BIT_22_0                     _MK_ADDR_CONST(0x258)
+#define FUSE_SPARE_BIT_22_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_22_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_22_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_22_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_22_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SHIFT)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_RANGE                  0:0
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_22_0_SPARE_BIT_22_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_23_0  
+#define FUSE_SPARE_BIT_23_0                     _MK_ADDR_CONST(0x25c)
+#define FUSE_SPARE_BIT_23_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_23_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_23_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_23_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_23_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SHIFT)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_RANGE                  0:0
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_23_0_SPARE_BIT_23_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_24_0  
+#define FUSE_SPARE_BIT_24_0                     _MK_ADDR_CONST(0x260)
+#define FUSE_SPARE_BIT_24_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_24_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_24_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_24_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_24_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SHIFT)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_RANGE                  0:0
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_24_0_SPARE_BIT_24_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_25_0  
+#define FUSE_SPARE_BIT_25_0                     _MK_ADDR_CONST(0x264)
+#define FUSE_SPARE_BIT_25_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_25_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_25_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_25_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_25_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SHIFT)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_RANGE                  0:0
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_25_0_SPARE_BIT_25_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_26_0  
+#define FUSE_SPARE_BIT_26_0                     _MK_ADDR_CONST(0x268)
+#define FUSE_SPARE_BIT_26_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_26_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_26_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_26_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_26_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SHIFT)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_RANGE                  0:0
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_26_0_SPARE_BIT_26_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_27_0  
+#define FUSE_SPARE_BIT_27_0                     _MK_ADDR_CONST(0x26c)
+#define FUSE_SPARE_BIT_27_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_27_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_27_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_27_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_27_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SHIFT)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_RANGE                  0:0
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_27_0_SPARE_BIT_27_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_28_0  
+#define FUSE_SPARE_BIT_28_0                     _MK_ADDR_CONST(0x270)
+#define FUSE_SPARE_BIT_28_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_28_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_28_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_28_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_28_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SHIFT)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_RANGE                  0:0
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_28_0_SPARE_BIT_28_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_29_0  
+#define FUSE_SPARE_BIT_29_0                     _MK_ADDR_CONST(0x274)
+#define FUSE_SPARE_BIT_29_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_29_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_29_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_29_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_29_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SHIFT)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_RANGE                  0:0
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_29_0_SPARE_BIT_29_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_30_0  
+#define FUSE_SPARE_BIT_30_0                     _MK_ADDR_CONST(0x278)
+#define FUSE_SPARE_BIT_30_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_30_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_30_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_30_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_30_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SHIFT)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_RANGE                  0:0
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_30_0_SPARE_BIT_30_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_31_0  
+#define FUSE_SPARE_BIT_31_0                     _MK_ADDR_CONST(0x27c)
+#define FUSE_SPARE_BIT_31_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_31_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_31_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_31_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_31_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SHIFT)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_RANGE                  0:0
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_31_0_SPARE_BIT_31_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_32_0  
+#define FUSE_SPARE_BIT_32_0                     _MK_ADDR_CONST(0x280)
+#define FUSE_SPARE_BIT_32_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_32_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_32_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_32_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_32_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SHIFT)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_RANGE                  0:0
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_32_0_SPARE_BIT_32_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_33_0  
+#define FUSE_SPARE_BIT_33_0                     _MK_ADDR_CONST(0x284)
+#define FUSE_SPARE_BIT_33_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_33_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_33_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_33_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_33_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SHIFT)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_RANGE                  0:0
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_33_0_SPARE_BIT_33_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_34_0  
+#define FUSE_SPARE_BIT_34_0                     _MK_ADDR_CONST(0x288)
+#define FUSE_SPARE_BIT_34_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_34_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_34_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_34_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_34_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SHIFT)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_RANGE                  0:0
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_34_0_SPARE_BIT_34_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_35_0  
+#define FUSE_SPARE_BIT_35_0                     _MK_ADDR_CONST(0x28c)
+#define FUSE_SPARE_BIT_35_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_35_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_35_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_35_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_35_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SHIFT)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_RANGE                  0:0
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_35_0_SPARE_BIT_35_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_36_0  
+#define FUSE_SPARE_BIT_36_0                     _MK_ADDR_CONST(0x290)
+#define FUSE_SPARE_BIT_36_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_36_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_36_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_36_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_36_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SHIFT)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_RANGE                  0:0
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_36_0_SPARE_BIT_36_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_37_0  
+#define FUSE_SPARE_BIT_37_0                     _MK_ADDR_CONST(0x294)
+#define FUSE_SPARE_BIT_37_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_37_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_37_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_37_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_37_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SHIFT)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_RANGE                  0:0
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_37_0_SPARE_BIT_37_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_38_0  
+#define FUSE_SPARE_BIT_38_0                     _MK_ADDR_CONST(0x298)
+#define FUSE_SPARE_BIT_38_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_38_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_38_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_38_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_38_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SHIFT)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_RANGE                  0:0
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_38_0_SPARE_BIT_38_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_39_0  
+#define FUSE_SPARE_BIT_39_0                     _MK_ADDR_CONST(0x29c)
+#define FUSE_SPARE_BIT_39_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_39_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_39_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_39_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_39_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SHIFT)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_RANGE                  0:0
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_39_0_SPARE_BIT_39_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_40_0  
+#define FUSE_SPARE_BIT_40_0                     _MK_ADDR_CONST(0x2a0)
+#define FUSE_SPARE_BIT_40_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_40_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_40_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_40_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_40_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SHIFT)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_RANGE                  0:0
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_40_0_SPARE_BIT_40_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_41_0  
+#define FUSE_SPARE_BIT_41_0                     _MK_ADDR_CONST(0x2a4)
+#define FUSE_SPARE_BIT_41_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_41_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_41_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_41_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_41_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SHIFT)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_RANGE                  0:0
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_41_0_SPARE_BIT_41_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_42_0  
+#define FUSE_SPARE_BIT_42_0                     _MK_ADDR_CONST(0x2a8)
+#define FUSE_SPARE_BIT_42_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_42_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_42_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_42_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_42_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SHIFT)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_RANGE                  0:0
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_42_0_SPARE_BIT_42_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_43_0  
+#define FUSE_SPARE_BIT_43_0                     _MK_ADDR_CONST(0x2ac)
+#define FUSE_SPARE_BIT_43_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_43_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_43_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_43_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_43_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SHIFT)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_RANGE                  0:0
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_43_0_SPARE_BIT_43_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_44_0  
+#define FUSE_SPARE_BIT_44_0                     _MK_ADDR_CONST(0x2b0)
+#define FUSE_SPARE_BIT_44_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_44_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_44_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_44_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_44_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SHIFT)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_RANGE                  0:0
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_44_0_SPARE_BIT_44_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_45_0  
+#define FUSE_SPARE_BIT_45_0                     _MK_ADDR_CONST(0x2b4)
+#define FUSE_SPARE_BIT_45_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_45_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_45_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_45_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_45_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SHIFT)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_RANGE                  0:0
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_45_0_SPARE_BIT_45_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_46_0  
+#define FUSE_SPARE_BIT_46_0                     _MK_ADDR_CONST(0x2b8)
+#define FUSE_SPARE_BIT_46_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_46_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_46_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_46_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_46_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SHIFT)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_RANGE                  0:0
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_46_0_SPARE_BIT_46_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_47_0  
+#define FUSE_SPARE_BIT_47_0                     _MK_ADDR_CONST(0x2bc)
+#define FUSE_SPARE_BIT_47_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_47_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_47_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_47_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_47_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SHIFT)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_RANGE                  0:0
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_47_0_SPARE_BIT_47_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_48_0  
+#define FUSE_SPARE_BIT_48_0                     _MK_ADDR_CONST(0x2c0)
+#define FUSE_SPARE_BIT_48_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_48_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_48_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_48_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_48_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SHIFT)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_RANGE                  0:0
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_48_0_SPARE_BIT_48_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_49_0  
+#define FUSE_SPARE_BIT_49_0                     _MK_ADDR_CONST(0x2c4)
+#define FUSE_SPARE_BIT_49_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_49_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_49_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_49_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_49_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SHIFT)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_RANGE                  0:0
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_49_0_SPARE_BIT_49_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_50_0  
+#define FUSE_SPARE_BIT_50_0                     _MK_ADDR_CONST(0x2c8)
+#define FUSE_SPARE_BIT_50_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_50_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_50_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_50_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_50_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SHIFT)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_RANGE                  0:0
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_50_0_SPARE_BIT_50_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_51_0  
+#define FUSE_SPARE_BIT_51_0                     _MK_ADDR_CONST(0x2cc)
+#define FUSE_SPARE_BIT_51_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_51_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_51_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_51_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_51_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SHIFT)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_RANGE                  0:0
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_51_0_SPARE_BIT_51_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_52_0  
+#define FUSE_SPARE_BIT_52_0                     _MK_ADDR_CONST(0x2d0)
+#define FUSE_SPARE_BIT_52_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_52_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_52_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_52_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_52_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SHIFT)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_RANGE                  0:0
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_52_0_SPARE_BIT_52_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_53_0  
+#define FUSE_SPARE_BIT_53_0                     _MK_ADDR_CONST(0x2d4)
+#define FUSE_SPARE_BIT_53_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_53_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_53_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_53_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_53_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SHIFT)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_RANGE                  0:0
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_53_0_SPARE_BIT_53_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_54_0  
+#define FUSE_SPARE_BIT_54_0                     _MK_ADDR_CONST(0x2d8)
+#define FUSE_SPARE_BIT_54_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_54_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_54_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_54_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_54_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SHIFT)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_RANGE                  0:0
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_54_0_SPARE_BIT_54_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_55_0  
+#define FUSE_SPARE_BIT_55_0                     _MK_ADDR_CONST(0x2dc)
+#define FUSE_SPARE_BIT_55_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_55_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_55_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_55_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_55_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SHIFT)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_RANGE                  0:0
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_55_0_SPARE_BIT_55_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_56_0  
+#define FUSE_SPARE_BIT_56_0                     _MK_ADDR_CONST(0x2e0)
+#define FUSE_SPARE_BIT_56_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_56_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_56_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_56_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_56_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SHIFT)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_RANGE                  0:0
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_56_0_SPARE_BIT_56_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_57_0  
+#define FUSE_SPARE_BIT_57_0                     _MK_ADDR_CONST(0x2e4)
+#define FUSE_SPARE_BIT_57_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_57_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_57_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_57_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_57_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SHIFT)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_RANGE                  0:0
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_57_0_SPARE_BIT_57_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_58_0  
+#define FUSE_SPARE_BIT_58_0                     _MK_ADDR_CONST(0x2e8)
+#define FUSE_SPARE_BIT_58_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_58_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_58_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_58_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_58_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SHIFT)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_RANGE                  0:0
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_58_0_SPARE_BIT_58_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_59_0  
+#define FUSE_SPARE_BIT_59_0                     _MK_ADDR_CONST(0x2ec)
+#define FUSE_SPARE_BIT_59_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_59_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_59_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_59_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_59_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SHIFT)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_RANGE                  0:0
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_59_0_SPARE_BIT_59_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_60_0  
+#define FUSE_SPARE_BIT_60_0                     _MK_ADDR_CONST(0x2f0)
+#define FUSE_SPARE_BIT_60_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_60_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_60_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_60_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_60_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SHIFT)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_RANGE                  0:0
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_60_0_SPARE_BIT_60_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register FUSE_SPARE_BIT_61_0  
+#define FUSE_SPARE_BIT_61_0                     _MK_ADDR_CONST(0x2f4)
+#define FUSE_SPARE_BIT_61_0_SECURE                      0x0
+#define FUSE_SPARE_BIT_61_0_WORD_COUNT                  0x1
+#define FUSE_SPARE_BIT_61_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_61_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_61_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SHIFT                  _MK_SHIFT_CONST(0)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_FIELD                  (_MK_MASK_CONST(0x1) << FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SHIFT)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_RANGE                  0:0
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_WOFFSET                        0x0
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_DEFAULT                        _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define FUSE_SPARE_BIT_61_0_SPARE_BIT_61_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARFUSE_REGS(_op_) \
+_op_(FUSE_FUSECTRL_0) \
+_op_(FUSE_FUSEADDR_0) \
+_op_(FUSE_FUSERDATA_0) \
+_op_(FUSE_FUSEWDATA_0) \
+_op_(FUSE_FUSETIME_RD1_0) \
+_op_(FUSE_FUSETIME_RD2_0) \
+_op_(FUSE_FUSETIME_PGM1_0) \
+_op_(FUSE_FUSETIME_PGM2_0) \
+_op_(FUSE_PRIV2INTFC_START_0) \
+_op_(FUSE_FUSEBYPASS_0) \
+_op_(FUSE_PRIVATEKEYDISABLE_0) \
+_op_(FUSE_DISABLEREGPROGRAM_0) \
+_op_(FUSE_WRITE_ACCESS_SW_0) \
+_op_(FUSE_PWR_GOOD_SW_0) \
+_op_(FUSE_REG_REF_CTRL_0) \
+_op_(FUSE_REG_BIAS_CTRL_0) \
+_op_(FUSE_PRIVATE_KEY0_NONZERO_0) \
+_op_(FUSE_PRIVATE_KEY1_NONZERO_0) \
+_op_(FUSE_PRIVATE_KEY2_NONZERO_0) \
+_op_(FUSE_PRIVATE_KEY3_NONZERO_0) \
+_op_(FUSE_PRIVATE_KEY4_NONZERO_0) \
+_op_(FUSE_PRODUCTION_MODE_0) \
+_op_(FUSE_JTAG_SECUREID_VALID_0) \
+_op_(FUSE_JTAG_SECUREID_0_0) \
+_op_(FUSE_JTAG_SECUREID_1_0) \
+_op_(FUSE_SKU_INFO_0) \
+_op_(FUSE_PROCESS_CALIB_0) \
+_op_(FUSE_IO_CALIB_0) \
+_op_(FUSE_DAC_CRT_CALIB_0) \
+_op_(FUSE_DAC_HDTV_CALIB_0) \
+_op_(FUSE_DAC_SDTV_CALIB_0) \
+_op_(FUSE_FA_0) \
+_op_(FUSE_RESERVED_PRODUCTION_0) \
+_op_(FUSE_HDMI_LANE0_CALIB_0) \
+_op_(FUSE_HDMI_LANE1_CALIB_0) \
+_op_(FUSE_HDMI_LANE2_CALIB_0) \
+_op_(FUSE_HDMI_LANE3_CALIB_0) \
+_op_(FUSE_SECURITY_MODE_0) \
+_op_(FUSE_PRIVATE_KEY0_0) \
+_op_(FUSE_PRIVATE_KEY1_0) \
+_op_(FUSE_PRIVATE_KEY2_0) \
+_op_(FUSE_PRIVATE_KEY3_0) \
+_op_(FUSE_PRIVATE_KEY4_0) \
+_op_(FUSE_ARM_DEBUG_DIS_0) \
+_op_(FUSE_BOOT_DEVICE_INFO_0) \
+_op_(FUSE_RESERVED_SW_0) \
+_op_(FUSE_ARM_DEBUG_CONTROL_0) \
+_op_(FUSE_RESERVED_ODM0_0) \
+_op_(FUSE_RESERVED_ODM1_0) \
+_op_(FUSE_RESERVED_ODM2_0) \
+_op_(FUSE_RESERVED_ODM3_0) \
+_op_(FUSE_RESERVED_ODM4_0) \
+_op_(FUSE_RESERVED_ODM5_0) \
+_op_(FUSE_RESERVED_ODM6_0) \
+_op_(FUSE_RESERVED_ODM7_0) \
+_op_(FUSE_OBS_DIS_0) \
+_op_(FUSE_NOR_INFO_0) \
+_op_(FUSE_USB_CALIB_0) \
+_op_(FUSE_KFUSE_PRIVKEY_CTRL_0) \
+_op_(FUSE_PACKAGE_INFO_0) \
+_op_(FUSE_SPARE_BIT_0_0) \
+_op_(FUSE_SPARE_BIT_1_0) \
+_op_(FUSE_SPARE_BIT_2_0) \
+_op_(FUSE_SPARE_BIT_3_0) \
+_op_(FUSE_SPARE_BIT_4_0) \
+_op_(FUSE_SPARE_BIT_5_0) \
+_op_(FUSE_SPARE_BIT_6_0) \
+_op_(FUSE_SPARE_BIT_7_0) \
+_op_(FUSE_SPARE_BIT_8_0) \
+_op_(FUSE_SPARE_BIT_9_0) \
+_op_(FUSE_SPARE_BIT_10_0) \
+_op_(FUSE_SPARE_BIT_11_0) \
+_op_(FUSE_SPARE_BIT_12_0) \
+_op_(FUSE_SPARE_BIT_13_0) \
+_op_(FUSE_SPARE_BIT_14_0) \
+_op_(FUSE_SPARE_BIT_15_0) \
+_op_(FUSE_SPARE_BIT_16_0) \
+_op_(FUSE_SPARE_BIT_17_0) \
+_op_(FUSE_SPARE_BIT_18_0) \
+_op_(FUSE_SPARE_BIT_19_0) \
+_op_(FUSE_SPARE_BIT_20_0) \
+_op_(FUSE_SPARE_BIT_21_0) \
+_op_(FUSE_SPARE_BIT_22_0) \
+_op_(FUSE_SPARE_BIT_23_0) \
+_op_(FUSE_SPARE_BIT_24_0) \
+_op_(FUSE_SPARE_BIT_25_0) \
+_op_(FUSE_SPARE_BIT_26_0) \
+_op_(FUSE_SPARE_BIT_27_0) \
+_op_(FUSE_SPARE_BIT_28_0) \
+_op_(FUSE_SPARE_BIT_29_0) \
+_op_(FUSE_SPARE_BIT_30_0) \
+_op_(FUSE_SPARE_BIT_31_0) \
+_op_(FUSE_SPARE_BIT_32_0) \
+_op_(FUSE_SPARE_BIT_33_0) \
+_op_(FUSE_SPARE_BIT_34_0) \
+_op_(FUSE_SPARE_BIT_35_0) \
+_op_(FUSE_SPARE_BIT_36_0) \
+_op_(FUSE_SPARE_BIT_37_0) \
+_op_(FUSE_SPARE_BIT_38_0) \
+_op_(FUSE_SPARE_BIT_39_0) \
+_op_(FUSE_SPARE_BIT_40_0) \
+_op_(FUSE_SPARE_BIT_41_0) \
+_op_(FUSE_SPARE_BIT_42_0) \
+_op_(FUSE_SPARE_BIT_43_0) \
+_op_(FUSE_SPARE_BIT_44_0) \
+_op_(FUSE_SPARE_BIT_45_0) \
+_op_(FUSE_SPARE_BIT_46_0) \
+_op_(FUSE_SPARE_BIT_47_0) \
+_op_(FUSE_SPARE_BIT_48_0) \
+_op_(FUSE_SPARE_BIT_49_0) \
+_op_(FUSE_SPARE_BIT_50_0) \
+_op_(FUSE_SPARE_BIT_51_0) \
+_op_(FUSE_SPARE_BIT_52_0) \
+_op_(FUSE_SPARE_BIT_53_0) \
+_op_(FUSE_SPARE_BIT_54_0) \
+_op_(FUSE_SPARE_BIT_55_0) \
+_op_(FUSE_SPARE_BIT_56_0) \
+_op_(FUSE_SPARE_BIT_57_0) \
+_op_(FUSE_SPARE_BIT_58_0) \
+_op_(FUSE_SPARE_BIT_59_0) \
+_op_(FUSE_SPARE_BIT_60_0) \
+_op_(FUSE_SPARE_BIT_61_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_FUSE       0x00000000
+
+//
+// ARFUSE REGISTER BANKS
+//
+
+#define FUSE0_FIRST_REG 0x0000 // FUSE_FUSECTRL_0
+#define FUSE0_LAST_REG 0x0034 // FUSE_PWR_GOOD_SW_0
+#define FUSE1_FIRST_REG 0x0048 // FUSE_REG_REF_CTRL_0
+#define FUSE1_LAST_REG 0x0060 // FUSE_PRIVATE_KEY4_NONZERO_0
+#define FUSE2_FIRST_REG 0x0100 // FUSE_PRODUCTION_MODE_0
+#define FUSE2_LAST_REG 0x0124 // FUSE_DAC_SDTV_CALIB_0
+#define FUSE3_FIRST_REG 0x0148 // FUSE_FA_0
+#define FUSE3_LAST_REG 0x015c // FUSE_HDMI_LANE3_CALIB_0
+#define FUSE4_FIRST_REG 0x01a0 // FUSE_SECURITY_MODE_0
+#define FUSE4_LAST_REG 0x01f0 // FUSE_USB_CALIB_0
+#define FUSE5_FIRST_REG 0x01f8 // FUSE_KFUSE_PRIVKEY_CTRL_0
+#define FUSE5_LAST_REG 0x02f4 // FUSE_SPARE_BIT_61_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARFUSE_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/ari2c.h b/arch/arm/mach-tegra/nv/include/ap20/ari2c.h
new file mode 100644
index 000000000000..ffe4e11f404a
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/ari2c.h
@@ -0,0 +1,1393 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARI2C_H_INC_
+#define ___ARI2C_H_INC_
+
+// Register I2C_I2C_CNFG_0  
+#define I2C_I2C_CNFG_0                  _MK_ADDR_CONST(0x0)
+#define I2C_I2C_CNFG_0_SECURE                   0x0
+#define I2C_I2C_CNFG_0_WORD_COUNT                       0x1
+#define I2C_I2C_CNFG_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_RESET_MASK                       _MK_MASK_CONST(0x7fff)
+#define I2C_I2C_CNFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_READ_MASK                        _MK_MASK_CONST(0x7fff)
+#define I2C_I2C_CNFG_0_WRITE_MASK                       _MK_MASK_CONST(0x7fff)
+// Debounce period for sda and scl lines
+// 0 = No debounce
+// 1 = 2T
+// 2  = 4T
+// 3 =  6T etc
+// where T is the period of the fix PLL 
+//clk source coming to i2c.
+//Maximum debounce period programmable is 
+//14T.A debounce period of >50ns is desirable
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT                       _MK_SHIFT_CONST(12)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_FIELD                       (_MK_MASK_CONST(0x7) << I2C_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_RANGE                       14:12
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Write 1 to enable new master fsm
+// 0 = old fsm
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT                     _MK_SHIFT_CONST(11)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_FIELD                     (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_RANGE                     11:11
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_WOFFSET                   0x0
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DISABLE                   _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_ENABLE                    _MK_ENUM_CONST(1)
+
+// Write 1 to initiate transfer in packet mode.
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SHIFT                     _MK_SHIFT_CONST(10)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_FIELD                     (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_PACKET_MODE_EN_SHIFT)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_RANGE                     10:10
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_WOFFSET                   0x0
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_NOP                       _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_GO                        _MK_ENUM_CONST(1)
+
+// Writing a 1 causes the master to initiate the
+// transaction in normal mode. Values of other  bits are not
+// affected when this bit is 1,Cleared by 
+// hardware.  Other bits of the register are
+// masked for writes when this bit is programmed
+// to one.hence,firware should first configure
+// all other registrs and  bits [8:0] of 
+// I2C_CNFG register before the bit
+// I2C_CNFG[9] is programmed to Zero.
+#define I2C_I2C_CNFG_0_SEND_SHIFT                       _MK_SHIFT_CONST(9)
+#define I2C_I2C_CNFG_0_SEND_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_SEND_SHIFT)
+#define I2C_I2C_CNFG_0_SEND_RANGE                       9:9
+#define I2C_I2C_CNFG_0_SEND_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_SEND_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_SEND_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_NOP                 _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_SEND_GO                  _MK_ENUM_CONST(1)
+
+// Enable mode to handle devices that do not generate ACK. 
+// 1 - dont look for an ack at the end of the Enable
+#define I2C_I2C_CNFG_0_NOACK_SHIFT                      _MK_SHIFT_CONST(8)
+#define I2C_I2C_CNFG_0_NOACK_FIELD                      (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_NOACK_SHIFT)
+#define I2C_I2C_CNFG_0_NOACK_RANGE                      8:8
+#define I2C_I2C_CNFG_0_NOACK_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_NOACK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_NOACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_DISABLE                    _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_NOACK_ENABLE                     _MK_ENUM_CONST(1)
+
+// Read/Write Command for Slave 2:
+// 1 -  Read Transaction; 0 -  write Transaction.
+// For a 7-bit slave address,this bit must match
+// with the LSB of address byte for slave 2.
+// Valid only when  bit-4 of this register is 
+// set
+#define I2C_I2C_CNFG_0_CMD2_SHIFT                       _MK_SHIFT_CONST(7)
+#define I2C_I2C_CNFG_0_CMD2_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_CMD2_SHIFT)
+#define I2C_I2C_CNFG_0_CMD2_RANGE                       7:7
+#define I2C_I2C_CNFG_0_CMD2_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_CMD2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_CMD2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_CMD2_ENABLE                      _MK_ENUM_CONST(1)
+
+// Read/Write Command for Slave 1: 
+// 1 - Read Transaction; 0 -  write Transaction.
+// Command for Slave 1: For a 7-bit slave address
+// this bit must match with the LSB of address 
+// byte for slave1.
+#define I2C_I2C_CNFG_0_CMD1_SHIFT                       _MK_SHIFT_CONST(6)
+#define I2C_I2C_CNFG_0_CMD1_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_CMD1_SHIFT)
+#define I2C_I2C_CNFG_0_CMD1_RANGE                       6:6
+#define I2C_I2C_CNFG_0_CMD1_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_CMD1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_CMD1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_CMD1_ENABLE                      _MK_ENUM_CONST(1)
+
+//  1 = Yes, a Start byte needs to be  sent.
+#define I2C_I2C_CNFG_0_START_SHIFT                      _MK_SHIFT_CONST(5)
+#define I2C_I2C_CNFG_0_START_FIELD                      (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_START_SHIFT)
+#define I2C_I2C_CNFG_0_START_RANGE                      5:5
+#define I2C_I2C_CNFG_0_START_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_DISABLE                    _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_START_ENABLE                     _MK_ENUM_CONST(1)
+
+//  1 - Enables a two slave transaction ;
+//  0 = No command for Slave 2 present.
+#define I2C_I2C_CNFG_0_SLV2_SHIFT                       _MK_SHIFT_CONST(4)
+#define I2C_I2C_CNFG_0_SLV2_FIELD                       (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_SLV2_SHIFT)
+#define I2C_I2C_CNFG_0_SLV2_RANGE                       4:4
+#define I2C_I2C_CNFG_0_SLV2_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_SLV2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_SLV2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_SLV2_ENABLE                      _MK_ENUM_CONST(1)
+
+// The Number of bytes to be transmitted per
+// transaction 000= 1byte ... 111 = 8bytes;
+// In a two slave transaction number of bytes
+// should be programmed less than 011.
+#define I2C_I2C_CNFG_0_LENGTH_SHIFT                     _MK_SHIFT_CONST(1)
+#define I2C_I2C_CNFG_0_LENGTH_FIELD                     (_MK_MASK_CONST(0x7) << I2C_I2C_CNFG_0_LENGTH_SHIFT)
+#define I2C_I2C_CNFG_0_LENGTH_RANGE                     3:1
+#define I2C_I2C_CNFG_0_LENGTH_WOFFSET                   0x0
+#define I2C_I2C_CNFG_0_LENGTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_LENGTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define I2C_I2C_CNFG_0_LENGTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_LENGTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Address mode defines whether a 7-bit or a 
+// 10-bit slave address is programmed. 1 = 10-bit
+// device address 0  = 7-bit device address  
+#define I2C_I2C_CNFG_0_A_MOD_SHIFT                      _MK_SHIFT_CONST(0)
+#define I2C_I2C_CNFG_0_A_MOD_FIELD                      (_MK_MASK_CONST(0x1) << I2C_I2C_CNFG_0_A_MOD_SHIFT)
+#define I2C_I2C_CNFG_0_A_MOD_RANGE                      0:0
+#define I2C_I2C_CNFG_0_A_MOD_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_A_MOD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_A_MOD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_SEVEN_BIT_DEVICE_ADDRESS                   _MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_A_MOD_TEN_BIT_DEVICE_ADDRESS                     _MK_ENUM_CONST(1)
+
+
+// Register I2C_I2C_CMD_ADDR0_0  
+#define I2C_I2C_CMD_ADDR0_0                     _MK_ADDR_CONST(0x4)
+#define I2C_I2C_CMD_ADDR0_0_SECURE                      0x0
+#define I2C_I2C_CMD_ADDR0_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_ADDR0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR0_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+// In case of 7-Bit mode address is written in the 
+// I2C_CMD_ADDR0[7:1] and I2C_CMD_ADDR0[0] indicates the
+// read/write transaction.I2C_CMD_ADDR0[0] bit must match 
+// with the I2C_CNFG[6].
+// In case of 10-Bit mode addess is written in 
+// I2C_CMD_ADDR0[9:0] and I2C_CNFG[6]  indicates the 
+// read/write transaction. 
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_FIELD                 (_MK_MASK_CONST(0x3ff) << I2C_I2C_CMD_ADDR0_0_ADDR0_SHIFT)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_RANGE                 9:0
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_WOFFSET                       0x0
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_CMD_ADDR1_0  
+#define I2C_I2C_CMD_ADDR1_0                     _MK_ADDR_CONST(0x8)
+#define I2C_I2C_CMD_ADDR1_0_SECURE                      0x0
+#define I2C_I2C_CMD_ADDR1_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_ADDR1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_RESET_MASK                  _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_READ_MASK                   _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR1_0_WRITE_MASK                  _MK_MASK_CONST(0x3ff)
+// In case of 7-Bit mode address is written in the 
+// I2C_CMD_ADDR0[7:1] and I2C_CMD_ADDR0[0] indicates the 
+// read/write transaction.I2C_CMD_ADDR0[0] bit must match
+// with the I2C_CNFG[7].        
+// In case of 10-Bit mode addess is written in 
+// I2C_CMD_ADDR0[9:0] and I2C_CNFG[7] indicates the 
+// read/write transaction. 
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_FIELD                 (_MK_MASK_CONST(0x3ff) << I2C_I2C_CMD_ADDR1_0_ADDR1_SHIFT)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_RANGE                 9:0
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_WOFFSET                       0x0
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_DEFAULT_MASK                  _MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_CMD_DATA1_0  
+#define I2C_I2C_CMD_DATA1_0                     _MK_ADDR_CONST(0xc)
+#define I2C_I2C_CMD_DATA1_0_SECURE                      0x0
+#define I2C_I2C_CMD_DATA1_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_DATA1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA1_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Fourth data byte to be sent/received
+#define I2C_I2C_CMD_DATA1_0_DATA4_SHIFT                 _MK_SHIFT_CONST(24)
+#define I2C_I2C_CMD_DATA1_0_DATA4_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA4_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA4_RANGE                 31:24
+#define I2C_I2C_CMD_DATA1_0_DATA4_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA4_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Third data byte to be sent/received
+#define I2C_I2C_CMD_DATA1_0_DATA3_SHIFT                 _MK_SHIFT_CONST(16)
+#define I2C_I2C_CMD_DATA1_0_DATA3_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA3_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA3_RANGE                 23:16
+#define I2C_I2C_CMD_DATA1_0_DATA3_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Second data byte to be sent/received
+#define I2C_I2C_CMD_DATA1_0_DATA2_SHIFT                 _MK_SHIFT_CONST(8)
+#define I2C_I2C_CMD_DATA1_0_DATA2_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA2_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA2_RANGE                 15:8
+#define I2C_I2C_CMD_DATA1_0_DATA2_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This register contains the first data byte to be  sent/received.
+#define I2C_I2C_CMD_DATA1_0_DATA1_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA1_0_DATA1_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA1_RANGE                 7:0
+#define I2C_I2C_CMD_DATA1_0_DATA1_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_CMD_DATA2_0  
+#define I2C_I2C_CMD_DATA2_0                     _MK_ADDR_CONST(0x10)
+#define I2C_I2C_CMD_DATA2_0_SECURE                      0x0
+#define I2C_I2C_CMD_DATA2_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_DATA2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA2_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Eighth data byte to be sent/received
+#define I2C_I2C_CMD_DATA2_0_DATA8_SHIFT                 _MK_SHIFT_CONST(24)
+#define I2C_I2C_CMD_DATA2_0_DATA8_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA8_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA8_RANGE                 31:24
+#define I2C_I2C_CMD_DATA2_0_DATA8_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA8_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Seventh data byte to be sent/received
+#define I2C_I2C_CMD_DATA2_0_DATA7_SHIFT                 _MK_SHIFT_CONST(16)
+#define I2C_I2C_CMD_DATA2_0_DATA7_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA7_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA7_RANGE                 23:16
+#define I2C_I2C_CMD_DATA2_0_DATA7_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA7_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Sixth data byte to be sent/received
+#define I2C_I2C_CMD_DATA2_0_DATA6_SHIFT                 _MK_SHIFT_CONST(8)
+#define I2C_I2C_CMD_DATA2_0_DATA6_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA6_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA6_RANGE                 15:8
+#define I2C_I2C_CMD_DATA2_0_DATA6_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA6_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This register contains the Fifth data byte to be  sent/received.
+#define I2C_I2C_CMD_DATA2_0_DATA5_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_CMD_DATA2_0_DATA5_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA5_RANGE                 7:0
+#define I2C_I2C_CMD_DATA2_0_DATA5_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+
+// Register I2C_I2C_STATUS_0  
+#define I2C_I2C_STATUS_0                        _MK_ADDR_CONST(0x1c)
+#define I2C_I2C_STATUS_0_SECURE                         0x0
+#define I2C_I2C_STATUS_0_WORD_COUNT                     0x1
+#define I2C_I2C_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x1ff)
+#define I2C_I2C_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x1ff)
+#define I2C_I2C_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+//  1 = Busy.
+#define I2C_I2C_STATUS_0_BUSY_SHIFT                     _MK_SHIFT_CONST(8)
+#define I2C_I2C_STATUS_0_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << I2C_I2C_STATUS_0_BUSY_SHIFT)
+#define I2C_I2C_STATUS_0_BUSY_RANGE                     8:8
+#define I2C_I2C_STATUS_0_BUSY_WOFFSET                   0x0
+#define I2C_I2C_STATUS_0_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_I2C_STATUS_0_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_NOT_BUSY                  _MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_BUSY_BUSY                      _MK_ENUM_CONST(1)
+
+// Transaction for Slave2 for x byte failed. x is 'h0 to 'ha.
+// all others invalid 
+#define I2C_I2C_STATUS_0_CMD2_STAT_SHIFT                        _MK_SHIFT_CONST(4)
+#define I2C_I2C_STATUS_0_CMD2_STAT_FIELD                        (_MK_MASK_CONST(0xf) << I2C_I2C_STATUS_0_CMD2_STAT_SHIFT)
+#define I2C_I2C_STATUS_0_CMD2_STAT_RANGE                        7:4
+#define I2C_I2C_STATUS_0_CMD2_STAT_WOFFSET                      0x0
+#define I2C_I2C_STATUS_0_CMD2_STAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_XFER_SUCCESSFUL                  _MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE1                  _MK_ENUM_CONST(1)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE2                  _MK_ENUM_CONST(2)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE3                  _MK_ENUM_CONST(3)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE4                  _MK_ENUM_CONST(4)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE5                  _MK_ENUM_CONST(5)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE6                  _MK_ENUM_CONST(6)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE7                  _MK_ENUM_CONST(7)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE8                  _MK_ENUM_CONST(8)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE9                  _MK_ENUM_CONST(9)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE10                 _MK_ENUM_CONST(10)
+
+// Transaction for Slave1 for x byte failed. x is 'h0 to 'ha.
+// all others invalid
+#define I2C_I2C_STATUS_0_CMD1_STAT_SHIFT                        _MK_SHIFT_CONST(0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_FIELD                        (_MK_MASK_CONST(0xf) << I2C_I2C_STATUS_0_CMD1_STAT_SHIFT)
+#define I2C_I2C_STATUS_0_CMD1_STAT_RANGE                        3:0
+#define I2C_I2C_STATUS_0_CMD1_STAT_WOFFSET                      0x0
+#define I2C_I2C_STATUS_0_CMD1_STAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_XFER_SUCCESSFUL                  _MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE1                  _MK_ENUM_CONST(1)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE2                  _MK_ENUM_CONST(2)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE3                  _MK_ENUM_CONST(3)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE4                  _MK_ENUM_CONST(4)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE5                  _MK_ENUM_CONST(5)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE6                  _MK_ENUM_CONST(6)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE7                  _MK_ENUM_CONST(7)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE8                  _MK_ENUM_CONST(8)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE9                  _MK_ENUM_CONST(9)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE10                 _MK_ENUM_CONST(10)
+
+
+// Register I2C_I2C_SL_CNFG_0  
+#define I2C_I2C_SL_CNFG_0                       _MK_ADDR_CONST(0x20)
+#define I2C_I2C_SL_CNFG_0_SECURE                        0x0
+#define I2C_I2C_SL_CNFG_0_WORD_COUNT                    0x1
+#define I2C_I2C_SL_CNFG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESET_MASK                    _MK_MASK_CONST(0x7)
+#define I2C_I2C_SL_CNFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_READ_MASK                     _MK_MASK_CONST(0x7)
+#define I2C_I2C_SL_CNFG_0_WRITE_MASK                    _MK_MASK_CONST(0x7)
+// New Slave
+// 1 - use new slave
+#define I2C_I2C_SL_CNFG_0_NEWSL_SHIFT                   _MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_CNFG_0_NEWSL_FIELD                   (_MK_MASK_CONST(0x1) << I2C_I2C_SL_CNFG_0_NEWSL_SHIFT)
+#define I2C_I2C_SL_CNFG_0_NEWSL_RANGE                   2:2
+#define I2C_I2C_SL_CNFG_0_NEWSL_WOFFSET                 0x0
+#define I2C_I2C_SL_CNFG_0_NEWSL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_NEWSL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_DISABLE                 _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_ENABLE                  _MK_ENUM_CONST(1)
+
+// Disable Slave Ack. 
+// 1 - slave will not ack reception of address or data byte. 
+#define I2C_I2C_SL_CNFG_0_NACK_SHIFT                    _MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_CNFG_0_NACK_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_CNFG_0_NACK_SHIFT)
+#define I2C_I2C_SL_CNFG_0_NACK_RANGE                    1:1
+#define I2C_I2C_SL_CNFG_0_NACK_WOFFSET                  0x0
+#define I2C_I2C_SL_CNFG_0_NACK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_NACK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_NACK_ENABLE                   _MK_ENUM_CONST(1)
+
+// Slave response to general call address (zero address) 
+// 1 - Enable.
+#define I2C_I2C_SL_CNFG_0_RESP_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_CNFG_0_RESP_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_CNFG_0_RESP_SHIFT)
+#define I2C_I2C_SL_CNFG_0_RESP_RANGE                    0:0
+#define I2C_I2C_SL_CNFG_0_RESP_WOFFSET                  0x0
+#define I2C_I2C_SL_CNFG_0_RESP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_RESP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_RESP_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register I2C_I2C_SL_RCVD_0  
+#define I2C_I2C_SL_RCVD_0                       _MK_ADDR_CONST(0x24)
+#define I2C_I2C_SL_RCVD_0_SECURE                        0x0
+#define I2C_I2C_SL_RCVD_0_WORD_COUNT                    0x1
+#define I2C_I2C_SL_RCVD_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_RCVD_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_RCVD_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+//slave Received data 
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_FIELD                 (_MK_MASK_CONST(0xff) << I2C_I2C_SL_RCVD_0_SL_DATA_SHIFT)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_RANGE                 7:0
+#define I2C_I2C_SL_RCVD_0_SL_DATA_WOFFSET                       0x0
+#define I2C_I2C_SL_RCVD_0_SL_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_SL_STATUS_0  
+#define I2C_I2C_SL_STATUS_0                     _MK_ADDR_CONST(0x28)
+#define I2C_I2C_SL_STATUS_0_SECURE                      0x0
+#define I2C_I2C_SL_STATUS_0_WORD_COUNT                  0x1
+#define I2C_I2C_SL_STATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RESET_MASK                  _MK_MASK_CONST(0x7fff)
+#define I2C_I2C_SL_STATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_READ_MASK                   _MK_MASK_CONST(0x7fff)
+#define I2C_I2C_SL_STATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+//  HW master addr received via general call addressing.
+//  This field is meaningful only if HW_MSTR_INT is set.
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SHIFT                   _MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_FIELD                   (_MK_MASK_CONST(0x7f) << I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SHIFT)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_RANGE                   14:8
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_WOFFSET                 0x0
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_DEFAULT_MASK                    _MK_MASK_CONST(0x7f)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  1 = Interrupt has been generated by  slave  
+//  Hardware Master Address is received after
+//  General Call Address.
+//  1 = Received HW Master Address
+//  0 = No event.
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SHIFT                   _MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_FIELD                   (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SHIFT)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_RANGE                   7:7
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_WOFFSET                 0x0
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//  1 = Interrupt has been generated by  slave  
+//  By after General Call Address is 0x04.
+//  1 = Reprogram slave address.
+//  0 = No action.
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_SHIFT                     _MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_FIELD                     (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_REPROG_SL_SHIFT)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_RANGE                     6:6
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_WOFFSET                   0x0
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1 = Interrupt has been generated by  slave  
+//  By after General Call Address is 0x06.
+//  1 = Reset and reprogram slave address.
+//  0 = No action.
+#define I2C_I2C_SL_STATUS_0_RST_SL_SHIFT                        _MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_STATUS_0_RST_SL_FIELD                        (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_RST_SL_SHIFT)
+#define I2C_I2C_SL_STATUS_0_RST_SL_RANGE                        5:5
+#define I2C_I2C_SL_STATUS_0_RST_SL_WOFFSET                      0x0
+#define I2C_I2C_SL_STATUS_0_RST_SL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RST_SL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RST_SL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RST_SL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//  1 = Interrupt has been generated by  slave  
+//  Transaction completed as indicated by stop/repeat start condition.
+//  1 = Transaction completed.
+//  0 = No transaction occurred  or transaction in progress.
+#define I2C_I2C_SL_STATUS_0_END_TRANS_SHIFT                     _MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_FIELD                     (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_END_TRANS_SHIFT)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_RANGE                     4:4
+#define I2C_I2C_SL_STATUS_0_END_TRANS_WOFFSET                   0x0
+#define I2C_I2C_SL_STATUS_0_END_TRANS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  1 = Interrupt has been generated by  slave  
+//  0 = No interrupt generated  
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SHIFT                        _MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_FIELD                        (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_SL_IRQ_SHIFT)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_RANGE                        3:3
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_WOFFSET                      0x0
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_UNSET                        _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SET                  _MK_ENUM_CONST(1)
+
+//  New Transaction Receieved status
+//  1 = Transaction occurred. 
+//  0  = No transaction occurred 
+#define I2C_I2C_SL_STATUS_0_RCVD_SHIFT                  _MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_STATUS_0_RCVD_FIELD                  (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_RCVD_SHIFT)
+#define I2C_I2C_SL_STATUS_0_RCVD_RANGE                  2:2
+#define I2C_I2C_SL_STATUS_0_RCVD_WOFFSET                        0x0
+#define I2C_I2C_SL_STATUS_0_RCVD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RCVD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_NO_TRANSACTION_OCCURED                 _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_RCVD_TRANSACTION_OCCURED                    _MK_ENUM_CONST(1)
+
+//  Slave Transaction status 
+//  0 = Write
+//  1=Read
+#define I2C_I2C_SL_STATUS_0_RNW_SHIFT                   _MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_STATUS_0_RNW_FIELD                   (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_RNW_SHIFT)
+#define I2C_I2C_SL_STATUS_0_RNW_RANGE                   1:1
+#define I2C_I2C_SL_STATUS_0_RNW_WOFFSET                 0x0
+#define I2C_I2C_SL_STATUS_0_RNW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RNW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_WRITE                   _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_RNW_READ                    _MK_ENUM_CONST(1)
+
+//  Zero Address Status
+//  1 = Yes, slave responded  
+//  0  = No, slave did not respond
+#define I2C_I2C_SL_STATUS_0_ZA_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_STATUS_0_ZA_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_STATUS_0_ZA_SHIFT)
+#define I2C_I2C_SL_STATUS_0_ZA_RANGE                    0:0
+#define I2C_I2C_SL_STATUS_0_ZA_WOFFSET                  0x0
+#define I2C_I2C_SL_STATUS_0_ZA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_ZA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_NO_SLAVE_RESPONSE                        _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_ZA_SLAVE_RESPONSE                   _MK_ENUM_CONST(1)
+
+
+// Register I2C_I2C_SL_ADDR1_0  
+#define I2C_I2C_SL_ADDR1_0                      _MK_ADDR_CONST(0x2c)
+#define I2C_I2C_SL_ADDR1_0_SECURE                       0x0
+#define I2C_I2C_SL_ADDR1_0_WORD_COUNT                   0x1
+#define I2C_I2C_SL_ADDR1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_ADDR1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_ADDR1_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+//   For a 10-bit slave address, this field is the least significant 8 bits. 
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SHIFT                       _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_FIELD                       (_MK_MASK_CONST(0xff) << I2C_I2C_SL_ADDR1_0_SL_ADDR0_SHIFT)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_RANGE                       7:0
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_WOFFSET                     0x0
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_SL_ADDR2_0  
+#define I2C_I2C_SL_ADDR2_0                      _MK_ADDR_CONST(0x30)
+#define I2C_I2C_SL_ADDR2_0_SECURE                       0x0
+#define I2C_I2C_SL_ADDR2_0_WORD_COUNT                   0x1
+#define I2C_I2C_SL_ADDR2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_RESET_MASK                   _MK_MASK_CONST(0x7)
+#define I2C_I2C_SL_ADDR2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_READ_MASK                    _MK_MASK_CONST(0x7)
+#define I2C_I2C_SL_ADDR2_0_WRITE_MASK                   _MK_MASK_CONST(0x7)
+// In 7 bit address mode these bits are dont care;
+// In 10 bit address mode they represent the 2 MSB of the address.
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SHIFT                     _MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_FIELD                     (_MK_MASK_CONST(0x3) << I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_RANGE                     2:1
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_WOFFSET                   0x0
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 0 = 7-bit addressing.
+// 1 - 10 bit addressing.  
+#define I2C_I2C_SL_ADDR2_0_VLD_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_ADDR2_0_VLD_FIELD                    (_MK_MASK_CONST(0x1) << I2C_I2C_SL_ADDR2_0_VLD_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_VLD_RANGE                    0:0
+#define I2C_I2C_SL_ADDR2_0_VLD_WOFFSET                  0x0
+#define I2C_I2C_SL_ADDR2_0_VLD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_ADDR2_0_VLD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_SEVEN_BIT_ADDR_MODE                      _MK_ENUM_CONST(0)
+#define I2C_I2C_SL_ADDR2_0_VLD_TEN_BIT_ADDR_MODE                        _MK_ENUM_CONST(1)
+
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Register I2C_I2C_SL_DELAY_COUNT_0  
+#define I2C_I2C_SL_DELAY_COUNT_0                        _MK_ADDR_CONST(0x3c)
+#define I2C_I2C_SL_DELAY_COUNT_0_SECURE                         0x0
+#define I2C_I2C_SL_DELAY_COUNT_0_WORD_COUNT                     0x1
+#define I2C_I2C_SL_DELAY_COUNT_0_RESET_VAL                      _MK_MASK_CONST(0x1e)
+#define I2C_I2C_SL_DELAY_COUNT_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+// The value determines the timing  between an address 
+// cycle and a subsequent data cycle or two consecutive 
+// data  cycles on the bus.The I2C_SL_DELAY_COUNT is valid
+// only when internal slave is accessed.
+// I2C_SL_DELAY_COUNT has to be programmed such that 
+// TIMING = T * DLY where T is period of clock source
+// selected for I2c; and DLY is I2C_SL_DELAY_COUNT ;
+// TIMING is the desired timing, A value of >= 1250 ns is
+// advisable.
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_FIELD                   (_MK_MASK_CONST(0xffff) << I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SHIFT)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_RANGE                   15:0
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_WOFFSET                 0x0
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_DEFAULT                 _MK_MASK_CONST(0x1e)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Packet I2C_IO_PACKET_HEADER_0
+#define I2C_IO_PACKET_HEADER_0_SIZE 32
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT                        _MK_SHIFT_CONST(30)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_FIELD                        (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT                      _MK_SHIFT_CONST(28)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_FIELD                      (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_RANGE                      _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(28)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_ROW                        0
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_ONE                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_TWO                        _MK_ENUM_CONST(1)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_THREE                      _MK_ENUM_CONST(2)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_FOUR                       _MK_ENUM_CONST(3)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT                        _MK_SHIFT_CONST(24)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_FIELD                        (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_RANGE                        _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PKTID_SHIFT                      _MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_PKTID_FIELD                      (_MK_MASK_CONST(0xff) << I2C_IO_PACKET_HEADER_0_PKTID_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PKTID_RANGE                      _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_PKTID_ROW                        0
+
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT                      _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_FIELD                      (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_RANGE                      _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_ROW                        0
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C1                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C2                       _MK_ENUM_CONST(1)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C3                       _MK_ENUM_CONST(2)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_DVC_I2C                    _MK_ENUM_CONST(3)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT                        _MK_SHIFT_CONST(8)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_FIELD                        (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT                   _MK_SHIFT_CONST(4)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_FIELD                   (_MK_MASK_CONST(0xf) << I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RANGE                   _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(4)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_ROW                     0
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RESERVED                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_I2C                     _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT                        _MK_SHIFT_CONST(3)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_FIELD                        (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_FIELD                    (_MK_MASK_CONST(0x7) << I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_ROW                      0
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT                        _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_FIELD                        (_MK_MASK_CONST(0xfffff) << I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_ROW                  1
+
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT                        _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_FIELD                        (_MK_MASK_CONST(0xfff) << I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_ROW                  1
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT                        _MK_SHIFT_CONST(23)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_FIELD                        (_MK_MASK_CONST(0x1ff) << I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(23)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT                    _MK_SHIFT_CONST(22)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_RANGE                    _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT                    _MK_SHIFT_CONST(21)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_RANGE                    _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT                    _MK_SHIFT_CONST(20)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_FIELD                    (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_RANGE                    _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_READ_SHIFT                       _MK_SHIFT_CONST(19)
+#define I2C_IO_PACKET_HEADER_0_READ_FIELD                       (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_READ_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_READ_RANGE                       _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19)
+#define I2C_IO_PACKET_HEADER_0_READ_ROW                 2
+#define I2C_IO_PACKET_HEADER_0_READ_WRITE                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_READ_READ                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT                  _MK_SHIFT_CONST(18)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_FIELD                  (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_RANGE                  _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_ROW                    2
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SEVEN_BIT                      _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_TEN_BIT                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_IE_SHIFT                 _MK_SHIFT_CONST(17)
+#define I2C_IO_PACKET_HEADER_0_IE_FIELD                 (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_IE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_IE_RANGE                 _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17)
+#define I2C_IO_PACKET_HEADER_0_IE_ROW                   2
+#define I2C_IO_PACKET_HEADER_0_IE_DISABLE                       _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_IE_ENABLE                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT                       _MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_FIELD                       (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_RANGE                       _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_ROW                 2
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_STOP                        _MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_REPEAT_START                        _MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_SHIFT                        _MK_SHIFT_CONST(15)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_FIELD                        (_MK_MASK_CONST(0x1) << I2C_IO_PACKET_HEADER_0_RESERVED2_1_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_1_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT                     _MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_FIELD                     (_MK_MASK_CONST(0x7) << I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_ROW                       2
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT                        _MK_SHIFT_CONST(10)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_FIELD                        (_MK_MASK_CONST(0x3) << I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_FIELD                 (_MK_MASK_CONST(0x3ff) << I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_RANGE                 _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_ROW                   2
+
+
+// Register I2C_I2C_TX_PACKET_FIFO_0  
+#define I2C_I2C_TX_PACKET_FIFO_0                        _MK_ADDR_CONST(0x50)
+#define I2C_I2C_TX_PACKET_FIFO_0_SECURE                         0x0
+#define I2C_I2C_TX_PACKET_FIFO_0_WORD_COUNT                     0x1
+#define I2C_I2C_TX_PACKET_FIFO_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_TX_PACKET_FIFO_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+//SW writes packets into this register  
+//A packet may contain generic
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT                        _MK_SHIFT_CONST(0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_FIELD                        (_MK_MASK_CONST(0xffffffff) << I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_RANGE                        31:0
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_WOFFSET                      0x0
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT_MASK                 _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register I2C_I2C_RX_FIFO_0  
+#define I2C_I2C_RX_FIFO_0                       _MK_ADDR_CONST(0x54)
+#define I2C_I2C_RX_FIFO_0_SECURE                        0x0
+#define I2C_I2C_RX_FIFO_0_WORD_COUNT                    0x1
+#define I2C_I2C_RX_FIFO_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_RX_FIFO_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_RX_FIFO_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+//SW Reads data from this register,causes pop  
+#define I2C_I2C_RX_FIFO_0_RD_DATA_SHIFT                 _MK_SHIFT_CONST(0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_FIELD                 (_MK_MASK_CONST(0xffffffff) << I2C_I2C_RX_FIFO_0_RD_DATA_SHIFT)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_RANGE                 31:0
+#define I2C_I2C_RX_FIFO_0_RD_DATA_WOFFSET                       0x0
+#define I2C_I2C_RX_FIFO_0_RD_DATA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register I2C_PACKET_TRANSFER_STATUS_0  
+#define I2C_PACKET_TRANSFER_STATUS_0                    _MK_ADDR_CONST(0x58)
+#define I2C_PACKET_TRANSFER_STATUS_0_SECURE                     0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_WORD_COUNT                         0x1
+#define I2C_PACKET_TRANSFER_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x1ffffff)
+#define I2C_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1ffffff)
+#define I2C_PACKET_TRANSFER_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+//The packet transfer for which last packet is set has been
+//completed       
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT                    _MK_SHIFT_CONST(24)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_FIELD                    (_MK_MASK_CONST(0x1) << I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_RANGE                    24:24
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_WOFFSET                  0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_UNSET                    _MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SET                      _MK_ENUM_CONST(1)
+
+//The current packet id for which the transaction is 
+//happening on the bus
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT                      _MK_SHIFT_CONST(16)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_FIELD                      (_MK_MASK_CONST(0xff) << I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_RANGE                      23:16
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_WOFFSET                    0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//The number of bytes transferred in the current packet 
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT                     _MK_SHIFT_CONST(4)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_FIELD                     (_MK_MASK_CONST(0xfff) << I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_RANGE                     15:4
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_WOFFSET                   0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//No ack recieved for the addr byte
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT                       _MK_SHIFT_CONST(3)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_FIELD                       (_MK_MASK_CONST(0x1) << I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_RANGE                       3:3
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_WOFFSET                     0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_UNSET                       _MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SET                 _MK_ENUM_CONST(1)
+
+//No ack recieved for the data byte
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT                       _MK_SHIFT_CONST(2)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_FIELD                       (_MK_MASK_CONST(0x1) << I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_RANGE                       2:2
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_WOFFSET                     0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_UNSET                       _MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SET                 _MK_ENUM_CONST(1)
+
+//Arbitration lost for the current byte
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT                     _MK_SHIFT_CONST(1)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_FIELD                     (_MK_MASK_CONST(0x1) << I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_RANGE                     1:1
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_WOFFSET                   0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_UNSET                     _MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SET                       _MK_ENUM_CONST(1)
+
+//1 = Controller is busy
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT                      _MK_SHIFT_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_FIELD                      (_MK_MASK_CONST(0x1) << I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_RANGE                      0:0
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_WOFFSET                    0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_UNSET                      _MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SET                        _MK_ENUM_CONST(1)
+
+
+// Register I2C_FIFO_CONTROL_0  
+#define I2C_FIFO_CONTROL_0                      _MK_ADDR_CONST(0x5c)
+#define I2C_FIFO_CONTROL_0_SECURE                       0x0
+#define I2C_FIFO_CONTROL_0_WORD_COUNT                   0x1
+#define I2C_FIFO_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define I2C_FIFO_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define I2C_FIFO_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+//Transmit fifo trigger level 
+//000 = 1 word,  Dma trigger is asserted when 
+//at least one word empty in the fifo 
+//010 = 2 word,  Dma trigger is asserted when 
+//at least 2 words empty in the fifo 
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT                   _MK_SHIFT_CONST(5)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_FIELD                   (_MK_MASK_CONST(0x7) << I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_RANGE                   7:5
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_WOFFSET                 0x0
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//Receive fifo trigger level 
+//000 = 1 word  Dma trigger is asserted when 
+//at least one word full in the fifo 
+//010 = 2 word  Dma trigger is asserted when 
+//at least 2 word full in the fifo 
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT                   _MK_SHIFT_CONST(2)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_FIELD                   (_MK_MASK_CONST(0x7) << I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_RANGE                   4:2
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_WOFFSET                 0x0
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//1= flush the tx fifo,cleared after fifo is flushed
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT                  _MK_SHIFT_CONST(1)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_FIELD                  (_MK_MASK_CONST(0x1) << I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_RANGE                  1:1
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_WOFFSET                        0x0
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_UNSET                  _MK_ENUM_CONST(0)
+#define I2C_FIFO_CONTROL_0_TX_FIFO_FLUSH_SET                    _MK_ENUM_CONST(1)
+
+//1= flush the rx fifo,cleared after fifo is flushed 
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT                  _MK_SHIFT_CONST(0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_FIELD                  (_MK_MASK_CONST(0x1) << I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_RANGE                  0:0
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_WOFFSET                        0x0
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_UNSET                  _MK_ENUM_CONST(0)
+#define I2C_FIFO_CONTROL_0_RX_FIFO_FLUSH_SET                    _MK_ENUM_CONST(1)
+
+
+// Register I2C_FIFO_STATUS_0  
+#define I2C_FIFO_STATUS_0                       _MK_ADDR_CONST(0x60)
+#define I2C_FIFO_STATUS_0_SECURE                        0x0
+#define I2C_FIFO_STATUS_0_WORD_COUNT                    0x1
+#define I2C_FIFO_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define I2C_FIFO_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define I2C_FIFO_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+//The number of slots that can be written to the tx fifo
+//0000 = tx_fifo full
+//0001 = 1 slot empty 
+//0010 = 2 slots empty 
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT                       _MK_SHIFT_CONST(4)
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_FIELD                       (_MK_MASK_CONST(0xf) << I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT)
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_RANGE                       7:4
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_WOFFSET                     0x0
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//The number of slots to be read from  the rx fifo
+//0000 = rx_fifo empty
+//0001 = 1 slot  full
+//0010 = 2 slots  full
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_FIELD                        (_MK_MASK_CONST(0xf) << I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT)
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_RANGE                        3:0
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_WOFFSET                      0x0
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register I2C_INTERRUPT_MASK_REGISTER_0  
+#define I2C_INTERRUPT_MASK_REGISTER_0                   _MK_ADDR_CONST(0x64)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SECURE                    0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_WORD_COUNT                        0x1
+#define I2C_INTERRUPT_MASK_REGISTER_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RESET_MASK                        _MK_MASK_CONST(0x7f)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_READ_MASK                         _MK_MASK_CONST(0x7f)
+#define I2C_INTERRUPT_MASK_REGISTER_0_WRITE_MASK                        _MK_MASK_CONST(0x7f)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT                    _MK_SHIFT_CONST(6)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_RANGE                    6:6
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT                    _MK_SHIFT_CONST(5)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_RANGE                    5:5
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT                    _MK_SHIFT_CONST(4)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_RANGE                    4:4
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT                        _MK_SHIFT_CONST(3)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_RANGE                        3:3
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_WOFFSET                      0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_FIELD                     (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_RANGE                     2:2
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_WOFFSET                   0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT                       _MK_SHIFT_CONST(1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_RANGE                       1:1
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_RANGE                       0:0
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register I2C_INTERRUPT_STATUS_REGISTER_0  //This register indicates the status bit for which the interrupt is set.If set,Write 1 to clear it
+//However TFIFO_DATA_REQ,RFIFO_DATA_REQ fields depend on the fifo trigger levels and cannot be cleared.
+#define I2C_INTERRUPT_STATUS_REGISTER_0                 _MK_ADDR_CONST(0x68)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SECURE                  0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_WORD_COUNT                      0x1
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+//A packet has been transferred succesfully.
+//TRANSFER_PKT_ID filed can be used to know the 
+//current byte under transfer.This bit can be
+//masked by the IE field in the i2c specific header
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT                      _MK_SHIFT_CONST(7)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_FIELD                      (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_RANGE                      7:7
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_WOFFSET                    0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_UNSET                      _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SET                        _MK_ENUM_CONST(1)
+
+//All the packets transferred succesfully
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT                 _MK_SHIFT_CONST(6)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_FIELD                 (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_RANGE                 6:6
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_UNSET                 _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SET                   _MK_ENUM_CONST(1)
+
+//Tx fifo overflow
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT                 _MK_SHIFT_CONST(5)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_FIELD                 (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_RANGE                 5:5
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_UNSET                 _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SET                   _MK_ENUM_CONST(1)
+
+//rx fifo underflow
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT                 _MK_SHIFT_CONST(4)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_FIELD                 (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_RANGE                 4:4
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_UNSET                 _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SET                   _MK_ENUM_CONST(1)
+
+//No ACK from slave
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT                     _MK_SHIFT_CONST(3)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_FIELD                     (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_RANGE                     3:3
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_WOFFSET                   0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_UNSET                     _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SET                       _MK_ENUM_CONST(1)
+
+//Arbitration lost
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT                  _MK_SHIFT_CONST(2)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_FIELD                  (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_RANGE                  2:2
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_WOFFSET                        0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_UNSET                  _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SET                    _MK_ENUM_CONST(1)
+
+//Tx fifo data req
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT                    _MK_SHIFT_CONST(1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_FIELD                    (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_RANGE                    1:1
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_WOFFSET                  0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_UNSET                    _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SET                      _MK_ENUM_CONST(1)
+
+//rx fifo data req
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT                    _MK_SHIFT_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_FIELD                    (_MK_MASK_CONST(0x1) << I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_RANGE                    0:0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_WOFFSET                  0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_UNSET                    _MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SET                      _MK_ENUM_CONST(1)
+
+
+// Register I2C_I2C_CLK_DIVISOR_REGISTER_0  
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0                  _MK_ADDR_CONST(0x6c)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SECURE                   0x0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_WORD_COUNT                       0x1
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//N= divide by n+1
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT                     _MK_SHIFT_CONST(0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_FIELD                     (_MK_MASK_CONST(0xffff) << I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_RANGE                     15:0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_WOFFSET                   0x0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARI2C_REGS(_op_) \
+_op_(I2C_I2C_CNFG_0) \
+_op_(I2C_I2C_CMD_ADDR0_0) \
+_op_(I2C_I2C_CMD_ADDR1_0) \
+_op_(I2C_I2C_CMD_DATA1_0) \
+_op_(I2C_I2C_CMD_DATA2_0) \
+_op_(I2C_I2C_STATUS_0) \
+_op_(I2C_I2C_SL_CNFG_0) \
+_op_(I2C_I2C_SL_RCVD_0) \
+_op_(I2C_I2C_SL_STATUS_0) \
+_op_(I2C_I2C_SL_ADDR1_0) \
+_op_(I2C_I2C_SL_ADDR2_0) \
+_op_(I2C_I2C_SL_DELAY_COUNT_0) \
+_op_(I2C_I2C_TX_PACKET_FIFO_0) \
+_op_(I2C_I2C_RX_FIFO_0) \
+_op_(I2C_PACKET_TRANSFER_STATUS_0) \
+_op_(I2C_FIFO_CONTROL_0) \
+_op_(I2C_FIFO_STATUS_0) \
+_op_(I2C_INTERRUPT_MASK_REGISTER_0) \
+_op_(I2C_INTERRUPT_STATUS_REGISTER_0) \
+_op_(I2C_I2C_CLK_DIVISOR_REGISTER_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_I2C        0x00000000
+
+//
+// ARI2C REGISTER BANKS
+//
+
+#define I2C0_FIRST_REG 0x0000 // I2C_I2C_CNFG_0
+#define I2C0_LAST_REG 0x0010 // I2C_I2C_CMD_DATA2_0
+#define I2C1_FIRST_REG 0x001c // I2C_I2C_STATUS_0
+#define I2C1_LAST_REG 0x0030 // I2C_I2C_SL_ADDR2_0
+#define I2C2_FIRST_REG 0x003c // I2C_I2C_SL_DELAY_COUNT_0
+#define I2C2_LAST_REG 0x003c // I2C_I2C_SL_DELAY_COUNT_0
+#define I2C3_FIRST_REG 0x0050 // I2C_I2C_TX_PACKET_FIFO_0
+#define I2C3_LAST_REG 0x006c // I2C_I2C_CLK_DIVISOR_REGISTER_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARI2C_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/armc.h b/arch/arm/mach-tegra/nv/include/ap20/armc.h
new file mode 100644
index 000000000000..6db92de69f18
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/armc.h
@@ -0,0 +1,9705 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARMC_H_INC_
+#define ___ARMC_H_INC_
+
+// Register MC_INTSTATUS_0  
+#define MC_INTSTATUS_0                  _MK_ADDR_CONST(0x0)
+#define MC_INTSTATUS_0_SECURE                   0x0
+#define MC_INTSTATUS_0_WORD_COUNT                       0x1
+#define MC_INTSTATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_RESET_MASK                       _MK_MASK_CONST(0x1c0)
+#define MC_INTSTATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_READ_MASK                        _MK_MASK_CONST(0x1c0)
+#define MC_INTSTATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x1c0)
+// EMEM Address Decode Error for a non AXI client.
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_FIELD                     (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SHIFT)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_RANGE                     6:6
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_WOFFSET                   0x0
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_INIT_ENUM                 CLEAR
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_CLEAR                     _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_DECERR_EMEM_OTHERS_INT_SET                       _MK_ENUM_CONST(1)
+
+// A GART access was attepted to an invalid page.
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SHIFT                      _MK_SHIFT_CONST(7)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_FIELD                      (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SHIFT)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_RANGE                      7:7
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_WOFFSET                    0x0
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_INIT_ENUM                  CLEAR
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_CLEAR                      _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_INVALID_GART_PAGE_INT_SET                        _MK_ENUM_CONST(1)
+
+// A nonsecure access was attempted to a secured region.
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_FIELD                     (_MK_MASK_CONST(0x1) << MC_INTSTATUS_0_SECURITY_VIOLATION_INT_SHIFT)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_RANGE                     8:8
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_WOFFSET                   0x0
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_INIT_ENUM                 CLEAR
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_CLEAR                     _MK_ENUM_CONST(0)
+#define MC_INTSTATUS_0_SECURITY_VIOLATION_INT_SET                       _MK_ENUM_CONST(1)
+
+
+// Register MC_INTMASK_0  
+#define MC_INTMASK_0                    _MK_ADDR_CONST(0x4)
+#define MC_INTMASK_0_SECURE                     0x0
+#define MC_INTMASK_0_WORD_COUNT                         0x1
+#define MC_INTMASK_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_RESET_MASK                         _MK_MASK_CONST(0x1c0)
+#define MC_INTMASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_READ_MASK                  _MK_MASK_CONST(0x1c0)
+#define MC_INTMASK_0_WRITE_MASK                         _MK_MASK_CONST(0x1c0)
+// EMEM Address Decode Error for a non AXI client.
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_FIELD                   (_MK_MASK_CONST(0x1) << MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SHIFT)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_RANGE                   6:6
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_WOFFSET                 0x0
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_INIT_ENUM                       MASKED
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_MASKED                  _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_DECERR_EMEM_OTHERS_INTMASK_UNMASKED                        _MK_ENUM_CONST(1)
+
+// A GART access was attepted to an invalid page.
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_FIELD                    (_MK_MASK_CONST(0x1) << MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SHIFT)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_RANGE                    7:7
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_WOFFSET                  0x0
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_INIT_ENUM                        MASKED
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_MASKED                   _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_INVALID_GART_PAGE_INTMASK_UNMASKED                 _MK_ENUM_CONST(1)
+
+// A nonsecure access was attempted to a secured region.
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_FIELD                   (_MK_MASK_CONST(0x1) << MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_SHIFT)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_RANGE                   8:8
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_WOFFSET                 0x0
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_INIT_ENUM                       MASKED
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_MASKED                  _MK_ENUM_CONST(0)
+#define MC_INTMASK_0_SECURITY_VIOLATION_INTMASK_UNMASKED                        _MK_ENUM_CONST(1)
+
+
+// Reserved address 8 [0x8] 
+
+// Register MC_EMEM_CFG_0  
+#define MC_EMEM_CFG_0                   _MK_ADDR_CONST(0xc)
+#define MC_EMEM_CFG_0_SECURE                    0x0
+#define MC_EMEM_CFG_0_WORD_COUNT                        0x1
+#define MC_EMEM_CFG_0_RESET_VAL                         _MK_MASK_CONST(0x10000)
+#define MC_EMEM_CFG_0_RESET_MASK                        _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_READ_MASK                         _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_FIELD                        (_MK_MASK_CONST(0x3fffff) << MC_EMEM_CFG_0_EMEM_SIZE_KB_SHIFT)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_RANGE                        21:0
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_WOFFSET                      0x0
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_DEFAULT                      _MK_MASK_CONST(0x10000)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_DEFAULT_MASK                 _MK_MASK_CONST(0x3fffff)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_CFG_0_EMEM_SIZE_KB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_EMEM_ADR_CFG_0  
+#define MC_EMEM_ADR_CFG_0                       _MK_ADDR_CONST(0x10)
+#define MC_EMEM_ADR_CFG_0_SECURE                        0x0
+#define MC_EMEM_ADR_CFG_0_WORD_COUNT                    0x1
+#define MC_EMEM_ADR_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x40202)
+#define MC_EMEM_ADR_CFG_0_RESET_MASK                    _MK_MASK_CONST(0x30f0307)
+#define MC_EMEM_ADR_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_READ_MASK                     _MK_MASK_CONST(0x30f0307)
+#define MC_EMEM_ADR_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x30f0307)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_FIELD                   (_MK_MASK_CONST(0x7) << MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_RANGE                   2:0
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_WOFFSET                 0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT                 _MK_MASK_CONST(0x2)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_INIT_ENUM                       W9
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W7                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W8                      _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W9                      _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W10                     _MK_ENUM_CONST(3)
+#define MC_EMEM_ADR_CFG_0_EMEM_COLWIDTH_W11                     _MK_ENUM_CONST(4)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT                  _MK_SHIFT_CONST(8)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_FIELD                  (_MK_MASK_CONST(0x3) << MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_RANGE                  9:8
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_WOFFSET                        0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT                        _MK_MASK_CONST(0x2)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_INIT_ENUM                      W2
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W1                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W2                     _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_BANKWIDTH_W3                     _MK_ENUM_CONST(3)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SHIFT                    _MK_SHIFT_CONST(16)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_FIELD                    (_MK_MASK_CONST(0xf) << MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_RANGE                    19:16
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_WOFFSET                  0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_INIT_ENUM                        D64MB
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D4MB                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D8MB                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D16MB                    _MK_ENUM_CONST(2)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D32MB                    _MK_ENUM_CONST(3)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D64MB                    _MK_ENUM_CONST(4)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D128MB                   _MK_ENUM_CONST(5)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D256MB                   _MK_ENUM_CONST(6)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D512MB                   _MK_ENUM_CONST(7)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D1024MB                  _MK_ENUM_CONST(8)
+#define MC_EMEM_ADR_CFG_0_EMEM_DEVSIZE_D1GB                     _MK_ENUM_CONST(8)
+
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SHIFT                     _MK_SHIFT_CONST(24)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_FIELD                     (_MK_MASK_CONST(0x3) << MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SHIFT)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_RANGE                     25:24
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_WOFFSET                   0x0
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_INIT_ENUM                 N1
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_N1                        _MK_ENUM_CONST(0)
+#define MC_EMEM_ADR_CFG_0_EMEM_NUMDEV_N2                        _MK_ENUM_CONST(1)
+
+#define NV_MC_ARB_EMEM_SPMSB    5
+
+// Register MC_EMEM_ARB_CFG0_0  
+#define MC_EMEM_ARB_CFG0_0                      _MK_ADDR_CONST(0x14)
+#define MC_EMEM_ARB_CFG0_0_SECURE                       0x0
+#define MC_EMEM_ARB_CFG0_0_WORD_COUNT                   0x1
+#define MC_EMEM_ARB_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x102030)
+#define MC_EMEM_ARB_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x703fffff)
+#define MC_EMEM_ARB_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x703fffff)
+#define MC_EMEM_ARB_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x703fffff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_FIELD                  (_MK_MASK_CONST(0xff) << MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_RANGE                  7:0
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_DEFAULT                        _MK_MASK_CONST(0x30)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_RWCNT_TH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SHIFT                  _MK_SHIFT_CONST(8)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_FIELD                  (_MK_MASK_CONST(0xff) << MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_RANGE                  15:8
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_DEFAULT                        _MK_MASK_CONST(0x20)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_WRCNT_TH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_SHIFT                      _MK_SHIFT_CONST(16)
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_FIELD                      (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_RANGE                      21:16
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_DEFAULT                    _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_SP_MAX_GRANT_OVERALL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_RANGE                        28:28
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_INIT_ENUM                    DISABLE
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_SP_ON_AUTOPC_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SHIFT                       _MK_SHIFT_CONST(29)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_RANGE                       29:29
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_WOFFSET                     0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_INIT_ENUM                   DISABLE
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_CLEAR_AP_PREV_SPREQ_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_SHIFT                   _MK_SHIFT_CONST(30)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_FIELD                   (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_SHIFT)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_RANGE                   30:30
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_WOFFSET                 0x0
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_INIT_ENUM                       DISABLE
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG0_0_EMEM_NOBLOCK_BY_BANK_WHEN_HP_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register MC_EMEM_ARB_CFG1_0  
+#define MC_EMEM_ARB_CFG1_0                      _MK_ADDR_CONST(0x18)
+#define MC_EMEM_ARB_CFG1_0_SECURE                       0x0
+#define MC_EMEM_ARB_CFG1_0_WORD_COUNT                   0x1
+#define MC_EMEM_ARB_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x1010f7df)
+#define MC_EMEM_ARB_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0x3f3ff7df)
+#define MC_EMEM_ARB_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_READ_MASK                    _MK_MASK_CONST(0x3f3ff7df)
+#define MC_EMEM_ARB_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0x3f3ff7df)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_FIELD                  (_MK_MASK_CONST(0x1f) << MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_RANGE                  4:0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_DEFAULT                        _MK_MASK_CONST(0x1f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_INIT_ENUM                      ALL
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_NONE                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RCL_MASK_ALL                    _MK_ENUM_CONST(31)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SHIFT                  _MK_SHIFT_CONST(6)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_FIELD                  (_MK_MASK_CONST(0x1f) << MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_RANGE                  10:6
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_WOFFSET                        0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_DEFAULT                        _MK_MASK_CONST(0x1f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_INIT_ENUM                      ALL
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_NONE                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WCL_MASK_ALL                    _MK_ENUM_CONST(31)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_RANGE                        12:12
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_INIT_ENUM                    ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NORWSWITCH_BKBLOCK_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SHIFT                        _MK_SHIFT_CONST(13)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_FIELD                        (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_RANGE                        13:13
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_WOFFSET                      0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_INIT_ENUM                    ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_NOWRSWITCH_BKBLOCK_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SHIFT                      _MK_SHIFT_CONST(14)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_FIELD                      (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_RANGE                      14:14
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_INIT_ENUM                  ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_RWSWITCH_RWINEXPIRED_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_FIELD                      (_MK_MASK_CONST(0x1) << MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_RANGE                      15:15
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_INIT_ENUM                  ENABLE
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_WRSWITCH_WWINEXPIRED_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SHIFT                      _MK_SHIFT_CONST(16)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_FIELD                      (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RANGE                      21:16
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_WOFFSET                    0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_DEFAULT                    _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_SHIFT                   _MK_SHIFT_CONST(24)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_FIELD                   (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_SHIFT)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_RANGE                   29:24
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_WOFFSET                 0x0
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_DEFAULT                 _MK_MASK_CONST(0x10)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG1_0_EMEM_SP_MAX_GRANT_RW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_EMEM_ARB_CFG2_0  
+#define MC_EMEM_ARB_CFG2_0                      _MK_ADDR_CONST(0x1c)
+#define MC_EMEM_ARB_CFG2_0_SECURE                       0x0
+#define MC_EMEM_ARB_CFG2_0_WORD_COUNT                   0x1
+#define MC_EMEM_ARB_CFG2_0_RESET_VAL                    _MK_MASK_CONST(0xc080c08)
+#define MC_EMEM_ARB_CFG2_0_RESET_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
+#define MC_EMEM_ARB_CFG2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_READ_MASK                    _MK_MASK_CONST(0x3f3f3f3f)
+#define MC_EMEM_ARB_CFG2_0_WRITE_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_FIELD                     (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_SHIFT)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_RANGE                     5:0
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_WOFFSET                   0x0
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_DEFAULT                   _MK_MASK_CONST(0x8)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_RD_TH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_FIELD                 (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_SHIFT)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_RANGE                 13:8
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_WOFFSET                       0x0
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_DEFAULT                       _MK_MASK_CONST(0xc)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_RD_TH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_SHIFT                     _MK_SHIFT_CONST(16)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_FIELD                     (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_SHIFT)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_RANGE                     21:16
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_WOFFSET                   0x0
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_DEFAULT                   _MK_MASK_CONST(0x8)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_WR_TH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_SHIFT                 _MK_SHIFT_CONST(24)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_FIELD                 (_MK_MASK_CONST(0x3f) << MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_SHIFT)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_RANGE                 29:24
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_WOFFSET                       0x0
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_DEFAULT                       _MK_MASK_CONST(0xc)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_EMEM_ARB_CFG2_0_EMEM_BANKCNT_NSP_WR_TH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 32 [0x20] 
+
+// Register MC_GART_CONFIG_0  
+#define MC_GART_CONFIG_0                        _MK_ADDR_CONST(0x24)
+#define MC_GART_CONFIG_0_SECURE                         0x0
+#define MC_GART_CONFIG_0_WORD_COUNT                     0x1
+#define MC_GART_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_GART_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_GART_CONFIG_0_GART_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_GART_CONFIG_0_GART_ENABLE_SHIFT)
+#define MC_GART_CONFIG_0_GART_ENABLE_RANGE                      0:0
+#define MC_GART_CONFIG_0_GART_ENABLE_WOFFSET                    0x0
+#define MC_GART_CONFIG_0_GART_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_GART_CONFIG_0_GART_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_CONFIG_0_GART_ENABLE_INIT_ENUM                  DISABLE
+#define MC_GART_CONFIG_0_GART_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_GART_CONFIG_0_GART_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register MC_GART_ENTRY_ADDR_0  
+#define MC_GART_ENTRY_ADDR_0                    _MK_ADDR_CONST(0x28)
+#define MC_GART_ENTRY_ADDR_0_SECURE                     0x0
+#define MC_GART_ENTRY_ADDR_0_WORD_COUNT                         0x1
+#define MC_GART_ENTRY_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_READ_MASK                  _MK_MASK_CONST(0x1fff000)
+#define MC_GART_ENTRY_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff000)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_FIELD                   (_MK_MASK_CONST(0x1fff) << MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SHIFT)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_RANGE                   24:12
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_WOFFSET                 0x0
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_ADDR_0_GART_ENTRY_ADDR_TABLE_ADDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ENTRY_DATA_0  
+#define MC_GART_ENTRY_DATA_0                    _MK_ADDR_CONST(0x2c)
+#define MC_GART_ENTRY_DATA_0_SECURE                     0x0
+#define MC_GART_ENTRY_DATA_0_WORD_COUNT                         0x1
+#define MC_GART_ENTRY_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_READ_MASK                  _MK_MASK_CONST(0xfffff000)
+#define MC_GART_ENTRY_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff000)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_FIELD                      (_MK_MASK_CONST(0x1) << MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SHIFT)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_RANGE                      31:31
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_WOFFSET                    0x0
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_VALID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_FIELD                    (_MK_MASK_CONST(0x7ffff) << MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SHIFT)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_RANGE                    30:12
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_WOFFSET                  0x0
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_GART_ENTRY_DATA_0_GART_ENTRY_DATA_PHYS_ADDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ERROR_REQ_0  
+#define MC_GART_ERROR_REQ_0                     _MK_ADDR_CONST(0x30)
+#define MC_GART_ERROR_REQ_0_SECURE                      0x0
+#define MC_GART_ERROR_REQ_0_WORD_COUNT                  0x1
+#define MC_GART_ERROR_REQ_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_READ_MASK                   _MK_MASK_CONST(0x7f)
+#define MC_GART_ERROR_REQ_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SHIFT)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_RANGE                  0:0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_WOFFSET                        0x0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_READ                   _MK_ENUM_CONST(0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_DIRECTION_WRITE                  _MK_ENUM_CONST(1)
+
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SHIFT                  _MK_SHIFT_CONST(1)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_FIELD                  (_MK_MASK_CONST(0x3f) << MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SHIFT)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_RANGE                  6:1
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_WOFFSET                        0x0
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_REQ_0_GART_ERROR_CLIENT_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_GART_ERROR_ADDR_0  
+#define MC_GART_ERROR_ADDR_0                    _MK_ADDR_CONST(0x34)
+#define MC_GART_ERROR_ADDR_0_SECURE                     0x0
+#define MC_GART_ERROR_ADDR_0_WORD_COUNT                         0x1
+#define MC_GART_ERROR_ADDR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_GART_ERROR_ADDR_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SHIFT)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_RANGE                   31:0
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_WOFFSET                 0x0
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_GART_ERROR_ADDR_0_GART_ERROR_ADDRESS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 56 [0x38] 
+
+// Register MC_TIMEOUT_CTRL_0  
+#define MC_TIMEOUT_CTRL_0                       _MK_ADDR_CONST(0x3c)
+#define MC_TIMEOUT_CTRL_0_SECURE                        0x0
+#define MC_TIMEOUT_CTRL_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_CTRL_0_RESET_VAL                     _MK_MASK_CONST(0x28)
+#define MC_TIMEOUT_CTRL_0_RESET_MASK                    _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_READ_MASK                     _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x78)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SHIFT                 _MK_SHIFT_CONST(3)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_FIELD                 (_MK_MASK_CONST(0x7) << MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SHIFT)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_RANGE                 5:3
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_WOFFSET                       0x0
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_DEFAULT                       _MK_MASK_CONST(0x5)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_EMEM_TM_SFACTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_FIELD                       (_MK_MASK_CONST(0x1) << MC_TIMEOUT_CTRL_0_TMCREDITS_SHIFT)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_RANGE                       6:6
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_WOFFSET                     0x0
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_INIT_ENUM                   FROM_CIF_FIFO
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_FROM_CIF_FIFO                       _MK_ENUM_CONST(0)
+#define MC_TIMEOUT_CTRL_0_TMCREDITS_ONE                 _MK_ENUM_CONST(1)
+
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Register MC_DECERR_EMEM_OTHERS_STATUS_0  
+#define MC_DECERR_EMEM_OTHERS_STATUS_0                  _MK_ADDR_CONST(0x58)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_SECURE                   0x0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_WORD_COUNT                       0x1
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x8000003f)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_FIELD                      (_MK_MASK_CONST(0x3f) << MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_RANGE                      5:0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_WOFFSET                    0x0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_FIELD                      (_MK_MASK_CONST(0x1) << MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_RANGE                      31:31
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_WOFFSET                    0x0
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_READ                       _MK_ENUM_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_STATUS_0_DECERR_EMEM_OTHERS_RW_WRITE                      _MK_ENUM_CONST(1)
+
+
+// Register MC_DECERR_EMEM_OTHERS_ADR_0  
+#define MC_DECERR_EMEM_OTHERS_ADR_0                     _MK_ADDR_CONST(0x5c)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_SECURE                      0x0
+#define MC_DECERR_EMEM_OTHERS_ADR_0_WORD_COUNT                  0x1
+#define MC_DECERR_EMEM_OTHERS_ADR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SHIFT)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_RANGE                        31:0
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_WOFFSET                      0x0
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_DECERR_EMEM_OTHERS_ADR_0_DECERR_EMEM_OTHERS_ADR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 96 [0x60] 
+
+// Reserved address 100 [0x64] 
+
+// Register MC_CLKEN_OVERRIDE_0  
+#define MC_CLKEN_OVERRIDE_0                     _MK_ADDR_CONST(0x68)
+#define MC_CLKEN_OVERRIDE_0_SECURE                      0x0
+#define MC_CLKEN_OVERRIDE_0_WORD_COUNT                  0x1
+#define MC_CLKEN_OVERRIDE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_RESET_MASK                  _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_READ_MASK                   _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_WRITE_MASK                  _MK_MASK_CONST(0x1d)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_RANGE                 0:0
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_WOFFSET                       0x0
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_INIT_ENUM                     CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_CLK_GATED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_CLK_ALWAYS_ON                 _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_CIF_CLKEN_OVR_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_RANGE                        2:2
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_ESEQ_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(3)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_RANGE                        3:3
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_REGS_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SHIFT)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_RANGE                        4:4
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_WOFFSET                      0x0
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLKEN_OVERRIDE_0_GART_CLKEN_OVR_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Register MC_SECURITY_CFG0_0  
+#define MC_SECURITY_CFG0_0                      _MK_ADDR_CONST(0x6c)
+#define MC_SECURITY_CFG0_0_SECURE                       0x1
+#define MC_SECURITY_CFG0_0_WORD_COUNT                   0x1
+#define MC_SECURITY_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_SHIFT                   _MK_SHIFT_CONST(20)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_FIELD                   (_MK_MASK_CONST(0xfff) << MC_SECURITY_CFG0_0_SECURITY_BOM_SHIFT)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_RANGE                   31:20
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_WOFFSET                 0x0
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG0_0_SECURITY_BOM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_SECURITY_CFG1_0  
+#define MC_SECURITY_CFG1_0                      _MK_ADDR_CONST(0x70)
+#define MC_SECURITY_CFG1_0_SECURE                       0x1
+#define MC_SECURITY_CFG1_0_WORD_COUNT                   0x1
+#define MC_SECURITY_CFG1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG1_0_RESET_MASK                   _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG1_0_READ_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG1_0_WRITE_MASK                   _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_FIELD                       (_MK_MASK_CONST(0xfff) << MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_SHIFT)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_RANGE                       11:0
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_WOFFSET                     0x0
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_DEFAULT_MASK                        _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG1_0_SECURITY_SIZE_MB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_SECURITY_VIOLATION_STATUS_0  
+#define MC_SECURITY_VIOLATION_STATUS_0                  _MK_ADDR_CONST(0x74)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURE                   0x0
+#define MC_SECURITY_VIOLATION_STATUS_0_WORD_COUNT                       0x1
+#define MC_SECURITY_VIOLATION_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_READ_MASK                        _MK_MASK_CONST(0xc000003f)
+#define MC_SECURITY_VIOLATION_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_FIELD                      (_MK_MASK_CONST(0x3f) << MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_SHIFT)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_RANGE                      5:0
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_WOFFSET                    0x0
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_SHIFT                    _MK_SHIFT_CONST(30)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_FIELD                    (_MK_MASK_CONST(0x1) << MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_SHIFT)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_RANGE                    30:30
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_WOFFSET                  0x0
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_TRUSTZONE                        _MK_ENUM_CONST(0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_TYPE_CARVEOUT                 _MK_ENUM_CONST(1)
+
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_FIELD                      (_MK_MASK_CONST(0x1) << MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_SHIFT)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_RANGE                      31:31
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_WOFFSET                    0x0
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_READ                       _MK_ENUM_CONST(0)
+#define MC_SECURITY_VIOLATION_STATUS_0_SECURITY_VIOLATION_RW_WRITE                      _MK_ENUM_CONST(1)
+
+
+// Register MC_SECURITY_VIOLATION_ADR_0  
+#define MC_SECURITY_VIOLATION_ADR_0                     _MK_ADDR_CONST(0x78)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURE                      0x0
+#define MC_SECURITY_VIOLATION_ADR_0_WORD_COUNT                  0x1
+#define MC_SECURITY_VIOLATION_ADR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_SECURITY_VIOLATION_ADR_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_SHIFT)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_RANGE                        31:0
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_WOFFSET                      0x0
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_SECURITY_VIOLATION_ADR_0_SECURITY_VIOLATION_ADR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_SECURITY_CFG2_0  
+#define MC_SECURITY_CFG2_0                      _MK_ADDR_CONST(0x7c)
+#define MC_SECURITY_CFG2_0_SECURE                       0x1
+#define MC_SECURITY_CFG2_0_WORD_COUNT                   0x1
+#define MC_SECURITY_CFG2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG2_0_RESET_MASK                   _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG2_0_READ_MASK                    _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG2_0_WRITE_MASK                   _MK_MASK_CONST(0xfff00000)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_SHIFT                   _MK_SHIFT_CONST(20)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_FIELD                   (_MK_MASK_CONST(0xfff) << MC_SECURITY_CFG2_0_CARVEOUT_BOM_SHIFT)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_RANGE                   31:20
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_WOFFSET                 0x0
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_SECURITY_CFG2_0_CARVEOUT_BOM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Register MC_STAT_CONTROL_0  
+#define MC_STAT_CONTROL_0                       _MK_ADDR_CONST(0x90)
+#define MC_STAT_CONTROL_0_SECURE                        0x0
+#define MC_STAT_CONTROL_0_WORD_COUNT                    0x1
+#define MC_STAT_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x300)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_STAT_CONTROL_0_EMC_GATHER_FIELD                      (_MK_MASK_CONST(0x3) << MC_STAT_CONTROL_0_EMC_GATHER_SHIFT)
+#define MC_STAT_CONTROL_0_EMC_GATHER_RANGE                      9:8
+#define MC_STAT_CONTROL_0_EMC_GATHER_WOFFSET                    0x0
+#define MC_STAT_CONTROL_0_EMC_GATHER_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_INIT_ENUM                  RST
+#define MC_STAT_CONTROL_0_EMC_GATHER_RST                        _MK_ENUM_CONST(0)
+#define MC_STAT_CONTROL_0_EMC_GATHER_CLEAR                      _MK_ENUM_CONST(1)
+#define MC_STAT_CONTROL_0_EMC_GATHER_DISABLE                    _MK_ENUM_CONST(2)
+#define MC_STAT_CONTROL_0_EMC_GATHER_ENABLE                     _MK_ENUM_CONST(3)
+
+
+// Register MC_STAT_STATUS_0  
+#define MC_STAT_STATUS_0                        _MK_ADDR_CONST(0x94)
+#define MC_STAT_STATUS_0_SECURE                         0x0
+#define MC_STAT_STATUS_0_WORD_COUNT                     0x1
+#define MC_STAT_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_READ_MASK                      _MK_MASK_CONST(0x100)
+#define MC_STAT_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_STAT_STATUS_0_EMC_LIMIT_FIELD                        (_MK_MASK_CONST(0x1) << MC_STAT_STATUS_0_EMC_LIMIT_SHIFT)
+#define MC_STAT_STATUS_0_EMC_LIMIT_RANGE                        8:8
+#define MC_STAT_STATUS_0_EMC_LIMIT_WOFFSET                      0x0
+#define MC_STAT_STATUS_0_EMC_LIMIT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_STATUS_0_EMC_LIMIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_ADDR_LOW_0  
+#define MC_STAT_EMC_ADDR_LOW_0                  _MK_ADDR_CONST(0x98)
+#define MC_STAT_EMC_ADDR_LOW_0_SECURE                   0x0
+#define MC_STAT_EMC_ADDR_LOW_0_WORD_COUNT                       0x1
+#define MC_STAT_EMC_ADDR_LOW_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_RESET_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_READ_MASK                        _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_WRITE_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_FIELD                       (_MK_MASK_CONST(0x3ffffff) << MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SHIFT)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_RANGE                       29:4
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_WOFFSET                     0x0
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_DEFAULT_MASK                        _MK_MASK_CONST(0x3ffffff)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_LOW_0_EMC_ADDR_LOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_ADDR_HIGH_0  
+#define MC_STAT_EMC_ADDR_HIGH_0                 _MK_ADDR_CONST(0x9c)
+#define MC_STAT_EMC_ADDR_HIGH_0_SECURE                  0x0
+#define MC_STAT_EMC_ADDR_HIGH_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_ADDR_HIGH_0_RESET_VAL                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_RESET_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_READ_MASK                       _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_WRITE_MASK                      _MK_MASK_CONST(0x3ffffff0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_FIELD                     (_MK_MASK_CONST(0x3ffffff) << MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SHIFT)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_RANGE                     29:4
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_WOFFSET                   0x0
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_DEFAULT                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_DEFAULT_MASK                      _MK_MASK_CONST(0x3ffffff)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_ADDR_HIGH_0_EMC_ADDR_HIGH_INIT_ENUM                 -1
+
+
+// Register MC_STAT_EMC_CLOCK_LIMIT_0  
+#define MC_STAT_EMC_CLOCK_LIMIT_0                       _MK_ADDR_CONST(0xa0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_SECURE                        0x0
+#define MC_STAT_EMC_CLOCK_LIMIT_0_WORD_COUNT                    0x1
+#define MC_STAT_EMC_CLOCK_LIMIT_0_RESET_VAL                     _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SHIFT)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_RANGE                 31:0
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_WOFFSET                       0x0
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_DEFAULT                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCK_LIMIT_0_EMC_CLOCK_LIMIT_INIT_ENUM                     -1
+
+
+// Register MC_STAT_EMC_CLOCKS_0  
+#define MC_STAT_EMC_CLOCKS_0                    _MK_ADDR_CONST(0xa4)
+#define MC_STAT_EMC_CLOCKS_0_SECURE                     0x0
+#define MC_STAT_EMC_CLOCKS_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_CLOCKS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CLOCKS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SHIFT)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_RANGE                   31:0
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_WOFFSET                 0x0
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CLOCKS_0_EMC_CLOCKS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Packet ARMC_STAT_CONTROL
+#define ARMC_STAT_CONTROL_SIZE 32
+
+#define ARMC_STAT_CONTROL_MODE_SHIFT                    _MK_SHIFT_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_FIELD                    (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_MODE_SHIFT)
+#define ARMC_STAT_CONTROL_MODE_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_ROW                      0
+#define ARMC_STAT_CONTROL_MODE_BANDWIDTH                        _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_MODE_LATENCY_AVG                      _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_MODE_LATENCY_HISTO                    _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_SKIP_SHIFT                    _MK_SHIFT_CONST(4)
+#define ARMC_STAT_CONTROL_SKIP_FIELD                    (_MK_MASK_CONST(0x7) << ARMC_STAT_CONTROL_SKIP_SHIFT)
+#define ARMC_STAT_CONTROL_SKIP_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(4)
+#define ARMC_STAT_CONTROL_SKIP_ROW                      0
+
+#define ARMC_STAT_CONTROL_CLIENT_ID_SHIFT                       _MK_SHIFT_CONST(8)
+#define ARMC_STAT_CONTROL_CLIENT_ID_FIELD                       (_MK_MASK_CONST(0x3f) << ARMC_STAT_CONTROL_CLIENT_ID_SHIFT)
+#define ARMC_STAT_CONTROL_CLIENT_ID_RANGE                       _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(8)
+#define ARMC_STAT_CONTROL_CLIENT_ID_ROW                 0
+
+#define ARMC_STAT_CONTROL_EVENT_SHIFT                   _MK_SHIFT_CONST(16)
+#define ARMC_STAT_CONTROL_EVENT_FIELD                   (_MK_MASK_CONST(0xff) << ARMC_STAT_CONTROL_EVENT_SHIFT)
+#define ARMC_STAT_CONTROL_EVENT_RANGE                   _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define ARMC_STAT_CONTROL_EVENT_ROW                     0
+#define ARMC_STAT_CONTROL_EVENT_QUALIFIED                       _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_EVENT_ANY_READ                        _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_EVENT_ANY_WRITE                       _MK_ENUM_CONST(2)
+#define ARMC_STAT_CONTROL_EVENT_RD_WR_CHANGE                    _MK_ENUM_CONST(3)
+#define ARMC_STAT_CONTROL_EVENT_SUCCESSIVE                      _MK_ENUM_CONST(4)
+#define ARMC_STAT_CONTROL_EVENT_ARB_BANK_AA                     _MK_ENUM_CONST(5)
+#define ARMC_STAT_CONTROL_EVENT_ARB_BANK_BB                     _MK_ENUM_CONST(6)
+#define ARMC_STAT_CONTROL_EVENT_PAGE_MISS                       _MK_ENUM_CONST(7)
+#define ARMC_STAT_CONTROL_EVENT_AUTO_PRECHARGE                  _MK_ENUM_CONST(8)
+
+#define ARMC_STAT_CONTROL_PRI_EVENT_SHIFT                       _MK_SHIFT_CONST(24)
+#define ARMC_STAT_CONTROL_PRI_EVENT_FIELD                       (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_PRI_EVENT_SHIFT)
+#define ARMC_STAT_CONTROL_PRI_EVENT_RANGE                       _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(24)
+#define ARMC_STAT_CONTROL_PRI_EVENT_ROW                 0
+#define ARMC_STAT_CONTROL_PRI_EVENT_HP                  _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_PRI_EVENT_TM                  _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_PRI_EVENT_BW                  _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT                   _MK_SHIFT_CONST(26)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_FIELD                   (_MK_MASK_CONST(0x1) << ARMC_STAT_CONTROL_FILTER_CLIENT_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_RANGE                   _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_ROW                     0
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_DISABLE                 _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_CLIENT_ENABLE                  _MK_ENUM_CONST(1)
+
+#define ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT                     _MK_SHIFT_CONST(27)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_FIELD                     (_MK_MASK_CONST(0x1) << ARMC_STAT_CONTROL_FILTER_ADDR_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_ROW                       0
+#define ARMC_STAT_CONTROL_FILTER_ADDR_DISABLE                   _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_ADDR_ENABLE                    _MK_ENUM_CONST(1)
+
+#define ARMC_STAT_CONTROL_FILTER_PRI_SHIFT                      _MK_SHIFT_CONST(28)
+#define ARMC_STAT_CONTROL_FILTER_PRI_FIELD                      (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_FILTER_PRI_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_PRI_RANGE                      _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(28)
+#define ARMC_STAT_CONTROL_FILTER_PRI_ROW                        0
+#define ARMC_STAT_CONTROL_FILTER_PRI_DISABLE                    _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_PRI_NO                 _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_FILTER_PRI_YES                        _MK_ENUM_CONST(2)
+
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT                        _MK_SHIFT_CONST(30)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_FIELD                        (_MK_MASK_CONST(0x3) << ARMC_STAT_CONTROL_FILTER_COALESCED_SHIFT)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_ROW                  0
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_DISABLE                      _MK_ENUM_CONST(0)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_NO                   _MK_ENUM_CONST(1)
+#define ARMC_STAT_CONTROL_FILTER_COALESCED_YES                  _MK_ENUM_CONST(2)
+
+
+// Register MC_STAT_EMC_CONTROL_0_0  
+#define MC_STAT_EMC_CONTROL_0_0                 _MK_ADDR_CONST(0xa8)
+#define MC_STAT_EMC_CONTROL_0_0_SECURE                  0x0
+#define MC_STAT_EMC_CONTROL_0_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_CONTROL_0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SHIFT)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_RANGE                     31:0
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_WOFFSET                   0x0
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_0_0_EMC_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_CONTROL_1_0  
+#define MC_STAT_EMC_CONTROL_1_0                 _MK_ADDR_CONST(0xac)
+#define MC_STAT_EMC_CONTROL_1_0_SECURE                  0x0
+#define MC_STAT_EMC_CONTROL_1_0_WORD_COUNT                      0x1
+#define MC_STAT_EMC_CONTROL_1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_FIELD                     (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SHIFT)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_RANGE                     31:0
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_WOFFSET                   0x0
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_CONTROL_1_0_EMC_CONTROL_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Packet ARMC_STAT_HIST_LIMIT
+#define ARMC_STAT_HIST_LIMIT_SIZE 32
+
+#define ARMC_STAT_HIST_LIMIT_LOW_SHIFT                  _MK_SHIFT_CONST(0)
+#define ARMC_STAT_HIST_LIMIT_LOW_FIELD                  (_MK_MASK_CONST(0xffff) << ARMC_STAT_HIST_LIMIT_LOW_SHIFT)
+#define ARMC_STAT_HIST_LIMIT_LOW_RANGE                  _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define ARMC_STAT_HIST_LIMIT_LOW_ROW                    0
+
+#define ARMC_STAT_HIST_LIMIT_HIGH_SHIFT                 _MK_SHIFT_CONST(16)
+#define ARMC_STAT_HIST_LIMIT_HIGH_FIELD                 (_MK_MASK_CONST(0xffff) << ARMC_STAT_HIST_LIMIT_HIGH_SHIFT)
+#define ARMC_STAT_HIST_LIMIT_HIGH_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define ARMC_STAT_HIST_LIMIT_HIGH_ROW                   0
+
+
+// Register MC_STAT_EMC_HIST_LIMIT_0_0  
+#define MC_STAT_EMC_HIST_LIMIT_0_0                      _MK_ADDR_CONST(0xb0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_SECURE                       0x0
+#define MC_STAT_EMC_HIST_LIMIT_0_0_WORD_COUNT                   0x1
+#define MC_STAT_EMC_HIST_LIMIT_0_0_RESET_VAL                    _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_FIELD                       (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SHIFT)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_RANGE                       31:0
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_WOFFSET                     0x0
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_DEFAULT                     _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_0_0_EMC_HIST_LIMIT_0_INIT_ENUM                   -65536
+
+
+// Register MC_STAT_EMC_HIST_LIMIT_1_0  
+#define MC_STAT_EMC_HIST_LIMIT_1_0                      _MK_ADDR_CONST(0xb4)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_SECURE                       0x0
+#define MC_STAT_EMC_HIST_LIMIT_1_0_WORD_COUNT                   0x1
+#define MC_STAT_EMC_HIST_LIMIT_1_0_RESET_VAL                    _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_FIELD                       (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SHIFT)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_RANGE                       31:0
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_WOFFSET                     0x0
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_DEFAULT                     _MK_MASK_CONST(0xffff0000)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_LIMIT_1_0_EMC_HIST_LIMIT_1_INIT_ENUM                   -65536
+
+
+// Register MC_STAT_EMC_COUNT_0_0  
+#define MC_STAT_EMC_COUNT_0_0                   _MK_ADDR_CONST(0xb8)
+#define MC_STAT_EMC_COUNT_0_0_SECURE                    0x0
+#define MC_STAT_EMC_COUNT_0_0_WORD_COUNT                        0x1
+#define MC_STAT_EMC_COUNT_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_COUNT_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SHIFT)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_RANGE                 31:0
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_WOFFSET                       0x0
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_0_0_EMC_COUNT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_COUNT_1_0  
+#define MC_STAT_EMC_COUNT_1_0                   _MK_ADDR_CONST(0xbc)
+#define MC_STAT_EMC_COUNT_1_0_SECURE                    0x0
+#define MC_STAT_EMC_COUNT_1_0_WORD_COUNT                        0x1
+#define MC_STAT_EMC_COUNT_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_COUNT_1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_FIELD                 (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SHIFT)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_RANGE                 31:0
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_WOFFSET                       0x0
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_COUNT_1_0_EMC_COUNT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_HIST_0_0  
+#define MC_STAT_EMC_HIST_0_0                    _MK_ADDR_CONST(0xc0)
+#define MC_STAT_EMC_HIST_0_0_SECURE                     0x0
+#define MC_STAT_EMC_HIST_0_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_HIST_0_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SHIFT)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_RANGE                   31:0
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_WOFFSET                 0x0
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_0_0_EMC_HIST_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_STAT_EMC_HIST_1_0  
+#define MC_STAT_EMC_HIST_1_0                    _MK_ADDR_CONST(0xc4)
+#define MC_STAT_EMC_HIST_1_0_SECURE                     0x0
+#define MC_STAT_EMC_HIST_1_0_WORD_COUNT                         0x1
+#define MC_STAT_EMC_HIST_1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_STAT_EMC_HIST_1_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_FIELD                   (_MK_MASK_CONST(0xffffffff) << MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SHIFT)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_RANGE                   31:0
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_WOFFSET                 0x0
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_STAT_EMC_HIST_1_0_EMC_HIST_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_CLIENT_CTRL_DISABLE  0
+#define MC_CLIENT_CTRL_ENABLE   1
+
+// Register MC_CLIENT_CTRL_0  
+#define MC_CLIENT_CTRL_0                        _MK_ADDR_CONST(0x100)
+#define MC_CLIENT_CTRL_0_SECURE                         0x0
+#define MC_CLIENT_CTRL_0_WORD_COUNT                     0x1
+#define MC_CLIENT_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_READ_MASK                      _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_AVPC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_RANGE                      0:0
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_AVPC_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SHIFT                        _MK_SHIFT_CONST(1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_DC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_RANGE                        1:1
+#define MC_CLIENT_CTRL_0_DC_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DC_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_DCB_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_RANGE                       2:2
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_DCB_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_EPP_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_RANGE                       3:3
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_EPP_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_G2_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_RANGE                        4:4
+#define MC_CLIENT_CTRL_0_G2_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_G2_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_HC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_RANGE                        5:5
+#define MC_CLIENT_CTRL_0_HC_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_HC_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_ISP_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_RANGE                       6:6
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_ISP_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPCORE_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_RANGE                    7:7
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_WOFFSET                  0x0
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_INIT_ENUM                        ENABLE
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPCORE_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEA_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_RANGE                      8:8
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEA_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SHIFT                      _MK_SHIFT_CONST(9)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEB_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_RANGE                      9:9
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEB_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SHIFT                      _MK_SHIFT_CONST(10)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_MPEC_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_RANGE                      10:10
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_MPEC_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_NV_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_RANGE                        11:11
+#define MC_CLIENT_CTRL_0_NV_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_NV_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_PPCS_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_RANGE                      12:12
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_WOFFSET                    0x0
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_INIT_ENUM                  ENABLE
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_PPCS_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SHIFT                       _MK_SHIFT_CONST(13)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_VDE_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_RANGE                       13:13
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_WOFFSET                     0x0
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_INIT_ENUM                   ENABLE
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VDE_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_CTRL_0_VI_ENABLE_SHIFT)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_RANGE                        14:14
+#define MC_CLIENT_CTRL_0_VI_ENABLE_WOFFSET                      0x0
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_INIT_ENUM                    ENABLE
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_CTRL_0_VI_ENABLE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_DISABLE     1
+#define MC_CLIENT_HOTRESETN_ENABLE      0
+
+// Register MC_CLIENT_HOTRESETN_0  
+#define MC_CLIENT_HOTRESETN_0                   _MK_ADDR_CONST(0x104)
+#define MC_CLIENT_HOTRESETN_0_SECURE                    0x0
+#define MC_CLIENT_HOTRESETN_0_WORD_COUNT                        0x1
+#define MC_CLIENT_HOTRESETN_0_RESET_VAL                         _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_RESET_MASK                        _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_READ_MASK                         _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_WRITE_MASK                        _MK_MASK_CONST(0x7fff)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_RANGE                      0:0
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_AVPC_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_RANGE                        1:1
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DC_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_RANGE                       2:2
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_DCB_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_RANGE                       3:3
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_EPP_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_RANGE                        4:4
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_G2_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_RANGE                        5:5
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_HC_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_RANGE                       6:6
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_ISP_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_RANGE                    7:7
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_WOFFSET                  0x0
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_INIT_ENUM                        DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_ENABLE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DISABLE                  _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_ENABLED                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPCORE_HOTRESETN_DISABLED                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_RANGE                      8:8
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEA_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(9)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_RANGE                      9:9
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEB_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(10)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_RANGE                      10:10
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_MPEC_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_RANGE                        11:11
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_NV_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_RANGE                      12:12
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_WOFFSET                    0x0
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_INIT_ENUM                  DISABLE
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_ENABLE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DISABLE                    _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_ENABLED                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_PPCS_HOTRESETN_DISABLED                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SHIFT                       _MK_SHIFT_CONST(13)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_RANGE                       13:13
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_WOFFSET                     0x0
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_INIT_ENUM                   DISABLE
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_ENABLE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DISABLE                     _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_ENABLED                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VDE_HOTRESETN_DISABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SHIFT)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_RANGE                        14:14
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_WOFFSET                      0x0
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_INIT_ENUM                    DISABLE
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_ENABLE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DISABLE                      _MK_ENUM_CONST(1)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_ENABLED                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_HOTRESETN_0_VI_HOTRESETN_DISABLED                     _MK_ENUM_CONST(1)
+
+
+// Register MC_AXI_DECERR_OVR_0  
+#define MC_AXI_DECERR_OVR_0                     _MK_ADDR_CONST(0x108)
+#define MC_AXI_DECERR_OVR_0_SECURE                      0x0
+#define MC_AXI_DECERR_OVR_0_WORD_COUNT                  0x1
+#define MC_AXI_DECERR_OVR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define MC_AXI_DECERR_OVR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define MC_AXI_DECERR_OVR_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_RANGE                    0:0
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_WOFFSET                  0x0
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_INIT_ENUM                        DISABLE
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DECERR_ALLOWED                   _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ALWAYS_OK                        _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCORER_DECERR_OVR_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SHIFT                    _MK_SHIFT_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SHIFT)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_RANGE                    1:1
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_WOFFSET                  0x0
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_INIT_ENUM                        DISABLE
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DECERR_ALLOWED                   _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ALWAYS_OK                        _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AXI_DECERR_OVR_0_MPCOREW_DECERR_OVR_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_LL_CTRL_DISABLE       0
+#define MC_CLIENT_LL_CTRL_ENABLE        1
+
+// Register MC_LOWLATENCY_CONFIG_0  
+#define MC_LOWLATENCY_CONFIG_0                  _MK_ADDR_CONST(0x10c)
+#define MC_LOWLATENCY_CONFIG_0_SECURE                   0x0
+#define MC_LOWLATENCY_CONFIG_0_WORD_COUNT                       0x1
+#define MC_LOWLATENCY_CONFIG_0_RESET_VAL                        _MK_MASK_CONST(0x80000003)
+#define MC_LOWLATENCY_CONFIG_0_RESET_MASK                       _MK_MASK_CONST(0x80000003)
+#define MC_LOWLATENCY_CONFIG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_READ_MASK                        _MK_MASK_CONST(0x80000003)
+#define MC_LOWLATENCY_CONFIG_0_WRITE_MASK                       _MK_MASK_CONST(0x80000003)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_RANGE                    0:0
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_WOFFSET                  0x0
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_RANGE                       1:1
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_WOFFSET                     0x0
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SHIFT                 _MK_SHIFT_CONST(31)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_FIELD                 (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SHIFT)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_RANGE                 31:31
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_WOFFSET                       0x0
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_INIT_ENUM                     ENABLE
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0  
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0                     _MK_ADDR_CONST(0x110)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_SECURE                      0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_WORD_COUNT                  0x1
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_RESET_VAL                   _MK_MASK_CONST(0xfffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_WRITE_MASK                  _MK_MASK_CONST(0xfffff)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_RANGE                       0:0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPU_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_RANGE                       1:1
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPV_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_RANGE                       2:2
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_EPPY_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SHIFT                  _MK_SHIFT_CONST(3)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_FIELD                  (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_RANGE                  3:3
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_WOFFSET                        0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_INIT_ENUM                      ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPEUNIFBW_LL_RAW_PARTICIPATE_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_FIELD                      (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_RANGE                      4:4
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_WOFFSET                    0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_INIT_ENUM                  ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWSB_LL_RAW_PARTICIPATE_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(5)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_RANGE                       5:5
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWU_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_RANGE                       6:6
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWV_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(7)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_RANGE                       7:7
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VIWY_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_RANGE                       8:8
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_G2DW_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_SHIFT                  _MK_SHIFT_CONST(9)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_FIELD                  (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_RANGE                  9:9
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_WOFFSET                        0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_INIT_ENUM                      ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_AVPCARM7W_LL_RAW_PARTICIPATE_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SHIFT                     _MK_SHIFT_CONST(10)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_FIELD                     (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_RANGE                     10:10
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_WOFFSET                   0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_INIT_ENUM                 ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_FDCDWR_LL_RAW_PARTICIPATE_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_RANGE                    11:11
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_HOST1XW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_FIELD                       (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_RANGE                       12:12
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_WOFFSET                     0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_INIT_ENUM                   ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_ISPW_LL_RAW_PARTICIPATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(13)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_RANGE                    13:13
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPCOREW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(14)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_RANGE                    14:14
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_MPECSWR_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SHIFT                        _MK_SHIFT_CONST(15)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_FIELD                        (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_RANGE                        15:15
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_WOFFSET                      0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_INIT_ENUM                    ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBDMAW_LL_RAW_PARTICIPATE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_FIELD                        (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_RANGE                        16:16
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_WOFFSET                      0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_INIT_ENUM                    ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_PPCSAHBSLVW_LL_RAW_PARTICIPATE_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SHIFT                   _MK_SHIFT_CONST(17)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_FIELD                   (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_RANGE                   17:17
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_WOFFSET                 0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_INIT_ENUM                       ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEBSEVW_LL_RAW_PARTICIPATE_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(18)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_RANGE                    18:18
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDEMBEW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SHIFT                    _MK_SHIFT_CONST(19)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_FIELD                    (_MK_MASK_CONST(0x1) << MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SHIFT)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_RANGE                    19:19
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_WOFFSET                  0x0
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_INIT_ENUM                        ENABLE
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0_VDETPMW_LL_RAW_PARTICIPATE_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_BWSHARE_DISABLE       0
+#define MC_CLIENT_BWSHARE_ENABLE        1
+
+// Register MC_BWSHARE_TMVAL_0  
+#define MC_BWSHARE_TMVAL_0                      _MK_ADDR_CONST(0x114)
+#define MC_BWSHARE_TMVAL_0_SECURE                       0x0
+#define MC_BWSHARE_TMVAL_0_WORD_COUNT                   0x1
+#define MC_BWSHARE_TMVAL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_FIELD                 (_MK_MASK_CONST(0xf) << MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SHIFT)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_RANGE                 3:0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_WOFFSET                       0x0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_FIELD                 (_MK_MASK_CONST(0xf) << MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SHIFT)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_RANGE                 7:4
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_WOFFSET                       0x0
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_TMVAL_0_BW_TM_SFACTOR2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Register MC_BWSHARE_EMEM_CTRL_0_0  
+#define MC_BWSHARE_EMEM_CTRL_0_0                        _MK_ADDR_CONST(0x120)
+#define MC_BWSHARE_EMEM_CTRL_0_0_SECURE                         0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EMEM_CTRL_0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_RANGE                        0:0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0A_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_RANGE                       1:1
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0AB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_RANGE                        2:2
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0B_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_RANGE                       3:3
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0BB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_RANGE                        4:4
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0C_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(5)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_RANGE                       5:5
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY0CB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(6)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_RANGE                        6:6
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1B_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(7)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_RANGE                       7:7
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAY1BB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_RANGE                    8:8
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_EPPUP_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(9)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_RANGE                     9:9
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2PR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(10)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_RANGE                     10:10
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2SR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_RANGE                        11:11
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEUNIFBR_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_RANGE                    12:12
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VIRUV_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(13)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_RANGE                        13:13
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_AVPCARM7R_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(14)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_RANGE                        14:14
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHC_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(15)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_RANGE                       15:15
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_DISPLAYHCB_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_RANGE                   16:16
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_FDCDRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(17)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_RANGE                     17:17
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_G2DR_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SHIFT                       _MK_SHIFT_CONST(18)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_RANGE                       18:18
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_WOFFSET                     0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XDMAR_BW_EMEM_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_RANGE                  19:19
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_HOST1XR_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(20)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_RANGE                   20:20
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_IDXSRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(21)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_RANGE                  21:21
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPCORER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(22)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_RANGE                        22:22
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPE_IPRED_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(23)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_RANGE                        23:23
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPEAMEMRD_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(24)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_RANGE                  24:24
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_MPECSRD_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(25)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_RANGE                      25:25
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBDMAR_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(26)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_RANGE                      26:26
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_PPCSAHBSLVR_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_RANGE                   27:27
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_TEXSRD_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_RANGE                 28:28
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEBSEVR_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(29)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_RANGE                  29:29
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMBER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(30)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_RANGE                  30:30
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDEMCER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(31)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_RANGE                  31:31
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_0_0_VDETPER_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_EMEM_CTRL_1_0  
+#define MC_BWSHARE_EMEM_CTRL_1_0                        _MK_ADDR_CONST(0x124)
+#define MC_BWSHARE_EMEM_CTRL_1_0_SECURE                         0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EMEM_CTRL_1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_RANGE                     0:0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPU_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_RANGE                     1:1
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPV_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(2)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_RANGE                     2:2
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_EPPY_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(3)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_RANGE                        3:3
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPEUNIFBW_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_RANGE                    4:4
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_WOFFSET                  0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_INIT_ENUM                        DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWSB_BW_EMEM_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(5)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_RANGE                     5:5
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWU_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_RANGE                     6:6
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWV_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(7)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_RANGE                     7:7
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VIWY_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_RANGE                     8:8
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_G2DW_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_SHIFT                        _MK_SHIFT_CONST(9)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_RANGE                        9:9
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_WOFFSET                      0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_INIT_ENUM                    DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_AVPCARM7W_BW_EMEM_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SHIFT                   _MK_SHIFT_CONST(10)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_RANGE                   10:10
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_WOFFSET                 0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_FDCDWR_BW_EMEM_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_RANGE                  11:11
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_HOST1XW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SHIFT                     _MK_SHIFT_CONST(12)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_FIELD                     (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_RANGE                     12:12
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_WOFFSET                   0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_INIT_ENUM                 DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_ISPW_BW_EMEM_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(13)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_RANGE                  13:13
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPCOREW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(14)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_RANGE                  14:14
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_MPECSWR_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_RANGE                      15:15
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBDMAW_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SHIFT                      _MK_SHIFT_CONST(16)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_RANGE                      16:16
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_WOFFSET                    0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_INIT_ENUM                  DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_PPCSAHBSLVW_BW_EMEM_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SHIFT                 _MK_SHIFT_CONST(17)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_RANGE                 17:17
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_WOFFSET                       0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEBSEVW_BW_EMEM_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(18)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_RANGE                  18:18
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDEMBEW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SHIFT                  _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_FIELD                  (_MK_MASK_CONST(0x1) << MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SHIFT)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_RANGE                  19:19
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_WOFFSET                        0x0
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_INIT_ENUM                      DISABLE
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EMEM_CTRL_1_0_VDETPMW_BW_EMEM_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_AP_CTRL_DISABLE       0
+#define MC_CLIENT_AP_CTRL_ENABLE        1
+
+// Register MC_AP_CTRL_0_0  
+#define MC_AP_CTRL_0_0                  _MK_ADDR_CONST(0x128)
+#define MC_AP_CTRL_0_0_SECURE                   0x0
+#define MC_AP_CTRL_0_0_WORD_COUNT                       0x1
+#define MC_AP_CTRL_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_RANGE                    0:0
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0A_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_RANGE                   1:1
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0AB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_RANGE                    2:2
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0B_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SHIFT                   _MK_SHIFT_CONST(3)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_RANGE                   3:3
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0BB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_RANGE                    4:4
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0C_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SHIFT                   _MK_SHIFT_CONST(5)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_RANGE                   5:5
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY0CB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_RANGE                    6:6
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1B_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SHIFT                   _MK_SHIFT_CONST(7)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_RANGE                   7:7
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAY1BB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_EPPUP_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_RANGE                        8:8
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_EPPUP_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SHIFT                 _MK_SHIFT_CONST(9)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2PR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_RANGE                 9:9
+#define MC_AP_CTRL_0_0_G2PR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2PR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SHIFT                 _MK_SHIFT_CONST(10)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2SR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_RANGE                 10:10
+#define MC_AP_CTRL_0_0_G2SR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2SR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_RANGE                    11:11
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEUNIFBR_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VIRUV_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_RANGE                        12:12
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VIRUV_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_SHIFT                    _MK_SHIFT_CONST(13)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_AVPCARM7R_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_RANGE                    13:13
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_AVPCARM7R_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SHIFT                    _MK_SHIFT_CONST(14)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_RANGE                    14:14
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHC_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SHIFT                   _MK_SHIFT_CONST(15)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_RANGE                   15:15
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_DISPLAYHCB_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SHIFT                       _MK_SHIFT_CONST(16)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_FDCDRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_RANGE                       16:16
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_FDCDRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SHIFT                 _MK_SHIFT_CONST(17)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_G2DR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_RANGE                 17:17
+#define MC_AP_CTRL_0_0_G2DR_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_G2DR_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SHIFT                   _MK_SHIFT_CONST(18)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_FIELD                   (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_RANGE                   18:18
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_WOFFSET                 0x0
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_INIT_ENUM                       DISABLE
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XDMAR_APVAL_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SHIFT                      _MK_SHIFT_CONST(19)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_HOST1XR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_RANGE                      19:19
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_HOST1XR_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SHIFT                       _MK_SHIFT_CONST(20)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_IDXSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_RANGE                       20:20
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_IDXSRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SHIFT                      _MK_SHIFT_CONST(21)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPCORER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_RANGE                      21:21
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPCORER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SHIFT                    _MK_SHIFT_CONST(22)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_RANGE                    22:22
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPE_IPRED_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SHIFT                    _MK_SHIFT_CONST(23)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_RANGE                    23:23
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPEAMEMRD_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SHIFT                      _MK_SHIFT_CONST(24)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_MPECSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_RANGE                      24:24
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_MPECSRD_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SHIFT                  _MK_SHIFT_CONST(25)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_RANGE                  25:25
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBDMAR_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SHIFT                  _MK_SHIFT_CONST(26)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_RANGE                  26:26
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_PPCSAHBSLVR_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_TEXSRD_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_RANGE                       27:27
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_TEXSRD_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SHIFT                     _MK_SHIFT_CONST(28)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_RANGE                     28:28
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEBSEVR_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SHIFT                      _MK_SHIFT_CONST(29)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEMBER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_RANGE                      29:29
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMBER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_SHIFT                      _MK_SHIFT_CONST(30)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDEMCER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_RANGE                      30:30
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDEMCER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_SHIFT                      _MK_SHIFT_CONST(31)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_0_0_VDETPER_APVAL_SHIFT)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_RANGE                      31:31
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_0_0_VDETPER_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+
+// Register MC_AP_CTRL_1_0  
+#define MC_AP_CTRL_1_0                  _MK_ADDR_CONST(0x12c)
+#define MC_AP_CTRL_1_0_SECURE                   0x0
+#define MC_AP_CTRL_1_0_WORD_COUNT                       0x1
+#define MC_AP_CTRL_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_RESET_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_AP_CTRL_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_READ_MASK                        _MK_MASK_CONST(0xfffff)
+#define MC_AP_CTRL_1_0_WRITE_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPU_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_RANGE                 0:0
+#define MC_AP_CTRL_1_0_EPPU_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPU_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SHIFT                 _MK_SHIFT_CONST(1)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPV_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_RANGE                 1:1
+#define MC_AP_CTRL_1_0_EPPV_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPV_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SHIFT                 _MK_SHIFT_CONST(2)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_EPPY_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_RANGE                 2:2
+#define MC_AP_CTRL_1_0_EPPY_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_EPPY_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SHIFT                    _MK_SHIFT_CONST(3)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_RANGE                    3:3
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPEUNIFBW_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_FIELD                        (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWSB_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_RANGE                        4:4
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_WOFFSET                      0x0
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_INIT_ENUM                    DISABLE
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWSB_APVAL_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SHIFT                 _MK_SHIFT_CONST(5)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWU_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_RANGE                 5:5
+#define MC_AP_CTRL_1_0_VIWU_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWU_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SHIFT                 _MK_SHIFT_CONST(6)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWV_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_RANGE                 6:6
+#define MC_AP_CTRL_1_0_VIWV_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWV_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SHIFT                 _MK_SHIFT_CONST(7)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VIWY_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_RANGE                 7:7
+#define MC_AP_CTRL_1_0_VIWY_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VIWY_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_G2DW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_RANGE                 8:8
+#define MC_AP_CTRL_1_0_G2DW_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_G2DW_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_SHIFT                    _MK_SHIFT_CONST(9)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_FIELD                    (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_AVPCARM7W_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_RANGE                    9:9
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_WOFFSET                  0x0
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_INIT_ENUM                        DISABLE
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_DISABLE                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_ENABLE                   _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_DISABLED                 _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_AVPCARM7W_APVAL_ENABLED                  _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SHIFT                       _MK_SHIFT_CONST(10)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_FIELD                       (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_FDCDWR_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_RANGE                       10:10
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_WOFFSET                     0x0
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_INIT_ENUM                   DISABLE
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_FDCDWR_APVAL_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_HOST1XW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_RANGE                      11:11
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_HOST1XW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SHIFT                 _MK_SHIFT_CONST(12)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_FIELD                 (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_ISPW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_RANGE                 12:12
+#define MC_AP_CTRL_1_0_ISPW_APVAL_WOFFSET                       0x0
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_INIT_ENUM                     DISABLE
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_ISPW_APVAL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SHIFT                      _MK_SHIFT_CONST(13)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPCOREW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_RANGE                      13:13
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPCOREW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SHIFT                      _MK_SHIFT_CONST(14)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_MPECSWR_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_RANGE                      14:14
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_MPECSWR_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SHIFT                  _MK_SHIFT_CONST(15)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_RANGE                  15:15
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBDMAW_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SHIFT                  _MK_SHIFT_CONST(16)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_FIELD                  (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_RANGE                  16:16
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_WOFFSET                        0x0
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_INIT_ENUM                      DISABLE
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_PPCSAHBSLVW_APVAL_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SHIFT                     _MK_SHIFT_CONST(17)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_FIELD                     (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_RANGE                     17:17
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_WOFFSET                   0x0
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_INIT_ENUM                 DISABLE
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DISABLE                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_ENABLE                    _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_DISABLED                  _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEBSEVW_APVAL_ENABLED                   _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SHIFT                      _MK_SHIFT_CONST(18)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDEMBEW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_RANGE                      18:18
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDEMBEW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SHIFT                      _MK_SHIFT_CONST(19)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_FIELD                      (_MK_MASK_CONST(0x1) << MC_AP_CTRL_1_0_VDETPMW_APVAL_SHIFT)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_RANGE                      19:19
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_WOFFSET                    0x0
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_INIT_ENUM                  DISABLE
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_ENABLE                     _MK_ENUM_CONST(1)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_DISABLED                   _MK_ENUM_CONST(0)
+#define MC_AP_CTRL_1_0_VDETPMW_APVAL_ENABLED                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_INACTIVE     0
+#define MC_CLIENT_ACTIVITY_MONITOR_ACTIVE       1
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Register MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0  
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0                     _MK_ADDR_CONST(0x138)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_SECURE                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_WORD_COUNT                  0x1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_RANGE                       0:0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0A_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_RANGE                      1:1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0AB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(2)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_RANGE                       2:2
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0B_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(3)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_RANGE                      3:3
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0BB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_RANGE                       4:4
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0C_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(5)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_RANGE                      5:5
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY0CB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(6)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_RANGE                       6:6
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1B_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(7)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_RANGE                      7:7
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAY1BB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_RANGE                   8:8
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_EPPUP_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(9)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_RANGE                    9:9
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2PR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(10)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_RANGE                    10:10
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2SR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(11)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_RANGE                       11:11
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEUNIFBR_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_RANGE                   12:12
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VIRUV_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(13)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_RANGE                       13:13
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_AVPCARM7R_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(14)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_RANGE                       14:14
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHC_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(15)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_RANGE                      15:15
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_DISPLAYHCB_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(16)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_RANGE                  16:16
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_FDCDRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(17)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_RANGE                    17:17
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_G2DR_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SHIFT                      _MK_SHIFT_CONST(18)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_FIELD                      (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_RANGE                      18:18
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_WOFFSET                    0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_INIT_ENUM                  DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_INACTIVE                   _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XDMAR_EMEM_ACTIVITY_ACTIVE                     _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(19)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_RANGE                 19:19
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_HOST1XR_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(20)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_RANGE                  20:20
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_IDXSRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(21)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_RANGE                 21:21
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPCORER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(22)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_RANGE                       22:22
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPE_IPRED_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(23)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_RANGE                       23:23
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPEAMEMRD_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(24)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_RANGE                 24:24
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_MPECSRD_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(25)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_RANGE                     25:25
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBDMAR_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(26)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_RANGE                     26:26
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_PPCSAHBSLVR_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(27)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_RANGE                  27:27
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_TEXSRD_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_RANGE                        28:28
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEBSEVR_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(29)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_RANGE                 29:29
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMBER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(30)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_RANGE                 30:30
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDEMCER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(31)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_RANGE                 31:31
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0_VDETPER_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+
+// Register MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0  
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0                     _MK_ADDR_CONST(0x13c)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_SECURE                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_WORD_COUNT                  0x1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_RESET_MASK                  _MK_MASK_CONST(0xfffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_READ_MASK                   _MK_MASK_CONST(0xfffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_WRITE_MASK                  _MK_MASK_CONST(0xfffff)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_RANGE                    0:0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPU_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_RANGE                    1:1
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPV_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_RANGE                    2:2
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_EPPY_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(3)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_RANGE                       3:3
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPEUNIFBW_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_FIELD                   (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_RANGE                   4:4
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_WOFFSET                 0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_INIT_ENUM                       DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_INACTIVE                        _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWSB_EMEM_ACTIVITY_ACTIVE                  _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(5)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_RANGE                    5:5
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWU_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_RANGE                    6:6
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWV_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(7)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_RANGE                    7:7
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VIWY_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_RANGE                    8:8
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_G2DW_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_SHIFT                       _MK_SHIFT_CONST(9)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_FIELD                       (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_RANGE                       9:9
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_WOFFSET                     0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_INIT_ENUM                   DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_INACTIVE                    _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_AVPCARM7W_EMEM_ACTIVITY_ACTIVE                      _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SHIFT                  _MK_SHIFT_CONST(10)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_FIELD                  (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_RANGE                  10:10
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_WOFFSET                        0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_INIT_ENUM                      DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_INACTIVE                       _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_FDCDWR_EMEM_ACTIVITY_ACTIVE                 _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(11)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_RANGE                 11:11
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_HOST1XW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_FIELD                    (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_RANGE                    12:12
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_WOFFSET                  0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_INIT_ENUM                        DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_INACTIVE                 _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_ISPW_EMEM_ACTIVITY_ACTIVE                   _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(13)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_RANGE                 13:13
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPCOREW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(14)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_RANGE                 14:14
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_MPECSWR_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(15)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_RANGE                     15:15
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBDMAW_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SHIFT                     _MK_SHIFT_CONST(16)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_FIELD                     (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_RANGE                     16:16
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_WOFFSET                   0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_INIT_ENUM                 DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_INACTIVE                  _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_PPCSAHBSLVW_EMEM_ACTIVITY_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SHIFT                        _MK_SHIFT_CONST(17)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_FIELD                        (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_RANGE                        17:17
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_WOFFSET                      0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_INIT_ENUM                    DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_INACTIVE                     _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEBSEVW_EMEM_ACTIVITY_ACTIVE                       _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(18)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_RANGE                 18:18
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDEMBEW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SHIFT                 _MK_SHIFT_CONST(19)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_FIELD                 (_MK_MASK_CONST(0x1) << MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SHIFT)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_RANGE                 19:19
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_WOFFSET                       0x0
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_INIT_ENUM                     DISABLE
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_INACTIVE                      _MK_ENUM_CONST(0)
+#define MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0_VDETPMW_EMEM_ACTIVITY_ACTIVE                        _MK_ENUM_CONST(1)
+
+
+// Register MC_AVPC_ORRC_0  
+#define MC_AVPC_ORRC_0                  _MK_ADDR_CONST(0x140)
+#define MC_AVPC_ORRC_0_SECURE                   0x0
+#define MC_AVPC_ORRC_0_WORD_COUNT                       0x1
+#define MC_AVPC_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_AVPC_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_AVPC_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_AVPC_ORRC_0_AVPC_OUTREQCNT_SHIFT)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_RANGE                     7:0
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_WOFFSET                   0x0
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_AVPC_ORRC_0_AVPC_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_DC_ORRC_0  
+#define MC_DC_ORRC_0                    _MK_ADDR_CONST(0x144)
+#define MC_DC_ORRC_0_SECURE                     0x0
+#define MC_DC_ORRC_0_WORD_COUNT                         0x1
+#define MC_DC_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_DC_ORRC_0_DC_OUTREQCNT_SHIFT)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_RANGE                 7:0
+#define MC_DC_ORRC_0_DC_OUTREQCNT_WOFFSET                       0x0
+#define MC_DC_ORRC_0_DC_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_DC_ORRC_0_DC_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_DCB_ORRC_0  
+#define MC_DCB_ORRC_0                   _MK_ADDR_CONST(0x148)
+#define MC_DCB_ORRC_0_SECURE                    0x0
+#define MC_DCB_ORRC_0_WORD_COUNT                        0x1
+#define MC_DCB_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_DCB_ORRC_0_DCB_OUTREQCNT_SHIFT)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_RANGE                       7:0
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_WOFFSET                     0x0
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_DCB_ORRC_0_DCB_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_EPP_ORRC_0  
+#define MC_EPP_ORRC_0                   _MK_ADDR_CONST(0x14c)
+#define MC_EPP_ORRC_0_SECURE                    0x0
+#define MC_EPP_ORRC_0_WORD_COUNT                        0x1
+#define MC_EPP_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_EPP_ORRC_0_EPP_OUTREQCNT_SHIFT)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_RANGE                       7:0
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_WOFFSET                     0x0
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_EPP_ORRC_0_EPP_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_G2_ORRC_0  
+#define MC_G2_ORRC_0                    _MK_ADDR_CONST(0x150)
+#define MC_G2_ORRC_0_SECURE                     0x0
+#define MC_G2_ORRC_0_WORD_COUNT                         0x1
+#define MC_G2_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_G2_ORRC_0_G2_OUTREQCNT_SHIFT)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_RANGE                 7:0
+#define MC_G2_ORRC_0_G2_OUTREQCNT_WOFFSET                       0x0
+#define MC_G2_ORRC_0_G2_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_G2_ORRC_0_G2_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_HC_ORRC_0  
+#define MC_HC_ORRC_0                    _MK_ADDR_CONST(0x154)
+#define MC_HC_ORRC_0_SECURE                     0x0
+#define MC_HC_ORRC_0_WORD_COUNT                         0x1
+#define MC_HC_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_HC_ORRC_0_HC_OUTREQCNT_SHIFT)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_RANGE                 7:0
+#define MC_HC_ORRC_0_HC_OUTREQCNT_WOFFSET                       0x0
+#define MC_HC_ORRC_0_HC_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_HC_ORRC_0_HC_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_ISP_ORRC_0  
+#define MC_ISP_ORRC_0                   _MK_ADDR_CONST(0x158)
+#define MC_ISP_ORRC_0_SECURE                    0x0
+#define MC_ISP_ORRC_0_WORD_COUNT                        0x1
+#define MC_ISP_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_ISP_ORRC_0_ISP_OUTREQCNT_SHIFT)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_RANGE                       7:0
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_WOFFSET                     0x0
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_ISP_ORRC_0_ISP_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPCORE_ORRC_0  
+#define MC_MPCORE_ORRC_0                        _MK_ADDR_CONST(0x15c)
+#define MC_MPCORE_ORRC_0_SECURE                         0x0
+#define MC_MPCORE_ORRC_0_WORD_COUNT                     0x1
+#define MC_MPCORE_ORRC_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_RESET_MASK                     _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SHIFT)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_RANGE                 7:0
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_WOFFSET                       0x0
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_MPCORE_ORRC_0_MPCORE_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEA_ORRC_0  
+#define MC_MPEA_ORRC_0                  _MK_ADDR_CONST(0x160)
+#define MC_MPEA_ORRC_0_SECURE                   0x0
+#define MC_MPEA_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEA_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SHIFT)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_RANGE                     7:0
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEA_ORRC_0_MPEA_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEB_ORRC_0  
+#define MC_MPEB_ORRC_0                  _MK_ADDR_CONST(0x164)
+#define MC_MPEB_ORRC_0_SECURE                   0x0
+#define MC_MPEB_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEB_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SHIFT)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_RANGE                     7:0
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEB_ORRC_0_MPEB_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_MPEC_ORRC_0  
+#define MC_MPEC_ORRC_0                  _MK_ADDR_CONST(0x168)
+#define MC_MPEC_ORRC_0_SECURE                   0x0
+#define MC_MPEC_ORRC_0_WORD_COUNT                       0x1
+#define MC_MPEC_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SHIFT)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_RANGE                     7:0
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_WOFFSET                   0x0
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_MPEC_ORRC_0_MPEC_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_NV_ORRC_0  
+#define MC_NV_ORRC_0                    _MK_ADDR_CONST(0x16c)
+#define MC_NV_ORRC_0_SECURE                     0x0
+#define MC_NV_ORRC_0_WORD_COUNT                         0x1
+#define MC_NV_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_NV_ORRC_0_NV_OUTREQCNT_SHIFT)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_RANGE                 7:0
+#define MC_NV_ORRC_0_NV_OUTREQCNT_WOFFSET                       0x0
+#define MC_NV_ORRC_0_NV_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_NV_ORRC_0_NV_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_PPCS_ORRC_0  
+#define MC_PPCS_ORRC_0                  _MK_ADDR_CONST(0x170)
+#define MC_PPCS_ORRC_0_SECURE                   0x0
+#define MC_PPCS_ORRC_0_WORD_COUNT                       0x1
+#define MC_PPCS_ORRC_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_FIELD                     (_MK_MASK_CONST(0xff) << MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SHIFT)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_RANGE                     7:0
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_WOFFSET                   0x0
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_PPCS_ORRC_0_PPCS_OUTREQCNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_VDE_ORRC_0  
+#define MC_VDE_ORRC_0                   _MK_ADDR_CONST(0x174)
+#define MC_VDE_ORRC_0_SECURE                    0x0
+#define MC_VDE_ORRC_0_WORD_COUNT                        0x1
+#define MC_VDE_ORRC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_FIELD                       (_MK_MASK_CONST(0xff) << MC_VDE_ORRC_0_VDE_OUTREQCNT_SHIFT)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_RANGE                       7:0
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_WOFFSET                     0x0
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_VDE_ORRC_0_VDE_OUTREQCNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_VI_ORRC_0  
+#define MC_VI_ORRC_0                    _MK_ADDR_CONST(0x178)
+#define MC_VI_ORRC_0_SECURE                     0x0
+#define MC_VI_ORRC_0_WORD_COUNT                         0x1
+#define MC_VI_ORRC_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_FIELD                 (_MK_MASK_CONST(0xff) << MC_VI_ORRC_0_VI_OUTREQCNT_SHIFT)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_RANGE                 7:0
+#define MC_VI_ORRC_0_VI_OUTREQCNT_WOFFSET                       0x0
+#define MC_VI_ORRC_0_VI_OUTREQCNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_VI_ORRC_0_VI_OUTREQCNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_FPRI_CTRL_AVPC_0  
+#define MC_FPRI_CTRL_AVPC_0                     _MK_ADDR_CONST(0x17c)
+#define MC_FPRI_CTRL_AVPC_0_SECURE                      0x0
+#define MC_FPRI_CTRL_AVPC_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_AVPC_0_RESET_VAL                   _MK_MASK_CONST(0x5)
+#define MC_FPRI_CTRL_AVPC_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_AVPC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_AVPC_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7R_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_AVPC_0_AVPCARM7W_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_DC_0  
+#define MC_FPRI_CTRL_DC_0                       _MK_ADDR_CONST(0x180)
+#define MC_FPRI_CTRL_DC_0_SECURE                        0x0
+#define MC_FPRI_CTRL_DC_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_DC_0_RESET_VAL                     _MK_MASK_CONST(0x155)
+#define MC_FPRI_CTRL_DC_0_RESET_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_READ_MASK                     _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_WRITE_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0A_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_RANGE                        3:2
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0B_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_RANGE                        5:4
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY0C_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SHIFT                        _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_RANGE                        7:6
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAY1B_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_RANGE                        9:8
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DC_0_DISPLAYHC_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_DCB_0  
+#define MC_FPRI_CTRL_DCB_0                      _MK_ADDR_CONST(0x184)
+#define MC_FPRI_CTRL_DCB_0_SECURE                       0x0
+#define MC_FPRI_CTRL_DCB_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_DCB_0_RESET_VAL                    _MK_MASK_CONST(0x155)
+#define MC_FPRI_CTRL_DCB_0_RESET_MASK                   _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_READ_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_WRITE_MASK                   _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0AB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0BB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_RANGE                      5:4
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY0CB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_RANGE                      7:6
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAY1BB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_RANGE                      9:8
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_DCB_0_DISPLAYHCB_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_EPP_0  
+#define MC_FPRI_CTRL_EPP_0                      _MK_ADDR_CONST(0x188)
+#define MC_FPRI_CTRL_EPP_0_SECURE                       0x0
+#define MC_FPRI_CTRL_EPP_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_EPP_0_RESET_VAL                    _MK_MASK_CONST(0x55)
+#define MC_FPRI_CTRL_EPP_0_RESET_MASK                   _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_READ_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_WRITE_MASK                   _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_RANGE                   1:0
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_INIT_ENUM                       LOW
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPUP_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPU_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_RANGE                    5:4
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPV_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_RANGE                    7:6
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_EPP_0_EPPY_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_G2_0  
+#define MC_FPRI_CTRL_G2_0                       _MK_ADDR_CONST(0x18c)
+#define MC_FPRI_CTRL_G2_0_SECURE                        0x0
+#define MC_FPRI_CTRL_G2_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_G2_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_RANGE                     1:0
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2PR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_RANGE                     3:2
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2SR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_RANGE                     5:4
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2DR_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_RANGE                     7:6
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_INIT_ENUM                 LOWEST
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_G2_0_G2DW_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_HC_0  
+#define MC_FPRI_CTRL_HC_0                       _MK_ADDR_CONST(0x190)
+#define MC_FPRI_CTRL_HC_0_SECURE                        0x0
+#define MC_FPRI_CTRL_HC_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_HC_0_RESET_VAL                     _MK_MASK_CONST(0x15)
+#define MC_FPRI_CTRL_HC_0_RESET_MASK                    _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_READ_MASK                     _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_WRITE_MASK                    _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_FIELD                       (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_RANGE                       1:0
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_WOFFSET                     0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_INIT_ENUM                   LOW
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_LOWEST                      _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_LOW                 _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_MED                 _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XDMAR_PRIVAL_HIGH                        _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SHIFT                  _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_FIELD                  (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_RANGE                  3:2
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_WOFFSET                        0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_INIT_ENUM                      LOW
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_LOWEST                 _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_LOW                    _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_MED                    _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XR_PRIVAL_HIGH                   _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SHIFT                  _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_FIELD                  (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_RANGE                  5:4
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_WOFFSET                        0x0
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_INIT_ENUM                      LOW
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_LOWEST                 _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_LOW                    _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_MED                    _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_HC_0_HOST1XW_PRIVAL_HIGH                   _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_ISP_0  
+#define MC_FPRI_CTRL_ISP_0                      _MK_ADDR_CONST(0x194)
+#define MC_FPRI_CTRL_ISP_0_SECURE                       0x0
+#define MC_FPRI_CTRL_ISP_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_ISP_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_ISP_0_RESET_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_READ_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_ISP_0_ISPW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPCORE_0  
+#define MC_FPRI_CTRL_MPCORE_0                   _MK_ADDR_CONST(0x198)
+#define MC_FPRI_CTRL_MPCORE_0_SECURE                    0x0
+#define MC_FPRI_CTRL_MPCORE_0_WORD_COUNT                        0x1
+#define MC_FPRI_CTRL_MPCORE_0_RESET_VAL                         _MK_MASK_CONST(0x5)
+#define MC_FPRI_CTRL_MPCORE_0_RESET_MASK                        _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCORER_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPCORE_0_MPCOREW_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEA_0  
+#define MC_FPRI_CTRL_MPEA_0                     _MK_ADDR_CONST(0x19c)
+#define MC_FPRI_CTRL_MPEA_0_SECURE                      0x0
+#define MC_FPRI_CTRL_MPEA_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEA_0_RESET_VAL                   _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEA_0_RESET_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_READ_MASK                   _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_WRITE_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEA_0_MPEAMEMRD_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEB_0  
+#define MC_FPRI_CTRL_MPEB_0                     _MK_ADDR_CONST(0x1a0)
+#define MC_FPRI_CTRL_MPEB_0_SECURE                      0x0
+#define MC_FPRI_CTRL_MPEB_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEB_0_RESET_VAL                   _MK_MASK_CONST(0x15)
+#define MC_FPRI_CTRL_MPEB_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_READ_MASK                   _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_WRITE_MASK                  _MK_MASK_CONST(0x3f)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_RANGE                      1:0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBR_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SHIFT                      _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_RANGE                      3:2
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPE_IPRED_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_FIELD                      (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_RANGE                      5:4
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_WOFFSET                    0x0
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_INIT_ENUM                  LOW
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_LOWEST                     _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_LOW                        _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_MED                        _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEB_0_MPEUNIFBW_PRIVAL_HIGH                       _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_MPEC_0  
+#define MC_FPRI_CTRL_MPEC_0                     _MK_ADDR_CONST(0x1a4)
+#define MC_FPRI_CTRL_MPEC_0_SECURE                      0x0
+#define MC_FPRI_CTRL_MPEC_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_MPEC_0_RESET_VAL                   _MK_MASK_CONST(0x5)
+#define MC_FPRI_CTRL_MPEC_0_RESET_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_READ_MASK                   _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_WRITE_MASK                  _MK_MASK_CONST(0xf)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSRD_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SHIFT                        _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_RANGE                        3:2
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_MPEC_0_MPECSWR_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_NV_0  
+#define MC_FPRI_CTRL_NV_0                       _MK_ADDR_CONST(0x1a8)
+#define MC_FPRI_CTRL_NV_0_SECURE                        0x0
+#define MC_FPRI_CTRL_NV_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_NV_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_RANGE                   1:0
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_FDCDRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_RANGE                   3:2
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_IDXSRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_RANGE                   5:4
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_TEXSRD_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_FIELD                   (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_RANGE                   7:6
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_WOFFSET                 0x0
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_INIT_ENUM                       LOWEST
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_LOWEST                  _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_LOW                     _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_MED                     _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_NV_0_FDCDWR_PRIVAL_HIGH                    _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_PPCS_0  
+#define MC_FPRI_CTRL_PPCS_0                     _MK_ADDR_CONST(0x1ac)
+#define MC_FPRI_CTRL_PPCS_0_SECURE                      0x0
+#define MC_FPRI_CTRL_PPCS_0_WORD_COUNT                  0x1
+#define MC_FPRI_CTRL_PPCS_0_RESET_VAL                   _MK_MASK_CONST(0x55)
+#define MC_FPRI_CTRL_PPCS_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_PPCS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_PPCS_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAR_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVR_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_RANGE                    5:4
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBDMAW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SHIFT                    _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_RANGE                    7:6
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_PPCS_0_PPCSAHBSLVW_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_VDE_0  
+#define MC_FPRI_CTRL_VDE_0                      _MK_ADDR_CONST(0x1b0)
+#define MC_FPRI_CTRL_VDE_0_SECURE                       0x0
+#define MC_FPRI_CTRL_VDE_0_WORD_COUNT                   0x1
+#define MC_FPRI_CTRL_VDE_0_RESET_VAL                    _MK_MASK_CONST(0x1555)
+#define MC_FPRI_CTRL_VDE_0_RESET_MASK                   _MK_MASK_CONST(0x3fff)
+#define MC_FPRI_CTRL_VDE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_READ_MASK                    _MK_MASK_CONST(0x3fff)
+#define MC_FPRI_CTRL_VDE_0_WRITE_MASK                   _MK_MASK_CONST(0x3fff)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_RANGE                        1:0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVR_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_RANGE                 3:2
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_INIT_ENUM                     LOW
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMBER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_RANGE                 5:4
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_INIT_ENUM                     LOW
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMCER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SHIFT                 _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_RANGE                 7:6
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_INIT_ENUM                     LOW
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDETPER_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_FIELD                        (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_RANGE                        9:8
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_WOFFSET                      0x0
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_INIT_ENUM                    LOW
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_LOWEST                       _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_LOW                  _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_MED                  _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEBSEVW_PRIVAL_HIGH                 _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SHIFT                 _MK_SHIFT_CONST(10)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_RANGE                 11:10
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_INIT_ENUM                     LOW
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDEMBEW_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SHIFT                 _MK_SHIFT_CONST(12)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_FIELD                 (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_RANGE                 13:12
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_WOFFSET                       0x0
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_DEFAULT                       _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_INIT_ENUM                     LOW
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_LOWEST                        _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_LOW                   _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_MED                   _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VDE_0_VDETPMW_PRIVAL_HIGH                  _MK_ENUM_CONST(3)
+
+
+// Register MC_FPRI_CTRL_VI_0  
+#define MC_FPRI_CTRL_VI_0                       _MK_ADDR_CONST(0x1b4)
+#define MC_FPRI_CTRL_VI_0_SECURE                        0x0
+#define MC_FPRI_CTRL_VI_0_WORD_COUNT                    0x1
+#define MC_FPRI_CTRL_VI_0_RESET_VAL                     _MK_MASK_CONST(0x155)
+#define MC_FPRI_CTRL_VI_0_RESET_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_READ_MASK                     _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_WRITE_MASK                    _MK_MASK_CONST(0x3ff)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_RANGE                    1:0
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIRUV_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SHIFT                    _MK_SHIFT_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_FIELD                    (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_RANGE                    3:2
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_WOFFSET                  0x0
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_INIT_ENUM                        LOW
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_LOWEST                   _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_LOW                      _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_MED                      _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWSB_PRIVAL_HIGH                     _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_RANGE                     5:4
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_INIT_ENUM                 LOW
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWU_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SHIFT                     _MK_SHIFT_CONST(6)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_RANGE                     7:6
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_INIT_ENUM                 LOW
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWV_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_FIELD                     (_MK_MASK_CONST(0x3) << MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SHIFT)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_RANGE                     9:8
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_WOFFSET                   0x0
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_DEFAULT                   _MK_MASK_CONST(0x1)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_INIT_ENUM                 LOW
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_LOWEST                    _MK_ENUM_CONST(0)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_LOW                       _MK_ENUM_CONST(1)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_MED                       _MK_ENUM_CONST(2)
+#define MC_FPRI_CTRL_VI_0_VIWY_PRIVAL_HIGH                      _MK_ENUM_CONST(3)
+
+
+// Register MC_TIMEOUT_AVPC_0  
+#define MC_TIMEOUT_AVPC_0                       _MK_ADDR_CONST(0x1b8)
+#define MC_TIMEOUT_AVPC_0_SECURE                        0x0
+#define MC_TIMEOUT_AVPC_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_AVPC_0_RESET_VAL                     _MK_MASK_CONST(0x88)
+#define MC_TIMEOUT_AVPC_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_AVPC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_AVPC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_AVPC_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_AVPC_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_SHIFT)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7R_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_SHIFT)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_AVPC_0_AVPCARM7W_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_DC_0  
+#define MC_TIMEOUT_DC_0                 _MK_ADDR_CONST(0x1bc)
+#define MC_TIMEOUT_DC_0_SECURE                  0x0
+#define MC_TIMEOUT_DC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_DC_0_RESET_VAL                       _MK_MASK_CONST(0x88888)
+#define MC_TIMEOUT_DC_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0A_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0B_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_RANGE                   11:8
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY0C_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SHIFT                   _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_RANGE                   15:12
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAY1B_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SHIFT)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_RANGE                   19:16
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DC_0_DISPLAYHC_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_DCB_0  
+#define MC_TIMEOUT_DCB_0                        _MK_ADDR_CONST(0x1c0)
+#define MC_TIMEOUT_DCB_0_SECURE                         0x0
+#define MC_TIMEOUT_DCB_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_DCB_0_RESET_VAL                      _MK_MASK_CONST(0x88888)
+#define MC_TIMEOUT_DCB_0_RESET_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0AB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0BB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_RANGE                 11:8
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY0CB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SHIFT                 _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_RANGE                 15:12
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAY1BB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SHIFT                 _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SHIFT)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_RANGE                 19:16
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_DCB_0_DISPLAYHCB_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_EPP_0  
+#define MC_TIMEOUT_EPP_0                        _MK_ADDR_CONST(0x1c4)
+#define MC_TIMEOUT_EPP_0_SECURE                         0x0
+#define MC_TIMEOUT_EPP_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_EPP_0_RESET_VAL                      _MK_MASK_CONST(0x8888)
+#define MC_TIMEOUT_EPP_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_RANGE                      3:0
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_DEFAULT                    _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPUP_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPU_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPU_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPV_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_RANGE                       11:8
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPV_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_EPP_0_EPPY_TMVAL_SHIFT)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_RANGE                       15:12
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_EPP_0_EPPY_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_G2_0  
+#define MC_TIMEOUT_G2_0                 _MK_ADDR_CONST(0x1c8)
+#define MC_TIMEOUT_G2_0_SECURE                  0x0
+#define MC_TIMEOUT_G2_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_G2_0_RESET_VAL                       _MK_MASK_CONST(0x8888)
+#define MC_TIMEOUT_G2_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2PR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_RANGE                        3:0
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2PR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SHIFT                        _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2SR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_RANGE                        7:4
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2SR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2DR_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_RANGE                        11:8
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DR_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_G2_0_G2DW_TMVAL_SHIFT)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_RANGE                        15:12
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_G2_0_G2DW_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_HC_0  
+#define MC_TIMEOUT_HC_0                 _MK_ADDR_CONST(0x1cc)
+#define MC_TIMEOUT_HC_0_SECURE                  0x0
+#define MC_TIMEOUT_HC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_HC_0_RESET_VAL                       _MK_MASK_CONST(0x888)
+#define MC_TIMEOUT_HC_0_RESET_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_READ_MASK                       _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_WRITE_MASK                      _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_FIELD                  (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_RANGE                  3:0
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_DEFAULT                        _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XDMAR_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SHIFT                     _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_RANGE                     7:4
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XR_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_FIELD                     (_MK_MASK_CONST(0xf) << MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SHIFT)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_RANGE                     11:8
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_DEFAULT                   _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_HC_0_HOST1XW_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_ISP_0  
+#define MC_TIMEOUT_ISP_0                        _MK_ADDR_CONST(0x1d0)
+#define MC_TIMEOUT_ISP_0_SECURE                         0x0
+#define MC_TIMEOUT_ISP_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_ISP_0_RESET_VAL                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_ISP_0_RESET_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_READ_MASK                      _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_ISP_0_ISPW_TMVAL_SHIFT)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_ISP_0_ISPW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPCORE_0  
+#define MC_TIMEOUT_MPCORE_0                     _MK_ADDR_CONST(0x1d4)
+#define MC_TIMEOUT_MPCORE_0_SECURE                      0x0
+#define MC_TIMEOUT_MPCORE_0_WORD_COUNT                  0x1
+#define MC_TIMEOUT_MPCORE_0_RESET_VAL                   _MK_MASK_CONST(0x88)
+#define MC_TIMEOUT_MPCORE_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCORER_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPCORE_0_MPCOREW_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEA_0  
+#define MC_TIMEOUT_MPEA_0                       _MK_ADDR_CONST(0x1d8)
+#define MC_TIMEOUT_MPEA_0_SECURE                        0x0
+#define MC_TIMEOUT_MPEA_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEA_0_RESET_VAL                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEA_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_WRITE_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEA_0_MPEAMEMRD_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEB_0  
+#define MC_TIMEOUT_MPEB_0                       _MK_ADDR_CONST(0x1dc)
+#define MC_TIMEOUT_MPEB_0_SECURE                        0x0
+#define MC_TIMEOUT_MPEB_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEB_0_RESET_VAL                     _MK_MASK_CONST(0x888)
+#define MC_TIMEOUT_MPEB_0_RESET_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_READ_MASK                     _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_WRITE_MASK                    _MK_MASK_CONST(0xfff)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_RANGE                 3:0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBR_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SHIFT                 _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_RANGE                 7:4
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPE_IPRED_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_FIELD                 (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_RANGE                 11:8
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEB_0_MPEUNIFBW_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_MPEC_0  
+#define MC_TIMEOUT_MPEC_0                       _MK_ADDR_CONST(0x1e0)
+#define MC_TIMEOUT_MPEC_0_SECURE                        0x0
+#define MC_TIMEOUT_MPEC_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_MPEC_0_RESET_VAL                     _MK_MASK_CONST(0x88)
+#define MC_TIMEOUT_MPEC_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSRD_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SHIFT)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_RANGE                   7:4
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_DEFAULT                 _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_MPEC_0_MPECSWR_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_NV_0  
+#define MC_TIMEOUT_NV_0                 _MK_ADDR_CONST(0x1e4)
+#define MC_TIMEOUT_NV_0_SECURE                  0x0
+#define MC_TIMEOUT_NV_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_NV_0_RESET_VAL                       _MK_MASK_CONST(0x8888)
+#define MC_TIMEOUT_NV_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_RANGE                      3:0
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_RANGE                      7:4
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_IDXSRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SHIFT                      _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_RANGE                      11:8
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_DEFAULT                    _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_TEXSRD_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SHIFT                      _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_FIELD                      (_MK_MASK_CONST(0xf) << MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SHIFT)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_RANGE                      15:12
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_DEFAULT                    _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_NV_0_FDCDWR_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_PPCS_0  
+#define MC_TIMEOUT_PPCS_0                       _MK_ADDR_CONST(0x1e8)
+#define MC_TIMEOUT_PPCS_0_SECURE                        0x0
+#define MC_TIMEOUT_PPCS_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_PPCS_0_RESET_VAL                     _MK_MASK_CONST(0x8888)
+#define MC_TIMEOUT_PPCS_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_PPCS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_PPCS_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAR_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVR_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_RANGE                       11:8
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBDMAW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SHIFT)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_RANGE                       15:12
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_PPCS_0_PPCSAHBSLVW_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_VDE_0  
+#define MC_TIMEOUT_VDE_0                        _MK_ADDR_CONST(0x1ec)
+#define MC_TIMEOUT_VDE_0_SECURE                         0x0
+#define MC_TIMEOUT_VDE_0_WORD_COUNT                     0x1
+#define MC_TIMEOUT_VDE_0_RESET_VAL                      _MK_MASK_CONST(0x4444444)
+#define MC_TIMEOUT_VDE_0_RESET_MASK                     _MK_MASK_CONST(0xfffffff)
+#define MC_TIMEOUT_VDE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_READ_MASK                      _MK_MASK_CONST(0xfffffff)
+#define MC_TIMEOUT_VDE_0_WRITE_MASK                     _MK_MASK_CONST(0xfffffff)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_RANGE                   3:0
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_DEFAULT                 _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVR_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SHIFT                    _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_RANGE                    7:4
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_RANGE                    11:8
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMCER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SHIFT                    _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_RANGE                    15:12
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDETPER_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_FIELD                   (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_RANGE                   19:16
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_DEFAULT                 _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEBSEVW_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SHIFT                    _MK_SHIFT_CONST(20)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_RANGE                    23:20
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDEMBEW_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_SHIFT                    _MK_SHIFT_CONST(24)
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_FIELD                    (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_SHIFT)
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_RANGE                    27:24
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VDE_0_VDETPMW_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_VI_0  
+#define MC_TIMEOUT_VI_0                 _MK_ADDR_CONST(0x1f0)
+#define MC_TIMEOUT_VI_0_SECURE                  0x0
+#define MC_TIMEOUT_VI_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_VI_0_RESET_VAL                       _MK_MASK_CONST(0x88888)
+#define MC_TIMEOUT_VI_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIRUV_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_RANGE                       3:0
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIRUV_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SHIFT                       _MK_SHIFT_CONST(4)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_FIELD                       (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWSB_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_RANGE                       7:4
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_DEFAULT                     _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWSB_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWU_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_RANGE                        11:8
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWU_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SHIFT                        _MK_SHIFT_CONST(12)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWV_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_RANGE                        15:12
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWV_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_FIELD                        (_MK_MASK_CONST(0xf) << MC_TIMEOUT_VI_0_VIWY_TMVAL_SHIFT)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_RANGE                        19:16
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_DEFAULT                      _MK_MASK_CONST(0x8)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_VI_0_VIWY_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_AVPC_0  
+#define MC_TIMEOUT_RCOAL_AVPC_0                 _MK_ADDR_CONST(0x1f4)
+#define MC_TIMEOUT_RCOAL_AVPC_0_SECURE                  0x0
+#define MC_TIMEOUT_RCOAL_AVPC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_AVPC_0_RESET_VAL                       _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_AVPC_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_AVPC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_AVPC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_AVPC_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_AVPC_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_RANGE                     7:0
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_AVPC_0_AVPCARM7R_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_DC_0  
+#define MC_TIMEOUT_RCOAL_DC_0                   _MK_ADDR_CONST(0x1f8)
+#define MC_TIMEOUT_RCOAL_DC_0_SECURE                    0x0
+#define MC_TIMEOUT_RCOAL_DC_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_DC_0_RESET_VAL                         _MK_MASK_CONST(0x4040404)
+#define MC_TIMEOUT_RCOAL_DC_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DC_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_RANGE                       7:0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0A_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_RANGE                       15:8
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0B_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_RANGE                       23:16
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY0C_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(24)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_RANGE                       31:24
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DC_0_DISPLAY1B_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT1_RCOAL_DC_0  
+#define MC_TIMEOUT1_RCOAL_DC_0                  _MK_ADDR_CONST(0x1fc)
+#define MC_TIMEOUT1_RCOAL_DC_0_SECURE                   0x0
+#define MC_TIMEOUT1_RCOAL_DC_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT1_RCOAL_DC_0_RESET_VAL                        _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT1_RCOAL_DC_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DC_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DC_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DC_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DC_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_FIELD                      (_MK_MASK_CONST(0xff) << MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_RANGE                      7:0
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_DEFAULT                    _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DC_0_DISPLAYHC_RCOAL_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_DCB_0  
+#define MC_TIMEOUT_RCOAL_DCB_0                  _MK_ADDR_CONST(0x200)
+#define MC_TIMEOUT_RCOAL_DCB_0_SECURE                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_DCB_0_RESET_VAL                        _MK_MASK_CONST(0x4040404)
+#define MC_TIMEOUT_RCOAL_DCB_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_RANGE                     7:0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0AB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_RANGE                     15:8
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0BB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_RANGE                     23:16
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY0CB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(24)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_RANGE                     31:24
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_DCB_0_DISPLAY1BB_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT1_RCOAL_DCB_0  
+#define MC_TIMEOUT1_RCOAL_DCB_0                 _MK_ADDR_CONST(0x204)
+#define MC_TIMEOUT1_RCOAL_DCB_0_SECURE                  0x0
+#define MC_TIMEOUT1_RCOAL_DCB_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT1_RCOAL_DCB_0_RESET_VAL                       _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT1_RCOAL_DCB_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DCB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DCB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DCB_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DCB_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_RANGE                    7:0
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT1_RCOAL_DCB_0_DISPLAYHCB_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_EPP_0  
+#define MC_TIMEOUT_RCOAL_EPP_0                  _MK_ADDR_CONST(0x208)
+#define MC_TIMEOUT_RCOAL_EPP_0_SECURE                   0x0
+#define MC_TIMEOUT_RCOAL_EPP_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_EPP_0_RESET_VAL                        _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_EPP_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_EPP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_EPP_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_RANGE                  7:0
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_EPP_0_EPPUP_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_G2_0  
+#define MC_TIMEOUT_RCOAL_G2_0                   _MK_ADDR_CONST(0x20c)
+#define MC_TIMEOUT_RCOAL_G2_0_SECURE                    0x0
+#define MC_TIMEOUT_RCOAL_G2_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_G2_0_RESET_VAL                         _MK_MASK_CONST(0x40404)
+#define MC_TIMEOUT_RCOAL_G2_0_RESET_MASK                        _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_RCOAL_G2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_READ_MASK                         _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_RCOAL_G2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffff)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_RANGE                    7:0
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2PR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_RANGE                    15:8
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2SR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_RANGE                    23:16
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_WOFFSET                  0x0
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_G2_0_G2DR_RCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_HC_0  
+#define MC_TIMEOUT_RCOAL_HC_0                   _MK_ADDR_CONST(0x210)
+#define MC_TIMEOUT_RCOAL_HC_0_SECURE                    0x0
+#define MC_TIMEOUT_RCOAL_HC_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_HC_0_RESET_VAL                         _MK_MASK_CONST(0x404)
+#define MC_TIMEOUT_RCOAL_HC_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_HC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_HC_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_FIELD                      (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_RANGE                      7:0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_WOFFSET                    0x0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_DEFAULT                    _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XDMAR_RCOAL_TMVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SHIFT                 _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_FIELD                 (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_RANGE                 15:8
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_WOFFSET                       0x0
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_DEFAULT                       _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_HC_0_HOST1XR_RCOAL_TMVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPCORE_0  
+#define MC_TIMEOUT_RCOAL_MPCORE_0                       _MK_ADDR_CONST(0x214)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_SECURE                        0x0
+#define MC_TIMEOUT_RCOAL_MPCORE_0_WORD_COUNT                    0x1
+#define MC_TIMEOUT_RCOAL_MPCORE_0_RESET_VAL                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_RANGE                     7:0
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPCORE_0_MPCORER_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEA_0  
+#define MC_TIMEOUT_RCOAL_MPEA_0                 _MK_ADDR_CONST(0x218)
+#define MC_TIMEOUT_RCOAL_MPEA_0_SECURE                  0x0
+#define MC_TIMEOUT_RCOAL_MPEA_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEA_0_RESET_VAL                       _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEA_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEA_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_RANGE                     7:0
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEA_0_MPEAMEMRD_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEB_0  
+#define MC_TIMEOUT_RCOAL_MPEB_0                 _MK_ADDR_CONST(0x21c)
+#define MC_TIMEOUT_RCOAL_MPEB_0_SECURE                  0x0
+#define MC_TIMEOUT_RCOAL_MPEB_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEB_0_RESET_VAL                       _MK_MASK_CONST(0x404)
+#define MC_TIMEOUT_RCOAL_MPEB_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_RANGE                     7:0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPEUNIFBR_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SHIFT                     _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_FIELD                     (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_RANGE                     15:8
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_WOFFSET                   0x0
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_DEFAULT                   _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEB_0_MPE_IPRED_RCOAL_TMVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_MPEC_0  
+#define MC_TIMEOUT_RCOAL_MPEC_0                 _MK_ADDR_CONST(0x220)
+#define MC_TIMEOUT_RCOAL_MPEC_0_SECURE                  0x0
+#define MC_TIMEOUT_RCOAL_MPEC_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_MPEC_0_RESET_VAL                       _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEC_0_RESET_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEC_0_WRITE_MASK                      _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_RANGE                       7:0
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_MPEC_0_MPECSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_NV_0  
+#define MC_TIMEOUT_RCOAL_NV_0                   _MK_ADDR_CONST(0x224)
+#define MC_TIMEOUT_RCOAL_NV_0_SECURE                    0x0
+#define MC_TIMEOUT_RCOAL_NV_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_NV_0_RESET_VAL                         _MK_MASK_CONST(0x404)
+#define MC_TIMEOUT_RCOAL_NV_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_NV_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_NV_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_RANGE                  7:0
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_IDXSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SHIFT                  _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_FIELD                  (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_RANGE                  15:8
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_WOFFSET                        0x0
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_DEFAULT                        _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_NV_0_TEXSRD_RCOAL_TMVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_PPCS_0  
+#define MC_TIMEOUT_RCOAL_PPCS_0                 _MK_ADDR_CONST(0x228)
+#define MC_TIMEOUT_RCOAL_PPCS_0_SECURE                  0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_WORD_COUNT                      0x1
+#define MC_TIMEOUT_RCOAL_PPCS_0_RESET_VAL                       _MK_MASK_CONST(0x404)
+#define MC_TIMEOUT_RCOAL_PPCS_0_RESET_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_RANGE                   7:0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBDMAR_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_RANGE                   15:8
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_PPCS_0_PPCSAHBSLVR_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_VDE_0  
+#define MC_TIMEOUT_RCOAL_VDE_0                  _MK_ADDR_CONST(0x22c)
+#define MC_TIMEOUT_RCOAL_VDE_0_SECURE                   0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_WORD_COUNT                       0x1
+#define MC_TIMEOUT_RCOAL_VDE_0_RESET_VAL                        _MK_MASK_CONST(0x4040404)
+#define MC_TIMEOUT_RCOAL_VDE_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SHIFT                       _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_FIELD                       (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_RANGE                       7:0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_WOFFSET                     0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_DEFAULT                     _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEBSEVR_RCOAL_TMVAL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(8)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_RANGE                        15:8
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMBER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(16)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_RANGE                        23:16
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDEMCER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SHIFT                        _MK_SHIFT_CONST(24)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_FIELD                        (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_RANGE                        31:24
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_WOFFSET                      0x0
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_DEFAULT                      _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VDE_0_VDETPER_RCOAL_TMVAL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register MC_TIMEOUT_RCOAL_VI_0  
+#define MC_TIMEOUT_RCOAL_VI_0                   _MK_ADDR_CONST(0x230)
+#define MC_TIMEOUT_RCOAL_VI_0_SECURE                    0x0
+#define MC_TIMEOUT_RCOAL_VI_0_WORD_COUNT                        0x1
+#define MC_TIMEOUT_RCOAL_VI_0_RESET_VAL                         _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VI_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VI_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xff) << MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SHIFT)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_RANGE                   7:0
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_WOFFSET                 0x0
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x4)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_TIMEOUT_RCOAL_VI_0_VIRUV_RCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_CLIENT_RCOAL_AUTODISABLE_DISABLE     0
+#define MC_CLIENT_RCOAL_AUTODISABLE_ENABLE      1
+
+// Register MC_RCOAL_AUTODISABLE_0_0  
+#define MC_RCOAL_AUTODISABLE_0_0                        _MK_ADDR_CONST(0x234)
+#define MC_RCOAL_AUTODISABLE_0_0_SECURE                         0x0
+#define MC_RCOAL_AUTODISABLE_0_0_WORD_COUNT                     0x1
+#define MC_RCOAL_AUTODISABLE_0_0_RESET_VAL                      _MK_MASK_CONST(0x1fff)
+#define MC_RCOAL_AUTODISABLE_0_0_RESET_MASK                     _MK_MASK_CONST(0x1fff)
+#define MC_RCOAL_AUTODISABLE_0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_READ_MASK                      _MK_MASK_CONST(0x1fff)
+#define MC_RCOAL_AUTODISABLE_0_0_WRITE_MASK                     _MK_MASK_CONST(0x1fff)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_SHIFT                   _MK_SHIFT_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_FIELD                   (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_RANGE                   0:0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_WOFFSET                 0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_INIT_ENUM                       ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0A_RCOAL_AUTODISABLE_EN_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_SHIFT                  _MK_SHIFT_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_FIELD                  (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_RANGE                  1:1
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_WOFFSET                        0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_INIT_ENUM                      ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0AB_RCOAL_AUTODISABLE_EN_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_FIELD                   (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_RANGE                   2:2
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_WOFFSET                 0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_INIT_ENUM                       ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0B_RCOAL_AUTODISABLE_EN_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_SHIFT                  _MK_SHIFT_CONST(3)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_FIELD                  (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_RANGE                  3:3
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_WOFFSET                        0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_INIT_ENUM                      ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0BB_RCOAL_AUTODISABLE_EN_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_SHIFT                   _MK_SHIFT_CONST(4)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_FIELD                   (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_RANGE                   4:4
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_WOFFSET                 0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_INIT_ENUM                       ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0C_RCOAL_AUTODISABLE_EN_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_SHIFT                  _MK_SHIFT_CONST(5)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_FIELD                  (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_RANGE                  5:5
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_WOFFSET                        0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_INIT_ENUM                      ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY0CB_RCOAL_AUTODISABLE_EN_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_SHIFT                   _MK_SHIFT_CONST(6)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_FIELD                   (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_RANGE                   6:6
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_WOFFSET                 0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_INIT_ENUM                       ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1B_RCOAL_AUTODISABLE_EN_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_SHIFT                  _MK_SHIFT_CONST(7)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_FIELD                  (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_RANGE                  7:7
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_WOFFSET                        0x0
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_INIT_ENUM                      ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_ENABLE                 _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_DISABLED                       _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_DISPLAY1BB_RCOAL_AUTODISABLE_EN_ENABLED                        _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_SHIFT                       _MK_SHIFT_CONST(8)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_FIELD                       (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_RANGE                       8:8
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_WOFFSET                     0x0
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_INIT_ENUM                   ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_EPPUP_RCOAL_AUTODISABLE_EN_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_SHIFT                        _MK_SHIFT_CONST(9)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_FIELD                        (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_RANGE                        9:9
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_WOFFSET                      0x0
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_INIT_ENUM                    ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2PR_RCOAL_AUTODISABLE_EN_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_SHIFT                        _MK_SHIFT_CONST(10)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_FIELD                        (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_RANGE                        10:10
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_WOFFSET                      0x0
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_INIT_ENUM                    ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_ENABLE                       _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_DISABLED                     _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_G2SR_RCOAL_AUTODISABLE_EN_ENABLED                      _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_SHIFT                   _MK_SHIFT_CONST(11)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_FIELD                   (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_RANGE                   11:11
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_WOFFSET                 0x0
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_INIT_ENUM                       ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_MPEUNIFBR_RCOAL_AUTODISABLE_EN_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_SHIFT                       _MK_SHIFT_CONST(12)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_FIELD                       (_MK_MASK_CONST(0x1) << MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_SHIFT)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_RANGE                       12:12
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_WOFFSET                     0x0
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_INIT_ENUM                   ENABLE
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_RCOAL_AUTODISABLE_0_0_VIRUV_RCOAL_AUTODISABLE_EN_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_INCVAL_SIZE  11
+#define MC_BWSHARE_HIGHTH_SIZE  8
+#define MC_BWSHARE_MAXTH_SIZE   8
+#define MC_BWSHARE_ALWAYSINC_DISABLE    0
+#define MC_BWSHARE_ALWAYSINC_ENABLE     1
+#define MC_BWSHARE_TMSFACTORSEL_1       0
+#define MC_BWSHARE_TMSFACTORSEL_2       1
+
+// Register MC_BWSHARE_AVPC_0  
+#define MC_BWSHARE_AVPC_0                       _MK_ADDR_CONST(0x238)
+#define MC_BWSHARE_AVPC_0_SECURE                        0x0
+#define MC_BWSHARE_AVPC_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_AVPC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_AVPC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_AVPC_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_AVPC_0_AVPC_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_DC_0  
+#define MC_BWSHARE_DC_0                 _MK_ADDR_CONST(0x23c)
+#define MC_BWSHARE_DC_0_SECURE                  0x0
+#define MC_BWSHARE_DC_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_DC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DC_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_DC_0_DC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_DC_0_DC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_DC_0_DC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DC_0_DC_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DC_0_DC_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_DCB_0  
+#define MC_BWSHARE_DCB_0                        _MK_ADDR_CONST(0x240)
+#define MC_BWSHARE_DCB_0_SECURE                         0x0
+#define MC_BWSHARE_DCB_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_DCB_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DCB_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DCB_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_DCB_0_DCB_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_DCB_0_DCB_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DCB_0_DCB_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_DCB_0_DCB_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_EPP_0  
+#define MC_BWSHARE_EPP_0                        _MK_ADDR_CONST(0x244)
+#define MC_BWSHARE_EPP_0_SECURE                         0x0
+#define MC_BWSHARE_EPP_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_EPP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_EPP_0_EPP_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_G2_0  
+#define MC_BWSHARE_G2_0                 _MK_ADDR_CONST(0x248)
+#define MC_BWSHARE_G2_0_SECURE                  0x0
+#define MC_BWSHARE_G2_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_G2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_G2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_G2_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_G2_0_G2_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_G2_0_G2_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_G2_0_G2_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_G2_0_G2_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_G2_0_G2_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_HC_0  
+#define MC_BWSHARE_HC_0                 _MK_ADDR_CONST(0x24c)
+#define MC_BWSHARE_HC_0_SECURE                  0x0
+#define MC_BWSHARE_HC_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_HC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HC_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_HC_0_HC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_HC_0_HC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_HC_0_HC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HC_0_HC_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_HC_0_HC_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_ISP_0  
+#define MC_BWSHARE_ISP_0                        _MK_ADDR_CONST(0x250)
+#define MC_BWSHARE_ISP_0_SECURE                         0x0
+#define MC_BWSHARE_ISP_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_ISP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_ISP_0_ISP_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPCORE_0  
+#define MC_BWSHARE_MPCORE_0                     _MK_ADDR_CONST(0x254)
+#define MC_BWSHARE_MPCORE_0_SECURE                      0x0
+#define MC_BWSHARE_MPCORE_0_WORD_COUNT                  0x1
+#define MC_BWSHARE_MPCORE_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_RESET_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_READ_MASK                   _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_WRITE_MASK                  _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPCORE_0_MPCORE_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEA_0  
+#define MC_BWSHARE_MPEA_0                       _MK_ADDR_CONST(0x258)
+#define MC_BWSHARE_MPEA_0_SECURE                        0x0
+#define MC_BWSHARE_MPEA_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEA_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEA_0_MPEA_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEB_0  
+#define MC_BWSHARE_MPEB_0                       _MK_ADDR_CONST(0x25c)
+#define MC_BWSHARE_MPEB_0_SECURE                        0x0
+#define MC_BWSHARE_MPEB_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEB_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEB_0_MPEB_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_MPEC_0  
+#define MC_BWSHARE_MPEC_0                       _MK_ADDR_CONST(0x260)
+#define MC_BWSHARE_MPEC_0_SECURE                        0x0
+#define MC_BWSHARE_MPEC_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_MPEC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_MPEC_0_MPEC_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_NV_0  
+#define MC_BWSHARE_NV_0                 _MK_ADDR_CONST(0x264)
+#define MC_BWSHARE_NV_0_SECURE                  0x0
+#define MC_BWSHARE_NV_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_NV_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_NV_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_NV_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_NV_0_NV_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_NV_0_NV_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_NV_0_NV_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_NV_0_NV_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_NV_0_NV_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_PPCS_0  
+#define MC_BWSHARE_PPCS_0                       _MK_ADDR_CONST(0x268)
+#define MC_BWSHARE_PPCS_0_SECURE                        0x0
+#define MC_BWSHARE_PPCS_0_WORD_COUNT                    0x1
+#define MC_BWSHARE_PPCS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_RESET_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_READ_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_WRITE_MASK                    _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SHIFT                  _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_FIELD                  (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_RANGE                  10:0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_WOFFSET                        0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_DEFAULT_MASK                   _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_INCVAL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SHIFT                  _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_FIELD                  (_MK_MASK_CONST(0xff) << MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_RANGE                  18:11
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_WOFFSET                        0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_HIGHTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SHIFT                   _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_FIELD                   (_MK_MASK_CONST(0xff) << MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_RANGE                   26:19
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_WOFFSET                 0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_MAXTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SHIFT                       _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_FIELD                       (_MK_MASK_CONST(0x1) << MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_RANGE                       27:27
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_WOFFSET                     0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_INIT_ENUM                   DISABLE
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DISABLE                     _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_ENABLE                      _MK_ENUM_CONST(1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_DISABLED                    _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_ALWAYSINC_ENABLED                     _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SHIFT                    _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_FIELD                    (_MK_MASK_CONST(0x1) << MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_RANGE                    28:28
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_WOFFSET                  0x0
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_INIT_ENUM                        TM_SFACTOR1
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_TM_SFACTOR1                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_PPCS_0_PPCS_BW_TMSFACTORSEL_TM_SFACTOR2                      _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_VDE_0  
+#define MC_BWSHARE_VDE_0                        _MK_ADDR_CONST(0x26c)
+#define MC_BWSHARE_VDE_0_SECURE                         0x0
+#define MC_BWSHARE_VDE_0_WORD_COUNT                     0x1
+#define MC_BWSHARE_VDE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_RESET_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_READ_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_WRITE_MASK                     _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_FIELD                    (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_RANGE                    10:0
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_WOFFSET                  0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_DEFAULT_MASK                     _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_INCVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SHIFT                    _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_FIELD                    (_MK_MASK_CONST(0xff) << MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_RANGE                    18:11
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_WOFFSET                  0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_HIGHTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SHIFT                     _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_FIELD                     (_MK_MASK_CONST(0xff) << MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_RANGE                     26:19
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_WOFFSET                   0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_MAXTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SHIFT                 _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_FIELD                 (_MK_MASK_CONST(0x1) << MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_RANGE                 27:27
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_WOFFSET                       0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_INIT_ENUM                     DISABLE
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DISABLE                       _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_ENABLE                        _MK_ENUM_CONST(1)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_DISABLED                      _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_ALWAYSINC_ENABLED                       _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SHIFT                      _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_FIELD                      (_MK_MASK_CONST(0x1) << MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_RANGE                      28:28
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_WOFFSET                    0x0
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_INIT_ENUM                  TM_SFACTOR1
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_TM_SFACTOR1                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VDE_0_VDE_BW_TMSFACTORSEL_TM_SFACTOR2                        _MK_ENUM_CONST(1)
+
+
+// Register MC_BWSHARE_VI_0  
+#define MC_BWSHARE_VI_0                 _MK_ADDR_CONST(0x270)
+#define MC_BWSHARE_VI_0_SECURE                  0x0
+#define MC_BWSHARE_VI_0_WORD_COUNT                      0x1
+#define MC_BWSHARE_VI_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_RESET_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_READ_MASK                       _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_WRITE_MASK                      _MK_MASK_CONST(0x1fffffff)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_FIELD                      (_MK_MASK_CONST(0x7ff) << MC_BWSHARE_VI_0_VI_BW_INCVAL_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_RANGE                      10:0
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_WOFFSET                    0x0
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x7ff)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_INCVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SHIFT                      _MK_SHIFT_CONST(11)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_FIELD                      (_MK_MASK_CONST(0xff) << MC_BWSHARE_VI_0_VI_BW_HIGHTH_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_RANGE                      18:11
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_WOFFSET                    0x0
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_HIGHTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SHIFT                       _MK_SHIFT_CONST(19)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_FIELD                       (_MK_MASK_CONST(0xff) << MC_BWSHARE_VI_0_VI_BW_MAXTH_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_RANGE                       26:19
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_WOFFSET                     0x0
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_MAXTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SHIFT                   _MK_SHIFT_CONST(27)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_FIELD                   (_MK_MASK_CONST(0x1) << MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_RANGE                   27:27
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_WOFFSET                 0x0
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_INIT_ENUM                       DISABLE
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DISABLE                 _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_ENABLE                  _MK_ENUM_CONST(1)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_DISABLED                        _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_ALWAYSINC_ENABLED                 _MK_ENUM_CONST(1)
+
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SHIFT                        _MK_SHIFT_CONST(28)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_FIELD                        (_MK_MASK_CONST(0x1) << MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SHIFT)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_RANGE                        28:28
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_WOFFSET                      0x0
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_INIT_ENUM                    TM_SFACTOR1
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_TM_SFACTOR1                  _MK_ENUM_CONST(0)
+#define MC_BWSHARE_VI_0_VI_BW_TMSFACTORSEL_TM_SFACTOR2                  _MK_ENUM_CONST(1)
+
+#define NV_MC_EMEM_DFIFO_DEPTH  4
+#define NV_MC_IMEM_DFIFO_DEPTH  5
+#define NV_MC_EMEM_APFIFO_DEPTH 5
+#define NV_MC_ARB_EMEM_REGLEVEL 3
+#define NV_MC_EMEM_REQ_ID_WIDEREQ       8
+#define NV_MC_EMEM_RDI_ID_WIDERDI       8
+#define NV_MC_EMEM_REQ_ID_ILLEGALACC    7
+#define NV_MC_EMEM_RDI_ID_ILLEGALACC    7
+#define NV_MC_EMEM_REQ_ID_LLRAWDECR     6
+#define NV_MC_EMEM_RDI_ID_LLRAWDECR     6
+#define NV_MC_EMEM_REQ_ID_APCIGNORE     5
+#define NV_MC_EMEM_RDI_ID_APCIGNORE     5
+
+// Packet MC2EMC
+#define MC2EMC_SIZE 186
+
+#define MC2EMC_WDO_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_SHIFT)
+#define MC2EMC_WDO_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_ROW                  0
+
+#define MC2EMC_WDO_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_0_SHIFT)
+#define MC2EMC_WDO_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC2EMC_WDO_0_ROW                        0
+
+#define MC2EMC_WDO_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_1_SHIFT)
+#define MC2EMC_WDO_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define MC2EMC_WDO_1_ROW                        0
+
+#define MC2EMC_WDO_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_2_SHIFT)
+#define MC2EMC_WDO_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define MC2EMC_WDO_2_ROW                        0
+
+#define MC2EMC_WDO_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << MC2EMC_WDO_3_SHIFT)
+#define MC2EMC_WDO_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define MC2EMC_WDO_3_ROW                        0
+
+#define MC2EMC_BE_SHIFT                 _MK_SHIFT_CONST(128)
+#define MC2EMC_BE_FIELD                 (_MK_MASK_CONST(0xffff) << MC2EMC_BE_SHIFT)
+#define MC2EMC_BE_RANGE                 _MK_SHIFT_CONST(143):_MK_SHIFT_CONST(128)
+#define MC2EMC_BE_ROW                   0
+
+#define MC2EMC_ADR_SHIFT                        _MK_SHIFT_CONST(144)
+#define MC2EMC_ADR_FIELD                        (_MK_MASK_CONST(0x3ffffff) << MC2EMC_ADR_SHIFT)
+#define MC2EMC_ADR_RANGE                        _MK_SHIFT_CONST(169):_MK_SHIFT_CONST(144)
+#define MC2EMC_ADR_ROW                  0
+
+#define MC2EMC_REQ_ID_SHIFT                     _MK_SHIFT_CONST(170)
+#define MC2EMC_REQ_ID_FIELD                     (_MK_MASK_CONST(0x1ff) << MC2EMC_REQ_ID_SHIFT)
+#define MC2EMC_REQ_ID_RANGE                     _MK_SHIFT_CONST(178):_MK_SHIFT_CONST(170)
+#define MC2EMC_REQ_ID_ROW                       0
+
+#define MC2EMC_AP_SHIFT                 _MK_SHIFT_CONST(179)
+#define MC2EMC_AP_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_AP_SHIFT)
+#define MC2EMC_AP_RANGE                 _MK_SHIFT_CONST(179):_MK_SHIFT_CONST(179)
+#define MC2EMC_AP_ROW                   0
+
+#define MC2EMC_WE_SHIFT                 _MK_SHIFT_CONST(180)
+#define MC2EMC_WE_FIELD                 (_MK_MASK_CONST(0x1) << MC2EMC_WE_SHIFT)
+#define MC2EMC_WE_RANGE                 _MK_SHIFT_CONST(180):_MK_SHIFT_CONST(180)
+#define MC2EMC_WE_ROW                   0
+
+#define MC2EMC_TAG_SHIFT                        _MK_SHIFT_CONST(181)
+#define MC2EMC_TAG_FIELD                        (_MK_MASK_CONST(0x1f) << MC2EMC_TAG_SHIFT)
+#define MC2EMC_TAG_RANGE                        _MK_SHIFT_CONST(185):_MK_SHIFT_CONST(181)
+#define MC2EMC_TAG_ROW                  0
+
+
+// Packet MC2EMC_APC
+#define MC2EMC_APC_SIZE 3
+
+#define MC2EMC_APC_CLR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_FIELD                    (_MK_MASK_CONST(0x1) << MC2EMC_APC_CLR_SHIFT)
+#define MC2EMC_APC_CLR_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define MC2EMC_APC_CLR_ROW                      0
+
+#define MC2EMC_APC_BANK_SHIFT                   _MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_FIELD                   (_MK_MASK_CONST(0x3) << MC2EMC_APC_BANK_SHIFT)
+#define MC2EMC_APC_BANK_RANGE                   _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define MC2EMC_APC_BANK_ROW                     0
+
+
+// Packet EMC2MC
+#define EMC2MC_SIZE 137
+
+#define EMC2MC_RDI_SHIFT                        _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_FIELD                        (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_SHIFT)
+#define EMC2MC_RDI_RANGE                        _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_ROW                  0
+
+#define EMC2MC_RDI_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_0_SHIFT)
+#define EMC2MC_RDI_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define EMC2MC_RDI_0_ROW                        0
+
+#define EMC2MC_RDI_1_SHIFT                      _MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_1_SHIFT)
+#define EMC2MC_RDI_1_RANGE                      _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define EMC2MC_RDI_1_ROW                        0
+
+#define EMC2MC_RDI_2_SHIFT                      _MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_2_SHIFT)
+#define EMC2MC_RDI_2_RANGE                      _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define EMC2MC_RDI_2_ROW                        0
+
+#define EMC2MC_RDI_3_SHIFT                      _MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_FIELD                      (_MK_MASK_CONST(0xffffffff) << EMC2MC_RDI_3_SHIFT)
+#define EMC2MC_RDI_3_RANGE                      _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define EMC2MC_RDI_3_ROW                        0
+
+#define EMC2MC_RDI_ID_SHIFT                     _MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_FIELD                     (_MK_MASK_CONST(0x1ff) << EMC2MC_RDI_ID_SHIFT)
+#define EMC2MC_RDI_ID_RANGE                     _MK_SHIFT_CONST(136):_MK_SHIFT_CONST(128)
+#define EMC2MC_RDI_ID_ROW                       0
+
+
+// Packet MC2EMC_LL
+#define MC2EMC_LL_SIZE 33
+
+#define MC2EMC_LL_ADR_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ADR_FIELD                     (_MK_MASK_CONST(0x7ffffff) << MC2EMC_LL_ADR_SHIFT)
+#define MC2EMC_LL_ADR_RANGE                     _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ADR_ROW                       0
+
+#define MC2EMC_LL_TAG_SHIFT                     _MK_SHIFT_CONST(27)
+#define MC2EMC_LL_TAG_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_TAG_SHIFT)
+#define MC2EMC_LL_TAG_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(27)
+#define MC2EMC_LL_TAG_ROW                       0
+
+#define MC2EMC_LL_DOUBLEREQ_SHIFT                       _MK_SHIFT_CONST(32)
+#define MC2EMC_LL_DOUBLEREQ_FIELD                       (_MK_MASK_CONST(0x1) << MC2EMC_LL_DOUBLEREQ_SHIFT)
+#define MC2EMC_LL_DOUBLEREQ_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define MC2EMC_LL_DOUBLEREQ_ROW                 0
+
+
+// Packet EMC2MC_LL
+#define EMC2MC_LL_SIZE 64
+
+#define EMC2MC_LL_RDI_SHIFT                     _MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_FIELD                     (_MK_MASK_CONST(0xffffffff) << EMC2MC_LL_RDI_SHIFT)
+#define EMC2MC_LL_RDI_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define EMC2MC_LL_RDI_ROW                       0
+
+
+// Packet MC2EMC_LL_CRITINFO
+#define MC2EMC_LL_CRITINFO_SIZE 11
+
+#define MC2EMC_LL_CRITINFO_HP_SHIFT                     _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_FIELD                     (_MK_MASK_CONST(0x1f) << MC2EMC_LL_CRITINFO_HP_SHIFT)
+#define MC2EMC_LL_CRITINFO_HP_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_CRITINFO_HP_ROW                       0
+
+#define MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT                        _MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_FIELD                        (_MK_MASK_CONST(0x3f) << MC2EMC_LL_CRITINFO_TIMEOUT_SHIFT)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_RANGE                        _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(5)
+#define MC2EMC_LL_CRITINFO_TIMEOUT_ROW                  0
+
+
+// Packet MC2EMC_LL_ARBINFO
+#define MC2EMC_LL_ARBINFO_SIZE 2
+
+#define MC2EMC_LL_ARBINFO_BANK_SHIFT                    _MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_FIELD                    (_MK_MASK_CONST(0x3) << MC2EMC_LL_ARBINFO_BANK_SHIFT)
+#define MC2EMC_LL_ARBINFO_BANK_RANGE                    _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define MC2EMC_LL_ARBINFO_BANK_ROW                      0
+
+
+// Packet CMC2MC_AXI_A
+#define CMC2MC_AXI_A_SIZE 63
+
+#define CMC2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_A_AADDR_SHIFT)
+#define CMC2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_A_AADDR_ROW                  0
+
+#define CMC2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_A_AID_SHIFT)
+#define CMC2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define CMC2MC_AXI_A_AID_ROW                    0
+
+#define CMC2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define CMC2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ALEN_SHIFT)
+#define CMC2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define CMC2MC_AXI_A_ALEN_ROW                   0
+#define CMC2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define CMC2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define CMC2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define CMC2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define CMC2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_ASIZE_SHIFT)
+#define CMC2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define CMC2MC_AXI_A_ASIZE_ROW                  0
+#define CMC2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define CMC2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define CMC2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ABURST_SHIFT)
+#define CMC2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define CMC2MC_AXI_A_ABURST_ROW                 0
+#define CMC2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define CMC2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_A_ALOCK_SHIFT)
+#define CMC2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define CMC2MC_AXI_A_ALOCK_ROW                  0
+#define CMC2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define CMC2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << CMC2MC_AXI_A_ACACHE_SHIFT)
+#define CMC2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define CMC2MC_AXI_A_ACACHE_ROW                 0
+#define CMC2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define CMC2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define CMC2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define CMC2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << CMC2MC_AXI_A_APROT_SHIFT)
+#define CMC2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define CMC2MC_AXI_A_APROT_ROW                  0
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define CMC2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define CMC2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet CMC2MC_AXI_W
+#define CMC2MC_AXI_W_SIZE 86
+
+#define CMC2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_W_WDATA_SHIFT)
+#define CMC2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_W_WDATA_ROW                  0
+
+#define CMC2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_W_WID_SHIFT)
+#define CMC2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_W_WID_ROW                    0
+
+#define CMC2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xff) << CMC2MC_AXI_W_WSTRB_SHIFT)
+#define CMC2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(84):_MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_W_WSTRB_ROW                  0
+
+#define CMC2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(85)
+#define CMC2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_W_WLAST_SHIFT)
+#define CMC2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(85):_MK_SHIFT_CONST(85)
+#define CMC2MC_AXI_W_WLAST_ROW                  0
+#define CMC2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet CMC2MC_AXI_B
+#define CMC2MC_AXI_B_SIZE 15
+
+#define CMC2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_B_BID_SHIFT)
+#define CMC2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_B_BID_ROW                    0
+
+#define CMC2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(13)
+#define CMC2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_B_BRESP_SHIFT)
+#define CMC2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define CMC2MC_AXI_B_BRESP_ROW                  0
+#define CMC2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet CMC2MC_AXI_R
+#define CMC2MC_AXI_R_SIZE 80
+
+#define CMC2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << CMC2MC_AXI_R_RDATA_SHIFT)
+#define CMC2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define CMC2MC_AXI_R_RDATA_ROW                  0
+
+#define CMC2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0x1fff) << CMC2MC_AXI_R_RID_SHIFT)
+#define CMC2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define CMC2MC_AXI_R_RID_ROW                    0
+
+#define CMC2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << CMC2MC_AXI_R_RRESP_SHIFT)
+#define CMC2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(78):_MK_SHIFT_CONST(77)
+#define CMC2MC_AXI_R_RRESP_ROW                  0
+#define CMC2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define CMC2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define CMC2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define CMC2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(79)
+#define CMC2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << CMC2MC_AXI_R_RLAST_SHIFT)
+#define CMC2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(79)
+#define CMC2MC_AXI_R_RLAST_ROW                  0
+#define CMC2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define CMC2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_A
+#define MSELECT2MC_AXI_A_SIZE 63
+
+#define MSELECT2MC_AXI_A_AADDR_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_A_AADDR_SHIFT)
+#define MSELECT2MC_AXI_A_AADDR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_A_AADDR_ROW                      0
+
+#define MSELECT2MC_AXI_A_AID_SHIFT                      _MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_A_AID_SHIFT)
+#define MSELECT2MC_AXI_A_AID_RANGE                      _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define MSELECT2MC_AXI_A_AID_ROW                        0
+
+#define MSELECT2MC_AXI_A_ALEN_SHIFT                     _MK_SHIFT_CONST(45)
+#define MSELECT2MC_AXI_A_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ALEN_SHIFT)
+#define MSELECT2MC_AXI_A_ALEN_RANGE                     _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define MSELECT2MC_AXI_A_ALEN_ROW                       0
+#define MSELECT2MC_AXI_A_ALEN_ONEDATA                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALEN_TWODATA                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALEN_THREEDATA                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALEN_FOURDATA                  _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ALEN_FIVEDATA                  _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ALEN_SIXDATA                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ALEN_SEVENDATA                 _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ALEN_EIGHTDATA                 _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ALEN_NINEDATA                  _MK_ENUM_CONST(8)
+#define MSELECT2MC_AXI_A_ALEN_TENDATA                   _MK_ENUM_CONST(9)
+#define MSELECT2MC_AXI_A_ALEN_ELEVENDATA                        _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ALEN_TWELVEDATA                        _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ALEN_THIRTEENDATA                      _MK_ENUM_CONST(12)
+#define MSELECT2MC_AXI_A_ALEN_FOURTEENDATA                      _MK_ENUM_CONST(13)
+#define MSELECT2MC_AXI_A_ALEN_FIFTHTEENDATA                     _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ALEN_SIXTEENDATA                       _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_ASIZE_SHIFT                    _MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_ASIZE_SHIFT)
+#define MSELECT2MC_AXI_A_ASIZE_RANGE                    _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define MSELECT2MC_AXI_A_ASIZE_ROW                      0
+#define MSELECT2MC_AXI_A_ASIZE_ONEBYTE                  _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ASIZE_TWOBYTES                 _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ASIZE_FOURBYTES                        _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ASIZE_EIGHTBYTES                       _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTEENBYTES                     _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_ASIZE_THIRTYTWOBYTES                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_ASIZE_SIXTYFOURBYTES                   _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                       _MK_ENUM_CONST(7)
+
+#define MSELECT2MC_AXI_A_ABURST_SHIFT                   _MK_SHIFT_CONST(52)
+#define MSELECT2MC_AXI_A_ABURST_FIELD                   (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ABURST_SHIFT)
+#define MSELECT2MC_AXI_A_ABURST_RANGE                   _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define MSELECT2MC_AXI_A_ABURST_ROW                     0
+#define MSELECT2MC_AXI_A_ABURST_FIXED                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ABURST_INCR                    _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ABURST_WRAP                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ABURST_RSVD                    _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ALOCK_SHIFT                    _MK_SHIFT_CONST(54)
+#define MSELECT2MC_AXI_A_ALOCK_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_A_ALOCK_SHIFT)
+#define MSELECT2MC_AXI_A_ALOCK_RANGE                    _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define MSELECT2MC_AXI_A_ALOCK_ROW                      0
+#define MSELECT2MC_AXI_A_ALOCK_NORMAL                   _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ALOCK_EXCLUSIVE                        _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ALOCK_LOCKED                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ALOCK_RSVD                     _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_A_ACACHE_SHIFT                   _MK_SHIFT_CONST(56)
+#define MSELECT2MC_AXI_A_ACACHE_FIELD                   (_MK_MASK_CONST(0xf) << MSELECT2MC_AXI_A_ACACHE_SHIFT)
+#define MSELECT2MC_AXI_A_ACACHE_RANGE                   _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define MSELECT2MC_AXI_A_ACACHE_ROW                     0
+#define MSELECT2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                      _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_ACACHE_BUFFERABLE                      _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                 _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                      _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                       _MK_ENUM_CONST(7)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                   _MK_ENUM_CONST(10)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                      _MK_ENUM_CONST(11)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                       _MK_ENUM_CONST(14)
+#define MSELECT2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                  _MK_ENUM_CONST(15)
+
+#define MSELECT2MC_AXI_A_APROT_SHIFT                    _MK_SHIFT_CONST(60)
+#define MSELECT2MC_AXI_A_APROT_FIELD                    (_MK_MASK_CONST(0x7) << MSELECT2MC_AXI_A_APROT_SHIFT)
+#define MSELECT2MC_AXI_A_APROT_RANGE                    _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define MSELECT2MC_AXI_A_APROT_ROW                      0
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_NORMAL                       _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                    _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(3)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_NORMAL                       _MK_ENUM_CONST(4)
+#define MSELECT2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                   _MK_ENUM_CONST(5)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                    _MK_ENUM_CONST(6)
+#define MSELECT2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                        _MK_ENUM_CONST(7)
+
+
+// Packet MSELECT2MC_AXI_W
+#define MSELECT2MC_AXI_W_SIZE 86
+
+#define MSELECT2MC_AXI_W_WDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_W_WDATA_SHIFT)
+#define MSELECT2MC_AXI_W_WDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_W_WDATA_ROW                      0
+
+#define MSELECT2MC_AXI_W_WID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_W_WID_SHIFT)
+#define MSELECT2MC_AXI_W_WID_RANGE                      _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_W_WID_ROW                        0
+
+#define MSELECT2MC_AXI_W_WSTRB_SHIFT                    _MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_W_WSTRB_FIELD                    (_MK_MASK_CONST(0xff) << MSELECT2MC_AXI_W_WSTRB_SHIFT)
+#define MSELECT2MC_AXI_W_WSTRB_RANGE                    _MK_SHIFT_CONST(84):_MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_W_WSTRB_ROW                      0
+
+#define MSELECT2MC_AXI_W_WLAST_SHIFT                    _MK_SHIFT_CONST(85)
+#define MSELECT2MC_AXI_W_WLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_W_WLAST_SHIFT)
+#define MSELECT2MC_AXI_W_WLAST_RANGE                    _MK_SHIFT_CONST(85):_MK_SHIFT_CONST(85)
+#define MSELECT2MC_AXI_W_WLAST_ROW                      0
+#define MSELECT2MC_AXI_W_WLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_W_WLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet MSELECT2MC_AXI_B
+#define MSELECT2MC_AXI_B_SIZE 15
+
+#define MSELECT2MC_AXI_B_BID_SHIFT                      _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_B_BID_SHIFT)
+#define MSELECT2MC_AXI_B_BID_RANGE                      _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_B_BID_ROW                        0
+
+#define MSELECT2MC_AXI_B_BRESP_SHIFT                    _MK_SHIFT_CONST(13)
+#define MSELECT2MC_AXI_B_BRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_B_BRESP_SHIFT)
+#define MSELECT2MC_AXI_B_BRESP_RANGE                    _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define MSELECT2MC_AXI_B_BRESP_ROW                      0
+#define MSELECT2MC_AXI_B_BRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_B_BRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_B_BRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_B_BRESP_DECERR                   _MK_ENUM_CONST(3)
+
+
+// Packet MSELECT2MC_AXI_R
+#define MSELECT2MC_AXI_R_SIZE 80
+
+#define MSELECT2MC_AXI_R_RDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_FIELD                    (_MK_MASK_CONST(0xffffffff) << MSELECT2MC_AXI_R_RDATA_SHIFT)
+#define MSELECT2MC_AXI_R_RDATA_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(0)
+#define MSELECT2MC_AXI_R_RDATA_ROW                      0
+
+#define MSELECT2MC_AXI_R_RID_SHIFT                      _MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_FIELD                      (_MK_MASK_CONST(0x1fff) << MSELECT2MC_AXI_R_RID_SHIFT)
+#define MSELECT2MC_AXI_R_RID_RANGE                      _MK_SHIFT_CONST(76):_MK_SHIFT_CONST(64)
+#define MSELECT2MC_AXI_R_RID_ROW                        0
+
+#define MSELECT2MC_AXI_R_RRESP_SHIFT                    _MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_R_RRESP_FIELD                    (_MK_MASK_CONST(0x3) << MSELECT2MC_AXI_R_RRESP_SHIFT)
+#define MSELECT2MC_AXI_R_RRESP_RANGE                    _MK_SHIFT_CONST(78):_MK_SHIFT_CONST(77)
+#define MSELECT2MC_AXI_R_RRESP_ROW                      0
+#define MSELECT2MC_AXI_R_RRESP_OKAY                     _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RRESP_EXOKAY                   _MK_ENUM_CONST(1)
+#define MSELECT2MC_AXI_R_RRESP_SLVERR                   _MK_ENUM_CONST(2)
+#define MSELECT2MC_AXI_R_RRESP_DECERR                   _MK_ENUM_CONST(3)
+
+#define MSELECT2MC_AXI_R_RLAST_SHIFT                    _MK_SHIFT_CONST(79)
+#define MSELECT2MC_AXI_R_RLAST_FIELD                    (_MK_MASK_CONST(0x1) << MSELECT2MC_AXI_R_RLAST_SHIFT)
+#define MSELECT2MC_AXI_R_RLAST_RANGE                    _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(79)
+#define MSELECT2MC_AXI_R_RLAST_ROW                      0
+#define MSELECT2MC_AXI_R_RLAST_DISABLED                 _MK_ENUM_CONST(0)
+#define MSELECT2MC_AXI_R_RLAST_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_A
+#define AXI2MC_AXI_A_SIZE 63
+
+#define AXI2MC_AXI_A_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_A_AADDR_SHIFT)
+#define AXI2MC_AXI_A_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_A_AADDR_ROW                  0
+
+#define AXI2MC_AXI_A_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_A_AID_SHIFT)
+#define AXI2MC_AXI_A_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define AXI2MC_AXI_A_AID_ROW                    0
+
+#define AXI2MC_AXI_A_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define AXI2MC_AXI_A_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ALEN_SHIFT)
+#define AXI2MC_AXI_A_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define AXI2MC_AXI_A_ALEN_ROW                   0
+#define AXI2MC_AXI_A_ALEN_ONEDATA                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALEN_TWODATA                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALEN_THREEDATA                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALEN_FOURDATA                      _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ALEN_FIVEDATA                      _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ALEN_SIXDATA                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ALEN_SEVENDATA                     _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ALEN_EIGHTDATA                     _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ALEN_NINEDATA                      _MK_ENUM_CONST(8)
+#define AXI2MC_AXI_A_ALEN_TENDATA                       _MK_ENUM_CONST(9)
+#define AXI2MC_AXI_A_ALEN_ELEVENDATA                    _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ALEN_TWELVEDATA                    _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ALEN_THIRTEENDATA                  _MK_ENUM_CONST(12)
+#define AXI2MC_AXI_A_ALEN_FOURTEENDATA                  _MK_ENUM_CONST(13)
+#define AXI2MC_AXI_A_ALEN_FIFTHTEENDATA                 _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ALEN_SIXTEENDATA                   _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_ASIZE_SHIFT)
+#define AXI2MC_AXI_A_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define AXI2MC_AXI_A_ASIZE_ROW                  0
+#define AXI2MC_AXI_A_ASIZE_ONEBYTE                      _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ASIZE_TWOBYTES                     _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ASIZE_FOURBYTES                    _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ASIZE_EIGHTBYTES                   _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ASIZE_SIXTEENBYTES                 _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_ASIZE_THIRTYTWOBYTES                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_ASIZE_SIXTYFOURBYTES                       _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ASIZE_ONEHUNDREDTWENTYEIGHTBYTES                   _MK_ENUM_CONST(7)
+
+#define AXI2MC_AXI_A_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define AXI2MC_AXI_A_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ABURST_SHIFT)
+#define AXI2MC_AXI_A_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define AXI2MC_AXI_A_ABURST_ROW                 0
+#define AXI2MC_AXI_A_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define AXI2MC_AXI_A_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_A_ALOCK_SHIFT)
+#define AXI2MC_AXI_A_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define AXI2MC_AXI_A_ALOCK_ROW                  0
+#define AXI2MC_AXI_A_ALOCK_NORMAL                       _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ALOCK_EXCLUSIVE                    _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ALOCK_LOCKED                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ALOCK_RSVD                 _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_A_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define AXI2MC_AXI_A_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << AXI2MC_AXI_A_ACACHE_SHIFT)
+#define AXI2MC_AXI_A_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define AXI2MC_AXI_A_ACACHE_ROW                 0
+#define AXI2MC_AXI_A_ACACHE_NONCACHEABLE_NONBUFFERABLE                  _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_ACACHE_BUFFERABLE                  _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_DONOTALLOCATE                     _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLE_BUFFERABLE_DONOTALLOCATE                  _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREAD                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREAD                   _MK_ENUM_CONST(7)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONWRITE                       _MK_ENUM_CONST(10)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONWRITE                  _MK_ENUM_CONST(11)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITETHROUGH_ALLOCATEONREADWRITE                   _MK_ENUM_CONST(14)
+#define AXI2MC_AXI_A_ACACHE_CACHEABLEWRITEBACK_ALLOCATEONREADWRITE                      _MK_ENUM_CONST(15)
+
+#define AXI2MC_AXI_A_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define AXI2MC_AXI_A_APROT_FIELD                        (_MK_MASK_CONST(0x7) << AXI2MC_AXI_A_APROT_SHIFT)
+#define AXI2MC_AXI_A_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define AXI2MC_AXI_A_APROT_ROW                  0
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_NORMAL                   _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_A_APROT_DATA_SECURE_PRIVILEGED                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_NORMAL                        _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_A_APROT_DATA_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(3)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_NORMAL                   _MK_ENUM_CONST(4)
+#define AXI2MC_AXI_A_APROT_INST_SECURE_PRIVILEGED                       _MK_ENUM_CONST(5)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_NORMAL                        _MK_ENUM_CONST(6)
+#define AXI2MC_AXI_A_APROT_INST_NONSECURE_PRIVILEGED                    _MK_ENUM_CONST(7)
+
+
+// Packet AXI2MC_AXI_W
+#define AXI2MC_AXI_W_SIZE 302
+
+#define AXI2MC_AXI_W_WDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WDATA_SHIFT)
+#define AXI2MC_AXI_W_WDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_W_WDATA_ROW                  0
+
+#define AXI2MC_AXI_W_WID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_W_WID_SHIFT)
+#define AXI2MC_AXI_W_WID_RANGE                  _MK_SHIFT_CONST(268):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_W_WID_ROW                    0
+
+#define AXI2MC_AXI_W_WSTRB_SHIFT                        _MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_W_WSTRB_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_W_WSTRB_SHIFT)
+#define AXI2MC_AXI_W_WSTRB_RANGE                        _MK_SHIFT_CONST(300):_MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_W_WSTRB_ROW                  0
+
+#define AXI2MC_AXI_W_WLAST_SHIFT                        _MK_SHIFT_CONST(301)
+#define AXI2MC_AXI_W_WLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_W_WLAST_SHIFT)
+#define AXI2MC_AXI_W_WLAST_RANGE                        _MK_SHIFT_CONST(301):_MK_SHIFT_CONST(301)
+#define AXI2MC_AXI_W_WLAST_ROW                  0
+#define AXI2MC_AXI_W_WLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_W_WLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet AXI2MC_AXI_B
+#define AXI2MC_AXI_B_SIZE 15
+
+#define AXI2MC_AXI_B_BID_SHIFT                  _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_B_BID_SHIFT)
+#define AXI2MC_AXI_B_BID_RANGE                  _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_B_BID_ROW                    0
+
+#define AXI2MC_AXI_B_BRESP_SHIFT                        _MK_SHIFT_CONST(13)
+#define AXI2MC_AXI_B_BRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_B_BRESP_SHIFT)
+#define AXI2MC_AXI_B_BRESP_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(13)
+#define AXI2MC_AXI_B_BRESP_ROW                  0
+#define AXI2MC_AXI_B_BRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_B_BRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_B_BRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_B_BRESP_DECERR                       _MK_ENUM_CONST(3)
+
+
+// Packet AXI2MC_AXI_R
+#define AXI2MC_AXI_R_SIZE 272
+
+#define AXI2MC_AXI_R_RDATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_FIELD                        (_MK_MASK_CONST(0xffffffff) << AXI2MC_AXI_R_RDATA_SHIFT)
+#define AXI2MC_AXI_R_RDATA_RANGE                        _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define AXI2MC_AXI_R_RDATA_ROW                  0
+
+#define AXI2MC_AXI_R_RID_SHIFT                  _MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_FIELD                  (_MK_MASK_CONST(0x1fff) << AXI2MC_AXI_R_RID_SHIFT)
+#define AXI2MC_AXI_R_RID_RANGE                  _MK_SHIFT_CONST(268):_MK_SHIFT_CONST(256)
+#define AXI2MC_AXI_R_RID_ROW                    0
+
+#define AXI2MC_AXI_R_RRESP_SHIFT                        _MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_R_RRESP_FIELD                        (_MK_MASK_CONST(0x3) << AXI2MC_AXI_R_RRESP_SHIFT)
+#define AXI2MC_AXI_R_RRESP_RANGE                        _MK_SHIFT_CONST(270):_MK_SHIFT_CONST(269)
+#define AXI2MC_AXI_R_RRESP_ROW                  0
+#define AXI2MC_AXI_R_RRESP_OKAY                 _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RRESP_EXOKAY                       _MK_ENUM_CONST(1)
+#define AXI2MC_AXI_R_RRESP_SLVERR                       _MK_ENUM_CONST(2)
+#define AXI2MC_AXI_R_RRESP_DECERR                       _MK_ENUM_CONST(3)
+
+#define AXI2MC_AXI_R_RLAST_SHIFT                        _MK_SHIFT_CONST(271)
+#define AXI2MC_AXI_R_RLAST_FIELD                        (_MK_MASK_CONST(0x1) << AXI2MC_AXI_R_RLAST_SHIFT)
+#define AXI2MC_AXI_R_RLAST_RANGE                        _MK_SHIFT_CONST(271):_MK_SHIFT_CONST(271)
+#define AXI2MC_AXI_R_RLAST_ROW                  0
+#define AXI2MC_AXI_R_RLAST_DISABLED                     _MK_ENUM_CONST(0)
+#define AXI2MC_AXI_R_RLAST_ENABLED                      _MK_ENUM_CONST(1)
+
+
+// Packet MC_AXI_RWREQ
+#define MC_AXI_RWREQ_SIZE 112
+
+#define MC_AXI_RWREQ_AADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_AADDR_SHIFT)
+#define MC_AXI_RWREQ_AADDR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define MC_AXI_RWREQ_AADDR_ROW                  0
+
+#define MC_AXI_RWREQ_AID_SHIFT                  _MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_FIELD                  (_MK_MASK_CONST(0x1fff) << MC_AXI_RWREQ_AID_SHIFT)
+#define MC_AXI_RWREQ_AID_RANGE                  _MK_SHIFT_CONST(44):_MK_SHIFT_CONST(32)
+#define MC_AXI_RWREQ_AID_ROW                    0
+
+#define MC_AXI_RWREQ_ALEN_SHIFT                 _MK_SHIFT_CONST(45)
+#define MC_AXI_RWREQ_ALEN_FIELD                 (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ALEN_RANGE                 _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(45)
+#define MC_AXI_RWREQ_ALEN_ROW                   0
+
+#define MC_AXI_RWREQ_ASIZE_SHIFT                        _MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ASIZE_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ASIZE_RANGE                        _MK_SHIFT_CONST(51):_MK_SHIFT_CONST(49)
+#define MC_AXI_RWREQ_ASIZE_ROW                  2
+
+#define MC_AXI_RWREQ_ABURST_SHIFT                       _MK_SHIFT_CONST(52)
+#define MC_AXI_RWREQ_ABURST_FIELD                       (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ABURST_SHIFT)
+#define MC_AXI_RWREQ_ABURST_RANGE                       _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(52)
+#define MC_AXI_RWREQ_ABURST_ROW                 0
+#define MC_AXI_RWREQ_ABURST_FIXED                       _MK_ENUM_CONST(0)
+#define MC_AXI_RWREQ_ABURST_INCR                        _MK_ENUM_CONST(1)
+#define MC_AXI_RWREQ_ABURST_WRAP                        _MK_ENUM_CONST(2)
+#define MC_AXI_RWREQ_ABURST_RSVD                        _MK_ENUM_CONST(3)
+
+#define MC_AXI_RWREQ_ALOCK_SHIFT                        _MK_SHIFT_CONST(54)
+#define MC_AXI_RWREQ_ALOCK_FIELD                        (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ALOCK_SHIFT)
+#define MC_AXI_RWREQ_ALOCK_RANGE                        _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(54)
+#define MC_AXI_RWREQ_ALOCK_ROW                  0
+
+#define MC_AXI_RWREQ_ACACHE_SHIFT                       _MK_SHIFT_CONST(56)
+#define MC_AXI_RWREQ_ACACHE_FIELD                       (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACACHE_SHIFT)
+#define MC_AXI_RWREQ_ACACHE_RANGE                       _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(56)
+#define MC_AXI_RWREQ_ACACHE_ROW                 0
+
+#define MC_AXI_RWREQ_APROT_SHIFT                        _MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_APROT_FIELD                        (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_APROT_SHIFT)
+#define MC_AXI_RWREQ_APROT_RANGE                        _MK_SHIFT_CONST(62):_MK_SHIFT_CONST(60)
+#define MC_AXI_RWREQ_APROT_ROW                  0
+
+#define MC_AXI_RWREQ_ASB_SHIFT                  _MK_SHIFT_CONST(63)
+#define MC_AXI_RWREQ_ASB_FIELD                  (_MK_MASK_CONST(0x3) << MC_AXI_RWREQ_ASB_SHIFT)
+#define MC_AXI_RWREQ_ASB_RANGE                  _MK_SHIFT_CONST(64):_MK_SHIFT_CONST(63)
+#define MC_AXI_RWREQ_ASB_ROW                    0
+
+#define MC_AXI_RWREQ_ARW_SHIFT                  _MK_SHIFT_CONST(65)
+#define MC_AXI_RWREQ_ARW_FIELD                  (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ARW_SHIFT)
+#define MC_AXI_RWREQ_ARW_RANGE                  _MK_SHIFT_CONST(65):_MK_SHIFT_CONST(65)
+#define MC_AXI_RWREQ_ARW_ROW                    0
+
+#define MC_AXI_RWREQ_ACT_AADDR_SHIFT                    _MK_SHIFT_CONST(66)
+#define MC_AXI_RWREQ_ACT_AADDR_FIELD                    (_MK_MASK_CONST(0xffffffff) << MC_AXI_RWREQ_ACT_AADDR_SHIFT)
+#define MC_AXI_RWREQ_ACT_AADDR_RANGE                    _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(66)
+#define MC_AXI_RWREQ_ACT_AADDR_ROW                      0
+
+#define MC_AXI_RWREQ_ACT_ALEN_SHIFT                     _MK_SHIFT_CONST(98)
+#define MC_AXI_RWREQ_ACT_ALEN_FIELD                     (_MK_MASK_CONST(0xf) << MC_AXI_RWREQ_ACT_ALEN_SHIFT)
+#define MC_AXI_RWREQ_ACT_ALEN_RANGE                     _MK_SHIFT_CONST(101):_MK_SHIFT_CONST(98)
+#define MC_AXI_RWREQ_ACT_ALEN_ROW                       0
+
+#define MC_AXI_RWREQ_ACT_ASIZE_SHIFT                    _MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_ACT_ASIZE_FIELD                    (_MK_MASK_CONST(0x7) << MC_AXI_RWREQ_ACT_ASIZE_SHIFT)
+#define MC_AXI_RWREQ_ACT_ASIZE_RANGE                    _MK_SHIFT_CONST(104):_MK_SHIFT_CONST(102)
+#define MC_AXI_RWREQ_ACT_ASIZE_ROW                      0
+
+#define MC_AXI_RWREQ_DOUBLEREQ_SHIFT                    _MK_SHIFT_CONST(105)
+#define MC_AXI_RWREQ_DOUBLEREQ_FIELD                    (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_DOUBLEREQ_SHIFT)
+#define MC_AXI_RWREQ_DOUBLEREQ_RANGE                    _MK_SHIFT_CONST(105):_MK_SHIFT_CONST(105)
+#define MC_AXI_RWREQ_DOUBLEREQ_ROW                      0
+
+#define MC_AXI_RWREQ_ILLEGALACC_SHIFT                   _MK_SHIFT_CONST(106)
+#define MC_AXI_RWREQ_ILLEGALACC_FIELD                   (_MK_MASK_CONST(0x1) << MC_AXI_RWREQ_ILLEGALACC_SHIFT)
+#define MC_AXI_RWREQ_ILLEGALACC_RANGE                   _MK_SHIFT_CONST(106):_MK_SHIFT_CONST(106)
+#define MC_AXI_RWREQ_ILLEGALACC_ROW                     0
+
+#define MC_AXI_RWREQ_TAG_SHIFT                  _MK_SHIFT_CONST(107)
+#define MC_AXI_RWREQ_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << MC_AXI_RWREQ_TAG_SHIFT)
+#define MC_AXI_RWREQ_TAG_RANGE                  _MK_SHIFT_CONST(111):_MK_SHIFT_CONST(107)
+#define MC_AXI_RWREQ_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_RESET
+#define CSR_C2MC_RESET_SIZE 1
+
+#define CSR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_RESET_RSTN_SHIFT)
+#define CSR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSR_C2MC_REQ
+#define CSR_C2MC_REQ_SIZE 32
+
+#define CSR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_REQ_ADR_SHIFT)
+#define CSR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_REQ_ADR_ROW                    0
+
+
+// Packet CSR_C2MC_SIZE
+#define CSR_C2MC_SIZE_SIZE 1
+
+#define CSR_C2MC_SIZE_SIZE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSR_C2MC_SIZE_SIZE_FIELD                        (_MK_MASK_CONST(0x1) << CSR_C2MC_SIZE_SIZE_SHIFT)
+#define CSR_C2MC_SIZE_SIZE_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_SIZE_SIZE_ROW                  0
+
+
+// Packet CSR_C2MC_SECURE
+#define CSR_C2MC_SECURE_SIZE 1
+
+#define CSR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CSR_C2MC_SECURE_SECURE_SHIFT)
+#define CSR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CSR_C2MC_TAG
+#define CSR_C2MC_TAG_SIZE 5
+
+#define CSR_C2MC_TAG_TAG_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TAG_TAG_FIELD                  (_MK_MASK_CONST(0x1f) << CSR_C2MC_TAG_TAG_SHIFT)
+#define CSR_C2MC_TAG_TAG_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TAG_TAG_ROW                    0
+
+
+// Packet CSR_C2MC_BP_REQ
+#define CSR_C2MC_BP_REQ_SIZE 48
+
+#define CSR_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSR_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSR_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSR_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSR_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_BP_REQ_PITCH_ROW                       0
+
+
+// Packet CSR_C2MC_ADRXY
+#define CSR_C2MC_ADRXY_SIZE 30
+
+#define CSR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSR_C2MC_ADRXY_OFFX_SHIFT)
+#define CSR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSR_C2MC_ADRXY_OFFY_SHIFT)
+#define CSR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSR_C2MC_TILE
+#define CSR_C2MC_TILE_SIZE 33
+
+#define CSR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_TILE_LINADR_SHIFT)
+#define CSR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_TILE_LINADR_ROW                        0
+
+#define CSR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSR_C2MC_TILE_TMODE_SHIFT)
+#define CSR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_TILE_TMODE_ROW                 0
+#define CSR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSR_C2MC_RDI
+#define CSR_C2MC_RDI_SIZE 256
+
+#define CSR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_RDI_RDI_SHIFT)
+#define CSR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CSR_C2MC_HP
+#define CSR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CSR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSR_C2MC_HP_HPTH_SHIFT)
+#define CSR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CSR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CSR_C2MC_HP_HPTM_SHIFT)
+#define CSR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CSR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CSR_C2MC_HYST
+#define CSR_C2MC_HYST_SIZE 32
+
+#define CSR_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSR_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CSR_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSR_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CSR_C2MC_HYST_DHYST_TM_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSR_C2MC_HYST_DHYST_TM_FIELD                    (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_DHYST_TM_SHIFT)
+#define CSR_C2MC_HYST_DHYST_TM_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSR_C2MC_HYST_DHYST_TM_ROW                      0
+
+#define CSR_C2MC_HYST_DHYST_TH_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSR_C2MC_HYST_DHYST_TH_FIELD                    (_MK_MASK_CONST(0xff) << CSR_C2MC_HYST_DHYST_TH_SHIFT)
+#define CSR_C2MC_HYST_DHYST_TH_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSR_C2MC_HYST_DHYST_TH_ROW                      0
+
+#define CSR_C2MC_HYST_HYST_TM_SHIFT                     _MK_SHIFT_CONST(24)
+#define CSR_C2MC_HYST_HYST_TM_FIELD                     (_MK_MASK_CONST(0xf) << CSR_C2MC_HYST_HYST_TM_SHIFT)
+#define CSR_C2MC_HYST_HYST_TM_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define CSR_C2MC_HYST_HYST_TM_ROW                       0
+
+#define CSR_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CSR_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CSR_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CSR_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CSR_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CSR_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CSR_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CSR_C2MC_HYST_HYST_EN_SHIFT)
+#define CSR_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CSR_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CSW_C2MC_RESET
+#define CSW_C2MC_RESET_SIZE 1
+
+#define CSW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_RESET_RSTN_SHIFT)
+#define CSW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CSW_C2MC_REQ
+#define CSW_C2MC_REQ_SIZE 321
+
+#define CSW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_ADR_SHIFT)
+#define CSW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_REQ_ADR_ROW                    0
+
+#define CSW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_BE_SHIFT)
+#define CSW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_REQ_BE_ROW                     0
+
+#define CSW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_REQ_WDO_SHIFT)
+#define CSW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CSW_C2MC_REQ_WDO_ROW                    0
+
+#define CSW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CSW_C2MC_REQ_TAG_SHIFT)
+#define CSW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CSW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CSW_C2MC_SECURE
+#define CSW_C2MC_SECURE_SIZE 1
+
+#define CSW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CSW_C2MC_SECURE_SECURE_SHIFT)
+#define CSW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CSW_C2MC_BP_REQ
+#define CSW_C2MC_BP_REQ_SIZE 337
+
+#define CSW_C2MC_BP_REQ_BASEADR_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BASEADR_SHIFT)
+#define CSW_C2MC_BP_REQ_BASEADR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_BP_REQ_BASEADR_ROW                     0
+
+#define CSW_C2MC_BP_REQ_PITCH_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_FIELD                     (_MK_MASK_CONST(0xffff) << CSW_C2MC_BP_REQ_PITCH_SHIFT)
+#define CSW_C2MC_BP_REQ_PITCH_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_BP_REQ_PITCH_ROW                       0
+
+#define CSW_C2MC_BP_REQ_BE_SHIFT                        _MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_BE_SHIFT)
+#define CSW_C2MC_BP_REQ_BE_RANGE                        _MK_SHIFT_CONST(79):_MK_SHIFT_CONST(48)
+#define CSW_C2MC_BP_REQ_BE_ROW                  0
+
+#define CSW_C2MC_BP_REQ_WDO_SHIFT                       _MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_FIELD                       (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_BP_REQ_WDO_SHIFT)
+#define CSW_C2MC_BP_REQ_WDO_RANGE                       _MK_SHIFT_CONST(335):_MK_SHIFT_CONST(80)
+#define CSW_C2MC_BP_REQ_WDO_ROW                 0
+
+#define CSW_C2MC_BP_REQ_TAG_SHIFT                       _MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_BP_REQ_TAG_SHIFT)
+#define CSW_C2MC_BP_REQ_TAG_RANGE                       _MK_SHIFT_CONST(336):_MK_SHIFT_CONST(336)
+#define CSW_C2MC_BP_REQ_TAG_ROW                 0
+
+
+// Packet CSW_C2MC_ADRXY
+#define CSW_C2MC_ADRXY_SIZE 30
+
+#define CSW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CSW_C2MC_ADRXY_OFFX_SHIFT)
+#define CSW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CSW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CSW_C2MC_ADRXY_OFFY_SHIFT)
+#define CSW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CSW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CSW_C2MC_TILE
+#define CSW_C2MC_TILE_SIZE 33
+
+#define CSW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_TILE_LINADR_SHIFT)
+#define CSW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_TILE_LINADR_ROW                        0
+
+#define CSW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CSW_C2MC_TILE_TMODE_SHIFT)
+#define CSW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CSW_C2MC_TILE_TMODE_ROW                 0
+#define CSW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CSW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CSW_C2MC_XDI
+#define CSW_C2MC_XDI_SIZE 32
+
+// sometimes fake data
+#define CSW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_XDI_XDI_SHIFT)
+#define CSW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CSW_C2MC_HP
+#define CSW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CSW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HP_HPTH_SHIFT)
+#define CSW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CSW_C2MC_WCOAL
+#define CSW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CSW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CSW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CSW_C2MC_HYST
+#define CSW_C2MC_HYST_SIZE 32
+
+// hysteresis control register
+#define CSW_C2MC_HYST_HYST_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSW_C2MC_HYST_HYST_FIELD                        (_MK_MASK_CONST(0xffffffff) << CSW_C2MC_HYST_HYST_SHIFT)
+#define CSW_C2MC_HYST_HYST_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CSW_C2MC_HYST_HYST_ROW                  0
+
+
+// Packet CBR_C2MC_RESET
+#define CBR_C2MC_RESET_SIZE 1
+
+#define CBR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RESET_RSTN_SHIFT)
+#define CBR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBR_C2MC_REQP
+#define CBR_C2MC_REQP_SIZE 263
+
+#define CBR_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADR_SHIFT)
+#define CBR_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_REQP_ADR_ROW                   0
+
+#define CBR_C2MC_REQP_ADRU_SHIFT                        _MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRU_SHIFT)
+#define CBR_C2MC_REQP_ADRU_RANGE                        _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_REQP_ADRU_ROW                  0
+
+#define CBR_C2MC_REQP_ADRV_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_ADRV_SHIFT)
+#define CBR_C2MC_REQP_ADRV_RANGE                        _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_REQP_ADRV_ROW                  0
+
+#define CBR_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LS_SHIFT)
+#define CBR_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_REQP_LS_ROW                    0
+
+#define CBR_C2MC_REQP_LSUV_SHIFT                        _MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_LSUV_SHIFT)
+#define CBR_C2MC_REQP_LSUV_RANGE                        _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CBR_C2MC_REQP_LSUV_ROW                  0
+
+#define CBR_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_HS_SHIFT)
+#define CBR_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(191):_MK_SHIFT_CONST(160)
+#define CBR_C2MC_REQP_HS_ROW                    0
+
+#define CBR_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_VS_SHIFT)
+#define CBR_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(223):_MK_SHIFT_CONST(192)
+#define CBR_C2MC_REQP_VS_ROW                    0
+
+#define CBR_C2MC_REQP_DL_SHIFT                  _MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_REQP_DL_SHIFT)
+#define CBR_C2MC_REQP_DL_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(224)
+#define CBR_C2MC_REQP_DL_ROW                    0
+
+#define CBR_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_HD_SHIFT)
+#define CBR_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_REQP_HD_ROW                    0
+
+#define CBR_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VD_SHIFT)
+#define CBR_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(257):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_REQP_VD_ROW                    0
+
+#define CBR_C2MC_REQP_VX2_SHIFT                 _MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_VX2_SHIFT)
+#define CBR_C2MC_REQP_VX2_RANGE                 _MK_SHIFT_CONST(258):_MK_SHIFT_CONST(258)
+#define CBR_C2MC_REQP_VX2_ROW                   0
+
+#define CBR_C2MC_REQP_LP_SHIFT                  _MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_FIELD                  (_MK_MASK_CONST(0x1) << CBR_C2MC_REQP_LP_SHIFT)
+#define CBR_C2MC_REQP_LP_RANGE                  _MK_SHIFT_CONST(259):_MK_SHIFT_CONST(259)
+#define CBR_C2MC_REQP_LP_ROW                    0
+
+#define CBR_C2MC_REQP_YUV_SHIFT                 _MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_REQP_YUV_SHIFT)
+#define CBR_C2MC_REQP_YUV_RANGE                 _MK_SHIFT_CONST(262):_MK_SHIFT_CONST(260)
+#define CBR_C2MC_REQP_YUV_ROW                   0
+
+
+// Packet CBR_C2MC_SECURE
+#define CBR_C2MC_SECURE_SIZE 1
+
+#define CBR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_SECURE_SECURE_SHIFT)
+#define CBR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CBR_C2MC_ADRXY
+#define CBR_C2MC_ADRXY_SIZE 44
+
+#define CBR_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_ADRXY_OFFX_SHIFT)
+#define CBR_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFY_SHIFT)
+#define CBR_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_ADRXY_OFFY_ROW                 0
+
+#define CBR_C2MC_ADRXY_OFFYUV_SHIFT                     _MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_FIELD                     (_MK_MASK_CONST(0x3fff) << CBR_C2MC_ADRXY_OFFYUV_SHIFT)
+#define CBR_C2MC_ADRXY_OFFYUV_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(30)
+#define CBR_C2MC_ADRXY_OFFYUV_ROW                       0
+
+
+// Packet CBR_C2MC_TILE
+#define CBR_C2MC_TILE_SIZE 98
+
+#define CBR_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADR_SHIFT)
+#define CBR_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_TILE_LINADR_ROW                        0
+
+#define CBR_C2MC_TILE_LINADRU_SHIFT                     _MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRU_SHIFT)
+#define CBR_C2MC_TILE_LINADRU_RANGE                     _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_TILE_LINADRU_ROW                       0
+
+#define CBR_C2MC_TILE_LINADRV_SHIFT                     _MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_FIELD                     (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_TILE_LINADRV_SHIFT)
+#define CBR_C2MC_TILE_LINADRV_RANGE                     _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBR_C2MC_TILE_LINADRV_ROW                       0
+
+#define CBR_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODE_SHIFT)
+#define CBR_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(96):_MK_SHIFT_CONST(96)
+#define CBR_C2MC_TILE_TMODE_ROW                 0
+#define CBR_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+#define CBR_C2MC_TILE_TMODEUV_SHIFT                     _MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_TILE_TMODEUV_SHIFT)
+#define CBR_C2MC_TILE_TMODEUV_RANGE                     _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(97)
+#define CBR_C2MC_TILE_TMODEUV_ROW                       0
+#define CBR_C2MC_TILE_TMODEUV_LINEAR                    _MK_ENUM_CONST(0)
+#define CBR_C2MC_TILE_TMODEUV_TILED                     _MK_ENUM_CONST(1)
+
+
+// Packet CBR_C2MC_RDYP
+#define CBR_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBR_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_RDYP_RDYP_SHIFT)
+#define CBR_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBR_C2MC_OUTSTD
+#define CBR_C2MC_OUTSTD_SIZE 1
+
+#define CBR_C2MC_OUTSTD_OUTSTD_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_FIELD                    (_MK_MASK_CONST(0x1) << CBR_C2MC_OUTSTD_OUTSTD_SHIFT)
+#define CBR_C2MC_OUTSTD_OUTSTD_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_OUTSTD_OUTSTD_ROW                      0
+
+
+// Packet CBR_C2MC_STOP
+#define CBR_C2MC_STOP_SIZE 1
+
+#define CBR_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBR_C2MC_STOP_STOP_SHIFT)
+#define CBR_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBR_C2MC_RDI
+#define CBR_C2MC_RDI_SIZE 262
+
+#define CBR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_RDI_RDI_SHIFT)
+#define CBR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_RDI_RDI_ROW                    0
+
+#define CBR_C2MC_RDI_RDILST_SHIFT                       _MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_FIELD                       (_MK_MASK_CONST(0x1) << CBR_C2MC_RDI_RDILST_SHIFT)
+#define CBR_C2MC_RDI_RDILST_RANGE                       _MK_SHIFT_CONST(256):_MK_SHIFT_CONST(256)
+#define CBR_C2MC_RDI_RDILST_ROW                 0
+
+#define CBR_C2MC_RDI_RDINB_SHIFT                        _MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_FIELD                        (_MK_MASK_CONST(0x1f) << CBR_C2MC_RDI_RDINB_SHIFT)
+#define CBR_C2MC_RDI_RDINB_RANGE                        _MK_SHIFT_CONST(261):_MK_SHIFT_CONST(257)
+#define CBR_C2MC_RDI_RDINB_ROW                  0
+
+
+// Packet CBR_C2MC_DOREQ
+#define CBR_C2MC_DOREQ_SIZE 64
+
+#define CBR_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_ADR_SHIFT)
+#define CBR_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBR_C2MC_DOREQ_LS_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_DOREQ_LS_SHIFT)
+#define CBR_C2MC_DOREQ_LS_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_DOREQ_LS_ROW                   0
+
+
+// Packet CBR_C2MC_HP
+#define CBR_C2MC_HP_SIZE 71
+
+// high-priority threshold
+#define CBR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBR_C2MC_HP_HPTH_SHIFT)
+#define CBR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CBR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CBR_C2MC_HP_HPTM_SHIFT)
+#define CBR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CBR_C2MC_HP_HPTM_ROW                    0
+
+// suppression - start of frame
+#define CBR_C2MC_HP_HPSOF_SHIFT                 _MK_SHIFT_CONST(38)
+#define CBR_C2MC_HP_HPSOF_FIELD                 (_MK_MASK_CONST(0x1) << CBR_C2MC_HP_HPSOF_SHIFT)
+#define CBR_C2MC_HP_HPSOF_RANGE                 _MK_SHIFT_CONST(38):_MK_SHIFT_CONST(38)
+#define CBR_C2MC_HP_HPSOF_ROW                   0
+
+// suppression - cycles per word
+#define CBR_C2MC_HP_HPCPW_SHIFT                 _MK_SHIFT_CONST(39)
+#define CBR_C2MC_HP_HPCPW_FIELD                 (_MK_MASK_CONST(0xffff) << CBR_C2MC_HP_HPCPW_SHIFT)
+#define CBR_C2MC_HP_HPCPW_RANGE                 _MK_SHIFT_CONST(54):_MK_SHIFT_CONST(39)
+#define CBR_C2MC_HP_HPCPW_ROW                   0
+
+// suppression - words per line
+#define CBR_C2MC_HP_HPCBNPW_SHIFT                       _MK_SHIFT_CONST(55)
+#define CBR_C2MC_HP_HPCBNPW_FIELD                       (_MK_MASK_CONST(0xffff) << CBR_C2MC_HP_HPCBNPW_SHIFT)
+#define CBR_C2MC_HP_HPCBNPW_RANGE                       _MK_SHIFT_CONST(70):_MK_SHIFT_CONST(55)
+#define CBR_C2MC_HP_HPCBNPW_ROW                 0
+
+
+// Packet CBR_C2MC_HYST
+#define CBR_C2MC_HYST_SIZE 32
+
+#define CBR_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBR_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CBR_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CBR_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CBR_C2MC_HYST_DHYST_TM_SHIFT                    _MK_SHIFT_CONST(8)
+#define CBR_C2MC_HYST_DHYST_TM_FIELD                    (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_DHYST_TM_SHIFT)
+#define CBR_C2MC_HYST_DHYST_TM_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CBR_C2MC_HYST_DHYST_TM_ROW                      0
+
+#define CBR_C2MC_HYST_DHYST_TH_SHIFT                    _MK_SHIFT_CONST(16)
+#define CBR_C2MC_HYST_DHYST_TH_FIELD                    (_MK_MASK_CONST(0xff) << CBR_C2MC_HYST_DHYST_TH_SHIFT)
+#define CBR_C2MC_HYST_DHYST_TH_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CBR_C2MC_HYST_DHYST_TH_ROW                      0
+
+#define CBR_C2MC_HYST_HYST_TM_SHIFT                     _MK_SHIFT_CONST(24)
+#define CBR_C2MC_HYST_HYST_TM_FIELD                     (_MK_MASK_CONST(0xf) << CBR_C2MC_HYST_HYST_TM_SHIFT)
+#define CBR_C2MC_HYST_HYST_TM_RANGE                     _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(24)
+#define CBR_C2MC_HYST_HYST_TM_ROW                       0
+
+#define CBR_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CBR_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CBR_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CBR_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CBR_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CBR_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CBR_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CBR_C2MC_HYST_HYST_EN_SHIFT)
+#define CBR_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CBR_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CBW_C2MC_RESET
+#define CBW_C2MC_RESET_SIZE 1
+
+#define CBW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_RESET_RSTN_SHIFT)
+#define CBW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CBW_C2MC_REQP
+#define CBW_C2MC_REQP_SIZE 134
+
+#define CBW_C2MC_REQP_ADR_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_ADR_SHIFT)
+#define CBW_C2MC_REQP_ADR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_REQP_ADR_ROW                   0
+
+#define CBW_C2MC_REQP_LS_SHIFT                  _MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_LS_SHIFT)
+#define CBW_C2MC_REQP_LS_RANGE                  _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_REQP_LS_ROW                    0
+
+#define CBW_C2MC_REQP_HS_SHIFT                  _MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_HS_SHIFT)
+#define CBW_C2MC_REQP_HS_RANGE                  _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_REQP_HS_ROW                    0
+
+#define CBW_C2MC_REQP_VS_SHIFT                  _MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_REQP_VS_SHIFT)
+#define CBW_C2MC_REQP_VS_RANGE                  _MK_SHIFT_CONST(127):_MK_SHIFT_CONST(96)
+#define CBW_C2MC_REQP_VS_ROW                    0
+
+#define CBW_C2MC_REQP_HD_SHIFT                  _MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_HD_SHIFT)
+#define CBW_C2MC_REQP_HD_RANGE                  _MK_SHIFT_CONST(128):_MK_SHIFT_CONST(128)
+#define CBW_C2MC_REQP_HD_ROW                    0
+
+#define CBW_C2MC_REQP_VD_SHIFT                  _MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_VD_SHIFT)
+#define CBW_C2MC_REQP_VD_RANGE                  _MK_SHIFT_CONST(129):_MK_SHIFT_CONST(129)
+#define CBW_C2MC_REQP_VD_ROW                    0
+
+#define CBW_C2MC_REQP_BPP_SHIFT                 _MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_FIELD                 (_MK_MASK_CONST(0x3) << CBW_C2MC_REQP_BPP_SHIFT)
+#define CBW_C2MC_REQP_BPP_RANGE                 _MK_SHIFT_CONST(131):_MK_SHIFT_CONST(130)
+#define CBW_C2MC_REQP_BPP_ROW                   0
+
+#define CBW_C2MC_REQP_XY_SHIFT                  _MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_XY_SHIFT)
+#define CBW_C2MC_REQP_XY_RANGE                  _MK_SHIFT_CONST(132):_MK_SHIFT_CONST(132)
+#define CBW_C2MC_REQP_XY_ROW                    0
+
+#define CBW_C2MC_REQP_PK_SHIFT                  _MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_REQP_PK_SHIFT)
+#define CBW_C2MC_REQP_PK_RANGE                  _MK_SHIFT_CONST(133):_MK_SHIFT_CONST(133)
+#define CBW_C2MC_REQP_PK_ROW                    0
+
+
+// Packet CBW_C2MC_SECURE
+#define CBW_C2MC_SECURE_SIZE 1
+
+#define CBW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CBW_C2MC_SECURE_SECURE_SHIFT)
+#define CBW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CBW_C2MC_ADRXY
+#define CBW_C2MC_ADRXY_SIZE 30
+
+#define CBW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CBW_C2MC_ADRXY_OFFX_SHIFT)
+#define CBW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CBW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CBW_C2MC_ADRXY_OFFY_SHIFT)
+#define CBW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CBW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CBW_C2MC_TILE
+#define CBW_C2MC_TILE_SIZE 33
+
+#define CBW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_TILE_LINADR_SHIFT)
+#define CBW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_TILE_LINADR_ROW                        0
+
+#define CBW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CBW_C2MC_TILE_TMODE_SHIFT)
+#define CBW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_TILE_TMODE_ROW                 0
+#define CBW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CBW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CBW_C2MC_RDYP
+#define CBW_C2MC_RDYP_SIZE 1
+
+// fake data
+#define CBW_C2MC_RDYP_RDYP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_RDYP_RDYP_SHIFT)
+#define CBW_C2MC_RDYP_RDYP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_RDYP_RDYP_ROW                  0
+
+
+// Packet CBW_C2MC_STOP
+#define CBW_C2MC_STOP_SIZE 1
+
+#define CBW_C2MC_STOP_STOP_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_STOP_STOP_SHIFT)
+#define CBW_C2MC_STOP_STOP_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_STOP_STOP_ROW                  0
+
+
+// Packet CBW_C2MC_XDI
+#define CBW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CBW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CBW_C2MC_XDI_XDI_SHIFT)
+#define CBW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CBW_C2MC_DOREQ
+#define CBW_C2MC_DOREQ_SIZE 321
+
+#define CBW_C2MC_DOREQ_ADR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_ADR_SHIFT)
+#define CBW_C2MC_DOREQ_ADR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_DOREQ_ADR_ROW                  0
+
+#define CBW_C2MC_DOREQ_BE_SHIFT                 _MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_FIELD                 (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_BE_SHIFT)
+#define CBW_C2MC_DOREQ_BE_RANGE                 _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CBW_C2MC_DOREQ_BE_ROW                   0
+
+#define CBW_C2MC_DOREQ_WDO_SHIFT                        _MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_FIELD                        (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_DOREQ_WDO_SHIFT)
+#define CBW_C2MC_DOREQ_WDO_RANGE                        _MK_SHIFT_CONST(319):_MK_SHIFT_CONST(64)
+#define CBW_C2MC_DOREQ_WDO_ROW                  0
+
+#define CBW_C2MC_DOREQ_TAG_SHIFT                        _MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_FIELD                        (_MK_MASK_CONST(0x1) << CBW_C2MC_DOREQ_TAG_SHIFT)
+#define CBW_C2MC_DOREQ_TAG_RANGE                        _MK_SHIFT_CONST(320):_MK_SHIFT_CONST(320)
+#define CBW_C2MC_DOREQ_TAG_ROW                  0
+
+
+// Packet CBW_C2MC_HP
+#define CBW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CBW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_HP_HPTH_SHIFT)
+#define CBW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CBW_C2MC_WCOAL
+#define CBW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CBW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CBW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CBW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CBW_C2MC_HYST
+#define CBW_C2MC_HYST_SIZE 32
+
+#define CBW_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CBW_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xfff) << CBW_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CBW_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define CBW_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CBW_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CBW_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CBW_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CBW_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CBW_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CBW_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CBW_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CBW_C2MC_HYST_HYST_EN_SHIFT)
+#define CBW_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CBW_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet CCR_C2MC_RESET
+#define CCR_C2MC_RESET_SIZE 1
+
+#define CCR_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCR_C2MC_RESET_RSTN_SHIFT)
+#define CCR_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCR_C2MC_REQ
+#define CCR_C2MC_REQ_SIZE 101
+
+#define CCR_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_ADR_SHIFT)
+#define CCR_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_REQ_ADR_ROW                    0
+
+#define CCR_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_LS_SHIFT)
+#define CCR_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCR_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_REQ_HINC_SHIFT)
+#define CCR_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCR_C2MC_REQ_HINC_ROW                   0
+
+#define CCR_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCR_C2MC_REQ_ACMD_SHIFT)
+#define CCR_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCR_C2MC_REQ_ACMD_ROW                   0
+
+#define CCR_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_LN_SHIFT)
+#define CCR_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCR_C2MC_REQ_LN_ROW                     0
+
+#define CCR_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_HD_SHIFT)
+#define CCR_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCR_C2MC_REQ_HD_ROW                     0
+
+#define CCR_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCR_C2MC_REQ_VD_SHIFT)
+#define CCR_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCR_C2MC_REQ_VD_ROW                     0
+
+
+// Packet CCR_C2MC_SECURE
+#define CCR_C2MC_SECURE_SIZE 1
+
+#define CCR_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCR_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CCR_C2MC_SECURE_SECURE_SHIFT)
+#define CCR_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CCR_C2MC_RDI
+#define CCR_C2MC_RDI_SIZE 256
+
+#define CCR_C2MC_RDI_RDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_RDI_RDI_SHIFT)
+#define CCR_C2MC_RDI_RDI_RANGE                  _MK_SHIFT_CONST(255):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_RDI_RDI_ROW                    0
+
+
+// Packet CCR_C2MC_HP
+#define CCR_C2MC_HP_SIZE 38
+
+// high-priority threshold
+#define CCR_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HP_HPTH_SHIFT)
+#define CCR_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HP_HPTH_ROW                    0
+
+// high-priority timer
+#define CCR_C2MC_HP_HPTM_SHIFT                  _MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_FIELD                  (_MK_MASK_CONST(0x3f) << CCR_C2MC_HP_HPTM_SHIFT)
+#define CCR_C2MC_HP_HPTM_RANGE                  _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CCR_C2MC_HP_HPTM_ROW                    0
+
+
+// Packet CCR_C2MC_HYST
+#define CCR_C2MC_HYST_SIZE 32
+
+// hysteresis control register
+#define CCR_C2MC_HYST_HYST_SHIFT                        _MK_SHIFT_CONST(0)
+#define CCR_C2MC_HYST_HYST_FIELD                        (_MK_MASK_CONST(0xffffffff) << CCR_C2MC_HYST_HYST_SHIFT)
+#define CCR_C2MC_HYST_HYST_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCR_C2MC_HYST_HYST_ROW                  0
+
+
+// Packet CCW_C2MC_RESET
+#define CCW_C2MC_RESET_SIZE 1
+
+#define CCW_C2MC_RESET_RSTN_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_RESET_RSTN_SHIFT)
+#define CCW_C2MC_RESET_RSTN_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_RESET_RSTN_ROW                 0
+
+
+// Packet CCW_C2MC_REQ
+#define CCW_C2MC_REQ_SIZE 417
+
+#define CCW_C2MC_REQ_ADR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_ADR_SHIFT)
+#define CCW_C2MC_REQ_ADR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_REQ_ADR_ROW                    0
+
+#define CCW_C2MC_REQ_LS_SHIFT                   _MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_LS_SHIFT)
+#define CCW_C2MC_REQ_LS_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_REQ_LS_ROW                     0
+
+// HI is apparently a reserved keyword
+#define CCW_C2MC_REQ_HINC_SHIFT                 _MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_FIELD                 (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_HINC_SHIFT)
+#define CCW_C2MC_REQ_HINC_RANGE                 _MK_SHIFT_CONST(95):_MK_SHIFT_CONST(64)
+#define CCW_C2MC_REQ_HINC_ROW                   0
+
+#define CCW_C2MC_REQ_ACMD_SHIFT                 _MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_FIELD                 (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_ACMD_SHIFT)
+#define CCW_C2MC_REQ_ACMD_RANGE                 _MK_SHIFT_CONST(97):_MK_SHIFT_CONST(96)
+#define CCW_C2MC_REQ_ACMD_ROW                   0
+
+#define CCW_C2MC_REQ_LN_SHIFT                   _MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_LN_SHIFT)
+#define CCW_C2MC_REQ_LN_RANGE                   _MK_SHIFT_CONST(98):_MK_SHIFT_CONST(98)
+#define CCW_C2MC_REQ_LN_ROW                     0
+
+#define CCW_C2MC_REQ_HD_SHIFT                   _MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_HD_SHIFT)
+#define CCW_C2MC_REQ_HD_RANGE                   _MK_SHIFT_CONST(99):_MK_SHIFT_CONST(99)
+#define CCW_C2MC_REQ_HD_ROW                     0
+
+#define CCW_C2MC_REQ_VD_SHIFT                   _MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_VD_SHIFT)
+#define CCW_C2MC_REQ_VD_RANGE                   _MK_SHIFT_CONST(100):_MK_SHIFT_CONST(100)
+#define CCW_C2MC_REQ_VD_ROW                     0
+
+#define CCW_C2MC_REQ_BPP_SHIFT                  _MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_FIELD                  (_MK_MASK_CONST(0x3) << CCW_C2MC_REQ_BPP_SHIFT)
+#define CCW_C2MC_REQ_BPP_RANGE                  _MK_SHIFT_CONST(102):_MK_SHIFT_CONST(101)
+#define CCW_C2MC_REQ_BPP_ROW                    0
+
+#define CCW_C2MC_REQ_XY_SHIFT                   _MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_FIELD                   (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_XY_SHIFT)
+#define CCW_C2MC_REQ_XY_RANGE                   _MK_SHIFT_CONST(103):_MK_SHIFT_CONST(103)
+#define CCW_C2MC_REQ_XY_ROW                     0
+
+#define CCW_C2MC_REQ_BE_SHIFT                   _MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_FIELD                   (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_BE_SHIFT)
+#define CCW_C2MC_REQ_BE_RANGE                   _MK_SHIFT_CONST(159):_MK_SHIFT_CONST(128)
+#define CCW_C2MC_REQ_BE_ROW                     0
+
+#define CCW_C2MC_REQ_WDO_SHIFT                  _MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_REQ_WDO_SHIFT)
+#define CCW_C2MC_REQ_WDO_RANGE                  _MK_SHIFT_CONST(415):_MK_SHIFT_CONST(160)
+#define CCW_C2MC_REQ_WDO_ROW                    0
+
+#define CCW_C2MC_REQ_TAG_SHIFT                  _MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_REQ_TAG_SHIFT)
+#define CCW_C2MC_REQ_TAG_RANGE                  _MK_SHIFT_CONST(416):_MK_SHIFT_CONST(416)
+#define CCW_C2MC_REQ_TAG_ROW                    0
+
+
+// Packet CCW_C2MC_SECURE
+#define CCW_C2MC_SECURE_SIZE 1
+
+#define CCW_C2MC_SECURE_SECURE_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_SECURE_SECURE_FIELD                    (_MK_MASK_CONST(0x1) << CCW_C2MC_SECURE_SECURE_SHIFT)
+#define CCW_C2MC_SECURE_SECURE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_SECURE_SECURE_ROW                      0
+
+
+// Packet CCW_C2MC_ADRXY
+#define CCW_C2MC_ADRXY_SIZE 30
+
+#define CCW_C2MC_ADRXY_OFFX_SHIFT                       _MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_FIELD                       (_MK_MASK_CONST(0xffff) << CCW_C2MC_ADRXY_OFFX_SHIFT)
+#define CCW_C2MC_ADRXY_OFFX_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_ADRXY_OFFX_ROW                 0
+
+#define CCW_C2MC_ADRXY_OFFY_SHIFT                       _MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_FIELD                       (_MK_MASK_CONST(0x3fff) << CCW_C2MC_ADRXY_OFFY_SHIFT)
+#define CCW_C2MC_ADRXY_OFFY_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(16)
+#define CCW_C2MC_ADRXY_OFFY_ROW                 0
+
+
+// Packet CCW_C2MC_TILE
+#define CCW_C2MC_TILE_SIZE 33
+
+#define CCW_C2MC_TILE_LINADR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_FIELD                      (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_TILE_LINADR_SHIFT)
+#define CCW_C2MC_TILE_LINADR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_TILE_LINADR_ROW                        0
+
+#define CCW_C2MC_TILE_TMODE_SHIFT                       _MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_FIELD                       (_MK_MASK_CONST(0x1) << CCW_C2MC_TILE_TMODE_SHIFT)
+#define CCW_C2MC_TILE_TMODE_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define CCW_C2MC_TILE_TMODE_ROW                 0
+#define CCW_C2MC_TILE_TMODE_LINEAR                      _MK_ENUM_CONST(0)
+#define CCW_C2MC_TILE_TMODE_TILED                       _MK_ENUM_CONST(1)
+
+
+// Packet CCW_C2MC_XDI
+#define CCW_C2MC_XDI_SIZE 1
+
+// fake data
+#define CCW_C2MC_XDI_XDI_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_FIELD                  (_MK_MASK_CONST(0x1) << CCW_C2MC_XDI_XDI_SHIFT)
+#define CCW_C2MC_XDI_XDI_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_XDI_XDI_ROW                    0
+
+
+// Packet CCW_C2MC_HP
+#define CCW_C2MC_HP_SIZE 32
+
+// high-priority threshold
+#define CCW_C2MC_HP_HPTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_FIELD                  (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_HP_HPTH_SHIFT)
+#define CCW_C2MC_HP_HPTH_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HP_HPTH_ROW                    0
+
+
+// Packet CCW_C2MC_WCOAL
+#define CCW_C2MC_WCOAL_SIZE 32
+
+// write-coalescing time-out
+#define CCW_C2MC_WCOAL_WCOALTM_SHIFT                    _MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_FIELD                    (_MK_MASK_CONST(0xffffffff) << CCW_C2MC_WCOAL_WCOALTM_SHIFT)
+#define CCW_C2MC_WCOAL_WCOALTM_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_WCOAL_WCOALTM_ROW                      0
+
+
+// Packet CCW_C2MC_HYST
+#define CCW_C2MC_HYST_SIZE 32
+
+#define CCW_C2MC_HYST_HYST_REQ_TM_SHIFT                 _MK_SHIFT_CONST(0)
+#define CCW_C2MC_HYST_HYST_REQ_TM_FIELD                 (_MK_MASK_CONST(0xfff) << CCW_C2MC_HYST_HYST_REQ_TM_SHIFT)
+#define CCW_C2MC_HYST_HYST_REQ_TM_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define CCW_C2MC_HYST_HYST_REQ_TM_ROW                   0
+
+#define CCW_C2MC_HYST_HYST_REQ_TH_SHIFT                 _MK_SHIFT_CONST(28)
+#define CCW_C2MC_HYST_HYST_REQ_TH_FIELD                 (_MK_MASK_CONST(0x7) << CCW_C2MC_HYST_HYST_REQ_TH_SHIFT)
+#define CCW_C2MC_HYST_HYST_REQ_TH_RANGE                 _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(28)
+#define CCW_C2MC_HYST_HYST_REQ_TH_ROW                   0
+
+#define CCW_C2MC_HYST_HYST_EN_SHIFT                     _MK_SHIFT_CONST(31)
+#define CCW_C2MC_HYST_HYST_EN_FIELD                     (_MK_MASK_CONST(0x1) << CCW_C2MC_HYST_HYST_EN_SHIFT)
+#define CCW_C2MC_HYST_HYST_EN_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define CCW_C2MC_HYST_HYST_EN_ROW                       0
+
+
+// Packet SC_MCCIF_ASYNC
+#define SC_MCCIF_ASYNC_SIZE 4
+
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT                        _MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDCL_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define SC_MCCIF_ASYNC_RDCL_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT                        _MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_RDMC_RDFAST_SHIFT)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_RANGE                        _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define SC_MCCIF_ASYNC_RDMC_RDFAST_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT                        _MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRCL_MCLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define SC_MCCIF_ASYNC_WRCL_MCLE2X_ROW                  0
+
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT                        _MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_FIELD                        (_MK_MASK_CONST(0x1) << SC_MCCIF_ASYNC_WRMC_CLLE2X_SHIFT)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_RANGE                        _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define SC_MCCIF_ASYNC_WRMC_CLLE2X_ROW                  0
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARMC_REGS(_op_) \
+_op_(MC_INTSTATUS_0) \
+_op_(MC_INTMASK_0) \
+_op_(MC_EMEM_CFG_0) \
+_op_(MC_EMEM_ADR_CFG_0) \
+_op_(MC_EMEM_ARB_CFG0_0) \
+_op_(MC_EMEM_ARB_CFG1_0) \
+_op_(MC_EMEM_ARB_CFG2_0) \
+_op_(MC_GART_CONFIG_0) \
+_op_(MC_GART_ENTRY_ADDR_0) \
+_op_(MC_GART_ENTRY_DATA_0) \
+_op_(MC_GART_ERROR_REQ_0) \
+_op_(MC_GART_ERROR_ADDR_0) \
+_op_(MC_TIMEOUT_CTRL_0) \
+_op_(MC_DECERR_EMEM_OTHERS_STATUS_0) \
+_op_(MC_DECERR_EMEM_OTHERS_ADR_0) \
+_op_(MC_CLKEN_OVERRIDE_0) \
+_op_(MC_SECURITY_CFG0_0) \
+_op_(MC_SECURITY_CFG1_0) \
+_op_(MC_SECURITY_VIOLATION_STATUS_0) \
+_op_(MC_SECURITY_VIOLATION_ADR_0) \
+_op_(MC_SECURITY_CFG2_0) \
+_op_(MC_STAT_CONTROL_0) \
+_op_(MC_STAT_STATUS_0) \
+_op_(MC_STAT_EMC_ADDR_LOW_0) \
+_op_(MC_STAT_EMC_ADDR_HIGH_0) \
+_op_(MC_STAT_EMC_CLOCK_LIMIT_0) \
+_op_(MC_STAT_EMC_CLOCKS_0) \
+_op_(MC_STAT_EMC_CONTROL_0_0) \
+_op_(MC_STAT_EMC_CONTROL_1_0) \
+_op_(MC_STAT_EMC_HIST_LIMIT_0_0) \
+_op_(MC_STAT_EMC_HIST_LIMIT_1_0) \
+_op_(MC_STAT_EMC_COUNT_0_0) \
+_op_(MC_STAT_EMC_COUNT_1_0) \
+_op_(MC_STAT_EMC_HIST_0_0) \
+_op_(MC_STAT_EMC_HIST_1_0) \
+_op_(MC_CLIENT_CTRL_0) \
+_op_(MC_CLIENT_HOTRESETN_0) \
+_op_(MC_AXI_DECERR_OVR_0) \
+_op_(MC_LOWLATENCY_CONFIG_0) \
+_op_(MC_LOWLATENCY_RAWLOGIC_WRITE_PARTICIPANTS_0) \
+_op_(MC_BWSHARE_TMVAL_0) \
+_op_(MC_BWSHARE_EMEM_CTRL_0_0) \
+_op_(MC_BWSHARE_EMEM_CTRL_1_0) \
+_op_(MC_AP_CTRL_0_0) \
+_op_(MC_AP_CTRL_1_0) \
+_op_(MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0) \
+_op_(MC_CLIENT_ACTIVITY_MONITOR_EMEM_1_0) \
+_op_(MC_AVPC_ORRC_0) \
+_op_(MC_DC_ORRC_0) \
+_op_(MC_DCB_ORRC_0) \
+_op_(MC_EPP_ORRC_0) \
+_op_(MC_G2_ORRC_0) \
+_op_(MC_HC_ORRC_0) \
+_op_(MC_ISP_ORRC_0) \
+_op_(MC_MPCORE_ORRC_0) \
+_op_(MC_MPEA_ORRC_0) \
+_op_(MC_MPEB_ORRC_0) \
+_op_(MC_MPEC_ORRC_0) \
+_op_(MC_NV_ORRC_0) \
+_op_(MC_PPCS_ORRC_0) \
+_op_(MC_VDE_ORRC_0) \
+_op_(MC_VI_ORRC_0) \
+_op_(MC_FPRI_CTRL_AVPC_0) \
+_op_(MC_FPRI_CTRL_DC_0) \
+_op_(MC_FPRI_CTRL_DCB_0) \
+_op_(MC_FPRI_CTRL_EPP_0) \
+_op_(MC_FPRI_CTRL_G2_0) \
+_op_(MC_FPRI_CTRL_HC_0) \
+_op_(MC_FPRI_CTRL_ISP_0) \
+_op_(MC_FPRI_CTRL_MPCORE_0) \
+_op_(MC_FPRI_CTRL_MPEA_0) \
+_op_(MC_FPRI_CTRL_MPEB_0) \
+_op_(MC_FPRI_CTRL_MPEC_0) \
+_op_(MC_FPRI_CTRL_NV_0) \
+_op_(MC_FPRI_CTRL_PPCS_0) \
+_op_(MC_FPRI_CTRL_VDE_0) \
+_op_(MC_FPRI_CTRL_VI_0) \
+_op_(MC_TIMEOUT_AVPC_0) \
+_op_(MC_TIMEOUT_DC_0) \
+_op_(MC_TIMEOUT_DCB_0) \
+_op_(MC_TIMEOUT_EPP_0) \
+_op_(MC_TIMEOUT_G2_0) \
+_op_(MC_TIMEOUT_HC_0) \
+_op_(MC_TIMEOUT_ISP_0) \
+_op_(MC_TIMEOUT_MPCORE_0) \
+_op_(MC_TIMEOUT_MPEA_0) \
+_op_(MC_TIMEOUT_MPEB_0) \
+_op_(MC_TIMEOUT_MPEC_0) \
+_op_(MC_TIMEOUT_NV_0) \
+_op_(MC_TIMEOUT_PPCS_0) \
+_op_(MC_TIMEOUT_VDE_0) \
+_op_(MC_TIMEOUT_VI_0) \
+_op_(MC_TIMEOUT_RCOAL_AVPC_0) \
+_op_(MC_TIMEOUT_RCOAL_DC_0) \
+_op_(MC_TIMEOUT1_RCOAL_DC_0) \
+_op_(MC_TIMEOUT_RCOAL_DCB_0) \
+_op_(MC_TIMEOUT1_RCOAL_DCB_0) \
+_op_(MC_TIMEOUT_RCOAL_EPP_0) \
+_op_(MC_TIMEOUT_RCOAL_G2_0) \
+_op_(MC_TIMEOUT_RCOAL_HC_0) \
+_op_(MC_TIMEOUT_RCOAL_MPCORE_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEA_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEB_0) \
+_op_(MC_TIMEOUT_RCOAL_MPEC_0) \
+_op_(MC_TIMEOUT_RCOAL_NV_0) \
+_op_(MC_TIMEOUT_RCOAL_PPCS_0) \
+_op_(MC_TIMEOUT_RCOAL_VDE_0) \
+_op_(MC_TIMEOUT_RCOAL_VI_0) \
+_op_(MC_RCOAL_AUTODISABLE_0_0) \
+_op_(MC_BWSHARE_AVPC_0) \
+_op_(MC_BWSHARE_DC_0) \
+_op_(MC_BWSHARE_DCB_0) \
+_op_(MC_BWSHARE_EPP_0) \
+_op_(MC_BWSHARE_G2_0) \
+_op_(MC_BWSHARE_HC_0) \
+_op_(MC_BWSHARE_ISP_0) \
+_op_(MC_BWSHARE_MPCORE_0) \
+_op_(MC_BWSHARE_MPEA_0) \
+_op_(MC_BWSHARE_MPEB_0) \
+_op_(MC_BWSHARE_MPEC_0) \
+_op_(MC_BWSHARE_NV_0) \
+_op_(MC_BWSHARE_PPCS_0) \
+_op_(MC_BWSHARE_VDE_0) \
+_op_(MC_BWSHARE_VI_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_MC 0x00000000
+
+//
+// ARMC REGISTER BANKS
+//
+
+#define MC0_FIRST_REG 0x0000 // MC_INTSTATUS_0
+#define MC0_LAST_REG 0x0004 // MC_INTMASK_0
+#define MC1_FIRST_REG 0x000c // MC_EMEM_CFG_0
+#define MC1_LAST_REG 0x001c // MC_EMEM_ARB_CFG2_0
+#define MC2_FIRST_REG 0x0024 // MC_GART_CONFIG_0
+#define MC2_LAST_REG 0x0034 // MC_GART_ERROR_ADDR_0
+#define MC3_FIRST_REG 0x003c // MC_TIMEOUT_CTRL_0
+#define MC3_LAST_REG 0x003c // MC_TIMEOUT_CTRL_0
+#define MC4_FIRST_REG 0x0058 // MC_DECERR_EMEM_OTHERS_STATUS_0
+#define MC4_LAST_REG 0x005c // MC_DECERR_EMEM_OTHERS_ADR_0
+#define MC5_FIRST_REG 0x0068 // MC_CLKEN_OVERRIDE_0
+#define MC5_LAST_REG 0x007c // MC_SECURITY_CFG2_0
+#define MC6_FIRST_REG 0x0090 // MC_STAT_CONTROL_0
+#define MC6_LAST_REG 0x00c4 // MC_STAT_EMC_HIST_1_0
+#define MC7_FIRST_REG 0x0100 // MC_CLIENT_CTRL_0
+#define MC7_LAST_REG 0x0114 // MC_BWSHARE_TMVAL_0
+#define MC8_FIRST_REG 0x0120 // MC_BWSHARE_EMEM_CTRL_0_0
+#define MC8_LAST_REG 0x012c // MC_AP_CTRL_1_0
+#define MC9_FIRST_REG 0x0138 // MC_CLIENT_ACTIVITY_MONITOR_EMEM_0_0
+#define MC9_LAST_REG 0x0270 // MC_BWSHARE_VI_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARMC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arnandflash.h b/arch/arm/mach-tegra/nv/include/ap20/arnandflash.h
new file mode 100644
index 000000000000..73075f5f8760
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arnandflash.h
@@ -0,0 +1,4245 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARNANDFLASH_H_INC_
+#define ___ARNANDFLASH_H_INC_
+#define NDFLASH_CMDQ_FIFO_WIDTH 32
+#define NDFLASH_CMDQ_FIFO_DEPTH 8
+#define NDFLASH_ECC_FIFO_WIDTH  32
+#define NDFLASH_ECC_FIFO_DEPTH  128
+#define NDFLASH_AFIFO_WIDTH     32
+#define NDFLASH_AFIFO_DEPTH     1024
+#define NDFLASH_BFIFO_WIDTH     32
+#define NDFLASH_BFIFO_DEPTH     128
+#define NDFLASH_CS_MAX  8
+#define NDFLASH_DMA_MAX_BYTES   65536
+#define NDFLASH_DMA_PTR_ALIGN   4
+#define NDFLASH_CMDQ_MAX_PKT_LENGTH     15
+#define NDFLASH_PARITY_SZ_RS_T1_256     4
+#define NDFLASH_PARITY_SZ_RS_T4_512     12
+#define NDFLASH_PARITY_SZ_RS_T4_1024    20
+#define NDFLASH_PARITY_SZ_RS_T4_2048    36
+#define NDFLASH_PARITY_SZ_RS_T4_4096    72
+#define NDFLASH_PARITY_SZ_RS_T6_512     16
+#define NDFLASH_PARITY_SZ_RS_T6_1024    28
+#define NDFLASH_PARITY_SZ_RS_T6_2048    56
+#define NDFLASH_PARITY_SZ_RS_T6_4096    108
+#define NDFLASH_PARITY_SZ_RS_T8_512     20
+#define NDFLASH_PARITY_SZ_RS_T8_1024    36
+#define NDFLASH_PARITY_SZ_RS_T8_2048    72
+#define NDFLASH_PARITY_SZ_RS_T8_4096    144
+#define NDFLASH_PARITY_SZ_HAMMING_256   4
+#define NDFLASH_PARITY_SZ_HAMMING_512   4
+#define NDFLASH_PARITY_SZ_HAMMING_1024  8
+#define NDFLASH_PARITY_SZ_HAMMING_2048  16
+#define NDFLASH_PARITY_SZ_HAMMING_4096  32
+#define NDFLASH_PARITY_SZ_HAMMING_SPARE 4
+#define NDFLASH_PARITY_SZ_BCH_T4_512    7
+#define NDFLASH_PARITY_SZ_BCH_T8_512    13
+#define NDFLASH_PARITY_SZ_BCH_T14_512   23
+#define NDFLASH_PARITY_SZ_BCH_T16_512   26
+
+// Register NAND_COMMAND_0  
+#define NAND_COMMAND_0                  _MK_ADDR_CONST(0x0)
+#define NAND_COMMAND_0_SECURE                   0x0
+#define NAND_COMMAND_0_WORD_COUNT                       0x1
+#define NAND_COMMAND_0_RESET_VAL                        _MK_MASK_CONST(0x800004)
+#define NAND_COMMAND_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_COMMAND_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define NAND_COMMAND_0_WRITE_MASK                       _MK_MASK_CONST(0x7fffffff)
+// 0 = HW clears when programmed nand IO 
+//     operation is completed.
+#define NAND_COMMAND_0_GO_SHIFT                 _MK_SHIFT_CONST(31)
+#define NAND_COMMAND_0_GO_FIELD                 (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_GO_SHIFT)
+#define NAND_COMMAND_0_GO_RANGE                 31:31
+#define NAND_COMMAND_0_GO_WOFFSET                       0x0
+#define NAND_COMMAND_0_GO_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_GO_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_GO_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_GO_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_GO_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_GO_ENABLE                        _MK_ENUM_CONST(1)
+
+// CLE enable
+// 1 = Flash sequence has Command Cycle(CLE) enabled 
+// 0 = Flash sequence has Command Cycle(CLE) disabled
+#define NAND_COMMAND_0_CLE_SHIFT                        _MK_SHIFT_CONST(30)
+#define NAND_COMMAND_0_CLE_FIELD                        (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CLE_SHIFT)
+#define NAND_COMMAND_0_CLE_RANGE                        30:30
+#define NAND_COMMAND_0_CLE_WOFFSET                      0x0
+#define NAND_COMMAND_0_CLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_CLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CLE_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_CLE_ENABLE                       _MK_ENUM_CONST(1)
+
+// ALE enable
+// 1 = Flash sequence has Address Cycle(CLE) enabled 
+// 0 = Flash sequence has Address Cycle(CLE) disabled 
+#define NAND_COMMAND_0_ALE_SHIFT                        _MK_SHIFT_CONST(29)
+#define NAND_COMMAND_0_ALE_FIELD                        (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_ALE_SHIFT)
+#define NAND_COMMAND_0_ALE_RANGE                        29:29
+#define NAND_COMMAND_0_ALE_WOFFSET                      0x0
+#define NAND_COMMAND_0_ALE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_ALE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_ALE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_ALE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_ALE_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_ALE_ENABLE                       _MK_ENUM_CONST(1)
+
+// PIO mode of operation enable
+// 1 = Dataout is from NAND_RESP register
+//     and Datain is to NAND_RESP register
+// 0 = Dataout is from FIFO buffer
+//     and Datain to FIFO buffer
+#define NAND_COMMAND_0_PIO_SHIFT                        _MK_SHIFT_CONST(28)
+#define NAND_COMMAND_0_PIO_FIELD                        (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_PIO_SHIFT)
+#define NAND_COMMAND_0_PIO_RANGE                        28:28
+#define NAND_COMMAND_0_PIO_WOFFSET                      0x0
+#define NAND_COMMAND_0_PIO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_PIO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_PIO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_PIO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_PIO_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_PIO_ENABLE                       _MK_ENUM_CONST(1)
+
+// write data transfer enable - required for FLASH program
+// 1 = Write data transfers to flash is enabled
+// 0 = Write data transfers to flash is disabled
+#define NAND_COMMAND_0_TX_SHIFT                 _MK_SHIFT_CONST(27)
+#define NAND_COMMAND_0_TX_FIELD                 (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_TX_SHIFT)
+#define NAND_COMMAND_0_TX_RANGE                 27:27
+#define NAND_COMMAND_0_TX_WOFFSET                       0x0
+#define NAND_COMMAND_0_TX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_TX_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_TX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_TX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_TX_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_TX_ENABLE                        _MK_ENUM_CONST(1)
+
+// read data transfer enabled - required for FLASH read
+// 1 = Read data transfers from flash is enabled
+// 0 = Read data transfers from flash is disabled
+#define NAND_COMMAND_0_RX_SHIFT                 _MK_SHIFT_CONST(26)
+#define NAND_COMMAND_0_RX_FIELD                 (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_RX_SHIFT)
+#define NAND_COMMAND_0_RX_RANGE                 26:26
+#define NAND_COMMAND_0_RX_WOFFSET                       0x0
+#define NAND_COMMAND_0_RX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_RX_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_RX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_RX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_RX_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_RX_ENABLE                        _MK_ENUM_CONST(1)
+
+// CMD2 sequence to flash enable
+// 1 = NAND command sequence have a second command(CLE)
+//     cycle
+// 0 = NAND command sequence doesnt have second CLE cycle
+#define NAND_COMMAND_0_SEC_CMD_SHIFT                    _MK_SHIFT_CONST(25)
+#define NAND_COMMAND_0_SEC_CMD_FIELD                    (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_SEC_CMD_SHIFT)
+#define NAND_COMMAND_0_SEC_CMD_RANGE                    25:25
+#define NAND_COMMAND_0_SEC_CMD_WOFFSET                  0x0
+#define NAND_COMMAND_0_SEC_CMD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_SEC_CMD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_SEC_CMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_SEC_CMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_SEC_CMD_DISABLE                  _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_SEC_CMD_ENABLE                   _MK_ENUM_CONST(1)
+
+// CMD2 placement control
+// 1 - CMD2 CLE cycle is issued after data transfer cycles.
+//     this is the typical usage during FLASH program
+// 0 - CMD2 CLE cycle is issued right after Address transfer
+//      cycles, typical usage during FLASH read
+#define NAND_COMMAND_0_AFT_DAT_SHIFT                    _MK_SHIFT_CONST(24)
+#define NAND_COMMAND_0_AFT_DAT_FIELD                    (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_AFT_DAT_SHIFT)
+#define NAND_COMMAND_0_AFT_DAT_RANGE                    24:24
+#define NAND_COMMAND_0_AFT_DAT_WOFFSET                  0x0
+#define NAND_COMMAND_0_AFT_DAT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_AFT_DAT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_AFT_DAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_AFT_DAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_AFT_DAT_DISABLE                  _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_AFT_DAT_ENABLE                   _MK_ENUM_CONST(1)
+
+// Transfer size of bytes  Depends on PAGE_SIZE_SEL field of CONFIG register
+#define NAND_COMMAND_0_TRANS_SIZE_SHIFT                 _MK_SHIFT_CONST(20)
+#define NAND_COMMAND_0_TRANS_SIZE_FIELD                 (_MK_MASK_CONST(0xf) << NAND_COMMAND_0_TRANS_SIZE_SHIFT)
+#define NAND_COMMAND_0_TRANS_SIZE_RANGE                 23:20
+#define NAND_COMMAND_0_TRANS_SIZE_WOFFSET                       0x0
+#define NAND_COMMAND_0_TRANS_SIZE_DEFAULT                       _MK_MASK_CONST(0x8)
+#define NAND_COMMAND_0_TRANS_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define NAND_COMMAND_0_TRANS_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_TRANS_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_TRANS_SIZE_BYTES1                        _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_TRANS_SIZE_BYTES2                        _MK_ENUM_CONST(1)
+#define NAND_COMMAND_0_TRANS_SIZE_BYTES3                        _MK_ENUM_CONST(2)
+#define NAND_COMMAND_0_TRANS_SIZE_BYTES4                        _MK_ENUM_CONST(3)
+#define NAND_COMMAND_0_TRANS_SIZE_BYTES5                        _MK_ENUM_CONST(4)
+#define NAND_COMMAND_0_TRANS_SIZE_BYTES6                        _MK_ENUM_CONST(5)
+#define NAND_COMMAND_0_TRANS_SIZE_BYTES7                        _MK_ENUM_CONST(6)
+#define NAND_COMMAND_0_TRANS_SIZE_BYTES8                        _MK_ENUM_CONST(7)
+#define NAND_COMMAND_0_TRANS_SIZE_BYTES_PAGE_SIZE_SEL                   _MK_ENUM_CONST(8)
+
+// Main data region transer enable 
+// 1 = Involves Main area data transfer in flash sequence
+// 0 = Doesnt involve Main area data transfer
+#define NAND_COMMAND_0_A_VALID_SHIFT                    _MK_SHIFT_CONST(19)
+#define NAND_COMMAND_0_A_VALID_FIELD                    (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_A_VALID_SHIFT)
+#define NAND_COMMAND_0_A_VALID_RANGE                    19:19
+#define NAND_COMMAND_0_A_VALID_WOFFSET                  0x0
+#define NAND_COMMAND_0_A_VALID_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_A_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_A_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_A_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_A_VALID_DISABLE                  _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_A_VALID_ENABLE                   _MK_ENUM_CONST(1)
+
+// Spare region (aka TAG) transfer enable
+// 1 = Involves spare area data transfer in flash sequence
+// 0 = Doesnt involve spare area data transfer
+#define NAND_COMMAND_0_B_VALID_SHIFT                    _MK_SHIFT_CONST(18)
+#define NAND_COMMAND_0_B_VALID_FIELD                    (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_B_VALID_SHIFT)
+#define NAND_COMMAND_0_B_VALID_RANGE                    18:18
+#define NAND_COMMAND_0_B_VALID_WOFFSET                  0x0
+#define NAND_COMMAND_0_B_VALID_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_B_VALID_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_B_VALID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_B_VALID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_B_VALID_DISABLE                  _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_B_VALID_ENABLE                   _MK_ENUM_CONST(1)
+
+// H/W assisted read status check enable
+// 1 = Indicates to controller that current IO sequence 
+//     need RD STATUS check condition to be qualified. 
+// 0 = auto read status check is disabled
+// notes: please refer to NAND_HWSTATUS_CMD register for
+//        qualifier conditon 
+#define NAND_COMMAND_0_RD_STATUS_CHK_SHIFT                      _MK_SHIFT_CONST(17)
+#define NAND_COMMAND_0_RD_STATUS_CHK_FIELD                      (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_RD_STATUS_CHK_SHIFT)
+#define NAND_COMMAND_0_RD_STATUS_CHK_RANGE                      17:17
+#define NAND_COMMAND_0_RD_STATUS_CHK_WOFFSET                    0x0
+#define NAND_COMMAND_0_RD_STATUS_CHK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_RD_STATUS_CHK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_RD_STATUS_CHK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_RD_STATUS_CHK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_RD_STATUS_CHK_DISABLE                    _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_RD_STATUS_CHK_ENABLE                     _MK_ENUM_CONST(1)
+
+// H/W assited rbsy check enable 
+// 1 = Indicates to controller that current IO sequence 
+//     need RBSY check condition to be qualified. 
+// 0 = auto RBSY check is disabled
+// notes: please refer to NAND_HWSTATUS_CMD register for
+//        qualifier conditon 
+#define NAND_COMMAND_0_RBSY_CHK_SHIFT                   _MK_SHIFT_CONST(16)
+#define NAND_COMMAND_0_RBSY_CHK_FIELD                   (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_RBSY_CHK_SHIFT)
+#define NAND_COMMAND_0_RBSY_CHK_RANGE                   16:16
+#define NAND_COMMAND_0_RBSY_CHK_WOFFSET                 0x0
+#define NAND_COMMAND_0_RBSY_CHK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_RBSY_CHK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_RBSY_CHK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_RBSY_CHK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_RBSY_CHK_DISABLE                 _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_RBSY_CHK_ENABLE                  _MK_ENUM_CONST(1)
+
+// Chip select enable for Flash Card 7
+// 0 = Disable 1 = Enable
+#define NAND_COMMAND_0_CE7_SHIFT                        _MK_SHIFT_CONST(15)
+#define NAND_COMMAND_0_CE7_FIELD                        (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE7_SHIFT)
+#define NAND_COMMAND_0_CE7_RANGE                        15:15
+#define NAND_COMMAND_0_CE7_WOFFSET                      0x0
+#define NAND_COMMAND_0_CE7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_CE7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE7_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_CE7_ENABLE                       _MK_ENUM_CONST(1)
+
+// Chip select enable for Flash Card 6
+// 0 = Disable 1 = Enable
+#define NAND_COMMAND_0_CE6_SHIFT                        _MK_SHIFT_CONST(14)
+#define NAND_COMMAND_0_CE6_FIELD                        (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE6_SHIFT)
+#define NAND_COMMAND_0_CE6_RANGE                        14:14
+#define NAND_COMMAND_0_CE6_WOFFSET                      0x0
+#define NAND_COMMAND_0_CE6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_CE6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE6_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_CE6_ENABLE                       _MK_ENUM_CONST(1)
+
+// Chip select enable for Flash Card 5
+// 0 = Disable 1 = Enable
+#define NAND_COMMAND_0_CE5_SHIFT                        _MK_SHIFT_CONST(13)
+#define NAND_COMMAND_0_CE5_FIELD                        (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE5_SHIFT)
+#define NAND_COMMAND_0_CE5_RANGE                        13:13
+#define NAND_COMMAND_0_CE5_WOFFSET                      0x0
+#define NAND_COMMAND_0_CE5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_CE5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE5_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_CE5_ENABLE                       _MK_ENUM_CONST(1)
+
+// Chip select enable for Flash Card 4
+// 0 = Disable 1 = Enable
+#define NAND_COMMAND_0_CE4_SHIFT                        _MK_SHIFT_CONST(12)
+#define NAND_COMMAND_0_CE4_FIELD                        (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE4_SHIFT)
+#define NAND_COMMAND_0_CE4_RANGE                        12:12
+#define NAND_COMMAND_0_CE4_WOFFSET                      0x0
+#define NAND_COMMAND_0_CE4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_CE4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE4_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_CE4_ENABLE                       _MK_ENUM_CONST(1)
+
+// Chip select enable for Flash Card 3
+// 0 = Disable 1 = Enable
+#define NAND_COMMAND_0_CE3_SHIFT                        _MK_SHIFT_CONST(11)
+#define NAND_COMMAND_0_CE3_FIELD                        (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE3_SHIFT)
+#define NAND_COMMAND_0_CE3_RANGE                        11:11
+#define NAND_COMMAND_0_CE3_WOFFSET                      0x0
+#define NAND_COMMAND_0_CE3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_CE3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE3_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_CE3_ENABLE                       _MK_ENUM_CONST(1)
+
+// Chip select enable for Flash Card 2
+// 0 = Disable 1 = Enable
+#define NAND_COMMAND_0_CE2_SHIFT                        _MK_SHIFT_CONST(10)
+#define NAND_COMMAND_0_CE2_FIELD                        (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE2_SHIFT)
+#define NAND_COMMAND_0_CE2_RANGE                        10:10
+#define NAND_COMMAND_0_CE2_WOFFSET                      0x0
+#define NAND_COMMAND_0_CE2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_CE2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE2_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_CE2_ENABLE                       _MK_ENUM_CONST(1)
+
+// Chip select enable for Flash Card 1
+// 0 = Disable 1 = Enable
+#define NAND_COMMAND_0_CE1_SHIFT                        _MK_SHIFT_CONST(9)
+#define NAND_COMMAND_0_CE1_FIELD                        (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE1_SHIFT)
+#define NAND_COMMAND_0_CE1_RANGE                        9:9
+#define NAND_COMMAND_0_CE1_WOFFSET                      0x0
+#define NAND_COMMAND_0_CE1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_CE1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE1_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_CE1_ENABLE                       _MK_ENUM_CONST(1)
+
+// Chip select enable for Flash Card 0
+// 0 = Disable 1 = Enable
+#define NAND_COMMAND_0_CE0_SHIFT                        _MK_SHIFT_CONST(8)
+#define NAND_COMMAND_0_CE0_FIELD                        (_MK_MASK_CONST(0x1) << NAND_COMMAND_0_CE0_SHIFT)
+#define NAND_COMMAND_0_CE0_RANGE                        8:8
+#define NAND_COMMAND_0_CE0_WOFFSET                      0x0
+#define NAND_COMMAND_0_CE0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_COMMAND_0_CE0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CE0_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_CE0_ENABLE                       _MK_ENUM_CONST(1)
+
+#define NAND_COMMAND_0_RSVD_SHIFT                       _MK_SHIFT_CONST(6)
+#define NAND_COMMAND_0_RSVD_FIELD                       (_MK_MASK_CONST(0x3) << NAND_COMMAND_0_RSVD_SHIFT)
+#define NAND_COMMAND_0_RSVD_RANGE                       7:6
+#define NAND_COMMAND_0_RSVD_WOFFSET                     0x0
+#define NAND_COMMAND_0_RSVD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_RSVD_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define NAND_COMMAND_0_RSVD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_RSVD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  Command cycle byte count
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_SHIFT                      _MK_SHIFT_CONST(4)
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_FIELD                      (_MK_MASK_CONST(0x3) << NAND_COMMAND_0_CLE_BYTE_SIZE_SHIFT)
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_RANGE                      5:4
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_WOFFSET                    0x0
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_CLE_BYTES1                 _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_CLE_BYTES2                 _MK_ENUM_CONST(1)
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_CLE_BYTES3                 _MK_ENUM_CONST(2)
+#define NAND_COMMAND_0_CLE_BYTE_SIZE_CLE_BYTES4                 _MK_ENUM_CONST(3)
+
+// Address cycle byte count Reserved
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_FIELD                      (_MK_MASK_CONST(0xf) << NAND_COMMAND_0_ALE_BYTE_SIZE_SHIFT)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_RANGE                      3:0
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_WOFFSET                    0x0
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_DEFAULT                    _MK_MASK_CONST(0x4)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES1                 _MK_ENUM_CONST(0)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES2                 _MK_ENUM_CONST(1)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES3                 _MK_ENUM_CONST(2)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES4                 _MK_ENUM_CONST(3)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES5                 _MK_ENUM_CONST(4)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES6                 _MK_ENUM_CONST(5)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES7                 _MK_ENUM_CONST(6)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES8                 _MK_ENUM_CONST(7)
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES9                 _MK_ENUM_CONST(8)    // // Reserved
+
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES10                        _MK_ENUM_CONST(9)    // // Reserved
+
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES11                        _MK_ENUM_CONST(10)    // // Reserved
+
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES12                        _MK_ENUM_CONST(11)    // // Reserved
+
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES13                        _MK_ENUM_CONST(12)    // // Reserved
+
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES14                        _MK_ENUM_CONST(13)    // // Reserved
+
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES15                        _MK_ENUM_CONST(14)    // // Reserved
+
+#define NAND_COMMAND_0_ALE_BYTE_SIZE_ALE_BYTES16                        _MK_ENUM_CONST(15)
+
+
+// Register NAND_STATUS_0  
+#define NAND_STATUS_0                   _MK_ADDR_CONST(0x4)
+#define NAND_STATUS_0_SECURE                    0x0
+#define NAND_STATUS_0_WORD_COUNT                        0x1
+#define NAND_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffc1)
+#define NAND_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xffffffc1)
+#define NAND_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_NA2_SHIFT                 _MK_SHIFT_CONST(16)
+#define NAND_STATUS_0_NA2_FIELD                 (_MK_MASK_CONST(0xffff) << NAND_STATUS_0_NA2_SHIFT)
+#define NAND_STATUS_0_NA2_RANGE                 31:16
+#define NAND_STATUS_0_NA2_WOFFSET                       0x0
+#define NAND_STATUS_0_NA2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_NA2_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define NAND_STATUS_0_NA2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_NA2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = Indicates flash7 is RDY
+#define NAND_STATUS_0_RBSY7_SHIFT                       _MK_SHIFT_CONST(15)
+#define NAND_STATUS_0_RBSY7_FIELD                       (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY7_SHIFT)
+#define NAND_STATUS_0_RBSY7_RANGE                       15:15
+#define NAND_STATUS_0_RBSY7_WOFFSET                     0x0
+#define NAND_STATUS_0_RBSY7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_STATUS_0_RBSY7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = Indicates flash6 is RDY
+#define NAND_STATUS_0_RBSY6_SHIFT                       _MK_SHIFT_CONST(14)
+#define NAND_STATUS_0_RBSY6_FIELD                       (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY6_SHIFT)
+#define NAND_STATUS_0_RBSY6_RANGE                       14:14
+#define NAND_STATUS_0_RBSY6_WOFFSET                     0x0
+#define NAND_STATUS_0_RBSY6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_STATUS_0_RBSY6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = Indicates flash5 is RDY
+#define NAND_STATUS_0_RBSY5_SHIFT                       _MK_SHIFT_CONST(13)
+#define NAND_STATUS_0_RBSY5_FIELD                       (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY5_SHIFT)
+#define NAND_STATUS_0_RBSY5_RANGE                       13:13
+#define NAND_STATUS_0_RBSY5_WOFFSET                     0x0
+#define NAND_STATUS_0_RBSY5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_STATUS_0_RBSY5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = Indicates flash4 is RDY
+#define NAND_STATUS_0_RBSY4_SHIFT                       _MK_SHIFT_CONST(12)
+#define NAND_STATUS_0_RBSY4_FIELD                       (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY4_SHIFT)
+#define NAND_STATUS_0_RBSY4_RANGE                       12:12
+#define NAND_STATUS_0_RBSY4_WOFFSET                     0x0
+#define NAND_STATUS_0_RBSY4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_STATUS_0_RBSY4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = Indicates flash3 is RDY
+#define NAND_STATUS_0_RBSY3_SHIFT                       _MK_SHIFT_CONST(11)
+#define NAND_STATUS_0_RBSY3_FIELD                       (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY3_SHIFT)
+#define NAND_STATUS_0_RBSY3_RANGE                       11:11
+#define NAND_STATUS_0_RBSY3_WOFFSET                     0x0
+#define NAND_STATUS_0_RBSY3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_STATUS_0_RBSY3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = Indicates flash2 is RDY
+#define NAND_STATUS_0_RBSY2_SHIFT                       _MK_SHIFT_CONST(10)
+#define NAND_STATUS_0_RBSY2_FIELD                       (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY2_SHIFT)
+#define NAND_STATUS_0_RBSY2_RANGE                       10:10
+#define NAND_STATUS_0_RBSY2_WOFFSET                     0x0
+#define NAND_STATUS_0_RBSY2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_STATUS_0_RBSY2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = Indicates flash1 is RDY
+#define NAND_STATUS_0_RBSY1_SHIFT                       _MK_SHIFT_CONST(9)
+#define NAND_STATUS_0_RBSY1_FIELD                       (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY1_SHIFT)
+#define NAND_STATUS_0_RBSY1_RANGE                       9:9
+#define NAND_STATUS_0_RBSY1_WOFFSET                     0x0
+#define NAND_STATUS_0_RBSY1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_STATUS_0_RBSY1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = Indicates flash0 is RDY
+#define NAND_STATUS_0_RBSY0_SHIFT                       _MK_SHIFT_CONST(8)
+#define NAND_STATUS_0_RBSY0_FIELD                       (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RBSY0_SHIFT)
+#define NAND_STATUS_0_RBSY0_RANGE                       8:8
+#define NAND_STATUS_0_RBSY0_WOFFSET                     0x0
+#define NAND_STATUS_0_RBSY0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_STATUS_0_RBSY0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RBSY0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  1 = Indicates write cycles to flash are in progress
+#define NAND_STATUS_0_WR_ACT_SHIFT                      _MK_SHIFT_CONST(7)
+#define NAND_STATUS_0_WR_ACT_FIELD                      (_MK_MASK_CONST(0x1) << NAND_STATUS_0_WR_ACT_SHIFT)
+#define NAND_STATUS_0_WR_ACT_RANGE                      7:7
+#define NAND_STATUS_0_WR_ACT_WOFFSET                    0x0
+#define NAND_STATUS_0_WR_ACT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_WR_ACT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_STATUS_0_WR_ACT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_WR_ACT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  1 = Indicates read cycles to flash are in progress
+#define NAND_STATUS_0_RD_ACT_SHIFT                      _MK_SHIFT_CONST(6)
+#define NAND_STATUS_0_RD_ACT_FIELD                      (_MK_MASK_CONST(0x1) << NAND_STATUS_0_RD_ACT_SHIFT)
+#define NAND_STATUS_0_RD_ACT_RANGE                      6:6
+#define NAND_STATUS_0_RD_ACT_WOFFSET                    0x0
+#define NAND_STATUS_0_RD_ACT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RD_ACT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_STATUS_0_RD_ACT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_RD_ACT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  1 = Indicates NAND controller is in IDLE state of operation, 
+//      and there are no flash/DMA transactions are pending.
+#define NAND_STATUS_0_ISEMPTY_SHIFT                     _MK_SHIFT_CONST(0)
+#define NAND_STATUS_0_ISEMPTY_FIELD                     (_MK_MASK_CONST(0x1) << NAND_STATUS_0_ISEMPTY_SHIFT)
+#define NAND_STATUS_0_ISEMPTY_RANGE                     0:0
+#define NAND_STATUS_0_ISEMPTY_WOFFSET                   0x0
+#define NAND_STATUS_0_ISEMPTY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_ISEMPTY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define NAND_STATUS_0_ISEMPTY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_STATUS_0_ISEMPTY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register NAND_ISR_0  
+#define NAND_ISR_0                      _MK_ADDR_CONST(0x8)
+#define NAND_ISR_0_SECURE                       0x0
+#define NAND_ISR_0_WORD_COUNT                   0x1
+#define NAND_ISR_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_RESET_MASK                   _MK_MASK_CONST(0xfffc)
+#define NAND_ISR_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_READ_MASK                    _MK_MASK_CONST(0x100fffc)
+#define NAND_ISR_0_WRITE_MASK                   _MK_MASK_CONST(0xfffc)
+// 1 = Correctable OR Un-correctable errors occurred in the DMA transfer 
+//     without regard to HW_ERR_CORRECTION feature is enabled or not. 
+//     Use extended decode results in NAND_DEC_RESULT and NAND_DEC_STATUS_EXT 
+//     to figure out further action for block replacement/wear leveling during 
+//     file system management for s/w.
+//     Covers all ECC selection: RS/Hamming/BCH modes
+#define NAND_ISR_0_CORRFAIL_ERR_SHIFT                   _MK_SHIFT_CONST(24)
+#define NAND_ISR_0_CORRFAIL_ERR_FIELD                   (_MK_MASK_CONST(0x1) << NAND_ISR_0_CORRFAIL_ERR_SHIFT)
+#define NAND_ISR_0_CORRFAIL_ERR_RANGE                   24:24
+#define NAND_ISR_0_CORRFAIL_ERR_WOFFSET                 0x0
+#define NAND_ISR_0_CORRFAIL_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_CORRFAIL_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_CORRFAIL_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_CORRFAIL_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1 = Flash7 is Ready interrupt occured 
+// This is SET only when NOT running in COMMAND QUEUE  MODE
+#define NAND_ISR_0_IS_RBSY7_SHIFT                       _MK_SHIFT_CONST(15)
+#define NAND_ISR_0_IS_RBSY7_FIELD                       (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY7_SHIFT)
+#define NAND_ISR_0_IS_RBSY7_RANGE                       15:15
+#define NAND_ISR_0_IS_RBSY7_WOFFSET                     0x0
+#define NAND_ISR_0_IS_RBSY7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_RBSY7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = Flash6 is Ready interrupt occured
+// This is SET only when NOT running in COMMAND QUEUE MODE
+#define NAND_ISR_0_IS_RBSY6_SHIFT                       _MK_SHIFT_CONST(14)
+#define NAND_ISR_0_IS_RBSY6_FIELD                       (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY6_SHIFT)
+#define NAND_ISR_0_IS_RBSY6_RANGE                       14:14
+#define NAND_ISR_0_IS_RBSY6_WOFFSET                     0x0
+#define NAND_ISR_0_IS_RBSY6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_RBSY6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = Flash5 is Ready interrupt occured
+// This is SET only when NOT running in COMMAND QUEUE MODE
+#define NAND_ISR_0_IS_RBSY5_SHIFT                       _MK_SHIFT_CONST(13)
+#define NAND_ISR_0_IS_RBSY5_FIELD                       (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY5_SHIFT)
+#define NAND_ISR_0_IS_RBSY5_RANGE                       13:13
+#define NAND_ISR_0_IS_RBSY5_WOFFSET                     0x0
+#define NAND_ISR_0_IS_RBSY5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_RBSY5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = Flash4 is Ready interrupt occured
+// This is SET only when NOT running in COMMAND QUEUE MODE
+#define NAND_ISR_0_IS_RBSY4_SHIFT                       _MK_SHIFT_CONST(12)
+#define NAND_ISR_0_IS_RBSY4_FIELD                       (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY4_SHIFT)
+#define NAND_ISR_0_IS_RBSY4_RANGE                       12:12
+#define NAND_ISR_0_IS_RBSY4_WOFFSET                     0x0
+#define NAND_ISR_0_IS_RBSY4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_RBSY4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = Flash3 is Ready interrupt occured
+// This is SET only when NOT running in COMMAND QUEUE MODE
+#define NAND_ISR_0_IS_RBSY3_SHIFT                       _MK_SHIFT_CONST(11)
+#define NAND_ISR_0_IS_RBSY3_FIELD                       (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY3_SHIFT)
+#define NAND_ISR_0_IS_RBSY3_RANGE                       11:11
+#define NAND_ISR_0_IS_RBSY3_WOFFSET                     0x0
+#define NAND_ISR_0_IS_RBSY3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_RBSY3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = Flash2 is Ready interrupt occured
+// This is SET only when NOT running in COMMAND QUEUE MODE
+#define NAND_ISR_0_IS_RBSY2_SHIFT                       _MK_SHIFT_CONST(10)
+#define NAND_ISR_0_IS_RBSY2_FIELD                       (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY2_SHIFT)
+#define NAND_ISR_0_IS_RBSY2_RANGE                       10:10
+#define NAND_ISR_0_IS_RBSY2_WOFFSET                     0x0
+#define NAND_ISR_0_IS_RBSY2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_RBSY2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = Flash1 is Ready interrupt occured
+// This is SET only when NOT running in COMMAND QUEUE MODE
+#define NAND_ISR_0_IS_RBSY1_SHIFT                       _MK_SHIFT_CONST(9)
+#define NAND_ISR_0_IS_RBSY1_FIELD                       (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY1_SHIFT)
+#define NAND_ISR_0_IS_RBSY1_RANGE                       9:9
+#define NAND_ISR_0_IS_RBSY1_WOFFSET                     0x0
+#define NAND_ISR_0_IS_RBSY1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_RBSY1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = Flash0 is Ready interrupt occured
+// This is SET only when NOT running in COMMAND QUEUE MODE
+#define NAND_ISR_0_IS_RBSY0_SHIFT                       _MK_SHIFT_CONST(8)
+#define NAND_ISR_0_IS_RBSY0_FIELD                       (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_RBSY0_SHIFT)
+#define NAND_ISR_0_IS_RBSY0_RANGE                       8:8
+#define NAND_ISR_0_IS_RBSY0_WOFFSET                     0x0
+#define NAND_ISR_0_IS_RBSY0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_RBSY0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_RBSY0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1 = FIFO under run interrupt occured
+// this should not happen in general usage, if it happens
+// there is a potential h/w issue.
+#define NAND_ISR_0_IS_UND_SHIFT                 _MK_SHIFT_CONST(7)
+#define NAND_ISR_0_IS_UND_FIELD                 (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_UND_SHIFT)
+#define NAND_ISR_0_IS_UND_RANGE                 7:7
+#define NAND_ISR_0_IS_UND_WOFFSET                       0x0
+#define NAND_ISR_0_IS_UND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_UND_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_UND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_UND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 1 = FIFO is Overrun
+// this should not happen in general usage, if it happens
+// there is potential h/w issue.
+#define NAND_ISR_0_IS_OVR_SHIFT                 _MK_SHIFT_CONST(6)
+#define NAND_ISR_0_IS_OVR_FIELD                 (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_OVR_SHIFT)
+#define NAND_ISR_0_IS_OVR_RANGE                 6:6
+#define NAND_ISR_0_IS_OVR_WOFFSET                       0x0
+#define NAND_ISR_0_IS_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 1 = Command operations are completed as per NAND 
+//     command register settings.
+//     This is set ONLY when not running in COMMAND QUEUE  MODE
+#define NAND_ISR_0_IS_CMD_DONE_SHIFT                    _MK_SHIFT_CONST(5)
+#define NAND_ISR_0_IS_CMD_DONE_FIELD                    (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_CMD_DONE_SHIFT)
+#define NAND_ISR_0_IS_CMD_DONE_RANGE                    5:5
+#define NAND_ISR_0_IS_CMD_DONE_WOFFSET                  0x0
+#define NAND_ISR_0_IS_CMD_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_CMD_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_CMD_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_CMD_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 = ECC error generated for following reasons.  
+//     ->ecc decode resulted in uncorrectable errors in one of 
+//       sector(sub-page)
+//     ->ecc decode resulted in correctable errors more than
+//       trigger level as defined in TRIG_LVL in NAND_CONFIG
+//       register
+// Bit is set for legacy mode of ECC selection with HW_ECC & ECC_TAG_EN only.
+// i.e. for RS/Hamming selection. Will not be set for BCH selection
+//
+#define NAND_ISR_0_IS_ECC_ERR_SHIFT                     _MK_SHIFT_CONST(4)
+#define NAND_ISR_0_IS_ECC_ERR_FIELD                     (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_ECC_ERR_SHIFT)
+#define NAND_ISR_0_IS_ECC_ERR_RANGE                     4:4
+#define NAND_ISR_0_IS_ECC_ERR_WOFFSET                   0x0
+#define NAND_ISR_0_IS_ECC_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_ECC_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_ECC_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_ECC_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 = Command queue execution completed 
+#define NAND_ISR_0_IS_LL_DONE_SHIFT                     _MK_SHIFT_CONST(3)
+#define NAND_ISR_0_IS_LL_DONE_FIELD                     (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_LL_DONE_SHIFT)
+#define NAND_ISR_0_IS_LL_DONE_RANGE                     3:3
+#define NAND_ISR_0_IS_LL_DONE_WOFFSET                   0x0
+#define NAND_ISR_0_IS_LL_DONE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_LL_DONE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_LL_DONE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_LL_DONE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 = One of the Command queue packet execution  returned ERROR
+#define NAND_ISR_0_IS_LL_ERR_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_ISR_0_IS_LL_ERR_FIELD                      (_MK_MASK_CONST(0x1) << NAND_ISR_0_IS_LL_ERR_SHIFT)
+#define NAND_ISR_0_IS_LL_ERR_RANGE                      2:2
+#define NAND_ISR_0_IS_LL_ERR_WOFFSET                    0x0
+#define NAND_ISR_0_IS_LL_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_LL_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_ISR_0_IS_LL_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_ISR_0_IS_LL_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_IER_0  
+#define NAND_IER_0                      _MK_ADDR_CONST(0xc)
+#define NAND_IER_0_SECURE                       0x0
+#define NAND_IER_0_WORD_COUNT                   0x1
+#define NAND_IER_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_IER_0_RESET_MASK                   _MK_MASK_CONST(0xffffd)
+#define NAND_IER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_IER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_IER_0_READ_MASK                    _MK_MASK_CONST(0xffffd)
+#define NAND_IER_0_WRITE_MASK                   _MK_MASK_CONST(0xffffd)
+// Trigger for correctable error Interrupts by main ECC RS decoder, if 
+// HW_ERR_CORRECTION feature is enabled. Mechansim for SW to get an idea
+// on error pattern development over a period of usage. NAND controller
+// will trigger interrupt if the current main page read transfer resulted 
+// in correctable errors reached this trigger value for Reed-Solomon selection. 
+// For example, of ECC_ERROR interrupt for t=4, with ERR_TRIG_VAL=3 could 
+// imply only one of the following.
+// a) If DEC_FAIL = 1, one of the sub-page decode returned failure because no. 
+// of symbol errors are more than 4.
+// b) If DEC_FAIL = 0, one of the sub-page decode returned 3 correctable errors.
+#define NAND_IER_0_ERR_TRIG_VAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define NAND_IER_0_ERR_TRIG_VAL_FIELD                   (_MK_MASK_CONST(0xf) << NAND_IER_0_ERR_TRIG_VAL_SHIFT)
+#define NAND_IER_0_ERR_TRIG_VAL_RANGE                   19:16
+#define NAND_IER_0_ERR_TRIG_VAL_WOFFSET                 0x0
+#define NAND_IER_0_ERR_TRIG_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_IER_0_ERR_TRIG_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define NAND_IER_0_ERR_TRIG_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_IER_0_ERR_TRIG_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_0                     _MK_ENUM_CONST(0)    // // Reports for every single error, equivalent to ECC_ERROR interrupt without
+// HW_ERR_CORRECTION feature.
+
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_1                     _MK_ENUM_CONST(1)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_2                     _MK_ENUM_CONST(2)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_3                     _MK_ENUM_CONST(3)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_4                     _MK_ENUM_CONST(4)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_5                     _MK_ENUM_CONST(5)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_6                     _MK_ENUM_CONST(6)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_7                     _MK_ENUM_CONST(7)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_8                     _MK_ENUM_CONST(8)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_9                     _MK_ENUM_CONST(9)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_10                    _MK_ENUM_CONST(10)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_11                    _MK_ENUM_CONST(11)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_12                    _MK_ENUM_CONST(12)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_13                    _MK_ENUM_CONST(13)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_14                    _MK_ENUM_CONST(14)
+#define NAND_IER_0_ERR_TRIG_VAL_CORR_ERRS_15                    _MK_ENUM_CONST(15)
+
+// 1 = flash7 RBSY line High interrupt
+#define NAND_IER_0_IE_RBSY7_SHIFT                       _MK_SHIFT_CONST(15)
+#define NAND_IER_0_IE_RBSY7_FIELD                       (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY7_SHIFT)
+#define NAND_IER_0_IE_RBSY7_RANGE                       15:15
+#define NAND_IER_0_IE_RBSY7_WOFFSET                     0x0
+#define NAND_IER_0_IE_RBSY7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_RBSY7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY7_DISABLE                     _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_RBSY7_ENABLE                      _MK_ENUM_CONST(1)
+
+// 1 = flash6 RBSY line High interrupt
+#define NAND_IER_0_IE_RBSY6_SHIFT                       _MK_SHIFT_CONST(14)
+#define NAND_IER_0_IE_RBSY6_FIELD                       (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY6_SHIFT)
+#define NAND_IER_0_IE_RBSY6_RANGE                       14:14
+#define NAND_IER_0_IE_RBSY6_WOFFSET                     0x0
+#define NAND_IER_0_IE_RBSY6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_RBSY6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY6_DISABLE                     _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_RBSY6_ENABLE                      _MK_ENUM_CONST(1)
+
+// 1 = flash5 RBSY line High interrupt
+#define NAND_IER_0_IE_RBSY5_SHIFT                       _MK_SHIFT_CONST(13)
+#define NAND_IER_0_IE_RBSY5_FIELD                       (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY5_SHIFT)
+#define NAND_IER_0_IE_RBSY5_RANGE                       13:13
+#define NAND_IER_0_IE_RBSY5_WOFFSET                     0x0
+#define NAND_IER_0_IE_RBSY5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_RBSY5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY5_DISABLE                     _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_RBSY5_ENABLE                      _MK_ENUM_CONST(1)
+
+// 1 = flash4 RBSY line High interrupt
+#define NAND_IER_0_IE_RBSY4_SHIFT                       _MK_SHIFT_CONST(12)
+#define NAND_IER_0_IE_RBSY4_FIELD                       (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY4_SHIFT)
+#define NAND_IER_0_IE_RBSY4_RANGE                       12:12
+#define NAND_IER_0_IE_RBSY4_WOFFSET                     0x0
+#define NAND_IER_0_IE_RBSY4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_RBSY4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY4_DISABLE                     _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_RBSY4_ENABLE                      _MK_ENUM_CONST(1)
+
+// 1 = flash3 RBSY line High interrupt
+#define NAND_IER_0_IE_RBSY3_SHIFT                       _MK_SHIFT_CONST(11)
+#define NAND_IER_0_IE_RBSY3_FIELD                       (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY3_SHIFT)
+#define NAND_IER_0_IE_RBSY3_RANGE                       11:11
+#define NAND_IER_0_IE_RBSY3_WOFFSET                     0x0
+#define NAND_IER_0_IE_RBSY3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_RBSY3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY3_DISABLE                     _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_RBSY3_ENABLE                      _MK_ENUM_CONST(1)
+
+// 1 = flash2 RBSY line High interrupt 
+#define NAND_IER_0_IE_RBSY2_SHIFT                       _MK_SHIFT_CONST(10)
+#define NAND_IER_0_IE_RBSY2_FIELD                       (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY2_SHIFT)
+#define NAND_IER_0_IE_RBSY2_RANGE                       10:10
+#define NAND_IER_0_IE_RBSY2_WOFFSET                     0x0
+#define NAND_IER_0_IE_RBSY2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_RBSY2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY2_DISABLE                     _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_RBSY2_ENABLE                      _MK_ENUM_CONST(1)
+
+// 1 = flash1 RBSY line High interrupt
+#define NAND_IER_0_IE_RBSY1_SHIFT                       _MK_SHIFT_CONST(9)
+#define NAND_IER_0_IE_RBSY1_FIELD                       (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY1_SHIFT)
+#define NAND_IER_0_IE_RBSY1_RANGE                       9:9
+#define NAND_IER_0_IE_RBSY1_WOFFSET                     0x0
+#define NAND_IER_0_IE_RBSY1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_RBSY1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY1_DISABLE                     _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_RBSY1_ENABLE                      _MK_ENUM_CONST(1)
+
+// 1 = flash0 RBSY line High interrupt
+#define NAND_IER_0_IE_RBSY0_SHIFT                       _MK_SHIFT_CONST(8)
+#define NAND_IER_0_IE_RBSY0_FIELD                       (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_RBSY0_SHIFT)
+#define NAND_IER_0_IE_RBSY0_RANGE                       8:8
+#define NAND_IER_0_IE_RBSY0_WOFFSET                     0x0
+#define NAND_IER_0_IE_RBSY0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_RBSY0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_RBSY0_DISABLE                     _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_RBSY0_ENABLE                      _MK_ENUM_CONST(1)
+
+// 1 = FIFO underrun interrupt 
+#define NAND_IER_0_IE_UND_SHIFT                 _MK_SHIFT_CONST(7)
+#define NAND_IER_0_IE_UND_FIELD                 (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_UND_SHIFT)
+#define NAND_IER_0_IE_UND_RANGE                 7:7
+#define NAND_IER_0_IE_UND_WOFFSET                       0x0
+#define NAND_IER_0_IE_UND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_UND_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_UND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_UND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_UND_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_UND_ENABLE                        _MK_ENUM_CONST(1)
+
+// 1 = FIFO overrun interupt 
+#define NAND_IER_0_IE_OVR_SHIFT                 _MK_SHIFT_CONST(6)
+#define NAND_IER_0_IE_OVR_FIELD                 (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_OVR_SHIFT)
+#define NAND_IER_0_IE_OVR_RANGE                 6:6
+#define NAND_IER_0_IE_OVR_WOFFSET                       0x0
+#define NAND_IER_0_IE_OVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_OVR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_OVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_OVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_OVR_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_OVR_ENABLE                        _MK_ENUM_CONST(1)
+
+// 1 = Command operations are completed as per NAND  
+//     command register settings.
+#define NAND_IER_0_IE_CMD_DONE_SHIFT                    _MK_SHIFT_CONST(5)
+#define NAND_IER_0_IE_CMD_DONE_FIELD                    (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_CMD_DONE_SHIFT)
+#define NAND_IER_0_IE_CMD_DONE_RANGE                    5:5
+#define NAND_IER_0_IE_CMD_DONE_WOFFSET                  0x0
+#define NAND_IER_0_IE_CMD_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_CMD_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_CMD_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_CMD_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_CMD_DONE_DISABLE                  _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_CMD_DONE_ENABLE                   _MK_ENUM_CONST(1)
+
+// 1 = ECC error interrupt 
+// please refer to IS_ECC_ERR above for interrupt event
+// details
+#define NAND_IER_0_IE_ECC_ERR_SHIFT                     _MK_SHIFT_CONST(4)
+#define NAND_IER_0_IE_ECC_ERR_FIELD                     (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_ECC_ERR_SHIFT)
+#define NAND_IER_0_IE_ECC_ERR_RANGE                     4:4
+#define NAND_IER_0_IE_ECC_ERR_WOFFSET                   0x0
+#define NAND_IER_0_IE_ECC_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_ECC_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_ECC_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_ECC_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_ECC_ERR_DISABLE                   _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_ECC_ERR_ENABLE                    _MK_ENUM_CONST(1)
+
+// Command queue execution completion interrupt
+#define NAND_IER_0_IE_LL_DONE_SHIFT                     _MK_SHIFT_CONST(3)
+#define NAND_IER_0_IE_LL_DONE_FIELD                     (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_LL_DONE_SHIFT)
+#define NAND_IER_0_IE_LL_DONE_RANGE                     3:3
+#define NAND_IER_0_IE_LL_DONE_WOFFSET                   0x0
+#define NAND_IER_0_IE_LL_DONE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_LL_DONE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_LL_DONE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_LL_DONE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_LL_DONE_DISABLE                   _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_LL_DONE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Flash errors in Command queue  execution interrupt
+#define NAND_IER_0_IE_LL_ERR_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_IER_0_IE_LL_ERR_FIELD                      (_MK_MASK_CONST(0x1) << NAND_IER_0_IE_LL_ERR_SHIFT)
+#define NAND_IER_0_IE_LL_ERR_RANGE                      2:2
+#define NAND_IER_0_IE_LL_ERR_WOFFSET                    0x0
+#define NAND_IER_0_IE_LL_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_LL_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_IER_0_IE_LL_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_LL_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_IER_0_IE_LL_ERR_DISABLE                    _MK_ENUM_CONST(0)
+#define NAND_IER_0_IE_LL_ERR_ENABLE                     _MK_ENUM_CONST(1)
+
+// 0 = Masks all of the interrupts, and interrupt to
+//     signal to cpu is disabled.
+#define NAND_IER_0_GIE_SHIFT                    _MK_SHIFT_CONST(0)
+#define NAND_IER_0_GIE_FIELD                    (_MK_MASK_CONST(0x1) << NAND_IER_0_GIE_SHIFT)
+#define NAND_IER_0_GIE_RANGE                    0:0
+#define NAND_IER_0_GIE_WOFFSET                  0x0
+#define NAND_IER_0_GIE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_GIE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define NAND_IER_0_GIE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_IER_0_GIE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_IER_0_GIE_DISABLE                  _MK_ENUM_CONST(0)
+#define NAND_IER_0_GIE_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register NAND_CONFIG_0  
+#define NAND_CONFIG_0                   _MK_ADDR_CONST(0x10)
+#define NAND_CONFIG_0_SECURE                    0x0
+#define NAND_CONFIG_0_WORD_COUNT                        0x1
+#define NAND_CONFIG_0_RESET_VAL                         _MK_MASK_CONST(0x10030000)
+#define NAND_CONFIG_0_RESET_MASK                        _MK_MASK_CONST(0xfbffffff)
+#define NAND_CONFIG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_READ_MASK                         _MK_MASK_CONST(0xfbffffff)
+#define NAND_CONFIG_0_WRITE_MASK                        _MK_MASK_CONST(0xfbffffff)
+// HW Error detection enable for Main page read data
+#define NAND_CONFIG_0_HW_ECC_SHIFT                      _MK_SHIFT_CONST(31)
+#define NAND_CONFIG_0_HW_ECC_FIELD                      (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_HW_ECC_SHIFT)
+#define NAND_CONFIG_0_HW_ECC_RANGE                      31:31
+#define NAND_CONFIG_0_HW_ECC_WOFFSET                    0x0
+#define NAND_CONFIG_0_HW_ECC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_HW_ECC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_HW_ECC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_HW_ECC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_HW_ECC_DISABLE                    _MK_ENUM_CONST(0)
+#define NAND_CONFIG_0_HW_ECC_ENABLE                     _MK_ENUM_CONST(1)
+
+// HE Error detection algorithm selection
+#define NAND_CONFIG_0_ECC_SEL_SHIFT                     _MK_SHIFT_CONST(30)
+#define NAND_CONFIG_0_ECC_SEL_FIELD                     (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_ECC_SEL_SHIFT)
+#define NAND_CONFIG_0_ECC_SEL_RANGE                     30:30
+#define NAND_CONFIG_0_ECC_SEL_WOFFSET                   0x0
+#define NAND_CONFIG_0_ECC_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_ECC_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_ECC_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_ECC_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_ECC_SEL_HAMMING                   _MK_ENUM_CONST(0)
+#define NAND_CONFIG_0_ECC_SEL_RS                        _MK_ENUM_CONST(1)
+
+// Enable Auto HW correction. Emulates SW behavior of reading the error 
+// vectors from system buffer as pointed in the error vector address register,
+// applies correction and updates the memory word with corrected data.
+// This is done on page basis as soon as the decode information is avialable
+// as the flash read is placed in memory.
+#define NAND_CONFIG_0_HW_ERR_CORRECTION_SHIFT                   _MK_SHIFT_CONST(29)
+#define NAND_CONFIG_0_HW_ERR_CORRECTION_FIELD                   (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_HW_ERR_CORRECTION_SHIFT)
+#define NAND_CONFIG_0_HW_ERR_CORRECTION_RANGE                   29:29
+#define NAND_CONFIG_0_HW_ERR_CORRECTION_WOFFSET                 0x0
+#define NAND_CONFIG_0_HW_ERR_CORRECTION_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_HW_ERR_CORRECTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_HW_ERR_CORRECTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_HW_ERR_CORRECTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_HW_ERR_CORRECTION_DISABLE                 _MK_ENUM_CONST(0)
+#define NAND_CONFIG_0_HW_ERR_CORRECTION_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable next page flash READ data transfer even before current page ECC 
+// Decode is completed. If disabled, new page READ is started  only 
+// after the previous page flash read, ECC decode(detection) are completed.
+#define NAND_CONFIG_0_PIPELINE_EN_SHIFT                 _MK_SHIFT_CONST(28)
+#define NAND_CONFIG_0_PIPELINE_EN_FIELD                 (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_PIPELINE_EN_SHIFT)
+#define NAND_CONFIG_0_PIPELINE_EN_RANGE                 28:28
+#define NAND_CONFIG_0_PIPELINE_EN_WOFFSET                       0x0
+#define NAND_CONFIG_0_PIPELINE_EN_DEFAULT                       _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_PIPELINE_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_PIPELINE_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_PIPELINE_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_PIPELINE_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_CONFIG_0_PIPELINE_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// HW Error detection enable for Spare read data
+#define NAND_CONFIG_0_ECC_EN_TAG_SHIFT                  _MK_SHIFT_CONST(27)
+#define NAND_CONFIG_0_ECC_EN_TAG_FIELD                  (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_ECC_EN_TAG_SHIFT)
+#define NAND_CONFIG_0_ECC_EN_TAG_RANGE                  27:27
+#define NAND_CONFIG_0_ECC_EN_TAG_WOFFSET                        0x0
+#define NAND_CONFIG_0_ECC_EN_TAG_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_ECC_EN_TAG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_ECC_EN_TAG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_ECC_EN_TAG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_ECC_EN_TAG_DISABLE                        _MK_ENUM_CONST(0)
+#define NAND_CONFIG_0_ECC_EN_TAG_ENABLE                 _MK_ENUM_CONST(1)
+
+// HW Error correction algorithm tValue for RS EDC selction  11 = Rsvd
+#define NAND_CONFIG_0_TVALUE_SHIFT                      _MK_SHIFT_CONST(24)
+#define NAND_CONFIG_0_TVALUE_FIELD                      (_MK_MASK_CONST(0x3) << NAND_CONFIG_0_TVALUE_SHIFT)
+#define NAND_CONFIG_0_TVALUE_RANGE                      25:24
+#define NAND_CONFIG_0_TVALUE_WOFFSET                    0x0
+#define NAND_CONFIG_0_TVALUE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_TVALUE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define NAND_CONFIG_0_TVALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_TVALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_TVALUE_TVAL4                      _MK_ENUM_CONST(0)    // // (t=4) 4 bit error correction per each 512 bytes of data
+
+#define NAND_CONFIG_0_TVALUE_TVAL6                      _MK_ENUM_CONST(1)    // // (t=6) 6 bit error correction per each 512 bytes of data
+
+#define NAND_CONFIG_0_TVALUE_TVAL8                      _MK_ENUM_CONST(2)    // // (t=8) 8 bit error correction per each 512 bytes of data
+
+#define NAND_CONFIG_0_TVALUE_TVAL_RSVD                  _MK_ENUM_CONST(3)
+
+// Skip spare region in flash to start read/write bytes after 
+// completing the main area transfer.
+// SKIP_SPAE_SEL below indicates how many bytes in spare
+// area of flash to be skipped over either for reading/writing
+// all spare access will offset to this.
+#define NAND_CONFIG_0_SKIP_SPARE_SHIFT                  _MK_SHIFT_CONST(23)
+#define NAND_CONFIG_0_SKIP_SPARE_FIELD                  (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_SKIP_SPARE_SHIFT)
+#define NAND_CONFIG_0_SKIP_SPARE_RANGE                  23:23
+#define NAND_CONFIG_0_SKIP_SPARE_WOFFSET                        0x0
+#define NAND_CONFIG_0_SKIP_SPARE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_SKIP_SPARE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_SKIP_SPARE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_SKIP_SPARE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_SKIP_SPARE_DISABLE                        _MK_ENUM_CONST(0)
+#define NAND_CONFIG_0_SKIP_SPARE_ENABLE                 _MK_ENUM_CONST(1)
+
+//  RBSY0 is from Flash card 0
+#define NAND_CONFIG_0_COM_BSY_SHIFT                     _MK_SHIFT_CONST(22)
+#define NAND_CONFIG_0_COM_BSY_FIELD                     (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_COM_BSY_SHIFT)
+#define NAND_CONFIG_0_COM_BSY_RANGE                     22:22
+#define NAND_CONFIG_0_COM_BSY_WOFFSET                   0x0
+#define NAND_CONFIG_0_COM_BSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_COM_BSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_COM_BSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_COM_BSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_COM_BSY_DISABLE                   _MK_ENUM_CONST(0)    // // RBSY0 seen by HW is wired AND of all flash cards connected
+
+#define NAND_CONFIG_0_COM_BSY_ENABLE                    _MK_ENUM_CONST(1)
+
+//Flash read/write databus width selection Datsbus width 8-bit
+#define NAND_CONFIG_0_BUS_WIDTH_SHIFT                   _MK_SHIFT_CONST(21)
+#define NAND_CONFIG_0_BUS_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_BUS_WIDTH_SHIFT)
+#define NAND_CONFIG_0_BUS_WIDTH_RANGE                   21:21
+#define NAND_CONFIG_0_BUS_WIDTH_WOFFSET                 0x0
+#define NAND_CONFIG_0_BUS_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_BUS_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_BUS_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_BUS_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_BUS_WIDTH_BUS_WIDTH_8                     _MK_ENUM_CONST(0)    // // Databus width 16-bit
+
+#define NAND_CONFIG_0_BUS_WIDTH_BUS_WIDTH_16                    _MK_ENUM_CONST(1)
+
+// LPDDR1 mode of pin ordering Pin ordering to be package friendly with LPDDR1
+#define NAND_CONFIG_0_LPDDR1_MODE_SHIFT                 _MK_SHIFT_CONST(20)
+#define NAND_CONFIG_0_LPDDR1_MODE_FIELD                 (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_LPDDR1_MODE_SHIFT)
+#define NAND_CONFIG_0_LPDDR1_MODE_RANGE                 20:20
+#define NAND_CONFIG_0_LPDDR1_MODE_WOFFSET                       0x0
+#define NAND_CONFIG_0_LPDDR1_MODE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_LPDDR1_MODE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_LPDDR1_MODE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_LPDDR1_MODE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_LPDDR1_MODE_DISABLE                       _MK_ENUM_CONST(0)    // // Standard mode of pin ordering
+
+#define NAND_CONFIG_0_LPDDR1_MODE_ENABLE                        _MK_ENUM_CONST(1)
+
+// EDO mode of flash read data sampling sampled on posedge of REN 
+#define NAND_CONFIG_0_EDO_MODE_SHIFT                    _MK_SHIFT_CONST(19)
+#define NAND_CONFIG_0_EDO_MODE_FIELD                    (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_EDO_MODE_SHIFT)
+#define NAND_CONFIG_0_EDO_MODE_RANGE                    19:19
+#define NAND_CONFIG_0_EDO_MODE_WOFFSET                  0x0
+#define NAND_CONFIG_0_EDO_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_EDO_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_EDO_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_EDO_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_EDO_MODE_DISABLE                  _MK_ENUM_CONST(0)    // // sampled on completion of read cycle time
+
+#define NAND_CONFIG_0_EDO_MODE_ENABLE                   _MK_ENUM_CONST(1)
+
+// Page size selection - depends on Flash used.
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_SHIFT                       _MK_SHIFT_CONST(16)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_FIELD                       (_MK_MASK_CONST(0x7) << NAND_CONFIG_0_PAGE_SIZE_SEL_SHIFT)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_RANGE                       18:16
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_WOFFSET                     0x0
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_DEFAULT                     _MK_MASK_CONST(0x3)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_256                       _MK_ENUM_CONST(0)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_512                       _MK_ENUM_CONST(1)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_1024                      _MK_ENUM_CONST(2)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_2048                      _MK_ENUM_CONST(3)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_4096                      _MK_ENUM_CONST(4)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_RSVD1                     _MK_ENUM_CONST(5)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_RSVD2                     _MK_ENUM_CONST(6)
+#define NAND_CONFIG_0_PAGE_SIZE_SEL_PAGE_SIZE_RSVD3                     _MK_ENUM_CONST(7)
+
+// Size in granularity of 4 bytes to skippedd for spare access
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_SHIFT                      _MK_SHIFT_CONST(14)
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_FIELD                      (_MK_MASK_CONST(0x3) << NAND_CONFIG_0_SKIP_SPARE_SEL_SHIFT)
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_RANGE                      15:14
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_WOFFSET                    0x0
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_SKIP_SPARE_SIZE_4                  _MK_ENUM_CONST(0)
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_SKIP_SPARE_SIZE_8                  _MK_ENUM_CONST(1)
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_SKIP_SPARE_SIZE_12                 _MK_ENUM_CONST(2)
+#define NAND_CONFIG_0_SKIP_SPARE_SEL_SKIP_SPARE_SIZE_16                 _MK_ENUM_CONST(3)
+
+// Debug mode selection for HW debug
+#define NAND_CONFIG_0_DEBUG_MODE_SHIFT                  _MK_SHIFT_CONST(13)
+#define NAND_CONFIG_0_DEBUG_MODE_FIELD                  (_MK_MASK_CONST(0x1) << NAND_CONFIG_0_DEBUG_MODE_SHIFT)
+#define NAND_CONFIG_0_DEBUG_MODE_RANGE                  13:13
+#define NAND_CONFIG_0_DEBUG_MODE_WOFFSET                        0x0
+#define NAND_CONFIG_0_DEBUG_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_DEBUG_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define NAND_CONFIG_0_DEBUG_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_DEBUG_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Debug selection for HW debug
+#define NAND_CONFIG_0_DEBUG_SEL_SHIFT                   _MK_SHIFT_CONST(9)
+#define NAND_CONFIG_0_DEBUG_SEL_FIELD                   (_MK_MASK_CONST(0xf) << NAND_CONFIG_0_DEBUG_SEL_SHIFT)
+#define NAND_CONFIG_0_DEBUG_SEL_RANGE                   12:9
+#define NAND_CONFIG_0_DEBUG_SEL_WOFFSET                 0x0
+#define NAND_CONFIG_0_DEBUG_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_DEBUG_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define NAND_CONFIG_0_DEBUG_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_DEBUG_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Block Size in Bytes for TAG  data from spare area of flash.
+// This is used for specifying the size of the TAG Block data byets 
+// to be move/from to spare area. Used when B_VALID is true.
+// Specified in Bytes (n-1 encoding)
+#define NAND_CONFIG_0_TAG_BYTE_SIZE_SHIFT                       _MK_SHIFT_CONST(0)
+#define NAND_CONFIG_0_TAG_BYTE_SIZE_FIELD                       (_MK_MASK_CONST(0x1ff) << NAND_CONFIG_0_TAG_BYTE_SIZE_SHIFT)
+#define NAND_CONFIG_0_TAG_BYTE_SIZE_RANGE                       8:0
+#define NAND_CONFIG_0_TAG_BYTE_SIZE_WOFFSET                     0x0
+#define NAND_CONFIG_0_TAG_BYTE_SIZE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_TAG_BYTE_SIZE_DEFAULT_MASK                        _MK_MASK_CONST(0x1ff)
+#define NAND_CONFIG_0_TAG_BYTE_SIZE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_CONFIG_0_TAG_BYTE_SIZE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register NAND_TIMING_0  
+#define NAND_TIMING_0                   _MK_ADDR_CONST(0x14)
+#define NAND_TIMING_0_SECURE                    0x0
+#define NAND_TIMING_0_WORD_COUNT                        0x1
+#define NAND_TIMING_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define NAND_TIMING_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define NAND_TIMING_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Read pulse width(RE Low time)timing for status read cycles 
+// Generated timing = (n+1) * NAND_CLK_PERIOD ns,
+// 
+// -----------------------------------------------------------------------------
+// GUIDELINE: for tRP_RESP/tRP timing 
+// -----------------------------------------------------------------------------
+//        
+// non-EDO mode: Max(tRP, tREA) timing + 6ns (round trip delay) 
+// EDO mode:     tRP timing from flash datasheet
+//
+// Notes: 
+// (1)"round trip delay" to account for - REN out PAD delay + REN out board delay 
+//        + DATA driven OUT from flash to chip input + DATA INPUT pad delay. 
+//
+//    Based on AP15 timings, PAD delays attribute to 4ns and rest
+//    2ns is estimated for board delays. If it's more than one need to 
+//    increase the "round trip delay" number to come up 
+//    with "tRP/TRP_RESP" timing requirement. 
+// (2)For EDO modes - since controller latches data without regard 
+//    to `nRE' (REN) posedge tREA, round trip delay factors need not 
+//    be considered. 
+#define NAND_TIMING_0_TRP_RESP_CNT_SHIFT                        _MK_SHIFT_CONST(28)
+#define NAND_TIMING_0_TRP_RESP_CNT_FIELD                        (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TRP_RESP_CNT_SHIFT)
+#define NAND_TIMING_0_TRP_RESP_CNT_RANGE                        31:28
+#define NAND_TIMING_0_TRP_RESP_CNT_WOFFSET                      0x0
+#define NAND_TIMING_0_TRP_RESP_CNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TRP_RESP_CNT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define NAND_TIMING_0_TRP_RESP_CNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TRP_RESP_CNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// WE High to RBSY low asserted (by flash) timing
+// Generated timing = (n+1) * NAND_CLK_PERIOD ns.
+// -----------------------------------------------------------------------------
+// GUIDELINE: Refer to tWB timing from flash datasheet
+// -----------------------------------------------------------------------------
+#define NAND_TIMING_0_TWB_CNT_SHIFT                     _MK_SHIFT_CONST(24)
+#define NAND_TIMING_0_TWB_CNT_FIELD                     (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TWB_CNT_SHIFT)
+#define NAND_TIMING_0_TWB_CNT_RANGE                     27:24
+#define NAND_TIMING_0_TWB_CNT_WOFFSET                   0x0
+#define NAND_TIMING_0_TWB_CNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TWB_CNT_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define NAND_TIMING_0_TWB_CNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TWB_CNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// RBSY High to RE low timing
+// Generated timing = (n+3) * NAND_CLK_PERIOD ns.
+// -----------------------------------------------------------------------------
+// GUIDELINE: Program Max(tCR, tAR, tRR) timings from flash data sheet
+// -----------------------------------------------------------------------------
+#define NAND_TIMING_0_TCR_TAR_TRR_CNT_SHIFT                     _MK_SHIFT_CONST(20)
+#define NAND_TIMING_0_TCR_TAR_TRR_CNT_FIELD                     (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TCR_TAR_TRR_CNT_SHIFT)
+#define NAND_TIMING_0_TCR_TAR_TRR_CNT_RANGE                     23:20
+#define NAND_TIMING_0_TCR_TAR_TRR_CNT_WOFFSET                   0x0
+#define NAND_TIMING_0_TCR_TAR_TRR_CNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TCR_TAR_TRR_CNT_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define NAND_TIMING_0_TCR_TAR_TRR_CNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TCR_TAR_TRR_CNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// WE High to RE Low timing - Status Read Cycles
+// Generated timing = (n+1) * NAND_CLK_PERIOD ns.
+// -----------------------------------------------------------------------------
+// GUIDELINE: Refer to tWHR timing from flash data sheet
+// -----------------------------------------------------------------------------
+#define NAND_TIMING_0_TWHR_CNT_SHIFT                    _MK_SHIFT_CONST(16)
+#define NAND_TIMING_0_TWHR_CNT_FIELD                    (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TWHR_CNT_SHIFT)
+#define NAND_TIMING_0_TWHR_CNT_RANGE                    19:16
+#define NAND_TIMING_0_TWHR_CNT_WOFFSET                  0x0
+#define NAND_TIMING_0_TWHR_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TWHR_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define NAND_TIMING_0_TWHR_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TWHR_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CS/CLE/ALE Setup/Hold time.
+// Generated timing: 
+// tCLS/tALS/tCS [for setup timing] = [tCS_CNT + tWP CNT + 2 ] * NAND_CLK_PERIOD 
+// tCLH/tALH/tCH [for hold timing]  = [tCS_CNT + tWH CNT + 3 ] * NAND_CLK_PERIO
+// -----------------------------------------------------------------------------
+// GUIDELINE: Program for Max(tCS, tCH, tALS, tALH, tCLS, TCLH) timings from 
+//            flash datasheet
+// -----------------------------------------------------------------------------
+// This timing is met timing requirements.
+// 1. from CE Low -> WE posedge of CLE/ALE.
+// 2. from WE posedge of CLE to-> WE posedge of ALE.
+#define NAND_TIMING_0_TCS_CNT_SHIFT                     _MK_SHIFT_CONST(14)
+#define NAND_TIMING_0_TCS_CNT_FIELD                     (_MK_MASK_CONST(0x3) << NAND_TIMING_0_TCS_CNT_SHIFT)
+#define NAND_TIMING_0_TCS_CNT_RANGE                     15:14
+#define NAND_TIMING_0_TCS_CNT_WOFFSET                   0x0
+#define NAND_TIMING_0_TCS_CNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TCS_CNT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define NAND_TIMING_0_TCS_CNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TCS_CNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Write pulse HOLD time
+// Generated timing = (n+1) * NAND_CLK_PERIOD ns.
+// -----------------------------------------------------------------------------
+// GUIDELINE: Refer to tWH timing from flash datasheet
+// -----------------------------------------------------------------------------
+#define NAND_TIMING_0_TWH_CNT_SHIFT                     _MK_SHIFT_CONST(12)
+#define NAND_TIMING_0_TWH_CNT_FIELD                     (_MK_MASK_CONST(0x3) << NAND_TIMING_0_TWH_CNT_SHIFT)
+#define NAND_TIMING_0_TWH_CNT_RANGE                     13:12
+#define NAND_TIMING_0_TWH_CNT_WOFFSET                   0x0
+#define NAND_TIMING_0_TWH_CNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TWH_CNT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define NAND_TIMING_0_TWH_CNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TWH_CNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Write pulse width time
+// Generated timing = (n+1) * NAND_CLK_PERIOD ns.
+// -----------------------------------------------------------------------------
+// GUIDELINE: Refer to tWP timing from flash datasheet
+// -----------------------------------------------------------------------------
+#define NAND_TIMING_0_TWP_CNT_SHIFT                     _MK_SHIFT_CONST(8)
+#define NAND_TIMING_0_TWP_CNT_FIELD                     (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TWP_CNT_SHIFT)
+#define NAND_TIMING_0_TWP_CNT_RANGE                     11:8
+#define NAND_TIMING_0_TWP_CNT_WOFFSET                   0x0
+#define NAND_TIMING_0_TWP_CNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TWP_CNT_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define NAND_TIMING_0_TWP_CNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TWP_CNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define NAND_TIMING_0_NA1_SHIFT                 _MK_SHIFT_CONST(6)
+#define NAND_TIMING_0_NA1_FIELD                 (_MK_MASK_CONST(0x3) << NAND_TIMING_0_NA1_SHIFT)
+#define NAND_TIMING_0_NA1_RANGE                 7:6
+#define NAND_TIMING_0_NA1_WOFFSET                       0x0
+#define NAND_TIMING_0_NA1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_NA1_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define NAND_TIMING_0_NA1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_NA1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Read pulse HOLD time
+// Generated timing = (n+1) * NAND_CLK_PERIOD ns.
+// -----------------------------------------------------------------------------
+// GUIDELINE: Refer to tRH timing from flash datasheet
+// -----------------------------------------------------------------------------
+#define NAND_TIMING_0_TRH_CNT_SHIFT                     _MK_SHIFT_CONST(4)
+#define NAND_TIMING_0_TRH_CNT_FIELD                     (_MK_MASK_CONST(0x3) << NAND_TIMING_0_TRH_CNT_SHIFT)
+#define NAND_TIMING_0_TRH_CNT_RANGE                     5:4
+#define NAND_TIMING_0_TRH_CNT_WOFFSET                   0x0
+#define NAND_TIMING_0_TRH_CNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TRH_CNT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define NAND_TIMING_0_TRH_CNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TRH_CNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Read pulse width(RE Low time)timing for Data read cycles 
+// Generated timing = (n+1) * NAND_CLKS,
+// 
+// where n - value programmed in the tRP_RESP_CNT field of timing register.
+//
+// -----------------------------------------------------------------------------
+// GUIDELINE: tRP_RESP/tRP timing register programming  
+// -----------------------------------------------------------------------------
+// non-EDO mode: Max(tRP, tREA) timing + 6ns (round trip delay) 
+// EDO mode:     tRP timing 
+//Notes: 
+// (1) "round trip delay" to account for - REN out PAD delay + REN out board delay 
+//     + DATA driven OUT from flash to chip input + DATA INPUT pad delay. 
+//     Based on AP15 timings, PAD delays attribute to 4ns and rest
+//     2ns is estimated for board delays. If it's more than one need to 
+//     increase the "round trip delay" number to come up 
+//     with "tRP/TRP_RESP" timing requirement. 
+// (2) For EDO modes - since controller latches data without regard 
+//     to `nRE' (REN) posedge tREA, round trip delay factors need not 
+//     be considered. 
+#define NAND_TIMING_0_TRP_CNT_SHIFT                     _MK_SHIFT_CONST(0)
+#define NAND_TIMING_0_TRP_CNT_FIELD                     (_MK_MASK_CONST(0xf) << NAND_TIMING_0_TRP_CNT_SHIFT)
+#define NAND_TIMING_0_TRP_CNT_RANGE                     3:0
+#define NAND_TIMING_0_TRP_CNT_WOFFSET                   0x0
+#define NAND_TIMING_0_TRP_CNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TRP_CNT_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define NAND_TIMING_0_TRP_CNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_TIMING_0_TRP_CNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register NAND_RESP_0  
+#define NAND_RESP_0                     _MK_ADDR_CONST(0x18)
+#define NAND_RESP_0_SECURE                      0x0
+#define NAND_RESP_0_WORD_COUNT                  0x1
+#define NAND_RESP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define NAND_RESP_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define NAND_RESP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_RESP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_RESP_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define NAND_RESP_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Write/Response data byte 3 (MSB)
+#define NAND_RESP_0_BYTE3_SHIFT                 _MK_SHIFT_CONST(24)
+#define NAND_RESP_0_BYTE3_FIELD                 (_MK_MASK_CONST(0xff) << NAND_RESP_0_BYTE3_SHIFT)
+#define NAND_RESP_0_BYTE3_RANGE                 31:24
+#define NAND_RESP_0_BYTE3_WOFFSET                       0x0
+#define NAND_RESP_0_BYTE3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_RESP_0_BYTE3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_RESP_0_BYTE3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_RESP_0_BYTE3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Write/Response data byte 2
+#define NAND_RESP_0_BYTE2_SHIFT                 _MK_SHIFT_CONST(16)
+#define NAND_RESP_0_BYTE2_FIELD                 (_MK_MASK_CONST(0xff) << NAND_RESP_0_BYTE2_SHIFT)
+#define NAND_RESP_0_BYTE2_RANGE                 23:16
+#define NAND_RESP_0_BYTE2_WOFFSET                       0x0
+#define NAND_RESP_0_BYTE2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_RESP_0_BYTE2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_RESP_0_BYTE2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_RESP_0_BYTE2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Write/Response data byte 1
+#define NAND_RESP_0_BYTE1_SHIFT                 _MK_SHIFT_CONST(8)
+#define NAND_RESP_0_BYTE1_FIELD                 (_MK_MASK_CONST(0xff) << NAND_RESP_0_BYTE1_SHIFT)
+#define NAND_RESP_0_BYTE1_RANGE                 15:8
+#define NAND_RESP_0_BYTE1_WOFFSET                       0x0
+#define NAND_RESP_0_BYTE1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_RESP_0_BYTE1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_RESP_0_BYTE1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_RESP_0_BYTE1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Write/Response data byte 0 (LSB)
+#define NAND_RESP_0_BYTE0_SHIFT                 _MK_SHIFT_CONST(0)
+#define NAND_RESP_0_BYTE0_FIELD                 (_MK_MASK_CONST(0xff) << NAND_RESP_0_BYTE0_SHIFT)
+#define NAND_RESP_0_BYTE0_RANGE                 7:0
+#define NAND_RESP_0_BYTE0_WOFFSET                       0x0
+#define NAND_RESP_0_BYTE0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_RESP_0_BYTE0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_RESP_0_BYTE0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_RESP_0_BYTE0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register NAND_TIMING2_0  
+#define NAND_TIMING2_0                  _MK_ADDR_CONST(0x1c)
+#define NAND_TIMING2_0_SECURE                   0x0
+#define NAND_TIMING2_0_WORD_COUNT                       0x1
+#define NAND_TIMING2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define NAND_TIMING2_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_TIMING2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define NAND_TIMING2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_TIMING2_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define NAND_TIMING2_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_TIMING2_0_NA1_SHIFT                        _MK_SHIFT_CONST(4)
+#define NAND_TIMING2_0_NA1_FIELD                        (_MK_MASK_CONST(0xfffffff) << NAND_TIMING2_0_NA1_SHIFT)
+#define NAND_TIMING2_0_NA1_RANGE                        31:4
+#define NAND_TIMING2_0_NA1_WOFFSET                      0x0
+#define NAND_TIMING2_0_NA1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_TIMING2_0_NA1_DEFAULT_MASK                 _MK_MASK_CONST(0xfffffff)
+#define NAND_TIMING2_0_NA1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_TIMING2_0_NA1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// WE posedge of address cycle to WE posedge of data cycle
+//
+// Generated timing = (n+3) * NAND_CLK_PERIOD ns.
+// -----------------------------------------------------------------------------
+// GUIDELINE: Refer to tADL timing from flash datasheet
+// -----------------------------------------------------------------------------
+//
+// Please note that timing generated from controller is for the duration from 
+// ALE low to WP low. In the convention of flash vendor tADL timing
+// this amounts to = (n+3)*NAND_CLK_PERIOD + tWH(previous address cycle)
+//                                         + tWP(following data cycle).
+// 
+#define NAND_TIMING2_0_TADL_CNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define NAND_TIMING2_0_TADL_CNT_FIELD                   (_MK_MASK_CONST(0xf) << NAND_TIMING2_0_TADL_CNT_SHIFT)
+#define NAND_TIMING2_0_TADL_CNT_RANGE                   3:0
+#define NAND_TIMING2_0_TADL_CNT_WOFFSET                 0x0
+#define NAND_TIMING2_0_TADL_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_TIMING2_0_TADL_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define NAND_TIMING2_0_TADL_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_TIMING2_0_TADL_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register NAND_CMD_REG1_0  // Commmand cycle generation use these during COMMAND1 time
+#define NAND_CMD_REG1_0                 _MK_ADDR_CONST(0x20)
+#define NAND_CMD_REG1_0_SECURE                  0x0
+#define NAND_CMD_REG1_0_WORD_COUNT                      0x1
+#define NAND_CMD_REG1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_CMD_REG1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_CMD_REG1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Command byte 3(MSB)
+#define NAND_CMD_REG1_0_CMD_BYTE3_SHIFT                 _MK_SHIFT_CONST(24)
+#define NAND_CMD_REG1_0_CMD_BYTE3_FIELD                 (_MK_MASK_CONST(0xff) << NAND_CMD_REG1_0_CMD_BYTE3_SHIFT)
+#define NAND_CMD_REG1_0_CMD_BYTE3_RANGE                 31:24
+#define NAND_CMD_REG1_0_CMD_BYTE3_WOFFSET                       0x0
+#define NAND_CMD_REG1_0_CMD_BYTE3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG1_0_CMD_BYTE3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_CMD_REG1_0_CMD_BYTE3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG1_0_CMD_BYTE3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Command byte 2
+#define NAND_CMD_REG1_0_CMD_BYTE2_SHIFT                 _MK_SHIFT_CONST(16)
+#define NAND_CMD_REG1_0_CMD_BYTE2_FIELD                 (_MK_MASK_CONST(0xff) << NAND_CMD_REG1_0_CMD_BYTE2_SHIFT)
+#define NAND_CMD_REG1_0_CMD_BYTE2_RANGE                 23:16
+#define NAND_CMD_REG1_0_CMD_BYTE2_WOFFSET                       0x0
+#define NAND_CMD_REG1_0_CMD_BYTE2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG1_0_CMD_BYTE2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_CMD_REG1_0_CMD_BYTE2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG1_0_CMD_BYTE2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Command byte 1
+#define NAND_CMD_REG1_0_CMD_BYTE1_SHIFT                 _MK_SHIFT_CONST(8)
+#define NAND_CMD_REG1_0_CMD_BYTE1_FIELD                 (_MK_MASK_CONST(0xff) << NAND_CMD_REG1_0_CMD_BYTE1_SHIFT)
+#define NAND_CMD_REG1_0_CMD_BYTE1_RANGE                 15:8
+#define NAND_CMD_REG1_0_CMD_BYTE1_WOFFSET                       0x0
+#define NAND_CMD_REG1_0_CMD_BYTE1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG1_0_CMD_BYTE1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_CMD_REG1_0_CMD_BYTE1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG1_0_CMD_BYTE1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Command byte 0(LSB)
+#define NAND_CMD_REG1_0_CMD_BYTE0_SHIFT                 _MK_SHIFT_CONST(0)
+#define NAND_CMD_REG1_0_CMD_BYTE0_FIELD                 (_MK_MASK_CONST(0xff) << NAND_CMD_REG1_0_CMD_BYTE0_SHIFT)
+#define NAND_CMD_REG1_0_CMD_BYTE0_RANGE                 7:0
+#define NAND_CMD_REG1_0_CMD_BYTE0_WOFFSET                       0x0
+#define NAND_CMD_REG1_0_CMD_BYTE0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG1_0_CMD_BYTE0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_CMD_REG1_0_CMD_BYTE0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG1_0_CMD_BYTE0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register NAND_CMD_REG2_0  // Commmand cycle generation use these during COMMAND2 time
+#define NAND_CMD_REG2_0                 _MK_ADDR_CONST(0x24)
+#define NAND_CMD_REG2_0_SECURE                  0x0
+#define NAND_CMD_REG2_0_WORD_COUNT                      0x1
+#define NAND_CMD_REG2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG2_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_CMD_REG2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_CMD_REG2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Command byte 3(MSB)
+#define NAND_CMD_REG2_0_CMD_BYTE3_SHIFT                 _MK_SHIFT_CONST(24)
+#define NAND_CMD_REG2_0_CMD_BYTE3_FIELD                 (_MK_MASK_CONST(0xff) << NAND_CMD_REG2_0_CMD_BYTE3_SHIFT)
+#define NAND_CMD_REG2_0_CMD_BYTE3_RANGE                 31:24
+#define NAND_CMD_REG2_0_CMD_BYTE3_WOFFSET                       0x0
+#define NAND_CMD_REG2_0_CMD_BYTE3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG2_0_CMD_BYTE3_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_CMD_REG2_0_CMD_BYTE3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG2_0_CMD_BYTE3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Command byte 2
+#define NAND_CMD_REG2_0_CMD_BYTE2_SHIFT                 _MK_SHIFT_CONST(16)
+#define NAND_CMD_REG2_0_CMD_BYTE2_FIELD                 (_MK_MASK_CONST(0xff) << NAND_CMD_REG2_0_CMD_BYTE2_SHIFT)
+#define NAND_CMD_REG2_0_CMD_BYTE2_RANGE                 23:16
+#define NAND_CMD_REG2_0_CMD_BYTE2_WOFFSET                       0x0
+#define NAND_CMD_REG2_0_CMD_BYTE2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG2_0_CMD_BYTE2_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_CMD_REG2_0_CMD_BYTE2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG2_0_CMD_BYTE2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Command byte 1
+#define NAND_CMD_REG2_0_CMD_BYTE1_SHIFT                 _MK_SHIFT_CONST(8)
+#define NAND_CMD_REG2_0_CMD_BYTE1_FIELD                 (_MK_MASK_CONST(0xff) << NAND_CMD_REG2_0_CMD_BYTE1_SHIFT)
+#define NAND_CMD_REG2_0_CMD_BYTE1_RANGE                 15:8
+#define NAND_CMD_REG2_0_CMD_BYTE1_WOFFSET                       0x0
+#define NAND_CMD_REG2_0_CMD_BYTE1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG2_0_CMD_BYTE1_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_CMD_REG2_0_CMD_BYTE1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG2_0_CMD_BYTE1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Command byte 0(LSB)
+#define NAND_CMD_REG2_0_CMD_BYTE0_SHIFT                 _MK_SHIFT_CONST(0)
+#define NAND_CMD_REG2_0_CMD_BYTE0_FIELD                 (_MK_MASK_CONST(0xff) << NAND_CMD_REG2_0_CMD_BYTE0_SHIFT)
+#define NAND_CMD_REG2_0_CMD_BYTE0_RANGE                 7:0
+#define NAND_CMD_REG2_0_CMD_BYTE0_WOFFSET                       0x0
+#define NAND_CMD_REG2_0_CMD_BYTE0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG2_0_CMD_BYTE0_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_CMD_REG2_0_CMD_BYTE0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_CMD_REG2_0_CMD_BYTE0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register NAND_ADDR_REG1_0  // Adderss cycle generation use these bytes 
+#define NAND_ADDR_REG1_0                        _MK_ADDR_CONST(0x28)
+#define NAND_ADDR_REG1_0_SECURE                         0x0
+#define NAND_ADDR_REG1_0_WORD_COUNT                     0x1
+#define NAND_ADDR_REG1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG1_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define NAND_ADDR_REG1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG1_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_ADDR_REG1_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Address byte 3
+#define NAND_ADDR_REG1_0_ADDR_BYTE3_SHIFT                       _MK_SHIFT_CONST(24)
+#define NAND_ADDR_REG1_0_ADDR_BYTE3_FIELD                       (_MK_MASK_CONST(0xff) << NAND_ADDR_REG1_0_ADDR_BYTE3_SHIFT)
+#define NAND_ADDR_REG1_0_ADDR_BYTE3_RANGE                       31:24
+#define NAND_ADDR_REG1_0_ADDR_BYTE3_WOFFSET                     0x0
+#define NAND_ADDR_REG1_0_ADDR_BYTE3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG1_0_ADDR_BYTE3_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define NAND_ADDR_REG1_0_ADDR_BYTE3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG1_0_ADDR_BYTE3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Address byte 2
+#define NAND_ADDR_REG1_0_ADDR_BYTE2_SHIFT                       _MK_SHIFT_CONST(16)
+#define NAND_ADDR_REG1_0_ADDR_BYTE2_FIELD                       (_MK_MASK_CONST(0xff) << NAND_ADDR_REG1_0_ADDR_BYTE2_SHIFT)
+#define NAND_ADDR_REG1_0_ADDR_BYTE2_RANGE                       23:16
+#define NAND_ADDR_REG1_0_ADDR_BYTE2_WOFFSET                     0x0
+#define NAND_ADDR_REG1_0_ADDR_BYTE2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG1_0_ADDR_BYTE2_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define NAND_ADDR_REG1_0_ADDR_BYTE2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG1_0_ADDR_BYTE2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Address byte 1
+#define NAND_ADDR_REG1_0_ADDR_BYTE1_SHIFT                       _MK_SHIFT_CONST(8)
+#define NAND_ADDR_REG1_0_ADDR_BYTE1_FIELD                       (_MK_MASK_CONST(0xff) << NAND_ADDR_REG1_0_ADDR_BYTE1_SHIFT)
+#define NAND_ADDR_REG1_0_ADDR_BYTE1_RANGE                       15:8
+#define NAND_ADDR_REG1_0_ADDR_BYTE1_WOFFSET                     0x0
+#define NAND_ADDR_REG1_0_ADDR_BYTE1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG1_0_ADDR_BYTE1_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define NAND_ADDR_REG1_0_ADDR_BYTE1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG1_0_ADDR_BYTE1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Address byte 0 (LSB)
+#define NAND_ADDR_REG1_0_ADDR_BYTE0_SHIFT                       _MK_SHIFT_CONST(0)
+#define NAND_ADDR_REG1_0_ADDR_BYTE0_FIELD                       (_MK_MASK_CONST(0xff) << NAND_ADDR_REG1_0_ADDR_BYTE0_SHIFT)
+#define NAND_ADDR_REG1_0_ADDR_BYTE0_RANGE                       7:0
+#define NAND_ADDR_REG1_0_ADDR_BYTE0_WOFFSET                     0x0
+#define NAND_ADDR_REG1_0_ADDR_BYTE0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG1_0_ADDR_BYTE0_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define NAND_ADDR_REG1_0_ADDR_BYTE0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG1_0_ADDR_BYTE0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register NAND_ADDR_REG2_0  // Adderss cycle generation use these bytes
+#define NAND_ADDR_REG2_0                        _MK_ADDR_CONST(0x2c)
+#define NAND_ADDR_REG2_0_SECURE                         0x0
+#define NAND_ADDR_REG2_0_WORD_COUNT                     0x1
+#define NAND_ADDR_REG2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG2_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define NAND_ADDR_REG2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG2_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_ADDR_REG2_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Address byte 3
+#define NAND_ADDR_REG2_0_ADDR_BYTE7_SHIFT                       _MK_SHIFT_CONST(24)
+#define NAND_ADDR_REG2_0_ADDR_BYTE7_FIELD                       (_MK_MASK_CONST(0xff) << NAND_ADDR_REG2_0_ADDR_BYTE7_SHIFT)
+#define NAND_ADDR_REG2_0_ADDR_BYTE7_RANGE                       31:24
+#define NAND_ADDR_REG2_0_ADDR_BYTE7_WOFFSET                     0x0
+#define NAND_ADDR_REG2_0_ADDR_BYTE7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG2_0_ADDR_BYTE7_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define NAND_ADDR_REG2_0_ADDR_BYTE7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG2_0_ADDR_BYTE7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Address byte 2
+#define NAND_ADDR_REG2_0_ADDR_BYTE6_SHIFT                       _MK_SHIFT_CONST(16)
+#define NAND_ADDR_REG2_0_ADDR_BYTE6_FIELD                       (_MK_MASK_CONST(0xff) << NAND_ADDR_REG2_0_ADDR_BYTE6_SHIFT)
+#define NAND_ADDR_REG2_0_ADDR_BYTE6_RANGE                       23:16
+#define NAND_ADDR_REG2_0_ADDR_BYTE6_WOFFSET                     0x0
+#define NAND_ADDR_REG2_0_ADDR_BYTE6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG2_0_ADDR_BYTE6_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define NAND_ADDR_REG2_0_ADDR_BYTE6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG2_0_ADDR_BYTE6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Address byte 1
+#define NAND_ADDR_REG2_0_ADDR_BYTE5_SHIFT                       _MK_SHIFT_CONST(8)
+#define NAND_ADDR_REG2_0_ADDR_BYTE5_FIELD                       (_MK_MASK_CONST(0xff) << NAND_ADDR_REG2_0_ADDR_BYTE5_SHIFT)
+#define NAND_ADDR_REG2_0_ADDR_BYTE5_RANGE                       15:8
+#define NAND_ADDR_REG2_0_ADDR_BYTE5_WOFFSET                     0x0
+#define NAND_ADDR_REG2_0_ADDR_BYTE5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG2_0_ADDR_BYTE5_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define NAND_ADDR_REG2_0_ADDR_BYTE5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG2_0_ADDR_BYTE5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Address byte 0 (LSB)
+#define NAND_ADDR_REG2_0_ADDR_BYTE4_SHIFT                       _MK_SHIFT_CONST(0)
+#define NAND_ADDR_REG2_0_ADDR_BYTE4_FIELD                       (_MK_MASK_CONST(0xff) << NAND_ADDR_REG2_0_ADDR_BYTE4_SHIFT)
+#define NAND_ADDR_REG2_0_ADDR_BYTE4_RANGE                       7:0
+#define NAND_ADDR_REG2_0_ADDR_BYTE4_WOFFSET                     0x0
+#define NAND_ADDR_REG2_0_ADDR_BYTE4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG2_0_ADDR_BYTE4_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define NAND_ADDR_REG2_0_ADDR_BYTE4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_ADDR_REG2_0_ADDR_BYTE4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register NAND_DMA_MST_CTRL_0  
+#define NAND_DMA_MST_CTRL_0                     _MK_ADDR_CONST(0x30)
+#define NAND_DMA_MST_CTRL_0_SECURE                      0x0
+#define NAND_DMA_MST_CTRL_0_WORD_COUNT                  0x1
+#define NAND_DMA_MST_CTRL_0_RESET_VAL                   _MK_MASK_CONST(0x24000000)
+#define NAND_DMA_MST_CTRL_0_RESET_MASK                  _MK_MASK_CONST(0xff100006)
+#define NAND_DMA_MST_CTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_READ_MASK                   _MK_MASK_CONST(0xff100006)
+#define NAND_DMA_MST_CTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x7f100006)
+// Enable NAND DMA interface for data transfers. Auto clear type.
+// HW clears when programmed length of data transfer is completed.
+#define NAND_DMA_MST_CTRL_0_DMA_GO_SHIFT                        _MK_SHIFT_CONST(31)
+#define NAND_DMA_MST_CTRL_0_DMA_GO_FIELD                        (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_DMA_GO_SHIFT)
+#define NAND_DMA_MST_CTRL_0_DMA_GO_RANGE                        31:31
+#define NAND_DMA_MST_CTRL_0_DMA_GO_WOFFSET                      0x0
+#define NAND_DMA_MST_CTRL_0_DMA_GO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DMA_GO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_DMA_MST_CTRL_0_DMA_GO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DMA_GO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DMA_GO_DISABLE                      _MK_ENUM_CONST(0)
+#define NAND_DMA_MST_CTRL_0_DMA_GO_ENABLE                       _MK_ENUM_CONST(1)
+
+// DMA data transfer direction  Read from system and write to flash
+#define NAND_DMA_MST_CTRL_0_DIR_SHIFT                   _MK_SHIFT_CONST(30)
+#define NAND_DMA_MST_CTRL_0_DIR_FIELD                   (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_DIR_SHIFT)
+#define NAND_DMA_MST_CTRL_0_DIR_RANGE                   30:30
+#define NAND_DMA_MST_CTRL_0_DIR_WOFFSET                 0x0
+#define NAND_DMA_MST_CTRL_0_DIR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DIR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define NAND_DMA_MST_CTRL_0_DIR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DIR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DIR_DMA_RD                  _MK_ENUM_CONST(0)    // // Write to  system and read from flash
+
+#define NAND_DMA_MST_CTRL_0_DIR_DMA_WR                  _MK_ENUM_CONST(1)
+
+// DMA peformace feature enable. as soon as the Error vectors equal to BURST  SIZE programmed 
+// received DMA suspends current data transfers and moves to 
+// Error vector transfer and waits till that page decode is completed.
+// Potentially if Error vectors are received around each 512 sub-page
+// boundary  this could cause stall of next page READ data transfers 
+// causing performance  degradation. To take advantage of 
+// PIPELINE_EN ECC decoder pipeline  capability this should be enabled.
+#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_SHIFT                   _MK_SHIFT_CONST(29)
+#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_FIELD                   (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_DMA_PERF_EN_SHIFT)
+#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_RANGE                   29:29
+#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_WOFFSET                 0x0
+#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_DISABLE                 _MK_ENUM_CONST(0)    // //
+
+#define NAND_DMA_MST_CTRL_0_DMA_PERF_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable interrupt on DMA transfer completion 
+#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_SHIFT                   _MK_SHIFT_CONST(28)
+#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_FIELD                   (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_IE_DMA_DONE_SHIFT)
+#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_RANGE                   28:28
+#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_WOFFSET                 0x0
+#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_DISABLE                 _MK_ENUM_CONST(0)
+#define NAND_DMA_MST_CTRL_0_IE_DMA_DONE_ENABLE                  _MK_ENUM_CONST(1)
+
+// increments the Error Vector  destination address continuously 
+// till the total DMA transfer size is done
+#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_SHIFT                  _MK_SHIFT_CONST(27)
+#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_FIELD                  (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_REUSE_BUFFER_SHIFT)
+#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_RANGE                  27:27
+#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_WOFFSET                        0x0
+#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_DISABLE                        _MK_ENUM_CONST(0)
+#define NAND_DMA_MST_CTRL_0_REUSE_BUFFER_ENABLE                 _MK_ENUM_CONST(1)
+
+// DMA burst size
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_SHIFT                    _MK_SHIFT_CONST(24)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_FIELD                    (_MK_MASK_CONST(0x7) << NAND_DMA_MST_CTRL_0_BURST_SIZE_SHIFT)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_RANGE                    26:24
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_WOFFSET                  0x0
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_DEFAULT                  _MK_MASK_CONST(0x4)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_RSVD1                      _MK_ENUM_CONST(0)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_RSVD2                      _MK_ENUM_CONST(1)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_1WORDS                     _MK_ENUM_CONST(2)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_4WORDS                     _MK_ENUM_CONST(3)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_8WORDS                     _MK_ENUM_CONST(4)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_16WORDS                    _MK_ENUM_CONST(5)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_RSVD3                      _MK_ENUM_CONST(6)
+#define NAND_DMA_MST_CTRL_0_BURST_SIZE_BURST_RSVD4                      _MK_ENUM_CONST(7)
+
+// 1 = DMA transfer completed interrupt. 
+// This is set ONLY when  not running in COMMAND QUEUE MODE
+#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_SHIFT                   _MK_SHIFT_CONST(20)
+#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_FIELD                   (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_IS_DMA_DONE_SHIFT)
+#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_RANGE                   20:20
+#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_WOFFSET                 0x0
+#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_IS_DMA_DONE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Enable DMA transfer for Data (A) 
+#define NAND_DMA_MST_CTRL_0_DMA_EN_A_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_A_FIELD                      (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_DMA_EN_A_SHIFT)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_A_RANGE                      2:2
+#define NAND_DMA_MST_CTRL_0_DMA_EN_A_WOFFSET                    0x0
+#define NAND_DMA_MST_CTRL_0_DMA_EN_A_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_A_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_A_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_A_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_A_DISABLE                    _MK_ENUM_CONST(0)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_A_ENABLE                     _MK_ENUM_CONST(1)
+
+// Enable DMA transfer for TAG/Spare (B)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_B_SHIFT                      _MK_SHIFT_CONST(1)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_B_FIELD                      (_MK_MASK_CONST(0x1) << NAND_DMA_MST_CTRL_0_DMA_EN_B_SHIFT)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_B_RANGE                      1:1
+#define NAND_DMA_MST_CTRL_0_DMA_EN_B_WOFFSET                    0x0
+#define NAND_DMA_MST_CTRL_0_DMA_EN_B_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_B_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_B_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_B_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_B_DISABLE                    _MK_ENUM_CONST(0)
+#define NAND_DMA_MST_CTRL_0_DMA_EN_B_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register NAND_DMA_CFG_A_0  
+#define NAND_DMA_CFG_A_0                        _MK_ADDR_CONST(0x34)
+#define NAND_DMA_CFG_A_0_SECURE                         0x0
+#define NAND_DMA_CFG_A_0_WORD_COUNT                     0x1
+#define NAND_DMA_CFG_A_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_DMA_CFG_A_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define NAND_DMA_CFG_A_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_DMA_CFG_A_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_DMA_CFG_A_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define NAND_DMA_CFG_A_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+// DMA Data Block size in Bytes(N-1) value
+#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_SHIFT                 _MK_SHIFT_CONST(0)
+#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_FIELD                 (_MK_MASK_CONST(0xffff) << NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_SHIFT)
+#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_RANGE                 15:0
+#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_WOFFSET                       0x0
+#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_DMA_CFG_A_0_DMA_BLOCK_SIZE_A_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register NAND_DMA_CFG_B_0  
+#define NAND_DMA_CFG_B_0                        _MK_ADDR_CONST(0x38)
+#define NAND_DMA_CFG_B_0_SECURE                         0x0
+#define NAND_DMA_CFG_B_0_WORD_COUNT                     0x1
+#define NAND_DMA_CFG_B_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_DMA_CFG_B_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define NAND_DMA_CFG_B_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_DMA_CFG_B_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_DMA_CFG_B_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define NAND_DMA_CFG_B_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+// DMA TAG Block size in Bytes(N-1) value
+#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_SHIFT                 _MK_SHIFT_CONST(0)
+#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_FIELD                 (_MK_MASK_CONST(0xffff) << NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_SHIFT)
+#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_RANGE                 15:0
+#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_WOFFSET                       0x0
+#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_DMA_CFG_B_0_DMA_BLOCK_SIZE_B_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register NAND_FIFO_CTRL_0  
+#define NAND_FIFO_CTRL_0                        _MK_ADDR_CONST(0x3c)
+#define NAND_FIFO_CTRL_0_SECURE                         0x0
+#define NAND_FIFO_CTRL_0_WORD_COUNT                     0x1
+#define NAND_FIFO_CTRL_0_RESET_VAL                      _MK_MASK_CONST(0xaa00)
+#define NAND_FIFO_CTRL_0_RESET_MASK                     _MK_MASK_CONST(0xff0f)
+#define NAND_FIFO_CTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_READ_MASK                      _MK_MASK_CONST(0xff0f)
+#define NAND_FIFO_CTRL_0_WRITE_MASK                     _MK_MASK_CONST(0xf)
+// 1 = Indicates Command queue FIFO Empty
+#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_SHIFT                     _MK_SHIFT_CONST(15)
+#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_FIELD                     (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_LL_BUF_EMPTY_SHIFT)
+#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_RANGE                     15:15
+#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_WOFFSET                   0x0
+#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_DEFAULT                   _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_LL_BUF_EMPTY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 = Indicates Command queue FIFO Full
+#define NAND_FIFO_CTRL_0_LL_BUF_FULL_SHIFT                      _MK_SHIFT_CONST(14)
+#define NAND_FIFO_CTRL_0_LL_BUF_FULL_FIELD                      (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_LL_BUF_FULL_SHIFT)
+#define NAND_FIFO_CTRL_0_LL_BUF_FULL_RANGE                      14:14
+#define NAND_FIFO_CTRL_0_LL_BUF_FULL_WOFFSET                    0x0
+#define NAND_FIFO_CTRL_0_LL_BUF_FULL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_LL_BUF_FULL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_LL_BUF_FULL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_LL_BUF_FULL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = Indicates Data FIFO Empty
+#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_SHIFT                     _MK_SHIFT_CONST(13)
+#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_FIELD                     (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_A_EMPTY_SHIFT)
+#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_RANGE                     13:13
+#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_WOFFSET                   0x0
+#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_DEFAULT                   _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_A_EMPTY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 = Indicates Data FIFO Full
+#define NAND_FIFO_CTRL_0_FIFO_A_FULL_SHIFT                      _MK_SHIFT_CONST(12)
+#define NAND_FIFO_CTRL_0_FIFO_A_FULL_FIELD                      (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_A_FULL_SHIFT)
+#define NAND_FIFO_CTRL_0_FIFO_A_FULL_RANGE                      12:12
+#define NAND_FIFO_CTRL_0_FIFO_A_FULL_WOFFSET                    0x0
+#define NAND_FIFO_CTRL_0_FIFO_A_FULL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_A_FULL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_A_FULL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_A_FULL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = Indicates TAG FIFO Empty
+#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_SHIFT                     _MK_SHIFT_CONST(11)
+#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_FIELD                     (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_B_EMPTY_SHIFT)
+#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_RANGE                     11:11
+#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_WOFFSET                   0x0
+#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_DEFAULT                   _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_B_EMPTY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 = Indicates TAG FIFO Full
+#define NAND_FIFO_CTRL_0_FIFO_B_FULL_SHIFT                      _MK_SHIFT_CONST(10)
+#define NAND_FIFO_CTRL_0_FIFO_B_FULL_FIELD                      (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_B_FULL_SHIFT)
+#define NAND_FIFO_CTRL_0_FIFO_B_FULL_RANGE                      10:10
+#define NAND_FIFO_CTRL_0_FIFO_B_FULL_WOFFSET                    0x0
+#define NAND_FIFO_CTRL_0_FIFO_B_FULL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_B_FULL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_B_FULL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_B_FULL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 1 = Indicates ECC FIFO Empty
+#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_SHIFT                     _MK_SHIFT_CONST(9)
+#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_FIELD                     (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_C_EMPTY_SHIFT)
+#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_RANGE                     9:9
+#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_WOFFSET                   0x0
+#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_DEFAULT                   _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_C_EMPTY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 1 = Indicates ECC FIFO Full
+#define NAND_FIFO_CTRL_0_FIFO_C_FULL_SHIFT                      _MK_SHIFT_CONST(8)
+#define NAND_FIFO_CTRL_0_FIFO_C_FULL_FIELD                      (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_C_FULL_SHIFT)
+#define NAND_FIFO_CTRL_0_FIFO_C_FULL_RANGE                      8:8
+#define NAND_FIFO_CTRL_0_FIFO_C_FULL_WOFFSET                    0x0
+#define NAND_FIFO_CTRL_0_FIFO_C_FULL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_C_FULL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_C_FULL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_C_FULL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// field set to "CLEAR_ALL_FIFO" flushs all the buffers(i.e.,LL_BUF,FIFO_A,FIFO_B,FIFO_C) 
+#define NAND_FIFO_CTRL_0_LL_BUF_CLR_SHIFT                       _MK_SHIFT_CONST(3)
+#define NAND_FIFO_CTRL_0_LL_BUF_CLR_FIELD                       (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_LL_BUF_CLR_SHIFT)
+#define NAND_FIFO_CTRL_0_LL_BUF_CLR_RANGE                       3:3
+#define NAND_FIFO_CTRL_0_LL_BUF_CLR_WOFFSET                     0x0
+#define NAND_FIFO_CTRL_0_LL_BUF_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_LL_BUF_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_LL_BUF_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_LL_BUF_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_LL_BUF_CLR_CLEAR_NO_FIFO                       _MK_ENUM_CONST(0)
+#define NAND_FIFO_CTRL_0_LL_BUF_CLR_CLEAR_ALL_FIFO                      _MK_ENUM_CONST(1)
+
+// Flush the DATA FIFO contents
+#define NAND_FIFO_CTRL_0_FIFO_A_CLR_SHIFT                       _MK_SHIFT_CONST(2)
+#define NAND_FIFO_CTRL_0_FIFO_A_CLR_FIELD                       (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_A_CLR_SHIFT)
+#define NAND_FIFO_CTRL_0_FIFO_A_CLR_RANGE                       2:2
+#define NAND_FIFO_CTRL_0_FIFO_A_CLR_WOFFSET                     0x0
+#define NAND_FIFO_CTRL_0_FIFO_A_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_A_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_A_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_A_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Flush the TAG FIFO contents
+#define NAND_FIFO_CTRL_0_FIFO_B_CLR_SHIFT                       _MK_SHIFT_CONST(1)
+#define NAND_FIFO_CTRL_0_FIFO_B_CLR_FIELD                       (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_B_CLR_SHIFT)
+#define NAND_FIFO_CTRL_0_FIFO_B_CLR_RANGE                       1:1
+#define NAND_FIFO_CTRL_0_FIFO_B_CLR_WOFFSET                     0x0
+#define NAND_FIFO_CTRL_0_FIFO_B_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_B_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_B_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_B_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Flush the ECC FIFO contents
+#define NAND_FIFO_CTRL_0_FIFO_C_CLR_SHIFT                       _MK_SHIFT_CONST(0)
+#define NAND_FIFO_CTRL_0_FIFO_C_CLR_FIELD                       (_MK_MASK_CONST(0x1) << NAND_FIFO_CTRL_0_FIFO_C_CLR_SHIFT)
+#define NAND_FIFO_CTRL_0_FIFO_C_CLR_RANGE                       0:0
+#define NAND_FIFO_CTRL_0_FIFO_C_CLR_WOFFSET                     0x0
+#define NAND_FIFO_CTRL_0_FIFO_C_CLR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_C_CLR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_FIFO_CTRL_0_FIFO_C_CLR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_FIFO_CTRL_0_FIFO_C_CLR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register NAND_DATA_BLOCK_PTR_0  
+#define NAND_DATA_BLOCK_PTR_0                   _MK_ADDR_CONST(0x40)
+#define NAND_DATA_BLOCK_PTR_0_SECURE                    0x0
+#define NAND_DATA_BLOCK_PTR_0_WORD_COUNT                        0x1
+#define NAND_DATA_BLOCK_PTR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_DATA_BLOCK_PTR_0_RESET_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define NAND_DATA_BLOCK_PTR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_DATA_BLOCK_PTR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_DATA_BLOCK_PTR_0_READ_MASK                         _MK_MASK_CONST(0xfffffffc)
+#define NAND_DATA_BLOCK_PTR_0_WRITE_MASK                        _MK_MASK_CONST(0xfffffffc)
+// DMA data block source/destination address pointer
+#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_SHIFT                  _MK_SHIFT_CONST(2)
+#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_FIELD                  (_MK_MASK_CONST(0x3fffffff) << NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_SHIFT)
+#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_RANGE                  31:2
+#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_WOFFSET                        0x0
+#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_DEFAULT_MASK                   _MK_MASK_CONST(0x3fffffff)
+#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_DATA_BLOCK_PTR_0_DMA_DATA_BLOCK_PTR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register NAND_TAG_PTR_0  
+#define NAND_TAG_PTR_0                  _MK_ADDR_CONST(0x44)
+#define NAND_TAG_PTR_0_SECURE                   0x0
+#define NAND_TAG_PTR_0_WORD_COUNT                       0x1
+#define NAND_TAG_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define NAND_TAG_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define NAND_TAG_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define NAND_TAG_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_TAG_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define NAND_TAG_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// DMA TAG block source/destination address pointer
+#define NAND_TAG_PTR_0_DMA_TAG_PTR_SHIFT                        _MK_SHIFT_CONST(2)
+#define NAND_TAG_PTR_0_DMA_TAG_PTR_FIELD                        (_MK_MASK_CONST(0x3fffffff) << NAND_TAG_PTR_0_DMA_TAG_PTR_SHIFT)
+#define NAND_TAG_PTR_0_DMA_TAG_PTR_RANGE                        31:2
+#define NAND_TAG_PTR_0_DMA_TAG_PTR_WOFFSET                      0x0
+#define NAND_TAG_PTR_0_DMA_TAG_PTR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_TAG_PTR_0_DMA_TAG_PTR_DEFAULT_MASK                 _MK_MASK_CONST(0x3fffffff)
+#define NAND_TAG_PTR_0_DMA_TAG_PTR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_TAG_PTR_0_DMA_TAG_PTR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register NAND_ECC_PTR_0  
+#define NAND_ECC_PTR_0                  _MK_ADDR_CONST(0x48)
+#define NAND_ECC_PTR_0_SECURE                   0x0
+#define NAND_ECC_PTR_0_WORD_COUNT                       0x1
+#define NAND_ECC_PTR_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define NAND_ECC_PTR_0_RESET_MASK                       _MK_MASK_CONST(0xfffffffc)
+#define NAND_ECC_PTR_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define NAND_ECC_PTR_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define NAND_ECC_PTR_0_READ_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define NAND_ECC_PTR_0_WRITE_MASK                       _MK_MASK_CONST(0xfffffffc)
+// DMA Error vector destination address pointer
+#define NAND_ECC_PTR_0_DMA_ECC_PTR_SHIFT                        _MK_SHIFT_CONST(2)
+#define NAND_ECC_PTR_0_DMA_ECC_PTR_FIELD                        (_MK_MASK_CONST(0x3fffffff) << NAND_ECC_PTR_0_DMA_ECC_PTR_SHIFT)
+#define NAND_ECC_PTR_0_DMA_ECC_PTR_RANGE                        31:2
+#define NAND_ECC_PTR_0_DMA_ECC_PTR_WOFFSET                      0x0
+#define NAND_ECC_PTR_0_DMA_ECC_PTR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_ECC_PTR_0_DMA_ECC_PTR_DEFAULT_MASK                 _MK_MASK_CONST(0x3fffffff)
+#define NAND_ECC_PTR_0_DMA_ECC_PTR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_ECC_PTR_0_DMA_ECC_PTR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register NAND_DEC_STATUS_0  
+#define NAND_DEC_STATUS_0                       _MK_ADDR_CONST(0x4c)
+#define NAND_DEC_STATUS_0_SECURE                        0x0
+#define NAND_DEC_STATUS_0_WORD_COUNT                    0x1
+#define NAND_DEC_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0xffffff03)
+#define NAND_DEC_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xffffff03)
+#define NAND_DEC_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Indicates the reference to the PAGE for Error  Correction 
+// to be applied. Valid when IS_ECC_ERROR is generated
+#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_SHIFT                 _MK_SHIFT_CONST(24)
+#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_FIELD                 (_MK_MASK_CONST(0xff) << NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_SHIFT)
+#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_RANGE                 31:24
+#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_WOFFSET                       0x0
+#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_ERR_PAGE_NUMBER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// No. of Errors occurred in main block READ data  plus TAG read 
+// data when corresponding features are enabled.
+#define NAND_DEC_STATUS_0_ERR_COUNT_SHIFT                       _MK_SHIFT_CONST(16)
+#define NAND_DEC_STATUS_0_ERR_COUNT_FIELD                       (_MK_MASK_CONST(0xff) << NAND_DEC_STATUS_0_ERR_COUNT_SHIFT)
+#define NAND_DEC_STATUS_0_ERR_COUNT_RANGE                       23:16
+#define NAND_DEC_STATUS_0_ERR_COUNT_WOFFSET                     0x0
+#define NAND_DEC_STATUS_0_ERR_COUNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_ERR_COUNT_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define NAND_DEC_STATUS_0_ERR_COUNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_ERR_COUNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Indicates sub-page decode failure within a page size. 
+// When decode failure is observed SW can use to figure
+// out which sub-page (512 byte) decode failure. 
+// for ex: of 2K page size selection,
+// bit 0 - first sub-page
+// bit 1 - second sub-page
+// bit 2 - third sub-page
+// bit 3 - fourth sub-page
+// and so on as applicable
+#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_SHIFT                   _MK_SHIFT_CONST(8)
+#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_FIELD                   (_MK_MASK_CONST(0xff) << NAND_DEC_STATUS_0_SUB_PAGE_FAIL_SHIFT)
+#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_RANGE                   15:8
+#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_WOFFSET                 0x0
+#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_SUB_PAGE_FAIL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 0 = Main block data decode without decode fail
+#define NAND_DEC_STATUS_0_A_ECC_FAIL_SHIFT                      _MK_SHIFT_CONST(1)
+#define NAND_DEC_STATUS_0_A_ECC_FAIL_FIELD                      (_MK_MASK_CONST(0x1) << NAND_DEC_STATUS_0_A_ECC_FAIL_SHIFT)
+#define NAND_DEC_STATUS_0_A_ECC_FAIL_RANGE                      1:1
+#define NAND_DEC_STATUS_0_A_ECC_FAIL_WOFFSET                    0x0
+#define NAND_DEC_STATUS_0_A_ECC_FAIL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_A_ECC_FAIL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_DEC_STATUS_0_A_ECC_FAIL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_A_ECC_FAIL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 0 = Tag block data decode without decode fail
+#define NAND_DEC_STATUS_0_B_ECC_FAIL_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_DEC_STATUS_0_B_ECC_FAIL_FIELD                      (_MK_MASK_CONST(0x1) << NAND_DEC_STATUS_0_B_ECC_FAIL_SHIFT)
+#define NAND_DEC_STATUS_0_B_ECC_FAIL_RANGE                      0:0
+#define NAND_DEC_STATUS_0_B_ECC_FAIL_WOFFSET                    0x0
+#define NAND_DEC_STATUS_0_B_ECC_FAIL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_B_ECC_FAIL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_DEC_STATUS_0_B_ECC_FAIL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_DEC_STATUS_0_B_ECC_FAIL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_HWSTATUS_CMD_0  
+#define NAND_HWSTATUS_CMD_0                     _MK_ADDR_CONST(0x50)
+#define NAND_HWSTATUS_CMD_0_SECURE                      0x0
+#define NAND_HWSTATUS_CMD_0_WORD_COUNT                  0x1
+#define NAND_HWSTATUS_CMD_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define NAND_HWSTATUS_CMD_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_HWSTATUS_CMD_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_HWSTATUS_CMD_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_HWSTATUS_CMD_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define NAND_HWSTATUS_CMD_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+// Command byte value used for READ STATUS commands  when 
+// automatic HW RBSY_CHK or RD_STATUS_CHK are enabled.
+#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_SHIFT                  _MK_SHIFT_CONST(0)
+#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_FIELD                  (_MK_MASK_CONST(0xff) << NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_SHIFT)
+#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_RANGE                  7:0
+#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_WOFFSET                        0x0
+#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_HWSTATUS_CMD_0_HWSTATUS_CMD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register NAND_HWSTATUS_MASK_0  
+#define NAND_HWSTATUS_MASK_0                    _MK_ADDR_CONST(0x54)
+#define NAND_HWSTATUS_MASK_0_SECURE                     0x0
+#define NAND_HWSTATUS_MASK_0_WORD_COUNT                         0x1
+#define NAND_HWSTATUS_MASK_0_RESET_VAL                  _MK_MASK_CONST(0xffe04040)
+#define NAND_HWSTATUS_MASK_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define NAND_HWSTATUS_MASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define NAND_HWSTATUS_MASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_HWSTATUS_MASK_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define NAND_HWSTATUS_MASK_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// 8 bit Mask value to extract the correct bit fields 
+// from READ STATUS information for RD_STATUS_CHK
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_SHIFT                        _MK_SHIFT_CONST(24)
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_FIELD                        (_MK_MASK_CONST(0xff) << NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_SHIFT)
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_RANGE                        31:24
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_WOFFSET                      0x0
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_DEFAULT                      _MK_MASK_CONST(0xff)
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 8 bit expected RD STATUS VALUE for RD_STATUS_CHK
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_SHIFT                     _MK_SHIFT_CONST(16)
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_FIELD                     (_MK_MASK_CONST(0xff) << NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_SHIFT)
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_RANGE                     23:16
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_WOFFSET                   0x0
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_DEFAULT                   _MK_MASK_CONST(0xe0)
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_HWSTATUS_MASK_0_RDSTATUS_EXP_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// 8 bit Mask value to extract the correct bit fields 
+// from READ STATUS information for RBSY_CHK
+#define NAND_HWSTATUS_MASK_0_RBSY_MASK_SHIFT                    _MK_SHIFT_CONST(8)
+#define NAND_HWSTATUS_MASK_0_RBSY_MASK_FIELD                    (_MK_MASK_CONST(0xff) << NAND_HWSTATUS_MASK_0_RBSY_MASK_SHIFT)
+#define NAND_HWSTATUS_MASK_0_RBSY_MASK_RANGE                    15:8
+#define NAND_HWSTATUS_MASK_0_RBSY_MASK_WOFFSET                  0x0
+#define NAND_HWSTATUS_MASK_0_RBSY_MASK_DEFAULT                  _MK_MASK_CONST(0x40)
+#define NAND_HWSTATUS_MASK_0_RBSY_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define NAND_HWSTATUS_MASK_0_RBSY_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_HWSTATUS_MASK_0_RBSY_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 8 bit expected RD STATUS VALUE for RBSY_CHK
+#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_SHIFT                 _MK_SHIFT_CONST(0)
+#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_FIELD                 (_MK_MASK_CONST(0xff) << NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_SHIFT)
+#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_RANGE                 7:0
+#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_WOFFSET                       0x0
+#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_DEFAULT                       _MK_MASK_CONST(0x40)
+#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_HWSTATUS_MASK_0_RBSY_EXP_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LL_CONFIG_0  
+#define NAND_LL_CONFIG_0                        _MK_ADDR_CONST(0x58)
+#define NAND_LL_CONFIG_0_SECURE                         0x0
+#define NAND_LL_CONFIG_0_WORD_COUNT                     0x1
+#define NAND_LL_CONFIG_0_RESET_VAL                      _MK_MASK_CONST(0xc0000)
+#define NAND_LL_CONFIG_0_RESET_MASK                     _MK_MASK_CONST(0x800f0fff)
+#define NAND_LL_CONFIG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LL_CONFIG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LL_CONFIG_0_READ_MASK                      _MK_MASK_CONST(0x800f0fff)
+#define NAND_LL_CONFIG_0_WRITE_MASK                     _MK_MASK_CONST(0xf0fff)
+// HW clears when command queue data and flash operations
+// are completed.
+#define NAND_LL_CONFIG_0_LL_START_SHIFT                 _MK_SHIFT_CONST(31)
+#define NAND_LL_CONFIG_0_LL_START_FIELD                 (_MK_MASK_CONST(0x1) << NAND_LL_CONFIG_0_LL_START_SHIFT)
+#define NAND_LL_CONFIG_0_LL_START_RANGE                 31:31
+#define NAND_LL_CONFIG_0_LL_START_WOFFSET                       0x0
+#define NAND_LL_CONFIG_0_LL_START_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_LL_CONFIG_0_LL_START_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_LL_CONFIG_0_LL_START_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LL_CONFIG_0_LL_START_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LL_CONFIG_0_LL_START_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_LL_CONFIG_0_LL_START_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable word count status update in  LL_STATUS register
+#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_SHIFT                       _MK_SHIFT_CONST(19)
+#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_FIELD                       (_MK_MASK_CONST(0x1) << NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_SHIFT)
+#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_RANGE                       19:19
+#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_WOFFSET                     0x0
+#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define NAND_LL_CONFIG_0_WORD_CNT_STATUS_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+//DMA burst size for  Command Queue data requests
+#define NAND_LL_CONFIG_0_BURST_SIZE_SHIFT                       _MK_SHIFT_CONST(16)
+#define NAND_LL_CONFIG_0_BURST_SIZE_FIELD                       (_MK_MASK_CONST(0x7) << NAND_LL_CONFIG_0_BURST_SIZE_SHIFT)
+#define NAND_LL_CONFIG_0_BURST_SIZE_RANGE                       18:16
+#define NAND_LL_CONFIG_0_BURST_SIZE_WOFFSET                     0x0
+#define NAND_LL_CONFIG_0_BURST_SIZE_DEFAULT                     _MK_MASK_CONST(0x4)
+#define NAND_LL_CONFIG_0_BURST_SIZE_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define NAND_LL_CONFIG_0_BURST_SIZE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_LL_CONFIG_0_BURST_SIZE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_RSVD1                 _MK_ENUM_CONST(0)
+#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_RSVD2                 _MK_ENUM_CONST(1)
+#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_1WORDS                        _MK_ENUM_CONST(2)
+#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_4WORDS                        _MK_ENUM_CONST(3)
+#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_8WORDS                        _MK_ENUM_CONST(4)
+#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_16WORDS                       _MK_ENUM_CONST(5)
+#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_RSVD3                 _MK_ENUM_CONST(6)
+#define NAND_LL_CONFIG_0_BURST_SIZE_BURST_RSVD4                 _MK_ENUM_CONST(7)
+
+// Command queue up word length programmed is parsed  and `START is 
+// done when the execution is complete. However for when errors  are 
+// detected for any case of the flash operation failure command queue  
+// execution is aborted immediately before this length. 
+#define NAND_LL_CONFIG_0_LL_LENGTH_SHIFT                        _MK_SHIFT_CONST(0)
+#define NAND_LL_CONFIG_0_LL_LENGTH_FIELD                        (_MK_MASK_CONST(0xfff) << NAND_LL_CONFIG_0_LL_LENGTH_SHIFT)
+#define NAND_LL_CONFIG_0_LL_LENGTH_RANGE                        11:0
+#define NAND_LL_CONFIG_0_LL_LENGTH_WOFFSET                      0x0
+#define NAND_LL_CONFIG_0_LL_LENGTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LL_CONFIG_0_LL_LENGTH_DEFAULT_MASK                 _MK_MASK_CONST(0xfff)
+#define NAND_LL_CONFIG_0_LL_LENGTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_LL_CONFIG_0_LL_LENGTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LL_PTR_0  
+#define NAND_LL_PTR_0                   _MK_ADDR_CONST(0x5c)
+#define NAND_LL_PTR_0_SECURE                    0x0
+#define NAND_LL_PTR_0_WORD_COUNT                        0x1
+#define NAND_LL_PTR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LL_PTR_0_RESET_MASK                        _MK_MASK_CONST(0xfffffffc)
+#define NAND_LL_PTR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_LL_PTR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_LL_PTR_0_READ_MASK                         _MK_MASK_CONST(0xfffffffc)
+#define NAND_LL_PTR_0_WRITE_MASK                        _MK_MASK_CONST(0xfffffffc)
+// Command queue data pointer Register
+#define NAND_LL_PTR_0_LL_PTR_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_LL_PTR_0_LL_PTR_FIELD                      (_MK_MASK_CONST(0x3fffffff) << NAND_LL_PTR_0_LL_PTR_SHIFT)
+#define NAND_LL_PTR_0_LL_PTR_RANGE                      31:2
+#define NAND_LL_PTR_0_LL_PTR_WOFFSET                    0x0
+#define NAND_LL_PTR_0_LL_PTR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LL_PTR_0_LL_PTR_DEFAULT_MASK                       _MK_MASK_CONST(0x3fffffff)
+#define NAND_LL_PTR_0_LL_PTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LL_PTR_0_LL_PTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LL_STATUS_0  
+#define NAND_LL_STATUS_0                        _MK_ADDR_CONST(0x60)
+#define NAND_LL_STATUS_0_SECURE                         0x0
+#define NAND_LL_STATUS_0_WORD_COUNT                     0x1
+#define NAND_LL_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0xffcf0fff)
+#define NAND_LL_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xffcf0fff)
+#define NAND_LL_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0xc00000)
+// Command queue PACKET ID completed at this time.  S/W has write 
+// access to this bit field position so that any time S/W can  clear
+// this field. Also NAND controller reset will reset this status.
+#define NAND_LL_STATUS_0_LL_PKT_ID_SHIFT                        _MK_SHIFT_CONST(24)
+#define NAND_LL_STATUS_0_LL_PKT_ID_FIELD                        (_MK_MASK_CONST(0xff) << NAND_LL_STATUS_0_LL_PKT_ID_SHIFT)
+#define NAND_LL_STATUS_0_LL_PKT_ID_RANGE                        31:24
+#define NAND_LL_STATUS_0_LL_PKT_ID_WOFFSET                      0x0
+#define NAND_LL_STATUS_0_LL_PKT_ID_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_LL_PKT_ID_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define NAND_LL_STATUS_0_LL_PKT_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_LL_PKT_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Interrupt status of LL_DONE { Read Only}
+#define NAND_LL_STATUS_0_IS_LL_DONE_SHIFT                       _MK_SHIFT_CONST(23)
+#define NAND_LL_STATUS_0_IS_LL_DONE_FIELD                       (_MK_MASK_CONST(0x1) << NAND_LL_STATUS_0_IS_LL_DONE_SHIFT)
+#define NAND_LL_STATUS_0_IS_LL_DONE_RANGE                       23:23
+#define NAND_LL_STATUS_0_IS_LL_DONE_WOFFSET                     0x0
+#define NAND_LL_STATUS_0_IS_LL_DONE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_IS_LL_DONE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define NAND_LL_STATUS_0_IS_LL_DONE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_IS_LL_DONE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Interrupt status of LL_ERR { Read Only}
+#define NAND_LL_STATUS_0_IS_LL_ERR_SHIFT                        _MK_SHIFT_CONST(22)
+#define NAND_LL_STATUS_0_IS_LL_ERR_FIELD                        (_MK_MASK_CONST(0x1) << NAND_LL_STATUS_0_IS_LL_ERR_SHIFT)
+#define NAND_LL_STATUS_0_IS_LL_ERR_RANGE                        22:22
+#define NAND_LL_STATUS_0_IS_LL_ERR_WOFFSET                      0x0
+#define NAND_LL_STATUS_0_IS_LL_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_IS_LL_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define NAND_LL_STATUS_0_IS_LL_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_IS_LL_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Command queue Word length of last packet executed  in the queue.
+// Please note that WORD_CNT_STATUS_EN in LL_CONFIG should be  enabled 
+// for this status update
+#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_SHIFT                       _MK_SHIFT_CONST(16)
+#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_FIELD                       (_MK_MASK_CONST(0xf) << NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_SHIFT)
+#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_RANGE                       19:16
+#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_WOFFSET                     0x0
+#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_LL_LENGTH_LAST_PKT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Command queue Word length(32-bit) completed till  this time.
+// Please note that WORD_CNT_STATUS_EN in LL_CONFIG should be  enabled 
+// for this status update
+#define NAND_LL_STATUS_0_LL_LENGTH_DONE_SHIFT                   _MK_SHIFT_CONST(0)
+#define NAND_LL_STATUS_0_LL_LENGTH_DONE_FIELD                   (_MK_MASK_CONST(0xfff) << NAND_LL_STATUS_0_LL_LENGTH_DONE_SHIFT)
+#define NAND_LL_STATUS_0_LL_LENGTH_DONE_RANGE                   11:0
+#define NAND_LL_STATUS_0_LL_LENGTH_DONE_WOFFSET                 0x0
+#define NAND_LL_STATUS_0_LL_LENGTH_DONE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_LL_LENGTH_DONE_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define NAND_LL_STATUS_0_LL_LENGTH_DONE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LL_STATUS_0_LL_LENGTH_DONE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_CONTROL_0  
+#define NAND_LOCK_CONTROL_0                     _MK_ADDR_CONST(0x64)
+#define NAND_LOCK_CONTROL_0_SECURE                      0x0
+#define NAND_LOCK_CONTROL_0_WORD_COUNT                  0x1
+#define NAND_LOCK_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1ff)
+#define NAND_LOCK_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x1ff)
+#define NAND_LOCK_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x1ff)
+// Intterrupt enable on memory range match.
+#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_SHIFT                   _MK_SHIFT_CONST(8)
+#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_FIELD                   (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_IE_LOCK_ERR_SHIFT)
+#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_RANGE                   8:8
+#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_WOFFSET                 0x0
+#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_DISABLE                 _MK_ENUM_CONST(0)
+#define NAND_LOCK_CONTROL_0_IE_LOCK_ERR_ENABLE                  _MK_ENUM_CONST(1)
+
+// Enable lock feature for selected apertures 7 Can be set only once register field, h/w reset OR controller reset ONLY 
+// can disable this feature.
+// LOCK_APER_START7, LOCK_APER_END7, LOCK_APER_CHIPID7 cant be
+// programmed once this SET
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_SHIFT                 _MK_SHIFT_CONST(7)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_FIELD                 (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN7_SHIFT)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_RANGE                 7:7
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_WOFFSET                       0x0
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN7_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable lock feature for selected apertures 6 Can be set only once register field, h/w reset OR controller reset ONLY 
+// can disable this feature.
+// LOCK_APER_START6, LOCK_APER_END6, LOCK_APER_CHIPID6 cant be
+// programmed once this SET
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_SHIFT                 _MK_SHIFT_CONST(6)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_FIELD                 (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN6_SHIFT)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_RANGE                 6:6
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_WOFFSET                       0x0
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN6_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable lock feature for selected apertures 5 Can be set only once register field, h/w reset OR controller reset ONLY 
+// can disable this feature.
+// LOCK_APER_START5, LOCK_APER_END5, LOCK_APER_CHIPID5 cant be
+// programmed once this SET
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_SHIFT                 _MK_SHIFT_CONST(5)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_FIELD                 (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN5_SHIFT)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_RANGE                 5:5
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_WOFFSET                       0x0
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN5_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable lock feature for selected apertures 4 Can be set only once register field, h/w reset OR controller reset ONLY 
+// can disable this feature.
+// LOCK_APER_START4, LOCK_APER_END4, LOCK_APER_CHIPID4 cant be
+// programmed once this SET
+//
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_SHIFT                 _MK_SHIFT_CONST(4)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_FIELD                 (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN4_SHIFT)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_RANGE                 4:4
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_WOFFSET                       0x0
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN4_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable lock feature for selected apertures 3 Can be set only once register field, h/w reset OR controller reset ONLY
+// can disable this feature.
+// LOCK_APER_START3, LOCK_APER_END3, LOCK_APER_CHIPID3 cant be
+// programmed once this SET
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_SHIFT                 _MK_SHIFT_CONST(3)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_FIELD                 (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN3_SHIFT)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_RANGE                 3:3
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_WOFFSET                       0x0
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN3_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable lock feature for selected apertures 2 Can be set only once register field, h/w reset OR controller reset ONLY 
+// can disable this feature.
+// LOCK_APER_START2, LOCK_APER_END2, LOCK_APER_CHIPID2 cant be
+// programmed once this SET
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_SHIFT                 _MK_SHIFT_CONST(2)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_FIELD                 (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN2_SHIFT)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_RANGE                 2:2
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_WOFFSET                       0x0
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN2_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable lock feature for selected apertures 1 Can be set only once register field, h/w reset OR controller reset ONLY
+// can disable this feature.
+// LOCK_APER_START1, LOCK_APER_END1, LOCK_APER_CHIPID1 cant be
+// programmed once this SET
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_SHIFT                 _MK_SHIFT_CONST(1)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_FIELD                 (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN1_SHIFT)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_RANGE                 1:1
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_WOFFSET                       0x0
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN1_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable lock feature for selected apertures 0 Can be set only once register field, h/w reset OR controller reset ONLY
+// can disable this feature.
+// LOCK_APER_START0, LOCK_APER_END0, LOCK_APER_CHIPID0 cant be
+// programmed once this SET
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_SHIFT                 _MK_SHIFT_CONST(0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_FIELD                 (_MK_MASK_CONST(0x1) << NAND_LOCK_CONTROL_0_LOCK_APER_EN0_SHIFT)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_RANGE                 0:0
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_WOFFSET                       0x0
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_DISABLE                       _MK_ENUM_CONST(0)
+#define NAND_LOCK_CONTROL_0_LOCK_APER_EN0_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register NAND_LOCK_STATUS_0  
+#define NAND_LOCK_STATUS_0                      _MK_ADDR_CONST(0x68)
+#define NAND_LOCK_STATUS_0_SECURE                       0x0
+#define NAND_LOCK_STATUS_0_WORD_COUNT                   0x1
+#define NAND_LOCK_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x1ff)
+#define NAND_LOCK_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define NAND_LOCK_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// 1 = Memory protection error detected
+// check LOCK_STATUS register to identify
+// which aperture matched.
+#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_SHIFT                    _MK_SHIFT_CONST(8)
+#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_FIELD                    (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_IS_LOCK_ERR_SHIFT)
+#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_RANGE                    8:8
+#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_WOFFSET                  0x0
+#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_IS_LOCK_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Respective bit is set by HW on protection range detection. 
+// Write 1 to clear IS.LOCK_ERR will clear this status information
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_SHIFT                      _MK_SHIFT_CONST(7)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_SHIFT)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_RANGE                      7:7
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_WOFFSET                    0x0
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Respective bit is set by HW on protection range detection. 
+// Write 1 to clear IS.LOCK_ERR will clear this status information
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_SHIFT                      _MK_SHIFT_CONST(6)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_SHIFT)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_RANGE                      6:6
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_WOFFSET                    0x0
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Respective bit is set by HW on protection range detection. 
+// Write 1 to clear IS.LOCK_ERR will clear this status information
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_SHIFT                      _MK_SHIFT_CONST(5)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_SHIFT)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_RANGE                      5:5
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_WOFFSET                    0x0
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Respective bit is set by HW on protection range detection. 
+// Write 1 to clear IS.LOCK_ERR will clear this status information
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_SHIFT                      _MK_SHIFT_CONST(4)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_SHIFT)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_RANGE                      4:4
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_WOFFSET                    0x0
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Respective bit is set by HW on protection range detection. 
+// Write 1 to clear IS.LOCK_ERR will clear this status information
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_SHIFT                      _MK_SHIFT_CONST(3)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_SHIFT)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_RANGE                      3:3
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_WOFFSET                    0x0
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Respective bit is set by HW on protection range detection. 
+// Write 1 to clear IS.LOCK_ERR will clear this status information
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_SHIFT)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_RANGE                      2:2
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_WOFFSET                    0x0
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Respective bit is set by HW on protection range detection. 
+// Write 1 to clear IS.LOCK_ERR will clear this status information
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_SHIFT                      _MK_SHIFT_CONST(1)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_SHIFT)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_RANGE                      1:1
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_WOFFSET                    0x0
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Respective bit is set by HW on protection range detection. 
+// Write 1 to clear IS.LOCK_ERR will clear this status information
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_SHIFT)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_RANGE                      0:0
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_WOFFSET                    0x0
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_STATUS_0_LOCK_APER_STATUS0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_START0_0  
+#define NAND_LOCK_APER_START0_0                 _MK_ADDR_CONST(0x6c)
+#define NAND_LOCK_APER_START0_0_SECURE                  0x0
+#define NAND_LOCK_APER_START0_0_WORD_COUNT                      0x1
+#define NAND_LOCK_APER_START0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START0_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START0_0_ADDR_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_START0_0_ADDR_FIELD                      (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START0_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_START0_0_ADDR_RANGE                      31:0
+#define NAND_LOCK_APER_START0_0_ADDR_WOFFSET                    0x0
+#define NAND_LOCK_APER_START0_0_ADDR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START0_0_ADDR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START0_0_ADDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START0_0_ADDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_START1_0  
+#define NAND_LOCK_APER_START1_0                 _MK_ADDR_CONST(0x70)
+#define NAND_LOCK_APER_START1_0_SECURE                  0x0
+#define NAND_LOCK_APER_START1_0_WORD_COUNT                      0x1
+#define NAND_LOCK_APER_START1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START1_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START1_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START1_0_ADDR_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_START1_0_ADDR_FIELD                      (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START1_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_START1_0_ADDR_RANGE                      31:0
+#define NAND_LOCK_APER_START1_0_ADDR_WOFFSET                    0x0
+#define NAND_LOCK_APER_START1_0_ADDR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START1_0_ADDR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START1_0_ADDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START1_0_ADDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_START2_0  
+#define NAND_LOCK_APER_START2_0                 _MK_ADDR_CONST(0x74)
+#define NAND_LOCK_APER_START2_0_SECURE                  0x0
+#define NAND_LOCK_APER_START2_0_WORD_COUNT                      0x1
+#define NAND_LOCK_APER_START2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START2_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START2_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START2_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START2_0_ADDR_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_START2_0_ADDR_FIELD                      (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START2_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_START2_0_ADDR_RANGE                      31:0
+#define NAND_LOCK_APER_START2_0_ADDR_WOFFSET                    0x0
+#define NAND_LOCK_APER_START2_0_ADDR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START2_0_ADDR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START2_0_ADDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START2_0_ADDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_START3_0  
+#define NAND_LOCK_APER_START3_0                 _MK_ADDR_CONST(0x78)
+#define NAND_LOCK_APER_START3_0_SECURE                  0x0
+#define NAND_LOCK_APER_START3_0_WORD_COUNT                      0x1
+#define NAND_LOCK_APER_START3_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START3_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START3_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START3_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START3_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START3_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START3_0_ADDR_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_START3_0_ADDR_FIELD                      (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START3_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_START3_0_ADDR_RANGE                      31:0
+#define NAND_LOCK_APER_START3_0_ADDR_WOFFSET                    0x0
+#define NAND_LOCK_APER_START3_0_ADDR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START3_0_ADDR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START3_0_ADDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START3_0_ADDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_START4_0  
+#define NAND_LOCK_APER_START4_0                 _MK_ADDR_CONST(0x7c)
+#define NAND_LOCK_APER_START4_0_SECURE                  0x0
+#define NAND_LOCK_APER_START4_0_WORD_COUNT                      0x1
+#define NAND_LOCK_APER_START4_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START4_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START4_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START4_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START4_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START4_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START4_0_ADDR_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_START4_0_ADDR_FIELD                      (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START4_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_START4_0_ADDR_RANGE                      31:0
+#define NAND_LOCK_APER_START4_0_ADDR_WOFFSET                    0x0
+#define NAND_LOCK_APER_START4_0_ADDR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START4_0_ADDR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START4_0_ADDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START4_0_ADDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_START5_0  
+#define NAND_LOCK_APER_START5_0                 _MK_ADDR_CONST(0x80)
+#define NAND_LOCK_APER_START5_0_SECURE                  0x0
+#define NAND_LOCK_APER_START5_0_WORD_COUNT                      0x1
+#define NAND_LOCK_APER_START5_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START5_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START5_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START5_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START5_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START5_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START5_0_ADDR_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_START5_0_ADDR_FIELD                      (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START5_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_START5_0_ADDR_RANGE                      31:0
+#define NAND_LOCK_APER_START5_0_ADDR_WOFFSET                    0x0
+#define NAND_LOCK_APER_START5_0_ADDR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START5_0_ADDR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START5_0_ADDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START5_0_ADDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_START6_0  
+#define NAND_LOCK_APER_START6_0                 _MK_ADDR_CONST(0x84)
+#define NAND_LOCK_APER_START6_0_SECURE                  0x0
+#define NAND_LOCK_APER_START6_0_WORD_COUNT                      0x1
+#define NAND_LOCK_APER_START6_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START6_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START6_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START6_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START6_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START6_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START6_0_ADDR_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_START6_0_ADDR_FIELD                      (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START6_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_START6_0_ADDR_RANGE                      31:0
+#define NAND_LOCK_APER_START6_0_ADDR_WOFFSET                    0x0
+#define NAND_LOCK_APER_START6_0_ADDR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START6_0_ADDR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START6_0_ADDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START6_0_ADDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_START7_0  
+#define NAND_LOCK_APER_START7_0                 _MK_ADDR_CONST(0x88)
+#define NAND_LOCK_APER_START7_0_SECURE                  0x0
+#define NAND_LOCK_APER_START7_0_WORD_COUNT                      0x1
+#define NAND_LOCK_APER_START7_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START7_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START7_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START7_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START7_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START7_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_START7_0_ADDR_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_START7_0_ADDR_FIELD                      (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_START7_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_START7_0_ADDR_RANGE                      31:0
+#define NAND_LOCK_APER_START7_0_ADDR_WOFFSET                    0x0
+#define NAND_LOCK_APER_START7_0_ADDR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START7_0_ADDR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START7_0_ADDR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_START7_0_ADDR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_END0_0  
+#define NAND_LOCK_APER_END0_0                   _MK_ADDR_CONST(0x8c)
+#define NAND_LOCK_APER_END0_0_SECURE                    0x0
+#define NAND_LOCK_APER_END0_0_WORD_COUNT                        0x1
+#define NAND_LOCK_APER_END0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END0_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END0_0_ADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_END0_0_ADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END0_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_END0_0_ADDR_RANGE                        31:0
+#define NAND_LOCK_APER_END0_0_ADDR_WOFFSET                      0x0
+#define NAND_LOCK_APER_END0_0_ADDR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END0_0_ADDR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END0_0_ADDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END0_0_ADDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_END1_0  
+#define NAND_LOCK_APER_END1_0                   _MK_ADDR_CONST(0x90)
+#define NAND_LOCK_APER_END1_0_SECURE                    0x0
+#define NAND_LOCK_APER_END1_0_WORD_COUNT                        0x1
+#define NAND_LOCK_APER_END1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END1_0_ADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_END1_0_ADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END1_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_END1_0_ADDR_RANGE                        31:0
+#define NAND_LOCK_APER_END1_0_ADDR_WOFFSET                      0x0
+#define NAND_LOCK_APER_END1_0_ADDR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END1_0_ADDR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END1_0_ADDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END1_0_ADDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_END2_0  
+#define NAND_LOCK_APER_END2_0                   _MK_ADDR_CONST(0x94)
+#define NAND_LOCK_APER_END2_0_SECURE                    0x0
+#define NAND_LOCK_APER_END2_0_WORD_COUNT                        0x1
+#define NAND_LOCK_APER_END2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END2_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END2_0_ADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_END2_0_ADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END2_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_END2_0_ADDR_RANGE                        31:0
+#define NAND_LOCK_APER_END2_0_ADDR_WOFFSET                      0x0
+#define NAND_LOCK_APER_END2_0_ADDR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END2_0_ADDR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END2_0_ADDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END2_0_ADDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_END3_0  
+#define NAND_LOCK_APER_END3_0                   _MK_ADDR_CONST(0x98)
+#define NAND_LOCK_APER_END3_0_SECURE                    0x0
+#define NAND_LOCK_APER_END3_0_WORD_COUNT                        0x1
+#define NAND_LOCK_APER_END3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END3_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END3_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END3_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END3_0_ADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_END3_0_ADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END3_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_END3_0_ADDR_RANGE                        31:0
+#define NAND_LOCK_APER_END3_0_ADDR_WOFFSET                      0x0
+#define NAND_LOCK_APER_END3_0_ADDR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END3_0_ADDR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END3_0_ADDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END3_0_ADDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_END4_0  
+#define NAND_LOCK_APER_END4_0                   _MK_ADDR_CONST(0x9c)
+#define NAND_LOCK_APER_END4_0_SECURE                    0x0
+#define NAND_LOCK_APER_END4_0_WORD_COUNT                        0x1
+#define NAND_LOCK_APER_END4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END4_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END4_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END4_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END4_0_ADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_END4_0_ADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END4_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_END4_0_ADDR_RANGE                        31:0
+#define NAND_LOCK_APER_END4_0_ADDR_WOFFSET                      0x0
+#define NAND_LOCK_APER_END4_0_ADDR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END4_0_ADDR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END4_0_ADDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END4_0_ADDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_END5_0  
+#define NAND_LOCK_APER_END5_0                   _MK_ADDR_CONST(0xa0)
+#define NAND_LOCK_APER_END5_0_SECURE                    0x0
+#define NAND_LOCK_APER_END5_0_WORD_COUNT                        0x1
+#define NAND_LOCK_APER_END5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END5_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END5_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END5_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END5_0_ADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_END5_0_ADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END5_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_END5_0_ADDR_RANGE                        31:0
+#define NAND_LOCK_APER_END5_0_ADDR_WOFFSET                      0x0
+#define NAND_LOCK_APER_END5_0_ADDR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END5_0_ADDR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END5_0_ADDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END5_0_ADDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_END6_0  
+#define NAND_LOCK_APER_END6_0                   _MK_ADDR_CONST(0xa4)
+#define NAND_LOCK_APER_END6_0_SECURE                    0x0
+#define NAND_LOCK_APER_END6_0_WORD_COUNT                        0x1
+#define NAND_LOCK_APER_END6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END6_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END6_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END6_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END6_0_ADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_END6_0_ADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END6_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_END6_0_ADDR_RANGE                        31:0
+#define NAND_LOCK_APER_END6_0_ADDR_WOFFSET                      0x0
+#define NAND_LOCK_APER_END6_0_ADDR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END6_0_ADDR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END6_0_ADDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END6_0_ADDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_END7_0  
+#define NAND_LOCK_APER_END7_0                   _MK_ADDR_CONST(0xa8)
+#define NAND_LOCK_APER_END7_0_SECURE                    0x0
+#define NAND_LOCK_APER_END7_0_WORD_COUNT                        0x1
+#define NAND_LOCK_APER_END7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END7_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END7_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END7_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define NAND_LOCK_APER_END7_0_ADDR_SHIFT                        _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_END7_0_ADDR_FIELD                        (_MK_MASK_CONST(0xffffffff) << NAND_LOCK_APER_END7_0_ADDR_SHIFT)
+#define NAND_LOCK_APER_END7_0_ADDR_RANGE                        31:0
+#define NAND_LOCK_APER_END7_0_ADDR_WOFFSET                      0x0
+#define NAND_LOCK_APER_END7_0_ADDR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END7_0_ADDR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END7_0_ADDR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_END7_0_ADDR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register NAND_LOCK_APER_CHIPID0_0  
+#define NAND_LOCK_APER_CHIPID0_0                        _MK_ADDR_CONST(0xac)
+#define NAND_LOCK_APER_CHIPID0_0_SECURE                         0x0
+#define NAND_LOCK_APER_CHIPID0_0_WORD_COUNT                     0x1
+#define NAND_LOCK_APER_CHIPID0_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define NAND_LOCK_APER_CHIPID0_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+// Memory Protection of aperture[0-7] valid for Chip select7
+#define NAND_LOCK_APER_CHIPID0_0_CS7_SHIFT                      _MK_SHIFT_CONST(7)
+#define NAND_LOCK_APER_CHIPID0_0_CS7_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS7_SHIFT)
+#define NAND_LOCK_APER_CHIPID0_0_CS7_RANGE                      7:7
+#define NAND_LOCK_APER_CHIPID0_0_CS7_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID0_0_CS7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS7_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS7_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select7 
+
+#define NAND_LOCK_APER_CHIPID0_0_CS7_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select6
+#define NAND_LOCK_APER_CHIPID0_0_CS6_SHIFT                      _MK_SHIFT_CONST(6)
+#define NAND_LOCK_APER_CHIPID0_0_CS6_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS6_SHIFT)
+#define NAND_LOCK_APER_CHIPID0_0_CS6_RANGE                      6:6
+#define NAND_LOCK_APER_CHIPID0_0_CS6_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID0_0_CS6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS6_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS6_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select6 
+
+#define NAND_LOCK_APER_CHIPID0_0_CS6_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select5
+#define NAND_LOCK_APER_CHIPID0_0_CS5_SHIFT                      _MK_SHIFT_CONST(5)
+#define NAND_LOCK_APER_CHIPID0_0_CS5_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS5_SHIFT)
+#define NAND_LOCK_APER_CHIPID0_0_CS5_RANGE                      5:5
+#define NAND_LOCK_APER_CHIPID0_0_CS5_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID0_0_CS5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS5_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select5 
+
+#define NAND_LOCK_APER_CHIPID0_0_CS5_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select4
+#define NAND_LOCK_APER_CHIPID0_0_CS4_SHIFT                      _MK_SHIFT_CONST(4)
+#define NAND_LOCK_APER_CHIPID0_0_CS4_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS4_SHIFT)
+#define NAND_LOCK_APER_CHIPID0_0_CS4_RANGE                      4:4
+#define NAND_LOCK_APER_CHIPID0_0_CS4_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID0_0_CS4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS4_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select4 
+
+#define NAND_LOCK_APER_CHIPID0_0_CS4_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select3
+#define NAND_LOCK_APER_CHIPID0_0_CS3_SHIFT                      _MK_SHIFT_CONST(3)
+#define NAND_LOCK_APER_CHIPID0_0_CS3_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS3_SHIFT)
+#define NAND_LOCK_APER_CHIPID0_0_CS3_RANGE                      3:3
+#define NAND_LOCK_APER_CHIPID0_0_CS3_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID0_0_CS3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS3_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select3 
+
+#define NAND_LOCK_APER_CHIPID0_0_CS3_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select2
+#define NAND_LOCK_APER_CHIPID0_0_CS2_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_LOCK_APER_CHIPID0_0_CS2_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS2_SHIFT)
+#define NAND_LOCK_APER_CHIPID0_0_CS2_RANGE                      2:2
+#define NAND_LOCK_APER_CHIPID0_0_CS2_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID0_0_CS2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS2_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select2 
+
+#define NAND_LOCK_APER_CHIPID0_0_CS2_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select1
+#define NAND_LOCK_APER_CHIPID0_0_CS1_SHIFT                      _MK_SHIFT_CONST(1)
+#define NAND_LOCK_APER_CHIPID0_0_CS1_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS1_SHIFT)
+#define NAND_LOCK_APER_CHIPID0_0_CS1_RANGE                      1:1
+#define NAND_LOCK_APER_CHIPID0_0_CS1_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID0_0_CS1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS1_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select1 
+
+#define NAND_LOCK_APER_CHIPID0_0_CS1_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select0
+#define NAND_LOCK_APER_CHIPID0_0_CS0_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_CHIPID0_0_CS0_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID0_0_CS0_SHIFT)
+#define NAND_LOCK_APER_CHIPID0_0_CS0_RANGE                      0:0
+#define NAND_LOCK_APER_CHIPID0_0_CS0_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID0_0_CS0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID0_0_CS0_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select0 
+
+#define NAND_LOCK_APER_CHIPID0_0_CS0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register NAND_LOCK_APER_CHIPID1_0  
+#define NAND_LOCK_APER_CHIPID1_0                        _MK_ADDR_CONST(0xb0)
+#define NAND_LOCK_APER_CHIPID1_0_SECURE                         0x0
+#define NAND_LOCK_APER_CHIPID1_0_WORD_COUNT                     0x1
+#define NAND_LOCK_APER_CHIPID1_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define NAND_LOCK_APER_CHIPID1_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+// Memory Protection of aperture[0-7] valid for Chip select7
+#define NAND_LOCK_APER_CHIPID1_0_CS7_SHIFT                      _MK_SHIFT_CONST(7)
+#define NAND_LOCK_APER_CHIPID1_0_CS7_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS7_SHIFT)
+#define NAND_LOCK_APER_CHIPID1_0_CS7_RANGE                      7:7
+#define NAND_LOCK_APER_CHIPID1_0_CS7_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID1_0_CS7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS7_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS7_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select7 
+
+#define NAND_LOCK_APER_CHIPID1_0_CS7_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select6
+#define NAND_LOCK_APER_CHIPID1_0_CS6_SHIFT                      _MK_SHIFT_CONST(6)
+#define NAND_LOCK_APER_CHIPID1_0_CS6_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS6_SHIFT)
+#define NAND_LOCK_APER_CHIPID1_0_CS6_RANGE                      6:6
+#define NAND_LOCK_APER_CHIPID1_0_CS6_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID1_0_CS6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS6_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS6_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select6 
+
+#define NAND_LOCK_APER_CHIPID1_0_CS6_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select5
+#define NAND_LOCK_APER_CHIPID1_0_CS5_SHIFT                      _MK_SHIFT_CONST(5)
+#define NAND_LOCK_APER_CHIPID1_0_CS5_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS5_SHIFT)
+#define NAND_LOCK_APER_CHIPID1_0_CS5_RANGE                      5:5
+#define NAND_LOCK_APER_CHIPID1_0_CS5_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID1_0_CS5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS5_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select5 
+
+#define NAND_LOCK_APER_CHIPID1_0_CS5_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select4
+#define NAND_LOCK_APER_CHIPID1_0_CS4_SHIFT                      _MK_SHIFT_CONST(4)
+#define NAND_LOCK_APER_CHIPID1_0_CS4_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS4_SHIFT)
+#define NAND_LOCK_APER_CHIPID1_0_CS4_RANGE                      4:4
+#define NAND_LOCK_APER_CHIPID1_0_CS4_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID1_0_CS4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS4_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select4 
+
+#define NAND_LOCK_APER_CHIPID1_0_CS4_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select3
+#define NAND_LOCK_APER_CHIPID1_0_CS3_SHIFT                      _MK_SHIFT_CONST(3)
+#define NAND_LOCK_APER_CHIPID1_0_CS3_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS3_SHIFT)
+#define NAND_LOCK_APER_CHIPID1_0_CS3_RANGE                      3:3
+#define NAND_LOCK_APER_CHIPID1_0_CS3_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID1_0_CS3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS3_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select3 
+
+#define NAND_LOCK_APER_CHIPID1_0_CS3_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select2
+#define NAND_LOCK_APER_CHIPID1_0_CS2_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_LOCK_APER_CHIPID1_0_CS2_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS2_SHIFT)
+#define NAND_LOCK_APER_CHIPID1_0_CS2_RANGE                      2:2
+#define NAND_LOCK_APER_CHIPID1_0_CS2_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID1_0_CS2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS2_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select2 
+
+#define NAND_LOCK_APER_CHIPID1_0_CS2_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select1
+#define NAND_LOCK_APER_CHIPID1_0_CS1_SHIFT                      _MK_SHIFT_CONST(1)
+#define NAND_LOCK_APER_CHIPID1_0_CS1_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS1_SHIFT)
+#define NAND_LOCK_APER_CHIPID1_0_CS1_RANGE                      1:1
+#define NAND_LOCK_APER_CHIPID1_0_CS1_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID1_0_CS1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS1_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select1 
+
+#define NAND_LOCK_APER_CHIPID1_0_CS1_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select0
+#define NAND_LOCK_APER_CHIPID1_0_CS0_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_CHIPID1_0_CS0_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID1_0_CS0_SHIFT)
+#define NAND_LOCK_APER_CHIPID1_0_CS0_RANGE                      0:0
+#define NAND_LOCK_APER_CHIPID1_0_CS0_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID1_0_CS0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID1_0_CS0_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select0 
+
+#define NAND_LOCK_APER_CHIPID1_0_CS0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register NAND_LOCK_APER_CHIPID2_0  
+#define NAND_LOCK_APER_CHIPID2_0                        _MK_ADDR_CONST(0xb4)
+#define NAND_LOCK_APER_CHIPID2_0_SECURE                         0x0
+#define NAND_LOCK_APER_CHIPID2_0_WORD_COUNT                     0x1
+#define NAND_LOCK_APER_CHIPID2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define NAND_LOCK_APER_CHIPID2_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+// Memory Protection of aperture[0-7] valid for Chip select7
+#define NAND_LOCK_APER_CHIPID2_0_CS7_SHIFT                      _MK_SHIFT_CONST(7)
+#define NAND_LOCK_APER_CHIPID2_0_CS7_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS7_SHIFT)
+#define NAND_LOCK_APER_CHIPID2_0_CS7_RANGE                      7:7
+#define NAND_LOCK_APER_CHIPID2_0_CS7_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID2_0_CS7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS7_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS7_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select7 
+
+#define NAND_LOCK_APER_CHIPID2_0_CS7_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select6
+#define NAND_LOCK_APER_CHIPID2_0_CS6_SHIFT                      _MK_SHIFT_CONST(6)
+#define NAND_LOCK_APER_CHIPID2_0_CS6_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS6_SHIFT)
+#define NAND_LOCK_APER_CHIPID2_0_CS6_RANGE                      6:6
+#define NAND_LOCK_APER_CHIPID2_0_CS6_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID2_0_CS6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS6_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS6_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select6 
+
+#define NAND_LOCK_APER_CHIPID2_0_CS6_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select5
+#define NAND_LOCK_APER_CHIPID2_0_CS5_SHIFT                      _MK_SHIFT_CONST(5)
+#define NAND_LOCK_APER_CHIPID2_0_CS5_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS5_SHIFT)
+#define NAND_LOCK_APER_CHIPID2_0_CS5_RANGE                      5:5
+#define NAND_LOCK_APER_CHIPID2_0_CS5_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID2_0_CS5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS5_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select5 
+
+#define NAND_LOCK_APER_CHIPID2_0_CS5_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select4
+#define NAND_LOCK_APER_CHIPID2_0_CS4_SHIFT                      _MK_SHIFT_CONST(4)
+#define NAND_LOCK_APER_CHIPID2_0_CS4_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS4_SHIFT)
+#define NAND_LOCK_APER_CHIPID2_0_CS4_RANGE                      4:4
+#define NAND_LOCK_APER_CHIPID2_0_CS4_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID2_0_CS4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS4_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select4 
+
+#define NAND_LOCK_APER_CHIPID2_0_CS4_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select3
+#define NAND_LOCK_APER_CHIPID2_0_CS3_SHIFT                      _MK_SHIFT_CONST(3)
+#define NAND_LOCK_APER_CHIPID2_0_CS3_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS3_SHIFT)
+#define NAND_LOCK_APER_CHIPID2_0_CS3_RANGE                      3:3
+#define NAND_LOCK_APER_CHIPID2_0_CS3_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID2_0_CS3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS3_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select3 
+
+#define NAND_LOCK_APER_CHIPID2_0_CS3_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select2
+#define NAND_LOCK_APER_CHIPID2_0_CS2_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_LOCK_APER_CHIPID2_0_CS2_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS2_SHIFT)
+#define NAND_LOCK_APER_CHIPID2_0_CS2_RANGE                      2:2
+#define NAND_LOCK_APER_CHIPID2_0_CS2_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID2_0_CS2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS2_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select2 
+
+#define NAND_LOCK_APER_CHIPID2_0_CS2_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select1
+#define NAND_LOCK_APER_CHIPID2_0_CS1_SHIFT                      _MK_SHIFT_CONST(1)
+#define NAND_LOCK_APER_CHIPID2_0_CS1_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS1_SHIFT)
+#define NAND_LOCK_APER_CHIPID2_0_CS1_RANGE                      1:1
+#define NAND_LOCK_APER_CHIPID2_0_CS1_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID2_0_CS1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS1_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select1 
+
+#define NAND_LOCK_APER_CHIPID2_0_CS1_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select0
+#define NAND_LOCK_APER_CHIPID2_0_CS0_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_CHIPID2_0_CS0_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID2_0_CS0_SHIFT)
+#define NAND_LOCK_APER_CHIPID2_0_CS0_RANGE                      0:0
+#define NAND_LOCK_APER_CHIPID2_0_CS0_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID2_0_CS0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID2_0_CS0_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select0 
+
+#define NAND_LOCK_APER_CHIPID2_0_CS0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register NAND_LOCK_APER_CHIPID3_0  
+#define NAND_LOCK_APER_CHIPID3_0                        _MK_ADDR_CONST(0xb8)
+#define NAND_LOCK_APER_CHIPID3_0_SECURE                         0x0
+#define NAND_LOCK_APER_CHIPID3_0_WORD_COUNT                     0x1
+#define NAND_LOCK_APER_CHIPID3_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define NAND_LOCK_APER_CHIPID3_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+// Memory Protection of aperture[0-7] valid for Chip select7
+#define NAND_LOCK_APER_CHIPID3_0_CS7_SHIFT                      _MK_SHIFT_CONST(7)
+#define NAND_LOCK_APER_CHIPID3_0_CS7_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS7_SHIFT)
+#define NAND_LOCK_APER_CHIPID3_0_CS7_RANGE                      7:7
+#define NAND_LOCK_APER_CHIPID3_0_CS7_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID3_0_CS7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS7_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS7_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select7 
+
+#define NAND_LOCK_APER_CHIPID3_0_CS7_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select6
+#define NAND_LOCK_APER_CHIPID3_0_CS6_SHIFT                      _MK_SHIFT_CONST(6)
+#define NAND_LOCK_APER_CHIPID3_0_CS6_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS6_SHIFT)
+#define NAND_LOCK_APER_CHIPID3_0_CS6_RANGE                      6:6
+#define NAND_LOCK_APER_CHIPID3_0_CS6_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID3_0_CS6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS6_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS6_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select6 
+
+#define NAND_LOCK_APER_CHIPID3_0_CS6_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select5
+#define NAND_LOCK_APER_CHIPID3_0_CS5_SHIFT                      _MK_SHIFT_CONST(5)
+#define NAND_LOCK_APER_CHIPID3_0_CS5_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS5_SHIFT)
+#define NAND_LOCK_APER_CHIPID3_0_CS5_RANGE                      5:5
+#define NAND_LOCK_APER_CHIPID3_0_CS5_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID3_0_CS5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS5_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select5 
+
+#define NAND_LOCK_APER_CHIPID3_0_CS5_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select4
+#define NAND_LOCK_APER_CHIPID3_0_CS4_SHIFT                      _MK_SHIFT_CONST(4)
+#define NAND_LOCK_APER_CHIPID3_0_CS4_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS4_SHIFT)
+#define NAND_LOCK_APER_CHIPID3_0_CS4_RANGE                      4:4
+#define NAND_LOCK_APER_CHIPID3_0_CS4_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID3_0_CS4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS4_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select4 
+
+#define NAND_LOCK_APER_CHIPID3_0_CS4_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select3
+#define NAND_LOCK_APER_CHIPID3_0_CS3_SHIFT                      _MK_SHIFT_CONST(3)
+#define NAND_LOCK_APER_CHIPID3_0_CS3_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS3_SHIFT)
+#define NAND_LOCK_APER_CHIPID3_0_CS3_RANGE                      3:3
+#define NAND_LOCK_APER_CHIPID3_0_CS3_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID3_0_CS3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS3_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select3 
+
+#define NAND_LOCK_APER_CHIPID3_0_CS3_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select2
+#define NAND_LOCK_APER_CHIPID3_0_CS2_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_LOCK_APER_CHIPID3_0_CS2_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS2_SHIFT)
+#define NAND_LOCK_APER_CHIPID3_0_CS2_RANGE                      2:2
+#define NAND_LOCK_APER_CHIPID3_0_CS2_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID3_0_CS2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS2_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select2 
+
+#define NAND_LOCK_APER_CHIPID3_0_CS2_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select1
+#define NAND_LOCK_APER_CHIPID3_0_CS1_SHIFT                      _MK_SHIFT_CONST(1)
+#define NAND_LOCK_APER_CHIPID3_0_CS1_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS1_SHIFT)
+#define NAND_LOCK_APER_CHIPID3_0_CS1_RANGE                      1:1
+#define NAND_LOCK_APER_CHIPID3_0_CS1_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID3_0_CS1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS1_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select1 
+
+#define NAND_LOCK_APER_CHIPID3_0_CS1_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select0
+#define NAND_LOCK_APER_CHIPID3_0_CS0_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_CHIPID3_0_CS0_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID3_0_CS0_SHIFT)
+#define NAND_LOCK_APER_CHIPID3_0_CS0_RANGE                      0:0
+#define NAND_LOCK_APER_CHIPID3_0_CS0_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID3_0_CS0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID3_0_CS0_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select0 
+
+#define NAND_LOCK_APER_CHIPID3_0_CS0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register NAND_LOCK_APER_CHIPID4_0  
+#define NAND_LOCK_APER_CHIPID4_0                        _MK_ADDR_CONST(0xbc)
+#define NAND_LOCK_APER_CHIPID4_0_SECURE                         0x0
+#define NAND_LOCK_APER_CHIPID4_0_WORD_COUNT                     0x1
+#define NAND_LOCK_APER_CHIPID4_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define NAND_LOCK_APER_CHIPID4_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+// Memory Protection of aperture[0-7] valid for Chip select7
+#define NAND_LOCK_APER_CHIPID4_0_CS7_SHIFT                      _MK_SHIFT_CONST(7)
+#define NAND_LOCK_APER_CHIPID4_0_CS7_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS7_SHIFT)
+#define NAND_LOCK_APER_CHIPID4_0_CS7_RANGE                      7:7
+#define NAND_LOCK_APER_CHIPID4_0_CS7_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID4_0_CS7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS7_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS7_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select7 
+
+#define NAND_LOCK_APER_CHIPID4_0_CS7_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select6
+#define NAND_LOCK_APER_CHIPID4_0_CS6_SHIFT                      _MK_SHIFT_CONST(6)
+#define NAND_LOCK_APER_CHIPID4_0_CS6_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS6_SHIFT)
+#define NAND_LOCK_APER_CHIPID4_0_CS6_RANGE                      6:6
+#define NAND_LOCK_APER_CHIPID4_0_CS6_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID4_0_CS6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS6_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS6_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select6 
+
+#define NAND_LOCK_APER_CHIPID4_0_CS6_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select5
+#define NAND_LOCK_APER_CHIPID4_0_CS5_SHIFT                      _MK_SHIFT_CONST(5)
+#define NAND_LOCK_APER_CHIPID4_0_CS5_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS5_SHIFT)
+#define NAND_LOCK_APER_CHIPID4_0_CS5_RANGE                      5:5
+#define NAND_LOCK_APER_CHIPID4_0_CS5_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID4_0_CS5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS5_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select5 
+
+#define NAND_LOCK_APER_CHIPID4_0_CS5_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select4
+#define NAND_LOCK_APER_CHIPID4_0_CS4_SHIFT                      _MK_SHIFT_CONST(4)
+#define NAND_LOCK_APER_CHIPID4_0_CS4_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS4_SHIFT)
+#define NAND_LOCK_APER_CHIPID4_0_CS4_RANGE                      4:4
+#define NAND_LOCK_APER_CHIPID4_0_CS4_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID4_0_CS4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS4_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select4 
+
+#define NAND_LOCK_APER_CHIPID4_0_CS4_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select3
+#define NAND_LOCK_APER_CHIPID4_0_CS3_SHIFT                      _MK_SHIFT_CONST(3)
+#define NAND_LOCK_APER_CHIPID4_0_CS3_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS3_SHIFT)
+#define NAND_LOCK_APER_CHIPID4_0_CS3_RANGE                      3:3
+#define NAND_LOCK_APER_CHIPID4_0_CS3_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID4_0_CS3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS3_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select3 
+
+#define NAND_LOCK_APER_CHIPID4_0_CS3_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select2
+#define NAND_LOCK_APER_CHIPID4_0_CS2_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_LOCK_APER_CHIPID4_0_CS2_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS2_SHIFT)
+#define NAND_LOCK_APER_CHIPID4_0_CS2_RANGE                      2:2
+#define NAND_LOCK_APER_CHIPID4_0_CS2_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID4_0_CS2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS2_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select2 
+
+#define NAND_LOCK_APER_CHIPID4_0_CS2_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select1
+#define NAND_LOCK_APER_CHIPID4_0_CS1_SHIFT                      _MK_SHIFT_CONST(1)
+#define NAND_LOCK_APER_CHIPID4_0_CS1_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS1_SHIFT)
+#define NAND_LOCK_APER_CHIPID4_0_CS1_RANGE                      1:1
+#define NAND_LOCK_APER_CHIPID4_0_CS1_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID4_0_CS1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS1_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select1 
+
+#define NAND_LOCK_APER_CHIPID4_0_CS1_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select0
+#define NAND_LOCK_APER_CHIPID4_0_CS0_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_CHIPID4_0_CS0_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID4_0_CS0_SHIFT)
+#define NAND_LOCK_APER_CHIPID4_0_CS0_RANGE                      0:0
+#define NAND_LOCK_APER_CHIPID4_0_CS0_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID4_0_CS0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID4_0_CS0_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select0 
+
+#define NAND_LOCK_APER_CHIPID4_0_CS0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register NAND_LOCK_APER_CHIPID5_0  
+#define NAND_LOCK_APER_CHIPID5_0                        _MK_ADDR_CONST(0xc0)
+#define NAND_LOCK_APER_CHIPID5_0_SECURE                         0x0
+#define NAND_LOCK_APER_CHIPID5_0_WORD_COUNT                     0x1
+#define NAND_LOCK_APER_CHIPID5_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define NAND_LOCK_APER_CHIPID5_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+// Memory Protection of aperture[0-7] valid for Chip select7
+#define NAND_LOCK_APER_CHIPID5_0_CS7_SHIFT                      _MK_SHIFT_CONST(7)
+#define NAND_LOCK_APER_CHIPID5_0_CS7_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS7_SHIFT)
+#define NAND_LOCK_APER_CHIPID5_0_CS7_RANGE                      7:7
+#define NAND_LOCK_APER_CHIPID5_0_CS7_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID5_0_CS7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS7_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS7_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select7 
+
+#define NAND_LOCK_APER_CHIPID5_0_CS7_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select6
+#define NAND_LOCK_APER_CHIPID5_0_CS6_SHIFT                      _MK_SHIFT_CONST(6)
+#define NAND_LOCK_APER_CHIPID5_0_CS6_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS6_SHIFT)
+#define NAND_LOCK_APER_CHIPID5_0_CS6_RANGE                      6:6
+#define NAND_LOCK_APER_CHIPID5_0_CS6_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID5_0_CS6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS6_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS6_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select6 
+
+#define NAND_LOCK_APER_CHIPID5_0_CS6_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select5
+#define NAND_LOCK_APER_CHIPID5_0_CS5_SHIFT                      _MK_SHIFT_CONST(5)
+#define NAND_LOCK_APER_CHIPID5_0_CS5_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS5_SHIFT)
+#define NAND_LOCK_APER_CHIPID5_0_CS5_RANGE                      5:5
+#define NAND_LOCK_APER_CHIPID5_0_CS5_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID5_0_CS5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS5_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select5 
+
+#define NAND_LOCK_APER_CHIPID5_0_CS5_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select4
+#define NAND_LOCK_APER_CHIPID5_0_CS4_SHIFT                      _MK_SHIFT_CONST(4)
+#define NAND_LOCK_APER_CHIPID5_0_CS4_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS4_SHIFT)
+#define NAND_LOCK_APER_CHIPID5_0_CS4_RANGE                      4:4
+#define NAND_LOCK_APER_CHIPID5_0_CS4_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID5_0_CS4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS4_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select4 
+
+#define NAND_LOCK_APER_CHIPID5_0_CS4_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select3
+#define NAND_LOCK_APER_CHIPID5_0_CS3_SHIFT                      _MK_SHIFT_CONST(3)
+#define NAND_LOCK_APER_CHIPID5_0_CS3_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS3_SHIFT)
+#define NAND_LOCK_APER_CHIPID5_0_CS3_RANGE                      3:3
+#define NAND_LOCK_APER_CHIPID5_0_CS3_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID5_0_CS3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS3_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select3 
+
+#define NAND_LOCK_APER_CHIPID5_0_CS3_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select2
+#define NAND_LOCK_APER_CHIPID5_0_CS2_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_LOCK_APER_CHIPID5_0_CS2_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS2_SHIFT)
+#define NAND_LOCK_APER_CHIPID5_0_CS2_RANGE                      2:2
+#define NAND_LOCK_APER_CHIPID5_0_CS2_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID5_0_CS2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS2_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select2 
+
+#define NAND_LOCK_APER_CHIPID5_0_CS2_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select1
+#define NAND_LOCK_APER_CHIPID5_0_CS1_SHIFT                      _MK_SHIFT_CONST(1)
+#define NAND_LOCK_APER_CHIPID5_0_CS1_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS1_SHIFT)
+#define NAND_LOCK_APER_CHIPID5_0_CS1_RANGE                      1:1
+#define NAND_LOCK_APER_CHIPID5_0_CS1_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID5_0_CS1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS1_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select1 
+
+#define NAND_LOCK_APER_CHIPID5_0_CS1_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select0
+#define NAND_LOCK_APER_CHIPID5_0_CS0_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_CHIPID5_0_CS0_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID5_0_CS0_SHIFT)
+#define NAND_LOCK_APER_CHIPID5_0_CS0_RANGE                      0:0
+#define NAND_LOCK_APER_CHIPID5_0_CS0_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID5_0_CS0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID5_0_CS0_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select0 
+
+#define NAND_LOCK_APER_CHIPID5_0_CS0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register NAND_LOCK_APER_CHIPID6_0  
+#define NAND_LOCK_APER_CHIPID6_0                        _MK_ADDR_CONST(0xc4)
+#define NAND_LOCK_APER_CHIPID6_0_SECURE                         0x0
+#define NAND_LOCK_APER_CHIPID6_0_WORD_COUNT                     0x1
+#define NAND_LOCK_APER_CHIPID6_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define NAND_LOCK_APER_CHIPID6_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+// Memory Protection of aperture[0-7] valid for Chip select7
+#define NAND_LOCK_APER_CHIPID6_0_CS7_SHIFT                      _MK_SHIFT_CONST(7)
+#define NAND_LOCK_APER_CHIPID6_0_CS7_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS7_SHIFT)
+#define NAND_LOCK_APER_CHIPID6_0_CS7_RANGE                      7:7
+#define NAND_LOCK_APER_CHIPID6_0_CS7_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID6_0_CS7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS7_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS7_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select7 
+
+#define NAND_LOCK_APER_CHIPID6_0_CS7_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select6
+#define NAND_LOCK_APER_CHIPID6_0_CS6_SHIFT                      _MK_SHIFT_CONST(6)
+#define NAND_LOCK_APER_CHIPID6_0_CS6_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS6_SHIFT)
+#define NAND_LOCK_APER_CHIPID6_0_CS6_RANGE                      6:6
+#define NAND_LOCK_APER_CHIPID6_0_CS6_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID6_0_CS6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS6_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS6_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select6 
+
+#define NAND_LOCK_APER_CHIPID6_0_CS6_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select5
+#define NAND_LOCK_APER_CHIPID6_0_CS5_SHIFT                      _MK_SHIFT_CONST(5)
+#define NAND_LOCK_APER_CHIPID6_0_CS5_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS5_SHIFT)
+#define NAND_LOCK_APER_CHIPID6_0_CS5_RANGE                      5:5
+#define NAND_LOCK_APER_CHIPID6_0_CS5_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID6_0_CS5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS5_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select5 
+
+#define NAND_LOCK_APER_CHIPID6_0_CS5_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select4
+#define NAND_LOCK_APER_CHIPID6_0_CS4_SHIFT                      _MK_SHIFT_CONST(4)
+#define NAND_LOCK_APER_CHIPID6_0_CS4_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS4_SHIFT)
+#define NAND_LOCK_APER_CHIPID6_0_CS4_RANGE                      4:4
+#define NAND_LOCK_APER_CHIPID6_0_CS4_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID6_0_CS4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS4_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select4 
+
+#define NAND_LOCK_APER_CHIPID6_0_CS4_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select3
+#define NAND_LOCK_APER_CHIPID6_0_CS3_SHIFT                      _MK_SHIFT_CONST(3)
+#define NAND_LOCK_APER_CHIPID6_0_CS3_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS3_SHIFT)
+#define NAND_LOCK_APER_CHIPID6_0_CS3_RANGE                      3:3
+#define NAND_LOCK_APER_CHIPID6_0_CS3_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID6_0_CS3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS3_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select3 
+
+#define NAND_LOCK_APER_CHIPID6_0_CS3_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select2
+#define NAND_LOCK_APER_CHIPID6_0_CS2_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_LOCK_APER_CHIPID6_0_CS2_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS2_SHIFT)
+#define NAND_LOCK_APER_CHIPID6_0_CS2_RANGE                      2:2
+#define NAND_LOCK_APER_CHIPID6_0_CS2_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID6_0_CS2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS2_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select2 
+
+#define NAND_LOCK_APER_CHIPID6_0_CS2_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select1
+#define NAND_LOCK_APER_CHIPID6_0_CS1_SHIFT                      _MK_SHIFT_CONST(1)
+#define NAND_LOCK_APER_CHIPID6_0_CS1_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS1_SHIFT)
+#define NAND_LOCK_APER_CHIPID6_0_CS1_RANGE                      1:1
+#define NAND_LOCK_APER_CHIPID6_0_CS1_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID6_0_CS1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS1_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select1 
+
+#define NAND_LOCK_APER_CHIPID6_0_CS1_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select0
+#define NAND_LOCK_APER_CHIPID6_0_CS0_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_CHIPID6_0_CS0_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID6_0_CS0_SHIFT)
+#define NAND_LOCK_APER_CHIPID6_0_CS0_RANGE                      0:0
+#define NAND_LOCK_APER_CHIPID6_0_CS0_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID6_0_CS0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID6_0_CS0_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select0 
+
+#define NAND_LOCK_APER_CHIPID6_0_CS0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register NAND_LOCK_APER_CHIPID7_0  
+#define NAND_LOCK_APER_CHIPID7_0                        _MK_ADDR_CONST(0xc8)
+#define NAND_LOCK_APER_CHIPID7_0_SECURE                         0x0
+#define NAND_LOCK_APER_CHIPID7_0_WORD_COUNT                     0x1
+#define NAND_LOCK_APER_CHIPID7_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_READ_MASK                      _MK_MASK_CONST(0xff)
+#define NAND_LOCK_APER_CHIPID7_0_WRITE_MASK                     _MK_MASK_CONST(0xff)
+// Memory Protection of aperture[0-7] valid for Chip select7
+#define NAND_LOCK_APER_CHIPID7_0_CS7_SHIFT                      _MK_SHIFT_CONST(7)
+#define NAND_LOCK_APER_CHIPID7_0_CS7_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS7_SHIFT)
+#define NAND_LOCK_APER_CHIPID7_0_CS7_RANGE                      7:7
+#define NAND_LOCK_APER_CHIPID7_0_CS7_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID7_0_CS7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS7_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS7_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select7 
+
+#define NAND_LOCK_APER_CHIPID7_0_CS7_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select6
+#define NAND_LOCK_APER_CHIPID7_0_CS6_SHIFT                      _MK_SHIFT_CONST(6)
+#define NAND_LOCK_APER_CHIPID7_0_CS6_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS6_SHIFT)
+#define NAND_LOCK_APER_CHIPID7_0_CS6_RANGE                      6:6
+#define NAND_LOCK_APER_CHIPID7_0_CS6_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID7_0_CS6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS6_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS6_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select6 
+
+#define NAND_LOCK_APER_CHIPID7_0_CS6_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select5
+#define NAND_LOCK_APER_CHIPID7_0_CS5_SHIFT                      _MK_SHIFT_CONST(5)
+#define NAND_LOCK_APER_CHIPID7_0_CS5_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS5_SHIFT)
+#define NAND_LOCK_APER_CHIPID7_0_CS5_RANGE                      5:5
+#define NAND_LOCK_APER_CHIPID7_0_CS5_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID7_0_CS5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS5_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS5_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select5 
+
+#define NAND_LOCK_APER_CHIPID7_0_CS5_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select4
+#define NAND_LOCK_APER_CHIPID7_0_CS4_SHIFT                      _MK_SHIFT_CONST(4)
+#define NAND_LOCK_APER_CHIPID7_0_CS4_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS4_SHIFT)
+#define NAND_LOCK_APER_CHIPID7_0_CS4_RANGE                      4:4
+#define NAND_LOCK_APER_CHIPID7_0_CS4_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID7_0_CS4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS4_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS4_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select4 
+
+#define NAND_LOCK_APER_CHIPID7_0_CS4_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select3
+#define NAND_LOCK_APER_CHIPID7_0_CS3_SHIFT                      _MK_SHIFT_CONST(3)
+#define NAND_LOCK_APER_CHIPID7_0_CS3_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS3_SHIFT)
+#define NAND_LOCK_APER_CHIPID7_0_CS3_RANGE                      3:3
+#define NAND_LOCK_APER_CHIPID7_0_CS3_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID7_0_CS3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS3_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS3_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select3 
+
+#define NAND_LOCK_APER_CHIPID7_0_CS3_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select2
+#define NAND_LOCK_APER_CHIPID7_0_CS2_SHIFT                      _MK_SHIFT_CONST(2)
+#define NAND_LOCK_APER_CHIPID7_0_CS2_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS2_SHIFT)
+#define NAND_LOCK_APER_CHIPID7_0_CS2_RANGE                      2:2
+#define NAND_LOCK_APER_CHIPID7_0_CS2_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID7_0_CS2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS2_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select2 
+
+#define NAND_LOCK_APER_CHIPID7_0_CS2_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select1
+#define NAND_LOCK_APER_CHIPID7_0_CS1_SHIFT                      _MK_SHIFT_CONST(1)
+#define NAND_LOCK_APER_CHIPID7_0_CS1_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS1_SHIFT)
+#define NAND_LOCK_APER_CHIPID7_0_CS1_RANGE                      1:1
+#define NAND_LOCK_APER_CHIPID7_0_CS1_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID7_0_CS1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS1_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select1 
+
+#define NAND_LOCK_APER_CHIPID7_0_CS1_ENABLE                     _MK_ENUM_CONST(1)
+
+// Memory Protection of aperture[0-7] valid for Chip select0
+#define NAND_LOCK_APER_CHIPID7_0_CS0_SHIFT                      _MK_SHIFT_CONST(0)
+#define NAND_LOCK_APER_CHIPID7_0_CS0_FIELD                      (_MK_MASK_CONST(0x1) << NAND_LOCK_APER_CHIPID7_0_CS0_SHIFT)
+#define NAND_LOCK_APER_CHIPID7_0_CS0_RANGE                      0:0
+#define NAND_LOCK_APER_CHIPID7_0_CS0_WOFFSET                    0x0
+#define NAND_LOCK_APER_CHIPID7_0_CS0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_LOCK_APER_CHIPID7_0_CS0_DISABLE                    _MK_ENUM_CONST(0)    // // Memory Protection of aperture[0-7] not valid for Chip select0 
+
+#define NAND_LOCK_APER_CHIPID7_0_CS0_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register NAND_BCH_CONFIG_0  
+#define NAND_BCH_CONFIG_0                       _MK_ADDR_CONST(0xcc)
+#define NAND_BCH_CONFIG_0_SECURE                        0x0
+#define NAND_BCH_CONFIG_0_WORD_COUNT                    0x1
+#define NAND_BCH_CONFIG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define NAND_BCH_CONFIG_0_RESET_MASK                    _MK_MASK_CONST(0x31)
+#define NAND_BCH_CONFIG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define NAND_BCH_CONFIG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_BCH_CONFIG_0_READ_MASK                     _MK_MASK_CONST(0x31)
+#define NAND_BCH_CONFIG_0_WRITE_MASK                    _MK_MASK_CONST(0x31)
+// BCH error correction strength selection 16 single bit random errors per sector 
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_SHIFT                      _MK_SHIFT_CONST(4)
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_FIELD                      (_MK_MASK_CONST(0x3) << NAND_BCH_CONFIG_0_BCH_TVALUE_SHIFT)
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_RANGE                      5:4
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_WOFFSET                    0x0
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_BCH_TVAL4                  _MK_ENUM_CONST(0)    // // 4 single bit random errors per sector
+
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_BCH_TVAL8                  _MK_ENUM_CONST(1)    // // 8 single bit random errors per sector
+
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_BCH_TVAL14                 _MK_ENUM_CONST(2)    // // 14 single bit random errors per sector
+
+#define NAND_BCH_CONFIG_0_BCH_TVALUE_BCH_TVAL16                 _MK_ENUM_CONST(3)
+
+// BCH encoder & decoder is enabled
+#define NAND_BCH_CONFIG_0_BCH_ECC_SHIFT                 _MK_SHIFT_CONST(0)
+#define NAND_BCH_CONFIG_0_BCH_ECC_FIELD                 (_MK_MASK_CONST(0x1) << NAND_BCH_CONFIG_0_BCH_ECC_SHIFT)
+#define NAND_BCH_CONFIG_0_BCH_ECC_RANGE                 0:0
+#define NAND_BCH_CONFIG_0_BCH_ECC_WOFFSET                       0x0
+#define NAND_BCH_CONFIG_0_BCH_ECC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_BCH_CONFIG_0_BCH_ECC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define NAND_BCH_CONFIG_0_BCH_ECC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define NAND_BCH_CONFIG_0_BCH_ECC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_BCH_CONFIG_0_BCH_ECC_DISABLE                       _MK_ENUM_CONST(0)    // // BCH encoder & decoder is not enabled
+
+#define NAND_BCH_CONFIG_0_BCH_ECC_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register NAND_BCH_DEC_RESULT_0  
+#define NAND_BCH_DEC_RESULT_0                   _MK_ADDR_CONST(0xd0)
+#define NAND_BCH_DEC_RESULT_0_SECURE                    0x0
+#define NAND_BCH_DEC_RESULT_0_WORD_COUNT                        0x1
+#define NAND_BCH_DEC_RESULT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_RESULT_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_RESULT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_RESULT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_RESULT_0_READ_MASK                         _MK_MASK_CONST(0x1ff)
+#define NAND_BCH_DEC_RESULT_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// 1 = Correctable OR Un-correctable errors occurred in the DMA transfer 
+//     without regard to HW_ERR_CORRECTION feature is enabled or not. 
+//     Use extended decode results in NAND_DEC_RESULT and NAND_DEC_STATUS_EXT 
+//     to figure out further action for block replacement/wear leveling during 
+//     file system management for s/w.
+#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_SHIFT                        _MK_SHIFT_CONST(8)
+#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_FIELD                        (_MK_MASK_CONST(0x1) << NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_SHIFT)
+#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_RANGE                        8:8
+#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_WOFFSET                      0x0
+#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_RESULT_0_CORRFAIL_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// No. of pages resulted either in un-correctable or correctable errors
+#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_SHIFT                  _MK_SHIFT_CONST(0)
+#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_FIELD                  (_MK_MASK_CONST(0xff) << NAND_BCH_DEC_RESULT_0_PAGE_COUNT_SHIFT)
+#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_RANGE                  7:0
+#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_WOFFSET                        0x0
+#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_RESULT_0_PAGE_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register NAND_BCH_DEC_STATUS_BUF_0  
+#define NAND_BCH_DEC_STATUS_BUF_0                       _MK_ADDR_CONST(0xd4)
+#define NAND_BCH_DEC_STATUS_BUF_0_SECURE                        0x0
+#define NAND_BCH_DEC_STATUS_BUF_0_WORD_COUNT                    0x1
+#define NAND_BCH_DEC_STATUS_BUF_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_READ_MASK                     _MK_MASK_CONST(0xffff7fff)
+#define NAND_BCH_DEC_STATUS_BUF_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Sector wise un-correctable error indicator
+// Bit 31 = 1, sector 7 has un-correctable errors
+// Bit 31 = 0, sector 7 has no un-correctable errors
+// ...
+// Bit 24 = 1, sector 0 has un-correctable errors
+// Bit 24 = 0, sector 0 has no un-correctable errors
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_SHIFT                   _MK_SHIFT_CONST(24)
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_FIELD                   (_MK_MASK_CONST(0xff) << NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_SHIFT)
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_RANGE                   31:24
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_WOFFSET                 0x0
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_SEC_FLAG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Sector wise correctable error indicator
+// Bit 23 = 1, sector 7 has correctable errors
+// Bit 23 = 0, sector 7 has no correctable errors
+// ...
+// Bit 16 = 1, sector 0 has correctable errors
+// Bit 16 = 0, sector 0 has no correctable errors
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_SHIFT                   _MK_SHIFT_CONST(16)
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_FIELD                   (_MK_MASK_CONST(0xff) << NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_SHIFT)
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_RANGE                   23:16
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_WOFFSET                 0x0
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_SEC_FLAG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare area error decode resulted in un-correctable errors 
+// in case of RS/Hamming ECC selection.
+// For BCH this field is not applicable.
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_SHIFT                        _MK_SHIFT_CONST(14)
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_FIELD                        (_MK_MASK_CONST(0x1) << NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_SHIFT)
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_RANGE                        14:14
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_WOFFSET                      0x0
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_FAIL_TAG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Spare area error decode resulted in correctable errors 
+// in case of RS/Hamming ECC selection.
+// For BCH this field is not applicable.
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_SHIFT                        _MK_SHIFT_CONST(13)
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_FIELD                        (_MK_MASK_CONST(0x1) << NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_SHIFT)
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_RANGE                        13:13
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_WOFFSET                      0x0
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_DEFAULT                      _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_CORR_TAG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Maximum no. of correctable errors occurred out of all sectors.
+// For example of 2K page, if sector 0 has 2 correctable errors 
+// and sector3 has 4 errors MAX_ERR_CNT will reflect as 4                                      
+#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_SHIFT                    _MK_SHIFT_CONST(8)
+#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_FIELD                    (_MK_MASK_CONST(0x1f) << NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_SHIFT)
+#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_RANGE                    12:8
+#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_WOFFSET                  0x0
+#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_MAX_CORR_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Page number which resulted in either correctable/un-correctable errors
+// 0 to 63 indicattion for 64 pages of DMA transfer.
+#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_SHIFT                     _MK_SHIFT_CONST(0)
+#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_FIELD                     (_MK_MASK_CONST(0xff) << NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_SHIFT)
+#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_RANGE                     7:0
+#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_WOFFSET                   0x0
+#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define NAND_BCH_DEC_STATUS_BUF_0_PAGE_NUMBER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Packet CMDQ_CMD
+#define CMDQ_CMD_SIZE 32
+
+// Pakcet ID
+#define CMDQ_CMD_PKT_ID_SHIFT                   _MK_SHIFT_CONST(24)
+#define CMDQ_CMD_PKT_ID_FIELD                   (_MK_MASK_CONST(0xff) << CMDQ_CMD_PKT_ID_SHIFT)
+#define CMDQ_CMD_PKT_ID_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CMDQ_CMD_PKT_ID_ROW                     0
+
+// not used range
+#define CMDQ_CMD_RSVD_SHIFT                     _MK_SHIFT_CONST(14)
+#define CMDQ_CMD_RSVD_FIELD                     (_MK_MASK_CONST(0x3ff) << CMDQ_CMD_RSVD_SHIFT)
+#define CMDQ_CMD_RSVD_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(14)
+#define CMDQ_CMD_RSVD_ROW                       0
+
+// ENABLE = NAND_COMMAND register requires update in this packet execution
+#define CMDQ_CMD_COMMAND_SHIFT                  _MK_SHIFT_CONST(13)
+#define CMDQ_CMD_COMMAND_FIELD                  (_MK_MASK_CONST(0x1) << CMDQ_CMD_COMMAND_SHIFT)
+#define CMDQ_CMD_COMMAND_RANGE                  _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13)
+#define CMDQ_CMD_COMMAND_ROW                    0
+#define CMDQ_CMD_COMMAND_DISABLE                        _MK_ENUM_CONST(0)
+#define CMDQ_CMD_COMMAND_ENABLE                 _MK_ENUM_CONST(1)
+
+// ENABLE = NAND_HWSTATUS_MASK register requires update in this packet execution
+#define CMDQ_CMD_HWSTATUS_MASK_SHIFT                    _MK_SHIFT_CONST(12)
+#define CMDQ_CMD_HWSTATUS_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CMDQ_CMD_HWSTATUS_MASK_SHIFT)
+#define CMDQ_CMD_HWSTATUS_MASK_RANGE                    _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12)
+#define CMDQ_CMD_HWSTATUS_MASK_ROW                      0
+#define CMDQ_CMD_HWSTATUS_MASK_DISABLE                  _MK_ENUM_CONST(0)
+#define CMDQ_CMD_HWSTATUS_MASK_ENABLE                   _MK_ENUM_CONST(1)
+
+//
+#define CMDQ_CMD_HWSTATUS_CMD_SHIFT                     _MK_SHIFT_CONST(11)
+#define CMDQ_CMD_HWSTATUS_CMD_FIELD                     (_MK_MASK_CONST(0x1) << CMDQ_CMD_HWSTATUS_CMD_SHIFT)
+#define CMDQ_CMD_HWSTATUS_CMD_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
+#define CMDQ_CMD_HWSTATUS_CMD_ROW                       0
+#define CMDQ_CMD_HWSTATUS_CMD_DISABLE                   _MK_ENUM_CONST(0)
+#define CMDQ_CMD_HWSTATUS_CMD_ENABLE                    _MK_ENUM_CONST(1)
+
+//
+#define CMDQ_CMD_CMD_REG2_SHIFT                 _MK_SHIFT_CONST(10)
+#define CMDQ_CMD_CMD_REG2_FIELD                 (_MK_MASK_CONST(0x1) << CMDQ_CMD_CMD_REG2_SHIFT)
+#define CMDQ_CMD_CMD_REG2_RANGE                 _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10)
+#define CMDQ_CMD_CMD_REG2_ROW                   0
+#define CMDQ_CMD_CMD_REG2_DISABLE                       _MK_ENUM_CONST(0)
+#define CMDQ_CMD_CMD_REG2_ENABLE                        _MK_ENUM_CONST(1)
+
+//
+#define CMDQ_CMD_CMD_REG1_SHIFT                 _MK_SHIFT_CONST(9)
+#define CMDQ_CMD_CMD_REG1_FIELD                 (_MK_MASK_CONST(0x1) << CMDQ_CMD_CMD_REG1_SHIFT)
+#define CMDQ_CMD_CMD_REG1_RANGE                 _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
+#define CMDQ_CMD_CMD_REG1_ROW                   0
+#define CMDQ_CMD_CMD_REG1_DISABLE                       _MK_ENUM_CONST(0)
+#define CMDQ_CMD_CMD_REG1_ENABLE                        _MK_ENUM_CONST(1)
+
+//
+#define CMDQ_CMD_ADDR_REG2_SHIFT                        _MK_SHIFT_CONST(8)
+#define CMDQ_CMD_ADDR_REG2_FIELD                        (_MK_MASK_CONST(0x1) << CMDQ_CMD_ADDR_REG2_SHIFT)
+#define CMDQ_CMD_ADDR_REG2_RANGE                        _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
+#define CMDQ_CMD_ADDR_REG2_ROW                  0
+#define CMDQ_CMD_ADDR_REG2_DISABLE                      _MK_ENUM_CONST(0)
+#define CMDQ_CMD_ADDR_REG2_ENABLE                       _MK_ENUM_CONST(1)
+
+//
+#define CMDQ_CMD_ADDR_REG1_SHIFT                        _MK_SHIFT_CONST(7)
+#define CMDQ_CMD_ADDR_REG1_FIELD                        (_MK_MASK_CONST(0x1) << CMDQ_CMD_ADDR_REG1_SHIFT)
+#define CMDQ_CMD_ADDR_REG1_RANGE                        _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define CMDQ_CMD_ADDR_REG1_ROW                  0
+#define CMDQ_CMD_ADDR_REG1_DISABLE                      _MK_ENUM_CONST(0)
+#define CMDQ_CMD_ADDR_REG1_ENABLE                       _MK_ENUM_CONST(1)
+
+//
+#define CMDQ_CMD_MST_CTRL_SHIFT                 _MK_SHIFT_CONST(6)
+#define CMDQ_CMD_MST_CTRL_FIELD                 (_MK_MASK_CONST(0x1) << CMDQ_CMD_MST_CTRL_SHIFT)
+#define CMDQ_CMD_MST_CTRL_RANGE                 _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define CMDQ_CMD_MST_CTRL_ROW                   0
+#define CMDQ_CMD_MST_CTRL_DISABLE                       _MK_ENUM_CONST(0)
+#define CMDQ_CMD_MST_CTRL_ENABLE                        _MK_ENUM_CONST(1)
+
+//
+#define CMDQ_CMD_ECC_PTR_SHIFT                  _MK_SHIFT_CONST(5)
+#define CMDQ_CMD_ECC_PTR_FIELD                  (_MK_MASK_CONST(0x1) << CMDQ_CMD_ECC_PTR_SHIFT)
+#define CMDQ_CMD_ECC_PTR_RANGE                  _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define CMDQ_CMD_ECC_PTR_ROW                    0
+#define CMDQ_CMD_ECC_PTR_DISABLE                        _MK_ENUM_CONST(0)
+#define CMDQ_CMD_ECC_PTR_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define CMDQ_CMD_TAG_PTR_SHIFT                  _MK_SHIFT_CONST(4)
+#define CMDQ_CMD_TAG_PTR_FIELD                  (_MK_MASK_CONST(0x1) << CMDQ_CMD_TAG_PTR_SHIFT)
+#define CMDQ_CMD_TAG_PTR_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define CMDQ_CMD_TAG_PTR_ROW                    0
+#define CMDQ_CMD_TAG_PTR_DISABLE                        _MK_ENUM_CONST(0)
+#define CMDQ_CMD_TAG_PTR_ENABLE                 _MK_ENUM_CONST(1)
+
+//
+#define CMDQ_CMD_DATA_BLOCK_PTR_SHIFT                   _MK_SHIFT_CONST(3)
+#define CMDQ_CMD_DATA_BLOCK_PTR_FIELD                   (_MK_MASK_CONST(0x1) << CMDQ_CMD_DATA_BLOCK_PTR_SHIFT)
+#define CMDQ_CMD_DATA_BLOCK_PTR_RANGE                   _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define CMDQ_CMD_DATA_BLOCK_PTR_ROW                     0
+#define CMDQ_CMD_DATA_BLOCK_PTR_DISABLE                 _MK_ENUM_CONST(0)
+#define CMDQ_CMD_DATA_BLOCK_PTR_ENABLE                  _MK_ENUM_CONST(1)
+
+//
+#define CMDQ_CMD_DMA_CNFGB_SHIFT                        _MK_SHIFT_CONST(2)
+#define CMDQ_CMD_DMA_CNFGB_FIELD                        (_MK_MASK_CONST(0x1) << CMDQ_CMD_DMA_CNFGB_SHIFT)
+#define CMDQ_CMD_DMA_CNFGB_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define CMDQ_CMD_DMA_CNFGB_ROW                  0
+#define CMDQ_CMD_DMA_CNFGB_DISABLE                      _MK_ENUM_CONST(0)
+#define CMDQ_CMD_DMA_CNFGB_ENABLE                       _MK_ENUM_CONST(1)
+
+//
+#define CMDQ_CMD_DMA_CNFGA_SHIFT                        _MK_SHIFT_CONST(1)
+#define CMDQ_CMD_DMA_CNFGA_FIELD                        (_MK_MASK_CONST(0x1) << CMDQ_CMD_DMA_CNFGA_SHIFT)
+#define CMDQ_CMD_DMA_CNFGA_RANGE                        _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define CMDQ_CMD_DMA_CNFGA_ROW                  0
+#define CMDQ_CMD_DMA_CNFGA_DISABLE                      _MK_ENUM_CONST(0)
+#define CMDQ_CMD_DMA_CNFGA_ENABLE                       _MK_ENUM_CONST(1)
+
+// 
+#define CMDQ_CMD_CONFIG_SHIFT                   _MK_SHIFT_CONST(0)
+#define CMDQ_CMD_CONFIG_FIELD                   (_MK_MASK_CONST(0x1) << CMDQ_CMD_CONFIG_SHIFT)
+#define CMDQ_CMD_CONFIG_RANGE                   _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define CMDQ_CMD_CONFIG_ROW                     0
+#define CMDQ_CMD_CONFIG_DISABLE                 _MK_ENUM_CONST(0)
+#define CMDQ_CMD_CONFIG_ENABLE                  _MK_ENUM_CONST(1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARNANDFLASH_REGS(_op_) \
+_op_(NAND_COMMAND_0) \
+_op_(NAND_STATUS_0) \
+_op_(NAND_ISR_0) \
+_op_(NAND_IER_0) \
+_op_(NAND_CONFIG_0) \
+_op_(NAND_TIMING_0) \
+_op_(NAND_RESP_0) \
+_op_(NAND_TIMING2_0) \
+_op_(NAND_CMD_REG1_0) \
+_op_(NAND_CMD_REG2_0) \
+_op_(NAND_ADDR_REG1_0) \
+_op_(NAND_ADDR_REG2_0) \
+_op_(NAND_DMA_MST_CTRL_0) \
+_op_(NAND_DMA_CFG_A_0) \
+_op_(NAND_DMA_CFG_B_0) \
+_op_(NAND_FIFO_CTRL_0) \
+_op_(NAND_DATA_BLOCK_PTR_0) \
+_op_(NAND_TAG_PTR_0) \
+_op_(NAND_ECC_PTR_0) \
+_op_(NAND_DEC_STATUS_0) \
+_op_(NAND_HWSTATUS_CMD_0) \
+_op_(NAND_HWSTATUS_MASK_0) \
+_op_(NAND_LL_CONFIG_0) \
+_op_(NAND_LL_PTR_0) \
+_op_(NAND_LL_STATUS_0) \
+_op_(NAND_LOCK_CONTROL_0) \
+_op_(NAND_LOCK_STATUS_0) \
+_op_(NAND_LOCK_APER_START0_0) \
+_op_(NAND_LOCK_APER_START1_0) \
+_op_(NAND_LOCK_APER_START2_0) \
+_op_(NAND_LOCK_APER_START3_0) \
+_op_(NAND_LOCK_APER_START4_0) \
+_op_(NAND_LOCK_APER_START5_0) \
+_op_(NAND_LOCK_APER_START6_0) \
+_op_(NAND_LOCK_APER_START7_0) \
+_op_(NAND_LOCK_APER_END0_0) \
+_op_(NAND_LOCK_APER_END1_0) \
+_op_(NAND_LOCK_APER_END2_0) \
+_op_(NAND_LOCK_APER_END3_0) \
+_op_(NAND_LOCK_APER_END4_0) \
+_op_(NAND_LOCK_APER_END5_0) \
+_op_(NAND_LOCK_APER_END6_0) \
+_op_(NAND_LOCK_APER_END7_0) \
+_op_(NAND_LOCK_APER_CHIPID0_0) \
+_op_(NAND_LOCK_APER_CHIPID1_0) \
+_op_(NAND_LOCK_APER_CHIPID2_0) \
+_op_(NAND_LOCK_APER_CHIPID3_0) \
+_op_(NAND_LOCK_APER_CHIPID4_0) \
+_op_(NAND_LOCK_APER_CHIPID5_0) \
+_op_(NAND_LOCK_APER_CHIPID6_0) \
+_op_(NAND_LOCK_APER_CHIPID7_0) \
+_op_(NAND_BCH_CONFIG_0) \
+_op_(NAND_BCH_DEC_RESULT_0) \
+_op_(NAND_BCH_DEC_STATUS_BUF_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_NAND       0x00000000
+
+//
+// ARNANDFLASH REGISTER BANKS
+//
+
+#define NAND0_FIRST_REG 0x0000 // NAND_COMMAND_0
+#define NAND0_LAST_REG 0x00d4 // NAND_BCH_DEC_STATUS_BUF_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARNANDFLASH_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arowr.h b/arch/arm/mach-tegra/nv/include/ap20/arowr.h
new file mode 100644
index 000000000000..5cec2977a406
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arowr.h
@@ -0,0 +1,1675 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___AROWR_H_INC_
+#define ___AROWR_H_INC_
+#define OWR_TX_FIFO_DEPTH       32
+#define OWR_RX_FIFO_DEPTH       32
+
+// Register OWR_CONTROL_0  
+#define OWR_CONTROL_0                   _MK_ADDR_CONST(0x0)
+#define OWR_CONTROL_0_SECURE                    0x0
+#define OWR_CONTROL_0_WORD_COUNT                        0x1
+#define OWR_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define OWR_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+//Generate Reset Presence Pulse 
+//write only bit 
+//read to this register will return 0
+//bit should be programed after all the registers are programed
+#define OWR_CONTROL_0_GO_SHIFT                  _MK_SHIFT_CONST(0)
+#define OWR_CONTROL_0_GO_FIELD                  (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_GO_SHIFT)
+#define OWR_CONTROL_0_GO_RANGE                  0:0
+#define OWR_CONTROL_0_GO_WOFFSET                        0x0
+#define OWR_CONTROL_0_GO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_GO_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_GO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_GO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_GO_NO_PRESENCE_PULSE                      _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_GO_START_PRESENCE_PULSE                   _MK_ENUM_CONST(1)
+
+// when set, dq is driven to low by master before the slave does 
+// clearing this bit disables the ppm    
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_SHIFT                      _MK_SHIFT_CONST(1)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_FIELD                      (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_PRESENCE_PULSE_MASKING_SHIFT)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_RANGE                      1:1
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_WOFFSET                    0x0
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_NO_PPM                     _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_PRESENCE_PULSE_MASKING_START_PPM                  _MK_ENUM_CONST(1)
+
+// if set to 1 data transfer is done bit by bit
+// if set to 0 data transfer is done through byte
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_SHIFT                  _MK_SHIFT_CONST(2)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_FIELD                  (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_DATA_TRANSFER_MODE_SHIFT)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_RANGE                  2:2
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_WOFFSET                        0x0
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_BYTE_TRANSFER_MODE                     _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_DATA_TRANSFER_MODE_BIT_TRANSFER_MODE                      _MK_ENUM_CONST(1)
+
+// if set to 1 16bit crc is executed
+// if set to 0 8bit crc is executed
+#define OWR_CONTROL_0_CRC_16BIT_EN_SHIFT                        _MK_SHIFT_CONST(3)
+#define OWR_CONTROL_0_CRC_16BIT_EN_FIELD                        (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_CRC_16BIT_EN_SHIFT)
+#define OWR_CONTROL_0_CRC_16BIT_EN_RANGE                        3:3
+#define OWR_CONTROL_0_CRC_16BIT_EN_WOFFSET                      0x0
+#define OWR_CONTROL_0_CRC_16BIT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_CRC_16BIT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_CRC_16BIT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_CRC_16BIT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_CRC_16BIT_EN_CRC_8BIT_EN                  _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_CRC_16BIT_EN_CRC_16BIT_EN                 _MK_ENUM_CONST(1)
+
+// Transmit fifo attention level
+// 000 = 1 word, fifo req is asserted when least one word empty in the fifo
+// 001 = 2 word, fifo req is asserted when least 2 words empty in the fifo
+// etc.......
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_SHIFT                 _MK_SHIFT_CONST(4)
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_FIELD                 (_MK_MASK_CONST(0x1f) << OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_SHIFT)
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_RANGE                 8:4
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_WOFFSET                       0x0
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_TX_FIFO_ATTEN_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Receive  fifo attention level
+// 000 = 1 word, fifo req is asserted when least one word full in the fifo
+// 001 = 2 word, fifo req is asserted when least 2 words full in the fifo
+// etc.....
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_SHIFT                 _MK_SHIFT_CONST(9)
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_FIELD                 (_MK_MASK_CONST(0x1f) << OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_SHIFT)
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_RANGE                 13:9
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_WOFFSET                       0x0
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RX_FIFO_ATTEN_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//This bit is set to 1, if crc is required 
+//for read memory cmd at end of memory
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_SHIFT                      _MK_SHIFT_CONST(14)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_FIELD                      (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_RD_MEM_CRC_REQ_SHIFT)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_RANGE                      14:14
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_WOFFSET                    0x0
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_NO_CRC_READ                        _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_RD_MEM_CRC_REQ_CRC_READ                   _MK_ENUM_CONST(1)
+
+//presence pulse sample clk, master samples the data_in 
+//which should be less than or equal to (tpdl - 6) clks   
+// 6 clks are used for dglitch, 
+// if Deglitch bypassed 3 clks should be enough
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_SHIFT                 _MK_SHIFT_CONST(15)
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_FIELD                 (_MK_MASK_CONST(0xff) << OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_SHIFT)
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_RANGE                 22:15
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_WOFFSET                       0x0
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_PRESENCE_SAMPLE_CLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//read data sample window, master samples the data_in
+//which should be less than or equal to (tlow1 - 6) clks   
+// 6 clks are used for Deglitch, 
+// if Deglitch bypassed 3 clks should be enough
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_SHIFT                  _MK_SHIFT_CONST(23)
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_FIELD                  (_MK_MASK_CONST(0xf) << OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_SHIFT)
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_RANGE                  26:23
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_WOFFSET                        0x0
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_DATA_SAMPLE_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// This bit is used to bypass the deglitch logic,
+// If 1, just takes the sync output
+// If 0, looks for any glitch in the sample window for at least 1us,
+// Deglitch requires a minimum of 6 clks(2 for sync, 2 for deglitch,
+// if glitch, checks for 2 more clks, still glitch exists, err interrupt is
+// asserted and data transfer should start from first)  
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_SHIFT                     _MK_SHIFT_CONST(27)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_FIELD                     (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_BY_PASS_DGLITCH_SHIFT)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_RANGE                     27:27
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_WOFFSET                   0x0
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_START_DGLITCH                     _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_BY_PASS_DGLITCH_NO_DGLITCH                        _MK_ENUM_CONST(1)
+
+// this bit is set to 1, if transfer needs to continue on crc err
+// else on err transfer stops, 
+// and again transfer should start on setting rpp reset(go bit)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_SHIFT                     _MK_SHIFT_CONST(28)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_FIELD                     (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_BY_PASS_CRC_ERR_SHIFT)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_RANGE                     28:28
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_WOFFSET                   0x0
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_STOP_TRANSFER_ON_CRC_ERR                  _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_BY_PASS_CRC_ERR_CONTINUE_TRANSFER_ON_CRC_ERR                      _MK_ENUM_CONST(1)
+
+// if 0 no transfer is done
+// if 1 write one time slot is executed
+//This bit is a write only 
+//read to this register will return 0
+#define OWR_CONTROL_0_WR1_BIT_SHIFT                     _MK_SHIFT_CONST(29)
+#define OWR_CONTROL_0_WR1_BIT_FIELD                     (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_WR1_BIT_SHIFT)
+#define OWR_CONTROL_0_WR1_BIT_RANGE                     29:29
+#define OWR_CONTROL_0_WR1_BIT_WOFFSET                   0x0
+#define OWR_CONTROL_0_WR1_BIT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR1_BIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_WR1_BIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR1_BIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR1_BIT_NO_TRANSFER                       _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_WR1_BIT_TRANSFER_ONE                      _MK_ENUM_CONST(1)
+
+// if 0 no transfer is done
+// if 1 write zero time slot is executed
+//write only bit
+//read to this register will return 0
+#define OWR_CONTROL_0_WR0_BIT_SHIFT                     _MK_SHIFT_CONST(30)
+#define OWR_CONTROL_0_WR0_BIT_FIELD                     (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_WR0_BIT_SHIFT)
+#define OWR_CONTROL_0_WR0_BIT_RANGE                     30:30
+#define OWR_CONTROL_0_WR0_BIT_WOFFSET                   0x0
+#define OWR_CONTROL_0_WR0_BIT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR0_BIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_WR0_BIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR0_BIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_WR0_BIT_NO_TRANSFER                       _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_WR0_BIT_TRANSFER_ZERO                     _MK_ENUM_CONST(1)
+
+// if 0 no transfer is done
+// if 1 read time slot is executed
+//write only bit 
+//read to this register will return 0
+#define OWR_CONTROL_0_RD_BIT_SHIFT                      _MK_SHIFT_CONST(31)
+#define OWR_CONTROL_0_RD_BIT_FIELD                      (_MK_MASK_CONST(0x1) << OWR_CONTROL_0_RD_BIT_SHIFT)
+#define OWR_CONTROL_0_RD_BIT_RANGE                      31:31
+#define OWR_CONTROL_0_RD_BIT_WOFFSET                    0x0
+#define OWR_CONTROL_0_RD_BIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_BIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_CONTROL_0_RD_BIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_BIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_CONTROL_0_RD_BIT_NO_TRANSFER                        _MK_ENUM_CONST(0)
+#define OWR_CONTROL_0_RD_BIT_TRANSFER_READ_SLOT                 _MK_ENUM_CONST(1)
+
+
+// Register OWR_COMMAND_0  
+#define OWR_COMMAND_0                   _MK_ADDR_CONST(0x4)
+#define OWR_COMMAND_0_SECURE                    0x0
+#define OWR_COMMAND_0_WORD_COUNT                        0x1
+#define OWR_COMMAND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_COMMAND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define OWR_COMMAND_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+//1-wire ROM commands 
+#define OWR_COMMAND_0_ROM_CMD_SHIFT                     _MK_SHIFT_CONST(0)
+#define OWR_COMMAND_0_ROM_CMD_FIELD                     (_MK_MASK_CONST(0xff) << OWR_COMMAND_0_ROM_CMD_SHIFT)
+#define OWR_COMMAND_0_ROM_CMD_RANGE                     7:0
+#define OWR_COMMAND_0_ROM_CMD_WOFFSET                   0x0
+#define OWR_COMMAND_0_ROM_CMD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_ROM_CMD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define OWR_COMMAND_0_ROM_CMD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_ROM_CMD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//1-wire MEM commands 
+#define OWR_COMMAND_0_MEM_CMD_SHIFT                     _MK_SHIFT_CONST(8)
+#define OWR_COMMAND_0_MEM_CMD_FIELD                     (_MK_MASK_CONST(0xff) << OWR_COMMAND_0_MEM_CMD_SHIFT)
+#define OWR_COMMAND_0_MEM_CMD_RANGE                     15:8
+#define OWR_COMMAND_0_MEM_CMD_WOFFSET                   0x0
+#define OWR_COMMAND_0_MEM_CMD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_MEM_CMD_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define OWR_COMMAND_0_MEM_CMD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_MEM_CMD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//Eprom Starting Address[15:0] to write/read data into Eprom
+#define OWR_COMMAND_0_MEM_ADDR_SHIFT                    _MK_SHIFT_CONST(16)
+#define OWR_COMMAND_0_MEM_ADDR_FIELD                    (_MK_MASK_CONST(0xffff) << OWR_COMMAND_0_MEM_ADDR_SHIFT)
+#define OWR_COMMAND_0_MEM_ADDR_RANGE                    31:16
+#define OWR_COMMAND_0_MEM_ADDR_WOFFSET                  0x0
+#define OWR_COMMAND_0_MEM_ADDR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_MEM_ADDR_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define OWR_COMMAND_0_MEM_ADDR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_COMMAND_0_MEM_ADDR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register OWR_EPROM_0  
+#define OWR_EPROM_0                     _MK_ADDR_CONST(0x8)
+#define OWR_EPROM_0_SECURE                      0x0
+#define OWR_EPROM_0_WORD_COUNT                  0x1
+#define OWR_EPROM_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define OWR_EPROM_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define OWR_EPROM_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Num of Eprom memory bytes to transfer, 
+// Mem_Addr - Eprom end address
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_SHIFT                 _MK_SHIFT_CONST(0)
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_FIELD                 (_MK_MASK_CONST(0xffff) << OWR_EPROM_0_MEMORY_BYTES_TRANSFER_SHIFT)
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_RANGE                 15:0
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_WOFFSET                       0x0
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_MEMORY_BYTES_TRANSFER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Num of Eprom Status bytes to transfer, 
+// Mem_Addr - Status bytes end address
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_SHIFT                 _MK_SHIFT_CONST(16)
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_FIELD                 (_MK_MASK_CONST(0xffff) << OWR_EPROM_0_STATUS_BYTES_TRANSFER_SHIFT)
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_RANGE                 31:16
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_WOFFSET                       0x0
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_EPROM_0_STATUS_BYTES_TRANSFER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register OWR_WR_RD_TCTL_0  
+#define OWR_WR_RD_TCTL_0                        _MK_ADDR_CONST(0xc)
+#define OWR_WR_RD_TCTL_0_SECURE                         0x0
+#define OWR_WR_RD_TCTL_0_WORD_COUNT                     0x1
+#define OWR_WR_RD_TCTL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_RESET_MASK                     _MK_MASK_CONST(0x3fffffff)
+#define OWR_WR_RD_TCTL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_READ_MASK                      _MK_MASK_CONST(0x3fffffff)
+#define OWR_WR_RD_TCTL_0_WRITE_MASK                     _MK_MASK_CONST(0x3fffffff)
+// Active time slot for write or read data,
+// Tslot = N+1 owr clks,    Range = 60 <= tslot < 120
+#define OWR_WR_RD_TCTL_0_TSLOT_SHIFT                    _MK_SHIFT_CONST(0)
+#define OWR_WR_RD_TCTL_0_TSLOT_FIELD                    (_MK_MASK_CONST(0x7f) << OWR_WR_RD_TCTL_0_TSLOT_SHIFT)
+#define OWR_WR_RD_TCTL_0_TSLOT_RANGE                    6:0
+#define OWR_WR_RD_TCTL_0_TSLOT_WOFFSET                  0x0
+#define OWR_WR_RD_TCTL_0_TSLOT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TSLOT_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define OWR_WR_RD_TCTL_0_TSLOT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TSLOT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Write one time Low, or TLOWR both are same
+// Tlow1 = N+1 owr clks,    Range = 1 <= tlow1 < 15
+// TlowR = N+1 owr clks,    Range = 1 <= tlowR < 15
+#define OWR_WR_RD_TCTL_0_TLOW1_SHIFT                    _MK_SHIFT_CONST(7)
+#define OWR_WR_RD_TCTL_0_TLOW1_FIELD                    (_MK_MASK_CONST(0xf) << OWR_WR_RD_TCTL_0_TLOW1_SHIFT)
+#define OWR_WR_RD_TCTL_0_TLOW1_RANGE                    10:7
+#define OWR_WR_RD_TCTL_0_TLOW1_WOFFSET                  0x0
+#define OWR_WR_RD_TCTL_0_TLOW1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TLOW1_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define OWR_WR_RD_TCTL_0_TLOW1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TLOW1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Write Zero time Low,
+// Tlow0 = N+1 owr clks,    Range = 60 <= tlow0 < tslot < 120
+#define OWR_WR_RD_TCTL_0_TLOW0_SHIFT                    _MK_SHIFT_CONST(11)
+#define OWR_WR_RD_TCTL_0_TLOW0_FIELD                    (_MK_MASK_CONST(0x7f) << OWR_WR_RD_TCTL_0_TLOW0_SHIFT)
+#define OWR_WR_RD_TCTL_0_TLOW0_RANGE                    17:11
+#define OWR_WR_RD_TCTL_0_TLOW0_WOFFSET                  0x0
+#define OWR_WR_RD_TCTL_0_TLOW0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TLOW0_DEFAULT_MASK                     _MK_MASK_CONST(0x7f)
+#define OWR_WR_RD_TCTL_0_TLOW0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TLOW0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Read data valid time,
+// Trdv  = N+1 owr clks,    Range = Exactly 15
+#define OWR_WR_RD_TCTL_0_TRDV_SHIFT                     _MK_SHIFT_CONST(18)
+#define OWR_WR_RD_TCTL_0_TRDV_FIELD                     (_MK_MASK_CONST(0xf) << OWR_WR_RD_TCTL_0_TRDV_SHIFT)
+#define OWR_WR_RD_TCTL_0_TRDV_RANGE                     21:18
+#define OWR_WR_RD_TCTL_0_TRDV_WOFFSET                   0x0
+#define OWR_WR_RD_TCTL_0_TRDV_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TRDV_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define OWR_WR_RD_TCTL_0_TRDV_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TRDV_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Release 1-wire Time,
+// Trelease = N owr clks,   Range = 0 <= trelease < 45
+#define OWR_WR_RD_TCTL_0_TRELEASE_SHIFT                 _MK_SHIFT_CONST(22)
+#define OWR_WR_RD_TCTL_0_TRELEASE_FIELD                 (_MK_MASK_CONST(0x3f) << OWR_WR_RD_TCTL_0_TRELEASE_SHIFT)
+#define OWR_WR_RD_TCTL_0_TRELEASE_RANGE                 27:22
+#define OWR_WR_RD_TCTL_0_TRELEASE_WOFFSET                       0x0
+#define OWR_WR_RD_TCTL_0_TRELEASE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TRELEASE_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define OWR_WR_RD_TCTL_0_TRELEASE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TRELEASE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Read Data Setup,
+// Tsu = N owr clks,        Range = tsu < 1 
+#define OWR_WR_RD_TCTL_0_TSU_SHIFT                      _MK_SHIFT_CONST(28)
+#define OWR_WR_RD_TCTL_0_TSU_FIELD                      (_MK_MASK_CONST(0x3) << OWR_WR_RD_TCTL_0_TSU_SHIFT)
+#define OWR_WR_RD_TCTL_0_TSU_RANGE                      29:28
+#define OWR_WR_RD_TCTL_0_TSU_WOFFSET                    0x0
+#define OWR_WR_RD_TCTL_0_TSU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TSU_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define OWR_WR_RD_TCTL_0_TSU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_WR_RD_TCTL_0_TSU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register OWR_RST_PRESENCE_TCTL_0  
+#define OWR_RST_PRESENCE_TCTL_0                 _MK_ADDR_CONST(0x10)
+#define OWR_RST_PRESENCE_TCTL_0_SECURE                  0x0
+#define OWR_RST_PRESENCE_TCTL_0_WORD_COUNT                      0x1
+#define OWR_RST_PRESENCE_TCTL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define OWR_RST_PRESENCE_TCTL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define OWR_RST_PRESENCE_TCTL_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// RESET_TIME_HIGH,
+// Trsth = N+1 owr clks, Range = 480 <= trsth < infinity  
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_SHIFT                     _MK_SHIFT_CONST(0)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_FIELD                     (_MK_MASK_CONST(0x1ff) << OWR_RST_PRESENCE_TCTL_0_TRSTH_SHIFT)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_RANGE                     8:0
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_WOFFSET                   0x0
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// RESET_TIME_LOW 
+// Trstl = N+1 owr clks, Range = 480 <= trstl < infinity  
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_SHIFT                     _MK_SHIFT_CONST(9)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_FIELD                     (_MK_MASK_CONST(0x1ff) << OWR_RST_PRESENCE_TCTL_0_TRSTL_SHIFT)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_RANGE                     17:9
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_WOFFSET                   0x0
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TRSTL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// PRESENCE_DETECT_HIGH  
+// Tpdh = N+1 owr clks,  Range = 15  <= tpdh < 60  
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_SHIFT                      _MK_SHIFT_CONST(18)
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_FIELD                      (_MK_MASK_CONST(0x3f) << OWR_RST_PRESENCE_TCTL_0_TPDH_SHIFT)
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_RANGE                      23:18
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_WOFFSET                    0x0
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TPDH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// PRESENCE_DETECT_LOW 
+// Tpdl = N owr clks,    Range = 60  <= tpdl < 240  
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_SHIFT                      _MK_SHIFT_CONST(24)
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_FIELD                      (_MK_MASK_CONST(0xff) << OWR_RST_PRESENCE_TCTL_0_TPDL_SHIFT)
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_RANGE                      31:24
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_WOFFSET                    0x0
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_RST_PRESENCE_TCTL_0_TPDL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register OWR_PPM_CORRECTION_TCTL_0  
+#define OWR_PPM_CORRECTION_TCTL_0                       _MK_ADDR_CONST(0x14)
+#define OWR_PPM_CORRECTION_TCTL_0_SECURE                        0x0
+#define OWR_PPM_CORRECTION_TCTL_0_WORD_COUNT                    0x1
+#define OWR_PPM_CORRECTION_TCTL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define OWR_PPM_CORRECTION_TCTL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define OWR_PPM_CORRECTION_TCTL_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
+// PRESENCE PULSE MASK START
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_SHIFT                   _MK_SHIFT_CONST(0)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_FIELD                   (_MK_MASK_CONST(0x3f) << OWR_PPM_CORRECTION_TCTL_0_TPPM1_SHIFT)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_RANGE                   5:0
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_WOFFSET                 0x0
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// PRESENCE PULSE MASK STOP 
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_SHIFT                   _MK_SHIFT_CONST(6)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_FIELD                   (_MK_MASK_CONST(0x3ff) << OWR_PPM_CORRECTION_TCTL_0_TPPM2_SHIFT)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_RANGE                   15:6
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_WOFFSET                 0x0
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_DEFAULT_MASK                    _MK_MASK_CONST(0x3ff)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_PPM_CORRECTION_TCTL_0_TPPM2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register OWR_PROG_PULSE_TCTL_0  
+#define OWR_PROG_PULSE_TCTL_0                   _MK_ADDR_CONST(0x18)
+#define OWR_PROG_PULSE_TCTL_0_SECURE                    0x0
+#define OWR_PROG_PULSE_TCTL_0_WORD_COUNT                        0x1
+#define OWR_PROG_PULSE_TCTL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_PROG_PULSE_TCTL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define OWR_PROG_PULSE_TCTL_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Delay to program 
+// Tpd = N+1 owr clks, Range = > 5  
+#define OWR_PROG_PULSE_TCTL_0_TPD_SHIFT                 _MK_SHIFT_CONST(0)
+#define OWR_PROG_PULSE_TCTL_0_TPD_FIELD                 (_MK_MASK_CONST(0xf) << OWR_PROG_PULSE_TCTL_0_TPD_SHIFT)
+#define OWR_PROG_PULSE_TCTL_0_TPD_RANGE                 3:0
+#define OWR_PROG_PULSE_TCTL_0_TPD_WOFFSET                       0x0
+#define OWR_PROG_PULSE_TCTL_0_TPD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TPD_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define OWR_PROG_PULSE_TCTL_0_TPD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TPD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Delay to verify
+// Tdv = N owr clks,   Range = > 5       
+#define OWR_PROG_PULSE_TCTL_0_TDV_SHIFT                 _MK_SHIFT_CONST(4)
+#define OWR_PROG_PULSE_TCTL_0_TDV_FIELD                 (_MK_MASK_CONST(0xf) << OWR_PROG_PULSE_TCTL_0_TDV_SHIFT)
+#define OWR_PROG_PULSE_TCTL_0_TDV_RANGE                 7:4
+#define OWR_PROG_PULSE_TCTL_0_TDV_WOFFSET                       0x0
+#define OWR_PROG_PULSE_TCTL_0_TDV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TDV_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define OWR_PROG_PULSE_TCTL_0_TDV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TDV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Program Voltage Rise Time
+// Trp = N owr clks    Range = 0.5 to 5 
+#define OWR_PROG_PULSE_TCTL_0_TRP_SHIFT                 _MK_SHIFT_CONST(8)
+#define OWR_PROG_PULSE_TCTL_0_TRP_FIELD                 (_MK_MASK_CONST(0xf) << OWR_PROG_PULSE_TCTL_0_TRP_SHIFT)
+#define OWR_PROG_PULSE_TCTL_0_TRP_RANGE                 11:8
+#define OWR_PROG_PULSE_TCTL_0_TRP_WOFFSET                       0x0
+#define OWR_PROG_PULSE_TCTL_0_TRP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TRP_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define OWR_PROG_PULSE_TCTL_0_TRP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TRP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Program Voltage Fall Time
+// Tfp = N owr clks    Range = 0.5 to 5 
+#define OWR_PROG_PULSE_TCTL_0_TFP_SHIFT                 _MK_SHIFT_CONST(12)
+#define OWR_PROG_PULSE_TCTL_0_TFP_FIELD                 (_MK_MASK_CONST(0xf) << OWR_PROG_PULSE_TCTL_0_TFP_SHIFT)
+#define OWR_PROG_PULSE_TCTL_0_TFP_RANGE                 15:12
+#define OWR_PROG_PULSE_TCTL_0_TFP_WOFFSET                       0x0
+#define OWR_PROG_PULSE_TCTL_0_TFP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TFP_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define OWR_PROG_PULSE_TCTL_0_TFP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TFP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Program Pulse Width
+// Tpp = N owr clks    Range = 480 to 5000 
+#define OWR_PROG_PULSE_TCTL_0_TPP_SHIFT                 _MK_SHIFT_CONST(16)
+#define OWR_PROG_PULSE_TCTL_0_TPP_FIELD                 (_MK_MASK_CONST(0xffff) << OWR_PROG_PULSE_TCTL_0_TPP_SHIFT)
+#define OWR_PROG_PULSE_TCTL_0_TPP_RANGE                 31:16
+#define OWR_PROG_PULSE_TCTL_0_TPP_WOFFSET                       0x0
+#define OWR_PROG_PULSE_TCTL_0_TPP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TPP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define OWR_PROG_PULSE_TCTL_0_TPP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_PROG_PULSE_TCTL_0_TPP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register OWR_READ_ROM0_0  
+#define OWR_READ_ROM0_0                 _MK_ADDR_CONST(0x1c)
+#define OWR_READ_ROM0_0_SECURE                  0x0
+#define OWR_READ_ROM0_0_WORD_COUNT                      0x1
+#define OWR_READ_ROM0_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define OWR_READ_ROM0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define OWR_READ_ROM0_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// Reads the 8 bit family code of ROM 
+#define OWR_READ_ROM0_0_FAMILY_CODE_SHIFT                       _MK_SHIFT_CONST(0)
+#define OWR_READ_ROM0_0_FAMILY_CODE_FIELD                       (_MK_MASK_CONST(0xff) << OWR_READ_ROM0_0_FAMILY_CODE_SHIFT)
+#define OWR_READ_ROM0_0_FAMILY_CODE_RANGE                       7:0
+#define OWR_READ_ROM0_0_FAMILY_CODE_WOFFSET                     0x0
+#define OWR_READ_ROM0_0_FAMILY_CODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_FAMILY_CODE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define OWR_READ_ROM0_0_FAMILY_CODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_FAMILY_CODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Reads the first 24 bits of rom  serial number
+#define OWR_READ_ROM0_0_SERIAL_NUM0_SHIFT                       _MK_SHIFT_CONST(8)
+#define OWR_READ_ROM0_0_SERIAL_NUM0_FIELD                       (_MK_MASK_CONST(0xffffff) << OWR_READ_ROM0_0_SERIAL_NUM0_SHIFT)
+#define OWR_READ_ROM0_0_SERIAL_NUM0_RANGE                       31:8
+#define OWR_READ_ROM0_0_SERIAL_NUM0_WOFFSET                     0x0
+#define OWR_READ_ROM0_0_SERIAL_NUM0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_SERIAL_NUM0_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define OWR_READ_ROM0_0_SERIAL_NUM0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM0_0_SERIAL_NUM0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register OWR_READ_ROM1_0  
+#define OWR_READ_ROM1_0                 _MK_ADDR_CONST(0x20)
+#define OWR_READ_ROM1_0_SECURE                  0x0
+#define OWR_READ_ROM1_0_WORD_COUNT                      0x1
+#define OWR_READ_ROM1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define OWR_READ_ROM1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define OWR_READ_ROM1_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// Reads the next 24 bits of rom serial number
+#define OWR_READ_ROM1_0_SERIAL_NUM1_SHIFT                       _MK_SHIFT_CONST(0)
+#define OWR_READ_ROM1_0_SERIAL_NUM1_FIELD                       (_MK_MASK_CONST(0xffffff) << OWR_READ_ROM1_0_SERIAL_NUM1_SHIFT)
+#define OWR_READ_ROM1_0_SERIAL_NUM1_RANGE                       23:0
+#define OWR_READ_ROM1_0_SERIAL_NUM1_WOFFSET                     0x0
+#define OWR_READ_ROM1_0_SERIAL_NUM1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_SERIAL_NUM1_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define OWR_READ_ROM1_0_SERIAL_NUM1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_SERIAL_NUM1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Reads the 8 bit CRC code of ROM
+#define OWR_READ_ROM1_0_CRC_BYTE_SHIFT                  _MK_SHIFT_CONST(24)
+#define OWR_READ_ROM1_0_CRC_BYTE_FIELD                  (_MK_MASK_CONST(0xff) << OWR_READ_ROM1_0_CRC_BYTE_SHIFT)
+#define OWR_READ_ROM1_0_CRC_BYTE_RANGE                  31:24
+#define OWR_READ_ROM1_0_CRC_BYTE_WOFFSET                        0x0
+#define OWR_READ_ROM1_0_CRC_BYTE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_CRC_BYTE_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define OWR_READ_ROM1_0_CRC_BYTE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_READ_ROM1_0_CRC_BYTE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register OWR_INTR_MASK_0  
+#define OWR_INTR_MASK_0                 _MK_ADDR_CONST(0x24)
+#define OWR_INTR_MASK_0_SECURE                  0x0
+#define OWR_INTR_MASK_0_WORD_COUNT                      0x1
+#define OWR_INTR_MASK_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RESET_MASK                      _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_MASK_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_READ_MASK                       _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_MASK_0_WRITE_MASK                      _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_SHIFT                       _MK_SHIFT_CONST(0)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_RANGE                       0:0
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_WOFFSET                     0x0
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_PRESENCE_ERR_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_SHIFT                    _MK_SHIFT_CONST(1)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_CRC_ERR_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_RANGE                    1:1
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_CRC_ERR_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_SHIFT                 _MK_SHIFT_CONST(2)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_RANGE                 2:2
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_WOFFSET                       0x0
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_MEM_WR_ERR_INT_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_SHIFT                    _MK_SHIFT_CONST(3)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_ERR_CMD_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_RANGE                    3:3
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_ERR_CMD_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_SHIFT                 _MK_SHIFT_CONST(4)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_RESET_DONE_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_RANGE                 4:4
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_WOFFSET                       0x0
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_RESET_DONE_INT_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_SHIFT                      _MK_SHIFT_CONST(5)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_RANGE                      5:5
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_WOFFSET                    0x0
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_PRESENCE_DONE_INT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_SHIFT                       _MK_SHIFT_CONST(6)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_RANGE                       6:6
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_WOFFSET                     0x0
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_ROM_CMD_DONE_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_SHIFT                       _MK_SHIFT_CONST(7)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_RANGE                       7:7
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_WOFFSET                     0x0
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_MEM_CMD_DONE_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_SHIFT                    _MK_SHIFT_CONST(8)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_TXF_OVF_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_RANGE                    8:8
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_TXF_OVF_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_SHIFT                    _MK_SHIFT_CONST(9)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_RXF_UNR_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_RANGE                    9:9
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_RXF_UNR_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_SHIFT                    _MK_SHIFT_CONST(10)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_DGLITCH_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_RANGE                    10:10
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_DGLITCH_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_SHIFT                    _MK_SHIFT_CONST(11)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_RANGE                    11:11
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_TXFIFO_DATA_REQ_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_SHIFT                    _MK_SHIFT_CONST(12)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_RANGE                    12:12
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_WOFFSET                  0x0
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_RXFIFO_DATA_REQ_INT_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_SHIFT                  _MK_SHIFT_CONST(13)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_SHIFT)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_RANGE                  13:13
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_WOFFSET                        0x0
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define OWR_INTR_MASK_0_BIT_TRANSFER_DONE_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register OWR_INTR_STATUS_0  
+#define OWR_INTR_STATUS_0                       _MK_ADDR_CONST(0x28)
+#define OWR_INTR_STATUS_0_SECURE                        0x0
+#define OWR_INTR_STATUS_0_WORD_COUNT                    0x1
+#define OWR_INTR_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x27ff)
+// Presence ERROR. This bit is set when device presence not found  
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_SHIFT                    _MK_SHIFT_CONST(0)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_PRESENCE_ERR_SHIFT)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_RANGE                    0:0
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_WOFFSET                  0x0
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_SLAVE_DETECTED                   _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_PRESENCE_ERR_NO_SLAVE_DETECTED                        _MK_ENUM_CONST(1)
+
+// CRC ERROR: Indicates the received data is correct or not
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_CRC_ERR_SHIFT                 _MK_SHIFT_CONST(1)
+#define OWR_INTR_STATUS_0_CRC_ERR_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_CRC_ERR_SHIFT)
+#define OWR_INTR_STATUS_0_CRC_ERR_RANGE                 1:1
+#define OWR_INTR_STATUS_0_CRC_ERR_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_CRC_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_CRC_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_CRC_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_CRC_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_CRC_ERR_N0_ERROR                      _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_CRC_ERR_ERROR                 _MK_ENUM_CONST(1)
+
+// MEM WR ERROR: Indicates the received data from eprom is correct or not
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_SHIFT                      _MK_SHIFT_CONST(2)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_MEM_WR_ERR_SHIFT)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_RANGE                      2:2
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_WOFFSET                    0x0
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_N0_ERROR                   _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_MEM_WR_ERR_ERROR                      _MK_ENUM_CONST(1)
+
+// ERROR CMD:Indicates error command written in the register
+// It should be ignored when transfer is in single bit mode 
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_ERR_CMD_SHIFT                 _MK_SHIFT_CONST(3)
+#define OWR_INTR_STATUS_0_ERR_CMD_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_ERR_CMD_SHIFT)
+#define OWR_INTR_STATUS_0_ERR_CMD_RANGE                 3:3
+#define OWR_INTR_STATUS_0_ERR_CMD_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_ERR_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ERR_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_ERR_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ERR_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ERR_CMD_CORRECT_CMD                   _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_ERR_CMD_ERROR_CMD                     _MK_ENUM_CONST(1)
+
+// This indicates the master has send the reset, then waits for presence
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_RESET_DONE_SHIFT                      _MK_SHIFT_CONST(4)
+#define OWR_INTR_STATUS_0_RESET_DONE_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_RESET_DONE_SHIFT)
+#define OWR_INTR_STATUS_0_RESET_DONE_RANGE                      4:4
+#define OWR_INTR_STATUS_0_RESET_DONE_WOFFSET                    0x0
+#define OWR_INTR_STATUS_0_RESET_DONE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RESET_DONE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_RESET_DONE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RESET_DONE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RESET_DONE_NOT_DONE                   _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_RESET_DONE_DONE                       _MK_ENUM_CONST(1)
+
+// This indicates the presence done, master has detected the device
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_SHIFT                   _MK_SHIFT_CONST(5)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_FIELD                   (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_PRESENCE_DONE_SHIFT)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_RANGE                   5:5
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_WOFFSET                 0x0
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_NOT_DONE                        _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_PRESENCE_DONE_DONE                    _MK_ENUM_CONST(1)
+
+// This indicates master has received the rom data from battery
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_SHIFT                    _MK_SHIFT_CONST(6)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_ROM_CMD_DONE_SHIFT)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_RANGE                    6:6
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_WOFFSET                  0x0
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_NOT_DONE                 _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_ROM_CMD_DONE_DONE                     _MK_ENUM_CONST(1)
+
+// This Indicates the master has written data into eprom or data received
+// from eprom without any error 
+// Software writes a 1 to clear it. 
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_SHIFT                    _MK_SHIFT_CONST(7)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_MEM_CMD_DONE_SHIFT)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_RANGE                    7:7
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_WOFFSET                  0x0
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_NOT_DONE                 _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_MEM_CMD_DONE_DONE                     _MK_ENUM_CONST(1)
+
+// TX FIFO Overflow: RO.  This bit is set to 1 whenever software tries 
+// to write to a full TX FIFO. 
+// Software writes a 1 to clear this bit. 
+#define OWR_INTR_STATUS_0_TXF_OVF_SHIFT                 _MK_SHIFT_CONST(8)
+#define OWR_INTR_STATUS_0_TXF_OVF_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_TXF_OVF_SHIFT)
+#define OWR_INTR_STATUS_0_TXF_OVF_RANGE                 8:8
+#define OWR_INTR_STATUS_0_TXF_OVF_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_TXF_OVF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXF_OVF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_TXF_OVF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXF_OVF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXF_OVF_NOT_EMPTY                     _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_TXF_OVF_EMPTY                 _MK_ENUM_CONST(1)
+
+// RX FIFO Under run: RO.  This bit is set to 1 whenever software tries to
+// read from an empty RX FIFO. 
+// Software writes a 1 to clear this bit. 
+#define OWR_INTR_STATUS_0_RXF_UNR_SHIFT                 _MK_SHIFT_CONST(9)
+#define OWR_INTR_STATUS_0_RXF_UNR_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_RXF_UNR_SHIFT)
+#define OWR_INTR_STATUS_0_RXF_UNR_RANGE                 9:9
+#define OWR_INTR_STATUS_0_RXF_UNR_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_RXF_UNR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXF_UNR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_RXF_UNR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXF_UNR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXF_UNR_NOT_EMPTY                     _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_RXF_UNR_EMPTY                 _MK_ENUM_CONST(1)
+
+// This bit is set when data is not stable for at least 1us,
+// Software writes a 1 to clear this bit. 
+// if deglitch detected data transfer should start from 1st. 
+#define OWR_INTR_STATUS_0_DGLITCH_SHIFT                 _MK_SHIFT_CONST(10)
+#define OWR_INTR_STATUS_0_DGLITCH_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_DGLITCH_SHIFT)
+#define OWR_INTR_STATUS_0_DGLITCH_RANGE                 10:10
+#define OWR_INTR_STATUS_0_DGLITCH_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_DGLITCH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_DGLITCH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_DGLITCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_DGLITCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_DGLITCH_DGLITCH_NOT_DETECTED                  _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_DGLITCH_DGLITCH_DETECTED                      _MK_ENUM_CONST(1)
+
+// TX FIFO data req
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_SHIFT                 _MK_SHIFT_CONST(11)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_SHIFT)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_RANGE                 11:11
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_TX_NOT_RDY                    _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_TXFIFO_DATA_REQ_TX_RDY                        _MK_ENUM_CONST(1)
+
+// RX FIFO data req  
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_SHIFT                 _MK_SHIFT_CONST(12)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_SHIFT)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_RANGE                 12:12
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_WOFFSET                       0x0
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_RX_NOT_RDY                    _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_RXFIFO_DATA_REQ_RX_RDY                        _MK_ENUM_CONST(1)
+
+// This bit is set when transfer of each bit done
+// this is set on in one bit transfer mode
+// software writes 1 to clear this bit
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_SHIFT                       _MK_SHIFT_CONST(13)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_SHIFT)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_RANGE                       13:13
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_WOFFSET                     0x0
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_NOT_DONE                    _MK_ENUM_CONST(0)
+#define OWR_INTR_STATUS_0_BIT_TRANSFER_DONE_DONE                        _MK_ENUM_CONST(1)
+
+
+// Register OWR_INTR_SOURCE_0  
+#define OWR_INTR_SOURCE_0                       _MK_ADDR_CONST(0x2c)
+#define OWR_INTR_SOURCE_0_SECURE                        0x0
+#define OWR_INTR_SOURCE_0_WORD_COUNT                    0x1
+#define OWR_INTR_SOURCE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RESET_MASK                    _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_SOURCE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_READ_MASK                     _MK_MASK_CONST(0x3fff)
+#define OWR_INTR_SOURCE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_SHIFT                    _MK_SHIFT_CONST(0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_PRESENCE_ERR_SHIFT)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_RANGE                    0:0
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_WOFFSET                  0x0
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_SLAVE_DETECTED                   _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_PRESENCE_ERR_NO_SLAVE_DETECTED                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_CRC_ERR_SHIFT                 _MK_SHIFT_CONST(1)
+#define OWR_INTR_SOURCE_0_CRC_ERR_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_CRC_ERR_SHIFT)
+#define OWR_INTR_SOURCE_0_CRC_ERR_RANGE                 1:1
+#define OWR_INTR_SOURCE_0_CRC_ERR_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_CRC_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_CRC_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_CRC_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_CRC_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_CRC_ERR_N0_ERROR                      _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_CRC_ERR_ERROR                 _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_SHIFT                      _MK_SHIFT_CONST(2)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_MEM_WR_ERR_SHIFT)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_RANGE                      2:2
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_WOFFSET                    0x0
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_N0_ERROR                   _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_MEM_WR_ERR_ERROR                      _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_ERR_CMD_SHIFT                 _MK_SHIFT_CONST(3)
+#define OWR_INTR_SOURCE_0_ERR_CMD_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_ERR_CMD_SHIFT)
+#define OWR_INTR_SOURCE_0_ERR_CMD_RANGE                 3:3
+#define OWR_INTR_SOURCE_0_ERR_CMD_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_ERR_CMD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ERR_CMD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_ERR_CMD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ERR_CMD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ERR_CMD_CORRECT_CMD                   _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_ERR_CMD_ERROR_CMD                     _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_RESET_DONE_SHIFT                      _MK_SHIFT_CONST(4)
+#define OWR_INTR_SOURCE_0_RESET_DONE_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_RESET_DONE_SHIFT)
+#define OWR_INTR_SOURCE_0_RESET_DONE_RANGE                      4:4
+#define OWR_INTR_SOURCE_0_RESET_DONE_WOFFSET                    0x0
+#define OWR_INTR_SOURCE_0_RESET_DONE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RESET_DONE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_RESET_DONE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RESET_DONE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RESET_DONE_NOT_DONE                   _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_RESET_DONE_DONE                       _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_SHIFT                   _MK_SHIFT_CONST(5)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_FIELD                   (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_PRESENCE_DONE_SHIFT)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_RANGE                   5:5
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_WOFFSET                 0x0
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_NOT_DONE                        _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_PRESENCE_DONE_DONE                    _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_SHIFT                    _MK_SHIFT_CONST(6)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_ROM_CMD_DONE_SHIFT)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_RANGE                    6:6
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_WOFFSET                  0x0
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_NOT_DONE                 _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_ROM_CMD_DONE_DONE                     _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_SHIFT                    _MK_SHIFT_CONST(7)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_MEM_CMD_DONE_SHIFT)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_RANGE                    7:7
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_WOFFSET                  0x0
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_NOT_DONE                 _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_MEM_CMD_DONE_DONE                     _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_TXF_OVF_SHIFT                 _MK_SHIFT_CONST(8)
+#define OWR_INTR_SOURCE_0_TXF_OVF_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_TXF_OVF_SHIFT)
+#define OWR_INTR_SOURCE_0_TXF_OVF_RANGE                 8:8
+#define OWR_INTR_SOURCE_0_TXF_OVF_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_TXF_OVF_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXF_OVF_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_TXF_OVF_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXF_OVF_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXF_OVF_NOT_EMPTY                     _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_TXF_OVF_EMPTY                 _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_RXF_UNR_SHIFT                 _MK_SHIFT_CONST(9)
+#define OWR_INTR_SOURCE_0_RXF_UNR_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_RXF_UNR_SHIFT)
+#define OWR_INTR_SOURCE_0_RXF_UNR_RANGE                 9:9
+#define OWR_INTR_SOURCE_0_RXF_UNR_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_RXF_UNR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXF_UNR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_RXF_UNR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXF_UNR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXF_UNR_NOT_EMPTY                     _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_RXF_UNR_EMPTY                 _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_DGLITCH_SHIFT                 _MK_SHIFT_CONST(10)
+#define OWR_INTR_SOURCE_0_DGLITCH_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_DGLITCH_SHIFT)
+#define OWR_INTR_SOURCE_0_DGLITCH_RANGE                 10:10
+#define OWR_INTR_SOURCE_0_DGLITCH_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_DGLITCH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_DGLITCH_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_DGLITCH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_DGLITCH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_DGLITCH_DGLITCH_NOT_DETECTED                  _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_DGLITCH_DGLITCH_DETECTED                      _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_SHIFT                 _MK_SHIFT_CONST(11)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_SHIFT)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_RANGE                 11:11
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_TX_NOT_RDY                    _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_TXFIFO_DATA_REQ_TX_RDY                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_SHIFT                 _MK_SHIFT_CONST(12)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_SHIFT)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_RANGE                 12:12
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_WOFFSET                       0x0
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_RX_NOT_RDY                    _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_RXFIFO_DATA_REQ_RX_RDY                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_SHIFT                       _MK_SHIFT_CONST(13)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_SHIFT)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_RANGE                       13:13
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_WOFFSET                     0x0
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_NOT_DONE                    _MK_ENUM_CONST(0)
+#define OWR_INTR_SOURCE_0_BIT_TRANSFER_DONE_DONE                        _MK_ENUM_CONST(1)
+
+
+// Register OWR_INTR_SET_0  
+#define OWR_INTR_SET_0                  _MK_ADDR_CONST(0x30)
+#define OWR_INTR_SET_0_SECURE                   0x0
+#define OWR_INTR_SET_0_WORD_COUNT                       0x1
+#define OWR_INTR_SET_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RESET_MASK                       _MK_MASK_CONST(0x27ff)
+#define OWR_INTR_SET_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_READ_MASK                        _MK_MASK_CONST(0x27ff)
+#define OWR_INTR_SET_0_WRITE_MASK                       _MK_MASK_CONST(0x27ff)
+#define OWR_INTR_SET_0_PRESENCE_ERR_SHIFT                       _MK_SHIFT_CONST(0)
+#define OWR_INTR_SET_0_PRESENCE_ERR_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_PRESENCE_ERR_SHIFT)
+#define OWR_INTR_SET_0_PRESENCE_ERR_RANGE                       0:0
+#define OWR_INTR_SET_0_PRESENCE_ERR_WOFFSET                     0x0
+#define OWR_INTR_SET_0_PRESENCE_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_PRESENCE_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_ERR_SLAVE_DETECTED                      _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_PRESENCE_ERR_NO_SLAVE_DETECTED                   _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_CRC_ERR_SHIFT                    _MK_SHIFT_CONST(1)
+#define OWR_INTR_SET_0_CRC_ERR_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_CRC_ERR_SHIFT)
+#define OWR_INTR_SET_0_CRC_ERR_RANGE                    1:1
+#define OWR_INTR_SET_0_CRC_ERR_WOFFSET                  0x0
+#define OWR_INTR_SET_0_CRC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_CRC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_CRC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_CRC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_CRC_ERR_N0_ERROR                 _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_CRC_ERR_ERROR                    _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_MEM_WR_ERR_SHIFT                 _MK_SHIFT_CONST(2)
+#define OWR_INTR_SET_0_MEM_WR_ERR_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_MEM_WR_ERR_SHIFT)
+#define OWR_INTR_SET_0_MEM_WR_ERR_RANGE                 2:2
+#define OWR_INTR_SET_0_MEM_WR_ERR_WOFFSET                       0x0
+#define OWR_INTR_SET_0_MEM_WR_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_WR_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_MEM_WR_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_WR_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_WR_ERR_N0_ERROR                      _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_MEM_WR_ERR_ERROR                 _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_ERR_CMD_SHIFT                    _MK_SHIFT_CONST(3)
+#define OWR_INTR_SET_0_ERR_CMD_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_ERR_CMD_SHIFT)
+#define OWR_INTR_SET_0_ERR_CMD_RANGE                    3:3
+#define OWR_INTR_SET_0_ERR_CMD_WOFFSET                  0x0
+#define OWR_INTR_SET_0_ERR_CMD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ERR_CMD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_ERR_CMD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ERR_CMD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ERR_CMD_CORRECT_CMD                      _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_ERR_CMD_ERROR_CMD                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_RESET_DONE_SHIFT                 _MK_SHIFT_CONST(4)
+#define OWR_INTR_SET_0_RESET_DONE_FIELD                 (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_RESET_DONE_SHIFT)
+#define OWR_INTR_SET_0_RESET_DONE_RANGE                 4:4
+#define OWR_INTR_SET_0_RESET_DONE_WOFFSET                       0x0
+#define OWR_INTR_SET_0_RESET_DONE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RESET_DONE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_RESET_DONE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RESET_DONE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RESET_DONE_NOT_DONE                      _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_RESET_DONE_DONE                  _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_PRESENCE_DONE_SHIFT                      _MK_SHIFT_CONST(5)
+#define OWR_INTR_SET_0_PRESENCE_DONE_FIELD                      (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_PRESENCE_DONE_SHIFT)
+#define OWR_INTR_SET_0_PRESENCE_DONE_RANGE                      5:5
+#define OWR_INTR_SET_0_PRESENCE_DONE_WOFFSET                    0x0
+#define OWR_INTR_SET_0_PRESENCE_DONE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_DONE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_PRESENCE_DONE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_DONE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_PRESENCE_DONE_NOT_DONE                   _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_PRESENCE_DONE_DONE                       _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_ROM_CMD_DONE_SHIFT                       _MK_SHIFT_CONST(6)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_ROM_CMD_DONE_SHIFT)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_RANGE                       6:6
+#define OWR_INTR_SET_0_ROM_CMD_DONE_WOFFSET                     0x0
+#define OWR_INTR_SET_0_ROM_CMD_DONE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_NOT_DONE                    _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_ROM_CMD_DONE_DONE                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_MEM_CMD_DONE_SHIFT                       _MK_SHIFT_CONST(7)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_FIELD                       (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_MEM_CMD_DONE_SHIFT)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_RANGE                       7:7
+#define OWR_INTR_SET_0_MEM_CMD_DONE_WOFFSET                     0x0
+#define OWR_INTR_SET_0_MEM_CMD_DONE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_NOT_DONE                    _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_MEM_CMD_DONE_DONE                        _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_TXF_OVF_SHIFT                    _MK_SHIFT_CONST(8)
+#define OWR_INTR_SET_0_TXF_OVF_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_TXF_OVF_SHIFT)
+#define OWR_INTR_SET_0_TXF_OVF_RANGE                    8:8
+#define OWR_INTR_SET_0_TXF_OVF_WOFFSET                  0x0
+#define OWR_INTR_SET_0_TXF_OVF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_TXF_OVF_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_TXF_OVF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_TXF_OVF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_TXF_OVF_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_TXF_OVF_EMPTY                    _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_RXF_UNR_SHIFT                    _MK_SHIFT_CONST(9)
+#define OWR_INTR_SET_0_RXF_UNR_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_RXF_UNR_SHIFT)
+#define OWR_INTR_SET_0_RXF_UNR_RANGE                    9:9
+#define OWR_INTR_SET_0_RXF_UNR_WOFFSET                  0x0
+#define OWR_INTR_SET_0_RXF_UNR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RXF_UNR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_RXF_UNR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RXF_UNR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_RXF_UNR_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_RXF_UNR_EMPTY                    _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_DGLITCH_SHIFT                    _MK_SHIFT_CONST(10)
+#define OWR_INTR_SET_0_DGLITCH_FIELD                    (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_DGLITCH_SHIFT)
+#define OWR_INTR_SET_0_DGLITCH_RANGE                    10:10
+#define OWR_INTR_SET_0_DGLITCH_WOFFSET                  0x0
+#define OWR_INTR_SET_0_DGLITCH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_DGLITCH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_DGLITCH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_DGLITCH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_DGLITCH_DGLITCH_NOT_DETECTED                     _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_DGLITCH_DGLITCH_DETECTED                 _MK_ENUM_CONST(1)
+
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_SHIFT                  _MK_SHIFT_CONST(13)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_FIELD                  (_MK_MASK_CONST(0x1) << OWR_INTR_SET_0_BIT_TRANSFER_DONE_SHIFT)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_RANGE                  13:13
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_WOFFSET                        0x0
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_NOT_DONE                       _MK_ENUM_CONST(0)
+#define OWR_INTR_SET_0_BIT_TRANSFER_DONE_DONE                   _MK_ENUM_CONST(1)
+
+
+// Register OWR_STATUS_0  
+#define OWR_STATUS_0                    _MK_ADDR_CONST(0x34)
+#define OWR_STATUS_0_SECURE                     0x0
+#define OWR_STATUS_0_WORD_COUNT                         0x1
+#define OWR_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x15)
+#define OWR_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
+#define OWR_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
+#define OWR_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x60)
+// Ready bit. This bit is set at the end of every transfer and 
+// its cleared by hardware when next transfer starts  
+#define OWR_STATUS_0_RDY_SHIFT                  _MK_SHIFT_CONST(0)
+#define OWR_STATUS_0_RDY_FIELD                  (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RDY_SHIFT)
+#define OWR_STATUS_0_RDY_RANGE                  0:0
+#define OWR_STATUS_0_RDY_WOFFSET                        0x0
+#define OWR_STATUS_0_RDY_DEFAULT                        _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RDY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RDY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RDY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RDY_NOT_READY                      _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RDY_READY                  _MK_ENUM_CONST(1)
+
+// TX FIFO full status: RO.Hardware sets this bit to 1 if TX FIFO is full.
+// Otherwise, this bit is set to 0. 
+#define OWR_STATUS_0_TXF_FULL_SHIFT                     _MK_SHIFT_CONST(1)
+#define OWR_STATUS_0_TXF_FULL_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_TXF_FULL_SHIFT)
+#define OWR_STATUS_0_TXF_FULL_RANGE                     1:1
+#define OWR_STATUS_0_TXF_FULL_WOFFSET                   0x0
+#define OWR_STATUS_0_TXF_FULL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TXF_FULL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_TXF_FULL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TXF_FULL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TXF_FULL_NOT_FULL                  _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_TXF_FULL_FULL                      _MK_ENUM_CONST(1)
+
+// TX FIFO empty status: RO.Hardware sets this bit to 1 if TX FIFO is empty
+// Otherwise, this bit is set to 0.   
+#define OWR_STATUS_0_TXF_EMPTY_SHIFT                    _MK_SHIFT_CONST(2)
+#define OWR_STATUS_0_TXF_EMPTY_FIELD                    (_MK_MASK_CONST(0x1) << OWR_STATUS_0_TXF_EMPTY_SHIFT)
+#define OWR_STATUS_0_TXF_EMPTY_RANGE                    2:2
+#define OWR_STATUS_0_TXF_EMPTY_WOFFSET                  0x0
+#define OWR_STATUS_0_TXF_EMPTY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_TXF_EMPTY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_TXF_EMPTY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TXF_EMPTY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TXF_EMPTY_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_TXF_EMPTY_EMPTY                    _MK_ENUM_CONST(1)
+
+// RX FIFO full status: RO.Hardware sets this bit to 1 if RX FIFO is full.
+// Otherwise, this bit is set to 0.  
+#define OWR_STATUS_0_RXF_FULL_SHIFT                     _MK_SHIFT_CONST(3)
+#define OWR_STATUS_0_RXF_FULL_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RXF_FULL_SHIFT)
+#define OWR_STATUS_0_RXF_FULL_RANGE                     3:3
+#define OWR_STATUS_0_RXF_FULL_WOFFSET                   0x0
+#define OWR_STATUS_0_RXF_FULL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RXF_FULL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RXF_FULL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RXF_FULL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RXF_FULL_NOT_FULL                  _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RXF_FULL_FULL                      _MK_ENUM_CONST(1)
+
+// RX FIFO empty status: RO.Hardware sets this bit to 1 if RX FIFO is empty
+// Otherwise, this bit is set to 0.  
+#define OWR_STATUS_0_RXF_EMPTY_SHIFT                    _MK_SHIFT_CONST(4)
+#define OWR_STATUS_0_RXF_EMPTY_FIELD                    (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RXF_EMPTY_SHIFT)
+#define OWR_STATUS_0_RXF_EMPTY_RANGE                    4:4
+#define OWR_STATUS_0_RXF_EMPTY_WOFFSET                  0x0
+#define OWR_STATUS_0_RXF_EMPTY_DEFAULT                  _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RXF_EMPTY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RXF_EMPTY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RXF_EMPTY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RXF_EMPTY_NOT_EMPTY                        _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RXF_EMPTY_EMPTY                    _MK_ENUM_CONST(1)
+
+// flush the tx fifo,cleared after fifo is empty 
+#define OWR_STATUS_0_TX_FLUSH_SHIFT                     _MK_SHIFT_CONST(5)
+#define OWR_STATUS_0_TX_FLUSH_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_TX_FLUSH_SHIFT)
+#define OWR_STATUS_0_TX_FLUSH_RANGE                     5:5
+#define OWR_STATUS_0_TX_FLUSH_WOFFSET                   0x0
+#define OWR_STATUS_0_TX_FLUSH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TX_FLUSH_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_TX_FLUSH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TX_FLUSH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TX_FLUSH_DISABLE                   _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_TX_FLUSH_ENABLE                    _MK_ENUM_CONST(1)
+
+// flush the rx fifo,cleared after fifo is empty 
+#define OWR_STATUS_0_RX_FLUSH_SHIFT                     _MK_SHIFT_CONST(6)
+#define OWR_STATUS_0_RX_FLUSH_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RX_FLUSH_SHIFT)
+#define OWR_STATUS_0_RX_FLUSH_RANGE                     6:6
+#define OWR_STATUS_0_RX_FLUSH_WOFFSET                   0x0
+#define OWR_STATUS_0_RX_FLUSH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RX_FLUSH_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RX_FLUSH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RX_FLUSH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RX_FLUSH_DISABLE                   _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RX_FLUSH_ENABLE                    _MK_ENUM_CONST(1)
+
+// The number of slots to be read from  the rx fifo
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_SHIFT                     _MK_SHIFT_CONST(7)
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_FIELD                     (_MK_MASK_CONST(0x3f) << OWR_STATUS_0_RX_FIFO_FULL_CNT_SHIFT)
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_RANGE                     12:7
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_WOFFSET                   0x0
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// The number of slots that can be written to the tx fifo
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT                    _MK_SHIFT_CONST(13)
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_FIELD                    (_MK_MASK_CONST(0x3f) << OWR_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT)
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_RANGE                    18:13
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_WOFFSET                  0x0
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// this is set when rpp reset bit is set in ctl reg(go), 
+// auto cleared on completion of reset initialization sequence.
+#define OWR_STATUS_0_RPP_SHIFT                  _MK_SHIFT_CONST(19)
+#define OWR_STATUS_0_RPP_FIELD                  (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RPP_SHIFT)
+#define OWR_STATUS_0_RPP_RANGE                  19:19
+#define OWR_STATUS_0_RPP_WOFFSET                        0x0
+#define OWR_STATUS_0_RPP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RPP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RPP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RPP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RPP_IDLE                   _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RPP_RESET_PRESENCE_PULSE                   _MK_ENUM_CONST(1)
+
+// WRITE 0 : This bit is self clearing,and is cleared 
+// when write zero time slot completes 
+// on write sequence 0  is transfered 
+#define OWR_STATUS_0_WR0_BUSY_SHIFT                     _MK_SHIFT_CONST(20)
+#define OWR_STATUS_0_WR0_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_WR0_BUSY_SHIFT)
+#define OWR_STATUS_0_WR0_BUSY_RANGE                     20:20
+#define OWR_STATUS_0_WR0_BUSY_WOFFSET                   0x0
+#define OWR_STATUS_0_WR0_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR0_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_WR0_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR0_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR0_BUSY_IDLE                      _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_WR0_BUSY_BUSY                      _MK_ENUM_CONST(1)
+
+// WRITE1 : This is a self clearing bit and is cleared 
+// when write one time slot completes
+// on write sequence 1  is transfered 
+#define OWR_STATUS_0_WR1_BUSY_SHIFT                     _MK_SHIFT_CONST(21)
+#define OWR_STATUS_0_WR1_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_WR1_BUSY_SHIFT)
+#define OWR_STATUS_0_WR1_BUSY_RANGE                     21:21
+#define OWR_STATUS_0_WR1_BUSY_WOFFSET                   0x0
+#define OWR_STATUS_0_WR1_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR1_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_WR1_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR1_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_WR1_BUSY_IDLE                      _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_WR1_BUSY_BUSY                      _MK_ENUM_CONST(1)
+
+// READ : This is a self clearing bit and is cleared 
+// when read time slot completes
+// on read sequence the sampled read bit is stored in READ_BIT
+#define OWR_STATUS_0_RD_BUSY_SHIFT                      _MK_SHIFT_CONST(22)
+#define OWR_STATUS_0_RD_BUSY_FIELD                      (_MK_MASK_CONST(0x1) << OWR_STATUS_0_RD_BUSY_SHIFT)
+#define OWR_STATUS_0_RD_BUSY_RANGE                      22:22
+#define OWR_STATUS_0_RD_BUSY_WOFFSET                    0x0
+#define OWR_STATUS_0_RD_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RD_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_RD_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RD_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_RD_BUSY_IDLE                       _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_RD_BUSY_BUSY                       _MK_ENUM_CONST(1)
+
+// the bit is valid only RD_BUSY is cleared 
+#define OWR_STATUS_0_READ_SAMPLED_BIT_SHIFT                     _MK_SHIFT_CONST(23)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_FIELD                     (_MK_MASK_CONST(0x1) << OWR_STATUS_0_READ_SAMPLED_BIT_SHIFT)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_RANGE                     23:23
+#define OWR_STATUS_0_READ_SAMPLED_BIT_WOFFSET                   0x0
+#define OWR_STATUS_0_READ_SAMPLED_BIT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_READ_ZERO                 _MK_ENUM_CONST(0)
+#define OWR_STATUS_0_READ_SAMPLED_BIT_READ_ONE                  _MK_ENUM_CONST(1)
+
+
+// Register OWR_CRC_0  
+#define OWR_CRC_0                       _MK_ADDR_CONST(0x38)
+#define OWR_CRC_0_SECURE                        0x0
+#define OWR_CRC_0_WORD_COUNT                    0x1
+#define OWR_CRC_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define OWR_CRC_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define OWR_CRC_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// CRC Received on Read Data
+#define OWR_CRC_0_CRC_RECEV_SHIFT                       _MK_SHIFT_CONST(0)
+#define OWR_CRC_0_CRC_RECEV_FIELD                       (_MK_MASK_CONST(0xffff) << OWR_CRC_0_CRC_RECEV_SHIFT)
+#define OWR_CRC_0_CRC_RECEV_RANGE                       15:0
+#define OWR_CRC_0_CRC_RECEV_WOFFSET                     0x0
+#define OWR_CRC_0_CRC_RECEV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_CRC_RECEV_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define OWR_CRC_0_CRC_RECEV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_CRC_RECEV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// CRC calculated by owr current wr/rd operation
+#define OWR_CRC_0_CRC_CALC_SHIFT                        _MK_SHIFT_CONST(16)
+#define OWR_CRC_0_CRC_CALC_FIELD                        (_MK_MASK_CONST(0xffff) << OWR_CRC_0_CRC_CALC_SHIFT)
+#define OWR_CRC_0_CRC_CALC_RANGE                        31:16
+#define OWR_CRC_0_CRC_CALC_WOFFSET                      0x0
+#define OWR_CRC_0_CRC_CALC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_CRC_CALC_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define OWR_CRC_0_CRC_CALC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_CRC_0_CRC_CALC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register OWR_BYTE_CNT_0  
+#define OWR_BYTE_CNT_0                  _MK_ADDR_CONST(0x3c)
+#define OWR_BYTE_CNT_0_SECURE                   0x0
+#define OWR_BYTE_CNT_0_WORD_COUNT                       0x1
+#define OWR_BYTE_CNT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define OWR_BYTE_CNT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_BYTE_CNT_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// Number of bytes Received on Read Data includes crc byte cnt
+#define OWR_BYTE_CNT_0_RECEIVED_SHIFT                   _MK_SHIFT_CONST(0)
+#define OWR_BYTE_CNT_0_RECEIVED_FIELD                   (_MK_MASK_CONST(0xffff) << OWR_BYTE_CNT_0_RECEIVED_SHIFT)
+#define OWR_BYTE_CNT_0_RECEIVED_RANGE                   15:0
+#define OWR_BYTE_CNT_0_RECEIVED_WOFFSET                 0x0
+#define OWR_BYTE_CNT_0_RECEIVED_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_RECEIVED_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define OWR_BYTE_CNT_0_RECEIVED_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_RECEIVED_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of bytes Transmitted on wr cmds or addr sent
+#define OWR_BYTE_CNT_0_TRANSMITTED_SHIFT                        _MK_SHIFT_CONST(16)
+#define OWR_BYTE_CNT_0_TRANSMITTED_FIELD                        (_MK_MASK_CONST(0xffff) << OWR_BYTE_CNT_0_TRANSMITTED_SHIFT)
+#define OWR_BYTE_CNT_0_TRANSMITTED_RANGE                        31:16
+#define OWR_BYTE_CNT_0_TRANSMITTED_WOFFSET                      0x0
+#define OWR_BYTE_CNT_0_TRANSMITTED_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_TRANSMITTED_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define OWR_BYTE_CNT_0_TRANSMITTED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_BYTE_CNT_0_TRANSMITTED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register OWR_TX_FIFO_0  
+#define OWR_TX_FIFO_0                   _MK_ADDR_CONST(0x40)
+#define OWR_TX_FIFO_0_SECURE                    0x0
+#define OWR_TX_FIFO_0_WORD_COUNT                        0x1
+#define OWR_TX_FIFO_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_TX_FIFO_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_TX_FIFO_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define OWR_TX_FIFO_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_TX_FIFO_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define OWR_TX_FIFO_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// TX FIFO
+#define OWR_TX_FIFO_0_WR_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define OWR_TX_FIFO_0_WR_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << OWR_TX_FIFO_0_WR_DATA_SHIFT)
+#define OWR_TX_FIFO_0_WR_DATA_RANGE                     31:0
+#define OWR_TX_FIFO_0_WR_DATA_WOFFSET                   0x0
+#define OWR_TX_FIFO_0_WR_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_TX_FIFO_0_WR_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define OWR_TX_FIFO_0_WR_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_TX_FIFO_0_WR_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register OWR_RX_FIFO_0  
+#define OWR_RX_FIFO_0                   _MK_ADDR_CONST(0x44)
+#define OWR_RX_FIFO_0_SECURE                    0x0
+#define OWR_RX_FIFO_0_WORD_COUNT                        0x1
+#define OWR_RX_FIFO_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_RX_FIFO_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define OWR_RX_FIFO_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define OWR_RX_FIFO_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define OWR_RX_FIFO_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define OWR_RX_FIFO_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// RX FIFO
+#define OWR_RX_FIFO_0_RD_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define OWR_RX_FIFO_0_RD_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << OWR_RX_FIFO_0_RD_DATA_SHIFT)
+#define OWR_RX_FIFO_0_RD_DATA_RANGE                     31:0
+#define OWR_RX_FIFO_0_RD_DATA_WOFFSET                   0x0
+#define OWR_RX_FIFO_0_RD_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_RX_FIFO_0_RD_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define OWR_RX_FIFO_0_RD_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define OWR_RX_FIFO_0_RD_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register OWR_STATE_BITS_0  
+#define OWR_STATE_BITS_0                        _MK_ADDR_CONST(0x48)
+#define OWR_STATE_BITS_0_SECURE                         0x0
+#define OWR_STATE_BITS_0_WORD_COUNT                     0x1
+#define OWR_STATE_BITS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define OWR_STATE_BITS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define OWR_STATE_BITS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// controls reset initialization sequence , rom cmd and mem cmd
+#define OWR_STATE_BITS_0_OWR_STATE_SHIFT                        _MK_SHIFT_CONST(0)
+#define OWR_STATE_BITS_0_OWR_STATE_FIELD                        (_MK_MASK_CONST(0xf) << OWR_STATE_BITS_0_OWR_STATE_SHIFT)
+#define OWR_STATE_BITS_0_OWR_STATE_RANGE                        3:0
+#define OWR_STATE_BITS_0_OWR_STATE_WOFFSET                      0x0
+#define OWR_STATE_BITS_0_OWR_STATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_OWR_STATE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define OWR_STATE_BITS_0_OWR_STATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_OWR_STATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// executes a particular cmd in rom or mem cmd
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_SHIFT                        _MK_SHIFT_CONST(4)
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_FIELD                        (_MK_MASK_CONST(0xf) << OWR_STATE_BITS_0_CMD_EXECUTE_STATE_SHIFT)
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_RANGE                        7:4
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_WOFFSET                      0x0
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_CMD_EXECUTE_STATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// executes write time slots
+#define OWR_STATE_BITS_0_WRITE_STATE_SHIFT                      _MK_SHIFT_CONST(8)
+#define OWR_STATE_BITS_0_WRITE_STATE_FIELD                      (_MK_MASK_CONST(0xf) << OWR_STATE_BITS_0_WRITE_STATE_SHIFT)
+#define OWR_STATE_BITS_0_WRITE_STATE_RANGE                      11:8
+#define OWR_STATE_BITS_0_WRITE_STATE_WOFFSET                    0x0
+#define OWR_STATE_BITS_0_WRITE_STATE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_WRITE_STATE_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define OWR_STATE_BITS_0_WRITE_STATE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_WRITE_STATE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// executes read time slots 
+#define OWR_STATE_BITS_0_READ_STATE_SHIFT                       _MK_SHIFT_CONST(12)
+#define OWR_STATE_BITS_0_READ_STATE_FIELD                       (_MK_MASK_CONST(0xf) << OWR_STATE_BITS_0_READ_STATE_SHIFT)
+#define OWR_STATE_BITS_0_READ_STATE_RANGE                       15:12
+#define OWR_STATE_BITS_0_READ_STATE_WOFFSET                     0x0
+#define OWR_STATE_BITS_0_READ_STATE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_READ_STATE_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define OWR_STATE_BITS_0_READ_STATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define OWR_STATE_BITS_0_READ_STATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_AROWR_REGS(_op_) \
+_op_(OWR_CONTROL_0) \
+_op_(OWR_COMMAND_0) \
+_op_(OWR_EPROM_0) \
+_op_(OWR_WR_RD_TCTL_0) \
+_op_(OWR_RST_PRESENCE_TCTL_0) \
+_op_(OWR_PPM_CORRECTION_TCTL_0) \
+_op_(OWR_PROG_PULSE_TCTL_0) \
+_op_(OWR_READ_ROM0_0) \
+_op_(OWR_READ_ROM1_0) \
+_op_(OWR_INTR_MASK_0) \
+_op_(OWR_INTR_STATUS_0) \
+_op_(OWR_INTR_SOURCE_0) \
+_op_(OWR_INTR_SET_0) \
+_op_(OWR_STATUS_0) \
+_op_(OWR_CRC_0) \
+_op_(OWR_BYTE_CNT_0) \
+_op_(OWR_TX_FIFO_0) \
+_op_(OWR_RX_FIFO_0) \
+_op_(OWR_STATE_BITS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_OWR        0x00000000
+
+//
+// AROWR REGISTER BANKS
+//
+
+#define OWR0_FIRST_REG 0x0000 // OWR_CONTROL_0
+#define OWR0_LAST_REG 0x0048 // OWR_STATE_BITS_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___AROWR_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arpl310.h b/arch/arm/mach-tegra/nv/include/ap20/arpl310.h
new file mode 100644
index 000000000000..d3899a2821f3
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arpl310.h
@@ -0,0 +1,2472 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARPL310_H_INC_
+#define ___ARPL310_H_INC_
+
+// Register PL310_CACHE_ID_0  
+#define PL310_CACHE_ID_0                        _MK_ADDR_CONST(0x0)
+#define PL310_CACHE_ID_0_SECURE                         0x0
+#define PL310_CACHE_ID_0_WORD_COUNT                     0x1
+#define PL310_CACHE_ID_0_RESET_VAL                      _MK_MASK_CONST(0x410000c4)
+#define PL310_CACHE_ID_0_RESET_MASK                     _MK_MASK_CONST(0xff00ffff)
+#define PL310_CACHE_ID_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_CACHE_ID_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_CACHE_ID_0_READ_MASK                      _MK_MASK_CONST(0xff00ffff)
+#define PL310_CACHE_ID_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+#define PL310_CACHE_ID_0_RTL_RELEASE_SHIFT                      _MK_SHIFT_CONST(0)
+#define PL310_CACHE_ID_0_RTL_RELEASE_FIELD                      (_MK_MASK_CONST(0x3f) << PL310_CACHE_ID_0_RTL_RELEASE_SHIFT)
+#define PL310_CACHE_ID_0_RTL_RELEASE_RANGE                      5:0
+#define PL310_CACHE_ID_0_RTL_RELEASE_WOFFSET                    0x0
+#define PL310_CACHE_ID_0_RTL_RELEASE_DEFAULT                    _MK_MASK_CONST(0x4)
+#define PL310_CACHE_ID_0_RTL_RELEASE_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define PL310_CACHE_ID_0_RTL_RELEASE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_CACHE_ID_0_RTL_RELEASE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_CACHE_ID_0_PART_NUMBER_SHIFT                      _MK_SHIFT_CONST(6)
+#define PL310_CACHE_ID_0_PART_NUMBER_FIELD                      (_MK_MASK_CONST(0xf) << PL310_CACHE_ID_0_PART_NUMBER_SHIFT)
+#define PL310_CACHE_ID_0_PART_NUMBER_RANGE                      9:6
+#define PL310_CACHE_ID_0_PART_NUMBER_WOFFSET                    0x0
+#define PL310_CACHE_ID_0_PART_NUMBER_DEFAULT                    _MK_MASK_CONST(0x3)
+#define PL310_CACHE_ID_0_PART_NUMBER_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define PL310_CACHE_ID_0_PART_NUMBER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_CACHE_ID_0_PART_NUMBER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_CACHE_ID_0_CACHE_ID_SHIFT                 _MK_SHIFT_CONST(10)
+#define PL310_CACHE_ID_0_CACHE_ID_FIELD                 (_MK_MASK_CONST(0x3f) << PL310_CACHE_ID_0_CACHE_ID_SHIFT)
+#define PL310_CACHE_ID_0_CACHE_ID_RANGE                 15:10
+#define PL310_CACHE_ID_0_CACHE_ID_WOFFSET                       0x0
+#define PL310_CACHE_ID_0_CACHE_ID_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_CACHE_ID_0_CACHE_ID_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define PL310_CACHE_ID_0_CACHE_ID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_CACHE_ID_0_CACHE_ID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define PL310_CACHE_ID_0_IMPLEMENTER_SHIFT                      _MK_SHIFT_CONST(24)
+#define PL310_CACHE_ID_0_IMPLEMENTER_FIELD                      (_MK_MASK_CONST(0xff) << PL310_CACHE_ID_0_IMPLEMENTER_SHIFT)
+#define PL310_CACHE_ID_0_IMPLEMENTER_RANGE                      31:24
+#define PL310_CACHE_ID_0_IMPLEMENTER_WOFFSET                    0x0
+#define PL310_CACHE_ID_0_IMPLEMENTER_DEFAULT                    _MK_MASK_CONST(0x41)
+#define PL310_CACHE_ID_0_IMPLEMENTER_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_CACHE_ID_0_IMPLEMENTER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_CACHE_ID_0_IMPLEMENTER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register PL310_CACHE_TYPE_0  
+#define PL310_CACHE_TYPE_0                      _MK_ADDR_CONST(0x4)
+#define PL310_CACHE_TYPE_0_SECURE                       0x0
+#define PL310_CACHE_TYPE_0_WORD_COUNT                   0x1
+#define PL310_CACHE_TYPE_0_RESET_VAL                    _MK_MASK_CONST(0x1c400400)
+#define PL310_CACHE_TYPE_0_RESET_MASK                   _MK_MASK_CONST(0x1f743743)
+#define PL310_CACHE_TYPE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_READ_MASK                    _MK_MASK_CONST(0x1f743743)
+#define PL310_CACHE_TYPE_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_I_LINE_SIZE_SHIFT                    _MK_SHIFT_CONST(0)
+#define PL310_CACHE_TYPE_0_I_LINE_SIZE_FIELD                    (_MK_MASK_CONST(0x3) << PL310_CACHE_TYPE_0_I_LINE_SIZE_SHIFT)
+#define PL310_CACHE_TYPE_0_I_LINE_SIZE_RANGE                    1:0
+#define PL310_CACHE_TYPE_0_I_LINE_SIZE_WOFFSET                  0x0
+#define PL310_CACHE_TYPE_0_I_LINE_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_I_LINE_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define PL310_CACHE_TYPE_0_I_LINE_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_I_LINE_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_I_LINE_SIZE_SIZE_32B                 _MK_ENUM_CONST(0)
+
+#define PL310_CACHE_TYPE_0_I_ASSOCIATIVITY_SHIFT                        _MK_SHIFT_CONST(6)
+#define PL310_CACHE_TYPE_0_I_ASSOCIATIVITY_FIELD                        (_MK_MASK_CONST(0x1) << PL310_CACHE_TYPE_0_I_ASSOCIATIVITY_SHIFT)
+#define PL310_CACHE_TYPE_0_I_ASSOCIATIVITY_RANGE                        6:6
+#define PL310_CACHE_TYPE_0_I_ASSOCIATIVITY_WOFFSET                      0x0
+#define PL310_CACHE_TYPE_0_I_ASSOCIATIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_I_ASSOCIATIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_CACHE_TYPE_0_I_ASSOCIATIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_I_ASSOCIATIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_I_ASSOCIATIVITY_ASSOC_8                      _MK_ENUM_CONST(0)
+#define PL310_CACHE_TYPE_0_I_ASSOCIATIVITY_ASSOC_16                     _MK_ENUM_CONST(1)
+
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_SHIFT                     _MK_SHIFT_CONST(8)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_FIELD                     (_MK_MASK_CONST(0x7) << PL310_CACHE_TYPE_0_I_WAY_SIZE_SHIFT)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_RANGE                     10:8
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_WOFFSET                   0x0
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_DEFAULT                   _MK_MASK_CONST(0x4)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_WAY_RES16KB                       _MK_ENUM_CONST(0)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_WAY_16KB                  _MK_ENUM_CONST(1)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_WAY_32KB                  _MK_ENUM_CONST(2)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_WAY_64KB                  _MK_ENUM_CONST(3)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_WAY_128KB                 _MK_ENUM_CONST(4)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_WAY_256KB                 _MK_ENUM_CONST(5)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_WAY_512KB                 _MK_ENUM_CONST(6)
+#define PL310_CACHE_TYPE_0_I_WAY_SIZE_WAY_RES512kB                      _MK_ENUM_CONST(7)
+
+#define PL310_CACHE_TYPE_0_D_LINE_SIZE_SHIFT                    _MK_SHIFT_CONST(12)
+#define PL310_CACHE_TYPE_0_D_LINE_SIZE_FIELD                    (_MK_MASK_CONST(0x3) << PL310_CACHE_TYPE_0_D_LINE_SIZE_SHIFT)
+#define PL310_CACHE_TYPE_0_D_LINE_SIZE_RANGE                    13:12
+#define PL310_CACHE_TYPE_0_D_LINE_SIZE_WOFFSET                  0x0
+#define PL310_CACHE_TYPE_0_D_LINE_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_D_LINE_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define PL310_CACHE_TYPE_0_D_LINE_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_D_LINE_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_D_LINE_SIZE_SIZE_32B                 _MK_ENUM_CONST(0)
+
+#define PL310_CACHE_TYPE_0_D_ASSOCIATIVITY_SHIFT                        _MK_SHIFT_CONST(18)
+#define PL310_CACHE_TYPE_0_D_ASSOCIATIVITY_FIELD                        (_MK_MASK_CONST(0x1) << PL310_CACHE_TYPE_0_D_ASSOCIATIVITY_SHIFT)
+#define PL310_CACHE_TYPE_0_D_ASSOCIATIVITY_RANGE                        18:18
+#define PL310_CACHE_TYPE_0_D_ASSOCIATIVITY_WOFFSET                      0x0
+#define PL310_CACHE_TYPE_0_D_ASSOCIATIVITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_D_ASSOCIATIVITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_CACHE_TYPE_0_D_ASSOCIATIVITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_D_ASSOCIATIVITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_D_ASSOCIATIVITY_ASSOC_8                      _MK_ENUM_CONST(0)
+#define PL310_CACHE_TYPE_0_D_ASSOCIATIVITY_ASSOC_16                     _MK_ENUM_CONST(1)
+
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_SHIFT                     _MK_SHIFT_CONST(20)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_FIELD                     (_MK_MASK_CONST(0x7) << PL310_CACHE_TYPE_0_D_WAY_SIZE_SHIFT)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_RANGE                     22:20
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_WOFFSET                   0x0
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_DEFAULT                   _MK_MASK_CONST(0x4)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_WAY_RES16KB                       _MK_ENUM_CONST(0)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_WAY_16KB                  _MK_ENUM_CONST(1)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_WAY_32KB                  _MK_ENUM_CONST(2)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_WAY_64KB                  _MK_ENUM_CONST(3)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_WAY_128KB                 _MK_ENUM_CONST(4)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_WAY_256KB                 _MK_ENUM_CONST(5)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_WAY_512KB                 _MK_ENUM_CONST(6)
+#define PL310_CACHE_TYPE_0_D_WAY_SIZE_WAY_RES512kB                      _MK_ENUM_CONST(7)
+
+#define PL310_CACHE_TYPE_0_ORGANIZATION_SHIFT                   _MK_SHIFT_CONST(24)
+#define PL310_CACHE_TYPE_0_ORGANIZATION_FIELD                   (_MK_MASK_CONST(0x1) << PL310_CACHE_TYPE_0_ORGANIZATION_SHIFT)
+#define PL310_CACHE_TYPE_0_ORGANIZATION_RANGE                   24:24
+#define PL310_CACHE_TYPE_0_ORGANIZATION_WOFFSET                 0x0
+#define PL310_CACHE_TYPE_0_ORGANIZATION_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_ORGANIZATION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define PL310_CACHE_TYPE_0_ORGANIZATION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_ORGANIZATION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_ORGANIZATION_UNIFIED                 _MK_ENUM_CONST(0)
+#define PL310_CACHE_TYPE_0_ORGANIZATION_HARVARD                 _MK_ENUM_CONST(1)
+
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_LINE_SHIFT                       _MK_SHIFT_CONST(25)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_LINE_FIELD                       (_MK_MASK_CONST(0x1) << PL310_CACHE_TYPE_0_LOCKDOWN_BY_LINE_SHIFT)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_LINE_RANGE                       25:25
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_LINE_WOFFSET                     0x0
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_LINE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_LINE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_LINE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_LINE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_LINE_NOT_IMPLEMENTED                     _MK_ENUM_CONST(0)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_LINE_IMPLEMENTED                 _MK_ENUM_CONST(1)
+
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_MASTER_SHIFT                     _MK_SHIFT_CONST(26)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_MASTER_FIELD                     (_MK_MASK_CONST(0x1) << PL310_CACHE_TYPE_0_LOCKDOWN_BY_MASTER_SHIFT)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_MASTER_RANGE                     26:26
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_MASTER_WOFFSET                   0x0
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_MASTER_DEFAULT                   _MK_MASK_CONST(0x1)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_MASTER_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_MASTER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_MASTER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_MASTER_NOT_IMPLEMENTED                   _MK_ENUM_CONST(0)
+#define PL310_CACHE_TYPE_0_LOCKDOWN_BY_MASTER_IMPLEMENTED                       _MK_ENUM_CONST(1)
+
+#define PL310_CACHE_TYPE_0_CTYPE_SHIFT                  _MK_SHIFT_CONST(27)
+#define PL310_CACHE_TYPE_0_CTYPE_FIELD                  (_MK_MASK_CONST(0x3) << PL310_CACHE_TYPE_0_CTYPE_SHIFT)
+#define PL310_CACHE_TYPE_0_CTYPE_RANGE                  28:27
+#define PL310_CACHE_TYPE_0_CTYPE_WOFFSET                        0x0
+#define PL310_CACHE_TYPE_0_CTYPE_DEFAULT                        _MK_MASK_CONST(0x3)
+#define PL310_CACHE_TYPE_0_CTYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define PL310_CACHE_TYPE_0_CTYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_CTYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_CACHE_TYPE_0_CTYPE_PL310                  _MK_ENUM_CONST(3)
+
+
+// Register PL310_CONTROL_0  
+#define PL310_CONTROL_0                 _MK_ADDR_CONST(0x100)
+#define PL310_CONTROL_0_SECURE                  0x0
+#define PL310_CONTROL_0_WORD_COUNT                      0x1
+#define PL310_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define PL310_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define PL310_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define PL310_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define PL310_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_CONTROL_0_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define PL310_CONTROL_0_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << PL310_CONTROL_0_ENABLE_SHIFT)
+#define PL310_CONTROL_0_ENABLE_RANGE                    0:0
+#define PL310_CONTROL_0_ENABLE_WOFFSET                  0x0
+#define PL310_CONTROL_0_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_CONTROL_0_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PL310_CONTROL_0_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_CONTROL_0_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_CONTROL_0_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define PL310_CONTROL_0_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register PL310_AUXILIARY_CONTROL_0  
+#define PL310_AUXILIARY_CONTROL_0                       _MK_ADDR_CONST(0x104)
+#define PL310_AUXILIARY_CONTROL_0_SECURE                        0x0
+#define PL310_AUXILIARY_CONTROL_0_WORD_COUNT                    0x1
+#define PL310_AUXILIARY_CONTROL_0_RESET_VAL                     _MK_MASK_CONST(0x80000)
+#define PL310_AUXILIARY_CONTROL_0_RESET_MASK                    _MK_MASK_CONST(0x7dff3401)
+#define PL310_AUXILIARY_CONTROL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_READ_MASK                     _MK_MASK_CONST(0x7dff3401)
+#define PL310_AUXILIARY_CONTROL_0_WRITE_MASK                    _MK_MASK_CONST(0x7dff3401)
+#define PL310_AUXILIARY_CONTROL_0_FULL_LINE_OF_ZERO_SHIFT                       _MK_SHIFT_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_FULL_LINE_OF_ZERO_FIELD                       (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_FULL_LINE_OF_ZERO_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_FULL_LINE_OF_ZERO_RANGE                       0:0
+#define PL310_AUXILIARY_CONTROL_0_FULL_LINE_OF_ZERO_WOFFSET                     0x0
+#define PL310_AUXILIARY_CONTROL_0_FULL_LINE_OF_ZERO_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_FULL_LINE_OF_ZERO_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_FULL_LINE_OF_ZERO_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_FULL_LINE_OF_ZERO_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_FULL_LINE_OF_ZERO_DISABLED                    _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_FULL_LINE_OF_ZERO_ENABLED                     _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_SO_DEV_HIGH_PRIORITY_SHIFT                    _MK_SHIFT_CONST(10)
+#define PL310_AUXILIARY_CONTROL_0_SO_DEV_HIGH_PRIORITY_FIELD                    (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_SO_DEV_HIGH_PRIORITY_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_SO_DEV_HIGH_PRIORITY_RANGE                    10:10
+#define PL310_AUXILIARY_CONTROL_0_SO_DEV_HIGH_PRIORITY_WOFFSET                  0x0
+#define PL310_AUXILIARY_CONTROL_0_SO_DEV_HIGH_PRIORITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_SO_DEV_HIGH_PRIORITY_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_SO_DEV_HIGH_PRIORITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_SO_DEV_HIGH_PRIORITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_SO_DEV_HIGH_PRIORITY_DISABLED                 _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_SO_DEV_HIGH_PRIORITY_ENABLED                  _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_EXCLUSIVE_SHIFT                       _MK_SHIFT_CONST(12)
+#define PL310_AUXILIARY_CONTROL_0_EXCLUSIVE_FIELD                       (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_EXCLUSIVE_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_EXCLUSIVE_RANGE                       12:12
+#define PL310_AUXILIARY_CONTROL_0_EXCLUSIVE_WOFFSET                     0x0
+#define PL310_AUXILIARY_CONTROL_0_EXCLUSIVE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_EXCLUSIVE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_EXCLUSIVE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_EXCLUSIVE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_EXCLUSIVE_DISABLED                    _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_EXCLUSIVE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_SHARED_INVALIDATE_SHIFT                       _MK_SHIFT_CONST(13)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_INVALIDATE_FIELD                       (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_SHARED_INVALIDATE_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_INVALIDATE_RANGE                       13:13
+#define PL310_AUXILIARY_CONTROL_0_SHARED_INVALIDATE_WOFFSET                     0x0
+#define PL310_AUXILIARY_CONTROL_0_SHARED_INVALIDATE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_INVALIDATE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_INVALIDATE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_INVALIDATE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_INVALIDATE_DISABLED                    _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_INVALIDATE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_ASSOCIATIVITY_SHIFT                   _MK_SHIFT_CONST(16)
+#define PL310_AUXILIARY_CONTROL_0_ASSOCIATIVITY_FIELD                   (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_ASSOCIATIVITY_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_ASSOCIATIVITY_RANGE                   16:16
+#define PL310_AUXILIARY_CONTROL_0_ASSOCIATIVITY_WOFFSET                 0x0
+#define PL310_AUXILIARY_CONTROL_0_ASSOCIATIVITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_ASSOCIATIVITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_ASSOCIATIVITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_ASSOCIATIVITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_ASSOCIATIVITY_ASSOC_8                 _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_ASSOCIATIVITY_ASSOC_16                        _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_SHIFT                        _MK_SHIFT_CONST(17)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_FIELD                        (_MK_MASK_CONST(0x7) << PL310_AUXILIARY_CONTROL_0_WAY_SIZE_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_RANGE                        19:17
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_WOFFSET                      0x0
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_DEFAULT                      _MK_MASK_CONST(0x4)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_WAY_RES16KB                  _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_WAY_16KB                     _MK_ENUM_CONST(1)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_WAY_32KB                     _MK_ENUM_CONST(2)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_WAY_64KB                     _MK_ENUM_CONST(3)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_WAY_128KB                    _MK_ENUM_CONST(4)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_WAY_256KB                    _MK_ENUM_CONST(5)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_WAY_512KB                    _MK_ENUM_CONST(6)
+#define PL310_AUXILIARY_CONTROL_0_WAY_SIZE_WAY_RES512kB                 _MK_ENUM_CONST(7)
+
+#define PL310_AUXILIARY_CONTROL_0_EVENT_MONITOR_BUS_SHIFT                       _MK_SHIFT_CONST(20)
+#define PL310_AUXILIARY_CONTROL_0_EVENT_MONITOR_BUS_FIELD                       (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_EVENT_MONITOR_BUS_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_EVENT_MONITOR_BUS_RANGE                       20:20
+#define PL310_AUXILIARY_CONTROL_0_EVENT_MONITOR_BUS_WOFFSET                     0x0
+#define PL310_AUXILIARY_CONTROL_0_EVENT_MONITOR_BUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_EVENT_MONITOR_BUS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_EVENT_MONITOR_BUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_EVENT_MONITOR_BUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_EVENT_MONITOR_BUS_DISABLED                    _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_EVENT_MONITOR_BUS_ENABLED                     _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_PARITY_SHIFT                  _MK_SHIFT_CONST(21)
+#define PL310_AUXILIARY_CONTROL_0_PARITY_FIELD                  (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_PARITY_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_PARITY_RANGE                  21:21
+#define PL310_AUXILIARY_CONTROL_0_PARITY_WOFFSET                        0x0
+#define PL310_AUXILIARY_CONTROL_0_PARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_PARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_PARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_PARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_PARITY_DISABLED                       _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_PARITY_ENABLED                        _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_SHARED_ATTRIBUTE_OVERRIDE_SHIFT                       _MK_SHIFT_CONST(22)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_ATTRIBUTE_OVERRIDE_FIELD                       (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_SHARED_ATTRIBUTE_OVERRIDE_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_ATTRIBUTE_OVERRIDE_RANGE                       22:22
+#define PL310_AUXILIARY_CONTROL_0_SHARED_ATTRIBUTE_OVERRIDE_WOFFSET                     0x0
+#define PL310_AUXILIARY_CONTROL_0_SHARED_ATTRIBUTE_OVERRIDE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_ATTRIBUTE_OVERRIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_ATTRIBUTE_OVERRIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_ATTRIBUTE_OVERRIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_ATTRIBUTE_OVERRIDE_DISABLED                    _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_SHARED_ATTRIBUTE_OVERRIDE_ENABLED                     _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_SHIFT                    _MK_SHIFT_CONST(23)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_FIELD                    (_MK_MASK_CONST(0x3) << PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_RANGE                    24:23
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_WOFFSET                  0x0
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_DISABLED                 _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_USE_AWCACHE                      _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_FORCE_NO_WA                      _MK_ENUM_CONST(1)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_OVERRIDE_AWCACHE_TO_NOWA                 _MK_ENUM_CONST(1)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_FORCE_WA                 _MK_ENUM_CONST(2)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_OVERRIDE_AWCACHE_TO_WA                   _MK_ENUM_CONST(2)
+#define PL310_AUXILIARY_CONTROL_0_FORCE_WRITE_ALLOCATE_RES_MAPPED_TO_0                  _MK_ENUM_CONST(3)
+
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_LOCKDOWN_WR_SHIFT                  _MK_SHIFT_CONST(26)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_LOCKDOWN_WR_FIELD                  (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_NON_SECURE_LOCKDOWN_WR_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_LOCKDOWN_WR_RANGE                  26:26
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_LOCKDOWN_WR_WOFFSET                        0x0
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_LOCKDOWN_WR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_LOCKDOWN_WR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_LOCKDOWN_WR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_LOCKDOWN_WR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_LOCKDOWN_WR_DISABLED                       _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_LOCKDOWN_WR_ENABLED                        _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_INTERRUPT_ACCESS_SHIFT                     _MK_SHIFT_CONST(27)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_INTERRUPT_ACCESS_FIELD                     (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_NON_SECURE_INTERRUPT_ACCESS_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_INTERRUPT_ACCESS_RANGE                     27:27
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_INTERRUPT_ACCESS_WOFFSET                   0x0
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_INTERRUPT_ACCESS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_INTERRUPT_ACCESS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_INTERRUPT_ACCESS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_INTERRUPT_ACCESS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_INTERRUPT_ACCESS_DISABLED                  _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_NON_SECURE_INTERRUPT_ACCESS_ENABLED                   _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_DATA_PREFETCH_SHIFT                   _MK_SHIFT_CONST(28)
+#define PL310_AUXILIARY_CONTROL_0_DATA_PREFETCH_FIELD                   (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_DATA_PREFETCH_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_DATA_PREFETCH_RANGE                   28:28
+#define PL310_AUXILIARY_CONTROL_0_DATA_PREFETCH_WOFFSET                 0x0
+#define PL310_AUXILIARY_CONTROL_0_DATA_PREFETCH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_DATA_PREFETCH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_DATA_PREFETCH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_DATA_PREFETCH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_DATA_PREFETCH_DISABLED                        _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_DATA_PREFETCH_ENABLED                 _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_INSTRUCTION_PREFETCH_SHIFT                    _MK_SHIFT_CONST(29)
+#define PL310_AUXILIARY_CONTROL_0_INSTRUCTION_PREFETCH_FIELD                    (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_INSTRUCTION_PREFETCH_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_INSTRUCTION_PREFETCH_RANGE                    29:29
+#define PL310_AUXILIARY_CONTROL_0_INSTRUCTION_PREFETCH_WOFFSET                  0x0
+#define PL310_AUXILIARY_CONTROL_0_INSTRUCTION_PREFETCH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_INSTRUCTION_PREFETCH_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_INSTRUCTION_PREFETCH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_INSTRUCTION_PREFETCH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_INSTRUCTION_PREFETCH_DISABLED                 _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_INSTRUCTION_PREFETCH_ENABLED                  _MK_ENUM_CONST(1)
+
+#define PL310_AUXILIARY_CONTROL_0_EARLY_BRESP_SHIFT                     _MK_SHIFT_CONST(30)
+#define PL310_AUXILIARY_CONTROL_0_EARLY_BRESP_FIELD                     (_MK_MASK_CONST(0x1) << PL310_AUXILIARY_CONTROL_0_EARLY_BRESP_SHIFT)
+#define PL310_AUXILIARY_CONTROL_0_EARLY_BRESP_RANGE                     30:30
+#define PL310_AUXILIARY_CONTROL_0_EARLY_BRESP_WOFFSET                   0x0
+#define PL310_AUXILIARY_CONTROL_0_EARLY_BRESP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_EARLY_BRESP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_AUXILIARY_CONTROL_0_EARLY_BRESP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_EARLY_BRESP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_AUXILIARY_CONTROL_0_EARLY_BRESP_DISABLED                  _MK_ENUM_CONST(0)
+#define PL310_AUXILIARY_CONTROL_0_EARLY_BRESP_ENABLED                   _MK_ENUM_CONST(1)
+
+
+// Register PL310_TAG_RAM_LATENCY_0  
+#define PL310_TAG_RAM_LATENCY_0                 _MK_ADDR_CONST(0x108)
+#define PL310_TAG_RAM_LATENCY_0_SECURE                  0x0
+#define PL310_TAG_RAM_LATENCY_0_WORD_COUNT                      0x1
+#define PL310_TAG_RAM_LATENCY_0_RESET_VAL                       _MK_MASK_CONST(0x777)
+#define PL310_TAG_RAM_LATENCY_0_RESET_MASK                      _MK_MASK_CONST(0x777)
+#define PL310_TAG_RAM_LATENCY_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x331)
+#define PL310_TAG_RAM_LATENCY_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x777)
+#define PL310_TAG_RAM_LATENCY_0_READ_MASK                       _MK_MASK_CONST(0x777)
+#define PL310_TAG_RAM_LATENCY_0_WRITE_MASK                      _MK_MASK_CONST(0x777)
+#define PL310_TAG_RAM_LATENCY_0_SETUP_SHIFT                     _MK_SHIFT_CONST(0)
+#define PL310_TAG_RAM_LATENCY_0_SETUP_FIELD                     (_MK_MASK_CONST(0x7) << PL310_TAG_RAM_LATENCY_0_SETUP_SHIFT)
+#define PL310_TAG_RAM_LATENCY_0_SETUP_RANGE                     2:0
+#define PL310_TAG_RAM_LATENCY_0_SETUP_WOFFSET                   0x0
+#define PL310_TAG_RAM_LATENCY_0_SETUP_DEFAULT                   _MK_MASK_CONST(0x7)
+#define PL310_TAG_RAM_LATENCY_0_SETUP_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define PL310_TAG_RAM_LATENCY_0_SETUP_SW_DEFAULT                        _MK_MASK_CONST(0x1)
+#define PL310_TAG_RAM_LATENCY_0_SETUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+
+#define PL310_TAG_RAM_LATENCY_0_READ_SHIFT                      _MK_SHIFT_CONST(4)
+#define PL310_TAG_RAM_LATENCY_0_READ_FIELD                      (_MK_MASK_CONST(0x7) << PL310_TAG_RAM_LATENCY_0_READ_SHIFT)
+#define PL310_TAG_RAM_LATENCY_0_READ_RANGE                      6:4
+#define PL310_TAG_RAM_LATENCY_0_READ_WOFFSET                    0x0
+#define PL310_TAG_RAM_LATENCY_0_READ_DEFAULT                    _MK_MASK_CONST(0x7)
+#define PL310_TAG_RAM_LATENCY_0_READ_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define PL310_TAG_RAM_LATENCY_0_READ_SW_DEFAULT                 _MK_MASK_CONST(0x3)
+#define PL310_TAG_RAM_LATENCY_0_READ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+
+#define PL310_TAG_RAM_LATENCY_0_WRITE_SHIFT                     _MK_SHIFT_CONST(8)
+#define PL310_TAG_RAM_LATENCY_0_WRITE_FIELD                     (_MK_MASK_CONST(0x7) << PL310_TAG_RAM_LATENCY_0_WRITE_SHIFT)
+#define PL310_TAG_RAM_LATENCY_0_WRITE_RANGE                     10:8
+#define PL310_TAG_RAM_LATENCY_0_WRITE_WOFFSET                   0x0
+#define PL310_TAG_RAM_LATENCY_0_WRITE_DEFAULT                   _MK_MASK_CONST(0x7)
+#define PL310_TAG_RAM_LATENCY_0_WRITE_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define PL310_TAG_RAM_LATENCY_0_WRITE_SW_DEFAULT                        _MK_MASK_CONST(0x3)
+#define PL310_TAG_RAM_LATENCY_0_WRITE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+
+
+// Register PL310_DATA_RAM_LATENCY_0  
+#define PL310_DATA_RAM_LATENCY_0                        _MK_ADDR_CONST(0x10c)
+#define PL310_DATA_RAM_LATENCY_0_SECURE                         0x0
+#define PL310_DATA_RAM_LATENCY_0_WORD_COUNT                     0x1
+#define PL310_DATA_RAM_LATENCY_0_RESET_VAL                      _MK_MASK_CONST(0x777)
+#define PL310_DATA_RAM_LATENCY_0_RESET_MASK                     _MK_MASK_CONST(0x777)
+#define PL310_DATA_RAM_LATENCY_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x441)
+#define PL310_DATA_RAM_LATENCY_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x777)
+#define PL310_DATA_RAM_LATENCY_0_READ_MASK                      _MK_MASK_CONST(0x777)
+#define PL310_DATA_RAM_LATENCY_0_WRITE_MASK                     _MK_MASK_CONST(0x777)
+#define PL310_DATA_RAM_LATENCY_0_SETUP_SHIFT                    _MK_SHIFT_CONST(0)
+#define PL310_DATA_RAM_LATENCY_0_SETUP_FIELD                    (_MK_MASK_CONST(0x7) << PL310_DATA_RAM_LATENCY_0_SETUP_SHIFT)
+#define PL310_DATA_RAM_LATENCY_0_SETUP_RANGE                    2:0
+#define PL310_DATA_RAM_LATENCY_0_SETUP_WOFFSET                  0x0
+#define PL310_DATA_RAM_LATENCY_0_SETUP_DEFAULT                  _MK_MASK_CONST(0x7)
+#define PL310_DATA_RAM_LATENCY_0_SETUP_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define PL310_DATA_RAM_LATENCY_0_SETUP_SW_DEFAULT                       _MK_MASK_CONST(0x1)
+#define PL310_DATA_RAM_LATENCY_0_SETUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+
+#define PL310_DATA_RAM_LATENCY_0_READ_SHIFT                     _MK_SHIFT_CONST(4)
+#define PL310_DATA_RAM_LATENCY_0_READ_FIELD                     (_MK_MASK_CONST(0x7) << PL310_DATA_RAM_LATENCY_0_READ_SHIFT)
+#define PL310_DATA_RAM_LATENCY_0_READ_RANGE                     6:4
+#define PL310_DATA_RAM_LATENCY_0_READ_WOFFSET                   0x0
+#define PL310_DATA_RAM_LATENCY_0_READ_DEFAULT                   _MK_MASK_CONST(0x7)
+#define PL310_DATA_RAM_LATENCY_0_READ_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define PL310_DATA_RAM_LATENCY_0_READ_SW_DEFAULT                        _MK_MASK_CONST(0x4)
+#define PL310_DATA_RAM_LATENCY_0_READ_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+
+#define PL310_DATA_RAM_LATENCY_0_WRITE_SHIFT                    _MK_SHIFT_CONST(8)
+#define PL310_DATA_RAM_LATENCY_0_WRITE_FIELD                    (_MK_MASK_CONST(0x7) << PL310_DATA_RAM_LATENCY_0_WRITE_SHIFT)
+#define PL310_DATA_RAM_LATENCY_0_WRITE_RANGE                    10:8
+#define PL310_DATA_RAM_LATENCY_0_WRITE_WOFFSET                  0x0
+#define PL310_DATA_RAM_LATENCY_0_WRITE_DEFAULT                  _MK_MASK_CONST(0x7)
+#define PL310_DATA_RAM_LATENCY_0_WRITE_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define PL310_DATA_RAM_LATENCY_0_WRITE_SW_DEFAULT                       _MK_MASK_CONST(0x4)
+#define PL310_DATA_RAM_LATENCY_0_WRITE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+
+
+// Register PL310_EVENT_COUNTER_CONTROL_0  
+#define PL310_EVENT_COUNTER_CONTROL_0                   _MK_ADDR_CONST(0x200)
+#define PL310_EVENT_COUNTER_CONTROL_0_SECURE                    0x0
+#define PL310_EVENT_COUNTER_CONTROL_0_WORD_COUNT                        0x1
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x7)
+#define PL310_EVENT_COUNTER_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x7)
+#define PL310_EVENT_COUNTER_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
+#define PL310_EVENT_COUNTER_CONTROL_0_EVENT_COUNTING_SHIFT                      _MK_SHIFT_CONST(0)
+#define PL310_EVENT_COUNTER_CONTROL_0_EVENT_COUNTING_FIELD                      (_MK_MASK_CONST(0x1) << PL310_EVENT_COUNTER_CONTROL_0_EVENT_COUNTING_SHIFT)
+#define PL310_EVENT_COUNTER_CONTROL_0_EVENT_COUNTING_RANGE                      0:0
+#define PL310_EVENT_COUNTER_CONTROL_0_EVENT_COUNTING_WOFFSET                    0x0
+#define PL310_EVENT_COUNTER_CONTROL_0_EVENT_COUNTING_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_EVENT_COUNTING_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define PL310_EVENT_COUNTER_CONTROL_0_EVENT_COUNTING_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_EVENT_COUNTING_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_EVENT_COUNTING_DISABLED                   _MK_ENUM_CONST(0)
+#define PL310_EVENT_COUNTER_CONTROL_0_EVENT_COUNTING_ENABLED                    _MK_ENUM_CONST(1)
+
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_0_SHIFT                     _MK_SHIFT_CONST(1)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_0_FIELD                     (_MK_MASK_CONST(0x1) << PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_0_SHIFT)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_0_RANGE                     1:1
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_0_WOFFSET                   0x0
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_0_CLEAR_COUNTER                     _MK_ENUM_CONST(1)
+
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_1_SHIFT                     _MK_SHIFT_CONST(2)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_1_FIELD                     (_MK_MASK_CONST(0x1) << PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_1_SHIFT)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_1_RANGE                     2:2
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_1_WOFFSET                   0x0
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER_CONTROL_0_RESET_COUNTER_1_CLEAR_COUNTER                     _MK_ENUM_CONST(1)
+
+
+// Register PL310_EVENT_COUNTER1_CONFIGURATION_0  
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0                    _MK_ADDR_CONST(0x204)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_SECURE                     0x0
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_WORD_COUNT                         0x1
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_READ_MASK                  _MK_MASK_CONST(0x3f)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_SHIFT                    _MK_SHIFT_CONST(0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_FIELD                    (_MK_MASK_CONST(0x3) << PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_SHIFT)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_RANGE                    1:0
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_WOFFSET                  0x0
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_DISABLED                 _MK_ENUM_CONST(0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_ENABLED_INCREMENT                        _MK_ENUM_CONST(1)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_ENABLED_OVERFLOW                 _MK_ENUM_CONST(2)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_COUNTER_INTERRUPT_RES_DISABLED                     _MK_ENUM_CONST(3)
+
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_SHIFT                 _MK_SHIFT_CONST(2)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_FIELD                 (_MK_MASK_CONST(0xf) << PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_SHIFT)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_RANGE                 5:2
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_WOFFSET                       0x0
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_DISABLED                      _MK_ENUM_CONST(0)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_CO                    _MK_ENUM_CONST(1)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_EVICT                 _MK_ENUM_CONST(1)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_DRHIT                 _MK_ENUM_CONST(2)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_DRREQ                 _MK_ENUM_CONST(3)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_DWHIT                 _MK_ENUM_CONST(4)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_DWREQ                 _MK_ENUM_CONST(5)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_DWTREQ                        _MK_ENUM_CONST(6)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_IRHIT                 _MK_ENUM_CONST(7)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_IRREQ                 _MK_ENUM_CONST(8)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_WA                    _MK_ENUM_CONST(9)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_PF                    _MK_ENUM_CONST(10)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_RES_DISABLED_B                        _MK_ENUM_CONST(11)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_RES_DISABLED_C                        _MK_ENUM_CONST(12)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_RES_DISABLED_D                        _MK_ENUM_CONST(13)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_RES_DISABLED_E                        _MK_ENUM_CONST(14)
+#define PL310_EVENT_COUNTER1_CONFIGURATION_0_EVENT_SOURCE_RES_DISABLED_F                        _MK_ENUM_CONST(15)
+
+
+// Register PL310_EVENT_COUNTER0_CONFIGURATION_0  
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0                    _MK_ADDR_CONST(0x208)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_SECURE                     0x0
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_WORD_COUNT                         0x1
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_RESET_MASK                         _MK_MASK_CONST(0x3f)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_READ_MASK                  _MK_MASK_CONST(0x3f)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_SHIFT                    _MK_SHIFT_CONST(0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_FIELD                    (_MK_MASK_CONST(0x3) << PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_SHIFT)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_RANGE                    1:0
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_WOFFSET                  0x0
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_DISABLED                 _MK_ENUM_CONST(0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_ENABLED_INCREMENT                        _MK_ENUM_CONST(1)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_ENABLED_OVERFLOW                 _MK_ENUM_CONST(2)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_COUNTER_INTERRUPT_RES_DISABLED                     _MK_ENUM_CONST(3)
+
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_SHIFT                 _MK_SHIFT_CONST(2)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_FIELD                 (_MK_MASK_CONST(0xf) << PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_SHIFT)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_RANGE                 5:2
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_WOFFSET                       0x0
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_DISABLED                      _MK_ENUM_CONST(0)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_CO                    _MK_ENUM_CONST(1)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_EVICT                 _MK_ENUM_CONST(1)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_DRHIT                 _MK_ENUM_CONST(2)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_DRREQ                 _MK_ENUM_CONST(3)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_DWHIT                 _MK_ENUM_CONST(4)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_DWREQ                 _MK_ENUM_CONST(5)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_DWTREQ                        _MK_ENUM_CONST(6)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_IRHIT                 _MK_ENUM_CONST(7)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_IRREQ                 _MK_ENUM_CONST(8)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_WA                    _MK_ENUM_CONST(9)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_PF                    _MK_ENUM_CONST(10)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_RES_DISABLED_B                        _MK_ENUM_CONST(11)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_RES_DISABLED_C                        _MK_ENUM_CONST(12)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_RES_DISABLED_D                        _MK_ENUM_CONST(13)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_RES_DISABLED_E                        _MK_ENUM_CONST(14)
+#define PL310_EVENT_COUNTER0_CONFIGURATION_0_EVENT_SOURCE_RES_DISABLED_F                        _MK_ENUM_CONST(15)
+
+
+// Register PL310_EVENT_COUNTER1_0  
+#define PL310_EVENT_COUNTER1_0                  _MK_ADDR_CONST(0x20c)
+#define PL310_EVENT_COUNTER1_0_SECURE                   0x0
+#define PL310_EVENT_COUNTER1_0_WORD_COUNT                       0x1
+#define PL310_EVENT_COUNTER1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define PL310_EVENT_COUNTER1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define PL310_EVENT_COUNTER1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define PL310_EVENT_COUNTER1_0_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
+#define PL310_EVENT_COUNTER1_0_VALUE_FIELD                      (_MK_MASK_CONST(0xffffffff) << PL310_EVENT_COUNTER1_0_VALUE_SHIFT)
+#define PL310_EVENT_COUNTER1_0_VALUE_RANGE                      31:0
+#define PL310_EVENT_COUNTER1_0_VALUE_WOFFSET                    0x0
+#define PL310_EVENT_COUNTER1_0_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_0_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define PL310_EVENT_COUNTER1_0_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER1_0_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register PL310_EVENT_COUNTER0_0  
+#define PL310_EVENT_COUNTER0_0                  _MK_ADDR_CONST(0x210)
+#define PL310_EVENT_COUNTER0_0_SECURE                   0x0
+#define PL310_EVENT_COUNTER0_0_WORD_COUNT                       0x1
+#define PL310_EVENT_COUNTER0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define PL310_EVENT_COUNTER0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define PL310_EVENT_COUNTER0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define PL310_EVENT_COUNTER0_0_VALUE_SHIFT                      _MK_SHIFT_CONST(0)
+#define PL310_EVENT_COUNTER0_0_VALUE_FIELD                      (_MK_MASK_CONST(0xffffffff) << PL310_EVENT_COUNTER0_0_VALUE_SHIFT)
+#define PL310_EVENT_COUNTER0_0_VALUE_RANGE                      31:0
+#define PL310_EVENT_COUNTER0_0_VALUE_WOFFSET                    0x0
+#define PL310_EVENT_COUNTER0_0_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_0_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define PL310_EVENT_COUNTER0_0_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_EVENT_COUNTER0_0_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register PL310_INTERRUPT_MASK_0  
+#define PL310_INTERRUPT_MASK_0                  _MK_ADDR_CONST(0x214)
+#define PL310_INTERRUPT_MASK_0_SECURE                   0x0
+#define PL310_INTERRUPT_MASK_0_WORD_COUNT                       0x1
+#define PL310_INTERRUPT_MASK_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_RESET_MASK                       _MK_MASK_CONST(0x1ff)
+#define PL310_INTERRUPT_MASK_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
+#define PL310_INTERRUPT_MASK_0_WRITE_MASK                       _MK_MASK_CONST(0x1ff)
+#define PL310_INTERRUPT_MASK_0_ECNTR_SHIFT                      _MK_SHIFT_CONST(0)
+#define PL310_INTERRUPT_MASK_0_ECNTR_FIELD                      (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_MASK_0_ECNTR_SHIFT)
+#define PL310_INTERRUPT_MASK_0_ECNTR_RANGE                      0:0
+#define PL310_INTERRUPT_MASK_0_ECNTR_WOFFSET                    0x0
+#define PL310_INTERRUPT_MASK_0_ECNTR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_ECNTR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_MASK_0_ECNTR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_ECNTR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_MASK_0_PARRT_SHIFT                      _MK_SHIFT_CONST(1)
+#define PL310_INTERRUPT_MASK_0_PARRT_FIELD                      (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_MASK_0_PARRT_SHIFT)
+#define PL310_INTERRUPT_MASK_0_PARRT_RANGE                      1:1
+#define PL310_INTERRUPT_MASK_0_PARRT_WOFFSET                    0x0
+#define PL310_INTERRUPT_MASK_0_PARRT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_PARRT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_MASK_0_PARRT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_PARRT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_MASK_0_PARRD_SHIFT                      _MK_SHIFT_CONST(2)
+#define PL310_INTERRUPT_MASK_0_PARRD_FIELD                      (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_MASK_0_PARRD_SHIFT)
+#define PL310_INTERRUPT_MASK_0_PARRD_RANGE                      2:2
+#define PL310_INTERRUPT_MASK_0_PARRD_WOFFSET                    0x0
+#define PL310_INTERRUPT_MASK_0_PARRD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_PARRD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_MASK_0_PARRD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_PARRD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_MASK_0_ERRWT_SHIFT                      _MK_SHIFT_CONST(3)
+#define PL310_INTERRUPT_MASK_0_ERRWT_FIELD                      (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_MASK_0_ERRWT_SHIFT)
+#define PL310_INTERRUPT_MASK_0_ERRWT_RANGE                      3:3
+#define PL310_INTERRUPT_MASK_0_ERRWT_WOFFSET                    0x0
+#define PL310_INTERRUPT_MASK_0_ERRWT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_ERRWT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_MASK_0_ERRWT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_ERRWT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_MASK_0_ERRWD_SHIFT                      _MK_SHIFT_CONST(4)
+#define PL310_INTERRUPT_MASK_0_ERRWD_FIELD                      (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_MASK_0_ERRWD_SHIFT)
+#define PL310_INTERRUPT_MASK_0_ERRWD_RANGE                      4:4
+#define PL310_INTERRUPT_MASK_0_ERRWD_WOFFSET                    0x0
+#define PL310_INTERRUPT_MASK_0_ERRWD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_ERRWD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_MASK_0_ERRWD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_ERRWD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_MASK_0_ERRRT_SHIFT                      _MK_SHIFT_CONST(5)
+#define PL310_INTERRUPT_MASK_0_ERRRT_FIELD                      (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_MASK_0_ERRRT_SHIFT)
+#define PL310_INTERRUPT_MASK_0_ERRRT_RANGE                      5:5
+#define PL310_INTERRUPT_MASK_0_ERRRT_WOFFSET                    0x0
+#define PL310_INTERRUPT_MASK_0_ERRRT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_ERRRT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_MASK_0_ERRRT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_ERRRT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_MASK_0_ERRRD_SHIFT                      _MK_SHIFT_CONST(6)
+#define PL310_INTERRUPT_MASK_0_ERRRD_FIELD                      (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_MASK_0_ERRRD_SHIFT)
+#define PL310_INTERRUPT_MASK_0_ERRRD_RANGE                      6:6
+#define PL310_INTERRUPT_MASK_0_ERRRD_WOFFSET                    0x0
+#define PL310_INTERRUPT_MASK_0_ERRRD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_ERRRD_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_MASK_0_ERRRD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_ERRRD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_MASK_0_SLVERR_SHIFT                     _MK_SHIFT_CONST(7)
+#define PL310_INTERRUPT_MASK_0_SLVERR_FIELD                     (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_MASK_0_SLVERR_SHIFT)
+#define PL310_INTERRUPT_MASK_0_SLVERR_RANGE                     7:7
+#define PL310_INTERRUPT_MASK_0_SLVERR_WOFFSET                   0x0
+#define PL310_INTERRUPT_MASK_0_SLVERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_SLVERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_MASK_0_SLVERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_SLVERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_MASK_0_DECERR_SHIFT                     _MK_SHIFT_CONST(8)
+#define PL310_INTERRUPT_MASK_0_DECERR_FIELD                     (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_MASK_0_DECERR_SHIFT)
+#define PL310_INTERRUPT_MASK_0_DECERR_RANGE                     8:8
+#define PL310_INTERRUPT_MASK_0_DECERR_WOFFSET                   0x0
+#define PL310_INTERRUPT_MASK_0_DECERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_DECERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_MASK_0_DECERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_MASK_0_DECERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register PL310_MASKED_INTERRUPT_STATUS_0  
+#define PL310_MASKED_INTERRUPT_STATUS_0                 _MK_ADDR_CONST(0x218)
+#define PL310_MASKED_INTERRUPT_STATUS_0_SECURE                  0x0
+#define PL310_MASKED_INTERRUPT_STATUS_0_WORD_COUNT                      0x1
+#define PL310_MASKED_INTERRUPT_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x1ff)
+#define PL310_MASKED_INTERRUPT_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x1ff)
+#define PL310_MASKED_INTERRUPT_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ECNTR_SHIFT                     _MK_SHIFT_CONST(0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ECNTR_FIELD                     (_MK_MASK_CONST(0x1) << PL310_MASKED_INTERRUPT_STATUS_0_ECNTR_SHIFT)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ECNTR_RANGE                     0:0
+#define PL310_MASKED_INTERRUPT_STATUS_0_ECNTR_WOFFSET                   0x0
+#define PL310_MASKED_INTERRUPT_STATUS_0_ECNTR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ECNTR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ECNTR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ECNTR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRT_SHIFT                     _MK_SHIFT_CONST(1)
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRT_FIELD                     (_MK_MASK_CONST(0x1) << PL310_MASKED_INTERRUPT_STATUS_0_PARRT_SHIFT)
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRT_RANGE                     1:1
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRT_WOFFSET                   0x0
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRD_SHIFT                     _MK_SHIFT_CONST(2)
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRD_FIELD                     (_MK_MASK_CONST(0x1) << PL310_MASKED_INTERRUPT_STATUS_0_PARRD_SHIFT)
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRD_RANGE                     2:2
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRD_WOFFSET                   0x0
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_PARRD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWT_SHIFT                     _MK_SHIFT_CONST(3)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWT_FIELD                     (_MK_MASK_CONST(0x1) << PL310_MASKED_INTERRUPT_STATUS_0_ERRWT_SHIFT)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWT_RANGE                     3:3
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWT_WOFFSET                   0x0
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWD_SHIFT                     _MK_SHIFT_CONST(4)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWD_FIELD                     (_MK_MASK_CONST(0x1) << PL310_MASKED_INTERRUPT_STATUS_0_ERRWD_SHIFT)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWD_RANGE                     4:4
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWD_WOFFSET                   0x0
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRWD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRT_SHIFT                     _MK_SHIFT_CONST(5)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRT_FIELD                     (_MK_MASK_CONST(0x1) << PL310_MASKED_INTERRUPT_STATUS_0_ERRRT_SHIFT)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRT_RANGE                     5:5
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRT_WOFFSET                   0x0
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRD_SHIFT                     _MK_SHIFT_CONST(6)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRD_FIELD                     (_MK_MASK_CONST(0x1) << PL310_MASKED_INTERRUPT_STATUS_0_ERRRD_SHIFT)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRD_RANGE                     6:6
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRD_WOFFSET                   0x0
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_ERRRD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_MASKED_INTERRUPT_STATUS_0_SLVERR_SHIFT                    _MK_SHIFT_CONST(7)
+#define PL310_MASKED_INTERRUPT_STATUS_0_SLVERR_FIELD                    (_MK_MASK_CONST(0x1) << PL310_MASKED_INTERRUPT_STATUS_0_SLVERR_SHIFT)
+#define PL310_MASKED_INTERRUPT_STATUS_0_SLVERR_RANGE                    7:7
+#define PL310_MASKED_INTERRUPT_STATUS_0_SLVERR_WOFFSET                  0x0
+#define PL310_MASKED_INTERRUPT_STATUS_0_SLVERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_SLVERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PL310_MASKED_INTERRUPT_STATUS_0_SLVERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_SLVERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define PL310_MASKED_INTERRUPT_STATUS_0_DECERR_SHIFT                    _MK_SHIFT_CONST(8)
+#define PL310_MASKED_INTERRUPT_STATUS_0_DECERR_FIELD                    (_MK_MASK_CONST(0x1) << PL310_MASKED_INTERRUPT_STATUS_0_DECERR_SHIFT)
+#define PL310_MASKED_INTERRUPT_STATUS_0_DECERR_RANGE                    8:8
+#define PL310_MASKED_INTERRUPT_STATUS_0_DECERR_WOFFSET                  0x0
+#define PL310_MASKED_INTERRUPT_STATUS_0_DECERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_DECERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PL310_MASKED_INTERRUPT_STATUS_0_DECERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_MASKED_INTERRUPT_STATUS_0_DECERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register PL310_RAW_INTERRUPT_STATUS_0  
+#define PL310_RAW_INTERRUPT_STATUS_0                    _MK_ADDR_CONST(0x21c)
+#define PL310_RAW_INTERRUPT_STATUS_0_SECURE                     0x0
+#define PL310_RAW_INTERRUPT_STATUS_0_WORD_COUNT                         0x1
+#define PL310_RAW_INTERRUPT_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x1ff)
+#define PL310_RAW_INTERRUPT_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
+#define PL310_RAW_INTERRUPT_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ECNTR_SHIFT                        _MK_SHIFT_CONST(0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ECNTR_FIELD                        (_MK_MASK_CONST(0x1) << PL310_RAW_INTERRUPT_STATUS_0_ECNTR_SHIFT)
+#define PL310_RAW_INTERRUPT_STATUS_0_ECNTR_RANGE                        0:0
+#define PL310_RAW_INTERRUPT_STATUS_0_ECNTR_WOFFSET                      0x0
+#define PL310_RAW_INTERRUPT_STATUS_0_ECNTR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ECNTR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_RAW_INTERRUPT_STATUS_0_ECNTR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ECNTR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRT_SHIFT                        _MK_SHIFT_CONST(1)
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRT_FIELD                        (_MK_MASK_CONST(0x1) << PL310_RAW_INTERRUPT_STATUS_0_PARRT_SHIFT)
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRT_RANGE                        1:1
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRT_WOFFSET                      0x0
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRD_SHIFT                        _MK_SHIFT_CONST(2)
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRD_FIELD                        (_MK_MASK_CONST(0x1) << PL310_RAW_INTERRUPT_STATUS_0_PARRD_SHIFT)
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRD_RANGE                        2:2
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRD_WOFFSET                      0x0
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_PARRD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWT_SHIFT                        _MK_SHIFT_CONST(3)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWT_FIELD                        (_MK_MASK_CONST(0x1) << PL310_RAW_INTERRUPT_STATUS_0_ERRWT_SHIFT)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWT_RANGE                        3:3
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWT_WOFFSET                      0x0
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWD_SHIFT                        _MK_SHIFT_CONST(4)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWD_FIELD                        (_MK_MASK_CONST(0x1) << PL310_RAW_INTERRUPT_STATUS_0_ERRWD_SHIFT)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWD_RANGE                        4:4
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWD_WOFFSET                      0x0
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRWD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRT_SHIFT                        _MK_SHIFT_CONST(5)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRT_FIELD                        (_MK_MASK_CONST(0x1) << PL310_RAW_INTERRUPT_STATUS_0_ERRRT_SHIFT)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRT_RANGE                        5:5
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRT_WOFFSET                      0x0
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRD_SHIFT                        _MK_SHIFT_CONST(6)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRD_FIELD                        (_MK_MASK_CONST(0x1) << PL310_RAW_INTERRUPT_STATUS_0_ERRRD_SHIFT)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRD_RANGE                        6:6
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRD_WOFFSET                      0x0
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_ERRRD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define PL310_RAW_INTERRUPT_STATUS_0_SLVERR_SHIFT                       _MK_SHIFT_CONST(7)
+#define PL310_RAW_INTERRUPT_STATUS_0_SLVERR_FIELD                       (_MK_MASK_CONST(0x1) << PL310_RAW_INTERRUPT_STATUS_0_SLVERR_SHIFT)
+#define PL310_RAW_INTERRUPT_STATUS_0_SLVERR_RANGE                       7:7
+#define PL310_RAW_INTERRUPT_STATUS_0_SLVERR_WOFFSET                     0x0
+#define PL310_RAW_INTERRUPT_STATUS_0_SLVERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_SLVERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define PL310_RAW_INTERRUPT_STATUS_0_SLVERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_SLVERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define PL310_RAW_INTERRUPT_STATUS_0_DECERR_SHIFT                       _MK_SHIFT_CONST(8)
+#define PL310_RAW_INTERRUPT_STATUS_0_DECERR_FIELD                       (_MK_MASK_CONST(0x1) << PL310_RAW_INTERRUPT_STATUS_0_DECERR_SHIFT)
+#define PL310_RAW_INTERRUPT_STATUS_0_DECERR_RANGE                       8:8
+#define PL310_RAW_INTERRUPT_STATUS_0_DECERR_WOFFSET                     0x0
+#define PL310_RAW_INTERRUPT_STATUS_0_DECERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_DECERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define PL310_RAW_INTERRUPT_STATUS_0_DECERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_RAW_INTERRUPT_STATUS_0_DECERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register PL310_INTERRUPT_CLEAR_0  
+#define PL310_INTERRUPT_CLEAR_0                 _MK_ADDR_CONST(0x220)
+#define PL310_INTERRUPT_CLEAR_0_SECURE                  0x0
+#define PL310_INTERRUPT_CLEAR_0_WORD_COUNT                      0x1
+#define PL310_INTERRUPT_CLEAR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_RESET_MASK                      _MK_MASK_CONST(0x1ff)
+#define PL310_INTERRUPT_CLEAR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_READ_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_WRITE_MASK                      _MK_MASK_CONST(0x1ff)
+#define PL310_INTERRUPT_CLEAR_0_ECNTR_SHIFT                     _MK_SHIFT_CONST(0)
+#define PL310_INTERRUPT_CLEAR_0_ECNTR_FIELD                     (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_CLEAR_0_ECNTR_SHIFT)
+#define PL310_INTERRUPT_CLEAR_0_ECNTR_RANGE                     0:0
+#define PL310_INTERRUPT_CLEAR_0_ECNTR_WOFFSET                   0x0
+#define PL310_INTERRUPT_CLEAR_0_ECNTR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_ECNTR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_CLEAR_0_ECNTR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_ECNTR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_CLEAR_0_PARRT_SHIFT                     _MK_SHIFT_CONST(1)
+#define PL310_INTERRUPT_CLEAR_0_PARRT_FIELD                     (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_CLEAR_0_PARRT_SHIFT)
+#define PL310_INTERRUPT_CLEAR_0_PARRT_RANGE                     1:1
+#define PL310_INTERRUPT_CLEAR_0_PARRT_WOFFSET                   0x0
+#define PL310_INTERRUPT_CLEAR_0_PARRT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_PARRT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_CLEAR_0_PARRT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_PARRT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_CLEAR_0_PARRD_SHIFT                     _MK_SHIFT_CONST(2)
+#define PL310_INTERRUPT_CLEAR_0_PARRD_FIELD                     (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_CLEAR_0_PARRD_SHIFT)
+#define PL310_INTERRUPT_CLEAR_0_PARRD_RANGE                     2:2
+#define PL310_INTERRUPT_CLEAR_0_PARRD_WOFFSET                   0x0
+#define PL310_INTERRUPT_CLEAR_0_PARRD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_PARRD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_CLEAR_0_PARRD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_PARRD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_CLEAR_0_ERRWT_SHIFT                     _MK_SHIFT_CONST(3)
+#define PL310_INTERRUPT_CLEAR_0_ERRWT_FIELD                     (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_CLEAR_0_ERRWT_SHIFT)
+#define PL310_INTERRUPT_CLEAR_0_ERRWT_RANGE                     3:3
+#define PL310_INTERRUPT_CLEAR_0_ERRWT_WOFFSET                   0x0
+#define PL310_INTERRUPT_CLEAR_0_ERRWT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_ERRWT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_CLEAR_0_ERRWT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_ERRWT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_CLEAR_0_ERRWD_SHIFT                     _MK_SHIFT_CONST(4)
+#define PL310_INTERRUPT_CLEAR_0_ERRWD_FIELD                     (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_CLEAR_0_ERRWD_SHIFT)
+#define PL310_INTERRUPT_CLEAR_0_ERRWD_RANGE                     4:4
+#define PL310_INTERRUPT_CLEAR_0_ERRWD_WOFFSET                   0x0
+#define PL310_INTERRUPT_CLEAR_0_ERRWD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_ERRWD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_CLEAR_0_ERRWD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_ERRWD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_CLEAR_0_ERRRT_SHIFT                     _MK_SHIFT_CONST(5)
+#define PL310_INTERRUPT_CLEAR_0_ERRRT_FIELD                     (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_CLEAR_0_ERRRT_SHIFT)
+#define PL310_INTERRUPT_CLEAR_0_ERRRT_RANGE                     5:5
+#define PL310_INTERRUPT_CLEAR_0_ERRRT_WOFFSET                   0x0
+#define PL310_INTERRUPT_CLEAR_0_ERRRT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_ERRRT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_CLEAR_0_ERRRT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_ERRRT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_CLEAR_0_ERRRD_SHIFT                     _MK_SHIFT_CONST(6)
+#define PL310_INTERRUPT_CLEAR_0_ERRRD_FIELD                     (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_CLEAR_0_ERRRD_SHIFT)
+#define PL310_INTERRUPT_CLEAR_0_ERRRD_RANGE                     6:6
+#define PL310_INTERRUPT_CLEAR_0_ERRRD_WOFFSET                   0x0
+#define PL310_INTERRUPT_CLEAR_0_ERRRD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_ERRRD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_CLEAR_0_ERRRD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_ERRRD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_CLEAR_0_SLVERR_SHIFT                    _MK_SHIFT_CONST(7)
+#define PL310_INTERRUPT_CLEAR_0_SLVERR_FIELD                    (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_CLEAR_0_SLVERR_SHIFT)
+#define PL310_INTERRUPT_CLEAR_0_SLVERR_RANGE                    7:7
+#define PL310_INTERRUPT_CLEAR_0_SLVERR_WOFFSET                  0x0
+#define PL310_INTERRUPT_CLEAR_0_SLVERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_SLVERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_CLEAR_0_SLVERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_SLVERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define PL310_INTERRUPT_CLEAR_0_DECERR_SHIFT                    _MK_SHIFT_CONST(8)
+#define PL310_INTERRUPT_CLEAR_0_DECERR_FIELD                    (_MK_MASK_CONST(0x1) << PL310_INTERRUPT_CLEAR_0_DECERR_SHIFT)
+#define PL310_INTERRUPT_CLEAR_0_DECERR_RANGE                    8:8
+#define PL310_INTERRUPT_CLEAR_0_DECERR_WOFFSET                  0x0
+#define PL310_INTERRUPT_CLEAR_0_DECERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_DECERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PL310_INTERRUPT_CLEAR_0_DECERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_INTERRUPT_CLEAR_0_DECERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 768 [0x300] 
+
+// Reserved address 1024 [0x400] 
+
+// Reserved address 1280 [0x500] 
+
+// Reserved address 1536 [0x600] 
+
+// Reserved address 1792 [0x700] 
+
+// Reserved address 1793 [0x701] 
+
+// Reserved address 1794 [0x702] 
+
+// Reserved address 1795 [0x703] 
+
+// Reserved address 1796 [0x704] 
+
+// Reserved address 1797 [0x705] 
+
+// Reserved address 1798 [0x706] 
+
+// Reserved address 1799 [0x707] 
+
+// Reserved address 1800 [0x708] 
+
+// Reserved address 1801 [0x709] 
+
+// Reserved address 1802 [0x70a] 
+
+// Reserved address 1803 [0x70b] 
+
+// Reserved address 1804 [0x70c] 
+
+// Reserved address 1805 [0x70d] 
+
+// Reserved address 1806 [0x70e] 
+
+// Reserved address 1807 [0x70f] 
+
+// Reserved address 1808 [0x710] 
+
+// Reserved address 1809 [0x711] 
+
+// Reserved address 1810 [0x712] 
+
+// Reserved address 1811 [0x713] 
+
+// Reserved address 1812 [0x714] 
+
+// Reserved address 1813 [0x715] 
+
+// Reserved address 1814 [0x716] 
+
+// Reserved address 1815 [0x717] 
+
+// Reserved address 1816 [0x718] 
+
+// Reserved address 1817 [0x719] 
+
+// Reserved address 1818 [0x71a] 
+
+// Reserved address 1819 [0x71b] 
+
+// Reserved address 1820 [0x71c] 
+
+// Reserved address 1821 [0x71d] 
+
+// Reserved address 1822 [0x71e] 
+
+// Reserved address 1823 [0x71f] 
+
+// Reserved address 1824 [0x720] 
+
+// Reserved address 1825 [0x721] 
+
+// Reserved address 1826 [0x722] 
+
+// Reserved address 1827 [0x723] 
+
+// Reserved address 1828 [0x724] 
+
+// Reserved address 1829 [0x725] 
+
+// Reserved address 1830 [0x726] 
+
+// Reserved address 1831 [0x727] 
+
+// Reserved address 1832 [0x728] 
+
+// Reserved address 1833 [0x729] 
+
+// Reserved address 1834 [0x72a] 
+
+// Reserved address 1835 [0x72b] 
+
+// Reserved address 1836 [0x72c] 
+
+// Reserved address 1837 [0x72d] 
+
+// Reserved address 1838 [0x72e] 
+
+// Reserved address 1839 [0x72f] 
+
+// Register PL310_CACHE_SYNC_0  
+#define PL310_CACHE_SYNC_0                      _MK_ADDR_CONST(0x730)
+#define PL310_CACHE_SYNC_0_SECURE                       0x0
+#define PL310_CACHE_SYNC_0_WORD_COUNT                   0x1
+#define PL310_CACHE_SYNC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_CACHE_SYNC_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define PL310_CACHE_SYNC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define PL310_CACHE_SYNC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PL310_CACHE_SYNC_0_READ_MASK                    _MK_MASK_CONST(0x0)
+#define PL310_CACHE_SYNC_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+#define PL310_CACHE_SYNC_0_DUMMY_BIT_TO_KEEP_SIMSPEC_HAPPY_SHIFT                        _MK_SHIFT_CONST(0)
+#define PL310_CACHE_SYNC_0_DUMMY_BIT_TO_KEEP_SIMSPEC_HAPPY_FIELD                        (_MK_MASK_CONST(0x1) << PL310_CACHE_SYNC_0_DUMMY_BIT_TO_KEEP_SIMSPEC_HAPPY_SHIFT)
+#define PL310_CACHE_SYNC_0_DUMMY_BIT_TO_KEEP_SIMSPEC_HAPPY_RANGE                        0:0
+#define PL310_CACHE_SYNC_0_DUMMY_BIT_TO_KEEP_SIMSPEC_HAPPY_WOFFSET                      0x0
+#define PL310_CACHE_SYNC_0_DUMMY_BIT_TO_KEEP_SIMSPEC_HAPPY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_CACHE_SYNC_0_DUMMY_BIT_TO_KEEP_SIMSPEC_HAPPY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_CACHE_SYNC_0_DUMMY_BIT_TO_KEEP_SIMSPEC_HAPPY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_CACHE_SYNC_0_DUMMY_BIT_TO_KEEP_SIMSPEC_HAPPY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 1844 [0x734] 
+
+// Reserved address 1845 [0x735] 
+
+// Reserved address 1846 [0x736] 
+
+// Reserved address 1847 [0x737] 
+
+// Reserved address 1848 [0x738] 
+
+// Reserved address 1849 [0x739] 
+
+// Reserved address 1850 [0x73a] 
+
+// Reserved address 1851 [0x73b] 
+
+// Reserved address 1852 [0x73c] 
+
+// Reserved address 1853 [0x73d] 
+
+// Reserved address 1854 [0x73e] 
+
+// Reserved address 1855 [0x73f] 
+
+// Reserved address 1856 [0x740] 
+
+// Reserved address 1857 [0x741] 
+
+// Reserved address 1858 [0x742] 
+
+// Reserved address 1859 [0x743] 
+
+// Reserved address 1860 [0x744] 
+
+// Reserved address 1861 [0x745] 
+
+// Reserved address 1862 [0x746] 
+
+// Reserved address 1863 [0x747] 
+
+// Reserved address 1864 [0x748] 
+
+// Reserved address 1865 [0x749] 
+
+// Reserved address 1866 [0x74a] 
+
+// Reserved address 1867 [0x74b] 
+
+// Reserved address 1868 [0x74c] 
+
+// Reserved address 1869 [0x74d] 
+
+// Reserved address 1870 [0x74e] 
+
+// Reserved address 1871 [0x74f] 
+
+// Reserved address 1872 [0x750] 
+
+// Reserved address 1873 [0x751] 
+
+// Reserved address 1874 [0x752] 
+
+// Reserved address 1875 [0x753] 
+
+// Reserved address 1876 [0x754] 
+
+// Reserved address 1877 [0x755] 
+
+// Reserved address 1878 [0x756] 
+
+// Reserved address 1879 [0x757] 
+
+// Reserved address 1880 [0x758] 
+
+// Reserved address 1881 [0x759] 
+
+// Reserved address 1882 [0x75a] 
+
+// Reserved address 1883 [0x75b] 
+
+// Reserved address 1884 [0x75c] 
+
+// Reserved address 1885 [0x75d] 
+
+// Reserved address 1886 [0x75e] 
+
+// Reserved address 1887 [0x75f] 
+
+// Reserved address 1888 [0x760] 
+
+// Reserved address 1889 [0x761] 
+
+// Reserved address 1890 [0x762] 
+
+// Reserved address 1891 [0x763] 
+
+// Reserved address 1892 [0x764] 
+
+// Reserved address 1893 [0x765] 
+
+// Reserved address 1894 [0x766] 
+
+// Reserved address 1895 [0x767] 
+
+// Reserved address 1896 [0x768] 
+
+// Reserved address 1897 [0x769] 
+
+// Reserved address 1898 [0x76a] 
+
+// Reserved address 1899 [0x76b] 
+
+// Reserved address 1900 [0x76c] 
+
+// Reserved address 1901 [0x76d] 
+
+// Reserved address 1902 [0x76e] 
+
+// Reserved address 1903 [0x76f] 
+
+// Register PL310_INVALIDATE_LINE_BY_PA_0  
+#define PL310_INVALIDATE_LINE_BY_PA_0                   _MK_ADDR_CONST(0x770)
+#define PL310_INVALIDATE_LINE_BY_PA_0_SECURE                    0x0
+#define PL310_INVALIDATE_LINE_BY_PA_0_WORD_COUNT                        0x1
+#define PL310_INVALIDATE_LINE_BY_PA_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define PL310_INVALIDATE_LINE_BY_PA_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define PL310_INVALIDATE_LINE_BY_PA_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define PL310_INVALIDATE_LINE_BY_PA_0_C_SHIFT                   _MK_SHIFT_CONST(0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_C_FIELD                   (_MK_MASK_CONST(0x1) << PL310_INVALIDATE_LINE_BY_PA_0_C_SHIFT)
+#define PL310_INVALIDATE_LINE_BY_PA_0_C_RANGE                   0:0
+#define PL310_INVALIDATE_LINE_BY_PA_0_C_WOFFSET                 0x0
+#define PL310_INVALIDATE_LINE_BY_PA_0_C_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_C_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define PL310_INVALIDATE_LINE_BY_PA_0_C_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_C_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define PL310_INVALIDATE_LINE_BY_PA_0_BUSY_SHIFT                        _MK_SHIFT_CONST(0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_BUSY_FIELD                        (_MK_MASK_CONST(0x1) << PL310_INVALIDATE_LINE_BY_PA_0_BUSY_SHIFT)
+#define PL310_INVALIDATE_LINE_BY_PA_0_BUSY_RANGE                        0:0
+#define PL310_INVALIDATE_LINE_BY_PA_0_BUSY_WOFFSET                      0x0
+#define PL310_INVALIDATE_LINE_BY_PA_0_BUSY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_BUSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_INVALIDATE_LINE_BY_PA_0_BUSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_BUSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define PL310_INVALIDATE_LINE_BY_PA_0_SBZ_SHIFT                 _MK_SHIFT_CONST(1)
+#define PL310_INVALIDATE_LINE_BY_PA_0_SBZ_FIELD                 (_MK_MASK_CONST(0xf) << PL310_INVALIDATE_LINE_BY_PA_0_SBZ_SHIFT)
+#define PL310_INVALIDATE_LINE_BY_PA_0_SBZ_RANGE                 4:1
+#define PL310_INVALIDATE_LINE_BY_PA_0_SBZ_WOFFSET                       0x0
+#define PL310_INVALIDATE_LINE_BY_PA_0_SBZ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_SBZ_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define PL310_INVALIDATE_LINE_BY_PA_0_SBZ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_SBZ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define PL310_INVALIDATE_LINE_BY_PA_0_PA_MSB_SHIFT                      _MK_SHIFT_CONST(5)
+#define PL310_INVALIDATE_LINE_BY_PA_0_PA_MSB_FIELD                      (_MK_MASK_CONST(0x7ffffff) << PL310_INVALIDATE_LINE_BY_PA_0_PA_MSB_SHIFT)
+#define PL310_INVALIDATE_LINE_BY_PA_0_PA_MSB_RANGE                      31:5
+#define PL310_INVALIDATE_LINE_BY_PA_0_PA_MSB_WOFFSET                    0x0
+#define PL310_INVALIDATE_LINE_BY_PA_0_PA_MSB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_PA_MSB_DEFAULT_MASK                       _MK_MASK_CONST(0x7ffffff)
+#define PL310_INVALIDATE_LINE_BY_PA_0_PA_MSB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_LINE_BY_PA_0_PA_MSB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 1908 [0x774] 
+
+// Reserved address 1912 [0x778] 
+
+// Register PL310_INVALIDATE_BY_WAY_0  
+#define PL310_INVALIDATE_BY_WAY_0                       _MK_ADDR_CONST(0x77c)
+#define PL310_INVALIDATE_BY_WAY_0_SECURE                        0x0
+#define PL310_INVALIDATE_BY_WAY_0_WORD_COUNT                    0x1
+#define PL310_INVALIDATE_BY_WAY_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_BY_WAY_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define PL310_INVALIDATE_BY_WAY_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_BY_WAY_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_BY_WAY_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define PL310_INVALIDATE_BY_WAY_0_WRITE_MASK                    _MK_MASK_CONST(0xff)
+#define PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_SHIFT                      _MK_SHIFT_CONST(0)
+#define PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_FIELD                      (_MK_MASK_CONST(0xff) << PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_SHIFT)
+#define PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_RANGE                      7:0
+#define PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_WOFFSET                    0x0
+#define PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_NO_WAYS                    _MK_ENUM_CONST(0)
+#define PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_EMPTY                      _MK_ENUM_CONST(0)
+#define PL310_INVALIDATE_BY_WAY_0_WAY_BITMAP_ALL_WAYS                   _MK_ENUM_CONST(255)
+
+
+// Reserved address 1920 [0x780] 
+
+// Reserved address 1921 [0x781] 
+
+// Reserved address 1922 [0x782] 
+
+// Reserved address 1923 [0x783] 
+
+// Reserved address 1924 [0x784] 
+
+// Reserved address 1925 [0x785] 
+
+// Reserved address 1926 [0x786] 
+
+// Reserved address 1927 [0x787] 
+
+// Reserved address 1928 [0x788] 
+
+// Reserved address 1929 [0x789] 
+
+// Reserved address 1930 [0x78a] 
+
+// Reserved address 1931 [0x78b] 
+
+// Reserved address 1932 [0x78c] 
+
+// Reserved address 1933 [0x78d] 
+
+// Reserved address 1934 [0x78e] 
+
+// Reserved address 1935 [0x78f] 
+
+// Reserved address 1936 [0x790] 
+
+// Reserved address 1937 [0x791] 
+
+// Reserved address 1938 [0x792] 
+
+// Reserved address 1939 [0x793] 
+
+// Reserved address 1940 [0x794] 
+
+// Reserved address 1941 [0x795] 
+
+// Reserved address 1942 [0x796] 
+
+// Reserved address 1943 [0x797] 
+
+// Reserved address 1944 [0x798] 
+
+// Reserved address 1945 [0x799] 
+
+// Reserved address 1946 [0x79a] 
+
+// Reserved address 1947 [0x79b] 
+
+// Reserved address 1948 [0x79c] 
+
+// Reserved address 1949 [0x79d] 
+
+// Reserved address 1950 [0x79e] 
+
+// Reserved address 1951 [0x79f] 
+
+// Reserved address 1952 [0x7a0] 
+
+// Reserved address 1953 [0x7a1] 
+
+// Reserved address 1954 [0x7a2] 
+
+// Reserved address 1955 [0x7a3] 
+
+// Reserved address 1956 [0x7a4] 
+
+// Reserved address 1957 [0x7a5] 
+
+// Reserved address 1958 [0x7a6] 
+
+// Reserved address 1959 [0x7a7] 
+
+// Reserved address 1960 [0x7a8] 
+
+// Reserved address 1961 [0x7a9] 
+
+// Reserved address 1962 [0x7aa] 
+
+// Reserved address 1963 [0x7ab] 
+
+// Reserved address 1964 [0x7ac] 
+
+// Reserved address 1965 [0x7ad] 
+
+// Reserved address 1966 [0x7ae] 
+
+// Reserved address 1967 [0x7af] 
+
+// Register PL310_CLEAN_LINE_BY_PA_0  
+#define PL310_CLEAN_LINE_BY_PA_0                        _MK_ADDR_CONST(0x7b0)
+#define PL310_CLEAN_LINE_BY_PA_0_SECURE                         0x0
+#define PL310_CLEAN_LINE_BY_PA_0_WORD_COUNT                     0x1
+#define PL310_CLEAN_LINE_BY_PA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_PA_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define PL310_CLEAN_LINE_BY_PA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_PA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_PA_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define PL310_CLEAN_LINE_BY_PA_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define PL310_CLEAN_LINE_BY_PA_0_C_SHIFT                        _MK_SHIFT_CONST(0)
+#define PL310_CLEAN_LINE_BY_PA_0_C_FIELD                        (_MK_MASK_CONST(0x1) << PL310_CLEAN_LINE_BY_PA_0_C_SHIFT)
+#define PL310_CLEAN_LINE_BY_PA_0_C_RANGE                        0:0
+#define PL310_CLEAN_LINE_BY_PA_0_C_WOFFSET                      0x0
+#define PL310_CLEAN_LINE_BY_PA_0_C_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_PA_0_C_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define PL310_CLEAN_LINE_BY_PA_0_C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_PA_0_C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_LINE_BY_PA_0_BUSY_SHIFT                     _MK_SHIFT_CONST(0)
+#define PL310_CLEAN_LINE_BY_PA_0_BUSY_FIELD                     (_MK_MASK_CONST(0x1) << PL310_CLEAN_LINE_BY_PA_0_BUSY_SHIFT)
+#define PL310_CLEAN_LINE_BY_PA_0_BUSY_RANGE                     0:0
+#define PL310_CLEAN_LINE_BY_PA_0_BUSY_WOFFSET                   0x0
+#define PL310_CLEAN_LINE_BY_PA_0_BUSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_PA_0_BUSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_CLEAN_LINE_BY_PA_0_BUSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_PA_0_BUSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_LINE_BY_PA_0_SBZ_SHIFT                      _MK_SHIFT_CONST(1)
+#define PL310_CLEAN_LINE_BY_PA_0_SBZ_FIELD                      (_MK_MASK_CONST(0xf) << PL310_CLEAN_LINE_BY_PA_0_SBZ_SHIFT)
+#define PL310_CLEAN_LINE_BY_PA_0_SBZ_RANGE                      4:1
+#define PL310_CLEAN_LINE_BY_PA_0_SBZ_WOFFSET                    0x0
+#define PL310_CLEAN_LINE_BY_PA_0_SBZ_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_PA_0_SBZ_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define PL310_CLEAN_LINE_BY_PA_0_SBZ_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_PA_0_SBZ_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_LINE_BY_PA_0_PA_MSB_SHIFT                   _MK_SHIFT_CONST(5)
+#define PL310_CLEAN_LINE_BY_PA_0_PA_MSB_FIELD                   (_MK_MASK_CONST(0x7ffffff) << PL310_CLEAN_LINE_BY_PA_0_PA_MSB_SHIFT)
+#define PL310_CLEAN_LINE_BY_PA_0_PA_MSB_RANGE                   31:5
+#define PL310_CLEAN_LINE_BY_PA_0_PA_MSB_WOFFSET                 0x0
+#define PL310_CLEAN_LINE_BY_PA_0_PA_MSB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_PA_0_PA_MSB_DEFAULT_MASK                    _MK_MASK_CONST(0x7ffffff)
+#define PL310_CLEAN_LINE_BY_PA_0_PA_MSB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_PA_0_PA_MSB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 1972 [0x7b4] 
+
+// Register PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0  
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0                     _MK_ADDR_CONST(0x7b8)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_SECURE                      0x0
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_WORD_COUNT                  0x1
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_RESET_MASK                  _MK_MASK_CONST(0xf0000fff)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_READ_MASK                   _MK_MASK_CONST(0xf0000fff)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_WRITE_MASK                  _MK_MASK_CONST(0xf0000fff)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_BUSY_SHIFT                  _MK_SHIFT_CONST(0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_BUSY_FIELD                  (_MK_MASK_CONST(0x1) << PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_BUSY_SHIFT)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_BUSY_RANGE                  0:0
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_BUSY_WOFFSET                        0x0
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_BUSY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_BUSY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_BUSY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_BUSY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_C_SHIFT                     _MK_SHIFT_CONST(1)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_C_FIELD                     (_MK_MASK_CONST(0xf) << PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_C_SHIFT)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_C_RANGE                     4:1
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_C_WOFFSET                   0x0
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_C_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_C_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_C_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_C_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_INDEX_SHIFT                 _MK_SHIFT_CONST(5)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_INDEX_FIELD                 (_MK_MASK_CONST(0x7f) << PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_INDEX_SHIFT)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_INDEX_RANGE                 11:5
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_INDEX_WOFFSET                       0x0
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_INDEX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_INDEX_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_INDEX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_INDEX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_WAY_SHIFT                   _MK_SHIFT_CONST(28)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_WAY_FIELD                   (_MK_MASK_CONST(0x3f) << PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_WAY_SHIFT)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_WAY_RANGE                   33:28
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_WAY_WOFFSET                 0x0
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_WAY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_WAY_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_WAY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0_WAY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register PL310_CLEAN_BY_WAY_0  
+#define PL310_CLEAN_BY_WAY_0                    _MK_ADDR_CONST(0x7bc)
+#define PL310_CLEAN_BY_WAY_0_SECURE                     0x0
+#define PL310_CLEAN_BY_WAY_0_WORD_COUNT                         0x1
+#define PL310_CLEAN_BY_WAY_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_BY_WAY_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define PL310_CLEAN_BY_WAY_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_BY_WAY_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_BY_WAY_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define PL310_CLEAN_BY_WAY_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
+#define PL310_CLEAN_BY_WAY_0_WAY_BITMAP_SHIFT                   _MK_SHIFT_CONST(0)
+#define PL310_CLEAN_BY_WAY_0_WAY_BITMAP_FIELD                   (_MK_MASK_CONST(0xff) << PL310_CLEAN_BY_WAY_0_WAY_BITMAP_SHIFT)
+#define PL310_CLEAN_BY_WAY_0_WAY_BITMAP_RANGE                   7:0
+#define PL310_CLEAN_BY_WAY_0_WAY_BITMAP_WOFFSET                 0x0
+#define PL310_CLEAN_BY_WAY_0_WAY_BITMAP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_BY_WAY_0_WAY_BITMAP_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define PL310_CLEAN_BY_WAY_0_WAY_BITMAP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_BY_WAY_0_WAY_BITMAP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_BY_WAY_0_WAY_BITMAP_NO_WAYS                 _MK_ENUM_CONST(0)
+#define PL310_CLEAN_BY_WAY_0_WAY_BITMAP_EMPTY                   _MK_ENUM_CONST(0)
+#define PL310_CLEAN_BY_WAY_0_WAY_BITMAP_ALL_WAYS                        _MK_ENUM_CONST(255)
+
+
+// Reserved address 1984 [0x7c0] 
+
+// Reserved address 1985 [0x7c1] 
+
+// Reserved address 1986 [0x7c2] 
+
+// Reserved address 1987 [0x7c3] 
+
+// Reserved address 1988 [0x7c4] 
+
+// Reserved address 1989 [0x7c5] 
+
+// Reserved address 1990 [0x7c6] 
+
+// Reserved address 1991 [0x7c7] 
+
+// Reserved address 1992 [0x7c8] 
+
+// Reserved address 1993 [0x7c9] 
+
+// Reserved address 1994 [0x7ca] 
+
+// Reserved address 1995 [0x7cb] 
+
+// Reserved address 1996 [0x7cc] 
+
+// Reserved address 1997 [0x7cd] 
+
+// Reserved address 1998 [0x7ce] 
+
+// Reserved address 1999 [0x7cf] 
+
+// Reserved address 2000 [0x7d0] 
+
+// Reserved address 2001 [0x7d1] 
+
+// Reserved address 2002 [0x7d2] 
+
+// Reserved address 2003 [0x7d3] 
+
+// Reserved address 2004 [0x7d4] 
+
+// Reserved address 2005 [0x7d5] 
+
+// Reserved address 2006 [0x7d6] 
+
+// Reserved address 2007 [0x7d7] 
+
+// Reserved address 2008 [0x7d8] 
+
+// Reserved address 2009 [0x7d9] 
+
+// Reserved address 2010 [0x7da] 
+
+// Reserved address 2011 [0x7db] 
+
+// Reserved address 2012 [0x7dc] 
+
+// Reserved address 2013 [0x7dd] 
+
+// Reserved address 2014 [0x7de] 
+
+// Reserved address 2015 [0x7df] 
+
+// Reserved address 2016 [0x7e0] 
+
+// Reserved address 2017 [0x7e1] 
+
+// Reserved address 2018 [0x7e2] 
+
+// Reserved address 2019 [0x7e3] 
+
+// Reserved address 2020 [0x7e4] 
+
+// Reserved address 2021 [0x7e5] 
+
+// Reserved address 2022 [0x7e6] 
+
+// Reserved address 2023 [0x7e7] 
+
+// Reserved address 2024 [0x7e8] 
+
+// Reserved address 2025 [0x7e9] 
+
+// Reserved address 2026 [0x7ea] 
+
+// Reserved address 2027 [0x7eb] 
+
+// Reserved address 2028 [0x7ec] 
+
+// Reserved address 2029 [0x7ed] 
+
+// Reserved address 2030 [0x7ee] 
+
+// Reserved address 2031 [0x7ef] 
+
+// Register PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0  
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0                 _MK_ADDR_CONST(0x7f0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SECURE                  0x0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_WORD_COUNT                      0x1
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_C_SHIFT                 _MK_SHIFT_CONST(0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_C_FIELD                 (_MK_MASK_CONST(0x1) << PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_C_SHIFT)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_C_RANGE                 0:0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_C_WOFFSET                       0x0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_C_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_C_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_C_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_C_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_BUSY_SHIFT                      _MK_SHIFT_CONST(0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_BUSY_FIELD                      (_MK_MASK_CONST(0x1) << PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_BUSY_SHIFT)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_BUSY_RANGE                      0:0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_BUSY_WOFFSET                    0x0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_BUSY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_BUSY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_BUSY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_BUSY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SBZ_SHIFT                       _MK_SHIFT_CONST(1)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SBZ_FIELD                       (_MK_MASK_CONST(0xf) << PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SBZ_SHIFT)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SBZ_RANGE                       4:1
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SBZ_WOFFSET                     0x0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SBZ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SBZ_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SBZ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_SBZ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_PA_MSB_SHIFT                    _MK_SHIFT_CONST(5)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_PA_MSB_FIELD                    (_MK_MASK_CONST(0x7ffffff) << PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_PA_MSB_SHIFT)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_PA_MSB_RANGE                    31:5
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_PA_MSB_WOFFSET                  0x0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_PA_MSB_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_PA_MSB_DEFAULT_MASK                     _MK_MASK_CONST(0x7ffffff)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_PA_MSB_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0_PA_MSB_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 2036 [0x7f4] 
+
+// Register PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0  
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0                      _MK_ADDR_CONST(0x7f8)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_SECURE                       0x0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_WORD_COUNT                   0x1
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_RESET_MASK                   _MK_MASK_CONST(0xf0000fff)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_READ_MASK                    _MK_MASK_CONST(0xf0000fff)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_WRITE_MASK                   _MK_MASK_CONST(0xf0000fff)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_BUSY_SHIFT                   _MK_SHIFT_CONST(0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_BUSY_FIELD                   (_MK_MASK_CONST(0x1) << PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_BUSY_SHIFT)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_BUSY_RANGE                   0:0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_BUSY_WOFFSET                 0x0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_BUSY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_BUSY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_BUSY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_BUSY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_C_SHIFT                      _MK_SHIFT_CONST(1)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_C_FIELD                      (_MK_MASK_CONST(0xf) << PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_C_SHIFT)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_C_RANGE                      4:1
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_C_WOFFSET                    0x0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_C_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_C_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_C_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_C_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_INDEX_SHIFT                  _MK_SHIFT_CONST(5)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_INDEX_FIELD                  (_MK_MASK_CONST(0x7f) << PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_INDEX_SHIFT)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_INDEX_RANGE                  11:5
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_INDEX_WOFFSET                        0x0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_INDEX_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_INDEX_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_INDEX_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_INDEX_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_WAY_SHIFT                    _MK_SHIFT_CONST(28)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_WAY_FIELD                    (_MK_MASK_CONST(0x3f) << PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_WAY_SHIFT)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_WAY_RANGE                    33:28
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_WAY_WOFFSET                  0x0
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_WAY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_WAY_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_WAY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0_WAY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register PL310_CLEAN_AND_INVALIDATE_BY_WAY_0  
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0                     _MK_ADDR_CONST(0x7fc)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_SECURE                      0x0
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WORD_COUNT                  0x1
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WRITE_MASK                  _MK_MASK_CONST(0xff)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_SHIFT                    _MK_SHIFT_CONST(0)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_FIELD                    (_MK_MASK_CONST(0xff) << PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_SHIFT)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_RANGE                    7:0
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_WOFFSET                  0x0
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_NO_WAYS                  _MK_ENUM_CONST(0)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_EMPTY                    _MK_ENUM_CONST(0)
+#define PL310_CLEAN_AND_INVALIDATE_BY_WAY_0_WAY_BITMAP_ALL_WAYS                 _MK_ENUM_CONST(255)
+
+
+// Reserved address 2048 [0x800] 
+
+// Register PL310_DATA_LOCKDOWN0_0  
+#define PL310_DATA_LOCKDOWN0_0                  _MK_ADDR_CONST(0x900)
+#define PL310_DATA_LOCKDOWN0_0_SECURE                   0x0
+#define PL310_DATA_LOCKDOWN0_0_WORD_COUNT                       0x1
+#define PL310_DATA_LOCKDOWN0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN0_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN0_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN0_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_FIELD                 (_MK_MASK_CONST(0xff) << PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_SHIFT)
+#define PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_RANGE                 7:0
+#define PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_WOFFSET                       0x0
+#define PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_NO_WAYS                       _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_EMPTY                 _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN0_0_WAY_BITMAP_ALL_WAYS                      _MK_ENUM_CONST(255)
+
+
+// Register PL310_INSTRUCTION_LOCKDOWN0_0  
+#define PL310_INSTRUCTION_LOCKDOWN0_0                   _MK_ADDR_CONST(0x904)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_SECURE                    0x0
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WORD_COUNT                        0x1
+#define PL310_INSTRUCTION_LOCKDOWN0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_SHIFT                  _MK_SHIFT_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_FIELD                  (_MK_MASK_CONST(0xff) << PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_SHIFT)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_RANGE                  7:0
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_WOFFSET                        0x0
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_NO_WAYS                        _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_EMPTY                  _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN0_0_WAY_BITMAP_ALL_WAYS                       _MK_ENUM_CONST(255)
+
+
+// Register PL310_DATA_LOCKDOWN1_0  
+#define PL310_DATA_LOCKDOWN1_0                  _MK_ADDR_CONST(0x908)
+#define PL310_DATA_LOCKDOWN1_0_SECURE                   0x0
+#define PL310_DATA_LOCKDOWN1_0_WORD_COUNT                       0x1
+#define PL310_DATA_LOCKDOWN1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN1_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN1_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN1_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_FIELD                 (_MK_MASK_CONST(0xff) << PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_SHIFT)
+#define PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_RANGE                 7:0
+#define PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_WOFFSET                       0x0
+#define PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_NO_WAYS                       _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_EMPTY                 _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN1_0_WAY_BITMAP_ALL_WAYS                      _MK_ENUM_CONST(255)
+
+
+// Register PL310_INSTRUCTION_LOCKDOWN1_0  
+#define PL310_INSTRUCTION_LOCKDOWN1_0                   _MK_ADDR_CONST(0x90c)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_SECURE                    0x0
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WORD_COUNT                        0x1
+#define PL310_INSTRUCTION_LOCKDOWN1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_SHIFT                  _MK_SHIFT_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_FIELD                  (_MK_MASK_CONST(0xff) << PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_SHIFT)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_RANGE                  7:0
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_WOFFSET                        0x0
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_NO_WAYS                        _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_EMPTY                  _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN1_0_WAY_BITMAP_ALL_WAYS                       _MK_ENUM_CONST(255)
+
+
+// Register PL310_DATA_LOCKDOWN2_0  
+#define PL310_DATA_LOCKDOWN2_0                  _MK_ADDR_CONST(0x910)
+#define PL310_DATA_LOCKDOWN2_0_SECURE                   0x0
+#define PL310_DATA_LOCKDOWN2_0_WORD_COUNT                       0x1
+#define PL310_DATA_LOCKDOWN2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN2_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN2_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN2_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_FIELD                 (_MK_MASK_CONST(0xff) << PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_SHIFT)
+#define PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_RANGE                 7:0
+#define PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_WOFFSET                       0x0
+#define PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_NO_WAYS                       _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_EMPTY                 _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN2_0_WAY_BITMAP_ALL_WAYS                      _MK_ENUM_CONST(255)
+
+
+// Register PL310_INSTRUCTION_LOCKDOWN2_0  
+#define PL310_INSTRUCTION_LOCKDOWN2_0                   _MK_ADDR_CONST(0x914)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_SECURE                    0x0
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WORD_COUNT                        0x1
+#define PL310_INSTRUCTION_LOCKDOWN2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_SHIFT                  _MK_SHIFT_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_FIELD                  (_MK_MASK_CONST(0xff) << PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_SHIFT)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_RANGE                  7:0
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_WOFFSET                        0x0
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_NO_WAYS                        _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_EMPTY                  _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN2_0_WAY_BITMAP_ALL_WAYS                       _MK_ENUM_CONST(255)
+
+
+// Register PL310_DATA_LOCKDOWN3_0  
+#define PL310_DATA_LOCKDOWN3_0                  _MK_ADDR_CONST(0x918)
+#define PL310_DATA_LOCKDOWN3_0_SECURE                   0x0
+#define PL310_DATA_LOCKDOWN3_0_WORD_COUNT                       0x1
+#define PL310_DATA_LOCKDOWN3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN3_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN3_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN3_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_FIELD                 (_MK_MASK_CONST(0xff) << PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_SHIFT)
+#define PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_RANGE                 7:0
+#define PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_WOFFSET                       0x0
+#define PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_NO_WAYS                       _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_EMPTY                 _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN3_0_WAY_BITMAP_ALL_WAYS                      _MK_ENUM_CONST(255)
+
+
+// Register PL310_INSTRUCTION_LOCKDOWN3_0  
+#define PL310_INSTRUCTION_LOCKDOWN3_0                   _MK_ADDR_CONST(0x91c)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_SECURE                    0x0
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WORD_COUNT                        0x1
+#define PL310_INSTRUCTION_LOCKDOWN3_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_SHIFT                  _MK_SHIFT_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_FIELD                  (_MK_MASK_CONST(0xff) << PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_SHIFT)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_RANGE                  7:0
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_WOFFSET                        0x0
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_NO_WAYS                        _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_EMPTY                  _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN3_0_WAY_BITMAP_ALL_WAYS                       _MK_ENUM_CONST(255)
+
+
+// Register PL310_DATA_LOCKDOWN4_0  
+#define PL310_DATA_LOCKDOWN4_0                  _MK_ADDR_CONST(0x920)
+#define PL310_DATA_LOCKDOWN4_0_SECURE                   0x0
+#define PL310_DATA_LOCKDOWN4_0_WORD_COUNT                       0x1
+#define PL310_DATA_LOCKDOWN4_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN4_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN4_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN4_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_FIELD                 (_MK_MASK_CONST(0xff) << PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_SHIFT)
+#define PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_RANGE                 7:0
+#define PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_WOFFSET                       0x0
+#define PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_NO_WAYS                       _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_EMPTY                 _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN4_0_WAY_BITMAP_ALL_WAYS                      _MK_ENUM_CONST(255)
+
+
+// Register PL310_INSTRUCTION_LOCKDOWN4_0  
+#define PL310_INSTRUCTION_LOCKDOWN4_0                   _MK_ADDR_CONST(0x924)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_SECURE                    0x0
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WORD_COUNT                        0x1
+#define PL310_INSTRUCTION_LOCKDOWN4_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_SHIFT                  _MK_SHIFT_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_FIELD                  (_MK_MASK_CONST(0xff) << PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_SHIFT)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_RANGE                  7:0
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_WOFFSET                        0x0
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_NO_WAYS                        _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_EMPTY                  _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN4_0_WAY_BITMAP_ALL_WAYS                       _MK_ENUM_CONST(255)
+
+
+// Register PL310_DATA_LOCKDOWN5_0  
+#define PL310_DATA_LOCKDOWN5_0                  _MK_ADDR_CONST(0x928)
+#define PL310_DATA_LOCKDOWN5_0_SECURE                   0x0
+#define PL310_DATA_LOCKDOWN5_0_WORD_COUNT                       0x1
+#define PL310_DATA_LOCKDOWN5_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN5_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN5_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN5_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN5_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN5_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_FIELD                 (_MK_MASK_CONST(0xff) << PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_SHIFT)
+#define PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_RANGE                 7:0
+#define PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_WOFFSET                       0x0
+#define PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_NO_WAYS                       _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_EMPTY                 _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN5_0_WAY_BITMAP_ALL_WAYS                      _MK_ENUM_CONST(255)
+
+
+// Register PL310_INSTRUCTION_LOCKDOWN5_0  
+#define PL310_INSTRUCTION_LOCKDOWN5_0                   _MK_ADDR_CONST(0x92c)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_SECURE                    0x0
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WORD_COUNT                        0x1
+#define PL310_INSTRUCTION_LOCKDOWN5_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_SHIFT                  _MK_SHIFT_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_FIELD                  (_MK_MASK_CONST(0xff) << PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_SHIFT)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_RANGE                  7:0
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_WOFFSET                        0x0
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_NO_WAYS                        _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_EMPTY                  _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN5_0_WAY_BITMAP_ALL_WAYS                       _MK_ENUM_CONST(255)
+
+
+// Register PL310_DATA_LOCKDOWN6_0  
+#define PL310_DATA_LOCKDOWN6_0                  _MK_ADDR_CONST(0x930)
+#define PL310_DATA_LOCKDOWN6_0_SECURE                   0x0
+#define PL310_DATA_LOCKDOWN6_0_WORD_COUNT                       0x1
+#define PL310_DATA_LOCKDOWN6_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN6_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN6_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN6_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN6_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN6_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_FIELD                 (_MK_MASK_CONST(0xff) << PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_SHIFT)
+#define PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_RANGE                 7:0
+#define PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_WOFFSET                       0x0
+#define PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_NO_WAYS                       _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_EMPTY                 _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN6_0_WAY_BITMAP_ALL_WAYS                      _MK_ENUM_CONST(255)
+
+
+// Register PL310_INSTRUCTION_LOCKDOWN6_0  
+#define PL310_INSTRUCTION_LOCKDOWN6_0                   _MK_ADDR_CONST(0x934)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_SECURE                    0x0
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WORD_COUNT                        0x1
+#define PL310_INSTRUCTION_LOCKDOWN6_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_SHIFT                  _MK_SHIFT_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_FIELD                  (_MK_MASK_CONST(0xff) << PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_SHIFT)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_RANGE                  7:0
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_WOFFSET                        0x0
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_NO_WAYS                        _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_EMPTY                  _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN6_0_WAY_BITMAP_ALL_WAYS                       _MK_ENUM_CONST(255)
+
+
+// Register PL310_DATA_LOCKDOWN7_0  
+#define PL310_DATA_LOCKDOWN7_0                  _MK_ADDR_CONST(0x938)
+#define PL310_DATA_LOCKDOWN7_0_SECURE                   0x0
+#define PL310_DATA_LOCKDOWN7_0_WORD_COUNT                       0x1
+#define PL310_DATA_LOCKDOWN7_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN7_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN7_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN7_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN7_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN7_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_FIELD                 (_MK_MASK_CONST(0xff) << PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_SHIFT)
+#define PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_RANGE                 7:0
+#define PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_WOFFSET                       0x0
+#define PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_NO_WAYS                       _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_EMPTY                 _MK_ENUM_CONST(0)
+#define PL310_DATA_LOCKDOWN7_0_WAY_BITMAP_ALL_WAYS                      _MK_ENUM_CONST(255)
+
+
+// Register PL310_INSTRUCTION_LOCKDOWN7_0  
+#define PL310_INSTRUCTION_LOCKDOWN7_0                   _MK_ADDR_CONST(0x93c)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_SECURE                    0x0
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WORD_COUNT                        0x1
+#define PL310_INSTRUCTION_LOCKDOWN7_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_SHIFT                  _MK_SHIFT_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_FIELD                  (_MK_MASK_CONST(0xff) << PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_SHIFT)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_RANGE                  7:0
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_WOFFSET                        0x0
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_NO_WAYS                        _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_EMPTY                  _MK_ENUM_CONST(0)
+#define PL310_INSTRUCTION_LOCKDOWN7_0_WAY_BITMAP_ALL_WAYS                       _MK_ENUM_CONST(255)
+
+
+// Reserved address 2560 [0xa00] 
+
+// Reserved address 2816 [0xb00] 
+
+// Register PL310_ADDRESS_FILTERING_START_0  
+#define PL310_ADDRESS_FILTERING_START_0                 _MK_ADDR_CONST(0xc00)
+#define PL310_ADDRESS_FILTERING_START_0_SECURE                  0x0
+#define PL310_ADDRESS_FILTERING_START_0_WORD_COUNT                      0x1
+#define PL310_ADDRESS_FILTERING_START_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define PL310_ADDRESS_FILTERING_START_0_RESET_MASK                      _MK_MASK_CONST(0xfff00001)
+#define PL310_ADDRESS_FILTERING_START_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define PL310_ADDRESS_FILTERING_START_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define PL310_ADDRESS_FILTERING_START_0_READ_MASK                       _MK_MASK_CONST(0xfff00001)
+#define PL310_ADDRESS_FILTERING_START_0_WRITE_MASK                      _MK_MASK_CONST(0xfff00001)
+#define PL310_ADDRESS_FILTERING_START_0_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define PL310_ADDRESS_FILTERING_START_0_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << PL310_ADDRESS_FILTERING_START_0_ENABLE_SHIFT)
+#define PL310_ADDRESS_FILTERING_START_0_ENABLE_RANGE                    0:0
+#define PL310_ADDRESS_FILTERING_START_0_ENABLE_WOFFSET                  0x0
+#define PL310_ADDRESS_FILTERING_START_0_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_ADDRESS_FILTERING_START_0_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PL310_ADDRESS_FILTERING_START_0_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_ADDRESS_FILTERING_START_0_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define PL310_ADDRESS_FILTERING_START_0_ADDRESS_MSB_SHIFT                       _MK_SHIFT_CONST(20)
+#define PL310_ADDRESS_FILTERING_START_0_ADDRESS_MSB_FIELD                       (_MK_MASK_CONST(0xfff) << PL310_ADDRESS_FILTERING_START_0_ADDRESS_MSB_SHIFT)
+#define PL310_ADDRESS_FILTERING_START_0_ADDRESS_MSB_RANGE                       31:20
+#define PL310_ADDRESS_FILTERING_START_0_ADDRESS_MSB_WOFFSET                     0x0
+#define PL310_ADDRESS_FILTERING_START_0_ADDRESS_MSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define PL310_ADDRESS_FILTERING_START_0_ADDRESS_MSB_DEFAULT_MASK                        _MK_MASK_CONST(0xfff)
+#define PL310_ADDRESS_FILTERING_START_0_ADDRESS_MSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_ADDRESS_FILTERING_START_0_ADDRESS_MSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register PL310_ADDRESS_FILTERING_END_0  
+#define PL310_ADDRESS_FILTERING_END_0                   _MK_ADDR_CONST(0xc04)
+#define PL310_ADDRESS_FILTERING_END_0_SECURE                    0x0
+#define PL310_ADDRESS_FILTERING_END_0_WORD_COUNT                        0x1
+#define PL310_ADDRESS_FILTERING_END_0_RESET_VAL                         _MK_MASK_CONST(0x40000000)
+#define PL310_ADDRESS_FILTERING_END_0_RESET_MASK                        _MK_MASK_CONST(0xfff00000)
+#define PL310_ADDRESS_FILTERING_END_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_ADDRESS_FILTERING_END_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_ADDRESS_FILTERING_END_0_READ_MASK                         _MK_MASK_CONST(0xfff00000)
+#define PL310_ADDRESS_FILTERING_END_0_WRITE_MASK                        _MK_MASK_CONST(0xfff00000)
+#define PL310_ADDRESS_FILTERING_END_0_ADDRESS_MSB_SHIFT                 _MK_SHIFT_CONST(20)
+#define PL310_ADDRESS_FILTERING_END_0_ADDRESS_MSB_FIELD                 (_MK_MASK_CONST(0xfff) << PL310_ADDRESS_FILTERING_END_0_ADDRESS_MSB_SHIFT)
+#define PL310_ADDRESS_FILTERING_END_0_ADDRESS_MSB_RANGE                 31:20
+#define PL310_ADDRESS_FILTERING_END_0_ADDRESS_MSB_WOFFSET                       0x0
+#define PL310_ADDRESS_FILTERING_END_0_ADDRESS_MSB_DEFAULT                       _MK_MASK_CONST(0x400)
+#define PL310_ADDRESS_FILTERING_END_0_ADDRESS_MSB_DEFAULT_MASK                  _MK_MASK_CONST(0xfff)
+#define PL310_ADDRESS_FILTERING_END_0_ADDRESS_MSB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_ADDRESS_FILTERING_END_0_ADDRESS_MSB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 3328 [0xd00] 
+
+// Reserved address 3584 [0xe00] 
+
+// Reserved address 3840 [0xf00] 
+
+// Register PL310_DEBUG_CONTROL_0  
+#define PL310_DEBUG_CONTROL_0                   _MK_ADDR_CONST(0xf40)
+#define PL310_DEBUG_CONTROL_0_SECURE                    0x0
+#define PL310_DEBUG_CONTROL_0_WORD_COUNT                        0x1
+#define PL310_DEBUG_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x7)
+#define PL310_DEBUG_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x7)
+#define PL310_DEBUG_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x3)
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_LINEFILL_SHIFT                      _MK_SHIFT_CONST(0)
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_LINEFILL_FIELD                      (_MK_MASK_CONST(0x1) << PL310_DEBUG_CONTROL_0_DISABLE_CACHE_LINEFILL_SHIFT)
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_LINEFILL_RANGE                      0:0
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_LINEFILL_WOFFSET                    0x0
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_LINEFILL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_LINEFILL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_LINEFILL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_LINEFILL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define PL310_DEBUG_CONTROL_0_DCL_SHIFT                 _MK_SHIFT_CONST(0)
+#define PL310_DEBUG_CONTROL_0_DCL_FIELD                 (_MK_MASK_CONST(0x1) << PL310_DEBUG_CONTROL_0_DCL_SHIFT)
+#define PL310_DEBUG_CONTROL_0_DCL_RANGE                 0:0
+#define PL310_DEBUG_CONTROL_0_DCL_WOFFSET                       0x0
+#define PL310_DEBUG_CONTROL_0_DCL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_DCL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define PL310_DEBUG_CONTROL_0_DCL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_DCL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_WRITEBACK_SHIFT                     _MK_SHIFT_CONST(1)
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_WRITEBACK_FIELD                     (_MK_MASK_CONST(0x1) << PL310_DEBUG_CONTROL_0_DISABLE_CACHE_WRITEBACK_SHIFT)
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_WRITEBACK_RANGE                     1:1
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_WRITEBACK_WOFFSET                   0x0
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_WRITEBACK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_WRITEBACK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_WRITEBACK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_DISABLE_CACHE_WRITEBACK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define PL310_DEBUG_CONTROL_0_FORCE_WT_SHIFT                    _MK_SHIFT_CONST(1)
+#define PL310_DEBUG_CONTROL_0_FORCE_WT_FIELD                    (_MK_MASK_CONST(0x1) << PL310_DEBUG_CONTROL_0_FORCE_WT_SHIFT)
+#define PL310_DEBUG_CONTROL_0_FORCE_WT_RANGE                    1:1
+#define PL310_DEBUG_CONTROL_0_FORCE_WT_WOFFSET                  0x0
+#define PL310_DEBUG_CONTROL_0_FORCE_WT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_FORCE_WT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define PL310_DEBUG_CONTROL_0_FORCE_WT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_FORCE_WT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define PL310_DEBUG_CONTROL_0_DWB_SHIFT                 _MK_SHIFT_CONST(1)
+#define PL310_DEBUG_CONTROL_0_DWB_FIELD                 (_MK_MASK_CONST(0x1) << PL310_DEBUG_CONTROL_0_DWB_SHIFT)
+#define PL310_DEBUG_CONTROL_0_DWB_RANGE                 1:1
+#define PL310_DEBUG_CONTROL_0_DWB_WOFFSET                       0x0
+#define PL310_DEBUG_CONTROL_0_DWB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_DWB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define PL310_DEBUG_CONTROL_0_DWB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_DWB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define PL310_DEBUG_CONTROL_0_SPNIDEN_SHIFT                     _MK_SHIFT_CONST(2)
+#define PL310_DEBUG_CONTROL_0_SPNIDEN_FIELD                     (_MK_MASK_CONST(0x1) << PL310_DEBUG_CONTROL_0_SPNIDEN_SHIFT)
+#define PL310_DEBUG_CONTROL_0_SPNIDEN_RANGE                     2:2
+#define PL310_DEBUG_CONTROL_0_SPNIDEN_WOFFSET                   0x0
+#define PL310_DEBUG_CONTROL_0_SPNIDEN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_SPNIDEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define PL310_DEBUG_CONTROL_0_SPNIDEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define PL310_DEBUG_CONTROL_0_SPNIDEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 3908 [0xf44] 
+
+// Reserved address 3909 [0xf45] 
+
+// Reserved address 3910 [0xf46] 
+
+// Reserved address 3911 [0xf47] 
+
+// Reserved address 3912 [0xf48] 
+
+// Reserved address 3913 [0xf49] 
+
+// Reserved address 3914 [0xf4a] 
+
+// Reserved address 3915 [0xf4b] 
+
+// Reserved address 3916 [0xf4c] 
+
+// Reserved address 3917 [0xf4d] 
+
+// Reserved address 3918 [0xf4e] 
+
+// Reserved address 3919 [0xf4f] 
+
+// Reserved address 3920 [0xf50] 
+
+// Reserved address 3921 [0xf51] 
+
+// Reserved address 3922 [0xf52] 
+
+// Reserved address 3923 [0xf53] 
+
+// Reserved address 3924 [0xf54] 
+
+// Reserved address 3925 [0xf55] 
+
+// Reserved address 3926 [0xf56] 
+
+// Reserved address 3927 [0xf57] 
+
+// Reserved address 3928 [0xf58] 
+
+// Reserved address 3929 [0xf59] 
+
+// Reserved address 3930 [0xf5a] 
+
+// Reserved address 3931 [0xf5b] 
+
+// Reserved address 3932 [0xf5c] 
+
+// Reserved address 3933 [0xf5d] 
+
+// Reserved address 3934 [0xf5e] 
+
+// Reserved address 3935 [0xf5f] 
+
+// Register PL310_PREFETCH_OFFSET_0  
+#define PL310_PREFETCH_OFFSET_0                 _MK_ADDR_CONST(0xf60)
+#define PL310_PREFETCH_OFFSET_0_SECURE                  0x0
+#define PL310_PREFETCH_OFFSET_0_WORD_COUNT                      0x1
+#define PL310_PREFETCH_OFFSET_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define PL310_PREFETCH_OFFSET_0_RESET_MASK                      _MK_MASK_CONST(0x1f)
+#define PL310_PREFETCH_OFFSET_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define PL310_PREFETCH_OFFSET_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define PL310_PREFETCH_OFFSET_0_READ_MASK                       _MK_MASK_CONST(0x1f)
+#define PL310_PREFETCH_OFFSET_0_WRITE_MASK                      _MK_MASK_CONST(0x1f)
+// prefetch 1 + delta cache lines ahead of the current address 
+#define PL310_PREFETCH_OFFSET_0_CACHELINE_DELTA_SHIFT                   _MK_SHIFT_CONST(0)
+#define PL310_PREFETCH_OFFSET_0_CACHELINE_DELTA_FIELD                   (_MK_MASK_CONST(0x1f) << PL310_PREFETCH_OFFSET_0_CACHELINE_DELTA_SHIFT)
+#define PL310_PREFETCH_OFFSET_0_CACHELINE_DELTA_RANGE                   4:0
+#define PL310_PREFETCH_OFFSET_0_CACHELINE_DELTA_WOFFSET                 0x0
+#define PL310_PREFETCH_OFFSET_0_CACHELINE_DELTA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define PL310_PREFETCH_OFFSET_0_CACHELINE_DELTA_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define PL310_PREFETCH_OFFSET_0_CACHELINE_DELTA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define PL310_PREFETCH_OFFSET_0_CACHELINE_DELTA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARPL310_REGS(_op_) \
+_op_(PL310_CACHE_ID_0) \
+_op_(PL310_CACHE_TYPE_0) \
+_op_(PL310_CONTROL_0) \
+_op_(PL310_AUXILIARY_CONTROL_0) \
+_op_(PL310_TAG_RAM_LATENCY_0) \
+_op_(PL310_DATA_RAM_LATENCY_0) \
+_op_(PL310_EVENT_COUNTER_CONTROL_0) \
+_op_(PL310_EVENT_COUNTER1_CONFIGURATION_0) \
+_op_(PL310_EVENT_COUNTER0_CONFIGURATION_0) \
+_op_(PL310_EVENT_COUNTER1_0) \
+_op_(PL310_EVENT_COUNTER0_0) \
+_op_(PL310_INTERRUPT_MASK_0) \
+_op_(PL310_MASKED_INTERRUPT_STATUS_0) \
+_op_(PL310_RAW_INTERRUPT_STATUS_0) \
+_op_(PL310_INTERRUPT_CLEAR_0) \
+_op_(PL310_CACHE_SYNC_0) \
+_op_(PL310_INVALIDATE_LINE_BY_PA_0) \
+_op_(PL310_INVALIDATE_BY_WAY_0) \
+_op_(PL310_CLEAN_LINE_BY_PA_0) \
+_op_(PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0) \
+_op_(PL310_CLEAN_BY_WAY_0) \
+_op_(PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0) \
+_op_(PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0) \
+_op_(PL310_CLEAN_AND_INVALIDATE_BY_WAY_0) \
+_op_(PL310_DATA_LOCKDOWN0_0) \
+_op_(PL310_INSTRUCTION_LOCKDOWN0_0) \
+_op_(PL310_DATA_LOCKDOWN1_0) \
+_op_(PL310_INSTRUCTION_LOCKDOWN1_0) \
+_op_(PL310_DATA_LOCKDOWN2_0) \
+_op_(PL310_INSTRUCTION_LOCKDOWN2_0) \
+_op_(PL310_DATA_LOCKDOWN3_0) \
+_op_(PL310_INSTRUCTION_LOCKDOWN3_0) \
+_op_(PL310_DATA_LOCKDOWN4_0) \
+_op_(PL310_INSTRUCTION_LOCKDOWN4_0) \
+_op_(PL310_DATA_LOCKDOWN5_0) \
+_op_(PL310_INSTRUCTION_LOCKDOWN5_0) \
+_op_(PL310_DATA_LOCKDOWN6_0) \
+_op_(PL310_INSTRUCTION_LOCKDOWN6_0) \
+_op_(PL310_DATA_LOCKDOWN7_0) \
+_op_(PL310_INSTRUCTION_LOCKDOWN7_0) \
+_op_(PL310_ADDRESS_FILTERING_START_0) \
+_op_(PL310_ADDRESS_FILTERING_END_0) \
+_op_(PL310_DEBUG_CONTROL_0) \
+_op_(PL310_PREFETCH_OFFSET_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_PL310      0x00000000
+
+//
+// ARPL310 REGISTER BANKS
+//
+
+#define PL3100_FIRST_REG 0x0000 // PL310_CACHE_ID_0
+#define PL3100_LAST_REG 0x0004 // PL310_CACHE_TYPE_0
+#define PL3101_FIRST_REG 0x0100 // PL310_CONTROL_0
+#define PL3101_LAST_REG 0x010c // PL310_DATA_RAM_LATENCY_0
+#define PL3102_FIRST_REG 0x0200 // PL310_EVENT_COUNTER_CONTROL_0
+#define PL3102_LAST_REG 0x0220 // PL310_INTERRUPT_CLEAR_0
+#define PL3103_FIRST_REG 0x0730 // PL310_CACHE_SYNC_0
+#define PL3103_LAST_REG 0x0730 // PL310_CACHE_SYNC_0
+#define PL3104_FIRST_REG 0x0770 // PL310_INVALIDATE_LINE_BY_PA_0
+#define PL3104_LAST_REG 0x0770 // PL310_INVALIDATE_LINE_BY_PA_0
+#define PL3105_FIRST_REG 0x077c // PL310_INVALIDATE_BY_WAY_0
+#define PL3105_LAST_REG 0x077c // PL310_INVALIDATE_BY_WAY_0
+#define PL3106_FIRST_REG 0x07b0 // PL310_CLEAN_LINE_BY_PA_0
+#define PL3106_LAST_REG 0x07b0 // PL310_CLEAN_LINE_BY_PA_0
+#define PL3107_FIRST_REG 0x07b8 // PL310_CLEAN_LINE_BY_INDEX_AND_WAY_0
+#define PL3107_LAST_REG 0x07bc // PL310_CLEAN_BY_WAY_0
+#define PL3108_FIRST_REG 0x07f0 // PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0
+#define PL3108_LAST_REG 0x07f0 // PL310_CLEAN_AND_INVALIDATE_LINE_BY_PA_0
+#define PL3109_FIRST_REG 0x07f8 // PL310_CLEAN_AND_INVALIDATE_LINE_BY_INDEX_AND_WAY_0
+#define PL3109_LAST_REG 0x07fc // PL310_CLEAN_AND_INVALIDATE_BY_WAY_0
+#define PL31010_FIRST_REG 0x0900 // PL310_DATA_LOCKDOWN0_0
+#define PL31010_LAST_REG 0x093c // PL310_INSTRUCTION_LOCKDOWN7_0
+#define PL31011_FIRST_REG 0x0c00 // PL310_ADDRESS_FILTERING_START_0
+#define PL31011_LAST_REG 0x0c04 // PL310_ADDRESS_FILTERING_END_0
+#define PL31012_FIRST_REG 0x0f40 // PL310_DEBUG_CONTROL_0
+#define PL31012_LAST_REG 0x0f40 // PL310_DEBUG_CONTROL_0
+#define PL31013_FIRST_REG 0x0f60 // PL310_PREFETCH_OFFSET_0
+#define PL31013_LAST_REG 0x0f60 // PL310_PREFETCH_OFFSET_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARPL310_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arscu.h b/arch/arm/mach-tegra/nv/include/ap20/arscu.h
new file mode 100644
index 000000000000..f4626a526df7
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arscu.h
@@ -0,0 +1,583 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARSCU_H_INC_
+#define ___ARSCU_H_INC_
+
+// Register SCU_CONTROL_0  
+#define SCU_CONTROL_0                   _MK_ADDR_CONST(0x0)
+#define SCU_CONTROL_0_SECURE                    0x0
+#define SCU_CONTROL_0_WORD_COUNT                        0x1
+#define SCU_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SCU_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x7)
+#define SCU_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SCU_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SCU_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x7)
+#define SCU_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x7)
+#define SCU_CONTROL_0_SCU_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define SCU_CONTROL_0_SCU_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << SCU_CONTROL_0_SCU_ENABLE_SHIFT)
+#define SCU_CONTROL_0_SCU_ENABLE_RANGE                  0:0
+#define SCU_CONTROL_0_SCU_ENABLE_WOFFSET                        0x0
+#define SCU_CONTROL_0_SCU_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_CONTROL_0_SCU_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SCU_CONTROL_0_SCU_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SCU_CONTROL_0_SCU_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define SCU_CONTROL_0_ADDR_FILTER_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define SCU_CONTROL_0_ADDR_FILTER_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << SCU_CONTROL_0_ADDR_FILTER_ENABLE_SHIFT)
+#define SCU_CONTROL_0_ADDR_FILTER_ENABLE_RANGE                  1:1
+#define SCU_CONTROL_0_ADDR_FILTER_ENABLE_WOFFSET                        0x0
+#define SCU_CONTROL_0_ADDR_FILTER_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_CONTROL_0_ADDR_FILTER_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SCU_CONTROL_0_ADDR_FILTER_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SCU_CONTROL_0_ADDR_FILTER_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define SCU_CONTROL_0_PARITY_ON_SHIFT                   _MK_SHIFT_CONST(2)
+#define SCU_CONTROL_0_PARITY_ON_FIELD                   (_MK_MASK_CONST(0x1) << SCU_CONTROL_0_PARITY_ON_SHIFT)
+#define SCU_CONTROL_0_PARITY_ON_RANGE                   2:2
+#define SCU_CONTROL_0_PARITY_ON_WOFFSET                 0x0
+#define SCU_CONTROL_0_PARITY_ON_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SCU_CONTROL_0_PARITY_ON_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SCU_CONTROL_0_PARITY_ON_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SCU_CONTROL_0_PARITY_ON_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register SCU_CONFIG_0  
+#define SCU_CONFIG_0                    _MK_ADDR_CONST(0x4)
+#define SCU_CONFIG_0_SECURE                     0x0
+#define SCU_CONFIG_0_WORD_COUNT                         0x1
+#define SCU_CONFIG_0_RESET_VAL                  _MK_MASK_CONST(0xff00)
+#define SCU_CONFIG_0_RESET_MASK                         _MK_MASK_CONST(0xfff3)
+#define SCU_CONFIG_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_READ_MASK                  _MK_MASK_CONST(0xfff3)
+#define SCU_CONFIG_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU_NUM_SHIFT                      _MK_SHIFT_CONST(0)
+#define SCU_CONFIG_0_CPU_NUM_FIELD                      (_MK_MASK_CONST(0x3) << SCU_CONFIG_0_CPU_NUM_SHIFT)
+#define SCU_CONFIG_0_CPU_NUM_RANGE                      1:0
+#define SCU_CONFIG_0_CPU_NUM_WOFFSET                    0x0
+#define SCU_CONFIG_0_CPU_NUM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU_NUM_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define SCU_CONFIG_0_CPU_NUM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU_NUM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU_NUM_INIT_ENUM                  ONE
+#define SCU_CONFIG_0_CPU_NUM_ONE                        _MK_ENUM_CONST(0)
+#define SCU_CONFIG_0_CPU_NUM_TWO                        _MK_ENUM_CONST(1)
+#define SCU_CONFIG_0_CPU_NUM_THREE                      _MK_ENUM_CONST(2)
+#define SCU_CONFIG_0_CPU_NUM_FOUR                       _MK_ENUM_CONST(3)
+
+// define SMP mode for core 0
+#define SCU_CONFIG_0_CPU0_SMP_SHIFT                     _MK_SHIFT_CONST(4)
+#define SCU_CONFIG_0_CPU0_SMP_FIELD                     (_MK_MASK_CONST(0x1) << SCU_CONFIG_0_CPU0_SMP_SHIFT)
+#define SCU_CONFIG_0_CPU0_SMP_RANGE                     4:4
+#define SCU_CONFIG_0_CPU0_SMP_WOFFSET                   0x0
+#define SCU_CONFIG_0_CPU0_SMP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU0_SMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_CONFIG_0_CPU0_SMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU0_SMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//                     core 1
+#define SCU_CONFIG_0_CPU1_SMP_SHIFT                     _MK_SHIFT_CONST(5)
+#define SCU_CONFIG_0_CPU1_SMP_FIELD                     (_MK_MASK_CONST(0x1) << SCU_CONFIG_0_CPU1_SMP_SHIFT)
+#define SCU_CONFIG_0_CPU1_SMP_RANGE                     5:5
+#define SCU_CONFIG_0_CPU1_SMP_WOFFSET                   0x0
+#define SCU_CONFIG_0_CPU1_SMP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU1_SMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_CONFIG_0_CPU1_SMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU1_SMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//                     core 2
+#define SCU_CONFIG_0_CPU2_SMP_SHIFT                     _MK_SHIFT_CONST(6)
+#define SCU_CONFIG_0_CPU2_SMP_FIELD                     (_MK_MASK_CONST(0x1) << SCU_CONFIG_0_CPU2_SMP_SHIFT)
+#define SCU_CONFIG_0_CPU2_SMP_RANGE                     6:6
+#define SCU_CONFIG_0_CPU2_SMP_WOFFSET                   0x0
+#define SCU_CONFIG_0_CPU2_SMP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU2_SMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_CONFIG_0_CPU2_SMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU2_SMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//                     core 3
+#define SCU_CONFIG_0_CPU3_SMP_SHIFT                     _MK_SHIFT_CONST(7)
+#define SCU_CONFIG_0_CPU3_SMP_FIELD                     (_MK_MASK_CONST(0x1) << SCU_CONFIG_0_CPU3_SMP_SHIFT)
+#define SCU_CONFIG_0_CPU3_SMP_RANGE                     7:7
+#define SCU_CONFIG_0_CPU3_SMP_WOFFSET                   0x0
+#define SCU_CONFIG_0_CPU3_SMP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU3_SMP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_CONFIG_0_CPU3_SMP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU3_SMP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_SHIFT                    _MK_SHIFT_CONST(8)
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_FIELD                    (_MK_MASK_CONST(0x3) << SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_SHIFT)
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_RANGE                    9:8
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_WOFFSET                  0x0
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_DEFAULT                  _MK_MASK_CONST(0x3)
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_INIT_ENUM                        T64KB
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_T16KB                    _MK_ENUM_CONST(0)
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_T32KB                    _MK_ENUM_CONST(1)
+#define SCU_CONFIG_0_CPU0_TAG_RAM_SIZE_T64KB                    _MK_ENUM_CONST(3)
+
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_SHIFT                    _MK_SHIFT_CONST(10)
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_FIELD                    (_MK_MASK_CONST(0x3) << SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_SHIFT)
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_RANGE                    11:10
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_WOFFSET                  0x0
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_DEFAULT                  _MK_MASK_CONST(0x3)
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_INIT_ENUM                        T64KB
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_T16KB                    _MK_ENUM_CONST(0)
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_T32KB                    _MK_ENUM_CONST(1)
+#define SCU_CONFIG_0_CPU1_TAG_RAM_SIZE_T64KB                    _MK_ENUM_CONST(3)
+
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_SHIFT                    _MK_SHIFT_CONST(12)
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_FIELD                    (_MK_MASK_CONST(0x3) << SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_SHIFT)
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_RANGE                    13:12
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_WOFFSET                  0x0
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_DEFAULT                  _MK_MASK_CONST(0x3)
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_INIT_ENUM                        T64KB
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_T16KB                    _MK_ENUM_CONST(0)
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_T32KB                    _MK_ENUM_CONST(1)
+#define SCU_CONFIG_0_CPU2_TAG_RAM_SIZE_T64KB                    _MK_ENUM_CONST(3)
+
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_SHIFT                    _MK_SHIFT_CONST(14)
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_FIELD                    (_MK_MASK_CONST(0x3) << SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_SHIFT)
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_RANGE                    15:14
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_WOFFSET                  0x0
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_DEFAULT                  _MK_MASK_CONST(0x3)
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_INIT_ENUM                        T64KB
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_T16KB                    _MK_ENUM_CONST(0)
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_T32KB                    _MK_ENUM_CONST(1)
+#define SCU_CONFIG_0_CPU3_TAG_RAM_SIZE_T64KB                    _MK_ENUM_CONST(3)
+
+
+// Register SCU_POWER_STATUS_0  
+#define SCU_POWER_STATUS_0                      _MK_ADDR_CONST(0x8)
+#define SCU_POWER_STATUS_0_SECURE                       0x0
+#define SCU_POWER_STATUS_0_WORD_COUNT                   0x1
+#define SCU_POWER_STATUS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_RESET_MASK                   _MK_MASK_CONST(0x3030303)
+#define SCU_POWER_STATUS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_READ_MASK                    _MK_MASK_CONST(0x3030303)
+#define SCU_POWER_STATUS_0_WRITE_MASK                   _MK_MASK_CONST(0x3030303)
+#define SCU_POWER_STATUS_0_CPU0_STATUS_SHIFT                    _MK_SHIFT_CONST(0)
+#define SCU_POWER_STATUS_0_CPU0_STATUS_FIELD                    (_MK_MASK_CONST(0x3) << SCU_POWER_STATUS_0_CPU0_STATUS_SHIFT)
+#define SCU_POWER_STATUS_0_CPU0_STATUS_RANGE                    1:0
+#define SCU_POWER_STATUS_0_CPU0_STATUS_WOFFSET                  0x0
+#define SCU_POWER_STATUS_0_CPU0_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU0_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SCU_POWER_STATUS_0_CPU0_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU0_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU0_STATUS_INIT_ENUM                        NORMAL
+#define SCU_POWER_STATUS_0_CPU0_STATUS_NORMAL                   _MK_ENUM_CONST(0)
+#define SCU_POWER_STATUS_0_CPU0_STATUS_DORMANT                  _MK_ENUM_CONST(2)
+#define SCU_POWER_STATUS_0_CPU0_STATUS_PWROFF                   _MK_ENUM_CONST(3)
+
+#define SCU_POWER_STATUS_0_CPU1_STATUS_SHIFT                    _MK_SHIFT_CONST(8)
+#define SCU_POWER_STATUS_0_CPU1_STATUS_FIELD                    (_MK_MASK_CONST(0x3) << SCU_POWER_STATUS_0_CPU1_STATUS_SHIFT)
+#define SCU_POWER_STATUS_0_CPU1_STATUS_RANGE                    9:8
+#define SCU_POWER_STATUS_0_CPU1_STATUS_WOFFSET                  0x0
+#define SCU_POWER_STATUS_0_CPU1_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU1_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SCU_POWER_STATUS_0_CPU1_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU1_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU1_STATUS_INIT_ENUM                        NORMAL
+#define SCU_POWER_STATUS_0_CPU1_STATUS_NORMAL                   _MK_ENUM_CONST(0)
+#define SCU_POWER_STATUS_0_CPU1_STATUS_DORMANT                  _MK_ENUM_CONST(2)
+#define SCU_POWER_STATUS_0_CPU1_STATUS_PWROFF                   _MK_ENUM_CONST(3)
+
+#define SCU_POWER_STATUS_0_CPU2_STATUS_SHIFT                    _MK_SHIFT_CONST(16)
+#define SCU_POWER_STATUS_0_CPU2_STATUS_FIELD                    (_MK_MASK_CONST(0x3) << SCU_POWER_STATUS_0_CPU2_STATUS_SHIFT)
+#define SCU_POWER_STATUS_0_CPU2_STATUS_RANGE                    17:16
+#define SCU_POWER_STATUS_0_CPU2_STATUS_WOFFSET                  0x0
+#define SCU_POWER_STATUS_0_CPU2_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU2_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SCU_POWER_STATUS_0_CPU2_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU2_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU2_STATUS_INIT_ENUM                        NORMAL
+#define SCU_POWER_STATUS_0_CPU2_STATUS_NORMAL                   _MK_ENUM_CONST(0)
+#define SCU_POWER_STATUS_0_CPU2_STATUS_DORMANT                  _MK_ENUM_CONST(2)
+#define SCU_POWER_STATUS_0_CPU2_STATUS_PWROFF                   _MK_ENUM_CONST(3)
+
+#define SCU_POWER_STATUS_0_CPU3_STATUS_SHIFT                    _MK_SHIFT_CONST(24)
+#define SCU_POWER_STATUS_0_CPU3_STATUS_FIELD                    (_MK_MASK_CONST(0x3) << SCU_POWER_STATUS_0_CPU3_STATUS_SHIFT)
+#define SCU_POWER_STATUS_0_CPU3_STATUS_RANGE                    25:24
+#define SCU_POWER_STATUS_0_CPU3_STATUS_WOFFSET                  0x0
+#define SCU_POWER_STATUS_0_CPU3_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU3_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SCU_POWER_STATUS_0_CPU3_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU3_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SCU_POWER_STATUS_0_CPU3_STATUS_INIT_ENUM                        NORMAL
+#define SCU_POWER_STATUS_0_CPU3_STATUS_NORMAL                   _MK_ENUM_CONST(0)
+#define SCU_POWER_STATUS_0_CPU3_STATUS_DORMANT                  _MK_ENUM_CONST(2)
+#define SCU_POWER_STATUS_0_CPU3_STATUS_PWROFF                   _MK_ENUM_CONST(3)
+
+
+// Register SCU_INVALID_ALL_0  
+#define SCU_INVALID_ALL_0                       _MK_ADDR_CONST(0xc)
+#define SCU_INVALID_ALL_0_SECURE                        0x0
+#define SCU_INVALID_ALL_0_WORD_COUNT                    0x1
+#define SCU_INVALID_ALL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define SCU_INVALID_ALL_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define SCU_INVALID_ALL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define SCU_INVALID_ALL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SCU_INVALID_ALL_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define SCU_INVALID_ALL_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
+#define SCU_INVALID_ALL_0_CPU0_WAYS_SHIFT                       _MK_SHIFT_CONST(0)
+#define SCU_INVALID_ALL_0_CPU0_WAYS_FIELD                       (_MK_MASK_CONST(0xf) << SCU_INVALID_ALL_0_CPU0_WAYS_SHIFT)
+#define SCU_INVALID_ALL_0_CPU0_WAYS_RANGE                       3:0
+#define SCU_INVALID_ALL_0_CPU0_WAYS_WOFFSET                     0x0
+#define SCU_INVALID_ALL_0_CPU0_WAYS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SCU_INVALID_ALL_0_CPU0_WAYS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define SCU_INVALID_ALL_0_CPU0_WAYS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_INVALID_ALL_0_CPU0_WAYS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define SCU_INVALID_ALL_0_CPU1_WAYS_SHIFT                       _MK_SHIFT_CONST(4)
+#define SCU_INVALID_ALL_0_CPU1_WAYS_FIELD                       (_MK_MASK_CONST(0xf) << SCU_INVALID_ALL_0_CPU1_WAYS_SHIFT)
+#define SCU_INVALID_ALL_0_CPU1_WAYS_RANGE                       7:4
+#define SCU_INVALID_ALL_0_CPU1_WAYS_WOFFSET                     0x0
+#define SCU_INVALID_ALL_0_CPU1_WAYS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SCU_INVALID_ALL_0_CPU1_WAYS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define SCU_INVALID_ALL_0_CPU1_WAYS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_INVALID_ALL_0_CPU1_WAYS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define SCU_INVALID_ALL_0_CPU2_WAYS_SHIFT                       _MK_SHIFT_CONST(8)
+#define SCU_INVALID_ALL_0_CPU2_WAYS_FIELD                       (_MK_MASK_CONST(0xf) << SCU_INVALID_ALL_0_CPU2_WAYS_SHIFT)
+#define SCU_INVALID_ALL_0_CPU2_WAYS_RANGE                       11:8
+#define SCU_INVALID_ALL_0_CPU2_WAYS_WOFFSET                     0x0
+#define SCU_INVALID_ALL_0_CPU2_WAYS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SCU_INVALID_ALL_0_CPU2_WAYS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define SCU_INVALID_ALL_0_CPU2_WAYS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_INVALID_ALL_0_CPU2_WAYS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define SCU_INVALID_ALL_0_CPU3_WAYS_SHIFT                       _MK_SHIFT_CONST(12)
+#define SCU_INVALID_ALL_0_CPU3_WAYS_FIELD                       (_MK_MASK_CONST(0xf) << SCU_INVALID_ALL_0_CPU3_WAYS_SHIFT)
+#define SCU_INVALID_ALL_0_CPU3_WAYS_RANGE                       15:12
+#define SCU_INVALID_ALL_0_CPU3_WAYS_WOFFSET                     0x0
+#define SCU_INVALID_ALL_0_CPU3_WAYS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SCU_INVALID_ALL_0_CPU3_WAYS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define SCU_INVALID_ALL_0_CPU3_WAYS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_INVALID_ALL_0_CPU3_WAYS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Reserved address 16 [0x10] 
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 24 [0x18] 
+
+// Reserved address 28 [0x1c] 
+
+// Reserved address 32 [0x20] 
+
+// Reserved address 36 [0x24] 
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Register SCU_FILTER_START_0  
+#define SCU_FILTER_START_0                      _MK_ADDR_CONST(0x40)
+#define SCU_FILTER_START_0_SECURE                       0x0
+#define SCU_FILTER_START_0_WORD_COUNT                   0x1
+#define SCU_FILTER_START_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define SCU_FILTER_START_0_RESET_MASK                   _MK_MASK_CONST(0xfff00000)
+#define SCU_FILTER_START_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define SCU_FILTER_START_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SCU_FILTER_START_0_READ_MASK                    _MK_MASK_CONST(0xfff00000)
+#define SCU_FILTER_START_0_WRITE_MASK                   _MK_MASK_CONST(0xfff00000)
+#define SCU_FILTER_START_0_ADDR_SHIFT                   _MK_SHIFT_CONST(20)
+#define SCU_FILTER_START_0_ADDR_FIELD                   (_MK_MASK_CONST(0xfff) << SCU_FILTER_START_0_ADDR_SHIFT)
+#define SCU_FILTER_START_0_ADDR_RANGE                   31:20
+#define SCU_FILTER_START_0_ADDR_WOFFSET                 0x0
+#define SCU_FILTER_START_0_ADDR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SCU_FILTER_START_0_ADDR_DEFAULT_MASK                    _MK_MASK_CONST(0xfff)
+#define SCU_FILTER_START_0_ADDR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SCU_FILTER_START_0_ADDR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register SCU_FILTER_END_0  
+#define SCU_FILTER_END_0                        _MK_ADDR_CONST(0x44)
+#define SCU_FILTER_END_0_SECURE                         0x0
+#define SCU_FILTER_END_0_WORD_COUNT                     0x1
+#define SCU_FILTER_END_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SCU_FILTER_END_0_RESET_MASK                     _MK_MASK_CONST(0xfff00000)
+#define SCU_FILTER_END_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SCU_FILTER_END_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SCU_FILTER_END_0_READ_MASK                      _MK_MASK_CONST(0xfff00000)
+#define SCU_FILTER_END_0_WRITE_MASK                     _MK_MASK_CONST(0xfff00000)
+#define SCU_FILTER_END_0_ADDR_SHIFT                     _MK_SHIFT_CONST(20)
+#define SCU_FILTER_END_0_ADDR_FIELD                     (_MK_MASK_CONST(0xfff) << SCU_FILTER_END_0_ADDR_SHIFT)
+#define SCU_FILTER_END_0_ADDR_RANGE                     31:20
+#define SCU_FILTER_END_0_ADDR_WOFFSET                   0x0
+#define SCU_FILTER_END_0_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_FILTER_END_0_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
+#define SCU_FILTER_END_0_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_FILTER_END_0_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Register SCU_ACCESS_CONTROL_0  
+#define SCU_ACCESS_CONTROL_0                    _MK_ADDR_CONST(0x50)
+#define SCU_ACCESS_CONTROL_0_SECURE                     0x0
+#define SCU_ACCESS_CONTROL_0_WORD_COUNT                         0x1
+#define SCU_ACCESS_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0xf)
+#define SCU_ACCESS_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0xf)
+#define SCU_ACCESS_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define SCU_ACCESS_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SCU_ACCESS_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0xf)
+#define SCU_ACCESS_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0xf)
+// 1: access_allowed
+#define SCU_ACCESS_CONTROL_0_CPU0_CTRL_SHIFT                    _MK_SHIFT_CONST(0)
+#define SCU_ACCESS_CONTROL_0_CPU0_CTRL_FIELD                    (_MK_MASK_CONST(0x1) << SCU_ACCESS_CONTROL_0_CPU0_CTRL_SHIFT)
+#define SCU_ACCESS_CONTROL_0_CPU0_CTRL_RANGE                    0:0
+#define SCU_ACCESS_CONTROL_0_CPU0_CTRL_WOFFSET                  0x0
+#define SCU_ACCESS_CONTROL_0_CPU0_CTRL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define SCU_ACCESS_CONTROL_0_CPU0_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SCU_ACCESS_CONTROL_0_CPU0_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_ACCESS_CONTROL_0_CPU0_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define SCU_ACCESS_CONTROL_0_CPU1_CTRL_SHIFT                    _MK_SHIFT_CONST(1)
+#define SCU_ACCESS_CONTROL_0_CPU1_CTRL_FIELD                    (_MK_MASK_CONST(0x1) << SCU_ACCESS_CONTROL_0_CPU1_CTRL_SHIFT)
+#define SCU_ACCESS_CONTROL_0_CPU1_CTRL_RANGE                    1:1
+#define SCU_ACCESS_CONTROL_0_CPU1_CTRL_WOFFSET                  0x0
+#define SCU_ACCESS_CONTROL_0_CPU1_CTRL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define SCU_ACCESS_CONTROL_0_CPU1_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SCU_ACCESS_CONTROL_0_CPU1_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_ACCESS_CONTROL_0_CPU1_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define SCU_ACCESS_CONTROL_0_CPU2_CTRL_SHIFT                    _MK_SHIFT_CONST(2)
+#define SCU_ACCESS_CONTROL_0_CPU2_CTRL_FIELD                    (_MK_MASK_CONST(0x1) << SCU_ACCESS_CONTROL_0_CPU2_CTRL_SHIFT)
+#define SCU_ACCESS_CONTROL_0_CPU2_CTRL_RANGE                    2:2
+#define SCU_ACCESS_CONTROL_0_CPU2_CTRL_WOFFSET                  0x0
+#define SCU_ACCESS_CONTROL_0_CPU2_CTRL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define SCU_ACCESS_CONTROL_0_CPU2_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SCU_ACCESS_CONTROL_0_CPU2_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_ACCESS_CONTROL_0_CPU2_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define SCU_ACCESS_CONTROL_0_CPU3_CTRL_SHIFT                    _MK_SHIFT_CONST(3)
+#define SCU_ACCESS_CONTROL_0_CPU3_CTRL_FIELD                    (_MK_MASK_CONST(0x1) << SCU_ACCESS_CONTROL_0_CPU3_CTRL_SHIFT)
+#define SCU_ACCESS_CONTROL_0_CPU3_CTRL_RANGE                    3:3
+#define SCU_ACCESS_CONTROL_0_CPU3_CTRL_WOFFSET                  0x0
+#define SCU_ACCESS_CONTROL_0_CPU3_CTRL_DEFAULT                  _MK_MASK_CONST(0x1)
+#define SCU_ACCESS_CONTROL_0_CPU3_CTRL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SCU_ACCESS_CONTROL_0_CPU3_CTRL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_ACCESS_CONTROL_0_CPU3_CTRL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SCU_SECURE_ACCESS_CONTROL_0  
+#define SCU_SECURE_ACCESS_CONTROL_0                     _MK_ADDR_CONST(0x54)
+#define SCU_SECURE_ACCESS_CONTROL_0_SECURE                      0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_WORD_COUNT                  0x1
+#define SCU_SECURE_ACCESS_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0xfff)
+#define SCU_SECURE_ACCESS_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0xfff)
+#define SCU_SECURE_ACCESS_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0xfff)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_SHIFT                     _MK_SHIFT_CONST(0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_FIELD                     (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_RANGE                     0:0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_WOFFSET                   0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_SHIFT                     _MK_SHIFT_CONST(1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_FIELD                     (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_RANGE                     1:1
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_WOFFSET                   0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_SHIFT                     _MK_SHIFT_CONST(2)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_FIELD                     (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_RANGE                     2:2
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_WOFFSET                   0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_SHIFT                     _MK_SHIFT_CONST(3)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_FIELD                     (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_RANGE                     3:3
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_WOFFSET                   0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_CTRL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_SHIFT                    _MK_SHIFT_CONST(4)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_FIELD                    (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_RANGE                    4:4
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_WOFFSET                  0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_TIMER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_SHIFT                    _MK_SHIFT_CONST(5)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_FIELD                    (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_RANGE                    5:5
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_WOFFSET                  0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_TIMER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_SHIFT                    _MK_SHIFT_CONST(6)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_FIELD                    (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_RANGE                    6:6
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_WOFFSET                  0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_TIMER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_SHIFT                    _MK_SHIFT_CONST(7)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_FIELD                    (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_RANGE                    7:7
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_WOFFSET                  0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_TIMER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_SHIFT                     _MK_SHIFT_CONST(8)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_FIELD                     (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_RANGE                     8:8
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_WOFFSET                   0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU0_GLOBAL_TIMER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_SHIFT                     _MK_SHIFT_CONST(9)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_FIELD                     (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_RANGE                     9:9
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_WOFFSET                   0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU1_GLOBAL_TIMER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_SHIFT                     _MK_SHIFT_CONST(10)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_FIELD                     (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_RANGE                     10:10
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_WOFFSET                   0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU2_GLOBAL_TIMER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_SHIFT                     _MK_SHIFT_CONST(11)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_FIELD                     (_MK_MASK_CONST(0x1) << SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_SHIFT)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_RANGE                     11:11
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_WOFFSET                   0x0
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SCU_SECURE_ACCESS_CONTROL_0_CPU3_GLOBAL_TIMER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSCU_REGS(_op_) \
+_op_(SCU_CONTROL_0) \
+_op_(SCU_CONFIG_0) \
+_op_(SCU_POWER_STATUS_0) \
+_op_(SCU_INVALID_ALL_0) \
+_op_(SCU_FILTER_START_0) \
+_op_(SCU_FILTER_END_0) \
+_op_(SCU_ACCESS_CONTROL_0) \
+_op_(SCU_SECURE_ACCESS_CONTROL_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_SCU        0x00000000
+
+//
+// ARSCU REGISTER BANKS
+//
+
+#define SCU0_FIRST_REG 0x0000 // SCU_CONTROL_0
+#define SCU0_LAST_REG 0x000c // SCU_INVALID_ALL_0
+#define SCU1_FIRST_REG 0x0040 // SCU_FILTER_START_0
+#define SCU1_LAST_REG 0x0044 // SCU_FILTER_END_0
+#define SCU2_FIRST_REG 0x0050 // SCU_ACCESS_CONTROL_0
+#define SCU2_LAST_REG 0x0054 // SCU_SECURE_ACCESS_CONTROL_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARSCU_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arsdmmc.h b/arch/arm/mach-tegra/nv/include/ap20/arsdmmc.h
new file mode 100644
index 000000000000..e4505b05f3cb
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arsdmmc.h
@@ -0,0 +1,2756 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARSDMMC_H_INC_
+#define ___ARSDMMC_H_INC_
+
+// Register SDMMC_SYSTEM_ADDRESS_0  
+#define SDMMC_SYSTEM_ADDRESS_0                  _MK_ADDR_CONST(0x0)
+#define SDMMC_SYSTEM_ADDRESS_0_SECURE                   0x0
+#define SDMMC_SYSTEM_ADDRESS_0_WORD_COUNT                       0x1
+#define SDMMC_SYSTEM_ADDRESS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define SDMMC_SYSTEM_ADDRESS_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SDMMC_SYSTEM_ADDRESS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SDMMC_SYSTEM_ADDRESS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_SYSTEM_ADDRESS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SDMMC_SYSTEM_ADDRESS_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SDMMC_SYSTEM_ADDRESS_0_ADDRESS_SHIFT                    _MK_SHIFT_CONST(0)
+#define SDMMC_SYSTEM_ADDRESS_0_ADDRESS_FIELD                    (_MK_MASK_CONST(0xffffffff) << SDMMC_SYSTEM_ADDRESS_0_ADDRESS_SHIFT)
+#define SDMMC_SYSTEM_ADDRESS_0_ADDRESS_RANGE                    31:0
+#define SDMMC_SYSTEM_ADDRESS_0_ADDRESS_WOFFSET                  0x0
+#define SDMMC_SYSTEM_ADDRESS_0_ADDRESS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_SYSTEM_ADDRESS_0_ADDRESS_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SDMMC_SYSTEM_ADDRESS_0_ADDRESS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_SYSTEM_ADDRESS_0_ADDRESS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_BLOCK_SIZE_BLOCK_COUNT_0  
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0                  _MK_ADDR_CONST(0x4)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_SECURE                   0x0
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_WORD_COUNT                       0x1
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_SHIFT                       _MK_SHIFT_CONST(16)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_FIELD                       (_MK_MASK_CONST(0xffff) << SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_SHIFT)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_RANGE                       31:16
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_WOFFSET                     0x0
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_DEFAULT_MASK                        _MK_MASK_CONST(0xffff)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_BLOCKS_COUNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_12_SHIFT                 _MK_SHIFT_CONST(15)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_12_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_12_SHIFT)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_12_RANGE                 15:15
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_12_WOFFSET                       0x0
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_SHIFT                       _MK_SHIFT_CONST(12)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_FIELD                       (_MK_MASK_CONST(0x7) << SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_SHIFT)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_RANGE                       14:12
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_WOFFSET                     0x0
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA4K                       _MK_ENUM_CONST(0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA8K                       _MK_ENUM_CONST(1)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA16K                      _MK_ENUM_CONST(2)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA32K                      _MK_ENUM_CONST(3)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA64K                      _MK_ENUM_CONST(4)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA128K                     _MK_ENUM_CONST(5)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA256K                     _MK_ENUM_CONST(6)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_HOST_DMA_BUFFER_SIZE_DMA512K                     _MK_ENUM_CONST(7)
+
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_FIELD                       (_MK_MASK_CONST(0xfff) << SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_SHIFT)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_RANGE                       11:0
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_WOFFSET                     0x0
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_DEFAULT_MASK                        _MK_MASK_CONST(0xfff)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_BLOCK_SIZE_BLOCK_COUNT_0_XFER_BLOCK_SIZE_11_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_ARGUMENT_0  
+#define SDMMC_ARGUMENT_0                        _MK_ADDR_CONST(0x8)
+#define SDMMC_ARGUMENT_0_SECURE                         0x0
+#define SDMMC_ARGUMENT_0_WORD_COUNT                     0x1
+#define SDMMC_ARGUMENT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SDMMC_ARGUMENT_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SDMMC_ARGUMENT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SDMMC_ARGUMENT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_ARGUMENT_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SDMMC_ARGUMENT_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SDMMC_ARGUMENT_0_COMMAND_ARGUMENT_SHIFT                 _MK_SHIFT_CONST(0)
+#define SDMMC_ARGUMENT_0_COMMAND_ARGUMENT_FIELD                 (_MK_MASK_CONST(0xffffffff) << SDMMC_ARGUMENT_0_COMMAND_ARGUMENT_SHIFT)
+#define SDMMC_ARGUMENT_0_COMMAND_ARGUMENT_RANGE                 31:0
+#define SDMMC_ARGUMENT_0_COMMAND_ARGUMENT_WOFFSET                       0x0
+#define SDMMC_ARGUMENT_0_COMMAND_ARGUMENT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_ARGUMENT_0_COMMAND_ARGUMENT_DEFAULT_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SDMMC_ARGUMENT_0_COMMAND_ARGUMENT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_ARGUMENT_0_COMMAND_ARGUMENT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_CMD_XFER_MODE_0  
+#define SDMMC_CMD_XFER_MODE_0                   _MK_ADDR_CONST(0xc)
+#define SDMMC_CMD_XFER_MODE_0_SECURE                    0x0
+#define SDMMC_CMD_XFER_MODE_0_WORD_COUNT                        0x1
+#define SDMMC_CMD_XFER_MODE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_RESET_MASK                        _MK_MASK_CONST(0x3ffb00f7)
+#define SDMMC_CMD_XFER_MODE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_READ_MASK                         _MK_MASK_CONST(0x3ffb00f7)
+#define SDMMC_CMD_XFER_MODE_0_WRITE_MASK                        _MK_MASK_CONST(0x3ffb00f7)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_INDEX_SHIFT                       _MK_SHIFT_CONST(24)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_INDEX_FIELD                       (_MK_MASK_CONST(0x3f) << SDMMC_CMD_XFER_MODE_0_COMMAND_INDEX_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_INDEX_RANGE                       29:24
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_INDEX_WOFFSET                     0x0
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_INDEX_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_INDEX_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_INDEX_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_INDEX_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_SHIFT                        _MK_SHIFT_CONST(22)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_FIELD                        (_MK_MASK_CONST(0x3) << SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_RANGE                        23:22
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_WOFFSET                      0x0
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_NORMAL                       _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_SUSPEND                      _MK_ENUM_CONST(1)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_RESUME                       _MK_ENUM_CONST(2)
+#define SDMMC_CMD_XFER_MODE_0_COMMAND_TYPE_ABORT                        _MK_ENUM_CONST(3)
+
+#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_SHIFT                 _MK_SHIFT_CONST(21)
+#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_RANGE                 21:21
+#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_WOFFSET                       0x0
+#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_NO_DATA_TRANSFER                      _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_DATA_PRESENT_SELECT_DATA_TRANSFER                 _MK_ENUM_CONST(1)
+
+#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_SHIFT                  _MK_SHIFT_CONST(20)
+#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_RANGE                  20:20
+#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_WOFFSET                        0x0
+#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_INDEX_CHECK_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_SHIFT                    _MK_SHIFT_CONST(19)
+#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_RANGE                    19:19
+#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_WOFFSET                  0x0
+#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_CRC_CHECK_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SHIFT                    _MK_SHIFT_CONST(16)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_FIELD                    (_MK_MASK_CONST(0x3) << SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RANGE                    17:16
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_WOFFSET                  0x0
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_NO_RESPONSE                      _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RESP_LENGTH_136                  _MK_ENUM_CONST(1)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RESP_LENGTH_48                   _MK_ENUM_CONST(2)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_RESP_LENGTH_48BUSY                       _MK_ENUM_CONST(3)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SPI_R1_RESPONSE                  _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SPI_R2_RESPONSE                  _MK_ENUM_CONST(1)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SPI_R3_RESPONSE                  _MK_ENUM_CONST(2)
+#define SDMMC_CMD_XFER_MODE_0_RESP_TYPE_SELECT_SPI_R1b_RESPONSE                 _MK_ENUM_CONST(3)
+
+#define SDMMC_CMD_XFER_MODE_0_SPI_MODE_SHIFT                    _MK_SHIFT_CONST(7)
+#define SDMMC_CMD_XFER_MODE_0_SPI_MODE_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_CMD_XFER_MODE_0_SPI_MODE_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_SPI_MODE_RANGE                    7:7
+#define SDMMC_CMD_XFER_MODE_0_SPI_MODE_WOFFSET                  0x0
+#define SDMMC_CMD_XFER_MODE_0_SPI_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_SPI_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_CMD_XFER_MODE_0_SPI_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_SPI_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_SPI_MODE_DISABLE                  _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_SPI_MODE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define SDMMC_CMD_XFER_MODE_0_CMD_COMP_ATA_SHIFT                        _MK_SHIFT_CONST(6)
+#define SDMMC_CMD_XFER_MODE_0_CMD_COMP_ATA_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_CMD_XFER_MODE_0_CMD_COMP_ATA_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_CMD_COMP_ATA_RANGE                        6:6
+#define SDMMC_CMD_XFER_MODE_0_CMD_COMP_ATA_WOFFSET                      0x0
+#define SDMMC_CMD_XFER_MODE_0_CMD_COMP_ATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_COMP_ATA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_CMD_XFER_MODE_0_CMD_COMP_ATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_COMP_ATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_COMP_ATA_DISABLE                      _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_CMD_COMP_ATA_ENABLE                       _MK_ENUM_CONST(1)
+
+#define SDMMC_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_SHIFT                  _MK_SHIFT_CONST(5)
+#define SDMMC_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_RANGE                  5:5
+#define SDMMC_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_WOFFSET                        0x0
+#define SDMMC_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_DISABLE                        _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_MULTI_BLOCK_SELECT_ENABLE                 _MK_ENUM_CONST(1)
+
+#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_SHIFT                   _MK_SHIFT_CONST(4)
+#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_RANGE                   4:4
+#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_WOFFSET                 0x0
+#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_WRITE                   _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_DATA_XFER_DIR_SEL_READ                    _MK_ENUM_CONST(1)
+
+#define SDMMC_CMD_XFER_MODE_0_AUTO_CMD12_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define SDMMC_CMD_XFER_MODE_0_AUTO_CMD12_EN_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_CMD_XFER_MODE_0_AUTO_CMD12_EN_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_AUTO_CMD12_EN_RANGE                       2:2
+#define SDMMC_CMD_XFER_MODE_0_AUTO_CMD12_EN_WOFFSET                     0x0
+#define SDMMC_CMD_XFER_MODE_0_AUTO_CMD12_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_AUTO_CMD12_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_CMD_XFER_MODE_0_AUTO_CMD12_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_AUTO_CMD12_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_AUTO_CMD12_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_AUTO_CMD12_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_SHIFT                      _MK_SHIFT_CONST(1)
+#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_RANGE                      1:1
+#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_WOFFSET                    0x0
+#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_BLOCK_COUNT_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define SDMMC_CMD_XFER_MODE_0_DMA_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_DMA_EN_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_CMD_XFER_MODE_0_DMA_EN_SHIFT)
+#define SDMMC_CMD_XFER_MODE_0_DMA_EN_RANGE                      0:0
+#define SDMMC_CMD_XFER_MODE_0_DMA_EN_WOFFSET                    0x0
+#define SDMMC_CMD_XFER_MODE_0_DMA_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_DMA_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_CMD_XFER_MODE_0_DMA_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_DMA_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_CMD_XFER_MODE_0_DMA_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SDMMC_CMD_XFER_MODE_0_DMA_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_RESPONSE_R0_R1_0  
+#define SDMMC_RESPONSE_R0_R1_0                  _MK_ADDR_CONST(0x10)
+#define SDMMC_RESPONSE_R0_R1_0_SECURE                   0x0
+#define SDMMC_RESPONSE_R0_R1_0_WORD_COUNT                       0x1
+#define SDMMC_RESPONSE_R0_R1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R0_R1_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SDMMC_RESPONSE_R0_R1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R0_R1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R0_R1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SDMMC_RESPONSE_R0_R1_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_31_16_SHIFT                     _MK_SHIFT_CONST(16)
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_31_16_FIELD                     (_MK_MASK_CONST(0xffff) << SDMMC_RESPONSE_R0_R1_0_CMD_RESP_31_16_SHIFT)
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_31_16_RANGE                     31:16
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_31_16_WOFFSET                   0x0
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_31_16_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_31_16_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_31_16_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_31_16_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_15_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_15_0_FIELD                      (_MK_MASK_CONST(0xffff) << SDMMC_RESPONSE_R0_R1_0_CMD_RESP_15_0_SHIFT)
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_15_0_RANGE                      15:0
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_15_0_WOFFSET                    0x0
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_15_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_15_0_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_15_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R0_R1_0_CMD_RESP_15_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_RESPONSE_R2_R3_0  
+#define SDMMC_RESPONSE_R2_R3_0                  _MK_ADDR_CONST(0x14)
+#define SDMMC_RESPONSE_R2_R3_0_SECURE                   0x0
+#define SDMMC_RESPONSE_R2_R3_0_WORD_COUNT                       0x1
+#define SDMMC_RESPONSE_R2_R3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R2_R3_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SDMMC_RESPONSE_R2_R3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R2_R3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R2_R3_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SDMMC_RESPONSE_R2_R3_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_63_48_SHIFT                     _MK_SHIFT_CONST(16)
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_63_48_FIELD                     (_MK_MASK_CONST(0xffff) << SDMMC_RESPONSE_R2_R3_0_CMD_RESP_63_48_SHIFT)
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_63_48_RANGE                     31:16
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_63_48_WOFFSET                   0x0
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_63_48_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_63_48_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_63_48_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_63_48_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_47_32_SHIFT                     _MK_SHIFT_CONST(0)
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_47_32_FIELD                     (_MK_MASK_CONST(0xffff) << SDMMC_RESPONSE_R2_R3_0_CMD_RESP_47_32_SHIFT)
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_47_32_RANGE                     15:0
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_47_32_WOFFSET                   0x0
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_47_32_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_47_32_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_47_32_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R2_R3_0_CMD_RESP_47_32_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_RESPONSE_R4_R5_0  
+#define SDMMC_RESPONSE_R4_R5_0                  _MK_ADDR_CONST(0x18)
+#define SDMMC_RESPONSE_R4_R5_0_SECURE                   0x0
+#define SDMMC_RESPONSE_R4_R5_0_WORD_COUNT                       0x1
+#define SDMMC_RESPONSE_R4_R5_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R4_R5_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SDMMC_RESPONSE_R4_R5_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R4_R5_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R4_R5_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SDMMC_RESPONSE_R4_R5_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_95_80_SHIFT                     _MK_SHIFT_CONST(16)
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_95_80_FIELD                     (_MK_MASK_CONST(0xffff) << SDMMC_RESPONSE_R4_R5_0_CMD_RESP_95_80_SHIFT)
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_95_80_RANGE                     31:16
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_95_80_WOFFSET                   0x0
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_95_80_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_95_80_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_95_80_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_95_80_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_79_64_SHIFT                     _MK_SHIFT_CONST(0)
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_79_64_FIELD                     (_MK_MASK_CONST(0xffff) << SDMMC_RESPONSE_R4_R5_0_CMD_RESP_79_64_SHIFT)
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_79_64_RANGE                     15:0
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_79_64_WOFFSET                   0x0
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_79_64_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_79_64_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_79_64_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R4_R5_0_CMD_RESP_79_64_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_RESPONSE_R6_R7_0  
+#define SDMMC_RESPONSE_R6_R7_0                  _MK_ADDR_CONST(0x1c)
+#define SDMMC_RESPONSE_R6_R7_0_SECURE                   0x0
+#define SDMMC_RESPONSE_R6_R7_0_WORD_COUNT                       0x1
+#define SDMMC_RESPONSE_R6_R7_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R6_R7_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SDMMC_RESPONSE_R6_R7_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R6_R7_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R6_R7_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SDMMC_RESPONSE_R6_R7_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_127_112_SHIFT                   _MK_SHIFT_CONST(16)
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_127_112_FIELD                   (_MK_MASK_CONST(0xffff) << SDMMC_RESPONSE_R6_R7_0_CMD_RESP_127_112_SHIFT)
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_127_112_RANGE                   31:16
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_127_112_WOFFSET                 0x0
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_127_112_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_127_112_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_127_112_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_127_112_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_111_96_SHIFT                    _MK_SHIFT_CONST(0)
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_111_96_FIELD                    (_MK_MASK_CONST(0xffff) << SDMMC_RESPONSE_R6_R7_0_CMD_RESP_111_96_SHIFT)
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_111_96_RANGE                    15:0
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_111_96_WOFFSET                  0x0
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_111_96_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_111_96_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_111_96_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_RESPONSE_R6_R7_0_CMD_RESP_111_96_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_BUFFER_DATA_PORT_0  
+#define SDMMC_BUFFER_DATA_PORT_0                        _MK_ADDR_CONST(0x20)
+#define SDMMC_BUFFER_DATA_PORT_0_SECURE                         0x0
+#define SDMMC_BUFFER_DATA_PORT_0_WORD_COUNT                     0x1
+#define SDMMC_BUFFER_DATA_PORT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SDMMC_BUFFER_DATA_PORT_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SDMMC_BUFFER_DATA_PORT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SDMMC_BUFFER_DATA_PORT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_BUFFER_DATA_PORT_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SDMMC_BUFFER_DATA_PORT_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// 
+#define SDMMC_BUFFER_DATA_PORT_0_BUFFER_DATA_SHIFT                      _MK_SHIFT_CONST(0)
+#define SDMMC_BUFFER_DATA_PORT_0_BUFFER_DATA_FIELD                      (_MK_MASK_CONST(0xffffffff) << SDMMC_BUFFER_DATA_PORT_0_BUFFER_DATA_SHIFT)
+#define SDMMC_BUFFER_DATA_PORT_0_BUFFER_DATA_RANGE                      31:0
+#define SDMMC_BUFFER_DATA_PORT_0_BUFFER_DATA_WOFFSET                    0x0
+#define SDMMC_BUFFER_DATA_PORT_0_BUFFER_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_BUFFER_DATA_PORT_0_BUFFER_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SDMMC_BUFFER_DATA_PORT_0_BUFFER_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_BUFFER_DATA_PORT_0_BUFFER_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_PRESENT_STATE_0  
+#define SDMMC_PRESENT_STATE_0                   _MK_ADDR_CONST(0x24)
+#define SDMMC_PRESENT_STATE_0_SECURE                    0x0
+#define SDMMC_PRESENT_STATE_0_WORD_COUNT                        0x1
+#define SDMMC_PRESENT_STATE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_RESET_MASK                        _MK_MASK_CONST(0x1fff0f07)
+#define SDMMC_PRESENT_STATE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_READ_MASK                         _MK_MASK_CONST(0x1fff0f07)
+#define SDMMC_PRESENT_STATE_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_SHIFT                  _MK_SHIFT_CONST(25)
+#define SDMMC_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_FIELD                  (_MK_MASK_CONST(0xf) << SDMMC_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_SHIFT)
+#define SDMMC_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_RANGE                  28:25
+#define SDMMC_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_WOFFSET                        0x0
+#define SDMMC_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define SDMMC_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_DAT_7_4_LINE_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define SDMMC_PRESENT_STATE_0_CMD_LINE_LEVEL_SHIFT                      _MK_SHIFT_CONST(24)
+#define SDMMC_PRESENT_STATE_0_CMD_LINE_LEVEL_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_CMD_LINE_LEVEL_SHIFT)
+#define SDMMC_PRESENT_STATE_0_CMD_LINE_LEVEL_RANGE                      24:24
+#define SDMMC_PRESENT_STATE_0_CMD_LINE_LEVEL_WOFFSET                    0x0
+#define SDMMC_PRESENT_STATE_0_CMD_LINE_LEVEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CMD_LINE_LEVEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_CMD_LINE_LEVEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CMD_LINE_LEVEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CMD_LINE_LEVEL_LOW                        _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_CMD_LINE_LEVEL_HIGH                       _MK_ENUM_CONST(1)
+
+#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_SHIFT                  _MK_SHIFT_CONST(20)
+#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_FIELD                  (_MK_MASK_CONST(0xf) << SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_SHIFT)
+#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_RANGE                  23:20
+#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_WOFFSET                        0x0
+#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_DAT_3_0_LINE_LEVEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define SDMMC_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_SHIFT                 _MK_SHIFT_CONST(19)
+#define SDMMC_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_SHIFT)
+#define SDMMC_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_RANGE                 19:19
+#define SDMMC_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_WOFFSET                       0x0
+#define SDMMC_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_PROTECTED                     _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_WRITE_PROTECT_LEVEL_ENABLED                       _MK_ENUM_CONST(1)
+
+#define SDMMC_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_SHIFT                       _MK_SHIFT_CONST(18)
+#define SDMMC_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_SHIFT)
+#define SDMMC_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_RANGE                       18:18
+#define SDMMC_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_WOFFSET                     0x0
+#define SDMMC_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_NO_CARD                     _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_CARD_DETECT_PIN_LEVEL_CARD                        _MK_ENUM_CONST(1)
+
+#define SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_SHIFT                   _MK_SHIFT_CONST(17)
+#define SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_SHIFT)
+#define SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_RANGE                   17:17
+#define SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_WOFFSET                 0x0
+#define SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_DEBOUNCE                        _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_CARD_STATE_STABLE_INSERTED                        _MK_ENUM_CONST(1)
+
+#define SDMMC_PRESENT_STATE_0_CARD_INSERTED_SHIFT                       _MK_SHIFT_CONST(16)
+#define SDMMC_PRESENT_STATE_0_CARD_INSERTED_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_CARD_INSERTED_SHIFT)
+#define SDMMC_PRESENT_STATE_0_CARD_INSERTED_RANGE                       16:16
+#define SDMMC_PRESENT_STATE_0_CARD_INSERTED_WOFFSET                     0x0
+#define SDMMC_PRESENT_STATE_0_CARD_INSERTED_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CARD_INSERTED_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_CARD_INSERTED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CARD_INSERTED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CARD_INSERTED_DEBOUNCE                    _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_CARD_INSERTED_INSERTED                    _MK_ENUM_CONST(1)
+
+#define SDMMC_PRESENT_STATE_0_BUFFER_READ_EN_SHIFT                      _MK_SHIFT_CONST(11)
+#define SDMMC_PRESENT_STATE_0_BUFFER_READ_EN_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_BUFFER_READ_EN_SHIFT)
+#define SDMMC_PRESENT_STATE_0_BUFFER_READ_EN_RANGE                      11:11
+#define SDMMC_PRESENT_STATE_0_BUFFER_READ_EN_WOFFSET                    0x0
+#define SDMMC_PRESENT_STATE_0_BUFFER_READ_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_BUFFER_READ_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_BUFFER_READ_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_BUFFER_READ_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_BUFFER_READ_EN_DISABLE                    _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_BUFFER_READ_EN_ENABLE                     _MK_ENUM_CONST(1)
+
+#define SDMMC_PRESENT_STATE_0_BUFFER_WRITE_EN_SHIFT                     _MK_SHIFT_CONST(10)
+#define SDMMC_PRESENT_STATE_0_BUFFER_WRITE_EN_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_BUFFER_WRITE_EN_SHIFT)
+#define SDMMC_PRESENT_STATE_0_BUFFER_WRITE_EN_RANGE                     10:10
+#define SDMMC_PRESENT_STATE_0_BUFFER_WRITE_EN_WOFFSET                   0x0
+#define SDMMC_PRESENT_STATE_0_BUFFER_WRITE_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_BUFFER_WRITE_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_BUFFER_WRITE_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_BUFFER_WRITE_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_BUFFER_WRITE_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_BUFFER_WRITE_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+#define SDMMC_PRESENT_STATE_0_READ_XFER_ACTIVE_SHIFT                    _MK_SHIFT_CONST(9)
+#define SDMMC_PRESENT_STATE_0_READ_XFER_ACTIVE_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_READ_XFER_ACTIVE_SHIFT)
+#define SDMMC_PRESENT_STATE_0_READ_XFER_ACTIVE_RANGE                    9:9
+#define SDMMC_PRESENT_STATE_0_READ_XFER_ACTIVE_WOFFSET                  0x0
+#define SDMMC_PRESENT_STATE_0_READ_XFER_ACTIVE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_READ_XFER_ACTIVE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_READ_XFER_ACTIVE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_READ_XFER_ACTIVE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_READ_XFER_ACTIVE_NO_DATA                  _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_READ_XFER_ACTIVE_TRANSFERING                      _MK_ENUM_CONST(1)
+
+#define SDMMC_PRESENT_STATE_0_WRITE_XFER_ACTIVE_SHIFT                   _MK_SHIFT_CONST(8)
+#define SDMMC_PRESENT_STATE_0_WRITE_XFER_ACTIVE_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_WRITE_XFER_ACTIVE_SHIFT)
+#define SDMMC_PRESENT_STATE_0_WRITE_XFER_ACTIVE_RANGE                   8:8
+#define SDMMC_PRESENT_STATE_0_WRITE_XFER_ACTIVE_WOFFSET                 0x0
+#define SDMMC_PRESENT_STATE_0_WRITE_XFER_ACTIVE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_WRITE_XFER_ACTIVE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_WRITE_XFER_ACTIVE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_WRITE_XFER_ACTIVE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_WRITE_XFER_ACTIVE_NO_DATA                 _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_WRITE_XFER_ACTIVE_TRANSFERING                     _MK_ENUM_CONST(1)
+
+#define SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_SHIFT                     _MK_SHIFT_CONST(2)
+#define SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_SHIFT)
+#define SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_RANGE                     2:2
+#define SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_WOFFSET                   0x0
+#define SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_INACTIVE                  _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_DAT_LINE_ACTIVE_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_SHIFT                     _MK_SHIFT_CONST(1)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_SHIFT)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_RANGE                     1:1
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_WOFFSET                   0x0
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_INACTIVE                  _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_DAT_ACTIVE                    _MK_ENUM_CONST(1)
+
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_SHIFT                     _MK_SHIFT_CONST(0)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_SHIFT)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_RANGE                     0:0
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_WOFFSET                   0x0
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_INACTIVE                  _MK_ENUM_CONST(0)
+#define SDMMC_PRESENT_STATE_0_CMD_INHIBIT_CMD_ACTIVE                    _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_POWER_CONTROL_HOST_0  
+#define SDMMC_POWER_CONTROL_HOST_0                      _MK_ADDR_CONST(0x28)
+#define SDMMC_POWER_CONTROL_HOST_0_SECURE                       0x0
+#define SDMMC_POWER_CONTROL_HOST_0_WORD_COUNT                   0x1
+#define SDMMC_POWER_CONTROL_HOST_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_RESET_MASK                   _MK_MASK_CONST(0x70f0fff)
+#define SDMMC_POWER_CONTROL_HOST_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_READ_MASK                    _MK_MASK_CONST(0x70f0fff)
+#define SDMMC_POWER_CONTROL_HOST_0_WRITE_MASK                   _MK_MASK_CONST(0x70f0fff)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_SHIFT                 _MK_SHIFT_CONST(26)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_RANGE                 26:26
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_WOFFSET                       0x0
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_DISABLE                       _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_REMOVAL_ENABLE                        _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_SHIFT                       _MK_SHIFT_CONST(25)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_RANGE                       25:25
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_WOFFSET                     0x0
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_DISABLE                     _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INSERTION_ENABLE                      _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_SHIFT                       _MK_SHIFT_CONST(24)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_RANGE                       24:24
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_WOFFSET                     0x0
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_DISABLE                     _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_WAKEUP_ON_CARD_INTERRUPT_ENABLE                      _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_SHIFT                 _MK_SHIFT_CONST(19)
+#define SDMMC_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_RANGE                 19:19
+#define SDMMC_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_WOFFSET                       0x0
+#define SDMMC_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_DISABLE                       _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_INTERRUPT_AT_BLOCK_GAP_ENABLE                        _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_SHIFT                      _MK_SHIFT_CONST(18)
+#define SDMMC_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_RANGE                      18:18
+#define SDMMC_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_WOFFSET                    0x0
+#define SDMMC_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_DISABLE                    _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_READ_WAIT_CONTROL_ENABLE                     _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_SHIFT                       _MK_SHIFT_CONST(17)
+#define SDMMC_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_RANGE                       17:17
+#define SDMMC_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_WOFFSET                     0x0
+#define SDMMC_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_IGNORED                     _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_CONTINUE_REQUEST_RESTART                     _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_SHIFT                      _MK_SHIFT_CONST(16)
+#define SDMMC_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_RANGE                      16:16
+#define SDMMC_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_WOFFSET                    0x0
+#define SDMMC_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_STOP                       _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_STOP_AT_BLOCK_GAP_REQUEST_TRANSFER                   _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_SHIFT                  _MK_SHIFT_CONST(9)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_FIELD                  (_MK_MASK_CONST(0x7) << SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_RANGE                  11:9
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_WOFFSET                        0x0
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_V1_8                   _MK_ENUM_CONST(5)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_V3_0                   _MK_ENUM_CONST(6)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_VOLTAGE_SELECT_V3_3                   _MK_ENUM_CONST(7)
+
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_SHIFT                   _MK_SHIFT_CONST(8)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_RANGE                   8:8
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_WOFFSET                 0x0
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_POWER_OFF                       _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_SD_BUS_POWER_POWER_ON                        _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_SHIFT                      _MK_SHIFT_CONST(7)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_RANGE                      7:7
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_WOFFSET                    0x0
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_SDCD                       _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_SIGNAL_DETECT_CARD_DTECT_TST_LVL                 _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_SHIFT                   _MK_SHIFT_CONST(6)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_RANGE                   6:6
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_WOFFSET                 0x0
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_NO_CARD                 _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_CARD_DETECT_TEST_LVL_CARD_INSERTED                   _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_SHIFT                   _MK_SHIFT_CONST(5)
+#define SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_RANGE                   5:5
+#define SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_WOFFSET                 0x0
+#define SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_NOBIT_8                 _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_EXTENDED_DATA_TRANSFER_WIDTH_BIT_8                   _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_SHIFT                     _MK_SHIFT_CONST(3)
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_FIELD                     (_MK_MASK_CONST(0x3) << SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_RANGE                     4:3
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_WOFFSET                   0x0
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_SDMA                      _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_ADMA1_32BIT                       _MK_ENUM_CONST(1)
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_ADMA2_32BIT                       _MK_ENUM_CONST(2)
+#define SDMMC_POWER_CONTROL_HOST_0_DMA_SELECT_ADMA2_64BIT                       _MK_ENUM_CONST(3)
+
+#define SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_SHIFT                  _MK_SHIFT_CONST(2)
+#define SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_RANGE                  2:2
+#define SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_WOFFSET                        0x0
+#define SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_NORMAL_SPEED                   _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_HIGH_SPEED_EN_HIGH_SPEED                     _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_SHIFT                        _MK_SHIFT_CONST(1)
+#define SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_RANGE                        1:1
+#define SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_WOFFSET                      0x0
+#define SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_BIT_1                        _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_DATA_XFER_WIDTH_BIT_4                        _MK_ENUM_CONST(1)
+
+#define SDMMC_POWER_CONTROL_HOST_0_LED_CONTROL_SHIFT                    _MK_SHIFT_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_LED_CONTROL_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_POWER_CONTROL_HOST_0_LED_CONTROL_SHIFT)
+#define SDMMC_POWER_CONTROL_HOST_0_LED_CONTROL_RANGE                    0:0
+#define SDMMC_POWER_CONTROL_HOST_0_LED_CONTROL_WOFFSET                  0x0
+#define SDMMC_POWER_CONTROL_HOST_0_LED_CONTROL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_LED_CONTROL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_POWER_CONTROL_HOST_0_LED_CONTROL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_LED_CONTROL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_POWER_CONTROL_HOST_0_LED_CONTROL_OFF                      _MK_ENUM_CONST(0)
+#define SDMMC_POWER_CONTROL_HOST_0_LED_CONTROL_ON                       _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0  
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0                     _MK_ADDR_CONST(0x2c)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SECURE                      0x0
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_WORD_COUNT                  0x1
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x70fff07)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x70fff07)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x70fff05)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_SHIFT                 _MK_SHIFT_CONST(26)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_SHIFT)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_RANGE                 26:26
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_WOFFSET                       0x0
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_WORK                  _MK_ENUM_CONST(0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_DAT_LINE_RESETED                       _MK_ENUM_CONST(1)
+
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_SHIFT                 _MK_SHIFT_CONST(25)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_SHIFT)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_RANGE                 25:25
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_WOFFSET                       0x0
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_WORK                  _MK_ENUM_CONST(0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_CMD_LINE_RESETED                       _MK_ENUM_CONST(1)
+
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_SHIFT                      _MK_SHIFT_CONST(24)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_SHIFT)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_RANGE                      24:24
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_WOFFSET                    0x0
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_WORK                       _MK_ENUM_CONST(0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SW_RESET_FOR_ALL_RESETED                    _MK_ENUM_CONST(1)
+
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_SHIFT                    _MK_SHIFT_CONST(16)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_FIELD                    (_MK_MASK_CONST(0xf) << SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_SHIFT)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_RANGE                    19:16
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_WOFFSET                  0x0
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_DATA_TIMEOUT_COUNTER_VALUE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_SHIFT                 _MK_SHIFT_CONST(8)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_FIELD                 (_MK_MASK_CONST(0xff) << SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_SHIFT)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_RANGE                 15:8
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_WOFFSET                       0x0
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV256                        _MK_ENUM_CONST(128)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV128                        _MK_ENUM_CONST(64)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV64                 _MK_ENUM_CONST(32)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV32                 _MK_ENUM_CONST(16)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV16                 _MK_ENUM_CONST(8)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV8                  _MK_ENUM_CONST(4)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV4                  _MK_ENUM_CONST(2)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_DIV2                  _MK_ENUM_CONST(1)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SDCLK_FREQUENCYSELECT_BASE                  _MK_ENUM_CONST(0)
+
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_SHIFT                   _MK_SHIFT_CONST(2)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_SHIFT)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_RANGE                   2:2
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_WOFFSET                 0x0
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_SD_CLOCK_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_SHIFT                 _MK_SHIFT_CONST(1)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_SHIFT)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_RANGE                 1:1
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_WOFFSET                       0x0
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_NOT_READY                     _MK_ENUM_CONST(0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_STABLE_READY                 _MK_ENUM_CONST(1)
+
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_SHIFT                     _MK_SHIFT_CONST(0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_SHIFT)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_RANGE                     0:0
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_WOFFSET                   0x0
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_STOP                      _MK_ENUM_CONST(0)
+#define SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0_INTERNAL_CLOCK_EN_OSCILLATE                 _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_INTERRUPT_STATUS_0  
+#define SDMMC_INTERRUPT_STATUS_0                        _MK_ADDR_CONST(0x30)
+#define SDMMC_INTERRUPT_STATUS_0_SECURE                         0x0
+#define SDMMC_INTERRUPT_STATUS_0_WORD_COUNT                     0x1
+#define SDMMC_INTERRUPT_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0xfbff81ff)
+#define SDMMC_INTERRUPT_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xfbff81ff)
+#define SDMMC_INTERRUPT_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0xfbff00ff)
+#define SDMMC_INTERRUPT_STATUS_0_VEND_SPEC_ERR_SHIFT                    _MK_SHIFT_CONST(30)
+#define SDMMC_INTERRUPT_STATUS_0_VEND_SPEC_ERR_FIELD                    (_MK_MASK_CONST(0x3) << SDMMC_INTERRUPT_STATUS_0_VEND_SPEC_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_VEND_SPEC_ERR_RANGE                    31:30
+#define SDMMC_INTERRUPT_STATUS_0_VEND_SPEC_ERR_WOFFSET                  0x0
+#define SDMMC_INTERRUPT_STATUS_0_VEND_SPEC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_VEND_SPEC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SDMMC_INTERRUPT_STATUS_0_VEND_SPEC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_VEND_SPEC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_VEND_SPEC_ERR_DISABLE                  _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_VEND_SPEC_ERR_ENABLE                   _MK_ENUM_CONST(3)
+
+#define SDMMC_INTERRUPT_STATUS_0_CEATA_ERROR_SHIFT                      _MK_SHIFT_CONST(29)
+#define SDMMC_INTERRUPT_STATUS_0_CEATA_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_CEATA_ERROR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_CEATA_ERROR_RANGE                      29:29
+#define SDMMC_INTERRUPT_STATUS_0_CEATA_ERROR_WOFFSET                    0x0
+#define SDMMC_INTERRUPT_STATUS_0_CEATA_ERROR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CEATA_ERROR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_CEATA_ERROR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CEATA_ERROR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CEATA_ERROR_NO_ERROR                   _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_CEATA_ERROR_ERROR                      _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_SHIFT                        _MK_SHIFT_CONST(28)
+#define SDMMC_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_RANGE                        28:28
+#define SDMMC_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_WOFFSET                      0x0
+#define SDMMC_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_NO_ERROR                     _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_TARGET_RESP_ERROR_ERROR                        _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_SPI_ERR_SHIFT                  _MK_SHIFT_CONST(27)
+#define SDMMC_INTERRUPT_STATUS_0_SPI_ERR_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_SPI_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_SPI_ERR_RANGE                  27:27
+#define SDMMC_INTERRUPT_STATUS_0_SPI_ERR_WOFFSET                        0x0
+#define SDMMC_INTERRUPT_STATUS_0_SPI_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_SPI_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_SPI_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_SPI_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_SPI_ERR_NO_ERR                 _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_SPI_ERR_ERR                    _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_ADMA_ERR_SHIFT                 _MK_SHIFT_CONST(25)
+#define SDMMC_INTERRUPT_STATUS_0_ADMA_ERR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_ADMA_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_ADMA_ERR_RANGE                 25:25
+#define SDMMC_INTERRUPT_STATUS_0_ADMA_ERR_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_STATUS_0_ADMA_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_ADMA_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_ADMA_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_ADMA_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_ADMA_ERR_NO_ERR                        _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_ADMA_ERR_ERR                   _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_SHIFT                   _MK_SHIFT_CONST(24)
+#define SDMMC_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_RANGE                   24:24
+#define SDMMC_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_WOFFSET                 0x0
+#define SDMMC_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_NO_ERR                  _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_AUTO_CMD12_ERR_ERR                     _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_SHIFT                        _MK_SHIFT_CONST(23)
+#define SDMMC_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_RANGE                        23:23
+#define SDMMC_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_WOFFSET                      0x0
+#define SDMMC_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_NO_ERR                       _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_CURRENT_LIMIT_ERR_POWER_FAIL                   _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_SHIFT                 _MK_SHIFT_CONST(22)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_RANGE                 22:22
+#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_NO_ERR                        _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_END_BIT_ERR_ERR                   _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_SHIFT                     _MK_SHIFT_CONST(21)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_RANGE                     21:21
+#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_WOFFSET                   0x0
+#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_NO_ERR                    _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_CRC_ERR_ERR                       _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_SHIFT                 _MK_SHIFT_CONST(20)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_RANGE                 20:20
+#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_NO_ERR                        _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_DATA_TIMEOUT_ERR_TIMEOUT                       _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_SHIFT                        _MK_SHIFT_CONST(19)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_RANGE                        19:19
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_WOFFSET                      0x0
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_NO_ERR                       _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_INDEX_ERR_ERR                  _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_SHIFT                      _MK_SHIFT_CONST(18)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_RANGE                      18:18
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_WOFFSET                    0x0
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_NO_ERR                     _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_END_BIT_ERR_END_BIT_ERR_GENERATED                      _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_SHIFT                  _MK_SHIFT_CONST(17)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_RANGE                  17:17
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_WOFFSET                        0x0
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_NO_ERR                 _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_CRC_ERR_CRC_ERR_GENERATED                      _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_SHIFT                      _MK_SHIFT_CONST(16)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_RANGE                      16:16
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_WOFFSET                    0x0
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_NO_ERR                     _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_COMMAND_TIMEOUT_ERR_TIMEOUT                    _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_ERR_INTERRUPT_SHIFT                    _MK_SHIFT_CONST(15)
+#define SDMMC_INTERRUPT_STATUS_0_ERR_INTERRUPT_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_ERR_INTERRUPT_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_ERR_INTERRUPT_RANGE                    15:15
+#define SDMMC_INTERRUPT_STATUS_0_ERR_INTERRUPT_WOFFSET                  0x0
+#define SDMMC_INTERRUPT_STATUS_0_ERR_INTERRUPT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_ERR_INTERRUPT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_ERR_INTERRUPT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_ERR_INTERRUPT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_ERR_INTERRUPT_NO_ERR                   _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_ERR_INTERRUPT_ERR                      _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INTERRUPT_SHIFT                   _MK_SHIFT_CONST(8)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INTERRUPT_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_CARD_INTERRUPT_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INTERRUPT_RANGE                   8:8
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INTERRUPT_WOFFSET                 0x0
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INTERRUPT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INTERRUPT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INTERRUPT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INTERRUPT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INTERRUPT_NO_INT                  _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INTERRUPT_GEN_INT                 _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_CARD_REMOVAL_SHIFT                     _MK_SHIFT_CONST(7)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_REMOVAL_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_CARD_REMOVAL_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_REMOVAL_RANGE                     7:7
+#define SDMMC_INTERRUPT_STATUS_0_CARD_REMOVAL_WOFFSET                   0x0
+#define SDMMC_INTERRUPT_STATUS_0_CARD_REMOVAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_REMOVAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_REMOVAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_REMOVAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_REMOVAL_NO_INT                    _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_REMOVAL_GEN_INT                   _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INSERTION_SHIFT                   _MK_SHIFT_CONST(6)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INSERTION_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_CARD_INSERTION_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INSERTION_RANGE                   6:6
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INSERTION_WOFFSET                 0x0
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INSERTION_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INSERTION_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INSERTION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INSERTION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INSERTION_NO_INT                  _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_CARD_INSERTION_GEN_INT                 _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_READ_READY_SHIFT                        _MK_SHIFT_CONST(5)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_READ_READY_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_BUFFER_READ_READY_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_READ_READY_RANGE                        5:5
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_READ_READY_WOFFSET                      0x0
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_READ_READY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_READ_READY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_READ_READY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_READ_READY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_READ_READY_NO_INT                       _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_READ_READY_GEN_INT                      _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_SHIFT                       _MK_SHIFT_CONST(4)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_RANGE                       4:4
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_WOFFSET                     0x0
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_NO_INT                      _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_BUFFER_WRITE_READY_GEN_INT                     _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_SHIFT                    _MK_SHIFT_CONST(3)
+#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_RANGE                    3:3
+#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_WOFFSET                  0x0
+#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_NO_INT                   _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_DMA_INTERRUPT_GEN_INT                  _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_SHIFT                  _MK_SHIFT_CONST(2)
+#define SDMMC_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_RANGE                  2:2
+#define SDMMC_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_WOFFSET                        0x0
+#define SDMMC_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_NO_INT                 _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_BLOCK_GAP_EVENT_GEN_INT                        _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_SHIFT                    _MK_SHIFT_CONST(1)
+#define SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_RANGE                    1:1
+#define SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_WOFFSET                  0x0
+#define SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_NO_INT                   _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_XFER_COMPLETE_GEN_INT                  _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_SHIFT                     _MK_SHIFT_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_RANGE                     0:0
+#define SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_WOFFSET                   0x0
+#define SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_NO_INT                    _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_0_CMD_COMPLETE_GEN_INT                   _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_INTERRUPT_STATUS_ENABLE_0  
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0                 _MK_ADDR_CONST(0x34)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SECURE                  0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_WORD_COUNT                      0x1
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_RESET_MASK                      _MK_MASK_CONST(0xfbff01ff)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_READ_MASK                       _MK_MASK_CONST(0xfbff01ff)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_WRITE_MASK                      _MK_MASK_CONST(0xfbff01ff)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_SHIFT                       _MK_SHIFT_CONST(30)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_FIELD                       (_MK_MASK_CONST(0x3) << SDMMC_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_RANGE                       31:30
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_WOFFSET                     0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_DISABLE                     _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_VENDOR_SPECIFIC_ERR_ENABLE                      _MK_ENUM_CONST(3)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CEATA_ERROR_SHIFT                       _MK_SHIFT_CONST(29)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CEATA_ERROR_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_CEATA_ERROR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CEATA_ERROR_RANGE                       29:29
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CEATA_ERROR_WOFFSET                     0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CEATA_ERROR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CEATA_ERROR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CEATA_ERROR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CEATA_ERROR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CEATA_ERROR_NO_ERROR                    _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CEATA_ERROR_ERROR                       _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_SHIFT                 _MK_SHIFT_CONST(28)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_RANGE                 28:28
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_NO_ERROR                      _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TARGET_RESP_ERROR_ERROR                 _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_SHIFT                   _MK_SHIFT_CONST(27)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_RANGE                   27:27
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_WOFFSET                 0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_DISABLE                 _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_SPI_ERR_ENABLE                  _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_SHIFT                  _MK_SHIFT_CONST(25)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_RANGE                  25:25
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_WOFFSET                        0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_DISABLE                        _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_ADMA_ERR_ENABLE                 _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_SHIFT                    _MK_SHIFT_CONST(24)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_RANGE                    24:24
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_WOFFSET                  0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_DISABLE                  _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_AUTO_CMD12_ERR_ENABLE                   _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_SHIFT                 _MK_SHIFT_CONST(23)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_RANGE                 23:23
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_DISABLE                       _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CURRENT_LIMIT_ERR_ENABLE                        _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_SHIFT                  _MK_SHIFT_CONST(22)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_RANGE                  22:22
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_WOFFSET                        0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_DISABLE                        _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_END_BIT_ERR_ENABLE                 _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_SHIFT                      _MK_SHIFT_CONST(21)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_RANGE                      21:21
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_WOFFSET                    0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_DISABLE                    _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_CRC_ERR_ENABLE                     _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_SHIFT                  _MK_SHIFT_CONST(20)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_RANGE                  20:20
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_WOFFSET                        0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_DISABLE                        _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DATA_TIMEOUT_ERR_ENABLE                 _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_SHIFT                 _MK_SHIFT_CONST(19)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_RANGE                 19:19
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_DISABLE                       _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_INDEX_ERR_ENABLE                        _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_SHIFT                       _MK_SHIFT_CONST(18)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_RANGE                       18:18
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_WOFFSET                     0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_DISABLE                     _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_END_BIT_ERR_ENABLE                      _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_SHIFT                   _MK_SHIFT_CONST(17)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_RANGE                   17:17
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_WOFFSET                 0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_DISABLE                 _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_CRC_ERR_ENABLE                  _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_SHIFT                       _MK_SHIFT_CONST(16)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_RANGE                       16:16
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_WOFFSET                     0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_DISABLE                     _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_TIMEOUT_ERR_ENABLE                      _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_SHIFT                    _MK_SHIFT_CONST(8)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_RANGE                    8:8
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_WOFFSET                  0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_DISABLE                  _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INTERRUPT_ENABLE                   _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_SHIFT                      _MK_SHIFT_CONST(7)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_RANGE                      7:7
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_WOFFSET                    0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_REMOVAL_ENABLE                     _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_SHIFT                    _MK_SHIFT_CONST(6)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_RANGE                    6:6
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_WOFFSET                  0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_DISABLE                  _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_CARD_INSERTION_ENABLE                   _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_SHIFT                 _MK_SHIFT_CONST(5)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_RANGE                 5:5
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_DISABLE                       _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_READ_READY_ENABLE                        _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_SHIFT                        _MK_SHIFT_CONST(4)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_RANGE                        4:4
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_WOFFSET                      0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_DISABLE                      _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BUFFER_WRITE_READY_ENABLE                       _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_SHIFT                     _MK_SHIFT_CONST(3)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_RANGE                     3:3
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_WOFFSET                   0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_DISABLE                   _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_DMA_INTERRUPT_ENABLE                    _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_SHIFT                   _MK_SHIFT_CONST(2)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_RANGE                   2:2
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_WOFFSET                 0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_DISABLE                 _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_BLOCK_GAP_EVENT_ENABLE                  _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_SHIFT                 _MK_SHIFT_CONST(1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_RANGE                 1:1
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_DISABLE                       _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_TRANSFER_COMPLETE_ENABLE                        _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_SHIFT                  _MK_SHIFT_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_SHIFT)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_RANGE                  0:0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_WOFFSET                        0x0
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_DISABLE                        _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_STATUS_ENABLE_0_COMMAND_COMPLETE_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_INTERRUPT_SIGNAL_ENABLE_0  
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0                 _MK_ADDR_CONST(0x38)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SECURE                  0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_WORD_COUNT                      0x1
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_RESET_MASK                      _MK_MASK_CONST(0xfbff01ff)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_READ_MASK                       _MK_MASK_CONST(0xfbff01ff)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_WRITE_MASK                      _MK_MASK_CONST(0xfbff01ff)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_SHIFT                       _MK_SHIFT_CONST(30)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_FIELD                       (_MK_MASK_CONST(0x3) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_RANGE                       31:30
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_WOFFSET                     0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_DISABLE                     _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_VENDOR_SPECIFIC_ERR_ENABLE                      _MK_ENUM_CONST(3)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CEATA_ERROR_SHIFT                       _MK_SHIFT_CONST(29)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CEATA_ERROR_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CEATA_ERROR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CEATA_ERROR_RANGE                       29:29
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CEATA_ERROR_WOFFSET                     0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CEATA_ERROR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CEATA_ERROR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CEATA_ERROR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CEATA_ERROR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CEATA_ERROR_NO_ERROR                    _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CEATA_ERROR_ERROR                       _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_SHIFT                 _MK_SHIFT_CONST(28)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_RANGE                 28:28
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_NO_ERROR                      _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TARGET_RESP_ERROR_ERROR                 _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_SHIFT                   _MK_SHIFT_CONST(27)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_RANGE                   27:27
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_WOFFSET                 0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_DISABLE                 _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_SPI_ERR_ENABLE                  _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_SHIFT                  _MK_SHIFT_CONST(25)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_RANGE                  25:25
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_WOFFSET                        0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_DISABLE                        _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_ADMA_ERR_ENABLE                 _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_SHIFT                    _MK_SHIFT_CONST(24)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_RANGE                    24:24
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_WOFFSET                  0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_DISABLE                  _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_AUTO_CMD12_ERR_ENABLE                   _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_SHIFT                 _MK_SHIFT_CONST(23)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_RANGE                 23:23
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_DISABLE                       _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CURRENT_LIMIT_ERR_ENABLE                        _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_SHIFT                  _MK_SHIFT_CONST(22)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_RANGE                  22:22
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_WOFFSET                        0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_DISABLE                        _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_END_BIT_ERR_ENABLE                 _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_SHIFT                      _MK_SHIFT_CONST(21)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_RANGE                      21:21
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_WOFFSET                    0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_DISABLE                    _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_CRC_ERR_ENABLE                     _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_SHIFT                  _MK_SHIFT_CONST(20)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_RANGE                  20:20
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_WOFFSET                        0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_DISABLE                        _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DATA_TIMEOUT_ERR_ENABLE                 _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_SHIFT                 _MK_SHIFT_CONST(19)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_RANGE                 19:19
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_DISABLE                       _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_INDEX_ERR_ENABLE                        _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_SHIFT                       _MK_SHIFT_CONST(18)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_RANGE                       18:18
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_WOFFSET                     0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_DISABLE                     _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_END_BIT_ERR_ENABLE                      _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_SHIFT                   _MK_SHIFT_CONST(17)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_RANGE                   17:17
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_WOFFSET                 0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_DISABLE                 _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_CRC_ERR_ENABLE                  _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_SHIFT                       _MK_SHIFT_CONST(16)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_RANGE                       16:16
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_WOFFSET                     0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_DISABLE                     _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_TIMEOUT_ERR_ENABLE                      _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_SHIFT                    _MK_SHIFT_CONST(8)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_RANGE                    8:8
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_WOFFSET                  0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_DISABLE                  _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INTERRUPT_ENABLE                   _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_SHIFT                      _MK_SHIFT_CONST(7)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_RANGE                      7:7
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_WOFFSET                    0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_DISABLE                    _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_REMOVAL_ENABLE                     _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_SHIFT                    _MK_SHIFT_CONST(6)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_RANGE                    6:6
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_WOFFSET                  0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_DISABLE                  _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_CARD_INSERTION_ENABLE                   _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_SHIFT                 _MK_SHIFT_CONST(5)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_RANGE                 5:5
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_DISABLE                       _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_READ_READY_ENABLE                        _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_SHIFT                        _MK_SHIFT_CONST(4)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_RANGE                        4:4
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_WOFFSET                      0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_DISABLE                      _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BUFFER_WRITE_READY_ENABLE                       _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_SHIFT                     _MK_SHIFT_CONST(3)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_RANGE                     3:3
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_WOFFSET                   0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_DISABLE                   _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_DMA_INTERRUPT_ENABLE                    _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_SHIFT                   _MK_SHIFT_CONST(2)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_RANGE                   2:2
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_WOFFSET                 0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_DISABLE                 _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_BLOCK_GAP_EVENT_ENABLE                  _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_SHIFT                 _MK_SHIFT_CONST(1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_RANGE                 1:1
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_WOFFSET                       0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_DISABLE                       _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_TRANSFER_COMPLETE_ENABLE                        _MK_ENUM_CONST(1)
+
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_SHIFT                  _MK_SHIFT_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_SHIFT)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_RANGE                  0:0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_WOFFSET                        0x0
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_DISABLE                        _MK_ENUM_CONST(0)
+#define SDMMC_INTERRUPT_SIGNAL_ENABLE_0_COMMAND_COMPLETE_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_AUTO_CMD12_ERR_STATUS_0  
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0                   _MK_ADDR_CONST(0x3c)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_SECURE                    0x0
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_WORD_COUNT                        0x1
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x9f)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x9f)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_SHIFT                  _MK_SHIFT_CONST(7)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_SHIFT)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_RANGE                  7:7
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_WOFFSET                        0x0
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_NO_ERR                 _MK_ENUM_CONST(0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_COMMAND_NOT_ISSUED_NOT_ISSUED                     _MK_ENUM_CONST(1)
+
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_SHIFT                   _MK_SHIFT_CONST(4)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_SHIFT)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_RANGE                   4:4
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_WOFFSET                 0x0
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_NO_ERR                  _MK_ENUM_CONST(0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_INDEX_ERR_ERR                     _MK_ENUM_CONST(1)
+
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_SHIFT                 _MK_SHIFT_CONST(3)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_SHIFT)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_RANGE                 3:3
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_WOFFSET                       0x0
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_NO_ERR                        _MK_ENUM_CONST(0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_END_BIT_ERR_END_BIT_ERR_GENERATED                 _MK_ENUM_CONST(1)
+
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_SHIFT                     _MK_SHIFT_CONST(2)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_SHIFT)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_RANGE                     2:2
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_WOFFSET                   0x0
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_NO_ERR                    _MK_ENUM_CONST(0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_CRC_ERR_CRC_ERR_GENERATED                 _MK_ENUM_CONST(1)
+
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_SHIFT                 _MK_SHIFT_CONST(1)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_SHIFT)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_RANGE                 1:1
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_WOFFSET                       0x0
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_NO_ERR                        _MK_ENUM_CONST(0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_TIMEOUT_ERR_TIMEOUT                       _MK_ENUM_CONST(1)
+
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_SHIFT                        _MK_SHIFT_CONST(0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_SHIFT)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_RANGE                        0:0
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_WOFFSET                      0x0
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_EXECUTED                     _MK_ENUM_CONST(0)
+#define SDMMC_AUTO_CMD12_ERR_STATUS_0_NOT_EXECUTED_NOT_EXECUTED                 _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_CAPABILITIES_0  
+#define SDMMC_CAPABILITIES_0                    _MK_ADDR_CONST(0x40)
+#define SDMMC_CAPABILITIES_0_SECURE                     0x0
+#define SDMMC_CAPABILITIES_0_WORD_COUNT                         0x1
+#define SDMMC_CAPABILITIES_0_RESET_VAL                  _MK_MASK_CONST(0x61ff30b0)
+#define SDMMC_CAPABILITIES_0_RESET_MASK                         _MK_MASK_CONST(0x7fff3fbf)
+#define SDMMC_CAPABILITIES_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_READ_MASK                  _MK_MASK_CONST(0x7fff3fbf)
+#define SDMMC_CAPABILITIES_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_SPI_BLOCK_MODE_SHIFT                       _MK_SHIFT_CONST(30)
+#define SDMMC_CAPABILITIES_0_SPI_BLOCK_MODE_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_SPI_BLOCK_MODE_SHIFT)
+#define SDMMC_CAPABILITIES_0_SPI_BLOCK_MODE_RANGE                       30:30
+#define SDMMC_CAPABILITIES_0_SPI_BLOCK_MODE_WOFFSET                     0x0
+#define SDMMC_CAPABILITIES_0_SPI_BLOCK_MODE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_SPI_BLOCK_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_SPI_BLOCK_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_SPI_BLOCK_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_SPI_BLOCK_MODE_NOT_SUPPORTED                       _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_SPI_BLOCK_MODE_SUPPORTED                   _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_SPI_MODE_SHIFT                     _MK_SHIFT_CONST(29)
+#define SDMMC_CAPABILITIES_0_SPI_MODE_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_SPI_MODE_SHIFT)
+#define SDMMC_CAPABILITIES_0_SPI_MODE_RANGE                     29:29
+#define SDMMC_CAPABILITIES_0_SPI_MODE_WOFFSET                   0x0
+#define SDMMC_CAPABILITIES_0_SPI_MODE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_SPI_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_SPI_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_SPI_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_SPI_MODE_NOT_SUPPORTED                     _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_SPI_MODE_SUPPORTED                 _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_SHIFT                     _MK_SHIFT_CONST(28)
+#define SDMMC_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_SHIFT)
+#define SDMMC_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_RANGE                     28:28
+#define SDMMC_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_WOFFSET                   0x0
+#define SDMMC_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_NOT_SUPPORTED                     _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_SYSTEM_BUS_64BIT_SUPPORT_SUPPORTED                 _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_INTERRUPT_MODE_SHIFT                       _MK_SHIFT_CONST(27)
+#define SDMMC_CAPABILITIES_0_INTERRUPT_MODE_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_INTERRUPT_MODE_SHIFT)
+#define SDMMC_CAPABILITIES_0_INTERRUPT_MODE_RANGE                       27:27
+#define SDMMC_CAPABILITIES_0_INTERRUPT_MODE_WOFFSET                     0x0
+#define SDMMC_CAPABILITIES_0_INTERRUPT_MODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_INTERRUPT_MODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_INTERRUPT_MODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_INTERRUPT_MODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_INTERRUPT_MODE_NOT_SUPPORTED                       _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_INTERRUPT_MODE_SUPPORTED                   _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_SHIFT                        _MK_SHIFT_CONST(26)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_SHIFT)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_RANGE                        26:26
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_WOFFSET                      0x0
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_NOT_SUPPORTED                        _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_1_8_V_SUPPORTED                    _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_SHIFT                        _MK_SHIFT_CONST(25)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_SHIFT)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_RANGE                        25:25
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_WOFFSET                      0x0
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_NOT_SUPPORTED                        _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_0_V_SUPPORTED                    _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_SHIFT                        _MK_SHIFT_CONST(24)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_SHIFT)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_RANGE                        24:24
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_WOFFSET                      0x0
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_DEFAULT                      _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_NOT_SUPPORTED                        _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_VOLTAGE_SUPPORT_3_3_V_SUPPORTED                    _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_SHIFT                       _MK_SHIFT_CONST(23)
+#define SDMMC_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_SHIFT)
+#define SDMMC_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_RANGE                       23:23
+#define SDMMC_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_WOFFSET                     0x0
+#define SDMMC_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_DEFAULT                     _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_NOT_SUPPORTED                       _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_SUSPEND_RESUME_SUPPORT_SUPPORTED                   _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_DMA_SUPPORT_SHIFT                  _MK_SHIFT_CONST(22)
+#define SDMMC_CAPABILITIES_0_DMA_SUPPORT_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_DMA_SUPPORT_SHIFT)
+#define SDMMC_CAPABILITIES_0_DMA_SUPPORT_RANGE                  22:22
+#define SDMMC_CAPABILITIES_0_DMA_SUPPORT_WOFFSET                        0x0
+#define SDMMC_CAPABILITIES_0_DMA_SUPPORT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_DMA_SUPPORT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_DMA_SUPPORT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_DMA_SUPPORT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_DMA_SUPPORT_NOT_SUPPORTED                  _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_DMA_SUPPORT_SUPPORTED                      _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_SHIFT                   _MK_SHIFT_CONST(21)
+#define SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_SHIFT)
+#define SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_RANGE                   21:21
+#define SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_WOFFSET                 0x0
+#define SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_NOT_SUPPORTED                   _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_HIGH_SPEED_SUPPORT_SUPPORTED                       _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_ADMA1_SUPPORT_SHIFT                        _MK_SHIFT_CONST(20)
+#define SDMMC_CAPABILITIES_0_ADMA1_SUPPORT_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_ADMA1_SUPPORT_SHIFT)
+#define SDMMC_CAPABILITIES_0_ADMA1_SUPPORT_RANGE                        20:20
+#define SDMMC_CAPABILITIES_0_ADMA1_SUPPORT_WOFFSET                      0x0
+#define SDMMC_CAPABILITIES_0_ADMA1_SUPPORT_DEFAULT                      _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_ADMA1_SUPPORT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_ADMA1_SUPPORT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_ADMA1_SUPPORT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_ADMA1_SUPPORT_NOT_SUPPORTED                        _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_ADMA1_SUPPORT_SUPPORTED                    _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_ADMA2_SUPPORT_SHIFT                        _MK_SHIFT_CONST(19)
+#define SDMMC_CAPABILITIES_0_ADMA2_SUPPORT_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_ADMA2_SUPPORT_SHIFT)
+#define SDMMC_CAPABILITIES_0_ADMA2_SUPPORT_RANGE                        19:19
+#define SDMMC_CAPABILITIES_0_ADMA2_SUPPORT_WOFFSET                      0x0
+#define SDMMC_CAPABILITIES_0_ADMA2_SUPPORT_DEFAULT                      _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_ADMA2_SUPPORT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_ADMA2_SUPPORT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_ADMA2_SUPPORT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_ADMA2_SUPPORT_NOT_SUPPORTED                        _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_ADMA2_SUPPORT_SUPPORTED                    _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_SHIFT                   _MK_SHIFT_CONST(18)
+#define SDMMC_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_SHIFT)
+#define SDMMC_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_RANGE                   18:18
+#define SDMMC_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_WOFFSET                 0x0
+#define SDMMC_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_NOT_SUPPORTED                   _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_EXTENDED_MEDIA_BUS_SUPPORT_SUPPORTED                       _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_SHIFT                     _MK_SHIFT_CONST(16)
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_FIELD                     (_MK_MASK_CONST(0x3) << SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_SHIFT)
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_RANGE                     17:16
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_WOFFSET                   0x0
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_DEFAULT                   _MK_MASK_CONST(0x3)
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_BYTE512                   _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_BYTE1024                  _MK_ENUM_CONST(1)
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_BYTE2048                  _MK_ENUM_CONST(2)
+#define SDMMC_CAPABILITIES_0_MAX_BLOCK_LENGTH_RESERVED                  _MK_ENUM_CONST(3)
+
+#define SDMMC_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_SHIFT                 _MK_SHIFT_CONST(8)
+#define SDMMC_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_FIELD                 (_MK_MASK_CONST(0x3f) << SDMMC_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_SHIFT)
+#define SDMMC_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_RANGE                 13:8
+#define SDMMC_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_WOFFSET                       0x0
+#define SDMMC_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_DEFAULT                       _MK_MASK_CONST(0x30)
+#define SDMMC_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define SDMMC_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_BASE_CLOCK_FREQUENCY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_SHIFT                   _MK_SHIFT_CONST(7)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_SHIFT)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_RANGE                   7:7
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_WOFFSET                 0x0
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_KHZ                     _MK_ENUM_CONST(0)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_UNIT_MHZ                     _MK_ENUM_CONST(1)
+
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_SHIFT                      _MK_SHIFT_CONST(0)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_FIELD                      (_MK_MASK_CONST(0x3f) << SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_SHIFT)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_RANGE                      5:0
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_WOFFSET                    0x0
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_DEFAULT                    _MK_MASK_CONST(0x30)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_CAPABILITIES_0_TIMEOUT_CLOCK_FREQUENCY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 68 [0x44] 
+
+// Register SDMMC_MAXIMUM_CURRENT_0  
+#define SDMMC_MAXIMUM_CURRENT_0                 _MK_ADDR_CONST(0x48)
+#define SDMMC_MAXIMUM_CURRENT_0_SECURE                  0x0
+#define SDMMC_MAXIMUM_CURRENT_0_WORD_COUNT                      0x1
+#define SDMMC_MAXIMUM_CURRENT_0_RESET_VAL                       _MK_MASK_CONST(0x1)
+#define SDMMC_MAXIMUM_CURRENT_0_RESET_MASK                      _MK_MASK_CONST(0xffffff)
+#define SDMMC_MAXIMUM_CURRENT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SDMMC_MAXIMUM_CURRENT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SDMMC_MAXIMUM_CURRENT_0_READ_MASK                       _MK_MASK_CONST(0xffffff)
+#define SDMMC_MAXIMUM_CURRENT_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// Maximum Current for 1.8V
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_SHIFT                  _MK_SHIFT_CONST(16)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_FIELD                  (_MK_MASK_CONST(0xff) << SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_SHIFT)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_RANGE                  23:16
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_WOFFSET                        0x0
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_1_8V_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum Current for 3.0V
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_SHIFT                  _MK_SHIFT_CONST(8)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_FIELD                  (_MK_MASK_CONST(0xff) << SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_SHIFT)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_RANGE                  15:8
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_WOFFSET                        0x0
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_0V_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Maximum Current for 3.3V
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_SHIFT                  _MK_SHIFT_CONST(0)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_FIELD                  (_MK_MASK_CONST(0xff) << SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_SHIFT)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_RANGE                  7:0
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_WOFFSET                        0x0
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_DEFAULT                        _MK_MASK_CONST(0x1)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_MAXIMUM_CURRENT_0_MAXIMUM_CURRENT_FOR_3_3V_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 76 [0x4c] 
+
+// Register SDMMC_FORCE_EVENT_0  
+#define SDMMC_FORCE_EVENT_0                     _MK_ADDR_CONST(0x50)
+#define SDMMC_FORCE_EVENT_0_SECURE                      0x0
+#define SDMMC_FORCE_EVENT_0_WORD_COUNT                  0x1
+#define SDMMC_FORCE_EVENT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_RESET_MASK                  _MK_MASK_CONST(0xfbff009f)
+#define SDMMC_FORCE_EVENT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_READ_MASK                   _MK_MASK_CONST(0xfbff009f)
+#define SDMMC_FORCE_EVENT_0_WRITE_MASK                  _MK_MASK_CONST(0xfbff009f)
+#define SDMMC_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_SHIFT                    _MK_SHIFT_CONST(30)
+#define SDMMC_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_FIELD                    (_MK_MASK_CONST(0x3) << SDMMC_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_SHIFT)
+#define SDMMC_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_RANGE                    31:30
+#define SDMMC_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_WOFFSET                  0x0
+#define SDMMC_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SDMMC_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_DISABLE                  _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_VENDOR_SPECIFIC_ERR_STATUS_ENABLE                   _MK_ENUM_CONST(3)
+
+#define SDMMC_FORCE_EVENT_0_CEATA_ERROR_SHIFT                   _MK_SHIFT_CONST(29)
+#define SDMMC_FORCE_EVENT_0_CEATA_ERROR_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_CEATA_ERROR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_CEATA_ERROR_RANGE                   29:29
+#define SDMMC_FORCE_EVENT_0_CEATA_ERROR_WOFFSET                 0x0
+#define SDMMC_FORCE_EVENT_0_CEATA_ERROR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_CEATA_ERROR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_CEATA_ERROR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_CEATA_ERROR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_CEATA_ERROR_NO_ERROR                        _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_CEATA_ERROR_ERROR                   _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_TARGET_RESP_ERROR_SHIFT                     _MK_SHIFT_CONST(28)
+#define SDMMC_FORCE_EVENT_0_TARGET_RESP_ERROR_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_TARGET_RESP_ERROR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_TARGET_RESP_ERROR_RANGE                     28:28
+#define SDMMC_FORCE_EVENT_0_TARGET_RESP_ERROR_WOFFSET                   0x0
+#define SDMMC_FORCE_EVENT_0_TARGET_RESP_ERROR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_TARGET_RESP_ERROR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_TARGET_RESP_ERROR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_TARGET_RESP_ERROR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_TARGET_RESP_ERROR_NO_ERROR                  _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_TARGET_RESP_ERROR_ERROR                     _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_SPI_ERR_SHIFT                       _MK_SHIFT_CONST(27)
+#define SDMMC_FORCE_EVENT_0_SPI_ERR_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_SPI_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_SPI_ERR_RANGE                       27:27
+#define SDMMC_FORCE_EVENT_0_SPI_ERR_WOFFSET                     0x0
+#define SDMMC_FORCE_EVENT_0_SPI_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_SPI_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_SPI_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_SPI_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_SPI_ERR_DISABLE                     _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_SPI_ERR_ENABLE                      _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_ADMA_ERR_SHIFT                      _MK_SHIFT_CONST(25)
+#define SDMMC_FORCE_EVENT_0_ADMA_ERR_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_ADMA_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_ADMA_ERR_RANGE                      25:25
+#define SDMMC_FORCE_EVENT_0_ADMA_ERR_WOFFSET                    0x0
+#define SDMMC_FORCE_EVENT_0_ADMA_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_ADMA_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_ADMA_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_ADMA_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_ADMA_ERR_NO_INTERRUPT                       _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_ADMA_ERR_INTERRUPT                  _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_AUTOCMD12_ERR_SHIFT                 _MK_SHIFT_CONST(24)
+#define SDMMC_FORCE_EVENT_0_AUTOCMD12_ERR_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_AUTOCMD12_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_AUTOCMD12_ERR_RANGE                 24:24
+#define SDMMC_FORCE_EVENT_0_AUTOCMD12_ERR_WOFFSET                       0x0
+#define SDMMC_FORCE_EVENT_0_AUTOCMD12_ERR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTOCMD12_ERR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_AUTOCMD12_ERR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTOCMD12_ERR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTOCMD12_ERR_NO_INTERRUPT                  _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_AUTOCMD12_ERR_INTERRUPT                     _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_CURRENTLIMIT_ERR_SHIFT                      _MK_SHIFT_CONST(23)
+#define SDMMC_FORCE_EVENT_0_CURRENTLIMIT_ERR_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_CURRENTLIMIT_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_CURRENTLIMIT_ERR_RANGE                      23:23
+#define SDMMC_FORCE_EVENT_0_CURRENTLIMIT_ERR_WOFFSET                    0x0
+#define SDMMC_FORCE_EVENT_0_CURRENTLIMIT_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_CURRENTLIMIT_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_CURRENTLIMIT_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_CURRENTLIMIT_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_CURRENTLIMIT_ERR_NO_INTERRUPT                       _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_CURRENTLIMIT_ERR_INTERRUPT                  _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_DATA_END_BIT_ERR_SHIFT                      _MK_SHIFT_CONST(22)
+#define SDMMC_FORCE_EVENT_0_DATA_END_BIT_ERR_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_DATA_END_BIT_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_DATA_END_BIT_ERR_RANGE                      22:22
+#define SDMMC_FORCE_EVENT_0_DATA_END_BIT_ERR_WOFFSET                    0x0
+#define SDMMC_FORCE_EVENT_0_DATA_END_BIT_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_DATA_END_BIT_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_DATA_END_BIT_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_DATA_END_BIT_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_DATA_END_BIT_ERR_NO_INTERRUPT                       _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_DATA_END_BIT_ERR_INTERRUPT                  _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_DATACRC_ERR_SHIFT                   _MK_SHIFT_CONST(21)
+#define SDMMC_FORCE_EVENT_0_DATACRC_ERR_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_DATACRC_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_DATACRC_ERR_RANGE                   21:21
+#define SDMMC_FORCE_EVENT_0_DATACRC_ERR_WOFFSET                 0x0
+#define SDMMC_FORCE_EVENT_0_DATACRC_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_DATACRC_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_DATACRC_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_DATACRC_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_DATACRC_ERR_NO_INTERRUPT                    _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_DATACRC_ERR_INTERRUPT                       _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_DATATIMEOUT_ERR_SHIFT                       _MK_SHIFT_CONST(20)
+#define SDMMC_FORCE_EVENT_0_DATATIMEOUT_ERR_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_DATATIMEOUT_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_DATATIMEOUT_ERR_RANGE                       20:20
+#define SDMMC_FORCE_EVENT_0_DATATIMEOUT_ERR_WOFFSET                     0x0
+#define SDMMC_FORCE_EVENT_0_DATATIMEOUT_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_DATATIMEOUT_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_DATATIMEOUT_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_DATATIMEOUT_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_DATATIMEOUT_ERR_NO_INTERRUPT                        _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_DATATIMEOUT_ERR_INTERRUPT                   _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_COMMAND_INDEX_ERR_SHIFT                     _MK_SHIFT_CONST(19)
+#define SDMMC_FORCE_EVENT_0_COMMAND_INDEX_ERR_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_COMMAND_INDEX_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_COMMAND_INDEX_ERR_RANGE                     19:19
+#define SDMMC_FORCE_EVENT_0_COMMAND_INDEX_ERR_WOFFSET                   0x0
+#define SDMMC_FORCE_EVENT_0_COMMAND_INDEX_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_INDEX_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_COMMAND_INDEX_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_INDEX_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_INDEX_ERR_NO_INTERRUPT                      _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_INDEX_ERR_INTERRUPT                 _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_COMMAND_END_BIT_ERR_SHIFT                   _MK_SHIFT_CONST(18)
+#define SDMMC_FORCE_EVENT_0_COMMAND_END_BIT_ERR_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_COMMAND_END_BIT_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_COMMAND_END_BIT_ERR_RANGE                   18:18
+#define SDMMC_FORCE_EVENT_0_COMMAND_END_BIT_ERR_WOFFSET                 0x0
+#define SDMMC_FORCE_EVENT_0_COMMAND_END_BIT_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_END_BIT_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_COMMAND_END_BIT_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_END_BIT_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_END_BIT_ERR_NO_INTERRUPT                    _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_END_BIT_ERR_INTERRUPT                       _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_COMMAND_CRC_ERR_SHIFT                       _MK_SHIFT_CONST(17)
+#define SDMMC_FORCE_EVENT_0_COMMAND_CRC_ERR_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_COMMAND_CRC_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_COMMAND_CRC_ERR_RANGE                       17:17
+#define SDMMC_FORCE_EVENT_0_COMMAND_CRC_ERR_WOFFSET                     0x0
+#define SDMMC_FORCE_EVENT_0_COMMAND_CRC_ERR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_CRC_ERR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_COMMAND_CRC_ERR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_CRC_ERR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_CRC_ERR_NO_INTERRUPT                        _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_CRC_ERR_INTERRUPT                   _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_SHIFT                   _MK_SHIFT_CONST(16)
+#define SDMMC_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_FIELD                   (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_RANGE                   16:16
+#define SDMMC_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_WOFFSET                 0x0
+#define SDMMC_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_NO_INTERRUPT                    _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_COMMAND_TIMEOUT_ERR_INTERRUPT                       _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_SHIFT                 _MK_SHIFT_CONST(7)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_SHIFT)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_RANGE                 7:7
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_WOFFSET                       0x0
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_NO_INTERRUPT                  _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_ISSUED_INTERRUPT                     _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_SHIFT                  _MK_SHIFT_CONST(4)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_RANGE                  4:4
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_WOFFSET                        0x0
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_NO_INTERRUPT                   _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_INDEX_ERR_INTERRUPT                      _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_SHIFT                        _MK_SHIFT_CONST(3)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_RANGE                        3:3
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_WOFFSET                      0x0
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_NO_INTERRUPT                 _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_END_BIT_ERR_INTERRUPT                    _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_SHIFT                    _MK_SHIFT_CONST(2)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_RANGE                    2:2
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_WOFFSET                  0x0
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_NO_INTERRUPT                     _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_CRC_ERR_INTERRUPT                        _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_SHIFT                        _MK_SHIFT_CONST(1)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_SHIFT)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_RANGE                        1:1
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_WOFFSET                      0x0
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_NO_INTERRUPT                 _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_TIMEOUT_ERR_INTERRUPT                    _MK_ENUM_CONST(1)
+
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_SHIFT                       _MK_SHIFT_CONST(0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_FIELD                       (_MK_MASK_CONST(0x1) << SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_SHIFT)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_RANGE                       0:0
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_WOFFSET                     0x0
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_NO_INTERRUPT                        _MK_ENUM_CONST(0)
+#define SDMMC_FORCE_EVENT_0_AUTO_CMD12_NOT_EXECUTED_INTERRUPT                   _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_ADMA_ERR_STATUS_0  
+#define SDMMC_ADMA_ERR_STATUS_0                 _MK_ADDR_CONST(0x54)
+#define SDMMC_ADMA_ERR_STATUS_0_SECURE                  0x0
+#define SDMMC_ADMA_ERR_STATUS_0_WORD_COUNT                      0x1
+#define SDMMC_ADMA_ERR_STATUS_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_ERR_STATUS_0_RESET_MASK                      _MK_MASK_CONST(0x7)
+#define SDMMC_ADMA_ERR_STATUS_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_ERR_STATUS_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_ERR_STATUS_0_READ_MASK                       _MK_MASK_CONST(0x7)
+#define SDMMC_ADMA_ERR_STATUS_0_WRITE_MASK                      _MK_MASK_CONST(0x7)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_SHIFT                  _MK_SHIFT_CONST(2)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_FIELD                  (_MK_MASK_CONST(0x1) << SDMMC_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_SHIFT)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_RANGE                  2:2
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_WOFFSET                        0x0
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_NO_ERR                 _MK_ENUM_CONST(0)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_LENGTH_MISMATCH_ERR_ERR                    _MK_ENUM_CONST(1)
+
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_SHIFT                    _MK_SHIFT_CONST(0)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_FIELD                    (_MK_MASK_CONST(0x3) << SDMMC_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_SHIFT)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_RANGE                    1:0
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_WOFFSET                  0x0
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_ERR_STATUS_0_ADMA_ERR_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_ADMA_SYSTEM_ADDRESS_0  
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0                     _MK_ADDR_CONST(0x58)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_SECURE                      0x0
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_WORD_COUNT                  0x1
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_SHIFT                   _MK_SHIFT_CONST(0)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_FIELD                   (_MK_MASK_CONST(0xffffffff) << SDMMC_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_SHIFT)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_RANGE                   31:0
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_WOFFSET                 0x0
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_ADMA_SYSTEM_ADDRESS_0_ADMA_SYSTEM_ADDRESS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 92 [0x5c] 
+
+// Register SDMMC_DEBUG_SELECTION_REGISTER_0  
+#define SDMMC_DEBUG_SELECTION_REGISTER_0                        _MK_ADDR_CONST(0x60)
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_SECURE                         0x0
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_WORD_COUNT                     0x1
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// 1 = CMD REGISTER, INTERRUPT STATUS,AHB_IFACE_MODULE.
+// 0 = RECEIVER MODULE and FIFO CONTROL
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_DEBUG_SEL_SHIFT                        _MK_SHIFT_CONST(0)
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_DEBUG_SEL_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_DEBUG_SELECTION_REGISTER_0_DEBUG_SEL_SHIFT)
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_DEBUG_SEL_RANGE                        0:0
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_DEBUG_SEL_WOFFSET                      0x0
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_DEBUG_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_DEBUG_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_DEBUG_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_DEBUG_SELECTION_REGISTER_0_DEBUG_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Reserved address 112 [0x70] 
+
+// Reserved address 116 [0x74] 
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Register SDMMC_SPI_INTERRUPT_SUPPORT_0  
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0                   _MK_ADDR_CONST(0xf0)
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_SECURE                    0x0
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_WORD_COUNT                        0x1
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+//This bit is set to indicate the assertion of interrupts in SPI MODE at anytime
+// Irrespective on the staus of card select. 
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_SPI_INT_SUPPORT_SHIFT                     _MK_SHIFT_CONST(0)
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_SPI_INT_SUPPORT_FIELD                     (_MK_MASK_CONST(0xff) << SDMMC_SPI_INTERRUPT_SUPPORT_0_SPI_INT_SUPPORT_SHIFT)
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_SPI_INT_SUPPORT_RANGE                     7:0
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_SPI_INT_SUPPORT_WOFFSET                   0x0
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_SPI_INT_SUPPORT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_SPI_INT_SUPPORT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_SPI_INT_SUPPORT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_SPI_INTERRUPT_SUPPORT_0_SPI_INT_SUPPORT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Register SDMMC_SLOT_INTERRUPT_STATUS_0  
+#define SDMMC_SLOT_INTERRUPT_STATUS_0                   _MK_ADDR_CONST(0xfc)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_SECURE                    0x0
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_WORD_COUNT                        0x1
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0xffff00ff)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xffff00ff)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_SHIFT                       _MK_SHIFT_CONST(24)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_FIELD                       (_MK_MASK_CONST(0xff) << SDMMC_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_SHIFT)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_RANGE                       31:24
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_WOFFSET                     0x0
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_VENDOR_VERSION_NUMBER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_SHIFT                        _MK_SHIFT_CONST(16)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_FIELD                        (_MK_MASK_CONST(0xff) << SDMMC_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_SHIFT)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_RANGE                        23:16
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_WOFFSET                      0x0
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_SPECIFICATION_VERSION_NUMBER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_SHIFT                      _MK_SHIFT_CONST(0)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_FIELD                      (_MK_MASK_CONST(0xff) << SDMMC_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_SHIFT)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_RANGE                      7:0
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_WOFFSET                    0x0
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_SLOT_INTERRUPT_STATUS_0_INTERRUPT_SIGNAL_FOR_EACH_SLOT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_VENDOR_CLOCK_CNTRL_0  
+#define SDMMC_VENDOR_CLOCK_CNTRL_0                      _MK_ADDR_CONST(0x100)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SECURE                       0x0
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_WORD_COUNT                   0x1
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+//  This is set when sdmmc_clk is supplied by the CAR module.Prior to sdmmc_clk switch OFF.This bit should be written '0'.  Prior to sdmmc_clk switch OFF.This bit should be written '0'.
+//  By writing zero,the asynchronous card interrupt is routed to the Interrupt controller.
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_SHIFT                      _MK_SHIFT_CONST(0)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_FIELD                      (_MK_MASK_CONST(0x1) << SDMMC_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_SHIFT)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_RANGE                      0:0
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_WOFFSET                    0x0
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_DEFAULT                    _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_DISABLE                    _MK_ENUM_CONST(0)
+#define SDMMC_VENDOR_CLOCK_CNTRL_0_SDMMC_CLK_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_VENDOR_SPI_CNTRL_0  
+#define SDMMC_VENDOR_SPI_CNTRL_0                        _MK_ADDR_CONST(0x104)
+#define SDMMC_VENDOR_SPI_CNTRL_0_SECURE                         0x0
+#define SDMMC_VENDOR_SPI_CNTRL_0_WORD_COUNT                     0x1
+#define SDMMC_VENDOR_SPI_CNTRL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_CNTRL_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_SPI_CNTRL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_CNTRL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_CNTRL_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_SPI_CNTRL_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+//  This is a mirror bit.The SPI mode is set if this bit is set or CMD_XFER_MODE[7] is set  Writing 1 will drive the CS Low and writing zero will de-assert the CS Signal
+#define SDMMC_VENDOR_SPI_CNTRL_0_SPI_MODE_SHIFT                 _MK_SHIFT_CONST(0)
+#define SDMMC_VENDOR_SPI_CNTRL_0_SPI_MODE_FIELD                 (_MK_MASK_CONST(0x1) << SDMMC_VENDOR_SPI_CNTRL_0_SPI_MODE_SHIFT)
+#define SDMMC_VENDOR_SPI_CNTRL_0_SPI_MODE_RANGE                 0:0
+#define SDMMC_VENDOR_SPI_CNTRL_0_SPI_MODE_WOFFSET                       0x0
+#define SDMMC_VENDOR_SPI_CNTRL_0_SPI_MODE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_CNTRL_0_SPI_MODE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_SPI_CNTRL_0_SPI_MODE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_CNTRL_0_SPI_MODE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_CNTRL_0_SPI_MODE_DISABLE                       _MK_ENUM_CONST(0)
+#define SDMMC_VENDOR_SPI_CNTRL_0_SPI_MODE_ENABLE                        _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_VENDOR_SPI_INTR_STATUS_0  
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0                  _MK_ADDR_CONST(0x108)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_SECURE                   0x0
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_WORD_COUNT                       0x1
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0x1ff)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+//  Data Error Token,while read from card. 
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_ERR_TOKEN_SHIFT                      _MK_SHIFT_CONST(5)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_ERR_TOKEN_FIELD                      (_MK_MASK_CONST(0xf) << SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_ERR_TOKEN_SHIFT)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_ERR_TOKEN_RANGE                      8:5
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_ERR_TOKEN_WOFFSET                    0x0
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_ERR_TOKEN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_ERR_TOKEN_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_ERR_TOKEN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_ERR_TOKEN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+//  Data Response while write to card  
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_SHIFT                       _MK_SHIFT_CONST(0)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_FIELD                       (_MK_MASK_CONST(0x1f) << SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_SHIFT)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_RANGE                       4:0
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_WOFFSET                     0x0
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_DATA_ACCEPTED                       _MK_ENUM_CONST(5)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_CRC_ERR                     _MK_ENUM_CONST(11)
+#define SDMMC_VENDOR_SPI_INTR_STATUS_0_DAT_RESPONSE_WRITE_ERR                   _MK_ENUM_CONST(13)
+
+
+// Register SDMMC_VENDOR_CEATA_CNTRL_0  
+#define SDMMC_VENDOR_CEATA_CNTRL_0                      _MK_ADDR_CONST(0x10c)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_SECURE                       0x0
+#define SDMMC_VENDOR_CEATA_CNTRL_0_WORD_COUNT                   0x1
+#define SDMMC_VENDOR_CEATA_CNTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_RESET_MASK                   _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_READ_MASK                    _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x1)
+//  If this bit is set to 1,the controller expects a Command completion signal from the card after the transfer.  If the CCS Signal doesnt come within Data Timeout Value the CEATA Error is flagged.
+#define SDMMC_VENDOR_CEATA_CNTRL_0_CCS_SIGNAL_SHIFT                     _MK_SHIFT_CONST(0)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_CCS_SIGNAL_FIELD                     (_MK_MASK_CONST(0x1) << SDMMC_VENDOR_CEATA_CNTRL_0_CCS_SIGNAL_SHIFT)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_CCS_SIGNAL_RANGE                     0:0
+#define SDMMC_VENDOR_CEATA_CNTRL_0_CCS_SIGNAL_WOFFSET                   0x0
+#define SDMMC_VENDOR_CEATA_CNTRL_0_CCS_SIGNAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_CCS_SIGNAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_CCS_SIGNAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_CCS_SIGNAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_CCS_SIGNAL_DISABLE                   _MK_ENUM_CONST(0)
+#define SDMMC_VENDOR_CEATA_CNTRL_0_CCS_SIGNAL_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_VENDOR_BOOT_CNTRL_0  
+#define SDMMC_VENDOR_BOOT_CNTRL_0                       _MK_ADDR_CONST(0x110)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_SECURE                        0x0
+#define SDMMC_VENDOR_BOOT_CNTRL_0_WORD_COUNT                    0x1
+#define SDMMC_VENDOR_BOOT_CNTRL_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_RESET_MASK                    _MK_MASK_CONST(0x3)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_READ_MASK                     _MK_MASK_CONST(0x3)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_WRITE_MASK                    _MK_MASK_CONST(0x3)
+//  This bit is used to support Boot Option in MMC 4.3 version cards.  If set Boot acknowledgment is given by card else not given by card  
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_SHIFT                        _MK_SHIFT_CONST(1)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_FIELD                        (_MK_MASK_CONST(0x1) << SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_SHIFT)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_RANGE                        1:1
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_WOFFSET                      0x0
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_DISABLE                      _MK_ENUM_CONST(0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ACK_ENABLE                       _MK_ENUM_CONST(1)
+
+//  This bit enables/disable BootOption1.If set BootOption1 is enable,HW auto clears it when boot data is done.  Writing 0 terminates the BootOption1    
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_SHIFT                    _MK_SHIFT_CONST(0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_FIELD                    (_MK_MASK_CONST(0x1) << SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_SHIFT)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_RANGE                    0:0
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_WOFFSET                  0x0
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_DISABLE                  _MK_ENUM_CONST(0)
+#define SDMMC_VENDOR_BOOT_CNTRL_0_BOOT_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0  
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0                 _MK_ADDR_CONST(0x114)
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_SECURE                  0x0
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_WORD_COUNT                      0x1
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_RESET_MASK                      _MK_MASK_CONST(0xfffff)
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_READ_MASK                       _MK_MASK_CONST(0xfffff)
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_WRITE_MASK                      _MK_MASK_CONST(0xfffff)
+//  If Boot Acknowledgment is not recieved within the the programmed number of cycles. 
+//  Boot Acknowledgement Timeout error occurs(VENDOR_SPECIFIC_ERR[0])
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_FIELD                     (_MK_MASK_CONST(0xfffff) << SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_SHIFT)
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_RANGE                     19:0
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_WOFFSET                   0x0
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0xfffff)
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0  
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0                 _MK_ADDR_CONST(0x118)
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_SECURE                  0x0
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_WORD_COUNT                      0x1
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_RESET_MASK                      _MK_MASK_CONST(0x1ffffff)
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_READ_MASK                       _MK_MASK_CONST(0x1ffffff)
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_WRITE_MASK                      _MK_MASK_CONST(0x1ffffff)
+//  If Boot Data is not recieved within the the programmed number of cycles. Then Data Timeout error occurs.
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_SHIFT                     _MK_SHIFT_CONST(0)
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_FIELD                     (_MK_MASK_CONST(0x1ffffff) << SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_SHIFT)
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_RANGE                     24:0
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_WOFFSET                   0x0
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0x1ffffff)
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_VENDOR_DEBOUNCE_COUNT_0  
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0                   _MK_ADDR_CONST(0x11c)
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_SECURE                    0x0
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_WORD_COUNT                        0x1
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_RESET_VAL                         _MK_MASK_CONST(0xc80)
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_RESET_MASK                        _MK_MASK_CONST(0xffffff)
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_READ_MASK                         _MK_MASK_CONST(0xffffff)
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_WRITE_MASK                        _MK_MASK_CONST(0xffffff)
+//  The number of 32KHz clock cycles is programed to meet Debounce period of the card slot.
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_VALUE_SHIFT                       _MK_SHIFT_CONST(0)
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_VALUE_FIELD                       (_MK_MASK_CONST(0xffffff) << SDMMC_VENDOR_DEBOUNCE_COUNT_0_VALUE_SHIFT)
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_VALUE_RANGE                       23:0
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_VALUE_WOFFSET                     0x0
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_VALUE_DEFAULT                     _MK_MASK_CONST(0xc80)
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_VALUE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffff)
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_VALUE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_DEBOUNCE_COUNT_0_VALUE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register SDMMC_VENDOR_OBS_BUS_0  
+#define SDMMC_VENDOR_OBS_BUS_0                  _MK_ADDR_CONST(0x120)
+#define SDMMC_VENDOR_OBS_BUS_0_SECURE                   0x0
+#define SDMMC_VENDOR_OBS_BUS_0_WORD_COUNT                       0x1
+#define SDMMC_VENDOR_OBS_BUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_OBS_BUS_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SDMMC_VENDOR_OBS_BUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_OBS_BUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_OBS_BUS_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define SDMMC_VENDOR_OBS_BUS_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+//  Debug Information.
+#define SDMMC_VENDOR_OBS_BUS_0_DATA_SHIFT                       _MK_SHIFT_CONST(4)
+#define SDMMC_VENDOR_OBS_BUS_0_DATA_FIELD                       (_MK_MASK_CONST(0xfffffff) << SDMMC_VENDOR_OBS_BUS_0_DATA_SHIFT)
+#define SDMMC_VENDOR_OBS_BUS_0_DATA_RANGE                       31:4
+#define SDMMC_VENDOR_OBS_BUS_0_DATA_WOFFSET                     0x0
+#define SDMMC_VENDOR_OBS_BUS_0_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_OBS_BUS_0_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0xfffffff)
+#define SDMMC_VENDOR_OBS_BUS_0_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_OBS_BUS_0_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//  Debug Select.Values from 0 to 7 are valid. 
+#define SDMMC_VENDOR_OBS_BUS_0_SEL_SHIFT                        _MK_SHIFT_CONST(0)
+#define SDMMC_VENDOR_OBS_BUS_0_SEL_FIELD                        (_MK_MASK_CONST(0xf) << SDMMC_VENDOR_OBS_BUS_0_SEL_SHIFT)
+#define SDMMC_VENDOR_OBS_BUS_0_SEL_RANGE                        3:0
+#define SDMMC_VENDOR_OBS_BUS_0_SEL_WOFFSET                      0x0
+#define SDMMC_VENDOR_OBS_BUS_0_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_OBS_BUS_0_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define SDMMC_VENDOR_OBS_BUS_0_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SDMMC_VENDOR_OBS_BUS_0_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSDMMC_REGS(_op_) \
+_op_(SDMMC_SYSTEM_ADDRESS_0) \
+_op_(SDMMC_BLOCK_SIZE_BLOCK_COUNT_0) \
+_op_(SDMMC_ARGUMENT_0) \
+_op_(SDMMC_CMD_XFER_MODE_0) \
+_op_(SDMMC_RESPONSE_R0_R1_0) \
+_op_(SDMMC_RESPONSE_R2_R3_0) \
+_op_(SDMMC_RESPONSE_R4_R5_0) \
+_op_(SDMMC_RESPONSE_R6_R7_0) \
+_op_(SDMMC_BUFFER_DATA_PORT_0) \
+_op_(SDMMC_PRESENT_STATE_0) \
+_op_(SDMMC_POWER_CONTROL_HOST_0) \
+_op_(SDMMC_SW_RESET_TIMEOUT_CTRL_CLOCK_CONTROL_0) \
+_op_(SDMMC_INTERRUPT_STATUS_0) \
+_op_(SDMMC_INTERRUPT_STATUS_ENABLE_0) \
+_op_(SDMMC_INTERRUPT_SIGNAL_ENABLE_0) \
+_op_(SDMMC_AUTO_CMD12_ERR_STATUS_0) \
+_op_(SDMMC_CAPABILITIES_0) \
+_op_(SDMMC_MAXIMUM_CURRENT_0) \
+_op_(SDMMC_FORCE_EVENT_0) \
+_op_(SDMMC_ADMA_ERR_STATUS_0) \
+_op_(SDMMC_ADMA_SYSTEM_ADDRESS_0) \
+_op_(SDMMC_DEBUG_SELECTION_REGISTER_0) \
+_op_(SDMMC_SPI_INTERRUPT_SUPPORT_0) \
+_op_(SDMMC_SLOT_INTERRUPT_STATUS_0) \
+_op_(SDMMC_VENDOR_CLOCK_CNTRL_0) \
+_op_(SDMMC_VENDOR_SPI_CNTRL_0) \
+_op_(SDMMC_VENDOR_SPI_INTR_STATUS_0) \
+_op_(SDMMC_VENDOR_CEATA_CNTRL_0) \
+_op_(SDMMC_VENDOR_BOOT_CNTRL_0) \
+_op_(SDMMC_VENDOR_BOOT_ACK_TIMEOUT_0) \
+_op_(SDMMC_VENDOR_BOOT_DAT_TIMEOUT_0) \
+_op_(SDMMC_VENDOR_DEBOUNCE_COUNT_0) \
+_op_(SDMMC_VENDOR_OBS_BUS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_SDMMC      0x00000000
+
+//
+// ARSDMMC REGISTER BANKS
+//
+
+#define SDMMC0_FIRST_REG 0x0000 // SDMMC_SYSTEM_ADDRESS_0
+#define SDMMC0_LAST_REG 0x0040 // SDMMC_CAPABILITIES_0
+#define SDMMC1_FIRST_REG 0x0048 // SDMMC_MAXIMUM_CURRENT_0
+#define SDMMC1_LAST_REG 0x0048 // SDMMC_MAXIMUM_CURRENT_0
+#define SDMMC2_FIRST_REG 0x0050 // SDMMC_FORCE_EVENT_0
+#define SDMMC2_LAST_REG 0x0058 // SDMMC_ADMA_SYSTEM_ADDRESS_0
+#define SDMMC3_FIRST_REG 0x0060 // SDMMC_DEBUG_SELECTION_REGISTER_0
+#define SDMMC3_LAST_REG 0x0060 // SDMMC_DEBUG_SELECTION_REGISTER_0
+#define SDMMC4_FIRST_REG 0x00f0 // SDMMC_SPI_INTERRUPT_SUPPORT_0
+#define SDMMC4_LAST_REG 0x00f0 // SDMMC_SPI_INTERRUPT_SUPPORT_0
+#define SDMMC5_FIRST_REG 0x00fc // SDMMC_SLOT_INTERRUPT_STATUS_0
+#define SDMMC5_LAST_REG 0x0120 // SDMMC_VENDOR_OBS_BUS_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARSDMMC_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arslink.h b/arch/arm/mach-tegra/nv/include/ap20/arslink.h
new file mode 100644
index 000000000000..cfd1ef7eed24
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arslink.h
@@ -0,0 +1,1125 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARSLINK_H_INC_
+#define ___ARSLINK_H_INC_
+
+// Register SLINK_COMMAND_0  
+#define SLINK_COMMAND_0                 _MK_ADDR_CONST(0x0)
+#define SLINK_COMMAND_0_SECURE                  0x0
+#define SLINK_COMMAND_0_WORD_COUNT                      0x1
+#define SLINK_COMMAND_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_RESET_MASK                      _MK_MASK_CONST(0xf3f33fff)
+#define SLINK_COMMAND_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_READ_MASK                       _MK_MASK_CONST(0xf3f33fff)
+#define SLINK_COMMAND_0_WRITE_MASK                      _MK_MASK_CONST(0xf3f33fff)
+// RD/WD access to Data Register would start the next  transfer. (This allows continuous Receive via RD of Buffer and Automated  Transmit per WD of Buffer Register)
+#define SLINK_COMMAND_0_ENB_SHIFT                       _MK_SHIFT_CONST(31)
+#define SLINK_COMMAND_0_ENB_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_ENB_SHIFT)
+#define SLINK_COMMAND_0_ENB_RANGE                       31:31
+#define SLINK_COMMAND_0_ENB_WOFFSET                     0x0
+#define SLINK_COMMAND_0_ENB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_ENB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_ENB_DISABLE                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_ENB_ENABLE                      _MK_ENUM_CONST(1)
+
+// Program 1 after all the other bits in the COMMAND2 and COMMAND are programmed to start the trasnfer
+// HW clears this bit automatically after the trasnfer is done
+// Clearing of the bit by SW will stop the Shifter  and latch the partial data into buffer
+#define SLINK_COMMAND_0_GO_SHIFT                        _MK_SHIFT_CONST(30)
+#define SLINK_COMMAND_0_GO_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_GO_SHIFT)
+#define SLINK_COMMAND_0_GO_RANGE                        30:30
+#define SLINK_COMMAND_0_GO_WOFFSET                      0x0
+#define SLINK_COMMAND_0_GO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_GO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_GO_STOP                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_GO_GO                   _MK_ENUM_CONST(1)
+
+//  1 = Hold APB Cycle from writing another data into COMMAND register until RDY 0  = NOP. Use of this bit is deprecated.
+#define SLINK_COMMAND_0_WAIT_SHIFT                      _MK_SHIFT_CONST(29)
+#define SLINK_COMMAND_0_WAIT_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_WAIT_SHIFT)
+#define SLINK_COMMAND_0_WAIT_RANGE                      29:29
+#define SLINK_COMMAND_0_WAIT_WOFFSET                    0x0
+#define SLINK_COMMAND_0_WAIT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_WAIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WAIT_NOP                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_WAIT_WAIT                       _MK_ENUM_CONST(1)
+
+// 1 = Master Mode (internal Clock) 0 = Slave Mode  (external Clock)
+#define SLINK_COMMAND_0_M_S_SHIFT                       _MK_SHIFT_CONST(28)
+#define SLINK_COMMAND_0_M_S_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_M_S_SHIFT)
+#define SLINK_COMMAND_0_M_S_RANGE                       28:28
+#define SLINK_COMMAND_0_M_S_WOFFSET                     0x0
+#define SLINK_COMMAND_0_M_S_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_M_S_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_M_S_SLAVE                       _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_M_S_MASTER                      _MK_ENUM_CONST(1)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High 00 =  Driven Low (def)
+#define SLINK_COMMAND_0_IDLE_SCLK_SHIFT                 _MK_SHIFT_CONST(24)
+#define SLINK_COMMAND_0_IDLE_SCLK_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_IDLE_SCLK_SHIFT)
+#define SLINK_COMMAND_0_IDLE_SCLK_RANGE                 25:24
+#define SLINK_COMMAND_0_IDLE_SCLK_WOFFSET                       0x0
+#define SLINK_COMMAND_0_IDLE_SCLK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_IDLE_SCLK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DRIVE_LOW                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_IDLE_SCLK_DRIVE_HIGH                    _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_IDLE_SCLK_PULL_LOW                      _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_IDLE_SCLK_PULL_HIGH                     _MK_ENUM_CONST(3)
+
+//  1 = CS3 active high  0  = CS3 active low
+#define SLINK_COMMAND_0_CS_POLARITY3_SHIFT                      _MK_SHIFT_CONST(23)
+#define SLINK_COMMAND_0_CS_POLARITY3_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_POLARITY3_SHIFT)
+#define SLINK_COMMAND_0_CS_POLARITY3_RANGE                      23:23
+#define SLINK_COMMAND_0_CS_POLARITY3_WOFFSET                    0x0
+#define SLINK_COMMAND_0_CS_POLARITY3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_POLARITY3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY3_LOW                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_POLARITY3_HIGH                       _MK_ENUM_CONST(1)
+
+//  1 = CS2 active high  0  = CS2 active low
+#define SLINK_COMMAND_0_CS_POLARITY2_SHIFT                      _MK_SHIFT_CONST(22)
+#define SLINK_COMMAND_0_CS_POLARITY2_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_POLARITY2_SHIFT)
+#define SLINK_COMMAND_0_CS_POLARITY2_RANGE                      22:22
+#define SLINK_COMMAND_0_CS_POLARITY2_WOFFSET                    0x0
+#define SLINK_COMMAND_0_CS_POLARITY2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_POLARITY2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY2_LOW                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_POLARITY2_HIGH                       _MK_ENUM_CONST(1)
+
+//  1 = Rising Edge 0 =  Falling Edge (def)
+#define SLINK_COMMAND_0_CK_SDA_SHIFT                    _MK_SHIFT_CONST(21)
+#define SLINK_COMMAND_0_CK_SDA_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CK_SDA_SHIFT)
+#define SLINK_COMMAND_0_CK_SDA_RANGE                    21:21
+#define SLINK_COMMAND_0_CK_SDA_WOFFSET                  0x0
+#define SLINK_COMMAND_0_CK_SDA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CK_SDA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CK_SDA_FIRST_CLK_EDGE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CK_SDA_SECOND_CLK_EDGE                  _MK_ENUM_CONST(1)
+
+//  1 = CS1 active high  0  = CS1 active low
+#define SLINK_COMMAND_0_CS_POLARITY1_SHIFT                      _MK_SHIFT_CONST(20)
+#define SLINK_COMMAND_0_CS_POLARITY1_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_POLARITY1_SHIFT)
+#define SLINK_COMMAND_0_CS_POLARITY1_RANGE                      20:20
+#define SLINK_COMMAND_0_CS_POLARITY1_WOFFSET                    0x0
+#define SLINK_COMMAND_0_CS_POLARITY1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_POLARITY1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY1_LOW                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_POLARITY1_HIGH                       _MK_ENUM_CONST(1)
+
+// 11 = Pull High 10 = Pull Low 01 = Driven High 00  = Driven Low
+#define SLINK_COMMAND_0_IDLE_SDA_SHIFT                  _MK_SHIFT_CONST(16)
+#define SLINK_COMMAND_0_IDLE_SDA_FIELD                  (_MK_MASK_CONST(0x3) << SLINK_COMMAND_0_IDLE_SDA_SHIFT)
+#define SLINK_COMMAND_0_IDLE_SDA_RANGE                  17:16
+#define SLINK_COMMAND_0_IDLE_SDA_WOFFSET                        0x0
+#define SLINK_COMMAND_0_IDLE_SDA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND_0_IDLE_SDA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_IDLE_SDA_DRIVE_LOW                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_IDLE_SDA_DRIVE_HIGH                     _MK_ENUM_CONST(1)
+#define SLINK_COMMAND_0_IDLE_SDA_PULL_LOW                       _MK_ENUM_CONST(2)
+#define SLINK_COMMAND_0_IDLE_SDA_PULL_HIGH                      _MK_ENUM_CONST(3)
+
+//  1 = CS0 active high  0  = CS0 active low
+#define SLINK_COMMAND_0_CS_POLARITY0_SHIFT                      _MK_SHIFT_CONST(13)
+#define SLINK_COMMAND_0_CS_POLARITY0_FIELD                      (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_POLARITY0_SHIFT)
+#define SLINK_COMMAND_0_CS_POLARITY0_RANGE                      13:13
+#define SLINK_COMMAND_0_CS_POLARITY0_WOFFSET                    0x0
+#define SLINK_COMMAND_0_CS_POLARITY0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_POLARITY0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_POLARITY0_LOW                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_POLARITY0_HIGH                       _MK_ENUM_CONST(1)
+
+//  1 = CS is high  0  = CS is low  
+#define SLINK_COMMAND_0_CS_VALUE_SHIFT                  _MK_SHIFT_CONST(12)
+#define SLINK_COMMAND_0_CS_VALUE_FIELD                  (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_VALUE_SHIFT)
+#define SLINK_COMMAND_0_CS_VALUE_RANGE                  12:12
+#define SLINK_COMMAND_0_CS_VALUE_WOFFSET                        0x0
+#define SLINK_COMMAND_0_CS_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_VALUE_LOW                    _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_VALUE_HIGH                   _MK_ENUM_CONST(1)
+
+//  1 = CS controlled by SW   0  = CS controlled by hardware
+#define SLINK_COMMAND_0_CS_SW_SHIFT                     _MK_SHIFT_CONST(11)
+#define SLINK_COMMAND_0_CS_SW_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_CS_SW_SHIFT)
+#define SLINK_COMMAND_0_CS_SW_RANGE                     11:11
+#define SLINK_COMMAND_0_CS_SW_WOFFSET                   0x0
+#define SLINK_COMMAND_0_CS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_CS_SW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_CS_SW_HARD                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_CS_SW_SOFT                      _MK_ENUM_CONST(1)
+
+//  1 = both lines transmit/receive   0  = one line transmit and other receive 
+#define SLINK_COMMAND_0_BOTH_EN_SHIFT                   _MK_SHIFT_CONST(10)
+#define SLINK_COMMAND_0_BOTH_EN_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_COMMAND_0_BOTH_EN_SHIFT)
+#define SLINK_COMMAND_0_BOTH_EN_RANGE                   10:10
+#define SLINK_COMMAND_0_BOTH_EN_WOFFSET                 0x0
+#define SLINK_COMMAND_0_BOTH_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND_0_BOTH_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BOTH_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND_0_BOTH_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// 31 = Thirty Two words (Max)
+#define SLINK_COMMAND_0_WORD_SIZE_SHIFT                 _MK_SHIFT_CONST(5)
+#define SLINK_COMMAND_0_WORD_SIZE_FIELD                 (_MK_MASK_CONST(0x1f) << SLINK_COMMAND_0_WORD_SIZE_SHIFT)
+#define SLINK_COMMAND_0_WORD_SIZE_RANGE                 9:5
+#define SLINK_COMMAND_0_WORD_SIZE_WOFFSET                       0x0
+#define SLINK_COMMAND_0_WORD_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WORD_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND_0_WORD_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_WORD_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 31 = Thirty Two bit Transfers (Max)
+#define SLINK_COMMAND_0_BIT_LENGTH_SHIFT                        _MK_SHIFT_CONST(0)
+#define SLINK_COMMAND_0_BIT_LENGTH_FIELD                        (_MK_MASK_CONST(0x1f) << SLINK_COMMAND_0_BIT_LENGTH_SHIFT)
+#define SLINK_COMMAND_0_BIT_LENGTH_RANGE                        4:0
+#define SLINK_COMMAND_0_BIT_LENGTH_WOFFSET                      0x0
+#define SLINK_COMMAND_0_BIT_LENGTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BIT_LENGTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND_0_BIT_LENGTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND_0_BIT_LENGTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_COMMAND2_0  
+#define SLINK_COMMAND2_0                        _MK_ADDR_CONST(0x4)
+#define SLINK_COMMAND2_0_SECURE                         0x0
+#define SLINK_COMMAND2_0_WORD_COUNT                     0x1
+#define SLINK_COMMAND2_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RESET_MASK                     _MK_MASK_CONST(0xfcfe1fd3)
+#define SLINK_COMMAND2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_READ_MASK                      _MK_MASK_CONST(0xfcfe1fd3)
+#define SLINK_COMMAND2_0_WRITE_MASK                     _MK_MASK_CONST(0xfcfe1fd3)
+// Receive enable 
+#define SLINK_COMMAND2_0_RXEN_SHIFT                     _MK_SHIFT_CONST(31)
+#define SLINK_COMMAND2_0_RXEN_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_RXEN_SHIFT)
+#define SLINK_COMMAND2_0_RXEN_RANGE                     31:31
+#define SLINK_COMMAND2_0_RXEN_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_RXEN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_RXEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_RXEN_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_RXEN_ENABLE                    _MK_ENUM_CONST(1)
+
+// Transmit enable 
+#define SLINK_COMMAND2_0_TXEN_SHIFT                     _MK_SHIFT_CONST(30)
+#define SLINK_COMMAND2_0_TXEN_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_TXEN_SHIFT)
+#define SLINK_COMMAND2_0_TXEN_RANGE                     30:30
+#define SLINK_COMMAND2_0_TXEN_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_TXEN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_TXEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_TXEN_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_TXEN_ENABLE                    _MK_ENUM_CONST(1)
+
+//  1 = bi directional mode 0 = Normal mode
+#define SLINK_COMMAND2_0_SPC0_SHIFT                     _MK_SHIFT_CONST(29)
+#define SLINK_COMMAND2_0_SPC0_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SPC0_SHIFT)
+#define SLINK_COMMAND2_0_SPC0_RANGE                     29:29
+#define SLINK_COMMAND2_0_SPC0_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SPC0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SPC0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPC0_NORMAL                    _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SPC0_BIDIR                     _MK_ENUM_CONST(1)
+
+// number of cycles between two packs in the DMA. Use of this field is deprecated. Use INT_SIZE 8 = number of cycles between 2 packs (Max) 
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SHIFT                    _MK_SHIFT_CONST(26)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_FIELD                    (_MK_MASK_CONST(0x7) << SLINK_COMMAND2_0_WAIT_PACK_INT_SHIFT)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_RANGE                    28:26
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_WAIT_PACK_INT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of transfers the CS should stay low for word sizes more than 32.
+// This will enable to do the trasnfer of word sizes > 32 without using apb-dma
+// 0x00  For word_sizes 1 to 32
+// 0x01  For word_sizes 33 to 64
+// 0x10  For word sizes 65 to 96
+// 0x11  For word sizes 97 to 128
+#define SLINK_COMMAND2_0_FIFO_REFILLS_SHIFT                     _MK_SHIFT_CONST(22)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_FIELD                     (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_FIFO_REFILLS_SHIFT)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_RANGE                     23:22
+#define SLINK_COMMAND2_0_FIFO_REFILLS_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_FIFO_REFILLS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_REFILL0                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_REFILL1                   _MK_ENUM_CONST(1)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_REFILL2                   _MK_ENUM_CONST(2)
+#define SLINK_COMMAND2_0_FIFO_REFILLS_REFILL3                   _MK_ENUM_CONST(3)
+
+// number of cycles CS should stay inactive between packets 4 = number of cycles in setup for chip select (Max)   
+#define SLINK_COMMAND2_0_SS_SETUP_SHIFT                 _MK_SHIFT_CONST(20)
+#define SLINK_COMMAND2_0_SS_SETUP_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_SS_SETUP_SHIFT)
+#define SLINK_COMMAND2_0_SS_SETUP_RANGE                 21:20
+#define SLINK_COMMAND2_0_SS_SETUP_WOFFSET                       0x0
+#define SLINK_COMMAND2_0_SS_SETUP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_SETUP_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_SS_SETUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_SETUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 11 = chip select3 10 = chip select2 01 = chip select1 00 = chip select0(def)
+#define SLINK_COMMAND2_0_SS_EN_SHIFT                    _MK_SHIFT_CONST(18)
+#define SLINK_COMMAND2_0_SS_EN_FIELD                    (_MK_MASK_CONST(0x3) << SLINK_COMMAND2_0_SS_EN_SHIFT)
+#define SLINK_COMMAND2_0_SS_EN_RANGE                    19:18
+#define SLINK_COMMAND2_0_SS_EN_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_SS_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define SLINK_COMMAND2_0_SS_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SS_EN_CS0                      _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SS_EN_CS1                      _MK_ENUM_CONST(1)
+#define SLINK_COMMAND2_0_SS_EN_CS2                      _MK_ENUM_CONST(2)
+#define SLINK_COMMAND2_0_SS_EN_CS3                      _MK_ENUM_CONST(3)
+
+// 1 = CS active between two packets 0 = CS inactive between two packets
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_SHIFT                        _MK_SHIFT_CONST(17)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_SHIFT)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_RANGE                        17:17
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_WOFFSET                      0x0
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_LOW                  _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_CS_ACTIVE_BETWEEN_HIGH                 _MK_ENUM_CONST(1)
+
+// number of IDLE cycles between two packets
+// 31 = thirty two cycles between 2 packets
+#define SLINK_COMMAND2_0_INT_SIZE_SHIFT                 _MK_SHIFT_CONST(8)
+#define SLINK_COMMAND2_0_INT_SIZE_FIELD                 (_MK_MASK_CONST(0x1f) << SLINK_COMMAND2_0_INT_SIZE_SHIFT)
+#define SLINK_COMMAND2_0_INT_SIZE_RANGE                 12:8
+#define SLINK_COMMAND2_0_INT_SIZE_WOFFSET                       0x0
+#define SLINK_COMMAND2_0_INT_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_INT_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define SLINK_COMMAND2_0_INT_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_INT_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//  1 = Enable Modef   0 = Disable Modef (def)
+#define SLINK_COMMAND2_0_MODFEN_SHIFT                   _MK_SHIFT_CONST(7)
+#define SLINK_COMMAND2_0_MODFEN_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_MODFEN_SHIFT)
+#define SLINK_COMMAND2_0_MODFEN_RANGE                   7:7
+#define SLINK_COMMAND2_0_MODFEN_WOFFSET                 0x0
+#define SLINK_COMMAND2_0_MODFEN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_MODFEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_MODFEN_DISABLE                 _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_MODFEN_ENABLE                  _MK_ENUM_CONST(1)
+
+// When set to 1 SLINK uses only one data line (mosi/miso) for Tx and Rx depending on Master/Slave mode.
+// This has effect only when SPC0 is set to 1
+// 1 = Enable Output buffer 0 = Disable Output buffer (def)
+#define SLINK_COMMAND2_0_BIDIROE_SHIFT                  _MK_SHIFT_CONST(6)
+#define SLINK_COMMAND2_0_BIDIROE_FIELD                  (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_BIDIROE_SHIFT)
+#define SLINK_COMMAND2_0_BIDIROE_RANGE                  6:6
+#define SLINK_COMMAND2_0_BIDIROE_WOFFSET                        0x0
+#define SLINK_COMMAND2_0_BIDIROE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_BIDIROE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_BIDIROE_DISABLE                        _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_BIDIROE_ENABLE                 _MK_ENUM_CONST(1)
+
+// 1 = Enable SPIE interrupt 0 = Disable SPIE interrupt
+#define SLINK_COMMAND2_0_SPIE_SHIFT                     _MK_SHIFT_CONST(4)
+#define SLINK_COMMAND2_0_SPIE_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SPIE_SHIFT)
+#define SLINK_COMMAND2_0_SPIE_RANGE                     4:4
+#define SLINK_COMMAND2_0_SPIE_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SPIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SPIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SPIE_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SPIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// 1 = Enable 0 = Disable (def)
+#define SLINK_COMMAND2_0_SSOE_SHIFT                     _MK_SHIFT_CONST(1)
+#define SLINK_COMMAND2_0_SSOE_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_SSOE_SHIFT)
+#define SLINK_COMMAND2_0_SSOE_RANGE                     1:1
+#define SLINK_COMMAND2_0_SSOE_WOFFSET                   0x0
+#define SLINK_COMMAND2_0_SSOE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_SSOE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_SSOE_DISABLE                   _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_SSOE_ENABLE                    _MK_ENUM_CONST(1)
+
+//  1 = Transmit LSB first 0 = Transmit LSB last
+#define SLINK_COMMAND2_0_LSBFE_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_COMMAND2_0_LSBFE_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_COMMAND2_0_LSBFE_SHIFT)
+#define SLINK_COMMAND2_0_LSBFE_RANGE                    0:0
+#define SLINK_COMMAND2_0_LSBFE_WOFFSET                  0x0
+#define SLINK_COMMAND2_0_LSBFE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_COMMAND2_0_LSBFE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_COMMAND2_0_LSBFE_LAST                     _MK_ENUM_CONST(0)
+#define SLINK_COMMAND2_0_LSBFE_FIRST                    _MK_ENUM_CONST(1)
+
+
+// Register SLINK_STATUS_0  
+#define SLINK_STATUS_0                  _MK_ADDR_CONST(0x8)
+#define SLINK_STATUS_0_SECURE                   0x0
+#define SLINK_STATUS_0_WORD_COUNT                       0x1
+#define SLINK_STATUS_0_RESET_VAL                        _MK_MASK_CONST(0xa00000)
+#define SLINK_STATUS_0_RESET_MASK                       _MK_MASK_CONST(0xfffdffff)
+#define SLINK_STATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_READ_MASK                        _MK_MASK_CONST(0xfffdffff)
+#define SLINK_STATUS_0_WRITE_MASK                       _MK_MASK_CONST(0xfffdffff)
+//  1 = Controller is Busy 0 =  Controller is Free
+#define SLINK_STATUS_0_BSY_SHIFT                        _MK_SHIFT_CONST(31)
+#define SLINK_STATUS_0_BSY_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_BSY_SHIFT)
+#define SLINK_STATUS_0_BSY_RANGE                        31:31
+#define SLINK_STATUS_0_BSY_WOFFSET                      0x0
+#define SLINK_STATUS_0_BSY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_BSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BSY_IDLE                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_BSY_BUSY                 _MK_ENUM_CONST(1)
+
+// 1= contoller is Ready for transfer 0 = controller is Busy. Write 1 to clear the flag
+#define SLINK_STATUS_0_RDY_SHIFT                        _MK_SHIFT_CONST(30)
+#define SLINK_STATUS_0_RDY_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RDY_SHIFT)
+#define SLINK_STATUS_0_RDY_RANGE                        30:30
+#define SLINK_STATUS_0_RDY_WOFFSET                      0x0
+#define SLINK_STATUS_0_RDY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RDY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RDY_NOT_READY                    _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RDY_READY                        _MK_ENUM_CONST(1)
+
+// Will be set to 1 by HW when Errors such as Underflow/overflow occurs.Write 1 to clear the flag
+#define SLINK_STATUS_0_ERR_SHIFT                        _MK_SHIFT_CONST(29)
+#define SLINK_STATUS_0_ERR_FIELD                        (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_ERR_SHIFT)
+#define SLINK_STATUS_0_ERR_RANGE                        29:29
+#define SLINK_STATUS_0_ERR_WOFFSET                      0x0
+#define SLINK_STATUS_0_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_ERR_OK                   _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_ERR_ERROR                        _MK_ENUM_CONST(1)
+
+// SCLK input signal State
+#define SLINK_STATUS_0_SCLK_SHIFT                       _MK_SHIFT_CONST(28)
+#define SLINK_STATUS_0_SCLK_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_SCLK_SHIFT)
+#define SLINK_STATUS_0_SCLK_RANGE                       28:28
+#define SLINK_STATUS_0_SCLK_WOFFSET                     0x0
+#define SLINK_STATUS_0_SCLK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_SCLK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_SCLK_LOW                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_SCLK_HIGH                        _MK_ENUM_CONST(1)
+
+// Flush the RX FIFO
+#define SLINK_STATUS_0_RX_FLUSH_SHIFT                   _MK_SHIFT_CONST(27)
+#define SLINK_STATUS_0_RX_FLUSH_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_FLUSH_SHIFT)
+#define SLINK_STATUS_0_RX_FLUSH_RANGE                   27:27
+#define SLINK_STATUS_0_RX_FLUSH_WOFFSET                 0x0
+#define SLINK_STATUS_0_RX_FLUSH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_FLUSH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FLUSH_NOP                     _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_FLUSH_FLUSH                   _MK_ENUM_CONST(1)
+
+// Flush the TX FIFO
+#define SLINK_STATUS_0_TX_FLUSH_SHIFT                   _MK_SHIFT_CONST(26)
+#define SLINK_STATUS_0_TX_FLUSH_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_FLUSH_SHIFT)
+#define SLINK_STATUS_0_TX_FLUSH_RANGE                   26:26
+#define SLINK_STATUS_0_TX_FLUSH_WOFFSET                 0x0
+#define SLINK_STATUS_0_TX_FLUSH_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_FLUSH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FLUSH_NOP                     _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_FLUSH_FLUSH                   _MK_ENUM_CONST(1)
+
+// RX FIFO Overflow
+#define SLINK_STATUS_0_RX_OVF_SHIFT                     _MK_SHIFT_CONST(25)
+#define SLINK_STATUS_0_RX_OVF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_OVF_SHIFT)
+#define SLINK_STATUS_0_RX_OVF_RANGE                     25:25
+#define SLINK_STATUS_0_RX_OVF_WOFFSET                   0x0
+#define SLINK_STATUS_0_RX_OVF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_OVF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_OVF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_OVF_ERROR                     _MK_ENUM_CONST(1)
+
+// TX FIFO Underflow
+#define SLINK_STATUS_0_TX_UNF_SHIFT                     _MK_SHIFT_CONST(24)
+#define SLINK_STATUS_0_TX_UNF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_UNF_SHIFT)
+#define SLINK_STATUS_0_TX_UNF_RANGE                     24:24
+#define SLINK_STATUS_0_TX_UNF_WOFFSET                   0x0
+#define SLINK_STATUS_0_TX_UNF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_UNF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_UNF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_UNF_ERROR                     _MK_ENUM_CONST(1)
+
+// RX FIFO Empty
+#define SLINK_STATUS_0_RX_EMPTY_SHIFT                   _MK_SHIFT_CONST(23)
+#define SLINK_STATUS_0_RX_EMPTY_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_EMPTY_SHIFT)
+#define SLINK_STATUS_0_RX_EMPTY_RANGE                   23:23
+#define SLINK_STATUS_0_RX_EMPTY_WOFFSET                 0x0
+#define SLINK_STATUS_0_RX_EMPTY_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_EMPTY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_EMPTY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_EMPTY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_EMPTY_NOT_EMPTY                       _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_EMPTY_EMPTY                   _MK_ENUM_CONST(1)
+
+// RX FIFO Full
+#define SLINK_STATUS_0_RX_FULL_SHIFT                    _MK_SHIFT_CONST(22)
+#define SLINK_STATUS_0_RX_FULL_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_FULL_SHIFT)
+#define SLINK_STATUS_0_RX_FULL_RANGE                    22:22
+#define SLINK_STATUS_0_RX_FULL_WOFFSET                  0x0
+#define SLINK_STATUS_0_RX_FULL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_FULL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_FULL_NOT_FULL                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_FULL_FULL                     _MK_ENUM_CONST(1)
+
+// TX FIFO Empty
+#define SLINK_STATUS_0_TX_EMPTY_SHIFT                   _MK_SHIFT_CONST(21)
+#define SLINK_STATUS_0_TX_EMPTY_FIELD                   (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_EMPTY_SHIFT)
+#define SLINK_STATUS_0_TX_EMPTY_RANGE                   21:21
+#define SLINK_STATUS_0_TX_EMPTY_WOFFSET                 0x0
+#define SLINK_STATUS_0_TX_EMPTY_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_EMPTY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_EMPTY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_EMPTY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_EMPTY_NOT_EMPTY                       _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_EMPTY_EMPTY                   _MK_ENUM_CONST(1)
+
+// TX FIFO Full
+#define SLINK_STATUS_0_TX_FULL_SHIFT                    _MK_SHIFT_CONST(20)
+#define SLINK_STATUS_0_TX_FULL_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_FULL_SHIFT)
+#define SLINK_STATUS_0_TX_FULL_RANGE                    20:20
+#define SLINK_STATUS_0_TX_FULL_WOFFSET                  0x0
+#define SLINK_STATUS_0_TX_FULL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_FULL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_FULL_NOT_FULL                 _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_FULL_FULL                     _MK_ENUM_CONST(1)
+
+// TX FIFO Overflow
+#define SLINK_STATUS_0_TX_OVF_SHIFT                     _MK_SHIFT_CONST(19)
+#define SLINK_STATUS_0_TX_OVF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_TX_OVF_SHIFT)
+#define SLINK_STATUS_0_TX_OVF_RANGE                     19:19
+#define SLINK_STATUS_0_TX_OVF_WOFFSET                   0x0
+#define SLINK_STATUS_0_TX_OVF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_TX_OVF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_TX_OVF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_TX_OVF_ERROR                     _MK_ENUM_CONST(1)
+
+// RX FIFO Underflow
+#define SLINK_STATUS_0_RX_UNF_SHIFT                     _MK_SHIFT_CONST(18)
+#define SLINK_STATUS_0_RX_UNF_FIELD                     (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_RX_UNF_SHIFT)
+#define SLINK_STATUS_0_RX_UNF_RANGE                     18:18
+#define SLINK_STATUS_0_RX_UNF_WOFFSET                   0x0
+#define SLINK_STATUS_0_RX_UNF_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_RX_UNF_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_RX_UNF_OK                        _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_RX_UNF_ERROR                     _MK_ENUM_CONST(1)
+
+// Mode fault
+#define SLINK_STATUS_0_MODF_SHIFT                       _MK_SHIFT_CONST(16)
+#define SLINK_STATUS_0_MODF_FIELD                       (_MK_MASK_CONST(0x1) << SLINK_STATUS_0_MODF_SHIFT)
+#define SLINK_STATUS_0_MODF_RANGE                       16:16
+#define SLINK_STATUS_0_MODF_WOFFSET                     0x0
+#define SLINK_STATUS_0_MODF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SLINK_STATUS_0_MODF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_MODF_OK                  _MK_ENUM_CONST(0)
+#define SLINK_STATUS_0_MODF_ERROR                       _MK_ENUM_CONST(1)
+
+// number of blocks transferred (BLOCK count) during dma
+#define SLINK_STATUS_0_BLK_CNT_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_STATUS_0_BLK_CNT_FIELD                    (_MK_MASK_CONST(0xffff) << SLINK_STATUS_0_BLK_CNT_SHIFT)
+#define SLINK_STATUS_0_BLK_CNT_RANGE                    15:0
+#define SLINK_STATUS_0_BLK_CNT_WOFFSET                  0x0
+#define SLINK_STATUS_0_BLK_CNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BLK_CNT_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define SLINK_STATUS_0_BLK_CNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_BLK_CNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// In GO mode indicates number of words transferred (word count) 
+#define SLINK_STATUS_0_WORD_SHIFT                       _MK_SHIFT_CONST(5)
+#define SLINK_STATUS_0_WORD_FIELD                       (_MK_MASK_CONST(0x1f) << SLINK_STATUS_0_WORD_SHIFT)
+#define SLINK_STATUS_0_WORD_RANGE                       9:5
+#define SLINK_STATUS_0_WORD_WOFFSET                     0x0
+#define SLINK_STATUS_0_WORD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_WORD_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define SLINK_STATUS_0_WORD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_WORD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// In Go mode indicates mumber of bits trasnferred (bit count)
+#define SLINK_STATUS_0_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
+#define SLINK_STATUS_0_COUNT_FIELD                      (_MK_MASK_CONST(0x1f) << SLINK_STATUS_0_COUNT_SHIFT)
+#define SLINK_STATUS_0_COUNT_RANGE                      4:0
+#define SLINK_STATUS_0_COUNT_WOFFSET                    0x0
+#define SLINK_STATUS_0_COUNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_COUNT_DEFAULT_MASK                       _MK_MASK_CONST(0x1f)
+#define SLINK_STATUS_0_COUNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_STATUS_0_COUNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 12 [0xc] 
+
+// Register SLINK_MAS_DATA_0  
+#define SLINK_MAS_DATA_0                        _MK_ADDR_CONST(0x10)
+#define SLINK_MAS_DATA_0_SECURE                         0x0
+#define SLINK_MAS_DATA_0_WORD_COUNT                     0x1
+#define SLINK_MAS_DATA_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_FIELD                    (_MK_MASK_CONST(0xffffffff) << SLINK_MAS_DATA_0_MASTER_BUFFER_SHIFT)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_RANGE                    31:0
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_WOFFSET                  0x0
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_DEFAULT_MASK                     _MK_MASK_CONST(0xffffffff)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_MAS_DATA_0_MASTER_BUFFER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_SLAVE_DATA_0  
+#define SLINK_SLAVE_DATA_0                      _MK_ADDR_CONST(0x14)
+#define SLINK_SLAVE_DATA_0_SECURE                       0x0
+#define SLINK_SLAVE_DATA_0_WORD_COUNT                   0x1
+#define SLINK_SLAVE_DATA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SHIFT                   _MK_SHIFT_CONST(0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_FIELD                   (_MK_MASK_CONST(0xffffffff) << SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SHIFT)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_RANGE                   31:0
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_WOFFSET                 0x0
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_DEFAULT_MASK                    _MK_MASK_CONST(0xffffffff)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_SLAVE_DATA_0_SLAVE_BUFFER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_DMA_CTL_0  
+#define SLINK_DMA_CTL_0                 _MK_ADDR_CONST(0x18)
+#define SLINK_DMA_CTL_0_SECURE                  0x0
+#define SLINK_DMA_CTL_0_WORD_COUNT                      0x1
+#define SLINK_DMA_CTL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RESET_MASK                      _MK_MASK_CONST(0x8c7fffff)
+#define SLINK_DMA_CTL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_READ_MASK                       _MK_MASK_CONST(0x8c7fffff)
+#define SLINK_DMA_CTL_0_WRITE_MASK                      _MK_MASK_CONST(0x8c7fffff)
+//  1 = DMA mode is enabled, 0 = DMA disabled
+#define SLINK_DMA_CTL_0_DMA_EN_SHIFT                    _MK_SHIFT_CONST(31)
+#define SLINK_DMA_CTL_0_DMA_EN_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_DMA_EN_SHIFT)
+#define SLINK_DMA_CTL_0_DMA_EN_RANGE                    31:31
+#define SLINK_DMA_CTL_0_DMA_EN_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_DMA_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_DMA_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_DMA_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupt enable on receive completion.
+// 1 = Enable interrupt generation at the end of a receive transfer.
+// 0 = Disable interrupt generation for receive.
+#define SLINK_DMA_CTL_0_IE_RXC_SHIFT                    _MK_SHIFT_CONST(27)
+#define SLINK_DMA_CTL_0_IE_RXC_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_IE_RXC_SHIFT)
+#define SLINK_DMA_CTL_0_IE_RXC_RANGE                    27:27
+#define SLINK_DMA_CTL_0_IE_RXC_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_IE_RXC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_IE_RXC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_RXC_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_IE_RXC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Interrupt enable on transmit completion.
+// 1 = Enable interrupt generation at the end of a transmit transfer.
+// 0 = Disable interrupt generation for transmit.
+#define SLINK_DMA_CTL_0_IE_TXC_SHIFT                    _MK_SHIFT_CONST(26)
+#define SLINK_DMA_CTL_0_IE_TXC_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_IE_TXC_SHIFT)
+#define SLINK_DMA_CTL_0_IE_TXC_RANGE                    26:26
+#define SLINK_DMA_CTL_0_IE_TXC_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_IE_TXC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_IE_TXC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_IE_TXC_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_IE_TXC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Specifies the packet size during the DMA mode
+//             00      = 4 bits in a pack
+//           01      = 8bits in a pack
+//            10      = 16 in a pack
+//               10      = 32 in a pack
+#define SLINK_DMA_CTL_0_PACK_SIZE_SHIFT                 _MK_SHIFT_CONST(21)
+#define SLINK_DMA_CTL_0_PACK_SIZE_FIELD                 (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_PACK_SIZE_SHIFT)
+#define SLINK_DMA_CTL_0_PACK_SIZE_RANGE                 22:21
+#define SLINK_DMA_CTL_0_PACK_SIZE_WOFFSET                       0x0
+#define SLINK_DMA_CTL_0_PACK_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_PACK_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK4                 _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK8                 _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK16                        _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_PACK_SIZE_PACK32                        _MK_ENUM_CONST(3)
+
+// Packed mode enable bit.
+//  1 = Packed mode is enabled. This is only valid if BIT_LENGTH in SBCX_COMMAND register is set to 3, 7, 15 or 31
+// When enabled, all 32-bits of data in the FIFO contains valid
+// data packets of either 8-bit or 16-bit length.
+// 0 = Packed mode is disabled.
+#define SLINK_DMA_CTL_0_PACKED_SHIFT                    _MK_SHIFT_CONST(20)
+#define SLINK_DMA_CTL_0_PACKED_FIELD                    (_MK_MASK_CONST(0x1) << SLINK_DMA_CTL_0_PACKED_SHIFT)
+#define SLINK_DMA_CTL_0_PACKED_RANGE                    20:20
+#define SLINK_DMA_CTL_0_PACKED_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_PACKED_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SLINK_DMA_CTL_0_PACKED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_PACKED_DISABLE                  _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_PACKED_ENABLE                   _MK_ENUM_CONST(1)
+
+// Receive FIFO trigger level.
+// 00: 1 word. DMA trigger is asserted whenever there is at least 1 word in the RX FIFO.
+// 01: 4 word. DMA trigger is asserted when there are at least 4 words in the RX FIFO.
+// 10: 8 word. DMA trigger is asserted when there are at least 8 words in the RX FIFO.
+// 11: 16 word. DMA trigger is asserted when there are at least 16 words in the RX FIFO.
+#define SLINK_DMA_CTL_0_RX_TRIG_SHIFT                   _MK_SHIFT_CONST(18)
+#define SLINK_DMA_CTL_0_RX_TRIG_FIELD                   (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_RX_TRIG_SHIFT)
+#define SLINK_DMA_CTL_0_RX_TRIG_RANGE                   19:18
+#define SLINK_DMA_CTL_0_RX_TRIG_WOFFSET                 0x0
+#define SLINK_DMA_CTL_0_RX_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_RX_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG1                   _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG4                   _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG8                   _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_RX_TRIG_TRIG16                  _MK_ENUM_CONST(3)
+
+// Transmit FIFO trigger level.
+// 00: 1 word. DMA trigger is asserted whenever there is at least 1 word in the TX FIFO.
+// 01: 4 word. DMA trigger is asserted when there are at least 4 words in the TX FIFO.
+// 10: 8 word. DMA trigger is asserted when there are at least 8 words in the TX FIFO.
+// 11: 16 word. DMA trigger is asserted when there are at least 16 words in the TX FIFO.
+#define SLINK_DMA_CTL_0_TX_TRIG_SHIFT                   _MK_SHIFT_CONST(16)
+#define SLINK_DMA_CTL_0_TX_TRIG_FIELD                   (_MK_MASK_CONST(0x3) << SLINK_DMA_CTL_0_TX_TRIG_SHIFT)
+#define SLINK_DMA_CTL_0_TX_TRIG_RANGE                   17:16
+#define SLINK_DMA_CTL_0_TX_TRIG_WOFFSET                 0x0
+#define SLINK_DMA_CTL_0_TX_TRIG_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define SLINK_DMA_CTL_0_TX_TRIG_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG1                   _MK_ENUM_CONST(0)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG4                   _MK_ENUM_CONST(1)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG8                   _MK_ENUM_CONST(2)
+#define SLINK_DMA_CTL_0_TX_TRIG_TRIG16                  _MK_ENUM_CONST(3)
+
+// N = N+1 packets
+// number of packets should be aligned in the packed mode trasnfers.
+// packed mode     --> Number of packets
+//    3                                        multiple of 8
+//    7                                   multiple of 4
+//    15                          multiple of 2
+//    31                          from 0 to N
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT                    _MK_SHIFT_CONST(0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_FIELD                    (_MK_MASK_CONST(0xffff) << SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SHIFT)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_RANGE                    15:0
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_WOFFSET                  0x0
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SLINK_DMA_CTL_0_DMA_BLOCK_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register SLINK_STATUS2_0  
+#define SLINK_STATUS2_0                 _MK_ADDR_CONST(0x1c)
+#define SLINK_STATUS2_0_SECURE                  0x0
+#define SLINK_STATUS2_0_WORD_COUNT                      0x1
+#define SLINK_STATUS2_0_RESET_VAL                       _MK_MASK_CONST(0x20)
+#define SLINK_STATUS2_0_RESET_MASK                      _MK_MASK_CONST(0x3f003f)
+#define SLINK_STATUS2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_STATUS2_0_READ_MASK                       _MK_MASK_CONST(0x3f003f)
+#define SLINK_STATUS2_0_WRITE_MASK                      _MK_MASK_CONST(0x3f003f)
+// Indicates the number of words in the receive FIFO 
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_SHIFT                        _MK_SHIFT_CONST(16)
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_FIELD                        (_MK_MASK_CONST(0x3f) << SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_SHIFT)
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_RANGE                        21:16
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_WOFFSET                      0x0
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SLINK_STATUS2_0_RX_FIFO_FULL_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Indicates the number of empty slots in the transmit FIFO 
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_FIELD                       (_MK_MASK_CONST(0x3f) << SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_SHIFT)
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_RANGE                       5:0
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_WOFFSET                     0x0
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_DEFAULT                     _MK_MASK_CONST(0x20)
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SLINK_STATUS2_0_TX_FIFO_EMPTY_COUNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Reserved address 32 [0x20] 
+
+// Reserved address 36 [0x24] 
+
+// Reserved address 40 [0x28] 
+
+// Reserved address 44 [0x2c] 
+
+// Reserved address 48 [0x30] 
+
+// Reserved address 52 [0x34] 
+
+// Reserved address 56 [0x38] 
+
+// Reserved address 60 [0x3c] 
+
+// Reserved address 64 [0x40] 
+
+// Reserved address 68 [0x44] 
+
+// Reserved address 72 [0x48] 
+
+// Reserved address 76 [0x4c] 
+
+// Reserved address 80 [0x50] 
+
+// Reserved address 84 [0x54] 
+
+// Reserved address 88 [0x58] 
+
+// Reserved address 92 [0x5c] 
+
+// Reserved address 96 [0x60] 
+
+// Reserved address 100 [0x64] 
+
+// Reserved address 104 [0x68] 
+
+// Reserved address 108 [0x6c] 
+
+// Reserved address 112 [0x70] 
+
+// Reserved address 116 [0x74] 
+
+// Reserved address 120 [0x78] 
+
+// Reserved address 124 [0x7c] 
+
+// Reserved address 128 [0x80] 
+
+// Reserved address 132 [0x84] 
+
+// Reserved address 136 [0x88] 
+
+// Reserved address 140 [0x8c] 
+
+// Reserved address 144 [0x90] 
+
+// Reserved address 148 [0x94] 
+
+// Reserved address 152 [0x98] 
+
+// Reserved address 156 [0x9c] 
+
+// Reserved address 160 [0xa0] 
+
+// Reserved address 164 [0xa4] 
+
+// Reserved address 168 [0xa8] 
+
+// Reserved address 172 [0xac] 
+
+// Reserved address 176 [0xb0] 
+
+// Reserved address 180 [0xb4] 
+
+// Reserved address 184 [0xb8] 
+
+// Reserved address 188 [0xbc] 
+
+// Reserved address 192 [0xc0] 
+
+// Reserved address 196 [0xc4] 
+
+// Reserved address 200 [0xc8] 
+
+// Reserved address 204 [0xcc] 
+
+// Reserved address 208 [0xd0] 
+
+// Reserved address 212 [0xd4] 
+
+// Reserved address 216 [0xd8] 
+
+// Reserved address 220 [0xdc] 
+
+// Reserved address 224 [0xe0] 
+
+// Reserved address 228 [0xe4] 
+
+// Reserved address 232 [0xe8] 
+
+// Reserved address 236 [0xec] 
+
+// Reserved address 240 [0xf0] 
+
+// Reserved address 244 [0xf4] 
+
+// Reserved address 248 [0xf8] 
+
+// Reserved address 252 [0xfc] 
+
+// Register SLINK_TX_FIFO_0  
+#define SLINK_TX_FIFO_0                 _MK_ADDR_CONST(0x100)
+#define SLINK_TX_FIFO_0_SECURE                  0x0
+#define SLINK_TX_FIFO_0_WORD_COUNT                      0x1
+#define SLINK_TX_FIFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT                  _MK_SHIFT_CONST(0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_FIELD                  (_MK_MASK_CONST(0xffffffff) << SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_RANGE                  31:0
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_WOFFSET                        0x0
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 260 [0x104] 
+
+// Reserved address 264 [0x108] 
+
+// Reserved address 268 [0x10c] 
+
+// Reserved address 272 [0x110] 
+
+// Reserved address 276 [0x114] 
+
+// Reserved address 280 [0x118] 
+
+// Reserved address 284 [0x11c] 
+
+// Reserved address 288 [0x120] 
+
+// Reserved address 292 [0x124] 
+
+// Reserved address 296 [0x128] 
+
+// Reserved address 300 [0x12c] 
+
+// Reserved address 304 [0x130] 
+
+// Reserved address 308 [0x134] 
+
+// Reserved address 312 [0x138] 
+
+// Reserved address 316 [0x13c] 
+
+// Reserved address 320 [0x140] 
+
+// Reserved address 324 [0x144] 
+
+// Reserved address 328 [0x148] 
+
+// Reserved address 332 [0x14c] 
+
+// Reserved address 336 [0x150] 
+
+// Reserved address 340 [0x154] 
+
+// Reserved address 344 [0x158] 
+
+// Reserved address 348 [0x15c] 
+
+// Reserved address 352 [0x160] 
+
+// Reserved address 356 [0x164] 
+
+// Reserved address 360 [0x168] 
+
+// Reserved address 364 [0x16c] 
+
+// Reserved address 368 [0x170] 
+
+// Reserved address 372 [0x174] 
+
+// Reserved address 376 [0x178] 
+
+// Reserved address 380 [0x17c] 
+
+// Register SLINK_RX_FIFO_0  
+#define SLINK_RX_FIFO_0                 _MK_ADDR_CONST(0x180)
+#define SLINK_RX_FIFO_0_SECURE                  0x0
+#define SLINK_RX_FIFO_0_WORD_COUNT                      0x1
+#define SLINK_RX_FIFO_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Tx/Rx Shift Pattern
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT                  _MK_SHIFT_CONST(0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_FIELD                  (_MK_MASK_CONST(0xffffffff) << SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_RANGE                  31:0
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_WOFFSET                        0x0
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SLINK_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSLINK_REGS(_op_) \
+_op_(SLINK_COMMAND_0) \
+_op_(SLINK_COMMAND2_0) \
+_op_(SLINK_STATUS_0) \
+_op_(SLINK_MAS_DATA_0) \
+_op_(SLINK_SLAVE_DATA_0) \
+_op_(SLINK_DMA_CTL_0) \
+_op_(SLINK_STATUS2_0) \
+_op_(SLINK_TX_FIFO_0) \
+_op_(SLINK_RX_FIFO_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_SLINK      0x00000000
+
+//
+// ARSLINK REGISTER BANKS
+//
+
+#define SLINK0_FIRST_REG 0x0000 // SLINK_COMMAND_0
+#define SLINK0_LAST_REG 0x0008 // SLINK_STATUS_0
+#define SLINK1_FIRST_REG 0x0010 // SLINK_MAS_DATA_0
+#define SLINK1_LAST_REG 0x001c // SLINK_STATUS2_0
+#define SLINK2_FIRST_REG 0x0100 // SLINK_TX_FIFO_0
+#define SLINK2_LAST_REG 0x0100 // SLINK_TX_FIFO_0
+#define SLINK3_FIRST_REG 0x0180 // SLINK_RX_FIFO_0
+#define SLINK3_LAST_REG 0x0180 // SLINK_RX_FIFO_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARSLINK_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arsnor.h b/arch/arm/mach-tegra/nv/include/ap20/arsnor.h
new file mode 100644
index 000000000000..b583c6c996a7
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arsnor.h
@@ -0,0 +1,893 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARSNOR_H_INC_
+#define ___ARSNOR_H_INC_
+
+// Register SNOR_CONFIG_0  
+#define SNOR_CONFIG_0                   _MK_ADDR_CONST(0x0)
+#define SNOR_CONFIG_0_SECURE                    0x0
+#define SNOR_CONFIG_0_WORD_COUNT                        0x1
+#define SNOR_CONFIG_0_RESET_VAL                         _MK_MASK_CONST(0x10800000)
+#define SNOR_CONFIG_0_RESET_MASK                        _MK_MASK_CONST(0xfdf887ff)
+#define SNOR_CONFIG_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_READ_MASK                         _MK_MASK_CONST(0xfdf887ff)
+#define SNOR_CONFIG_0_WRITE_MASK                        _MK_MASK_CONST(0xfdf887ff)
+// When set a NOR operation commences. 
+#define SNOR_CONFIG_0_GO_NOR_SHIFT                      _MK_SHIFT_CONST(31)
+#define SNOR_CONFIG_0_GO_NOR_FIELD                      (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_GO_NOR_SHIFT)
+#define SNOR_CONFIG_0_GO_NOR_RANGE                      31:31
+#define SNOR_CONFIG_0_GO_NOR_WOFFSET                    0x0
+#define SNOR_CONFIG_0_GO_NOR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_GO_NOR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_GO_NOR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_GO_NOR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_GO_NOR_DISABLE                    _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_GO_NOR_ENABLE                     _MK_ENUM_CONST(1)
+
+// NOR Device DataBus width Configuration Bit 0=16Bit, 1=32Bit. 
+#define SNOR_CONFIG_0_WORDWIDE_GMI_SHIFT                        _MK_SHIFT_CONST(30)
+#define SNOR_CONFIG_0_WORDWIDE_GMI_FIELD                        (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_WORDWIDE_GMI_SHIFT)
+#define SNOR_CONFIG_0_WORDWIDE_GMI_RANGE                        30:30
+#define SNOR_CONFIG_0_WORDWIDE_GMI_WOFFSET                      0x0
+#define SNOR_CONFIG_0_WORDWIDE_GMI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_WORDWIDE_GMI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_WORDWIDE_GMI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_WORDWIDE_GMI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_WORDWIDE_GMI_NOR16BIT                     _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_WORDWIDE_GMI_NOR32BIT                     _MK_ENUM_CONST(1)
+
+// External NOR Memory Type 0=SNOR, 1=MUXONENAND(simulation purpoes). 
+#define SNOR_CONFIG_0_NOR_DEVICE_TYPE_SHIFT                     _MK_SHIFT_CONST(29)
+#define SNOR_CONFIG_0_NOR_DEVICE_TYPE_FIELD                     (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_NOR_DEVICE_TYPE_SHIFT)
+#define SNOR_CONFIG_0_NOR_DEVICE_TYPE_RANGE                     29:29
+#define SNOR_CONFIG_0_NOR_DEVICE_TYPE_WOFFSET                   0x0
+#define SNOR_CONFIG_0_NOR_DEVICE_TYPE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_NOR_DEVICE_TYPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_NOR_DEVICE_TYPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_NOR_DEVICE_TYPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_NOR_DEVICE_TYPE_SNOR                      _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_NOR_DEVICE_TYPE_MUXONENAND                        _MK_ENUM_CONST(1)
+
+// NOR Device Address-Data Configuration Bit 0=NON-MUX Mode, 1=MUX Mode. 
+#define SNOR_CONFIG_0_MUXMODE_GMI_SHIFT                 _MK_SHIFT_CONST(28)
+#define SNOR_CONFIG_0_MUXMODE_GMI_FIELD                 (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_MUXMODE_GMI_SHIFT)
+#define SNOR_CONFIG_0_MUXMODE_GMI_RANGE                 28:28
+#define SNOR_CONFIG_0_MUXMODE_GMI_WOFFSET                       0x0
+#define SNOR_CONFIG_0_MUXMODE_GMI_DEFAULT                       _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_MUXMODE_GMI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_MUXMODE_GMI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_MUXMODE_GMI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_MUXMODE_GMI_AD_NONMUX                     _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_MUXMODE_GMI_AD_MUX                        _MK_ENUM_CONST(1)
+
+// Burst Length Types 00=Continuous Burst, 01=8 Words, 10=16 Words, 11=32 Words. 
+#define SNOR_CONFIG_0_BURST_LENGTH_SHIFT                        _MK_SHIFT_CONST(26)
+#define SNOR_CONFIG_0_BURST_LENGTH_FIELD                        (_MK_MASK_CONST(0x3) << SNOR_CONFIG_0_BURST_LENGTH_SHIFT)
+#define SNOR_CONFIG_0_BURST_LENGTH_RANGE                        27:26
+#define SNOR_CONFIG_0_BURST_LENGTH_WOFFSET                      0x0
+#define SNOR_CONFIG_0_BURST_LENGTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_BURST_LENGTH_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define SNOR_CONFIG_0_BURST_LENGTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_BURST_LENGTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_BURST_LENGTH_CNTBRST                      _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_BURST_LENGTH_BL8WORD                      _MK_ENUM_CONST(1)
+#define SNOR_CONFIG_0_BURST_LENGTH_BL16WORD                     _MK_ENUM_CONST(2)
+#define SNOR_CONFIG_0_BURST_LENGTH_BL32WORD                     _MK_ENUM_CONST(3)
+
+// Device RDY Active Status 0=With Data, 1=One Cycle Before Data. 
+#define SNOR_CONFIG_0_RDY_ACTIVE_SHIFT                  _MK_SHIFT_CONST(24)
+#define SNOR_CONFIG_0_RDY_ACTIVE_FIELD                  (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_RDY_ACTIVE_SHIFT)
+#define SNOR_CONFIG_0_RDY_ACTIVE_RANGE                  24:24
+#define SNOR_CONFIG_0_RDY_ACTIVE_WOFFSET                        0x0
+#define SNOR_CONFIG_0_RDY_ACTIVE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_RDY_ACTIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_RDY_ACTIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_RDY_ACTIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_RDY_ACTIVE_WITHDATA                       _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_RDY_ACTIVE_BEFOREDATA                     _MK_ENUM_CONST(1)
+
+// Ready signal polarity 0=Active low, 1=Active high. 
+#define SNOR_CONFIG_0_RDY_POLARITY_SHIFT                        _MK_SHIFT_CONST(23)
+#define SNOR_CONFIG_0_RDY_POLARITY_FIELD                        (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_RDY_POLARITY_SHIFT)
+#define SNOR_CONFIG_0_RDY_POLARITY_RANGE                        23:23
+#define SNOR_CONFIG_0_RDY_POLARITY_WOFFSET                      0x0
+#define SNOR_CONFIG_0_RDY_POLARITY_DEFAULT                      _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_RDY_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_RDY_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_RDY_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_RDY_POLARITY_RESV                 _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_RDY_POLARITY_HIGH                 _MK_ENUM_CONST(1)
+
+// ADV pulse polarity 0=Active low, 1=Active high. 
+#define SNOR_CONFIG_0_ADV_POLARITY_SHIFT                        _MK_SHIFT_CONST(22)
+#define SNOR_CONFIG_0_ADV_POLARITY_FIELD                        (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_ADV_POLARITY_SHIFT)
+#define SNOR_CONFIG_0_ADV_POLARITY_RANGE                        22:22
+#define SNOR_CONFIG_0_ADV_POLARITY_WOFFSET                      0x0
+#define SNOR_CONFIG_0_ADV_POLARITY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_ADV_POLARITY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_ADV_POLARITY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_ADV_POLARITY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_ADV_POLARITY_LOW                  _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_ADV_POLARITY_RESV                 _MK_ENUM_CONST(1)
+
+// OE/WE polarity 0=Active low, 1=Active high. 
+#define SNOR_CONFIG_0_OE_WE_POLARITY_SHIFT                      _MK_SHIFT_CONST(21)
+#define SNOR_CONFIG_0_OE_WE_POLARITY_FIELD                      (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_OE_WE_POLARITY_SHIFT)
+#define SNOR_CONFIG_0_OE_WE_POLARITY_RANGE                      21:21
+#define SNOR_CONFIG_0_OE_WE_POLARITY_WOFFSET                    0x0
+#define SNOR_CONFIG_0_OE_WE_POLARITY_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_OE_WE_POLARITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_OE_WE_POLARITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_OE_WE_POLARITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_OE_WE_POLARITY_LOW                        _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_OE_WE_POLARITY_RESV                       _MK_ENUM_CONST(1)
+
+// Chip Select polarity 0=Active low, 1=Active high. 
+#define SNOR_CONFIG_0_CS_POLARITY_SHIFT                 _MK_SHIFT_CONST(20)
+#define SNOR_CONFIG_0_CS_POLARITY_FIELD                 (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_CS_POLARITY_SHIFT)
+#define SNOR_CONFIG_0_CS_POLARITY_RANGE                 20:20
+#define SNOR_CONFIG_0_CS_POLARITY_WOFFSET                       0x0
+#define SNOR_CONFIG_0_CS_POLARITY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_CS_POLARITY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_CS_POLARITY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_CS_POLARITY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_CS_POLARITY_LOW                   _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_CS_POLARITY_RESV                  _MK_ENUM_CONST(1)
+
+// Indicates the Power Down Mode enable bit. 
+#define SNOR_CONFIG_0_NOR_DPD_SHIFT                     _MK_SHIFT_CONST(19)
+#define SNOR_CONFIG_0_NOR_DPD_FIELD                     (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_NOR_DPD_SHIFT)
+#define SNOR_CONFIG_0_NOR_DPD_RANGE                     19:19
+#define SNOR_CONFIG_0_NOR_DPD_WOFFSET                   0x0
+#define SNOR_CONFIG_0_NOR_DPD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_NOR_DPD_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_NOR_DPD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_NOR_DPD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_NOR_DPD_DISABLE                   _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_NOR_DPD_ENABLE                    _MK_ENUM_CONST(1)
+
+// Sets the NOR Write protect enable bit. 
+#define SNOR_CONFIG_0_NOR_WP_SHIFT                      _MK_SHIFT_CONST(15)
+#define SNOR_CONFIG_0_NOR_WP_FIELD                      (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_NOR_WP_SHIFT)
+#define SNOR_CONFIG_0_NOR_WP_RANGE                      15:15
+#define SNOR_CONFIG_0_NOR_WP_WOFFSET                    0x0
+#define SNOR_CONFIG_0_NOR_WP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_NOR_WP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_NOR_WP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_NOR_WP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_NOR_WP_DISABLE                    _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_NOR_WP_ENABLE                     _MK_ENUM_CONST(1)
+
+// Sets the number of words in a page if page mode is selected. 
+#define SNOR_CONFIG_0_PAGE_SIZE_SHIFT                   _MK_SHIFT_CONST(8)
+#define SNOR_CONFIG_0_PAGE_SIZE_FIELD                   (_MK_MASK_CONST(0x7) << SNOR_CONFIG_0_PAGE_SIZE_SHIFT)
+#define SNOR_CONFIG_0_PAGE_SIZE_RANGE                   10:8
+#define SNOR_CONFIG_0_PAGE_SIZE_WOFFSET                 0x0
+#define SNOR_CONFIG_0_PAGE_SIZE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_PAGE_SIZE_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define SNOR_CONFIG_0_PAGE_SIZE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_PAGE_SIZE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_PAGE_SIZE_BRST                    _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_PAGE_SIZE_PG4WORD                 _MK_ENUM_CONST(1)
+#define SNOR_CONFIG_0_PAGE_SIZE_PG8WORD                 _MK_ENUM_CONST(2)
+#define SNOR_CONFIG_0_PAGE_SIZE_PG16WORD                        _MK_ENUM_CONST(3)
+#define SNOR_CONFIG_0_PAGE_SIZE_RESV4                   _MK_ENUM_CONST(4)
+#define SNOR_CONFIG_0_PAGE_SIZE_RESV5                   _MK_ENUM_CONST(5)
+#define SNOR_CONFIG_0_PAGE_SIZE_RESV6                   _MK_ENUM_CONST(6)
+#define SNOR_CONFIG_0_PAGE_SIZE_RESV7                   _MK_ENUM_CONST(7)
+
+// Selection bit between Master DMA and Slave Interface. 
+#define SNOR_CONFIG_0_MST_ENB_SHIFT                     _MK_SHIFT_CONST(7)
+#define SNOR_CONFIG_0_MST_ENB_FIELD                     (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_MST_ENB_SHIFT)
+#define SNOR_CONFIG_0_MST_ENB_RANGE                     7:7
+#define SNOR_CONFIG_0_MST_ENB_WOFFSET                   0x0
+#define SNOR_CONFIG_0_MST_ENB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_MST_ENB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_MST_ENB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_MST_ENB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_MST_ENB_DISABLE                   _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_MST_ENB_ENABLE                    _MK_ENUM_CONST(1)
+
+// SNOR 8 chip selects combinations.
+#define SNOR_CONFIG_0_SNOR_SEL_SHIFT                    _MK_SHIFT_CONST(4)
+#define SNOR_CONFIG_0_SNOR_SEL_FIELD                    (_MK_MASK_CONST(0x7) << SNOR_CONFIG_0_SNOR_SEL_SHIFT)
+#define SNOR_CONFIG_0_SNOR_SEL_RANGE                    6:4
+#define SNOR_CONFIG_0_SNOR_SEL_WOFFSET                  0x0
+#define SNOR_CONFIG_0_SNOR_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_SNOR_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SNOR_CONFIG_0_SNOR_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_SNOR_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_SNOR_SEL_CS0                      _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_SNOR_SEL_CS1                      _MK_ENUM_CONST(1)
+#define SNOR_CONFIG_0_SNOR_SEL_CS2                      _MK_ENUM_CONST(2)
+#define SNOR_CONFIG_0_SNOR_SEL_CS3                      _MK_ENUM_CONST(3)
+#define SNOR_CONFIG_0_SNOR_SEL_CS4                      _MK_ENUM_CONST(4)
+#define SNOR_CONFIG_0_SNOR_SEL_CS5                      _MK_ENUM_CONST(5)
+#define SNOR_CONFIG_0_SNOR_SEL_CS6                      _MK_ENUM_CONST(6)
+#define SNOR_CONFIG_0_SNOR_SEL_CS7                      _MK_ENUM_CONST(7)
+
+// Indicates if the ADV gets asserted before CE. 
+#define SNOR_CONFIG_0_CE_LAST_SHIFT                     _MK_SHIFT_CONST(3)
+#define SNOR_CONFIG_0_CE_LAST_FIELD                     (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_CE_LAST_SHIFT)
+#define SNOR_CONFIG_0_CE_LAST_RANGE                     3:3
+#define SNOR_CONFIG_0_CE_LAST_WOFFSET                   0x0
+#define SNOR_CONFIG_0_CE_LAST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_CE_LAST_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_CE_LAST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_CE_LAST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_CE_LAST_DISABLE                   _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_CE_LAST_RESV                      _MK_ENUM_CONST(1)
+
+// Indicates if the CE gets asserted before ADV.
+#define SNOR_CONFIG_0_CE_FIRST_SHIFT                    _MK_SHIFT_CONST(2)
+#define SNOR_CONFIG_0_CE_FIRST_FIELD                    (_MK_MASK_CONST(0x1) << SNOR_CONFIG_0_CE_FIRST_SHIFT)
+#define SNOR_CONFIG_0_CE_FIRST_RANGE                    2:2
+#define SNOR_CONFIG_0_CE_FIRST_WOFFSET                  0x0
+#define SNOR_CONFIG_0_CE_FIRST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_CE_FIRST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define SNOR_CONFIG_0_CE_FIRST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_CE_FIRST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_CE_FIRST_DISABLE                  _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_CE_FIRST_RESV                     _MK_ENUM_CONST(1)
+
+// This field specifies the Mode of Operation for SYNC Memories.
+#define SNOR_CONFIG_0_DEVICE_MODE_SHIFT                 _MK_SHIFT_CONST(0)
+#define SNOR_CONFIG_0_DEVICE_MODE_FIELD                 (_MK_MASK_CONST(0x3) << SNOR_CONFIG_0_DEVICE_MODE_SHIFT)
+#define SNOR_CONFIG_0_DEVICE_MODE_RANGE                 1:0
+#define SNOR_CONFIG_0_DEVICE_MODE_WOFFSET                       0x0
+#define SNOR_CONFIG_0_DEVICE_MODE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_DEVICE_MODE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define SNOR_CONFIG_0_DEVICE_MODE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_DEVICE_MODE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SNOR_CONFIG_0_DEVICE_MODE_ASYNC                 _MK_ENUM_CONST(0)
+#define SNOR_CONFIG_0_DEVICE_MODE_PAGE                  _MK_ENUM_CONST(1)
+#define SNOR_CONFIG_0_DEVICE_MODE_BURST                 _MK_ENUM_CONST(2)
+#define SNOR_CONFIG_0_DEVICE_MODE_RESV                  _MK_ENUM_CONST(3)
+
+
+// Register SNOR_STA_0  
+#define SNOR_STA_0                      _MK_ADDR_CONST(0x4)
+#define SNOR_STA_0_SECURE                       0x0
+#define SNOR_STA_0_WORD_COUNT                   0x1
+#define SNOR_STA_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_RESET_MASK                   _MK_MASK_CONST(0x8ff0ffff)
+#define SNOR_STA_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_READ_MASK                    _MK_MASK_CONST(0x8ff0ffff)
+#define SNOR_STA_0_WRITE_MASK                   _MK_MASK_CONST(0xf000000)
+// Indicates that the device status. 
+#define SNOR_STA_0_DEVICE_BSY_SHIFT                     _MK_SHIFT_CONST(31)
+#define SNOR_STA_0_DEVICE_BSY_FIELD                     (_MK_MASK_CONST(0x1) << SNOR_STA_0_DEVICE_BSY_SHIFT)
+#define SNOR_STA_0_DEVICE_BSY_RANGE                     31:31
+#define SNOR_STA_0_DEVICE_BSY_WOFFSET                   0x0
+#define SNOR_STA_0_DEVICE_BSY_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DEVICE_BSY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SNOR_STA_0_DEVICE_BSY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DEVICE_BSY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Device Interrupt-2 from MuxOneNand Memory. 
+#define SNOR_STA_0_DEVICE_INTR_2_SHIFT                  _MK_SHIFT_CONST(27)
+#define SNOR_STA_0_DEVICE_INTR_2_FIELD                  (_MK_MASK_CONST(0x1) << SNOR_STA_0_DEVICE_INTR_2_SHIFT)
+#define SNOR_STA_0_DEVICE_INTR_2_RANGE                  27:27
+#define SNOR_STA_0_DEVICE_INTR_2_WOFFSET                        0x0
+#define SNOR_STA_0_DEVICE_INTR_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DEVICE_INTR_2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SNOR_STA_0_DEVICE_INTR_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DEVICE_INTR_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Device Interrupt-1 from MuxOneNand Memory. 
+#define SNOR_STA_0_DEVICE_INTR_1_SHIFT                  _MK_SHIFT_CONST(26)
+#define SNOR_STA_0_DEVICE_INTR_1_FIELD                  (_MK_MASK_CONST(0x1) << SNOR_STA_0_DEVICE_INTR_1_SHIFT)
+#define SNOR_STA_0_DEVICE_INTR_1_RANGE                  26:26
+#define SNOR_STA_0_DEVICE_INTR_1_WOFFSET                        0x0
+#define SNOR_STA_0_DEVICE_INTR_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DEVICE_INTR_1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SNOR_STA_0_DEVICE_INTR_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DEVICE_INTR_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Device Interrupt-2 Enable Bit. 
+#define SNOR_STA_0_DEVICE_INTR_2_ENB_SHIFT                      _MK_SHIFT_CONST(25)
+#define SNOR_STA_0_DEVICE_INTR_2_ENB_FIELD                      (_MK_MASK_CONST(0x1) << SNOR_STA_0_DEVICE_INTR_2_ENB_SHIFT)
+#define SNOR_STA_0_DEVICE_INTR_2_ENB_RANGE                      25:25
+#define SNOR_STA_0_DEVICE_INTR_2_ENB_WOFFSET                    0x0
+#define SNOR_STA_0_DEVICE_INTR_2_ENB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DEVICE_INTR_2_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SNOR_STA_0_DEVICE_INTR_2_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DEVICE_INTR_2_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Device Interrupt-1 Enable Bit. 
+#define SNOR_STA_0_DEVICE_INTR_1_ENB_SHIFT                      _MK_SHIFT_CONST(24)
+#define SNOR_STA_0_DEVICE_INTR_1_ENB_FIELD                      (_MK_MASK_CONST(0x1) << SNOR_STA_0_DEVICE_INTR_1_ENB_SHIFT)
+#define SNOR_STA_0_DEVICE_INTR_1_ENB_RANGE                      24:24
+#define SNOR_STA_0_DEVICE_INTR_1_ENB_WOFFSET                    0x0
+#define SNOR_STA_0_DEVICE_INTR_1_ENB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DEVICE_INTR_1_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define SNOR_STA_0_DEVICE_INTR_1_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DEVICE_INTR_1_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// SLV FIFO full status. 
+#define SNOR_STA_0_SLV_FIFO_FULL_SHIFT                  _MK_SHIFT_CONST(23)
+#define SNOR_STA_0_SLV_FIFO_FULL_FIELD                  (_MK_MASK_CONST(0x1) << SNOR_STA_0_SLV_FIFO_FULL_SHIFT)
+#define SNOR_STA_0_SLV_FIFO_FULL_RANGE                  23:23
+#define SNOR_STA_0_SLV_FIFO_FULL_WOFFSET                        0x0
+#define SNOR_STA_0_SLV_FIFO_FULL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_SLV_FIFO_FULL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SNOR_STA_0_SLV_FIFO_FULL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_SLV_FIFO_FULL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// SLV FIFO empty status. 
+#define SNOR_STA_0_SLV_FIFO_EMPTY_SHIFT                 _MK_SHIFT_CONST(22)
+#define SNOR_STA_0_SLV_FIFO_EMPTY_FIELD                 (_MK_MASK_CONST(0x1) << SNOR_STA_0_SLV_FIFO_EMPTY_SHIFT)
+#define SNOR_STA_0_SLV_FIFO_EMPTY_RANGE                 22:22
+#define SNOR_STA_0_SLV_FIFO_EMPTY_WOFFSET                       0x0
+#define SNOR_STA_0_SLV_FIFO_EMPTY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_SLV_FIFO_EMPTY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SNOR_STA_0_SLV_FIFO_EMPTY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_SLV_FIFO_EMPTY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// MST FIFO full status. 
+#define SNOR_STA_0_MST_FIFO_FULL_SHIFT                  _MK_SHIFT_CONST(21)
+#define SNOR_STA_0_MST_FIFO_FULL_FIELD                  (_MK_MASK_CONST(0x1) << SNOR_STA_0_MST_FIFO_FULL_SHIFT)
+#define SNOR_STA_0_MST_FIFO_FULL_RANGE                  21:21
+#define SNOR_STA_0_MST_FIFO_FULL_WOFFSET                        0x0
+#define SNOR_STA_0_MST_FIFO_FULL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_MST_FIFO_FULL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define SNOR_STA_0_MST_FIFO_FULL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_MST_FIFO_FULL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// MST FIFO empty status. 
+#define SNOR_STA_0_MST_FIFO_EMPTY_SHIFT                 _MK_SHIFT_CONST(20)
+#define SNOR_STA_0_MST_FIFO_EMPTY_FIELD                 (_MK_MASK_CONST(0x1) << SNOR_STA_0_MST_FIFO_EMPTY_SHIFT)
+#define SNOR_STA_0_MST_FIFO_EMPTY_RANGE                 20:20
+#define SNOR_STA_0_MST_FIFO_EMPTY_WOFFSET                       0x0
+#define SNOR_STA_0_MST_FIFO_EMPTY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_MST_FIFO_EMPTY_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define SNOR_STA_0_MST_FIFO_EMPTY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_MST_FIFO_EMPTY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Indicates the number of Data to be transfered; current dma_data_count.
+#define SNOR_STA_0_DMA_DATA_CNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define SNOR_STA_0_DMA_DATA_CNT_FIELD                   (_MK_MASK_CONST(0xffff) << SNOR_STA_0_DMA_DATA_CNT_SHIFT)
+#define SNOR_STA_0_DMA_DATA_CNT_RANGE                   15:0
+#define SNOR_STA_0_DMA_DATA_CNT_WOFFSET                 0x0
+#define SNOR_STA_0_DMA_DATA_CNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DMA_DATA_CNT_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define SNOR_STA_0_DMA_DATA_CNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_STA_0_DMA_DATA_CNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register SNOR_NOR_ADDR_PTR_0  
+#define SNOR_NOR_ADDR_PTR_0                     _MK_ADDR_CONST(0x8)
+#define SNOR_NOR_ADDR_PTR_0_SECURE                      0x0
+#define SNOR_NOR_ADDR_PTR_0_WORD_COUNT                  0x1
+#define SNOR_NOR_ADDR_PTR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define SNOR_NOR_ADDR_PTR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SNOR_NOR_ADDR_PTR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define SNOR_NOR_ADDR_PTR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SNOR_NOR_ADDR_PTR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SNOR_NOR_ADDR_PTR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Indicates that the NOR controller Address.
+#define SNOR_NOR_ADDR_PTR_0_SNOR_NOR_ADDR_PTR_SHIFT                     _MK_SHIFT_CONST(0)
+#define SNOR_NOR_ADDR_PTR_0_SNOR_NOR_ADDR_PTR_FIELD                     (_MK_MASK_CONST(0xffffffff) << SNOR_NOR_ADDR_PTR_0_SNOR_NOR_ADDR_PTR_SHIFT)
+#define SNOR_NOR_ADDR_PTR_0_SNOR_NOR_ADDR_PTR_RANGE                     31:0
+#define SNOR_NOR_ADDR_PTR_0_SNOR_NOR_ADDR_PTR_WOFFSET                   0x0
+#define SNOR_NOR_ADDR_PTR_0_SNOR_NOR_ADDR_PTR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_NOR_ADDR_PTR_0_SNOR_NOR_ADDR_PTR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SNOR_NOR_ADDR_PTR_0_SNOR_NOR_ADDR_PTR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_NOR_ADDR_PTR_0_SNOR_NOR_ADDR_PTR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register SNOR_AHB_ADDR_PTR_0  
+#define SNOR_AHB_ADDR_PTR_0                     _MK_ADDR_CONST(0xc)
+#define SNOR_AHB_ADDR_PTR_0_SECURE                      0x0
+#define SNOR_AHB_ADDR_PTR_0_WORD_COUNT                  0x1
+#define SNOR_AHB_ADDR_PTR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define SNOR_AHB_ADDR_PTR_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define SNOR_AHB_ADDR_PTR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define SNOR_AHB_ADDR_PTR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SNOR_AHB_ADDR_PTR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define SNOR_AHB_ADDR_PTR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Indicates that the AHB side Address.
+#define SNOR_AHB_ADDR_PTR_0_SNOR_AHB_ADDR_PTR_SHIFT                     _MK_SHIFT_CONST(0)
+#define SNOR_AHB_ADDR_PTR_0_SNOR_AHB_ADDR_PTR_FIELD                     (_MK_MASK_CONST(0xffffffff) << SNOR_AHB_ADDR_PTR_0_SNOR_AHB_ADDR_PTR_SHIFT)
+#define SNOR_AHB_ADDR_PTR_0_SNOR_AHB_ADDR_PTR_RANGE                     31:0
+#define SNOR_AHB_ADDR_PTR_0_SNOR_AHB_ADDR_PTR_WOFFSET                   0x0
+#define SNOR_AHB_ADDR_PTR_0_SNOR_AHB_ADDR_PTR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_AHB_ADDR_PTR_0_SNOR_AHB_ADDR_PTR_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define SNOR_AHB_ADDR_PTR_0_SNOR_AHB_ADDR_PTR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_AHB_ADDR_PTR_0_SNOR_AHB_ADDR_PTR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register SNOR_TIMING0_0  
+#define SNOR_TIMING0_0                  _MK_ADDR_CONST(0x10)
+#define SNOR_TIMING0_0_SECURE                   0x0
+#define SNOR_TIMING0_0_WORD_COUNT                       0x1
+#define SNOR_TIMING0_0_RESET_VAL                        _MK_MASK_CONST(0x30101114)
+#define SNOR_TIMING0_0_RESET_MASK                       _MK_MASK_CONST(0xf0f0ffff)
+#define SNOR_TIMING0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SNOR_TIMING0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SNOR_TIMING0_0_READ_MASK                        _MK_MASK_CONST(0xf0f0ffff)
+#define SNOR_TIMING0_0_WRITE_MASK                       _MK_MASK_CONST(0xf0f0ffff)
+// This represents the number of wait clock cycles from address to 1st data ready.
+#define SNOR_TIMING0_0_PAGE_RDY_WIDTH_SHIFT                     _MK_SHIFT_CONST(28)
+#define SNOR_TIMING0_0_PAGE_RDY_WIDTH_FIELD                     (_MK_MASK_CONST(0xf) << SNOR_TIMING0_0_PAGE_RDY_WIDTH_SHIFT)
+#define SNOR_TIMING0_0_PAGE_RDY_WIDTH_RANGE                     31:28
+#define SNOR_TIMING0_0_PAGE_RDY_WIDTH_WOFFSET                   0x0
+#define SNOR_TIMING0_0_PAGE_RDY_WIDTH_DEFAULT                   _MK_MASK_CONST(0x3)
+#define SNOR_TIMING0_0_PAGE_RDY_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define SNOR_TIMING0_0_PAGE_RDY_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_TIMING0_0_PAGE_RDY_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Page Sequential width indicates the delay cycle between the intra page Read access.
+#define SNOR_TIMING0_0_PAGE_SEQ_WIDTH_SHIFT                     _MK_SHIFT_CONST(20)
+#define SNOR_TIMING0_0_PAGE_SEQ_WIDTH_FIELD                     (_MK_MASK_CONST(0xf) << SNOR_TIMING0_0_PAGE_SEQ_WIDTH_SHIFT)
+#define SNOR_TIMING0_0_PAGE_SEQ_WIDTH_RANGE                     23:20
+#define SNOR_TIMING0_0_PAGE_SEQ_WIDTH_WOFFSET                   0x0
+#define SNOR_TIMING0_0_PAGE_SEQ_WIDTH_DEFAULT                   _MK_MASK_CONST(0x1)
+#define SNOR_TIMING0_0_PAGE_SEQ_WIDTH_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define SNOR_TIMING0_0_PAGE_SEQ_WIDTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_TIMING0_0_PAGE_SEQ_WIDTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Indicates in number of cycles MUX address/data asserted on the bus.
+#define SNOR_TIMING0_0_MUXED_WIDTH_SHIFT                        _MK_SHIFT_CONST(12)
+#define SNOR_TIMING0_0_MUXED_WIDTH_FIELD                        (_MK_MASK_CONST(0xf) << SNOR_TIMING0_0_MUXED_WIDTH_SHIFT)
+#define SNOR_TIMING0_0_MUXED_WIDTH_RANGE                        15:12
+#define SNOR_TIMING0_0_MUXED_WIDTH_WOFFSET                      0x0
+#define SNOR_TIMING0_0_MUXED_WIDTH_DEFAULT                      _MK_MASK_CONST(0x1)
+#define SNOR_TIMING0_0_MUXED_WIDTH_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define SNOR_TIMING0_0_MUXED_WIDTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_TIMING0_0_MUXED_WIDTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Indicates in number of cycles CE stays asserted after the de-assertion of WE_(in case of SLAVE/MASTER Request) or OE_(in case of MASTER Request).
+#define SNOR_TIMING0_0_HOLD_WIDTH_SHIFT                 _MK_SHIFT_CONST(8)
+#define SNOR_TIMING0_0_HOLD_WIDTH_FIELD                 (_MK_MASK_CONST(0xf) << SNOR_TIMING0_0_HOLD_WIDTH_SHIFT)
+#define SNOR_TIMING0_0_HOLD_WIDTH_RANGE                 11:8
+#define SNOR_TIMING0_0_HOLD_WIDTH_WOFFSET                       0x0
+#define SNOR_TIMING0_0_HOLD_WIDTH_DEFAULT                       _MK_MASK_CONST(0x1)
+#define SNOR_TIMING0_0_HOLD_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define SNOR_TIMING0_0_HOLD_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_TIMING0_0_HOLD_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Indicates the number of cycles during which ADV stays asserted. 
+#define SNOR_TIMING0_0_ADV_WIDTH_SHIFT                  _MK_SHIFT_CONST(4)
+#define SNOR_TIMING0_0_ADV_WIDTH_FIELD                  (_MK_MASK_CONST(0xf) << SNOR_TIMING0_0_ADV_WIDTH_SHIFT)
+#define SNOR_TIMING0_0_ADV_WIDTH_RANGE                  7:4
+#define SNOR_TIMING0_0_ADV_WIDTH_WOFFSET                        0x0
+#define SNOR_TIMING0_0_ADV_WIDTH_DEFAULT                        _MK_MASK_CONST(0x1)
+#define SNOR_TIMING0_0_ADV_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define SNOR_TIMING0_0_ADV_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SNOR_TIMING0_0_ADV_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Indicates the number of cycles before CE is asserted. 
+#define SNOR_TIMING0_0_CE_WIDTH_SHIFT                   _MK_SHIFT_CONST(0)
+#define SNOR_TIMING0_0_CE_WIDTH_FIELD                   (_MK_MASK_CONST(0xf) << SNOR_TIMING0_0_CE_WIDTH_SHIFT)
+#define SNOR_TIMING0_0_CE_WIDTH_RANGE                   3:0
+#define SNOR_TIMING0_0_CE_WIDTH_WOFFSET                 0x0
+#define SNOR_TIMING0_0_CE_WIDTH_DEFAULT                 _MK_MASK_CONST(0x4)
+#define SNOR_TIMING0_0_CE_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define SNOR_TIMING0_0_CE_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_TIMING0_0_CE_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register SNOR_TIMING1_0  
+#define SNOR_TIMING1_0                  _MK_ADDR_CONST(0x14)
+#define SNOR_TIMING1_0_SECURE                   0x0
+#define SNOR_TIMING1_0_WORD_COUNT                       0x1
+#define SNOR_TIMING1_0_RESET_VAL                        _MK_MASK_CONST(0x10103)
+#define SNOR_TIMING1_0_RESET_MASK                       _MK_MASK_CONST(0xffffff)
+#define SNOR_TIMING1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SNOR_TIMING1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SNOR_TIMING1_0_READ_MASK                        _MK_MASK_CONST(0xffffff)
+#define SNOR_TIMING1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
+// Write access time. 
+#define SNOR_TIMING1_0_WE_WIDTH_SHIFT                   _MK_SHIFT_CONST(16)
+#define SNOR_TIMING1_0_WE_WIDTH_FIELD                   (_MK_MASK_CONST(0xff) << SNOR_TIMING1_0_WE_WIDTH_SHIFT)
+#define SNOR_TIMING1_0_WE_WIDTH_RANGE                   23:16
+#define SNOR_TIMING1_0_WE_WIDTH_WOFFSET                 0x0
+#define SNOR_TIMING1_0_WE_WIDTH_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SNOR_TIMING1_0_WE_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define SNOR_TIMING1_0_WE_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_TIMING1_0_WE_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Read access time.
+#define SNOR_TIMING1_0_OE_WIDTH_SHIFT                   _MK_SHIFT_CONST(8)
+#define SNOR_TIMING1_0_OE_WIDTH_FIELD                   (_MK_MASK_CONST(0xff) << SNOR_TIMING1_0_OE_WIDTH_SHIFT)
+#define SNOR_TIMING1_0_OE_WIDTH_RANGE                   15:8
+#define SNOR_TIMING1_0_OE_WIDTH_WOFFSET                 0x0
+#define SNOR_TIMING1_0_OE_WIDTH_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SNOR_TIMING1_0_OE_WIDTH_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define SNOR_TIMING1_0_OE_WIDTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_TIMING1_0_OE_WIDTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Indicates in cycles the number of wait states before when READY is issued.
+#define SNOR_TIMING1_0_WAIT_WIDTH_SHIFT                 _MK_SHIFT_CONST(0)
+#define SNOR_TIMING1_0_WAIT_WIDTH_FIELD                 (_MK_MASK_CONST(0xff) << SNOR_TIMING1_0_WAIT_WIDTH_SHIFT)
+#define SNOR_TIMING1_0_WAIT_WIDTH_RANGE                 7:0
+#define SNOR_TIMING1_0_WAIT_WIDTH_WOFFSET                       0x0
+#define SNOR_TIMING1_0_WAIT_WIDTH_DEFAULT                       _MK_MASK_CONST(0x3)
+#define SNOR_TIMING1_0_WAIT_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define SNOR_TIMING1_0_WAIT_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_TIMING1_0_WAIT_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register SNOR_MIO_CFG_0  
+#define SNOR_MIO_CFG_0                  _MK_ADDR_CONST(0x18)
+#define SNOR_MIO_CFG_0_SECURE                   0x0
+#define SNOR_MIO_CFG_0_WORD_COUNT                       0x1
+#define SNOR_MIO_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x10700000)
+#define SNOR_MIO_CFG_0_RESET_MASK                       _MK_MASK_CONST(0x30700000)
+#define SNOR_MIO_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SNOR_MIO_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SNOR_MIO_CFG_0_READ_MASK                        _MK_MASK_CONST(0x30700000)
+#define SNOR_MIO_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0x30700000)
+// Indicates the databus size of MIO Memory.
+#define SNOR_MIO_CFG_0_MIO_WORDWIDE_SHIFT                       _MK_SHIFT_CONST(29)
+#define SNOR_MIO_CFG_0_MIO_WORDWIDE_FIELD                       (_MK_MASK_CONST(0x1) << SNOR_MIO_CFG_0_MIO_WORDWIDE_SHIFT)
+#define SNOR_MIO_CFG_0_MIO_WORDWIDE_RANGE                       29:29
+#define SNOR_MIO_CFG_0_MIO_WORDWIDE_WOFFSET                     0x0
+#define SNOR_MIO_CFG_0_MIO_WORDWIDE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SNOR_MIO_CFG_0_MIO_WORDWIDE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define SNOR_MIO_CFG_0_MIO_WORDWIDE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define SNOR_MIO_CFG_0_MIO_WORDWIDE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define SNOR_MIO_CFG_0_MIO_WORDWIDE_MIO16BIT                    _MK_ENUM_CONST(0)
+#define SNOR_MIO_CFG_0_MIO_WORDWIDE_MIO32BIT                    _MK_ENUM_CONST(1)
+
+// Specifies the polarity of MIO RDY.
+#define SNOR_MIO_CFG_0_MIO_RDY_POL_SHIFT                        _MK_SHIFT_CONST(28)
+#define SNOR_MIO_CFG_0_MIO_RDY_POL_FIELD                        (_MK_MASK_CONST(0x1) << SNOR_MIO_CFG_0_MIO_RDY_POL_SHIFT)
+#define SNOR_MIO_CFG_0_MIO_RDY_POL_RANGE                        28:28
+#define SNOR_MIO_CFG_0_MIO_RDY_POL_WOFFSET                      0x0
+#define SNOR_MIO_CFG_0_MIO_RDY_POL_DEFAULT                      _MK_MASK_CONST(0x1)
+#define SNOR_MIO_CFG_0_MIO_RDY_POL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SNOR_MIO_CFG_0_MIO_RDY_POL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_MIO_CFG_0_MIO_RDY_POL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SNOR_MIO_CFG_0_MIO_RDY_POL_RESV                 _MK_ENUM_CONST(0)
+#define SNOR_MIO_CFG_0_MIO_RDY_POL_HIGH                 _MK_ENUM_CONST(1)
+
+// MIO 8 chip selects combinations.
+#define SNOR_MIO_CFG_0_MIO_SEL_SHIFT                    _MK_SHIFT_CONST(20)
+#define SNOR_MIO_CFG_0_MIO_SEL_FIELD                    (_MK_MASK_CONST(0x7) << SNOR_MIO_CFG_0_MIO_SEL_SHIFT)
+#define SNOR_MIO_CFG_0_MIO_SEL_RANGE                    22:20
+#define SNOR_MIO_CFG_0_MIO_SEL_WOFFSET                  0x0
+#define SNOR_MIO_CFG_0_MIO_SEL_DEFAULT                  _MK_MASK_CONST(0x7)
+#define SNOR_MIO_CFG_0_MIO_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define SNOR_MIO_CFG_0_MIO_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SNOR_MIO_CFG_0_MIO_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SNOR_MIO_CFG_0_MIO_SEL_MIO0                     _MK_ENUM_CONST(0)
+#define SNOR_MIO_CFG_0_MIO_SEL_MIO1                     _MK_ENUM_CONST(1)
+#define SNOR_MIO_CFG_0_MIO_SEL_MIO2                     _MK_ENUM_CONST(2)
+#define SNOR_MIO_CFG_0_MIO_SEL_MIO3                     _MK_ENUM_CONST(3)
+#define SNOR_MIO_CFG_0_MIO_SEL_MIO4                     _MK_ENUM_CONST(4)
+#define SNOR_MIO_CFG_0_MIO_SEL_MIO5                     _MK_ENUM_CONST(5)
+#define SNOR_MIO_CFG_0_MIO_SEL_MIO6                     _MK_ENUM_CONST(6)
+#define SNOR_MIO_CFG_0_MIO_SEL_MIO7                     _MK_ENUM_CONST(7)
+
+
+// Register SNOR_MIO_TIMING0_0  
+#define SNOR_MIO_TIMING0_0                      _MK_ADDR_CONST(0x1c)
+#define SNOR_MIO_TIMING0_0_SECURE                       0x0
+#define SNOR_MIO_TIMING0_0_WORD_COUNT                   0x1
+#define SNOR_MIO_TIMING0_0_RESET_VAL                    _MK_MASK_CONST(0x1020102)
+#define SNOR_MIO_TIMING0_0_RESET_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
+#define SNOR_MIO_TIMING0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define SNOR_MIO_TIMING0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SNOR_MIO_TIMING0_0_READ_MASK                    _MK_MASK_CONST(0x3f3f3f3f)
+#define SNOR_MIO_TIMING0_0_WRITE_MASK                   _MK_MASK_CONST(0x3f3f3f3f)
+// Minimum number of MIO bus clock cycles between the end of a write access 
+// and the start of the following access (write or read) for MIO.
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_WR_SHIFT                   _MK_SHIFT_CONST(24)
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_WR_FIELD                   (_MK_MASK_CONST(0x3f) << SNOR_MIO_TIMING0_0_MIO_A_DED_WR_SHIFT)
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_WR_RANGE                   29:24
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_WR_WOFFSET                 0x0
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_WR_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_WR_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_WR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_WR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Minimum number of MIO bus clock cycles during a write access that the MIO_RD
+// signal is set low for MIO.
+#define SNOR_MIO_TIMING0_0_MIO_A_WR_TIME_SHIFT                  _MK_SHIFT_CONST(16)
+#define SNOR_MIO_TIMING0_0_MIO_A_WR_TIME_FIELD                  (_MK_MASK_CONST(0x3f) << SNOR_MIO_TIMING0_0_MIO_A_WR_TIME_SHIFT)
+#define SNOR_MIO_TIMING0_0_MIO_A_WR_TIME_RANGE                  21:16
+#define SNOR_MIO_TIMING0_0_MIO_A_WR_TIME_WOFFSET                        0x0
+#define SNOR_MIO_TIMING0_0_MIO_A_WR_TIME_DEFAULT                        _MK_MASK_CONST(0x2)
+#define SNOR_MIO_TIMING0_0_MIO_A_WR_TIME_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define SNOR_MIO_TIMING0_0_MIO_A_WR_TIME_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SNOR_MIO_TIMING0_0_MIO_A_WR_TIME_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Minimum number of MIO bus clock cycles between the end of a read access 
+// and the start of the following access (write or read) for MIO.
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_RD_SHIFT                   _MK_SHIFT_CONST(8)
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_RD_FIELD                   (_MK_MASK_CONST(0x3f) << SNOR_MIO_TIMING0_0_MIO_A_DED_RD_SHIFT)
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_RD_RANGE                   13:8
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_RD_WOFFSET                 0x0
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_RD_DEFAULT                 _MK_MASK_CONST(0x1)
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_RD_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_RD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_MIO_TIMING0_0_MIO_A_DED_RD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Minimum number of MIO bus clock cycles during a read access that the MIO_RD
+// signal is set low for MIO.
+#define SNOR_MIO_TIMING0_0_MIO_A_RD_TIME_SHIFT                  _MK_SHIFT_CONST(0)
+#define SNOR_MIO_TIMING0_0_MIO_A_RD_TIME_FIELD                  (_MK_MASK_CONST(0x3f) << SNOR_MIO_TIMING0_0_MIO_A_RD_TIME_SHIFT)
+#define SNOR_MIO_TIMING0_0_MIO_A_RD_TIME_RANGE                  5:0
+#define SNOR_MIO_TIMING0_0_MIO_A_RD_TIME_WOFFSET                        0x0
+#define SNOR_MIO_TIMING0_0_MIO_A_RD_TIME_DEFAULT                        _MK_MASK_CONST(0x2)
+#define SNOR_MIO_TIMING0_0_MIO_A_RD_TIME_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define SNOR_MIO_TIMING0_0_MIO_A_RD_TIME_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define SNOR_MIO_TIMING0_0_MIO_A_RD_TIME_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register SNOR_DMA_CFG_0  
+#define SNOR_DMA_CFG_0                  _MK_ADDR_CONST(0x20)
+#define SNOR_DMA_CFG_0_SECURE                   0x0
+#define SNOR_DMA_CFG_0_WORD_COUNT                       0x1
+#define SNOR_DMA_CFG_0_RESET_VAL                        _MK_MASK_CONST(0x4000000)
+#define SNOR_DMA_CFG_0_RESET_MASK                       _MK_MASK_CONST(0xff00fffc)
+#define SNOR_DMA_CFG_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_READ_MASK                        _MK_MASK_CONST(0xff00fffc)
+#define SNOR_DMA_CFG_0_WRITE_MASK                       _MK_MASK_CONST(0xff00fffc)
+// This represents the number of DMA is enabled.
+#define SNOR_DMA_CFG_0_DMA_GO_SHIFT                     _MK_SHIFT_CONST(31)
+#define SNOR_DMA_CFG_0_DMA_GO_FIELD                     (_MK_MASK_CONST(0x1) << SNOR_DMA_CFG_0_DMA_GO_SHIFT)
+#define SNOR_DMA_CFG_0_DMA_GO_RANGE                     31:31
+#define SNOR_DMA_CFG_0_DMA_GO_WOFFSET                   0x0
+#define SNOR_DMA_CFG_0_DMA_GO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_DMA_GO_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define SNOR_DMA_CFG_0_DMA_GO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_DMA_GO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_DMA_GO_DISABLE                   _MK_ENUM_CONST(0)
+#define SNOR_DMA_CFG_0_DMA_GO_ENABLE                    _MK_ENUM_CONST(1)
+
+// Indicates the status of DMA.
+#define SNOR_DMA_CFG_0_BSY_SHIFT                        _MK_SHIFT_CONST(30)
+#define SNOR_DMA_CFG_0_BSY_FIELD                        (_MK_MASK_CONST(0x1) << SNOR_DMA_CFG_0_BSY_SHIFT)
+#define SNOR_DMA_CFG_0_BSY_RANGE                        30:30
+#define SNOR_DMA_CFG_0_BSY_WOFFSET                      0x0
+#define SNOR_DMA_CFG_0_BSY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_BSY_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SNOR_DMA_CFG_0_BSY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_BSY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// This represents the  the direction of DMA data Transfer.
+#define SNOR_DMA_CFG_0_DIR_SHIFT                        _MK_SHIFT_CONST(29)
+#define SNOR_DMA_CFG_0_DIR_FIELD                        (_MK_MASK_CONST(0x1) << SNOR_DMA_CFG_0_DIR_SHIFT)
+#define SNOR_DMA_CFG_0_DIR_RANGE                        29:29
+#define SNOR_DMA_CFG_0_DIR_WOFFSET                      0x0
+#define SNOR_DMA_CFG_0_DIR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_DIR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SNOR_DMA_CFG_0_DIR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_DIR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_DIR_NOR2AHB                      _MK_ENUM_CONST(0)
+#define SNOR_DMA_CFG_0_DIR_AHB2NOR                      _MK_ENUM_CONST(1)
+
+// Interrupt Enable on DMA transfer completion.
+#define SNOR_DMA_CFG_0_IE_DMA_DONE_SHIFT                        _MK_SHIFT_CONST(28)
+#define SNOR_DMA_CFG_0_IE_DMA_DONE_FIELD                        (_MK_MASK_CONST(0x1) << SNOR_DMA_CFG_0_IE_DMA_DONE_SHIFT)
+#define SNOR_DMA_CFG_0_IE_DMA_DONE_RANGE                        28:28
+#define SNOR_DMA_CFG_0_IE_DMA_DONE_WOFFSET                      0x0
+#define SNOR_DMA_CFG_0_IE_DMA_DONE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_IE_DMA_DONE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SNOR_DMA_CFG_0_IE_DMA_DONE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_IE_DMA_DONE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_IE_DMA_DONE_DISABLE                      _MK_ENUM_CONST(0)
+#define SNOR_DMA_CFG_0_IE_DMA_DONE_ENABLE                       _MK_ENUM_CONST(1)
+
+// Interrupt Status (Write 1 to clear).
+#define SNOR_DMA_CFG_0_IS_DMA_DONE_SHIFT                        _MK_SHIFT_CONST(27)
+#define SNOR_DMA_CFG_0_IS_DMA_DONE_FIELD                        (_MK_MASK_CONST(0x1) << SNOR_DMA_CFG_0_IS_DMA_DONE_SHIFT)
+#define SNOR_DMA_CFG_0_IS_DMA_DONE_RANGE                        27:27
+#define SNOR_DMA_CFG_0_IS_DMA_DONE_WOFFSET                      0x0
+#define SNOR_DMA_CFG_0_IS_DMA_DONE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_IS_DMA_DONE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define SNOR_DMA_CFG_0_IS_DMA_DONE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_IS_DMA_DONE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_IS_DMA_DONE_DISABLE                      _MK_ENUM_CONST(0)
+#define SNOR_DMA_CFG_0_IS_DMA_DONE_ENABLE                       _MK_ENUM_CONST(1)
+
+// DMA burst size.
+#define SNOR_DMA_CFG_0_BURST_SIZE_SHIFT                 _MK_SHIFT_CONST(24)
+#define SNOR_DMA_CFG_0_BURST_SIZE_FIELD                 (_MK_MASK_CONST(0x7) << SNOR_DMA_CFG_0_BURST_SIZE_SHIFT)
+#define SNOR_DMA_CFG_0_BURST_SIZE_RANGE                 26:24
+#define SNOR_DMA_CFG_0_BURST_SIZE_WOFFSET                       0x0
+#define SNOR_DMA_CFG_0_BURST_SIZE_DEFAULT                       _MK_MASK_CONST(0x4)
+#define SNOR_DMA_CFG_0_BURST_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define SNOR_DMA_CFG_0_BURST_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_BURST_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_BURST_SIZE_RESV0                 _MK_ENUM_CONST(0)
+#define SNOR_DMA_CFG_0_BURST_SIZE_RESV1                 _MK_ENUM_CONST(1)
+#define SNOR_DMA_CFG_0_BURST_SIZE_RESV2                 _MK_ENUM_CONST(2)
+#define SNOR_DMA_CFG_0_BURST_SIZE_RESV3                 _MK_ENUM_CONST(3)
+#define SNOR_DMA_CFG_0_BURST_SIZE_BS1WORD                       _MK_ENUM_CONST(4)
+#define SNOR_DMA_CFG_0_BURST_SIZE_BS4WORD                       _MK_ENUM_CONST(5)
+#define SNOR_DMA_CFG_0_BURST_SIZE_BS8WORD                       _MK_ENUM_CONST(6)
+#define SNOR_DMA_CFG_0_BURST_SIZE_RESV7                 _MK_ENUM_CONST(7)
+
+// Specifies the number of words that need to be transferred. 
+#define SNOR_DMA_CFG_0_WORD_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define SNOR_DMA_CFG_0_WORD_COUNT_FIELD                 (_MK_MASK_CONST(0x3fff) << SNOR_DMA_CFG_0_WORD_COUNT_SHIFT)
+#define SNOR_DMA_CFG_0_WORD_COUNT_RANGE                 15:2
+#define SNOR_DMA_CFG_0_WORD_COUNT_WOFFSET                       0x0
+#define SNOR_DMA_CFG_0_WORD_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_WORD_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define SNOR_DMA_CFG_0_WORD_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_DMA_CFG_0_WORD_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register SNOR_CS_MUX_CFG_0  
+#define SNOR_CS_MUX_CFG_0                       _MK_ADDR_CONST(0x24)
+#define SNOR_CS_MUX_CFG_0_SECURE                        0x0
+#define SNOR_CS_MUX_CFG_0_WORD_COUNT                    0x1
+#define SNOR_CS_MUX_CFG_0_RESET_VAL                     _MK_MASK_CONST(0x76543210)
+#define SNOR_CS_MUX_CFG_0_RESET_MASK                    _MK_MASK_CONST(0x77777777)
+#define SNOR_CS_MUX_CFG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define SNOR_CS_MUX_CFG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define SNOR_CS_MUX_CFG_0_READ_MASK                     _MK_MASK_CONST(0x77777777)
+#define SNOR_CS_MUX_CFG_0_WRITE_MASK                    _MK_MASK_CONST(0x77777777)
+// This represents the which chip selects goes to which memory. 
+// Chip selection between SNOR and MIO Memories.
+#define SNOR_CS_MUX_CFG_0_CS7_MUX_SHIFT                 _MK_SHIFT_CONST(28)
+#define SNOR_CS_MUX_CFG_0_CS7_MUX_FIELD                 (_MK_MASK_CONST(0x7) << SNOR_CS_MUX_CFG_0_CS7_MUX_SHIFT)
+#define SNOR_CS_MUX_CFG_0_CS7_MUX_RANGE                 30:28
+#define SNOR_CS_MUX_CFG_0_CS7_MUX_WOFFSET                       0x0
+#define SNOR_CS_MUX_CFG_0_CS7_MUX_DEFAULT                       _MK_MASK_CONST(0x7)
+#define SNOR_CS_MUX_CFG_0_CS7_MUX_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define SNOR_CS_MUX_CFG_0_CS7_MUX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CS_MUX_CFG_0_CS7_MUX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This represents the which chip selects goes to which memory. 
+// Chip selection between SNOR and MIO Memories.
+#define SNOR_CS_MUX_CFG_0_CS6_MUX_SHIFT                 _MK_SHIFT_CONST(24)
+#define SNOR_CS_MUX_CFG_0_CS6_MUX_FIELD                 (_MK_MASK_CONST(0x7) << SNOR_CS_MUX_CFG_0_CS6_MUX_SHIFT)
+#define SNOR_CS_MUX_CFG_0_CS6_MUX_RANGE                 26:24
+#define SNOR_CS_MUX_CFG_0_CS6_MUX_WOFFSET                       0x0
+#define SNOR_CS_MUX_CFG_0_CS6_MUX_DEFAULT                       _MK_MASK_CONST(0x6)
+#define SNOR_CS_MUX_CFG_0_CS6_MUX_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define SNOR_CS_MUX_CFG_0_CS6_MUX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CS_MUX_CFG_0_CS6_MUX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This represents the which chip selects goes to which memory. 
+// Chip selection between SNOR and MIO Memories.
+#define SNOR_CS_MUX_CFG_0_CS5_MUX_SHIFT                 _MK_SHIFT_CONST(20)
+#define SNOR_CS_MUX_CFG_0_CS5_MUX_FIELD                 (_MK_MASK_CONST(0x7) << SNOR_CS_MUX_CFG_0_CS5_MUX_SHIFT)
+#define SNOR_CS_MUX_CFG_0_CS5_MUX_RANGE                 22:20
+#define SNOR_CS_MUX_CFG_0_CS5_MUX_WOFFSET                       0x0
+#define SNOR_CS_MUX_CFG_0_CS5_MUX_DEFAULT                       _MK_MASK_CONST(0x5)
+#define SNOR_CS_MUX_CFG_0_CS5_MUX_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define SNOR_CS_MUX_CFG_0_CS5_MUX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CS_MUX_CFG_0_CS5_MUX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This represents the which chip selects goes to which memory. 
+// Chip selection between SNOR and MIO Memories.
+#define SNOR_CS_MUX_CFG_0_CS4_MUX_SHIFT                 _MK_SHIFT_CONST(16)
+#define SNOR_CS_MUX_CFG_0_CS4_MUX_FIELD                 (_MK_MASK_CONST(0x7) << SNOR_CS_MUX_CFG_0_CS4_MUX_SHIFT)
+#define SNOR_CS_MUX_CFG_0_CS4_MUX_RANGE                 18:16
+#define SNOR_CS_MUX_CFG_0_CS4_MUX_WOFFSET                       0x0
+#define SNOR_CS_MUX_CFG_0_CS4_MUX_DEFAULT                       _MK_MASK_CONST(0x4)
+#define SNOR_CS_MUX_CFG_0_CS4_MUX_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define SNOR_CS_MUX_CFG_0_CS4_MUX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CS_MUX_CFG_0_CS4_MUX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This represents the which chip selects goes to which memory. 
+// Chip selection between SNOR and MIO Memories.
+#define SNOR_CS_MUX_CFG_0_CS3_MUX_SHIFT                 _MK_SHIFT_CONST(12)
+#define SNOR_CS_MUX_CFG_0_CS3_MUX_FIELD                 (_MK_MASK_CONST(0x7) << SNOR_CS_MUX_CFG_0_CS3_MUX_SHIFT)
+#define SNOR_CS_MUX_CFG_0_CS3_MUX_RANGE                 14:12
+#define SNOR_CS_MUX_CFG_0_CS3_MUX_WOFFSET                       0x0
+#define SNOR_CS_MUX_CFG_0_CS3_MUX_DEFAULT                       _MK_MASK_CONST(0x3)
+#define SNOR_CS_MUX_CFG_0_CS3_MUX_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define SNOR_CS_MUX_CFG_0_CS3_MUX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CS_MUX_CFG_0_CS3_MUX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This represents the which chip selects goes to which memory. 
+// Chip selection between SNOR and MIO Memories.
+#define SNOR_CS_MUX_CFG_0_CS2_MUX_SHIFT                 _MK_SHIFT_CONST(8)
+#define SNOR_CS_MUX_CFG_0_CS2_MUX_FIELD                 (_MK_MASK_CONST(0x7) << SNOR_CS_MUX_CFG_0_CS2_MUX_SHIFT)
+#define SNOR_CS_MUX_CFG_0_CS2_MUX_RANGE                 10:8
+#define SNOR_CS_MUX_CFG_0_CS2_MUX_WOFFSET                       0x0
+#define SNOR_CS_MUX_CFG_0_CS2_MUX_DEFAULT                       _MK_MASK_CONST(0x2)
+#define SNOR_CS_MUX_CFG_0_CS2_MUX_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define SNOR_CS_MUX_CFG_0_CS2_MUX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CS_MUX_CFG_0_CS2_MUX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This represents the which chip selects goes to which memory. 
+// Chip selection between SNOR and MIO Memories.
+#define SNOR_CS_MUX_CFG_0_CS1_MUX_SHIFT                 _MK_SHIFT_CONST(4)
+#define SNOR_CS_MUX_CFG_0_CS1_MUX_FIELD                 (_MK_MASK_CONST(0x7) << SNOR_CS_MUX_CFG_0_CS1_MUX_SHIFT)
+#define SNOR_CS_MUX_CFG_0_CS1_MUX_RANGE                 6:4
+#define SNOR_CS_MUX_CFG_0_CS1_MUX_WOFFSET                       0x0
+#define SNOR_CS_MUX_CFG_0_CS1_MUX_DEFAULT                       _MK_MASK_CONST(0x1)
+#define SNOR_CS_MUX_CFG_0_CS1_MUX_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define SNOR_CS_MUX_CFG_0_CS1_MUX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CS_MUX_CFG_0_CS1_MUX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This represents the which chip selects goes to which memory. 
+// Chip selection between SNOR and MIO Memories.
+#define SNOR_CS_MUX_CFG_0_CS0_MUX_SHIFT                 _MK_SHIFT_CONST(0)
+#define SNOR_CS_MUX_CFG_0_CS0_MUX_FIELD                 (_MK_MASK_CONST(0x7) << SNOR_CS_MUX_CFG_0_CS0_MUX_SHIFT)
+#define SNOR_CS_MUX_CFG_0_CS0_MUX_RANGE                 2:0
+#define SNOR_CS_MUX_CFG_0_CS0_MUX_WOFFSET                       0x0
+#define SNOR_CS_MUX_CFG_0_CS0_MUX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define SNOR_CS_MUX_CFG_0_CS0_MUX_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define SNOR_CS_MUX_CFG_0_CS0_MUX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define SNOR_CS_MUX_CFG_0_CS0_MUX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSNOR_REGS(_op_) \
+_op_(SNOR_CONFIG_0) \
+_op_(SNOR_STA_0) \
+_op_(SNOR_NOR_ADDR_PTR_0) \
+_op_(SNOR_AHB_ADDR_PTR_0) \
+_op_(SNOR_TIMING0_0) \
+_op_(SNOR_TIMING1_0) \
+_op_(SNOR_MIO_CFG_0) \
+_op_(SNOR_MIO_TIMING0_0) \
+_op_(SNOR_DMA_CFG_0) \
+_op_(SNOR_CS_MUX_CFG_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_SNOR       0x00000000
+
+//
+// ARSNOR REGISTER BANKS
+//
+
+#define SNOR0_FIRST_REG 0x0000 // SNOR_CONFIG_0
+#define SNOR0_LAST_REG 0x0024 // SNOR_CS_MUX_CFG_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARSNOR_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arusb.h b/arch/arm/mach-tegra/nv/include/ap20/arusb.h
new file mode 100644
index 000000000000..b8663217a392
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arusb.h
@@ -0,0 +1,36904 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARUSB_H_INC_
+#define ___ARUSB_H_INC_
+
+// Register USB2_CONTROLLER_USB2D_ID_0  
+#define USB2_CONTROLLER_USB2D_ID_0                      _MK_ADDR_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ID_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ID_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ID_0_RESET_VAL                    _MK_MASK_CONST(0x33fa05)
+#define USB2_CONTROLLER_USB2D_ID_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_USB2D_ID_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ID_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ID_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_USB2D_ID_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// Revision number of the USB controller. This is set  to 0x33.
+#define USB2_CONTROLLER_USB2D_ID_0_REVISION_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ID_0_REVISION_FIELD                       (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_ID_0_REVISION_SHIFT)
+#define USB2_CONTROLLER_USB2D_ID_0_REVISION_RANGE                       23:16
+#define USB2_CONTROLLER_USB2D_ID_0_REVISION_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ID_0_REVISION_DEFAULT                     _MK_MASK_CONST(0x33)
+#define USB2_CONTROLLER_USB2D_ID_0_REVISION_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_ID_0_REVISION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ID_0_REVISION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Ones complement version of ID. This field is set  to 0xFA.
+#define USB2_CONTROLLER_USB2D_ID_0_NID_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_ID_0_NID_FIELD                    (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_ID_0_NID_SHIFT)
+#define USB2_CONTROLLER_USB2D_ID_0_NID_RANGE                    15:8
+#define USB2_CONTROLLER_USB2D_ID_0_NID_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ID_0_NID_DEFAULT                  _MK_MASK_CONST(0xfa)
+#define USB2_CONTROLLER_USB2D_ID_0_NID_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_ID_0_NID_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ID_0_NID_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Configuration number. This field is set to 0x05
+#define USB2_CONTROLLER_USB2D_ID_0_ID_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ID_0_ID_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_ID_0_ID_SHIFT)
+#define USB2_CONTROLLER_USB2D_ID_0_ID_RANGE                     7:0
+#define USB2_CONTROLLER_USB2D_ID_0_ID_WOFFSET                   0x0
+#define USB2_CONTROLLER_USB2D_ID_0_ID_DEFAULT                   _MK_MASK_CONST(0x5)
+#define USB2_CONTROLLER_USB2D_ID_0_ID_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_ID_0_ID_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ID_0_ID_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_HW_GENERAL_0  
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0                      _MK_ADDR_CONST(0x4)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_RESET_VAL                    _MK_MASK_CONST(0x35)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_RESET_MASK                   _MK_MASK_CONST(0x1f7)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_READ_MASK                    _MK_MASK_CONST(0x1f7)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// VUSB_HS_PHY_MODE : set to 0 for UTMI PHY
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYM_SHIFT                   _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYM_FIELD                   (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYM_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYM_RANGE                   8:6
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYM_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYM_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYM_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYM_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYM_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// VUSB_HS_PHY16_8 : Width of the UTMI parallel  interface. Set to 3 : 16-bit UTMI parallel interface software programmable to  8-bit
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYW_SHIFT                   _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYW_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYW_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYW_RANGE                   5:4
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYW_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYW_DEFAULT                 _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYW_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYW_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_PHYW_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// VUSB_HS_CLOCK_CONFIGURATION : Clock configuration  2 selected
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_CLKC_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_CLKC_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HW_GENERAL_0_CLKC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_CLKC_RANGE                   2:1
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_CLKC_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_CLKC_DEFAULT                 _MK_MASK_CONST(0x2)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_CLKC_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_CLKC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_CLKC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// VUSB_HS_RESET_TYPE : set to 1 = asynchronous reset
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_RT_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_RT_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HW_GENERAL_0_RT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_RT_RANGE                     0:0
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_RT_WOFFSET                   0x0
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_RT_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_RT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_RT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_GENERAL_0_RT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_HW_HOST_0  
+#define USB2_CONTROLLER_USB2D_HW_HOST_0                 _MK_ADDR_CONST(0x8)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_SECURE                  0x0
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_RESET_VAL                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_RESET_MASK                      _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_READ_MASK                       _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// VUSB_HS_NUM_PORT-1: This host controller has only  1 port. So this field will always be 0.
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_NPORT_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_NPORT_FIELD                     (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HW_HOST_0_NPORT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_NPORT_RANGE                     3:1
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_NPORT_WOFFSET                   0x0
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_NPORT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_NPORT_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_NPORT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_NPORT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VUSB_HS_HOST: Indicates support for host mode. Set  to 1.
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_HC_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_HC_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HW_HOST_0_HC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_HC_RANGE                        0:0
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_HC_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_HC_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_HC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_HC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_HOST_0_HC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_HW_DEVICE_0  
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0                       _MK_ADDR_CONST(0xc)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_SECURE                        0x0
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_RESET_VAL                     _MK_MASK_CONST(0x21)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_RESET_MASK                    _MK_MASK_CONST(0x3f)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_READ_MASK                     _MK_MASK_CONST(0x3f)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// VUSB_HS_DV_EP: No. of endpoints supported by this device controller. Set to 16. This includes control endpoint 0.
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DEVEP_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DEVEP_FIELD                   (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_USB2D_HW_DEVICE_0_DEVEP_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DEVEP_RANGE                   5:1
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DEVEP_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DEVEP_DEFAULT                 _MK_MASK_CONST(0x10)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DEVEP_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DEVEP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DEVEP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Device capable: Set to 1 indicating support for device mode.
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DC_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DC_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HW_DEVICE_0_DC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DC_RANGE                      0:0
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DC_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DC_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_DEVICE_0_DC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_HW_TXBUF_0  
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0                        _MK_ADDR_CONST(0x10)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_SECURE                         0x0
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_WORD_COUNT                     0x1
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_RESET_VAL                      _MK_MASK_CONST(0x70b08)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_RESET_MASK                     _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_READ_MASK                      _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// VUSB_HS_TX_CHAN_ADD: Total no. of address bits for the transmit buffer of each transmit endpoint. Set to 7. Each transmit buffer is 128 words deep.
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXCHANADD_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXCHANADD_FIELD                        (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXCHANADD_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXCHANADD_RANGE                        23:16
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXCHANADD_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXCHANADD_DEFAULT                      _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXCHANADD_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXCHANADD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXCHANADD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VUSB_HS_TX_ADD: Total no. of address bits for the transmit buffer. Set to 11. The total depth of the transmit buffer is 2048 words.
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXADD_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXADD_FIELD                    (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXADD_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXADD_RANGE                    15:8
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXADD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXADD_DEFAULT                  _MK_MASK_CONST(0xb)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXADD_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXADD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TXADD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// VUSB_HS_TX_BURST: Maximum burst size supported by the transmit endpoints for data transfers. Set to 8.
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TCBURST_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TCBURST_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HW_TXBUF_0_TCBURST_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TCBURST_RANGE                  7:0
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TCBURST_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TCBURST_DEFAULT                        _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TCBURST_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TCBURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_TXBUF_0_TCBURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_HW_RXBUF_0  
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0                        _MK_ADDR_CONST(0x14)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_SECURE                         0x0
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_WORD_COUNT                     0x1
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RESET_VAL                      _MK_MASK_CONST(0x708)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// VUSB_HS_RX_ADD: Total no. of address bits for the receive buffer. Set to 7. The total depth of the receive buffer is 128 words
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXADD_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXADD_FIELD                    (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXADD_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXADD_RANGE                    15:8
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXADD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXADD_DEFAULT                  _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXADD_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXADD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXADD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// VUSB_HS_RX_BURST: Maximum burst size supported by the receive endpoints for data transfers. Set to 8.
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXBURST_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXBURST_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXBURST_SHIFT)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXBURST_RANGE                  7:0
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXBURST_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXBURST_DEFAULT                        _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXBURST_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXBURST_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HW_RXBUF_0_RXBURST_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_CAPLENGTH_0  
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0                       _MK_ADDR_CONST(0x100)
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_SECURE                        0x0
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_RESET_VAL                     _MK_MASK_CONST(0x40)
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_RESET_MASK                    _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Indicates which offset to add to the register base address at the beginning of the Operational Register. Set to 0x40.
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_CAPLENGTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_CAPLENGTH_FIELD                       (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_CAPLENGTH_0_CAPLENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_CAPLENGTH_RANGE                       7:0
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_CAPLENGTH_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_CAPLENGTH_DEFAULT                     _MK_MASK_CONST(0x40)
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_CAPLENGTH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_CAPLENGTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_CAPLENGTH_0_CAPLENGTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_HCIVERSON_0  
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0                       _MK_ADDR_CONST(0x102)
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_SECURE                        0x0
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_RESET_VAL                     _MK_MASK_CONST(0x100)
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Contains a BCD encoding of the EHCI revision number supported by this host controller. The most significant byte of this register represents a major revision and the least significant byte is the minor revision. This host controller supports EHCI revision 1.00.
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_HCIVERSION_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_HCIVERSION_FIELD                      (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_USB2D_HCIVERSON_0_HCIVERSION_SHIFT)
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_HCIVERSION_RANGE                      15:0
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_HCIVERSION_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_HCIVERSION_DEFAULT                    _MK_MASK_CONST(0x100)
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_HCIVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_HCIVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCIVERSON_0_HCIVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_HCSPARAMS_0  
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0                       _MK_ADDR_CONST(0x104)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_SECURE                        0x0
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_RESET_VAL                     _MK_MASK_CONST(0x1100011)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_RESET_MASK                    _MK_MASK_CONST(0xff0ff1f)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_READ_MASK                     _MK_MASK_CONST(0xff0ff1f)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Number of Transaction Translators: indicates the number of embedded transaction translators associated with the USB2.0 host controller. This field is always set to 1 indicating only 1 embedded TT is implemented in this implementation. This is a non-EHCI field to support embedded TT.
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_TT_SHIFT                    _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_TT_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_TT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_TT_RANGE                    27:24
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_TT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_TT_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_TT_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_TT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_TT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of Ports per Transaction Translator: indicates the number of ports assigned to each transaction translator within the USB2.0 host controller. Field always equals N_PORTS. This is a non-EHCI field to support embedded TT.
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PTT_SHIFT                   _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PTT_FIELD                   (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PTT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PTT_RANGE                   23:20
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PTT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PTT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PTT_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PTT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PTT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of Companion Controller: indicates the number of companion controllers. This field is set to 0.
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_CC_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_CC_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_CC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_CC_RANGE                    15:12
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_CC_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_CC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_CC_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_CC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_CC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Number of Ports per Companion Controller: indicates the number of ports supported per internal companion controller. This field is set to 0.
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PCC_SHIFT                   _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PCC_FIELD                   (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PCC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PCC_RANGE                   11:8
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PCC_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PCC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PCC_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PCC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PCC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Port Power Control: indicates whether the host controller implementation includes port power control. 
+// 1 = Ports have port power switches         0= Ports do not have port power switches.
+// This field affects the functionality of the port Power field in each port status and control register. This field is set to 1.
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_PPC_SHIFT                     _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_PPC_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HCSPARAMS_0_PPC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_PPC_RANGE                     4:4
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_PPC_WOFFSET                   0x0
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_PPC_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_PPC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_PPC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_PPC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller. This field is fixed to 1, since this host controller only supports 1 port.
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PORTS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PORTS_FIELD                 (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PORTS_SHIFT)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PORTS_RANGE                 3:0
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PORTS_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PORTS_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PORTS_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PORTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCSPARAMS_0_N_PORTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_HCCPARAMS_0  
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0                       _MK_ADDR_CONST(0x108)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_SECURE                        0x0
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_RESET_VAL                     _MK_MASK_CONST(0x6)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_RESET_MASK                    _MK_MASK_CONST(0xfff6)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_READ_MASK                     _MK_MASK_CONST(0xfff6)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// EHCI Extended Capabilities Pointer: indicates a capabilities list exists. A value of 00h indicates no extended capabilities are implemented. For this implementation this field is always "0". 
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_EECP_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_EECP_FIELD                    (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HCCPARAMS_0_EECP_SHIFT)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_EECP_RANGE                    15:8
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_EECP_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_EECP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_EECP_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_EECP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_EECP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures  (one or more) before flushing the state. When bit [7] is a one, then host software assumes the host controller may cache an isochronous data structure for an entire frame. This field will always be "0". 
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_IST_SHIFT                     _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_IST_FIELD                     (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HCCPARAMS_0_IST_SHIFT)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_IST_RANGE                     7:4
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_IST_WOFFSET                   0x0
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_IST_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_IST_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_IST_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_IST_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Asynchronous Schedule Park Capability. 
+// 1 = (Default) the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. 
+// This field is always 1.
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_ASP_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_ASP_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HCCPARAMS_0_ASP_SHIFT)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_ASP_RANGE                     2:2
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_ASP_WOFFSET                   0x0
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_ASP_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_ASP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_ASP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_ASP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Programmable Frame List Flag. 
+// 0 = System software must use a frame list length of 1024 elements with this host controller. The USBCMD register Frame List Size field is a read-only register and must be set to zero. 
+// 1 = System software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field.  The frame list must always be aligned on a 4K-page boundary.  This requirement ensures that the frame list is always physically contiguous. 
+// This field will always be "1". 
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_PFL_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_PFL_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HCCPARAMS_0_PFL_SHIFT)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_PFL_RANGE                     1:1
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_PFL_WOFFSET                   0x0
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_PFL_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_PFL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_PFL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_HCCPARAMS_0_PFL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_DCIVERSION_0  
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0                      _MK_ADDR_CONST(0x120)
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_READ_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this  register. 
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_DCIVERSION_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_DCIVERSION_FIELD                     (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_USB2D_DCIVERSION_0_DCIVERSION_SHIFT)
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_DCIVERSION_RANGE                     15:0
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_DCIVERSION_WOFFSET                   0x0
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_DCIVERSION_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_DCIVERSION_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_DCIVERSION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_DCIVERSION_0_DCIVERSION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_DCCPARAMS_0  
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0                       _MK_ADDR_CONST(0x124)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_SECURE                        0x0
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_RESET_VAL                     _MK_MASK_CONST(0x190)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_RESET_MASK                    _MK_MASK_CONST(0x19f)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_READ_MASK                     _MK_MASK_CONST(0x19f)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Host Capable: 1 = This controller is capable of operating as an EHCI compatible USB 2 0 host controller operating as an EHCI  compatible USB 2.0 host controller. This field is set to 1.
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_HC_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_HC_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DCCPARAMS_0_HC_SHIFT)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_HC_RANGE                      8:8
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_HC_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_HC_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_HC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_HC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_HC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Device Capable: 1 = Controller is capable of operating as USB 2.0 device. This field is set to 1.
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DC_SHIFT                      _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DC_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DCCPARAMS_0_DC_SHIFT)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DC_RANGE                      7:7
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DC_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DC_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Device Endpoint Number: Number of endpoints built into the device controller. This is set to 16.
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DEN_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DEN_FIELD                     (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_USB2D_DCCPARAMS_0_DEN_SHIFT)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DEN_RANGE                     4:0
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DEN_WOFFSET                   0x0
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DEN_DEFAULT                   _MK_MASK_CONST(0x10)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_DCCPARAMS_0_DEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_USBCMD_0  
+#define USB2_CONTROLLER_USB2D_USBCMD_0                  _MK_ADDR_CONST(0x140)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SECURE                   0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_WORD_COUNT                       0x1
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RESET_VAL                        _MK_MASK_CONST(0x80b00)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RESET_MASK                       _MK_MASK_CONST(0xffebff)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_READ_MASK                        _MK_MASK_CONST(0xffebff)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_WRITE_MASK                       _MK_MASK_CONST(0xffeb7f)
+// Interrupt Threshold Control .Read/Write. Default 08h. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below.  
+// Value          Maximum Interrupt Interval 
+// 00h              Immediate (no threshold) 
+// 01h                1 micro-frame 
+// 02h           2 micro-frames 
+// 04h          4 micro-frames 
+// 08h          8 micro-frames 
+// 10h          16 micro-frames 
+// 20h         32 micro-frames 
+// 40h         64 micro-frames
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_FIELD                        (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_USBCMD_0_ITC_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_RANGE                        23:16
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_DEFAULT                      _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_IMMEDIATE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_ONE_MF                       _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_TWO_MF                       _MK_ENUM_CONST(4)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_EIGHT_MF                     _MK_ENUM_CONST(8)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_SIXTEEN_MF                   _MK_ENUM_CONST(16)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_THIRTY_TWO_MF                        _MK_ENUM_CONST(32)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ITC_SIXTY_FOUR_MF                        _MK_ENUM_CONST(64)
+
+// Bit 2 of Frame List Size.
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS2_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBCMD_0_FS2_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS2_RANGE                        15:15
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS2_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Frame List Size . (Read/Write).  000 = Default
+// This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one.  Hence this field is Read/Write for this implementation. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. 
+// Note that this field is made up from USBCMD bits 15, 3 and 2. 
+// 000 = 1024 elements (4096 bytes) Default value 
+// 001 = 512 elements (2048 bytes) 
+// 010 = 256 elements (1024 bytes)  
+// 011 = 128 elements (512 bytes) 
+// 100 = 64 elements (256 bytes) 
+// 101 = 32 elements (128 bytes) 
+// 110 = 16 elements (64 bytes) 
+// 111 = 8 elements (32 bytes)       
+// Only the host controller uses this field. 
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS1_FS0_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS1_FS0_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_USBCMD_0_FS1_FS0_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS1_FS0_RANGE                    3:2
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS1_FS0_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS1_FS0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS1_FS0_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS1_FS0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_FS1_FS0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Setup Tripwire. This bit is used as a semaphore when the 8 bytes  of setup data read extracted by the firmware. If the setup lockout mode is  off, then there exists a hazard when new setup data arrives and firmware is  copying setup data from the QH for a previous setup packet. This bit is set  and cleared by software and will be cleared by hardware when a hazard exists.
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SUTW_SHIFT                       _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SUTW_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBCMD_0_SUTW_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SUTW_RANGE                       13:13
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SUTW_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SUTW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SUTW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SUTW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SUTW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SUTW_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_SUTW_SET                 _MK_ENUM_CONST(1)
+
+// Add DTD Tripwire. This bit is used as a semaphore when a dTD is  added to an active (primed) endpoint. This bit is set and cleared by software  and will be cleared by hardware when a hazard exists such that adding a dTD  to a primed endpoint may go unnoticed.
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ATDTW_SHIFT                      _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ATDTW_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBCMD_0_ATDTW_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ATDTW_RANGE                      14:14
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ATDTW_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ATDTW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ATDTW_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ATDTW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ATDTW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ATDTW_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ATDTW_SET                        _MK_ENUM_CONST(1)
+
+// Asynchronous Schedule Park mode Enable. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled.  This field is set to "1" in this  implementation. 
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASPE_SHIFT                       _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASPE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBCMD_0_ASPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASPE_RANGE                       11:11
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASPE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASPE_DEFAULT                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASPE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASPE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASPE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASPE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASPE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Asynchronous Schedule Park Mode Count (OPTIONAL) Read/Write.  If the Asynchronous Park Capability bit in the HCCPARAMS register is a one,  then this field defaults to 3h and is R/W. Otherwise it defaults to zero and  is RO. It contains a count of the number of successive transactions the host  controller is allowed to execute from a high-speed queue head on the  Asynchronous schedule before continuing traversal of the Asynchronous  schedule. Valid values are 1h to 3h. Software must not write a zero to this  bit when Park Mode Enable is a one as this will result in undefined behavior.  This field is set to 3h in this implementation and is Read/Write capable. 
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASP1_ASP0_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASP1_ASP0_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_USBCMD_0_ASP1_ASP0_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASP1_ASP0_RANGE                  9:8
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASP1_ASP0_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASP1_ASP0_DEFAULT                        _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASP1_ASP0_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASP1_ASP0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASP1_ASP0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Light Host/Device Controller Reset (OPTIONAL) .  Read Only. Not Implemented. This field will always be "0". 
+#define USB2_CONTROLLER_USB2D_USBCMD_0_LR_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_LR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBCMD_0_LR_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_LR_RANGE                 7:7
+#define USB2_CONTROLLER_USB2D_USBCMD_0_LR_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_LR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_LR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_LR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_LR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Interrupt on Async Advance Doorbell. When the host controller has evicted all  appropriate cached schedule states, it sets the Interrupt on Async Advance  status bit in the USBSTS register. If the Interrupt on Sync Advance Enable  bit in the USBINTR register is one, then the host controller will assert an  interrupt at the next interrupt threshold. The host controller sets this bit  to zero after it has set the Interrupt on Sync Advance status bit in the  USBSTS register to one. Software should not write a one to this bit when the  asynchronous schedule is inactive. Doing so will yield undefined results. This  bit is only used in host mode. Writing a one to this bit when device mode is  selected will have undefined results. 
+#define USB2_CONTROLLER_USB2D_USBCMD_0_IAA_SHIFT                        _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_IAA_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBCMD_0_IAA_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_IAA_RANGE                        6:6
+#define USB2_CONTROLLER_USB2D_USBCMD_0_IAA_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_IAA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_IAA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_IAA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_IAA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_IAA_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_IAA_SET                  _MK_ENUM_CONST(1)
+
+// Asynchronous Schedule Enable. This bit controls whether the host controller skips processing the Asynchronous Schedule. 
+// 0 = Do not process the Asynchronous Schedule. 
+// 1 = Use the ASYNCLISTADDR register to access the  Asynchronous Schedule. 
+// Only the host controller uses this bit. 
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASE_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBCMD_0_ASE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASE_RANGE                        5:5
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASE_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASE_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_ASE_ENABLE                       _MK_ENUM_CONST(1)
+
+// Periodic Schedule Enable.This bit controls whether the host controller skips processing the Periodic Schedule. 
+// 0 = Do not process the Periodic Schedule 
+// 1 = Use the PERIODICLISTBASE register to access the Periodic  Schedule. 
+// Only the host controller uses this bit. 
+#define USB2_CONTROLLER_USB2D_USBCMD_0_PSE_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_PSE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBCMD_0_PSE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_PSE_RANGE                        4:4
+#define USB2_CONTROLLER_USB2D_USBCMD_0_PSE_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_PSE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_PSE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_PSE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_PSE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_PSE_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_PSE_ENABLE                       _MK_ENUM_CONST(1)
+
+// Controller Reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. 
+// Host Controller: 
+// When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero.  Attempting to reset an actively running host controller results in undefined behavior.   
+// Device Controller: 
+// When software writes a one to this bit, the Device  Controller resets its internal pipelines, timers, counters, state machines  etc. to their initial value. Any transaction currently in progress on USB is  immediately terminated. Writing a one to this bit in device mode is not  recommended. 
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RST_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RST_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBCMD_0_RST_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RST_RANGE                        1:1
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RST_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RST_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RST_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RST_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RST_SET                  _MK_ENUM_CONST(1)
+
+// Run/Stop: 
+// Host Controller: 
+// When set to a 1, the Host Controller proceeds with the execution of the schedule.  
+// The Host Controller continues execution as long as this bit is set to a one.  When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts.  The HCHalted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state.  Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one). 
+// Device Controller: 
+// Writing a one to this bit will cause the device  controller to enable a pull-up on D+ and initiate an attach event. This  control bit is not directly connected to the pull-up enable, as the pull-up  will become disabled upon transitioning into high-speed mode. Software should  use this bit to prevent an attach event before the device controller has been  properly initialized. Writing a 0 to this will cause a detach event. 
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBCMD_0_RS_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RS_RANGE                 0:0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RS_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RS_STOP                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBCMD_0_RS_RUN                   _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_USBSTS_0  
+#define USB2_CONTROLLER_USB2D_USBSTS_0                  _MK_ADDR_CONST(0x144)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SECURE                   0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_WORD_COUNT                       0x1
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RESET_VAL                        _MK_MASK_CONST(0x1000)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RESET_MASK                       _MK_MASK_CONST(0xf1ff)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_READ_MASK                        _MK_MASK_CONST(0xf1ff)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_WRITE_MASK                       _MK_MASK_CONST(0xd1ef)
+// Asynchronous Schedule Status. This bit reports the current real status of the Asynchronous Schedule.  When set to zero the asynchronous schedule status is disabled and if set to one the status is enabled.  The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register.  
+// If AS = ASE: 
+// 1= Enable Asynchronous Schedule    0= Disable Asynchronous Schedule
+// Only used by the host controller. 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AS_SHIFT                 _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_AS_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AS_RANGE                 15:15
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AS_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AS_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AS_ENABLE                        _MK_ENUM_CONST(1)
+
+// Periodic Schedule Status. This bit reports the current real status of the Periodic Schedule.  When set to zero the periodic schedule is disabled, and if set to one the status is enabled.  
+// The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD register.  
+// If PS = PSE then:
+// 1 = Periodic Schedule is enabled or 0 = Periodic Schedule is disabled
+// Only used by the host controller. 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PS_SHIFT                 _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_PS_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PS_RANGE                 14:14
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PS_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PS_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PS_ENABLE                        _MK_ENUM_CONST(1)
+
+// Reclamation. This is a read-only status bit used to detect an  empty asynchronous schedule. Only used by the host controller. 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RCL_SHIFT                        _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RCL_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_RCL_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RCL_RANGE                        13:13
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RCL_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RCL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RCL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RCL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RCL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RCL_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_RCL_ENABLE                       _MK_ENUM_CONST(1)
+
+// HCHalted. 1 = Default. This bit is a zero  whenever the Run/Stop bit is a one. The Host Controller sets this bit to one  after it has stopped executing because of the Run/Stop bit being set to 0,  either by software or by the Host Controller hardware (e.g. internal error). Only  used by the host controller. 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_HCH_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_HCH_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_HCH_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_HCH_RANGE                        12:12
+#define USB2_CONTROLLER_USB2D_USBSTS_0_HCH_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_HCH_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_HCH_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_HCH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_HCH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_HCH_UNHALTED                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_HCH_HALTED                       _MK_ENUM_CONST(1)
+
+// DCSuspend. When a device controller enters a suspend state  from an active state, this bit will be set to a 1. The device controller  clears the bit upon exiting from a suspend state. Only used by the device  controller. 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SLI_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SLI_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_SLI_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SLI_RANGE                        8:8
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SLI_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SLI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SLI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SLI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SLI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SLI_NOTSUSPEND                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SLI_SUSPENDED                    _MK_ENUM_CONST(1)
+
+// SOF Received. When the device controller detects a Start Of (micro) Frame, this bit will be set to a one. When a SOF is extremely late, the device controller will automatically set this bit to indicate that an SOF was expected.  Therefore, this bit will be set roughly every 1ms in device FS mode and every 125us in HS mode and will be synchronized to the actual SOF that is received. Since device controller is initialized to FS before connect, this bit Will be set at an interval of 1ms during the prelude to the connect and chirp. In host mode, this bit will be set every 125us and can be used by host controller driver as a time base. 
+// Software writes a 1 to this bit to clear it. This  is a non-EHCI status bit. 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SRI_SHIFT                        _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SRI_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_SRI_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SRI_RANGE                        7:7
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SRI_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SRI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SRI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SRI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SRI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SRI_SOF_NOT_RCVD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SRI_SOF_RCVD                     _MK_ENUM_CONST(1)
+
+// USB Reset Received. When the device controller detects a USB Reset and  enters the default state, this bit is set to a 1. Software can write a 1 to  this bit to clear the USB Reset Received status bit. Only used by the device  controller. 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_URI_SHIFT                        _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_URI_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_URI_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_URI_RANGE                        6:6
+#define USB2_CONTROLLER_USB2D_USBSTS_0_URI_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_URI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_URI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_URI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_URI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_URI_NO_USB_RESET                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_URI_USB_RESET                    _MK_ENUM_CONST(1)
+
+// Interrupt and Asynchronous Advance. System software can force the host controller to  issue an interrupt the next time the host controller advances the  asynchronous schedule by writing a one to the Interrupt on Async Advance  Doorbell bit in the USBCMD register. This status bit indicates the assertion  of that interrupt source. Only used by the host controller
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AAI_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AAI_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_AAI_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AAI_RANGE                        5:5
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AAI_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AAI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AAI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AAI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AAI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AAI_NOT_ADVANCED                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_AAI_ADVANCED                     _MK_ENUM_CONST(1)
+
+// System Error. This bit is not used in this  implementation and will always be set to "0". 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SEI_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SEI_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_SEI_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SEI_RANGE                        4:4
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SEI_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SEI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SEI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SEI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SEI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SEI_NO_ERROR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_SEI_ERROR                        _MK_ENUM_CONST(1)
+
+// Frame List Rollover. The Host Controller sets this bit to a 1 when  the Frame List Index rolls over from its maximum value to 0. The exact  value at which the rollover occurs depends on the frame list size. For  example. If the frame list size (as programmed in the Frame List Size field  of the USBCMD register) is 1024, the Frame Index Register rolls over every  time FRINDEX [1 3] toggles. Similarly, if the size is 512, the Host  Controller sets this bit to a 1 every time FHINDEX [12] toggles. Only used  by the host controller. 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_FRI_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_FRI_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_FRI_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_FRI_RANGE                        3:3
+#define USB2_CONTROLLER_USB2D_USBSTS_0_FRI_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_FRI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_FRI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_FRI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_FRI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_FRI_NO_ROLLOVER                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_FRI_ROLLOVER                     _MK_ENUM_CONST(1)
+
+// Port Change Detect. The Host Controller sets this bit to a 1 when on  any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the  Force Port Resume bit is set as the result of a J-K transition on the  suspended port. The Device Controller sets this bit to a one when the port  controller enters the full or high-speed operational state. When the port  controller exits the full or high-speed operational states due to Reset or  Suspend events, the notification mechanisms are the USB Reset Received bit  and the DCSuspend bits respectively. This bit is not EHCI compatible. 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PCI_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PCI_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_PCI_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PCI_RANGE                        2:2
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PCI_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PCI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PCI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PCI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PCI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PCI_NO_PORT_CHANGE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_PCI_PORT_CHANGE                  _MK_ENUM_CONST(1)
+
+// USB Error Interrupt. This bit gets set by the Host/Device controller  when completion of a USB transaction results in an error condition. This bit  is set along with the USBINT bit, if the TD on which the error interrupt  occurred also ad its interrupt on complete (IOC) bit set. 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UEI_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UEI_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_UEI_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UEI_RANGE                        1:1
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UEI_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UEI_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UEI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UEI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UEI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UEI_NO_ERROR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UEI_ERROR                        _MK_ENUM_CONST(1)
+
+// USB Interrupt. This bit is set by the Host/Device Controller when  the cause of an interrupt is a completion of a USB transaction where the  Transfer Descriptor (TD) as an interrupt on complete (IOC) bit set. This bit  is also set by the Host/Device Controller when a short packet is detected. A  short packet is when the actual number of bytes received was less than the  expected number of bytes. 
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UI_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBSTS_0_UI_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UI_RANGE                 0:0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UI_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UI_NO_INT                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBSTS_0_UI_INT                   _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_USBINTR_0  
+#define USB2_CONTROLLER_USB2D_USBINTR_0                 _MK_ADDR_CONST(0x148)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SECURE                  0x0
+#define USB2_CONTROLLER_USB2D_USBINTR_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_USB2D_USBINTR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_RESET_MASK                      _MK_MASK_CONST(0x1ff)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_READ_MASK                       _MK_MASK_CONST(0x1ff)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_WRITE_MASK                      _MK_MASK_CONST(0x1ff)
+// Sleep Enable. 1 = Device controller issues an interrupt if  DCSuspend bit in USBSTS register transitions. 
+// The interrupt is acknowledged by SW by writing a 1 to the DCSuspend bit. Only used by the device controller. 
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SLE_SHIFT                       _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SLE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBINTR_0_SLE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SLE_RANGE                       8:8
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SLE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SLE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SLE_ENABLE                      _MK_ENUM_CONST(1)
+
+// SOF Received Enable. 1 = Device controller issues an interrupt if SOF Received bit in USBSTS register = 1.
+// The interrupt is acknowledged by software clearing  the SOF Received bit. 
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SRE_SHIFT                       _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SRE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBINTR_0_SRE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SRE_RANGE                       7:7
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SRE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SRE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SRE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SRE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SRE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SRE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SRE_ENABLE                      _MK_ENUM_CONST(1)
+
+// USB Reset Enable.1 = Device controller issues an interrupt if USB Reset Received bit in USBSTS register  = 1 
+// The interrupt is acknowledged by software clearing  the USB Reset Received bit. Only used by the device controller. 
+#define USB2_CONTROLLER_USB2D_USBINTR_0_URE_SHIFT                       _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_URE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBINTR_0_URE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_URE_RANGE                       6:6
+#define USB2_CONTROLLER_USB2D_USBINTR_0_URE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_USBINTR_0_URE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_URE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_URE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_URE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_URE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_URE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Interrupt on Asynchronous Advance Enable. 1 = the host controller issues an interrupt at the  next interrupt threshold if Interrupt on Async Advance bit in USBSTS register  = 1. 
+// The interrupt is acknowledged by software clearing the Interrupt on  Async Advance bit. Only used by the host controller. 
+#define USB2_CONTROLLER_USB2D_USBINTR_0_AAE_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_AAE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBINTR_0_AAE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_AAE_RANGE                       5:5
+#define USB2_CONTROLLER_USB2D_USBINTR_0_AAE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_USBINTR_0_AAE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_AAE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_AAE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_AAE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_AAE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_AAE_ENABLE                      _MK_ENUM_CONST(1)
+
+// System Error Enable. 1 = Host/device controller issues an interrupt if  the System Error bit in USBSTS register = 1.
+// The interrupt is acknowledged by  software clearing the System Error bit. 
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SEE_SHIFT                       _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SEE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBINTR_0_SEE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SEE_RANGE                       4:4
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SEE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SEE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SEE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SEE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SEE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SEE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_SEE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Frame List Rollover Enable. 1 = Host controller issues an interrupt if Frame  List Rollover bit in the USBSTS register = 1.
+// The interrupt is acknowledged  by software clearing the Frame List Rollover bit. Only used by the host  controller. 
+#define USB2_CONTROLLER_USB2D_USBINTR_0_FRE_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_FRE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBINTR_0_FRE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_FRE_RANGE                       3:3
+#define USB2_CONTROLLER_USB2D_USBINTR_0_FRE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_USBINTR_0_FRE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_FRE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_FRE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_FRE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_FRE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_FRE_ENABLE                      _MK_ENUM_CONST(1)
+
+// Port Change Detect Enable. 1 = Host/device controller issues an interrupt if  Port Change Detect bit in USBSTS register = 1. 
+// The interrupt is acknowledged  by software clearing the Port Change Detect bit.
+#define USB2_CONTROLLER_USB2D_USBINTR_0_PCE_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_PCE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBINTR_0_PCE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_PCE_RANGE                       2:2
+#define USB2_CONTROLLER_USB2D_USBINTR_0_PCE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_USBINTR_0_PCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_PCE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_PCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_PCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_PCE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_PCE_ENABLE                      _MK_ENUM_CONST(1)
+
+// USB Error Interrupt Enable. 1 = Host controller issues an interrupt at the  next interrupt threshold if the USBERRINT bit in USBSTS = 1. 
+// The interrupt is  acknowledged by software clearing the USBERRINT bit in the USBSTS register. 
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UEE_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UEE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBINTR_0_UEE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UEE_RANGE                       1:1
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UEE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UEE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UEE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UEE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UEE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UEE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UEE_ENABLE                      _MK_ENUM_CONST(1)
+
+// USB Interrupt Enable. 1 = Host/device issues an interrupt at the next  interrupt threshold if the USBINT bit in USBSTS = 1. 
+// The interrupt is  acknowledged by software clearing the USBINT bit.
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UE_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBINTR_0_UE_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UE_RANGE                        0:0
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UE_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UE_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBINTR_0_UE_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_FRINDEX_0  
+#define USB2_CONTROLLER_USB2D_FRINDEX_0                 _MK_ADDR_CONST(0x14c)
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_SECURE                  0x0
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_RESET_MASK                      _MK_MASK_CONST(0x3fff)
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_READ_MASK                       _MK_MASK_CONST(0x3fff)
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// Frame Index.  
+// The value in this register increments at the end of each time frame (micro-frame). 
+// Bits [N: 3] are used for the Frame List current index. Each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index.  
+// The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. 
+// USBCMD          [Frame List Size] Number        Elements N 
+//   000b                   (1024)                  12 
+//   001b                   (512)                   11 
+//   010b                   (256)                   10 
+//   011b                   (128)                   9 
+//   100b            (64)                    8 
+//   101b            (32)                    7 
+//   110b            (16)                    6 
+//   111b            (8)                     5 
+// In device mode the value is the current frame  number of the last frame transmitted. It is not used as an index. In either  mode bits 2:0 indicate the current micro-frame. 
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_FRINDEX_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_FRINDEX_FIELD                   (_MK_MASK_CONST(0x3fff) << USB2_CONTROLLER_USB2D_FRINDEX_0_FRINDEX_SHIFT)
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_FRINDEX_RANGE                   13:0
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_FRINDEX_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_FRINDEX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_FRINDEX_DEFAULT_MASK                    _MK_MASK_CONST(0x3fff)
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_FRINDEX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_FRINDEX_0_FRINDEX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Reserved address 336 [0x150] 
+
+// Register USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0  
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0                        _MK_ADDR_CONST(0x154)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_SECURE                         0x0
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_WORD_COUNT                     0x1
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_RESET_MASK                     _MK_MASK_CONST(0xfffff000)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_READ_MASK                      _MK_MASK_CONST(0xfffff000)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_WRITE_MASK                     _MK_MASK_CONST(0xfffff000)
+// Host mode: This 32-bit register contains the beginning address of the Periodic Frame List in the system memory.  HCD loads this register prior to starting the schedule execution by the Host Controller.  The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned.  The contents of this register are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence. 
+// Base Address (Low). These bits correspond to memory address signals [31:12], respectively. Only used by the host controller. 
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_BASEADR_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_BASEADR_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_BASEADR_SHIFT)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_BASEADR_RANGE                  31:12
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_BASEADR_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_BASEADR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_BASEADR_DEFAULT_MASK                   _MK_MASK_CONST(0xfffff)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_BASEADR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_BASEADR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Device mode. The upper seven bits of this register represent the device address. After any controller reset or a USB reset, the device address is set to the default address (0). The default address will match all incoming addresses. Software shall reprogram the address after receiving a SET_ADDRESS request. 
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_USBADR_SHIFT                   _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_USBADR_FIELD                   (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_USBADR_SHIFT)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_USBADR_RANGE                   31:25
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_USBADR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_USBADR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_USBADR_DEFAULT_MASK                    _MK_MASK_CONST(0x7f)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_USBADR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0_USBADR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0  
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0                   _MK_ADDR_CONST(0x158)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_SECURE                    0x0
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_RESET_MASK                        _MK_MASK_CONST(0xffffffe0)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_READ_MASK                         _MK_MASK_CONST(0xffffffe0)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffe0)
+// Host mode. This 32-bit register contains the address of the next asynchronous queue head to be executed by the host.
+// Link Pointer Low (LPL). These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (OH). Only used by the host controller.
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_ASYBASE_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_ASYBASE_FIELD                     (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_ASYBASE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_ASYBASE_RANGE                     31:5
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_ASYBASE_WOFFSET                   0x0
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_ASYBASE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_ASYBASE_DEFAULT_MASK                      _MK_MASK_CONST(0x7ffffff)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_ASYBASE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_ASYBASE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Device mode. This register contains the address of the top of the endpoint list in system memory. These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Heads (QH). Only used by the device controller.
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_EPBASE_SHIFT                      _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_EPBASE_FIELD                      (_MK_MASK_CONST(0x1fffff) << USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_EPBASE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_EPBASE_RANGE                      31:11
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_EPBASE_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_EPBASE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_EPBASE_DEFAULT_MASK                       _MK_MASK_CONST(0x1fffff)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_EPBASE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0_EPBASE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_ASYNCTTSTS_0  
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0                      _MK_ADDR_CONST(0x15c)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_RESET_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_READ_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_WRITE_MASK                   _MK_MASK_CONST(0x2)
+// Embedded TT Async Buffers Clear. (Read/Write to  set) This field will clear all pending transactions in the embedded TT Async  Buffer(s). The clear will take as much time as necessary to clear buffer  without interfering with a transaction in progress. TTAC will return to zero  after being set by software only after the actual clear occurs. 
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAC_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAC_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAC_SHIFT)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAC_RANGE                   1:1
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAC_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Embedded TT Async Buffers Status. (Read Only) This  read only bit will be 1 if one or more transactions are being held in the  embedded TT Async. Buffers. When this bit is a zero, then all outstanding  transactions in the embedded TT have been flushed. 
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAS_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAS_RANGE                   0:0
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ASYNCTTSTS_0_TTAS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_BURSTSIZE_0  
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0                       _MK_ADDR_CONST(0x160)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_SECURE                        0x0
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_RESET_VAL                     _MK_MASK_CONST(0x808)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_RESET_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_READ_MASK                     _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_WRITE_MASK                    _MK_MASK_CONST(0xffff)
+// Programmable TX Burst Length.  (Read/Write) This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus.
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_TXPBURST_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_TXPBURST_FIELD                        (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_BURSTSIZE_0_TXPBURST_SHIFT)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_TXPBURST_RANGE                        15:8
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_TXPBURST_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_TXPBURST_DEFAULT                      _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_TXPBURST_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_TXPBURST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_TXPBURST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Programmable RX Burst Length.  (Read/Write) This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory.
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_RXPBURST_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_RXPBURST_FIELD                        (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_BURSTSIZE_0_RXPBURST_SHIFT)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_RXPBURST_RANGE                        7:0
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_RXPBURST_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_RXPBURST_DEFAULT                      _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_RXPBURST_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_RXPBURST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_BURSTSIZE_0_RXPBURST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_USB2D_TXFILLTUNING_0  
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0                    _MK_ADDR_CONST(0x164)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_SECURE                     0x0
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_RESET_VAL                  _MK_MASK_CONST(0x20000)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_RESET_MASK                         _MK_MASK_CONST(0x3f1fff)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_READ_MASK                  _MK_MASK_CONST(0x3f1fff)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_WRITE_MASK                         _MK_MASK_CONST(0x3f1fff)
+// FIFO Burst Threshold.  (Read/Write) This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus.  The minimum value is 2 and this value should be a low as possible to maximize USB performance.  A higher value can be used in systems with unpredicable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory.  This value is ignored if the Stream Disable bit in USBMODE register is set.
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXFIFOTHRES_FIELD                  (_MK_MASK_CONST(0x3f) << USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SHIFT)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXFIFOTHRES_RANGE                  21:16
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXFIFOTHRES_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXFIFOTHRES_DEFAULT                        _MK_MASK_CONST(0x2)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXFIFOTHRES_DEFAULT_MASK                   _MK_MASK_CONST(0x3f)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Scheduler Health Counter.  (Read/Write To Clear)  [Default = 0] This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame.
+// This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH.  Writing to this register will clear the counter and this counter will max. at 31.
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHHEALTH_FIELD                  (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHHEALTH_RANGE                  12:8
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHHEALTH_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHHEALTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHHEALTH_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Scheduler Overhead.  (Read/Write)  [Default = 0] This register adds an additional fixed offset to the schedule time estimator described above as Tff.  As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus.  Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization.
+// The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode.
+// The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHOH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHOH_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHOH_SHIFT)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHOH_RANGE                      7:0
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHOH_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHOH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHOH_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHOH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_TXFILLTUNING_0_TXSCHOH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 384 [0x180] 
+
+// Register USB2_CONTROLLER_USB2D_PORTSC1_0  
+#define USB2_CONTROLLER_USB2D_PORTSC1_0                 _MK_ADDR_CONST(0x184)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SECURE                  0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_RESET_VAL                       _MK_MASK_CONST(0x1004)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_RESET_MASK                      _MK_MASK_CONST(0xed7fffff)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_READ_MASK                       _MK_MASK_CONST(0xed7fffff)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WRITE_MASK                      _MK_MASK_CONST(0x17f114e)
+// 0 = UTMI interface. This is the only value  supported. This bit is not defined in the EHCI specification. 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTS_SHIFT                       _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_PTS_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTS_RANGE                       31:31
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTS_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTS_UTMI                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTS_RESERVED                    _MK_ENUM_CONST(1)
+
+// 0 = Serial transceiver not selected. This is the  only value supported. This bit is not defined in the EHCI specification. 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_STS_SHIFT                       _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_STS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_STS_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_STS_RANGE                       30:30
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_STS_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_STS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_STS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_STS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_STS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_STS_PARALLEL_IF                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_STS_SERIAL_IF                   _MK_ENUM_CONST(1)
+
+// Parallel Transceiver Width. Fixed to 0. This bit is not defined in the EHCI specification.  
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTW_SHIFT                       _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTW_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_PTW_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTW_RANGE                       29:29
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTW_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTW_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTW_EIGHT_BIT                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTW_RESERVED                    _MK_ENUM_CONST(1)
+
+// This register field indicates the speed at which the port is operating. 
+// 00 = Full Speed
+// 01 = Low Speed
+// 10 = High Speed 
+// This bit is not defined in the EHCI specification.  
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_SHIFT                      _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_FIELD                      (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_RANGE                      27:26
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_FULL_SPEED                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_LOW_SPEED                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_HIGH_SPEED                 _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PSPD_RESERVED                   _MK_ENUM_CONST(3)
+
+// Port Force Full Speed Connect: Writing this bit to a 1b forces the port to connect at Full Speed only. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. This bit is not defined in the EHCI specification.
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PFSC_SHIFT                      _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PFSC_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_PFSC_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PFSC_RANGE                      24:24
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PFSC_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PFSC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PFSC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PFSC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PFSC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PFSC_DONT_FORCE_FULL_SPEED                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PFSC_FORCE_FULL_SPEED                   _MK_ENUM_CONST(1)
+
+// Default = 0b. Wake on Over-current Enable: Writing this bit to a one enables  the port to be sensitive to over-current conditions as wake-up events. This  field is zero if Port Power(PP) is zero. This bit should only be used when  operating in Host mode. Writing this bit to 1 while the controller is working  in device mode can result in undefined behavior.
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKOC_SHIFT                      _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKOC_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_WKOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKOC_RANGE                      22:22
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKOC_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKOC_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKOC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKOC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKOC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKOC_DISBLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKOC_ENABLE                     _MK_ENUM_CONST(1)
+
+// Wake on Disconnect Enable: Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power(PP) is zero or in device mode. 
+// This bit should only be used when operating in Host mode. Writing this bit to 1 while the controller is working in device mode can result in undefined behaviour. 
+// This bit should not be written to 1 if there is no  device connected. After the device disconnect is detected, this bit should be  cleared to 0.
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKDS_SHIFT                      _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKDS_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_WKDS_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKDS_RANGE                      21:21
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKDS_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKDS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKDS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKDS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKDS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKDS_DISBLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKDS_ENABLE                     _MK_ENUM_CONST(1)
+
+// Wake on Connect Enable: Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PP) is zero or in device mode. 
+// This bit should only be used when operating in Host mode. Writing this bit to 1 while the controller is working in device mode can result in undefined behaviour. 
+// This bit should not be written to 1 while the  device is connected. After the device connection is detected, this bit should  be cleared to 0.
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKCN_SHIFT                      _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKCN_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_WKCN_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKCN_RANGE                      20:20
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKCN_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKCN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKCN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKCN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKCN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKCN_DISBLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_WKCN_ENABLE                     _MK_ENUM_CONST(1)
+
+// Port Test Control: Any other value than zero indicates that the port is operating in test mode. 
+//   Value                  Specific Test 
+//  0000b                Not enabled 
+//  0001b                  J_ STATE 
+//  0010b             K_STATE 
+//  0011b              SEQ_NAK 
+//  0100b              Packet 
+//  0101b               FORCE_ENABLE 
+//  0110b to 1111b         Reserved 
+// Refer to Chapter 7 of the USB Specification  Revision 2.0 for details on each test mode. 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_RANGE                       19:16
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_NORMAL_OP                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_TEST_J                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_TEST_K                      _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_TEST_SE0_NAK                        _MK_ENUM_CONST(3)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_TEST_PKT                    _MK_ENUM_CONST(4)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PTC_TEST_FORCE_ENABLE                   _MK_ENUM_CONST(5)
+
+// Port Indicator Control: This field is not supported in the current  implementation. Please use a GPIO if you wish to use Port Indicators.
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PIC_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PIC_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_PORTSC1_0_PIC_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PIC_RANGE                       15:14
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PIC_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PIC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PIC_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PIC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PIC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Port Owner. Port owner handoff is not implemented in this design, therefore this bit will  always be 0. 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PO_SHIFT                        _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PO_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_PO_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PO_RANGE                        13:13
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PO_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PO_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PO_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PO_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PO_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Port Power: The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: 
+// PPC                       PP  Operation 
+// 0b                           0b Read Only. A device controller with no OTG capability does not have port power control switches. 
+// 1b                          1b/0b RW.  Host/OTG controller requires port power control switches. 
+// This bit represents the current setting of the switch (0=off, 1=on).  When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. 
+// When an over-current condition is detected on a  powered port and PPC is a one, the PP bit in each affected port may be  transitioned by the host controller driver from a one to a zero (removing  power from the port). 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PP_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PP_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_PP_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PP_RANGE                        12:12
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PP_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PP_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PP_NOT_POWERED                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PP_POWERED                      _MK_ENUM_CONST(1)
+
+// Line state. These bits reflect the current logical levels of the D+ (bit 10) and D- (bit 11) signal lines. The encoding of the bits are:
+// 00b = SE0 
+// 01b = J-state 
+// 10b = K-state 
+// 11b = Undefined 
+// The value of this field is undefined if Port  Power(PP) is zero in host mode. In host mode, the use  of line-state by the host controller driver is not necessary (unlike EHCI),  because the port controller state machine and the port routing manage the  connection of LS and FS. In device mode, the use of line-state by the device  controller driver is not necessary. 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_SHIFT                        _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_FIELD                        (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_PORTSC1_0_LS_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_RANGE                        11:10
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_SE0                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_J_STATE                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_K_STATE                      _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_LS_UNDEFINED                    _MK_ENUM_CONST(3)
+
+// When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the host/device connected to the port is not in a high-speed mode. 
+// Note: HSP is redundant with PSPD(27:26). 
+// This bit is not defined in the EHCI specification.
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_HSP_SHIFT                       _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_HSP_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_HSP_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_HSP_RANGE                       9:9
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_HSP_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_HSP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_HSP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_HSP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_HSP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_HSP_NOT_HIGH_SPEED                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_HSP_HIGH_SPEED                  _MK_ENUM_CONST(1)
+
+// This field is zero if Port Power(PP) is zero. 
+// In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset.
+// When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver.  
+// In Device Mode: This bit is a read only status  bit. Device reset from the USB bus is also indicated in the USBSTS register. 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PR_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PR_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_PR_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PR_RANGE                        8:8
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PR_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PR_NOT_USB_RESET                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PR_USB_RESET                    _MK_ENUM_CONST(1)
+
+// Port suspend. 1=Port in suspend state. 0=Port not in suspend state. 
+// In Host Mode: Read/Write. 
+// Port Enabled Bit and Suspend bit of this register define the port states as follows: 
+// Bits [Port Enabled, Suspend]    Port State 
+//        0x                        Disable 
+//   10                        Enable 
+//    11                        Suspend 
+// When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. A write of zero to this bit is ignored by the host controller. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This field is zero if Port Power(PP) is zero in host mode.
+// In Device Mode: Read Only. This bit is a read only status bit. 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SUSP_SHIFT                      _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SUSP_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_SUSP_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SUSP_RANGE                      7:7
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SUSP_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SUSP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SUSP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SUSP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SUSP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SUSP_NOT_SUSPEND                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_SUSP_SUSPEND                    _MK_ENUM_CONST(1)
+
+// Force Port Resume. 1= Resume detected/driven on port. 0=No resume (K state) detected/driven on port. 
+// In Host Mode: 
+// Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one.  This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. 
+// Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one.  This bit remains a one until the port has switched to the high-speed idle.  Writing a zero has no effect because the port controller will time the resume operation to clear the bit when the port control state switches to HS or FS idle. This field is zero if Port Power(PP) is zero in host mode. This bit is not-EHCI compatible. 
+// In Device mode:  
+// After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. 
+// Software should ensure that the PHY clock is operational before writing a 1 to this bit to start the resume sequence. This is true for both Device and Host modes.
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_FPR_SHIFT                       _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_FPR_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_FPR_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_FPR_RANGE                       6:6
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_FPR_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_FPR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_FPR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_FPR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_FPR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_FPR_NO_RESUME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_FPR_RESUME                      _MK_ENUM_CONST(1)
+
+// Over-current Change: Not supported
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCC_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCC_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_OCC_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCC_RANGE                       5:5
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCC_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCC_NO_CHANGE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCC_CHANGE                      _MK_ENUM_CONST(1)
+
+// Over-current Active: Not supported
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCA_SHIFT                       _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCA_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_OCA_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCA_RANGE                       4:4
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCA_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCA_NO_OVER_CURRENT                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_OCA_OVER_CURRENT                        _MK_ENUM_CONST(1)
+
+// Port Enable/Disable Change: 1=Port enabled/disabled status has changed. 0=No change.
+// In Host Mode: 
+// For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This field is zero if Port Power(PP) is zero. 
+// In Device mode:  
+// The device port is always enabled. (This bit will  be zero) 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PEC_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PEC_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_PEC_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PEC_RANGE                       3:3
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PEC_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PEC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PEC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PEC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PEC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PEC_NO_CHANGE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PEC_CHANGE                      _MK_ENUM_CONST(1)
+
+// Port Enabled/Disabled: 1=Enable. 0=Disable (default)
+// In Host Mode: 
+// Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events.  When the port is disabled, (0b) downstream propagation of data is blocked except for reset. This field is zero if Port Power(PP) is zero in host mode. 
+// In Device Mode: 
+// The device port is always enabled. (This bit will  be one) 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PE_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_PE_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PE_RANGE                        2:2
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PE_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PE_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PE_PORT_DISABLED                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_PE_PORT_ENABLED                 _MK_ENUM_CONST(1)
+
+// Connect Status Change: 1 =Change in Current Connect Status. 0=No change (default) 
+// In Host Mode: 
+// Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (i.e., the bit will remain set).  Software clears this bit by writing a one to it. This field is zero if Port Power(PP) is zero in host mode. 
+// This bit is undefined in device controller mode. 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CSC_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CSC_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_CSC_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CSC_RANGE                       1:1
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CSC_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CSC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CSC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CSC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CSC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CSC_NO_CHANGE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CSC_CHANGE                      _MK_ENUM_CONST(1)
+
+// Current Connect Status: 
+// In Host Mode: 1=Device is present on port.                0=No device is present (default) 
+// This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power(PP) is zero in host mode. 
+// In Device Mode: 1=Attached                    0=Not Attached (default) 
+// A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. 
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CCS_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CCS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_PORTSC1_0_CCS_SHIFT)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CCS_RANGE                       0:0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CCS_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CCS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CCS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CCS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CCS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CCS_NOT_CONNECTED                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_PORTSC1_0_CCS_CONNECTED                   _MK_ENUM_CONST(1)
+
+
+// Reserved address 416 [0x1a0] 
+
+// Register USB2_CONTROLLER_USB2D_OTGSC_0  
+#define USB2_CONTROLLER_USB2D_OTGSC_0                   _MK_ADDR_CONST(0x1a4)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_SECURE                    0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_USB2D_OTGSC_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_RESET_MASK                        _MK_MASK_CONST(0x7f7f7f1b)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_READ_MASK                         _MK_MASK_CONST(0x7f7f7f1b)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_WRITE_MASK                        _MK_MASK_CONST(0x7f7f001b)
+// Data Pulse Interrupt Enable. Setting this bit enables the Data pulse interrupt.
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIE_SHIFT                        _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_DPIE_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIE_RANGE                        30:30
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIE_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIE_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIE_ENABLE                       _MK_ENUM_CONST(1)
+
+// 1 millisecond timer Interrupt enable. Setting this bit enables the 1 millisecond timer  interrupt.
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSE_SHIFT                      _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSE_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSE_RANGE                      29:29
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSE_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSE_ENABLE                     _MK_ENUM_CONST(1)
+
+// B Session End Interrupt Enable. Setting this bit enables the B session end  interrupt
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIE_SHIFT                       _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_BSEIE_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIE_RANGE                       28:28
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIE_ENABLE                      _MK_ENUM_CONST(1)
+
+// B Session Valid Interrupt Enable. Setting this bit enables the B session valid  interrupt
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIE_SHIFT                       _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_BSVIE_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIE_RANGE                       27:27
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIE_ENABLE                      _MK_ENUM_CONST(1)
+
+// A Session Valid Interrupt Enable. Setting this bit enables the A session valid  interrupt
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIE_SHIFT                       _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_ASVIE_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIE_RANGE                       26:26
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIE_ENABLE                      _MK_ENUM_CONST(1)
+
+// A VBus Valid Interrupt Enable. Setting this bit enables the A VBus valid  interrupt
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIE_SHIFT                       _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_AVVIE_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIE_RANGE                       25:25
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIE_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIE_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIE_ENABLE                      _MK_ENUM_CONST(1)
+
+// USB ID Interrupt Enable. Setting this bit enables the USB ID interrupt
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIE_SHIFT                        _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_IDIE_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIE_RANGE                        24:24
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIE_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIE_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIE_ENABLE                       _MK_ENUM_CONST(1)
+
+// Data Pulse Interrupt Status. This bit is set when data bus pulsing occurs on DP or DM.  Data bus pulsing is only detected when USBMODE.CM = Host (11) and PORTSC(0).PortPower = Off (0). Software writes a 1 to clear this bit.
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIS_SHIFT                        _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIS_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_DPIS_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIS_RANGE                        22:22
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIS_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIS_INT_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPIS_INT_SET                      _MK_ENUM_CONST(1)
+
+// 1 millisecond timer Interrupt Status: This bit is set once every millisecond. Software  writes a 1 to clear it.
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSS_SHIFT                      _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSS_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSS_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSS_RANGE                      21:21
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSS_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSS_INT_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMSS_INT_SET                    _MK_ENUM_CONST(1)
+
+// B Session End Interrupt Status. This bit is set when VBus has fallen below the B  session end threshold. Software writes a 1 to clear this bit .
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIS_SHIFT                       _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_BSEIS_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIS_RANGE                       20:20
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIS_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIS_INT_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSEIS_INT_SET                     _MK_ENUM_CONST(1)
+
+// B Session Valid Interrupt Status. This bit is set when VBus has either risen above  or fallen below the B session valid threshold (0.8 VDC). Software writes a 1  to clear this bit. 
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIS_SHIFT                       _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_BSVIS_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIS_RANGE                       19:19
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIS_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIS_INT_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSVIS_INT_SET                     _MK_ENUM_CONST(1)
+
+// A Session Valid Interrupt Status. This bit is set when VBus has either risen above  or fallen below the A session valid threshold (0.8 VDC). Software writes a  one to clear this bit. 
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIS_SHIFT                       _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_ASVIS_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIS_RANGE                       18:18
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIS_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIS_INT_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASVIS_INT_SET                     _MK_ENUM_CONST(1)
+
+// A VBus Valid Interrupt Status. This bit is set when VBus has either risen above  or fallen below the VBus valid threshold (4.4 VDC) on an A device. Software  writes a 1 to clear this bit. 
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIS_SHIFT                       _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_AVVIS_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIS_RANGE                       17:17
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIS_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIS_INT_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVVIS_INT_SET                     _MK_ENUM_CONST(1)
+
+// USB ID Interrupt Status. This bit is set when a change on the ID input has been detected. Software writes a 1 to clear this bit. 
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIS_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIS_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_IDIS_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIS_RANGE                        16:16
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIS_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIS_INT_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_IDIS_INT_SET                      _MK_ENUM_CONST(1)
+
+// Data Bus Pulsing Status. A 1 indicates data bus pulsing is being detected  on the port. 
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPS_SHIFT                 _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_DPS_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPS_RANGE                 14:14
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPS_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPS_STS_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DPS_STS_SET                       _MK_ENUM_CONST(1)
+
+// 1 millisecond timer toggle. This bit toggles once per millisecond
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMST_SHIFT                      _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMST_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_ONEMST_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMST_RANGE                      13:13
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMST_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMST_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMST_STS_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ONEMST_STS_SET                    _MK_ENUM_CONST(1)
+
+// B session End. Indicates VBus is below the B session end  threshold
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSE_SHIFT                 _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_BSE_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSE_RANGE                 12:12
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSE_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSE_STS_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSE_STS_SET                       _MK_ENUM_CONST(1)
+
+// B Session Valid. Indicates VBus is above the B session valid  threshold
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSV_SHIFT                 _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSV_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_BSV_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSV_RANGE                 11:11
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSV_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSV_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSV_STS_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_BSV_STS_SET                       _MK_ENUM_CONST(1)
+
+// A Session Valid. Indicates VBus is above the A session valid  threshold
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASV_SHIFT                 _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASV_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_ASV_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASV_RANGE                 10:10
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASV_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASV_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASV_STS_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ASV_STS_SET                       _MK_ENUM_CONST(1)
+
+// A VBus Valid. Indicates VBus is above the A VBus valid threshold
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVV_SHIFT                 _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVV_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_AVV_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVV_RANGE                 9:9
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVV_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVV_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVV_STS_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_AVV_STS_SET                       _MK_ENUM_CONST(1)
+
+// USB ID: 0 = A-device  1 = B-device
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ID_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ID_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_ID_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ID_RANGE                  8:8
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ID_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ID_A_DEV                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_ID_B_DEV                  _MK_ENUM_CONST(1)
+
+// Data Pulsing. Setting this bit causes the pull-up on DP to be  asserted for data pulsing during SRP. 
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DP_SHIFT                  _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DP_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_DP_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DP_RANGE                  4:4
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DP_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DP_NO_DATA_PULSE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_DP_DATA_PULSE                     _MK_ENUM_CONST(1)
+
+// OTG Termination. This bit must be set when the OTG device is in device mode, this controls the pulldown on DM. 
+#define USB2_CONTROLLER_USB2D_OTGSC_0_OT_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_OT_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_OT_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_OT_RANGE                  3:3
+#define USB2_CONTROLLER_USB2D_OTGSC_0_OT_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_OT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_OT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_OT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_OT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_OT_NO_OTG_TERM                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_OT_OTG_TERM                       _MK_ENUM_CONST(1)
+
+// VBUS Charge. Setting this bit causes the VBus line to be  charged. This is used for VBus pulsing during SRP. 
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VC_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VC_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_VC_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VC_RANGE                  1:1
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VC_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VC_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VC_NO_VBUS_CHRG                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VC_VBUS_CHRG                      _MK_ENUM_CONST(1)
+
+// VBUS_Discharge. Read/write. Setting this bit  causes Vbus to discharge through a resistor. 
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VD_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_OTGSC_0_VD_SHIFT)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VD_RANGE                  0:0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VD_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VD_NO_VBUS_DISCHRG                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_OTGSC_0_VD_VBUS_DISCHRG                   _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_USBMODE_0  
+#define USB2_CONTROLLER_USB2D_USBMODE_0                 _MK_ADDR_CONST(0x1a8)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SECURE                  0x0
+#define USB2_CONTROLLER_USB2D_USBMODE_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_USB2D_USBMODE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_RESET_MASK                      _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_READ_MASK                       _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// Stream disbable: 1 Streaming is disabled - helpful to avoid overrun/underruns when system load is too high.
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SDIS_SHIFT                      _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SDIS_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBMODE_0_SDIS_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SDIS_RANGE                      4:4
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SDIS_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SDIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SDIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SDIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SDIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SDIS_STREAM_ENABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SDIS_STREAM_DISABLE                     _MK_ENUM_CONST(1)
+
+// Setup Lockout Mode:
+// In device mode, this bit controls the behavior of the setup lockout mechanism.
+// 0 - Setup lockout is ON (default)
+// 1  Setup lockout is OFF. Firmware requires the  use of setup tripwire semaphore in USB2D_USBCMD register.
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SLOM_SHIFT                      _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SLOM_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBMODE_0_SLOM_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SLOM_RANGE                      3:3
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SLOM_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SLOM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SLOM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SLOM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SLOM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SLOM_LOCKOUT_OFF                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_SLOM_LOCKOUT_ON                 _MK_ENUM_CONST(1)
+
+// Endian Select: Note: For this implementation, this should be  always set to 0 (little endian).
+#define USB2_CONTROLLER_USB2D_USBMODE_0_ES_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_ES_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_USBMODE_0_ES_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_ES_RANGE                        2:2
+#define USB2_CONTROLLER_USB2D_USBMODE_0_ES_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBMODE_0_ES_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_ES_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_ES_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_ES_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_ES_LITTLE_ENDIAN                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_ES_RESERVED                     _MK_ENUM_CONST(1)
+
+// Controller Mode: The controller mode will default to an idle state and will need to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. 
+// 00 = Idle [Default] 
+// 01 = Reserved 
+// 10 = Device Controller  
+// 11 = Host Controller 
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_FIELD                        (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_USBMODE_0_CM_SHIFT)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_RANGE                        1:0
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_IDLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_RESERVED                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_DEVICE_MODE                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_USBMODE_0_CM_HOST_MODE                    _MK_ENUM_CONST(3)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0  
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0                  _MK_ADDR_CONST(0x1ac)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_SECURE                   0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_WORD_COUNT                       0x1
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Endpoint 15 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SHIFT                   _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_RANGE                   15:15
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_NOT_RCVD                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SETUP_RCVD                      _MK_ENUM_CONST(1)
+
+// Endpoint 14 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SHIFT                   _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_RANGE                   14:14
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_NOT_RCVD                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SETUP_RCVD                      _MK_ENUM_CONST(1)
+
+// Endpoint 13 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SHIFT                   _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_RANGE                   13:13
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_NOT_RCVD                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SETUP_RCVD                      _MK_ENUM_CONST(1)
+
+// Endpoint 12 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_RANGE                   12:12
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_NOT_RCVD                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SETUP_RCVD                      _MK_ENUM_CONST(1)
+
+// Endpoint 11 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SHIFT                   _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_RANGE                   11:11
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_NOT_RCVD                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SETUP_RCVD                      _MK_ENUM_CONST(1)
+
+// Endpoint 10 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SHIFT                   _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_RANGE                   10:10
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_NOT_RCVD                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SETUP_RCVD                      _MK_ENUM_CONST(1)
+
+// Endpoint 9 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SHIFT                    _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_RANGE                    9:9
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_NOT_RCVD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SETUP_RCVD                       _MK_ENUM_CONST(1)
+
+// Endpoint 8 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_RANGE                    8:8
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_NOT_RCVD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SETUP_RCVD                       _MK_ENUM_CONST(1)
+
+// Endpoint 7 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_RANGE                    7:7
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_NOT_RCVD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SETUP_RCVD                       _MK_ENUM_CONST(1)
+
+// Endpoint 6 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_RANGE                    6:6
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_NOT_RCVD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SETUP_RCVD                       _MK_ENUM_CONST(1)
+
+// Endpoint 5 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_RANGE                    5:5
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_NOT_RCVD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SETUP_RCVD                       _MK_ENUM_CONST(1)
+
+// Endpoint 4 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SHIFT                    _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_RANGE                    4:4
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_NOT_RCVD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SETUP_RCVD                       _MK_ENUM_CONST(1)
+
+// Endpoint 3 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SHIFT                    _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_RANGE                    3:3
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_NOT_RCVD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SETUP_RCVD                       _MK_ENUM_CONST(1)
+
+// Endpoint 2 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_RANGE                    2:2
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_NOT_RCVD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SETUP_RCVD                       _MK_ENUM_CONST(1)
+
+// Endpoint 1 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_RANGE                    1:1
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_NOT_RCVD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SETUP_RCVD                       _MK_ENUM_CONST(1)
+
+// Endpoint 0 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_RANGE                    0:0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_NOT_RCVD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SETUP_RCVD                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTPRIME_0  
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0                      _MK_ADDR_CONST(0x1b0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB15_SHIFT                 _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB15_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB15_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB15_RANGE                 31:31
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB15_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB15_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB15_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB14_SHIFT                 _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB14_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB14_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB14_RANGE                 30:30
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB14_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB14_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB14_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB13_SHIFT                 _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB13_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB13_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB13_RANGE                 29:29
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB13_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB13_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB13_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB12_SHIFT                 _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB12_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB12_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB12_RANGE                 28:28
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB12_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB12_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB12_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB11_SHIFT                 _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB11_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB11_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB11_RANGE                 27:27
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB11_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB11_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB11_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB10_SHIFT                 _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB10_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB10_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB10_RANGE                 26:26
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB10_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB10_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB10_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB9_SHIFT                  _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB9_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB9_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB9_RANGE                  25:25
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB9_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB9_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB9_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB8_SHIFT                  _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB8_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB8_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB8_RANGE                  24:24
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB8_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB8_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB8_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB7_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB7_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB7_RANGE                  23:23
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB7_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB7_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB7_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB6_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB6_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB6_RANGE                  22:22
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB6_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB6_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB6_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB5_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB5_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB5_RANGE                  21:21
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB5_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB5_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB5_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB4_SHIFT                  _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB4_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB4_RANGE                  20:20
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB4_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB4_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB4_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB3_SHIFT                  _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB3_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB3_RANGE                  19:19
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB3_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB3_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB3_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB2_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB2_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB2_RANGE                  18:18
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB2_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB2_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB2_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB1_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB1_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB1_RANGE                  17:17
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB1_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB1_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB1_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB0_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB0_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB0_RANGE                  16:16
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB0_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB0_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PETB0_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB15_SHIFT                 _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB15_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB15_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB15_RANGE                 15:15
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB15_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB15_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB15_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB14_SHIFT                 _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB14_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB14_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB14_RANGE                 14:14
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB14_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB14_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB14_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB13_SHIFT                 _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB13_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB13_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB13_RANGE                 13:13
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB13_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB13_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB13_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB12_SHIFT                 _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB12_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB12_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB12_RANGE                 12:12
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB12_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB12_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB12_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB11_SHIFT                 _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB11_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB11_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB11_RANGE                 11:11
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB11_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB11_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB11_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB10_SHIFT                 _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB10_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB10_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB10_RANGE                 10:10
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB10_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB10_DONT_PRIME                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB10_PRIME                 _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB9_SHIFT                  _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB9_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB9_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB9_RANGE                  9:9
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB9_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB9_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB9_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB8_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB8_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB8_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB8_RANGE                  8:8
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB8_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB8_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB8_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB7_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB7_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB7_RANGE                  7:7
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB7_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB7_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB7_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB6_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB6_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB6_RANGE                  6:6
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB6_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB6_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB6_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB5_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB5_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB5_RANGE                  5:5
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB5_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB5_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB5_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB4_SHIFT                  _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB4_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB4_RANGE                  4:4
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB4_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB4_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB4_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB3_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB3_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB3_RANGE                  3:3
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB3_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB3_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB3_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB2_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB2_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB2_RANGE                  2:2
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB2_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB2_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB2_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB1_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB1_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB1_RANGE                  1:1
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB1_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB1_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB1_PRIME                  _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB0_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB0_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB0_RANGE                  0:0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB0_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB0_DONT_PRIME                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTPRIME_0_PERB0_PRIME                  _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTFLUSH_0  
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0                      _MK_ADDR_CONST(0x1b4)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB15_SHIFT                 _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB15_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB15_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB15_RANGE                 31:31
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB15_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB15_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB15_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB14_SHIFT                 _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB14_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB14_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB14_RANGE                 30:30
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB14_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB14_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB14_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB13_SHIFT                 _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB13_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB13_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB13_RANGE                 29:29
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB13_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB13_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB13_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB12_SHIFT                 _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB12_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB12_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB12_RANGE                 28:28
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB12_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB12_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB12_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB11_SHIFT                 _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB11_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB11_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB11_RANGE                 27:27
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB11_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB11_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB11_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB10_SHIFT                 _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB10_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB10_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB10_RANGE                 26:26
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB10_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB10_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB10_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB9_SHIFT                  _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB9_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB9_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB9_RANGE                  25:25
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB9_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB9_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB9_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB8_SHIFT                  _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB8_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB8_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB8_RANGE                  24:24
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB8_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB8_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB8_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB7_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB7_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB7_RANGE                  23:23
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB7_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB7_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB7_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB6_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB6_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB6_RANGE                  22:22
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB6_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB6_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB6_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB5_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB5_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB5_RANGE                  21:21
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB5_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB5_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB5_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB4_SHIFT                  _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB4_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB4_RANGE                  20:20
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB4_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB4_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB4_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB3_SHIFT                  _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB3_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB3_RANGE                  19:19
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB3_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB3_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB3_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB2_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB2_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB2_RANGE                  18:18
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB2_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB2_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB2_FLUSH                  _MK_ENUM_CONST(1)
+
+// 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB1_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB1_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB1_RANGE                  17:17
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB1_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB1_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB1_FLUSH                  _MK_ENUM_CONST(1)
+
+//
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB0_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB0_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB0_RANGE                  16:16
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB0_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB0_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FETB0_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB15_SHIFT                 _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB15_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB15_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB15_RANGE                 15:15
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB15_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB15_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB15_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB14_SHIFT                 _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB14_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB14_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB14_RANGE                 14:14
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB14_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB14_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB14_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB13_SHIFT                 _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB13_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB13_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB13_RANGE                 13:13
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB13_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB13_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB13_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB12_SHIFT                 _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB12_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB12_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB12_RANGE                 12:12
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB12_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB12_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB12_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB11_SHIFT                 _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB11_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB11_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB11_RANGE                 11:11
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB11_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB11_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB11_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB10_SHIFT                 _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB10_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB10_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB10_RANGE                 10:10
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB10_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB10_DONT_FLUSH                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB10_FLUSH                 _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB9_SHIFT                  _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB9_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB9_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB9_RANGE                  9:9
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB9_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB9_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB9_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB8_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB8_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB8_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB8_RANGE                  8:8
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB8_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB8_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB8_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB7_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB7_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB7_RANGE                  7:7
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB7_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB7_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB7_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB6_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB6_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB6_RANGE                  6:6
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB6_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB6_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB6_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB5_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB5_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB5_RANGE                  5:5
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB5_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB5_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB5_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB4_SHIFT                  _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB4_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB4_RANGE                  4:4
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB4_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB4_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB4_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB3_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB3_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB3_RANGE                  3:3
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB3_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB3_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB3_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB2_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB2_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB2_RANGE                  2:2
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB2_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB2_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB2_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB1_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB1_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB1_RANGE                  1:1
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB1_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB1_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB1_FLUSH                  _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB0_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB0_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB0_RANGE                  0:0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB0_WOFFSET                        0x0
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB0_DONT_FLUSH                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTFLUSH_0_FERB0_FLUSH                  _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTSTATUS_0  
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0                     _MK_ADDR_CONST(0x1b8)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_SECURE                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR15_SHIFT                        _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR15_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR15_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR15_RANGE                        31:31
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR15_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR15_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR15_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR14_SHIFT                        _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR14_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR14_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR14_RANGE                        30:30
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR14_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR14_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR14_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR13_SHIFT                        _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR13_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR13_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR13_RANGE                        29:29
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR13_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR13_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR13_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR12_SHIFT                        _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR12_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR12_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR12_RANGE                        28:28
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR12_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR12_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR12_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR11_SHIFT                        _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR11_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR11_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR11_RANGE                        27:27
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR11_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR11_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR11_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR10_SHIFT                        _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR10_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR10_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR10_RANGE                        26:26
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR10_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR10_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR10_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR9_SHIFT                 _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR9_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR9_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR9_RANGE                 25:25
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR9_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR9_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR9_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR8_SHIFT                 _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR8_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR8_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR8_RANGE                 24:24
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR8_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR8_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR8_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR7_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR7_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR7_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR7_RANGE                 23:23
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR7_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR7_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR7_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR6_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR6_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR6_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR6_RANGE                 22:22
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR6_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR6_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR6_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR5_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR5_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR5_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR5_RANGE                 21:21
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR5_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR5_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR5_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR4_SHIFT                 _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR4_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR4_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR4_RANGE                 20:20
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR4_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR4_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR4_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR3_SHIFT                 _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR3_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR3_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR3_RANGE                 19:19
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR3_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR3_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR3_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR2_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR2_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR2_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR2_RANGE                 18:18
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR2_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR2_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR2_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR1_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR1_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR1_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR1_RANGE                 17:17
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR1_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR1_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR1_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR0_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR0_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR0_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR0_RANGE                 16:16
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR0_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR0_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ETBR0_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR15_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR15_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR15_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR15_RANGE                        15:15
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR15_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR15_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR15_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR15_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR15_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR15_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR15_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR14_SHIFT                        _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR14_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR14_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR14_RANGE                        14:14
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR14_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR14_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR14_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR14_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR14_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR14_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR14_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR13_SHIFT                        _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR13_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR13_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR13_RANGE                        13:13
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR13_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR13_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR13_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR13_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR13_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR13_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR13_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR12_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR12_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR12_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR12_RANGE                        12:12
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR12_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR12_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR12_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR12_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR12_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR12_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR12_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR11_SHIFT                        _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR11_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR11_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR11_RANGE                        11:11
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR11_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR11_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR11_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR11_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR11_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR11_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR11_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR10_SHIFT                        _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR10_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR10_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR10_RANGE                        10:10
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR10_WOFFSET                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR10_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR10_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR10_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR10_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR10_NOT_READY                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR10_READY                        _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR9_SHIFT                 _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR9_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR9_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR9_RANGE                 9:9
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR9_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR9_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR9_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR9_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR9_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR9_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR9_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR8_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR8_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR8_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR8_RANGE                 8:8
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR8_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR8_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR8_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR8_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR8_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR8_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR8_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR7_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR7_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR7_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR7_RANGE                 7:7
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR7_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR7_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR7_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR7_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR7_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR7_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR7_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR6_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR6_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR6_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR6_RANGE                 6:6
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR6_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR6_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR6_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR6_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR6_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR6_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR6_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR5_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR5_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR5_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR5_RANGE                 5:5
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR5_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR5_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR5_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR5_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR5_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR5_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR5_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR4_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR4_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR4_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR4_RANGE                 4:4
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR4_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR4_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR4_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR4_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR4_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR4_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR4_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR3_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR3_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR3_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR3_RANGE                 3:3
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR3_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR3_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR3_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR3_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR3_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR3_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR3_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR2_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR2_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR2_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR2_RANGE                 2:2
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR2_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR2_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR2_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR1_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR1_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR1_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR1_RANGE                 1:1
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR1_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR1_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR1_READY                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR0_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR0_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR0_RANGE                 0:0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR0_WOFFSET                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR0_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR0_NOT_READY                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTSTATUS_0_ERBR0_READY                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0                   _MK_ADDR_CONST(0x1bc)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_SECURE                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE15_SHIFT                      _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE15_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE15_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE15_RANGE                      31:31
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE15_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE15_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE15_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE15_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE15_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE15_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE15_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE14_SHIFT                      _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE14_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE14_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE14_RANGE                      30:30
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE14_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE14_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE14_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE14_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE14_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE13_SHIFT                      _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE13_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE13_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE13_RANGE                      29:29
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE13_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE13_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE13_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE13_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE13_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE12_SHIFT                      _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE12_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE12_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE12_RANGE                      28:28
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE12_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE12_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE12_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE12_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE12_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE11_SHIFT                      _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE11_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE11_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE11_RANGE                      27:27
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE11_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE11_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE11_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE11_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE11_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE10_SHIFT                      _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE10_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE10_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE10_RANGE                      26:26
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE10_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE10_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE10_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE10_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE10_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE9_SHIFT                       _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE9_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE9_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE9_RANGE                       25:25
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE9_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE9_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE9_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE9_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE9_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE8_SHIFT                       _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE8_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE8_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE8_RANGE                       24:24
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE8_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE8_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE8_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE8_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE8_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE7_SHIFT                       _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE7_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE7_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE7_RANGE                       23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE7_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE7_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE7_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE6_SHIFT                       _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE6_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE6_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE6_RANGE                       22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE6_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE6_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE6_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE5_SHIFT                       _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE5_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE5_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE5_RANGE                       21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE5_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE5_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE5_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE4_SHIFT                       _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE4_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE4_RANGE                       20:20
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE4_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE4_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE4_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE3_SHIFT                       _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE3_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE3_RANGE                       19:19
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE3_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE3_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE3_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE2_SHIFT                       _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE2_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE2_RANGE                       18:18
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE2_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE2_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE2_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE1_SHIFT                       _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE1_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE1_RANGE                       17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE1_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE1_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE1_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE0_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE0_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE0_RANGE                       16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE0_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE0_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ETCE0_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE15_SHIFT                      _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE15_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE15_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE15_RANGE                      15:15
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE15_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE15_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE15_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE15_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE15_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE15_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE15_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE14_SHIFT                      _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE14_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE14_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE14_RANGE                      14:14
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE14_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE14_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE14_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE14_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE14_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE13_SHIFT                      _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE13_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE13_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE13_RANGE                      13:13
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE13_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE13_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE13_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE13_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE13_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE12_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE12_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE12_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE12_RANGE                      12:12
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE12_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE12_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE12_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE12_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE12_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE11_SHIFT                      _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE11_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE11_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE11_RANGE                      11:11
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE11_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE11_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE11_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE11_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE11_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE10_SHIFT                      _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE10_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE10_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE10_RANGE                      10:10
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE10_WOFFSET                    0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE10_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE10_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE10_NOT_COMPLETE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE10_COMPLETE                   _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE9_SHIFT                       _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE9_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE9_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE9_RANGE                       9:9
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE9_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE9_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE9_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE9_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE9_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE8_SHIFT                       _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE8_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE8_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE8_RANGE                       8:8
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE8_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE8_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE8_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE8_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE8_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE7_SHIFT                       _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE7_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE7_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE7_RANGE                       7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE7_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE7_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE7_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE6_SHIFT                       _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE6_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE6_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE6_RANGE                       6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE6_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE6_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE6_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE5_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE5_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE5_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE5_RANGE                       5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE5_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE5_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE5_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE4_SHIFT                       _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE4_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE4_RANGE                       4:4
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE4_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE4_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE4_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE3_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE3_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE3_RANGE                       3:3
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE3_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE3_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE3_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE2_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE2_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE2_RANGE                       2:2
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE2_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE2_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE2_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE1_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE1_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE1_RANGE                       1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE1_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE1_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE1_COMPLETE                    _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE0_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE0_RANGE                       0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE0_WOFFSET                     0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE0_NOT_COMPLETE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0_ERCE0_COMPLETE                    _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL0_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0                      _MK_ADDR_CONST(0x1c0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RESET_VAL                    _MK_MASK_CONST(0x800080)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RESET_MASK                   _MK_MASK_CONST(0x8d008d)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_READ_MASK                    _MK_MASK_CONST(0x8d008d)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// TX Endpoint Enable. Endpoint 0 is always  enabled. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXE_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXE_RANGE                    23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type. Endpoint0 is fixed as a Control Endpoint. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_RANGE                    19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXT_INTR                     _MK_ENUM_CONST(3)
+
+// TX Endpoint Stall: Software can write a one to this bit to force the  endpoint to return a STALL handshake to the Host. It will continue returning  STALL until the bit is cleared by software or it will automatically be  cleared upon receipt of a new SETUP request. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXS_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXS_RANGE                    16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_TXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+//  RX Endpoint Enable. Endpoint 0 is always  enabled. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXE_RANGE                    7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type. Endpoint 0 is fixed as a Control Endpoint. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_RANGE                    3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXT_INTR                     _MK_ENUM_CONST(3)
+
+// RX Endpoint Stall: Software can write a one to this bit to force the  endpoint to return a STALL handshake to the Host. It will continue returning  STALL until the bit is cleared by software or it will automatically be  cleared upon receipt of a new SETUP request. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXS_RANGE                    0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL0_0_RXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL1_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0                      _MK_ADDR_CONST(0x1c4)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RESET_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_READ_MASK                    _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_WRITE_MASK                   _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXE_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXE_RANGE                    23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXR_SHIFT                    _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXR_RANGE                    22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXI_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXI_RANGE                    21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_RANGE                    19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXD_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXD_RANGE                    17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXS_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXS_RANGE                    16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_TXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXE_RANGE                    7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXR_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXR_RANGE                    6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXI_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXI_RANGE                    5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_RANGE                    3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXD_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXD_RANGE                    1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above, 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXS_RANGE                    0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL1_0_RXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL2_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0                      _MK_ADDR_CONST(0x1c8)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RESET_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_READ_MASK                    _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_WRITE_MASK                   _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXE_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXE_RANGE                    23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXR_SHIFT                    _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXR_RANGE                    22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXI_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXI_RANGE                    21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_RANGE                    19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXD_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXD_RANGE                    17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXS_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXS_RANGE                    16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_TXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXE_RANGE                    7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXR_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXR_RANGE                    6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXI_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXI_RANGE                    5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_RANGE                    3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXD_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXD_RANGE                    1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXS_RANGE                    0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL2_0_RXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL3_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0                      _MK_ADDR_CONST(0x1cc)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RESET_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_READ_MASK                    _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_WRITE_MASK                   _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXE_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXE_RANGE                    23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXR_SHIFT                    _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXR_RANGE                    22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXI_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXI_RANGE                    21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_RANGE                    19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXD_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXD_RANGE                    17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXS_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXS_RANGE                    16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_TXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXE_RANGE                    7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXR_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXR_RANGE                    6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXI_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXI_RANGE                    5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_RANGE                    3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXD_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXD_RANGE                    1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXS_RANGE                    0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL3_0_RXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL4_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0                      _MK_ADDR_CONST(0x1d0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RESET_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_READ_MASK                    _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_WRITE_MASK                   _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXE_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXE_RANGE                    23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXR_SHIFT                    _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXR_RANGE                    22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXI_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXI_RANGE                    21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_RANGE                    19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXD_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXD_RANGE                    17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXS_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXS_RANGE                    16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_TXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXE_RANGE                    7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXR_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXR_RANGE                    6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXI_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXI_RANGE                    5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_RANGE                    3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXD_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXD_RANGE                    1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXS_RANGE                    0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL4_0_RXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL5_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0                      _MK_ADDR_CONST(0x1d4)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RESET_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_READ_MASK                    _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_WRITE_MASK                   _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXE_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXE_RANGE                    23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXR_SHIFT                    _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXR_RANGE                    22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXI_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXI_RANGE                    21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_RANGE                    19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXD_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXD_RANGE                    17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXS_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXS_RANGE                    16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_TXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXE_RANGE                    7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXR_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXR_RANGE                    6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXI_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXI_RANGE                    5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_RANGE                    3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXD_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXD_RANGE                    1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXS_RANGE                    0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL5_0_RXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL6_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0                      _MK_ADDR_CONST(0x1d8)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RESET_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_READ_MASK                    _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_WRITE_MASK                   _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXE_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXE_RANGE                    23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXR_SHIFT                    _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXR_RANGE                    22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXI_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXI_RANGE                    21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_RANGE                    19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXD_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXD_RANGE                    17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXS_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXS_RANGE                    16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_TXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXE_RANGE                    7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXR_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXR_RANGE                    6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXI_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXI_RANGE                    5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_RANGE                    3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXD_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXD_RANGE                    1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXS_RANGE                    0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL6_0_RXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL7_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0                      _MK_ADDR_CONST(0x1dc)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RESET_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_READ_MASK                    _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_WRITE_MASK                   _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXE_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXE_RANGE                    23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXR_SHIFT                    _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXR_RANGE                    22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXI_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXI_RANGE                    21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_RANGE                    19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXD_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXD_RANGE                    17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXS_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXS_RANGE                    16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_TXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXE_RANGE                    7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXR_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXR_RANGE                    6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXI_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXI_RANGE                    5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_RANGE                    3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXD_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXD_RANGE                    1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXS_RANGE                    0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL7_0_RXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL8_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0                      _MK_ADDR_CONST(0x1e0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RESET_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_READ_MASK                    _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_WRITE_MASK                   _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXE_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXE_RANGE                    23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXR_SHIFT                    _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXR_RANGE                    22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXI_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXI_RANGE                    21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_RANGE                    19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXD_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXD_RANGE                    17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXS_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXS_RANGE                    16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_TXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXE_RANGE                    7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXR_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXR_RANGE                    6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXI_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXI_RANGE                    5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_RANGE                    3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXD_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXD_RANGE                    1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXS_RANGE                    0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL8_0_RXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL9_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0                      _MK_ADDR_CONST(0x1e4)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_SECURE                       0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RESET_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_READ_MASK                    _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_WRITE_MASK                   _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXE_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXE_RANGE                    23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXR_SHIFT                    _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXR_RANGE                    22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXI_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXI_RANGE                    21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_RANGE                    19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXD_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXD_RANGE                    17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXS_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXS_RANGE                    16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_TXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXE_RANGE                    7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXE_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXE_ENABLE                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXR_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXR_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXR_RANGE                    6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXR_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXR_KEEP_GOING                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXR_RESET_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXI_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXI_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXI_RANGE                    5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXI_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXI_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXI_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXI_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXI_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXI_DIS_PID_SEQ                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXI_ENB_PID_SEQ                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_RANGE                    3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_CTRL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_ISO                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_BULK                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXT_INTR                     _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXD_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXD_RANGE                    1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXD_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXS_RANGE                    0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXS_WOFFSET                  0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXS_EP_OK                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL9_0_RXS_EP_STALL                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL10_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0                     _MK_ADDR_CONST(0x1e8)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_SECURE                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RESET_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_READ_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_WRITE_MASK                  _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXE_SHIFT                   _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXE_RANGE                   23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXR_SHIFT                   _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXR_RANGE                   22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXI_SHIFT                   _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXI_RANGE                   21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_SHIFT                   _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_RANGE                   19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXD_SHIFT                   _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXD_RANGE                   17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXS_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXS_RANGE                   16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_TXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXE_SHIFT                   _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXE_RANGE                   7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXR_SHIFT                   _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXR_RANGE                   6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXI_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXI_RANGE                   5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_SHIFT                   _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_RANGE                   3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXD_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXD_RANGE                   1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXS_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXS_RANGE                   0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL10_0_RXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL11_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0                     _MK_ADDR_CONST(0x1ec)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_SECURE                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RESET_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_READ_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_WRITE_MASK                  _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXE_SHIFT                   _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXE_RANGE                   23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXR_SHIFT                   _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXR_RANGE                   22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXI_SHIFT                   _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXI_RANGE                   21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_SHIFT                   _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_RANGE                   19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXD_SHIFT                   _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXD_RANGE                   17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXS_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXS_RANGE                   16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_TXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXE_SHIFT                   _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXE_RANGE                   7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXR_SHIFT                   _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXR_RANGE                   6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXI_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXI_RANGE                   5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_SHIFT                   _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_RANGE                   3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXD_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXD_RANGE                   1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXS_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXS_RANGE                   0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL11_0_RXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL12_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0                     _MK_ADDR_CONST(0x1f0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_SECURE                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RESET_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_READ_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_WRITE_MASK                  _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXE_SHIFT                   _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXE_RANGE                   23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXR_SHIFT                   _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXR_RANGE                   22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXI_SHIFT                   _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXI_RANGE                   21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_SHIFT                   _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_RANGE                   19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXD_SHIFT                   _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXD_RANGE                   17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXS_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXS_RANGE                   16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_TXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXE_SHIFT                   _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXE_RANGE                   7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXR_SHIFT                   _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXR_RANGE                   6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXI_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXI_RANGE                   5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_SHIFT                   _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_RANGE                   3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXD_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXD_RANGE                   1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXS_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXS_RANGE                   0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL12_0_RXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL13_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0                     _MK_ADDR_CONST(0x1f4)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_SECURE                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RESET_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_READ_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_WRITE_MASK                  _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXE_SHIFT                   _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXE_RANGE                   23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXR_SHIFT                   _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXR_RANGE                   22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXI_SHIFT                   _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXI_RANGE                   21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_SHIFT                   _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_RANGE                   19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXD_SHIFT                   _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXD_RANGE                   17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXS_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXS_RANGE                   16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_TXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXE_SHIFT                   _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXE_RANGE                   7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXR_SHIFT                   _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXR_RANGE                   6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXI_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXI_RANGE                   5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_SHIFT                   _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_RANGE                   3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXD_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXD_RANGE                   1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXS_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXS_RANGE                   0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL13_0_RXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL14_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0                     _MK_ADDR_CONST(0x1f8)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_SECURE                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RESET_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_READ_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_WRITE_MASK                  _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXE_SHIFT                   _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXE_RANGE                   23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXR_SHIFT                   _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXR_RANGE                   22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXI_SHIFT                   _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXI_RANGE                   21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_SHIFT                   _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_RANGE                   19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXD_SHIFT                   _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXD_RANGE                   17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXS_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXS_RANGE                   16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_TXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXE_SHIFT                   _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXE_RANGE                   7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXR_SHIFT                   _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXR_RANGE                   6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXI_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXI_RANGE                   5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_SHIFT                   _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_RANGE                   3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXD_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXD_RANGE                   1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXS_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXS_RANGE                   0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL14_0_RXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_USB2D_ENDPTCTRL15_0  
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0                     _MK_ADDR_CONST(0x1fc)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_SECURE                      0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RESET_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_READ_MASK                   _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_WRITE_MASK                  _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXE_SHIFT                   _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXE_RANGE                   23:23
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXR_SHIFT                   _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXR_RANGE                   22:22
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXI_SHIFT                   _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXI_RANGE                   21:21
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_SHIFT                   _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_RANGE                   19:18
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXD_SHIFT                   _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXD_RANGE                   17:17
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXS_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXS_RANGE                   16:16
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_TXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXE_SHIFT                   _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXE_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXE_RANGE                   7:7
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXE_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXE_ENABLE                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXR_SHIFT                   _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXR_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXR_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXR_RANGE                   6:6
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXR_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXR_KEEP_GOING                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXR_RESET_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXI_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXI_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXI_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXI_RANGE                   5:5
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXI_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXI_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXI_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXI_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXI_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXI_DIS_PID_SEQ                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXI_ENB_PID_SEQ                     _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_SHIFT                   _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_RANGE                   3:2
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_CTRL                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_ISO                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_BULK                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXT_INTR                    _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXD_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXD_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXD_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXD_RANGE                   1:1
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXD_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXS_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXS_SHIFT)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXS_RANGE                   0:0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXS_WOFFSET                 0x0
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXS_EP_OK                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_ENDPTCTRL15_0_RXS_EP_STALL                        _MK_ENUM_CONST(1)
+
+
+// Packet USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_ROW                      0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_NON_ISO_IS_0                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_MULTI_1                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_MULT_2                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_MULTI_3                  _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_SHIFT                     _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_RANGE                     _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_ROW                       0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_ZERO_LENGTH_TERM_ENABLED                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_ZERO_LENGTH_TERM_DISABLED                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_SHIFT                     _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_RANGE                     _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_ROW                       0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_FIELD                       (_MK_MASK_CONST(0x7ff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_RANGE                       _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_SHIFT                     _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_ROW                       0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_ENABLE                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_FIELD                     (_MK_MASK_CONST(0x7fff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_ROW                       0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_FIELD                 (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_ROW                   1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_FIELD                     (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_ROW                       1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_FIELD                    (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_ROW                      2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_FIELD                     (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_ROW                 2
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_SET                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_FIELD                     (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_SHIFT                     _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_ROW                       3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_ENABLE                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_FIELD                     (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_ROW                       3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_ENABLE                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_RANGE                     _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_ROW                    3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_RANGE                  _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_ROW                    3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_RANGE                       _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_ROW                 3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SET                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_SHIFT                     _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_RANGE                       _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_ROW                 3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_SET                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_FIELD                     (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_RANGE                     _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_ROW                     4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_FIELD                      (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_ROW                        4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_ROW                     5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_ROW                       5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_ROW                     6
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_ROW                       6
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_ROW                     7
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_ROW                       7
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_ROW                     8
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_ROW                       8
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_ROW                       9
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_ROW                        10
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_ROW                        11
+
+
+// Packet USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_FIELD                   (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_ROW                     0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_ROW                      0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_FIELD                    (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT                    _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_ROW                      1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_ENABLE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_FIELD                    (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_RANGE                    _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_ROW                      1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_RANGE                    _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_ROW                   1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_RANGE                 _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_ROW                   1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_ROW                        1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_SHIFT                    _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT                      _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_RANGE                      _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_ROW                        1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_FIELD                    (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                    3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_ROW                    4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_ROW                      4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_ROW                    5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_ROW                      5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_ROW                    6
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_ROW                      6
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_FIELD                    (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_ROW                      0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_RANGE                       _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_ROW                 0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_ITD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_QH                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_SITD                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_FSTN                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_VALID_QH_PTR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_INVALID_QH_PTR                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_SHIFT                        _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_FIELD                        (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_SHIFT                      _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_RANGE                      _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_ROW                        1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_NOT_CTRL_EP                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_CTRP_EP                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_FIELD                    (_MK_MASK_CONST(0x7ff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_RANGE                    _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_SHIFT                     _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_ROW                       1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_SHIFT                  _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_RANGE                  _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_QH_DT                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_QTD_DT                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_RANGE                       _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_ROW                 1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_FULL_SPEED                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_LOW_SPEED                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_HIGH_SPEED                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_RESERVED                    _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_SHIFT                       _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_SHIFT                        _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_RANGE                        _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_ROW                  1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_NO_INACTIVATE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_INACTIVATE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_FIELD                       (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_RANGE                       _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_SHIFT                      _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_FIELD                      (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_ROW                        2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_NON_ISO_IS_0                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_MULTI_1                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_MULT_2                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_MULTI_3                    _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_SHIFT                       _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_FIELD                       (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_ROW                 2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_FIELD                  (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_RANGE                  _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_FIELD                   (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_ROW                     3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_FIELD                       (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_ROW                 3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_FIELD                      (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_ROW                        4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_ROW                 4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_RANGE                     _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_ROW                       4
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_VALID_TD_PTR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_INVALID_TD_PTR                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_FIELD                  (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_ROW                    5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_ROW                 5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_RANGE                 _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_ROW                   5
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_VALID_TD_PTR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_INVALID_TD_PTR                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_SHIFT                       _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_RANGE                       _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_ROW                 6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_DATA0                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_DATA1                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_FIELD                       (_MK_MASK_CONST(0x7fff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_RANGE                       _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_ROW                 6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_SHIFT                       _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_ROW                 6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_ENABLE                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_FIELD                      (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_RANGE                      _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_ROW                        6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_ROW                 6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_RANGE                  _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_ROW                    6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_OUT                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_IN                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_SETUP                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_RESERVED                       _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_RANGE                    _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_ROW                      6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_ROW                      6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_RANGE                 _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_ROW                   6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_SHIFT                   _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_RANGE                   _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_ROW                     6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_SET                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_RANGE                 _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_ROW                   6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_ROW                  6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_SET                  _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_RANGE                 _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_ROW                   6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_DO_START_SPLIT                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_DO_COMPLETE_SPLIT                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_ROW                  6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_DO_OUT                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_DO_PING                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_ROW                       7
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_FIELD                        (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_ROW                  7
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_ROW                       8
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_ROW                 8
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_ROW                       9
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_ROW                 9
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_ROW                       10
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_FIELD                      (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_ROW                        10
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_ROW                       11
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_FIELD                      (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_ROW                        11
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_FIELD                       (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_RANGE                       _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_FIELD                        (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_ROW                  0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_VALID_TD_PTR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_INVALID_TD_PTR                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_FIELD                   (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_ROW                     1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_FIELD                        (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_VALID_TD_PTR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_INVALID_TD_PTR                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_ROW                  2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_DATA0                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_DATA1                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_FIELD                        (_MK_MASK_CONST(0x7fff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_RANGE                        _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_ROW                  2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_ROW                  2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_FIELD                       (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_RANGE                       _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_ROW                 2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_SHIFT                        _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_FIELD                        (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_ROW                  2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_SHIFT                   _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_RANGE                   _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_ROW                     2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_OUT                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_IN                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_SETUP                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_RESERVED                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT                     _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_ROW                       2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_RANGE                     _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_ROW                       2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_RANGE                  _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT                    _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_ROW                      2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_RANGE                  _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_RANGE                 _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_ROW                   2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_RANGE                  _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_START_SPLIT                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_COMPLETE_SPLIT                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_RANGE                 _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_ROW                   2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_DO_OUT                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_DO_PING                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                        3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_ROW                   3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                        4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_FIELD                        (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_ROW                  4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_ROW                        5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_FIELD                        (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_ROW                  5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_ROW                        6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_ROW                 6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_ROW                        7
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_ROW                 7
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_FIELD                       (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_RANGE                       _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_RANGE                       _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_ROW                 0
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_ITD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_QH                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_SITD                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_FSTN                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_ROW                 0
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_FIELD                        (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_ROW                  0
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_ROW                    0
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_RANGE                  _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ROW                    0
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ITD                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_QH                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SITD                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FSTN                   _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_ROW                      0
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_VALID_LINK_PTR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_INVALID_LINK_PTR                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_ROW                       1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_ROW                      1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_ROW                   1
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_ROW                  1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_ROW                   1
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_ROW                       2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_ROW                      2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_ROW                   2
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_ROW                  2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_ROW                  2
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_ROW                   2
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_ROW                       3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_ROW                    3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_ROW                      3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_ROW                    3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_ROW                   3
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_ROW                  3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_ROW                  3
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_ROW                   3
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_ROW                       4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_ROW                    4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_ROW                      4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_ROW                    4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_ROW                   4
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_ROW                  4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_ROW                  4
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_ROW                   4
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_ROW                       5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_ROW                    5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_ROW                      5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_ROW                    5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_ROW                   5
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_ROW                  5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_ROW                  5
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_ROW                   5
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_ROW                       6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_ROW                    6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_ROW                      6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_ROW                    6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_ROW                   6
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_ROW                  6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_ROW                  6
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_ROW                   6
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_ROW                       7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_ROW                    7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_ROW                      7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_ROW                    7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_ROW                   7
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_ROW                  7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_ROW                  7
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_ROW                   7
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_ROW                       8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_ROW                    8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_ROW                      8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_ROW                    8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_ROW                   8
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_ROW                  8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_ROW                  8
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_ROW                   8
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                  9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_FIELD                  (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_RANGE                  _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_ROW                    9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_ROW                    9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_FIELD                  (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_RANGE                  _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_ROW                    9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                  10
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT                    _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_ROW                      10
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_OUT                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_IN                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_FIELD                 (_MK_MASK_CONST(0x7ff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_RANGE                 _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_ROW                   10
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_ROW                  11
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_FIELD                 (_MK_MASK_CONST(0x3ff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_ROW                   11
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_RANGE                 _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_ROW                   11
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_RESERVED                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_MULTI_1                       _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_MULT_2                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_MULTI_3                       _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_ROW                  12
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_ROW                   12
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_ROW                  13
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_ROW                   13
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_ROW                  14
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_ROW                   14
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_ROW                  15
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_ROW                   15
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_FIELD                  (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_ROW                    0
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT                    _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_ROW                      0
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ROW                      0
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ITD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_QH                       _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SITD                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FSTN                     _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_VALID_LINK_PTR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_INVALID_LINK_PTR                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT                      _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_ROW                        1
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_OUT                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_IN                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_SHIFT                    _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_FIELD                    (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_RANGE                    _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_FIELD                       (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_RANGE                       _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_RANGE                    _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_FIELD                    (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_FIELD                    (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_ROW                      2
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_RANGE                  _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_SHIFT                    _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_ROW                      3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_ENABLE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_RANGE                    _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT                    _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_FIELD                    (_MK_MASK_CONST(0x3ff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_RANGE                    _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_FIELD                    (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_ROW                   3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_RANGE                  _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_ROW                    3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_ROW                        3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_ROW                  3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SET                  _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT                      _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_RANGE                      _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_ROW                        3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_RANGE                     _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_ROW                       3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT                      _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_RANGE                      _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_ROW                        3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_START_SPLIT                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_COMPLETE_SPLIT                  _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                    4
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_ROW                       4
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                    5
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_FIELD                    (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_ROW                      5
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_RANGE                   _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_ROW                     5
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_ALL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_BEGIN                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_MID                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_END                     _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_FIELD                      (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_RANGE                      _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_ROW                        5
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_FIELD                  (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_ROW                    6
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_ROW                      6
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_RANGE                   _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_ROW                     6
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_VALID_BACK_PTR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_INVALID_BACK_PTR                        _MK_ENUM_CONST(1)
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_FIELD                      (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_ROW                        0
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_RANGE                       _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_ROW                 0
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_ITD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_QH                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_SITD                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_FSTN                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_RANGE                 _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_ROW                   0
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_VALID_LINK_PTR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_INVALID_LINK_PTR                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_FIELD                        (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_ROW                      1
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_ITD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_QH                       _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_SITD                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_FSTN                     _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_ROW                        1
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_VALID_LINK_PTR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_INVALID_LINK_PTR                   _MK_ENUM_CONST(1)
+
+
+// Register USB1_IF_USB_SUSP_CTRL_0  
+#define USB1_IF_USB_SUSP_CTRL_0                 _MK_ADDR_CONST(0x400)
+#define USB1_IF_USB_SUSP_CTRL_0_SECURE                  0x0
+#define USB1_IF_USB_SUSP_CTRL_0_WORD_COUNT                      0x1
+#define USB1_IF_USB_SUSP_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0x74fff)
+#define USB1_IF_USB_SUSP_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_READ_MASK                       _MK_MASK_CONST(0x74fff)
+#define USB1_IF_USB_SUSP_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x74e3e)
+// USB PHY wakeup debounce counter
+// USB will debounce any wakeup event by the number of clocks programmed 
+// in this counter.
+// A value of 0 results in no debounce.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_FIELD                 (_MK_MASK_CONST(0x7) << USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_RANGE                 18:16
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_WOFFSET                       0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+//Suspend Set
+// Software must write a 1 to this bit to set the PHY
+// into suspend mode. Software should also write 0 to clear it.
+// NOTE: It is required that software generate a  positive pulse on this
+// bit to guarantee proper operation.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_SET_SHIFT                      _MK_SHIFT_CONST(14)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_SET_FIELD                      (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_SET_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_SET_RANGE                      14:14
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_SET_WOFFSET                    0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_SET_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_SET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_SET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_SET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_SET_UNSET                      _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_SET_SET                        _MK_ENUM_CONST(1)
+
+// Reset going to UTMIP PHY (active high).
+// This should be set to 1 whenever programming the UTMIP config registers.
+// It should be cleared to 0 after the programming of UTMIP config registers is done.
+// UTMIP config registers should be programmed only once before doing any transactions on USB.
+// The UTMIP PHY registers should be programmed while UTMIP is in reset.
+#define USB1_IF_USB_SUSP_CTRL_0_UTMIP_RESET_SHIFT                       _MK_SHIFT_CONST(11)
+#define USB1_IF_USB_SUSP_CTRL_0_UTMIP_RESET_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_UTMIP_RESET_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_UTMIP_RESET_RANGE                       11:11
+#define USB1_IF_USB_SUSP_CTRL_0_UTMIP_RESET_WOFFSET                     0x0
+#define USB1_IF_USB_SUSP_CTRL_0_UTMIP_RESET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_UTMIP_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_UTMIP_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_UTMIP_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_UTMIP_RESET_DISABLE                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_UTMIP_RESET_ENABLE                      _MK_ENUM_CONST(1)
+
+// Polarity of the suspend signal going to USB PHY.
+// 0 = Active low (default)
+// 1 = Active high
+// This should not be changed by software.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_SHIFT                      _MK_SHIFT_CONST(10)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_FIELD                      (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_RANGE                      10:10
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_WOFFSET                    0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_ACTIVE_LOW                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_ACTIVE_HIGH                        _MK_ENUM_CONST(1)
+
+// USB PHY clock valid interrupt enable
+// If this bit is enabled, interrupt is generated
+// whenever USB clocks are resumed from a suspend.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SHIFT                 _MK_SHIFT_CONST(9)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_RANGE                 9:9
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_WOFFSET                       0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_DISABLE                       _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_ENABLE                        _MK_ENUM_CONST(1)
+
+// USB PHY clock valid interrupt status
+// This bit is set whenever USB PHY clock is waked up from suspend.
+// Software must write a 1 to clear this bit.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_RANGE                 8:8
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_WOFFSET                       0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_UNSET                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SET                   _MK_ENUM_CONST(1)
+
+// USB PHY clock valid status
+// This bit indicates whether the USB PHY is generating a valid clock to 
+// the USB controller.
+// If USB PHY clock is running, this bit is set to 1, else it is set to 0.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_RANGE                 7:7
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_WOFFSET                       0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_UNSET                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SET                   _MK_ENUM_CONST(1)
+
+// USB AHB clock enable status.
+// Indicates whether the AHB clock to the USB controller is enabled or not.
+// If AHB clock to USB controller is enabled, this bit is set to 1, else it is set to 0.
+// NOTE: even when this is set to 0, all essential blocks that are required
+// to resume USB clocks from suspend will be active and their AHB clock will not
+// be suspended.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_CLKEN_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_CLKEN_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_CLKEN_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_CLKEN_RANGE                 6:6
+#define USB1_IF_USB_SUSP_CTRL_0_USB_CLKEN_WOFFSET                       0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_CLKEN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_CLKEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_CLKEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_CLKEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_CLKEN_UNSET                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_CLKEN_SET                   _MK_ENUM_CONST(1)
+
+//Suspend Clear
+// Software must write a 1 to this bit to bring the PHY
+// out of suspend mode. This is used when the software stops the PHY
+// clock during suspend and then wants to initiate a resume. Software
+// should also write 0 to clear it.
+// NOTE: It is required that software generate a  positive pulse on this
+// bit to guarantee proper operation.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_FIELD                      (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_RANGE                      5:5
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_WOFFSET                    0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_UNSET                      _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SET                        _MK_ENUM_CONST(1)
+
+// Wake on Disconnect Enable (device mode)
+// When enabled (1), USB device will wakeup
+// from suspend on a disconnect event.
+// This is only valid when USB controller is in device mode, it is
+// not applicable when USB controller is in host mode.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_RANGE                 4:4
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_WOFFSET                       0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_DISABLE                       _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_ENABLE                        _MK_ENUM_CONST(1)
+
+// Wake on Connect Enable (device mode)
+// When enabled (1), USB device will wakeup
+// from suspend on a connect event.
+// This is only valid when USB controller is in device mode, it is
+// not applicable when USB controller is in host mode.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_FIELD                   (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_RANGE                   3:3
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_WOFFSET                 0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_DISABLE                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_ENABLE                  _MK_ENUM_CONST(1)
+
+// Wake on resume enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a resume event is detected on USB.
+// This is valid for both USB device and USB host modes.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_RANGE                     2:2
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_WOFFSET                   0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// USB wakeup interrupt enable
+// If this bit is enabled, interrupt is generated
+// whenever USB wakeup event is generated.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_RANGE                        1:1
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_WOFFSET                      0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_DISABLE                      _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_ENABLE                       _MK_ENUM_CONST(1)
+
+// USB wakeup interrupt status
+// This bit is set whenever USB wakes up from suspend (a wakeup event
+// is generated).
+// Software must write a 1 to clear this bit.
+// Note that during the wakeup sequence, PHY clocks will be resumed from suspend.
+// Software can check when the PHY clocks are resumed by reading the bit
+// USB_PHY_CLK_VALID. There is also a separate interrupt generated
+// when PHY clock is resumed if USB_PHY_CLK_VALID_INT_EN is set.
+// During the wakeup sequence, first USB_WAKEUP_INT_STS will be set, and
+// it will take some time for the PHY clock to resume, which can be detected
+// by checking USB_PHY_CLK_VALID.
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SHIFT)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_RANGE                        0:0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_WOFFSET                      0x0
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_UNSET                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SET                  _MK_ENUM_CONST(1)
+
+
+// Register USB1_IF_USB_PHY_VBUS_SENSORS_0  
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0                  _MK_ADDR_CONST(0x404)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_SECURE                   0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_WORD_COUNT                       0x1
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_RESET_MASK                       _MK_MASK_CONST(0x7f7f7f7f)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_READ_MASK                        _MK_MASK_CONST(0x7f7f7f7f)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_WRITE_MASK                       _MK_MASK_CONST(0x79797979)
+// A_VBUS_VLD wakeup enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a change is detected on A_VBUS_VLD.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_SHIFT                       _MK_SHIFT_CONST(30)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_RANGE                       30:30
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_WOFFSET                     0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT                       _MK_SHIFT_CONST(29)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_RANGE                       29:29
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_WOFFSET                     0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_A                       _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_B                       _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software value
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This is only valid when A_VBUS_VLD_SW_EN is set.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT                        _MK_SHIFT_CONST(28)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_RANGE                        28:28
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_UNSET                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SET                  _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software enable
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in A_VBUS_VLD_SW_VALUE to the USB
+// controller.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT                   _MK_SHIFT_CONST(27)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_FIELD                   (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_RANGE                   27:27
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_WOFFSET                 0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status
+// This is set to 1 whenever A_VBUS_VLD sensor
+// output is 1.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT                     _MK_SHIFT_CONST(26)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_RANGE                     26:26
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_UNSET                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SET                       _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_VBUS_VLD.
+// software writes a 1 to clear it
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT                 _MK_SHIFT_CONST(25)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_RANGE                 25:25
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_WOFFSET                       0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_UNSET                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SET                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever A_VBUS_VLD_CHG_DET is set to 1.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT                  _MK_SHIFT_CONST(24)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_RANGE                  24:24
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// A_SESS_VLD wakeup enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a change is detected on A_SESS_VLD.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_SHIFT                       _MK_SHIFT_CONST(22)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_RANGE                       22:22
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_WOFFSET                     0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT                       _MK_SHIFT_CONST(21)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_RANGE                       21:21
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_WOFFSET                     0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_A                       _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_B                       _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software value
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This is only valid when A_SESS_VLD_SW_EN is set.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT                        _MK_SHIFT_CONST(20)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_RANGE                        20:20
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_UNSET                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SET                  _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software enable
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in A_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT                   _MK_SHIFT_CONST(19)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_FIELD                   (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_RANGE                   19:19
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_WOFFSET                 0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status
+// This is set to 1 whenever A_SESS_VLD sensor
+// output is 1.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_RANGE                     18:18
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_UNSET                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SET                       _MK_ENUM_CONST(1)
+
+// A_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_SESS_VLD.
+// software writes a 1 to clear it
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_RANGE                 17:17
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_WOFFSET                       0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_UNSET                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SET                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever A_SESS_VLD_CHG_DET is set to 1.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_RANGE                  16:16
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// B_SESS_VLD wakeup enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a change is detected on B_SESS_VLD.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_RANGE                       14:14
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_WOFFSET                     0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT                       _MK_SHIFT_CONST(13)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_RANGE                       13:13
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_WOFFSET                     0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_A                       _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_B                       _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software value
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_VLD status.
+// This is only valid when B_SESS_VLD_SW_EN is set.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_RANGE                        12:12
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_UNSET                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SET                  _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software enable
+// Enable Software Controlled B_SESS_VLD.
+// Software sets this bit to drive the
+// value in B_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT                   _MK_SHIFT_CONST(11)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_FIELD                   (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_RANGE                   11:11
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_WOFFSET                 0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// B_SESS_VLD status
+// This is set to 1 whenever B_SESS_VLD sensor
+// output is 1.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT                     _MK_SHIFT_CONST(10)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_RANGE                     10:10
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_UNSET                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_VLD.
+// software writes a 1 to clear it
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT                 _MK_SHIFT_CONST(9)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_RANGE                 9:9
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_WOFFSET                       0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_UNSET                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_VLD_CHG_DET is set to 1.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_RANGE                  8:8
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// B_SESS_END wakeup enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a change is detected on B_SESS_END.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_SHIFT                       _MK_SHIFT_CONST(6)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_RANGE                       6:6
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_WOFFSET                     0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_END debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_RANGE                       5:5
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_WOFFSET                     0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_A                       _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_B                       _MK_ENUM_CONST(1)
+
+// B_SESS_END software value
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This is only valid when B_SESS_END_SW_EN is set.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_RANGE                        4:4
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_UNSET                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SET                  _MK_ENUM_CONST(1)
+
+// B_SESS_END software enable
+// Enable Software Controlled B_SESS_END
+// Software sets this bit to drive the
+// value in B_SESS_END_SW_VALUE to the USB
+// controller.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_FIELD                   (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_RANGE                   3:3
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_WOFFSET                 0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// B_SESS_END status
+// This is set to 1 whenever B_SESS_END sensor
+// output is 1.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_RANGE                     2:2
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_UNSET                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_END change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_END.
+// software writes a 1 to clear it
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_RANGE                 1:1
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_WOFFSET                       0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_UNSET                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_END interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_END_CHG_DET is set to 1.
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_RANGE                  0:0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0  
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0                        _MK_ADDR_CONST(0x408)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_SECURE                         0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_WORD_COUNT                     0x1
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_RESET_VAL                      _MK_MASK_CONST(0x40)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_RESET_MASK                     _MK_MASK_CONST(0x403f3f7f)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_READ_MASK                      _MK_MASK_CONST(0x403f3f7f)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_WRITE_MASK                     _MK_MASK_CONST(0x40393979)
+// VDAT_DET debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT                       _MK_SHIFT_CONST(21)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_RANGE                       21:21
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_WOFFSET                     0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_A                       _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_B                       _MK_ENUM_CONST(1)
+
+// VDAT_DET software value
+// Software should write the appropriate
+// value (1/0) to set/unset the VDAT_DET status.
+// This is only valid when VDAT_DET_SW_EN is set.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT                        _MK_SHIFT_CONST(20)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_RANGE                        20:20
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_UNSET                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SET                  _MK_ENUM_CONST(1)
+
+// VDAT_DET software enable
+// Enable Software Controlled VDAT_DET.
+// Software sets this bit to drive the
+// value in VDAT_DET_SW_VALUE to the USB
+// controller
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT                   _MK_SHIFT_CONST(19)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_FIELD                   (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_RANGE                   19:19
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_WOFFSET                 0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// VDAT_DET status
+// This is set to 1 whenever VDAT_DET sensor
+// output is 1.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_RANGE                     18:18
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_UNSET                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SET                       _MK_ENUM_CONST(1)
+
+// VDAT_DET change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VDAT_DET.
+// software writes a 1 to clear it
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_RANGE                 17:17
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_WOFFSET                       0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_UNSET                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SET                   _MK_ENUM_CONST(1)
+
+// VDAT_DET interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever VDAT_DET_CHG_DET is set to 1.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_RANGE                  16:16
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP wakeup enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a change is detected on VBUS_WAKEUP.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_FIELD                    (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_RANGE                    30:30
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_WOFFSET                  0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT                    _MK_SHIFT_CONST(13)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_FIELD                    (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_RANGE                    13:13
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_WOFFSET                  0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_A                    _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_B                    _MK_ENUM_CONST(1)
+
+// VBUS wakeup software value
+// Software should write the appropriate
+// value (1/0) to set/unset the VBUS_WAKEUP status.
+// This is only valid when VBUS_WAKEUP_SW_EN is set.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_RANGE                     12:12
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_UNSET                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SET                       _MK_ENUM_CONST(1)
+
+// VBUS wakeup software enable
+// Enable Software Controlled VBUS_WAKEUP.
+// Software sets this bit to drive the
+// value in VBUS_WAKEUP_SW_VALUE to the USB
+// controller.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT                        _MK_SHIFT_CONST(11)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_RANGE                        11:11
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// VBUS wakeup status
+// This is set to 1 whenever VBUS_WAKEUP sensor
+// output is 1.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT                  _MK_SHIFT_CONST(10)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_FIELD                  (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_RANGE                  10:10
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_UNSET                  _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SET                    _MK_ENUM_CONST(1)
+
+// VBUS wakeup change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VBUS_WAKEUP.
+// software writes a 1 to clear it
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT                      _MK_SHIFT_CONST(9)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_FIELD                      (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_RANGE                      9:9
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_WOFFSET                    0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_UNSET                      _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SET                        _MK_ENUM_CONST(1)
+
+// VBUS wakeup interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever VBUS_WAKEUP_CHG_DET is set to 1.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT                       _MK_SHIFT_CONST(8)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_RANGE                       8:8
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_WOFFSET                     0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// ID pullup enable. Set to 1.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_FIELD                    (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_RANGE                    6:6
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_WOFFSET                  0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_DISABLE                  _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_ENABLE                   _MK_ENUM_CONST(1)
+
+// ID debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_RANGE                     5:5
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_A                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_B                     _MK_ENUM_CONST(1)
+
+// ID software value
+// Software should write the appropriate
+// value (1/0) to set/unset the ID status.
+// This is only valid when ID_SW_EN is set.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT                      _MK_SHIFT_CONST(4)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_FIELD                      (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_RANGE                      4:4
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_WOFFSET                    0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_UNSET                      _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SET                        _MK_ENUM_CONST(1)
+
+// ID software enable
+// Enable Software Controlled ID.
+// Software sets this bit to drive the
+// value in ID_SW_VALUE to the USB
+// controller
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_RANGE                 3:3
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_WOFFSET                       0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ID status
+// This is set to 1 whenever ID sensor
+// output is 1.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT                   _MK_SHIFT_CONST(2)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_FIELD                   (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_RANGE                   2:2
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_WOFFSET                 0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_UNSET                   _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SET                     _MK_ENUM_CONST(1)
+
+// ID change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of ID.
+// software writes a 1 to clear it
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_FIELD                       (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_RANGE                       1:1
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_WOFFSET                     0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_UNSET                       _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SET                 _MK_ENUM_CONST(1)
+
+// ID interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever ID_CHG_DET is set to 1.
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_RANGE                        0:0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register USB1_IF_USB_PHY_ALT_VBUS_STS_0  
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0                  _MK_ADDR_CONST(0x40c)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_SECURE                   0x0
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_WORD_COUNT                       0x1
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_RESET_MASK                       _MK_MASK_CONST(0x7f)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_READ_MASK                        _MK_MASK_CONST(0x7f)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// A_SESS_VLD alternate status
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SHIFT)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_RANGE                     6:6
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_VLD alternate status
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SHIFT)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_RANGE                     5:5
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SET                       _MK_ENUM_CONST(1)
+
+// ID alternate status
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_RANGE                 4:4
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_WOFFSET                       0x0
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_END alternate status
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SHIFT                     _MK_SHIFT_CONST(3)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SHIFT)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_RANGE                     3:3
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SET                       _MK_ENUM_CONST(1)
+
+// Static GPI alternate status
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_RANGE                     2:2
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SET                       _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD alternate status
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_FIELD                     (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SHIFT)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_RANGE                     1:1
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SET                       _MK_ENUM_CONST(1)
+
+// Vbus wakeup alternate status
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_FIELD                    (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_RANGE                    0:0
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_WOFFSET                  0x0
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_UNSET                    _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SET                      _MK_ENUM_CONST(1)
+
+
+// Register USB1_IF_USB1_LEGACY_CTRL_0  
+#define USB1_IF_USB1_LEGACY_CTRL_0                      _MK_ADDR_CONST(0x410)
+#define USB1_IF_USB1_LEGACY_CTRL_0_SECURE                       0x0
+#define USB1_IF_USB1_LEGACY_CTRL_0_WORD_COUNT                   0x1
+#define USB1_IF_USB1_LEGACY_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0x7)
+#define USB1_IF_USB1_LEGACY_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_READ_MASK                    _MK_MASK_CONST(0x7)
+#define USB1_IF_USB1_LEGACY_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x7)
+// Vbus_sense control
+// Controls which VBUS sensor input is driven to the controller.
+// 00: Use VBUS_WAKEUP.
+// 01: Use (A_SESS_VLD || B_SESS_VLD) output from the PHY if the PHY clock is available.
+// Otherwise, use VBUS_WAKEUP.
+// 10: Use (A_SESS_VLD || B_SESS_VLD) output from the PHY
+// 11: Use A_SESS_VLD output from the PHY
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_FIELD                    (_MK_MASK_CONST(0x3) << USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_SHIFT)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_RANGE                    2:1
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_WOFFSET                  0x0
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_VBUS_WAKEUP                      _MK_ENUM_CONST(0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP                       _MK_ENUM_CONST(1)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_AB_SESS_VLD                      _MK_ENUM_CONST(2)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_VBUS_SENSE_CTL_A_SESS_VLD                       _MK_ENUM_CONST(3)
+
+// Legacy registers select
+// The default is to select legacy mode registers in 
+// APB_MISC for USB1. Selects new registers if this is set to 1.
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_NO_LEGACY_MODE_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_NO_LEGACY_MODE_FIELD                    (_MK_MASK_CONST(0x1) << USB1_IF_USB1_LEGACY_CTRL_0_USB1_NO_LEGACY_MODE_SHIFT)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_NO_LEGACY_MODE_RANGE                    0:0
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_NO_LEGACY_MODE_WOFFSET                  0x0
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_NO_LEGACY_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_NO_LEGACY_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_NO_LEGACY_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_NO_LEGACY_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_NO_LEGACY_MODE_LEGACY                   _MK_ENUM_CONST(0)
+#define USB1_IF_USB1_LEGACY_CTRL_0_USB1_NO_LEGACY_MODE_NEW                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 1044 [0x414] 
+
+// Reserved address 1048 [0x418] 
+
+// Reserved address 1052 [0x41c] 
+
+// Register USB1_IF_USB_INTER_PKT_DELAY_CTRL_0  
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0                      _MK_ADDR_CONST(0x420)
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_SECURE                       0x0
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_WORD_COUNT                   0x1
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x6)
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_READ_MASK                    _MK_MASK_CONST(0x3f)
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
+// HS Tx to Tx inter-packet delay.
+// Software should not change this.
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_FIELD                      (_MK_MASK_CONST(0x3f) << USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SHIFT)
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_RANGE                      5:0
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_WOFFSET                    0x0
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_DEFAULT                    _MK_MASK_CONST(0x6)
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 1060 [0x424] 
+
+// Reserved address 1064 [0x428] 
+
+// Register USB1_IF_USB_DEBUG_0  
+#define USB1_IF_USB_DEBUG_0                     _MK_ADDR_CONST(0x480)
+#define USB1_IF_USB_DEBUG_0_SECURE                      0x0
+#define USB1_IF_USB_DEBUG_0_WORD_COUNT                  0x1
+#define USB1_IF_USB_DEBUG_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_DEBUG_0_RESET_MASK                  _MK_MASK_CONST(0x60)
+#define USB1_IF_USB_DEBUG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_DEBUG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_DEBUG_0_READ_MASK                   _MK_MASK_CONST(0x60)
+#define USB1_IF_USB_DEBUG_0_WRITE_MASK                  _MK_MASK_CONST(0x60)
+// Lower 32-bits select.
+// Only valid for Tx and Rx memories that
+// have 36-bit interface. When 0, selects
+// upper 4-bits. When 1, selects lower
+// 32-bits.
+#define USB1_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SHIFT)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_RANGE                 6:6
+#define USB1_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_WOFFSET                       0x0
+#define USB1_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_UPPER_BITS                    _MK_ENUM_CONST(0)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_LOWER_BITS                    _MK_ENUM_CONST(1)
+
+// Route USB buffers to AHB interface for debug.
+// When this is set to 1, normal USB
+// operations cannot be done.
+#define USB1_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_FIELD                    (_MK_MASK_CONST(0x1) << USB1_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SHIFT)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_RANGE                    5:5
+#define USB1_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_WOFFSET                  0x0
+#define USB1_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_DISABLE                  _MK_ENUM_CONST(0)
+#define USB1_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register USB1_IF_USB_PHY_SELF_TEST_0  
+#define USB1_IF_USB_PHY_SELF_TEST_0                     _MK_ADDR_CONST(0x484)
+#define USB1_IF_USB_PHY_SELF_TEST_0_SECURE                      0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_WORD_COUNT                  0x1
+#define USB1_IF_USB_PHY_SELF_TEST_0_RESET_VAL                   _MK_MASK_CONST(0x10150008)
+#define USB1_IF_USB_PHY_SELF_TEST_0_RESET_MASK                  _MK_MASK_CONST(0xfffff37f)
+#define USB1_IF_USB_PHY_SELF_TEST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_READ_MASK                   _MK_MASK_CONST(0xfffff37f)
+#define USB1_IF_USB_PHY_SELF_TEST_0_WRITE_MASK                  _MK_MASK_CONST(0xffff7373)
+// No of test packets to be sent. 0 = infinite, continue sending
+// packets until test mode is disabled.
+#define USB1_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SHIFT                  _MK_SHIFT_CONST(24)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_FIELD                  (_MK_MASK_CONST(0xff) << USB1_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_RANGE                  31:24
+#define USB1_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_DEFAULT                        _MK_MASK_CONST(0x10)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Interpacket delay between two consecutive packets in no of 60 Mhz cycles
+#define USB1_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB1_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_FIELD                      (_MK_MASK_CONST(0xff) << USB1_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_RANGE                      23:16
+#define USB1_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_WOFFSET                    0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_DEFAULT                    _MK_MASK_CONST(0x15)
+#define USB1_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB1_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Status of Disconnect signal from PHY
+#define USB1_IF_USB_PHY_SELF_TEST_0_DISCON_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DISCON_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST_0_DISCON_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DISCON_RANGE                        15:15
+#define USB1_IF_USB_PHY_SELF_TEST_0_DISCON_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_DISCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DISCON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DISCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DISCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DISCON_UNSET                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DISCON_SET                  _MK_ENUM_CONST(1)
+
+// Enable transmission of SOF
+#define USB1_IF_USB_PHY_SELF_TEST_0_SOF_EN_SHIFT                        _MK_SHIFT_CONST(14)
+#define USB1_IF_USB_PHY_SELF_TEST_0_SOF_EN_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST_0_SOF_EN_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_SOF_EN_RANGE                        14:14
+#define USB1_IF_USB_PHY_SELF_TEST_0_SOF_EN_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_SOF_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_SOF_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_0_SOF_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_SOF_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_SOF_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_SOF_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable pulldown on DP
+#define USB1_IF_USB_PHY_SELF_TEST_0_DPPD_SHIFT                  _MK_SHIFT_CONST(13)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DPPD_FIELD                  (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST_0_DPPD_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DPPD_RANGE                  13:13
+#define USB1_IF_USB_PHY_SELF_TEST_0_DPPD_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_DPPD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DPPD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DPPD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DPPD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DPPD_DISABLE                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DPPD_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable pulldown on DM
+#define USB1_IF_USB_PHY_SELF_TEST_0_DMPD_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DMPD_FIELD                  (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST_0_DMPD_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DMPD_RANGE                  12:12
+#define USB1_IF_USB_PHY_SELF_TEST_0_DMPD_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_DMPD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DMPD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DMPD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DMPD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DMPD_DISABLE                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_DMPD_ENABLE                 _MK_ENUM_CONST(1)
+
+// Operational Mode
+#define USB1_IF_USB_PHY_SELF_TEST_0_OPMODE_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB1_IF_USB_PHY_SELF_TEST_0_OPMODE_FIELD                        (_MK_MASK_CONST(0x3) << USB1_IF_USB_PHY_SELF_TEST_0_OPMODE_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_OPMODE_RANGE                        9:8
+#define USB1_IF_USB_PHY_SELF_TEST_0_OPMODE_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_OPMODE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_OPMODE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define USB1_IF_USB_PHY_SELF_TEST_0_OPMODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_OPMODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Term_select
+#define USB1_IF_USB_PHY_SELF_TEST_0_TERM_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TERM_FIELD                  (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST_0_TERM_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TERM_RANGE                  6:6
+#define USB1_IF_USB_PHY_SELF_TEST_0_TERM_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_TERM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TERM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TERM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TERM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// XCVR_select:
+#define USB1_IF_USB_PHY_SELF_TEST_0_XCVR_SHIFT                  _MK_SHIFT_CONST(4)
+#define USB1_IF_USB_PHY_SELF_TEST_0_XCVR_FIELD                  (_MK_MASK_CONST(0x3) << USB1_IF_USB_PHY_SELF_TEST_0_XCVR_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_XCVR_RANGE                  5:4
+#define USB1_IF_USB_PHY_SELF_TEST_0_XCVR_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_XCVR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_XCVR_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB1_IF_USB_PHY_SELF_TEST_0_XCVR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_XCVR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// When test is started, this status signal starts as  1 and is set to 0 if an error is detected. Can be sampled when TSTEND is  asserted.
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTPS_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTPS_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST_0_TSTPS_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTPS_RANGE                 3:3
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTPS_WOFFSET                       0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTPS_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTPS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTPS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTPS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTPS_UNSET                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTPS_SET                   _MK_ENUM_CONST(1)
+
+// Goes to 1 when the test finishes. At that time,  TSTPASS is valid and indicates the tests pass/fail status
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTEND_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTEND_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST_0_TSTEND_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTEND_RANGE                        2:2
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTEND_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTEND_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTEND_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTEND_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTEND_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTEND_UNSET                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTEND_SET                  _MK_ENUM_CONST(1)
+
+// Sw writes a 1 to start the test. It writes a 0 to  end the test
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTON_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTON_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST_0_TSTON_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTON_RANGE                 1:1
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTON_WOFFSET                       0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTON_UNSET                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTON_SET                   _MK_ENUM_CONST(1)
+
+// Place UTMIP in test mode. This does not start the test.
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTENB_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTENB_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST_0_TSTENB_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTENB_RANGE                        0:0
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTENB_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTENB_DISABLE                      _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_0_TSTENB_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register USB1_IF_USB_PHY_SELF_TEST2_0  
+#define USB1_IF_USB_PHY_SELF_TEST2_0                    _MK_ADDR_CONST(0x488)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SECURE                     0x0
+#define USB1_IF_USB_PHY_SELF_TEST2_0_WORD_COUNT                         0x1
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
+// Enable reception of test packets
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_FIELD                 (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_RANGE                 4:4
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_WOFFSET                       0x0
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_DISABLE                       _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable transmission of test packets
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_FIELD                        (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_RANGE                        3:3
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_WOFFSET                      0x0
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_DISABLE                      _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable TEST_J transmission
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_FIELD                  (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_RANGE                  2:2
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_DISABLE                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable TEST_K transmission
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_FIELD                  (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_RANGE                  1:1
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_WOFFSET                        0x0
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_DISABLE                        _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_ENABLE                 _MK_ENUM_CONST(1)
+
+// If enabled, send SOF with EOP of J, else
+// send SOF with EOP of K
+#define USB1_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_FIELD                   (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_RANGE                   0:0
+#define USB1_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_WOFFSET                 0x0
+#define USB1_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_DISABLE                 _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Register USB1_IF_USB_PHY_SELF_TEST_DEBUG_0  
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0                       _MK_ADDR_CONST(0x48c)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_SECURE                        0x0
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_WORD_COUNT                    0x1
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RESET_MASK                    _MK_MASK_CONST(0x3ff3f)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_READ_MASK                     _MK_MASK_CONST(0x3ff3f)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// RX compare fail. Comparison on RX data failed.
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SHIFT                   _MK_SHIFT_CONST(17)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_FIELD                   (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_RANGE                   17:17
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_WOFFSET                 0x0
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_UNSET                   _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SET                     _MK_ENUM_CONST(1)
+
+// Rx valid/Rx validh fail: Indicates that the  Rxvalid/Rxvalidh werent generated according to protocol
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_FIELD                   (_MK_MASK_CONST(0x1) << USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_RANGE                   16:16
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_WOFFSET                 0x0
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_UNSET                   _MK_ENUM_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SET                     _MK_ENUM_CONST(1)
+
+// Failed packet no: Points to the failed packet no
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_FIELD                     (_MK_MASK_CONST(0xff) << USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_RANGE                     15:8
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_WOFFSET                   0x0
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Failed RX byte index: Points to the Rx byte no. in  the current packet which fails
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_FIELD                    (_MK_MASK_CONST(0x3f) << USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SHIFT)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_RANGE                    5:0
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_WOFFSET                  0x0
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_PLL_CFG0_0  // USB_PHY PLL Configuration Register 0
+//
+// The data sampling frequency relies on a 960MHz clock, so the goal of the PLL is to have:
+// In_Frequency*(PLL_VCOMULTBY2+1)*(PLL_NDIV/PLL_MDIV) = 960MHz
+//
+// With a 12MHz input from PLL_U, the default setting of 
+// PLL_VCOMULTBY2=1, PLL_NDIV=40 and PLL_MDIV=1 results in a correct output.
+#define USB1_UTMIP_PLL_CFG0_0                   _MK_ADDR_CONST(0x800)
+#define USB1_UTMIP_PLL_CFG0_0_SECURE                    0x0
+#define USB1_UTMIP_PLL_CFG0_0_WORD_COUNT                        0x1
+#define USB1_UTMIP_PLL_CFG0_0_RESET_VAL                         _MK_MASK_CONST(0x280180)
+#define USB1_UTMIP_PLL_CFG0_0_RESET_MASK                        _MK_MASK_CONST(0x7fffffff)
+#define USB1_UTMIP_PLL_CFG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_READ_MASK                         _MK_MASK_CONST(0x7fffffff)
+#define USB1_UTMIP_PLL_CFG0_0_WRITE_MASK                        _MK_MASK_CONST(0x7fffffff)
+// LOCK_ENABLE input of USB_PHY PLL.
+// Normally only used during test. See cell specification.
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_RANGE                        0:0
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_WOFFSET                      0x0
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// LOCKSEL[5:0] input of USB_PHY PLL.
+// Used in test modes only. See cell specification.
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_FIELD                   (_MK_MASK_CONST(0x3f) << USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_RANGE                   6:1
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_WOFFSET                 0x0
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// VCOMULTBY2 control of the UTMIP PHY PLL.
+// Recommended setting is on. Additional divide by 2 on the 
+// VCO feedback. Which is setting the bit to 1. See cell spec.
+//
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT                        _MK_SHIFT_CONST(7)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_RANGE                        7:7
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_WOFFSET                      0x0
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// MDIV[7:0] input of the USB_PHY PLL. This is the predivide on the PLL. 
+// 0x0 is not allowed. See cell specification.
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_FIELD                      (_MK_MASK_CONST(0xff) << USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_RANGE                      15:8
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_WOFFSET                    0x0
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// NDIV[7:0] input of USB_PHY PLL. 
+// This is the feedback divider on the VCO feedback. 
+// 0x0 is not allowed. See cell specification.
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_FIELD                      (_MK_MASK_CONST(0xff) << USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_RANGE                      23:16
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_WOFFSET                    0x0
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT                    _MK_MASK_CONST(0x28)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// PDIV[2:0] input of the USB_PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT                      _MK_SHIFT_CONST(24)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_FIELD                      (_MK_MASK_CONST(0x7) << USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_RANGE                      26:24
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_WOFFSET                    0x0
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// PDIVRST of the UTMIP PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT                   _MK_SHIFT_CONST(27)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_RANGE                   27:27
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_WOFFSET                 0x0
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Selects which of the eight 60MHz clock phases to produce at the output 
+// of the USB PHY PLL. This is for a test mode. See cell specification.
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT                    _MK_SHIFT_CONST(28)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_FIELD                    (_MK_MASK_CONST(0x7) << USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_RANGE                    30:28
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_WOFFSET                  0x0
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_PLL_CFG1_0  // UTMIP PLL and PLLU configuration register 1
+#define USB1_UTMIP_PLL_CFG1_0                   _MK_ADDR_CONST(0x804)
+#define USB1_UTMIP_PLL_CFG1_0_SECURE                    0x0
+#define USB1_UTMIP_PLL_CFG1_0_WORD_COUNT                        0x1
+#define USB1_UTMIP_PLL_CFG1_0_RESET_VAL                         _MK_MASK_CONST(0x182000c0)
+#define USB1_UTMIP_PLL_CFG1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_PLL_CFG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_PLL_CFG1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Determines the time to wait until the output of USB_PHY PLL is considered stable. 
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_FIELD                       (_MK_MASK_CONST(0xfff) << USB1_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_RANGE                       11:0
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_WOFFSET                     0x0
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT                     _MK_MASK_CONST(0xc0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT_MASK                        _MK_MASK_CONST(0xfff)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input off. (Overrides FORCE_PLL_ACTIVE_POWERUP.)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE                    12:12
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_WOFFSET                  0x0
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input on. 
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT                      _MK_SHIFT_CONST(13)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE                      13:13
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_WOFFSET                    0x0
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input off. (Overrides FORCE_PLL_ENABLE_POWERUP.)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT                    _MK_SHIFT_CONST(14)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE                    14:14
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_WOFFSET                  0x0
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input on. 
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT                      _MK_SHIFT_CONST(15)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE                      15:15
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_WOFFSET                    0x0
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power down. (Overrides FORCE_PLLU_POWERUP.)  
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_FIELD                  (_MK_MASK_CONST(0x1) << USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_RANGE                  16:16
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_WOFFSET                        0x0
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power up.
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_RANGE                    17:17
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_WOFFSET                  0x0
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SETUP[8:0] input of USB_PHY PLL.
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_FIELD                     (_MK_MASK_CONST(0x1ff) << USB1_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_RANGE                     26:18
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_WOFFSET                   0x0
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT                   _MK_MASK_CONST(0x8)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Controls the wait time to enable PLL_U when coming out of suspend or reset.
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT                 _MK_SHIFT_CONST(27)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_FIELD                 (_MK_MASK_CONST(0x1f) << USB1_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE                 31:27
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_WOFFSET                       0x0
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT                       _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_XCVR_CFG0_0  // UTMIP transceiver cell configuration register 0
+#define USB1_UTMIP_XCVR_CFG0_0                  _MK_ADDR_CONST(0x808)
+#define USB1_UTMIP_XCVR_CFG0_0_SECURE                   0x0
+#define USB1_UTMIP_XCVR_CFG0_0_WORD_COUNT                       0x1
+#define USB1_UTMIP_XCVR_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x20202500)
+#define USB1_UTMIP_XCVR_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_XCVR_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_XCVR_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// SETUP[3:0] input of XCVR cell. HS driver output control. 4 LSBs.
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_FIELD                   (_MK_MASK_CONST(0xf) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_RANGE                   3:0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_WOFFSET                 0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// HS slew rate control. The two LSBs.
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT                  _MK_SHIFT_CONST(4)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_FIELD                  (_MK_MASK_CONST(0x3) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_RANGE                  5:4
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_WOFFSET                        0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// FS slew rate control.
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_FIELD                  (_MK_MASK_CONST(0x3) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_RANGE                  7:6
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_WOFFSET                        0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// LS rising slew rate control.
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_FIELD                 (_MK_MASK_CONST(0x3) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_RANGE                 9:8
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_WOFFSET                       0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// LS falling slew rate control.
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT                 _MK_SHIFT_CONST(10)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_FIELD                 (_MK_MASK_CONST(0x3) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_RANGE                 11:10
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_WOFFSET                       0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Internal loopback inside XCVR cell. Used for IOBIST.
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_RANGE                      12:12
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_WOFFSET                    0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Enable HS termination.
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT                  _MK_SHIFT_CONST(13)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_FIELD                  (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_RANGE                  13:13
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_WOFFSET                        0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force PD input into power down. (Overrides FORCE_PD_POWERUP.)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT                   _MK_SHIFT_CONST(14)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_RANGE                   14:14
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_WOFFSET                 0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Force PD input into power up. 
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT                     _MK_SHIFT_CONST(15)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_RANGE                     15:15
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_WOFFSET                   0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power down. (Overrides FORCE_PD2_POWERUP.)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_FIELD                  (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_RANGE                  16:16
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_WOFFSET                        0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power up.
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_RANGE                    17:17
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_WOFFSET                  0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power down. (Overrides FORCE_PDZI_POWERUP.)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_RANGE                 18:18
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_WOFFSET                       0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power up.
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT                   _MK_SHIFT_CONST(19)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_RANGE                   19:19
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_WOFFSET                 0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Disconnect method on the usb transceiver pad
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SHIFT                   _MK_SHIFT_CONST(20)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_RANGE                   20:20
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_WOFFSET                 0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Low speed bias selection method for usb transceiver pad
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SHIFT                      _MK_SHIFT_CONST(21)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_RANGE                      21:21
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_WOFFSET                    0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Most significant bits of SETUP.
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SHIFT                       _MK_SHIFT_CONST(22)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_FIELD                       (_MK_MASK_CONST(0x7) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_RANGE                       24:22
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_WOFFSET                     0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Most significant bits of HS_SLEW.
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SHIFT                      _MK_SHIFT_CONST(25)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_FIELD                      (_MK_MASK_CONST(0x7f) << USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_RANGE                      31:25
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_WOFFSET                    0x0
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_DEFAULT                    _MK_MASK_CONST(0x10)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_BIAS_CFG0_0  // UTMIP Bias cell configuration register 0
+#define USB1_UTMIP_BIAS_CFG0_0                  _MK_ADDR_CONST(0x80c)
+#define USB1_UTMIP_BIAS_CFG0_0_SECURE                   0x0
+#define USB1_UTMIP_BIAS_CFG0_0_WORD_COUNT                       0x1
+#define USB1_UTMIP_BIAS_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x1ffffff)
+#define USB1_UTMIP_BIAS_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x1ffffff)
+#define USB1_UTMIP_BIAS_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x1ffffff)
+// HS squelch detector level.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_FIELD                      (_MK_MASK_CONST(0x3) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_RANGE                      1:0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_WOFFSET                    0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HS disconnect detector level.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_FIELD                       (_MK_MASK_CONST(0x3) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_RANGE                       3:2
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_WOFFSET                     0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HS chirp detector level.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_FIELD                        (_MK_MASK_CONST(0x3) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_RANGE                        5:4
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_WOFFSET                      0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// SessionEnd detector level.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_FIELD                     (_MK_MASK_CONST(0x3) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_RANGE                     7:6
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_WOFFSET                   0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Vbus detector level.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_FIELD                     (_MK_MASK_CONST(0x3) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_RANGE                     9:8
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_WOFFSET                   0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Power down bias circuit.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_FIELD                       (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_RANGE                       10:10
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_WOFFSET                     0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Power down OTG circuit.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT                        _MK_SHIFT_CONST(11)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_RANGE                        11:11
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_WOFFSET                      0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Active 1.5K pullup control offset.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT                 _MK_SHIFT_CONST(12)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_FIELD                 (_MK_MASK_CONST(0x7) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_RANGE                 14:12
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_WOFFSET                       0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Active termination control offset.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT                   _MK_SHIFT_CONST(15)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_FIELD                   (_MK_MASK_CONST(0x7) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_RANGE                   17:15
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_WOFFSET                 0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 0: StaticGpi = IdDig. 1: StaticGpi = GPI_VAL.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_RANGE                      18:18
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_WOFFSET                    0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// See GPI_SEL.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT                      _MK_SHIFT_CONST(19)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_RANGE                      19:19
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_WOFFSET                    0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 0: IdDig = IdDig. 1: IdDig = IDDIG_VAL.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT                    _MK_SHIFT_CONST(20)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_RANGE                    20:20
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_WOFFSET                  0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// See IDDIG_SEL.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_RANGE                    21:21
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_WOFFSET                  0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 0: IDPD = ~IdPullup. 1: IDPD = IDPD_VAL.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT                     _MK_SHIFT_CONST(22)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_RANGE                     22:22
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_WOFFSET                   0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// See IDPD_SEL.
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT                     _MK_SHIFT_CONST(23)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_RANGE                     23:23
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_WOFFSET                   0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Most significant bit of UTMIP_HSDISCON_LEVEL, bit 2
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SHIFT                   _MK_SHIFT_CONST(24)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SHIFT)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_RANGE                   24:24
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_WOFFSET                 0x0
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_HSRX_CFG0_0  // UTMIP High speed receive config 0 
+#define USB1_UTMIP_HSRX_CFG0_0                  _MK_ADDR_CONST(0x810)
+#define USB1_UTMIP_HSRX_CFG0_0_SECURE                   0x0
+#define USB1_UTMIP_HSRX_CFG0_0_WORD_COUNT                       0x1
+#define USB1_UTMIP_HSRX_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x91653400)
+#define USB1_UTMIP_HSRX_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_HSRX_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_HSRX_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// Require 4 sync pattern transitions (01) instead of 3
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_RANGE                        0:0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_WOFFSET                      0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Sync pattern detection needs 3 consecutive samples instead of 4
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_FIELD                       (_MK_MASK_CONST(0x1) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_RANGE                       1:1
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_WOFFSET                     0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Based on incoming edges and current sampling position, adjust phase
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_FIELD                 (_MK_MASK_CONST(0x3) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_RANGE                 3:2
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_WOFFSET                       0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Retime the path. 
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT                       _MK_SHIFT_CONST(4)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_FIELD                       (_MK_MASK_CONST(0x3) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_RANGE                       5:4
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_WOFFSET                     0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Pass through the feedback, do not block it.
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT                        _MK_SHIFT_CONST(6)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_RANGE                        6:6
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_WOFFSET                      0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// When in Chirp Mode, allow chirp rx data through
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT                   _MK_SHIFT_CONST(7)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_RANGE                   7:7
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_WOFFSET                 0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Do not declare underrun errors
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_RANGE                     8:8
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_WOFFSET                   0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Do not declare overrun errors until overflow of FIFO
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT                      _MK_SHIFT_CONST(9)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_RANGE                      9:9
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_WOFFSET                    0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Depth of elastic input store
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT                        _MK_SHIFT_CONST(10)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_FIELD                        (_MK_MASK_CONST(0x1f) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_RANGE                        14:10
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_WOFFSET                      0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT                      _MK_MASK_CONST(0xd)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Number of cycles of idle to declare IDLE. 
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT                    _MK_SHIFT_CONST(15)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_FIELD                    (_MK_MASK_CONST(0x1f) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_RANGE                    19:15
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_WOFFSET                  0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT                  _MK_MASK_CONST(0xa)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Do not strip incoming data
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT                 _MK_SHIFT_CONST(20)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_RANGE                 20:20
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_WOFFSET                       0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Limit the delay of the squelch at EOP time
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT                      _MK_SHIFT_CONST(21)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_FIELD                      (_MK_MASK_CONST(0x7) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_RANGE                      23:21
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_WOFFSET                    0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT                    _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// The number of (edges-1) needed to move the sampling point
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT                      _MK_SHIFT_CONST(24)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_FIELD                      (_MK_MASK_CONST(0xf) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_RANGE                      27:24
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_WOFFSET                    0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Realign the inertia counters on a new packet
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT                   _MK_SHIFT_CONST(28)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_RANGE                   28:28
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_WOFFSET                 0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Allow consecutive ups and downs on the bits, debug only, set to 0.
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_RANGE                    29:29
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_WOFFSET                  0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Keep the stay alive pattern on active
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_FIELD                  (_MK_MASK_CONST(0x3) << USB1_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_RANGE                  31:30
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_WOFFSET                        0x0
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT                        _MK_MASK_CONST(0x2)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_HSRX_CFG1_0  // UTMIP High speed receive config 1
+#define USB1_UTMIP_HSRX_CFG1_0                  _MK_ADDR_CONST(0x814)
+#define USB1_UTMIP_HSRX_CFG1_0_SECURE                   0x0
+#define USB1_UTMIP_HSRX_CFG1_0_WORD_COUNT                       0x1
+#define USB1_UTMIP_HSRX_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x13)
+#define USB1_UTMIP_HSRX_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0x3f)
+#define USB1_UTMIP_HSRX_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG1_0_READ_MASK                        _MK_MASK_CONST(0x3f)
+#define USB1_UTMIP_HSRX_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0x3f)
+// Allow Keep Alive packets 
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_FIELD                  (_MK_MASK_CONST(0x1) << USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT)
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_RANGE                  0:0
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_WOFFSET                        0x0
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// How long to wait before start of sync launches RxActive
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_FIELD                    (_MK_MASK_CONST(0x1f) << USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT)
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_RANGE                    5:1
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_WOFFSET                  0x0
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT                  _MK_MASK_CONST(0x9)
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_FSLSRX_CFG0_0  // UTMIP full and Low speed receive config 0
+#define USB1_UTMIP_FSLSRX_CFG0_0                        _MK_ADDR_CONST(0x818)
+#define USB1_UTMIP_FSLSRX_CFG0_0_SECURE                         0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_WORD_COUNT                     0x1
+#define USB1_UTMIP_FSLSRX_CFG0_0_RESET_VAL                      _MK_MASK_CONST(0xfd548429)
+#define USB1_UTMIP_FSLSRX_CFG0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_FSLSRX_CFG0_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Give up on packet if a long sequence of J 
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_RANGE                      0:0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_WOFFSET                    0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 20 bits of idle should end the packet if FsLsIdleCountLimitCfg=1.
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_FIELD                        (_MK_MASK_CONST(0x3f) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_RANGE                        6:1
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_WOFFSET                      0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT                      _MK_MASK_CONST(0x14)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Enable the reset of the state machine on extended SE0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT                       _MK_SHIFT_CONST(7)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_FIELD                       (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_RANGE                       7:7
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_WOFFSET                     0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 4 bits of of SEO should exceed the time limit
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_FIELD                 (_MK_MASK_CONST(0x3f) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_RANGE                 13:8
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_WOFFSET                       0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT                       _MK_MASK_CONST(0x4)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Require a full sync pattern to declare the data received
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT                   _MK_SHIFT_CONST(14)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_RANGE                   14:14
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_WOFFSET                 0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Limit the number of bit times a K can last
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT                  _MK_SHIFT_CONST(15)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_FIELD                  (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_RANGE                  15:15
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_WOFFSET                        0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Number of K bits in question
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_FIELD                    (_MK_MASK_CONST(0x3f) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_RANGE                    21:16
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_WOFFSET                  0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT                  _MK_MASK_CONST(0x14)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Only look for transitioning out of EOP
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT                       _MK_SHIFT_CONST(22)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_FIELD                       (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_RANGE                       22:22
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_WOFFSET                     0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Do not allow >= dribble bits 
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT                      _MK_SHIFT_CONST(23)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_FIELD                      (_MK_MASK_CONST(0x7) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_RANGE                      25:23
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_WOFFSET                    0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Do not allow <= dribble bits
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT                      _MK_SHIFT_CONST(26)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_FIELD                      (_MK_MASK_CONST(0x7) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_RANGE                      28:26
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_WOFFSET                    0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT                    _MK_MASK_CONST(0x7)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT                        _MK_SHIFT_CONST(29)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_RANGE                        29:29
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_WOFFSET                      0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Filter SE1
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_RANGE                    30:30
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_WOFFSET                  0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// One SE1, don't allow dribble
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT                    _MK_SHIFT_CONST(31)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_RANGE                    31:31
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_WOFFSET                  0x0
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_FSLSRX_CFG1_0  // UTMIP full and Low speed receive config 1
+#define USB1_UTMIP_FSLSRX_CFG1_0                        _MK_ADDR_CONST(0x81c)
+#define USB1_UTMIP_FSLSRX_CFG1_0_SECURE                         0x0
+#define USB1_UTMIP_FSLSRX_CFG1_0_WORD_COUNT                     0x1
+#define USB1_UTMIP_FSLSRX_CFG1_0_RESET_VAL                      _MK_MASK_CONST(0x2267400)
+#define USB1_UTMIP_FSLSRX_CFG1_0_RESET_MASK                     _MK_MASK_CONST(0x7ffffff)
+#define USB1_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_READ_MASK                      _MK_MASK_CONST(0x7ffffff)
+#define USB1_UTMIP_FSLSRX_CFG1_0_WRITE_MASK                     _MK_MASK_CONST(0x7ffffff)
+// Whether full speed EOP  is determined within 3(0) or 4(1) 60MHz cycles
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_RANGE                      0:0
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_WOFFSET                    0x0
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Whether full speed uses debouncing
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_RANGE                        1:1
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_WOFFSET                      0x0
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Only look for a KK pattern, instead of KJKK
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_FIELD                       (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_RANGE                       2:2
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_WOFFSET                     0x0
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in full speed mode
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_RANGE                 3:3
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_WOFFSET                       0x0
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in low  speed mode
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_RANGE                 4:4
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_WOFFSET                       0x0
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Only for this number of 60MHz of SEO and Idle to end packet
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_FIELD                       (_MK_MASK_CONST(0x3f) << USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_RANGE                       10:5
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_WOFFSET                     0x0
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT                     _MK_MASK_CONST(0x20)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Number of SEO clock cycles to block bit extraction
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT                 _MK_SHIFT_CONST(11)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_FIELD                 (_MK_MASK_CONST(0x3f) << USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_RANGE                 16:11
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_WOFFSET                       0x0
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT                       _MK_MASK_CONST(0xe)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Phase count on which LS bits are extracted
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT                        _MK_SHIFT_CONST(17)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_FIELD                        (_MK_MASK_CONST(0x3f) << USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_RANGE                        22:17
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_WOFFSET                      0x0
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT                      _MK_MASK_CONST(0x13)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Number of clock cycle of LS stable
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT                   _MK_SHIFT_CONST(23)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_FIELD                   (_MK_MASK_CONST(0x7) << USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_RANGE                   25:23
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_WOFFSET                 0x0
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT                 _MK_MASK_CONST(0x4)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Assumes line state filtering table is inclusive, not exclusive
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT                    _MK_SHIFT_CONST(26)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_RANGE                    26:26
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_WOFFSET                  0x0
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_TX_CFG0_0  // UTMIP transmit config signals 
+#define USB1_UTMIP_TX_CFG0_0                    _MK_ADDR_CONST(0x820)
+#define USB1_UTMIP_TX_CFG0_0_SECURE                     0x0
+#define USB1_UTMIP_TX_CFG0_0_WORD_COUNT                         0x1
+#define USB1_UTMIP_TX_CFG0_0_RESET_VAL                  _MK_MASK_CONST(0x10200)
+#define USB1_UTMIP_TX_CFG0_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
+#define USB1_UTMIP_TX_CFG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
+#define USB1_UTMIP_TX_CFG0_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff)
+// Do not sent SYNC or EOP
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_RANGE                 0:0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_WOFFSET                       0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// No encoding, static programming
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_RANGE                    1:1
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_WOFFSET                  0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// No bit stuffing, static programming
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_RANGE                    2:2
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_WOFFSET                  0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 2 -- not likely, for Chirp
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_FIELD                       (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_RANGE                       3:3
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_WOFFSET                     0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 3 -- perhaps, when sending controller made packets
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_RANGE                        4:4
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_WOFFSET                      0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// SIE, not macrocell, detects LineState change to resume
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_RANGE                        5:5
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_WOFFSET                      0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// output enable turns on  1 cycle before
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT                      _MK_SHIFT_CONST(6)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_RANGE                      6:6
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                    0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// output enable turns off 1 cycle after
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                     _MK_SHIFT_CONST(7)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_RANGE                     7:7
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                   0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Disable high speed disconnect
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_RANGE                      8:8
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_WOFFSET                    0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Only check during EOP
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT                     _MK_SHIFT_CONST(9)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_RANGE                     9:9
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_WOFFSET                   0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT                  _MK_SHIFT_CONST(10)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_FIELD                  (_MK_MASK_CONST(0x1f) << USB1_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_RANGE                  14:10
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_WOFFSET                        0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_RANGE                        15:15
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_WOFFSET                      0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Allow SOP to be source of transmit error stuffing
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_RANGE                    16:16
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_WOFFSET                  0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// output enable turns on  1/2 cycle before
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT                      _MK_SHIFT_CONST(17)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_RANGE                      17:17
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                    0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// output enable turns off 1/2 cycle after 
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_RANGE                     18:18
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                   0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// output enable sends an initial J before sync pattern
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT                  _MK_SHIFT_CONST(19)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_FIELD                  (_MK_MASK_CONST(0x1) << USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_RANGE                  19:19
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_WOFFSET                        0x0
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_MISC_CFG0_0  // UTMIP miscellaneous configurations
+#define USB1_UTMIP_MISC_CFG0_0                  _MK_ADDR_CONST(0x824)
+#define USB1_UTMIP_MISC_CFG0_0_SECURE                   0x0
+#define USB1_UTMIP_MISC_CFG0_0_WORD_COUNT                       0x1
+#define USB1_UTMIP_MISC_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x3e00078)
+#define USB1_UTMIP_MISC_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define USB1_UTMIP_MISC_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x7fffffff)
+#define USB1_UTMIP_MISC_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x7fffffff)
+// Use combinational terminations or synced through CLKXTAL
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_RANGE                   0:0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_WOFFSET                 0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Use free running terminations at all time
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_RANGE                    1:1
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_WOFFSET                  0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Ignore free running terminations, even when no clock
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_RANGE                     2:2
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_WOFFSET                   0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Don't use free running terminations during suspend.
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_RANGE                   3:3
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_WOFFSET                 0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Determines if all signal need to be stable to not change a config.
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT                   _MK_SHIFT_CONST(4)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_RANGE                   4:4
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_WOFFSET                 0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of cycles of crystal clock of signal not changing to consider stable.
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_FIELD                 (_MK_MASK_CONST(0x7) << USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_RANGE                 7:5
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_WOFFSET                       0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT                       _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force DM pulldown active.
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_RANGE                      8:8
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_WOFFSET                    0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force DP pulldown active.
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT                      _MK_SHIFT_CONST(9)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_RANGE                      9:9
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_WOFFSET                    0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force DM pullup active.      
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT                      _MK_SHIFT_CONST(10)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_RANGE                      10:10
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_WOFFSET                    0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force DP pullup active.
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT                      _MK_SHIFT_CONST(11)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_RANGE                      11:11
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_WOFFSET                    0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force DM pulldown inactive. (Overrides FORCE_PULLDN_DM.)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_RANGE                    12:12
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_WOFFSET                  0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force DP pulldown inactive. (Overrides FORCE_PULLDN_DP.)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT                    _MK_SHIFT_CONST(13)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_RANGE                    13:13
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_WOFFSET                  0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force DM pullup inactive. (Overrides FORCE_PULLUP_DM.)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT                    _MK_SHIFT_CONST(14)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_RANGE                    14:14
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_WOFFSET                  0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force DP pullup inactive. (Overrides FORCE_PULLUP_DP.)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT                    _MK_SHIFT_CONST(15)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_RANGE                    15:15
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_WOFFSET                  0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force HS termination active.
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_RANGE                        16:16
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_WOFFSET                      0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force HS termination inactive.
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT                      _MK_SHIFT_CONST(17)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_RANGE                      17:17
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_WOFFSET                    0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force HS clock always on.
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_RANGE                    18:18
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_WOFFSET                  0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force error insertion into RX path. (Used for IOBIST.)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT                    _MK_SHIFT_CONST(19)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_FIELD                    (_MK_MASK_CONST(0x3) << USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RANGE                    20:19
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_WOFFSET                  0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_ERR                  _MK_ENUM_CONST(1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RX_ERR                   _MK_ENUM_CONST(2)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_RX_ERR                       _MK_ENUM_CONST(3)
+
+// Don't block changes for 4ms when going from LS to FS (should not happen)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_FIELD                    (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_RANGE                    21:21
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_WOFFSET                  0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Suspend exit requires edge or simply a value...
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_RANGE                 22:22
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_WOFFSET                       0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT                        _MK_SHIFT_CONST(23)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_RANGE                        23:23
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_WOFFSET                      0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT                      _MK_SHIFT_CONST(24)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_RANGE                      24:24
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_WOFFSET                    0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT                  _MK_SHIFT_CONST(25)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_FIELD                  (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_RANGE                  25:25
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_WOFFSET                        0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Use DP/DM as obs bus
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT                 _MK_SHIFT_CONST(26)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_RANGE                 26:26
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_WOFFSET                       0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Select DP/DM obs signals
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT                     _MK_SHIFT_CONST(27)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_FIELD                     (_MK_MASK_CONST(0xf) << USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_RANGE                     30:27
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_WOFFSET                   0x0
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_MISC_CFG1_0  // UTMIP miscellaneous configurations
+#define USB1_UTMIP_MISC_CFG1_0                  _MK_ADDR_CONST(0x828)
+#define USB1_UTMIP_MISC_CFG1_0_SECURE                   0x0
+#define USB1_UTMIP_MISC_CFG1_0_WORD_COUNT                       0x1
+#define USB1_UTMIP_MISC_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x40198024)
+#define USB1_UTMIP_MISC_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define USB1_UTMIP_MISC_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_READ_MASK                        _MK_MASK_CONST(0x7fffffff)
+#define USB1_UTMIP_MISC_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0x7fffffff)
+// Bit 0: 0: 0xa5 -> treat as KeepAlive 
+//        1: treat as regular packet 
+// Bit 1: 0: Turn on FS EOP detection
+//        1: Turn off FS EOP detection
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_FIELD                     (_MK_MASK_CONST(0x3) << USB1_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_RANGE                     1:0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_WOFFSET                   0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_RANGE                      2:2
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_WOFFSET                    0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_RANGE                   3:3
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_WOFFSET                 0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT                      _MK_SHIFT_CONST(4)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_FIELD                      (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_RANGE                      4:4
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_WOFFSET                    0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_RANGE                     5:5
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_WOFFSET                   0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// WRONG! This should be 1ms -> 0x50
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_FIELD                    (_MK_MASK_CONST(0xfff) << USB1_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_RANGE                    17:6
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_WOFFSET                  0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT                  _MK_MASK_CONST(0x600)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 5 us / (1/19.2MHz) = 96 / 16 = 6
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_FIELD                 (_MK_MASK_CONST(0x1f) << USB1_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE                 22:18
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_WOFFSET                       0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT                       _MK_MASK_CONST(0x6)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_FIELD                  (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_RANGE                  23:23
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_WOFFSET                        0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT                     _MK_SHIFT_CONST(24)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_RANGE                     24:24
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_WOFFSET                   0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT                      _MK_SHIFT_CONST(25)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << USB1_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_RANGE                      26:25
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_WOFFSET                    0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 0: Use FS filtering on line state when XcvrSel=3
+// 1: Use LS filtering on line state when XcvrSel=3
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT                   _MK_SHIFT_CONST(27)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_RANGE                   27:27
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_WOFFSET                 0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Use neg edge sync for linestate
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT                        _MK_SHIFT_CONST(28)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_RANGE                        28:28
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_WOFFSET                      0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Bypass LineState reclocking logic
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT                     _MK_SHIFT_CONST(29)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_RANGE                     29:29
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_WOFFSET                   0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Selects whether to enable the crystal clock in the module.
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT                     _MK_SHIFT_CONST(30)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_FIELD                     (_MK_MASK_CONST(0x1) << USB1_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_RANGE                     30:30
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_WOFFSET                   0x0
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_DEBOUNCE_CFG0_0  // UTMIP Avalid and Bvalid debounce
+#define USB1_UTMIP_DEBOUNCE_CFG0_0                      _MK_ADDR_CONST(0x82c)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_SECURE                       0x0
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_WORD_COUNT                   0x1
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// simulation value -- Used for interrupts
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_FIELD                  (_MK_MASK_CONST(0xffff) << USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_RANGE                  15:0
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_WOFFSET                        0x0
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT                        _MK_MASK_CONST(0xffff)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// simulation value -- Used for interrupts
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_FIELD                  (_MK_MASK_CONST(0xffff) << USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_RANGE                  31:16
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_WOFFSET                        0x0
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT                        _MK_MASK_CONST(0xffff)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_BAT_CHRG_CFG0_0  // UTMIP battery charger configuration
+#define USB1_UTMIP_BAT_CHRG_CFG0_0                      _MK_ADDR_CONST(0x830)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_SECURE                       0x0
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_WORD_COUNT                   0x1
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x1f)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x1f)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x1f)
+// Power down charger circuit
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_FIELD                  (_MK_MASK_CONST(0x1) << USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_RANGE                  0:0
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_WOFFSET                        0x0
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_RANGE                       1:1
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_WOFFSET                     0x0
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_RANGE                       2:2
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_WOFFSET                     0x0
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_RANGE                        3:3
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_WOFFSET                      0x0
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_RANGE                        4:4
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_WOFFSET                      0x0
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_SPARE_CFG0_0  // Utmip spare configuration bits 
+#define USB1_UTMIP_SPARE_CFG0_0                 _MK_ADDR_CONST(0x834)
+#define USB1_UTMIP_SPARE_CFG0_0_SECURE                  0x0
+#define USB1_UTMIP_SPARE_CFG0_0_WORD_COUNT                      0x1
+#define USB1_UTMIP_SPARE_CFG0_0_RESET_VAL                       _MK_MASK_CONST(0xffff0000)
+#define USB1_UTMIP_SPARE_CFG0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_SPARE_CFG0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_SPARE_CFG0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_SPARE_CFG0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_SPARE_CFG0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Spare register bits
+// 0: HS_RX_IPG_ERROR_ENABLE
+// 1: HS_RX_FLUSH_ALAP. Flush as late as possible
+// 2: HS_RX_LATE_SQUELCH. Delay Squelch by 1 CLK480 cycle.
+// 3: FUSE_SETUP_SEL. Select between regular CFG value and JTAG values for UX_SETUP
+// 31 to 4: Reserved
+#define USB1_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB1_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT)
+#define USB1_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_RANGE                       31:0
+#define USB1_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_WOFFSET                     0x0
+#define USB1_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT                     _MK_MASK_CONST(0xffff0000)
+#define USB1_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_INIT_ENUM                   -65536
+
+
+// Register USB1_UTMIP_XCVR_CFG1_0  // UTMIP transceiver cell configuration register 1
+#define USB1_UTMIP_XCVR_CFG1_0                  _MK_ADDR_CONST(0x838)
+#define USB1_UTMIP_XCVR_CFG1_0_SECURE                   0x0
+#define USB1_UTMIP_XCVR_CFG1_0_WORD_COUNT                       0x1
+#define USB1_UTMIP_XCVR_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x822a)
+#define USB1_UTMIP_XCVR_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0xffffff)
+#define USB1_UTMIP_XCVR_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_READ_MASK                        _MK_MASK_CONST(0xffffff)
+#define USB1_UTMIP_XCVR_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
+// Force PDDISC input into power down. (Overrides FORCE_PDDISC_POWERUP.)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_FIELD                       (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_RANGE                       0:0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_WOFFSET                     0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Force PDDISC input into power up.
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_RANGE                 1:1
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_WOFFSET                       0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PDCHRP input input into power down. (Overrides FORCE_PDCHRP_POWERUP.)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_FIELD                       (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_RANGE                       2:2
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_WOFFSET                     0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Force PDCHRP input into power up.
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_RANGE                 3:3
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_WOFFSET                       0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PDDR input input into power down. (Overrides FORCE_PDDR_POWERUP.)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_RANGE                 4:4
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_WOFFSET                       0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PDDR input into power up.
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_FIELD                   (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_RANGE                   5:5
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_WOFFSET                 0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Encoded value to use on TCTRL when software override is enabled, 0 to 16 only
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_FIELD                 (_MK_MASK_CONST(0x1f) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_RANGE                 10:6
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_WOFFSET                       0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Use a software override on TCTRL instead of automatic bias control
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SHIFT                 _MK_SHIFT_CONST(11)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_RANGE                 11:11
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_WOFFSET                       0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Encoded value to use on RCTRL when software override is enabled, 0 to 16 only
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SHIFT                 _MK_SHIFT_CONST(12)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_FIELD                 (_MK_MASK_CONST(0x1f) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_RANGE                 16:12
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_WOFFSET                       0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Use a software override on RCTRL instead of automatic bias control
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_FIELD                 (_MK_MASK_CONST(0x1) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_RANGE                 17:17
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_WOFFSET                       0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Range adjusment on terminations.
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_FIELD                  (_MK_MASK_CONST(0xf) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_RANGE                  21:18
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_WOFFSET                        0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Spare bits for usb transceiver pad ECO.
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SHIFT                   _MK_SHIFT_CONST(22)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_FIELD                   (_MK_MASK_CONST(0x3) << USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SHIFT)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_RANGE                   23:22
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_WOFFSET                 0x0
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_BIAS_CFG1_0  // UTMIP Bias cell configuration register 1
+#define USB1_UTMIP_BIAS_CFG1_0                  _MK_ADDR_CONST(0x83c)
+#define USB1_UTMIP_BIAS_CFG1_0_SECURE                   0x0
+#define USB1_UTMIP_BIAS_CFG1_0_WORD_COUNT                       0x1
+#define USB1_UTMIP_BIAS_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x2a)
+#define USB1_UTMIP_BIAS_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0x3fff)
+#define USB1_UTMIP_BIAS_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG1_0_READ_MASK                        _MK_MASK_CONST(0x3fff)
+#define USB1_UTMIP_BIAS_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0x3fff)
+// Force PDTRK input into power down. (Overrides FORCE_PDTRK_POWERUP.)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SHIFT)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_RANGE                        0:0
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_WOFFSET                      0x0
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force PDTRK input into power up.
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SHIFT)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_RANGE                  1:1
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_WOFFSET                        0x0
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force VBUS_WAKEUP input into power down.
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << USB1_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SHIFT)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_RANGE                        2:2
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_WOFFSET                      0x0
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Control the BIAS cell power down lag. The lag should be 20us. For a Xtal clock of 13MHz it should be set a 5. 
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SHIFT                     _MK_SHIFT_CONST(3)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_RANGE                     7:3
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_WOFFSET                   0x0
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_DEFAULT                   _MK_MASK_CONST(0x5)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Debouncer time scaling, factor-1 to slow down debouncing by. So 0 is 1, 1 is 2, etc.
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_FIELD                      (_MK_MASK_CONST(0x3f) << USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_RANGE                      13:8
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_WOFFSET                    0x0
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB1_UTMIP_BIAS_STS0_0  // UTMIP Bias cell status register 0
+#define USB1_UTMIP_BIAS_STS0_0                  _MK_ADDR_CONST(0x840)
+#define USB1_UTMIP_BIAS_STS0_0_SECURE                   0x0
+#define USB1_UTMIP_BIAS_STS0_0_WORD_COUNT                       0x1
+#define USB1_UTMIP_BIAS_STS0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_STS0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_BIAS_STS0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_STS0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_STS0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB1_UTMIP_BIAS_STS0_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// Thermal encoding output from USB bias pad. 
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_FIELD                        (_MK_MASK_CONST(0xffff) << USB1_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SHIFT)
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_RANGE                        15:0
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_WOFFSET                      0x0
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Thermal encoding output from USB bias pad. 
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_FIELD                        (_MK_MASK_CONST(0xffff) << USB1_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SHIFT)
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_RANGE                        31:16
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_WOFFSET                      0x0
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB1_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_0_OUT_0  
+#define USB2_QH_USB2D_QH_EP_0_OUT_0                     _MK_ADDR_CONST(0x1000)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 0 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 0.
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_0_IN_0  
+#define USB2_QH_USB2D_QH_EP_0_IN_0                      _MK_ADDR_CONST(0x1040)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_0_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_0_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 0. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 0.
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_1_OUT_0  
+#define USB2_QH_USB2D_QH_EP_1_OUT_0                     _MK_ADDR_CONST(0x1080)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 1 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 1.
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_1_IN_0  
+#define USB2_QH_USB2D_QH_EP_1_IN_0                      _MK_ADDR_CONST(0x10c0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_1_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_1_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 1. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 1.
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_2_OUT_0  
+#define USB2_QH_USB2D_QH_EP_2_OUT_0                     _MK_ADDR_CONST(0x1100)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 2 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 2.
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_2_IN_0  
+#define USB2_QH_USB2D_QH_EP_2_IN_0                      _MK_ADDR_CONST(0x1140)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_2_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_2_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 2. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 2.
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_3_OUT_0  
+#define USB2_QH_USB2D_QH_EP_3_OUT_0                     _MK_ADDR_CONST(0x1180)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 3 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 3.
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_3_IN_0  
+#define USB2_QH_USB2D_QH_EP_3_IN_0                      _MK_ADDR_CONST(0x11c0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_3_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_3_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 3. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 3.
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_4_OUT_0  
+#define USB2_QH_USB2D_QH_EP_4_OUT_0                     _MK_ADDR_CONST(0x1200)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 4 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 4.
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_4_IN_0  
+#define USB2_QH_USB2D_QH_EP_4_IN_0                      _MK_ADDR_CONST(0x1240)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_4_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_4_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 4. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 4.
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_5_OUT_0  
+#define USB2_QH_USB2D_QH_EP_5_OUT_0                     _MK_ADDR_CONST(0x1280)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 5 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 5.
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_5_IN_0  
+#define USB2_QH_USB2D_QH_EP_5_IN_0                      _MK_ADDR_CONST(0x12c0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_5_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_5_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 5. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 5.
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_6_OUT_0  
+#define USB2_QH_USB2D_QH_EP_6_OUT_0                     _MK_ADDR_CONST(0x1300)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 6 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 6.
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_6_IN_0  
+#define USB2_QH_USB2D_QH_EP_6_IN_0                      _MK_ADDR_CONST(0x1340)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_6_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_6_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 6. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 6.
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_7_OUT_0  
+#define USB2_QH_USB2D_QH_EP_7_OUT_0                     _MK_ADDR_CONST(0x1380)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 7 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 7.
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_7_IN_0  
+#define USB2_QH_USB2D_QH_EP_7_IN_0                      _MK_ADDR_CONST(0x13c0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_7_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_7_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 7. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 7.
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_8_OUT_0  
+#define USB2_QH_USB2D_QH_EP_8_OUT_0                     _MK_ADDR_CONST(0x1400)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 8 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 8.
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_8_IN_0  
+#define USB2_QH_USB2D_QH_EP_8_IN_0                      _MK_ADDR_CONST(0x1440)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_8_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_8_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 8. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 8.
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_9_OUT_0  
+#define USB2_QH_USB2D_QH_EP_9_OUT_0                     _MK_ADDR_CONST(0x1480)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 9 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 9.
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_9_IN_0  
+#define USB2_QH_USB2D_QH_EP_9_IN_0                      _MK_ADDR_CONST(0x14c0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_9_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_9_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 9. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 9.
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_10_OUT_0  
+#define USB2_QH_USB2D_QH_EP_10_OUT_0                    _MK_ADDR_CONST(0x1500)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 10 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 10.
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_10_IN_0  
+#define USB2_QH_USB2D_QH_EP_10_IN_0                     _MK_ADDR_CONST(0x1540)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_10_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_10_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 10. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 10.
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_11_OUT_0  
+#define USB2_QH_USB2D_QH_EP_11_OUT_0                    _MK_ADDR_CONST(0x1580)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 11 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 11.
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_11_IN_0  
+#define USB2_QH_USB2D_QH_EP_11_IN_0                     _MK_ADDR_CONST(0x15c0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_11_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_11_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 11. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 11.
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_12_OUT_0  
+#define USB2_QH_USB2D_QH_EP_12_OUT_0                    _MK_ADDR_CONST(0x1600)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 12 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 12.
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_12_IN_0  
+#define USB2_QH_USB2D_QH_EP_12_IN_0                     _MK_ADDR_CONST(0x1640)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_12_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_12_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 12. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 12.
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_13_OUT_0  
+#define USB2_QH_USB2D_QH_EP_13_OUT_0                    _MK_ADDR_CONST(0x1680)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 13 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 13.
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_13_IN_0  
+#define USB2_QH_USB2D_QH_EP_13_IN_0                     _MK_ADDR_CONST(0x16c0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_13_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_13_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 13. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 13.
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_14_OUT_0  
+#define USB2_QH_USB2D_QH_EP_14_OUT_0                    _MK_ADDR_CONST(0x1700)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 14 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 14.
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_14_IN_0  
+#define USB2_QH_USB2D_QH_EP_14_IN_0                     _MK_ADDR_CONST(0x1740)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_14_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_14_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 14. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 14.
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_15_OUT_0  
+#define USB2_QH_USB2D_QH_EP_15_OUT_0                    _MK_ADDR_CONST(0x1780)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 15 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 15.
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_15_IN_0  
+#define USB2_QH_USB2D_QH_EP_15_IN_0                     _MK_ADDR_CONST(0x17c0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_15_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_15_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 15. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 15.
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_RX_MEM_USB2_RX_MEM_0  
+#define USB2_RX_MEM_USB2_RX_MEM_0                       _MK_ADDR_CONST(0x1800)
+#define USB2_RX_MEM_USB2_RX_MEM_0_SECURE                        0x0
+#define USB2_RX_MEM_USB2_RX_MEM_0_WORD_COUNT                    0x1
+#define USB2_RX_MEM_USB2_RX_MEM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB2_RX_MEM_USB2_RX_MEM_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// RX buffer memory
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SHIFT)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_RANGE                     31:0
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_WOFFSET                   0x0
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_RX_MEM_USB2_RX_MEM  
+#define USB2_RX_MEM_USB2_RX_MEM                 _MK_ADDR_CONST(0x1800)
+#define USB2_RX_MEM_USB2_RX_MEM_SECURE                  0x0
+#define USB2_RX_MEM_USB2_RX_MEM_WORD_COUNT                      0x1
+#define USB2_RX_MEM_USB2_RX_MEM_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_RX_MEM_USB2_RX_MEM_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// RX buffer memory
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SHIFT)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_RANGE                       31:0
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_WOFFSET                     0x0
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_TX_MEM_USB2_TX_MEM_0  
+#define USB2_TX_MEM_USB2_TX_MEM_0                       _MK_ADDR_CONST(0x2000)
+#define USB2_TX_MEM_USB2_TX_MEM_0_SECURE                        0x0
+#define USB2_TX_MEM_USB2_TX_MEM_0_WORD_COUNT                    0x1
+#define USB2_TX_MEM_USB2_TX_MEM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB2_TX_MEM_USB2_TX_MEM_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// TX buffer memory
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SHIFT)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_RANGE                     31:0
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_WOFFSET                   0x0
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_TX_MEM_USB2_TX_MEM  
+#define USB2_TX_MEM_USB2_TX_MEM                 _MK_ADDR_CONST(0x2000)
+#define USB2_TX_MEM_USB2_TX_MEM_SECURE                  0x0
+#define USB2_TX_MEM_USB2_TX_MEM_WORD_COUNT                      0x1
+#define USB2_TX_MEM_USB2_TX_MEM_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_TX_MEM_USB2_TX_MEM_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// TX buffer memory
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SHIFT)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_RANGE                       31:0
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_WOFFSET                     0x0
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ID_0  
+#define USB2_CONTROLLER_1_USB2D_ID_0                    _MK_ADDR_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ID_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ID_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ID_0_RESET_VAL                  _MK_MASK_CONST(0x33fa05)
+#define USB2_CONTROLLER_1_USB2D_ID_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_1_USB2D_ID_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ID_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ID_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_1_USB2D_ID_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Revision number of the USB controller. This is set  to 0x33.
+#define USB2_CONTROLLER_1_USB2D_ID_0_REVISION_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ID_0_REVISION_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_ID_0_REVISION_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ID_0_REVISION_RANGE                     23:16
+#define USB2_CONTROLLER_1_USB2D_ID_0_REVISION_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ID_0_REVISION_DEFAULT                   _MK_MASK_CONST(0x33)
+#define USB2_CONTROLLER_1_USB2D_ID_0_REVISION_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_ID_0_REVISION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ID_0_REVISION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Ones complement version of ID. This field is set  to 0xFA.
+#define USB2_CONTROLLER_1_USB2D_ID_0_NID_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_ID_0_NID_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_ID_0_NID_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ID_0_NID_RANGE                  15:8
+#define USB2_CONTROLLER_1_USB2D_ID_0_NID_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ID_0_NID_DEFAULT                        _MK_MASK_CONST(0xfa)
+#define USB2_CONTROLLER_1_USB2D_ID_0_NID_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_ID_0_NID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ID_0_NID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Configuration number. This field is set to 0x05
+#define USB2_CONTROLLER_1_USB2D_ID_0_ID_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ID_0_ID_FIELD                   (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_ID_0_ID_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ID_0_ID_RANGE                   7:0
+#define USB2_CONTROLLER_1_USB2D_ID_0_ID_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_ID_0_ID_DEFAULT                 _MK_MASK_CONST(0x5)
+#define USB2_CONTROLLER_1_USB2D_ID_0_ID_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_ID_0_ID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ID_0_ID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_HW_GENERAL_0  
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0                    _MK_ADDR_CONST(0x4)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_RESET_VAL                  _MK_MASK_CONST(0x35)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_RESET_MASK                         _MK_MASK_CONST(0x1f7)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_READ_MASK                  _MK_MASK_CONST(0x1f7)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// VUSB_HS_PHY_MODE : set to 0 for UTMI PHY
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYM_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYM_FIELD                 (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYM_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYM_RANGE                 8:6
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYM_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYM_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// VUSB_HS_PHY16_8 : Width of the UTMI parallel  interface. Set to 3 : 16-bit UTMI parallel interface software programmable to  8-bit
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYW_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYW_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYW_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYW_RANGE                 5:4
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYW_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYW_DEFAULT                       _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYW_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_PHYW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// VUSB_HS_CLOCK_CONFIGURATION : Clock configuration  2 selected
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_CLKC_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_CLKC_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_CLKC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_CLKC_RANGE                 2:1
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_CLKC_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_CLKC_DEFAULT                       _MK_MASK_CONST(0x2)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_CLKC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_CLKC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_CLKC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// VUSB_HS_RESET_TYPE : set to 1 = asynchronous reset
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_RT_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_RT_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_RT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_RT_RANGE                   0:0
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_RT_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_RT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_RT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_RT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_GENERAL_0_RT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_HW_HOST_0  
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0                       _MK_ADDR_CONST(0x8)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_SECURE                        0x0
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_RESET_VAL                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// VUSB_HS_NUM_PORT-1: This host controller has only  1 port. So this field will always be 0.
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_NPORT_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_NPORT_FIELD                   (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_1_USB2D_HW_HOST_0_NPORT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_NPORT_RANGE                   3:1
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_NPORT_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_NPORT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_NPORT_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_NPORT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_NPORT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// VUSB_HS_HOST: Indicates support for host mode. Set  to 1.
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_HC_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_HC_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_HW_HOST_0_HC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_HC_RANGE                      0:0
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_HC_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_HC_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_HC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_HC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_HOST_0_HC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_HW_DEVICE_0  
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0                     _MK_ADDR_CONST(0xc)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_SECURE                      0x0
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_RESET_VAL                   _MK_MASK_CONST(0x21)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_READ_MASK                   _MK_MASK_CONST(0x3f)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// VUSB_HS_DV_EP: No. of endpoints supported by this device controller. Set to 16. This includes control endpoint 0.
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DEVEP_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DEVEP_FIELD                 (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DEVEP_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DEVEP_RANGE                 5:1
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DEVEP_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DEVEP_DEFAULT                       _MK_MASK_CONST(0x10)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DEVEP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DEVEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DEVEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Device capable: Set to 1 indicating support for device mode.
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DC_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DC_RANGE                    0:0
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DC_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DC_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_DEVICE_0_DC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_HW_TXBUF_0  
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0                      _MK_ADDR_CONST(0x10)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_SECURE                       0x0
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_RESET_VAL                    _MK_MASK_CONST(0x70b08)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// VUSB_HS_TX_CHAN_ADD: Total no. of address bits for the transmit buffer of each transmit endpoint. Set to 7. Each transmit buffer is 128 words deep.
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXCHANADD_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXCHANADD_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXCHANADD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXCHANADD_RANGE                      23:16
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXCHANADD_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXCHANADD_DEFAULT                    _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXCHANADD_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXCHANADD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXCHANADD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VUSB_HS_TX_ADD: Total no. of address bits for the transmit buffer. Set to 11. The total depth of the transmit buffer is 2048 words.
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXADD_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXADD_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXADD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXADD_RANGE                  15:8
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXADD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXADD_DEFAULT                        _MK_MASK_CONST(0xb)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXADD_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXADD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TXADD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// VUSB_HS_TX_BURST: Maximum burst size supported by the transmit endpoints for data transfers. Set to 8.
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TCBURST_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TCBURST_FIELD                        (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TCBURST_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TCBURST_RANGE                        7:0
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TCBURST_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TCBURST_DEFAULT                      _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TCBURST_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TCBURST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_TXBUF_0_TCBURST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_HW_RXBUF_0  
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0                      _MK_ADDR_CONST(0x14)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_SECURE                       0x0
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RESET_VAL                    _MK_MASK_CONST(0x708)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_READ_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// VUSB_HS_RX_ADD: Total no. of address bits for the receive buffer. Set to 7. The total depth of the receive buffer is 128 words
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXADD_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXADD_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXADD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXADD_RANGE                  15:8
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXADD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXADD_DEFAULT                        _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXADD_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXADD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXADD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// VUSB_HS_RX_BURST: Maximum burst size supported by the receive endpoints for data transfers. Set to 8.
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXBURST_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXBURST_FIELD                        (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXBURST_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXBURST_RANGE                        7:0
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXBURST_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXBURST_DEFAULT                      _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXBURST_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXBURST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HW_RXBUF_0_RXBURST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_CAPLENGTH_0  
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0                     _MK_ADDR_CONST(0x100)
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_SECURE                      0x0
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_RESET_VAL                   _MK_MASK_CONST(0x40)
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Indicates which offset to add to the register base address at the beginning of the Operational Register. Set to 0x40.
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_CAPLENGTH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_CAPLENGTH_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_CAPLENGTH_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_CAPLENGTH_RANGE                     7:0
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_CAPLENGTH_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_CAPLENGTH_DEFAULT                   _MK_MASK_CONST(0x40)
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_CAPLENGTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_CAPLENGTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_CAPLENGTH_0_CAPLENGTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_HCIVERSON_0  
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0                     _MK_ADDR_CONST(0x102)
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_SECURE                      0x0
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_RESET_VAL                   _MK_MASK_CONST(0x100)
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_READ_MASK                   _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Contains a BCD encoding of the EHCI revision number supported by this host controller. The most significant byte of this register represents a major revision and the least significant byte is the minor revision. This host controller supports EHCI revision 1.00.
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_HCIVERSION_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_HCIVERSION_FIELD                    (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_1_USB2D_HCIVERSON_0_HCIVERSION_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_HCIVERSION_RANGE                    15:0
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_HCIVERSION_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_HCIVERSION_DEFAULT                  _MK_MASK_CONST(0x100)
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_HCIVERSION_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_HCIVERSION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCIVERSON_0_HCIVERSION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_HCSPARAMS_0  
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0                     _MK_ADDR_CONST(0x104)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_SECURE                      0x0
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_RESET_VAL                   _MK_MASK_CONST(0x1100011)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_RESET_MASK                  _MK_MASK_CONST(0xff0ff1f)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_READ_MASK                   _MK_MASK_CONST(0xff0ff1f)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number of Transaction Translators: indicates the number of embedded transaction translators associated with the USB2.0 host controller. This field is always set to 1 indicating only 1 embedded TT is implemented in this implementation. This is a non-EHCI field to support embedded TT.
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_TT_SHIFT                  _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_TT_FIELD                  (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_TT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_TT_RANGE                  27:24
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_TT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_TT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_TT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_TT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_TT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Number of Ports per Transaction Translator: indicates the number of ports assigned to each transaction translator within the USB2.0 host controller. Field always equals N_PORTS. This is a non-EHCI field to support embedded TT.
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PTT_SHIFT                 _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PTT_FIELD                 (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PTT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PTT_RANGE                 23:20
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PTT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PTT_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PTT_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PTT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PTT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Number of Companion Controller: indicates the number of companion controllers. This field is set to 0.
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_CC_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_CC_FIELD                  (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_CC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_CC_RANGE                  15:12
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_CC_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_CC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_CC_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_CC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_CC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Number of Ports per Companion Controller: indicates the number of ports supported per internal companion controller. This field is set to 0.
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PCC_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PCC_FIELD                 (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PCC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PCC_RANGE                 11:8
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PCC_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PCC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PCC_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PCC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PCC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Port Power Control: indicates whether the host controller implementation includes port power control. 
+// 1 = Ports have port power switches         0= Ports do not have port power switches.
+// This field affects the functionality of the port Power field in each port status and control register. This field is set to 1.
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_PPC_SHIFT                   _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_PPC_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_PPC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_PPC_RANGE                   4:4
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_PPC_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_PPC_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_PPC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_PPC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_PPC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller. This field is fixed to 1, since this host controller only supports 1 port.
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PORTS_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PORTS_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PORTS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PORTS_RANGE                       3:0
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PORTS_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PORTS_DEFAULT                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PORTS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PORTS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCSPARAMS_0_N_PORTS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_HCCPARAMS_0  
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0                     _MK_ADDR_CONST(0x108)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_SECURE                      0x0
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_RESET_VAL                   _MK_MASK_CONST(0x6)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_RESET_MASK                  _MK_MASK_CONST(0xfff6)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_READ_MASK                   _MK_MASK_CONST(0xfff6)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// EHCI Extended Capabilities Pointer: indicates a capabilities list exists. A value of 00h indicates no extended capabilities are implemented. For this implementation this field is always "0". 
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_EECP_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_EECP_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_EECP_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_EECP_RANGE                  15:8
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_EECP_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_EECP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_EECP_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_EECP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_EECP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures  (one or more) before flushing the state. When bit [7] is a one, then host software assumes the host controller may cache an isochronous data structure for an entire frame. This field will always be "0". 
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_IST_SHIFT                   _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_IST_FIELD                   (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_IST_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_IST_RANGE                   7:4
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_IST_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_IST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_IST_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_IST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_IST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Asynchronous Schedule Park Capability. 
+// 1 = (Default) the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. 
+// This field is always 1.
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_ASP_SHIFT                   _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_ASP_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_ASP_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_ASP_RANGE                   2:2
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_ASP_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_ASP_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_ASP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_ASP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_ASP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Programmable Frame List Flag. 
+// 0 = System software must use a frame list length of 1024 elements with this host controller. The USBCMD register Frame List Size field is a read-only register and must be set to zero. 
+// 1 = System software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field.  The frame list must always be aligned on a 4K-page boundary.  This requirement ensures that the frame list is always physically contiguous. 
+// This field will always be "1". 
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_PFL_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_PFL_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_PFL_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_PFL_RANGE                   1:1
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_PFL_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_PFL_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_PFL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_PFL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_HCCPARAMS_0_PFL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_DCIVERSION_0  
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0                    _MK_ADDR_CONST(0x120)
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_RESET_VAL                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this  register. 
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_DCIVERSION_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_DCIVERSION_FIELD                   (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_1_USB2D_DCIVERSION_0_DCIVERSION_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_DCIVERSION_RANGE                   15:0
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_DCIVERSION_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_DCIVERSION_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_DCIVERSION_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_DCIVERSION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_DCIVERSION_0_DCIVERSION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_DCCPARAMS_0  
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0                     _MK_ADDR_CONST(0x124)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_SECURE                      0x0
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_RESET_VAL                   _MK_MASK_CONST(0x190)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_RESET_MASK                  _MK_MASK_CONST(0x19f)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_READ_MASK                   _MK_MASK_CONST(0x19f)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Host Capable: 1 = This controller is capable of operating as an EHCI compatible USB 2 0 host controller operating as an EHCI  compatible USB 2.0 host controller. This field is set to 1.
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_HC_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_HC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_HC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_HC_RANGE                    8:8
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_HC_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_HC_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_HC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_HC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_HC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Device Capable: 1 = Controller is capable of operating as USB 2.0 device. This field is set to 1.
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DC_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DC_RANGE                    7:7
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DC_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DC_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Device Endpoint Number: Number of endpoints built into the device controller. This is set to 16.
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DEN_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DEN_FIELD                   (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DEN_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DEN_RANGE                   4:0
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DEN_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DEN_DEFAULT                 _MK_MASK_CONST(0x10)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_DCCPARAMS_0_DEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_USBCMD_0  
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0                        _MK_ADDR_CONST(0x140)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SECURE                         0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_WORD_COUNT                     0x1
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RESET_VAL                      _MK_MASK_CONST(0x80b00)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RESET_MASK                     _MK_MASK_CONST(0xffebff)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_READ_MASK                      _MK_MASK_CONST(0xffebff)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_WRITE_MASK                     _MK_MASK_CONST(0xffeb7f)
+// Interrupt Threshold Control .Read/Write. Default 08h. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below.  
+// Value          Maximum Interrupt Interval 
+// 00h              Immediate (no threshold) 
+// 01h                1 micro-frame 
+// 02h           2 micro-frames 
+// 04h          4 micro-frames 
+// 08h          8 micro-frames 
+// 10h          16 micro-frames 
+// 20h         32 micro-frames 
+// 40h         64 micro-frames
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_RANGE                      23:16
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_DEFAULT                    _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_IMMEDIATE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_ONE_MF                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_TWO_MF                     _MK_ENUM_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_EIGHT_MF                   _MK_ENUM_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_SIXTEEN_MF                 _MK_ENUM_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_THIRTY_TWO_MF                      _MK_ENUM_CONST(32)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ITC_SIXTY_FOUR_MF                      _MK_ENUM_CONST(64)
+
+// Bit 2 of Frame List Size.
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS2_SHIFT                      _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS2_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBCMD_0_FS2_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS2_RANGE                      15:15
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS2_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Frame List Size . (Read/Write).  000 = Default
+// This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one.  Hence this field is Read/Write for this implementation. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. 
+// Note that this field is made up from USBCMD bits 15, 3 and 2. 
+// 000 = 1024 elements (4096 bytes) Default value 
+// 001 = 512 elements (2048 bytes) 
+// 010 = 256 elements (1024 bytes)  
+// 011 = 128 elements (512 bytes) 
+// 100 = 64 elements (256 bytes) 
+// 101 = 32 elements (128 bytes) 
+// 110 = 16 elements (64 bytes) 
+// 111 = 8 elements (32 bytes)       
+// Only the host controller uses this field. 
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS1_FS0_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS1_FS0_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_USBCMD_0_FS1_FS0_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS1_FS0_RANGE                  3:2
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS1_FS0_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS1_FS0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS1_FS0_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS1_FS0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_FS1_FS0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Setup Tripwire. This bit is used as a semaphore when the 8 bytes  of setup data read extracted by the firmware. If the setup lockout mode is  off, then there exists a hazard when new setup data arrives and firmware is  copying setup data from the QH for a previous setup packet. This bit is set  and cleared by software and will be cleared by hardware when a hazard exists.
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SUTW_SHIFT                     _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SUTW_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBCMD_0_SUTW_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SUTW_RANGE                     13:13
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SUTW_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SUTW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SUTW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SUTW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SUTW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SUTW_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_SUTW_SET                       _MK_ENUM_CONST(1)
+
+// Add DTD Tripwire. This bit is used as a semaphore when a dTD is  added to an active (primed) endpoint. This bit is set and cleared by software  and will be cleared by hardware when a hazard exists such that adding a dTD  to a primed endpoint may go unnoticed.
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ATDTW_SHIFT                    _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ATDTW_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBCMD_0_ATDTW_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ATDTW_RANGE                    14:14
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ATDTW_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ATDTW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ATDTW_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ATDTW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ATDTW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ATDTW_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ATDTW_SET                      _MK_ENUM_CONST(1)
+
+// Asynchronous Schedule Park mode Enable. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled.  This field is set to "1" in this  implementation. 
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASPE_SHIFT                     _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASPE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBCMD_0_ASPE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASPE_RANGE                     11:11
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASPE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASPE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASPE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASPE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Asynchronous Schedule Park Mode Count (OPTIONAL) Read/Write.  If the Asynchronous Park Capability bit in the HCCPARAMS register is a one,  then this field defaults to 3h and is R/W. Otherwise it defaults to zero and  is RO. It contains a count of the number of successive transactions the host  controller is allowed to execute from a high-speed queue head on the  Asynchronous schedule before continuing traversal of the Asynchronous  schedule. Valid values are 1h to 3h. Software must not write a zero to this  bit when Park Mode Enable is a one as this will result in undefined behavior.  This field is set to 3h in this implementation and is Read/Write capable. 
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASP1_ASP0_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASP1_ASP0_FIELD                        (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_USBCMD_0_ASP1_ASP0_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASP1_ASP0_RANGE                        9:8
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASP1_ASP0_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASP1_ASP0_DEFAULT                      _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASP1_ASP0_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASP1_ASP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASP1_ASP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Light Host/Device Controller Reset (OPTIONAL) .  Read Only. Not Implemented. This field will always be "0". 
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_LR_SHIFT                       _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_LR_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBCMD_0_LR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_LR_RANGE                       7:7
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_LR_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_LR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_LR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_LR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_LR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Interrupt on Async Advance Doorbell. When the host controller has evicted all  appropriate cached schedule states, it sets the Interrupt on Async Advance  status bit in the USBSTS register. If the Interrupt on Sync Advance Enable  bit in the USBINTR register is one, then the host controller will assert an  interrupt at the next interrupt threshold. The host controller sets this bit  to zero after it has set the Interrupt on Sync Advance status bit in the  USBSTS register to one. Software should not write a one to this bit when the  asynchronous schedule is inactive. Doing so will yield undefined results. This  bit is only used in host mode. Writing a one to this bit when device mode is  selected will have undefined results. 
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_IAA_SHIFT                      _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_IAA_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBCMD_0_IAA_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_IAA_RANGE                      6:6
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_IAA_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_IAA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_IAA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_IAA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_IAA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_IAA_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_IAA_SET                        _MK_ENUM_CONST(1)
+
+// Asynchronous Schedule Enable. This bit controls whether the host controller skips processing the Asynchronous Schedule. 
+// 0 = Do not process the Asynchronous Schedule. 
+// 1 = Use the ASYNCLISTADDR register to access the  Asynchronous Schedule. 
+// Only the host controller uses this bit. 
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASE_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBCMD_0_ASE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASE_RANGE                      5:5
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASE_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_ASE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Periodic Schedule Enable.This bit controls whether the host controller skips processing the Periodic Schedule. 
+// 0 = Do not process the Periodic Schedule 
+// 1 = Use the PERIODICLISTBASE register to access the Periodic  Schedule. 
+// Only the host controller uses this bit. 
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_PSE_SHIFT                      _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_PSE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBCMD_0_PSE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_PSE_RANGE                      4:4
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_PSE_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_PSE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_PSE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_PSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_PSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_PSE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_PSE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Controller Reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. 
+// Host Controller: 
+// When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero.  Attempting to reset an actively running host controller results in undefined behavior.   
+// Device Controller: 
+// When software writes a one to this bit, the Device  Controller resets its internal pipelines, timers, counters, state machines  etc. to their initial value. Any transaction currently in progress on USB is  immediately terminated. Writing a one to this bit in device mode is not  recommended. 
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RST_SHIFT                      _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RST_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBCMD_0_RST_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RST_RANGE                      1:1
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RST_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RST_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RST_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RST_SET                        _MK_ENUM_CONST(1)
+
+// Run/Stop: 
+// Host Controller: 
+// When set to a 1, the Host Controller proceeds with the execution of the schedule.  
+// The Host Controller continues execution as long as this bit is set to a one.  When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts.  The HCHalted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state.  Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one). 
+// Device Controller: 
+// Writing a one to this bit will cause the device  controller to enable a pull-up on D+ and initiate an attach event. This  control bit is not directly connected to the pull-up enable, as the pull-up  will become disabled upon transitioning into high-speed mode. Software should  use this bit to prevent an attach event before the device controller has been  properly initialized. Writing a 0 to this will cause a detach event. 
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RS_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBCMD_0_RS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RS_RANGE                       0:0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RS_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RS_STOP                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBCMD_0_RS_RUN                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_USBSTS_0  
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0                        _MK_ADDR_CONST(0x144)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SECURE                         0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_WORD_COUNT                     0x1
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RESET_VAL                      _MK_MASK_CONST(0x1000)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RESET_MASK                     _MK_MASK_CONST(0xdf5ff)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_READ_MASK                      _MK_MASK_CONST(0xdf5ff)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_WRITE_MASK                     _MK_MASK_CONST(0xcd5ef)
+// USB Host Periodic Interrupt (USBHSTPERINT)  R/WC. This bit is set by the Host
+// Controller when the cause of an interrupt is a completion of a USB transaction where the
+// Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the
+// periodic schedule.
+// This bit is also set by the Host Controller when a short packet is detected AND the packet is on
+// the periodic schedule. A short packet is when the actual number of bytes received was less
+// than the expected number of bytes.
+// This bit is not used by the device controller and will always be zero.
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UPA_SHIFT                      _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UPA_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_UPA_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UPA_RANGE                      19:19
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UPA_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UPA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UPA_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UPA_ENABLE                     _MK_ENUM_CONST(1)
+
+// USB Host Asynchronous Interrupt (USBHSTASYNCINT)  R/WC. This bit is set by the
+// Host Controller when the cause of an interrupt is a completion of a USB transaction where the
+// Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the
+// asynchronous schedule.
+// This bit is also set by the Host when a short packet is detected AND the packet is on the
+// asynchronous schedule. A short packet is when the actual number of bytes received was
+// less than the expected number of bytes.
+// This bit is not used by the device controller and will always be zero.
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UAI_SHIFT                      _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UAI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_UAI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UAI_RANGE                      18:18
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UAI_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UAI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UAI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UAI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UAI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UAI_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UAI_ENABLE                     _MK_ENUM_CONST(1)
+
+// NAK Interrupt Bit  Read Only. This bit is readonly.
+// It is set by hardware when for a
+// particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint
+// NAK Enable bit are set. This bit is automatically cleared by hardware when the all the enabled
+// TX/RX Endpoint NAK bits are cleared.
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_NAKI_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_NAKI_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_NAKI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_NAKI_RANGE                     16:16
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_NAKI_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_NAKI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_NAKI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_NAKI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_NAKI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_NAKI_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_NAKI_ENABLE                    _MK_ENUM_CONST(1)
+
+// Asynchronous Schedule Status. 
+// This bit reports the current real status of the Asynchronous Schedule.  
+// When set to zero the asynchronous schedule status is disabled and 
+// if set to one the status is enabled.  The Host Controller is not required to 
+// immediately disable or enable the Asynchronous Schedule when software transitions
+// the Asynchronous Schedule Enable bit in the USBCMD register.  
+// If AS = ASE: 
+// 1= Enable Asynchronous Schedule 0= Disable Asynchronous Schedule
+// Only used by the host controller. 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AS_SHIFT                       _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_AS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AS_RANGE                       15:15
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AS_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AS_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AS_ENABLE                      _MK_ENUM_CONST(1)
+
+// Periodic Schedule Status.
+// This bit reports the current real status of the Periodic Schedule. 
+// When set to zero the periodic schedule is disabled, and if set to one
+// the status is enabled. The Host Controller is not required to immediately
+// disable or enable the Periodic Schedule when software transitions
+// the Periodic Schedule Enable bit in the USBCMD register.  
+// If PS = PSE then:
+// 1 = Periodic Schedule is enabled or 0 = Periodic Schedule is disabled
+// Only used by the host controller. 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PS_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_PS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PS_RANGE                       14:14
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PS_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PS_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PS_ENABLE                      _MK_ENUM_CONST(1)
+
+// Reclamation. 
+// This is a read-only status bit used to detect an empty asynchronous schedule.
+// Only used by the host controller. 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RCL_SHIFT                      _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RCL_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_RCL_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RCL_RANGE                      13:13
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RCL_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RCL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RCL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RCL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RCL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RCL_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_RCL_ENABLE                     _MK_ENUM_CONST(1)
+
+// HCHalted. 1 = Default. 
+// This bit is a zero  whenever the Run/Stop bit is a one. 
+// The Host Controller sets this bit to one  after it has stopped 
+// executing because of the Run/Stop bit being set to 0,  either by software
+// or by the Host Controller hardware (e.g. internal error). 
+// Only  used by the host controller. 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_HCH_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_HCH_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_HCH_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_HCH_RANGE                      12:12
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_HCH_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_HCH_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_HCH_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_HCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_HCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_HCH_UNHALTED                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_HCH_HALTED                     _MK_ENUM_CONST(1)
+
+// ULPI Interrupt. This bit is set whenever an interrupt is received from ULPI PHY.
+// Software writes 1 to clear it.
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_ULPI_INT_SHIFT                 _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_ULPI_INT_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_ULPI_INT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_ULPI_INT_RANGE                 10:10
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_ULPI_INT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_ULPI_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_ULPI_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_ULPI_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_ULPI_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_ULPI_INT_NOT_ULPI_INT                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_ULPI_INT_ULPI_INT                      _MK_ENUM_CONST(1)
+
+// DCSuspend. When a device controller enters a suspend state
+// from an active state, this bit will be set to a 1. 
+// The device controller  clears the bit upon exiting from a suspend state.
+// Only used by the device  controller. 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SLI_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SLI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_SLI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SLI_RANGE                      8:8
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SLI_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SLI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SLI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SLI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SLI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SLI_NOTSUSPEND                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SLI_SUSPENDED                  _MK_ENUM_CONST(1)
+
+// SOF Received. When the device controller detects a Start Of
+// (micro) Frame, this bit will be set to a one. 
+// When a SOF is extremely late, the device controller will automatically 
+// set this bit to indicate that an SOF was expected.  
+// Therefore, this bit will be set roughly every 1ms in device FS mode
+// and every 125us in HS mode and will be synchronized to the actual SOF that 
+// is received. Since device controller is initialized to FS before connect, 
+// this bit Will be set at an interval of 1ms during the prelude to the connect
+// and chirp. 
+// In host mode, this bit will be set every 125us and can be used by
+// host controller driver as a time base. 
+// Software writes a 1 to this bit to clear it. This  is a non-EHCI status bit. 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SRI_SHIFT                      _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SRI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_SRI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SRI_RANGE                      7:7
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SRI_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SRI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SRI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SRI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SRI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SRI_SOF_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SRI_SOF_RCVD                   _MK_ENUM_CONST(1)
+
+// USB Reset Received. 
+// When the device controller detects a USB Reset 
+// and  enters the default state, this bit is set to a 1.
+// Software can write a 1 to  this bit to clear the USB Reset
+// Received status bit. 
+// Only used by the device  controller. 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_URI_SHIFT                      _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_URI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_URI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_URI_RANGE                      6:6
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_URI_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_URI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_URI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_URI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_URI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_URI_NO_USB_RESET                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_URI_USB_RESET                  _MK_ENUM_CONST(1)
+
+// Interrupt and Asynchronous Advance. 
+// System software can force the host controller to  issue an interrupt
+// the next time the host controller advances the  asynchronous schedule
+// by writing a one to the Interrupt on Async Advance  Doorbell bit in the
+// USBCMD register. This status bit indicates the assertion  of that interrupt source.
+// Only used by the host controller
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AAI_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AAI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_AAI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AAI_RANGE                      5:5
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AAI_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AAI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AAI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AAI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AAI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AAI_NOT_ADVANCED                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_AAI_ADVANCED                   _MK_ENUM_CONST(1)
+
+// System Error. 
+// This bit is not used in this  implementation and will always be set to "0". 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SEI_SHIFT                      _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SEI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_SEI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SEI_RANGE                      4:4
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SEI_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SEI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SEI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SEI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SEI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SEI_NO_ERROR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_SEI_ERROR                      _MK_ENUM_CONST(1)
+
+// Frame List Rollover. 
+// The Host Controller sets this bit to a 1 when the Frame List Index rolls
+// over from its maximum value to 0. The exact  value at which the rollover
+// occurs depends on the frame list size. For  example. If the frame list
+// size (as programmed in the Frame List Size field  of the USBCMD register)
+// is 1024, the Frame Index Register rolls over every  time FRINDEX [1 3] toggles.
+// Similarly, if the size is 512, the Host  Controller sets this bit to
+// a 1 every time FHINDEX [12] toggles. 
+// Only used  by the host controller. 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_FRI_SHIFT                      _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_FRI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_FRI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_FRI_RANGE                      3:3
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_FRI_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_FRI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_FRI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_FRI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_FRI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_FRI_NO_ROLLOVER                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_FRI_ROLLOVER                   _MK_ENUM_CONST(1)
+
+// Port Change Detect. 
+// The Host Controller sets this bit to a 1 when on any port a Connect
+// Status occurs, a Port Enable/Disable Change occurs, or the  Force
+// Port Resume bit is set as the result of a J-K transition on the
+// suspended port. The Device Controller sets this bit to a one when
+// the port  controller enters the full or high-speed operational state.
+// When the port  controller exits the full or high-speed operational
+// states due to Reset or  Suspend events, the notification mechanisms
+// are the USB Reset Received bit  and the DCSuspend bits respectively. 
+// This bit is not EHCI compatible. 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PCI_SHIFT                      _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PCI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_PCI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PCI_RANGE                      2:2
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PCI_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PCI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PCI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PCI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PCI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PCI_NO_PORT_CHANGE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_PCI_PORT_CHANGE                        _MK_ENUM_CONST(1)
+
+// USB Error Interrupt. 
+// This bit gets set by the Host/Device controller  when completion
+// of a USB transaction results in an error condition. This bit  is set
+// along with the USBINT bit, if the TD on which the error interrupt
+// occurred also ad its interrupt on complete (IOC) bit set. 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UEI_SHIFT                      _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UEI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_UEI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UEI_RANGE                      1:1
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UEI_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UEI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UEI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UEI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UEI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UEI_NO_ERROR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UEI_ERROR                      _MK_ENUM_CONST(1)
+
+// USB Interrupt.
+// This bit is set by the Host/Device Controller when  the cause of
+// an interrupt is a completion of a USB transaction where the
+// Transfer Descriptor (TD) as an interrupt on complete (IOC) bit set.
+// This bit  is also set by the Host/Device Controller when a short
+// packet is detected. A  short packet is when the actual number of bytes
+// received was less than the  expected number of bytes. 
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UI_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UI_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBSTS_0_UI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UI_RANGE                       0:0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UI_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UI_NO_INT                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBSTS_0_UI_INT                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_USBINTR_0  
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0                       _MK_ADDR_CONST(0x148)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SECURE                        0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_RESET_MASK                    _MK_MASK_CONST(0xd05ff)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_READ_MASK                     _MK_MASK_CONST(0xd05ff)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_WRITE_MASK                    _MK_MASK_CONST(0xd05ff)
+// UPIE Interrupt Enable. 1 = USB controller issues an interrupt if UPA bit in USBSTS register transitions.
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UPIE_SHIFT                    _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UPIE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_UPIE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UPIE_RANGE                    19:19
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UPIE_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UPIE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UPIE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UPIE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UPIE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UPIE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UPIE_ENABLE                   _MK_ENUM_CONST(1)
+
+// UAIE Interrupt Enable. 1 = USB controller issues an interrupt if UAI bit in USBSTS register transitions.
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UAIE_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UAIE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_UAIE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UAIE_RANGE                    18:18
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UAIE_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UAIE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UAIE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UAIE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UAIE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UAIE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UAIE_ENABLE                   _MK_ENUM_CONST(1)
+
+// NAK Interrupt Enable. 1 = USB controller issues an interrupt if NAKI bit in USBSTS register transitions.
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_NAKE_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_NAKE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_NAKE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_NAKE_RANGE                    16:16
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_NAKE_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_NAKE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_NAKE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_NAKE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_NAKE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_NAKE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_NAKE_ENABLE                   _MK_ENUM_CONST(1)
+
+// ULPI Interrupt Enable. 1 = USB controller issues an interrupt if ULPI_INT bit in USBSTS register transitions.
+// The interrupt is acknowledged by SW by writing a 1 to the ULPI_INT bit.
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_ULPIE_SHIFT                   _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_ULPIE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_ULPIE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_ULPIE_RANGE                   10:10
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_ULPIE_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_ULPIE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_ULPIE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_ULPIE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_ULPIE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_ULPIE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_ULPIE_ENABLE                  _MK_ENUM_CONST(1)
+
+// Sleep Enable. 1 = Device controller issues an interrupt if  DCSuspend bit in USBSTS register transitions. 
+// The interrupt is acknowledged by SW by writing a 1 to the DCSuspend bit. Only used by the device controller. 
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SLE_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SLE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_SLE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SLE_RANGE                     8:8
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SLE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SLE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SLE_ENABLE                    _MK_ENUM_CONST(1)
+
+// SOF Received Enable. 1 = Device controller issues an interrupt if SOF Received bit in USBSTS register = 1.
+// The interrupt is acknowledged by software clearing  the SOF Received bit. 
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SRE_SHIFT                     _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SRE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_SRE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SRE_RANGE                     7:7
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SRE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SRE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SRE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SRE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SRE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SRE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SRE_ENABLE                    _MK_ENUM_CONST(1)
+
+// USB Reset Enable.1 = Device controller issues an interrupt if USB Reset Received bit in USBSTS register  = 1 
+// The interrupt is acknowledged by software clearing  the USB Reset Received bit. Only used by the device controller. 
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_URE_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_URE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_URE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_URE_RANGE                     6:6
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_URE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_URE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_URE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_URE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_URE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_URE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_URE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Interrupt on Asynchronous Advance Enable. 1 = the host controller issues an interrupt at the  next interrupt threshold if Interrupt on Async Advance bit in USBSTS register  = 1. 
+// The interrupt is acknowledged by software clearing the Interrupt on  Async Advance bit. Only used by the host controller. 
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_AAE_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_AAE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_AAE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_AAE_RANGE                     5:5
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_AAE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_AAE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_AAE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_AAE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_AAE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_AAE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_AAE_ENABLE                    _MK_ENUM_CONST(1)
+
+// System Error Enable. 1 = Host/device controller issues an interrupt if  the System Error bit in USBSTS register = 1.
+// The interrupt is acknowledged by  software clearing the System Error bit. 
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SEE_SHIFT                     _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SEE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_SEE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SEE_RANGE                     4:4
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SEE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SEE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SEE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SEE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SEE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SEE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_SEE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Frame List Rollover Enable. 1 = Host controller issues an interrupt if Frame  List Rollover bit in the USBSTS register = 1.
+// The interrupt is acknowledged  by software clearing the Frame List Rollover bit. Only used by the host  controller. 
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_FRE_SHIFT                     _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_FRE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_FRE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_FRE_RANGE                     3:3
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_FRE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_FRE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_FRE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_FRE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_FRE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_FRE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_FRE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Port Change Detect Enable. 1 = Host/device controller issues an interrupt if  Port Change Detect bit in USBSTS register = 1. 
+// The interrupt is acknowledged  by software clearing the Port Change Detect bit.
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_PCE_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_PCE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_PCE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_PCE_RANGE                     2:2
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_PCE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_PCE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_PCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_PCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_PCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_PCE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_PCE_ENABLE                    _MK_ENUM_CONST(1)
+
+// USB Error Interrupt Enable. 1 = Host controller issues an interrupt at the  next interrupt threshold if the USBERRINT bit in USBSTS = 1. 
+// The interrupt is  acknowledged by software clearing the USBERRINT bit in the USBSTS register. 
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UEE_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UEE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_UEE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UEE_RANGE                     1:1
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UEE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UEE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UEE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UEE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UEE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UEE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UEE_ENABLE                    _MK_ENUM_CONST(1)
+
+// USB Interrupt Enable. 1 = Host/device issues an interrupt at the next  interrupt threshold if the USBINT bit in USBSTS = 1. 
+// The interrupt is  acknowledged by software clearing the USBINT bit.
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBINTR_0_UE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UE_RANGE                      0:0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UE_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBINTR_0_UE_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_FRINDEX_0  
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0                       _MK_ADDR_CONST(0x14c)
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_SECURE                        0x0
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_RESET_MASK                    _MK_MASK_CONST(0x3fff)
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_READ_MASK                     _MK_MASK_CONST(0x3fff)
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Frame Index.  
+// The value in this register increments at the end of each time frame (micro-frame). 
+// Bits [N: 3] are used for the Frame List current index. Each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index.  
+// The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. 
+// USBCMD          [Frame List Size] Number        Elements N 
+//   000b                   (1024)                  12 
+//   001b                   (512)                   11 
+//   010b                   (256)                   10 
+//   011b                   (128)                   9 
+//   100b            (64)                    8 
+//   101b            (32)                    7 
+//   110b            (16)                    6 
+//   111b            (8)                     5 
+// In device mode the value is the current frame  number of the last frame transmitted. It is not used as an index. In either  mode bits 2:0 indicate the current micro-frame. 
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_FRINDEX_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_FRINDEX_FIELD                 (_MK_MASK_CONST(0x3fff) << USB2_CONTROLLER_1_USB2D_FRINDEX_0_FRINDEX_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_FRINDEX_RANGE                 13:0
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_FRINDEX_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_FRINDEX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_FRINDEX_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_FRINDEX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_FRINDEX_0_FRINDEX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 336 [0x150] 
+
+// Register USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0  
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0                      _MK_ADDR_CONST(0x154)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_SECURE                       0x0
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_RESET_MASK                   _MK_MASK_CONST(0xfffff000)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_READ_MASK                    _MK_MASK_CONST(0xfffff000)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff000)
+// Host mode: This 32-bit register contains the beginning address of the Periodic Frame List in the system memory.
+// HCD loads this register prior to starting the schedule execution by the Host Controller.
+// The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned.
+// The contents of this register are combined with the Frame Index Register (FRINDEX)
+// to enable the Host Controller to step through the Periodic Frame List in sequence. 
+// Base Address (Low). These bits correspond to memory address signals [31:12], respectively. 
+// Only used by the host controller. 
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_BASEADR_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_BASEADR_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_BASEADR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_BASEADR_RANGE                        31:12
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_BASEADR_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_BASEADR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_BASEADR_DEFAULT_MASK                 _MK_MASK_CONST(0xfffff)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_BASEADR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_BASEADR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Device mode. The upper seven bits of this register represent the device address. 
+// After any controller reset or a USB reset, the device address is set to the default address (0).
+// The default address will match all incoming addresses. 
+// Software shall reprogram the address after receiving a SET_ADDRESS request. 
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADR_SHIFT                 _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADR_FIELD                 (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADR_RANGE                 31:25
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADR_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Device Address Advance. Default=0. 
+// When this bit is 0, any writes to USBADR are instantaneous. 
+// When this bit is written to a 1 at the same time or before USBADR is written, 
+// the write to the USBADR field is staged and held in a hidden register. 
+// After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register.
+// Hardware will automatically clear this bit on the following conditions:
+// 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register).
+// 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated).
+// 3) Device Reset occurs (USBADR is reset to 0). 
+// Note: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program
+// the USBADR field. This mechanism will ensure this specification is met when 
+// the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. 
+// If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase 
+// (before the prime of the status phase), the USBADR will be programmed instantly 
+// at the correct time and meet the 2ms USB requirement.
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADRA_SHIFT                        _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADRA_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADRA_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADRA_RANGE                        24:24
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADRA_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADRA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADRA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADRA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0_USBADRA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0  
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0                 _MK_ADDR_CONST(0x158)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_SECURE                  0x0
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffe0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffe0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffe0)
+// Host mode. This 32-bit register contains the address of the next asynchronous queue head to be executed by the host.
+// Link Pointer Low (LPL). These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (OH). Only used by the host controller.
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_ASYBASE_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_ASYBASE_FIELD                   (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_ASYBASE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_ASYBASE_RANGE                   31:5
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_ASYBASE_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_ASYBASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_ASYBASE_DEFAULT_MASK                    _MK_MASK_CONST(0x7ffffff)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_ASYBASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_ASYBASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Device mode. This register contains the address of the top of the endpoint list in system memory. These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Heads (QH). Only used by the device controller.
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_EPBASE_SHIFT                    _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_EPBASE_FIELD                    (_MK_MASK_CONST(0x1fffff) << USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_EPBASE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_EPBASE_RANGE                    31:11
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_EPBASE_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_EPBASE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_EPBASE_DEFAULT_MASK                     _MK_MASK_CONST(0x1fffff)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_EPBASE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0_EPBASE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0  
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0                    _MK_ADDR_CONST(0x15c)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_RESET_MASK                         _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_READ_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_WRITE_MASK                         _MK_MASK_CONST(0x2)
+// Embedded TT Async Buffers Clear. (Read/Write to  set) This field will clear all pending transactions in the embedded TT Async  Buffer(s). The clear will take as much time as necessary to clear buffer  without interfering with a transaction in progress. TTAC will return to zero  after being set by software only after the actual clear occurs. 
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAC_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAC_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAC_RANGE                 1:1
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAC_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Embedded TT Async Buffers Status. (Read Only) This  read only bit will be 1 if one or more transactions are being held in the  embedded TT Async. Buffers. When this bit is a zero, then all outstanding  transactions in the embedded TT have been flushed. 
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAS_RANGE                 0:0
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0_TTAS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_BURSTSIZE_0  
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0                     _MK_ADDR_CONST(0x160)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_SECURE                      0x0
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_RESET_VAL                   _MK_MASK_CONST(0x808)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_READ_MASK                   _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
+// Programmable TX Burst Length.  (Read/Write) This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus.
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_TXPBURST_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_TXPBURST_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_TXPBURST_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_TXPBURST_RANGE                      15:8
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_TXPBURST_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_TXPBURST_DEFAULT                    _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_TXPBURST_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_TXPBURST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_TXPBURST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Programmable RX Burst Length.  (Read/Write) This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory.
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_RXPBURST_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_RXPBURST_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_RXPBURST_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_RXPBURST_RANGE                      7:0
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_RXPBURST_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_RXPBURST_DEFAULT                    _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_RXPBURST_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_RXPBURST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_BURSTSIZE_0_RXPBURST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0  
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0                  _MK_ADDR_CONST(0x164)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_SECURE                   0x0
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_WORD_COUNT                       0x1
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_RESET_VAL                        _MK_MASK_CONST(0x20000)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_RESET_MASK                       _MK_MASK_CONST(0x3f1fff)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_READ_MASK                        _MK_MASK_CONST(0x3f1fff)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_WRITE_MASK                       _MK_MASK_CONST(0x3f1fff)
+// FIFO Burst Threshold.  (Read/Write) This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus.  The minimum value is 2 and this value should be a low as possible to maximize USB performance.  A higher value can be used in systems with unpredicable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory.  This value is ignored if the Stream Disable bit in USBMODE register is set.
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXFIFOTHRES_FIELD                        (_MK_MASK_CONST(0x3f) << USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXFIFOTHRES_RANGE                        21:16
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXFIFOTHRES_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXFIFOTHRES_DEFAULT                      _MK_MASK_CONST(0x2)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXFIFOTHRES_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Scheduler Health Counter.  (Read/Write To Clear)  [Default = 0] This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame.
+// This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH.  Writing to this register will clear the counter and this counter will max. at 31.
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHHEALTH_FIELD                        (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHHEALTH_RANGE                        12:8
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHHEALTH_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHHEALTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHHEALTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Scheduler Overhead.  (Read/Write)  [Default = 0] This register adds an additional fixed offset to the schedule time estimator described above as Tff.  As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus.  Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization.
+// The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode.
+// The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHOH_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHOH_FIELD                    (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHOH_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHOH_RANGE                    7:0
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHOH_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHOH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHOH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHOH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0_TXSCHOH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 360 [0x168] 
+
+// Register USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0  
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0                    _MK_ADDR_CONST(0x16c)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_READ_MASK                  _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf)
+// ICUSB transceiver enable. 
+// This bit enables the ICUSB transceiver . 
+// To enable the interface, the bits PTS must be set to 11 in the PORTSCx.
+// Writing a '1' to this bit selects the IC_USB interface.
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_ENB1_SHIFT                      _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_ENB1_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_ENB1_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_ENB1_RANGE                      3:3
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_ENB1_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_ENB1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_ENB1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_ENB1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_ENB1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_ENB1_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_ENB1_ENABLE                     _MK_ENUM_CONST(1)
+
+// ICUSB voltage select.
+// It selects which voltage is being supplied to the ICUSB peripheral.
+// 000 -> No voltage
+// 001 -> 1.0V - reserved
+// 010 -> 1.2V - reserved
+// 011 -> 1.5V - reserved
+// 100 -> 1.8V
+// 101 -> 3.0V
+// 110 -> reserved
+// 111 -> reserved
+// The Voltage negotiation should happen between enabling port power (PP) and
+// asserting the run/stop bit in register.
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_VDD1_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_VDD1_FIELD                      (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_VDD1_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_VDD1_RANGE                      2:0
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_VDD1_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_VDD1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_VDD1_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_VDD1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0_IC_VDD1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0  
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0                 _MK_ADDR_CONST(0x170)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_SECURE                  0x0
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_RESET_MASK                      _MK_MASK_CONST(0xefffffff)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_READ_MASK                       _MK_MASK_CONST(0xefffffff)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_WRITE_MASK                      _MK_MASK_CONST(0xe7ff00ff)
+// ULPI Wakeup. Writing the 1 to this bit will begin the wakeup operation. 
+// The bit will automatically transition to 0 after the wakeup is complete. 
+// Once this bit is set, the driver can not set it back to 0. 
+// Note: The driver must never execute a wakeup and a read/write operation at the same time.
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_SHIFT                       _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_RANGE                       31:31
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_SET                 _MK_ENUM_CONST(1)
+
+// ULPI read/write Run. Writing the 1 to this bit will begin the read/write operation. 
+// The bit will automatically transition to 0 after the read/write is complete. 
+// Once this bit is set, the driver can not set it back to 0. 
+// Note: The driver must never execute a wakeup and a read/write operation at the same time.
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_RANGE                  30:30
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_SET                    _MK_ENUM_CONST(1)
+
+// ULPI read/write control. (0)  Read; (1)  Write. This bit selects between running a read or write operation.
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_SHIFT                        _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_RANGE                        29:29
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_READ                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_WRITE                        _MK_ENUM_CONST(1)
+
+// ULPI sync state. (1)  Normal Sync. State. (0) In another state (i.e. carkit, serial, low power)
+// This bit represents the state of the ULPI interface. 
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_SHIFT                   _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_RANGE                   27:27
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_NOT_NORMAL                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_NORMAL                  _MK_ENUM_CONST(1)
+
+// ULPI PHY port no. This field should be always written as 0.
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_SHIFT                 _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_FIELD                 (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_RANGE                 26:24
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// ULPI PHY register address. When doing a read or write operation to the ULPI PHY, 
+// the address of the ULPI PHY register being accessed is written to this field.
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_RANGE                     23:16
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// ULPI PHY data read. The data from the ULPI PHY register can be read from here after the read operation completes.
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_RANGE                      15:8
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// ULPI PHY data write. The data to write to the ULPI PHY register is written here.
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_RANGE                      7:0
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 372 [0x174] 
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTNAK_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0                      _MK_ADDR_CONST(0x178)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_SECURE                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// TX Endpoint NAK  R/WC. Each TX endpoint has 1 bit in this field.
+// The bit is set when the device sends a NAK handshake on a received
+// IN token for the corresponding endpoint.
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPTN_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPTN_FIELD                   (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPTN_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPTN_RANGE                   31:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPTN_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPTN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPTN_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPTN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPTN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPTN_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPTN_SET                     _MK_ENUM_CONST(1)
+
+// RX Endpoint NAK  R/WC. Each RX endpoint has 1 bit in this field.
+// The bit is set when the device sends a NAK handshake on a received
+// OUT or PING token for the corresponding endpoint.
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPRN_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPRN_FIELD                   (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPRN_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPRN_RANGE                   15:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPRN_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPRN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPRN_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPRN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPRN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPRN_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_0_EPRN_SET                     _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0                       _MK_ADDR_CONST(0x17c)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_SECURE                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// TX Endpoint NAK Enable  R/W. Each bit is an enable bit for
+// the corresponding TX Endpoint NAK bit. If this bit is set
+// and the corresponding TX Endpoint NAK bit is set, 
+// the NAK Interrupt bit is set.
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPTNE_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPTNE_FIELD                   (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPTNE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPTNE_RANGE                   31:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPTNE_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPTNE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPTNE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPTNE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPTNE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPTNE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPTNE_ENABLE                  _MK_ENUM_CONST(1)
+
+// RX Endpoint NAK Enable  R/W. Each bit is an enable bit for
+// the corresponding RX Endpoint NAK bit. If this bit is set and
+// the corresponding RX Endpoint NAK bit is set, 
+// the NAK Interrupt bit is set.
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPRNE_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPRNE_FIELD                   (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPRNE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPRNE_RANGE                   15:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPRNE_WOFFSET                 0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPRNE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPRNE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPRNE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPRNE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPRNE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0_EPRNE_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 384 [0x180] 
+
+// Register USB2_CONTROLLER_1_USB2D_PORTSC1_0  
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0                       _MK_ADDR_CONST(0x184)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SECURE                        0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_RESET_VAL                     _MK_MASK_CONST(0x1004)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WRITE_MASK                    _MK_MASK_CONST(0xe3ff114e)
+// Parallel transceiver select. This bit is not defined in the EHCI specification. 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_SHIFT                     _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_RANGE                     31:30
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_UTMI                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_RESERVED                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_ULPI                      _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTS_ICUSB_SER                 _MK_ENUM_CONST(3)
+
+// 0 = Serial transceiver not selected. This is the  only value supported. This bit is not defined in the EHCI specification. 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_STS_SHIFT                     _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_STS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_STS_RANGE                     29:29
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_STS_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_STS_PARALLEL_IF                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_STS_SERIAL_IF                 _MK_ENUM_CONST(1)
+
+// Parallel Transceiver Width. Fixed to 0. This bit is not defined in the EHCI specification.  
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTW_SHIFT                     _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTW_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTW_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTW_RANGE                     28:28
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTW_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTW_EIGHT_BIT                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTW_RESERVED                  _MK_ENUM_CONST(1)
+
+// This register field indicates the speed at which the port is operating. 
+// 00 = Full Speed
+// 01 = Low Speed
+// 10 = High Speed 
+// This bit is not defined in the EHCI specification.  
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_SHIFT                    _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_RANGE                    27:26
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_FULL_SPEED                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_LOW_SPEED                        _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_HIGH_SPEED                       _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PSPD_RESERVED                 _MK_ENUM_CONST(3)
+
+// Shorten USB Reset Time. Software should never set this to 1.
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SRT_SHIFT                     _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SRT_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_SRT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SRT_RANGE                     25:25
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SRT_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SRT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SRT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SRT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SRT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Port Force Full Speed Connect: Writing this bit to a 1b forces the port to connect at Full Speed only. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. This bit is not defined in the EHCI specification.
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PFSC_SHIFT                    _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PFSC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PFSC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PFSC_RANGE                    24:24
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PFSC_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PFSC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PFSC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PFSC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PFSC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PFSC_DONT_FORCE_FULL_SPEED                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PFSC_FORCE_FULL_SPEED                 _MK_ENUM_CONST(1)
+
+// PHY Low Power Suspend - Clock disable: Writing this bit to a 1 will disable the PHY clock. Write a 0 enables it. Reading this bit will indicate the status of the PHY clock.
+// In device mode, the PHY can be put into Low Power Suspend - Clock disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.
+// In host mode, the PHY can be put into Low Power Suspend - Clock disable when the downstream device has been put into suspend mode or when no downstream device is connected.
+// This bit is not defined in the EHCI specification.
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PHCD_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PHCD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PHCD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PHCD_RANGE                    23:23
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PHCD_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PHCD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PHCD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PHCD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PHCD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PHCD_DISBLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PHCD_ENABLE                   _MK_ENUM_CONST(1)
+
+// Default = 0b. Wake on Over-current Enable: Writing this bit to a one enables  the port to be sensitive to over-current conditions as wake-up events. This  field is zero if Port Power(PP) is zero. This bit should only be used when  operating in Host mode. Writing this bit to 1 while the controller is working  in device mode can result in undefined behavior.
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKOC_SHIFT                    _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKOC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKOC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKOC_RANGE                    22:22
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKOC_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKOC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKOC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKOC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKOC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKOC_DISBLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKOC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Wake on Disconnect Enable: Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power(PP) is zero or in device mode. 
+// This bit should only be used when operating in Host mode. Writing this bit to 1 while the controller is working in device mode can result in undefined behaviour. 
+// This bit should not be written to 1 if there is no  device connected. After the device disconnect is detected, this bit should be  cleared to 0.
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKDS_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKDS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKDS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKDS_RANGE                    21:21
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKDS_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKDS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKDS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKDS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKDS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKDS_DISBLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKDS_ENABLE                   _MK_ENUM_CONST(1)
+
+// Wake on Connect Enable: Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PP) is zero or in device mode. 
+// This bit should only be used when operating in Host mode. Writing this bit to 1 while the controller is working in device mode can result in undefined behaviour. 
+// This bit should not be written to 1 while the  device is connected. After the device connection is detected, this bit should  be cleared to 0.
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKCN_SHIFT                    _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKCN_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKCN_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKCN_RANGE                    20:20
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKCN_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKCN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKCN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKCN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKCN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKCN_DISBLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_WKCN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Port Test Control: Any other value than zero indicates that the port is operating in test mode. 
+//   Value                  Specific Test 
+//  0000b                Not enabled 
+//  0001b                  J_ STATE 
+//  0010b             K_STATE 
+//  0011b              SEQ_NAK 
+//  0100b              Packet 
+//  0101b               FORCE_ENABLE 
+//  0110b to 1111b         Reserved 
+// Refer to Chapter 7 of the USB Specification  Revision 2.0 for details on each test mode. 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_FIELD                     (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_RANGE                     19:16
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_NORMAL_OP                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_TEST_J                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_TEST_K                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_TEST_SE0_NAK                      _MK_ENUM_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_TEST_PKT                  _MK_ENUM_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PTC_TEST_FORCE_ENABLE                 _MK_ENUM_CONST(5)
+
+// Port Indicator Control: This field is not supported in the current  implementation. Please use a GPIO if you wish to use Port Indicators.
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PIC_SHIFT                     _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PIC_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PIC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PIC_RANGE                     15:14
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PIC_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PIC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PIC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PIC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PIC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Port Owner. Port owner handoff is not implemented in this design, therefore this bit will  always be 0. 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PO_SHIFT                      _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PO_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PO_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PO_RANGE                      13:13
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PO_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Port Power: The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: 
+// PPC                       PP  Operation 
+// 0b                           0b Read Only. A device controller with no OTG capability does not have port power control switches. 
+// 1b                          1b/0b RW.  Host/OTG controller requires port power control switches. 
+// This bit represents the current setting of the switch (0=off, 1=on).  When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. 
+// When an over-current condition is detected on a  powered port and PPC is a one, the PP bit in each affected port may be  transitioned by the host controller driver from a one to a zero (removing  power from the port). 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PP_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PP_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PP_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PP_RANGE                      12:12
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PP_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PP_NOT_POWERED                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PP_POWERED                    _MK_ENUM_CONST(1)
+
+// Line state. These bits reflect the current logical levels of the D+ (bit 10) and D- (bit 11) signal lines. The encoding of the bits are:
+// 00b = SE0 
+// 01b = J-state 
+// 10b = K-state 
+// 11b = Undefined 
+// The value of this field is undefined if Port  Power(PP) is zero in host mode. In host mode, the use  of line-state by the host controller driver is not necessary (unlike EHCI),  because the port controller state machine and the port routing manage the  connection of LS and FS. In device mode, the use of line-state by the device  controller driver is not necessary. 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_SHIFT                      _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_FIELD                      (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_RANGE                      11:10
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_SE0                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_J_STATE                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_K_STATE                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_LS_UNDEFINED                  _MK_ENUM_CONST(3)
+
+// When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the host/device connected to the port is not in a high-speed mode. 
+// Note: HSP is redundant with PSPD(27:26). 
+// This bit is not defined in the EHCI specification.
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_HSP_SHIFT                     _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_HSP_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_HSP_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_HSP_RANGE                     9:9
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_HSP_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_HSP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_HSP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_HSP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_HSP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_HSP_NOT_HIGH_SPEED                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_HSP_HIGH_SPEED                        _MK_ENUM_CONST(1)
+
+// This field is zero if Port Power(PP) is zero. 
+// In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset.
+// When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver.  
+// In Device Mode: This bit is a read only status  bit. Device reset from the USB bus is also indicated in the USBSTS register. 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PR_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PR_RANGE                      8:8
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PR_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PR_NOT_USB_RESET                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PR_USB_RESET                  _MK_ENUM_CONST(1)
+
+// Port suspend. 1=Port in suspend state. 0=Port not in suspend state. 
+// In Host Mode: Read/Write. 
+// Port Enabled Bit and Suspend bit of this register define the port states as follows: 
+// Bits [Port Enabled, Suspend]    Port State 
+//        0x                        Disable 
+//   10                        Enable 
+//    11                        Suspend 
+// When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. A write of zero to this bit is ignored by the host controller. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This field is zero if Port Power(PP) is zero in host mode.
+// In Device Mode: Read Only. This bit is a read only status bit. 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SUSP_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SUSP_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_SUSP_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SUSP_RANGE                    7:7
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SUSP_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SUSP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SUSP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SUSP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SUSP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SUSP_NOT_SUSPEND                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_SUSP_SUSPEND                  _MK_ENUM_CONST(1)
+
+// Force Port Resume. 1= Resume detected/driven on port. 0=No resume (K state) detected/driven on port. 
+// In Host Mode: 
+// Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one.  This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. 
+// Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one.  This bit remains a one until the port has switched to the high-speed idle.  Writing a zero has no effect because the port controller will time the resume operation to clear the bit when the port control state switches to HS or FS idle. This field is zero if Port Power(PP) is zero in host mode. This bit is not-EHCI compatible. 
+// In Device mode:  
+// After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. 
+// Software should ensure that the PHY clock is operational before writing a 1 to this bit to start the resume sequence. This is true for both Device and Host modes.
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_FPR_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_FPR_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_FPR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_FPR_RANGE                     6:6
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_FPR_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_FPR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_FPR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_FPR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_FPR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_FPR_NO_RESUME                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_FPR_RESUME                    _MK_ENUM_CONST(1)
+
+// Over-current Change: Not supported
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCC_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCC_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCC_RANGE                     5:5
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCC_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCC_NO_CHANGE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCC_CHANGE                    _MK_ENUM_CONST(1)
+
+// Over-current Active: Not supported
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCA_SHIFT                     _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCA_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCA_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCA_RANGE                     4:4
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCA_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCA_NO_OVER_CURRENT                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_OCA_OVER_CURRENT                      _MK_ENUM_CONST(1)
+
+// Port Enable/Disable Change: 1=Port enabled/disabled status has changed. 0=No change.
+// In Host Mode: 
+// For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This field is zero if Port Power(PP) is zero. 
+// In Device mode:  
+// The device port is always enabled. (This bit will  be zero) 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PEC_SHIFT                     _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PEC_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PEC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PEC_RANGE                     3:3
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PEC_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PEC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PEC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PEC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PEC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PEC_NO_CHANGE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PEC_CHANGE                    _MK_ENUM_CONST(1)
+
+// Port Enabled/Disabled: 1=Enable. 0=Disable (default)
+// In Host Mode: 
+// Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events.  When the port is disabled, (0b) downstream propagation of data is blocked except for reset. This field is zero if Port Power(PP) is zero in host mode. 
+// In Device Mode: 
+// The device port is always enabled. (This bit will  be one) 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PE_SHIFT                      _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_PE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PE_RANGE                      2:2
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PE_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PE_PORT_DISABLED                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_PE_PORT_ENABLED                       _MK_ENUM_CONST(1)
+
+// Connect Status Change: 1 =Change in Current Connect Status. 0=No change (default) 
+// In Host Mode: 
+// Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (i.e., the bit will remain set).  Software clears this bit by writing a one to it. This field is zero if Port Power(PP) is zero in host mode. 
+// This bit is undefined in device controller mode. 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CSC_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CSC_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_CSC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CSC_RANGE                     1:1
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CSC_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CSC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CSC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CSC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CSC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CSC_NO_CHANGE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CSC_CHANGE                    _MK_ENUM_CONST(1)
+
+// Current Connect Status: 
+// In Host Mode: 1=Device is present on port.                0=No device is present (default) 
+// This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power(PP) is zero in host mode. 
+// In Device Mode: 1=Attached                    0=Not Attached (default) 
+// A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. 
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CCS_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CCS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_PORTSC1_0_CCS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CCS_RANGE                     0:0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CCS_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CCS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CCS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CCS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CCS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CCS_NOT_CONNECTED                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_PORTSC1_0_CCS_CONNECTED                 _MK_ENUM_CONST(1)
+
+
+// Reserved address 416 [0x1a0] 
+
+// Register USB2_CONTROLLER_1_USB2D_OTGSC_0  
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0                 _MK_ADDR_CONST(0x1a4)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_SECURE                  0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_RESET_MASK                      _MK_MASK_CONST(0x7f7f7f3b)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_READ_MASK                       _MK_MASK_CONST(0x7f7f7f3b)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_WRITE_MASK                      _MK_MASK_CONST(0x7f7f003b)
+// Data Pulse Interrupt Enable. Setting this bit enables the Data pulse interrupt.
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIE_SHIFT                      _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIE_RANGE                      30:30
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIE_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIE_ENABLE                     _MK_ENUM_CONST(1)
+
+// 1 millisecond timer Interrupt enable. Setting this bit enables the 1 millisecond timer  interrupt.
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSE_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSE_RANGE                    29:29
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSE_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSE_ENABLE                   _MK_ENUM_CONST(1)
+
+// B Session End Interrupt Enable. Setting this bit enables the B session end  interrupt
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIE_SHIFT                     _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIE_RANGE                     28:28
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// B Session Valid Interrupt Enable. Setting this bit enables the B session valid  interrupt
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIE_SHIFT                     _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIE_RANGE                     27:27
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// A Session Valid Interrupt Enable. Setting this bit enables the A session valid  interrupt
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIE_SHIFT                     _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIE_RANGE                     26:26
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// A VBus Valid Interrupt Enable. Setting this bit enables the A VBus valid  interrupt
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIE_SHIFT                     _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIE_RANGE                     25:25
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIE_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// USB ID Interrupt Enable. Setting this bit enables the USB ID interrupt
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIE_SHIFT                      _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIE_RANGE                      24:24
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIE_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Data Pulse Interrupt Status. This bit is set when data bus pulsing occurs on DP or DM.  Data bus pulsing is only detected when USBMODE.CM = Host (11) and PORTSC(0).PortPower = Off (0). Software writes a 1 to clear this bit.
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIS_SHIFT                      _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIS_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIS_RANGE                      22:22
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIS_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIS_INT_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPIS_INT_SET                    _MK_ENUM_CONST(1)
+
+// 1 millisecond timer Interrupt Status: This bit is set once every millisecond. Software  writes a 1 to clear it.
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSS_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSS_RANGE                    21:21
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSS_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSS_INT_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMSS_INT_SET                  _MK_ENUM_CONST(1)
+
+// B Session End Interrupt Status. This bit is set when VBus has fallen below the B  session end threshold. Software writes a 1 to clear this bit .
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIS_SHIFT                     _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIS_RANGE                     20:20
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIS_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIS_INT_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSEIS_INT_SET                   _MK_ENUM_CONST(1)
+
+// B Session Valid Interrupt Status. This bit is set when VBus has either risen above  or fallen below the B session valid threshold (0.8 VDC). Software writes a 1  to clear this bit. 
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIS_SHIFT                     _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIS_RANGE                     19:19
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIS_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIS_INT_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSVIS_INT_SET                   _MK_ENUM_CONST(1)
+
+// A Session Valid Interrupt Status. This bit is set when VBus has either risen above  or fallen below the A session valid threshold (0.8 VDC). Software writes a  one to clear this bit. 
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIS_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIS_RANGE                     18:18
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIS_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIS_INT_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASVIS_INT_SET                   _MK_ENUM_CONST(1)
+
+// A VBus Valid Interrupt Status. This bit is set when VBus has either risen above  or fallen below the VBus valid threshold (4.4 VDC) on an A device. Software  writes a 1 to clear this bit. 
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIS_SHIFT                     _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIS_RANGE                     17:17
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIS_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIS_INT_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVVIS_INT_SET                   _MK_ENUM_CONST(1)
+
+// USB ID Interrupt Status. This bit is set when a change on the ID input has been detected. Software writes a 1 to clear this bit. 
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIS_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIS_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIS_RANGE                      16:16
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIS_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIS_INT_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDIS_INT_SET                    _MK_ENUM_CONST(1)
+
+// Data Bus Pulsing Status. A 1 indicates data bus pulsing is being detected  on the port. 
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPS_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_DPS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPS_RANGE                       14:14
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPS_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPS_STS_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DPS_STS_SET                     _MK_ENUM_CONST(1)
+
+// 1 millisecond timer toggle. This bit toggles once per millisecond
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMST_SHIFT                    _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMST_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMST_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMST_RANGE                    13:13
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMST_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMST_STS_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ONEMST_STS_SET                  _MK_ENUM_CONST(1)
+
+// B session End. Indicates VBus is below the B session end  threshold
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSE_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_BSE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSE_RANGE                       12:12
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSE_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSE_STS_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSE_STS_SET                     _MK_ENUM_CONST(1)
+
+// B Session Valid. Indicates VBus is above the B session valid  threshold
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSV_SHIFT                       _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSV_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_BSV_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSV_RANGE                       11:11
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSV_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSV_STS_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_BSV_STS_SET                     _MK_ENUM_CONST(1)
+
+// A Session Valid. Indicates VBus is above the A session valid  threshold
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASV_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASV_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_ASV_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASV_RANGE                       10:10
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASV_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASV_STS_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ASV_STS_SET                     _MK_ENUM_CONST(1)
+
+// A VBus Valid. Indicates VBus is above the A VBus valid threshold
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVV_SHIFT                       _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVV_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_AVV_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVV_RANGE                       9:9
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVV_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVV_STS_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_AVV_STS_SET                     _MK_ENUM_CONST(1)
+
+// USB ID: 0 = A-device  1 = B-device
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ID_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ID_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_ID_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ID_RANGE                        8:8
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ID_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ID_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ID_A_DEV                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_ID_B_DEV                        _MK_ENUM_CONST(1)
+
+// USB ID Pullup
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDPU_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDPU_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_IDPU_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDPU_RANGE                      5:5
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDPU_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDPU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDPU_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_IDPU_SET                        _MK_ENUM_CONST(1)
+
+// Data Pulsing. Setting this bit causes the pull-up on DP to be  asserted for data pulsing during SRP. 
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DP_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DP_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_DP_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DP_RANGE                        4:4
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DP_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DP_NO_DATA_PULSE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_DP_DATA_PULSE                   _MK_ENUM_CONST(1)
+
+// OTG Termination. This bit must be set when the OTG device is in device mode, this controls the pulldown on DM. 
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_OT_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_OT_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_OT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_OT_RANGE                        3:3
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_OT_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_OT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_OT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_OT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_OT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_OT_NO_OTG_TERM                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_OT_OTG_TERM                     _MK_ENUM_CONST(1)
+
+// VBUS Charge. Setting this bit causes the VBus line to be  charged. This is used for VBus pulsing during SRP. 
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VC_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VC_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_VC_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VC_RANGE                        1:1
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VC_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VC_NO_VBUS_CHRG                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VC_VBUS_CHRG                    _MK_ENUM_CONST(1)
+
+// VBUS_Discharge. Read/write. Setting this bit  causes Vbus to discharge through a resistor. 
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VD_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VD_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_OTGSC_0_VD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VD_RANGE                        0:0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VD_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VD_NO_VBUS_DISCHRG                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_OTGSC_0_VD_VBUS_DISCHRG                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_USBMODE_0  
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0                       _MK_ADDR_CONST(0x1a8)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SECURE                        0x0
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Stream disbable: 1 Streaming is disabled - helpful to avoid overrun/underruns when system load is too high.
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SDIS_SHIFT                    _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SDIS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBMODE_0_SDIS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SDIS_RANGE                    4:4
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SDIS_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SDIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SDIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SDIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SDIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SDIS_STREAM_ENABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SDIS_STREAM_DISABLE                   _MK_ENUM_CONST(1)
+
+// Setup Lockout Mode:
+// In device mode, this bit controls the behavior of the setup lockout mechanism.
+// 0 - Setup lockout is ON (default)
+// 1  Setup lockout is OFF. Firmware requires the  use of setup tripwire semaphore in USB2D_USBCMD register.
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SLOM_SHIFT                    _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SLOM_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBMODE_0_SLOM_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SLOM_RANGE                    3:3
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SLOM_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SLOM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SLOM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SLOM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SLOM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SLOM_LOCKOUT_OFF                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_SLOM_LOCKOUT_ON                       _MK_ENUM_CONST(1)
+
+// Endian Select: Note: For this implementation, this should be  always set to 0 (little endian).
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_ES_SHIFT                      _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_ES_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_USBMODE_0_ES_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_ES_RANGE                      2:2
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_ES_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_ES_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_ES_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_ES_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_ES_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_ES_LITTLE_ENDIAN                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_ES_RESERVED                   _MK_ENUM_CONST(1)
+
+// Controller Mode: The controller mode will default to an idle state and will need to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. 
+// 00 = Idle [Default] 
+// 01 = Reserved 
+// 10 = Device Controller  
+// 11 = Host Controller 
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_FIELD                      (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_RANGE                      1:0
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_IDLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_RESERVED                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_DEVICE_MODE                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_USBMODE_0_CM_HOST_MODE                  _MK_ENUM_CONST(3)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0                        _MK_ADDR_CONST(0x1ac)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_SECURE                         0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_WORD_COUNT                     0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+// Endpoint 15 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SHIFT                 _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_RANGE                 15:15
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 14 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SHIFT                 _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_RANGE                 14:14
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 13 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SHIFT                 _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_RANGE                 13:13
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 12 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SHIFT                 _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_RANGE                 12:12
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 11 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SHIFT                 _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_RANGE                 11:11
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 10 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SHIFT                 _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_RANGE                 10:10
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 9 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SHIFT                  _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_RANGE                  9:9
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 8 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_RANGE                  8:8
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 7 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_RANGE                  7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 6 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_RANGE                  6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 5 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_RANGE                  5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 4 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SHIFT                  _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_RANGE                  4:4
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 3 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_RANGE                  3:3
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 2 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_RANGE                  2:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 1 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_RANGE                  1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 0 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_RANGE                  0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0                    _MK_ADDR_CONST(0x1b0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB15_SHIFT                       _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB15_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB15_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB15_RANGE                       31:31
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB15_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB15_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB15_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB14_SHIFT                       _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB14_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB14_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB14_RANGE                       30:30
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB14_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB14_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB14_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB13_SHIFT                       _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB13_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB13_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB13_RANGE                       29:29
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB13_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB13_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB13_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB12_SHIFT                       _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB12_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB12_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB12_RANGE                       28:28
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB12_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB12_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB12_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB11_SHIFT                       _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB11_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB11_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB11_RANGE                       27:27
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB11_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB11_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB11_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB10_SHIFT                       _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB10_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB10_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB10_RANGE                       26:26
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB10_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB10_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB10_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB9_SHIFT                        _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB9_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB9_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB9_RANGE                        25:25
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB9_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB9_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB9_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB8_SHIFT                        _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB8_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB8_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB8_RANGE                        24:24
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB8_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB8_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB8_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB7_SHIFT                        _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB7_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB7_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB7_RANGE                        23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB7_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB7_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB7_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB6_SHIFT                        _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB6_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB6_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB6_RANGE                        22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB6_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB6_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB6_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB5_SHIFT                        _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB5_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB5_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB5_RANGE                        21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB5_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB5_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB5_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB4_SHIFT                        _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB4_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB4_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB4_RANGE                        20:20
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB4_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB4_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB4_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB3_SHIFT                        _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB3_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB3_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB3_RANGE                        19:19
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB3_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB3_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB3_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB2_SHIFT                        _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB2_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB2_RANGE                        18:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB2_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB2_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB2_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB1_SHIFT                        _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB1_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB1_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB1_RANGE                        17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB1_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB1_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB1_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB0_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB0_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB0_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB0_RANGE                        16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB0_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB0_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PETB0_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB15_SHIFT                       _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB15_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB15_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB15_RANGE                       15:15
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB15_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB15_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB15_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB14_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB14_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB14_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB14_RANGE                       14:14
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB14_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB14_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB14_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB13_SHIFT                       _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB13_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB13_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB13_RANGE                       13:13
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB13_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB13_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB13_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB12_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB12_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB12_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB12_RANGE                       12:12
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB12_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB12_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB12_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB11_SHIFT                       _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB11_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB11_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB11_RANGE                       11:11
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB11_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB11_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB11_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB10_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB10_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB10_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB10_RANGE                       10:10
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB10_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB10_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB10_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB9_SHIFT                        _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB9_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB9_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB9_RANGE                        9:9
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB9_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB9_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB9_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB8_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB8_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB8_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB8_RANGE                        8:8
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB8_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB8_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB8_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB7_SHIFT                        _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB7_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB7_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB7_RANGE                        7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB7_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB7_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB7_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB6_SHIFT                        _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB6_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB6_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB6_RANGE                        6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB6_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB6_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB6_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB5_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB5_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB5_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB5_RANGE                        5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB5_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB5_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB5_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB4_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB4_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB4_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB4_RANGE                        4:4
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB4_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB4_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB4_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB3_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB3_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB3_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB3_RANGE                        3:3
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB3_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB3_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB3_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB2_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB2_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB2_RANGE                        2:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB2_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB2_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB2_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB1_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB1_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB1_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB1_RANGE                        1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB1_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB1_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB1_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB0_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB0_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB0_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB0_RANGE                        0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB0_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB0_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0_PERB0_PRIME                        _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0                    _MK_ADDR_CONST(0x1b4)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB15_SHIFT                       _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB15_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB15_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB15_RANGE                       31:31
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB15_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB15_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB15_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB14_SHIFT                       _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB14_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB14_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB14_RANGE                       30:30
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB14_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB14_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB14_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB13_SHIFT                       _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB13_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB13_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB13_RANGE                       29:29
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB13_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB13_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB13_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB12_SHIFT                       _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB12_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB12_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB12_RANGE                       28:28
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB12_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB12_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB12_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB11_SHIFT                       _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB11_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB11_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB11_RANGE                       27:27
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB11_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB11_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB11_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB10_SHIFT                       _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB10_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB10_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB10_RANGE                       26:26
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB10_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB10_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB10_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB9_SHIFT                        _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB9_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB9_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB9_RANGE                        25:25
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB9_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB9_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB9_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB8_SHIFT                        _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB8_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB8_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB8_RANGE                        24:24
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB8_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB8_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB8_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB7_SHIFT                        _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB7_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB7_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB7_RANGE                        23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB7_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB7_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB7_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB6_SHIFT                        _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB6_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB6_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB6_RANGE                        22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB6_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB6_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB6_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB5_SHIFT                        _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB5_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB5_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB5_RANGE                        21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB5_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB5_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB5_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB4_SHIFT                        _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB4_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB4_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB4_RANGE                        20:20
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB4_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB4_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB4_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB3_SHIFT                        _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB3_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB3_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB3_RANGE                        19:19
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB3_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB3_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB3_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB2_SHIFT                        _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB2_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB2_RANGE                        18:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB2_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB2_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB2_FLUSH                        _MK_ENUM_CONST(1)
+
+// 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB1_SHIFT                        _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB1_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB1_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB1_RANGE                        17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB1_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB1_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB1_FLUSH                        _MK_ENUM_CONST(1)
+
+//
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB0_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB0_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB0_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB0_RANGE                        16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB0_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB0_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FETB0_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB15_SHIFT                       _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB15_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB15_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB15_RANGE                       15:15
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB15_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB15_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB15_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB14_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB14_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB14_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB14_RANGE                       14:14
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB14_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB14_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB14_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB13_SHIFT                       _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB13_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB13_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB13_RANGE                       13:13
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB13_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB13_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB13_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB12_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB12_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB12_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB12_RANGE                       12:12
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB12_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB12_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB12_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB11_SHIFT                       _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB11_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB11_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB11_RANGE                       11:11
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB11_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB11_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB11_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB10_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB10_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB10_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB10_RANGE                       10:10
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB10_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB10_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB10_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB9_SHIFT                        _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB9_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB9_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB9_RANGE                        9:9
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB9_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB9_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB9_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB8_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB8_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB8_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB8_RANGE                        8:8
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB8_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB8_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB8_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB7_SHIFT                        _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB7_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB7_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB7_RANGE                        7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB7_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB7_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB7_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB6_SHIFT                        _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB6_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB6_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB6_RANGE                        6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB6_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB6_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB6_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB5_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB5_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB5_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB5_RANGE                        5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB5_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB5_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB5_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB4_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB4_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB4_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB4_RANGE                        4:4
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB4_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB4_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB4_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB3_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB3_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB3_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB3_RANGE                        3:3
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB3_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB3_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB3_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB2_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB2_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB2_RANGE                        2:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB2_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB2_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB2_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB1_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB1_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB1_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB1_RANGE                        1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB1_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB1_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB1_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB0_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB0_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB0_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB0_RANGE                        0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB0_WOFFSET                      0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB0_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0_FERB0_FLUSH                        _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0                   _MK_ADDR_CONST(0x1b8)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_SECURE                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR15_SHIFT                      _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR15_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR15_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR15_RANGE                      31:31
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR15_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR15_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR15_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR15_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR15_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR15_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR15_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR14_SHIFT                      _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR14_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR14_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR14_RANGE                      30:30
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR14_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR14_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR14_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR14_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR14_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR13_SHIFT                      _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR13_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR13_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR13_RANGE                      29:29
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR13_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR13_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR13_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR13_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR13_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR12_SHIFT                      _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR12_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR12_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR12_RANGE                      28:28
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR12_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR12_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR12_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR12_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR12_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR11_SHIFT                      _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR11_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR11_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR11_RANGE                      27:27
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR11_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR11_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR11_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR11_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR11_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR10_SHIFT                      _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR10_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR10_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR10_RANGE                      26:26
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR10_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR10_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR10_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR10_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR10_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR9_SHIFT                       _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR9_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR9_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR9_RANGE                       25:25
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR9_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR9_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR9_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR9_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR9_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR8_SHIFT                       _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR8_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR8_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR8_RANGE                       24:24
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR8_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR8_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR8_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR8_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR8_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR7_SHIFT                       _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR7_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR7_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR7_RANGE                       23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR7_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR7_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR7_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR6_SHIFT                       _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR6_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR6_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR6_RANGE                       22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR6_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR6_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR6_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR5_SHIFT                       _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR5_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR5_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR5_RANGE                       21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR5_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR5_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR5_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR4_SHIFT                       _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR4_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR4_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR4_RANGE                       20:20
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR4_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR4_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR4_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR3_SHIFT                       _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR3_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR3_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR3_RANGE                       19:19
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR3_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR3_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR3_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR2_SHIFT                       _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR2_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR2_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR2_RANGE                       18:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR2_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR2_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR2_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR1_SHIFT                       _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR1_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR1_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR1_RANGE                       17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR1_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR1_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR1_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR0_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR0_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR0_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR0_RANGE                       16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR0_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR0_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ETBR0_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR15_SHIFT                      _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR15_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR15_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR15_RANGE                      15:15
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR15_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR15_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR15_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR15_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR15_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR15_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR15_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR14_SHIFT                      _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR14_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR14_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR14_RANGE                      14:14
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR14_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR14_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR14_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR14_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR14_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR13_SHIFT                      _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR13_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR13_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR13_RANGE                      13:13
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR13_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR13_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR13_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR13_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR13_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR12_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR12_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR12_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR12_RANGE                      12:12
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR12_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR12_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR12_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR12_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR12_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR11_SHIFT                      _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR11_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR11_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR11_RANGE                      11:11
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR11_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR11_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR11_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR11_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR11_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR10_SHIFT                      _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR10_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR10_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR10_RANGE                      10:10
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR10_WOFFSET                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR10_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR10_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR10_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR10_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR9_SHIFT                       _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR9_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR9_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR9_RANGE                       9:9
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR9_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR9_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR9_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR9_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR9_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR8_SHIFT                       _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR8_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR8_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR8_RANGE                       8:8
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR8_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR8_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR8_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR8_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR8_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR7_SHIFT                       _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR7_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR7_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR7_RANGE                       7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR7_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR7_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR7_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR6_SHIFT                       _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR6_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR6_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR6_RANGE                       6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR6_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR6_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR6_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR5_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR5_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR5_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR5_RANGE                       5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR5_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR5_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR5_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR4_SHIFT                       _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR4_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR4_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR4_RANGE                       4:4
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR4_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR4_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR4_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR3_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR3_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR3_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR3_RANGE                       3:3
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR3_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR3_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR3_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR2_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR2_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR2_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR2_RANGE                       2:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR2_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR2_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR2_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR1_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR1_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR1_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR1_RANGE                       1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR1_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR1_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR1_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR0_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR0_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR0_RANGE                       0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR0_WOFFSET                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR0_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0_ERBR0_READY                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0                 _MK_ADDR_CONST(0x1bc)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_SECURE                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE15_SHIFT                    _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE15_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE15_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE15_RANGE                    31:31
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE15_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE15_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE15_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE15_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE14_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE14_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE14_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE14_RANGE                    30:30
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE14_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE14_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE14_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE14_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE13_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE13_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE13_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE13_RANGE                    29:29
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE13_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE13_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE13_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE13_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE12_SHIFT                    _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE12_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE12_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE12_RANGE                    28:28
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE12_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE12_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE12_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE12_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE11_SHIFT                    _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE11_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE11_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE11_RANGE                    27:27
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE11_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE11_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE11_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE11_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE10_SHIFT                    _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE10_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE10_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE10_RANGE                    26:26
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE10_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE10_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE10_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE10_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE9_SHIFT                     _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE9_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE9_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE9_RANGE                     25:25
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE9_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE9_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE9_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE9_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE8_SHIFT                     _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE8_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE8_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE8_RANGE                     24:24
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE8_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE8_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE8_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE8_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE7_SHIFT                     _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE7_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE7_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE7_RANGE                     23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE7_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE7_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE7_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE6_SHIFT                     _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE6_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE6_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE6_RANGE                     22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE6_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE6_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE6_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE5_SHIFT                     _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE5_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE5_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE5_RANGE                     21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE5_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE5_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE5_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE4_SHIFT                     _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE4_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE4_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE4_RANGE                     20:20
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE4_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE4_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE4_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE3_SHIFT                     _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE3_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE3_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE3_RANGE                     19:19
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE3_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE3_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE3_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE2_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE2_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE2_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE2_RANGE                     18:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE2_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE2_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE2_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE1_SHIFT                     _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE1_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE1_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE1_RANGE                     17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE1_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE1_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE1_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE0_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE0_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE0_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE0_RANGE                     16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE0_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE0_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ETCE0_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE15_SHIFT                    _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE15_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE15_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE15_RANGE                    15:15
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE15_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE15_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE15_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE15_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE14_SHIFT                    _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE14_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE14_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE14_RANGE                    14:14
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE14_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE14_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE14_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE14_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE13_SHIFT                    _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE13_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE13_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE13_RANGE                    13:13
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE13_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE13_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE13_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE13_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE12_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE12_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE12_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE12_RANGE                    12:12
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE12_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE12_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE12_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE12_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE11_SHIFT                    _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE11_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE11_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE11_RANGE                    11:11
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE11_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE11_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE11_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE11_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE10_SHIFT                    _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE10_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE10_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE10_RANGE                    10:10
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE10_WOFFSET                  0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE10_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE10_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE10_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE9_SHIFT                     _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE9_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE9_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE9_RANGE                     9:9
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE9_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE9_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE9_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE9_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE8_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE8_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE8_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE8_RANGE                     8:8
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE8_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE8_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE8_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE8_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE7_SHIFT                     _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE7_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE7_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE7_RANGE                     7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE7_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE7_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE7_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE6_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE6_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE6_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE6_RANGE                     6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE6_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE6_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE6_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE5_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE5_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE5_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE5_RANGE                     5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE5_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE5_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE5_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE4_SHIFT                     _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE4_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE4_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE4_RANGE                     4:4
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE4_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE4_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE4_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE3_SHIFT                     _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE3_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE3_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE3_RANGE                     3:3
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE3_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE3_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE3_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE2_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE2_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE2_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE2_RANGE                     2:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE2_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE2_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE2_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE1_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE1_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE1_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE1_RANGE                     1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE1_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE1_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE1_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE0_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE0_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE0_RANGE                     0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE0_WOFFSET                   0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE0_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0_ERCE0_COMPLETE                  _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0                    _MK_ADDR_CONST(0x1c0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RESET_VAL                  _MK_MASK_CONST(0x800080)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RESET_MASK                         _MK_MASK_CONST(0x8d008d)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_READ_MASK                  _MK_MASK_CONST(0x8d008d)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// TX Endpoint Enable. Endpoint 0 is always  enabled. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Endpoint Type. Endpoint0 is fixed as a Control Endpoint. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// TX Endpoint Stall: Software can write a one to this bit to force the  endpoint to return a STALL handshake to the Host. It will continue returning  STALL until the bit is cleared by software or it will automatically be  cleared upon receipt of a new SETUP request. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+//  RX Endpoint Enable. Endpoint 0 is always  enabled. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Endpoint Type. Endpoint 0 is fixed as a Control Endpoint. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// RX Endpoint Stall: Software can write a one to this bit to force the  endpoint to return a STALL handshake to the Host. It will continue returning  STALL until the bit is cleared by software or it will automatically be  cleared upon receipt of a new SETUP request. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0                    _MK_ADDR_CONST(0x1c4)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above, 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0                    _MK_ADDR_CONST(0x1c8)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0                    _MK_ADDR_CONST(0x1cc)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0                    _MK_ADDR_CONST(0x1d0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0                    _MK_ADDR_CONST(0x1d4)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0                    _MK_ADDR_CONST(0x1d8)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0                    _MK_ADDR_CONST(0x1dc)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0                    _MK_ADDR_CONST(0x1e0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0                    _MK_ADDR_CONST(0x1e4)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_SECURE                     0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0                   _MK_ADDR_CONST(0x1e8)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_SECURE                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0                   _MK_ADDR_CONST(0x1ec)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_SECURE                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0                   _MK_ADDR_CONST(0x1f0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_SECURE                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0                   _MK_ADDR_CONST(0x1f4)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_SECURE                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0                   _MK_ADDR_CONST(0x1f8)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_SECURE                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0  
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0                   _MK_ADDR_CONST(0x1fc)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_SECURE                    0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXE_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXR_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXI_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXD_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXS_SHIFT)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Packet USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_ROW                      0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_NON_ISO_IS_0                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_MULTI_1                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_MULT_2                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_MULTI_3                  _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_SHIFT                     _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_RANGE                     _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_ROW                       0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_ZERO_LENGTH_TERM_ENABLED                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_ZERO_LENGTH_TERM_DISABLED                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_SHIFT                     _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_RANGE                     _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_ROW                       0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_FIELD                       (_MK_MASK_CONST(0x7ff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_RANGE                       _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_SHIFT                     _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_ROW                       0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_ENABLE                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_FIELD                     (_MK_MASK_CONST(0x7fff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_ROW                       0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_FIELD                 (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_ROW                   1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_FIELD                     (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_ROW                       1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_FIELD                    (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_ROW                      2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_FIELD                     (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_ROW                 2
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_SET                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_FIELD                     (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_SHIFT                     _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_ROW                       3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_ENABLE                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_FIELD                     (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_ROW                       3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_ENABLE                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_RANGE                     _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_ROW                    3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_RANGE                  _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_ROW                    3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_RANGE                       _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_ROW                 3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SET                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_SHIFT                     _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_RANGE                       _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_ROW                 3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_SET                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_FIELD                     (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_RANGE                     _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_ROW                     4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_FIELD                      (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_ROW                        4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_ROW                     5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_ROW                       5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_ROW                     6
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_ROW                       6
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_ROW                     7
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_ROW                       7
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_ROW                     8
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_ROW                       8
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_ROW                       9
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_ROW                        10
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_ROW                        11
+
+
+// Packet USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_FIELD                   (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_ROW                     0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_ROW                      0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_FIELD                    (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT                    _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_ROW                      1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_ENABLE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_FIELD                    (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_RANGE                    _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_ROW                      1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_RANGE                    _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_ROW                   1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_RANGE                 _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_ROW                   1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_ROW                        1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_SHIFT                    _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT                      _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_RANGE                      _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_ROW                        1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_FIELD                    (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                    3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_ROW                    4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_ROW                      4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_ROW                    5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_ROW                      5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_ROW                    6
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_ROW                      6
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_FIELD                    (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_ROW                      0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_RANGE                       _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_ROW                 0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_ITD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_QH                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_SITD                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_FSTN                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_VALID_QH_PTR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_INVALID_QH_PTR                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_SHIFT                        _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_FIELD                        (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_SHIFT                      _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_RANGE                      _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_ROW                        1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_NOT_CTRL_EP                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_CTRP_EP                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_FIELD                    (_MK_MASK_CONST(0x7ff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_RANGE                    _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_SHIFT                     _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_ROW                       1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_SHIFT                  _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_RANGE                  _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_QH_DT                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_QTD_DT                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_RANGE                       _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_ROW                 1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_FULL_SPEED                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_LOW_SPEED                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_HIGH_SPEED                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_RESERVED                    _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_SHIFT                       _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_SHIFT                        _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_RANGE                        _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_ROW                  1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_NO_INACTIVATE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_INACTIVATE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_FIELD                       (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_RANGE                       _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_SHIFT                      _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_FIELD                      (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_ROW                        2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_NON_ISO_IS_0                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_MULTI_1                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_MULT_2                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_MULTI_3                    _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_SHIFT                       _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_FIELD                       (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_ROW                 2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_FIELD                  (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_RANGE                  _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_FIELD                   (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_ROW                     3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_FIELD                       (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_ROW                 3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_FIELD                      (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_ROW                        4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_ROW                 4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_RANGE                     _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_ROW                       4
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_VALID_TD_PTR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_INVALID_TD_PTR                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_FIELD                  (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_ROW                    5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_ROW                 5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_RANGE                 _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_ROW                   5
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_VALID_TD_PTR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_INVALID_TD_PTR                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_SHIFT                       _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_RANGE                       _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_ROW                 6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_DATA0                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_DATA1                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_FIELD                       (_MK_MASK_CONST(0x7fff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_RANGE                       _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_ROW                 6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_SHIFT                       _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_ROW                 6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_ENABLE                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_FIELD                      (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_RANGE                      _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_ROW                        6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_ROW                 6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_RANGE                  _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_ROW                    6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_OUT                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_IN                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_SETUP                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_RESERVED                       _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_RANGE                    _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_ROW                      6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_ROW                      6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_RANGE                 _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_ROW                   6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_SHIFT                   _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_RANGE                   _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_ROW                     6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_SET                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_RANGE                 _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_ROW                   6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_ROW                  6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_SET                  _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_RANGE                 _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_ROW                   6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_DO_START_SPLIT                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_DO_COMPLETE_SPLIT                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_ROW                  6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_DO_OUT                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_DO_PING                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_ROW                       7
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_FIELD                        (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_ROW                  7
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_ROW                       8
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_ROW                 8
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_ROW                       9
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_ROW                 9
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_ROW                       10
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_FIELD                      (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_ROW                        10
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_ROW                       11
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_FIELD                      (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_ROW                        11
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_FIELD                       (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_RANGE                       _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_FIELD                        (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_ROW                  0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_VALID_TD_PTR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_INVALID_TD_PTR                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_FIELD                   (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_ROW                     1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_FIELD                        (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_VALID_TD_PTR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_INVALID_TD_PTR                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_ROW                  2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_DATA0                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_DATA1                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_FIELD                        (_MK_MASK_CONST(0x7fff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_RANGE                        _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_ROW                  2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_ROW                  2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_FIELD                       (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_RANGE                       _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_ROW                 2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_SHIFT                        _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_FIELD                        (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_ROW                  2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_SHIFT                   _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_RANGE                   _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_ROW                     2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_OUT                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_IN                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_SETUP                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_RESERVED                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT                     _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_ROW                       2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_RANGE                     _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_ROW                       2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_RANGE                  _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT                    _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_ROW                      2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_RANGE                  _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_RANGE                 _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_ROW                   2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_RANGE                  _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_START_SPLIT                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_COMPLETE_SPLIT                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_RANGE                 _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_ROW                   2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_DO_OUT                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_DO_PING                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                        3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_ROW                   3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                        4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_FIELD                        (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_ROW                  4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_ROW                        5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_FIELD                        (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_ROW                  5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_ROW                        6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_ROW                 6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_ROW                        7
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_ROW                 7
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_FIELD                       (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_RANGE                       _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_RANGE                       _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_ROW                 0
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_ITD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_QH                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_SITD                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_FSTN                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_ROW                 0
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_FIELD                        (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_ROW                  0
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_ROW                    0
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_RANGE                  _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ROW                    0
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ITD                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_QH                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SITD                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FSTN                   _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_ROW                      0
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_VALID_LINK_PTR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_INVALID_LINK_PTR                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_ROW                       1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_ROW                      1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_ROW                   1
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_ROW                  1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_ROW                   1
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_ROW                       2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_ROW                      2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_ROW                   2
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_ROW                  2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_ROW                  2
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_ROW                   2
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_ROW                       3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_ROW                    3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_ROW                      3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_ROW                    3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_ROW                   3
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_ROW                  3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_ROW                  3
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_ROW                   3
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_ROW                       4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_ROW                    4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_ROW                      4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_ROW                    4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_ROW                   4
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_ROW                  4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_ROW                  4
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_ROW                   4
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_ROW                       5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_ROW                    5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_ROW                      5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_ROW                    5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_ROW                   5
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_ROW                  5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_ROW                  5
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_ROW                   5
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_ROW                       6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_ROW                    6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_ROW                      6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_ROW                    6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_ROW                   6
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_ROW                  6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_ROW                  6
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_ROW                   6
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_ROW                       7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_ROW                    7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_ROW                      7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_ROW                    7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_ROW                   7
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_ROW                  7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_ROW                  7
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_ROW                   7
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_ROW                       8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_ROW                    8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_ROW                      8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_ROW                    8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_ROW                   8
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_ROW                  8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_ROW                  8
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_ROW                   8
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                  9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_FIELD                  (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_RANGE                  _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_ROW                    9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_ROW                    9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_FIELD                  (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_RANGE                  _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_ROW                    9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                  10
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT                    _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_ROW                      10
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_OUT                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_IN                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_FIELD                 (_MK_MASK_CONST(0x7ff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_RANGE                 _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_ROW                   10
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_ROW                  11
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_FIELD                 (_MK_MASK_CONST(0x3ff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_ROW                   11
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_RANGE                 _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_ROW                   11
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_RESERVED                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_MULTI_1                       _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_MULT_2                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_MULTI_3                       _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_ROW                  12
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_ROW                   12
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_ROW                  13
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_ROW                   13
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_ROW                  14
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_ROW                   14
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_ROW                  15
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_ROW                   15
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_FIELD                  (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_ROW                    0
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT                    _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_ROW                      0
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ROW                      0
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ITD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_QH                       _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SITD                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FSTN                     _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_VALID_LINK_PTR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_INVALID_LINK_PTR                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT                      _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_ROW                        1
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_OUT                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_IN                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_SHIFT                    _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_FIELD                    (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_RANGE                    _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_FIELD                       (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_RANGE                       _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_RANGE                    _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_FIELD                    (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_FIELD                    (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_ROW                      2
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_RANGE                  _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_SHIFT                    _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_ROW                      3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_ENABLE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_RANGE                    _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT                    _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_FIELD                    (_MK_MASK_CONST(0x3ff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_RANGE                    _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_FIELD                    (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_ROW                   3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_RANGE                  _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_ROW                    3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_ROW                        3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_ROW                  3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SET                  _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT                      _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_RANGE                      _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_ROW                        3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_RANGE                     _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_ROW                       3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT                      _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_RANGE                      _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_ROW                        3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_START_SPLIT                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_COMPLETE_SPLIT                  _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                    4
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_ROW                       4
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                    5
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_FIELD                    (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_ROW                      5
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_RANGE                   _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_ROW                     5
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_ALL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_BEGIN                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_MID                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_END                     _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_FIELD                      (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_RANGE                      _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_ROW                        5
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_FIELD                  (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_ROW                    6
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_ROW                      6
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_RANGE                   _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_ROW                     6
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_VALID_BACK_PTR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_INVALID_BACK_PTR                        _MK_ENUM_CONST(1)
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_FIELD                      (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_ROW                        0
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_RANGE                       _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_ROW                 0
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_ITD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_QH                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_SITD                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_FSTN                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_RANGE                 _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_ROW                   0
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_VALID_LINK_PTR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_INVALID_LINK_PTR                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_FIELD                        (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_ROW                      1
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_ITD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_QH                       _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_SITD                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_FSTN                     _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_ROW                        1
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_VALID_LINK_PTR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_INVALID_LINK_PTR                   _MK_ENUM_CONST(1)
+
+
+// Register USB2_IF_USB_SUSP_CTRL_0  
+#define USB2_IF_USB_SUSP_CTRL_0                 _MK_ADDR_CONST(0x400)
+#define USB2_IF_USB_SUSP_CTRL_0_SECURE                  0x0
+#define USB2_IF_USB_SUSP_CTRL_0_WORD_COUNT                      0x1
+#define USB2_IF_USB_SUSP_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0x73fff)
+#define USB2_IF_USB_SUSP_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_READ_MASK                       _MK_MASK_CONST(0x73fff)
+#define USB2_IF_USB_SUSP_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x73e3e)
+// USB PHY wakeup debounce counter
+// USB will debounce any wakeup event by the number of clocks programmed 
+// in this counter.
+// A value of 0 results in no debounce.
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_FIELD                 (_MK_MASK_CONST(0x7) << USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_RANGE                 18:16
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_WOFFSET                       0x0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Enable ULPI PHY mode.
+// Set this to 1 if using null or link ULPI PHY.
+// Otherwise set this to 0.
+#define USB2_IF_USB_SUSP_CTRL_0_ULPI_PHY_ENB_SHIFT                      _MK_SHIFT_CONST(13)
+#define USB2_IF_USB_SUSP_CTRL_0_ULPI_PHY_ENB_FIELD                      (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_ULPI_PHY_ENB_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_ULPI_PHY_ENB_RANGE                      13:13
+#define USB2_IF_USB_SUSP_CTRL_0_ULPI_PHY_ENB_WOFFSET                    0x0
+#define USB2_IF_USB_SUSP_CTRL_0_ULPI_PHY_ENB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_ULPI_PHY_ENB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_ULPI_PHY_ENB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_ULPI_PHY_ENB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_ULPI_PHY_ENB_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_ULPI_PHY_ENB_ENABLE                     _MK_ENUM_CONST(1)
+
+// Enable UHSIC PHY mode.
+// Set this to 1 if using UHSIC PHY.
+// Otherwise set this to 0.
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_PHY_ENB_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_PHY_ENB_FIELD                     (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_UHSIC_PHY_ENB_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_PHY_ENB_RANGE                     12:12
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_PHY_ENB_WOFFSET                   0x0
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_PHY_ENB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_PHY_ENB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_PHY_ENB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_PHY_ENB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_PHY_ENB_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_PHY_ENB_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset going to UHSIC PHY (active high).
+// This should be set to 1 whenever programming the UHSIC config registers.
+// It should be cleared to 0 after the programming of UHSIC config registers is done.
+// UHSIC config registers should be programmed only once before doing any transactions on
+// UHSIC.
+// The UHSIC PHY registers should be programmed while UHSIC is in reset.
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_RESET_SHIFT                       _MK_SHIFT_CONST(11)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_RESET_FIELD                       (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_UHSIC_RESET_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_RESET_RANGE                       11:11
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_RESET_WOFFSET                     0x0
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_RESET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_RESET_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_RESET_ENABLE                      _MK_ENUM_CONST(1)
+
+// Polarity of the suspend signal going to UHSIC PHY.
+// 0 = Active low (default)
+// 1 = Active high
+// This should not be changed by software.
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_SUSP_POL_SHIFT                    _MK_SHIFT_CONST(10)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_SUSP_POL_FIELD                    (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_UHSIC_SUSP_POL_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_SUSP_POL_RANGE                    10:10
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_SUSP_POL_WOFFSET                  0x0
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_SUSP_POL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_SUSP_POL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_SUSP_POL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_SUSP_POL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_SUSP_POL_ACTIVE_LOW                       _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_UHSIC_SUSP_POL_ACTIVE_HIGH                      _MK_ENUM_CONST(1)
+
+// USB PHY clock valid interrupt enable
+// If this bit is enabled, interrupt is generated
+// whenever USB clocks are resumed from a suspend.
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SHIFT                 _MK_SHIFT_CONST(9)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_FIELD                 (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_RANGE                 9:9
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_WOFFSET                       0x0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_ENABLE                        _MK_ENUM_CONST(1)
+
+// USB PHY clock valid interrupt status
+// This bit is set whenever USB PHY clock is waked up from suspend.
+// Software must write a 1 to clear this bit.
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_RANGE                 8:8
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_WOFFSET                       0x0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_UNSET                 _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SET                   _MK_ENUM_CONST(1)
+
+// USB PHY clock valid status
+// This bit indicates whether the USB PHY is generating a valid clock to 
+// the USB controller.
+// If USB PHY clock is running, this bit is set to 1, else it is set to 0.
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_FIELD                 (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_RANGE                 7:7
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_WOFFSET                       0x0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_UNSET                 _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SET                   _MK_ENUM_CONST(1)
+
+// USB AHB clock enable status.
+// Indicates whether the AHB clock to the USB controller is enabled or not.
+// If AHB clock to USB controller is enabled, this bit is set to 1, else it is set to 0.
+// NOTE: even when this is set to 0, all essential blocks that are required
+// to resume USB clocks from suspend will be active and their AHB clock will not
+// be suspended.
+#define USB2_IF_USB_SUSP_CTRL_0_USB_CLKEN_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_CLKEN_FIELD                 (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_USB_CLKEN_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_CLKEN_RANGE                 6:6
+#define USB2_IF_USB_SUSP_CTRL_0_USB_CLKEN_WOFFSET                       0x0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_CLKEN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_CLKEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_CLKEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_CLKEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_CLKEN_UNSET                 _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_CLKEN_SET                   _MK_ENUM_CONST(1)
+
+//Suspend Clear
+// Software must write a 1 to this bit to bring the PHY
+// out of suspend mode. This is used when the software stops the PHY
+// clock during suspend and then wants to initiate a resume. Software
+// should also write 0 to clear it.
+// NOTE: It is required that software generate a  positive pulse on this
+// bit to guarantee proper operation.
+#define USB2_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_RANGE                      5:5
+#define USB2_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_WOFFSET                    0x0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_UNSET                      _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SET                        _MK_ENUM_CONST(1)
+
+// Wake on Disconnect Enable (device mode)
+// When enabled (1), USB device will wakeup
+// from suspend on a disconnect event.
+// This is only valid when USB controller is in device mode, it is
+// not applicable when USB controller is in host mode.
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_FIELD                 (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_RANGE                 4:4
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_WOFFSET                       0x0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_ENABLE                        _MK_ENUM_CONST(1)
+
+// Wake on Connect Enable (device mode)
+// When enabled (1), USB device will wakeup
+// from suspend on a connect event.
+// This is only valid when USB controller is in device mode, it is
+// not applicable when USB controller is in host mode.
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_FIELD                   (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_RANGE                   3:3
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_WOFFSET                 0x0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_ENABLE                  _MK_ENUM_CONST(1)
+
+// Wake on resume enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a resume event is detected on USB.
+// This is valid for both USB device and USB host modes.
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_FIELD                     (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_RANGE                     2:2
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_WOFFSET                   0x0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// USB wakeup interrupt enable
+// If this bit is enabled, interrupt is generated
+// whenever USB wakeup event is generated.
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_FIELD                        (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_RANGE                        1:1
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_WOFFSET                      0x0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_ENABLE                       _MK_ENUM_CONST(1)
+
+// USB wakeup interrupt status
+// This bit is set whenever USB wakes up from suspend (a wakeup event
+// is generated).
+// Software must write a 1 to clear this bit.
+// Note that during the wakeup sequence, PHY clocks will be resumed from suspend.
+// Software can check when the PHY clocks are resumed by reading the bit
+// USB_PHY_CLK_VALID. There is also a separate interrupt generated
+// when PHY clock is resumed if USB_PHY_CLK_VALID_INT_EN is set.
+// During the wakeup sequence, first USB_WAKEUP_INT_STS will be set, and
+// it will take some time for the PHY clock to resume, which can be detected
+// by checking USB_PHY_CLK_VALID.
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_FIELD                        (_MK_MASK_CONST(0x1) << USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SHIFT)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_RANGE                        0:0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_WOFFSET                      0x0
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_UNSET                        _MK_ENUM_CONST(0)
+#define USB2_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SET                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 1028 [0x404] 
+
+// Reserved address 1032 [0x408] 
+
+// Reserved address 1036 [0x40c] 
+
+// Reserved address 1040 [0x410] 
+
+// Reserved address 1044 [0x414] 
+
+// Register USB2_IF_USB_ULPIS2S_CTRL_0  
+#define USB2_IF_USB_ULPIS2S_CTRL_0                      _MK_ADDR_CONST(0x418)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_SECURE                       0x0
+#define USB2_IF_USB_ULPIS2S_CTRL_0_WORD_COUNT                   0x1
+#define USB2_IF_USB_ULPIS2S_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0xff0f)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_READ_MASK                    _MK_MASK_CONST(0xff0f)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0xff0f)
+// When enabled, the ULPI link interface coming out of
+// the usb2 controller enters a NULL phy with two slaves. As a result the external
+// pins will have a slave ULPI interface.
+// When disabled, the ULPI link interface coming out of the usb2 controller go straight
+// to the pins. 
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_ENA_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_ENA_FIELD                    (_MK_MASK_CONST(0x1) << USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_ENA_SHIFT)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_ENA_RANGE                    0:0
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_ENA_WOFFSET                  0x0
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_ENA_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_ENA_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_ENA_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_ENA_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_ENA_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_ENA_ENABLE                   _MK_ENUM_CONST(1)
+
+// When disabled, the slave port that's connected to the pins
+// can be programmed to be host or a device depending on the value of the DpPulldown and
+// DmPulldown bits in the OTG_CTRL ULPI register.
+// When enables, the values of those bits in the OTG_CTRL register is ignored and the port
+// will always behave like a device.
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SLV1_FORCE_DEVICE_SHIFT                      _MK_SHIFT_CONST(1)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SLV1_FORCE_DEVICE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SLV1_FORCE_DEVICE_SHIFT)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SLV1_FORCE_DEVICE_RANGE                      1:1
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SLV1_FORCE_DEVICE_WOFFSET                    0x0
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SLV1_FORCE_DEVICE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SLV1_FORCE_DEVICE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SLV1_FORCE_DEVICE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SLV1_FORCE_DEVICE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SLV1_FORCE_DEVICE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SLV1_FORCE_DEVICE_ENABLE                     _MK_ENUM_CONST(1)
+
+// When disabled, the PHY will never detect a Disconnect.
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_DISCONNECT_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_DISCONNECT_FIELD                     (_MK_MASK_CONST(0x1) << USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_DISCONNECT_SHIFT)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_DISCONNECT_RANGE                     2:2
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_DISCONNECT_WOFFSET                   0x0
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_DISCONNECT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_DISCONNECT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_DISCONNECT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_DISCONNECT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_DISCONNECT_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_DISCONNECT_ENABLE                    _MK_ENUM_CONST(1)
+
+// When enabled, the PLLU 60MHz clock will be forced on.
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_PLLU_MASTER_BLASTER60_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_PLLU_MASTER_BLASTER60_FIELD                  (_MK_MASK_CONST(0x1) << USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_PLLU_MASTER_BLASTER60_SHIFT)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_PLLU_MASTER_BLASTER60_RANGE                  3:3
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_PLLU_MASTER_BLASTER60_WOFFSET                        0x0
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_PLLU_MASTER_BLASTER60_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_PLLU_MASTER_BLASTER60_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_PLLU_MASTER_BLASTER60_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_PLLU_MASTER_BLASTER60_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_PLLU_MASTER_BLASTER60_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_PLLU_MASTER_BLASTER60_ENABLE                 _MK_ENUM_CONST(1)
+
+// Reserved bits
+// When enabled, it will when the other side goes to OPMODE1.
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SPARE_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SPARE_FIELD                  (_MK_MASK_CONST(0xf) << USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SPARE_SHIFT)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SPARE_RANGE                  11:8
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SPARE_WOFFSET                        0x0
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SPARE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SPARE_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SPARE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SPARE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// When enabled and ULPIS2S_ENA is ENABLED, the external ULPI_CLOCK
+// pad will always carry the internal 60MHz clock, even if the interface is in shutdown mode.
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_FORCE_ULPI_CLK_OUT_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_FORCE_ULPI_CLK_OUT_FIELD                     (_MK_MASK_CONST(0x1) << USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_FORCE_ULPI_CLK_OUT_SHIFT)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_FORCE_ULPI_CLK_OUT_RANGE                     12:12
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_FORCE_ULPI_CLK_OUT_WOFFSET                   0x0
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_FORCE_ULPI_CLK_OUT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_FORCE_ULPI_CLK_OUT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_FORCE_ULPI_CLK_OUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_FORCE_ULPI_CLK_OUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_FORCE_ULPI_CLK_OUT_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_FORCE_ULPI_CLK_OUT_ENABLE                    _MK_ENUM_CONST(1)
+
+// When enabled, the disconnect detection logic will only check that
+// that the other side is 'driving' tri-state. It won't check whether or not the local side is
+// driving SE0.
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISCON_DONT_CHECK_SE0_SHIFT                  _MK_SHIFT_CONST(13)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISCON_DONT_CHECK_SE0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISCON_DONT_CHECK_SE0_SHIFT)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISCON_DONT_CHECK_SE0_RANGE                  13:13
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISCON_DONT_CHECK_SE0_WOFFSET                        0x0
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISCON_DONT_CHECK_SE0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISCON_DONT_CHECK_SE0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISCON_DONT_CHECK_SE0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISCON_DONT_CHECK_SE0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISCON_DONT_CHECK_SE0_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISCON_DONT_CHECK_SE0_ENABLE                 _MK_ENUM_CONST(1)
+
+// When enabled, the PHY will support HS KeepAlive packets. In that case,
+// this would be the only thing that's supported in Opmode3. All other Opmode3 generate packets are
+// not supported under any circumstances.
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_HS_KEEP_ALIVE_SHIFT                  _MK_SHIFT_CONST(14)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_HS_KEEP_ALIVE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_HS_KEEP_ALIVE_SHIFT)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_HS_KEEP_ALIVE_RANGE                  14:14
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_HS_KEEP_ALIVE_WOFFSET                        0x0
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_HS_KEEP_ALIVE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_HS_KEEP_ALIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_HS_KEEP_ALIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_HS_KEEP_ALIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_HS_KEEP_ALIVE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_SUPPORT_HS_KEEP_ALIVE_ENABLE                 _MK_ENUM_CONST(1)
+
+// When set to 1 and in ULPIS2S mode, the pullup on the STP pin will NOT be active, even if
+// the remote LINK asks to do so. In this case, an external pullup resistor would be required to
+// ensure valid levels when the remote link is not powered.
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISABLE_STP_PU_SHIFT                 _MK_SHIFT_CONST(15)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISABLE_STP_PU_FIELD                 (_MK_MASK_CONST(0x1) << USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISABLE_STP_PU_SHIFT)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISABLE_STP_PU_RANGE                 15:15
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISABLE_STP_PU_WOFFSET                       0x0
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISABLE_STP_PU_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISABLE_STP_PU_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISABLE_STP_PU_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_CTRL_0_ULPIS2S_DISABLE_STP_PU_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register USB2_IF_USB_ULPIS2S_SLV1_ID_0  
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0                   _MK_ADDR_CONST(0x41c)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_SECURE                    0x0
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_WORD_COUNT                        0x1
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// PHY product_id as seen by external ULPI master
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_PRODUCT_ID_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_PRODUCT_ID_FIELD                     (_MK_MASK_CONST(0xffff) << USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_PRODUCT_ID_SHIFT)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_PRODUCT_ID_RANGE                     15:0
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_PRODUCT_ID_WOFFSET                   0x0
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_PRODUCT_ID_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_PRODUCT_ID_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_PRODUCT_ID_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_PRODUCT_ID_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// PHY vendor_id as seen by external ULPI master
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_VENDOR_ID_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_VENDOR_ID_FIELD                      (_MK_MASK_CONST(0xffff) << USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_VENDOR_ID_SHIFT)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_VENDOR_ID_RANGE                      31:16
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_VENDOR_ID_WOFFSET                    0x0
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_VENDOR_ID_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_VENDOR_ID_DEFAULT_MASK                       _MK_MASK_CONST(0xffff)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_VENDOR_ID_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_ULPIS2S_SLV1_ID_0_ULPIS2S_SLV1_VENDOR_ID_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_IF_USB_INTER_PKT_DELAY_CTRL_0  
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0                      _MK_ADDR_CONST(0x420)
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_SECURE                       0x0
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_WORD_COUNT                   0x1
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x12)
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_READ_MASK                    _MK_MASK_CONST(0x3f)
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
+// HS Tx to Tx inter-packet delay.
+// This is valid only for UHSIC PHY.
+// Software should not change this.
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_FIELD                      (_MK_MASK_CONST(0x3f) << USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SHIFT)
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_RANGE                      5:0
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_WOFFSET                    0x0
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_DEFAULT                    _MK_MASK_CONST(0x12)
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_IF_ULPI_TIMING_CTRL_0_0  
+#define USB2_IF_ULPI_TIMING_CTRL_0_0                    _MK_ADDR_CONST(0x424)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_SECURE                     0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_WORD_COUNT                         0x1
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_RESET_VAL                  _MK_MASK_CONST(0x4000000)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_RESET_MASK                         _MK_MASK_CONST(0x3c1ffc1f)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_READ_MASK                  _MK_MASK_CONST(0x3c1ffc1f)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_WRITE_MASK                         _MK_MASK_CONST(0x3c1ffc1f)
+// Programmable delay on the ULPI Clock out
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLOCK_OUT_DELAY_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLOCK_OUT_DELAY_FIELD                 (_MK_MASK_CONST(0x1f) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLOCK_OUT_DELAY_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLOCK_OUT_DELAY_RANGE                 4:0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLOCK_OUT_DELAY_WOFFSET                       0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLOCK_OUT_DELAY_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLOCK_OUT_DELAY_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLOCK_OUT_DELAY_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLOCK_OUT_DELAY_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Bypass the pinmux on the ULPI output pins
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_OUTPUT_PINMUX_BYP_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_OUTPUT_PINMUX_BYP_FIELD                       (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_OUTPUT_PINMUX_BYP_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_OUTPUT_PINMUX_BYP_RANGE                       10:10
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_OUTPUT_PINMUX_BYP_WOFFSET                     0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_OUTPUT_PINMUX_BYP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_OUTPUT_PINMUX_BYP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_OUTPUT_PINMUX_BYP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_OUTPUT_PINMUX_BYP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_OUTPUT_PINMUX_BYP_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_OUTPUT_PINMUX_BYP_ENABLE                      _MK_ENUM_CONST(1)
+
+// Bypass the pinmux on the ULPI Clk
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLKOUT_PINMUX_BYP_SHIFT                       _MK_SHIFT_CONST(11)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLKOUT_PINMUX_BYP_FIELD                       (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLKOUT_PINMUX_BYP_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLKOUT_PINMUX_BYP_RANGE                       11:11
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLKOUT_PINMUX_BYP_WOFFSET                     0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLKOUT_PINMUX_BYP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLKOUT_PINMUX_BYP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLKOUT_PINMUX_BYP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLKOUT_PINMUX_BYP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLKOUT_PINMUX_BYP_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLKOUT_PINMUX_BYP_ENABLE                      _MK_ENUM_CONST(1)
+
+// Loopback the Shadow Clock at the PAD
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_LOOPBACK_EN_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_LOOPBACK_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_LOOPBACK_EN_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_LOOPBACK_EN_RANGE                  12:12
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_LOOPBACK_EN_WOFFSET                        0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_LOOPBACK_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_LOOPBACK_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_LOOPBACK_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_LOOPBACK_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_LOOPBACK_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_LOOPBACK_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// Mux to select between the pre-pad
+//   and post-pad Shadow clks 
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_SEL_SHIFT                  _MK_SHIFT_CONST(13)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_SEL_FIELD                  (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_SEL_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_SEL_RANGE                  13:13
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_SEL_WOFFSET                        0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_SEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_SEL_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_SEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_SEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_SEL_PRE_PAD                        _MK_ENUM_CONST(0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_SEL_POST_PAD                       _MK_ENUM_CONST(1)
+
+// Mux to select between the ulpi clk out and Shadow clk
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CORE_CLK_SEL_SHIFT                    _MK_SHIFT_CONST(14)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CORE_CLK_SEL_FIELD                    (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CORE_CLK_SEL_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CORE_CLK_SEL_RANGE                    14:14
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CORE_CLK_SEL_WOFFSET                  0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CORE_CLK_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CORE_CLK_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CORE_CLK_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CORE_CLK_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CORE_CLK_SEL_ULPI_CLK_OUT                     _MK_ENUM_CONST(0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CORE_CLK_SEL_SHADOW_CLK                       _MK_ENUM_CONST(1)
+
+// ULPI Clock polarity control
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_POL_SHIFT                 _MK_SHIFT_CONST(15)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_POL_FIELD                 (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_POL_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_POL_RANGE                 15:15
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_POL_WOFFSET                       0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_POL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_POL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_POL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_POL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_POL_NORMAL                        _MK_ENUM_CONST(0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_POL_INVERTED                      _MK_ENUM_CONST(1)
+
+// Programmable delay on the Shadow ULPI Clock 
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_DELAY_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_DELAY_FIELD                        (_MK_MASK_CONST(0x1f) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_DELAY_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_DELAY_RANGE                        20:16
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_DELAY_WOFFSET                      0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_DELAY_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_DELAY_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_DELAY_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_SHADOW_CLK_DELAY_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// LOOPBACK PAD Output Enable
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_EN_SHIFT                      _MK_SHIFT_CONST(26)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_EN_FIELD                      (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_EN_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_EN_RANGE                      26:26
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_EN_WOFFSET                    0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_EN_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_EN_OUTPUT                     _MK_ENUM_CONST(0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_EN_INPUT                      _MK_ENUM_CONST(1)
+
+// LOOPBACK PAD E_input_or input
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_E_INPUT_OR_SHIFT                      _MK_SHIFT_CONST(27)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_E_INPUT_OR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_E_INPUT_OR_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_E_INPUT_OR_RANGE                      27:27
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_E_INPUT_OR_WOFFSET                    0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_E_INPUT_OR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_E_INPUT_OR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_E_INPUT_OR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_LBK_PAD_E_INPUT_OR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Option to gate the ulpi_ck_out
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_OUT_ENA_SHIFT                     _MK_SHIFT_CONST(28)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_OUT_ENA_FIELD                     (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_OUT_ENA_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_OUT_ENA_RANGE                     28:28
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_OUT_ENA_WOFFSET                   0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_OUT_ENA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_OUT_ENA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_OUT_ENA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_OUT_ENA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Option to disable clk to the ulpi_clk_out pad
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_PADOUT_ENA_SHIFT                  _MK_SHIFT_CONST(29)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_PADOUT_ENA_FIELD                  (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_PADOUT_ENA_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_PADOUT_ENA_RANGE                  29:29
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_PADOUT_ENA_WOFFSET                        0x0
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_PADOUT_ENA_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_PADOUT_ENA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_PADOUT_ENA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_0_0_ULPI_CLK_PADOUT_ENA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register USB2_IF_ULPI_TIMING_CTRL_1_0  
+#define USB2_IF_ULPI_TIMING_CTRL_1_0                    _MK_ADDR_CONST(0x428)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_SECURE                     0x0
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_WORD_COUNT                         0x1
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_RESET_MASK                         _MK_MASK_CONST(0xf0f000f)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_READ_MASK                  _MK_MASK_CONST(0xf0f000f)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_WRITE_MASK                         _MK_MASK_CONST(0xf0f000f)
+// Load the trimmer value to the ulpi_data_trimmer on the ulpi_data_in signals
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_LOAD_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_LOAD_FIELD                       (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_LOAD_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_LOAD_RANGE                       0:0
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_LOAD_WOFFSET                     0x0
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_LOAD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_LOAD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_LOAD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_LOAD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// ULPI Data Trimmer Value
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_SEL_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_SEL_FIELD                        (_MK_MASK_CONST(0x7) << USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_SEL_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_SEL_RANGE                        3:1
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_SEL_WOFFSET                      0x0
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DATA_TRIMMER_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Load the trimmer value to the ulpi_stp/dir/nxt_trimmer 
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_LOAD_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_LOAD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_LOAD_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_LOAD_RANGE                  16:16
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_LOAD_WOFFSET                        0x0
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_LOAD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_LOAD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_LOAD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_LOAD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// ULPI STP/DIR/NXT Trimmer Value
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_SEL_SHIFT                   _MK_SHIFT_CONST(17)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_SEL_FIELD                   (_MK_MASK_CONST(0x7) << USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_SEL_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_SEL_RANGE                   19:17
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_SEL_WOFFSET                 0x0
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_SEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_SEL_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_SEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_STPDIRNXT_TRIMMER_SEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Load the trimmer value to the ulpi_dir that shut's off the oen's in ULPI mode
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_LOAD_SHIFT                        _MK_SHIFT_CONST(24)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_LOAD_FIELD                        (_MK_MASK_CONST(0x1) << USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_LOAD_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_LOAD_RANGE                        24:24
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_LOAD_WOFFSET                      0x0
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_LOAD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_LOAD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_LOAD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_LOAD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// ULPI DIR Trimmer Value (that shut's off the oen's in ULPI mode)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_SEL_SHIFT                 _MK_SHIFT_CONST(25)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_SEL_FIELD                 (_MK_MASK_CONST(0x7) << USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_SEL_SHIFT)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_SEL_RANGE                 27:25
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_SEL_WOFFSET                       0x0
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_ULPI_TIMING_CTRL_1_0_ULPI_DIR_TRIMMER_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register USB2_IF_USB_DEBUG_0  
+#define USB2_IF_USB_DEBUG_0                     _MK_ADDR_CONST(0x480)
+#define USB2_IF_USB_DEBUG_0_SECURE                      0x0
+#define USB2_IF_USB_DEBUG_0_WORD_COUNT                  0x1
+#define USB2_IF_USB_DEBUG_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_DEBUG_0_RESET_MASK                  _MK_MASK_CONST(0x60)
+#define USB2_IF_USB_DEBUG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_DEBUG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_DEBUG_0_READ_MASK                   _MK_MASK_CONST(0x60)
+#define USB2_IF_USB_DEBUG_0_WRITE_MASK                  _MK_MASK_CONST(0x60)
+// Lower 32-bits select.
+// Only valid for Tx and Rx memories that
+// have 36-bit interface. When 0, selects
+// upper 4-bits. When 1, selects lower
+// 32-bits.
+#define USB2_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_FIELD                 (_MK_MASK_CONST(0x1) << USB2_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SHIFT)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_RANGE                 6:6
+#define USB2_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_WOFFSET                       0x0
+#define USB2_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_UPPER_BITS                    _MK_ENUM_CONST(0)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_LOWER_BITS                    _MK_ENUM_CONST(1)
+
+// Route USB buffers to AHB interface for debug.
+// When this is set to 1, normal USB
+// operations cannot be done.
+#define USB2_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_FIELD                    (_MK_MASK_CONST(0x1) << USB2_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SHIFT)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_RANGE                    5:5
+#define USB2_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_WOFFSET                  0x0
+#define USB2_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Reserved address 1156 [0x484] 
+
+// Reserved address 1160 [0x488] 
+
+// Reserved address 1164 [0x48c] 
+
+// Register USB2_UHSIC_PLL_CFG0_0  // UHSIC  PHY PLL Configuration Register 0
+#define USB2_UHSIC_PLL_CFG0_0                   _MK_ADDR_CONST(0x800)
+#define USB2_UHSIC_PLL_CFG0_0_SECURE                    0x0
+#define USB2_UHSIC_PLL_CFG0_0_WORD_COUNT                        0x1
+#define USB2_UHSIC_PLL_CFG0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG0_0_RESET_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PLL_CFG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG0_0_READ_MASK                         _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PLL_CFG0_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
+// Reserved
+#define USB2_UHSIC_PLL_CFG0_0_UHSIC_PLL_SPARE_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_PLL_CFG0_0_UHSIC_PLL_SPARE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_UHSIC_PLL_CFG0_0_UHSIC_PLL_SPARE_SHIFT)
+#define USB2_UHSIC_PLL_CFG0_0_UHSIC_PLL_SPARE_RANGE                     0:0
+#define USB2_UHSIC_PLL_CFG0_0_UHSIC_PLL_SPARE_WOFFSET                   0x0
+#define USB2_UHSIC_PLL_CFG0_0_UHSIC_PLL_SPARE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG0_0_UHSIC_PLL_SPARE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PLL_CFG0_0_UHSIC_PLL_SPARE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG0_0_UHSIC_PLL_SPARE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_UHSIC_PLL_CFG1_0  // UHSIC PLL and PLLU configuration register 1
+#define USB2_UHSIC_PLL_CFG1_0                   _MK_ADDR_CONST(0x804)
+#define USB2_UHSIC_PLL_CFG1_0_SECURE                    0x0
+#define USB2_UHSIC_PLL_CFG1_0_WORD_COUNT                        0x1
+#define USB2_UHSIC_PLL_CFG1_0_RESET_VAL                         _MK_MASK_CONST(0xc0c0)
+#define USB2_UHSIC_PLL_CFG1_0_RESET_MASK                        _MK_MASK_CONST(0x7ffff)
+#define USB2_UHSIC_PLL_CFG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG1_0_READ_MASK                         _MK_MASK_CONST(0x7ffff)
+#define USB2_UHSIC_PLL_CFG1_0_WRITE_MASK                        _MK_MASK_CONST(0x7ffff)
+// 2.5ms / (1/19.2MHz) = 48000 / 256 = 187 = 0xBB
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_XTAL_FREQ_COUNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_XTAL_FREQ_COUNT_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_UHSIC_PLL_CFG1_0_UHSIC_XTAL_FREQ_COUNT_SHIFT)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_XTAL_FREQ_COUNT_RANGE                       11:0
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_XTAL_FREQ_COUNT_WOFFSET                     0x0
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_XTAL_FREQ_COUNT_DEFAULT                     _MK_MASK_CONST(0xc0)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_XTAL_FREQ_COUNT_DEFAULT_MASK                        _MK_MASK_CONST(0xfff)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_XTAL_FREQ_COUNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_XTAL_FREQ_COUNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERDOWN_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERDOWN_FIELD                  (_MK_MASK_CONST(0x1) << USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERDOWN_SHIFT)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERDOWN_RANGE                  12:12
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERDOWN_WOFFSET                        0x0
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERDOWN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERUP_SHIFT                    _MK_SHIFT_CONST(13)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERUP_FIELD                    (_MK_MASK_CONST(0x1) << USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERUP_SHIFT)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERUP_RANGE                    13:13
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERUP_WOFFSET                  0x0
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERUP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_FORCE_PLLU_POWERUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1 us / (1/19.2MHz) = 19 / 8 = 2.36 = 3
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_PLLU_ENABLE_DLY_COUNT_SHIFT                 _MK_SHIFT_CONST(14)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_PLLU_ENABLE_DLY_COUNT_FIELD                 (_MK_MASK_CONST(0x1f) << USB2_UHSIC_PLL_CFG1_0_UHSIC_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_PLLU_ENABLE_DLY_COUNT_RANGE                 18:14
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_PLLU_ENABLE_DLY_COUNT_WOFFSET                       0x0
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_PLLU_ENABLE_DLY_COUNT_DEFAULT                       _MK_MASK_CONST(0x3)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_PLLU_ENABLE_DLY_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PLL_CFG1_0_UHSIC_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register USB2_UHSIC_HSRX_CFG0_0  // UHSIC High speed receive config 0 
+#define USB2_UHSIC_HSRX_CFG0_0                  _MK_ADDR_CONST(0x808)
+#define USB2_UHSIC_HSRX_CFG0_0_SECURE                   0x0
+#define USB2_UHSIC_HSRX_CFG0_0_WORD_COUNT                       0x1
+#define USB2_UHSIC_HSRX_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x14e38)
+#define USB2_UHSIC_HSRX_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x7ffff)
+#define USB2_UHSIC_HSRX_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x7ffff)
+#define USB2_UHSIC_HSRX_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x7ffff)
+// Pass through the feedback, do not block it.
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_PASS_FEEDBACK_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_PASS_FEEDBACK_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_HSRX_CFG0_0_UHSIC_PASS_FEEDBACK_SHIFT)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_PASS_FEEDBACK_RANGE                        0:0
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_PASS_FEEDBACK_WOFFSET                      0x0
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_PASS_FEEDBACK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_PASS_FEEDBACK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_PASS_FEEDBACK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_PASS_FEEDBACK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Do not declare underrun errors
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_DISABLE_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_DISABLE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_DISABLE_SHIFT)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_DISABLE_RANGE                     1:1
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_DISABLE_WOFFSET                   0x0
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_DISABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_DISABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_LIMIT_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_LIMIT_FIELD                       (_MK_MASK_CONST(0x1f) << USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_LIMIT_SHIFT)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_LIMIT_RANGE                       6:2
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_LIMIT_WOFFSET                     0x0
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_LIMIT_DEFAULT                     _MK_MASK_CONST(0xe)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_LIMIT_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_LIMIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_UNDERRUN_LIMIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Do not declare overrun errors until overflow of FIFO
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_DISABLE_SHIFT                      _MK_SHIFT_CONST(7)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_DISABLE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_DISABLE_SHIFT)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_DISABLE_RANGE                      7:7
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_DISABLE_WOFFSET                    0x0
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_LIMIT_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_LIMIT_FIELD                        (_MK_MASK_CONST(0x1f) << USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_LIMIT_SHIFT)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_LIMIT_RANGE                        12:8
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_LIMIT_WOFFSET                      0x0
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_LIMIT_DEFAULT                      _MK_MASK_CONST(0xe)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_LIMIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_LIMIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_ELASTIC_OVERRUN_LIMIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Number of cycles of idle to declare IDLE. 
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_IDLE_WAIT_SHIFT                    _MK_SHIFT_CONST(13)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_IDLE_WAIT_FIELD                    (_MK_MASK_CONST(0x1f) << USB2_UHSIC_HSRX_CFG0_0_UHSIC_IDLE_WAIT_SHIFT)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_IDLE_WAIT_RANGE                    17:13
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_IDLE_WAIT_WOFFSET                  0x0
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_IDLE_WAIT_DEFAULT                  _MK_MASK_CONST(0xa)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_IDLE_WAIT_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_IDLE_WAIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_IDLE_WAIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Do not strip incoming data
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_NO_STRIPPING_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_NO_STRIPPING_FIELD                 (_MK_MASK_CONST(0x1) << USB2_UHSIC_HSRX_CFG0_0_UHSIC_NO_STRIPPING_SHIFT)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_NO_STRIPPING_RANGE                 18:18
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_NO_STRIPPING_WOFFSET                       0x0
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_NO_STRIPPING_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_NO_STRIPPING_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_NO_STRIPPING_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG0_0_UHSIC_NO_STRIPPING_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register USB2_UHSIC_HSRX_CFG1_0  // UHSIC High speed receive config 1
+#define USB2_UHSIC_HSRX_CFG1_0                  _MK_ADDR_CONST(0x80c)
+#define USB2_UHSIC_HSRX_CFG1_0_SECURE                   0x0
+#define USB2_UHSIC_HSRX_CFG1_0_WORD_COUNT                       0x1
+#define USB2_UHSIC_HSRX_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x882913)
+#define USB2_UHSIC_HSRX_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0xffffff)
+#define USB2_UHSIC_HSRX_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_READ_MASK                        _MK_MASK_CONST(0xffffff)
+#define USB2_UHSIC_HSRX_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
+// Allow Keep Alive packets 
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_ALLOW_KEEP_ALIVE_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_ALLOW_KEEP_ALIVE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_ALLOW_KEEP_ALIVE_SHIFT)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_ALLOW_KEEP_ALIVE_RANGE                  0:0
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_ALLOW_KEEP_ALIVE_WOFFSET                        0x0
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_ALLOW_KEEP_ALIVE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_ALLOW_KEEP_ALIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// How long to wait before start of sync launches RxActive
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_SYNC_START_DLY_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_SYNC_START_DLY_FIELD                    (_MK_MASK_CONST(0x1f) << USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_SYNC_START_DLY_SHIFT)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_SYNC_START_DLY_RANGE                    5:1
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_SYNC_START_DLY_WOFFSET                  0x0
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_SYNC_START_DLY_DEFAULT                  _MK_MASK_CONST(0x9)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_SYNC_START_DLY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_SYNC_START_DLY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_HS_SYNC_START_DLY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Assumes line state filtering table is inclusive, not exclusive
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_EARLY_LINE_STATE_FILTER_SHIFT                      _MK_SHIFT_CONST(6)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_EARLY_LINE_STATE_FILTER_FIELD                      (_MK_MASK_CONST(0x1) << USB2_UHSIC_HSRX_CFG1_0_UHSIC_EARLY_LINE_STATE_FILTER_SHIFT)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_EARLY_LINE_STATE_FILTER_RANGE                      6:6
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_EARLY_LINE_STATE_FILTER_WOFFSET                    0x0
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_EARLY_LINE_STATE_FILTER_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_EARLY_LINE_STATE_FILTER_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_EARLY_LINE_STATE_FILTER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_EARLY_LINE_STATE_FILTER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Bypass LineState reclocking logic
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_BYPASS_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_BYPASS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_BYPASS_SHIFT)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_BYPASS_RANGE                    7:7
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_BYPASS_WOFFSET                  0x0
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_BYPASS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_BYPASS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_BYPASS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_BYPASS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// When enabled, send an SE0 for 2 LS symbols at the end of ResumeK
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_RESUME_FAKE_SE0_SHIFT                   _MK_SHIFT_CONST(8)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_RESUME_FAKE_SE0_FIELD                   (_MK_MASK_CONST(0x1) << USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_RESUME_FAKE_SE0_SHIFT)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_RESUME_FAKE_SE0_RANGE                   8:8
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_RESUME_FAKE_SE0_WOFFSET                 0x0
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_RESUME_FAKE_SE0_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_RESUME_FAKE_SE0_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_RESUME_FAKE_SE0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_LINE_STATE_RESUME_FAKE_SE0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Depth of the 2-bit wide input FIFO. Maximum depth is 20. Can be tuned
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_INPUT_FIFO_DEPTH_SHIFT                     _MK_SHIFT_CONST(9)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_INPUT_FIFO_DEPTH_FIELD                     (_MK_MASK_CONST(0x1f) << USB2_UHSIC_HSRX_CFG1_0_UHSIC_INPUT_FIFO_DEPTH_SHIFT)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_INPUT_FIFO_DEPTH_RANGE                     13:9
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_INPUT_FIFO_DEPTH_WOFFSET                   0x0
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_INPUT_FIFO_DEPTH_DEFAULT                   _MK_MASK_CONST(0x14)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_INPUT_FIFO_DEPTH_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_INPUT_FIFO_DEPTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_INPUT_FIFO_DEPTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Nr of delays cells between UH_RX_STROBE and RxStrobeClk in zero cycle path
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_RX_STROBE_DLY_TRIMMER_SHIFT                        _MK_SHIFT_CONST(14)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_RX_STROBE_DLY_TRIMMER_FIELD                        (_MK_MASK_CONST(0x3f) << USB2_UHSIC_HSRX_CFG1_0_UHSIC_RX_STROBE_DLY_TRIMMER_SHIFT)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_RX_STROBE_DLY_TRIMMER_RANGE                        19:14
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_RX_STROBE_DLY_TRIMMER_WOFFSET                      0x0
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_RX_STROBE_DLY_TRIMMER_DEFAULT                      _MK_MASK_CONST(0x20)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_RX_STROBE_DLY_TRIMMER_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_RX_STROBE_DLY_TRIMMER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_RX_STROBE_DLY_TRIMMER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Controls how long after the end of transmission the receive path is blocked
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_TX_BLOCK_CNT_SHIFT                 _MK_SHIFT_CONST(20)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_TX_BLOCK_CNT_FIELD                 (_MK_MASK_CONST(0xf) << USB2_UHSIC_HSRX_CFG1_0_UHSIC_TX_BLOCK_CNT_SHIFT)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_TX_BLOCK_CNT_RANGE                 23:20
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_TX_BLOCK_CNT_WOFFSET                       0x0
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_TX_BLOCK_CNT_DEFAULT                       _MK_MASK_CONST(0x8)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_TX_BLOCK_CNT_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_TX_BLOCK_CNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_HSRX_CFG1_0_UHSIC_TX_BLOCK_CNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register USB2_UHSIC_TX_CFG0_0  // UHSIC transmit config signals 
+#define USB2_UHSIC_TX_CFG0_0                    _MK_ADDR_CONST(0x810)
+#define USB2_UHSIC_TX_CFG0_0_SECURE                     0x0
+#define USB2_UHSIC_TX_CFG0_0_WORD_COUNT                         0x1
+#define USB2_UHSIC_TX_CFG0_0_RESET_VAL                  _MK_MASK_CONST(0x200)
+#define USB2_UHSIC_TX_CFG0_0_RESET_MASK                         _MK_MASK_CONST(0x3ff)
+#define USB2_UHSIC_TX_CFG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_READ_MASK                  _MK_MASK_CONST(0x3ff)
+#define USB2_UHSIC_TX_CFG0_0_WRITE_MASK                         _MK_MASK_CONST(0x3ff)
+// Do not sent SYNC or EOP
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_SYNC_NO_EOP_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_SYNC_NO_EOP_FIELD                 (_MK_MASK_CONST(0x1) << USB2_UHSIC_TX_CFG0_0_UHSIC_NO_SYNC_NO_EOP_SHIFT)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_SYNC_NO_EOP_RANGE                 0:0
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_SYNC_NO_EOP_WOFFSET                       0x0
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_SYNC_NO_EOP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_SYNC_NO_EOP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_SYNC_NO_EOP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_SYNC_NO_EOP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// No encoding, static programming
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_ENCODING_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_ENCODING_FIELD                    (_MK_MASK_CONST(0x1) << USB2_UHSIC_TX_CFG0_0_UHSIC_NO_ENCODING_SHIFT)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_ENCODING_RANGE                    1:1
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_ENCODING_WOFFSET                  0x0
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_ENCODING_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_ENCODING_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_ENCODING_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_ENCODING_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// No bit stuffing, static programming
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_STUFFING_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_STUFFING_FIELD                    (_MK_MASK_CONST(0x1) << USB2_UHSIC_TX_CFG0_0_UHSIC_NO_STUFFING_SHIFT)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_STUFFING_RANGE                    2:2
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_STUFFING_WOFFSET                  0x0
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_STUFFING_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_STUFFING_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_STUFFING_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_NO_STUFFING_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 2 -- not likely, for Chirp
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_ENCODE_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_ENCODE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_ENCODE_SHIFT)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_ENCODE_RANGE                       3:3
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_ENCODE_WOFFSET                     0x0
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_ENCODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_ENCODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_ENCODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_ENCODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 3 -- perhaps, when sending controller made packets
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_STUFF_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_STUFF_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_STUFF_SHIFT)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_STUFF_RANGE                        4:4
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_STUFF_WOFFSET                      0x0
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_STUFF_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_STUFF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_STUFF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SOF_ON_NO_STUFF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// SIE, not macrocell, detects LineState change to resume
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SIE_RESUME_ON_LINESTATE_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SIE_RESUME_ON_LINESTATE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_TX_CFG0_0_UHSIC_SIE_RESUME_ON_LINESTATE_SHIFT)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SIE_RESUME_ON_LINESTATE_RANGE                        5:5
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SIE_RESUME_ON_LINESTATE_WOFFSET                      0x0
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SIE_RESUME_ON_LINESTATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SIE_RESUME_ON_LINESTATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SIE_RESUME_ON_LINESTATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_SIE_RESUME_ON_LINESTATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// output enable turns off 1 cycle after
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_UHSIC_TX_CFG0_0_UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE_RANGE                     6:6
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                   0x0
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force STROBE low during a regular instead of toggling it
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_FORCE_STROBE_LOW_SHIFT                        _MK_SHIFT_CONST(7)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_FORCE_STROBE_LOW_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_FORCE_STROBE_LOW_SHIFT)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_FORCE_STROBE_LOW_RANGE                        7:7
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_FORCE_STROBE_LOW_WOFFSET                      0x0
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_FORCE_STROBE_LOW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_FORCE_STROBE_LOW_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_FORCE_STROBE_LOW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_FORCE_STROBE_LOW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Invert data during a regular packet
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_INVERT_DATA_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_INVERT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_INVERT_DATA_SHIFT)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_INVERT_DATA_RANGE                     8:8
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_INVERT_DATA_WOFFSET                   0x0
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_INVERT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_INVERT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_INVERT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_PACKET_INVERT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_READY_WAIT_FOR_VALID_SHIFT                        _MK_SHIFT_CONST(9)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_READY_WAIT_FOR_VALID_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_TX_CFG0_0_UHSIC_HS_READY_WAIT_FOR_VALID_SHIFT)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_READY_WAIT_FOR_VALID_RANGE                        9:9
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_READY_WAIT_FOR_VALID_WOFFSET                      0x0
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_READY_WAIT_FOR_VALID_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_READY_WAIT_FOR_VALID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_READY_WAIT_FOR_VALID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_TX_CFG0_0_UHSIC_HS_READY_WAIT_FOR_VALID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_UHSIC_MISC_CFG0_0  // UHSIC miscellaneous configurations
+#define USB2_UHSIC_MISC_CFG0_0                  _MK_ADDR_CONST(0x814)
+#define USB2_UHSIC_MISC_CFG0_0_SECURE                   0x0
+#define USB2_UHSIC_MISC_CFG0_0_WORD_COUNT                       0x1
+#define USB2_UHSIC_MISC_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x44e8e)
+#define USB2_UHSIC_MISC_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x7ffff)
+#define USB2_UHSIC_MISC_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x7ffff)
+#define USB2_UHSIC_MISC_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x7ffff)
+// Use combinational terminations or synced through CLKXTAL           
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_COMB_TERMS_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_COMB_TERMS_FIELD                   (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_COMB_TERMS_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_COMB_TERMS_RANGE                   0:0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_COMB_TERMS_WOFFSET                 0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_COMB_TERMS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_COMB_TERMS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_COMB_TERMS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_COMB_TERMS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Determines if all signal need to be stable to not change a config.
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_ALL_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_ALL_FIELD                   (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_ALL_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_ALL_RANGE                   1:1
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_ALL_WOFFSET                 0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_ALL_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_ALL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_ALL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_ALL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of cycles of crystal clock of signal not changing to consider stable.
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_COUNT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_COUNT_FIELD                 (_MK_MASK_CONST(0x7) << USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_COUNT_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_COUNT_RANGE                 4:2
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_COUNT_WOFFSET                       0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_COUNT_DEFAULT                       _MK_MASK_CONST(0x3)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_STABLE_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force error insertion into RX path. (Used for IOBIST.)       
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_FIELD                    (_MK_MASK_CONST(0x3) << USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_RANGE                    6:5
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_WOFFSET                  0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_BIT_ERR                  _MK_ENUM_CONST(1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_RX_ERR                   _MK_ENUM_CONST(2)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_INJECT_ERROR_TYPE_BIT_RX_ERR                       _MK_ENUM_CONST(3)
+
+// Suspend exit requires edge or simply a value...
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SUSPEND_EXIT_ON_EDGE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SUSPEND_EXIT_ON_EDGE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_SUSPEND_EXIT_ON_EDGE_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SUSPEND_EXIT_ON_EDGE_RANGE                 7:7
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SUSPEND_EXIT_ON_EDGE_WOFFSET                       0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SUSPEND_EXIT_ON_EDGE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SUSPEND_EXIT_ON_EDGE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 0: use 3 edges (negative and positive) to detect a connect state on the line. 1: use 4 edges.
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_CONNECT_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_CONNECT_FIELD                 (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_CONNECT_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_CONNECT_RANGE                 8:8
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_CONNECT_WOFFSET                       0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_CONNECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_CONNECT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_CONNECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_CONNECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// 0: use 3 edges (negative and positive) to detect a idle state on the line. 1: use 4 edges.
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_IDLE_SHIFT                    _MK_SHIFT_CONST(9)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_IDLE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_IDLE_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_IDLE_RANGE                    9:9
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_IDLE_WOFFSET                  0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_IDLE_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_IDLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_IDLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_DETECT_SHORT_IDLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 1: Use TX state to determine starting time to drive bus keeper instead of waiting for IDLE detection.
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_TX_SHIFT                   _MK_SHIFT_CONST(10)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_TX_FIELD                   (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_TX_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_TX_RANGE                   10:10
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_TX_WOFFSET                 0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_TX_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_TX_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_TX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_TX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 1: Use RX state (EOP etc) to determine starting time to drive bus keeper instead of waiting for IDLE detection.
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_RX_SHIFT                   _MK_SHIFT_CONST(11)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_RX_FIELD                   (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_RX_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_RX_RANGE                   11:11
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_RX_WOFFSET                 0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_RX_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_RX_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_RX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ACTIVE_BK_DRIVE_RX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 0: STROBE is 2 periods long during connect. 1: STROBE is 3 periods long during connect
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_LONG_CONNECT_STROBE_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_LONG_CONNECT_STROBE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_LONG_CONNECT_STROBE_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_LONG_CONNECT_STROBE_RANGE                  12:12
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_LONG_CONNECT_STROBE_WOFFSET                        0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_LONG_CONNECT_STROBE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_LONG_CONNECT_STROBE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_LONG_CONNECT_STROBE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_LONG_CONNECT_STROBE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// 0: DATA keeps setup and hold requirements during CONNECT. 1: DATA moves together with STROBE
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ASYNC_CONNECT_DATA_SHIFT                   _MK_SHIFT_CONST(13)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ASYNC_CONNECT_DATA_FIELD                   (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_ASYNC_CONNECT_DATA_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ASYNC_CONNECT_DATA_RANGE                   13:13
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ASYNC_CONNECT_DATA_WOFFSET                 0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ASYNC_CONNECT_DATA_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ASYNC_CONNECT_DATA_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ASYNC_CONNECT_DATA_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_ASYNC_CONNECT_DATA_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 0: DATA goes high before STROBE goes low and low before STROBE goes high. 1: DATA goes high before STROBE goes low and goes low *after* STROBE goes high.
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SYMMETRIC_CONNECT_DATA_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SYMMETRIC_CONNECT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_SYMMETRIC_CONNECT_DATA_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SYMMETRIC_CONNECT_DATA_RANGE                       14:14
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SYMMETRIC_CONNECT_DATA_WOFFSET                     0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SYMMETRIC_CONNECT_DATA_DEFAULT                     _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SYMMETRIC_CONNECT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SYMMETRIC_CONNECT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_SYMMETRIC_CONNECT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 1: Force the values of XcvrSelect via config bits instead of via the controller
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVR_MODE_SHIFT                      _MK_SHIFT_CONST(15)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVR_MODE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVR_MODE_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVR_MODE_RANGE                      15:15
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVR_MODE_WOFFSET                    0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVR_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVR_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVR_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVR_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Value to be forced on XcvrSelect when FORCE_XCVR_MODE is set.
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVRSEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVRSEL_FIELD                        (_MK_MASK_CONST(0x3) << USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVRSEL_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVRSEL_RANGE                        17:16
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVRSEL_WOFFSET                      0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVRSEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVRSEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVRSEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_FORCE_XCVRSEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Drive buskeeper one cycle longer when going out of IDLE
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_EXTEND_BK_ACTIVE_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_EXTEND_BK_ACTIVE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG0_0_UHSIC_EXTEND_BK_ACTIVE_SHIFT)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_EXTEND_BK_ACTIVE_RANGE                     18:18
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_EXTEND_BK_ACTIVE_WOFFSET                   0x0
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_EXTEND_BK_ACTIVE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_EXTEND_BK_ACTIVE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_EXTEND_BK_ACTIVE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG0_0_UHSIC_EXTEND_BK_ACTIVE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_UHSIC_MISC_CFG1_0  // UHSIC miscellaneous configurations
+#define USB2_UHSIC_MISC_CFG1_0                  _MK_ADDR_CONST(0x818)
+#define USB2_UHSIC_MISC_CFG1_0_SECURE                   0x0
+#define USB2_UHSIC_MISC_CFG1_0_WORD_COUNT                       0x1
+#define USB2_UHSIC_MISC_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x21802)
+#define USB2_UHSIC_MISC_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0x3ffff)
+#define USB2_UHSIC_MISC_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG1_0_READ_MASK                        _MK_MASK_CONST(0x3ffff)
+#define USB2_UHSIC_MISC_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0x3ffff)
+// Enable IOBIST RxError counter when not in IOBIST mode. Allows one to read out the number of errors via JTAG during normal operation
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_EN_FIELD                      (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_EN_SHIFT)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_EN_RANGE                      0:0
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_EN_WOFFSET                    0x0
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Clear IOBST RxError counter
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_CLR_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_CLR_FIELD                     (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_CLR_SHIFT)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_CLR_RANGE                     1:1
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_CLR_WOFFSET                   0x0
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_CLR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_CLR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_CLR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_RX_ERROR_CNT_CLR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// WRONG! This should be 1ms -> 0x50
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PLLU_STABLE_COUNT_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PLLU_STABLE_COUNT_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_UHSIC_MISC_CFG1_0_UHSIC_PLLU_STABLE_COUNT_SHIFT)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PLLU_STABLE_COUNT_RANGE                    13:2
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PLLU_STABLE_COUNT_WOFFSET                  0x0
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PLLU_STABLE_COUNT_DEFAULT                  _MK_MASK_CONST(0x600)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PLLU_STABLE_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PLLU_STABLE_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PLLU_STABLE_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Always enable IoBist CLK60. This would be required when you want to use RX_ERROR_CNT_EN.
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_FORCE_IOBIST_CLK_ON_SHIFT                  _MK_SHIFT_CONST(14)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_FORCE_IOBIST_CLK_ON_FIELD                  (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG1_0_UHSIC_FORCE_IOBIST_CLK_ON_SHIFT)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_FORCE_IOBIST_CLK_ON_RANGE                  14:14
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_FORCE_IOBIST_CLK_ON_WOFFSET                        0x0
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_FORCE_IOBIST_CLK_ON_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_FORCE_IOBIST_CLK_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_FORCE_IOBIST_CLK_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_FORCE_IOBIST_CLK_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Select which one of 4 observation vectors is presented on the observation bus
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_OBS_SEL_SHIFT                      _MK_SHIFT_CONST(15)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_OBS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << USB2_UHSIC_MISC_CFG1_0_UHSIC_OBS_SEL_SHIFT)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_OBS_SEL_RANGE                      16:15
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_OBS_SEL_WOFFSET                    0x0
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_OBS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_OBS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_OBS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_OBS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Selects whether to enable the crystal clock in the module.
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PHY_XTAL_CLOCKEN_SHIFT                     _MK_SHIFT_CONST(17)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PHY_XTAL_CLOCKEN_FIELD                     (_MK_MASK_CONST(0x1) << USB2_UHSIC_MISC_CFG1_0_UHSIC_PHY_XTAL_CLOCKEN_SHIFT)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PHY_XTAL_CLOCKEN_RANGE                     17:17
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PHY_XTAL_CLOCKEN_WOFFSET                   0x0
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PHY_XTAL_CLOCKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PHY_XTAL_CLOCKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PHY_XTAL_CLOCKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_MISC_CFG1_0_UHSIC_PHY_XTAL_CLOCKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_UHSIC_PADS_CFG0_0  // Uhsic Pads settings
+#define USB2_UHSIC_PADS_CFG0_0                  _MK_ADDR_CONST(0x81c)
+#define USB2_UHSIC_PADS_CFG0_0_SECURE                   0x0
+#define USB2_UHSIC_PADS_CFG0_0_WORD_COUNT                       0x1
+#define USB2_UHSIC_PADS_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x888888)
+#define USB2_UHSIC_PADS_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_UHSIC_PADS_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_UHSIC_PADS_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// Output impedance adjustment for PMOS driver
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMP_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMP_FIELD                    (_MK_MASK_CONST(0xf) << USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMP_SHIFT)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMP_RANGE                    3:0
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMP_WOFFSET                  0x0
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMP_DEFAULT                  _MK_MASK_CONST(0x8)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMP_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Output impedance adjustment for NMOS driver
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMN_SHIFT                    _MK_SHIFT_CONST(4)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMN_FIELD                    (_MK_MASK_CONST(0xf) << USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMN_SHIFT)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMN_RANGE                    7:4
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMN_WOFFSET                  0x0
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMN_DEFAULT                  _MK_MASK_CONST(0x8)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTERMN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Fine tuned 50 Ohm termination resistor for PMOS driver
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEP_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEP_FIELD                    (_MK_MASK_CONST(0xf) << USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEP_SHIFT)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEP_RANGE                    11:8
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEP_WOFFSET                  0x0
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEP_DEFAULT                  _MK_MASK_CONST(0x8)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEP_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Fine tuned 50 Ohm termination resistor for NMOS driver
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEN_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEN_FIELD                    (_MK_MASK_CONST(0xf) << USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEN_SHIFT)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEN_RANGE                    15:12
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEN_WOFFSET                  0x0
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEN_DEFAULT                  _MK_MASK_CONST(0x8)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEN_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_RTUNEN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Output slew rate (rise time) adjustment
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWP_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWP_FIELD                     (_MK_MASK_CONST(0xf) << USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWP_SHIFT)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWP_RANGE                     19:16
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWP_WOFFSET                   0x0
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWP_DEFAULT                   _MK_MASK_CONST(0x8)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWP_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Output slew rate (fall time) adjustment
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWN_SHIFT                     _MK_SHIFT_CONST(20)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWN_FIELD                     (_MK_MASK_CONST(0xf) << USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWN_SHIFT)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWN_RANGE                     23:20
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWN_WOFFSET                   0x0
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWN_DEFAULT                   _MK_MASK_CONST(0x8)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWN_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_TX_SLEWN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Spare config bits
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_HSIC_OPT_SHIFT                     _MK_SHIFT_CONST(24)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_HSIC_OPT_FIELD                     (_MK_MASK_CONST(0xff) << USB2_UHSIC_PADS_CFG0_0_UHSIC_HSIC_OPT_SHIFT)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_HSIC_OPT_RANGE                     31:24
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_HSIC_OPT_WOFFSET                   0x0
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_HSIC_OPT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_HSIC_OPT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_HSIC_OPT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG0_0_UHSIC_HSIC_OPT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_UHSIC_PADS_CFG1_0  // Uhsic Pads settings
+#define USB2_UHSIC_PADS_CFG1_0                  _MK_ADDR_CONST(0x820)
+#define USB2_UHSIC_PADS_CFG1_0_SECURE                   0x0
+#define USB2_UHSIC_PADS_CFG1_0_WORD_COUNT                       0x1
+#define USB2_UHSIC_PADS_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x67d)
+#define USB2_UHSIC_PADS_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0x1fff)
+#define USB2_UHSIC_PADS_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_READ_MASK                        _MK_MASK_CONST(0x1fff)
+#define USB2_UHSIC_PADS_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0x1fff)
+// Enable auto-termination
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_AUTO_RTERM_EN_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_AUTO_RTERM_EN_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_AUTO_RTERM_EN_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_AUTO_RTERM_EN_RANGE                        0:0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_AUTO_RTERM_EN_WOFFSET                      0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_AUTO_RTERM_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_AUTO_RTERM_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_AUTO_RTERM_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_AUTO_RTERM_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Shut down analog blocks for IDDQ testing
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_IDDQ_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_IDDQ_FIELD                 (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_IDDQ_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_IDDQ_RANGE                 1:1
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_IDDQ_WOFFSET                       0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_IDDQ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_IDDQ_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_IDDQ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_IDDQ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Power down band-gap and bias generator
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_BG_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_BG_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_BG_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_BG_RANGE                        2:2
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_BG_WOFFSET                      0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_BG_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_BG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_BG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_BG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Power down transmitter
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TX_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TX_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TX_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TX_RANGE                        3:3
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TX_WOFFSET                      0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TX_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Power down tracking circuit
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TRK_SHIFT                       _MK_SHIFT_CONST(4)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TRK_FIELD                       (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TRK_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TRK_RANGE                       4:4
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TRK_WOFFSET                     0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TRK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TRK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TRK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_TRK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Power down receiver
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_RX_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_RX_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_RX_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_RX_RANGE                        5:5
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_RX_WOFFSET                      0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_RX_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_RX_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_RX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_RX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Power down single ended receiver
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_ZI_SHIFT                        _MK_SHIFT_CONST(6)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_ZI_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_ZI_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_ZI_RANGE                        6:6
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_ZI_WOFFSET                      0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_ZI_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_ZI_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_ZI_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_PD_ZI_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 0: differential read buffers, 1: single-ended buffers
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RX_SEL_SHIFT                       _MK_SHIFT_CONST(7)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RX_SEL_FIELD                       (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_RX_SEL_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RX_SEL_RANGE                       7:7
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RX_SEL_WOFFSET                     0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RX_SEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RX_SEL_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RX_SEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RX_SEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Internal digital loopback
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_LPBK_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_LPBK_FIELD                 (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_LPBK_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_LPBK_RANGE                 8:8
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_LPBK_WOFFSET                       0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_LPBK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_LPBK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_LPBK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_LPBK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Enable pull down on IO_DATA
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_DATA_SHIFT                     _MK_SHIFT_CONST(9)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_DATA_FIELD                     (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_DATA_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_DATA_RANGE                     9:9
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_DATA_WOFFSET                   0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_DATA_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Enable pull down on IO_STROBE
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_STROBE_SHIFT                   _MK_SHIFT_CONST(10)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_STROBE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_STROBE_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_STROBE_RANGE                   10:10
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_STROBE_WOFFSET                 0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_STROBE_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_STROBE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_STROBE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPD_STROBE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Enable pull up on IO_DATA
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_DATA_SHIFT                     _MK_SHIFT_CONST(11)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_DATA_FIELD                     (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_DATA_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_DATA_RANGE                     11:11
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_DATA_WOFFSET                   0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Enable pull up on IO_STROBE
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_STROBE_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_STROBE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_STROBE_SHIFT)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_STROBE_RANGE                   12:12
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_STROBE_WOFFSET                 0x0
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_STROBE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_STROBE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_STROBE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_PADS_CFG1_0_UHSIC_RPU_STROBE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_UHSIC_CMD_CFG0_0  
+#define USB2_UHSIC_CMD_CFG0_0                   _MK_ADDR_CONST(0x824)
+#define USB2_UHSIC_CMD_CFG0_0_SECURE                    0x0
+#define USB2_UHSIC_CMD_CFG0_0_WORD_COUNT                        0x1
+#define USB2_UHSIC_CMD_CFG0_0_RESET_VAL                         _MK_MASK_CONST(0x5)
+#define USB2_UHSIC_CMD_CFG0_0_RESET_MASK                        _MK_MASK_CONST(0x3f)
+#define USB2_UHSIC_CMD_CFG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_READ_MASK                         _MK_MASK_CONST(0x3f)
+#define USB2_UHSIC_CMD_CFG0_0_WRITE_MASK                        _MK_MASK_CONST(0x3f)
+// Upon power up, automatically move to activation mode and 
+// start going through connect procedure.
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_ACTIVATE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_ACTIVATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_ACTIVATE_SHIFT)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_ACTIVATE_RANGE                 0:0
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_ACTIVATE_WOFFSET                       0x0
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_ACTIVATE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_ACTIVATE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_ACTIVATE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_ACTIVATE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Upon rising value of this bit, instruct state machine to go into activation mode. 
+// Only useful when AUTO_ACTIVATE is disabled.
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_ACTIVATE_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_ACTIVATE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_ACTIVATE_SHIFT)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_ACTIVATE_RANGE                        1:1
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_ACTIVATE_WOFFSET                      0x0
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_ACTIVATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_ACTIVATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_ACTIVATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_ACTIVATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// As device, automatically send Connect during activation. 
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_CONNECT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_CONNECT_FIELD                  (_MK_MASK_CONST(0x1) << USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_CONNECT_SHIFT)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_CONNECT_RANGE                  2:2
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_CONNECT_WOFFSET                        0x0
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_CONNECT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_CONNECT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_CONNECT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_AUTO_CONNECT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Upon rising value of this bit, force device to send connect. Only useful when
+// AUTO_CONNECT is disabled.
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_CONNECT_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_CONNECT_FIELD                 (_MK_MASK_CONST(0x1) << USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_CONNECT_SHIFT)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_CONNECT_RANGE                 3:3
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_CONNECT_WOFFSET                       0x0
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_CONNECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_CONNECT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_CONNECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_CONNECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_RESET_SHIFT                   _MK_SHIFT_CONST(4)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_RESET_FIELD                   (_MK_MASK_CONST(0x1) << USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_RESET_SHIFT)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_RESET_RANGE                   4:4
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_RESET_WOFFSET                 0x0
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_RESET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_RESET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_RESET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_FORCE_RESET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_PRETEND_CONNECT_DETECT_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_PRETEND_CONNECT_DETECT_FIELD                        (_MK_MASK_CONST(0x1) << USB2_UHSIC_CMD_CFG0_0_UHSIC_PRETEND_CONNECT_DETECT_SHIFT)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_PRETEND_CONNECT_DETECT_RANGE                        5:5
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_PRETEND_CONNECT_DETECT_WOFFSET                      0x0
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_PRETEND_CONNECT_DETECT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_PRETEND_CONNECT_DETECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_PRETEND_CONNECT_DETECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_CMD_CFG0_0_UHSIC_PRETEND_CONNECT_DETECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_UHSIC_STAT_CFG0_0  
+#define USB2_UHSIC_STAT_CFG0_0                  _MK_ADDR_CONST(0x828)
+#define USB2_UHSIC_STAT_CFG0_0_SECURE                   0x0
+#define USB2_UHSIC_STAT_CFG0_0_WORD_COUNT                       0x1
+#define USB2_UHSIC_STAT_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_STAT_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffff07)
+#define USB2_UHSIC_STAT_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CONNECT_DETECT_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CONNECT_DETECT_FIELD                       (_MK_MASK_CONST(0x1) << USB2_UHSIC_STAT_CFG0_0_UHSIC_CONNECT_DETECT_SHIFT)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CONNECT_DETECT_RANGE                       0:0
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CONNECT_DETECT_WOFFSET                     0x0
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CONNECT_DETECT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CONNECT_DETECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CONNECT_DETECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CONNECT_DETECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_BUS_STATE_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_BUS_STATE_FIELD                    (_MK_MASK_CONST(0x3) << USB2_UHSIC_STAT_CFG0_0_UHSIC_BUS_STATE_SHIFT)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_BUS_STATE_RANGE                    2:1
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_BUS_STATE_WOFFSET                  0x0
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_BUS_STATE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_BUS_STATE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_BUS_STATE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_BUS_STATE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_SPARE_STATUS_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_SPARE_STATUS_FIELD                 (_MK_MASK_CONST(0xff) << USB2_UHSIC_STAT_CFG0_0_UHSIC_SPARE_STATUS_SHIFT)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_SPARE_STATUS_RANGE                 15:8
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_SPARE_STATUS_WOFFSET                       0x0
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_SPARE_STATUS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_SPARE_STATUS_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_SPARE_STATUS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_SPARE_STATUS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CALIOUT_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CALIOUT_FIELD                      (_MK_MASK_CONST(0xffff) << USB2_UHSIC_STAT_CFG0_0_UHSIC_CALIOUT_SHIFT)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CALIOUT_RANGE                      31:16
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CALIOUT_WOFFSET                    0x0
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CALIOUT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CALIOUT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CALIOUT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_STAT_CFG0_0_UHSIC_CALIOUT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_UHSIC_SPARE_CFG0_0  // Utmip spare configurations, spare configuration bits 
+#define USB2_UHSIC_SPARE_CFG0_0                 _MK_ADDR_CONST(0x82c)
+#define USB2_UHSIC_SPARE_CFG0_0_SECURE                  0x0
+#define USB2_UHSIC_SPARE_CFG0_0_WORD_COUNT                      0x1
+#define USB2_UHSIC_SPARE_CFG0_0_RESET_VAL                       _MK_MASK_CONST(0xffff0000)
+#define USB2_UHSIC_SPARE_CFG0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_UHSIC_SPARE_CFG0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_SPARE_CFG0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_SPARE_CFG0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_UHSIC_SPARE_CFG0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Bit 0    : HS_RX_IPG_ERROR_ENABLE
+// Bit 1    : HS_RX_FLUSH_ALAP
+// Bit 2    : FORCE_TRIM_ZERO           
+// Bit 7 :4 : RX_DATA_TRIM[3:0]         
+// Bit 11:8 : RX_STROBE_TRIM[3:0]
+// Bit 12   : FORCE_BK_ON
+// Bit 13   : BYPASS_INIT_BLOCK
+// bit 14   : FORCE_SM_IDLE
+#define USB2_UHSIC_SPARE_CFG0_0_UHSIC_SPARE_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_UHSIC_SPARE_CFG0_0_UHSIC_SPARE_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_UHSIC_SPARE_CFG0_0_UHSIC_SPARE_SHIFT)
+#define USB2_UHSIC_SPARE_CFG0_0_UHSIC_SPARE_RANGE                       31:0
+#define USB2_UHSIC_SPARE_CFG0_0_UHSIC_SPARE_WOFFSET                     0x0
+#define USB2_UHSIC_SPARE_CFG0_0_UHSIC_SPARE_DEFAULT                     _MK_MASK_CONST(0xffff0000)
+#define USB2_UHSIC_SPARE_CFG0_0_UHSIC_SPARE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_UHSIC_SPARE_CFG0_0_UHSIC_SPARE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_SPARE_CFG0_0_UHSIC_SPARE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_UHSIC_SPARE_CFG0_0_UHSIC_SPARE_INIT_ENUM                   -65536
+
+
+// Register USB2_QH_USB2D_QH_EP_0_OUT_0  
+#define USB2_QH_USB2D_QH_EP_0_OUT_0                     _MK_ADDR_CONST(0x1000)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 0 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 0.
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_0_IN_0  
+#define USB2_QH_USB2D_QH_EP_0_IN_0                      _MK_ADDR_CONST(0x1040)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_0_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_0_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 0. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 0.
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_1_OUT_0  
+#define USB2_QH_USB2D_QH_EP_1_OUT_0                     _MK_ADDR_CONST(0x1080)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 1 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 1.
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_1_IN_0  
+#define USB2_QH_USB2D_QH_EP_1_IN_0                      _MK_ADDR_CONST(0x10c0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_1_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_1_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 1. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 1.
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_2_OUT_0  
+#define USB2_QH_USB2D_QH_EP_2_OUT_0                     _MK_ADDR_CONST(0x1100)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 2 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 2.
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_2_IN_0  
+#define USB2_QH_USB2D_QH_EP_2_IN_0                      _MK_ADDR_CONST(0x1140)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_2_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_2_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 2. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 2.
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_3_OUT_0  
+#define USB2_QH_USB2D_QH_EP_3_OUT_0                     _MK_ADDR_CONST(0x1180)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 3 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 3.
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_3_IN_0  
+#define USB2_QH_USB2D_QH_EP_3_IN_0                      _MK_ADDR_CONST(0x11c0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_3_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_3_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 3. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 3.
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_4_OUT_0  
+#define USB2_QH_USB2D_QH_EP_4_OUT_0                     _MK_ADDR_CONST(0x1200)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 4 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 4.
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_4_IN_0  
+#define USB2_QH_USB2D_QH_EP_4_IN_0                      _MK_ADDR_CONST(0x1240)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_4_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_4_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 4. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 4.
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_5_OUT_0  
+#define USB2_QH_USB2D_QH_EP_5_OUT_0                     _MK_ADDR_CONST(0x1280)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 5 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 5.
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_5_IN_0  
+#define USB2_QH_USB2D_QH_EP_5_IN_0                      _MK_ADDR_CONST(0x12c0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_5_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_5_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 5. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 5.
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_6_OUT_0  
+#define USB2_QH_USB2D_QH_EP_6_OUT_0                     _MK_ADDR_CONST(0x1300)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 6 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 6.
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_6_IN_0  
+#define USB2_QH_USB2D_QH_EP_6_IN_0                      _MK_ADDR_CONST(0x1340)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_6_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_6_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 6. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 6.
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_7_OUT_0  
+#define USB2_QH_USB2D_QH_EP_7_OUT_0                     _MK_ADDR_CONST(0x1380)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 7 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 7.
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_7_IN_0  
+#define USB2_QH_USB2D_QH_EP_7_IN_0                      _MK_ADDR_CONST(0x13c0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_7_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_7_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 7. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 7.
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_8_OUT_0  
+#define USB2_QH_USB2D_QH_EP_8_OUT_0                     _MK_ADDR_CONST(0x1400)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 8 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 8.
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_8_IN_0  
+#define USB2_QH_USB2D_QH_EP_8_IN_0                      _MK_ADDR_CONST(0x1440)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_8_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_8_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 8. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 8.
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_9_OUT_0  
+#define USB2_QH_USB2D_QH_EP_9_OUT_0                     _MK_ADDR_CONST(0x1480)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 9 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 9.
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_9_IN_0  
+#define USB2_QH_USB2D_QH_EP_9_IN_0                      _MK_ADDR_CONST(0x14c0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_9_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_9_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 9. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 9.
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_10_OUT_0  
+#define USB2_QH_USB2D_QH_EP_10_OUT_0                    _MK_ADDR_CONST(0x1500)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 10 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 10.
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_10_IN_0  
+#define USB2_QH_USB2D_QH_EP_10_IN_0                     _MK_ADDR_CONST(0x1540)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_10_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_10_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 10. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 10.
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_11_OUT_0  
+#define USB2_QH_USB2D_QH_EP_11_OUT_0                    _MK_ADDR_CONST(0x1580)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 11 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 11.
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_11_IN_0  
+#define USB2_QH_USB2D_QH_EP_11_IN_0                     _MK_ADDR_CONST(0x15c0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_11_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_11_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 11. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 11.
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_12_OUT_0  
+#define USB2_QH_USB2D_QH_EP_12_OUT_0                    _MK_ADDR_CONST(0x1600)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 12 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 12.
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_12_IN_0  
+#define USB2_QH_USB2D_QH_EP_12_IN_0                     _MK_ADDR_CONST(0x1640)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_12_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_12_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 12. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 12.
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_13_OUT_0  
+#define USB2_QH_USB2D_QH_EP_13_OUT_0                    _MK_ADDR_CONST(0x1680)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 13 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 13.
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_13_IN_0  
+#define USB2_QH_USB2D_QH_EP_13_IN_0                     _MK_ADDR_CONST(0x16c0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_13_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_13_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 13. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 13.
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_14_OUT_0  
+#define USB2_QH_USB2D_QH_EP_14_OUT_0                    _MK_ADDR_CONST(0x1700)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 14 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 14.
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_14_IN_0  
+#define USB2_QH_USB2D_QH_EP_14_IN_0                     _MK_ADDR_CONST(0x1740)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_14_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_14_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 14. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 14.
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_15_OUT_0  
+#define USB2_QH_USB2D_QH_EP_15_OUT_0                    _MK_ADDR_CONST(0x1780)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 15 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 15.
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_15_IN_0  
+#define USB2_QH_USB2D_QH_EP_15_IN_0                     _MK_ADDR_CONST(0x17c0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_15_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_15_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 15. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 15.
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_RX_MEM_USB2_RX_MEM_0  
+#define USB2_RX_MEM_USB2_RX_MEM_0                       _MK_ADDR_CONST(0x1800)
+#define USB2_RX_MEM_USB2_RX_MEM_0_SECURE                        0x0
+#define USB2_RX_MEM_USB2_RX_MEM_0_WORD_COUNT                    0x1
+#define USB2_RX_MEM_USB2_RX_MEM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB2_RX_MEM_USB2_RX_MEM_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// RX buffer memory
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SHIFT)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_RANGE                     31:0
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_WOFFSET                   0x0
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_RX_MEM_USB2_RX_MEM  
+#define USB2_RX_MEM_USB2_RX_MEM                 _MK_ADDR_CONST(0x1800)
+#define USB2_RX_MEM_USB2_RX_MEM_SECURE                  0x0
+#define USB2_RX_MEM_USB2_RX_MEM_WORD_COUNT                      0x1
+#define USB2_RX_MEM_USB2_RX_MEM_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_RX_MEM_USB2_RX_MEM_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// RX buffer memory
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SHIFT)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_RANGE                       31:0
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_WOFFSET                     0x0
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_TX_MEM_USB2_TX_MEM_0  
+#define USB2_TX_MEM_USB2_TX_MEM_0                       _MK_ADDR_CONST(0x2000)
+#define USB2_TX_MEM_USB2_TX_MEM_0_SECURE                        0x0
+#define USB2_TX_MEM_USB2_TX_MEM_0_WORD_COUNT                    0x1
+#define USB2_TX_MEM_USB2_TX_MEM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB2_TX_MEM_USB2_TX_MEM_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// TX buffer memory
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SHIFT)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_RANGE                     31:0
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_WOFFSET                   0x0
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_TX_MEM_USB2_TX_MEM  
+#define USB2_TX_MEM_USB2_TX_MEM                 _MK_ADDR_CONST(0x2000)
+#define USB2_TX_MEM_USB2_TX_MEM_SECURE                  0x0
+#define USB2_TX_MEM_USB2_TX_MEM_WORD_COUNT                      0x1
+#define USB2_TX_MEM_USB2_TX_MEM_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_TX_MEM_USB2_TX_MEM_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// TX buffer memory
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SHIFT)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_RANGE                       31:0
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_WOFFSET                     0x0
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ID_0  
+#define USB2_CONTROLLER_2_USB2D_ID_0                    _MK_ADDR_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ID_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ID_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ID_0_RESET_VAL                  _MK_MASK_CONST(0x33fa05)
+#define USB2_CONTROLLER_2_USB2D_ID_0_RESET_MASK                         _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_2_USB2D_ID_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ID_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ID_0_READ_MASK                  _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_2_USB2D_ID_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Revision number of the USB controller. This is set  to 0x33.
+#define USB2_CONTROLLER_2_USB2D_ID_0_REVISION_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ID_0_REVISION_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_ID_0_REVISION_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ID_0_REVISION_RANGE                     23:16
+#define USB2_CONTROLLER_2_USB2D_ID_0_REVISION_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ID_0_REVISION_DEFAULT                   _MK_MASK_CONST(0x33)
+#define USB2_CONTROLLER_2_USB2D_ID_0_REVISION_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_ID_0_REVISION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ID_0_REVISION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Ones complement version of ID. This field is set  to 0xFA.
+#define USB2_CONTROLLER_2_USB2D_ID_0_NID_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_ID_0_NID_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_ID_0_NID_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ID_0_NID_RANGE                  15:8
+#define USB2_CONTROLLER_2_USB2D_ID_0_NID_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ID_0_NID_DEFAULT                        _MK_MASK_CONST(0xfa)
+#define USB2_CONTROLLER_2_USB2D_ID_0_NID_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_ID_0_NID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ID_0_NID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Configuration number. This field is set to 0x05
+#define USB2_CONTROLLER_2_USB2D_ID_0_ID_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ID_0_ID_FIELD                   (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_ID_0_ID_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ID_0_ID_RANGE                   7:0
+#define USB2_CONTROLLER_2_USB2D_ID_0_ID_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_ID_0_ID_DEFAULT                 _MK_MASK_CONST(0x5)
+#define USB2_CONTROLLER_2_USB2D_ID_0_ID_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_ID_0_ID_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ID_0_ID_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_HW_GENERAL_0  
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0                    _MK_ADDR_CONST(0x4)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_RESET_VAL                  _MK_MASK_CONST(0x35)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_RESET_MASK                         _MK_MASK_CONST(0x1f7)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_READ_MASK                  _MK_MASK_CONST(0x1f7)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// VUSB_HS_PHY_MODE : set to 0 for UTMI PHY
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYM_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYM_FIELD                 (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYM_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYM_RANGE                 8:6
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYM_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYM_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYM_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYM_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYM_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// VUSB_HS_PHY16_8 : Width of the UTMI parallel  interface. Set to 3 : 16-bit UTMI parallel interface software programmable to  8-bit
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYW_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYW_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYW_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYW_RANGE                 5:4
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYW_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYW_DEFAULT                       _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYW_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_PHYW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// VUSB_HS_CLOCK_CONFIGURATION : Clock configuration  2 selected
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_CLKC_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_CLKC_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_CLKC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_CLKC_RANGE                 2:1
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_CLKC_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_CLKC_DEFAULT                       _MK_MASK_CONST(0x2)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_CLKC_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_CLKC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_CLKC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// VUSB_HS_RESET_TYPE : set to 1 = asynchronous reset
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_RT_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_RT_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_RT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_RT_RANGE                   0:0
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_RT_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_RT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_RT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_RT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_GENERAL_0_RT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_HW_HOST_0  
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0                       _MK_ADDR_CONST(0x8)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_SECURE                        0x0
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_RESET_VAL                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_RESET_MASK                    _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_READ_MASK                     _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// VUSB_HS_NUM_PORT-1: This host controller has only  1 port. So this field will always be 0.
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_NPORT_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_NPORT_FIELD                   (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_2_USB2D_HW_HOST_0_NPORT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_NPORT_RANGE                   3:1
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_NPORT_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_NPORT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_NPORT_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_NPORT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_NPORT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// VUSB_HS_HOST: Indicates support for host mode. Set  to 1.
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_HC_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_HC_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_HW_HOST_0_HC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_HC_RANGE                      0:0
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_HC_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_HC_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_HC_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_HC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_HOST_0_HC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_HW_DEVICE_0  
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0                     _MK_ADDR_CONST(0xc)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_SECURE                      0x0
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_RESET_VAL                   _MK_MASK_CONST(0x21)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_RESET_MASK                  _MK_MASK_CONST(0x3f)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_READ_MASK                   _MK_MASK_CONST(0x3f)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// VUSB_HS_DV_EP: No. of endpoints supported by this device controller. Set to 16. This includes control endpoint 0.
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DEVEP_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DEVEP_FIELD                 (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DEVEP_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DEVEP_RANGE                 5:1
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DEVEP_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DEVEP_DEFAULT                       _MK_MASK_CONST(0x10)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DEVEP_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DEVEP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DEVEP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Device capable: Set to 1 indicating support for device mode.
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DC_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DC_RANGE                    0:0
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DC_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DC_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_DEVICE_0_DC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_HW_TXBUF_0  
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0                      _MK_ADDR_CONST(0x10)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_SECURE                       0x0
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_RESET_VAL                    _MK_MASK_CONST(0x70b08)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_RESET_MASK                   _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_READ_MASK                    _MK_MASK_CONST(0xffffff)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// VUSB_HS_TX_CHAN_ADD: Total no. of address bits for the transmit buffer of each transmit endpoint. Set to 7. Each transmit buffer is 128 words deep.
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXCHANADD_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXCHANADD_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXCHANADD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXCHANADD_RANGE                      23:16
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXCHANADD_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXCHANADD_DEFAULT                    _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXCHANADD_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXCHANADD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXCHANADD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VUSB_HS_TX_ADD: Total no. of address bits for the transmit buffer. Set to 11. The total depth of the transmit buffer is 2048 words.
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXADD_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXADD_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXADD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXADD_RANGE                  15:8
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXADD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXADD_DEFAULT                        _MK_MASK_CONST(0xb)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXADD_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXADD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TXADD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// VUSB_HS_TX_BURST: Maximum burst size supported by the transmit endpoints for data transfers. Set to 8.
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TCBURST_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TCBURST_FIELD                        (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TCBURST_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TCBURST_RANGE                        7:0
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TCBURST_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TCBURST_DEFAULT                      _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TCBURST_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TCBURST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_TXBUF_0_TCBURST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_HW_RXBUF_0  
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0                      _MK_ADDR_CONST(0x14)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_SECURE                       0x0
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RESET_VAL                    _MK_MASK_CONST(0x708)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RESET_MASK                   _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_READ_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_WRITE_MASK                   _MK_MASK_CONST(0x0)
+// VUSB_HS_RX_ADD: Total no. of address bits for the receive buffer. Set to 7. The total depth of the receive buffer is 128 words
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXADD_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXADD_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXADD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXADD_RANGE                  15:8
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXADD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXADD_DEFAULT                        _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXADD_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXADD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXADD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// VUSB_HS_RX_BURST: Maximum burst size supported by the receive endpoints for data transfers. Set to 8.
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXBURST_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXBURST_FIELD                        (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXBURST_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXBURST_RANGE                        7:0
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXBURST_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXBURST_DEFAULT                      _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXBURST_DEFAULT_MASK                 _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXBURST_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HW_RXBUF_0_RXBURST_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_CAPLENGTH_0  
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0                     _MK_ADDR_CONST(0x100)
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_SECURE                      0x0
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_RESET_VAL                   _MK_MASK_CONST(0x40)
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_RESET_MASK                  _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_READ_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Indicates which offset to add to the register base address at the beginning of the Operational Register. Set to 0x40.
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_CAPLENGTH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_CAPLENGTH_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_CAPLENGTH_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_CAPLENGTH_RANGE                     7:0
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_CAPLENGTH_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_CAPLENGTH_DEFAULT                   _MK_MASK_CONST(0x40)
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_CAPLENGTH_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_CAPLENGTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_CAPLENGTH_0_CAPLENGTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_HCIVERSON_0  
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0                     _MK_ADDR_CONST(0x102)
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_SECURE                      0x0
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_RESET_VAL                   _MK_MASK_CONST(0x100)
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_READ_MASK                   _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Contains a BCD encoding of the EHCI revision number supported by this host controller. The most significant byte of this register represents a major revision and the least significant byte is the minor revision. This host controller supports EHCI revision 1.00.
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_HCIVERSION_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_HCIVERSION_FIELD                    (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_2_USB2D_HCIVERSON_0_HCIVERSION_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_HCIVERSION_RANGE                    15:0
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_HCIVERSION_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_HCIVERSION_DEFAULT                  _MK_MASK_CONST(0x100)
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_HCIVERSION_DEFAULT_MASK                     _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_HCIVERSION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCIVERSON_0_HCIVERSION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_HCSPARAMS_0  
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0                     _MK_ADDR_CONST(0x104)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_SECURE                      0x0
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_RESET_VAL                   _MK_MASK_CONST(0x1100011)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_RESET_MASK                  _MK_MASK_CONST(0xff0ff1f)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_READ_MASK                   _MK_MASK_CONST(0xff0ff1f)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Number of Transaction Translators: indicates the number of embedded transaction translators associated with the USB2.0 host controller. This field is always set to 1 indicating only 1 embedded TT is implemented in this implementation. This is a non-EHCI field to support embedded TT.
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_TT_SHIFT                  _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_TT_FIELD                  (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_TT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_TT_RANGE                  27:24
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_TT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_TT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_TT_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_TT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_TT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Number of Ports per Transaction Translator: indicates the number of ports assigned to each transaction translator within the USB2.0 host controller. Field always equals N_PORTS. This is a non-EHCI field to support embedded TT.
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PTT_SHIFT                 _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PTT_FIELD                 (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PTT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PTT_RANGE                 23:20
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PTT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PTT_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PTT_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PTT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PTT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Number of Companion Controller: indicates the number of companion controllers. This field is set to 0.
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_CC_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_CC_FIELD                  (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_CC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_CC_RANGE                  15:12
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_CC_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_CC_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_CC_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_CC_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_CC_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Number of Ports per Companion Controller: indicates the number of ports supported per internal companion controller. This field is set to 0.
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PCC_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PCC_FIELD                 (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PCC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PCC_RANGE                 11:8
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PCC_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PCC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PCC_DEFAULT_MASK                  _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PCC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PCC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Port Power Control: indicates whether the host controller implementation includes port power control. 
+// 1 = Ports have port power switches         0= Ports do not have port power switches.
+// This field affects the functionality of the port Power field in each port status and control register. This field is set to 1.
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_PPC_SHIFT                   _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_PPC_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_PPC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_PPC_RANGE                   4:4
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_PPC_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_PPC_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_PPC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_PPC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_PPC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of downstream ports. This field specifies the number of physical downstream ports implemented on this host controller. This field is fixed to 1, since this host controller only supports 1 port.
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PORTS_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PORTS_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PORTS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PORTS_RANGE                       3:0
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PORTS_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PORTS_DEFAULT                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PORTS_DEFAULT_MASK                        _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PORTS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCSPARAMS_0_N_PORTS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_HCCPARAMS_0  
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0                     _MK_ADDR_CONST(0x108)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_SECURE                      0x0
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_RESET_VAL                   _MK_MASK_CONST(0x6)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_RESET_MASK                  _MK_MASK_CONST(0xfff6)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_READ_MASK                   _MK_MASK_CONST(0xfff6)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// EHCI Extended Capabilities Pointer: indicates a capabilities list exists. A value of 00h indicates no extended capabilities are implemented. For this implementation this field is always "0". 
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_EECP_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_EECP_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_EECP_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_EECP_RANGE                  15:8
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_EECP_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_EECP_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_EECP_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_EECP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_EECP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit [7] is zero, the value of the least significant 3 bits indicates the number of micro-frames a host controller can hold a set of isochronous data structures  (one or more) before flushing the state. When bit [7] is a one, then host software assumes the host controller may cache an isochronous data structure for an entire frame. This field will always be "0". 
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_IST_SHIFT                   _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_IST_FIELD                   (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_IST_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_IST_RANGE                   7:4
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_IST_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_IST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_IST_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_IST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_IST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Asynchronous Schedule Park Capability. 
+// 1 = (Default) the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the USBCMD register. 
+// This field is always 1.
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_ASP_SHIFT                   _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_ASP_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_ASP_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_ASP_RANGE                   2:2
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_ASP_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_ASP_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_ASP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_ASP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_ASP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Programmable Frame List Flag. 
+// 0 = System software must use a frame list length of 1024 elements with this host controller. The USBCMD register Frame List Size field is a read-only register and must be set to zero. 
+// 1 = System software can specify and use a smaller frame list and configure the host controller via the USBCMD register Frame List Size field.  The frame list must always be aligned on a 4K-page boundary.  This requirement ensures that the frame list is always physically contiguous. 
+// This field will always be "1". 
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_PFL_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_PFL_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_PFL_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_PFL_RANGE                   1:1
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_PFL_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_PFL_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_PFL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_PFL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_HCCPARAMS_0_PFL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_DCIVERSION_0  
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0                    _MK_ADDR_CONST(0x120)
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_RESET_VAL                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_RESET_MASK                         _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_READ_MASK                  _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// The device controller interface conforms to the two-byte BCD encoding of the interface version number contained in this  register. 
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_DCIVERSION_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_DCIVERSION_FIELD                   (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_2_USB2D_DCIVERSION_0_DCIVERSION_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_DCIVERSION_RANGE                   15:0
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_DCIVERSION_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_DCIVERSION_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_DCIVERSION_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_DCIVERSION_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_DCIVERSION_0_DCIVERSION_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_DCCPARAMS_0  
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0                     _MK_ADDR_CONST(0x124)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_SECURE                      0x0
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_RESET_VAL                   _MK_MASK_CONST(0x190)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_RESET_MASK                  _MK_MASK_CONST(0x19f)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_READ_MASK                   _MK_MASK_CONST(0x19f)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// Host Capable: 1 = This controller is capable of operating as an EHCI compatible USB 2 0 host controller operating as an EHCI  compatible USB 2.0 host controller. This field is set to 1.
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_HC_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_HC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_HC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_HC_RANGE                    8:8
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_HC_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_HC_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_HC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_HC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_HC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Device Capable: 1 = Controller is capable of operating as USB 2.0 device. This field is set to 1.
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DC_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DC_RANGE                    7:7
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DC_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DC_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Device Endpoint Number: Number of endpoints built into the device controller. This is set to 16.
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DEN_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DEN_FIELD                   (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DEN_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DEN_RANGE                   4:0
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DEN_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DEN_DEFAULT                 _MK_MASK_CONST(0x10)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DEN_DEFAULT_MASK                    _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DEN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_DCCPARAMS_0_DEN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_USBCMD_0  
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0                        _MK_ADDR_CONST(0x140)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SECURE                         0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_WORD_COUNT                     0x1
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RESET_VAL                      _MK_MASK_CONST(0x80b00)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RESET_MASK                     _MK_MASK_CONST(0xffebff)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_READ_MASK                      _MK_MASK_CONST(0xffebff)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_WRITE_MASK                     _MK_MASK_CONST(0xffeb7f)
+// Interrupt Threshold Control .Read/Write. Default 08h. The system software uses this field to set the maximum rate at which the host/device controller will issue interrupts. ITC contains the maximum interrupt interval measured in micro-frames. Valid values are shown below.  
+// Value          Maximum Interrupt Interval 
+// 00h              Immediate (no threshold) 
+// 01h                1 micro-frame 
+// 02h           2 micro-frames 
+// 04h          4 micro-frames 
+// 08h          8 micro-frames 
+// 10h          16 micro-frames 
+// 20h         32 micro-frames 
+// 40h         64 micro-frames
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_RANGE                      23:16
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_DEFAULT                    _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_IMMEDIATE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_ONE_MF                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_TWO_MF                     _MK_ENUM_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_EIGHT_MF                   _MK_ENUM_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_SIXTEEN_MF                 _MK_ENUM_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_THIRTY_TWO_MF                      _MK_ENUM_CONST(32)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ITC_SIXTY_FOUR_MF                      _MK_ENUM_CONST(64)
+
+// Bit 2 of Frame List Size.
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS2_SHIFT                      _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS2_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBCMD_0_FS2_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS2_RANGE                      15:15
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS2_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Frame List Size . (Read/Write).  000 = Default
+// This field is Read/Write only if Programmable Frame List Flag in the HCCPARAMS registers is set to one.  Hence this field is Read/Write for this implementation. This field specifies the size of the frame list that controls which bits in the Frame Index Register should be used for the Frame List Current index. 
+// Note that this field is made up from USBCMD bits 15, 3 and 2. 
+// 000 = 1024 elements (4096 bytes) Default value 
+// 001 = 512 elements (2048 bytes) 
+// 010 = 256 elements (1024 bytes)  
+// 011 = 128 elements (512 bytes) 
+// 100 = 64 elements (256 bytes) 
+// 101 = 32 elements (128 bytes) 
+// 110 = 16 elements (64 bytes) 
+// 111 = 8 elements (32 bytes)       
+// Only the host controller uses this field. 
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS1_FS0_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS1_FS0_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_USBCMD_0_FS1_FS0_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS1_FS0_RANGE                  3:2
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS1_FS0_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS1_FS0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS1_FS0_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS1_FS0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_FS1_FS0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Setup Tripwire. This bit is used as a semaphore when the 8 bytes  of setup data read extracted by the firmware. If the setup lockout mode is  off, then there exists a hazard when new setup data arrives and firmware is  copying setup data from the QH for a previous setup packet. This bit is set  and cleared by software and will be cleared by hardware when a hazard exists.
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SUTW_SHIFT                     _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SUTW_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBCMD_0_SUTW_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SUTW_RANGE                     13:13
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SUTW_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SUTW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SUTW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SUTW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SUTW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SUTW_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_SUTW_SET                       _MK_ENUM_CONST(1)
+
+// Add DTD Tripwire. This bit is used as a semaphore when a dTD is  added to an active (primed) endpoint. This bit is set and cleared by software  and will be cleared by hardware when a hazard exists such that adding a dTD  to a primed endpoint may go unnoticed.
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ATDTW_SHIFT                    _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ATDTW_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBCMD_0_ATDTW_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ATDTW_RANGE                    14:14
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ATDTW_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ATDTW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ATDTW_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ATDTW_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ATDTW_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ATDTW_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ATDTW_SET                      _MK_ENUM_CONST(1)
+
+// Asynchronous Schedule Park mode Enable. Software uses this bit to enable or disable Park mode. When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is disabled.  This field is set to "1" in this  implementation. 
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASPE_SHIFT                     _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASPE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBCMD_0_ASPE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASPE_RANGE                     11:11
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASPE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASPE_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASPE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASPE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASPE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASPE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASPE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Asynchronous Schedule Park Mode Count (OPTIONAL) Read/Write.  If the Asynchronous Park Capability bit in the HCCPARAMS register is a one,  then this field defaults to 3h and is R/W. Otherwise it defaults to zero and  is RO. It contains a count of the number of successive transactions the host  controller is allowed to execute from a high-speed queue head on the  Asynchronous schedule before continuing traversal of the Asynchronous  schedule. Valid values are 1h to 3h. Software must not write a zero to this  bit when Park Mode Enable is a one as this will result in undefined behavior.  This field is set to 3h in this implementation and is Read/Write capable. 
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASP1_ASP0_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASP1_ASP0_FIELD                        (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_USBCMD_0_ASP1_ASP0_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASP1_ASP0_RANGE                        9:8
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASP1_ASP0_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASP1_ASP0_DEFAULT                      _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASP1_ASP0_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASP1_ASP0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASP1_ASP0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Light Host/Device Controller Reset (OPTIONAL) .  Read Only. Not Implemented. This field will always be "0". 
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_LR_SHIFT                       _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_LR_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBCMD_0_LR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_LR_RANGE                       7:7
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_LR_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_LR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_LR_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_LR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_LR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Interrupt on Async Advance Doorbell. When the host controller has evicted all  appropriate cached schedule states, it sets the Interrupt on Async Advance  status bit in the USBSTS register. If the Interrupt on Sync Advance Enable  bit in the USBINTR register is one, then the host controller will assert an  interrupt at the next interrupt threshold. The host controller sets this bit  to zero after it has set the Interrupt on Sync Advance status bit in the  USBSTS register to one. Software should not write a one to this bit when the  asynchronous schedule is inactive. Doing so will yield undefined results. This  bit is only used in host mode. Writing a one to this bit when device mode is  selected will have undefined results. 
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_IAA_SHIFT                      _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_IAA_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBCMD_0_IAA_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_IAA_RANGE                      6:6
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_IAA_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_IAA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_IAA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_IAA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_IAA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_IAA_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_IAA_SET                        _MK_ENUM_CONST(1)
+
+// Asynchronous Schedule Enable. This bit controls whether the host controller skips processing the Asynchronous Schedule. 
+// 0 = Do not process the Asynchronous Schedule. 
+// 1 = Use the ASYNCLISTADDR register to access the  Asynchronous Schedule. 
+// Only the host controller uses this bit. 
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASE_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBCMD_0_ASE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASE_RANGE                      5:5
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASE_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_ASE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Periodic Schedule Enable.This bit controls whether the host controller skips processing the Periodic Schedule. 
+// 0 = Do not process the Periodic Schedule 
+// 1 = Use the PERIODICLISTBASE register to access the Periodic  Schedule. 
+// Only the host controller uses this bit. 
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_PSE_SHIFT                      _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_PSE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBCMD_0_PSE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_PSE_RANGE                      4:4
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_PSE_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_PSE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_PSE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_PSE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_PSE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_PSE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_PSE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Controller Reset. Software uses this bit to reset the controller. This bit is set to zero by the Host/Device Controller when the reset process is complete. Software cannot terminate the reset process early by writing a zero to this register. 
+// Host Controller: 
+// When software writes a one to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. Software should not set this bit to a one when the HCHalted bit in the USBSTS register is a zero.  Attempting to reset an actively running host controller results in undefined behavior.   
+// Device Controller: 
+// When software writes a one to this bit, the Device  Controller resets its internal pipelines, timers, counters, state machines  etc. to their initial value. Any transaction currently in progress on USB is  immediately terminated. Writing a one to this bit in device mode is not  recommended. 
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RST_SHIFT                      _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RST_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBCMD_0_RST_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RST_RANGE                      1:1
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RST_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RST_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RST_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RST_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RST_SET                        _MK_ENUM_CONST(1)
+
+// Run/Stop: 
+// Host Controller: 
+// When set to a 1, the Host Controller proceeds with the execution of the schedule.  
+// The Host Controller continues execution as long as this bit is set to a one.  When this bit is set to 0, the Host Controller completes the current transaction on the USB and then halts.  The HCHalted bit in the status register indicates when the Host Controller has finished the transaction and has entered the stopped state.  Software should not write a one to this field unless the host controller is in the Halted state (i.e. HCHalted in the USBSTS register is a one). 
+// Device Controller: 
+// Writing a one to this bit will cause the device  controller to enable a pull-up on D+ and initiate an attach event. This  control bit is not directly connected to the pull-up enable, as the pull-up  will become disabled upon transitioning into high-speed mode. Software should  use this bit to prevent an attach event before the device controller has been  properly initialized. Writing a 0 to this will cause a detach event. 
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RS_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBCMD_0_RS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RS_RANGE                       0:0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RS_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RS_STOP                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBCMD_0_RS_RUN                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_USBSTS_0  
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0                        _MK_ADDR_CONST(0x144)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SECURE                         0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_WORD_COUNT                     0x1
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RESET_VAL                      _MK_MASK_CONST(0x1000)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RESET_MASK                     _MK_MASK_CONST(0xdf5ff)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_READ_MASK                      _MK_MASK_CONST(0xdf5ff)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_WRITE_MASK                     _MK_MASK_CONST(0xcd5ef)
+// USB Host Periodic Interrupt (USBHSTPERINT)  R/WC. This bit is set by the Host
+// Controller when the cause of an interrupt is a completion of a USB transaction where the
+// Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set and the TD was from the
+// periodic schedule.
+// This bit is also set by the Host Controller when a short packet is detected AND the packet is on
+// the periodic schedule. A short packet is when the actual number of bytes received was less
+// than the expected number of bytes.
+// This bit is not used by the device controller and will always be zero.
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UPA_SHIFT                      _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UPA_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_UPA_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UPA_RANGE                      19:19
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UPA_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UPA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UPA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UPA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UPA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UPA_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UPA_ENABLE                     _MK_ENUM_CONST(1)
+
+// USB Host Asynchronous Interrupt (USBHSTASYNCINT)  R/WC. This bit is set by the
+// Host Controller when the cause of an interrupt is a completion of a USB transaction where the
+// Transfer Descriptor (TD) has an interrupt on complete (IOC) bit set AND the TD was from the
+// asynchronous schedule.
+// This bit is also set by the Host when a short packet is detected AND the packet is on the
+// asynchronous schedule. A short packet is when the actual number of bytes received was
+// less than the expected number of bytes.
+// This bit is not used by the device controller and will always be zero.
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UAI_SHIFT                      _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UAI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_UAI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UAI_RANGE                      18:18
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UAI_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UAI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UAI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UAI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UAI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UAI_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UAI_ENABLE                     _MK_ENUM_CONST(1)
+
+// NAK Interrupt Bit  Read Only. This bit is readonly.
+// It is set by hardware when for a
+// particular endpoint both the TX/RX Endpoint NAK bit and the corresponding TX/RX Endpoint
+// NAK Enable bit are set. This bit is automatically cleared by hardware when the all the enabled
+// TX/RX Endpoint NAK bits are cleared.
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_NAKI_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_NAKI_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_NAKI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_NAKI_RANGE                     16:16
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_NAKI_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_NAKI_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_NAKI_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_NAKI_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_NAKI_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_NAKI_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_NAKI_ENABLE                    _MK_ENUM_CONST(1)
+
+// Asynchronous Schedule Status. 
+// This bit reports the current real status of the Asynchronous Schedule.  
+// When set to zero the asynchronous schedule status is disabled and 
+// if set to one the status is enabled.  The Host Controller is not required to 
+// immediately disable or enable the Asynchronous Schedule when software transitions
+// the Asynchronous Schedule Enable bit in the USBCMD register.  
+// If AS = ASE: 
+// 1= Enable Asynchronous Schedule 0= Disable Asynchronous Schedule
+// Only used by the host controller. 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AS_SHIFT                       _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_AS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AS_RANGE                       15:15
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AS_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AS_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AS_ENABLE                      _MK_ENUM_CONST(1)
+
+// Periodic Schedule Status.
+// This bit reports the current real status of the Periodic Schedule. 
+// When set to zero the periodic schedule is disabled, and if set to one
+// the status is enabled. The Host Controller is not required to immediately
+// disable or enable the Periodic Schedule when software transitions
+// the Periodic Schedule Enable bit in the USBCMD register.  
+// If PS = PSE then:
+// 1 = Periodic Schedule is enabled or 0 = Periodic Schedule is disabled
+// Only used by the host controller. 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PS_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_PS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PS_RANGE                       14:14
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PS_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PS_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PS_ENABLE                      _MK_ENUM_CONST(1)
+
+// Reclamation. 
+// This is a read-only status bit used to detect an empty asynchronous schedule.
+// Only used by the host controller. 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RCL_SHIFT                      _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RCL_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_RCL_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RCL_RANGE                      13:13
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RCL_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RCL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RCL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RCL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RCL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RCL_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_RCL_ENABLE                     _MK_ENUM_CONST(1)
+
+// HCHalted. 1 = Default. 
+// This bit is a zero  whenever the Run/Stop bit is a one. 
+// The Host Controller sets this bit to one  after it has stopped 
+// executing because of the Run/Stop bit being set to 0,  either by software
+// or by the Host Controller hardware (e.g. internal error). 
+// Only  used by the host controller. 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_HCH_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_HCH_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_HCH_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_HCH_RANGE                      12:12
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_HCH_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_HCH_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_HCH_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_HCH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_HCH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_HCH_UNHALTED                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_HCH_HALTED                     _MK_ENUM_CONST(1)
+
+// ULPI Interrupt. This bit is set whenever an interrupt is received from ULPI PHY.
+// Software writes 1 to clear it.
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_ULPI_INT_SHIFT                 _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_ULPI_INT_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_ULPI_INT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_ULPI_INT_RANGE                 10:10
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_ULPI_INT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_ULPI_INT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_ULPI_INT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_ULPI_INT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_ULPI_INT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_ULPI_INT_NOT_ULPI_INT                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_ULPI_INT_ULPI_INT                      _MK_ENUM_CONST(1)
+
+// DCSuspend. When a device controller enters a suspend state
+// from an active state, this bit will be set to a 1. 
+// The device controller  clears the bit upon exiting from a suspend state.
+// Only used by the device  controller. 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SLI_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SLI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_SLI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SLI_RANGE                      8:8
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SLI_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SLI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SLI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SLI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SLI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SLI_NOTSUSPEND                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SLI_SUSPENDED                  _MK_ENUM_CONST(1)
+
+// SOF Received. When the device controller detects a Start Of
+// (micro) Frame, this bit will be set to a one. 
+// When a SOF is extremely late, the device controller will automatically 
+// set this bit to indicate that an SOF was expected.  
+// Therefore, this bit will be set roughly every 1ms in device FS mode
+// and every 125us in HS mode and will be synchronized to the actual SOF that 
+// is received. Since device controller is initialized to FS before connect, 
+// this bit Will be set at an interval of 1ms during the prelude to the connect
+// and chirp. 
+// In host mode, this bit will be set every 125us and can be used by
+// host controller driver as a time base. 
+// Software writes a 1 to this bit to clear it. This  is a non-EHCI status bit. 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SRI_SHIFT                      _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SRI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_SRI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SRI_RANGE                      7:7
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SRI_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SRI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SRI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SRI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SRI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SRI_SOF_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SRI_SOF_RCVD                   _MK_ENUM_CONST(1)
+
+// USB Reset Received. 
+// When the device controller detects a USB Reset 
+// and  enters the default state, this bit is set to a 1.
+// Software can write a 1 to  this bit to clear the USB Reset
+// Received status bit. 
+// Only used by the device  controller. 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_URI_SHIFT                      _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_URI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_URI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_URI_RANGE                      6:6
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_URI_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_URI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_URI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_URI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_URI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_URI_NO_USB_RESET                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_URI_USB_RESET                  _MK_ENUM_CONST(1)
+
+// Interrupt and Asynchronous Advance. 
+// System software can force the host controller to  issue an interrupt
+// the next time the host controller advances the  asynchronous schedule
+// by writing a one to the Interrupt on Async Advance  Doorbell bit in the
+// USBCMD register. This status bit indicates the assertion  of that interrupt source.
+// Only used by the host controller
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AAI_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AAI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_AAI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AAI_RANGE                      5:5
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AAI_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AAI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AAI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AAI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AAI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AAI_NOT_ADVANCED                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_AAI_ADVANCED                   _MK_ENUM_CONST(1)
+
+// System Error. 
+// This bit is not used in this  implementation and will always be set to "0". 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SEI_SHIFT                      _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SEI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_SEI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SEI_RANGE                      4:4
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SEI_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SEI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SEI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SEI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SEI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SEI_NO_ERROR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_SEI_ERROR                      _MK_ENUM_CONST(1)
+
+// Frame List Rollover. 
+// The Host Controller sets this bit to a 1 when the Frame List Index rolls
+// over from its maximum value to 0. The exact  value at which the rollover
+// occurs depends on the frame list size. For  example. If the frame list
+// size (as programmed in the Frame List Size field  of the USBCMD register)
+// is 1024, the Frame Index Register rolls over every  time FRINDEX [1 3] toggles.
+// Similarly, if the size is 512, the Host  Controller sets this bit to
+// a 1 every time FHINDEX [12] toggles. 
+// Only used  by the host controller. 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_FRI_SHIFT                      _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_FRI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_FRI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_FRI_RANGE                      3:3
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_FRI_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_FRI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_FRI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_FRI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_FRI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_FRI_NO_ROLLOVER                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_FRI_ROLLOVER                   _MK_ENUM_CONST(1)
+
+// Port Change Detect. 
+// The Host Controller sets this bit to a 1 when on any port a Connect
+// Status occurs, a Port Enable/Disable Change occurs, or the  Force
+// Port Resume bit is set as the result of a J-K transition on the
+// suspended port. The Device Controller sets this bit to a one when
+// the port  controller enters the full or high-speed operational state.
+// When the port  controller exits the full or high-speed operational
+// states due to Reset or  Suspend events, the notification mechanisms
+// are the USB Reset Received bit  and the DCSuspend bits respectively. 
+// This bit is not EHCI compatible. 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PCI_SHIFT                      _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PCI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_PCI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PCI_RANGE                      2:2
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PCI_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PCI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PCI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PCI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PCI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PCI_NO_PORT_CHANGE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_PCI_PORT_CHANGE                        _MK_ENUM_CONST(1)
+
+// USB Error Interrupt. 
+// This bit gets set by the Host/Device controller  when completion
+// of a USB transaction results in an error condition. This bit  is set
+// along with the USBINT bit, if the TD on which the error interrupt
+// occurred also ad its interrupt on complete (IOC) bit set. 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UEI_SHIFT                      _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UEI_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_UEI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UEI_RANGE                      1:1
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UEI_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UEI_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UEI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UEI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UEI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UEI_NO_ERROR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UEI_ERROR                      _MK_ENUM_CONST(1)
+
+// USB Interrupt.
+// This bit is set by the Host/Device Controller when  the cause of
+// an interrupt is a completion of a USB transaction where the
+// Transfer Descriptor (TD) as an interrupt on complete (IOC) bit set.
+// This bit  is also set by the Host/Device Controller when a short
+// packet is detected. A  short packet is when the actual number of bytes
+// received was less than the  expected number of bytes. 
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UI_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UI_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBSTS_0_UI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UI_RANGE                       0:0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UI_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UI_NO_INT                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBSTS_0_UI_INT                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_USBINTR_0  
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0                       _MK_ADDR_CONST(0x148)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SECURE                        0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_RESET_MASK                    _MK_MASK_CONST(0xd05ff)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_READ_MASK                     _MK_MASK_CONST(0xd05ff)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_WRITE_MASK                    _MK_MASK_CONST(0xd05ff)
+// UPIE Interrupt Enable. 1 = USB controller issues an interrupt if UPA bit in USBSTS register transitions.
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UPIE_SHIFT                    _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UPIE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_UPIE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UPIE_RANGE                    19:19
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UPIE_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UPIE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UPIE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UPIE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UPIE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UPIE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UPIE_ENABLE                   _MK_ENUM_CONST(1)
+
+// UAIE Interrupt Enable. 1 = USB controller issues an interrupt if UAI bit in USBSTS register transitions.
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UAIE_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UAIE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_UAIE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UAIE_RANGE                    18:18
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UAIE_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UAIE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UAIE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UAIE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UAIE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UAIE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UAIE_ENABLE                   _MK_ENUM_CONST(1)
+
+// NAK Interrupt Enable. 1 = USB controller issues an interrupt if NAKI bit in USBSTS register transitions.
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_NAKE_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_NAKE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_NAKE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_NAKE_RANGE                    16:16
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_NAKE_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_NAKE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_NAKE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_NAKE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_NAKE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_NAKE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_NAKE_ENABLE                   _MK_ENUM_CONST(1)
+
+// ULPI Interrupt Enable. 1 = USB controller issues an interrupt if ULPI_INT bit in USBSTS register transitions.
+// The interrupt is acknowledged by SW by writing a 1 to the ULPI_INT bit.
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_ULPIE_SHIFT                   _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_ULPIE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_ULPIE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_ULPIE_RANGE                   10:10
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_ULPIE_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_ULPIE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_ULPIE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_ULPIE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_ULPIE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_ULPIE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_ULPIE_ENABLE                  _MK_ENUM_CONST(1)
+
+// Sleep Enable. 1 = Device controller issues an interrupt if  DCSuspend bit in USBSTS register transitions. 
+// The interrupt is acknowledged by SW by writing a 1 to the DCSuspend bit. Only used by the device controller. 
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SLE_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SLE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_SLE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SLE_RANGE                     8:8
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SLE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SLE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SLE_ENABLE                    _MK_ENUM_CONST(1)
+
+// SOF Received Enable. 1 = Device controller issues an interrupt if SOF Received bit in USBSTS register = 1.
+// The interrupt is acknowledged by software clearing  the SOF Received bit. 
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SRE_SHIFT                     _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SRE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_SRE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SRE_RANGE                     7:7
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SRE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SRE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SRE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SRE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SRE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SRE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SRE_ENABLE                    _MK_ENUM_CONST(1)
+
+// USB Reset Enable.1 = Device controller issues an interrupt if USB Reset Received bit in USBSTS register  = 1 
+// The interrupt is acknowledged by software clearing  the USB Reset Received bit. Only used by the device controller. 
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_URE_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_URE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_URE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_URE_RANGE                     6:6
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_URE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_URE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_URE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_URE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_URE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_URE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_URE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Interrupt on Asynchronous Advance Enable. 1 = the host controller issues an interrupt at the  next interrupt threshold if Interrupt on Async Advance bit in USBSTS register  = 1. 
+// The interrupt is acknowledged by software clearing the Interrupt on  Async Advance bit. Only used by the host controller. 
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_AAE_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_AAE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_AAE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_AAE_RANGE                     5:5
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_AAE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_AAE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_AAE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_AAE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_AAE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_AAE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_AAE_ENABLE                    _MK_ENUM_CONST(1)
+
+// System Error Enable. 1 = Host/device controller issues an interrupt if  the System Error bit in USBSTS register = 1.
+// The interrupt is acknowledged by  software clearing the System Error bit. 
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SEE_SHIFT                     _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SEE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_SEE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SEE_RANGE                     4:4
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SEE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SEE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SEE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SEE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SEE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SEE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_SEE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Frame List Rollover Enable. 1 = Host controller issues an interrupt if Frame  List Rollover bit in the USBSTS register = 1.
+// The interrupt is acknowledged  by software clearing the Frame List Rollover bit. Only used by the host  controller. 
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_FRE_SHIFT                     _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_FRE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_FRE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_FRE_RANGE                     3:3
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_FRE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_FRE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_FRE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_FRE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_FRE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_FRE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_FRE_ENABLE                    _MK_ENUM_CONST(1)
+
+// Port Change Detect Enable. 1 = Host/device controller issues an interrupt if  Port Change Detect bit in USBSTS register = 1. 
+// The interrupt is acknowledged  by software clearing the Port Change Detect bit.
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_PCE_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_PCE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_PCE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_PCE_RANGE                     2:2
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_PCE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_PCE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_PCE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_PCE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_PCE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_PCE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_PCE_ENABLE                    _MK_ENUM_CONST(1)
+
+// USB Error Interrupt Enable. 1 = Host controller issues an interrupt at the  next interrupt threshold if the USBERRINT bit in USBSTS = 1. 
+// The interrupt is  acknowledged by software clearing the USBERRINT bit in the USBSTS register. 
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UEE_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UEE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_UEE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UEE_RANGE                     1:1
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UEE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UEE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UEE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UEE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UEE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UEE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UEE_ENABLE                    _MK_ENUM_CONST(1)
+
+// USB Interrupt Enable. 1 = Host/device issues an interrupt at the next  interrupt threshold if the USBINT bit in USBSTS = 1. 
+// The interrupt is  acknowledged by software clearing the USBINT bit.
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBINTR_0_UE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UE_RANGE                      0:0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UE_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBINTR_0_UE_ENABLE                     _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_FRINDEX_0  
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0                       _MK_ADDR_CONST(0x14c)
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_SECURE                        0x0
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_RESET_MASK                    _MK_MASK_CONST(0x3fff)
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_READ_MASK                     _MK_MASK_CONST(0x3fff)
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Frame Index.  
+// The value in this register increments at the end of each time frame (micro-frame). 
+// Bits [N: 3] are used for the Frame List current index. Each location of the frame list is accessed 8 times (frames or micro-frames) before moving to the next index.  
+// The following illustrates values of N based on the value of the Frame List Size field in the USBCMD register, when used in host mode. 
+// USBCMD          [Frame List Size] Number        Elements N 
+//   000b                   (1024)                  12 
+//   001b                   (512)                   11 
+//   010b                   (256)                   10 
+//   011b                   (128)                   9 
+//   100b            (64)                    8 
+//   101b            (32)                    7 
+//   110b            (16)                    6 
+//   111b            (8)                     5 
+// In device mode the value is the current frame  number of the last frame transmitted. It is not used as an index. In either  mode bits 2:0 indicate the current micro-frame. 
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_FRINDEX_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_FRINDEX_FIELD                 (_MK_MASK_CONST(0x3fff) << USB2_CONTROLLER_2_USB2D_FRINDEX_0_FRINDEX_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_FRINDEX_RANGE                 13:0
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_FRINDEX_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_FRINDEX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_FRINDEX_DEFAULT_MASK                  _MK_MASK_CONST(0x3fff)
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_FRINDEX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_FRINDEX_0_FRINDEX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 336 [0x150] 
+
+// Register USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0  
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0                      _MK_ADDR_CONST(0x154)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_SECURE                       0x0
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_RESET_MASK                   _MK_MASK_CONST(0xfffff000)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_READ_MASK                    _MK_MASK_CONST(0xfffff000)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_WRITE_MASK                   _MK_MASK_CONST(0xfffff000)
+// Host mode: This 32-bit register contains the beginning address of the Periodic Frame List in the system memory.
+// HCD loads this register prior to starting the schedule execution by the Host Controller.
+// The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned.
+// The contents of this register are combined with the Frame Index Register (FRINDEX)
+// to enable the Host Controller to step through the Periodic Frame List in sequence. 
+// Base Address (Low). These bits correspond to memory address signals [31:12], respectively. 
+// Only used by the host controller. 
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_BASEADR_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_BASEADR_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_BASEADR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_BASEADR_RANGE                        31:12
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_BASEADR_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_BASEADR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_BASEADR_DEFAULT_MASK                 _MK_MASK_CONST(0xfffff)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_BASEADR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_BASEADR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Device mode. The upper seven bits of this register represent the device address. 
+// After any controller reset or a USB reset, the device address is set to the default address (0).
+// The default address will match all incoming addresses. 
+// Software shall reprogram the address after receiving a SET_ADDRESS request. 
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADR_SHIFT                 _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADR_FIELD                 (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADR_RANGE                 31:25
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADR_DEFAULT_MASK                  _MK_MASK_CONST(0x7f)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Device Address Advance. Default=0. 
+// When this bit is 0, any writes to USBADR are instantaneous. 
+// When this bit is written to a 1 at the same time or before USBADR is written, 
+// the write to the USBADR field is staged and held in a hidden register. 
+// After an IN occurs on endpoint 0 and is ACKed, USBADR will be loaded from the holding register.
+// Hardware will automatically clear this bit on the following conditions:
+// 1) IN is ACKed to endpoint 0. (USBADR is updated from staging register).
+// 2) OUT/SETUP occur to endpoint 0. (USBADR is not updated).
+// 3) Device Reset occurs (USBADR is reset to 0). 
+// Note: After the status phase of the SET_ADDRESS descriptor, the DCD has 2 ms to program
+// the USBADR field. This mechanism will ensure this specification is met when 
+// the DCD can not write of the device address within 2ms from the SET_ADDRESS status phase. 
+// If the DCD writes the USBADR with USBADRA=1 after the SET_ADDRESS data phase 
+// (before the prime of the status phase), the USBADR will be programmed instantly 
+// at the correct time and meet the 2ms USB requirement.
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADRA_SHIFT                        _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADRA_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADRA_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADRA_RANGE                        24:24
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADRA_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADRA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADRA_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADRA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0_USBADRA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0  
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0                 _MK_ADDR_CONST(0x158)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_SECURE                  0x0
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_RESET_MASK                      _MK_MASK_CONST(0xffffffe0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_READ_MASK                       _MK_MASK_CONST(0xffffffe0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffe0)
+// Host mode. This 32-bit register contains the address of the next asynchronous queue head to be executed by the host.
+// Link Pointer Low (LPL). These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (OH). Only used by the host controller.
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_ASYBASE_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_ASYBASE_FIELD                   (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_ASYBASE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_ASYBASE_RANGE                   31:5
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_ASYBASE_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_ASYBASE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_ASYBASE_DEFAULT_MASK                    _MK_MASK_CONST(0x7ffffff)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_ASYBASE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_ASYBASE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Device mode. This register contains the address of the top of the endpoint list in system memory. These bits correspond to memory address signals [31:11], respectively. This field will reference a list of up to 32 Queue Heads (QH). Only used by the device controller.
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_EPBASE_SHIFT                    _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_EPBASE_FIELD                    (_MK_MASK_CONST(0x1fffff) << USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_EPBASE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_EPBASE_RANGE                    31:11
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_EPBASE_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_EPBASE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_EPBASE_DEFAULT_MASK                     _MK_MASK_CONST(0x1fffff)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_EPBASE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0_EPBASE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0  
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0                    _MK_ADDR_CONST(0x15c)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_RESET_MASK                         _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_READ_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_WRITE_MASK                         _MK_MASK_CONST(0x2)
+// Embedded TT Async Buffers Clear. (Read/Write to  set) This field will clear all pending transactions in the embedded TT Async  Buffer(s). The clear will take as much time as necessary to clear buffer  without interfering with a transaction in progress. TTAC will return to zero  after being set by software only after the actual clear occurs. 
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAC_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAC_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAC_RANGE                 1:1
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAC_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAC_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Embedded TT Async Buffers Status. (Read Only) This  read only bit will be 1 if one or more transactions are being held in the  embedded TT Async. Buffers. When this bit is a zero, then all outstanding  transactions in the embedded TT have been flushed. 
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAS_RANGE                 0:0
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0_TTAS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_BURSTSIZE_0  
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0                     _MK_ADDR_CONST(0x160)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_SECURE                      0x0
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_WORD_COUNT                  0x1
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_RESET_VAL                   _MK_MASK_CONST(0x808)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_RESET_MASK                  _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_READ_MASK                   _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_WRITE_MASK                  _MK_MASK_CONST(0xffff)
+// Programmable TX Burst Length.  (Read/Write) This register represents the maximum length of a burst in 32-bit words while moving data from system memory to the USB bus.
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_TXPBURST_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_TXPBURST_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_TXPBURST_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_TXPBURST_RANGE                      15:8
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_TXPBURST_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_TXPBURST_DEFAULT                    _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_TXPBURST_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_TXPBURST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_TXPBURST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Programmable RX Burst Length.  (Read/Write) This register represents the maximum length of a burst in 32-bit words while moving data from the USB bus to system memory.
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_RXPBURST_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_RXPBURST_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_RXPBURST_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_RXPBURST_RANGE                      7:0
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_RXPBURST_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_RXPBURST_DEFAULT                    _MK_MASK_CONST(0x8)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_RXPBURST_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_RXPBURST_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_BURSTSIZE_0_RXPBURST_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0  
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0                  _MK_ADDR_CONST(0x164)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_SECURE                   0x0
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_WORD_COUNT                       0x1
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_RESET_VAL                        _MK_MASK_CONST(0x20000)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_RESET_MASK                       _MK_MASK_CONST(0x3f1fff)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_READ_MASK                        _MK_MASK_CONST(0x3f1fff)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_WRITE_MASK                       _MK_MASK_CONST(0x3f1fff)
+// FIFO Burst Threshold.  (Read/Write) This register controls the number of data bursts that are posted to the TX latency FIFO in host mode before the packet begins on to the bus.  The minimum value is 2 and this value should be a low as possible to maximize USB performance.  A higher value can be used in systems with unpredicable latency and/or insufficient bandwidth where the FIFO may underrun because the data transferred from the latency FIFO to USB occurs before it can be replenished from system memory.  This value is ignored if the Stream Disable bit in USBMODE register is set.
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXFIFOTHRES_FIELD                        (_MK_MASK_CONST(0x3f) << USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXFIFOTHRES_RANGE                        21:16
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXFIFOTHRES_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXFIFOTHRES_DEFAULT                      _MK_MASK_CONST(0x2)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXFIFOTHRES_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXFIFOTHRES_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Scheduler Health Counter.  (Read/Write To Clear)  [Default = 0] This register increments when the host controller fails to fill the TX latency FIFO to the level programmed by TXFIFOTHRES before running out of time to send the packet before the next Start-Of-Frame.
+// This health counter measures the number of times this occurs to provide feedback to selecting a proper TXSCHOH.  Writing to this register will clear the counter and this counter will max. at 31.
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHHEALTH_FIELD                        (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHHEALTH_RANGE                        12:8
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHHEALTH_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHHEALTH_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHHEALTH_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHHEALTH_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Scheduler Overhead.  (Read/Write)  [Default = 0] This register adds an additional fixed offset to the schedule time estimator described above as Tff.  As an approximation, the value chosen for this register should limit the number of back-off events captured in the TXSCHHEALTH to less than 10 per second in a highly utilized bus.  Choosing a value that is too high for this register is not desired as it can needlessly reduce USB utilization.
+// The time unit represented in this register is 1.267us when a device is connected in High-Speed Mode.
+// The time unit represented in this register is 6.333us when a device is connected in Low/Full Speed Mode
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHOH_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHOH_FIELD                    (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHOH_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHOH_RANGE                    7:0
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHOH_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHOH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHOH_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHOH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0_TXSCHOH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Reserved address 360 [0x168] 
+
+// Register USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0  
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0                    _MK_ADDR_CONST(0x16c)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_RESET_MASK                         _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_READ_MASK                  _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_WRITE_MASK                         _MK_MASK_CONST(0xf)
+// ICUSB transceiver enable. 
+// This bit enables the ICUSB transceiver . 
+// To enable the interface, the bits PTS must be set to 11 in the PORTSCx.
+// Writing a '1' to this bit selects the IC_USB interface.
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_ENB1_SHIFT                      _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_ENB1_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_ENB1_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_ENB1_RANGE                      3:3
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_ENB1_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_ENB1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_ENB1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_ENB1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_ENB1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_ENB1_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_ENB1_ENABLE                     _MK_ENUM_CONST(1)
+
+// ICUSB voltage select.
+// It selects which voltage is being supplied to the ICUSB peripheral.
+// 000 -> No voltage
+// 001 -> 1.0V - reserved
+// 010 -> 1.2V - reserved
+// 011 -> 1.5V - reserved
+// 100 -> 1.8V
+// 101 -> 3.0V
+// 110 -> reserved
+// 111 -> reserved
+// The Voltage negotiation should happen between enabling port power (PP) and
+// asserting the run/stop bit in register.
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_VDD1_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_VDD1_FIELD                      (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_VDD1_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_VDD1_RANGE                      2:0
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_VDD1_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_VDD1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_VDD1_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_VDD1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0_IC_VDD1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0  
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0                 _MK_ADDR_CONST(0x170)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_SECURE                  0x0
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_RESET_MASK                      _MK_MASK_CONST(0xefffffff)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_READ_MASK                       _MK_MASK_CONST(0xefffffff)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_WRITE_MASK                      _MK_MASK_CONST(0xe7ff00ff)
+// ULPI Wakeup. Writing the 1 to this bit will begin the wakeup operation. 
+// The bit will automatically transition to 0 after the wakeup is complete. 
+// Once this bit is set, the driver can not set it back to 0. 
+// Note: The driver must never execute a wakeup and a read/write operation at the same time.
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_SHIFT                       _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_RANGE                       31:31
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_WAKEUP_SET                 _MK_ENUM_CONST(1)
+
+// ULPI read/write Run. Writing the 1 to this bit will begin the read/write operation. 
+// The bit will automatically transition to 0 after the read/write is complete. 
+// Once this bit is set, the driver can not set it back to 0. 
+// Note: The driver must never execute a wakeup and a read/write operation at the same time.
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_RANGE                  30:30
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RUN_SET                    _MK_ENUM_CONST(1)
+
+// ULPI read/write control. (0)  Read; (1)  Write. This bit selects between running a read or write operation.
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_SHIFT                        _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_RANGE                        29:29
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_READ                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_RD_WR_WRITE                        _MK_ENUM_CONST(1)
+
+// ULPI sync state. (1)  Normal Sync. State. (0) In another state (i.e. carkit, serial, low power)
+// This bit represents the state of the ULPI interface. 
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_SHIFT                   _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_RANGE                   27:27
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_NOT_NORMAL                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_SYNC_STATE_NORMAL                  _MK_ENUM_CONST(1)
+
+// ULPI PHY port no. This field should be always written as 0.
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_SHIFT                 _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_FIELD                 (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_RANGE                 26:24
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_PORT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// ULPI PHY register address. When doing a read or write operation to the ULPI PHY, 
+// the address of the ULPI PHY register being accessed is written to this field.
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_RANGE                     23:16
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_REG_ADDR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// ULPI PHY data read. The data from the ULPI PHY register can be read from here after the read operation completes.
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_RANGE                      15:8
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_RD_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// ULPI PHY data write. The data to write to the ULPI PHY register is written here.
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_FIELD                      (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_RANGE                      7:0
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0_ULPI_DATA_WR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 372 [0x174] 
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTNAK_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0                      _MK_ADDR_CONST(0x178)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_SECURE                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_WORD_COUNT                   0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// TX Endpoint NAK  R/WC. Each TX endpoint has 1 bit in this field.
+// The bit is set when the device sends a NAK handshake on a received
+// IN token for the corresponding endpoint.
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPTN_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPTN_FIELD                   (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPTN_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPTN_RANGE                   31:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPTN_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPTN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPTN_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPTN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPTN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPTN_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPTN_SET                     _MK_ENUM_CONST(1)
+
+// RX Endpoint NAK  R/WC. Each RX endpoint has 1 bit in this field.
+// The bit is set when the device sends a NAK handshake on a received
+// OUT or PING token for the corresponding endpoint.
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPRN_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPRN_FIELD                   (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPRN_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPRN_RANGE                   15:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPRN_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPRN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPRN_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPRN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPRN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPRN_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_0_EPRN_SET                     _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0                       _MK_ADDR_CONST(0x17c)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_SECURE                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// TX Endpoint NAK Enable  R/W. Each bit is an enable bit for
+// the corresponding TX Endpoint NAK bit. If this bit is set
+// and the corresponding TX Endpoint NAK bit is set, 
+// the NAK Interrupt bit is set.
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPTNE_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPTNE_FIELD                   (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPTNE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPTNE_RANGE                   31:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPTNE_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPTNE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPTNE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPTNE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPTNE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPTNE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPTNE_ENABLE                  _MK_ENUM_CONST(1)
+
+// RX Endpoint NAK Enable  R/W. Each bit is an enable bit for
+// the corresponding RX Endpoint NAK bit. If this bit is set and
+// the corresponding RX Endpoint NAK bit is set, 
+// the NAK Interrupt bit is set.
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPRNE_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPRNE_FIELD                   (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPRNE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPRNE_RANGE                   15:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPRNE_WOFFSET                 0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPRNE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPRNE_DEFAULT_MASK                    _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPRNE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPRNE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPRNE_DISABLE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0_EPRNE_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Reserved address 384 [0x180] 
+
+// Register USB2_CONTROLLER_2_USB2D_PORTSC1_0  
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0                       _MK_ADDR_CONST(0x184)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SECURE                        0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_RESET_VAL                     _MK_MASK_CONST(0x1004)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WRITE_MASK                    _MK_MASK_CONST(0xe3ff114e)
+// Parallel transceiver select. This bit is not defined in the EHCI specification. 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_SHIFT                     _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_RANGE                     31:30
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_UTMI                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_RESERVED                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_ULPI                      _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTS_ICUSB_SER                 _MK_ENUM_CONST(3)
+
+// 0 = Serial transceiver not selected. This is the  only value supported. This bit is not defined in the EHCI specification. 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_STS_SHIFT                     _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_STS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_STS_RANGE                     29:29
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_STS_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_STS_PARALLEL_IF                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_STS_SERIAL_IF                 _MK_ENUM_CONST(1)
+
+// Parallel Transceiver Width. Fixed to 0. This bit is not defined in the EHCI specification.  
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTW_SHIFT                     _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTW_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTW_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTW_RANGE                     28:28
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTW_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTW_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTW_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTW_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTW_EIGHT_BIT                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTW_RESERVED                  _MK_ENUM_CONST(1)
+
+// This register field indicates the speed at which the port is operating. 
+// 00 = Full Speed
+// 01 = Low Speed
+// 10 = High Speed 
+// This bit is not defined in the EHCI specification.  
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_SHIFT                    _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_RANGE                    27:26
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_FULL_SPEED                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_LOW_SPEED                        _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_HIGH_SPEED                       _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PSPD_RESERVED                 _MK_ENUM_CONST(3)
+
+// Shorten USB Reset Time. Software should never set this to 1.
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SRT_SHIFT                     _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SRT_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_SRT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SRT_RANGE                     25:25
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SRT_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SRT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SRT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SRT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SRT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Port Force Full Speed Connect: Writing this bit to a 1b forces the port to connect at Full Speed only. It disables the chirp sequence that allows the port to identify itself as High Speed. This is useful for testing FS configurations with a HS host, hub or device. This bit is not defined in the EHCI specification.
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PFSC_SHIFT                    _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PFSC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PFSC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PFSC_RANGE                    24:24
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PFSC_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PFSC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PFSC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PFSC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PFSC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PFSC_DONT_FORCE_FULL_SPEED                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PFSC_FORCE_FULL_SPEED                 _MK_ENUM_CONST(1)
+
+// PHY Low Power Suspend - Clock disable: Writing this bit to a 1 will disable the PHY clock. Write a 0 enables it. Reading this bit will indicate the status of the PHY clock.
+// In device mode, the PHY can be put into Low Power Suspend - Clock disable when the device is not running (USBCMD Run/Stop = 0) or the host has signaled suspend (PORTSC SUSPEND = 1). Low power suspend will be cleared automatically when the host has signaled resume. Before forcing a resume from the device, the device controller driver must clear this bit.
+// In host mode, the PHY can be put into Low Power Suspend - Clock disable when the downstream device has been put into suspend mode or when no downstream device is connected.
+// This bit is not defined in the EHCI specification.
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PHCD_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PHCD_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PHCD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PHCD_RANGE                    23:23
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PHCD_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PHCD_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PHCD_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PHCD_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PHCD_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PHCD_DISBLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PHCD_ENABLE                   _MK_ENUM_CONST(1)
+
+// Default = 0b. Wake on Over-current Enable: Writing this bit to a one enables  the port to be sensitive to over-current conditions as wake-up events. This  field is zero if Port Power(PP) is zero. This bit should only be used when  operating in Host mode. Writing this bit to 1 while the controller is working  in device mode can result in undefined behavior.
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKOC_SHIFT                    _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKOC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKOC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKOC_RANGE                    22:22
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKOC_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKOC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKOC_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKOC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKOC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKOC_DISBLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKOC_ENABLE                   _MK_ENUM_CONST(1)
+
+// Wake on Disconnect Enable: Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events. This field is zero if Port Power(PP) is zero or in device mode. 
+// This bit should only be used when operating in Host mode. Writing this bit to 1 while the controller is working in device mode can result in undefined behaviour. 
+// This bit should not be written to 1 if there is no  device connected. After the device disconnect is detected, this bit should be  cleared to 0.
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKDS_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKDS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKDS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKDS_RANGE                    21:21
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKDS_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKDS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKDS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKDS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKDS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKDS_DISBLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKDS_ENABLE                   _MK_ENUM_CONST(1)
+
+// Wake on Connect Enable: Writing this bit to a one enables the port to be sensitive to device connects as wake-up events. This field is zero if Port Power(PP) is zero or in device mode. 
+// This bit should only be used when operating in Host mode. Writing this bit to 1 while the controller is working in device mode can result in undefined behaviour. 
+// This bit should not be written to 1 while the  device is connected. After the device connection is detected, this bit should  be cleared to 0.
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKCN_SHIFT                    _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKCN_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKCN_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKCN_RANGE                    20:20
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKCN_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKCN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKCN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKCN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKCN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKCN_DISBLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_WKCN_ENABLE                   _MK_ENUM_CONST(1)
+
+// Port Test Control: Any other value than zero indicates that the port is operating in test mode. 
+//   Value                  Specific Test 
+//  0000b                Not enabled 
+//  0001b                  J_ STATE 
+//  0010b             K_STATE 
+//  0011b              SEQ_NAK 
+//  0100b              Packet 
+//  0101b               FORCE_ENABLE 
+//  0110b to 1111b         Reserved 
+// Refer to Chapter 7 of the USB Specification  Revision 2.0 for details on each test mode. 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_FIELD                     (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_RANGE                     19:16
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_NORMAL_OP                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_TEST_J                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_TEST_K                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_TEST_SE0_NAK                      _MK_ENUM_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_TEST_PKT                  _MK_ENUM_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PTC_TEST_FORCE_ENABLE                 _MK_ENUM_CONST(5)
+
+// Port Indicator Control: This field is not supported in the current  implementation. Please use a GPIO if you wish to use Port Indicators.
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PIC_SHIFT                     _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PIC_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PIC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PIC_RANGE                     15:14
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PIC_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PIC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PIC_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PIC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PIC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Port Owner. Port owner handoff is not implemented in this design, therefore this bit will  always be 0. 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PO_SHIFT                      _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PO_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PO_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PO_RANGE                      13:13
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PO_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Port Power: The function of this bit depends on the value of the Port Power Switching (PPC) field in the HCSPARAMS register. The behavior is as follows: 
+// PPC                       PP  Operation 
+// 0b                           0b Read Only. A device controller with no OTG capability does not have port power control switches. 
+// 1b                          1b/0b RW.  Host/OTG controller requires port power control switches. 
+// This bit represents the current setting of the switch (0=off, 1=on).  When power is not available on a port (i.e. PP equals a 0), the port is non-functional and will not report attaches, detaches, etc. 
+// When an over-current condition is detected on a  powered port and PPC is a one, the PP bit in each affected port may be  transitioned by the host controller driver from a one to a zero (removing  power from the port). 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PP_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PP_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PP_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PP_RANGE                      12:12
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PP_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PP_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PP_NOT_POWERED                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PP_POWERED                    _MK_ENUM_CONST(1)
+
+// Line state. These bits reflect the current logical levels of the D+ (bit 10) and D- (bit 11) signal lines. The encoding of the bits are:
+// 00b = SE0 
+// 01b = J-state 
+// 10b = K-state 
+// 11b = Undefined 
+// The value of this field is undefined if Port  Power(PP) is zero in host mode. In host mode, the use  of line-state by the host controller driver is not necessary (unlike EHCI),  because the port controller state machine and the port routing manage the  connection of LS and FS. In device mode, the use of line-state by the device  controller driver is not necessary. 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_SHIFT                      _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_FIELD                      (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_RANGE                      11:10
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_SE0                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_J_STATE                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_K_STATE                    _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_LS_UNDEFINED                  _MK_ENUM_CONST(3)
+
+// When the bit is one, the host/device connected to the port is in high-speed mode and if set to zero, the host/device connected to the port is not in a high-speed mode. 
+// Note: HSP is redundant with PSPD(27:26). 
+// This bit is not defined in the EHCI specification.
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_HSP_SHIFT                     _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_HSP_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_HSP_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_HSP_RANGE                     9:9
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_HSP_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_HSP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_HSP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_HSP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_HSP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_HSP_NOT_HIGH_SPEED                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_HSP_HIGH_SPEED                        _MK_ENUM_CONST(1)
+
+// This field is zero if Port Power(PP) is zero. 
+// In Host Mode: Read/Write. 1=Port is in Reset. 0=Port is not in Reset.
+// When software writes a one to this bit the bus-reset sequence as defined in the USB Specification Revision 2.0 is started. This bit will automatically change to zero after the reset sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the reset duration is timed in the driver.  
+// In Device Mode: This bit is a read only status  bit. Device reset from the USB bus is also indicated in the USBSTS register. 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PR_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PR_RANGE                      8:8
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PR_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PR_NOT_USB_RESET                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PR_USB_RESET                  _MK_ENUM_CONST(1)
+
+// Port suspend. 1=Port in suspend state. 0=Port not in suspend state. 
+// In Host Mode: Read/Write. 
+// Port Enabled Bit and Suspend bit of this register define the port states as follows: 
+// Bits [Port Enabled, Suspend]    Port State 
+//        0x                        Disable 
+//   10                        Enable 
+//    11                        Suspend 
+// When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. The host controller will unconditionally set this bit to zero when software sets the Force Port Resume bit to zero. A write of zero to this bit is ignored by the host controller. If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit is a zero) the results are undefined. This field is zero if Port Power(PP) is zero in host mode.
+// In Device Mode: Read Only. This bit is a read only status bit. 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SUSP_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SUSP_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_SUSP_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SUSP_RANGE                    7:7
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SUSP_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SUSP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SUSP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SUSP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SUSP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SUSP_NOT_SUSPEND                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_SUSP_SUSPEND                  _MK_ENUM_CONST(1)
+
+// Force Port Resume. 1= Resume detected/driven on port. 0=No resume (K state) detected/driven on port. 
+// In Host Mode: 
+// Software sets this bit to one to drive resume signaling. The Host Controller sets this bit to one if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one.  This bit will automatically change to zero after the resume sequence is complete. This behavior is different from EHCI where the host controller driver is required to set this bit to a zero after the resume duration is timed in the driver. 
+// Note that when the Host controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains a one.  This bit remains a one until the port has switched to the high-speed idle.  Writing a zero has no effect because the port controller will time the resume operation to clear the bit when the port control state switches to HS or FS idle. This field is zero if Port Power(PP) is zero in host mode. This bit is not-EHCI compatible. 
+// In Device mode:  
+// After the device has been in Suspend State for 5ms or more, software must set this bit to one to drive resume signaling before clearing. The Device Controller will set this bit to one if a J-to-K transition is detected while the port is in the Suspend state. The bit will be cleared when the device returns to normal operation. Also, when this bit transitions to a one because a J-to-K transition is detected, the Port Change Detect bit in the USBSTS register is also set to one. 
+// Software should ensure that the PHY clock is operational before writing a 1 to this bit to start the resume sequence. This is true for both Device and Host modes.
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_FPR_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_FPR_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_FPR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_FPR_RANGE                     6:6
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_FPR_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_FPR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_FPR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_FPR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_FPR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_FPR_NO_RESUME                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_FPR_RESUME                    _MK_ENUM_CONST(1)
+
+// Over-current Change: Not supported
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCC_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCC_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCC_RANGE                     5:5
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCC_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCC_NO_CHANGE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCC_CHANGE                    _MK_ENUM_CONST(1)
+
+// Over-current Active: Not supported
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCA_SHIFT                     _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCA_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCA_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCA_RANGE                     4:4
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCA_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCA_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCA_NO_OVER_CURRENT                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_OCA_OVER_CURRENT                      _MK_ENUM_CONST(1)
+
+// Port Enable/Disable Change: 1=Port enabled/disabled status has changed. 0=No change.
+// In Host Mode: 
+// For the root hub, this bit gets set to a one only when a port is disabled due to disconnect on the port or due to the appropriate conditions existing at the EOF2 point (See Chapter 11 of the USB Specification). Software clears this by writing a one to it. This field is zero if Port Power(PP) is zero. 
+// In Device mode:  
+// The device port is always enabled. (This bit will  be zero) 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PEC_SHIFT                     _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PEC_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PEC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PEC_RANGE                     3:3
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PEC_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PEC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PEC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PEC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PEC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PEC_NO_CHANGE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PEC_CHANGE                    _MK_ENUM_CONST(1)
+
+// Port Enabled/Disabled: 1=Enable. 0=Disable (default)
+// In Host Mode: 
+// Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a one to this field. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by the host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events.  When the port is disabled, (0b) downstream propagation of data is blocked except for reset. This field is zero if Port Power(PP) is zero in host mode. 
+// In Device Mode: 
+// The device port is always enabled. (This bit will  be one) 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PE_SHIFT                      _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_PE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PE_RANGE                      2:2
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PE_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PE_PORT_DISABLED                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_PE_PORT_ENABLED                       _MK_ENUM_CONST(1)
+
+// Connect Status Change: 1 =Change in Current Connect Status. 0=No change (default) 
+// In Host Mode: 
+// Indicates a change has occurred in the port's Current Connect Status. The host/device controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be 'setting' an already-set bit (i.e., the bit will remain set).  Software clears this bit by writing a one to it. This field is zero if Port Power(PP) is zero in host mode. 
+// This bit is undefined in device controller mode. 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CSC_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CSC_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_CSC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CSC_RANGE                     1:1
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CSC_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CSC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CSC_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CSC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CSC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CSC_NO_CHANGE                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CSC_CHANGE                    _MK_ENUM_CONST(1)
+
+// Current Connect Status: 
+// In Host Mode: 1=Device is present on port.                0=No device is present (default) 
+// This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is zero if Port Power(PP) is zero in host mode. 
+// In Device Mode: 1=Attached                    0=Not Attached (default) 
+// A one indicates that the device successfully attached and is operating in either high speed or full speed as indicated by the High Speed Port bit in this register. A zero indicates that the device did not attach successfully or was forcibly disconnected by the software writing a zero to the Run bit in the USBCMD register. It does not state the device being disconnected or suspended. 
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CCS_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CCS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_PORTSC1_0_CCS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CCS_RANGE                     0:0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CCS_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CCS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CCS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CCS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CCS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CCS_NOT_CONNECTED                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_PORTSC1_0_CCS_CONNECTED                 _MK_ENUM_CONST(1)
+
+
+// Reserved address 416 [0x1a0] 
+
+// Register USB2_CONTROLLER_2_USB2D_OTGSC_0  
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0                 _MK_ADDR_CONST(0x1a4)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_SECURE                  0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_RESET_MASK                      _MK_MASK_CONST(0x7f7f7f3b)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_READ_MASK                       _MK_MASK_CONST(0x7f7f7f3b)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_WRITE_MASK                      _MK_MASK_CONST(0x7f7f003b)
+// Data Pulse Interrupt Enable. Setting this bit enables the Data pulse interrupt.
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIE_SHIFT                      _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIE_RANGE                      30:30
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIE_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIE_ENABLE                     _MK_ENUM_CONST(1)
+
+// 1 millisecond timer Interrupt enable. Setting this bit enables the 1 millisecond timer  interrupt.
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSE_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSE_RANGE                    29:29
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSE_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSE_ENABLE                   _MK_ENUM_CONST(1)
+
+// B Session End Interrupt Enable. Setting this bit enables the B session end  interrupt
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIE_SHIFT                     _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIE_RANGE                     28:28
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// B Session Valid Interrupt Enable. Setting this bit enables the B session valid  interrupt
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIE_SHIFT                     _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIE_RANGE                     27:27
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// A Session Valid Interrupt Enable. Setting this bit enables the A session valid  interrupt
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIE_SHIFT                     _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIE_RANGE                     26:26
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// A VBus Valid Interrupt Enable. Setting this bit enables the A VBus valid  interrupt
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIE_SHIFT                     _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIE_RANGE                     25:25
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIE_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIE_ENABLE                    _MK_ENUM_CONST(1)
+
+// USB ID Interrupt Enable. Setting this bit enables the USB ID interrupt
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIE_SHIFT                      _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIE_RANGE                      24:24
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIE_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIE_DISABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIE_ENABLE                     _MK_ENUM_CONST(1)
+
+// Data Pulse Interrupt Status. This bit is set when data bus pulsing occurs on DP or DM.  Data bus pulsing is only detected when USBMODE.CM = Host (11) and PORTSC(0).PortPower = Off (0). Software writes a 1 to clear this bit.
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIS_SHIFT                      _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIS_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIS_RANGE                      22:22
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIS_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIS_INT_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPIS_INT_SET                    _MK_ENUM_CONST(1)
+
+// 1 millisecond timer Interrupt Status: This bit is set once every millisecond. Software  writes a 1 to clear it.
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSS_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSS_RANGE                    21:21
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSS_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSS_INT_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMSS_INT_SET                  _MK_ENUM_CONST(1)
+
+// B Session End Interrupt Status. This bit is set when VBus has fallen below the B  session end threshold. Software writes a 1 to clear this bit .
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIS_SHIFT                     _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIS_RANGE                     20:20
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIS_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIS_INT_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSEIS_INT_SET                   _MK_ENUM_CONST(1)
+
+// B Session Valid Interrupt Status. This bit is set when VBus has either risen above  or fallen below the B session valid threshold (0.8 VDC). Software writes a 1  to clear this bit. 
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIS_SHIFT                     _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIS_RANGE                     19:19
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIS_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIS_INT_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSVIS_INT_SET                   _MK_ENUM_CONST(1)
+
+// A Session Valid Interrupt Status. This bit is set when VBus has either risen above  or fallen below the A session valid threshold (0.8 VDC). Software writes a  one to clear this bit. 
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIS_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIS_RANGE                     18:18
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIS_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIS_INT_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASVIS_INT_SET                   _MK_ENUM_CONST(1)
+
+// A VBus Valid Interrupt Status. This bit is set when VBus has either risen above  or fallen below the VBus valid threshold (4.4 VDC) on an A device. Software  writes a 1 to clear this bit. 
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIS_SHIFT                     _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIS_RANGE                     17:17
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIS_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIS_INT_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVVIS_INT_SET                   _MK_ENUM_CONST(1)
+
+// USB ID Interrupt Status. This bit is set when a change on the ID input has been detected. Software writes a 1 to clear this bit. 
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIS_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIS_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIS_RANGE                      16:16
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIS_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIS_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIS_INT_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDIS_INT_SET                    _MK_ENUM_CONST(1)
+
+// Data Bus Pulsing Status. A 1 indicates data bus pulsing is being detected  on the port. 
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPS_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPS_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_DPS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPS_RANGE                       14:14
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPS_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPS_STS_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DPS_STS_SET                     _MK_ENUM_CONST(1)
+
+// 1 millisecond timer toggle. This bit toggles once per millisecond
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMST_SHIFT                    _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMST_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMST_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMST_RANGE                    13:13
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMST_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMST_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMST_STS_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ONEMST_STS_SET                  _MK_ENUM_CONST(1)
+
+// B session End. Indicates VBus is below the B session end  threshold
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSE_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_BSE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSE_RANGE                       12:12
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSE_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSE_STS_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSE_STS_SET                     _MK_ENUM_CONST(1)
+
+// B Session Valid. Indicates VBus is above the B session valid  threshold
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSV_SHIFT                       _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSV_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_BSV_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSV_RANGE                       11:11
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSV_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSV_STS_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_BSV_STS_SET                     _MK_ENUM_CONST(1)
+
+// A Session Valid. Indicates VBus is above the A session valid  threshold
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASV_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASV_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_ASV_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASV_RANGE                       10:10
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASV_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASV_STS_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ASV_STS_SET                     _MK_ENUM_CONST(1)
+
+// A VBus Valid. Indicates VBus is above the A VBus valid threshold
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVV_SHIFT                       _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVV_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_AVV_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVV_RANGE                       9:9
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVV_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVV_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVV_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVV_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVV_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVV_STS_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_AVV_STS_SET                     _MK_ENUM_CONST(1)
+
+// USB ID: 0 = A-device  1 = B-device
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ID_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ID_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_ID_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ID_RANGE                        8:8
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ID_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ID_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ID_A_DEV                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_ID_B_DEV                        _MK_ENUM_CONST(1)
+
+// USB ID Pullup
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDPU_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDPU_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_IDPU_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDPU_RANGE                      5:5
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDPU_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDPU_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDPU_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDPU_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDPU_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDPU_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_IDPU_SET                        _MK_ENUM_CONST(1)
+
+// Data Pulsing. Setting this bit causes the pull-up on DP to be  asserted for data pulsing during SRP. 
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DP_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DP_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_DP_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DP_RANGE                        4:4
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DP_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DP_NO_DATA_PULSE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_DP_DATA_PULSE                   _MK_ENUM_CONST(1)
+
+// OTG Termination. This bit must be set when the OTG device is in device mode, this controls the pulldown on DM. 
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_OT_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_OT_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_OT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_OT_RANGE                        3:3
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_OT_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_OT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_OT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_OT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_OT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_OT_NO_OTG_TERM                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_OT_OTG_TERM                     _MK_ENUM_CONST(1)
+
+// VBUS Charge. Setting this bit causes the VBus line to be  charged. This is used for VBus pulsing during SRP. 
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VC_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VC_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_VC_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VC_RANGE                        1:1
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VC_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VC_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VC_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VC_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VC_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VC_NO_VBUS_CHRG                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VC_VBUS_CHRG                    _MK_ENUM_CONST(1)
+
+// VBUS_Discharge. Read/write. Setting this bit  causes Vbus to discharge through a resistor. 
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VD_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VD_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_OTGSC_0_VD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VD_RANGE                        0:0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VD_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VD_NO_VBUS_DISCHRG                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_OTGSC_0_VD_VBUS_DISCHRG                 _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_USBMODE_0  
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0                       _MK_ADDR_CONST(0x1a8)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SECURE                        0x0
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_WORD_COUNT                    0x1
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_RESET_MASK                    _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Stream disbable: 1 Streaming is disabled - helpful to avoid overrun/underruns when system load is too high.
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SDIS_SHIFT                    _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SDIS_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBMODE_0_SDIS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SDIS_RANGE                    4:4
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SDIS_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SDIS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SDIS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SDIS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SDIS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SDIS_STREAM_ENABLE                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SDIS_STREAM_DISABLE                   _MK_ENUM_CONST(1)
+
+// Setup Lockout Mode:
+// In device mode, this bit controls the behavior of the setup lockout mechanism.
+// 0 - Setup lockout is ON (default)
+// 1  Setup lockout is OFF. Firmware requires the  use of setup tripwire semaphore in USB2D_USBCMD register.
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SLOM_SHIFT                    _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SLOM_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBMODE_0_SLOM_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SLOM_RANGE                    3:3
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SLOM_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SLOM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SLOM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SLOM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SLOM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SLOM_LOCKOUT_OFF                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_SLOM_LOCKOUT_ON                       _MK_ENUM_CONST(1)
+
+// Endian Select: Note: For this implementation, this should be  always set to 0 (little endian).
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_ES_SHIFT                      _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_ES_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_USBMODE_0_ES_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_ES_RANGE                      2:2
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_ES_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_ES_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_ES_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_ES_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_ES_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_ES_LITTLE_ENDIAN                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_ES_RESERVED                   _MK_ENUM_CONST(1)
+
+// Controller Mode: The controller mode will default to an idle state and will need to be initialized to the desired operating mode after reset. This register can only be written once after reset. If it is necessary to switch modes, software must reset the controller by writing to the RESET bit in the USBCMD register before reprogramming this register. 
+// 00 = Idle [Default] 
+// 01 = Reserved 
+// 10 = Device Controller  
+// 11 = Host Controller 
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_FIELD                      (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_RANGE                      1:0
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_IDLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_RESERVED                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_DEVICE_MODE                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_USBMODE_0_CM_HOST_MODE                  _MK_ENUM_CONST(3)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0                        _MK_ADDR_CONST(0x1ac)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_SECURE                         0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_WORD_COUNT                     0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_RESET_MASK                     _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_READ_MASK                      _MK_MASK_CONST(0xffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_WRITE_MASK                     _MK_MASK_CONST(0xffff)
+// Endpoint 15 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SHIFT                 _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_RANGE                 15:15
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT15_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 14 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SHIFT                 _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_RANGE                 14:14
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT14_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 13 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SHIFT                 _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_RANGE                 13:13
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT13_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 12 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SHIFT                 _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_RANGE                 12:12
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT12_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 11 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SHIFT                 _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_RANGE                 11:11
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT11_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 10 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SHIFT                 _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_RANGE                 10:10
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_NOT_RCVD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT10_SETUP_RCVD                    _MK_ENUM_CONST(1)
+
+// Endpoint 9 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SHIFT                  _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_RANGE                  9:9
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT9_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 8 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_RANGE                  8:8
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT8_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 7 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_RANGE                  7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT7_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 6 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_RANGE                  6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT6_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 5 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_RANGE                  5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT5_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 4 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SHIFT                  _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_RANGE                  4:4
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT4_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 3 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_RANGE                  3:3
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT3_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 2 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_RANGE                  2:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT2_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 1 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_RANGE                  1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT1_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+// Endpoint 0 Setup Status:
+// For every setup transaction that is received, this bit is set to 1. Software must clear or acknowledge the setup transfer by writing a 1 to it after it has read the setup data from Queue head. The response to a setup packet (as in the order of operations and total response time) is crucial to limit bus time-outs while the setup lock-out mechanism is engaged. 
+//  This register is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_RANGE                  0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_NOT_RCVD                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0_ENDPTSETUPSTAT0_SETUP_RCVD                     _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0                    _MK_ADDR_CONST(0x1b0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB15_SHIFT                       _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB15_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB15_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB15_RANGE                       31:31
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB15_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB15_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB15_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB14_SHIFT                       _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB14_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB14_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB14_RANGE                       30:30
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB14_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB14_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB14_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB13_SHIFT                       _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB13_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB13_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB13_RANGE                       29:29
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB13_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB13_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB13_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB12_SHIFT                       _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB12_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB12_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB12_RANGE                       28:28
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB12_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB12_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB12_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB11_SHIFT                       _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB11_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB11_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB11_RANGE                       27:27
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB11_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB11_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB11_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB10_SHIFT                       _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB10_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB10_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB10_RANGE                       26:26
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB10_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB10_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB10_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB9_SHIFT                        _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB9_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB9_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB9_RANGE                        25:25
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB9_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB9_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB9_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB8_SHIFT                        _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB8_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB8_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB8_RANGE                        24:24
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB8_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB8_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB8_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB7_SHIFT                        _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB7_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB7_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB7_RANGE                        23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB7_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB7_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB7_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB6_SHIFT                        _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB6_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB6_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB6_RANGE                        22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB6_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB6_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB6_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB5_SHIFT                        _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB5_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB5_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB5_RANGE                        21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB5_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB5_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB5_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB4_SHIFT                        _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB4_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB4_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB4_RANGE                        20:20
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB4_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB4_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB4_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB3_SHIFT                        _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB3_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB3_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB3_RANGE                        19:19
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB3_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB3_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB3_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB2_SHIFT                        _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB2_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB2_RANGE                        18:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB2_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB2_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB2_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB1_SHIFT                        _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB1_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB1_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB1_RANGE                        17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB1_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB1_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB1_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Transmit Buffer:
+// This bit is used to request that a buffer prepared for a transmit operation in order to respond to a USB IN/INTERRUPT transaction on this endpiont. Software should write a "1" to this bit when posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a transmit buffer. Hardware will clear this bit when this endpoint is successfully primed.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB0_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB0_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB0_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB0_RANGE                        16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB0_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB0_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PETB0_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB15_SHIFT                       _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB15_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB15_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB15_RANGE                       15:15
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB15_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB15_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB15_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB14_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB14_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB14_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB14_RANGE                       14:14
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB14_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB14_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB14_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB13_SHIFT                       _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB13_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB13_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB13_RANGE                       13:13
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB13_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB13_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB13_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB12_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB12_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB12_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB12_RANGE                       12:12
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB12_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB12_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB12_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB11_SHIFT                       _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB11_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB11_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB11_RANGE                       11:11
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB11_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB11_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB11_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB10_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB10_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB10_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB10_RANGE                       10:10
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB10_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB10_DONT_PRIME                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB10_PRIME                       _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB9_SHIFT                        _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB9_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB9_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB9_RANGE                        9:9
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB9_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB9_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB9_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB8_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB8_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB8_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB8_RANGE                        8:8
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB8_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB8_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB8_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB7_SHIFT                        _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB7_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB7_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB7_RANGE                        7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB7_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB7_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB7_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB6_SHIFT                        _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB6_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB6_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB6_RANGE                        6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB6_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB6_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB6_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB5_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB5_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB5_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB5_RANGE                        5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB5_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB5_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB5_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB4_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB4_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB4_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB4_RANGE                        4:4
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB4_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB4_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB4_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB3_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB3_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB3_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB3_RANGE                        3:3
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB3_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB3_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB3_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB2_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB2_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB2_RANGE                        2:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB2_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB2_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB2_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB1_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB1_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB1_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB1_RANGE                        1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB1_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB1_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB1_PRIME                        _MK_ENUM_CONST(1)
+
+// Prime Endpoint Receive Buffer:
+// This bit is used to request that a buffer prepared for a receive operation when a USB host initiates a USB OUT transaction to this endpoint. Software should write a one to this bit whenever posting a new transfer descriptor to this endpoint. Hardware will automatically use this bit to begin parsing for a new transfer descriptor from the queue head and prepare a receive buffer. Hardware will clear this bit when this endpoint is successfully primed. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB0_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB0_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB0_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB0_RANGE                        0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB0_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB0_DONT_PRIME                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0_PERB0_PRIME                        _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0                    _MK_ADDR_CONST(0x1b4)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB15_SHIFT                       _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB15_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB15_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB15_RANGE                       31:31
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB15_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB15_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB15_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB14_SHIFT                       _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB14_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB14_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB14_RANGE                       30:30
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB14_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB14_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB14_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB13_SHIFT                       _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB13_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB13_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB13_RANGE                       29:29
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB13_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB13_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB13_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB12_SHIFT                       _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB12_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB12_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB12_RANGE                       28:28
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB12_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB12_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB12_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB11_SHIFT                       _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB11_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB11_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB11_RANGE                       27:27
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB11_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB11_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB11_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB10_SHIFT                       _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB10_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB10_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB10_RANGE                       26:26
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB10_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB10_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB10_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB9_SHIFT                        _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB9_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB9_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB9_RANGE                        25:25
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB9_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB9_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB9_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB8_SHIFT                        _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB8_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB8_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB8_RANGE                        24:24
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB8_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB8_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB8_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB7_SHIFT                        _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB7_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB7_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB7_RANGE                        23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB7_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB7_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB7_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB6_SHIFT                        _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB6_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB6_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB6_RANGE                        22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB6_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB6_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB6_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB5_SHIFT                        _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB5_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB5_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB5_RANGE                        21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB5_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB5_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB5_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB4_SHIFT                        _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB4_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB4_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB4_RANGE                        20:20
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB4_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB4_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB4_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB3_SHIFT                        _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB3_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB3_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB3_RANGE                        19:19
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB3_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB3_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB3_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Transmit Buffer: 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB2_SHIFT                        _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB2_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB2_RANGE                        18:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB2_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB2_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB2_FLUSH                        _MK_ENUM_CONST(1)
+
+// 
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB1_SHIFT                        _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB1_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB1_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB1_RANGE                        17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB1_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB1_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB1_FLUSH                        _MK_ENUM_CONST(1)
+
+//
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB0_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB0_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB0_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB0_RANGE                        16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB0_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB0_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FETB0_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB15_SHIFT                       _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB15_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB15_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB15_RANGE                       15:15
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB15_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB15_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB15_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB15_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB15_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB15_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB15_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB14_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB14_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB14_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB14_RANGE                       14:14
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB14_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB14_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB14_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB14_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB14_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB14_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB14_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB13_SHIFT                       _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB13_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB13_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB13_RANGE                       13:13
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB13_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB13_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB13_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB13_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB13_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB13_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB13_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB12_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB12_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB12_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB12_RANGE                       12:12
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB12_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB12_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB12_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB12_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB12_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB12_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB12_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB11_SHIFT                       _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB11_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB11_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB11_RANGE                       11:11
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB11_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB11_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB11_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB11_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB11_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB11_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB11_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB10_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB10_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB10_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB10_RANGE                       10:10
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB10_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB10_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB10_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB10_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB10_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB10_DONT_FLUSH                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB10_FLUSH                       _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB9_SHIFT                        _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB9_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB9_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB9_RANGE                        9:9
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB9_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB9_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB9_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB9_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB9_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB9_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB9_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB8_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB8_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB8_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB8_RANGE                        8:8
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB8_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB8_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB8_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB8_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB8_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB8_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB8_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB7_SHIFT                        _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB7_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB7_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB7_RANGE                        7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB7_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB7_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB7_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB7_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB7_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB7_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB7_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB6_SHIFT                        _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB6_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB6_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB6_RANGE                        6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB6_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB6_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB6_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB6_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB6_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB6_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB6_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB5_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB5_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB5_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB5_RANGE                        5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB5_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB5_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB5_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB5_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB5_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB5_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB5_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB4_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB4_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB4_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB4_RANGE                        4:4
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB4_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB4_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB4_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB4_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB4_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB4_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB4_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB3_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB3_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB3_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB3_RANGE                        3:3
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB3_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB3_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB3_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB3_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB3_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB3_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB3_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB2_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB2_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB2_RANGE                        2:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB2_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB2_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB2_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB1_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB1_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB1_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB1_RANGE                        1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB1_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB1_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB1_FLUSH                        _MK_ENUM_CONST(1)
+
+// Flush Endpoint Receive Buffer:
+// Writing a one to this bit causes the associated endpoint to clear any primed buffers. If a packet is in progress for the associated endpoint that transfer will continue until completion. Hardware clears this register after the endpoint flush operation is successful. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB0_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB0_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB0_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB0_RANGE                        0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB0_WOFFSET                      0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB0_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB0_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB0_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB0_DONT_FLUSH                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0_FERB0_FLUSH                        _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0                   _MK_ADDR_CONST(0x1b8)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_SECURE                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR15_SHIFT                      _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR15_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR15_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR15_RANGE                      31:31
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR15_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR15_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR15_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR15_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR15_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR15_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR15_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR14_SHIFT                      _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR14_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR14_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR14_RANGE                      30:30
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR14_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR14_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR14_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR14_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR14_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR13_SHIFT                      _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR13_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR13_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR13_RANGE                      29:29
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR13_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR13_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR13_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR13_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR13_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR12_SHIFT                      _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR12_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR12_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR12_RANGE                      28:28
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR12_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR12_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR12_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR12_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR12_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR11_SHIFT                      _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR11_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR11_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR11_RANGE                      27:27
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR11_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR11_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR11_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR11_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR11_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR10_SHIFT                      _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR10_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR10_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR10_RANGE                      26:26
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR10_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR10_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR10_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR10_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR10_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR9_SHIFT                       _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR9_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR9_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR9_RANGE                       25:25
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR9_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR9_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR9_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR9_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR9_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR8_SHIFT                       _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR8_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR8_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR8_RANGE                       24:24
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR8_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR8_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR8_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR8_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR8_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR7_SHIFT                       _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR7_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR7_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR7_RANGE                       23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR7_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR7_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR7_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR6_SHIFT                       _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR6_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR6_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR6_RANGE                       22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR6_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR6_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR6_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR5_SHIFT                       _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR5_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR5_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR5_RANGE                       21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR5_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR5_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR5_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR4_SHIFT                       _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR4_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR4_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR4_RANGE                       20:20
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR4_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR4_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR4_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR3_SHIFT                       _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR3_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR3_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR3_RANGE                       19:19
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR3_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR3_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR3_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR2_SHIFT                       _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR2_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR2_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR2_RANGE                       18:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR2_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR2_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR2_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR1_SHIFT                       _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR1_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR1_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR1_RANGE                       17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR1_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR1_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR1_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR0_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR0_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR0_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR0_RANGE                       16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR0_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR0_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ETBR0_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR15_SHIFT                      _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR15_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR15_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR15_RANGE                      15:15
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR15_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR15_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR15_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR15_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR15_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR15_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR15_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR14_SHIFT                      _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR14_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR14_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR14_RANGE                      14:14
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR14_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR14_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR14_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR14_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR14_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR14_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR14_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR13_SHIFT                      _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR13_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR13_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR13_RANGE                      13:13
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR13_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR13_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR13_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR13_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR13_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR13_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR13_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR12_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR12_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR12_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR12_RANGE                      12:12
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR12_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR12_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR12_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR12_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR12_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR12_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR12_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR11_SHIFT                      _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR11_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR11_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR11_RANGE                      11:11
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR11_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR11_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR11_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR11_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR11_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR11_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR11_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR10_SHIFT                      _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR10_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR10_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR10_RANGE                      10:10
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR10_WOFFSET                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR10_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR10_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR10_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR10_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR10_NOT_READY                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR10_READY                      _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR9_SHIFT                       _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR9_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR9_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR9_RANGE                       9:9
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR9_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR9_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR9_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR9_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR9_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR9_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR9_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR8_SHIFT                       _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR8_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR8_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR8_RANGE                       8:8
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR8_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR8_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR8_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR8_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR8_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR8_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR8_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR7_SHIFT                       _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR7_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR7_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR7_RANGE                       7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR7_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR7_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR7_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR7_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR7_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR7_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR7_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR6_SHIFT                       _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR6_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR6_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR6_RANGE                       6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR6_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR6_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR6_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR6_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR6_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR6_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR6_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR5_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR5_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR5_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR5_RANGE                       5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR5_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR5_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR5_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR5_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR5_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR5_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR5_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR4_SHIFT                       _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR4_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR4_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR4_RANGE                       4:4
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR4_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR4_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR4_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR4_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR4_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR4_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR4_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR3_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR3_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR3_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR3_RANGE                       3:3
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR3_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR3_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR3_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR3_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR3_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR3_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR3_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR2_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR2_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR2_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR2_RANGE                       2:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR2_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR2_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR2_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR2_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR2_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR2_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR2_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR1_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR1_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR1_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR1_RANGE                       1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR1_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR1_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR1_READY                       _MK_ENUM_CONST(1)
+
+// Endpoint Receive Buffer Ready:
+// One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set to a one by the hardware as a response to receiving a command from a corresponding bit in the ENDPTPRIME register. There will always be a delay between setting a bit in the ENDPTPRIME register and endpoint indicating ready. This delay ime varies based upon the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR0_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR0_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR0_RANGE                       0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR0_WOFFSET                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR0_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR0_NOT_READY                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0_ERBR0_READY                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0                 _MK_ADDR_CONST(0x1bc)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_SECURE                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_WORD_COUNT                      0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE15_SHIFT                    _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE15_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE15_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE15_RANGE                    31:31
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE15_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE15_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE15_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE15_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE14_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE14_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE14_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE14_RANGE                    30:30
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE14_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE14_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE14_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE14_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE13_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE13_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE13_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE13_RANGE                    29:29
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE13_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE13_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE13_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE13_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE12_SHIFT                    _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE12_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE12_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE12_RANGE                    28:28
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE12_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE12_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE12_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE12_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE11_SHIFT                    _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE11_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE11_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE11_RANGE                    27:27
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE11_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE11_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE11_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE11_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE10_SHIFT                    _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE10_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE10_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE10_RANGE                    26:26
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE10_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE10_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE10_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE10_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE9_SHIFT                     _MK_SHIFT_CONST(25)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE9_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE9_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE9_RANGE                     25:25
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE9_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE9_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE9_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE9_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE8_SHIFT                     _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE8_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE8_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE8_RANGE                     24:24
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE8_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE8_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE8_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE8_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE7_SHIFT                     _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE7_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE7_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE7_RANGE                     23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE7_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE7_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE7_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE6_SHIFT                     _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE6_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE6_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE6_RANGE                     22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE6_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE6_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE6_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE5_SHIFT                     _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE5_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE5_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE5_RANGE                     21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE5_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE5_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE5_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE4_SHIFT                     _MK_SHIFT_CONST(20)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE4_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE4_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE4_RANGE                     20:20
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE4_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE4_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE4_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE3_SHIFT                     _MK_SHIFT_CONST(19)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE3_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE3_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE3_RANGE                     19:19
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE3_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE3_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE3_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE2_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE2_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE2_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE2_RANGE                     18:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE2_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE2_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE2_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE1_SHIFT                     _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE1_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE1_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE1_RANGE                     17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE1_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE1_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE1_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Transmit Complete Event:
+// Each bit indicates a transmit event (IN/INTERRUPT) occurred and software should read the corresponding endpoint queue to determine the endpoint status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register. 
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE0_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE0_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE0_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE0_RANGE                     16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE0_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE0_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ETCE0_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE15_SHIFT                    _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE15_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE15_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE15_RANGE                    15:15
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE15_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE15_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE15_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE15_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE15_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE15_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE15_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE14_SHIFT                    _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE14_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE14_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE14_RANGE                    14:14
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE14_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE14_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE14_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE14_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE14_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE14_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE14_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE13_SHIFT                    _MK_SHIFT_CONST(13)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE13_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE13_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE13_RANGE                    13:13
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE13_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE13_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE13_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE13_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE13_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE13_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE13_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE12_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE12_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE12_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE12_RANGE                    12:12
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE12_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE12_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE12_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE12_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE12_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE12_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE12_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE11_SHIFT                    _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE11_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE11_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE11_RANGE                    11:11
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE11_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE11_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE11_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE11_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE11_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE11_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE11_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE10_SHIFT                    _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE10_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE10_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE10_RANGE                    10:10
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE10_WOFFSET                  0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE10_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE10_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE10_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE10_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE10_NOT_COMPLETE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE10_COMPLETE                 _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE9_SHIFT                     _MK_SHIFT_CONST(9)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE9_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE9_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE9_RANGE                     9:9
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE9_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE9_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE9_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE9_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE9_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE9_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE9_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE8_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE8_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE8_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE8_RANGE                     8:8
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE8_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE8_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE8_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE8_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE8_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE8_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE8_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE7_SHIFT                     _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE7_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE7_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE7_RANGE                     7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE7_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE7_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE7_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE7_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE7_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE7_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE7_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE6_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE6_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE6_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE6_RANGE                     6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE6_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE6_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE6_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE5_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE5_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE5_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE5_RANGE                     5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE5_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE5_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE5_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE4_SHIFT                     _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE4_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE4_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE4_RANGE                     4:4
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE4_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE4_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE4_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE3_SHIFT                     _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE3_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE3_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE3_RANGE                     3:3
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE3_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE3_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE3_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE2_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE2_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE2_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE2_RANGE                     2:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE2_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE2_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE2_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE1_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE1_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE1_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE1_RANGE                     1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE1_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE1_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE1_COMPLETE                  _MK_ENUM_CONST(1)
+
+// Endpoint Receive Complete Event:
+// Each bit indicates a received event (OUT/SETUP) occurred and software should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set simultaneously with the USBINT. Writing a one clears the corresponding bit in this register.
+// This is only used in device mode.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE0_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE0_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE0_RANGE                     0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE0_WOFFSET                   0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE0_NOT_COMPLETE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0_ERCE0_COMPLETE                  _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0                    _MK_ADDR_CONST(0x1c0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RESET_VAL                  _MK_MASK_CONST(0x800080)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RESET_MASK                         _MK_MASK_CONST(0x8d008d)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_READ_MASK                  _MK_MASK_CONST(0x8d008d)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// TX Endpoint Enable. Endpoint 0 is always  enabled. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Endpoint Type. Endpoint0 is fixed as a Control Endpoint. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// TX Endpoint Stall: Software can write a one to this bit to force the  endpoint to return a STALL handshake to the Host. It will continue returning  STALL until the bit is cleared by software or it will automatically be  cleared upon receipt of a new SETUP request. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+//  RX Endpoint Enable. Endpoint 0 is always  enabled. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Endpoint Type. Endpoint 0 is fixed as a Control Endpoint. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// RX Endpoint Stall: Software can write a one to this bit to force the  endpoint to return a STALL handshake to the Host. It will continue returning  STALL until the bit is cleared by software or it will automatically be  cleared upon receipt of a new SETUP request. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0                    _MK_ADDR_CONST(0x1c4)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above, 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0                    _MK_ADDR_CONST(0x1c8)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0                    _MK_ADDR_CONST(0x1cc)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0                    _MK_ADDR_CONST(0x1d0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0                    _MK_ADDR_CONST(0x1d4)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0                    _MK_ADDR_CONST(0x1d8)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0                    _MK_ADDR_CONST(0x1dc)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0                    _MK_ADDR_CONST(0x1e0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0                    _MK_ADDR_CONST(0x1e4)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_SECURE                     0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_WORD_COUNT                         0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RESET_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_READ_MASK                  _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_WRITE_MASK                         _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXE_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXE_RANGE                  23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXR_SHIFT                  _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXR_RANGE                  22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXI_SHIFT                  _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXI_RANGE                  21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_RANGE                  19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXD_SHIFT                  _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXD_RANGE                  17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXS_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXS_RANGE                  16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_TXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXE_RANGE                  7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXE_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXE_DISABLE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXE_ENABLE                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXR_RANGE                  6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXR_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXR_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXR_KEEP_GOING                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXR_RESET_PID_SEQ                  _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXI_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXI_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXI_RANGE                  5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXI_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXI_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXI_DIS_PID_SEQ                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXI_ENB_PID_SEQ                    _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_RANGE                  3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_CTRL                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_ISO                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_BULK                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXT_INTR                   _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXD_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXD_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXD_RANGE                  1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXD_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXS_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXS_RANGE                  0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXS_WOFFSET                        0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXS_EP_OK                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0_RXS_EP_STALL                       _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0                   _MK_ADDR_CONST(0x1e8)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_SECURE                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0                   _MK_ADDR_CONST(0x1ec)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_SECURE                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0                   _MK_ADDR_CONST(0x1f0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_SECURE                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0                   _MK_ADDR_CONST(0x1f4)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_SECURE                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0                   _MK_ADDR_CONST(0x1f8)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_SECURE                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Register USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0  
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0                   _MK_ADDR_CONST(0x1fc)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_SECURE                    0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_WORD_COUNT                        0x1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RESET_MASK                        _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_READ_MASK                         _MK_MASK_CONST(0xef00ef)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_WRITE_MASK                        _MK_MASK_CONST(0xed00ed)
+// TX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXE_SHIFT                 _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXE_RANGE                 23:23
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// TX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint software must write a one to this bit in order to synchronize  the data PIDs between the Host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXR_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXR_RANGE                 22:22
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// TX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always transmit DATA0 for a data packet. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXI_SHIFT                 _MK_SHIFT_CONST(21)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXI_RANGE                 21:21
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// TX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_RANGE                 19:18
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXD_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXD_RANGE                 17:17
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// TX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt of a SETUP request if this  Endpoint is configured as a Control Endpoint. Software can write a one to  this bit to force the endpoint to return a STALL handshake to the Host. It  will continue to returning STALL until this bit is either cleared by software  or automatically cleared as above. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXS_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXS_RANGE                 16:16
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_TXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+// RX Endpoint Enable. An Endpoint should be enabled only after it has  been configured. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXE_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXE_RANGE                 7:7
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXE_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXE_DISABLE                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXE_ENABLE                        _MK_ENUM_CONST(1)
+
+// RX Data Toggle Reset: Whenever a configuration event is received for  this Endpoint, software must write a one to this bit in order to synchronize  the data PIDs between the host and device. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXR_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXR_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXR_RANGE                 6:6
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXR_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXR_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXR_KEEP_GOING                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXR_RESET_PID_SEQ                 _MK_ENUM_CONST(1)
+
+// RX Data Toggle Inhibit: This bit is only used for test and should always  be written as zero. Writing a one to this bit will cause this endpoint to  ignore the data toggle sequence and always accept data packet regardless of  their data PID. 
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXI_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXI_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXI_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXI_RANGE                 5:5
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXI_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXI_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXI_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXI_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXI_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXI_DIS_PID_SEQ                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXI_ENB_PID_SEQ                   _MK_ENUM_CONST(1)
+
+// RX Endpoint Type:
+// 00 = Control    01 = Isochronous                10 = Bulk               11 = Interrupt
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_RANGE                 3:2
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_CTRL                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_ISO                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_BULK                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXT_INTR                  _MK_ENUM_CONST(3)
+
+// This is fixed to 0.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXD_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXD_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXD_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXD_RANGE                 1:1
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXD_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXD_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXD_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXD_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXD_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// RX Endpoint Stall: This bit will be set automatically upon receipt of  a SETUP request if this Endpoint is not configured as a Control Endpoint. It  will be cleared automatically upon receipt a SETUP request if this Endpoint  is configured as a Control Endpoint, Software can write a one to this bit to  force the endpoint to return a STALL handshake to the Host. It will continue  to returning STALL until this bit is either cleared by software or  automatically cleared as above.
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXS_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXS_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXS_SHIFT)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXS_RANGE                 0:0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXS_WOFFSET                       0x0
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXS_EP_OK                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0_RXS_EP_STALL                      _MK_ENUM_CONST(1)
+
+
+// Packet USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_ROW                      0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_NON_ISO_IS_0                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_MULTI_1                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_MULT_2                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULT_MULTI_3                  _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_SHIFT                     _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_RANGE                     _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_ROW                       0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_ZERO_LENGTH_TERM_ENABLED                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ZLT_ZERO_LENGTH_TERM_DISABLED                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_SHIFT                     _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_RANGE                     _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_0_ROW                       0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_FIELD                       (_MK_MASK_CONST(0x7ff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_RANGE                       _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MAX_PACKET_LENGTH_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_SHIFT                     _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_ROW                       0
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOS_ENABLE                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_FIELD                     (_MK_MASK_CONST(0x7fff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED0_1_ROW                       0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_FIELD                 (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_RANGE                 _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_CURRENT_DTD_PTR_ROW                   1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_FIELD                     (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED1_0_ROW                       1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_FIELD                    (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_NEXT_DTD_PTR_ROW                      2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_FIELD                     (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED2_0_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_ROW                 2
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TERMINATE_SET                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT                     _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_FIELD                     (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TOTAL_BYTES_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_SHIFT                     _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_ROW                       3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_IOC_ENABLE                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_FIELD                     (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_RANGE                     _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_0_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_SHIFT                     _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_ROW                       3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_DISABLE                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_MULTIPLIER_OVERRIDE_ENABLE                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_FIELD                     (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_RANGE                     _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_1_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_ROW                    3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_ACTIVE_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_RANGE                  _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_ROW                    3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_HALTED_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_RANGE                       _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_ROW                 3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SET                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_SHIFT                     _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_RANGE                     _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_2_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_RANGE                       _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_ROW                 3
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_CLEAR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_TRANSACTION_ERROR_SET                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_FIELD                     (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_RANGE                     _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED3_3_ROW                       3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE0_ROW                     4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_FIELD                      (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_OFFSET_ROW                        4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE1_ROW                     5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED5_0_ROW                       5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE2_ROW                     6
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED6_0_ROW                       6
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE3_ROW                     7
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED7_0_ROW                       7
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT                   _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_FIELD                   (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_BUF_PTR_PAGE4_ROW                     8
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED8_0_ROW                       8
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_RESERVED9_0_ROW                       9
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES3_0_ROW                        10
+
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_QUEUE_HEAD_0_SETUP_BUF_BYTES7_4_ROW                        11
+
+
+// Packet USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_FIELD                   (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_NEXT_DTD_PTR_ROW                     0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED2_0_ROW                      0
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TERMINATE_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_FIELD                    (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT                    _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_ROW                      1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_IOC_ENABLE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_FIELD                    (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_RANGE                    _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_0_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_SHIFT                    _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_ROW                      1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_MULTIPLIER_OVERRIDE_ENABLE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_RANGE                    _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_1_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_ROW                   1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_ACTIVE_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_RANGE                 _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_ROW                   1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_HALTED_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_ROW                        1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_SHIFT                    _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_2_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT                      _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_RANGE                      _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_ROW                        1
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_FIELD                    (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED3_3_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                    3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_ROW                    4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED6_0_ROW                      4
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_ROW                    5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED7_0_ROW                      5
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_ROW                    6
+
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_FIELD                    (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_DEVICE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_ROW                      6
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_FIELD                    (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QUEUE_HEAD_HORIZONTAL_LINK_PTR_ROW                      0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED0_0_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_RANGE                       _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_ROW                 0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_ITD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_QH                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_SITD                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_ITD_TYPE_FSTN                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_VALID_QH_PTR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QH_TERMINATE_INVALID_QH_PTR                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_SHIFT                        _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_FIELD                        (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NAK_CNT_RL_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_SHIFT                      _MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_RANGE                      _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_ROW                        1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_NOT_CTRL_EP                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CTRL_EP_FLAG_CTRP_EP                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_FIELD                    (_MK_MASK_CONST(0x7ff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_RANGE                    _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MAX_PKT_LENGTH_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_SHIFT                     _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_ROW                       1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HEAD_RECLAMATION_LIST_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_SHIFT                  _MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_RANGE                  _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_QH_DT                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_CTRL_QTD_DT                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_RANGE                       _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_ROW                 1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_FULL_SPEED                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_LOW_SPEED                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_HIGH_SPEED                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENDPT_SPEED_RESERVED                    _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_SHIFT                       _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ENPT_NUMBER_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_SHIFT                        _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_RANGE                        _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_ROW                  1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_NO_INACTIVATE                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_INACTIVATE_INACTIVATE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_FIELD                       (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_RANGE                       _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DEV_ADDRESS_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_SHIFT                      _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_FIELD                      (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_ROW                        2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_NON_ISO_IS_0                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_MULTI_1                    _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_MULT_2                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MULT_MULTI_3                    _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_SHIFT                       _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_FIELD                       (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_RANGE                       _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PORT_NUMBER_ROW                 2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_FIELD                  (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_RANGE                  _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HUB_ADDR_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_C_MASK_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_FIELD                     (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_UFRAME_S_MASK_ROW                       2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_FIELD                   (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_QTD_PTR_ROW                     3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_FIELD                       (_MK_MASK_CONST(0x1f) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED3_0_ROW                 3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_FIELD                      (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_NEXT_QTD_PTR_ROW                        4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED4_0_ROW                 4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_RANGE                     _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_ROW                       4
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_VALID_TD_PTR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_QTD_TERMINATE_INVALID_TD_PTR                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_FIELD                  (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_NEXT_QTD_PTR_ROW                    5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_FIELD                       (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED5_0_ROW                 5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_RANGE                 _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_ROW                   5
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_VALID_TD_PTR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ALT_QTD_TERMINATE_INVALID_TD_PTR                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_SHIFT                       _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_RANGE                       _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_ROW                 6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_DATA0                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_TOGGLE_DATA1                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_FIELD                       (_MK_MASK_CONST(0x7fff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_RANGE                       _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TOTAL_BYTES_ROW                 6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_SHIFT                       _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_RANGE                       _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_ROW                 6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_DISABLE                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_IOC_ENABLE                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_FIELD                      (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_RANGE                      _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_CURRENT_PAGE_ROW                        6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ERR_COUNTER_ROW                 6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_RANGE                  _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_ROW                    6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_OUT                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_IN                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_SETUP                  _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PID_CODE_RESERVED                       _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_RANGE                    _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_ROW                      6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_ACTIVE_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_ROW                      6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_HALTED_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_RANGE                 _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_ROW                   6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_DATA_BUFFER_ERROR_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_SHIFT                   _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_RANGE                   _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_ROW                     6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_CLEAR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BABBLE_DETECTED_SET                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_RANGE                 _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_ROW                   6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_TRANSACTION_ERROR_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_RANGE                        _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_ROW                  6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_MISSED_MICRO_FRAME_SET                  _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_RANGE                 _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_ROW                   6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_DO_START_SPLIT                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_SPLIT_TRANS_STATE_DO_COMPLETE_SPLIT                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_RANGE                        _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_ROW                  6
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_DO_OUT                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_PING_STATE_DO_PING                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE0_ROW                       7
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_FIELD                        (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_OFFSET_ROW                  7
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE1_ROW                       8
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED8_0_ROW                 8
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE2_ROW                       9
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED9_0_ROW                 9
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE3_ROW                       10
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_FIELD                      (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED10_0_ROW                        10
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_FIELD                     (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_BUF_PTR_PAGE4_ROW                       11
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_FIELD                      (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_HEAD_0_RESERVED11_0_ROW                        11
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_FIELD                       (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_RANGE                       _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_NEXT_QTD_PTR_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_FIELD                        (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED4_0_ROW                  0
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_VALID_TD_PTR                       _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_QTD_TERMINATE_INVALID_TD_PTR                     _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_FIELD                   (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_RANGE                   _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_NEXT_QTD_PTR_ROW                     1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_FIELD                        (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED5_0_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_RANGE                  _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_VALID_TD_PTR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ALT_QTD_TERMINATE_INVALID_TD_PTR                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_SHIFT                        _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_ROW                  2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_DATA0                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_TOGGLE_DATA1                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_FIELD                        (_MK_MASK_CONST(0x7fff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_RANGE                        _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_ROW                  2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_ROW                  2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_IOC_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_SHIFT                       _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_FIELD                       (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_RANGE                       _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_CURRENT_PAGE_ROW                 2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_SHIFT                        _MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_FIELD                        (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(10)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ERR_COUNTER_ROW                  2
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_SHIFT                   _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_RANGE                   _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_ROW                     2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_OUT                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_IN                      _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_SETUP                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PID_CODE_RESERVED                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT                     _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_ROW                       2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_ACTIVE_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_RANGE                     _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_ROW                       2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_HALTED_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_RANGE                  _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT                    _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_ROW                      2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_RANGE                  _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_RANGE                 _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_ROW                   2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_RANGE                  _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_START_SPLIT                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_COMPLETE_SPLIT                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_RANGE                 _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_ROW                   2
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_DO_OUT                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_PING_STATE_DO_PING                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                        3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_ROW                   3
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                        4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_FIELD                        (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED8_0_ROW                  4
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_ROW                        5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_FIELD                        (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_RANGE                        _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED9_0_ROW                  5
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_ROW                        6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED10_0_ROW                 6
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_FIELD                      (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_ROW                        7
+
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_FIELD                       (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_RANGE                       _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_QUEUE_TRANSFER_DESCRIPTOR_0_RESERVED11_0_ROW                 7
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_FIELD                       (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_RANGE                       _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_FRAME_LIST_LINK_PTR_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED0_0_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_RANGE                       _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_ROW                 0
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_ITD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_QH                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_SITD                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_QH_ITD_TYPE_FSTN                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_FIELD                       (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_RANGE                       _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_FRAME_LIST_ELEMENT_0_RESERVED1_0_ROW                 0
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_FIELD                        (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_ROW                  0
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT                  _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_ROW                    0
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FIELD                  (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_RANGE                  _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ROW                    0
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ITD                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_QH                     _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SITD                   _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FSTN                   _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_ROW                      0
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_VALID_LINK_PTR                   _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_INVALID_LINK_PTR                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_ROW                       1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_0_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_0_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_ROW                      1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_0_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_ROW                    1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_0_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_LENGTH_ROW                   1
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_ROW                  1
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_0_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_0_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_0_OFFSET_ROW                   1
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_ROW                       2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_1_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_1_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_ROW                      2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_1_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_ROW                    2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_1_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_LENGTH_ROW                   2
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_ROW                  2
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_1_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_1_ROW                  2
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_1_OFFSET_ROW                   2
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_ROW                       3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_2_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_ROW                    3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_2_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_ROW                      3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_2_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_ROW                    3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_2_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_LENGTH_ROW                   3
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_ROW                  3
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_2_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_2_ROW                  3
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_2_OFFSET_ROW                   3
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_ROW                       4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_3_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_ROW                    4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_3_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_ROW                      4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_3_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_ROW                    4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_3_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_LENGTH_ROW                   4
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_ROW                  4
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_3_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_3_ROW                  4
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_3_OFFSET_ROW                   4
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_ROW                       5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_4_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_ROW                    5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_4_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_ROW                      5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_4_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_ROW                    5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_4_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_LENGTH_ROW                   5
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_ROW                  5
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_4_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_4_ROW                  5
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_4_OFFSET_ROW                   5
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_ROW                       6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_5_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_ROW                    6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_5_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_ROW                      6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_5_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_ROW                    6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_5_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_LENGTH_ROW                   6
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_ROW                  6
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_5_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_5_ROW                  6
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_5_OFFSET_ROW                   6
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_ROW                       7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_6_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_ROW                    7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_6_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_ROW                      7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_6_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_ROW                    7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_6_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_LENGTH_ROW                   7
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_ROW                  7
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_6_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_6_ROW                  7
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_6_OFFSET_ROW                   7
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_SHIFT                     _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_ROW                       8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_7_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_RANGE                  _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_ROW                    8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_7_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_ROW                      8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_CLEAR                    _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_7_SET                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_SHIFT                  _MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_RANGE                  _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_ROW                    8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_7_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_RANGE                 _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_LENGTH_ROW                   8
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_RANGE                        _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_ROW                  8
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_DISABLE                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_IOC_7_ENABLE                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_FIELD                        (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_RANGE                        _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_7_ROW                  8
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_7_OFFSET_ROW                   8
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                  9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_FIELD                  (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_RANGE                  _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_ROW                    9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT                  _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED9_0_ROW                    9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_FIELD                  (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_RANGE                  _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_ROW                    9
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                  10
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT                    _MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_ROW                      10
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_OUT                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_IN                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_FIELD                 (_MK_MASK_CONST(0x7ff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_RANGE                 _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MAX_PKT_SIZE_ROW                   10
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE2_ROW                  11
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_FIELD                 (_MK_MASK_CONST(0x3ff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED11_0_ROW                   11
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_FIELD                 (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_RANGE                 _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_ROW                   11
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_RESERVED                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_MULTI_1                       _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_MULT_2                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_MULT_MULTI_3                       _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE3_ROW                  12
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED12_0_ROW                   12
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE4_ROW                  13
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED13_0_ROW                   13
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE5_ROW                  14
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED14_0_ROW                   14
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_FIELD                        (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE6_ROW                  15
+
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_FIELD                 (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_RANGE                 _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_ISO_TRANSFER_DESCRIPTOR_0_RESERVED15_0_ROW                   15
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_FIELD                  (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_NEXT_LINK_PTR_ROW                    0
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT                    _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED0_0_ROW                      0
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ROW                      0
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_ITD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_QH                       _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_SITD                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_QH_ITD_TYPE_FSTN                     _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_ROW                        0
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_VALID_LINK_PTR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TERMINATE_INVALID_LINK_PTR                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT                      _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_ROW                        1
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_OUT                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DIRECTION_IN                 _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_SHIFT                    _MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_FIELD                    (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_RANGE                    _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(24)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PORT_NUMBER_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_SHIFT                    _MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_0_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_SHIFT                       _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_FIELD                       (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_RANGE                       _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_HUB_ADDR_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_1_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ENPT_NUMBER_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_SHIFT                    _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_RANGE                    _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED1_2_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_FIELD                    (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_RANGE                    _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DEV_ADDRESS_ROW                      1
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_FIELD                    (_MK_MASK_CONST(0xffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED2_0_ROW                      2
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_RANGE                  _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_C_MASK_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_FIELD                  (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_UFRAME_S_MASK_ROW                    2
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_SHIFT                    _MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_ROW                      3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_DISABLE                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_IOC_ENABLE                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_RANGE                    _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_PAGE_SELECT_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT                    _MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(26)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_0_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_FIELD                    (_MK_MASK_CONST(0x3ff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_RANGE                    _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(16)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TOTAL_BYTES_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_SHIFT                    _MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_FIELD                    (_MK_MASK_CONST(0xff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_C_PROG_MASK_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_ROW                   3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_CLEAR                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ACTIVE_SET                   _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_FIELD                  (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_RANGE                  _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_ROW                    3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_CLEAR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_ERROR_SET                    _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_ROW                        3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_DATA_BUFFER_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_FIELD                        (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_ROW                  3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_CLEAR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BABBLE_DETECTED_SET                  _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT                      _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_RANGE                      _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_ROW                        3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_CLEAR                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_ERROR_SET                        _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_FIELD                     (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_RANGE                     _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_ROW                       3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_CLEAR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_MISSED_MICRO_FRAME_SET                       _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT                      _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_RANGE                      _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_ROW                        3
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_START_SPLIT                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SPLIT_TRANS_STATE_DO_COMPLETE_SPLIT                  _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_FIELD                    (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_RANGE                    _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED3_1_ROW                      3
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE0_ROW                    4
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_FIELD                     (_MK_MASK_CONST(0xfff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_RANGE                     _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_OFFSET_ROW                       4
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_FIELD                  (_MK_MASK_CONST(0xfffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(12)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BUF_PTR_PAGE1_ROW                    5
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_FIELD                    (_MK_MASK_CONST(0x7f) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED5_0_ROW                      5
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_FIELD                   (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_RANGE                   _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_ROW                     5
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_ALL                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_BEGIN                   _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_MID                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_POSITION_END                     _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_FIELD                      (_MK_MASK_CONST(0x7) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_RANGE                      _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_TRANSACTION_COUNT_ROW                        5
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_SHIFT                  _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_FIELD                  (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_SITD_BACK_PTR_ROW                    6
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_FIELD                    (_MK_MASK_CONST(0xf) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_RESERVED6_0_ROW                      6
+
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_FIELD                   (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_RANGE                   _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_ROW                     6
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_VALID_BACK_PTR                  _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_SPLIT_ISO_TRANSFER_DESCRIPTOR_0_BP_TERMINATE_INVALID_BACK_PTR                        _MK_ENUM_CONST(1)
+
+
+// Packet USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_SIZE 32
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_FIELD                      (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_RANGE                      _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_NORMAL_PATH_LINK_PTR_ROW                        0
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED0_0_ROW                 0
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_RANGE                       _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_ROW                 0
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_ITD                 _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_QH                  _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_SITD                        _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_QH_ITD_TYPE_FSTN                        _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_FIELD                 (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_RANGE                 _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_ROW                   0
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_VALID_LINK_PTR                        _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_TERMINATE_INVALID_LINK_PTR                      _MK_ENUM_CONST(1)
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_FIELD                        (_MK_MASK_CONST(0x7ffffff) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_RANGE                        _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(5)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BACK_PATH_LINK_PTR_ROW                  1
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_FIELD                       (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_RANGE                       _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(3)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_RESERVED1_0_ROW                 1
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_FIELD                    (_MK_MASK_CONST(0x3) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_RANGE                    _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_ROW                      1
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_ITD                      _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_QH                       _MK_ENUM_CONST(1)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_SITD                     _MK_ENUM_CONST(2)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_QH_ITD_TYPE_FSTN                     _MK_ENUM_CONST(3)
+
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_FIELD                      (_MK_MASK_CONST(0x1) << USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_SHIFT)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_RANGE                      _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_ROW                        1
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_VALID_LINK_PTR                     _MK_ENUM_CONST(0)
+#define USB2_CONTROLLER_USB2D_HOST_PERIODIC_FRAME_SPAN_TRAVERSAL_NODE_0_BP_TERMINATE_INVALID_LINK_PTR                   _MK_ENUM_CONST(1)
+
+
+// Register USB3_IF_USB_SUSP_CTRL_0  
+#define USB3_IF_USB_SUSP_CTRL_0                 _MK_ADDR_CONST(0x400)
+#define USB3_IF_USB_SUSP_CTRL_0_SECURE                  0x0
+#define USB3_IF_USB_SUSP_CTRL_0_WORD_COUNT                      0x1
+#define USB3_IF_USB_SUSP_CTRL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_RESET_MASK                      _MK_MASK_CONST(0x7bfff)
+#define USB3_IF_USB_SUSP_CTRL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_READ_MASK                       _MK_MASK_CONST(0x7bfff)
+#define USB3_IF_USB_SUSP_CTRL_0_WRITE_MASK                      _MK_MASK_CONST(0x7be3e)
+// USB PHY wakeup debounce counter
+// USB will debounce any wakeup event by the number of clocks programmed 
+// in this counter.
+// A value of 0 results in no debounce.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SHIFT                 _MK_SHIFT_CONST(16)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_FIELD                 (_MK_MASK_CONST(0x7) << USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_RANGE                 18:16
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_WOFFSET                       0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_DEBOUNCE_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// ICUSB module clock enable.
+// Enables transceiver clock to USB controller when in ICUSB mode.
+// After setting ICUSB_PHY_ENB, software needs to wait until PLLU output is 
+// stable before setting ICUSB_MOD_CLK_ENB to ENABLE.
+// This will be reset to DISABLE whenever ICUSB is in suspend.
+// Software needs to enable it after ICUSB comes out of suspend after
+// waiting for PLLU output to be stable again.
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_MOD_CLK_ENB_SHIFT                 _MK_SHIFT_CONST(15)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_MOD_CLK_ENB_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_ICUSB_MOD_CLK_ENB_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_MOD_CLK_ENB_RANGE                 15:15
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_MOD_CLK_ENB_WOFFSET                       0x0
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_MOD_CLK_ENB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_MOD_CLK_ENB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_MOD_CLK_ENB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_MOD_CLK_ENB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_MOD_CLK_ENB_DISABLE                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_MOD_CLK_ENB_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable ICUSB PHY mode
+// Setting this will enable the PLLU output clock when ICUSB is not in suspend
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_PHY_ENB_SHIFT                     _MK_SHIFT_CONST(13)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_PHY_ENB_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_ICUSB_PHY_ENB_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_PHY_ENB_RANGE                     13:13
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_PHY_ENB_WOFFSET                   0x0
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_PHY_ENB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_PHY_ENB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_PHY_ENB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_PHY_ENB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_PHY_ENB_DISABLE                   _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_ICUSB_PHY_ENB_ENABLE                    _MK_ENUM_CONST(1)
+
+// Enable UTMIP PHY mode
+// Set this to 1 if using UTMIP PHY.
+// Otherwise set this to 0.
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_PHY_ENB_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_PHY_ENB_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_UTMIP_PHY_ENB_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_PHY_ENB_RANGE                     12:12
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_PHY_ENB_WOFFSET                   0x0
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_PHY_ENB_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_PHY_ENB_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_PHY_ENB_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_PHY_ENB_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_PHY_ENB_DISABLE                   _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_PHY_ENB_ENABLE                    _MK_ENUM_CONST(1)
+
+// Reset going to UTMIP PHY (active high).
+// This should be set to 1 whenever programming the UTMIP config registers.
+// It should be cleared to 0 after the programming of UTMIP config registers is done.
+// UTMIP config registers should be programmed only once before doing any transactions on USB.
+// The UTMIP PHY registers should be programmed while UTMIP is in reset.
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_RESET_SHIFT                       _MK_SHIFT_CONST(11)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_RESET_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_UTMIP_RESET_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_RESET_RANGE                       11:11
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_RESET_WOFFSET                     0x0
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_RESET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_RESET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_RESET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_RESET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_RESET_DISABLE                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_UTMIP_RESET_ENABLE                      _MK_ENUM_CONST(1)
+
+// Polarity of the suspend signal going to USB PHY.
+// 0 = Active low (default)
+// 1 = Active high
+// This should not be changed by software.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_SHIFT                      _MK_SHIFT_CONST(10)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_FIELD                      (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_RANGE                      10:10
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_WOFFSET                    0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_ACTIVE_LOW                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_POL_ACTIVE_HIGH                        _MK_ENUM_CONST(1)
+
+// USB PHY clock valid interrupt enable
+// If this bit is enabled, interrupt is generated
+// whenever USB clocks are resumed from a suspend.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SHIFT                 _MK_SHIFT_CONST(9)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_RANGE                 9:9
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_WOFFSET                       0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_DISABLE                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_ENB_ENABLE                        _MK_ENUM_CONST(1)
+
+// USB PHY clock valid interrupt status
+// This bit is set whenever USB PHY clock is waked up from suspend.
+// Software must write a 1 to clear this bit.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_RANGE                 8:8
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_WOFFSET                       0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_UNSET                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_INT_STS_SET                   _MK_ENUM_CONST(1)
+
+// USB PHY clock valid status
+// This bit indicates whether the USB PHY is generating a valid clock to 
+// the USB controller.
+// If USB PHY clock is running, this bit is set to 1, else it is set to 0.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SHIFT                 _MK_SHIFT_CONST(7)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_RANGE                 7:7
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_WOFFSET                       0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_UNSET                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_PHY_CLK_VALID_SET                   _MK_ENUM_CONST(1)
+
+// USB AHB clock enable status.
+// Indicates whether the AHB clock to the USB controller is enabled or not.
+// If AHB clock to USB controller is enabled, this bit is set to 1, else it is set to 0.
+// NOTE: even when this is set to 0, all essential blocks that are required
+// to resume USB clocks from suspend will be active and their AHB clock will not
+// be suspended.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_CLKEN_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_CLKEN_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_USB_CLKEN_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_CLKEN_RANGE                 6:6
+#define USB3_IF_USB_SUSP_CTRL_0_USB_CLKEN_WOFFSET                       0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_CLKEN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_CLKEN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_CLKEN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_CLKEN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_CLKEN_UNSET                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_CLKEN_SET                   _MK_ENUM_CONST(1)
+
+//Suspend Clear
+// Software must write a 1 to this bit to bring the PHY
+// out of suspend mode. This is used when the software stops the PHY
+// clock during suspend and then wants to initiate a resume. Software
+// should also write 0 to clear it.
+// NOTE: It is required that software generate a  positive pulse on this
+// bit to guarantee proper operation.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SHIFT                      _MK_SHIFT_CONST(5)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_FIELD                      (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_RANGE                      5:5
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_WOFFSET                    0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_UNSET                      _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_SUSP_CLR_SET                        _MK_ENUM_CONST(1)
+
+// Wake on Disconnect Enable (device mode)
+// When enabled (1), USB device will wakeup
+// from suspend on a disconnect event.
+// This is only valid when USB controller is in device mode, it is
+// not applicable when USB controller is in host mode.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_RANGE                 4:4
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_WOFFSET                       0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_DISABLE                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_DISCON_EN_DEV_ENABLE                        _MK_ENUM_CONST(1)
+
+// Wake on Connect Enable (device mode)
+// When enabled (1), USB device will wakeup
+// from suspend on a connect event.
+// This is only valid when USB controller is in device mode, it is
+// not applicable when USB controller is in host mode.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_FIELD                   (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_RANGE                   3:3
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_WOFFSET                 0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_DISABLE                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_CNNT_EN_DEV_ENABLE                  _MK_ENUM_CONST(1)
+
+// Wake on resume enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a resume event is detected on USB.
+// This is valid for both USB device and USB host modes.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_RANGE                     2:2
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_WOFFSET                   0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_DISABLE                   _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKE_ON_RESUME_EN_ENABLE                    _MK_ENUM_CONST(1)
+
+// USB wakeup interrupt enable
+// If this bit is enabled, interrupt is generated
+// whenever USB wakeup event is generated.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_RANGE                        1:1
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_WOFFSET                      0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_DISABLE                      _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_ENB_ENABLE                       _MK_ENUM_CONST(1)
+
+// USB wakeup interrupt status
+// This bit is set whenever USB wakes up from suspend (a wakeup event
+// is generated).
+// Software must write a 1 to clear this bit.
+// Note that during the wakeup sequence, PHY clocks will be resumed from suspend.
+// Software can check when the PHY clocks are resumed by reading the bit
+// USB_PHY_CLK_VALID. There is also a separate interrupt generated
+// when PHY clock is resumed if USB_PHY_CLK_VALID_INT_EN is set.
+// During the wakeup sequence, first USB_WAKEUP_INT_STS will be set, and
+// it will take some time for the PHY clock to resume, which can be detected
+// by checking USB_PHY_CLK_VALID.
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SHIFT)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_RANGE                        0:0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_WOFFSET                      0x0
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_UNSET                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_SUSP_CTRL_0_USB_WAKEUP_INT_STS_SET                  _MK_ENUM_CONST(1)
+
+
+// Register USB3_IF_USB_PHY_VBUS_SENSORS_0  
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0                  _MK_ADDR_CONST(0x404)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_SECURE                   0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_WORD_COUNT                       0x1
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_RESET_MASK                       _MK_MASK_CONST(0x7f7f7f7f)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_READ_MASK                        _MK_MASK_CONST(0x7f7f7f7f)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_WRITE_MASK                       _MK_MASK_CONST(0x79797979)
+// A_VBUS_VLD wakeup enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a change is detected on A_VBUS_VLD.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_SHIFT                       _MK_SHIFT_CONST(30)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_RANGE                       30:30
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_WAKEUP_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT                       _MK_SHIFT_CONST(29)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_RANGE                       29:29
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_A                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_DEB_SEL_B_SEL_B                       _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software value
+// Software should write the appropriate
+// value (1/0) to set/unset the A_VBUS_VLD status.
+// This is only valid when A_VBUS_VLD_SW_EN is set.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT                        _MK_SHIFT_CONST(28)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_RANGE                        28:28
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_UNSET                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_VALUE_SET                  _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD software enable
+// Enable Software Controlled A_VBUS_VLD.
+// Software sets this bit to drive the
+// value in A_VBUS_VLD_SW_VALUE to the USB
+// controller.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT                   _MK_SHIFT_CONST(27)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_FIELD                   (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_RANGE                   27:27
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_WOFFSET                 0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_SW_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD status
+// This is set to 1 whenever A_VBUS_VLD sensor
+// output is 1.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT                     _MK_SHIFT_CONST(26)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_RANGE                     26:26
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_UNSET                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_STS_SET                       _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_VBUS_VLD.
+// software writes a 1 to clear it
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT                 _MK_SHIFT_CONST(25)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_RANGE                 25:25
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_WOFFSET                       0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_UNSET                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_CHG_DET_SET                   _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever A_VBUS_VLD_CHG_DET is set to 1.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT                  _MK_SHIFT_CONST(24)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_RANGE                  24:24
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_VBUS_VLD_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// A_SESS_VLD wakeup enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a change is detected on A_SESS_VLD.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_SHIFT                       _MK_SHIFT_CONST(22)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_RANGE                       22:22
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_WAKEUP_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// A_SESS_VLD debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT                       _MK_SHIFT_CONST(21)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_RANGE                       21:21
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_A                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_DEB_SEL_B_SEL_B                       _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software value
+// Software should write the appropriate
+// value (1/0) to set/unset the A_SESS_VLD status.
+// This is only valid when A_SESS_VLD_SW_EN is set.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT                        _MK_SHIFT_CONST(20)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_RANGE                        20:20
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_UNSET                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_VALUE_SET                  _MK_ENUM_CONST(1)
+
+// A_SESS_VLD software enable
+// Enable Software Controlled A_SESS_VLD.
+// Software sets this bit to drive the
+// value in A_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT                   _MK_SHIFT_CONST(19)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_FIELD                   (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_RANGE                   19:19
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_WOFFSET                 0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_SW_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// A_SESS_VLD status
+// This is set to 1 whenever A_SESS_VLD sensor
+// output is 1.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_RANGE                     18:18
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_UNSET                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_STS_SET                       _MK_ENUM_CONST(1)
+
+// A_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of A_SESS_VLD.
+// software writes a 1 to clear it
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_RANGE                 17:17
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_WOFFSET                       0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_UNSET                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_CHG_DET_SET                   _MK_ENUM_CONST(1)
+
+// A_SESS_VLD interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever A_SESS_VLD_CHG_DET is set to 1.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_RANGE                  16:16
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_A_SESS_VLD_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// B_SESS_VLD wakeup enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a change is detected on B_SESS_VLD.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_SHIFT                       _MK_SHIFT_CONST(14)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_RANGE                       14:14
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_WAKEUP_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_VLD debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT                       _MK_SHIFT_CONST(13)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_RANGE                       13:13
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_A                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_DEB_SEL_B_SEL_B                       _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software value
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_VLD status.
+// This is only valid when B_SESS_VLD_SW_EN is set.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT                        _MK_SHIFT_CONST(12)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_RANGE                        12:12
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_UNSET                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_VALUE_SET                  _MK_ENUM_CONST(1)
+
+// B_SESS_VLD software enable
+// Enable Software Controlled B_SESS_VLD.
+// Software sets this bit to drive the
+// value in B_SESS_VLD_SW_VALUE to the USB
+// controller.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT                   _MK_SHIFT_CONST(11)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_FIELD                   (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_RANGE                   11:11
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_WOFFSET                 0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_SW_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// B_SESS_VLD status
+// This is set to 1 whenever B_SESS_VLD sensor
+// output is 1.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT                     _MK_SHIFT_CONST(10)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_RANGE                     10:10
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_UNSET                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_STS_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_VLD change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_VLD.
+// software writes a 1 to clear it
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT                 _MK_SHIFT_CONST(9)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_RANGE                 9:9
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_WOFFSET                       0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_UNSET                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_CHG_DET_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_VLD interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_VLD_CHG_DET is set to 1.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT                  _MK_SHIFT_CONST(8)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_RANGE                  8:8
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_VLD_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// B_SESS_END wakeup enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a change is detected on B_SESS_END.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_SHIFT                       _MK_SHIFT_CONST(6)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_RANGE                       6:6
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_WAKEUP_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// B_SESS_END debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_RANGE                       5:5
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_A                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_DEB_SEL_B_SEL_B                       _MK_ENUM_CONST(1)
+
+// B_SESS_END software value
+// Software should write the appropriate
+// value (1/0) to set/unset the B_SESS_END status.
+// This is only valid when B_SESS_END_SW_EN is set.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_RANGE                        4:4
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_UNSET                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_VALUE_SET                  _MK_ENUM_CONST(1)
+
+// B_SESS_END software enable
+// Enable Software Controlled B_SESS_END
+// Software sets this bit to drive the
+// value in B_SESS_END_SW_VALUE to the USB
+// controller.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_FIELD                   (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_RANGE                   3:3
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_WOFFSET                 0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_SW_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// B_SESS_END status
+// This is set to 1 whenever B_SESS_END sensor
+// output is 1.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_RANGE                     2:2
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_UNSET                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_STS_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_END change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of B_SESS_END.
+// software writes a 1 to clear it
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_RANGE                 1:1
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_WOFFSET                       0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_UNSET                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_CHG_DET_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_END interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever B_SESS_END_CHG_DET is set to 1.
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_RANGE                  0:0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_SENSORS_0_B_SESS_END_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+
+// Register USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0  
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0                        _MK_ADDR_CONST(0x408)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_SECURE                         0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_WORD_COUNT                     0x1
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_RESET_VAL                      _MK_MASK_CONST(0x40)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_RESET_MASK                     _MK_MASK_CONST(0x403f3fff)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_READ_MASK                      _MK_MASK_CONST(0x403f3fff)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_WRITE_MASK                     _MK_MASK_CONST(0x40393979)
+// VDAT_DET debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT                       _MK_SHIFT_CONST(21)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_RANGE                       21:21
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_A                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_DEB_SEL_B_SEL_B                       _MK_ENUM_CONST(1)
+
+// VDAT_DET software value
+// Software should write the appropriate
+// value (1/0) to set/unset the VDAT_DET status.
+// This is only valid when VDAT_DET_SW_EN is set.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT                        _MK_SHIFT_CONST(20)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_RANGE                        20:20
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_UNSET                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_VALUE_SET                  _MK_ENUM_CONST(1)
+
+// VDAT_DET software enable
+// Enable Software Controlled VDAT_DET.
+// Software sets this bit to drive the
+// value in VDAT_DET_SW_VALUE to the USB
+// controller
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT                   _MK_SHIFT_CONST(19)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_FIELD                   (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_RANGE                   19:19
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_WOFFSET                 0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_DISABLE                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_SW_EN_ENABLE                  _MK_ENUM_CONST(1)
+
+// VDAT_DET status
+// This is set to 1 whenever VDAT_DET sensor
+// output is 1.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_RANGE                     18:18
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_UNSET                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_STS_SET                       _MK_ENUM_CONST(1)
+
+// VDAT_DET change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VDAT_DET.
+// software writes a 1 to clear it
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_RANGE                 17:17
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_WOFFSET                       0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_UNSET                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_CHG_DET_SET                   _MK_ENUM_CONST(1)
+
+// VDAT_DET interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever VDAT_DET_CHG_DET is set to 1.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_RANGE                  16:16
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VDAT_DET_INT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP wakeup enable
+// If this bit is enabled, USB will wakeup from
+// suspend whenever a change is detected on VBUS_WAKEUP.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_FIELD                    (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_RANGE                    30:30
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_WOFFSET                  0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_DISABLE                  _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_WAKEUP_EN_ENABLE                   _MK_ENUM_CONST(1)
+
+// VBUS_WAKEUP debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT                    _MK_SHIFT_CONST(13)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_FIELD                    (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_RANGE                    13:13
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_WOFFSET                  0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_A                    _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_DEB_SEL_B_SEL_B                    _MK_ENUM_CONST(1)
+
+// VBUS wakeup software value
+// Software should write the appropriate
+// value (1/0) to set/unset the VBUS_WAKEUP status.
+// This is only valid when VBUS_WAKEUP_SW_EN is set.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT                     _MK_SHIFT_CONST(12)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_RANGE                     12:12
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_UNSET                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_VALUE_SET                       _MK_ENUM_CONST(1)
+
+// VBUS wakeup software enable
+// Enable Software Controlled VBUS_WAKEUP.
+// Software sets this bit to drive the
+// value in VBUS_WAKEUP_SW_VALUE to the USB
+// controller.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT                        _MK_SHIFT_CONST(11)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_RANGE                        11:11
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_SW_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// VBUS wakeup status
+// This is set to 1 whenever VBUS_WAKEUP sensor
+// output is 1.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT                  _MK_SHIFT_CONST(10)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_RANGE                  10:10
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_UNSET                  _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_STS_SET                    _MK_ENUM_CONST(1)
+
+// VBUS wakeup change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of VBUS_WAKEUP.
+// software writes a 1 to clear it
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT                      _MK_SHIFT_CONST(9)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_FIELD                      (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_RANGE                      9:9
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_WOFFSET                    0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_UNSET                      _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_CHG_DET_SET                        _MK_ENUM_CONST(1)
+
+// VBUS wakeup interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever VBUS_WAKEUP_CHG_DET is set to 1.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT                       _MK_SHIFT_CONST(8)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_RANGE                       8:8
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_DISABLE                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_VBUS_WAKEUP_INT_EN_ENABLE                      _MK_ENUM_CONST(1)
+
+// Static GPI status
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_STATIC_GPI_SHIFT                       _MK_SHIFT_CONST(7)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_STATIC_GPI_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_STATIC_GPI_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_STATIC_GPI_RANGE                       7:7
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_STATIC_GPI_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_STATIC_GPI_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_STATIC_GPI_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_STATIC_GPI_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_STATIC_GPI_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_STATIC_GPI_UNSET                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_STATIC_GPI_SET                 _MK_ENUM_CONST(1)
+
+// ID pullup enable. Set to 1.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_FIELD                    (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_RANGE                    6:6
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_WOFFSET                  0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_DISABLE                  _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_PU_ENABLE                   _MK_ENUM_CONST(1)
+
+// ID debounce A/B select
+// Selects between the two debounce values 
+// UTMIP_BIAS_DEBOUNCE_A or
+// UTMIP_BIAS_DEBOUNCE_B from the register
+// UTMIP_DEBOUNCE_CFG0.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_RANGE                     5:5
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_A                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_DEB_SEL_B_SEL_B                     _MK_ENUM_CONST(1)
+
+// ID software value
+// Software should write the appropriate
+// value (1/0) to set/unset the ID status.
+// This is only valid when ID_SW_EN is set.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT                      _MK_SHIFT_CONST(4)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_FIELD                      (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_RANGE                      4:4
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_WOFFSET                    0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_UNSET                      _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_VALUE_SET                        _MK_ENUM_CONST(1)
+
+// ID software enable
+// Enable Software Controlled ID.
+// Software sets this bit to drive the
+// value in ID_SW_VALUE to the USB
+// controller
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_RANGE                 3:3
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_WOFFSET                       0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_DISABLE                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_SW_EN_ENABLE                        _MK_ENUM_CONST(1)
+
+// ID status
+// This is set to 1 whenever ID sensor
+// output is 1.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT                   _MK_SHIFT_CONST(2)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_FIELD                   (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_RANGE                   2:2
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_WOFFSET                 0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_UNSET                   _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_STS_SET                     _MK_ENUM_CONST(1)
+
+// ID change detect.
+// This field is set by hardware whenever a change
+// is detected in the value of ID.
+// software writes a 1 to clear it
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_RANGE                       1:1
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_WOFFSET                     0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_UNSET                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_CHG_DET_SET                 _MK_ENUM_CONST(1)
+
+// ID interrupt enable
+// If this field is set to 1, an interrupt is
+// generated whenever ID_CHG_DET is set to 1.
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SHIFT)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_RANGE                        0:0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0_ID_INT_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register USB3_IF_USB_PHY_ALT_VBUS_STS_0  
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0                  _MK_ADDR_CONST(0x40c)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_SECURE                   0x0
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_WORD_COUNT                       0x1
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_RESET_MASK                       _MK_MASK_CONST(0x7f)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_READ_MASK                        _MK_MASK_CONST(0x7f)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// A_SESS_VLD alternate status
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SHIFT)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_RANGE                     6:6
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_SESS_VLD_ALT_SET                       _MK_ENUM_CONST(1)
+
+// B_SESS_VLD alternate status
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SHIFT)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_RANGE                     5:5
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_VLD_ALT_SET                       _MK_ENUM_CONST(1)
+
+// ID alternate status
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SHIFT)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_RANGE                 4:4
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_WOFFSET                       0x0
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_UNSET                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_ID_DIG_ALT_SET                   _MK_ENUM_CONST(1)
+
+// B_SESS_END alternate status
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SHIFT                     _MK_SHIFT_CONST(3)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SHIFT)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_RANGE                     3:3
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_B_SESS_END_ALT_SET                       _MK_ENUM_CONST(1)
+
+// Static GPI alternate status
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SHIFT)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_RANGE                     2:2
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_STATIC_GPI_ALT_SET                       _MK_ENUM_CONST(1)
+
+// A_VBUS_VLD alternate status
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SHIFT                     _MK_SHIFT_CONST(1)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_FIELD                     (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SHIFT)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_RANGE                     1:1
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_UNSET                     _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_A_VBUS_VLD_ALT_SET                       _MK_ENUM_CONST(1)
+
+// Vbus wakeup alternate status
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_FIELD                    (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SHIFT)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_RANGE                    0:0
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_WOFFSET                  0x0
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_UNSET                    _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_ALT_VBUS_STS_0_VBUS_WAKEUP_ALT_SET                      _MK_ENUM_CONST(1)
+
+
+// Reserved address 1040 [0x410] 
+
+// Register USB3_IF_ICUSB_XCVR_CFG_0  
+#define USB3_IF_ICUSB_XCVR_CFG_0                        _MK_ADDR_CONST(0x414)
+#define USB3_IF_ICUSB_XCVR_CFG_0_SECURE                         0x0
+#define USB3_IF_ICUSB_XCVR_CFG_0_WORD_COUNT                     0x1
+#define USB3_IF_ICUSB_XCVR_CFG_0_RESET_VAL                      _MK_MASK_CONST(0x100007)
+#define USB3_IF_ICUSB_XCVR_CFG_0_RESET_MASK                     _MK_MASK_CONST(0xff1f3f8f)
+#define USB3_IF_ICUSB_XCVR_CFG_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_READ_MASK                      _MK_MASK_CONST(0xff1f3f8f)
+#define USB3_IF_ICUSB_XCVR_CFG_0_WRITE_MASK                     _MK_MASK_CONST(0x1f3f8f)
+// ICUSB PHY calibration code
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_SHIFT                     _MK_SHIFT_CONST(24)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_FIELD                     (_MK_MASK_CONST(0xff) << USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_SHIFT)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_RANGE                     31:24
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_WOFFSET                   0x0
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// ICUSB PHY auto-calibration enable
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_EN_SHIFT                  _MK_SHIFT_CONST(20)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_EN_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_EN_SHIFT)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_EN_RANGE                  20:20
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_EN_WOFFSET                        0x0
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_EN_DISABLE                        _MK_ENUM_CONST(0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_CALOUT_EN_ENABLE                 _MK_ENUM_CONST(1)
+
+// ICUSB PHY Drive strength offset
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_DRV_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_DRV_FIELD                        (_MK_MASK_CONST(0xf) << USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_DRV_SHIFT)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_DRV_RANGE                        19:16
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_DRV_WOFFSET                      0x0
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_DRV_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_DRV_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_DRV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_DRV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// ICUSB PHY FS/LS slew rate control
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SLEW_SHIFT                       _MK_SHIFT_CONST(8)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SLEW_FIELD                       (_MK_MASK_CONST(0x3f) << USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SLEW_SHIFT)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SLEW_RANGE                       13:8
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SLEW_WOFFSET                     0x0
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SLEW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SLEW_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SLEW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SLEW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// ICUSB differential receiver select
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SEL_DIFF_RCVR_SHIFT                      _MK_SHIFT_CONST(7)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SEL_DIFF_RCVR_FIELD                      (_MK_MASK_CONST(0x1) << USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SEL_DIFF_RCVR_SHIFT)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SEL_DIFF_RCVR_RANGE                      7:7
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SEL_DIFF_RCVR_WOFFSET                    0x0
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SEL_DIFF_RCVR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SEL_DIFF_RCVR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SEL_DIFF_RCVR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SEL_DIFF_RCVR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SEL_DIFF_RCVR_SINGLE                     _MK_ENUM_CONST(0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_SEL_DIFF_RCVR_DIFF                       _MK_ENUM_CONST(1)
+
+// ICUSB PHY IDDQ shutdown mode
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_IDDQ_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_IDDQ_FIELD                       (_MK_MASK_CONST(0x1) << USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_IDDQ_SHIFT)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_IDDQ_RANGE                       3:3
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_IDDQ_WOFFSET                     0x0
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_IDDQ_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_IDDQ_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_IDDQ_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_IDDQ_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_IDDQ_NORMAL                      _MK_ENUM_CONST(0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_IDDQ_OFF                 _MK_ENUM_CONST(1)
+
+// ICUSB PHY Single-ended receiver power down
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_ZI_SHIFT                      _MK_SHIFT_CONST(2)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_ZI_FIELD                      (_MK_MASK_CONST(0x1) << USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_ZI_SHIFT)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_ZI_RANGE                      2:2
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_ZI_WOFFSET                    0x0
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_ZI_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_ZI_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_ZI_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_ZI_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_ZI_NORMAL                     _MK_ENUM_CONST(0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_ZI_OFF                        _MK_ENUM_CONST(1)
+
+// ICUSB PHY Differential receiver power down
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_DR_SHIFT                      _MK_SHIFT_CONST(1)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_DR_FIELD                      (_MK_MASK_CONST(0x1) << USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_DR_SHIFT)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_DR_RANGE                      1:1
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_DR_WOFFSET                    0x0
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_DR_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_DR_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_DR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_DR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_DR_NORMAL                     _MK_ENUM_CONST(0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_DR_OFF                        _MK_ENUM_CONST(1)
+
+// ICUSB PHY Low/full-speed driver power down
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_TX_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_TX_FIELD                      (_MK_MASK_CONST(0x1) << USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_TX_SHIFT)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_TX_RANGE                      0:0
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_TX_WOFFSET                    0x0
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_TX_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_TX_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_TX_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_TX_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_TX_NORMAL                     _MK_ENUM_CONST(0)
+#define USB3_IF_ICUSB_XCVR_CFG_0_ICUSB_PD_TX_OFF                        _MK_ENUM_CONST(1)
+
+
+// Reserved address 1048 [0x418] 
+
+// Reserved address 1052 [0x41c] 
+
+// Register USB3_IF_USB_INTER_PKT_DELAY_CTRL_0  
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0                      _MK_ADDR_CONST(0x420)
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_SECURE                       0x0
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_WORD_COUNT                   0x1
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_RESET_VAL                    _MK_MASK_CONST(0x12)
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_RESET_MASK                   _MK_MASK_CONST(0x3f)
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_READ_MASK                    _MK_MASK_CONST(0x3f)
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_WRITE_MASK                   _MK_MASK_CONST(0x3f)
+// HS Tx to Tx inter-packet delay.
+// This is valid only for UTMIP PHY
+// Software should not change this.
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_FIELD                      (_MK_MASK_CONST(0x3f) << USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SHIFT)
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_RANGE                      5:0
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_WOFFSET                    0x0
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_DEFAULT                    _MK_MASK_CONST(0x12)
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_INTER_PKT_DELAY_CTRL_0_IP_DELAY_TX2TX_HS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Reserved address 1060 [0x424] 
+
+// Reserved address 1064 [0x428] 
+
+// Register USB3_IF_USB_DEBUG_0  
+#define USB3_IF_USB_DEBUG_0                     _MK_ADDR_CONST(0x480)
+#define USB3_IF_USB_DEBUG_0_SECURE                      0x0
+#define USB3_IF_USB_DEBUG_0_WORD_COUNT                  0x1
+#define USB3_IF_USB_DEBUG_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_DEBUG_0_RESET_MASK                  _MK_MASK_CONST(0x60)
+#define USB3_IF_USB_DEBUG_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_DEBUG_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_DEBUG_0_READ_MASK                   _MK_MASK_CONST(0x60)
+#define USB3_IF_USB_DEBUG_0_WRITE_MASK                  _MK_MASK_CONST(0x60)
+// Lower 32-bits select.
+// Only valid for Tx and Rx memories that
+// have 36-bit interface. When 0, selects
+// upper 4-bits. When 1, selects lower
+// 32-bits.
+#define USB3_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SHIFT)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_RANGE                 6:6
+#define USB3_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_WOFFSET                       0x0
+#define USB3_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_UPPER_BITS                    _MK_ENUM_CONST(0)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_LOW32BITS_SEL_LOWER_BITS                    _MK_ENUM_CONST(1)
+
+// Route USB buffers to AHB interface for debug.
+// When this is set to 1, normal USB
+// operations cannot be done.
+#define USB3_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SHIFT                    _MK_SHIFT_CONST(5)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_FIELD                    (_MK_MASK_CONST(0x1) << USB3_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SHIFT)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_RANGE                    5:5
+#define USB3_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_WOFFSET                  0x0
+#define USB3_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_DISABLE                  _MK_ENUM_CONST(0)
+#define USB3_IF_USB_DEBUG_0_USB_BUF_AHB_IF_SEL_ENABLE                   _MK_ENUM_CONST(1)
+
+
+// Register USB3_IF_USB_PHY_SELF_TEST_0  
+#define USB3_IF_USB_PHY_SELF_TEST_0                     _MK_ADDR_CONST(0x484)
+#define USB3_IF_USB_PHY_SELF_TEST_0_SECURE                      0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_WORD_COUNT                  0x1
+#define USB3_IF_USB_PHY_SELF_TEST_0_RESET_VAL                   _MK_MASK_CONST(0x10150008)
+#define USB3_IF_USB_PHY_SELF_TEST_0_RESET_MASK                  _MK_MASK_CONST(0xfffff37f)
+#define USB3_IF_USB_PHY_SELF_TEST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_READ_MASK                   _MK_MASK_CONST(0xfffff37f)
+#define USB3_IF_USB_PHY_SELF_TEST_0_WRITE_MASK                  _MK_MASK_CONST(0xffff7373)
+// No of test packets to be sent. 0 = infinite, continue sending
+// packets until test mode is disabled.
+#define USB3_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SHIFT                  _MK_SHIFT_CONST(24)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_FIELD                  (_MK_MASK_CONST(0xff) << USB3_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_RANGE                  31:24
+#define USB3_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_DEFAULT                        _MK_MASK_CONST(0x10)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TEST_PKT_CNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Interpacket delay between two consecutive packets in no of 60 Mhz cycles
+#define USB3_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB3_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_FIELD                      (_MK_MASK_CONST(0xff) << USB3_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_RANGE                      23:16
+#define USB3_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_WOFFSET                    0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_DEFAULT                    _MK_MASK_CONST(0x15)
+#define USB3_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB3_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_IPKT_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Status of Disconnect signal from PHY
+#define USB3_IF_USB_PHY_SELF_TEST_0_DISCON_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DISCON_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST_0_DISCON_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DISCON_RANGE                        15:15
+#define USB3_IF_USB_PHY_SELF_TEST_0_DISCON_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_DISCON_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DISCON_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DISCON_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DISCON_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DISCON_UNSET                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DISCON_SET                  _MK_ENUM_CONST(1)
+
+// Enable transmission of SOF
+#define USB3_IF_USB_PHY_SELF_TEST_0_SOF_EN_SHIFT                        _MK_SHIFT_CONST(14)
+#define USB3_IF_USB_PHY_SELF_TEST_0_SOF_EN_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST_0_SOF_EN_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_SOF_EN_RANGE                        14:14
+#define USB3_IF_USB_PHY_SELF_TEST_0_SOF_EN_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_SOF_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_SOF_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_0_SOF_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_SOF_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_SOF_EN_DISABLE                      _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_SOF_EN_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable pulldown on DP
+#define USB3_IF_USB_PHY_SELF_TEST_0_DPPD_SHIFT                  _MK_SHIFT_CONST(13)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DPPD_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST_0_DPPD_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DPPD_RANGE                  13:13
+#define USB3_IF_USB_PHY_SELF_TEST_0_DPPD_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_DPPD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DPPD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DPPD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DPPD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DPPD_DISABLE                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DPPD_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable pulldown on DM
+#define USB3_IF_USB_PHY_SELF_TEST_0_DMPD_SHIFT                  _MK_SHIFT_CONST(12)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DMPD_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST_0_DMPD_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DMPD_RANGE                  12:12
+#define USB3_IF_USB_PHY_SELF_TEST_0_DMPD_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_DMPD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DMPD_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DMPD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DMPD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DMPD_DISABLE                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_DMPD_ENABLE                 _MK_ENUM_CONST(1)
+
+// Operational Mode
+#define USB3_IF_USB_PHY_SELF_TEST_0_OPMODE_SHIFT                        _MK_SHIFT_CONST(8)
+#define USB3_IF_USB_PHY_SELF_TEST_0_OPMODE_FIELD                        (_MK_MASK_CONST(0x3) << USB3_IF_USB_PHY_SELF_TEST_0_OPMODE_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_OPMODE_RANGE                        9:8
+#define USB3_IF_USB_PHY_SELF_TEST_0_OPMODE_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_OPMODE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_OPMODE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define USB3_IF_USB_PHY_SELF_TEST_0_OPMODE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_OPMODE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Term_select
+#define USB3_IF_USB_PHY_SELF_TEST_0_TERM_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TERM_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST_0_TERM_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TERM_RANGE                  6:6
+#define USB3_IF_USB_PHY_SELF_TEST_0_TERM_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_TERM_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TERM_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TERM_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TERM_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// XCVR_select:
+#define USB3_IF_USB_PHY_SELF_TEST_0_XCVR_SHIFT                  _MK_SHIFT_CONST(4)
+#define USB3_IF_USB_PHY_SELF_TEST_0_XCVR_FIELD                  (_MK_MASK_CONST(0x3) << USB3_IF_USB_PHY_SELF_TEST_0_XCVR_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_XCVR_RANGE                  5:4
+#define USB3_IF_USB_PHY_SELF_TEST_0_XCVR_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_XCVR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_XCVR_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB3_IF_USB_PHY_SELF_TEST_0_XCVR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_XCVR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// When test is started, this status signal starts as  1 and is set to 0 if an error is detected. Can be sampled when TSTEND is  asserted.
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTPS_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTPS_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST_0_TSTPS_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTPS_RANGE                 3:3
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTPS_WOFFSET                       0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTPS_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTPS_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTPS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTPS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTPS_UNSET                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTPS_SET                   _MK_ENUM_CONST(1)
+
+// Goes to 1 when the test finishes. At that time,  TSTPASS is valid and indicates the tests pass/fail status
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTEND_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTEND_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST_0_TSTEND_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTEND_RANGE                        2:2
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTEND_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTEND_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTEND_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTEND_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTEND_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTEND_UNSET                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTEND_SET                  _MK_ENUM_CONST(1)
+
+// Sw writes a 1 to start the test. It writes a 0 to  end the test
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTON_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTON_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST_0_TSTON_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTON_RANGE                 1:1
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTON_WOFFSET                       0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTON_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTON_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTON_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTON_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTON_UNSET                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTON_SET                   _MK_ENUM_CONST(1)
+
+// Place UTMIP in test mode. This does not start the test.
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTENB_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTENB_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST_0_TSTENB_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTENB_RANGE                        0:0
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTENB_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTENB_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTENB_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTENB_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTENB_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTENB_DISABLE                      _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_0_TSTENB_ENABLE                       _MK_ENUM_CONST(1)
+
+
+// Register USB3_IF_USB_PHY_SELF_TEST2_0  
+#define USB3_IF_USB_PHY_SELF_TEST2_0                    _MK_ADDR_CONST(0x488)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SECURE                     0x0
+#define USB3_IF_USB_PHY_SELF_TEST2_0_WORD_COUNT                         0x1
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RESET_MASK                         _MK_MASK_CONST(0x1f)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_WRITE_MASK                         _MK_MASK_CONST(0x1f)
+// Enable reception of test packets
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_FIELD                 (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_RANGE                 4:4
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_WOFFSET                       0x0
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_DISABLE                       _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_RCV_TEST_PKT_ENABLE                        _MK_ENUM_CONST(1)
+
+// Enable transmission of test packets
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_FIELD                        (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_RANGE                        3:3
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_WOFFSET                      0x0
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_DISABLE                      _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_PKT_ENABLE                       _MK_ENUM_CONST(1)
+
+// Enable TEST_J transmission
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_SHIFT                  _MK_SHIFT_CONST(2)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_RANGE                  2:2
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_DISABLE                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_K_ENABLE                 _MK_ENUM_CONST(1)
+
+// Enable TEST_K transmission
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_FIELD                  (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_RANGE                  1:1
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_WOFFSET                        0x0
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_DISABLE                        _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_SEND_TEST_J_ENABLE                 _MK_ENUM_CONST(1)
+
+// If enabled, send SOF with EOP of J, else
+// send SOF with EOP of K
+#define USB3_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_FIELD                   (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_RANGE                   0:0
+#define USB3_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_WOFFSET                 0x0
+#define USB3_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_DISABLE                 _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST2_0_TEST_SOF_J_ENABLE                  _MK_ENUM_CONST(1)
+
+
+// Register USB3_IF_USB_PHY_SELF_TEST_DEBUG_0  
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0                       _MK_ADDR_CONST(0x48c)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_SECURE                        0x0
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_WORD_COUNT                    0x1
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RESET_MASK                    _MK_MASK_CONST(0x3ff3f)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_READ_MASK                     _MK_MASK_CONST(0x3ff3f)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// RX compare fail. Comparison on RX data failed.
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SHIFT                   _MK_SHIFT_CONST(17)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_FIELD                   (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_RANGE                   17:17
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_WOFFSET                 0x0
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_UNSET                   _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXCMF_SET                     _MK_ENUM_CONST(1)
+
+// Rx valid/Rx validh fail: Indicates that the  Rxvalid/Rxvalidh werent generated according to protocol
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SHIFT                   _MK_SHIFT_CONST(16)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_FIELD                   (_MK_MASK_CONST(0x1) << USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_RANGE                   16:16
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_WOFFSET                 0x0
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_UNSET                   _MK_ENUM_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_RXVHF_SET                     _MK_ENUM_CONST(1)
+
+// Failed packet no: Points to the failed packet no
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_FIELD                     (_MK_MASK_CONST(0xff) << USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_RANGE                     15:8
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_WOFFSET                   0x0
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_DEFAULT_MASK                      _MK_MASK_CONST(0xff)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_PKT_NO_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Failed RX byte index: Points to the Rx byte no. in  the current packet which fails
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SHIFT                    _MK_SHIFT_CONST(0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_FIELD                    (_MK_MASK_CONST(0x3f) << USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SHIFT)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_RANGE                    5:0
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_WOFFSET                  0x0
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_IF_USB_PHY_SELF_TEST_DEBUG_0_FAIL_RX_BYTE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_PLL_CFG0_0  // USB_PHY PLL Configuration Register 0
+//
+// The data sampling frequency relies on a 960MHz clock, so the goal of the PLL is to have:
+// In_Frequency*(PLL_VCOMULTBY2+1)*(PLL_NDIV/PLL_MDIV) = 960MHz
+//
+// With a 12MHz input from PLL_U, the default setting of 
+// PLL_VCOMULTBY2=1, PLL_NDIV=40 and PLL_MDIV=1 results in a correct output.
+#define USB3_UTMIP_PLL_CFG0_0                   _MK_ADDR_CONST(0x800)
+#define USB3_UTMIP_PLL_CFG0_0_SECURE                    0x0
+#define USB3_UTMIP_PLL_CFG0_0_WORD_COUNT                        0x1
+#define USB3_UTMIP_PLL_CFG0_0_RESET_VAL                         _MK_MASK_CONST(0x280180)
+#define USB3_UTMIP_PLL_CFG0_0_RESET_MASK                        _MK_MASK_CONST(0x7fffffff)
+#define USB3_UTMIP_PLL_CFG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_READ_MASK                         _MK_MASK_CONST(0x7fffffff)
+#define USB3_UTMIP_PLL_CFG0_0_WRITE_MASK                        _MK_MASK_CONST(0x7fffffff)
+// LOCK_ENABLE input of USB_PHY PLL.
+// Normally only used during test. See cell specification.
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SHIFT)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_RANGE                        0:0
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_WOFFSET                      0x0
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// LOCKSEL[5:0] input of USB_PHY PLL.
+// Used in test modes only. See cell specification.
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT                   _MK_SHIFT_CONST(1)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_FIELD                   (_MK_MASK_CONST(0x3f) << USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SHIFT)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_RANGE                   6:1
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_WOFFSET                 0x0
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_DEFAULT_MASK                    _MK_MASK_CONST(0x3f)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_LOCKSEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// VCOMULTBY2 control of the UTMIP PHY PLL.
+// Recommended setting is on. Additional divide by 2 on the 
+// VCO feedback. Which is setting the bit to 1. See cell spec.
+//
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT                        _MK_SHIFT_CONST(7)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SHIFT)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_RANGE                        7:7
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_WOFFSET                      0x0
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_VCOMULTBY2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// MDIV[7:0] input of the USB_PHY PLL. This is the predivide on the PLL. 
+// 0x0 is not allowed. See cell specification.
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_FIELD                      (_MK_MASK_CONST(0xff) << USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SHIFT)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_RANGE                      15:8
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_WOFFSET                    0x0
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_MDIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// NDIV[7:0] input of USB_PHY PLL. 
+// This is the feedback divider on the VCO feedback. 
+// 0x0 is not allowed. See cell specification.
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT                      _MK_SHIFT_CONST(16)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_FIELD                      (_MK_MASK_CONST(0xff) << USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SHIFT)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_RANGE                      23:16
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_WOFFSET                    0x0
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT                    _MK_MASK_CONST(0x28)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_NDIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// PDIV[2:0] input of the USB_PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT                      _MK_SHIFT_CONST(24)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_FIELD                      (_MK_MASK_CONST(0x7) << USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SHIFT)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_RANGE                      26:24
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_WOFFSET                    0x0
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// PDIVRST of the UTMIP PHY PLL.
+// Reserved. Keep at 0x0. Currently there is no post divider on this PLL. 
+// See cell specification.
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT                   _MK_SHIFT_CONST(27)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SHIFT)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_RANGE                   27:27
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_WOFFSET                 0x0
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_PDIVRST_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Selects which of the eight 60MHz clock phases to produce at the output 
+// of the USB PHY PLL. This is for a test mode. See cell specification.
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT                    _MK_SHIFT_CONST(28)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_FIELD                    (_MK_MASK_CONST(0x7) << USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SHIFT)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_RANGE                    30:28
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_WOFFSET                  0x0
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG0_0_UTMIP_PLL_SELECT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_PLL_CFG1_0  // UTMIP PLL and PLLU configuration register 1
+#define USB3_UTMIP_PLL_CFG1_0                   _MK_ADDR_CONST(0x804)
+#define USB3_UTMIP_PLL_CFG1_0_SECURE                    0x0
+#define USB3_UTMIP_PLL_CFG1_0_WORD_COUNT                        0x1
+#define USB3_UTMIP_PLL_CFG1_0_RESET_VAL                         _MK_MASK_CONST(0x182000c0)
+#define USB3_UTMIP_PLL_CFG1_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_PLL_CFG1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_PLL_CFG1_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+// Determines the time to wait until the output of USB_PHY PLL is considered stable. 
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_FIELD                       (_MK_MASK_CONST(0xfff) << USB3_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SHIFT)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_RANGE                       11:0
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_WOFFSET                     0x0
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT                     _MK_MASK_CONST(0xc0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_DEFAULT_MASK                        _MK_MASK_CONST(0xfff)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_XTAL_FREQ_COUNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input off. (Overrides FORCE_PLL_ACTIVE_POWERUP.)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SHIFT)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_RANGE                    12:12
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_WOFFSET                  0x0
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_active input on. 
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT                      _MK_SHIFT_CONST(13)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SHIFT)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_RANGE                      13:13
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_WOFFSET                    0x0
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ACTIVE_POWERUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input off. (Overrides FORCE_PLL_ENABLE_POWERUP.)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT                    _MK_SHIFT_CONST(14)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SHIFT)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_RANGE                    14:14
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_WOFFSET                  0x0
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERDOWN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force USB_PHY PLL pll_enable input on. 
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT                      _MK_SHIFT_CONST(15)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SHIFT)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_RANGE                      15:15
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_WOFFSET                    0x0
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLL_ENABLE_POWERUP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power down. (Overrides FORCE_PLLU_POWERUP.)  
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_FIELD                  (_MK_MASK_CONST(0x1) << USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SHIFT)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_RANGE                  16:16
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_WOFFSET                        0x0
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force PLL_U into power up.
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SHIFT)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_RANGE                    17:17
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_WOFFSET                  0x0
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_FORCE_PLLU_POWERUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// SETUP[8:0] input of USB_PHY PLL.
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_FIELD                     (_MK_MASK_CONST(0x1ff) << USB3_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SHIFT)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_RANGE                     26:18
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_WOFFSET                   0x0
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT                   _MK_MASK_CONST(0x8)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1ff)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLL_SETUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Controls the wait time to enable PLL_U when coming out of suspend or reset.
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT                 _MK_SHIFT_CONST(27)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_FIELD                 (_MK_MASK_CONST(0x1f) << USB3_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_RANGE                 31:27
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_WOFFSET                       0x0
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT                       _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_PLL_CFG1_0_UTMIP_PLLU_ENABLE_DLY_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_XCVR_CFG0_0  // UTMIP transceiver cell configuration register 0
+#define USB3_UTMIP_XCVR_CFG0_0                  _MK_ADDR_CONST(0x808)
+#define USB3_UTMIP_XCVR_CFG0_0_SECURE                   0x0
+#define USB3_UTMIP_XCVR_CFG0_0_WORD_COUNT                       0x1
+#define USB3_UTMIP_XCVR_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x20256500)
+#define USB3_UTMIP_XCVR_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_XCVR_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_XCVR_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// SETUP[3:0] input of XCVR cell. HS driver output control. 4 LSBs.
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_FIELD                   (_MK_MASK_CONST(0xf) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_RANGE                   3:0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_WOFFSET                 0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// HS slew rate control. The two LSBs.
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT                  _MK_SHIFT_CONST(4)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_FIELD                  (_MK_MASK_CONST(0x3) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_RANGE                  5:4
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_WOFFSET                        0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// FS slew rate control.
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT                  _MK_SHIFT_CONST(6)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_FIELD                  (_MK_MASK_CONST(0x3) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_RANGE                  7:6
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_WOFFSET                        0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_FSSLEW_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// LS rising slew rate control.
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_FIELD                 (_MK_MASK_CONST(0x3) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_RANGE                 9:8
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_WOFFSET                       0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSRSLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// LS falling slew rate control.
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT                 _MK_SHIFT_CONST(10)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_FIELD                 (_MK_MASK_CONST(0x3) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_RANGE                 11:10
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_WOFFSET                       0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSFSLEW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Internal loopback inside XCVR cell. Used for IOBIST.
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT                      _MK_SHIFT_CONST(12)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_RANGE                      12:12
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_WOFFSET                    0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSLOOPBACK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Enable HS termination.
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT                  _MK_SHIFT_CONST(13)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_FIELD                  (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_RANGE                  13:13
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_WOFFSET                        0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_TERMEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force PD input into power down. (Overrides FORCE_PD_POWERUP.)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT                   _MK_SHIFT_CONST(14)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_RANGE                   14:14
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_WOFFSET                 0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERDOWN_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Force PD input into power up. 
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT                     _MK_SHIFT_CONST(15)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_RANGE                     15:15
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_WOFFSET                   0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD_POWERUP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power down. (Overrides FORCE_PD2_POWERUP.)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_FIELD                  (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_RANGE                  16:16
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_WOFFSET                        0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERDOWN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force PD2 input into power up.
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT                    _MK_SHIFT_CONST(17)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_RANGE                    17:17
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_WOFFSET                  0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PD2_POWERUP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power down. (Overrides FORCE_PDZI_POWERUP.)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_RANGE                 18:18
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_WOFFSET                       0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PDZI input into power up.
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT                   _MK_SHIFT_CONST(19)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_RANGE                   19:19
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_WOFFSET                 0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_FORCE_PDZI_POWERUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Disconnect method on the usb transceiver pad
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SHIFT                   _MK_SHIFT_CONST(20)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_RANGE                   20:20
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_WOFFSET                 0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_DISCON_METHOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Low speed bias selection method for usb transceiver pad
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SHIFT                      _MK_SHIFT_CONST(21)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_RANGE                      21:21
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_WOFFSET                    0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_LSBIAS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Most significant bits of SETUP.
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SHIFT                       _MK_SHIFT_CONST(22)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_FIELD                       (_MK_MASK_CONST(0x7) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_RANGE                       24:22
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_WOFFSET                     0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_SETUP_MSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Most significant bits of HS_SLEW.
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SHIFT                      _MK_SHIFT_CONST(25)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_FIELD                      (_MK_MASK_CONST(0x7f) << USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_RANGE                      31:25
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_WOFFSET                    0x0
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_DEFAULT                    _MK_MASK_CONST(0x10)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_DEFAULT_MASK                       _MK_MASK_CONST(0x7f)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG0_0_UTMIP_XCVR_HSSLEW_MSB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_BIAS_CFG0_0  // UTMIP Bias cell configuration register 0
+#define USB3_UTMIP_BIAS_CFG0_0                  _MK_ADDR_CONST(0x80c)
+#define USB3_UTMIP_BIAS_CFG0_0_SECURE                   0x0
+#define USB3_UTMIP_BIAS_CFG0_0_WORD_COUNT                       0x1
+#define USB3_UTMIP_BIAS_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x800)
+#define USB3_UTMIP_BIAS_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x1ffffff)
+#define USB3_UTMIP_BIAS_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x1ffffff)
+#define USB3_UTMIP_BIAS_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x1ffffff)
+// HS squelch detector level.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_FIELD                      (_MK_MASK_CONST(0x3) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_RANGE                      1:0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_WOFFSET                    0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSSQUELCH_LEVEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// HS disconnect detector level.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_FIELD                       (_MK_MASK_CONST(0x3) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_RANGE                       3:2
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_WOFFSET                     0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// HS chirp detector level.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_FIELD                        (_MK_MASK_CONST(0x3) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_RANGE                        5:4
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_WOFFSET                      0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSCHIRP_LEVEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// SessionEnd detector level.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT                     _MK_SHIFT_CONST(6)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_FIELD                     (_MK_MASK_CONST(0x3) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_RANGE                     7:6
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_WOFFSET                   0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_SESS_LEVEL_LEVEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Vbus detector level.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_FIELD                     (_MK_MASK_CONST(0x3) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_RANGE                     9:8
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_WOFFSET                   0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_VBUS_LEVEL_LEVEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Power down bias circuit.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT                       _MK_SHIFT_CONST(10)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_FIELD                       (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_RANGE                       10:10
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_WOFFSET                     0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_BIASPD_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Power down OTG circuit.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT                        _MK_SHIFT_CONST(11)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_RANGE                        11:11
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_WOFFSET                      0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_OTGPD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Active 1.5K pullup control offset.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT                 _MK_SHIFT_CONST(12)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_FIELD                 (_MK_MASK_CONST(0x7) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_RANGE                 14:12
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_WOFFSET                       0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_PULLUP_OFFSET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Active termination control offset.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT                   _MK_SHIFT_CONST(15)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_FIELD                   (_MK_MASK_CONST(0x7) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_RANGE                   17:15
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_WOFFSET                 0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_ACTIVE_TERM_OFFSET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// 0: StaticGpi = IdDig. 1: StaticGpi = GPI_VAL.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT                      _MK_SHIFT_CONST(18)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_RANGE                      18:18
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_WOFFSET                    0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// See GPI_SEL.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT                      _MK_SHIFT_CONST(19)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_RANGE                      19:19
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_WOFFSET                    0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_GPI_VAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 0: IdDig = IdDig. 1: IdDig = IDDIG_VAL.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT                    _MK_SHIFT_CONST(20)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_RANGE                    20:20
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_WOFFSET                  0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_SEL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// See IDDIG_SEL.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_RANGE                    21:21
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_WOFFSET                  0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDDIG_VAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 0: IDPD = ~IdPullup. 1: IDPD = IDPD_VAL.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT                     _MK_SHIFT_CONST(22)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_RANGE                     22:22
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_WOFFSET                   0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// See IDPD_SEL.
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT                     _MK_SHIFT_CONST(23)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_RANGE                     23:23
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_WOFFSET                   0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_IDPD_VAL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Most significant bit of UTMIP_HSDISCON_LEVEL, bit 2
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SHIFT                   _MK_SHIFT_CONST(24)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SHIFT)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_RANGE                   24:24
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_WOFFSET                 0x0
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG0_0_UTMIP_HSDISCON_LEVEL_MSB_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_HSRX_CFG0_0  // UTMIP High speed receive config 0 
+#define USB3_UTMIP_HSRX_CFG0_0                  _MK_ADDR_CONST(0x810)
+#define USB3_UTMIP_HSRX_CFG0_0_SECURE                   0x0
+#define USB3_UTMIP_HSRX_CFG0_0_WORD_COUNT                       0x1
+#define USB3_UTMIP_HSRX_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x91653400)
+#define USB3_UTMIP_HSRX_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_HSRX_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_HSRX_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0xffffffff)
+// Require 4 sync pattern transitions (01) instead of 3
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_RANGE                        0:0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_WOFFSET                      0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_USE4SYNC_TRAN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Sync pattern detection needs 3 consecutive samples instead of 4
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_FIELD                       (_MK_MASK_CONST(0x1) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_RANGE                       1:1
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_WOFFSET                     0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_THREE_SYNCBITS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Based on incoming edges and current sampling position, adjust phase
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT                 _MK_SHIFT_CONST(2)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_FIELD                 (_MK_MASK_CONST(0x3) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_RANGE                 3:2
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_WOFFSET                       0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PHASE_ADJUST_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Retime the path. 
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT                       _MK_SHIFT_CONST(4)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_FIELD                       (_MK_MASK_CONST(0x3) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_RANGE                       5:4
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_WOFFSET                     0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_INERTIA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Pass through the feedback, do not block it.
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT                        _MK_SHIFT_CONST(6)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_RANGE                        6:6
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_WOFFSET                      0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_FEEDBACK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// When in Chirp Mode, allow chirp rx data through
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT                   _MK_SHIFT_CONST(7)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_RANGE                   7:7
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_WOFFSET                 0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PASS_CHIRP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Do not declare underrun errors
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT                     _MK_SHIFT_CONST(8)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_RANGE                     8:8
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_WOFFSET                   0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_UNDERRUN_DISABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Do not declare overrun errors until overflow of FIFO
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT                      _MK_SHIFT_CONST(9)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_RANGE                      9:9
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_WOFFSET                    0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_OVERRUN_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Depth of elastic input store
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT                        _MK_SHIFT_CONST(10)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_FIELD                        (_MK_MASK_CONST(0x1f) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_RANGE                        14:10
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_WOFFSET                      0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT                      _MK_MASK_CONST(0xd)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ELASTIC_LIMIT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Number of cycles of idle to declare IDLE. 
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT                    _MK_SHIFT_CONST(15)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_FIELD                    (_MK_MASK_CONST(0x1f) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_RANGE                    19:15
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_WOFFSET                  0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT                  _MK_MASK_CONST(0xa)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_IDLE_WAIT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Do not strip incoming data
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT                 _MK_SHIFT_CONST(20)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_RANGE                 20:20
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_WOFFSET                       0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_NO_STRIPPING_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Limit the delay of the squelch at EOP time
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT                      _MK_SHIFT_CONST(21)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_FIELD                      (_MK_MASK_CONST(0x7) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_RANGE                      23:21
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_WOFFSET                    0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT                    _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_SQUELCH_EOP_DLY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// The number of (edges-1) needed to move the sampling point
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT                      _MK_SHIFT_CONST(24)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_FIELD                      (_MK_MASK_CONST(0xf) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_RANGE                      27:24
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_WOFFSET                    0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_DEFAULT_MASK                       _MK_MASK_CONST(0xf)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_PCOUNT_UPDN_DIV_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Realign the inertia counters on a new packet
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT                   _MK_SHIFT_CONST(28)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_RANGE                   28:28
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_WOFFSET                 0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_REALIGN_ON_NEW_PKT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Allow consecutive ups and downs on the bits, debug only, set to 0.
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT                    _MK_SHIFT_CONST(29)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_RANGE                    29:29
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_WOFFSET                  0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_ALLOW_CONSEC_UPDN_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Keep the stay alive pattern on active
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT                  _MK_SHIFT_CONST(30)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_FIELD                  (_MK_MASK_CONST(0x3) << USB3_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SHIFT)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_RANGE                  31:30
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_WOFFSET                        0x0
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT                        _MK_MASK_CONST(0x2)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG0_0_UTMIP_KEEP_PATT_ON_ACTIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_HSRX_CFG1_0  // UTMIP High speed receive config 1
+#define USB3_UTMIP_HSRX_CFG1_0                  _MK_ADDR_CONST(0x814)
+#define USB3_UTMIP_HSRX_CFG1_0_SECURE                   0x0
+#define USB3_UTMIP_HSRX_CFG1_0_WORD_COUNT                       0x1
+#define USB3_UTMIP_HSRX_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x13)
+#define USB3_UTMIP_HSRX_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0x3f)
+#define USB3_UTMIP_HSRX_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG1_0_READ_MASK                        _MK_MASK_CONST(0x3f)
+#define USB3_UTMIP_HSRX_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0x3f)
+// Allow Keep Alive packets 
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_FIELD                  (_MK_MASK_CONST(0x1) << USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SHIFT)
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_RANGE                  0:0
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_WOFFSET                        0x0
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_ALLOW_KEEP_ALIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// How long to wait before start of sync launches RxActive
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_FIELD                    (_MK_MASK_CONST(0x1f) << USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SHIFT)
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_RANGE                    5:1
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_WOFFSET                  0x0
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT                  _MK_MASK_CONST(0x9)
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_DEFAULT_MASK                     _MK_MASK_CONST(0x1f)
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_HSRX_CFG1_0_UTMIP_HS_SYNC_START_DLY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_FSLSRX_CFG0_0  // UTMIP full and Low speed receive config 0
+#define USB3_UTMIP_FSLSRX_CFG0_0                        _MK_ADDR_CONST(0x818)
+#define USB3_UTMIP_FSLSRX_CFG0_0_SECURE                         0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_WORD_COUNT                     0x1
+#define USB3_UTMIP_FSLSRX_CFG0_0_RESET_VAL                      _MK_MASK_CONST(0xfd548429)
+#define USB3_UTMIP_FSLSRX_CFG0_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_FSLSRX_CFG0_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Give up on packet if a long sequence of J 
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_RANGE                      0:0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_WOFFSET                    0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_LIMIT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 20 bits of idle should end the packet if FsLsIdleCountLimitCfg=1.
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_FIELD                        (_MK_MASK_CONST(0x3f) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_RANGE                        6:1
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_WOFFSET                      0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT                      _MK_MASK_CONST(0x14)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_COUNT_MAX_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Enable the reset of the state machine on extended SE0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT                       _MK_SHIFT_CONST(7)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_FIELD                       (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_RANGE                       7:7
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_WOFFSET                     0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_LIMIT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 4 bits of of SEO should exceed the time limit
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT                 _MK_SHIFT_CONST(8)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_FIELD                 (_MK_MASK_CONST(0x3f) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_RANGE                 13:8
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_WOFFSET                       0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT                       _MK_MASK_CONST(0x4)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_IDLE_WAIT_MAX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Require a full sync pattern to declare the data received
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT                   _MK_SHIFT_CONST(14)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_RANGE                   14:14
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_WOFFSET                 0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_ACTIVE_ON_FULL_SYNC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Limit the number of bit times a K can last
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT                  _MK_SHIFT_CONST(15)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_FIELD                  (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_RANGE                  15:15
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_WOFFSET                        0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_LIMIT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Number of K bits in question
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_FIELD                    (_MK_MASK_CONST(0x3f) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_RANGE                    21:16
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_WOFFSET                  0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT                  _MK_MASK_CONST(0x14)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_DEFAULT_MASK                     _MK_MASK_CONST(0x3f)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_KCOUNT_MAX_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Only look for transitioning out of EOP
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT                       _MK_SHIFT_CONST(22)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_FIELD                       (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_RANGE                       22:22
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_WOFFSET                     0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_EOP_ENDS_AT_SE0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Do not allow >= dribble bits 
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT                      _MK_SHIFT_CONST(23)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_FIELD                      (_MK_MASK_CONST(0x7) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_RANGE                      25:23
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_WOFFSET                    0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_LWR_DRIBBLE_SIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Do not allow <= dribble bits
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT                      _MK_SHIFT_CONST(26)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_FIELD                      (_MK_MASK_CONST(0x7) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_RANGE                      28:26
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_WOFFSET                    0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT                    _MK_MASK_CONST(0x7)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_UPR_DRIBBLE_SIZE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT                        _MK_SHIFT_CONST(29)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_RANGE                        29:29
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_WOFFSET                      0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SERIAL_SE0_RCV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Filter SE1
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT                    _MK_SHIFT_CONST(30)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_RANGE                    30:30
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_WOFFSET                  0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_FILTER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// One SE1, don't allow dribble
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT                    _MK_SHIFT_CONST(31)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_RANGE                    31:31
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_WOFFSET                  0x0
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG0_0_UTMIP_FSLS_SE1_DRIBBLE_FILTER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_FSLSRX_CFG1_0  // UTMIP full and Low speed receive config 1
+#define USB3_UTMIP_FSLSRX_CFG1_0                        _MK_ADDR_CONST(0x81c)
+#define USB3_UTMIP_FSLSRX_CFG1_0_SECURE                         0x0
+#define USB3_UTMIP_FSLSRX_CFG1_0_WORD_COUNT                     0x1
+#define USB3_UTMIP_FSLSRX_CFG1_0_RESET_VAL                      _MK_MASK_CONST(0x2267400)
+#define USB3_UTMIP_FSLSRX_CFG1_0_RESET_MASK                     _MK_MASK_CONST(0x7ffffff)
+#define USB3_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_READ_MASK                      _MK_MASK_CONST(0x7ffffff)
+#define USB3_UTMIP_FSLSRX_CFG1_0_WRITE_MASK                     _MK_MASK_CONST(0x7ffffff)
+// Whether full speed EOP  is determined within 3(0) or 4(1) 60MHz cycles
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_RANGE                      0:0
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_WOFFSET                    0x0
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_EOP_LENGTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Whether full speed uses debouncing
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT                        _MK_SHIFT_CONST(1)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_RANGE                        1:1
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_WOFFSET                      0x0
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_DEBOUNCE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Only look for a KK pattern, instead of KJKK
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_FIELD                       (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_RANGE                       2:2
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_WOFFSET                     0x0
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_WEAK_SYNC_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in full speed mode
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_RANGE                 3:3
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_WOFFSET                       0x0
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_FS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Allow for large dribble in low  speed mode
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_RANGE                 4:4
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_WOFFSET                       0x0
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_LENIENT_DRIBBLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Only for this number of 60MHz of SEO and Idle to end packet
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT                       _MK_SHIFT_CONST(5)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_FIELD                       (_MK_MASK_CONST(0x3f) << USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_RANGE                       10:5
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_WOFFSET                     0x0
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT                     _MK_MASK_CONST(0x20)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_DEFAULT_MASK                        _MK_MASK_CONST(0x3f)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_SE0_COUNT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Number of SEO clock cycles to block bit extraction
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT                 _MK_SHIFT_CONST(11)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_FIELD                 (_MK_MASK_CONST(0x3f) << USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_RANGE                 16:11
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_WOFFSET                       0x0
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT                       _MK_MASK_CONST(0xe)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x3f)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EOP_START_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Phase count on which LS bits are extracted
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT                        _MK_SHIFT_CONST(17)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_FIELD                        (_MK_MASK_CONST(0x3f) << USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_RANGE                        22:17
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_WOFFSET                      0x0
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT                      _MK_MASK_CONST(0x13)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x3f)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_EXTRACTION_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Number of clock cycle of LS stable
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT                   _MK_SHIFT_CONST(23)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_FIELD                   (_MK_MASK_CONST(0x7) << USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_RANGE                   25:23
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_WOFFSET                 0x0
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT                 _MK_MASK_CONST(0x4)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_DEFAULT_MASK                    _MK_MASK_CONST(0x7)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_LS_BOUNCE_LENGTH_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Assumes line state filtering table is inclusive, not exclusive
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT                    _MK_SHIFT_CONST(26)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SHIFT)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_RANGE                    26:26
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_WOFFSET                  0x0
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_FSLSRX_CFG1_0_UTMIP_EARLY_LINE_STATE_FILTER_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_TX_CFG0_0  // UTMIP transmit config signals 
+#define USB3_UTMIP_TX_CFG0_0                    _MK_ADDR_CONST(0x820)
+#define USB3_UTMIP_TX_CFG0_0_SECURE                     0x0
+#define USB3_UTMIP_TX_CFG0_0_WORD_COUNT                         0x1
+#define USB3_UTMIP_TX_CFG0_0_RESET_VAL                  _MK_MASK_CONST(0x10200)
+#define USB3_UTMIP_TX_CFG0_0_RESET_MASK                         _MK_MASK_CONST(0xfffff)
+#define USB3_UTMIP_TX_CFG0_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_READ_MASK                  _MK_MASK_CONST(0xfffff)
+#define USB3_UTMIP_TX_CFG0_0_WRITE_MASK                         _MK_MASK_CONST(0xfffff)
+// Do not sent SYNC or EOP
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT                 _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_RANGE                 0:0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_WOFFSET                       0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_SYNC_NO_EOP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// No encoding, static programming
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_RANGE                    1:1
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_WOFFSET                  0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_ENCODING_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// No bit stuffing, static programming
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT                    _MK_SHIFT_CONST(2)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_RANGE                    2:2
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_WOFFSET                  0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_NO_STUFFING_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 2 -- not likely, for Chirp
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT                       _MK_SHIFT_CONST(3)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_FIELD                       (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_RANGE                       3:3
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_WOFFSET                     0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_ENCODE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Sof when OpMode 3 -- perhaps, when sending controller made packets
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_RANGE                        4:4
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_WOFFSET                      0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SOF_ON_NO_STUFF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// SIE, not macrocell, detects LineState change to resume
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT                        _MK_SHIFT_CONST(5)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_RANGE                        5:5
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_WOFFSET                      0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_SIE_RESUME_ON_LINESTATE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// output enable turns on  1 cycle before
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT                      _MK_SHIFT_CONST(6)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_RANGE                      6:6
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                    0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// output enable turns off 1 cycle after
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                     _MK_SHIFT_CONST(7)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_RANGE                     7:7
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                   0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Disable high speed disconnect
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_RANGE                      8:8
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_WOFFSET                    0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_DISABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Only check during EOP
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT                     _MK_SHIFT_CONST(9)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_RANGE                     9:9
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_WOFFSET                   0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_DISCON_EOP_ONLY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT                  _MK_SHIFT_CONST(10)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_FIELD                  (_MK_MASK_CONST(0x1f) << USB3_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_RANGE                  14:10
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_WOFFSET                        0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_DEFAULT_MASK                   _MK_MASK_CONST(0x1f)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_TX_IPG_DLY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT                        _MK_SHIFT_CONST(15)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_RANGE                        15:15
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_WOFFSET                      0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_HS_READY_WAIT_FOR_VALID_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Allow SOP to be source of transmit error stuffing
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT                    _MK_SHIFT_CONST(16)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_RANGE                    16:16
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_WOFFSET                  0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FSLS_ALLOW_SOP_TX_STUFF_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// output enable turns on  1/2 cycle before
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT                      _MK_SHIFT_CONST(17)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_RANGE                      17:17
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_WOFFSET                    0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// output enable turns off 1/2 cycle after 
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT                     _MK_SHIFT_CONST(18)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_RANGE                     18:18
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_WOFFSET                   0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_POSTAMBLE_OUTPUT_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// output enable sends an initial J before sync pattern
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT                  _MK_SHIFT_CONST(19)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_FIELD                  (_MK_MASK_CONST(0x1) << USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SHIFT)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_RANGE                  19:19
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_WOFFSET                        0x0
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_TX_CFG0_0_UTMIP_FS_PREAMBLE_J_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_MISC_CFG0_0  // UTMIP miscellaneous configurations
+#define USB3_UTMIP_MISC_CFG0_0                  _MK_ADDR_CONST(0x824)
+#define USB3_UTMIP_MISC_CFG0_0_SECURE                   0x0
+#define USB3_UTMIP_MISC_CFG0_0_WORD_COUNT                       0x1
+#define USB3_UTMIP_MISC_CFG0_0_RESET_VAL                        _MK_MASK_CONST(0x3e00078)
+#define USB3_UTMIP_MISC_CFG0_0_RESET_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define USB3_UTMIP_MISC_CFG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_READ_MASK                        _MK_MASK_CONST(0x7fffffff)
+#define USB3_UTMIP_MISC_CFG0_0_WRITE_MASK                       _MK_MASK_CONST(0x7fffffff)
+// Use combinational terminations or synced through CLKXTAL
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT                   _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_RANGE                   0:0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_WOFFSET                 0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_COMB_TERMS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Use free running terminations at all time
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT                    _MK_SHIFT_CONST(1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_RANGE                    1:1
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_WOFFSET                  0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALWAYS_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Ignore free running terminations, even when no clock
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT                     _MK_SHIFT_CONST(2)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_RANGE                     2:2
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_WOFFSET                   0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NEVER_FREE_RUNNING_TERMS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Don't use free running terminations during suspend.
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_RANGE                   3:3
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_WOFFSET                 0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_NO_FREE_ON_SUSPEND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Determines if all signal need to be stable to not change a config.
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT                   _MK_SHIFT_CONST(4)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_RANGE                   4:4
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_WOFFSET                 0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_ALL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Number of cycles of crystal clock of signal not changing to consider stable.
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT                 _MK_SHIFT_CONST(5)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_FIELD                 (_MK_MASK_CONST(0x7) << USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_RANGE                 7:5
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_WOFFSET                       0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT                       _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_STABLE_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force DM pulldown active.
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_RANGE                      8:8
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_WOFFSET                    0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force DP pulldown active.
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT                      _MK_SHIFT_CONST(9)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_RANGE                      9:9
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_WOFFSET                    0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLDN_DP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force DM pullup active.      
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT                      _MK_SHIFT_CONST(10)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_RANGE                      10:10
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_WOFFSET                    0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force DP pullup active.
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT                      _MK_SHIFT_CONST(11)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_RANGE                      11:11
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_WOFFSET                    0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_PULLUP_DP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force DM pulldown inactive. (Overrides FORCE_PULLDN_DM.)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT                    _MK_SHIFT_CONST(12)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_RANGE                    12:12
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_WOFFSET                  0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force DP pulldown inactive. (Overrides FORCE_PULLDN_DP.)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT                    _MK_SHIFT_CONST(13)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_RANGE                    13:13
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_WOFFSET                  0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLDN_DP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force DM pullup inactive. (Overrides FORCE_PULLUP_DM.)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT                    _MK_SHIFT_CONST(14)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_RANGE                    14:14
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_WOFFSET                  0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force DP pullup inactive. (Overrides FORCE_PULLUP_DP.)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT                    _MK_SHIFT_CONST(15)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_RANGE                    15:15
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_WOFFSET                  0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_PULLUP_DP_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force HS termination active.
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_RANGE                        16:16
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_WOFFSET                      0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_TERM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force HS termination inactive.
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT                      _MK_SHIFT_CONST(17)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_RANGE                      17:17
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_WOFFSET                    0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DISABLE_HS_TERM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Force HS clock always on.
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT                    _MK_SHIFT_CONST(18)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_RANGE                    18:18
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_WOFFSET                  0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_HS_CLOCK_ON_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Force error insertion into RX path. (Used for IOBIST.)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT                    _MK_SHIFT_CONST(19)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_FIELD                    (_MK_MASK_CONST(0x3) << USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RANGE                    20:19
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_WOFFSET                  0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_DISABLE                  _MK_ENUM_CONST(0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_ERR                  _MK_ENUM_CONST(1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_RX_ERR                   _MK_ENUM_CONST(2)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_INJECT_ERROR_TYPE_BIT_RX_ERR                       _MK_ENUM_CONST(3)
+
+// Don't block changes for 4ms when going from LS to FS (should not happen)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT                    _MK_SHIFT_CONST(21)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_FIELD                    (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_RANGE                    21:21
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_WOFFSET                  0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_LS_TO_FS_SKIP_4MS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Suspend exit requires edge or simply a value...
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT                 _MK_SHIFT_CONST(22)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_RANGE                 22:22
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_WOFFSET                       0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_SUSPEND_EXIT_ON_EDGE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT                        _MK_SHIFT_CONST(23)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_RANGE                        23:23
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_WOFFSET                      0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_FORCE_FS_DISABLE_ON_DEV_CHIRP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT                      _MK_SHIFT_CONST(24)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_RANGE                      24:24
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_WOFFSET                    0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_ALLOW_LS_ON_SOFT_DISCON_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT                  _MK_SHIFT_CONST(25)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_FIELD                  (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_RANGE                  25:25
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_WOFFSET                        0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_KEEP_XCVR_PD_ON_SOFT_DISCON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Use DP/DM as obs bus
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT                 _MK_SHIFT_CONST(26)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_RANGE                 26:26
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_WOFFSET                       0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Select DP/DM obs signals
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT                     _MK_SHIFT_CONST(27)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_FIELD                     (_MK_MASK_CONST(0xf) << USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SHIFT)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_RANGE                     30:27
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_WOFFSET                   0x0
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG0_0_UTMIP_DPDM_OBSERVE_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_MISC_CFG1_0  // UTMIP miscellaneous configurations
+#define USB3_UTMIP_MISC_CFG1_0                  _MK_ADDR_CONST(0x828)
+#define USB3_UTMIP_MISC_CFG1_0_SECURE                   0x0
+#define USB3_UTMIP_MISC_CFG1_0_WORD_COUNT                       0x1
+#define USB3_UTMIP_MISC_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x40198024)
+#define USB3_UTMIP_MISC_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0x7fffffff)
+#define USB3_UTMIP_MISC_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_READ_MASK                        _MK_MASK_CONST(0x7fffffff)
+#define USB3_UTMIP_MISC_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0x7fffffff)
+// Bit 0: 0: 0xa5 -> treat as KeepAlive 
+//        1: treat as regular packet 
+// Bit 1: 0: Turn on FS EOP detection
+//        1: Turn off FS EOP detection
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_FIELD                     (_MK_MASK_CONST(0x3) << USB3_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_RANGE                     1:0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_WOFFSET                   0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_XCVRSEL3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT                      _MK_SHIFT_CONST(2)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_RANGE                      2:2
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_WOFFSET                    0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_SUSPEND_TERMSEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT                   _MK_SHIFT_CONST(3)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_RANGE                   3:3
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_WOFFSET                 0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FLIP_FSLS_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT                      _MK_SHIFT_CONST(4)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_FIELD                      (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_RANGE                      4:4
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_WOFFSET                    0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT                     _MK_SHIFT_CONST(5)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_RANGE                     5:5
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_WOFFSET                   0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_RX_ERROR_CNT_CLR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// WRONG! This should be 1ms -> 0x50
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT                    _MK_SHIFT_CONST(6)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_FIELD                    (_MK_MASK_CONST(0xfff) << USB3_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_RANGE                    17:6
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_WOFFSET                  0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT                  _MK_MASK_CONST(0x600)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLLU_STABLE_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// 5 us / (1/19.2MHz) = 96 / 16 = 6
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT                 _MK_SHIFT_CONST(18)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_FIELD                 (_MK_MASK_CONST(0x1f) << USB3_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_RANGE                 22:18
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_WOFFSET                       0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT                       _MK_MASK_CONST(0x6)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PLL_ACTIVE_DLY_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT                  _MK_SHIFT_CONST(23)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_FIELD                  (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_RANGE                  23:23
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_WOFFSET                        0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FORCE_IOBIST_CLK_ON_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT                     _MK_SHIFT_CONST(24)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_RANGE                     24:24
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_WOFFSET                   0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_FSLS_TDM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT                      _MK_SHIFT_CONST(25)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_FIELD                      (_MK_MASK_CONST(0x3) << USB3_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_RANGE                      26:25
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_WOFFSET                    0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_OBS_SEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// 0: Use FS filtering on line state when XcvrSel=3
+// 1: Use LS filtering on line state when XcvrSel=3
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT                   _MK_SHIFT_CONST(27)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_RANGE                   27:27
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_WOFFSET                 0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_XCVRSEL3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Use neg edge sync for linestate
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT                        _MK_SHIFT_CONST(28)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_RANGE                        28:28
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_WOFFSET                      0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_NEG_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Bypass LineState reclocking logic
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT                     _MK_SHIFT_CONST(29)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_RANGE                     29:29
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_WOFFSET                   0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_LINESTATE_BYPASS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Selects whether to enable the crystal clock in the module.
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT                     _MK_SHIFT_CONST(30)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_FIELD                     (_MK_MASK_CONST(0x1) << USB3_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SHIFT)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_RANGE                     30:30
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_WOFFSET                   0x0
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_MISC_CFG1_0_UTMIP_PHY_XTAL_CLOCKEN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_DEBOUNCE_CFG0_0  // UTMIP Avalid and Bvalid debounce
+#define USB3_UTMIP_DEBOUNCE_CFG0_0                      _MK_ADDR_CONST(0x82c)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_SECURE                       0x0
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_WORD_COUNT                   0x1
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// simulation value -- Used for interrupts
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_FIELD                  (_MK_MASK_CONST(0xffff) << USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SHIFT)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_RANGE                  15:0
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_WOFFSET                        0x0
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT                        _MK_MASK_CONST(0xffff)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_A_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// simulation value -- Used for interrupts
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT                  _MK_SHIFT_CONST(16)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_FIELD                  (_MK_MASK_CONST(0xffff) << USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SHIFT)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_RANGE                  31:16
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_WOFFSET                        0x0
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT                        _MK_MASK_CONST(0xffff)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_DEFAULT_MASK                   _MK_MASK_CONST(0xffff)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_DEBOUNCE_CFG0_0_UTMIP_BIAS_DEBOUNCE_B_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_BAT_CHRG_CFG0_0  // UTMIP battery charger configuration
+#define USB3_UTMIP_BAT_CHRG_CFG0_0                      _MK_ADDR_CONST(0x830)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_SECURE                       0x0
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_WORD_COUNT                   0x1
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_RESET_VAL                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_RESET_MASK                   _MK_MASK_CONST(0x1f)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_READ_MASK                    _MK_MASK_CONST(0x1f)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_WRITE_MASK                   _MK_MASK_CONST(0x1f)
+// Power down charger circuit
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT                  _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_FIELD                  (_MK_MASK_CONST(0x1) << USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SHIFT)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_RANGE                  0:0
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_WOFFSET                        0x0
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_PD_CHRG_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT                       _MK_SHIFT_CONST(1)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SHIFT)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_RANGE                       1:1
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_WOFFSET                     0x0
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SINK_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_FIELD                       (_MK_MASK_CONST(0x1) << USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SHIFT)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_RANGE                       2:2
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_WOFFSET                     0x0
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SINK_EN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT                        _MK_SHIFT_CONST(3)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SHIFT)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_RANGE                        3:3
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_WOFFSET                      0x0
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_OP_SRC_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT                        _MK_SHIFT_CONST(4)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SHIFT)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_RANGE                        4:4
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_WOFFSET                      0x0
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BAT_CHRG_CFG0_0_UTMIP_ON_SRC_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_SPARE_CFG0_0  // Utmip spare configuration bits 
+#define USB3_UTMIP_SPARE_CFG0_0                 _MK_ADDR_CONST(0x834)
+#define USB3_UTMIP_SPARE_CFG0_0_SECURE                  0x0
+#define USB3_UTMIP_SPARE_CFG0_0_WORD_COUNT                      0x1
+#define USB3_UTMIP_SPARE_CFG0_0_RESET_VAL                       _MK_MASK_CONST(0xffff0000)
+#define USB3_UTMIP_SPARE_CFG0_0_RESET_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_SPARE_CFG0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_SPARE_CFG0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_SPARE_CFG0_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_SPARE_CFG0_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// Spare register bits
+// 0: HS_RX_IPG_ERROR_ENABLE
+// 1: HS_RX_FLUSH_ALAP. Flush as late as possible
+// 2: HS_RX_LATE_SQUELCH. Delay Squelch by 1 CLK480 cycle.
+// 31 to 3: Reserved
+#define USB3_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB3_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SHIFT)
+#define USB3_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_RANGE                       31:0
+#define USB3_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_WOFFSET                     0x0
+#define USB3_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT                     _MK_MASK_CONST(0xffff0000)
+#define USB3_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_SPARE_CFG0_0_UTMIP_SPARE_INIT_ENUM                   -65536
+
+
+// Register USB3_UTMIP_XCVR_CFG1_0  // UTMIP transceiver cell configuration register 1
+#define USB3_UTMIP_XCVR_CFG1_0                  _MK_ADDR_CONST(0x838)
+#define USB3_UTMIP_XCVR_CFG1_0_SECURE                   0x0
+#define USB3_UTMIP_XCVR_CFG1_0_WORD_COUNT                       0x1
+#define USB3_UTMIP_XCVR_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x823f)
+#define USB3_UTMIP_XCVR_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0xffffff)
+#define USB3_UTMIP_XCVR_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_READ_MASK                        _MK_MASK_CONST(0xffffff)
+#define USB3_UTMIP_XCVR_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0xffffff)
+// Force PDDISC input into power down. (Overrides FORCE_PDDISC_POWERUP.)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_FIELD                       (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_RANGE                       0:0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_WOFFSET                     0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Force PDDISC input into power up.
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SHIFT                 _MK_SHIFT_CONST(1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_RANGE                 1:1
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_WOFFSET                       0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDISC_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PDCHRP input input into power down. (Overrides FORCE_PDCHRP_POWERUP.)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SHIFT                       _MK_SHIFT_CONST(2)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_FIELD                       (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_RANGE                       2:2
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_WOFFSET                     0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_DEFAULT                     _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERDOWN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Force PDCHRP input into power up.
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SHIFT                 _MK_SHIFT_CONST(3)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_RANGE                 3:3
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_WOFFSET                       0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDCHRP_POWERUP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PDDR input input into power down. (Overrides FORCE_PDDR_POWERUP.)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SHIFT                 _MK_SHIFT_CONST(4)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_RANGE                 4:4
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_WOFFSET                       0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_DEFAULT                       _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERDOWN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Force PDDR input into power up.
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SHIFT                   _MK_SHIFT_CONST(5)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_FIELD                   (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_RANGE                   5:5
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_WOFFSET                 0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_DEFAULT                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_FORCE_PDDR_POWERUP_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Encoded value to use on TCTRL when software override is enabled, 0 to 16 only
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SHIFT                 _MK_SHIFT_CONST(6)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_FIELD                 (_MK_MASK_CONST(0x1f) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_RANGE                 10:6
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_WOFFSET                       0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Use a software override on TCTRL instead of automatic bias control
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SHIFT                 _MK_SHIFT_CONST(11)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_RANGE                 11:11
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_WOFFSET                       0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_TCTRL_SW_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Encoded value to use on RCTRL when software override is enabled, 0 to 16 only
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SHIFT                 _MK_SHIFT_CONST(12)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_FIELD                 (_MK_MASK_CONST(0x1f) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_RANGE                 16:12
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_WOFFSET                       0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_DEFAULT                       _MK_MASK_CONST(0x8)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_DEFAULT_MASK                  _MK_MASK_CONST(0x1f)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_VAL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Use a software override on RCTRL instead of automatic bias control
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SHIFT                 _MK_SHIFT_CONST(17)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_FIELD                 (_MK_MASK_CONST(0x1) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_RANGE                 17:17
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_WOFFSET                       0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_RCTRL_SW_SET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Range adjusment on terminations.
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT                  _MK_SHIFT_CONST(18)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_FIELD                  (_MK_MASK_CONST(0xf) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_RANGE                  21:18
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_WOFFSET                        0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_DEFAULT_MASK                   _MK_MASK_CONST(0xf)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_TERM_RANGE_ADJ_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Spare bits for usb transceiver pad ECO.
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SHIFT                   _MK_SHIFT_CONST(22)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_FIELD                   (_MK_MASK_CONST(0x3) << USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SHIFT)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_RANGE                   23:22
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_WOFFSET                 0x0
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_XCVR_CFG1_0_UTMIP_XCVR_SPARE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_BIAS_CFG1_0  // UTMIP Bias cell configuration register 1
+#define USB3_UTMIP_BIAS_CFG1_0                  _MK_ADDR_CONST(0x83c)
+#define USB3_UTMIP_BIAS_CFG1_0_SECURE                   0x0
+#define USB3_UTMIP_BIAS_CFG1_0_WORD_COUNT                       0x1
+#define USB3_UTMIP_BIAS_CFG1_0_RESET_VAL                        _MK_MASK_CONST(0x2a)
+#define USB3_UTMIP_BIAS_CFG1_0_RESET_MASK                       _MK_MASK_CONST(0x3fff)
+#define USB3_UTMIP_BIAS_CFG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG1_0_READ_MASK                        _MK_MASK_CONST(0x3fff)
+#define USB3_UTMIP_BIAS_CFG1_0_WRITE_MASK                       _MK_MASK_CONST(0x3fff)
+// Force PDTRK input into power down. (Overrides FORCE_PDTRK_POWERUP.)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SHIFT)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_RANGE                        0:0
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_WOFFSET                      0x0
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Force PDTRK input into power up.
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SHIFT                  _MK_SHIFT_CONST(1)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_FIELD                  (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SHIFT)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_RANGE                  1:1
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_WOFFSET                        0x0
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_DEFAULT                        _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_FORCE_PDTRK_POWERUP_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Force VBUS_WAKEUP input into power down.
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SHIFT                        _MK_SHIFT_CONST(2)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_FIELD                        (_MK_MASK_CONST(0x1) << USB3_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SHIFT)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_RANGE                        2:2
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_WOFFSET                      0x0
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_VBUS_WAKEUP_POWERDOWN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Control the BIAS cell power down lag. The lag should be 20us. For a Xtal clock of 13MHz it should be set a 5. 
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SHIFT                     _MK_SHIFT_CONST(3)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_FIELD                     (_MK_MASK_CONST(0x1f) << USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SHIFT)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_RANGE                     7:3
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_WOFFSET                   0x0
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_DEFAULT                   _MK_MASK_CONST(0x5)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_DEFAULT_MASK                      _MK_MASK_CONST(0x1f)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_PDTRK_COUNT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Debouncer time scaling, factor-1 to slow down debouncing by. So 0 is 1, 1 is 2, etc.
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT                      _MK_SHIFT_CONST(8)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_FIELD                      (_MK_MASK_CONST(0x3f) << USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_RANGE                      13:8
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_WOFFSET                    0x0
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_DEFAULT_MASK                       _MK_MASK_CONST(0x3f)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_CFG1_0_UTMIP_BIAS_DEBOUNCE_TIMESCALE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB3_UTMIP_BIAS_STS0_0  // UTMIP Bias cell status register 0
+#define USB3_UTMIP_BIAS_STS0_0                  _MK_ADDR_CONST(0x840)
+#define USB3_UTMIP_BIAS_STS0_0_SECURE                   0x0
+#define USB3_UTMIP_BIAS_STS0_0_WORD_COUNT                       0x1
+#define USB3_UTMIP_BIAS_STS0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_STS0_0_RESET_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_BIAS_STS0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_STS0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_STS0_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB3_UTMIP_BIAS_STS0_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// Thermal encoding output from USB bias pad. 
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SHIFT                        _MK_SHIFT_CONST(0)
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_FIELD                        (_MK_MASK_CONST(0xffff) << USB3_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SHIFT)
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_RANGE                        15:0
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_WOFFSET                      0x0
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_RCTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Thermal encoding output from USB bias pad. 
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SHIFT                        _MK_SHIFT_CONST(16)
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_FIELD                        (_MK_MASK_CONST(0xffff) << USB3_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SHIFT)
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_RANGE                        31:16
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_WOFFSET                      0x0
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB3_UTMIP_BIAS_STS0_0_UTMIP_TCTRL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_0_OUT_0  
+#define USB2_QH_USB2D_QH_EP_0_OUT_0                     _MK_ADDR_CONST(0x1000)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 0 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 0.
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_0_IN_0  
+#define USB2_QH_USB2D_QH_EP_0_IN_0                      _MK_ADDR_CONST(0x1040)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_0_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_0_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 0. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 0.
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_0_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_1_OUT_0  
+#define USB2_QH_USB2D_QH_EP_1_OUT_0                     _MK_ADDR_CONST(0x1080)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 1 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 1.
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_1_IN_0  
+#define USB2_QH_USB2D_QH_EP_1_IN_0                      _MK_ADDR_CONST(0x10c0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_1_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_1_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 1. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 1.
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_1_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_2_OUT_0  
+#define USB2_QH_USB2D_QH_EP_2_OUT_0                     _MK_ADDR_CONST(0x1100)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 2 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 2.
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_2_IN_0  
+#define USB2_QH_USB2D_QH_EP_2_IN_0                      _MK_ADDR_CONST(0x1140)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_2_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_2_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 2. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 2.
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_2_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_3_OUT_0  
+#define USB2_QH_USB2D_QH_EP_3_OUT_0                     _MK_ADDR_CONST(0x1180)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 3 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 3.
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_3_IN_0  
+#define USB2_QH_USB2D_QH_EP_3_IN_0                      _MK_ADDR_CONST(0x11c0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_3_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_3_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 3. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 3.
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_3_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_4_OUT_0  
+#define USB2_QH_USB2D_QH_EP_4_OUT_0                     _MK_ADDR_CONST(0x1200)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 4 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 4.
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_4_IN_0  
+#define USB2_QH_USB2D_QH_EP_4_IN_0                      _MK_ADDR_CONST(0x1240)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_4_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_4_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 4. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 4.
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_4_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_5_OUT_0  
+#define USB2_QH_USB2D_QH_EP_5_OUT_0                     _MK_ADDR_CONST(0x1280)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 5 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 5.
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_5_IN_0  
+#define USB2_QH_USB2D_QH_EP_5_IN_0                      _MK_ADDR_CONST(0x12c0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_5_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_5_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 5. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 5.
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_5_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_6_OUT_0  
+#define USB2_QH_USB2D_QH_EP_6_OUT_0                     _MK_ADDR_CONST(0x1300)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 6 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 6.
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_6_IN_0  
+#define USB2_QH_USB2D_QH_EP_6_IN_0                      _MK_ADDR_CONST(0x1340)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_6_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_6_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 6. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 6.
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_6_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_7_OUT_0  
+#define USB2_QH_USB2D_QH_EP_7_OUT_0                     _MK_ADDR_CONST(0x1380)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 7 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 7.
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_7_IN_0  
+#define USB2_QH_USB2D_QH_EP_7_IN_0                      _MK_ADDR_CONST(0x13c0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_7_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_7_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 7. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 7.
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_7_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_8_OUT_0  
+#define USB2_QH_USB2D_QH_EP_8_OUT_0                     _MK_ADDR_CONST(0x1400)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 8 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 8.
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_8_IN_0  
+#define USB2_QH_USB2D_QH_EP_8_IN_0                      _MK_ADDR_CONST(0x1440)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_8_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_8_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 8. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 8.
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_8_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_9_OUT_0  
+#define USB2_QH_USB2D_QH_EP_9_OUT_0                     _MK_ADDR_CONST(0x1480)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 9 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 9.
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_OUT_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_9_IN_0  
+#define USB2_QH_USB2D_QH_EP_9_IN_0                      _MK_ADDR_CONST(0x14c0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_SECURE                       0x0
+#define USB2_QH_USB2D_QH_EP_9_IN_0_WORD_COUNT                   0x1
+#define USB2_QH_USB2D_QH_EP_9_IN_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_RESET_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 9. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 9.
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_RANGE                       31:0
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_WOFFSET                     0x0
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_DEFAULT_MASK                        _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_9_IN_0_USB2D_QH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_10_OUT_0  
+#define USB2_QH_USB2D_QH_EP_10_OUT_0                    _MK_ADDR_CONST(0x1500)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 10 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 10.
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_10_IN_0  
+#define USB2_QH_USB2D_QH_EP_10_IN_0                     _MK_ADDR_CONST(0x1540)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_10_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_10_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 10. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 10.
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_10_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_11_OUT_0  
+#define USB2_QH_USB2D_QH_EP_11_OUT_0                    _MK_ADDR_CONST(0x1580)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 11 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 11.
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_11_IN_0  
+#define USB2_QH_USB2D_QH_EP_11_IN_0                     _MK_ADDR_CONST(0x15c0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_11_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_11_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 11. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 11.
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_11_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_12_OUT_0  
+#define USB2_QH_USB2D_QH_EP_12_OUT_0                    _MK_ADDR_CONST(0x1600)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 12 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 12.
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_12_IN_0  
+#define USB2_QH_USB2D_QH_EP_12_IN_0                     _MK_ADDR_CONST(0x1640)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_12_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_12_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 12. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 12.
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_12_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_13_OUT_0  
+#define USB2_QH_USB2D_QH_EP_13_OUT_0                    _MK_ADDR_CONST(0x1680)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 13 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 13.
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_13_IN_0  
+#define USB2_QH_USB2D_QH_EP_13_IN_0                     _MK_ADDR_CONST(0x16c0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_13_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_13_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 13. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 13.
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_13_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_14_OUT_0  
+#define USB2_QH_USB2D_QH_EP_14_OUT_0                    _MK_ADDR_CONST(0x1700)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 14 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 14.
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_14_IN_0  
+#define USB2_QH_USB2D_QH_EP_14_IN_0                     _MK_ADDR_CONST(0x1740)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_14_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_14_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 14. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 14.
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_14_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_15_OUT_0  
+#define USB2_QH_USB2D_QH_EP_15_OUT_0                    _MK_ADDR_CONST(0x1780)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_SECURE                     0x0
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_WORD_COUNT                         0x1
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_RESET_MASK                         _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Queue Head for OUT endpoint 15 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for OUT endpoint 15.
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_RANGE                     31:0
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_WOFFSET                   0x0
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_OUT_0_USB2D_QH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register USB2_QH_USB2D_QH_EP_15_IN_0  
+#define USB2_QH_USB2D_QH_EP_15_IN_0                     _MK_ADDR_CONST(0x17c0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_SECURE                      0x0
+#define USB2_QH_USB2D_QH_EP_15_IN_0_WORD_COUNT                  0x1
+#define USB2_QH_USB2D_QH_EP_15_IN_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_RESET_MASK                  _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// Queue Head for IN endpoint 15. 
+// This is used to store a local Queue Head data structure for either device mode or host mode.
+// In device mode, it holds the Queue Head for IN endpoint 15.
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SHIFT                      _MK_SHIFT_CONST(0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_FIELD                      (_MK_MASK_CONST(0xffffffff) << USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SHIFT)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_RANGE                      31:0
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_WOFFSET                    0x0
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_DEFAULT_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define USB2_QH_USB2D_QH_EP_15_IN_0_USB2D_QH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_RX_MEM_USB2_RX_MEM_0  
+#define USB2_RX_MEM_USB2_RX_MEM_0                       _MK_ADDR_CONST(0x1800)
+#define USB2_RX_MEM_USB2_RX_MEM_0_SECURE                        0x0
+#define USB2_RX_MEM_USB2_RX_MEM_0_WORD_COUNT                    0x1
+#define USB2_RX_MEM_USB2_RX_MEM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB2_RX_MEM_USB2_RX_MEM_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// RX buffer memory
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SHIFT)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_RANGE                     31:0
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_WOFFSET                   0x0
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_0_USB2_RX_MEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_RX_MEM_USB2_RX_MEM  
+#define USB2_RX_MEM_USB2_RX_MEM                 _MK_ADDR_CONST(0x1800)
+#define USB2_RX_MEM_USB2_RX_MEM_SECURE                  0x0
+#define USB2_RX_MEM_USB2_RX_MEM_WORD_COUNT                      0x1
+#define USB2_RX_MEM_USB2_RX_MEM_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_RX_MEM_USB2_RX_MEM_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// RX buffer memory
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SHIFT)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_RANGE                       31:0
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_WOFFSET                     0x0
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_RX_MEM_USB2_RX_MEM_USB2_RX_MEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_TX_MEM_USB2_TX_MEM_0  
+#define USB2_TX_MEM_USB2_TX_MEM_0                       _MK_ADDR_CONST(0x2000)
+#define USB2_TX_MEM_USB2_TX_MEM_0_SECURE                        0x0
+#define USB2_TX_MEM_USB2_TX_MEM_0_WORD_COUNT                    0x1
+#define USB2_TX_MEM_USB2_TX_MEM_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define USB2_TX_MEM_USB2_TX_MEM_0_WRITE_MASK                    _MK_MASK_CONST(0xffffffff)
+// TX buffer memory
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SHIFT                     _MK_SHIFT_CONST(0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_FIELD                     (_MK_MASK_CONST(0xffffffff) << USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SHIFT)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_RANGE                     31:0
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_WOFFSET                   0x0
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_0_USB2_TX_MEM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Ram USB2_TX_MEM_USB2_TX_MEM  
+#define USB2_TX_MEM_USB2_TX_MEM                 _MK_ADDR_CONST(0x2000)
+#define USB2_TX_MEM_USB2_TX_MEM_SECURE                  0x0
+#define USB2_TX_MEM_USB2_TX_MEM_WORD_COUNT                      0x1
+#define USB2_TX_MEM_USB2_TX_MEM_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define USB2_TX_MEM_USB2_TX_MEM_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// TX buffer memory
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SHIFT                       _MK_SHIFT_CONST(0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_FIELD                       (_MK_MASK_CONST(0xffffffff) << USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SHIFT)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_RANGE                       31:0
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_WOFFSET                     0x0
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_DEFAULT                     _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define USB2_TX_MEM_USB2_TX_MEM_USB2_TX_MEM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARUSB_REGS(_op_) \
+_op_(USB2_CONTROLLER_USB2D_ID_0) \
+_op_(USB2_CONTROLLER_USB2D_HW_GENERAL_0) \
+_op_(USB2_CONTROLLER_USB2D_HW_HOST_0) \
+_op_(USB2_CONTROLLER_USB2D_HW_DEVICE_0) \
+_op_(USB2_CONTROLLER_USB2D_HW_TXBUF_0) \
+_op_(USB2_CONTROLLER_USB2D_HW_RXBUF_0) \
+_op_(USB2_CONTROLLER_USB2D_CAPLENGTH_0) \
+_op_(USB2_CONTROLLER_USB2D_HCIVERSON_0) \
+_op_(USB2_CONTROLLER_USB2D_HCSPARAMS_0) \
+_op_(USB2_CONTROLLER_USB2D_HCCPARAMS_0) \
+_op_(USB2_CONTROLLER_USB2D_DCIVERSION_0) \
+_op_(USB2_CONTROLLER_USB2D_DCCPARAMS_0) \
+_op_(USB2_CONTROLLER_USB2D_USBCMD_0) \
+_op_(USB2_CONTROLLER_USB2D_USBSTS_0) \
+_op_(USB2_CONTROLLER_USB2D_USBINTR_0) \
+_op_(USB2_CONTROLLER_USB2D_FRINDEX_0) \
+_op_(USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0) \
+_op_(USB2_CONTROLLER_USB2D_ASYNCLISTADDR_0) \
+_op_(USB2_CONTROLLER_USB2D_ASYNCTTSTS_0) \
+_op_(USB2_CONTROLLER_USB2D_BURSTSIZE_0) \
+_op_(USB2_CONTROLLER_USB2D_TXFILLTUNING_0) \
+_op_(USB2_CONTROLLER_USB2D_PORTSC1_0) \
+_op_(USB2_CONTROLLER_USB2D_OTGSC_0) \
+_op_(USB2_CONTROLLER_USB2D_USBMODE_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTSETUPSTAT_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTPRIME_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTFLUSH_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTSTATUS_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCOMPLETE_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL0_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL1_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL2_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL3_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL4_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL5_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL6_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL7_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL8_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL9_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL10_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL11_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL12_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL13_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL14_0) \
+_op_(USB2_CONTROLLER_USB2D_ENDPTCTRL15_0) \
+_op_(USB1_IF_USB_SUSP_CTRL_0) \
+_op_(USB1_IF_USB_PHY_VBUS_SENSORS_0) \
+_op_(USB1_IF_USB_PHY_VBUS_WAKEUP_ID_0) \
+_op_(USB1_IF_USB_PHY_ALT_VBUS_STS_0) \
+_op_(USB1_IF_USB1_LEGACY_CTRL_0) \
+_op_(USB1_IF_USB_INTER_PKT_DELAY_CTRL_0) \
+_op_(USB1_IF_USB_DEBUG_0) \
+_op_(USB1_IF_USB_PHY_SELF_TEST_0) \
+_op_(USB1_IF_USB_PHY_SELF_TEST2_0) \
+_op_(USB1_IF_USB_PHY_SELF_TEST_DEBUG_0) \
+_op_(USB1_UTMIP_PLL_CFG0_0) \
+_op_(USB1_UTMIP_PLL_CFG1_0) \
+_op_(USB1_UTMIP_XCVR_CFG0_0) \
+_op_(USB1_UTMIP_BIAS_CFG0_0) \
+_op_(USB1_UTMIP_HSRX_CFG0_0) \
+_op_(USB1_UTMIP_HSRX_CFG1_0) \
+_op_(USB1_UTMIP_FSLSRX_CFG0_0) \
+_op_(USB1_UTMIP_FSLSRX_CFG1_0) \
+_op_(USB1_UTMIP_TX_CFG0_0) \
+_op_(USB1_UTMIP_MISC_CFG0_0) \
+_op_(USB1_UTMIP_MISC_CFG1_0) \
+_op_(USB1_UTMIP_DEBOUNCE_CFG0_0) \
+_op_(USB1_UTMIP_BAT_CHRG_CFG0_0) \
+_op_(USB1_UTMIP_SPARE_CFG0_0) \
+_op_(USB1_UTMIP_XCVR_CFG1_0) \
+_op_(USB1_UTMIP_BIAS_CFG1_0) \
+_op_(USB1_UTMIP_BIAS_STS0_0) \
+_op_(USB2_QH_USB2D_QH_EP_0_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_0_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_1_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_1_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_2_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_2_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_3_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_3_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_4_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_4_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_5_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_5_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_6_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_6_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_7_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_7_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_8_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_8_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_9_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_9_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_10_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_10_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_11_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_11_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_12_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_12_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_13_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_13_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_14_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_14_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_15_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_15_IN_0) \
+_op_(USB2_RX_MEM_USB2_RX_MEM_0) \
+_op_(USB2_RX_MEM_USB2_RX_MEM) \
+_op_(USB2_TX_MEM_USB2_TX_MEM_0) \
+_op_(USB2_TX_MEM_USB2_TX_MEM) \
+_op_(USB2_CONTROLLER_1_USB2D_ID_0) \
+_op_(USB2_CONTROLLER_1_USB2D_HW_GENERAL_0) \
+_op_(USB2_CONTROLLER_1_USB2D_HW_HOST_0) \
+_op_(USB2_CONTROLLER_1_USB2D_HW_DEVICE_0) \
+_op_(USB2_CONTROLLER_1_USB2D_HW_TXBUF_0) \
+_op_(USB2_CONTROLLER_1_USB2D_HW_RXBUF_0) \
+_op_(USB2_CONTROLLER_1_USB2D_CAPLENGTH_0) \
+_op_(USB2_CONTROLLER_1_USB2D_HCIVERSON_0) \
+_op_(USB2_CONTROLLER_1_USB2D_HCSPARAMS_0) \
+_op_(USB2_CONTROLLER_1_USB2D_HCCPARAMS_0) \
+_op_(USB2_CONTROLLER_1_USB2D_DCIVERSION_0) \
+_op_(USB2_CONTROLLER_1_USB2D_DCCPARAMS_0) \
+_op_(USB2_CONTROLLER_1_USB2D_USBCMD_0) \
+_op_(USB2_CONTROLLER_1_USB2D_USBSTS_0) \
+_op_(USB2_CONTROLLER_1_USB2D_USBINTR_0) \
+_op_(USB2_CONTROLLER_1_USB2D_FRINDEX_0) \
+_op_(USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ASYNCLISTADDR_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ASYNCTTSTS_0) \
+_op_(USB2_CONTROLLER_1_USB2D_BURSTSIZE_0) \
+_op_(USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTNAK_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0) \
+_op_(USB2_CONTROLLER_1_USB2D_PORTSC1_0) \
+_op_(USB2_CONTROLLER_1_USB2D_OTGSC_0) \
+_op_(USB2_CONTROLLER_1_USB2D_USBMODE_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTSETUPSTAT_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTPRIME_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTFLUSH_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTSTATUS_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCOMPLETE_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL0_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL1_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL2_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL3_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL4_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL5_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL6_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL7_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL8_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL9_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL10_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL11_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL12_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL13_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL14_0) \
+_op_(USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0) \
+_op_(USB2_IF_USB_SUSP_CTRL_0) \
+_op_(USB2_IF_USB_ULPIS2S_CTRL_0) \
+_op_(USB2_IF_USB_ULPIS2S_SLV1_ID_0) \
+_op_(USB2_IF_USB_INTER_PKT_DELAY_CTRL_0) \
+_op_(USB2_IF_ULPI_TIMING_CTRL_0_0) \
+_op_(USB2_IF_ULPI_TIMING_CTRL_1_0) \
+_op_(USB2_IF_USB_DEBUG_0) \
+_op_(USB2_UHSIC_PLL_CFG0_0) \
+_op_(USB2_UHSIC_PLL_CFG1_0) \
+_op_(USB2_UHSIC_HSRX_CFG0_0) \
+_op_(USB2_UHSIC_HSRX_CFG1_0) \
+_op_(USB2_UHSIC_TX_CFG0_0) \
+_op_(USB2_UHSIC_MISC_CFG0_0) \
+_op_(USB2_UHSIC_MISC_CFG1_0) \
+_op_(USB2_UHSIC_PADS_CFG0_0) \
+_op_(USB2_UHSIC_PADS_CFG1_0) \
+_op_(USB2_UHSIC_CMD_CFG0_0) \
+_op_(USB2_UHSIC_STAT_CFG0_0) \
+_op_(USB2_UHSIC_SPARE_CFG0_0) \
+_op_(USB2_QH_USB2D_QH_EP_0_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_0_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_1_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_1_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_2_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_2_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_3_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_3_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_4_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_4_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_5_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_5_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_6_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_6_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_7_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_7_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_8_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_8_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_9_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_9_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_10_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_10_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_11_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_11_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_12_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_12_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_13_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_13_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_14_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_14_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_15_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_15_IN_0) \
+_op_(USB2_RX_MEM_USB2_RX_MEM_0) \
+_op_(USB2_RX_MEM_USB2_RX_MEM) \
+_op_(USB2_TX_MEM_USB2_TX_MEM_0) \
+_op_(USB2_TX_MEM_USB2_TX_MEM) \
+_op_(USB2_CONTROLLER_2_USB2D_ID_0) \
+_op_(USB2_CONTROLLER_2_USB2D_HW_GENERAL_0) \
+_op_(USB2_CONTROLLER_2_USB2D_HW_HOST_0) \
+_op_(USB2_CONTROLLER_2_USB2D_HW_DEVICE_0) \
+_op_(USB2_CONTROLLER_2_USB2D_HW_TXBUF_0) \
+_op_(USB2_CONTROLLER_2_USB2D_HW_RXBUF_0) \
+_op_(USB2_CONTROLLER_2_USB2D_CAPLENGTH_0) \
+_op_(USB2_CONTROLLER_2_USB2D_HCIVERSON_0) \
+_op_(USB2_CONTROLLER_2_USB2D_HCSPARAMS_0) \
+_op_(USB2_CONTROLLER_2_USB2D_HCCPARAMS_0) \
+_op_(USB2_CONTROLLER_2_USB2D_DCIVERSION_0) \
+_op_(USB2_CONTROLLER_2_USB2D_DCCPARAMS_0) \
+_op_(USB2_CONTROLLER_2_USB2D_USBCMD_0) \
+_op_(USB2_CONTROLLER_2_USB2D_USBSTS_0) \
+_op_(USB2_CONTROLLER_2_USB2D_USBINTR_0) \
+_op_(USB2_CONTROLLER_2_USB2D_FRINDEX_0) \
+_op_(USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ASYNCLISTADDR_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ASYNCTTSTS_0) \
+_op_(USB2_CONTROLLER_2_USB2D_BURSTSIZE_0) \
+_op_(USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTNAK_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0) \
+_op_(USB2_CONTROLLER_2_USB2D_PORTSC1_0) \
+_op_(USB2_CONTROLLER_2_USB2D_OTGSC_0) \
+_op_(USB2_CONTROLLER_2_USB2D_USBMODE_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTSETUPSTAT_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTPRIME_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTFLUSH_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTSTATUS_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCOMPLETE_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL0_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL1_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL2_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL3_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL4_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL5_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL6_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL7_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL8_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL9_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL10_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL11_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL12_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL13_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL14_0) \
+_op_(USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0) \
+_op_(USB3_IF_USB_SUSP_CTRL_0) \
+_op_(USB3_IF_USB_PHY_VBUS_SENSORS_0) \
+_op_(USB3_IF_USB_PHY_VBUS_WAKEUP_ID_0) \
+_op_(USB3_IF_USB_PHY_ALT_VBUS_STS_0) \
+_op_(USB3_IF_ICUSB_XCVR_CFG_0) \
+_op_(USB3_IF_USB_INTER_PKT_DELAY_CTRL_0) \
+_op_(USB3_IF_USB_DEBUG_0) \
+_op_(USB3_IF_USB_PHY_SELF_TEST_0) \
+_op_(USB3_IF_USB_PHY_SELF_TEST2_0) \
+_op_(USB3_IF_USB_PHY_SELF_TEST_DEBUG_0) \
+_op_(USB3_UTMIP_PLL_CFG0_0) \
+_op_(USB3_UTMIP_PLL_CFG1_0) \
+_op_(USB3_UTMIP_XCVR_CFG0_0) \
+_op_(USB3_UTMIP_BIAS_CFG0_0) \
+_op_(USB3_UTMIP_HSRX_CFG0_0) \
+_op_(USB3_UTMIP_HSRX_CFG1_0) \
+_op_(USB3_UTMIP_FSLSRX_CFG0_0) \
+_op_(USB3_UTMIP_FSLSRX_CFG1_0) \
+_op_(USB3_UTMIP_TX_CFG0_0) \
+_op_(USB3_UTMIP_MISC_CFG0_0) \
+_op_(USB3_UTMIP_MISC_CFG1_0) \
+_op_(USB3_UTMIP_DEBOUNCE_CFG0_0) \
+_op_(USB3_UTMIP_BAT_CHRG_CFG0_0) \
+_op_(USB3_UTMIP_SPARE_CFG0_0) \
+_op_(USB3_UTMIP_XCVR_CFG1_0) \
+_op_(USB3_UTMIP_BIAS_CFG1_0) \
+_op_(USB3_UTMIP_BIAS_STS0_0) \
+_op_(USB2_QH_USB2D_QH_EP_0_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_0_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_1_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_1_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_2_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_2_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_3_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_3_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_4_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_4_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_5_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_5_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_6_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_6_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_7_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_7_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_8_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_8_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_9_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_9_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_10_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_10_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_11_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_11_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_12_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_12_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_13_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_13_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_14_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_14_IN_0) \
+_op_(USB2_QH_USB2D_QH_EP_15_OUT_0) \
+_op_(USB2_QH_USB2D_QH_EP_15_IN_0) \
+_op_(USB2_RX_MEM_USB2_RX_MEM_0) \
+_op_(USB2_RX_MEM_USB2_RX_MEM) \
+_op_(USB2_TX_MEM_USB2_TX_MEM_0) \
+_op_(USB2_TX_MEM_USB2_TX_MEM)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_USB2_CONTROLLER    0x00000000
+#define BASE_ADDRESS_USB1_IF    0x00000400
+#define BASE_ADDRESS_USB1_UTMIP 0x00000800
+#define BASE_ADDRESS_USB2_QH    0x00001000
+#define BASE_ADDRESS_USB2_RX_MEM        0x00001800
+#define BASE_ADDRESS_USB2_TX_MEM        0x00002000
+#define BASE_ADDRESS_USB2_CONTROLLER_1  0x00000000
+#define BASE_ADDRESS_USB2_IF    0x00000400
+#define BASE_ADDRESS_USB2_UHSIC 0x00000800
+#define BASE_ADDRESS_USB2_QH    0x00001000
+#define BASE_ADDRESS_USB2_RX_MEM        0x00001800
+#define BASE_ADDRESS_USB2_TX_MEM        0x00002000
+#define BASE_ADDRESS_USB2_CONTROLLER_2  0x00000000
+#define BASE_ADDRESS_USB3_IF    0x00000400
+#define BASE_ADDRESS_USB3_UTMIP 0x00000800
+#define BASE_ADDRESS_USB2_QH    0x00001000
+#define BASE_ADDRESS_USB2_RX_MEM        0x00001800
+#define BASE_ADDRESS_USB2_TX_MEM        0x00002000
+
+//
+// ARUSB REGISTER BANKS
+//
+
+#define USB2_CONTROLLER0_FIRST_REG 0x0000 // USB2_CONTROLLER_USB2D_ID_0
+#define USB2_CONTROLLER0_LAST_REG 0x0014 // USB2_CONTROLLER_USB2D_HW_RXBUF_0
+#define USB2_CONTROLLER1_FIRST_REG 0x0100 // USB2_CONTROLLER_USB2D_CAPLENGTH_0
+#define USB2_CONTROLLER1_LAST_REG 0x0108 // USB2_CONTROLLER_USB2D_HCCPARAMS_0
+#define USB2_CONTROLLER2_FIRST_REG 0x0120 // USB2_CONTROLLER_USB2D_DCIVERSION_0
+#define USB2_CONTROLLER2_LAST_REG 0x0124 // USB2_CONTROLLER_USB2D_DCCPARAMS_0
+#define USB2_CONTROLLER3_FIRST_REG 0x0140 // USB2_CONTROLLER_USB2D_USBCMD_0
+#define USB2_CONTROLLER3_LAST_REG 0x014c // USB2_CONTROLLER_USB2D_FRINDEX_0
+#define USB2_CONTROLLER4_FIRST_REG 0x0154 // USB2_CONTROLLER_USB2D_PERIODICLISTBASE_0
+#define USB2_CONTROLLER4_LAST_REG 0x0164 // USB2_CONTROLLER_USB2D_TXFILLTUNING_0
+#define USB2_CONTROLLER5_FIRST_REG 0x0184 // USB2_CONTROLLER_USB2D_PORTSC1_0
+#define USB2_CONTROLLER5_LAST_REG 0x0184 // USB2_CONTROLLER_USB2D_PORTSC1_0
+#define USB2_CONTROLLER6_FIRST_REG 0x01a4 // USB2_CONTROLLER_USB2D_OTGSC_0
+#define USB2_CONTROLLER6_LAST_REG 0x01fc // USB2_CONTROLLER_USB2D_ENDPTCTRL15_0
+#define USB1_IF0_FIRST_REG 0x0400 // USB1_IF_USB_SUSP_CTRL_0
+#define USB1_IF0_LAST_REG 0x0410 // USB1_IF_USB1_LEGACY_CTRL_0
+#define USB1_IF1_FIRST_REG 0x0420 // USB1_IF_USB_INTER_PKT_DELAY_CTRL_0
+#define USB1_IF1_LAST_REG 0x0420 // USB1_IF_USB_INTER_PKT_DELAY_CTRL_0
+#define USB1_IF2_FIRST_REG 0x0480 // USB1_IF_USB_DEBUG_0
+#define USB1_IF2_LAST_REG 0x048c // USB1_IF_USB_PHY_SELF_TEST_DEBUG_0
+#define USB1_UTMIP0_FIRST_REG 0x0800 // USB1_UTMIP_PLL_CFG0_0
+#define USB1_UTMIP0_LAST_REG 0x0840 // USB1_UTMIP_BIAS_STS0_0
+#define USB2_QH0_FIRST_REG 0x1000 // USB2_QH_USB2D_QH_EP_0_OUT_0
+#define USB2_QH0_LAST_REG 0x1000 // USB2_QH_USB2D_QH_EP_0_OUT_0
+#define USB2_QH1_FIRST_REG 0x1040 // USB2_QH_USB2D_QH_EP_0_IN_0
+#define USB2_QH1_LAST_REG 0x1040 // USB2_QH_USB2D_QH_EP_0_IN_0
+#define USB2_QH2_FIRST_REG 0x1080 // USB2_QH_USB2D_QH_EP_1_OUT_0
+#define USB2_QH2_LAST_REG 0x1080 // USB2_QH_USB2D_QH_EP_1_OUT_0
+#define USB2_QH3_FIRST_REG 0x10c0 // USB2_QH_USB2D_QH_EP_1_IN_0
+#define USB2_QH3_LAST_REG 0x10c0 // USB2_QH_USB2D_QH_EP_1_IN_0
+#define USB2_QH4_FIRST_REG 0x1100 // USB2_QH_USB2D_QH_EP_2_OUT_0
+#define USB2_QH4_LAST_REG 0x1100 // USB2_QH_USB2D_QH_EP_2_OUT_0
+#define USB2_QH5_FIRST_REG 0x1140 // USB2_QH_USB2D_QH_EP_2_IN_0
+#define USB2_QH5_LAST_REG 0x1140 // USB2_QH_USB2D_QH_EP_2_IN_0
+#define USB2_QH6_FIRST_REG 0x1180 // USB2_QH_USB2D_QH_EP_3_OUT_0
+#define USB2_QH6_LAST_REG 0x1180 // USB2_QH_USB2D_QH_EP_3_OUT_0
+#define USB2_QH7_FIRST_REG 0x11c0 // USB2_QH_USB2D_QH_EP_3_IN_0
+#define USB2_QH7_LAST_REG 0x11c0 // USB2_QH_USB2D_QH_EP_3_IN_0
+#define USB2_QH8_FIRST_REG 0x1200 // USB2_QH_USB2D_QH_EP_4_OUT_0
+#define USB2_QH8_LAST_REG 0x1200 // USB2_QH_USB2D_QH_EP_4_OUT_0
+#define USB2_QH9_FIRST_REG 0x1240 // USB2_QH_USB2D_QH_EP_4_IN_0
+#define USB2_QH9_LAST_REG 0x1240 // USB2_QH_USB2D_QH_EP_4_IN_0
+#define USB2_QH10_FIRST_REG 0x1280 // USB2_QH_USB2D_QH_EP_5_OUT_0
+#define USB2_QH10_LAST_REG 0x1280 // USB2_QH_USB2D_QH_EP_5_OUT_0
+#define USB2_QH11_FIRST_REG 0x12c0 // USB2_QH_USB2D_QH_EP_5_IN_0
+#define USB2_QH11_LAST_REG 0x12c0 // USB2_QH_USB2D_QH_EP_5_IN_0
+#define USB2_QH12_FIRST_REG 0x1300 // USB2_QH_USB2D_QH_EP_6_OUT_0
+#define USB2_QH12_LAST_REG 0x1300 // USB2_QH_USB2D_QH_EP_6_OUT_0
+#define USB2_QH13_FIRST_REG 0x1340 // USB2_QH_USB2D_QH_EP_6_IN_0
+#define USB2_QH13_LAST_REG 0x1340 // USB2_QH_USB2D_QH_EP_6_IN_0
+#define USB2_QH14_FIRST_REG 0x1380 // USB2_QH_USB2D_QH_EP_7_OUT_0
+#define USB2_QH14_LAST_REG 0x1380 // USB2_QH_USB2D_QH_EP_7_OUT_0
+#define USB2_QH15_FIRST_REG 0x13c0 // USB2_QH_USB2D_QH_EP_7_IN_0
+#define USB2_QH15_LAST_REG 0x13c0 // USB2_QH_USB2D_QH_EP_7_IN_0
+#define USB2_QH16_FIRST_REG 0x1400 // USB2_QH_USB2D_QH_EP_8_OUT_0
+#define USB2_QH16_LAST_REG 0x1400 // USB2_QH_USB2D_QH_EP_8_OUT_0
+#define USB2_QH17_FIRST_REG 0x1440 // USB2_QH_USB2D_QH_EP_8_IN_0
+#define USB2_QH17_LAST_REG 0x1440 // USB2_QH_USB2D_QH_EP_8_IN_0
+#define USB2_QH18_FIRST_REG 0x1480 // USB2_QH_USB2D_QH_EP_9_OUT_0
+#define USB2_QH18_LAST_REG 0x1480 // USB2_QH_USB2D_QH_EP_9_OUT_0
+#define USB2_QH19_FIRST_REG 0x14c0 // USB2_QH_USB2D_QH_EP_9_IN_0
+#define USB2_QH19_LAST_REG 0x14c0 // USB2_QH_USB2D_QH_EP_9_IN_0
+#define USB2_QH20_FIRST_REG 0x1500 // USB2_QH_USB2D_QH_EP_10_OUT_0
+#define USB2_QH20_LAST_REG 0x1500 // USB2_QH_USB2D_QH_EP_10_OUT_0
+#define USB2_QH21_FIRST_REG 0x1540 // USB2_QH_USB2D_QH_EP_10_IN_0
+#define USB2_QH21_LAST_REG 0x1540 // USB2_QH_USB2D_QH_EP_10_IN_0
+#define USB2_QH22_FIRST_REG 0x1580 // USB2_QH_USB2D_QH_EP_11_OUT_0
+#define USB2_QH22_LAST_REG 0x1580 // USB2_QH_USB2D_QH_EP_11_OUT_0
+#define USB2_QH23_FIRST_REG 0x15c0 // USB2_QH_USB2D_QH_EP_11_IN_0
+#define USB2_QH23_LAST_REG 0x15c0 // USB2_QH_USB2D_QH_EP_11_IN_0
+#define USB2_QH24_FIRST_REG 0x1600 // USB2_QH_USB2D_QH_EP_12_OUT_0
+#define USB2_QH24_LAST_REG 0x1600 // USB2_QH_USB2D_QH_EP_12_OUT_0
+#define USB2_QH25_FIRST_REG 0x1640 // USB2_QH_USB2D_QH_EP_12_IN_0
+#define USB2_QH25_LAST_REG 0x1640 // USB2_QH_USB2D_QH_EP_12_IN_0
+#define USB2_QH26_FIRST_REG 0x1680 // USB2_QH_USB2D_QH_EP_13_OUT_0
+#define USB2_QH26_LAST_REG 0x1680 // USB2_QH_USB2D_QH_EP_13_OUT_0
+#define USB2_QH27_FIRST_REG 0x16c0 // USB2_QH_USB2D_QH_EP_13_IN_0
+#define USB2_QH27_LAST_REG 0x16c0 // USB2_QH_USB2D_QH_EP_13_IN_0
+#define USB2_QH28_FIRST_REG 0x1700 // USB2_QH_USB2D_QH_EP_14_OUT_0
+#define USB2_QH28_LAST_REG 0x1700 // USB2_QH_USB2D_QH_EP_14_OUT_0
+#define USB2_QH29_FIRST_REG 0x1740 // USB2_QH_USB2D_QH_EP_14_IN_0
+#define USB2_QH29_LAST_REG 0x1740 // USB2_QH_USB2D_QH_EP_14_IN_0
+#define USB2_QH30_FIRST_REG 0x1780 // USB2_QH_USB2D_QH_EP_15_OUT_0
+#define USB2_QH30_LAST_REG 0x1780 // USB2_QH_USB2D_QH_EP_15_OUT_0
+#define USB2_QH31_FIRST_REG 0x17c0 // USB2_QH_USB2D_QH_EP_15_IN_0
+#define USB2_QH31_LAST_REG 0x17c0 // USB2_QH_USB2D_QH_EP_15_IN_0
+#define USB2_RX_MEM0_FIRST_REG 0x1800 // USB2_RX_MEM_USB2_RX_MEM_0
+#define USB2_RX_MEM0_LAST_REG 0x1800 // USB2_RX_MEM_USB2_RX_MEM_0
+#define USB2_TX_MEM0_FIRST_REG 0x2000 // USB2_TX_MEM_USB2_TX_MEM_0
+#define USB2_TX_MEM0_LAST_REG 0x2000 // USB2_TX_MEM_USB2_TX_MEM_0
+#define USB2_CONTROLLER_10_FIRST_REG 0x0000 // USB2_CONTROLLER_1_USB2D_ID_0
+#define USB2_CONTROLLER_10_LAST_REG 0x0014 // USB2_CONTROLLER_1_USB2D_HW_RXBUF_0
+#define USB2_CONTROLLER_11_FIRST_REG 0x0100 // USB2_CONTROLLER_1_USB2D_CAPLENGTH_0
+#define USB2_CONTROLLER_11_LAST_REG 0x0108 // USB2_CONTROLLER_1_USB2D_HCCPARAMS_0
+#define USB2_CONTROLLER_12_FIRST_REG 0x0120 // USB2_CONTROLLER_1_USB2D_DCIVERSION_0
+#define USB2_CONTROLLER_12_LAST_REG 0x0124 // USB2_CONTROLLER_1_USB2D_DCCPARAMS_0
+#define USB2_CONTROLLER_13_FIRST_REG 0x0140 // USB2_CONTROLLER_1_USB2D_USBCMD_0
+#define USB2_CONTROLLER_13_LAST_REG 0x014c // USB2_CONTROLLER_1_USB2D_FRINDEX_0
+#define USB2_CONTROLLER_14_FIRST_REG 0x0154 // USB2_CONTROLLER_1_USB2D_PERIODICLISTBASE_0
+#define USB2_CONTROLLER_14_LAST_REG 0x0164 // USB2_CONTROLLER_1_USB2D_TXFILLTUNING_0
+#define USB2_CONTROLLER_15_FIRST_REG 0x016c // USB2_CONTROLLER_1_USB2D_ICUSB_CTRL_0
+#define USB2_CONTROLLER_15_LAST_REG 0x0170 // USB2_CONTROLLER_1_USB2D_ULPI_VIEWPORT_0
+#define USB2_CONTROLLER_16_FIRST_REG 0x0178 // USB2_CONTROLLER_1_USB2D_ENDPTNAK_0
+#define USB2_CONTROLLER_16_LAST_REG 0x017c // USB2_CONTROLLER_1_USB2D_ENDPTNAK_ENABLE_0
+#define USB2_CONTROLLER_17_FIRST_REG 0x0184 // USB2_CONTROLLER_1_USB2D_PORTSC1_0
+#define USB2_CONTROLLER_17_LAST_REG 0x0184 // USB2_CONTROLLER_1_USB2D_PORTSC1_0
+#define USB2_CONTROLLER_18_FIRST_REG 0x01a4 // USB2_CONTROLLER_1_USB2D_OTGSC_0
+#define USB2_CONTROLLER_18_LAST_REG 0x01fc // USB2_CONTROLLER_1_USB2D_ENDPTCTRL15_0
+#define USB2_IF0_FIRST_REG 0x0400 // USB2_IF_USB_SUSP_CTRL_0
+#define USB2_IF0_LAST_REG 0x0400 // USB2_IF_USB_SUSP_CTRL_0
+#define USB2_IF1_FIRST_REG 0x0418 // USB2_IF_USB_ULPIS2S_CTRL_0
+#define USB2_IF1_LAST_REG 0x0428 // USB2_IF_ULPI_TIMING_CTRL_1_0
+#define USB2_IF2_FIRST_REG 0x0480 // USB2_IF_USB_DEBUG_0
+#define USB2_IF2_LAST_REG 0x0480 // USB2_IF_USB_DEBUG_0
+#define USB2_UHSIC0_FIRST_REG 0x0800 // USB2_UHSIC_PLL_CFG0_0
+#define USB2_UHSIC0_LAST_REG 0x082c // USB2_UHSIC_SPARE_CFG0_0
+#define USB2_QH0_FIRST_REG 0x1000 // USB2_QH_USB2D_QH_EP_0_OUT_0
+#define USB2_QH0_LAST_REG 0x1000 // USB2_QH_USB2D_QH_EP_0_OUT_0
+#define USB2_QH1_FIRST_REG 0x1040 // USB2_QH_USB2D_QH_EP_0_IN_0
+#define USB2_QH1_LAST_REG 0x1040 // USB2_QH_USB2D_QH_EP_0_IN_0
+#define USB2_QH2_FIRST_REG 0x1080 // USB2_QH_USB2D_QH_EP_1_OUT_0
+#define USB2_QH2_LAST_REG 0x1080 // USB2_QH_USB2D_QH_EP_1_OUT_0
+#define USB2_QH3_FIRST_REG 0x10c0 // USB2_QH_USB2D_QH_EP_1_IN_0
+#define USB2_QH3_LAST_REG 0x10c0 // USB2_QH_USB2D_QH_EP_1_IN_0
+#define USB2_QH4_FIRST_REG 0x1100 // USB2_QH_USB2D_QH_EP_2_OUT_0
+#define USB2_QH4_LAST_REG 0x1100 // USB2_QH_USB2D_QH_EP_2_OUT_0
+#define USB2_QH5_FIRST_REG 0x1140 // USB2_QH_USB2D_QH_EP_2_IN_0
+#define USB2_QH5_LAST_REG 0x1140 // USB2_QH_USB2D_QH_EP_2_IN_0
+#define USB2_QH6_FIRST_REG 0x1180 // USB2_QH_USB2D_QH_EP_3_OUT_0
+#define USB2_QH6_LAST_REG 0x1180 // USB2_QH_USB2D_QH_EP_3_OUT_0
+#define USB2_QH7_FIRST_REG 0x11c0 // USB2_QH_USB2D_QH_EP_3_IN_0
+#define USB2_QH7_LAST_REG 0x11c0 // USB2_QH_USB2D_QH_EP_3_IN_0
+#define USB2_QH8_FIRST_REG 0x1200 // USB2_QH_USB2D_QH_EP_4_OUT_0
+#define USB2_QH8_LAST_REG 0x1200 // USB2_QH_USB2D_QH_EP_4_OUT_0
+#define USB2_QH9_FIRST_REG 0x1240 // USB2_QH_USB2D_QH_EP_4_IN_0
+#define USB2_QH9_LAST_REG 0x1240 // USB2_QH_USB2D_QH_EP_4_IN_0
+#define USB2_QH10_FIRST_REG 0x1280 // USB2_QH_USB2D_QH_EP_5_OUT_0
+#define USB2_QH10_LAST_REG 0x1280 // USB2_QH_USB2D_QH_EP_5_OUT_0
+#define USB2_QH11_FIRST_REG 0x12c0 // USB2_QH_USB2D_QH_EP_5_IN_0
+#define USB2_QH11_LAST_REG 0x12c0 // USB2_QH_USB2D_QH_EP_5_IN_0
+#define USB2_QH12_FIRST_REG 0x1300 // USB2_QH_USB2D_QH_EP_6_OUT_0
+#define USB2_QH12_LAST_REG 0x1300 // USB2_QH_USB2D_QH_EP_6_OUT_0
+#define USB2_QH13_FIRST_REG 0x1340 // USB2_QH_USB2D_QH_EP_6_IN_0
+#define USB2_QH13_LAST_REG 0x1340 // USB2_QH_USB2D_QH_EP_6_IN_0
+#define USB2_QH14_FIRST_REG 0x1380 // USB2_QH_USB2D_QH_EP_7_OUT_0
+#define USB2_QH14_LAST_REG 0x1380 // USB2_QH_USB2D_QH_EP_7_OUT_0
+#define USB2_QH15_FIRST_REG 0x13c0 // USB2_QH_USB2D_QH_EP_7_IN_0
+#define USB2_QH15_LAST_REG 0x13c0 // USB2_QH_USB2D_QH_EP_7_IN_0
+#define USB2_QH16_FIRST_REG 0x1400 // USB2_QH_USB2D_QH_EP_8_OUT_0
+#define USB2_QH16_LAST_REG 0x1400 // USB2_QH_USB2D_QH_EP_8_OUT_0
+#define USB2_QH17_FIRST_REG 0x1440 // USB2_QH_USB2D_QH_EP_8_IN_0
+#define USB2_QH17_LAST_REG 0x1440 // USB2_QH_USB2D_QH_EP_8_IN_0
+#define USB2_QH18_FIRST_REG 0x1480 // USB2_QH_USB2D_QH_EP_9_OUT_0
+#define USB2_QH18_LAST_REG 0x1480 // USB2_QH_USB2D_QH_EP_9_OUT_0
+#define USB2_QH19_FIRST_REG 0x14c0 // USB2_QH_USB2D_QH_EP_9_IN_0
+#define USB2_QH19_LAST_REG 0x14c0 // USB2_QH_USB2D_QH_EP_9_IN_0
+#define USB2_QH20_FIRST_REG 0x1500 // USB2_QH_USB2D_QH_EP_10_OUT_0
+#define USB2_QH20_LAST_REG 0x1500 // USB2_QH_USB2D_QH_EP_10_OUT_0
+#define USB2_QH21_FIRST_REG 0x1540 // USB2_QH_USB2D_QH_EP_10_IN_0
+#define USB2_QH21_LAST_REG 0x1540 // USB2_QH_USB2D_QH_EP_10_IN_0
+#define USB2_QH22_FIRST_REG 0x1580 // USB2_QH_USB2D_QH_EP_11_OUT_0
+#define USB2_QH22_LAST_REG 0x1580 // USB2_QH_USB2D_QH_EP_11_OUT_0
+#define USB2_QH23_FIRST_REG 0x15c0 // USB2_QH_USB2D_QH_EP_11_IN_0
+#define USB2_QH23_LAST_REG 0x15c0 // USB2_QH_USB2D_QH_EP_11_IN_0
+#define USB2_QH24_FIRST_REG 0x1600 // USB2_QH_USB2D_QH_EP_12_OUT_0
+#define USB2_QH24_LAST_REG 0x1600 // USB2_QH_USB2D_QH_EP_12_OUT_0
+#define USB2_QH25_FIRST_REG 0x1640 // USB2_QH_USB2D_QH_EP_12_IN_0
+#define USB2_QH25_LAST_REG 0x1640 // USB2_QH_USB2D_QH_EP_12_IN_0
+#define USB2_QH26_FIRST_REG 0x1680 // USB2_QH_USB2D_QH_EP_13_OUT_0
+#define USB2_QH26_LAST_REG 0x1680 // USB2_QH_USB2D_QH_EP_13_OUT_0
+#define USB2_QH27_FIRST_REG 0x16c0 // USB2_QH_USB2D_QH_EP_13_IN_0
+#define USB2_QH27_LAST_REG 0x16c0 // USB2_QH_USB2D_QH_EP_13_IN_0
+#define USB2_QH28_FIRST_REG 0x1700 // USB2_QH_USB2D_QH_EP_14_OUT_0
+#define USB2_QH28_LAST_REG 0x1700 // USB2_QH_USB2D_QH_EP_14_OUT_0
+#define USB2_QH29_FIRST_REG 0x1740 // USB2_QH_USB2D_QH_EP_14_IN_0
+#define USB2_QH29_LAST_REG 0x1740 // USB2_QH_USB2D_QH_EP_14_IN_0
+#define USB2_QH30_FIRST_REG 0x1780 // USB2_QH_USB2D_QH_EP_15_OUT_0
+#define USB2_QH30_LAST_REG 0x1780 // USB2_QH_USB2D_QH_EP_15_OUT_0
+#define USB2_QH31_FIRST_REG 0x17c0 // USB2_QH_USB2D_QH_EP_15_IN_0
+#define USB2_QH31_LAST_REG 0x17c0 // USB2_QH_USB2D_QH_EP_15_IN_0
+#define USB2_RX_MEM0_FIRST_REG 0x1800 // USB2_RX_MEM_USB2_RX_MEM_0
+#define USB2_RX_MEM0_LAST_REG 0x1800 // USB2_RX_MEM_USB2_RX_MEM_0
+#define USB2_TX_MEM0_FIRST_REG 0x2000 // USB2_TX_MEM_USB2_TX_MEM_0
+#define USB2_TX_MEM0_LAST_REG 0x2000 // USB2_TX_MEM_USB2_TX_MEM_0
+#define USB2_CONTROLLER_20_FIRST_REG 0x0000 // USB2_CONTROLLER_2_USB2D_ID_0
+#define USB2_CONTROLLER_20_LAST_REG 0x0014 // USB2_CONTROLLER_2_USB2D_HW_RXBUF_0
+#define USB2_CONTROLLER_21_FIRST_REG 0x0100 // USB2_CONTROLLER_2_USB2D_CAPLENGTH_0
+#define USB2_CONTROLLER_21_LAST_REG 0x0108 // USB2_CONTROLLER_2_USB2D_HCCPARAMS_0
+#define USB2_CONTROLLER_22_FIRST_REG 0x0120 // USB2_CONTROLLER_2_USB2D_DCIVERSION_0
+#define USB2_CONTROLLER_22_LAST_REG 0x0124 // USB2_CONTROLLER_2_USB2D_DCCPARAMS_0
+#define USB2_CONTROLLER_23_FIRST_REG 0x0140 // USB2_CONTROLLER_2_USB2D_USBCMD_0
+#define USB2_CONTROLLER_23_LAST_REG 0x014c // USB2_CONTROLLER_2_USB2D_FRINDEX_0
+#define USB2_CONTROLLER_24_FIRST_REG 0x0154 // USB2_CONTROLLER_2_USB2D_PERIODICLISTBASE_0
+#define USB2_CONTROLLER_24_LAST_REG 0x0164 // USB2_CONTROLLER_2_USB2D_TXFILLTUNING_0
+#define USB2_CONTROLLER_25_FIRST_REG 0x016c // USB2_CONTROLLER_2_USB2D_ICUSB_CTRL_0
+#define USB2_CONTROLLER_25_LAST_REG 0x0170 // USB2_CONTROLLER_2_USB2D_ULPI_VIEWPORT_0
+#define USB2_CONTROLLER_26_FIRST_REG 0x0178 // USB2_CONTROLLER_2_USB2D_ENDPTNAK_0
+#define USB2_CONTROLLER_26_LAST_REG 0x017c // USB2_CONTROLLER_2_USB2D_ENDPTNAK_ENABLE_0
+#define USB2_CONTROLLER_27_FIRST_REG 0x0184 // USB2_CONTROLLER_2_USB2D_PORTSC1_0
+#define USB2_CONTROLLER_27_LAST_REG 0x0184 // USB2_CONTROLLER_2_USB2D_PORTSC1_0
+#define USB2_CONTROLLER_28_FIRST_REG 0x01a4 // USB2_CONTROLLER_2_USB2D_OTGSC_0
+#define USB2_CONTROLLER_28_LAST_REG 0x01fc // USB2_CONTROLLER_2_USB2D_ENDPTCTRL15_0
+#define USB3_IF0_FIRST_REG 0x0400 // USB3_IF_USB_SUSP_CTRL_0
+#define USB3_IF0_LAST_REG 0x040c // USB3_IF_USB_PHY_ALT_VBUS_STS_0
+#define USB3_IF1_FIRST_REG 0x0414 // USB3_IF_ICUSB_XCVR_CFG_0
+#define USB3_IF1_LAST_REG 0x0414 // USB3_IF_ICUSB_XCVR_CFG_0
+#define USB3_IF2_FIRST_REG 0x0420 // USB3_IF_USB_INTER_PKT_DELAY_CTRL_0
+#define USB3_IF2_LAST_REG 0x0420 // USB3_IF_USB_INTER_PKT_DELAY_CTRL_0
+#define USB3_IF3_FIRST_REG 0x0480 // USB3_IF_USB_DEBUG_0
+#define USB3_IF3_LAST_REG 0x048c // USB3_IF_USB_PHY_SELF_TEST_DEBUG_0
+#define USB3_UTMIP0_FIRST_REG 0x0800 // USB3_UTMIP_PLL_CFG0_0
+#define USB3_UTMIP0_LAST_REG 0x0840 // USB3_UTMIP_BIAS_STS0_0
+#define USB2_QH0_FIRST_REG 0x1000 // USB2_QH_USB2D_QH_EP_0_OUT_0
+#define USB2_QH0_LAST_REG 0x1000 // USB2_QH_USB2D_QH_EP_0_OUT_0
+#define USB2_QH1_FIRST_REG 0x1040 // USB2_QH_USB2D_QH_EP_0_IN_0
+#define USB2_QH1_LAST_REG 0x1040 // USB2_QH_USB2D_QH_EP_0_IN_0
+#define USB2_QH2_FIRST_REG 0x1080 // USB2_QH_USB2D_QH_EP_1_OUT_0
+#define USB2_QH2_LAST_REG 0x1080 // USB2_QH_USB2D_QH_EP_1_OUT_0
+#define USB2_QH3_FIRST_REG 0x10c0 // USB2_QH_USB2D_QH_EP_1_IN_0
+#define USB2_QH3_LAST_REG 0x10c0 // USB2_QH_USB2D_QH_EP_1_IN_0
+#define USB2_QH4_FIRST_REG 0x1100 // USB2_QH_USB2D_QH_EP_2_OUT_0
+#define USB2_QH4_LAST_REG 0x1100 // USB2_QH_USB2D_QH_EP_2_OUT_0
+#define USB2_QH5_FIRST_REG 0x1140 // USB2_QH_USB2D_QH_EP_2_IN_0
+#define USB2_QH5_LAST_REG 0x1140 // USB2_QH_USB2D_QH_EP_2_IN_0
+#define USB2_QH6_FIRST_REG 0x1180 // USB2_QH_USB2D_QH_EP_3_OUT_0
+#define USB2_QH6_LAST_REG 0x1180 // USB2_QH_USB2D_QH_EP_3_OUT_0
+#define USB2_QH7_FIRST_REG 0x11c0 // USB2_QH_USB2D_QH_EP_3_IN_0
+#define USB2_QH7_LAST_REG 0x11c0 // USB2_QH_USB2D_QH_EP_3_IN_0
+#define USB2_QH8_FIRST_REG 0x1200 // USB2_QH_USB2D_QH_EP_4_OUT_0
+#define USB2_QH8_LAST_REG 0x1200 // USB2_QH_USB2D_QH_EP_4_OUT_0
+#define USB2_QH9_FIRST_REG 0x1240 // USB2_QH_USB2D_QH_EP_4_IN_0
+#define USB2_QH9_LAST_REG 0x1240 // USB2_QH_USB2D_QH_EP_4_IN_0
+#define USB2_QH10_FIRST_REG 0x1280 // USB2_QH_USB2D_QH_EP_5_OUT_0
+#define USB2_QH10_LAST_REG 0x1280 // USB2_QH_USB2D_QH_EP_5_OUT_0
+#define USB2_QH11_FIRST_REG 0x12c0 // USB2_QH_USB2D_QH_EP_5_IN_0
+#define USB2_QH11_LAST_REG 0x12c0 // USB2_QH_USB2D_QH_EP_5_IN_0
+#define USB2_QH12_FIRST_REG 0x1300 // USB2_QH_USB2D_QH_EP_6_OUT_0
+#define USB2_QH12_LAST_REG 0x1300 // USB2_QH_USB2D_QH_EP_6_OUT_0
+#define USB2_QH13_FIRST_REG 0x1340 // USB2_QH_USB2D_QH_EP_6_IN_0
+#define USB2_QH13_LAST_REG 0x1340 // USB2_QH_USB2D_QH_EP_6_IN_0
+#define USB2_QH14_FIRST_REG 0x1380 // USB2_QH_USB2D_QH_EP_7_OUT_0
+#define USB2_QH14_LAST_REG 0x1380 // USB2_QH_USB2D_QH_EP_7_OUT_0
+#define USB2_QH15_FIRST_REG 0x13c0 // USB2_QH_USB2D_QH_EP_7_IN_0
+#define USB2_QH15_LAST_REG 0x13c0 // USB2_QH_USB2D_QH_EP_7_IN_0
+#define USB2_QH16_FIRST_REG 0x1400 // USB2_QH_USB2D_QH_EP_8_OUT_0
+#define USB2_QH16_LAST_REG 0x1400 // USB2_QH_USB2D_QH_EP_8_OUT_0
+#define USB2_QH17_FIRST_REG 0x1440 // USB2_QH_USB2D_QH_EP_8_IN_0
+#define USB2_QH17_LAST_REG 0x1440 // USB2_QH_USB2D_QH_EP_8_IN_0
+#define USB2_QH18_FIRST_REG 0x1480 // USB2_QH_USB2D_QH_EP_9_OUT_0
+#define USB2_QH18_LAST_REG 0x1480 // USB2_QH_USB2D_QH_EP_9_OUT_0
+#define USB2_QH19_FIRST_REG 0x14c0 // USB2_QH_USB2D_QH_EP_9_IN_0
+#define USB2_QH19_LAST_REG 0x14c0 // USB2_QH_USB2D_QH_EP_9_IN_0
+#define USB2_QH20_FIRST_REG 0x1500 // USB2_QH_USB2D_QH_EP_10_OUT_0
+#define USB2_QH20_LAST_REG 0x1500 // USB2_QH_USB2D_QH_EP_10_OUT_0
+#define USB2_QH21_FIRST_REG 0x1540 // USB2_QH_USB2D_QH_EP_10_IN_0
+#define USB2_QH21_LAST_REG 0x1540 // USB2_QH_USB2D_QH_EP_10_IN_0
+#define USB2_QH22_FIRST_REG 0x1580 // USB2_QH_USB2D_QH_EP_11_OUT_0
+#define USB2_QH22_LAST_REG 0x1580 // USB2_QH_USB2D_QH_EP_11_OUT_0
+#define USB2_QH23_FIRST_REG 0x15c0 // USB2_QH_USB2D_QH_EP_11_IN_0
+#define USB2_QH23_LAST_REG 0x15c0 // USB2_QH_USB2D_QH_EP_11_IN_0
+#define USB2_QH24_FIRST_REG 0x1600 // USB2_QH_USB2D_QH_EP_12_OUT_0
+#define USB2_QH24_LAST_REG 0x1600 // USB2_QH_USB2D_QH_EP_12_OUT_0
+#define USB2_QH25_FIRST_REG 0x1640 // USB2_QH_USB2D_QH_EP_12_IN_0
+#define USB2_QH25_LAST_REG 0x1640 // USB2_QH_USB2D_QH_EP_12_IN_0
+#define USB2_QH26_FIRST_REG 0x1680 // USB2_QH_USB2D_QH_EP_13_OUT_0
+#define USB2_QH26_LAST_REG 0x1680 // USB2_QH_USB2D_QH_EP_13_OUT_0
+#define USB2_QH27_FIRST_REG 0x16c0 // USB2_QH_USB2D_QH_EP_13_IN_0
+#define USB2_QH27_LAST_REG 0x16c0 // USB2_QH_USB2D_QH_EP_13_IN_0
+#define USB2_QH28_FIRST_REG 0x1700 // USB2_QH_USB2D_QH_EP_14_OUT_0
+#define USB2_QH28_LAST_REG 0x1700 // USB2_QH_USB2D_QH_EP_14_OUT_0
+#define USB2_QH29_FIRST_REG 0x1740 // USB2_QH_USB2D_QH_EP_14_IN_0
+#define USB2_QH29_LAST_REG 0x1740 // USB2_QH_USB2D_QH_EP_14_IN_0
+#define USB2_QH30_FIRST_REG 0x1780 // USB2_QH_USB2D_QH_EP_15_OUT_0
+#define USB2_QH30_LAST_REG 0x1780 // USB2_QH_USB2D_QH_EP_15_OUT_0
+#define USB2_QH31_FIRST_REG 0x17c0 // USB2_QH_USB2D_QH_EP_15_IN_0
+#define USB2_QH31_LAST_REG 0x17c0 // USB2_QH_USB2D_QH_EP_15_IN_0
+#define USB2_RX_MEM0_FIRST_REG 0x1800 // USB2_RX_MEM_USB2_RX_MEM_0
+#define USB2_RX_MEM0_LAST_REG 0x1800 // USB2_RX_MEM_USB2_RX_MEM_0
+#define USB2_TX_MEM0_FIRST_REG 0x2000 // USB2_TX_MEM_USB2_TX_MEM_0
+#define USB2_TX_MEM0_LAST_REG 0x2000 // USB2_TX_MEM_USB2_TX_MEM_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARUSB_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/arvi.h b/arch/arm/mach-tegra/nv/include/ap20/arvi.h
new file mode 100644
index 000000000000..6ce52e8e9a72
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/arvi.h
@@ -0,0 +1,14813 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ___ARVI_H_INC_
+#define ___ARVI_H_INC_
+// --------------------------------------------------------------------------
+//
+// Copyright (c) 2004, NVIDIA Corp.
+// All Rights Reserved.
+//
+// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
+// the contents of this file may not be disclosed to third parties, copied or
+// duplicated in any form, in whole or in part, without the prior written
+// permission of NVIDIA Corp.
+//
+// RESTRICTED RIGHTS LEGEND:
+// Use, duplication or disclosure by the Government is subject to restrictions
+// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
+// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
+// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
+// rights reserved under the Copyright Laws of the United States.
+//
+// --------------------------------------------------------------------------
+//
+// align 256;
+// --------------------------------------------------------------------------
+//
+// Copyright (c) 2004, NVIDIA Corp.
+// All Rights Reserved.
+//
+// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
+// the contents of this file may not be disclosed to third parties, copied or
+// duplicated in any form, in whole or in part, without the prior written
+// permission of NVIDIA Corp.
+//
+// RESTRICTED RIGHTS LEGEND:
+// Use, duplication or disclosure by the Government is subject to restrictions
+// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
+// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
+// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
+// rights reserved under the Copyright Laws of the United States.
+//
+// --------------------------------------------------------------------------
+//
+// Video Camera Interface register definition
+//
+// The Video Camera Interface takes input data from the VI port or from host.
+// Data from VI port can be in the following format:
+//  a. ITU-R BT.656: 1-byte/clock U8Y8V8Y8 format with embedded syncs in the data stream.
+//  b. YUV422: 1-byte/clock U8Y8V8Y8 format with H sync on VHS pin and V sync on VVS pin.
+//  c. Bayer Pattern (currently not supported): R8G8, G8B8 format with H sync on VHS pin and
+//     V sync on VVS pin.
+//  For case b and c, it is also possible to generate H sync and V sync internally in VI
+//  module. These internally generated H sync and V sync can be output to the external device
+//  and also used internally by the VI module.
+// Data from Host can be in the following format:
+//  a. YUV422: non-planar 32-bit U8Y8V8Y8 format going through Y-FIFO.
+//  b. YUV420: planar 32-bit Y, U, V format going through Y-FIFO, U-FIFO, V-FIFO
+//     correspondingly.
+// **** In the future, data from host should come from command buffer interface where YUV420
+//      to YUV422 conversion, if necessary, should be done using the command buffer.
+//      It may not be necessary to convert YUV420 to YUV422 if there is no image processing
+//      needed.
+//
+// The processing stages are:
+//  a. Horizontal low-pass filtering
+//  b. Horizontal down-scaling with or without horizontal averaging
+//  c. Vertical down-scaling with or without vertical averaging
+//  d. YUV to RGB Color Space Conversion
+//
+// Output can be sent to memory (typically for previewing the video image on the display) and/or
+// can be sent to Encoder Pre-Processor module to be encoded.
+//
+// Interface to memory is a normal Block Write or a YUV Block Write interface with option
+// for horizontal flip, vertical flip, and XY transpose. Data to be stored in memory can be
+// in 16-bit RGB format with optional dithering, YUV422 non-planar, and YUV422/420 planar.
+// If output data is stored as YUV420 planar format, the chroma data averaging can be optionally
+// performed for each pair of input lines.
+// Normal block write is used when output data is in RGB or YUV non-planar format.
+// YUV block write is used when output data is YUV planar format.
+//
+// Output data stored in memory is stored in one buffer set: video buffer 0.
+// Output buffer set 0 consists of a programmable number of buffers (from 1 to 255) defined by
+// VB0_COUNT parameter.
+// Each output buffer consists of programmable number of lines (max 1 frame) defined by
+// VB0_V_SIZE parameter which should be even number when data is stored in YUV420 format.
+// VB0_H_SIZE parameter determines the line stride (in pixels) and VB0_BUFFER_STRIDE
+// determines the buffer stride. The number of active pixels per line in the output buffer
+// depends on the input video horizontal active period and the scaling factor and should
+// typically not more than the line stride.
+// When output DMA request is enabled, the encoder will send a request to send the output
+// buffers to the host. Request will be sent after each output buffer is filled and also at the
+// end of each encoded frame.
+// Note that at the end of frame, the encoded data may not end at output buffer boundary.
+// The encoder will send the start address of the buffer to be transferred via the output DMA
+// and the correct size of the buffer with each request.
+// These are 32-bit registers that can be written/read from host register interface.
+// AP15 flow control
+// For AP15, we will not use host1xRDMA engine. VI will write into output buffer as is. SW will
+// use SYNCPT_OP_DONE as an indicator of one VI output buffer is ready for read. After SW
+// consumes one buffer, SW will write to BUFFER_RELEASE register.
+// EPP has an internal counter. Every buffer filed will increament the buffer, every write from
+// SW to BUFFER_RELEASE register will decrease this counter. VI will stall input bus if:
+// counter >= EPP_OUTPUT_BUFFER_COUNT - 1
+// For SW to use this flow control correctly, SW has to release all the buffers that locked by
+// VI to maintain synchronizations of SW and VI. For example, after flow control is enabled,
+// VI output 4 buffers, our flowControlBufferCount = 4. SW only need 2 of them. SW should
+// write to BUFFER_RELEASE register 4 times before switch VI for other stream capturing. There
+// is no reset of this counter or wrap around. This buffer will be zero after reset. VI
+// RTL does provide a EPP_DEBUG_CONTROL_FLOW_COUNTER register, but it is for debug only.
+// This apply to both Output1 and Output2.
+// suggested syncpt programming sequence: mail from sep.7th, 2007
+// -ISP single shot is definitely broken.  The current ECO is probably not correct.
+// When VI receives EOF from ISP (in single shot mode), we should squash subsequent
+// vsyncs but NOT hsyncs or data.
+// -We should test what happens if ISP gets too many lines in a frame
+// We think that the following sequence will work in all cases...
+// enable continuous vi op_done
+// while(1) {
+//      program pipe
+//      program stream defines for entire pipe
+//      invoke single shot
+//      issue start_write
+//      wait start_write
+//      issue reg_wr_safe
+//  flush buffer
+//      wait op_done
+//  trigger next unit
+//  wait reg_write_safe
+// }
+// syncpt commentes:
+//
+// VI has two different types of syncpt, single-shot and continuous.
+// Single-shot syncpts are requested by SW via a write to the one of the INCR_SYNCPT registers.
+// When the condition becomes true, the syncpt is returned.  Continuous syncpts are enabled by
+// a write to a CONT_SYNCPT register, and will be returned whenever the condition becomes true,
+// and does not require SW to do an INCR_SYNCPT write.
+//
+// single-shot synpct: There are three registers related to single-shot syncpt,
+//   VI_OUT_1_INCR_SYNCPT - applies to VI Memory Channel 1
+//   VI_OUT_2_INCR_SYNCPT - applies to VI Memory Channel 2
+//   VI_MISC_INCR_SYNPCT  - applies to non-memory related conditions
+//
+// condition: There are 5 conditions for VI_OUT_1_INCR_SYNCPT and VI_OUT_2_INCR_SYNCPT
+//   0 -- immediate : syncpt index will be returned immediately when VI_OUT_1/2_INCR_SYNCPT is written.
+//   1 -- OP_DONE: syncpt index will be returned when the corresponding output is idle, either output1
+//        or output2. This syncpt is level triggered.
+//   2 -- RD_DONE:  this is treated the same as OP_DONE condition
+//   3 -- REG_WR_SAFE: when all the resources defined in RESOURCE_DEFINE register are all idle, the
+//        syncpt index will be returned. This synpct is level triggered.
+//   4 -- START_WRITE: when the first pixel is written to memory, either from camera or host, the syncpt
+//        index will be returned. This syncpt is edge triggered.
+// condition: There are 9 conditions for VI_MISC_INCR_SYNCPT
+//            single-shot syncpts (excpet immediate) are not supported on the MISC syncpt.
+//   0 -- immediate: syncpt index will be returned immediately when VI_MISC_INCR_SYNCPT is written.
+//        This is a level triggered syncpt.
+//
+// continuous syncpt: There are eight continuous syncpt in VI. Each of them can be enable by set the
+// ENABLE bit along with syncpt index field.
+// Whenever a continous syncpt is enabled, the corresponding single-shot syncpt may not be used.
+//
+// VI_CONT_SYNCPT_OUT_1:
+//      Condition for syncpt return is OP_DONE from output 1.
+// VI_CONT_SYNCPT_OUT_2:
+//      Condition for syncpt return is OP_DONE from output 1.
+// VI_CONT_SYNCPT_VIP_VSYNC:
+//      syncpt index will be returned when the first vsync from VIP input is received. This is an
+//      edge triggered syncpt.
+// VI_CONT_SYNCPT_VI2EPP:
+//      This condition will forward syncpt to EPP whenever data is sent to EPP. It will forward once per
+//      EPP buffer. The syncpt will sent to EPP at the first line of the buffer, and after every
+//      LINES_PER_BUFFER lines (as defined by the EPP_LINES_PER_BUFFER register). EPP will return the syncpt
+//      when the last byte of a buffer is written into memory(tag returned).
+// VI_CONT_SYNCPT_CSI_PPA_FRAME_START:
+//      The condition for this syncpt is CSI PPA port received a frame start.
+// VI_CONT_SYNCPT_CSI_PPA_FRAME_END:
+//      The condition for this syncpt is CSI PPA port received a frame end.
+// VI_CONT_SYNCPT_CSI_PPB_FRAME_START:
+//      The condition for this syncpt is CSI PPB port received a frame start. MISC_CSI_PPB_FRAME_START.
+// VI_CONT_SYNCPT_CSI_PPB_FRAME_END:
+//      The condition for this syncpt is CSI PPB port received a frame end.
+//
+// REG_WR_SAFE's "safe" condition is defined by the VI_STREAM_1_RESOURCE_DEFINE (for OUT_1) and
+// VI_STREAM_2_RESOURCE_DEFINE (for OUT_2).  The syncpt will return when all the requested resources are IDLE.
+// If no resources are requested, it will return immediately.
+//
+// Since REG_WR_SAFE is level triggered, it should be used in conjuction with START_WRITE.  In the format of:
+//      INCR_SYNCPT <START_WRITE>
+//      WAIT (START_WRITE)
+//      INCR_SYNCPT <REG_WR_SAFE>
+//
+// Continuous syncpt always use OP_DONE as condition. The mapping of continuous syncpt to single-shot syncpt:
+//   VI_CONT_SYNCPT_OUT_1                              mapped to VI_OUT_1_INCR_SYNCPT condition OP_DONE
+//   VI_CONT_SYNCPT_OUT_2                              mapped to VI_OUT_2_INCR_SYNCPT condition OP_DONE
+//   VI_CONT_SYNCPT_VIP_VSYN                        mapped to VI_MISC_INCR_SYNCPT condition MISC_VIP_VSYNC
+//   VI_CONT_SYNCPT_CSI_PPA_FRAME_START mapped to VI_MISC_INCR_SYNCPT condition MISC_CSI_PPA_FRAME_START
+//   VI_CONT_SYNCPT_CSI_PPA_FRAME_END     mapped to VI_MISC_INCR_SYNCPT condition MISC_CSI_PPA_FRAME_END
+//   VI_CONT_SYNCPT_CSI_PPB_FRAME_START mapped to VI_MISC_INCR_SYNCPT condition MISC_CSI_PPB_FRAME_START
+//   VI_CONT_SYNCPT_CSI_PPB_FRAME_END     mapped to VI_MISC_INCR_SYNCPT condition MISC_CSI_PPB_FRAME_END
+//   VI_CONT_SYNCPT_VI2EPP                             mapped to EPP_INCR_SYNCPT condition OP_DONE
+// Can not program continuous syncpt with mapping single_shot syncpt conditions. It is fine to program continuous
+// syncpt with other syncpt conditions. For example:
+//      enable VI_CONT_OUT_1 with VI_OUT_1_INCR_SYNCPT condition REG_WR_SAFE  -- ok
+//      enable VI_CONT_OUT_2 with VI_OUT_1_INCR_SYNCPT condition OP_DONE      -- ok
+//      enable VI_CONT_VIP_VSYNC with VI_MISC_INCR_SYNCPT condition VIP_VSYNC -- not ok
+//      enable VI_CONT_OUT1 with VI_OUT_1_INCR_SYNCPT condition OP_DONE       -- not ok
+//
+#define NV_VI_OUT_1_INCR_SYNCPT_NB_CONDS        5
+// --------------------------------------------------------------------------
+// 
+// Copyright (c) 2004, NVIDIA Corp.
+// All Rights Reserved.
+// 
+// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
+// the contents of this file may not be disclosed to third parties, copied or
+// duplicated in any form, in whole or in part, without the prior written
+// permission of NVIDIA Corp.
+// 
+// RESTRICTED RIGHTS LEGEND:
+// Use, duplication or disclosure by the Government is subject to restrictions
+// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
+// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
+// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
+// rights reserved under the Copyright Laws of the United States.
+// 
+// --------------------------------------------------------------------------
+// 
+
+// Register VI_OUT_1_INCR_SYNCPT_0  
+#define VI_OUT_1_INCR_SYNCPT_0                  _MK_ADDR_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_SECURE                   0x0
+#define VI_OUT_1_INCR_SYNCPT_0_WORD_COUNT                       0x1
+#define VI_OUT_1_INCR_SYNCPT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_OUT_1_INCR_SYNCPT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_OUT_1_INCR_SYNCPT_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Condition mapped from raise/wait
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SHIFT                 _MK_SHIFT_CONST(8)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_RANGE                 15:8
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_WOFFSET                       0x0
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_IMMEDIATE                     _MK_ENUM_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_OP_DONE                       _MK_ENUM_CONST(1)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_RD_DONE                       _MK_ENUM_CONST(2)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_REG_WR_SAFE                   _MK_ENUM_CONST(3)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_START_WRITE                   _MK_ENUM_CONST(4)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_5                        _MK_ENUM_CONST(5)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_6                        _MK_ENUM_CONST(6)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_7                        _MK_ENUM_CONST(7)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_8                        _MK_ENUM_CONST(8)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_9                        _MK_ENUM_CONST(9)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_10                       _MK_ENUM_CONST(10)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_11                       _MK_ENUM_CONST(11)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_12                       _MK_ENUM_CONST(12)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_13                       _MK_ENUM_CONST(13)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_14                       _MK_ENUM_CONST(14)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_COND_COND_15                       _MK_ENUM_CONST(15)
+
+// syncpt index value
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_RANGE                 7:0
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_WOFFSET                       0x0
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_0_OUT_1_INDX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_1_INCR_SYNCPT_CNTRL_0  
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0                    _MK_ADDR_CONST(0x1)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_SECURE                     0x0
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_WORD_COUNT                         0x1
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_RESET_MASK                         _MK_MASK_CONST(0x101)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_READ_MASK                  _MK_MASK_CONST(0x101)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x101)
+// If NO_STALL is 1, then when fifos are full,
+// INCR_SYNCPT methods will be dropped and the
+// INCR_SYNCPT_ERROR[COND] bit will be set.
+// If NO_STALL is 0, then when fifos are full,
+// the client host interface will be stalled.
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_FIELD                   (_MK_MASK_CONST(0x1) << VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_RANGE                   8:8
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_WOFFSET                 0x0
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// If SOFT_RESET is set, then all internal state
+// of the client syncpt block will be reset.
+// To do soft reset, first set SOFT_RESET of
+// all host1x clients affected, then clear all
+// SOFT_RESETs.
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_FIELD                 (_MK_MASK_CONST(0x1) << VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_RANGE                 0:0
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_WOFFSET                       0x0
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_CNTRL_0_OUT_1_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_1_INCR_SYNCPT_ERROR_0  
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0                    _MK_ADDR_CONST(0x2)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_SECURE                     0x0
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_WORD_COUNT                         0x1
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// COND_STATUS[COND] is set if the fifo for COND overflows.
+// This bit is sticky and will remain set until cleared.
+// Cleared by writing 1.
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_FIELD                    (_MK_MASK_CONST(0xffffffff) << VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SHIFT)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_RANGE                    31:0
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_WOFFSET                  0x0
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_1_INCR_SYNCPT_ERROR_0_OUT_1_COND_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// reserve locations for future expansion
+
+// Reserved address 3 [0x3] 
+
+// Reserved address 4 [0x4] 
+
+// Reserved address 5 [0x5] 
+
+// Reserved address 6 [0x6] 
+
+// Reserved address 7 [0x7] 
+// just in case names were redefined using macros
+#define NV_VI_OUT_2_INCR_SYNCPT_NB_CONDS        5
+// --------------------------------------------------------------------------
+// 
+// Copyright (c) 2004, NVIDIA Corp.
+// All Rights Reserved.
+// 
+// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
+// the contents of this file may not be disclosed to third parties, copied or
+// duplicated in any form, in whole or in part, without the prior written
+// permission of NVIDIA Corp.
+// 
+// RESTRICTED RIGHTS LEGEND:
+// Use, duplication or disclosure by the Government is subject to restrictions
+// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
+// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
+// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
+// rights reserved under the Copyright Laws of the United States.
+// 
+// --------------------------------------------------------------------------
+// 
+
+// Register VI_OUT_2_INCR_SYNCPT_0  
+#define VI_OUT_2_INCR_SYNCPT_0                  _MK_ADDR_CONST(0x8)
+#define VI_OUT_2_INCR_SYNCPT_0_SECURE                   0x0
+#define VI_OUT_2_INCR_SYNCPT_0_WORD_COUNT                       0x1
+#define VI_OUT_2_INCR_SYNCPT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_OUT_2_INCR_SYNCPT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_OUT_2_INCR_SYNCPT_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Condition mapped from raise/wait
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SHIFT                 _MK_SHIFT_CONST(8)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_RANGE                 15:8
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_WOFFSET                       0x0
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_IMMEDIATE                     _MK_ENUM_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_OP_DONE                       _MK_ENUM_CONST(1)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_RD_DONE                       _MK_ENUM_CONST(2)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_REG_WR_SAFE                   _MK_ENUM_CONST(3)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_START_WRITE                   _MK_ENUM_CONST(4)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_5                        _MK_ENUM_CONST(5)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_6                        _MK_ENUM_CONST(6)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_7                        _MK_ENUM_CONST(7)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_8                        _MK_ENUM_CONST(8)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_9                        _MK_ENUM_CONST(9)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_10                       _MK_ENUM_CONST(10)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_11                       _MK_ENUM_CONST(11)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_12                       _MK_ENUM_CONST(12)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_13                       _MK_ENUM_CONST(13)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_14                       _MK_ENUM_CONST(14)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_COND_COND_15                       _MK_ENUM_CONST(15)
+
+// syncpt index value
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_FIELD                 (_MK_MASK_CONST(0xff) << VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_RANGE                 7:0
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_WOFFSET                       0x0
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_DEFAULT_MASK                  _MK_MASK_CONST(0xff)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_0_OUT_2_INDX_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_2_INCR_SYNCPT_CNTRL_0  
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0                    _MK_ADDR_CONST(0x9)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_SECURE                     0x0
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_WORD_COUNT                         0x1
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_RESET_MASK                         _MK_MASK_CONST(0x101)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_READ_MASK                  _MK_MASK_CONST(0x101)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_WRITE_MASK                         _MK_MASK_CONST(0x101)
+// If NO_STALL is 1, then when fifos are full,
+// INCR_SYNCPT methods will be dropped and the
+// INCR_SYNCPT_ERROR[COND] bit will be set.
+// If NO_STALL is 0, then when fifos are full,
+// the client host interface will be stalled.
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_FIELD                   (_MK_MASK_CONST(0x1) << VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_RANGE                   8:8
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_WOFFSET                 0x0
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// If SOFT_RESET is set, then all internal state
+// of the client syncpt block will be reset.
+// To do soft reset, first set SOFT_RESET of
+// all host1x clients affected, then clear all
+// SOFT_RESETs.
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_FIELD                 (_MK_MASK_CONST(0x1) << VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_RANGE                 0:0
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_WOFFSET                       0x0
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_CNTRL_0_OUT_2_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_OUT_2_INCR_SYNCPT_ERROR_0  
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0                    _MK_ADDR_CONST(0xa)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_SECURE                     0x0
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_WORD_COUNT                         0x1
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// COND_STATUS[COND] is set if the fifo for COND overflows.
+// This bit is sticky and will remain set until cleared.
+// Cleared by writing 1.
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_FIELD                    (_MK_MASK_CONST(0xffffffff) << VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SHIFT)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_RANGE                    31:0
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_WOFFSET                  0x0
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_OUT_2_INCR_SYNCPT_ERROR_0_OUT_2_COND_STATUS_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// reserve locations for future expansion
+
+// Reserved address 11 [0xb] 
+
+// Reserved address 12 [0xc] 
+
+// Reserved address 13 [0xd] 
+
+// Reserved address 14 [0xe] 
+
+// Reserved address 15 [0xf] 
+// just in case names were redefined using macros
+#define NV_VI_MISC_INCR_SYNCPT_NB_CONDS 9
+// --------------------------------------------------------------------------
+// 
+// Copyright (c) 2004, NVIDIA Corp.
+// All Rights Reserved.
+// 
+// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
+// the contents of this file may not be disclosed to third parties, copied or
+// duplicated in any form, in whole or in part, without the prior written
+// permission of NVIDIA Corp.
+// 
+// RESTRICTED RIGHTS LEGEND:
+// Use, duplication or disclosure by the Government is subject to restrictions
+// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
+// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
+// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
+// rights reserved under the Copyright Laws of the United States.
+// 
+// --------------------------------------------------------------------------
+// 
+
+// Register VI_MISC_INCR_SYNCPT_0  
+#define VI_MISC_INCR_SYNCPT_0                   _MK_ADDR_CONST(0x10)
+#define VI_MISC_INCR_SYNCPT_0_SECURE                    0x0
+#define VI_MISC_INCR_SYNCPT_0_WORD_COUNT                        0x1
+#define VI_MISC_INCR_SYNCPT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_RESET_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_MISC_INCR_SYNCPT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_READ_MASK                         _MK_MASK_CONST(0xffff)
+#define VI_MISC_INCR_SYNCPT_0_WRITE_MASK                        _MK_MASK_CONST(0xffff)
+// Condition mapped from raise/wait
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_FIELD                   (_MK_MASK_CONST(0xff) << VI_MISC_INCR_SYNCPT_0_MISC_COND_SHIFT)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_RANGE                   15:8
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_WOFFSET                 0x0
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_IMMEDIATE                       _MK_ENUM_CONST(0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_OP_DONE                 _MK_ENUM_CONST(1)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_RD_DONE                 _MK_ENUM_CONST(2)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_REG_WR_SAFE                     _MK_ENUM_CONST(3)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_VIP_VSYNC                  _MK_ENUM_CONST(4)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPA_FRAME_START                        _MK_ENUM_CONST(5)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPA_FRAME_END                  _MK_ENUM_CONST(6)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPB_FRAME_START                        _MK_ENUM_CONST(7)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_MISC_CSI_PPB_FRAME_END                  _MK_ENUM_CONST(8)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_9                  _MK_ENUM_CONST(9)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_10                 _MK_ENUM_CONST(10)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_11                 _MK_ENUM_CONST(11)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_12                 _MK_ENUM_CONST(12)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_13                 _MK_ENUM_CONST(13)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_14                 _MK_ENUM_CONST(14)
+#define VI_MISC_INCR_SYNCPT_0_MISC_COND_COND_15                 _MK_ENUM_CONST(15)
+
+// syncpt index value
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_FIELD                   (_MK_MASK_CONST(0xff) << VI_MISC_INCR_SYNCPT_0_MISC_INDX_SHIFT)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_RANGE                   7:0
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_WOFFSET                 0x0
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_0_MISC_INDX_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_MISC_INCR_SYNCPT_CNTRL_0  
+#define VI_MISC_INCR_SYNCPT_CNTRL_0                     _MK_ADDR_CONST(0x11)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_SECURE                      0x0
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_WORD_COUNT                  0x1
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_RESET_MASK                  _MK_MASK_CONST(0x101)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_READ_MASK                   _MK_MASK_CONST(0x101)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_WRITE_MASK                  _MK_MASK_CONST(0x101)
+// If NO_STALL is 1, then when fifos are full,
+// INCR_SYNCPT methods will be dropped and the
+// INCR_SYNCPT_ERROR[COND] bit will be set.
+// If NO_STALL is 0, then when fifos are full,
+// the client host interface will be stalled.
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_FIELD                     (_MK_MASK_CONST(0x1) << VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SHIFT)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_RANGE                     8:8
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_WOFFSET                   0x0
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// If SOFT_RESET is set, then all internal state
+// of the client syncpt block will be reset.
+// To do soft reset, first set SOFT_RESET of
+// all host1x clients affected, then clear all
+// SOFT_RESETs.
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_FIELD                   (_MK_MASK_CONST(0x1) << VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SHIFT)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_RANGE                   0:0
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_WOFFSET                 0x0
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_CNTRL_0_MISC_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_MISC_INCR_SYNCPT_ERROR_0  
+#define VI_MISC_INCR_SYNCPT_ERROR_0                     _MK_ADDR_CONST(0x12)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_SECURE                      0x0
+#define VI_MISC_INCR_SYNCPT_ERROR_0_WORD_COUNT                  0x1
+#define VI_MISC_INCR_SYNCPT_ERROR_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+// COND_STATUS[COND] is set if the fifo for COND overflows.
+// This bit is sticky and will remain set until cleared.
+// Cleared by writing 1.
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SHIFT)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_RANGE                      31:0
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_WOFFSET                    0x0
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MISC_INCR_SYNCPT_ERROR_0_MISC_COND_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// reserve locations for future expansion
+
+// Reserved address 19 [0x13] 
+
+// Reserved address 20 [0x14] 
+
+// Reserved address 21 [0x15] 
+
+// Reserved address 22 [0x16] 
+
+// Reserved address 23 [0x17] 
+// just in case names were redefined using macros
+
+// Register VI_CONT_SYNCPT_OUT_1_0  
+#define VI_CONT_SYNCPT_OUT_1_0                  _MK_ADDR_CONST(0x18)
+#define VI_CONT_SYNCPT_OUT_1_0_SECURE                   0x0
+#define VI_CONT_SYNCPT_OUT_1_0_WORD_COUNT                       0x1
+#define VI_CONT_SYNCPT_OUT_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_RESET_MASK                       _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_OUT_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_OUT_1_0_WRITE_MASK                       _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SHIFT)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_RANGE                 7:0
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_INDX_OUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time OUT_1 condition is true and OUT_1_EN is set
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SHIFT)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_RANGE                   8:8
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_1_0_EN_OUT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_OUT_2_0  
+#define VI_CONT_SYNCPT_OUT_2_0                  _MK_ADDR_CONST(0x19)
+#define VI_CONT_SYNCPT_OUT_2_0_SECURE                   0x0
+#define VI_CONT_SYNCPT_OUT_2_0_WORD_COUNT                       0x1
+#define VI_CONT_SYNCPT_OUT_2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_RESET_MASK                       _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_OUT_2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_OUT_2_0_WRITE_MASK                       _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SHIFT)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_RANGE                 7:0
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_INDX_OUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time OUT_2 condition is true and OUT_2_EN is set
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SHIFT)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_RANGE                   8:8
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_OUT_2_0_EN_OUT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_VIP_VSYNC_0  
+#define VI_CONT_SYNCPT_VIP_VSYNC_0                      _MK_ADDR_CONST(0x1a)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_SECURE                       0x0
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_WORD_COUNT                   0x1
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_RESET_MASK                   _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SHIFT)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_RANGE                 7:0
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_INDX_VIP_VSYNC_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time VSYNC condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SHIFT)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_RANGE                   8:8
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VIP_VSYNC_0_EN_VIP_VSYNC_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_VI2EPP_0  
+#define VI_CONT_SYNCPT_VI2EPP_0                 _MK_ADDR_CONST(0x1b)
+#define VI_CONT_SYNCPT_VI2EPP_0_SECURE                  0x0
+#define VI_CONT_SYNCPT_VI2EPP_0_WORD_COUNT                      0x1
+#define VI_CONT_SYNCPT_VI2EPP_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_RESET_MASK                      _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_VI2EPP_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_READ_MASK                       _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_VI2EPP_0_WRITE_MASK                      _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_FIELD                       (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SHIFT)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_RANGE                       7:0
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_WOFFSET                     0x0
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_INDX_VI2EPP_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// on host read bus every time VI2EPP condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SHIFT                 _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_FIELD                 (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SHIFT)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_RANGE                 8:8
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_VI2EPP_0_EN_VI2EPP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0  
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0                    _MK_ADDR_CONST(0x1c)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_SECURE                     0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_WORD_COUNT                         0x1
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_RESET_MASK                         _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_FIELD                     (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_RANGE                     7:0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_WOFFSET                   0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_INDX_CSI_PPA_FRAME_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPA_FRAME_START condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_FIELD                       (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_RANGE                       8:8
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_WOFFSET                     0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0_EN_CSI_PPA_FRAME_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0  
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0                      _MK_ADDR_CONST(0x1d)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_SECURE                       0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_WORD_COUNT                   0x1
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_RESET_MASK                   _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_RANGE                 7:0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_INDX_CSI_PPA_FRAME_END_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPA_FRAME_END condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_RANGE                   8:8
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0_EN_CSI_PPA_FRAME_END_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0  
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0                    _MK_ADDR_CONST(0x1e)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_SECURE                     0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_WORD_COUNT                         0x1
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_RESET_MASK                         _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_READ_MASK                  _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_FIELD                     (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_RANGE                     7:0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_WOFFSET                   0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_INDX_CSI_PPB_FRAME_START_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPB_FRAME_START condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_FIELD                       (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_RANGE                       8:8
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_WOFFSET                     0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0_EN_CSI_PPB_FRAME_START_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0  
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0                      _MK_ADDR_CONST(0x1f)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_SECURE                       0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_WORD_COUNT                   0x1
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_RESET_MASK                   _MK_MASK_CONST(0x100)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// return INDX (set HOST_CLRD packet TYPE field to SYNCPT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_FIELD                 (_MK_MASK_CONST(0xff) << VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_RANGE                 7:0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_WOFFSET                       0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_INDX_CSI_PPB_FRAME_END_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// on host read bus every time CSI_PPB_FRAME_END condition is true and EN_VSYNC is set
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_FIELD                   (_MK_MASK_CONST(0x1) << VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SHIFT)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_RANGE                   8:8
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_WOFFSET                 0x0
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0_EN_CSI_PPB_FRAME_END_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Context switch register.  Should be common to all modules.  Includes the
+// current channel/class (which is writable by SW) and the next channel/class
+// (which the hardware sets when it receives a context switch).
+// Context switch works like this:
+// Any context switch request triggers an interrupt to the host and causes the
+// new channel/class to be stored in NEXT_CHANNEL/NEXT_CLASS (see
+// vmod/chexample).  SW sees that there is a context switch interrupt and does
+// the necessary operations to make the module ready to receive traffic from
+// the new context.  It clears the context switch interrupt and writes
+// CURR_CHANNEL/CLASS to the same value as NEXT_CHANNEL/CLASS, which causes a
+// context switch acknowledge packet to be sent to the host.  This completes
+// the context switch and allows the host to continue sending data to the
+// module.
+// Context switches can also be pre-loaded.  If CURR_CLASS/CHANNEL are written
+// and updated to the next CLASS/CHANNEL before the context switch request
+// occurs, an acknowledge will be generated by the module and no interrupt will
+// be triggered.  This is one way for software to avoid dealing with context
+// switch interrupts.
+// Another way to avoid context switch interrupts is to set the AUTO_ACK bit.
+// This bit tells the module to automatically acknowledge any incoming context
+// switch requests without triggering an interrupt.  CURR_* and NEXT_* will be
+// updated by the module so they will always be current.
+
+// Register VI_CTXSW_0  
+#define VI_CTXSW_0                      _MK_ADDR_CONST(0x20)
+#define VI_CTXSW_0_SECURE                       0x0
+#define VI_CTXSW_0_WORD_COUNT                   0x1
+#define VI_CTXSW_0_RESET_VAL                    _MK_MASK_CONST(0xf000f800)
+#define VI_CTXSW_0_RESET_MASK                   _MK_MASK_CONST(0xf3fffbff)
+#define VI_CTXSW_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_READ_MASK                    _MK_MASK_CONST(0xf3fffbff)
+#define VI_CTXSW_0_WRITE_MASK                   _MK_MASK_CONST(0xfbff)
+// Current working class
+#define VI_CTXSW_0_CURR_CLASS_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_CTXSW_0_CURR_CLASS_FIELD                     (_MK_MASK_CONST(0x3ff) << VI_CTXSW_0_CURR_CLASS_SHIFT)
+#define VI_CTXSW_0_CURR_CLASS_RANGE                     9:0
+#define VI_CTXSW_0_CURR_CLASS_WOFFSET                   0x0
+#define VI_CTXSW_0_CURR_CLASS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_CURR_CLASS_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
+#define VI_CTXSW_0_CURR_CLASS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_CURR_CLASS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Automatically acknowledge any incoming context switch requests
+#define VI_CTXSW_0_AUTO_ACK_SHIFT                       _MK_SHIFT_CONST(11)
+#define VI_CTXSW_0_AUTO_ACK_FIELD                       (_MK_MASK_CONST(0x1) << VI_CTXSW_0_AUTO_ACK_SHIFT)
+#define VI_CTXSW_0_AUTO_ACK_RANGE                       11:11
+#define VI_CTXSW_0_AUTO_ACK_WOFFSET                     0x0
+#define VI_CTXSW_0_AUTO_ACK_DEFAULT                     _MK_MASK_CONST(0x1)
+#define VI_CTXSW_0_AUTO_ACK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_CTXSW_0_AUTO_ACK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_AUTO_ACK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_AUTO_ACK_MANUAL                      _MK_ENUM_CONST(0)
+#define VI_CTXSW_0_AUTO_ACK_AUTOACK                     _MK_ENUM_CONST(1)
+
+// Current working channel, reset to 'invalid'
+#define VI_CTXSW_0_CURR_CHANNEL_SHIFT                   _MK_SHIFT_CONST(12)
+#define VI_CTXSW_0_CURR_CHANNEL_FIELD                   (_MK_MASK_CONST(0xf) << VI_CTXSW_0_CURR_CHANNEL_SHIFT)
+#define VI_CTXSW_0_CURR_CHANNEL_RANGE                   15:12
+#define VI_CTXSW_0_CURR_CHANNEL_WOFFSET                 0x0
+#define VI_CTXSW_0_CURR_CHANNEL_DEFAULT                 _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_CURR_CHANNEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_CURR_CHANNEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_CURR_CHANNEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Next requested class
+#define VI_CTXSW_0_NEXT_CLASS_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CTXSW_0_NEXT_CLASS_FIELD                     (_MK_MASK_CONST(0x3ff) << VI_CTXSW_0_NEXT_CLASS_SHIFT)
+#define VI_CTXSW_0_NEXT_CLASS_RANGE                     25:16
+#define VI_CTXSW_0_NEXT_CLASS_WOFFSET                   0x0
+#define VI_CTXSW_0_NEXT_CLASS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_NEXT_CLASS_DEFAULT_MASK                      _MK_MASK_CONST(0x3ff)
+#define VI_CTXSW_0_NEXT_CLASS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_NEXT_CLASS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Next requested channel
+#define VI_CTXSW_0_NEXT_CHANNEL_SHIFT                   _MK_SHIFT_CONST(28)
+#define VI_CTXSW_0_NEXT_CHANNEL_FIELD                   (_MK_MASK_CONST(0xf) << VI_CTXSW_0_NEXT_CHANNEL_SHIFT)
+#define VI_CTXSW_0_NEXT_CHANNEL_RANGE                   31:28
+#define VI_CTXSW_0_NEXT_CHANNEL_WOFFSET                 0x0
+#define VI_CTXSW_0_NEXT_CHANNEL_DEFAULT                 _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_NEXT_CHANNEL_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_INTSTATUS_0  
+#define VI_INTSTATUS_0                  _MK_ADDR_CONST(0x21)
+#define VI_INTSTATUS_0_SECURE                   0x0
+#define VI_INTSTATUS_0_WORD_COUNT                       0x1
+#define VI_INTSTATUS_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_RESET_MASK                       _MK_MASK_CONST(0x1)
+#define VI_INTSTATUS_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_READ_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTSTATUS_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// Context switch interrupt status (clear on write)
+#define VI_INTSTATUS_0_CTXSW_INT_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_INTSTATUS_0_CTXSW_INT_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTSTATUS_0_CTXSW_INT_SHIFT)
+#define VI_INTSTATUS_0_CTXSW_INT_RANGE                  0:0
+#define VI_INTSTATUS_0_CTXSW_INT_WOFFSET                        0x0
+#define VI_INTSTATUS_0_CTXSW_INT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_CTXSW_INT_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTSTATUS_0_CTXSW_INT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTSTATUS_0_CTXSW_INT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// For Parallel VIP input, limitation for vsync and hsync has to be followed to avoid ISP hang for AP15:
+// SW must always program parallel cameras (including the VIP pattern generator) in a way that
+// avoids simultaneous hsync and vsync active edges. copied from bug:361730
+
+// Register VI_VI_INPUT_CONTROL_0  // VI Input Control
+#define VI_VI_INPUT_CONTROL_0                   _MK_ADDR_CONST(0x22)
+#define VI_VI_INPUT_CONTROL_0_SECURE                    0x0
+#define VI_VI_INPUT_CONTROL_0_WORD_COUNT                        0x1
+#define VI_VI_INPUT_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x7f801fff)
+#define VI_VI_INPUT_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x7f801fff)
+#define VI_VI_INPUT_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x7f801fff)
+// Host Input Enable   0= DISABLED
+//   1= ENABLED
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_RANGE                   0:0
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VIP Input Enable   0= DISABLED
+//   1= ENABLED
+// This bit turn on clocks for VIP input logic. This
+//   bit has to be enabled before CAMERA_CONTROL's
+//   VIP_ENABLE bit for any VIP logic to start!
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_RANGE                    1:1
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_VIP_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// Input port data Format  (effective if input source is VI Port)
+//   0000= YUV422 or ITU-R BT.656
+//   0001= Reserved 1
+//   0010= Bayer Pattern, enables ISP
+//   0011= Reserved 2
+//   0100= Pattern A, written directly to memory
+//   0101= Pattern B, written directly to memory
+//   0110= Pattern C, written directly to memory
+//   0111= Pattern C, do not remove the 0xFF, 0x02
+//   1000= Pattern D, ISDB-T input
+//   1001= YUV420NP, written directly to memory as YUV420P
+//   1010= RGB565, written directly to EPP
+//   1011= RGB888, written directly to EPP
+//   1100= RGB444, written directly to EPP
+//   1101= CSI,    written directly to CSI
+//         For YUV420NP no cropping will be done.
+//         For RGB565,RGB888,RGB444 written to EPP
+//         all cropping will be done in the EPP.
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SHIFT                   _MK_SHIFT_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_FIELD                   (_MK_MASK_CONST(0xf) << VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RANGE                   5:2
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_YUV422                  _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RESERVED_1                      _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_BAYER                   _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RESERVED_2                      _MK_ENUM_CONST(3)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_A                       _MK_ENUM_CONST(4)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_B                       _MK_ENUM_CONST(5)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_C                       _MK_ENUM_CONST(6)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_C_RAW                   _MK_ENUM_CONST(7)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_PATTERN_D                       _MK_ENUM_CONST(8)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_YUV420                  _MK_ENUM_CONST(9)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RGB565                  _MK_ENUM_CONST(10)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RGB888                  _MK_ENUM_CONST(11)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_RGB444                  _MK_ENUM_CONST(12)
+#define VI_VI_INPUT_CONTROL_0_INPUT_PORT_FORMAT_CSI                     _MK_ENUM_CONST(13)
+
+// Host data Format  (effective if input source is host)
+//   00= Non-planar YUV422
+//      (only Y-FIFO is used)
+//   01= Planar YUV420
+//      (Y-FIFO, U-FIFO, V-FIFO are used)
+//   10= Bayer 8-bit  - enables ISP
+//   11= Bayer 12-bit - enables ISP
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_FIELD                 (_MK_MASK_CONST(0x3) << VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_RANGE                 7:6
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_NONPLANAR                     _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_PLANAR                        _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_BAYER8                        _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_BAYER12                       _MK_ENUM_CONST(3)
+
+// YUV Input Format This is applicable when input source is
+// VI Port and format is YUV422/ITU-R BT.656
+// or when input source is host and host
+// format is non-planar YUV422.
+//  8 bits per component
+//   00= UYVY => Y1_V0_Y0_U0 MSB to LSB 32bit mapping
+//   01= VYUY => Y1_U0_Y0_V0
+//   10= YUYV => V0_Y1_U0_Y0
+//   11= YVYU => U0_Y1_V0_Y0
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_RANGE                    9:8
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_WOFFSET                  0x0
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_UYVY                     _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_VYUY                     _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_YUYV                     _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_YUV_INPUT_FORMAT_YVYU                     _MK_ENUM_CONST(3)
+
+// Select a data source input to HOST (extension field).  (use when input source is host)
+//  000= Source is selected with HOST_FORMAT field (backward compatible)
+//  001= Bayer 10 bpp: 2 16-bit values packed into 32-bit, LSbit aligned {6'b0, bayer, 6'b0, bayer} (to ISP)
+//  010= Bayer 14 bpp: 2 16-bit values packed into 32-bit, LSbit aligned {2'b0, bayer, 2'b0, bayer} (to ISP)
+//  011= RGB565             (to EPP)
+//  100= MSB Alpha + RGB888 (to EPP)
+//  101= MSB Alpha + BGR888 (to EPP)
+//  110= CSI                (to CSI)
+//  111= reserved
+// 22:13 reserved
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SHIFT                     _MK_SHIFT_CONST(10)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_FIELD                     (_MK_MASK_CONST(0x7) << VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_RANGE                     12:10
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_WOFFSET                   0x0
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_DEFAULT_MASK                      _MK_MASK_CONST(0x7)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_USE_HOST_FORMAT                   _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_BAYER10                   _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_BAYER14                   _MK_ENUM_CONST(2)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_RGB565                    _MK_ENUM_CONST(3)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_ARGB8888                  _MK_ENUM_CONST(4)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_ABGR8888                  _MK_ENUM_CONST(5)
+#define VI_VI_INPUT_CONTROL_0_HOST_FORMAT_EXT_CSI                       _MK_ENUM_CONST(6)
+
+// VHS input signal active edge which is used  as horizontal reference of input data.
+//  VHS input inversion is evaluated first
+//  before determining active edge.
+//   0= Rising edge of VHS is active edge.
+//      For ITU-R BT.656 data, leading edge of
+//      horizontal sync is the active edge.
+//   1= Falling edge of VHS is active edge
+//      For ITU-R BT.656 data, trailing edge
+//      of horizontal sync is the active edge.
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SHIFT                 _MK_SHIFT_CONST(23)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_FIELD                 (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_RANGE                 23:23
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_RISING                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_VHS_IN_EDGE_FALLING                       _MK_ENUM_CONST(1)
+
+// VVS input signal active edge which is used  as vertical reference of input data
+//  VVS input inversion is evaluated first
+//  before determining active edge.
+//   0= Rising edge of VVS is active edge
+//      For ITU-R BT.656 data, leading edge of
+//      vertical sync is the active edge.
+//   1= Falling edge of VVS is active edge
+//      For ITU-R BT.656 data, trailing edge
+//      of vertical sync is the active edge.
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SHIFT                 _MK_SHIFT_CONST(24)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_FIELD                 (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_RANGE                 24:24
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_RISING                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_VVS_IN_EDGE_FALLING                       _MK_ENUM_CONST(1)
+
+// Horizontal and Vertical Sync Format  (effective if VIDEO_SOURCE is VIP)
+//   00= horizontal sync comes from VHS pin
+//       and vertical sync comes from VVS pin
+//       consistent with standard YUV422 data
+//       format.
+//       In this case, VHS_Input_Control and
+//       VVS_Input_Control must be enabled.
+//   01= horizontal and vertical syncs are
+//       decoded from the received video data
+//       bytes as specified in ITU-R BT.656
+//       (CCIR656) standard.
+//   10= horizontal and vertical syncs are
+//       generated internally and they are
+//       output on VHS and VVS pins if VHS and
+//       VVS are in output mode.
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SHIFT                 _MK_SHIFT_CONST(25)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_FIELD                 (_MK_MASK_CONST(0x3) << VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_RANGE                 26:25
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_WOFFSET                       0x0
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_YUV422                        _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_ITU656                        _MK_ENUM_CONST(1)
+#define VI_VI_INPUT_CONTROL_0_SYNC_FORMAT_INTHVS                        _MK_ENUM_CONST(2)
+
+// Interlaced video Field Detection  (effective if VIDEO_SOURCE is VIP)
+//   0= Disabled (top field only)
+//   1= Enabled
+//      When H/V syncs are decoded per ITU-R
+//      BT.656 standard, odd/even field is
+//      detected from the control bytes.
+//      When H/V syncs come from VHS/VVS pins
+//      (YUV422), odd/even field is detected
+//      from the position of VVS active edge
+//      with respect to VHS active pulse.
+//      This bit should be disabled for non-
+//      interlaced source or when H/V syncs
+//      are generated internally.
+//  If VIDEO_SOURCE is HOST, field information
+//  is always specified by host.
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SHIFT                        _MK_SHIFT_CONST(27)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_RANGE                        27:27
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_WOFFSET                      0x0
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_DETECT_ENABLED                      _MK_ENUM_CONST(1)
+
+// Odd/Even Field type  (effective for interlaced video source)
+//   0= Top field is odd field
+//   1= Top field is even field
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SHIFT                  _MK_SHIFT_CONST(28)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_RANGE                  28:28
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_WOFFSET                        0x0
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_TOPODD                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_FIELD_TYPE_TOPEVEN                        _MK_ENUM_CONST(1)
+
+// Horizontal Counter   0= Enabled
+//   1= Disabled (reset to 0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_SHIFT                   _MK_SHIFT_CONST(29)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_H_COUNTER_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_RANGE                   29:29
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_ENABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_H_COUNTER_DISABLED                        _MK_ENUM_CONST(1)
+
+// Vertical Counter   0= Enabled
+//   1= Disabled (reset to 0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_SHIFT                   _MK_SHIFT_CONST(30)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_INPUT_CONTROL_0_V_COUNTER_SHIFT)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_RANGE                   30:30
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_WOFFSET                 0x0
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_ENABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_INPUT_CONTROL_0_V_COUNTER_DISABLED                        _MK_ENUM_CONST(1)
+
+
+// Register VI_VI_CORE_CONTROL_0  // VI Core Control and Output to EPP/ISP
+#define VI_VI_CORE_CONTROL_0                    _MK_ADDR_CONST(0x23)
+#define VI_VI_CORE_CONTROL_0_SECURE                     0x0
+#define VI_VI_CORE_CONTROL_0_WORD_COUNT                         0x1
+#define VI_VI_CORE_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x7ff0f7f)
+#define VI_VI_CORE_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x7ef0f7f)
+#define VI_VI_CORE_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x7ff0f7f)
+// Output to ISP  Enable data output to ISP
+//   00= Output to ISP is disabled
+//   01= Parallel Video Input Port data
+//   10= Host I/F data
+//   11= reserved
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_FIELD                        (_MK_MASK_CONST(0x3) << VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SHIFT)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_RANGE                        1:0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_VIP                  _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_HOST                 _MK_ENUM_CONST(2)
+
+// Output to EPP enable  VI can output a YUV pixel stream to
+//  Encoder Pre-Processor (EPP) module
+//   000= Output to EPP is disabled
+//   001= YUV444 stream after down-scaling
+//   010= YUV444 stream before down-scaling
+//        WARNING: FOR YUV444PRE, only the selects
+//        in INPUT_TO_CORE are supported.  Selects from
+//        INPUT_TO_CORE_EXT are not supported since they
+//        are duplicated in the CSI* selections of this field.
+//   011= YUV444 stream from ISP, no LPF or down-scaling
+//   100= RGB565,RGB444,RGB888 from VIP, no LPF or down-scaling
+//   101= RGB565,RGB888 from Host
+//   110= CSI_PPA
+//   111= CSI_PPB
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SHIFT                        _MK_SHIFT_CONST(2)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_FIELD                        (_MK_MASK_CONST(0x7) << VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SHIFT)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_RANGE                        4:2
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_YUV444POST                   _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_YUV444PRE                    _MK_ENUM_CONST(2)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_YUV444ISP                    _MK_ENUM_CONST(3)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_RGB                  _MK_ENUM_CONST(4)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_HOST_RGB                     _MK_ENUM_CONST(5)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_CSI_PPA                      _MK_ENUM_CONST(6)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_EPP_CSI_PPB                      _MK_ENUM_CONST(7)
+
+// Downsample from YUV444 to YUV422   00 = Cosited, take even UV's for each two Y's.
+//   01 = Cosited, take odd UV's for each two Y's. (Not implemented)
+//   10 = Non Cosited, take even U and odd V, use for Bayer passthru
+//   11 = Averaged, average the odd and even UVs. (Not Implemented)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SHIFT                       _MK_SHIFT_CONST(5)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_FIELD                       (_MK_MASK_CONST(0x3) << VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SHIFT)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_RANGE                       6:5
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_WOFFSET                     0x0
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_DEFAULT_MASK                        _MK_MASK_CONST(0x3)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_COSITED_EVEN                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_COSITED_ODD                 _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_NONCOSITED                  _MK_ENUM_CONST(2)
+#define VI_VI_CORE_CONTROL_0_ISP_DOWNSAMPLE_AVERAGED                    _MK_ENUM_CONST(3)
+
+// Input to VI Core  Select between possible data input sources
+//   00= Parallel Video Input Port data
+//   01= Host I/F data
+//   10= ISP data, from 444 to 422 converter
+//   11= reserved
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_FIELD                        (_MK_MASK_CONST(0x3) << VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SHIFT)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_RANGE                        9:8
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_VIP                  _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_HOST                 _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_ISP                  _MK_ENUM_CONST(2)
+
+// Planar Conversion Module Input select   0= YUV422 after down-scaling, POST core
+//   1= YUV422 before down-scaling, PRE core
+//
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SHIFT                        _MK_SHIFT_CONST(10)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SHIFT)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_RANGE                        10:10
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_YUV422POST                   _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_PLANAR_CONV_INPUT_SEL_YUV422PRE                    _MK_ENUM_CONST(1)
+
+// Color Space Conversion Input select   0= YUV422 after down-scaling, POST core
+//   1= YUV422 before down-scaling, PRE core
+// 15:12 reserved
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SHIFT                        _MK_SHIFT_CONST(11)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SHIFT)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_RANGE                        11:11
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_YUV422POST                   _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_CSC_INPUT_SEL_YUV422PRE                    _MK_ENUM_CONST(1)
+
+// Horizontal Averaging   0= disabled, H_DOWNSCALING can be used
+//      to enable horizontal downscaling
+//   1= enabled, H_DOWNSCALING is ignored
+//      and horizontal downscaling is
+//      controlled by H_AVG_FACTOR
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_H_AVERAGING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_RANGE                  16:16
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_WOFFSET                        0x0
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_H_AVERAGING_ENABLED                        _MK_ENUM_CONST(1)
+
+// Horizontal Down-scaling  (effective if H_AVERAGING is DISABLED)
+//   0= disabled
+//   1= enabled and controlled by H_DOWN_M
+//      and H_DOWN_N parameters
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SHIFT                        _MK_SHIFT_CONST(17)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_RANGE                        17:17
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_H_DOWNSCALING_ENABLED                      _MK_ENUM_CONST(1)
+
+// Vertical Averaging   0= disabled, V_DOWNSCALING can be used
+//      to enable vertical downscaling
+//   1= enabled, V_DOWNSCALING is ignored
+//      and vertical downscaling is
+//      controlled by V_AVG_FACTOR
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_SHIFT                  _MK_SHIFT_CONST(18)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_V_AVERAGING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_RANGE                  18:18
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_WOFFSET                        0x0
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_V_AVERAGING_ENABLED                        _MK_ENUM_CONST(1)
+
+// Vertical Down-scaling  (effective if V_AVERAGING is DISABLED)
+//   0= disabled
+//   1= enabled and controlled by V_DOWN_M
+//      and V_DOWN_N parameters
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SHIFT                        _MK_SHIFT_CONST(19)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_FIELD                        (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SHIFT)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_RANGE                        19:19
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_WOFFSET                      0x0
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_DISABLED                     _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_V_DOWNSCALING_ENABLED                      _MK_ENUM_CONST(1)
+
+// ISP Host data stall capability is enabled by default  Use this bit to disable the host data stall capability
+//   0= disabled - default allows for VI to turn off
+//                 the ISP clock to stall the Host.
+//   1= enabled - to turn off the VI's ability to stall the Host
+//                when data from ISP comes from Host.
+//
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SHIFT                   _MK_SHIFT_CONST(20)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_FIELD                   (_MK_MASK_CONST(0x1) << VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SHIFT)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_RANGE                   20:20
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_WOFFSET                 0x0
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_ISP_HOST_STALL_OFF_ENABLED                 _MK_ENUM_CONST(1)
+
+// Select a data source output to ISP (extension field).
+//   000= Source is selected with OUTPUT_TO_ISP field (backward compatible)
+//   001= CSI Pixel Parser A
+//   010= CSI Pixel Parser B
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SHIFT                    _MK_SHIFT_CONST(21)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_FIELD                    (_MK_MASK_CONST(0x7) << VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SHIFT)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_RANGE                    23:21
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_WOFFSET                  0x0
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_USE_OUTPUT_TO_ISP                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_CSI_PPA                  _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_OUTPUT_TO_ISP_EXT_CSI_PPB                  _MK_ENUM_CONST(2)
+
+// Select a data source input to core (extension field).
+//   000= Source is selected with INPUT_TO_CORE field (backward compatible)
+//   001= CSI_PPA data in YUV444NP format
+//   010= CSI_PPA data in YUV422NP format
+//   011= CSI_PPB data in YUV444NP format
+//   100= CSI_PPB data in YUV422NP format
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SHIFT                    _MK_SHIFT_CONST(24)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_FIELD                    (_MK_MASK_CONST(0x7) << VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SHIFT)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_RANGE                    26:24
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_WOFFSET                  0x0
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_USE_INPUT_TO_CORE                        _MK_ENUM_CONST(0)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPA_YUV444                   _MK_ENUM_CONST(1)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPA_YUV422                   _MK_ENUM_CONST(2)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPB_YUV444                   _MK_ENUM_CONST(3)
+#define VI_VI_CORE_CONTROL_0_INPUT_TO_CORE_EXT_CSI_PPB_YUV422                   _MK_ENUM_CONST(4)
+
+
+// Register VI_VI_FIRST_OUTPUT_CONTROL_0  // VI Output Control of YUV/RGB and YUV420P
+#define VI_VI_FIRST_OUTPUT_CONTROL_0                    _MK_ADDR_CONST(0x24)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_SECURE                     0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_WORD_COUNT                         0x1
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x3f0107)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x3f0107)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x3f0107)
+// Output data Format  Take from the CSC Unit:
+//   000= 16-bit RGB (B5G6R5)
+//   001= 16-bit RGB (B5G6R5) Dithered
+//        (This is currently NOT implemented)
+//   010= 24-bit RGB (B8G8R8)
+//  Take from the YUV422 Core output path:
+//      (Same thing as using YUV422PRE and YUV_SOURCE==CORE_OUTPUT)
+//   011= YUV422 non-planar (U8Y8V8Y8) after down-scaling, POST
+//  Take from the YUV422 paths: (see YUV_SOURCE field)
+//   100= YUV422 non-planar (U8Y8V8Y8) before down-scaling, PRE
+//   101= YUV422 Planar
+//   110= YUV420 Planar
+//   111= YUV420 Planar with Averaging
+//        (UV is averaged for each line pair)
+// 7:3 reserved
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_FIELD                        (_MK_MASK_CONST(0x7) << VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RANGE                        2:0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_WOFFSET                      0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RGB16                        _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RGB16D                       _MK_ENUM_CONST(1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_RGB24                        _MK_ENUM_CONST(2)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV422POST                   _MK_ENUM_CONST(3)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV422PRE                    _MK_ENUM_CONST(4)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV422P                      _MK_ENUM_CONST(5)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV420P                      _MK_ENUM_CONST(6)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_FORMAT_YUV420PA                     _MK_ENUM_CONST(7)
+
+// For Planar Output Only, enabling this register  duplicates the last pixel of each line when
+//  the output width is set to an odd number of pixels.
+//  Used when JPEGE/MPEGE which requires valid data filled
+//  to the word(16-bit) boundary.
+//  The Buffer Horizontal Size (Line Stride) must be
+//  set to accomodate the extra pixel.
+//  Example: Disabled - y0,y1,y2,y3,y4
+//           Enabled - y0,y1,y2,y3,y4,y4
+// 15:9 reserved
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_RANGE                       8:8
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_WOFFSET                     0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_LAST_PIXEL_DUPLICATION_ENABLED                     _MK_ENUM_CONST(1)
+
+// Output Byte Swap  (effective if input source is host)
+//   0= disabled
+//   1= enabled
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_RANGE                     16:16
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_WOFFSET                   0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_OUTPUT_BYTE_SWAP_ENABLED                   _MK_ENUM_CONST(1)
+
+// YUV Output Format This is applicable when output format is
+// non-planar YUV422.
+//   00= UYVY => Y1_V0_Y1_U0 MSB to LSB 32bit mapping
+//   01= VYUY => Y1_U0_Y1_V0
+//   10= YUYV => V0_Y1_U0_Y0
+//   11= YVYU => U0_Y1_V0_Y0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SHIFT                    _MK_SHIFT_CONST(17)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_RANGE                    18:17
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_WOFFSET                  0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_UYVY                     _MK_ENUM_CONST(0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_VYUY                     _MK_ENUM_CONST(1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_YUYV                     _MK_ENUM_CONST(2)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_YUV_OUTPUT_FORMAT_YVYU                     _MK_ENUM_CONST(3)
+
+//  H-direction in internal memory
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SHIFT                  _MK_SHIFT_CONST(19)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_RANGE                  19:19
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_WOFFSET                        0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_H_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  V-direction in internal memory
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SHIFT                  _MK_SHIFT_CONST(20)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_RANGE                  20:20
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_WOFFSET                        0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_V_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  XY-Swap in internal memory
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SHIFT                      _MK_SHIFT_CONST(21)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SHIFT)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_RANGE                      21:21
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_WOFFSET                    0x0
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_FIRST_OUTPUT_CONTROL_0_XY_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_SECOND_OUTPUT_CONTROL_0  // VI Second Output Control of YUV422NP and RGB
+#define VI_VI_SECOND_OUTPUT_CONTROL_0                   _MK_ADDR_CONST(0x25)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECURE                    0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_WORD_COUNT                        0x1
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x3f000f)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x3f000f)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x3f000f)
+// Secondary Output to MC  Use case: when VI needs to send decimated preview data
+//  and at the same time send non-decimated data
+//  to the memory for StretchBLT, meanwhile the StretchBLT
+//  is sending EPP stretched data to be encoded.
+//  Only YUV422, RGB888, RGB565 is supported
+//
+//  Take from the CSC Unit
+//  0000= 16-bit RGB (B5G6R5), all RGB data can be pre or
+//        post decimated depending on mux select programming
+//        on the input to the Color Space Converter
+//  0001= 16-bit RGB (B5G6R5) Dithered
+//        (This is currently NOT implemented)
+//  0010= 24-bit RGB (B8G8R8)
+//  Take from the YUV422 Core output path:
+//      (Same thing as using YUV422PRE and YUV_SOURCE==CORE_OUTPUT)
+//  0011= YUV422 stream after down-scaling, POST
+//  Take from the YUV422 paths: (see YUV_SOURCE field)
+//  0100= YUV422 stream before down-scaling, PRE
+//  Take from the WriteBuffer interface logic, which is used for JPEG Stream
+//  0101= JPEG Stream (Pattern A,B,C)
+//  0110= VIP Bayer     direct to memory as a 16-bit value {6'b0, VIP_pad[9:0]}
+//  0111= CSI_PPA Bayer direct to memory as a 16-bit value {6'b0, CSI_SVD[15:6]}
+//  1000= CSI_PPB Bayer direct to memory as a 16-bit value {6'b0, CSI_SVD[15:6]}
+//  VIP_BAYER_DIRECT: Bayer data is written unmodified to memory
+//  as a 16-bit quantity.  Bit0 of incoming data is placed in
+//  bit0 of the 16-bit memory location. Upper bits are padded with 0.
+// 15:4 reserved
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_FIELD                        (_MK_MASK_CONST(0xf) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RANGE                        3:0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_WOFFSET                      0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RGB16                        _MK_ENUM_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RGB16D                       _MK_ENUM_CONST(1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_RGB24                        _MK_ENUM_CONST(2)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_YUV422POST                   _MK_ENUM_CONST(3)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_YUV422PRE                    _MK_ENUM_CONST(4)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_JPEG_STREAM                  _MK_ENUM_CONST(5)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_VIP_BAYER                    _MK_ENUM_CONST(6)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_CSI_PPA_BAYER                        _MK_ENUM_CONST(7)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_CSI_PPB_BAYER                        _MK_ENUM_CONST(8)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_FORMAT_VIP_BAYER_DIRECT                     _MK_ENUM_CONST(9)
+
+// Output Byte Swap  (effective if input source is host)
+//   0= disabled
+//   1= enabled
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_RANGE                     16:16
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_WOFFSET                   0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_OUTPUT_BYTE_SWAP_ENABLED                   _MK_ENUM_CONST(1)
+
+// YUV Second Output Format This is applicable when output format is
+// non-planar YUV422.
+//   00= UYVY => Y1_V0_Y1_U0 MSB to LSB 32bit mapping
+//   01= VYUY => Y1_U0_Y1_V0
+//   10= YUYV => V0_Y1_U0_Y0
+//   11= YVYU => U0_Y1_V0_Y0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SHIFT                    _MK_SHIFT_CONST(17)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_RANGE                    18:17
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_WOFFSET                  0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_UYVY                     _MK_ENUM_CONST(0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_VYUY                     _MK_ENUM_CONST(1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_YUYV                     _MK_ENUM_CONST(2)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_YUV_SECOND_OUTPUT_FORMAT_YVYU                     _MK_ENUM_CONST(3)
+
+//  Second output's H-direction in internal memory
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SHIFT                  _MK_SHIFT_CONST(19)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_RANGE                  19:19
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_WOFFSET                        0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_H_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Second output's V-direction in internal memory
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SHIFT                  _MK_SHIFT_CONST(20)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_RANGE                  20:20
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_WOFFSET                        0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_V_DIRECTION_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+//  Second output's XY-Swap in internal memory
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SHIFT                      _MK_SHIFT_CONST(21)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_FIELD                      (_MK_MASK_CONST(0x1) << VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SHIFT)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_RANGE                      21:21
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_WOFFSET                    0x0
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_SECOND_OUTPUT_CONTROL_0_SECOND_XY_SWAP_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Input Frame Width and Height give the total input data dimensions.  The VI input stage will cull/clip
+// pixels outside the Active Region (see register VI_HOST_H_ACTIVE & VI_HOST_V_ACTIVE).  The amount of data
+// per frame is expected to be INPUT_WIDTH * INPUT_HEIGHT * the bytes per pixel (determined from the
+// INPUT_HOST_FORMAT). For Planar, the BPP is 1 for the Y fifo, 1/2 for U and V. For non planar it is 2.
+// The Bayer data is treated as 1 byte per pixel, so if it is more, then the input width and the H_ACTIVE
+// should be scaled accordingly, so that internally generated hsync and vsyncs for ISP are correct.
+// For Bayer input, it is important to insert blanking data for horizontal and vertical, allowing ISP to do
+// side band calculations.
+
+// Register VI_HOST_INPUT_FRAME_SIZE_0  // Host Input Frame Width
+#define VI_HOST_INPUT_FRAME_SIZE_0                      _MK_ADDR_CONST(0x26)
+#define VI_HOST_INPUT_FRAME_SIZE_0_SECURE                       0x0
+#define VI_HOST_INPUT_FRAME_SIZE_0_WORD_COUNT                   0x1
+#define VI_HOST_INPUT_FRAME_SIZE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_HOST_INPUT_FRAME_SIZE_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Specifies in terms of pixels the width of
+// the input data coming from host.
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SHIFT)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_RANGE                      12:0
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_WOFFSET                    0x0
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_WIDTH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Host Input Frame Height
+// Specifies in terms of lines the height of
+// the input data coming from host.
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SHIFT)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_RANGE                     28:16
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_WOFFSET                   0x0
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_INPUT_FRAME_SIZE_0_INPUT_FRAME_HEIGHT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// This register defines the horizontal active area of the input video source with respect to
+// the internally generated horizontal sync.  (This is for data coming in from host.)
+
+// Register VI_HOST_H_ACTIVE_0  // VI Horizontal Active
+#define VI_HOST_H_ACTIVE_0                      _MK_ADDR_CONST(0x27)
+#define VI_HOST_H_ACTIVE_0_SECURE                       0x0
+#define VI_HOST_H_ACTIVE_0_WORD_COUNT                   0x1
+#define VI_HOST_H_ACTIVE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_HOST_H_ACTIVE_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  pixels to be discarded until the first
+//  active pixel. If programmed to 0, the
+//  first active pixel is the first pixel popped
+//  from the Host YUV FIFO.
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_FIELD                    (_MK_MASK_CONST(0x1fff) << VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SHIFT)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_RANGE                    12:0
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_WOFFSET                  0x0
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  H_ACTIVE_START + H_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_H_IN (or 8192) This parameter
+//  should be programmed with an even number
+//  (bit 16 is ignored internally).
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SHIFT)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_RANGE                   28:16
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_WOFFSET                 0x0
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_H_ACTIVE_0_HOST_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// This register defines the vertical active area of the input video source with respect to
+// the internally generated vertical sync.  (This is for data coming in from host.)
+
+// Register VI_HOST_V_ACTIVE_0  // Vertical Active
+#define VI_HOST_V_ACTIVE_0                      _MK_ADDR_CONST(0x28)
+#define VI_HOST_V_ACTIVE_0_SECURE                       0x0
+#define VI_HOST_V_ACTIVE_0_WORD_COUNT                   0x1
+#define VI_HOST_V_ACTIVE_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_HOST_V_ACTIVE_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_FIELD                    (_MK_MASK_CONST(0x1fff) << VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SHIFT)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_RANGE                    12:0
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_WOFFSET                  0x0
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_START_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  V_ACTIVE_START + V_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_V_IN (or 8192).
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SHIFT)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_RANGE                   28:16
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_WOFFSET                 0x0
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_V_ACTIVE_0_HOST_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// This register defines the horizontal active area of the input video source with respect to
+//  horizontal sync. (This is for VIP data.)
+
+// Register VI_VIP_H_ACTIVE_0  // VI Horizontal Active
+#define VI_VIP_H_ACTIVE_0                       _MK_ADDR_CONST(0x29)
+#define VI_VIP_H_ACTIVE_0_SECURE                        0x0
+#define VI_VIP_H_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_VIP_H_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff1fff)
+#define VI_VIP_H_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  clock active edges from horizontal
+//  sync active edge to the first horizontal
+//  active pixel. If programmed to 0, the
+//  first active line starts after the first
+//  active clock edge following the horizontal
+//  sync active edge.
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SHIFT)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_RANGE                      12:0
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_WOFFSET                    0x0
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  Bug #178631
+//  The value is the END of the active region,
+//  so PERIOD-START = active area
+//  This parameter should be programmed
+//  with an even number
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SHIFT)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VIP_H_ACTIVE_0_VIP_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// This register defines the vertical active area of the input video source with respect to
+//  vertical sync. (This is for VIP data.)
+
+// Register VI_VIP_V_ACTIVE_0  // Vertical Active
+#define VI_VIP_V_ACTIVE_0                       _MK_ADDR_CONST(0x2a)
+#define VI_VIP_V_ACTIVE_0_SECURE                        0x0
+#define VI_VIP_V_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_VIP_V_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff1fff)
+#define VI_VIP_V_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SHIFT)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_RANGE                      12:0
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_WOFFSET                    0x0
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  Bug #178631
+//  The value is the END of the active region,
+//  so PERIOD-START = active area
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SHIFT)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VIP_V_ACTIVE_0_VIP_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_PEER_CONTROL_0  // VI Peer to Peer Control
+// For all fields:
+//   00= Disabled
+//   01= First memory
+//   10= Second memory
+//   11= not defined
+#define VI_VI_PEER_CONTROL_0                    _MK_ADDR_CONST(0x2b)
+#define VI_VI_PEER_CONTROL_0_SECURE                     0x0
+#define VI_VI_PEER_CONTROL_0_WORD_COUNT                         0x1
+#define VI_VI_PEER_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0xff)
+#define VI_VI_PEER_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define VI_VI_PEER_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
+// VI to Display Control Bus enable  VI will send a valid buffer signal
+//  along with Y,U,V buffer addresses
+//  and Frame Start and Frame End
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_FIELD                      (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_RANGE                      1:0
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_WOFFSET                    0x0
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_FIRST                      _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_CONTROL_SECOND                     _MK_ENUM_CONST(2)
+
+// VI to JPEGE & MPEGE Control Bus enable  VI will send a valid buffer signal
+//  along with buffer index
+//  and Frame Start and Frame End
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_FIELD                      (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_RANGE                      3:2
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_WOFFSET                    0x0
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_FIRST                      _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_ENCODER_CONTROL_SECOND                     _MK_ENUM_CONST(2)
+
+// VI to StretchBLT Control Bus enable  VI will send a valid buffer signal
+//  along with buffer index
+//  and Frame Start and Frame End
+//  The VI to SB control bus is separate from
+//  the VI to JPEGE/MPEGE bus.  This control
+//  bus is controlled by the "2nd Output to
+//  MC" write client interface.
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SHIFT                   _MK_SHIFT_CONST(4)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_FIELD                   (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_SB_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_RANGE                   5:4
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_WOFFSET                 0x0
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_FIRST                   _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_SB_CONTROL_SECOND                  _MK_ENUM_CONST(2)
+
+// VI to Display B Control Bus enable  VI will send a valid buffer signal
+//  along with Y,U,V buffer addresses
+//  and Frame Start and Frame End
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SHIFT                    _MK_SHIFT_CONST(6)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SHIFT)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_RANGE                    7:6
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_WOFFSET                  0x0
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_FIRST                    _MK_ENUM_CONST(1)
+#define VI_VI_PEER_CONTROL_0_DISPLAY_B_CONTROL_SECOND                   _MK_ENUM_CONST(2)
+
+
+// Register VI_VI_DMA_SELECT_0  // Host DMA select
+#define VI_VI_DMA_SELECT_0                      _MK_ADDR_CONST(0x2c)
+#define VI_VI_DMA_SELECT_0_SECURE                       0x0
+#define VI_VI_DMA_SELECT_0_WORD_COUNT                   0x1
+#define VI_VI_DMA_SELECT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_RESET_MASK                   _MK_MASK_CONST(0x3)
+#define VI_VI_DMA_SELECT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_READ_MASK                    _MK_MASK_CONST(0x3)
+#define VI_VI_DMA_SELECT_0_WRITE_MASK                   _MK_MASK_CONST(0x3)
+// Host DMA Request enable at end of block  Request to host DMA can be enabled every
+//  time a block of video input data is
+//  written to memory.
+//   00= Disabled
+//   01= Write Buffer DMA for RAW data stream
+//   10= First memory
+//   11= Second memory
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_FIELD                    (_MK_MASK_CONST(0x3) << VI_VI_DMA_SELECT_0_DMA_REQUEST_SHIFT)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_RANGE                    1:0
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_WOFFSET                  0x0
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_DEFAULT_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_STREAM                   _MK_ENUM_CONST(1)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_FIRST                    _MK_ENUM_CONST(2)
+#define VI_VI_DMA_SELECT_0_DMA_REQUEST_SECOND                   _MK_ENUM_CONST(3)
+
+
+// Register VI_HOST_DMA_WRITE_BUFFER_0  // Host DMA Write Buffer Configuration Registers
+#define VI_HOST_DMA_WRITE_BUFFER_0                      _MK_ADDR_CONST(0x2d)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SECURE                       0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_WORD_COUNT                   0x1
+#define VI_HOST_DMA_WRITE_BUFFER_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_RESET_MASK                   _MK_MASK_CONST(0xe000000)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_READ_MASK                    _MK_MASK_CONST(0xfffffff)
+#define VI_HOST_DMA_WRITE_BUFFER_0_WRITE_MASK                   _MK_MASK_CONST(0xfffffff)
+// Buffer Size
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_FIELD                    (_MK_MASK_CONST(0xffff) << VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_RANGE                    15:0
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_WOFFSET                  0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_SIZE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Buffer Number
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_FIELD                  (_MK_MASK_CONST(0x1ff) << VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_RANGE                  24:16
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_WOFFSET                        0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_BUFFER_NUMBER_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// DMA Enable
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SHIFT                     _MK_SHIFT_CONST(25)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_FIELD                     (_MK_MASK_CONST(0x1) << VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_RANGE                     25:25
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_WOFFSET                   0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_DMA_ENABLE_ENABLED                   _MK_ENUM_CONST(1)
+
+// Data source selection 00= VIP     (backward compatible)
+// 01= CSI_PPA
+// 10= CSI_PPB
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SHIFT                     _MK_SHIFT_CONST(26)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_FIELD                     (_MK_MASK_CONST(0x3) << VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_RANGE                     27:26
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_WOFFSET                   0x0
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_VIP                       _MK_ENUM_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_CSI_PPA                   _MK_ENUM_CONST(1)
+#define VI_HOST_DMA_WRITE_BUFFER_0_SOURCE_SEL_CSI_PPB                   _MK_ENUM_CONST(2)
+
+
+// Register VI_HOST_DMA_BASE_ADDRESS_0  // Host DMA Write Buffer Configuration Registers
+#define VI_HOST_DMA_BASE_ADDRESS_0                      _MK_ADDR_CONST(0x2e)
+#define VI_HOST_DMA_BASE_ADDRESS_0_SECURE                       0x0
+#define VI_HOST_DMA_BASE_ADDRESS_0_WORD_COUNT                   0x1
+#define VI_HOST_DMA_BASE_ADDRESS_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_READ_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_HOST_DMA_BASE_ADDRESS_0_WRITE_MASK                   _MK_MASK_CONST(0xffffffff)
+// Base Address
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_FIELD                  (_MK_MASK_CONST(0xffffffff) << VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SHIFT)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_RANGE                  31:0
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_WOFFSET                        0x0
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_BASE_ADDRESS_0_DMA_BASE_ADDR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_DMA_WRITE_BUFFER_STATUS_0  // Host DMA Write Buffer Status Register
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0                       _MK_ADDR_CONST(0x2f)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_SECURE                        0x0
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WORD_COUNT                    0x1
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x7ffffff)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Read Only
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_FIELD                       (_MK_MASK_CONST(0x7ffffff) << VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SHIFT)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_RANGE                       26:0
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_WOFFSET                     0x0
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_BUFFER_STATUS_0_WB_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0  // Host DMA Write Buffer Pending Buffer Count
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0                       _MK_ADDR_CONST(0x30)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_SECURE                        0x0
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_WORD_COUNT                    0x1
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_READ_MASK                     _MK_MASK_CONST(0x1ff)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// Read Only
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_FIELD                   (_MK_MASK_CONST(0x1ff) << VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SHIFT)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_RANGE                   8:0
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_WOFFSET                 0x0
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0_PEND_BUFCOUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// FIRST OUTPUT Registers
+// These registers are used to setup the first of two memory outputs for VI
+// Address Y, U, V; Frame size; Count; Size (line stride and block height); and Buffer Stride
+
+// Register VI_VB0_START_ADDRESS_FIRST_0  // Video Buffer O Start Address for First Output
+#define VI_VB0_START_ADDRESS_FIRST_0                    _MK_ADDR_CONST(0x31)
+#define VI_VB0_START_ADDRESS_FIRST_0_SECURE                     0x0
+#define VI_VB0_START_ADDRESS_FIRST_0_WORD_COUNT                         0x1
+#define VI_VB0_START_ADDRESS_FIRST_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_FIRST_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0 if
+//  output data format is RGB or YUV non-planar.
+//  This is byte address of video buffer 0
+//  Y-plane if output data format is YUV planar.
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_FIELD                  (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SHIFT)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_RANGE                  31:0
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_WOFFSET                        0x0
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_FIRST_0_VB0_START_ADDRESS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// BASE address is used in Tiling mode. BASE address always points to the left_upper cornor
+// of a surface. A surface can contain multiple buffers, in circular_buffer case.
+// Write to the BASE address register with cause corresponding internal buffer index set back
+// to zero.
+
+// Register VI_VB0_BASE_ADDRESS_FIRST_0  // Video Buffer O BASE Address for First Output
+#define VI_VB0_BASE_ADDRESS_FIRST_0                     _MK_ADDR_CONST(0x32)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_SECURE                      0x0
+#define VI_VB0_BASE_ADDRESS_FIRST_0_WORD_COUNT                  0x1
+#define VI_VB0_BASE_ADDRESS_FIRST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+//  This is the first byte address of video
+//  buffer 0.
+//  This is byte address of video buffer 0
+//  Y-plane if output data format is planar.
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_FIELD                    (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SHIFT)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_RANGE                    31:0
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_WOFFSET                  0x0
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_FIRST_0_VB0_BASE_ADDRESS_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_START_ADDRESS_U_0  // Video Buffer O Start Address U (linked to First Output)
+#define VI_VB0_START_ADDRESS_U_0                        _MK_ADDR_CONST(0x33)
+#define VI_VB0_START_ADDRESS_U_0_SECURE                         0x0
+#define VI_VB0_START_ADDRESS_U_0_WORD_COUNT                     0x1
+#define VI_VB0_START_ADDRESS_U_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_U_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0
+//  U-plane if output data format is YUV planar.
+//  output data format is YUV planar.
+//  Due to clock gating, the primary
+//  OUTPUT_TO_MEMORY must be enabled and the
+//  OUTPUT_FORMAT must be set to a planar format
+//  prior to writing this register
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SHIFT)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_RANGE                      31:0
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_WOFFSET                    0x0
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_U_0_VB0_START_ADDRESS_U_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BASE_ADDRESS_U_0  // Video Buffer O BASE Address U
+//(linked to First Output)
+#define VI_VB0_BASE_ADDRESS_U_0                 _MK_ADDR_CONST(0x34)
+#define VI_VB0_BASE_ADDRESS_U_0_SECURE                  0x0
+#define VI_VB0_BASE_ADDRESS_U_0_WORD_COUNT                      0x1
+#define VI_VB0_BASE_ADDRESS_U_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_U_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+//  This is the first byte address of video
+//  buffer 0 U-plane if output data format
+//  is planar.
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_FIELD                        (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SHIFT)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_RANGE                        31:0
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_WOFFSET                      0x0
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_U_0_VB0_BASE_ADDRESS_U_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_START_ADDRESS_V_0  // Video Buffer O Start Address V (linked to First Output)
+#define VI_VB0_START_ADDRESS_V_0                        _MK_ADDR_CONST(0x35)
+#define VI_VB0_START_ADDRESS_V_0_SECURE                         0x0
+#define VI_VB0_START_ADDRESS_V_0_WORD_COUNT                     0x1
+#define VI_VB0_START_ADDRESS_V_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_V_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0
+//  V-plane if output data format is YUV planar.
+//  output data format is YUV planar.
+//  Due to clock gating, the primary
+//  OUTPUT_TO_MEMORY must be enabled and the
+//  OUTPUT_FORMAT must be set to a planar format
+//  prior to writing this register
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SHIFT)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_RANGE                      31:0
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_WOFFSET                    0x0
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_V_0_VB0_START_ADDRESS_V_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BASE_ADDRESS_V_0  // Video Buffer O BASE Address V
+//(linked to First Output)
+#define VI_VB0_BASE_ADDRESS_V_0                 _MK_ADDR_CONST(0x36)
+#define VI_VB0_BASE_ADDRESS_V_0_SECURE                  0x0
+#define VI_VB0_BASE_ADDRESS_V_0_WORD_COUNT                      0x1
+#define VI_VB0_BASE_ADDRESS_V_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_V_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0
+//  V-plane if output data format is YUV planar.
+//  output data format is YUV planar.
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_FIELD                        (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SHIFT)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_RANGE                        31:0
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_WOFFSET                      0x0
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_V_0_VB0_BASE_ADDRESS_V_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_SCRATCH_ADDRESS_UV_0  // Video Buffer O Scratch Address UV (linked to First Output)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0                     _MK_ADDR_CONST(0x37)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_SECURE                      0x0
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_WORD_COUNT                  0x1
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_READ_MASK                   _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_WRITE_MASK                  _MK_MASK_CONST(0xffffffff)
+//  If OUTPUT_FORMAT is YUV420PA, this is used.
+//  This is byte address of video buffer 0
+//  UV intermediate data is saved here during the
+//  YUV422 to YUV420PA conversion.
+//  The size allocated needs to match the
+//  FIRST_FRAME_WIDTH register setting
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_FIELD                        (_MK_MASK_CONST(0xffffffff) << VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SHIFT)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_RANGE                        31:0
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_WOFFSET                      0x0
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SCRATCH_ADDRESS_UV_0_VB0_SCRATCH_ADDRESS_UV_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_FIRST_OUTPUT_FRAME_SIZE_0  // Width and height of first output frame
+// This is the size of the frame being written to memory.
+// Apply decimation or averaging to calculate the output frame
+// size.  Whether or not downscaling is used specify whatever the
+// size of the frame being written to memory.
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0                    _MK_ADDR_CONST(0x38)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_SECURE                     0x0
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_WORD_COUNT                         0x1
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_READ_MASK                  _MK_MASK_CONST(0x1fff1fff)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff1fff)
+// frame width in pixel which VI needs to process
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_FIELD                    (_MK_MASK_CONST(0x1fff) << VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SHIFT)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_RANGE                    12:0
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_WOFFSET                  0x0
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_WIDTH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// frame height in lines which VI needs to process
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SHIFT)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_RANGE                   28:16
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_WOFFSET                 0x0
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_FIRST_OUTPUT_FRAME_SIZE_0_FIRST_FRAME_HEIGHT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_COUNT_FIRST_0  // Video Buffer Set 0 Count for First Output
+#define VI_VB0_COUNT_FIRST_0                    _MK_ADDR_CONST(0x39)
+#define VI_VB0_COUNT_FIRST_0_SECURE                     0x0
+#define VI_VB0_COUNT_FIRST_0_WORD_COUNT                         0x1
+#define VI_VB0_COUNT_FIRST_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_READ_MASK                  _MK_MASK_CONST(0xff)
+#define VI_VB0_COUNT_FIRST_0_WRITE_MASK                         _MK_MASK_CONST(0xff)
+// Video Buffer Set 0 Count
+//  This specifies the number of buffers in
+//  video buffer set 0.
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_FIELD                  (_MK_MASK_CONST(0xff) << VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SHIFT)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_RANGE                  7:0
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_WOFFSET                        0x0
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_FIRST_0_VB0_COUNT_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_SIZE_FIRST_0  // Video Buffer Set 0 Size for First Output
+#define VI_VB0_SIZE_FIRST_0                     _MK_ADDR_CONST(0x3a)
+#define VI_VB0_SIZE_FIRST_0_SECURE                      0x0
+#define VI_VB0_SIZE_FIRST_0_WORD_COUNT                  0x1
+#define VI_VB0_SIZE_FIRST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_READ_MASK                   _MK_MASK_CONST(0x1fff1fff)
+#define VI_VB0_SIZE_FIRST_0_WRITE_MASK                  _MK_MASK_CONST(0x1fff1fff)
+// Video Buffer Set 0 Horizontal Size
+//  This parameter specifies the line stride
+//  (in pixels) for lines in the video buffer
+//  set 0.
+//  For YUV non-planar format, this parameter
+//  must be programmed as multiple of 2 pixels
+//  (bit 0 is ignored).
+//  For YUV planar format, this parameter
+//  must be programmed as multiple of 8 pixels
+//  (bits 2-0 are ignored) and it specifies the
+//  luma line stride or twice the chroma line
+//  stride.
+//  This value will be divided by 2 for chroma
+//  buffers for YUV422 and YUV420 planar formats
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SHIFT)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_RANGE                  12:0
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_WOFFSET                        0x0
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_H_SIZE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Video Buffer Set 0 Vertical Size
+//  This specifies the number of lines in each
+//  buffer in video buffer set 0.
+//  This value will be divided by 2 for chroma
+//  buffers for YUV420 planar formats
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SHIFT)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_RANGE                  28:16
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_WOFFSET                        0x0
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_FIRST_0_VB0_V_SIZE_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BUFFER_STRIDE_FIRST_0  // Video Buffer Set 0 Buffer Stride
+#define VI_VB0_BUFFER_STRIDE_FIRST_0                    _MK_ADDR_CONST(0x3b)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_SECURE                     0x0
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_WORD_COUNT                         0x1
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+// Video Buffer Set 0 Luma Buffer Stride
+//  This is luma buffer stride (in bytes)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_FIELD                  (_MK_MASK_CONST(0x3fffffff) << VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SHIFT)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_RANGE                  29:0
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_WOFFSET                        0x0
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_L_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Video Buffer Set 0 Chroma Buffer Stride   00= Equal to Luma Buffer Stride
+//   01= Equal to Luma Buffer Stride divided by 2
+//       in this case Luma Buffer Stride should
+//       be multiple of 2 bytes.
+//   10= Equal to Luma Buffer Stride divided by 4
+//       in this case Luma Buffer Stride should
+//       be multiple of 4 bytes.
+//   1x= Reserved
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SHIFT                  _MK_SHIFT_CONST(30)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_FIELD                  (_MK_MASK_CONST(0x3) << VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SHIFT)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_RANGE                  31:30
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_WOFFSET                        0x0
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_CBS1X                  _MK_ENUM_CONST(0)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_CBS2X                  _MK_ENUM_CONST(1)
+#define VI_VB0_BUFFER_STRIDE_FIRST_0_VB0_BUFFER_STRIDE_C_CBS4X                  _MK_ENUM_CONST(2)
+
+// SECOND OUTPUT Registers
+// These registers are used to setup the second of two memory outputs for VI
+// Address; Frame size; Count; Size (line stride and block height); and Buffer Stride
+
+// Register VI_VB0_START_ADDRESS_SECOND_0  // Video Buffer O Start Address for Second Output
+#define VI_VB0_START_ADDRESS_SECOND_0                   _MK_ADDR_CONST(0x3c)
+#define VI_VB0_START_ADDRESS_SECOND_0_SECURE                    0x0
+#define VI_VB0_START_ADDRESS_SECOND_0_WORD_COUNT                        0x1
+#define VI_VB0_START_ADDRESS_SECOND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_START_ADDRESS_SECOND_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0 if
+//  output data format is RGB or YUV non-planar.
+//  This is byte address of video buffer 0
+//  This output data is read by the SB
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_FIELD                 (_MK_MASK_CONST(0xffffffff) << VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SHIFT)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_RANGE                 31:0
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_WOFFSET                       0x0
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_START_ADDRESS_SECOND_0_VB0_START_ADDRESS_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BASE_ADDRESS_SECOND_0  // Video Buffer O Base Address for Second Output
+#define VI_VB0_BASE_ADDRESS_SECOND_0                    _MK_ADDR_CONST(0x3d)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_SECURE                     0x0
+#define VI_VB0_BASE_ADDRESS_SECOND_0_WORD_COUNT                         0x1
+#define VI_VB0_BASE_ADDRESS_SECOND_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_READ_MASK                  _MK_MASK_CONST(0xffffffff)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_WRITE_MASK                         _MK_MASK_CONST(0xffffffff)
+//  This is byte address of video buffer 0 if
+//  output data format is RGB or non-planar.
+//  This is the first byte address of video
+//  buffer
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_FIELD                   (_MK_MASK_CONST(0xffffffff) << VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SHIFT)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_RANGE                   31:0
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_WOFFSET                 0x0
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_BASE_ADDRESS_SECOND_0_VB0_BASE_ADDRESS_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_SECOND_OUTPUT_FRAME_SIZE_0  // width and height of second output frame
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0                   _MK_ADDR_CONST(0x3e)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECURE                    0x0
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_WORD_COUNT                        0x1
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// frame width in pixel which VI needs to process
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SHIFT)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_RANGE                  12:0
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_WOFFSET                        0x0
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_WIDTH_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// frame height in lines which VI needs to process
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_FIELD                 (_MK_MASK_CONST(0x1fff) << VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SHIFT)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_RANGE                 28:16
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_WOFFSET                       0x0
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_SECOND_OUTPUT_FRAME_SIZE_0_SECOND_FRAME_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_COUNT_SECOND_0  // Video Buffer Set 0 Count for Second Output
+#define VI_VB0_COUNT_SECOND_0                   _MK_ADDR_CONST(0x3f)
+#define VI_VB0_COUNT_SECOND_0_SECURE                    0x0
+#define VI_VB0_COUNT_SECOND_0_WORD_COUNT                        0x1
+#define VI_VB0_COUNT_SECOND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define VI_VB0_COUNT_SECOND_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+//
+//  This specifies the number of buffers in
+//  video buffer set 0.
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_FIELD                 (_MK_MASK_CONST(0xff) << VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SHIFT)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_RANGE                 7:0
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_WOFFSET                       0x0
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_COUNT_SECOND_0_VB0_COUNT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_SIZE_SECOND_0  // Video Buffer Set 0 Size for Second Output
+#define VI_VB0_SIZE_SECOND_0                    _MK_ADDR_CONST(0x40)
+#define VI_VB0_SIZE_SECOND_0_SECURE                     0x0
+#define VI_VB0_SIZE_SECOND_0_WORD_COUNT                         0x1
+#define VI_VB0_SIZE_SECOND_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_READ_MASK                  _MK_MASK_CONST(0x1fff1fff)
+#define VI_VB0_SIZE_SECOND_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff1fff)
+// Video Buffer Set 0 Horizontal Size
+//  This parameter specifies the line stride
+//  (in pixels) for lines in the video buffer
+//  set 0.
+//  For YUV non-planar format, this parameter
+//  must be programmed as multiple of 2 pixels
+//  (bit 0 is ignored).
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_FIELD                 (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SHIFT)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_RANGE                 12:0
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_WOFFSET                       0x0
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_H_SIZE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Video Buffer Set 0 Vertical Size
+//  This specifies the number of lines in each
+//  buffer in video buffer set 0.
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_FIELD                 (_MK_MASK_CONST(0x1fff) << VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SHIFT)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_RANGE                 28:16
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_WOFFSET                       0x0
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_SIZE_SECOND_0_VB0_V_SIZE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VB0_BUFFER_STRIDE_SECOND_0  // Video Buffer Set 0 Buffer Stride for Second Output
+#define VI_VB0_BUFFER_STRIDE_SECOND_0                   _MK_ADDR_CONST(0x41)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_SECURE                    0x0
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_WORD_COUNT                        0x1
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_READ_MASK                         _MK_MASK_CONST(0x3fffffff)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_WRITE_MASK                        _MK_MASK_CONST(0x3fffffff)
+// Video Buffer Set 0 Luma Buffer Stride
+//  This is luma buffer stride (in bytes)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_FIELD                 (_MK_MASK_CONST(0x3fffffff) << VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SHIFT)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_RANGE                 29:0
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_WOFFSET                       0x0
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_BUFFER_STRIDE_SECOND_0_VB0_BUFFER_STRIDE_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This register controls horizontal low-pass filtering which can be enabled to improve quality
+// of the decimated image. The only valid programming values for this register are:
+//   0x02400240          No filtering
+//   0x0DBE092E          1-HPF^3
+//   0x01B60126          1-HPF^2
+//   0x05B70127          (1-HPF^2+LPF)/2
+//   0x06480248          LPF
+//   0x04910001          (LPF+LPF^2)/2
+//   0x00900000          LPF^2
+//   0x04980008          LPF^3
+//   0x07980308          LPF^2 * (0.5,0,0.5)
+//   0x07f80368          LPF * (0.5,0,0.5) * (2,-3,2)
+// The above list is ordered from the widest band-pass filter to the narrowest band-pass filter.
+#define VI_H_LPF_NO_FILTER      576
+#define VI_H_LPF_ONE_MINUS_HPF_CUBED_C  3518
+#define VI_H_LPF_ONE_MINUS_HPF_CUBED_L  2350
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_C        438
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_L        294
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_PLUS_LPF_C       1463
+#define VI_H_LPF_ONE_MINUS_HPF_SQUARED_PLUS_LPF_L       295
+#define VI_H_LPF_LPF_C  1608
+#define VI_H_LPF_LPF_L  584
+#define VI_H_LPF_LPF_PLUS_LPF_SQUARED_C 1169
+#define VI_H_LPF_LPF_PLUS_LPF_SQUARED_L 1
+#define VI_H_LPF_LPF_SQUARED_C  144
+#define VI_H_LPF_LPF_SQUARED_L  0
+#define VI_H_LPF_LPF_CUBED_C    1176
+#define VI_H_LPF_LPF_CUBED_L    8
+#define VI_H_LPF_LPF_SQUARED_SCALED_C   1944
+#define VI_H_LPF_LPF_SQUARED_SCALED_L   776
+#define VI_H_LPF_LPF_SQUARED_SCALED2_C  2040
+#define VI_H_LPF_LPF_SQUARED_SCALED2_L  872
+
+// Register VI_H_LPF_CONTROL_0  // VI Horizontal Low-Pass Filter (LPF) Control
+#define VI_H_LPF_CONTROL_0                      _MK_ADDR_CONST(0x42)
+#define VI_H_LPF_CONTROL_0_SECURE                       0x0
+#define VI_H_LPF_CONTROL_0_WORD_COUNT                   0x1
+#define VI_H_LPF_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0x2400240)
+#define VI_H_LPF_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0x1fff1fff)
+#define VI_H_LPF_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0x1fff1fff)
+#define VI_H_LPF_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0x1fff1fff)
+// Horizontal LPF Luminance filter
+//  This controls low pass filter for Y data.
+#define VI_H_LPF_CONTROL_0_H_LPF_L_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_H_LPF_CONTROL_0_H_LPF_L_SHIFT)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_RANGE                        12:0
+#define VI_H_LPF_CONTROL_0_H_LPF_L_WOFFSET                      0x0
+#define VI_H_LPF_CONTROL_0_H_LPF_L_DEFAULT                      _MK_MASK_CONST(0x240)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_DEFAULT_MASK                 _MK_MASK_CONST(0x1fff)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_H_LPF_L_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Horizontal LPF Chrominance filter
+//  This controls low pass filter for U V data.
+#define VI_H_LPF_CONTROL_0_H_LPF_C_SHIFT                        _MK_SHIFT_CONST(16)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_H_LPF_CONTROL_0_H_LPF_C_SHIFT)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_RANGE                        28:16
+#define VI_H_LPF_CONTROL_0_H_LPF_C_WOFFSET                      0x0
+#define VI_H_LPF_CONTROL_0_H_LPF_C_DEFAULT                      _MK_MASK_CONST(0x240)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_DEFAULT_MASK                 _MK_MASK_CONST(0x1fff)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_LPF_CONTROL_0_H_LPF_C_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Horizontal pixel processing starts with horizontal low-pass filtering.
+// Following horizontal low-pass filtering, horizontal down-scaling (decimation) can then be
+// performed with or without horizontal averaging.
+// If horizontal down-scaling (decimation) is performed without horizontal averaging, the
+// down-scaling factor is specified by input active period and output frame size.  Because the
+// VI has two input methods (VIP and HOST) and two memory outputs, there are mux selects to indicate
+// which registers to use in calculating the input and output frame sizes.
+// If horizontal down-scaling is performed with horizontal averaging, the down-scaling factors
+// are limited to few factors determined by H_AVG_CONTROL.  When enabling averaging PLEASE be careful
+// that the input and output ratios match the formula for the averaging decimation ratio exactly to the
+// pixel/line. The formula for each of the Averaging Decimation Ratio is as follows:
+//
+// Averaging Decimation Formalae
+// x = input size
+// y(x) = output size
+// 2-pixel averaging and 1/2 downscaling: y(x) = Floor(x/2)
+// 4-pixel averaging and 1/3 downscaling: y(x) = Floor((x-1)/3)
+// 4-pixel averaging and 1/4 downscaling: y(x) = Floor(x/4)
+// 8-pixel averaging and 1/7 downscaling: y(x) = Floor((x-1)/7)
+// 8-pixel averaging and 1/8 downscaling: y(x) = Floor(x/8)
+//
+// Horizontal Decimation Algorithm:
+// The Horizontal Decimator decides which pixels to drop by using a simple DDA algorithm.
+// The accumulator will continue to add the value of the output width (numerator) for each
+// pixel until the sum is equal or greater than the input width (denominator).  When the sum
+// is greater or equal to the input width (denominator), the hardware will flag that pixel as
+// a pixel to be written out to memory.  At the same time, the input width (denominator) will
+// be subtracted from the sum and the difference will be loaded back into the accumulator for
+// the next line.  By default the accumulator is initialized with 0's upon reset.  However the
+// user can set the H_DEC_INIT_VAL to initialize the accumulator with a certain value from
+// 0 to the input width (denominator).  Any H_DEC_INIT_VAL that is greater or equal to the
+// difference of the input width (denominator) and the output width (numerator) will cause the
+// first pixel to be written out to memory.  This register shifts the phase of the decimation
+// pattern.
+
+// Register VI_H_DOWNSCALE_CONTROL_0  // VI Horizontal Down-scaling Control
+#define VI_H_DOWNSCALE_CONTROL_0                        _MK_ADDR_CONST(0x43)
+#define VI_H_DOWNSCALE_CONTROL_0_SECURE                         0x0
+#define VI_H_DOWNSCALE_CONTROL_0_WORD_COUNT                     0x1
+#define VI_H_DOWNSCALE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x1fff000c)
+#define VI_H_DOWNSCALE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x1fff070f)
+#define VI_H_DOWNSCALE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x1fff070f)
+// Input Horizontal Size Select  Selects between the VIP and HOST input active
+//  area widths for the denominator in the
+//  downscaling ratio.  Uses VIP_H_ACTIVE_PERIOD or
+//  HOST_H_ACTIVE_PERIOD, which is the width of the
+//  data after cropping.  This is effective only when
+//  H_AVERAGING is DISABLED and H_DOWNSCALING is
+//  ENABLED.
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_FIELD                 (_MK_MASK_CONST(0x1) << VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_RANGE                 0:0
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_WOFFSET                       0x0
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_VIP                   _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_HOST                  _MK_ENUM_CONST(1)
+
+// Output Horizontal Size Select  Selects between the first and second memory output
+//  frame widths for the numerator in the downscaling
+//  ratio.  Uses FIRST_FRAME_WIDTH or
+//  SECOND_FRAME_WIDTH.
+//  This is effective
+//  only when H_AVERAGING is DISABLED and
+//  H_DOWNSCALING is ENABLED.
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_RANGE                        1:1
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_WOFFSET                      0x0
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_FIRST                        _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_OUTPUT_H_SIZE_SEL_SECOND                       _MK_ENUM_CONST(1)
+
+//  Selects input horizontal size into scalers (extension field)
+//  00= Hor. size selected with INPUT_H_SIZE_SEL field (backward compatible)
+//  01= Hor. size of CSI_PPA is provided by CSI_PPA_H_ACTIVE register
+//  10= Hor. size of CSI_PPB is provided by CSI_PPB_H_ACTIVE register
+//  11= Hor. size of ISP     is provided by ISP_H_ACTIVE     register
+// 7:4 reserved
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_FIELD                     (_MK_MASK_CONST(0x3) << VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_RANGE                     3:2
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_WOFFSET                   0x0
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_USE_INPUT_H_SIZE_SEL                      _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_CSI_PPA                   _MK_ENUM_CONST(1)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_CSI_PPB                   _MK_ENUM_CONST(2)
+#define VI_H_DOWNSCALE_CONTROL_0_INPUT_H_SIZE_SEL_EXT_ISP                       _MK_ENUM_CONST(3)
+
+// Horizontal Averaging Control  This specifies the number of pixels to
+//  average and to decimate horizontally.
+//   000= 2-pixel averaging and 1/2 down-scaling
+//   001= 4-pixel averaging and 1/3 down-scaling
+//   010= 4-pixel averaging and 1/4 down-scaling
+//   011= 8-pixel averaging and 1/7 down-scaling
+//   100= 8-pixel averaging and 1/8 down-scaling
+//   other= reserved
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_FIELD                    (_MK_MASK_CONST(0x7) << VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_RANGE                    10:8
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_WOFFSET                  0x0
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A2D2                     _MK_ENUM_CONST(0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A4D3                     _MK_ENUM_CONST(1)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A4D4                     _MK_ENUM_CONST(2)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A8D7                     _MK_ENUM_CONST(3)
+#define VI_H_DOWNSCALE_CONTROL_0_H_AVG_CONTROL_A8D8                     _MK_ENUM_CONST(4)
+
+// Horizontal Decimation Accumulator Initial Value
+//  The user may initialized the H-Dec accumulator with
+//  a value between 0-(H_ACTIVE_PERIOD) to change the phase
+//  of the decimation pattern.  This will allow the user
+//  to decide which is the first pixel to keep.
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SHIFT)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_RANGE                   28:16
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_WOFFSET                 0x0
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_H_DOWNSCALE_CONTROL_0_H_DEC_INIT_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Vertical processing consists of optional vertical down-scaling (decimation) which can be
+// performed with or without vertical averaging.
+// If vertical down-scaling (decimation) is performed without vertical averaging, the
+// down-scaling factor is specified by input active period and output frame size.  Because the
+// VI has two input methods (VIP and HOST) and two memory outputs, there are mux selects to indicate
+// which registers to use in calculating the input and output frame sizes.
+// If horizontal down-scaling is performed with vertical averaging, the down-scaling factors
+// are limited to few factors determined by V_AVG_CONTROL.  When enabling averaging PLEASE be careful
+// that the input and output ratios match the formula for the averaging decimation ratio exactly to the
+// pixel/line. The formula for each of the Averaging Decimation Ratio is as follows:
+//
+// Averaging Decimation Formalae
+// x = input size
+// y(x) = output size
+// 2-pixel averaging and 1/2 downscaling: y(x) = Floor(x/2)
+// 4-pixel averaging and 1/3 downscaling: y(x) = Floor((x-1)/3)
+// 4-pixel averaging and 1/4 downscaling: y(x) = Floor(x/4)
+// 8-pixel averaging and 1/7 downscaling: y(x) = Floor((x-1)/7)
+// 8-pixel averaging and 1/8 downscaling: y(x) = Floor(x/8)
+//
+// Vertical Decimation Algorithm: (same as the Horizontal Decimation Algorithm)
+// The Vertical Decimator decides which pixels to drop by using a simple DDA algorithm.
+// The accumulator will continue to add the value of the output height (numerator) for each
+// line until the sum is equal or greater than the input height (denominator).  When the sum
+// is greater or equal to the input height (denominator), the hardware will flag that line as
+// a line to be written out to memory.  At the same time, the input height (denominator) will
+// be subtracted from the sum and the difference will be loaded back into the accumulator for
+// the next line.  By default the accumulator is initialized with 0's upon reset.  However the
+// user can set the V_DEC_INIT_VAL to initialize the accumulator with a certain value from
+// 0 to the input height (denominator).  Any V_DEC_INIT_VAL that is greater or equal to the
+// difference of the input height (denominator) and the output height (numerator) will cause the
+// first line to be written out to memory.  This register shifts the phase of the decimation
+// pattern.
+
+// Register VI_V_DOWNSCALE_CONTROL_0  // VI Vertical Down-scaling Control
+#define VI_V_DOWNSCALE_CONTROL_0                        _MK_ADDR_CONST(0x44)
+#define VI_V_DOWNSCALE_CONTROL_0_SECURE                         0x0
+#define VI_V_DOWNSCALE_CONTROL_0_WORD_COUNT                     0x1
+#define VI_V_DOWNSCALE_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0x1fff000c)
+#define VI_V_DOWNSCALE_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0x1fff370f)
+#define VI_V_DOWNSCALE_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0x1fff370f)
+// Input Vertical Size Select  Selects between the VIP and HOST input active
+//  area heights for the denominator in the
+//  downscaling ratio.  Uses VIP_V_ACTIVE_PERIOD or
+//  HOST_V_ACTIVE_PERIOD, which is the height of the
+//  data after cropping.  This is effective only when
+//  V_AVERAGING is DISABLED and V_DOWNSCALING is
+//  ENABLED.
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_FIELD                 (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_RANGE                 0:0
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_WOFFSET                       0x0
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_VIP                   _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_HOST                  _MK_ENUM_CONST(1)
+
+// Output Vertical Size Select  Selects between the first and second memory output
+//  frame heights for the numerator in the downscaling
+//  ratio.  Uses FIRST_FRAME_HEIGHT or
+//  SECOND_FRAME_HEIGHT.
+//  This is effective
+//  only when V_AVERAGING is DISABLED and
+//  V_DOWNSCALING is ENABLED.
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_FIELD                        (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_RANGE                        1:1
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_WOFFSET                      0x0
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_FIRST                        _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_OUTPUT_V_SIZE_SEL_SECOND                       _MK_ENUM_CONST(1)
+
+//  Selects input vertical size into scalers (extension field)
+//  00= Vert. size selected with INPUT_V_SIZE_SEL field (backward compatible)
+//  01= Vert. size of CSI_PPA is provided by CSI_PPA_V_ACTIVE register
+//  10= Vert. size of CSI_PPB is provided by CSI_PPB_V_ACTIVE register
+//  11= Vert. size of ISP     is provided by ISP_V_ACTIVE     register
+// 7:4 reserved
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_FIELD                     (_MK_MASK_CONST(0x3) << VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_RANGE                     3:2
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_WOFFSET                   0x0
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_USE_INPUT_V_SIZE_SEL                      _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_CSI_PPA                   _MK_ENUM_CONST(1)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_CSI_PPB                   _MK_ENUM_CONST(2)
+#define VI_V_DOWNSCALE_CONTROL_0_INPUT_V_SIZE_SEL_EXT_ISP                       _MK_ENUM_CONST(3)
+
+// Vertical Averaging Control  This specifies the number of lines to
+//  average and to decimate vertically.
+//   000= 2-line averaging and 1/2 down-scaling
+//   001= 4-line averaging and 1/3 down-scaling
+//   010= 4-line averaging and 1/4 down-scaling
+//   011= 8-line averaging and 1/7 down-scaling
+//   100= 8-line averaging and 1/8 down-scaling
+//   other= reserved
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_FIELD                    (_MK_MASK_CONST(0x7) << VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_RANGE                    10:8
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_WOFFSET                  0x0
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A2D2                     _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A4D3                     _MK_ENUM_CONST(1)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A4D4                     _MK_ENUM_CONST(2)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A8D7                     _MK_ENUM_CONST(3)
+#define VI_V_DOWNSCALE_CONTROL_0_V_AVG_CONTROL_A8D8                     _MK_ENUM_CONST(4)
+
+// Flexible Vertical Scaling   0 = disabled, V_AVG_CONTROL specifies both
+//       vertical averaging and down-scaling
+//       factor.
+//   1 = enabled, fixed 2-line averaging with
+//       vertical downscaling controlled by
+//       V_DOWN_N and V_DOWN_D.
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SHIFT                  _MK_SHIFT_CONST(12)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_FIELD                  (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_RANGE                  12:12
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_WOFFSET                        0x0
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_FLEXIBLE_VSCALE_ENABLED                        _MK_ENUM_CONST(1)
+
+// Multi-Tap Vertical Averaging Filter   0 = disabled
+//   1 = enabled
+//  This will enable the Multi-Tap filtering
+//  when the Vertical Averaging is enabled.
+//  The filter settings will depend on the
+//  V_AVG_CONTROL value.
+//  000 - 3 Taps (1,2,1)/4
+//  001 - 5 Taps (1,2,2,2,1)/8
+//  010 - 6 Taps (1,1,2,2,1,1)/8
+//  011 - 11 Taps (1,1,1,2,2,2,2,2,1,1,1)/16
+//  100 - 12 Taps (1,1,1,1,2,2,2,2,1,1,1,1)/16
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SHIFT                   _MK_SHIFT_CONST(13)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_FIELD                   (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_RANGE                   13:13
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_WOFFSET                 0x0
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_MULTI_TAP_V_AVG_FILTER_ENABLED                 _MK_ENUM_CONST(1)
+
+// Vertical Decimation Accumulator Initial Value
+//  The user may initialized the V-Dec accumulator with
+//  a value between 0-(V_ACTIVE_PERIOD) to change the phase
+//  of the decimation pattern.  This will allow the user
+//  to decide which is the first line to keep.
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_FIELD                   (_MK_MASK_CONST(0x1fff) << VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_RANGE                   28:16
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_WOFFSET                 0x0
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_DEFAULT_MASK                    _MK_MASK_CONST(0x1fff)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_V_DEC_INIT_VAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Specifies whether odd/even field affects vertical  decimation.
+//   0 = disabled - odd/even field affects the vertical downscaling
+//   1 = enabled - field is ignored in vertical downscaling
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SHIFT                     _MK_SHIFT_CONST(28)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_FIELD                     (_MK_MASK_CONST(0x1) << VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SHIFT)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_RANGE                     28:28
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_WOFFSET                   0x0
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_V_DOWNSCALE_CONTROL_0_IGNORE_FIELD_ENABLED                   _MK_ENUM_CONST(1)
+
+// Color Space Conversion coefficients.
+// The CSC can be used for YUV to RGB conversion with brightness and hue/saturation control.
+// For Y color, the Y offset is applied first and saturation (clipping) is performed
+//   immediately after the Y offset is applied.
+//   R = sat(KYRGB * sat(Y + YOF) + KUR * U + KVR * V)
+//   G = sat(KYRGB * sat(Y + YOF) + KUG * U + KVG * V)
+//   B = sat(KYRGB * sat(Y + YOF) + KUB * U + KVB * V)
+// Saturation and rounding is performed in the range of 0 to 255 for the above equations.
+//
+// Typical values are:
+//   YOF = -16.000, KYRGB =  1.1644
+//   KUR =  0.0000, KVR   = -1.5960
+//   KUG = -0.3918, KVG   = -0.8130
+//   KUB =  2.0172, KVB   =  0.0000
+//   KUR and KVB are typically 0.0000 but they may be programmed non-zero for hue rotation.
+//
+// The CSC can also take RGB input, in which case YOF, KVB, KUG, KUR should be programmed to 0
+//   and KYRGB will be forced to 0 by the hardware for generating R and B. KYRGB will not be
+//   forced to 0 for generating G. KVR, KYRGB, and KUB can be programmed to 1.0 or used as
+//   gain control for R, G, B correspondingly.
+// Note that color value ranges from 0 to 255 for Y, R, G, B and -128 to 127 for U and V.
+
+// Register VI_CSC_Y_0  // CSC Y Offset and Gain
+#define VI_CSC_Y_0                      _MK_ADDR_CONST(0x45)
+#define VI_CSC_Y_0_SECURE                       0x0
+#define VI_CSC_Y_0_WORD_COUNT                   0x1
+#define VI_CSC_Y_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_READ_MASK                    _MK_MASK_CONST(0x3ff00ff)
+#define VI_CSC_Y_0_WRITE_MASK                   _MK_MASK_CONST(0x3ff00ff)
+// Y Offset in s.7.0 format
+#define VI_CSC_Y_0_YOF_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_CSC_Y_0_YOF_FIELD                    (_MK_MASK_CONST(0xff) << VI_CSC_Y_0_YOF_SHIFT)
+#define VI_CSC_Y_0_YOF_RANGE                    7:0
+#define VI_CSC_Y_0_YOF_WOFFSET                  0x0
+#define VI_CSC_Y_0_YOF_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_YOF_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_YOF_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_YOF_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Y Gain for R, G, B colors in 2.8 format
+#define VI_CSC_Y_0_KYRGB_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_CSC_Y_0_KYRGB_FIELD                  (_MK_MASK_CONST(0x3ff) << VI_CSC_Y_0_KYRGB_SHIFT)
+#define VI_CSC_Y_0_KYRGB_RANGE                  25:16
+#define VI_CSC_Y_0_KYRGB_WOFFSET                        0x0
+#define VI_CSC_Y_0_KYRGB_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_KYRGB_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_KYRGB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSC_Y_0_KYRGB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_UV_R_0  // CSC U & V coefficent for R
+#define VI_CSC_UV_R_0                   _MK_ADDR_CONST(0x46)
+#define VI_CSC_UV_R_0_SECURE                    0x0
+#define VI_CSC_UV_R_0_WORD_COUNT                        0x1
+#define VI_CSC_UV_R_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_READ_MASK                         _MK_MASK_CONST(0x7ff07ff)
+#define VI_CSC_UV_R_0_WRITE_MASK                        _MK_MASK_CONST(0x7ff07ff)
+// U coefficients for R in s.2.8 format
+#define VI_CSC_UV_R_0_KUR_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CSC_UV_R_0_KUR_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_R_0_KUR_SHIFT)
+#define VI_CSC_UV_R_0_KUR_RANGE                 10:0
+#define VI_CSC_UV_R_0_KUR_WOFFSET                       0x0
+#define VI_CSC_UV_R_0_KUR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KUR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KUR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KUR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// V coefficients for R in s.2.8 format
+#define VI_CSC_UV_R_0_KVR_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_CSC_UV_R_0_KVR_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_R_0_KVR_SHIFT)
+#define VI_CSC_UV_R_0_KVR_RANGE                 26:16
+#define VI_CSC_UV_R_0_KVR_WOFFSET                       0x0
+#define VI_CSC_UV_R_0_KVR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KVR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KVR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_R_0_KVR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_UV_G_0  // CSC U & V coefficent for G
+#define VI_CSC_UV_G_0                   _MK_ADDR_CONST(0x47)
+#define VI_CSC_UV_G_0_SECURE                    0x0
+#define VI_CSC_UV_G_0_WORD_COUNT                        0x1
+#define VI_CSC_UV_G_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_READ_MASK                         _MK_MASK_CONST(0x3ff03ff)
+#define VI_CSC_UV_G_0_WRITE_MASK                        _MK_MASK_CONST(0x3ff03ff)
+// U coefficients for G in s.1.8 format
+#define VI_CSC_UV_G_0_KUG_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CSC_UV_G_0_KUG_FIELD                 (_MK_MASK_CONST(0x3ff) << VI_CSC_UV_G_0_KUG_SHIFT)
+#define VI_CSC_UV_G_0_KUG_RANGE                 9:0
+#define VI_CSC_UV_G_0_KUG_WOFFSET                       0x0
+#define VI_CSC_UV_G_0_KUG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KUG_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KUG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KUG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// V coefficients for G in s.1.8 format
+#define VI_CSC_UV_G_0_KVG_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_CSC_UV_G_0_KVG_FIELD                 (_MK_MASK_CONST(0x3ff) << VI_CSC_UV_G_0_KVG_SHIFT)
+#define VI_CSC_UV_G_0_KVG_RANGE                 25:16
+#define VI_CSC_UV_G_0_KVG_WOFFSET                       0x0
+#define VI_CSC_UV_G_0_KVG_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KVG_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KVG_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_G_0_KVG_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_UV_B_0  // CSC U & V coefficent for B
+#define VI_CSC_UV_B_0                   _MK_ADDR_CONST(0x48)
+#define VI_CSC_UV_B_0_SECURE                    0x0
+#define VI_CSC_UV_B_0_WORD_COUNT                        0x1
+#define VI_CSC_UV_B_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_READ_MASK                         _MK_MASK_CONST(0x7ff07ff)
+#define VI_CSC_UV_B_0_WRITE_MASK                        _MK_MASK_CONST(0x7ff07ff)
+// U coefficients for B in s.2.8 format
+#define VI_CSC_UV_B_0_KUB_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_CSC_UV_B_0_KUB_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_B_0_KUB_SHIFT)
+#define VI_CSC_UV_B_0_KUB_RANGE                 10:0
+#define VI_CSC_UV_B_0_KUB_WOFFSET                       0x0
+#define VI_CSC_UV_B_0_KUB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KUB_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KUB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KUB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// V coefficients for B in s.2.8 format
+#define VI_CSC_UV_B_0_KVB_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_CSC_UV_B_0_KVB_FIELD                 (_MK_MASK_CONST(0x7ff) << VI_CSC_UV_B_0_KVB_SHIFT)
+#define VI_CSC_UV_B_0_KVB_RANGE                 26:16
+#define VI_CSC_UV_B_0_KVB_WOFFSET                       0x0
+#define VI_CSC_UV_B_0_KVB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KVB_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KVB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSC_UV_B_0_KVB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSC_ALPHA_0  // RGB Color Space Converter Alpha value
+#define VI_CSC_ALPHA_0                  _MK_ADDR_CONST(0x49)
+#define VI_CSC_ALPHA_0_SECURE                   0x0
+#define VI_CSC_ALPHA_0_WORD_COUNT                       0x1
+#define VI_CSC_ALPHA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_RESET_MASK                       _MK_MASK_CONST(0xff)
+#define VI_CSC_ALPHA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_READ_MASK                        _MK_MASK_CONST(0xff)
+#define VI_CSC_ALPHA_0_WRITE_MASK                       _MK_MASK_CONST(0xff)
+// When output format to memory is selected
+//  for RGB888, the pixel data is 32-bit aligned
+//  The value programmed here will be appended to the
+//  RGB888 data as the 8 MSBs and can be used as an
+//  alpha value.
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_FIELD                       (_MK_MASK_CONST(0xff) << VI_CSC_ALPHA_0_RGB888_ALPHA_SHIFT)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_RANGE                       7:0
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_WOFFSET                     0x0
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSC_ALPHA_0_RGB888_ALPHA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_HOST_VSYNC_0  // Valid when INPUT_SOURCE is HOST
+#define VI_HOST_VSYNC_0                 _MK_ADDR_CONST(0x4a)
+#define VI_HOST_VSYNC_0_SECURE                  0x0
+#define VI_HOST_VSYNC_0_WORD_COUNT                      0x1
+#define VI_HOST_VSYNC_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define VI_HOST_VSYNC_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+// This triggers VI's internal VSYNC generation
+// Always write once to this register with '1'
+// before writing the Frame's data to Y_FIFO_DATA
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_FIELD                        (_MK_MASK_CONST(0x1) << VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SHIFT)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_RANGE                        0:0
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_WOFFSET                      0x0
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_HOST_VSYNC_0_HOST_VSYNC_TRIGGER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// **** This eventually needs to be moved to command buffer interface.
+// This register is used initialize VI module when INPUT_SOURCE is HOST.
+// **** This register has a dual use purpose.  Host input VSYNC is created by
+// writing to this register.
+
+// Register VI_COMMAND_0  // VI Command
+#define VI_COMMAND_0                    _MK_ADDR_CONST(0x4b)
+#define VI_COMMAND_0_SECURE                     0x0
+#define VI_COMMAND_0_WORD_COUNT                         0x1
+#define VI_COMMAND_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_RESET_MASK                         _MK_MASK_CONST(0x1)
+#define VI_COMMAND_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_READ_MASK                  _MK_MASK_CONST(0x1fff0f01)
+#define VI_COMMAND_0_WRITE_MASK                         _MK_MASK_CONST(0x1fff0f01)
+// Process Odd/Even field  (effective when INPUT_SOURCE is HOST)
+//  Writing to this bit will initialize VI
+//  to receive one field of video.
+//   0= odd field
+//   1= even field
+#define VI_COMMAND_0_PROCESS_FIELD_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_COMMAND_0_PROCESS_FIELD_FIELD                        (_MK_MASK_CONST(0x1) << VI_COMMAND_0_PROCESS_FIELD_SHIFT)
+#define VI_COMMAND_0_PROCESS_FIELD_RANGE                        0:0
+#define VI_COMMAND_0_PROCESS_FIELD_WOFFSET                      0x0
+#define VI_COMMAND_0_PROCESS_FIELD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_PROCESS_FIELD_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_COMMAND_0_PROCESS_FIELD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_PROCESS_FIELD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_PROCESS_FIELD_ODD                  _MK_ENUM_CONST(0)
+#define VI_COMMAND_0_PROCESS_FIELD_EVEN                 _MK_ENUM_CONST(1)
+
+// Y-FIFO Threshold
+//  This specifies maximum number of filled
+//  locations in Y-FIFO for the Y-FIFO Threshold
+//  Status bit.
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_FIELD                     (_MK_MASK_CONST(0xf) << VI_COMMAND_0_Y_FIFO_THRESHOLD_SHIFT)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_RANGE                     11:8
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_WOFFSET                   0x0
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_Y_FIFO_THRESHOLD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Vertical Counter Threshold
+//  This specifies a threshold which, when
+//  exceeded, would generate the vertical
+//  counter interrupt if the interrupt is
+//  enabled. This is used to detect the case
+//  when the host is sending too many input data
+//  than expected by VI module.
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_FIELD                  (_MK_MASK_CONST(0x1fff) << VI_COMMAND_0_V_COUNTER_THRESHOLD_SHIFT)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_RANGE                  28:16
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_WOFFSET                        0x0
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_COMMAND_0_V_COUNTER_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// **** This is not needed if host input video goes through command buffer interface.
+
+// Register VI_HOST_FIFO_STATUS_0  // Host FIFO status
+#define VI_HOST_FIFO_STATUS_0                   _MK_ADDR_CONST(0x4c)
+#define VI_HOST_FIFO_STATUS_0_SECURE                    0x0
+#define VI_HOST_FIFO_STATUS_0_WORD_COUNT                        0x1
+#define VI_HOST_FIFO_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x770f)
+#define VI_HOST_FIFO_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// This indicates the number of filled locations
+//  in Y-FIFO. If the returned value is 4'h0, the
+//  fifo is empty and if the returned value is
+//  4'hF then the fifo is full.
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_FIELD                       (_MK_MASK_CONST(0xf) << VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SHIFT)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_RANGE                       3:0
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_WOFFSET                     0x0
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_Y_FIFO_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// This indicates the number of filled locations
+//  in U-FIFO. If the returned value is 3'h0, the
+//  fifo is empty and if the returned value is
+//  3'h7 then the fifo is full.
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_FIELD                       (_MK_MASK_CONST(0x7) << VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SHIFT)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_RANGE                       10:8
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_WOFFSET                     0x0
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_U_FIFO_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// This indicates the number of filled locations
+//  in V-FIFO. If the returned value is 3'h0, the
+//  fifo is empty and if the returned value is
+//  3'h7 then the fifo is full.
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SHIFT                       _MK_SHIFT_CONST(12)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_FIELD                       (_MK_MASK_CONST(0x7) << VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SHIFT)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_RANGE                       14:12
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_WOFFSET                     0x0
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_HOST_FIFO_STATUS_0_V_FIFO_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register VI_INTERRUPT_MASK_0  // Interrupt Mask
+#define VI_INTERRUPT_MASK_0                     _MK_ADDR_CONST(0x4d)
+#define VI_INTERRUPT_MASK_0_SECURE                      0x0
+#define VI_INTERRUPT_MASK_0_WORD_COUNT                  0x1
+#define VI_INTERRUPT_MASK_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RESET_MASK                  _MK_MASK_CONST(0x1fefffff)
+#define VI_INTERRUPT_MASK_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_READ_MASK                   _MK_MASK_CONST(0x1fefffff)
+#define VI_INTERRUPT_MASK_0_WRITE_MASK                  _MK_MASK_CONST(0x1fefffff)
+// VD8 pin Interrupt Mask  This bit controls interrupt when VD8
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD8_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_RANGE                  0:0
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD8_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Mask  This bit controls interrupt when VD9
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_SHIFT                  _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD9_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_RANGE                  1:1
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD9_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Mask  This bit controls interrupt when VD10
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_SHIFT                 _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD10_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_RANGE                 2:2
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD10_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Mask  This bit controls interrupt when VD11
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_SHIFT                 _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VD11_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_RANGE                 3:3
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VD11_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Mask  This bit controls interrupt when VGP4
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SHIFT                 _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_RANGE                 4:4
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VGP4_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Mask  This bit controls interrupt when VGP5
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SHIFT                 _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_RANGE                 5:5
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VGP5_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Mask  This bit controls interrupt when VGP6
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_RANGE                 6:6
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VGP6_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Mask  This bit controls interrupt when VHS
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_SHIFT                  _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VHS_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_RANGE                  7:7
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VHS_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Mask  This bit controls interrupt when VVS
+//  rising/falling edge is detected.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_SHIFT                  _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_VVS_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_RANGE                  8:8
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_VVS_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Vertical Counter Interrupt Mask  (effective when VIDEO_SOURCE is HOST)
+//  This bit controls interrupt when the
+//  vertical counter threshold is reached.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SHIFT                    _MK_SHIFT_CONST(9)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_RANGE                    9:9
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_V_COUNTER_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Y-FIFO Threshold Interrupt Mask  This bit controls interrupt when the number
+//  of filled locations in Y-FIFO is equal or
+//  greater than the Y_FIFO_THRESHOLD value.
+//  This bit should be set to 1 only when
+//  INPUT_SOURCE is HOST.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SHIFT                  _MK_SHIFT_CONST(10)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_RANGE                  10:10
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_Y_THRESHOLD_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Buffer Done First Output Interrupt Mask  This bit controls interrupt when the
+//  First Output to memory has written
+//  a buffer to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SHIFT                  _MK_SHIFT_CONST(11)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_RANGE                  11:11
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_BUFFER_FIRST_OUTPUT_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Frame Done First Output Interrupt Mask  This bit controls interrupt when the
+//  First Output to memory has written
+//  a frame to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SHIFT                   _MK_SHIFT_CONST(12)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_RANGE                   12:12
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_WOFFSET                 0x0
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FRAME_FIRST_OUTPUT_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Buffer Done Second Output Interrupt Mask  This bit controls interrupt when the
+//  Second Output to memory has written
+//  a buffer to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SHIFT                 _MK_SHIFT_CONST(13)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_RANGE                 13:13
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_WOFFSET                       0x0
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_BUFFER_SECOND_OUTPUT_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Buffer Done Second Output Interrupt Mask  This bit controls interrupt when the
+//  Second Output to memory has written
+//  a frame to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SHIFT                  _MK_SHIFT_CONST(14)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_RANGE                  14:14
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_WOFFSET                        0x0
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FRAME_SECOND_OUTPUT_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// VI to EPP Error Interrupt Mask  This bit controls interrupt when the
+//  VI drops data to the EPP because the
+//  EPP is stalling the vi2epp bus and
+//  data is coming from the pins
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(15)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_RANGE                    15:15
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_EPP_ERROR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// YUV420PA Error Interrupt Mask  This bit controls interrupt when the
+//  VI does not average data because the
+//  line buffer data is not ready from the
+//  memory controller.  The VI will write
+//  unaveraged data and will write the U,V
+//  data from the even line in such cases.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(16)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_RANGE                       16:16
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_WOFFSET                     0x0
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_YUV420PA_ERROR_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// VI to Peer stall - First Memory Output  This bit controls interrupt when the
+//  VI drops peer bus packet(s) because the
+//  peer is stalling the first output peer
+//  bus and data is coming from the pins
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SHIFT                      _MK_SHIFT_CONST(17)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_RANGE                      17:17
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_WOFFSET                    0x0
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_PEER_STALL_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// VI to Peer stall - Second Memory Output  This bit controls interrupt when the
+//  VI drops peer bus packet(s) because the
+//  peer is stalling the second output peer
+//  bus and data is coming from the pins
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SHIFT                     _MK_SHIFT_CONST(18)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_RANGE                     18:18
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_WOFFSET                   0x0
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_PEER_STALL_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Write Buffer DMA to VI Stalls VI and causes an error  This bit controls interrupt when the
+//  VI drops raw 8-bit stream data because
+//  the Write Buffer DMA is stalling.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SHIFT                    _MK_SHIFT_CONST(19)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_RANGE                    19:19
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_DMA_STALL_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Stream 1 raise  This bit controls interrupt when the
+//  the Stream 1 Raise is enabled and
+//  returned
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SHIFT                       _MK_SHIFT_CONST(21)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_RANGE                       21:21
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_WOFFSET                     0x0
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_1_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Stream 2 raise  This bit controls interrupt when the
+//  the Stream 2 Raise is enabled and
+//  returned
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SHIFT                       _MK_SHIFT_CONST(22)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_RANGE                       22:22
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_WOFFSET                     0x0
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_RAISE_STREAM_2_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T vi input gets an upstream error.
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(23)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_RANGE                    23:23
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_UPSTREAM_ERROR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T input get an underrun error
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(24)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_RANGE                    24:24
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_UNDERRUN_ERROR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T input get an overrun error
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(25)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_RANGE                     25:25
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_WOFFSET                   0x0
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_OVERRUN_ERROR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when the
+//  ISDB-T input get a packet which means
+//  FEC+BODY in totalsize but FEC and BODY
+//  do not match FEC_SIZE and BODY_SIZE
+//   0= Disabled
+//   1= Enabled
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SHIFT                      _MK_SHIFT_CONST(26)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_RANGE                      26:26
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_WOFFSET                    0x0
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_TS_OTHER_PROTOCOL_ERROR_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when VI drops
+// data to MC.
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT                    _MK_SHIFT_CONST(27)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_RANGE                    27:27
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_WOFFSET                  0x0
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_FIRST_OUTPUT_DROP_MC_DATA_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// This bit controls interrupt when VI drops
+// data to MC.
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT                   _MK_SHIFT_CONST(28)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SHIFT)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_RANGE                   28:28
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_WOFFSET                 0x0
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_MASK_0_SECOND_OUTPUT_DROP_MC_DATA_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register VI_INTERRUPT_TYPE_SELECT_0  // Interrupt Type Select
+#define VI_INTERRUPT_TYPE_SELECT_0                      _MK_ADDR_CONST(0x4e)
+#define VI_INTERRUPT_TYPE_SELECT_0_SECURE                       0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_WORD_COUNT                   0x1
+#define VI_INTERRUPT_TYPE_SELECT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_RESET_MASK                   _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_TYPE_SELECT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_READ_MASK                    _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_TYPE_SELECT_0_WRITE_MASK                   _MK_MASK_CONST(0x1ff)
+// VD8 pin Interrupt Type  This bit controls interrupt VD8
+//  if edge or level type
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_RANGE                   0:0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD8_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Type  This bit controls interrupt VD9
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_RANGE                   1:1
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD9_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Type  This bit controls interrupt VD10
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_RANGE                  2:2
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD10_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Type  This bit controls interrupt VD11
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_RANGE                  3:3
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VD11_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Type  This bit controls interrupt VGP4
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_RANGE                  4:4
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP4_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Type  This bit controls interrupt VGP5
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_RANGE                  5:5
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP5_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Type  This bit controls interrupt VGP6
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SHIFT                  _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_RANGE                  6:6
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_WOFFSET                        0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_EDGE                   _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VGP6_INT_TYPE_LEVEL                  _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Type  This bit controls interrupt VHS
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_RANGE                   7:7
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VHS_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Type  This bit controls interrupt VVS
+//   0= Edge type
+//   1= Level type
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SHIFT)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_RANGE                   8:8
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_WOFFSET                 0x0
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_EDGE                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_TYPE_SELECT_0_VVS_INT_TYPE_LEVEL                   _MK_ENUM_CONST(1)
+
+
+// Register VI_INTERRUPT_POLARITY_SELECT_0  // Interrupt Polarity Select
+#define VI_INTERRUPT_POLARITY_SELECT_0                  _MK_ADDR_CONST(0x4f)
+#define VI_INTERRUPT_POLARITY_SELECT_0_SECURE                   0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_WORD_COUNT                       0x1
+#define VI_INTERRUPT_POLARITY_SELECT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_RESET_MASK                       _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_POLARITY_SELECT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_READ_MASK                        _MK_MASK_CONST(0x1ff)
+#define VI_INTERRUPT_POLARITY_SELECT_0_WRITE_MASK                       _MK_MASK_CONST(0x1ff)
+// VD8 pin Interrupt Type  This bit controls interrupt VD8
+//  if edge or level type
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_RANGE                   0:0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD8_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Type  This bit controls interrupt VD9
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_RANGE                   1:1
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD9_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Type  This bit controls interrupt VD10
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_RANGE                  2:2
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD10_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Type  This bit controls interrupt VD11
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_RANGE                  3:3
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VD11_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Type  This bit controls interrupt VGP4
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_RANGE                  4:4
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP4_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Type  This bit controls interrupt VGP5
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_RANGE                  5:5
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP5_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Type  This bit controls interrupt VGP6
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SHIFT                  _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_RANGE                  6:6
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_WOFFSET                        0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_LOW                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VGP6_INT_POLARITY_HIGH                   _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Type  This bit controls interrupt VHS
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_RANGE                   7:7
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VHS_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Type  This bit controls interrupt VVS
+//   0= falling edge or low level
+//   1= rising edge or high level
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SHIFT)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_RANGE                   8:8
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_WOFFSET                 0x0
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_LOW                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_POLARITY_SELECT_0_VVS_INT_POLARITY_HIGH                    _MK_ENUM_CONST(1)
+
+// This register returns interrupt status when read. Except for bits 15-14, when this register
+// is written, the interrupt status corresponding to the bits written with 1 will be reset.
+// Interrupt status corresponding to the bits written with 0 will be left unchanged.
+// **** The following disclaimer is from SCx - not sure why they're needed ... interrupt should
+//      not be generated when the corresponding interrupt enable bit is disabled.
+// Note that interrupt status bits can be set even when their corresponding interrupt enable
+// bits, in VI10R, are cleared. When these bits are set and their corresponding interrupt
+// enable bits are set, an interrupt is generated. The interrupt can be cleared, or left
+// unchanged, by writing 1, or 0, respectively to the corresponding bits in this register.
+// Clearing the interrupt status bits does not affect the interrupt enable bits.
+
+// Register VI_INTERRUPT_STATUS_0  // Interrupt Enable
+#define VI_INTERRUPT_STATUS_0                   _MK_ADDR_CONST(0x50)
+#define VI_INTERRUPT_STATUS_0_SECURE                    0x0
+#define VI_INTERRUPT_STATUS_0_WORD_COUNT                        0x1
+#define VI_INTERRUPT_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_READ_MASK                         _MK_MASK_CONST(0x1fffffff)
+#define VI_INTERRUPT_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// VD8 pin Interrupt Status  This bit controls interrupt when VD8
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_RANGE                      0:0
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD8_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VD9 pin Interrupt Status  This bit controls interrupt when VD9
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_RANGE                      1:1
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD9_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VD10 pin Interrupt Status  This bit controls interrupt when VD10
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_RANGE                     2:2
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD10_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VD11 pin Interrupt Status  This bit controls interrupt when VD11
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(3)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_RANGE                     3:3
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VD11_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VGP4 pin Interrupt Status  This bit controls interrupt when VGP4
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_RANGE                     4:4
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VGP4_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VGP5 pin Interrupt Status  This bit controls interrupt when VGP5
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(5)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_RANGE                     5:5
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VGP5_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VGP6 pin Interrupt Status  This bit controls interrupt when VGP6
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(6)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_RANGE                     6:6
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VGP6_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// VHS pin Interrupt Status  This bit controls interrupt when VHS
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_RANGE                      7:7
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VHS_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VVS pin Interrupt Status  This bit controls interrupt when VVS
+//  rising/falling edge is detected.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(8)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_RANGE                      8:8
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_VVS_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// Vertical Counter Interrupt Status  (effective when VIDEO_SOURCE is HOST)
+//  This bit controls interrupt when the
+//  vertical counter threshold is reached.
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(9)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_RANGE                        9:9
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_V_COUNTER_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// Y-FIFO Threshold Interrupt Enable  This bit controls interrupt when the number
+//  of filled locations in Y-FIFO is equal or
+//  greater than the Y_FIFO_THRESHOLD value.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(10)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_RANGE                      10:10
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_Y_THRESHOLD_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// Buffer Done First Output Interrupt Status  This bit is set when a buffer has been
+//  written to memory by the first output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(11)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_RANGE                      11:11
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_FIRST_OUTPUT_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// Frame Done First Output Interrupt Status  This bit is set when a frame has been
+//  written to memory by the first output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(12)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_RANGE                       12:12
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_WOFFSET                     0x0
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_NOINTR                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FRAME_FIRST_OUTPUT_INT_STATUS_INTR                        _MK_ENUM_CONST(1)
+
+// Buffer Done Second Output Interrupt Status  This bit is set when a buffer has been
+//  written to memory by the second output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SHIFT                     _MK_SHIFT_CONST(13)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_FIELD                     (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_RANGE                     13:13
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_WOFFSET                   0x0
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_NOINTR                    _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_BUFFER_SECOND_OUTPUT_INT_STATUS_INTR                      _MK_ENUM_CONST(1)
+
+// Frame Done Second Output Interrupt Status  This bit is set when a frame has been
+//  written to memory by the second output.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SHIFT                      _MK_SHIFT_CONST(14)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_FIELD                      (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_RANGE                      14:14
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_WOFFSET                    0x0
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_NOINTR                     _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FRAME_SECOND_OUTPUT_INT_STATUS_INTR                       _MK_ENUM_CONST(1)
+
+// VI to EPP Error Interrupt Enable  This bit controls interrupt when the
+//  VI drops data to the EPP because the
+//  EPP is stalling the vi2epp bus and
+//  data is coming from the pins
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(15)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_RANGE                        15:15
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_EPP_ERROR_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// YUV420PA Error Interrupt Enable This bit shows the status of if the
+//  VI does not average data because the
+//  line buffer data is not ready from the
+//  memory controller.  The VI will write
+//  unaveraged data and will write the U,V
+//  data from the even line in such cases.
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_RANGE                   16:16
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_WOFFSET                 0x0
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_NOINTR                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_YUV420PA_ERROR_INT_STATUS_INTR                    _MK_ENUM_CONST(1)
+
+// This bit shows the status of if the
+//  VI dropped a buffer packet to the
+//  peer communicating with the first memory
+//  output
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SHIFT                  _MK_SHIFT_CONST(17)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_RANGE                  17:17
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_WOFFSET                        0x0
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_NOINTR                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_PEER_STALL_INT_STATUS_INTR                   _MK_ENUM_CONST(1)
+
+// This bit shows the status of if the
+//  VI dropped a buffer packet to the
+//  peer communicating with the second memory
+//  output
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SHIFT                 _MK_SHIFT_CONST(18)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_RANGE                 18:18
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_WOFFSET                       0x0
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_NOINTR                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_PEER_STALL_INT_STATUS_INTR                  _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  VI drops data to the Write Buffer DMA
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(19)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_RANGE                        19:19
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_DMA_STALL_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// Top or Bottom Field Status  This bit specifies whether the last received
+//  video data field is top field or bottom
+//  field as defined by FIELD_TYPE bit. This bit
+//  is forced to 0 if FIELD_DETECT is DISABLED
+//  when VIDEO_SOURCE is VIP.
+//  This bit cannot be reset by software by
+//  writing a 1.
+//   0= Bottom field received
+//   1= Top field received
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_SHIFT                        _MK_SHIFT_CONST(20)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FIELD_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_RANGE                        20:20
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_BOTTOM                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FIELD_STATUS_TOP                  _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  Raise Stream 1 returns to the Host
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SHIFT                   _MK_SHIFT_CONST(21)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_RANGE                   21:21
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_WOFFSET                 0x0
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_NOINTR                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_1_INT_STATUS_INTR                    _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  Raise Stream 2 returns to the Host
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SHIFT                   _MK_SHIFT_CONST(22)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_FIELD                   (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_RANGE                   22:22
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_WOFFSET                 0x0
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_NOINTR                  _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_RAISE_STREAM_2_INT_STATUS_INTR                    _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T vi input gets an upstream error (error from the tuner)
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(23)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_RANGE                        23:23
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_UPSTREAM_ERROR_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T input get an underrun error (START condition detected
+//  prior to receiving a full packet)
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(24)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_RANGE                        24:24
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_UNDERRUN_ERROR_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T input get an overrun error (more bytes in packet than specified
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SHIFT                 _MK_SHIFT_CONST(25)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_FIELD                 (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_RANGE                 25:25
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_WOFFSET                       0x0
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_NOINTR                        _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_OVERRUN_ERROR_INT_STATUS_INTR                  _MK_ENUM_CONST(1)
+
+// This bit shows the status of the condition when the
+//  ISDB-T input an other protocol error (ex:
+//  total packet received is FEC_SIZE+BODY_SIZE but
+//  the individual FEC portion != FEC_SIZE and
+//  the individual BODY portion != BODY_SIZE
+//   0= Interrupt not detected
+//   1= Interrupt detected
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SHIFT                  _MK_SHIFT_CONST(26)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_FIELD                  (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_RANGE                  26:26
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_WOFFSET                        0x0
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_NOINTR                 _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_TS_OTHER_PROTOCOL_ERROR_INT_STATUS_INTR                   _MK_ENUM_CONST(1)
+
+// If FIRST_OUTPUT is dropping data to MC, INTR
+//   will be set.
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT                        _MK_SHIFT_CONST(27)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_FIELD                        (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_RANGE                        27:27
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_WOFFSET                      0x0
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_NOINTR                       _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_FIRST_OUTPUT_DROP_MC_DATA_INT_STATUS_INTR                 _MK_ENUM_CONST(1)
+
+// If SECOND_OUTPUT is dropping data to MC, INTR
+//   will be set.
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT                       _MK_SHIFT_CONST(28)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_FIELD                       (_MK_MASK_CONST(0x1) << VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SHIFT)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_RANGE                       28:28
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_WOFFSET                     0x0
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_NOINTR                      _MK_ENUM_CONST(0)
+#define VI_INTERRUPT_STATUS_0_SECOND_OUTPUT_DROP_MC_DATA_INT_STATUS_INTR                        _MK_ENUM_CONST(1)
+
+
+// Register VI_VIP_INPUT_STATUS_0  // Video Input Port status
+#define VI_VIP_INPUT_STATUS_0                   _MK_ADDR_CONST(0x51)
+#define VI_VIP_INPUT_STATUS_0_SECURE                    0x0
+#define VI_VIP_INPUT_STATUS_0_WORD_COUNT                        0x1
+#define VI_VIP_INPUT_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define VI_VIP_INPUT_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// The number of lines received (hsyncs)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_FIELD                  (_MK_MASK_CONST(0xffff) << VI_VIP_INPUT_STATUS_0_LINE_COUNT_SHIFT)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_RANGE                  15:0
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_WOFFSET                        0x0
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_LINE_COUNT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// The number of frames received (vsyncs)
+// Any write to this register, clears.
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_FIELD                 (_MK_MASK_CONST(0xffff) << VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SHIFT)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_RANGE                 31:16
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_WOFFSET                       0x0
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VIP_INPUT_STATUS_0_FRAME_COUNT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_VIDEO_BUFFER_STATUS_0  // Interrupt Enable
+#define VI_VIDEO_BUFFER_STATUS_0                        _MK_ADDR_CONST(0x52)
+#define VI_VIDEO_BUFFER_STATUS_0_SECURE                         0x0
+#define VI_VIDEO_BUFFER_STATUS_0_WORD_COUNT                     0x1
+#define VI_VIDEO_BUFFER_STATUS_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_READ_MASK                      _MK_MASK_CONST(0xfffff)
+#define VI_VIDEO_BUFFER_STATUS_0_WRITE_MASK                     _MK_MASK_CONST(0x0)
+// Buffer status
+//  This specifies the buffer number of the
+//  the last video data field written to memory
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_FIELD                        (_MK_MASK_CONST(0xff) << VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SHIFT)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_RANGE                        7:0
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_WOFFSET                      0x0
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_FIRST_VIDEO_BUFFER_STATUS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Buffer status
+//  This specifies the buffer number of the
+//  the last video data field written to memory
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_FIELD                       (_MK_MASK_CONST(0xff) << VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SHIFT)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_RANGE                       15:8
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_WOFFSET                     0x0
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_SECOND_VIDEO_BUFFER_STATUS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Write count of the Raw Stream Write FIFO
+//  This is the fifo used to synchronize the
+//  data coming from pads into the vi clock domain.
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_FIELD                   (_MK_MASK_CONST(0xf) << VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SHIFT)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_RANGE                   19:16
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_WOFFSET                 0x0
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VIDEO_BUFFER_STATUS_0_RAW_STREAM_WRITE_COUNT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// This register controls VHS and VVS output when H/V syncs are generated internally in the
+// VI module (VIDEO_SOURCE is VIP and SYNC_FORMAT is INTHVS).
+// The generated VHS and VVS signal can be sent to external video source device and used
+// to synchronize the video data transfer from the video source to the VI module. VHS and VVS
+// pin should be configured in output mode to output the internally generated H/V syncs.
+// Also in this case, the internally generate H/V syncs can be used by the VI module
+// as horizontal and vertical reference signals for the incoming video data.
+
+// Register VI_SYNC_OUTPUT_0  // VI H and V sync Output control
+#define VI_SYNC_OUTPUT_0                        _MK_ADDR_CONST(0x53)
+#define VI_SYNC_OUTPUT_0_SECURE                         0x0
+#define VI_SYNC_OUTPUT_0_WORD_COUNT                     0x1
+#define VI_SYNC_OUTPUT_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_SYNC_OUTPUT_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// This specifies VHS output pulse width in
+//  term of number of VI clock cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 1 to 8.
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_FIELD                 (_MK_MASK_CONST(0x7) << VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SHIFT)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_RANGE                 2:0
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_WOFFSET                       0x0
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This specifies VHS output pulse period in
+//  term of number of VI clock cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 32 to 8192.
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SHIFT                        _MK_SHIFT_CONST(3)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SHIFT)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_RANGE                        15:3
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_WOFFSET                      0x0
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VHS_OUTPUT_PERIOD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// This specifies VVS output pulse width in
+//  term of number of VHS cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 1 to 8.
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_FIELD                 (_MK_MASK_CONST(0x7) << VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SHIFT)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_RANGE                 18:16
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_WOFFSET                       0x0
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_WIDTH_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This specifies VVS output pulse period in
+//  term of number of VHS cycles.
+//  Programmed value is actual value - 1 so
+//  valid value ranges from 2 to 4096.
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SHIFT                        _MK_SHIFT_CONST(19)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SHIFT)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_RANGE                        31:19
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_WOFFSET                      0x0
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_SYNC_OUTPUT_0_VVS_OUTPUT_PERIOD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_VVS_OUTPUT_DELAY_0  // VI V sync Output Delay
+#define VI_VVS_OUTPUT_DELAY_0                   _MK_ADDR_CONST(0x54)
+#define VI_VVS_OUTPUT_DELAY_0_SECURE                    0x0
+#define VI_VVS_OUTPUT_DELAY_0_WORD_COUNT                        0x1
+#define VI_VVS_OUTPUT_DELAY_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_READ_MASK                         _MK_MASK_CONST(0xf)
+#define VI_VVS_OUTPUT_DELAY_0_WRITE_MASK                        _MK_MASK_CONST(0xf)
+// This specifies the number of VI clock cycles
+//  from leading edge of VHS to leading edge of
+//  VVS.
+//  Programmed value is actual value + 2 so
+//  valid value ranges from -2 to 13.
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_FIELD                    (_MK_MASK_CONST(0xf) << VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SHIFT)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_RANGE                    3:0
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_WOFFSET                  0x0
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_VVS_OUTPUT_DELAY_0_VVS_OUTPUT_DELAY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// VI Pulse Width Modulation signal generation
+// PWM signal generation logic can generate up to 128 pulses per line internally and the PWM
+//  pulse select registers determines which of the 128 pulses will be output. Any of the 128
+//  internally generated pulse can be independently selected as output if they occur within
+//  one line time.
+// PWM signal can be output on the VGP6 pin if VGP6 output is enabled and the output select
+//  is set to PWM.
+// The PWM will be triggered by the first vsync after the PWM_ENABLE bit has been set.
+
+// Register VI_PWM_CONTROL_0  // VI Pulse Width Modulation Control
+#define VI_PWM_CONTROL_0                        _MK_ADDR_CONST(0x55)
+#define VI_PWM_CONTROL_0_SECURE                         0x0
+#define VI_PWM_CONTROL_0_WORD_COUNT                     0x1
+#define VI_PWM_CONTROL_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_RESET_MASK                     _MK_MASK_CONST(0xff30ff11)
+#define VI_PWM_CONTROL_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_READ_MASK                      _MK_MASK_CONST(0xff30ff11)
+#define VI_PWM_CONTROL_0_WRITE_MASK                     _MK_MASK_CONST(0xff30ff11)
+// PWM Enable  0= Disabled
+//  1= Enabled
+#define VI_PWM_CONTROL_0_PWM_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << VI_PWM_CONTROL_0_PWM_ENABLE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_RANGE                       0:0
+#define VI_PWM_CONTROL_0_PWM_ENABLE_WOFFSET                     0x0
+#define VI_PWM_CONTROL_0_PWM_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+// PWM Direction  0= Incrementing
+//  1= Decrementing
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_SHIFT                    _MK_SHIFT_CONST(4)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_FIELD                    (_MK_MASK_CONST(0x1) << VI_PWM_CONTROL_0_PWM_DIRECTION_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_RANGE                    4:4
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_WOFFSET                  0x0
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_INCR                     _MK_ENUM_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_DIRECTION_DECR                     _MK_ENUM_CONST(1)
+
+// PWM High Pulse (1 to 16)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SHIFT                   _MK_SHIFT_CONST(8)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_FIELD                   (_MK_MASK_CONST(0xf) << VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_RANGE                   11:8
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_WOFFSET                 0x0
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_HIGH_PULSE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// PWM Low Pulse  (1 to 16)
+// 19:16 reserved
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_SHIFT                    _MK_SHIFT_CONST(12)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_FIELD                    (_MK_MASK_CONST(0xf) << VI_PWM_CONTROL_0_PWM_LOW_PULSE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_RANGE                    15:12
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_WOFFSET                  0x0
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_DEFAULT_MASK                     _MK_MASK_CONST(0xf)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_LOW_PULSE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// PWM Mode Continous - after PWM is turned on, continue
+//              through the PWM's 128 cycles
+//              repeatedly until the pwm is turned off.
+// Single - after PWM is turned on, cycle once through
+//          the 128 cycles and stop.
+// Counter - after PWM is turned on, cycle through
+//           the 128 cycles PWM_COUNTER number of
+//           times then stop.
+// 23:22 reserved
+#define VI_PWM_CONTROL_0_PWM_MODE_SHIFT                 _MK_SHIFT_CONST(20)
+#define VI_PWM_CONTROL_0_PWM_MODE_FIELD                 (_MK_MASK_CONST(0x3) << VI_PWM_CONTROL_0_PWM_MODE_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_MODE_RANGE                 21:20
+#define VI_PWM_CONTROL_0_PWM_MODE_WOFFSET                       0x0
+#define VI_PWM_CONTROL_0_PWM_MODE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_MODE_DEFAULT_MASK                  _MK_MASK_CONST(0x3)
+#define VI_PWM_CONTROL_0_PWM_MODE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_MODE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_MODE_CONTINUOUS                    _MK_ENUM_CONST(0)
+#define VI_PWM_CONTROL_0_PWM_MODE_SINGLE                        _MK_ENUM_CONST(1)
+#define VI_PWM_CONTROL_0_PWM_MODE_COUNTER                       _MK_ENUM_CONST(2)
+
+// PWM Counter
+//  8-bit value used when PWM_MODE is set to COUNTER
+//  to determine how many times the PWM will cycle
+//  through the 128 cycles
+//  before stopping.
+#define VI_PWM_CONTROL_0_PWM_COUNTER_SHIFT                      _MK_SHIFT_CONST(24)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_FIELD                      (_MK_MASK_CONST(0xff) << VI_PWM_CONTROL_0_PWM_COUNTER_SHIFT)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_RANGE                      31:24
+#define VI_PWM_CONTROL_0_PWM_COUNTER_WOFFSET                    0x0
+#define VI_PWM_CONTROL_0_PWM_COUNTER_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_DEFAULT_MASK                       _MK_MASK_CONST(0xff)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_CONTROL_0_PWM_COUNTER_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// The next 4 registers select which of the internal 128 pulses to be output.
+//  Each bit in the four registers correspond to one internal pulse.
+
+// Register VI_PWM_SELECT_PULSE_A_0  // PWM Pulse Select A
+#define VI_PWM_SELECT_PULSE_A_0                 _MK_ADDR_CONST(0x56)
+#define VI_PWM_SELECT_PULSE_A_0_SECURE                  0x0
+#define VI_PWM_SELECT_PULSE_A_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_A_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_A_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 31 to 0
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SHIFT)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_A_0_PWM_SELECT_A_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_SELECT_PULSE_B_0  // PWM Pulse Select B
+#define VI_PWM_SELECT_PULSE_B_0                 _MK_ADDR_CONST(0x57)
+#define VI_PWM_SELECT_PULSE_B_0_SECURE                  0x0
+#define VI_PWM_SELECT_PULSE_B_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_B_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_B_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 63 to 32
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SHIFT)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_B_0_PWM_SELECT_B_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_SELECT_PULSE_C_0  // PWM Pulse Select C
+#define VI_PWM_SELECT_PULSE_C_0                 _MK_ADDR_CONST(0x58)
+#define VI_PWM_SELECT_PULSE_C_0_SECURE                  0x0
+#define VI_PWM_SELECT_PULSE_C_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_C_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_C_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 95 to 64
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SHIFT)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_C_0_PWM_SELECT_C_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_PWM_SELECT_PULSE_D_0  // PWM Pulse Select D
+#define VI_PWM_SELECT_PULSE_D_0                 _MK_ADDR_CONST(0x59)
+#define VI_PWM_SELECT_PULSE_D_0_SECURE                  0x0
+#define VI_PWM_SELECT_PULSE_D_0_WORD_COUNT                      0x1
+#define VI_PWM_SELECT_PULSE_D_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_READ_MASK                       _MK_MASK_CONST(0xffffffff)
+#define VI_PWM_SELECT_PULSE_D_0_WRITE_MASK                      _MK_MASK_CONST(0xffffffff)
+// PWM Select bits 127 to 96
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_FIELD                      (_MK_MASK_CONST(0xffffffff) << VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SHIFT)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_RANGE                      31:0
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_WOFFSET                    0x0
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PWM_SELECT_PULSE_D_0_PWM_SELECT_D_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_VI_DATA_INPUT_CONTROL_0  // VI Input Mask
+#define VI_VI_DATA_INPUT_CONTROL_0                      _MK_ADDR_CONST(0x5a)
+#define VI_VI_DATA_INPUT_CONTROL_0_SECURE                       0x0
+#define VI_VI_DATA_INPUT_CONTROL_0_WORD_COUNT                   0x1
+#define VI_VI_DATA_INPUT_CONTROL_0_RESET_VAL                    _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_RESET_MASK                   _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VI_DATA_INPUT_CONTROL_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VI_DATA_INPUT_CONTROL_0_READ_MASK                    _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_WRITE_MASK                   _MK_MASK_CONST(0xfff)
+// Mask the VD[11:0] pin inputs to the VI core and ISP
+// The mask is not applied to the Host GPIO read value
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_FIELD                     (_MK_MASK_CONST(0xfff) << VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SHIFT)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_RANGE                     11:0
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_WOFFSET                   0x0
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_DEFAULT                   _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0xfff)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_DATA_INPUT_CONTROL_0_VI_DATA_INPUT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_PIN_INPUT_ENABLE_0  // VI pins Input Enable
+#define VI_PIN_INPUT_ENABLE_0                   _MK_ADDR_CONST(0x5b)
+#define VI_PIN_INPUT_ENABLE_0_SECURE                    0x0
+#define VI_PIN_INPUT_ENABLE_0_WORD_COUNT                        0x1
+#define VI_PIN_INPUT_ENABLE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_RESET_MASK                        _MK_MASK_CONST(0x3fefff)
+#define VI_PIN_INPUT_ENABLE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_READ_MASK                         _MK_MASK_CONST(0x3fefff)
+#define VI_PIN_INPUT_ENABLE_0_WRITE_MASK                        _MK_MASK_CONST(0x3fefff)
+// VD0 pin Input Enable  This bit controls VD0 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_RANGE                    0:0
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD0_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD1 pin Input Enable  This bit controls VD1 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(1)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_RANGE                    1:1
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD1_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD2 pin Input Enable  This bit controls VD2 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(2)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_RANGE                    2:2
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD2_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD3 pin Input Enable  This bit controls VD3 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(3)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_RANGE                    3:3
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD3_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD4 pin Input Enable  This bit controls VD4 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(4)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_RANGE                    4:4
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD4_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD5 pin Input Enable  This bit controls VD5 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(5)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_RANGE                    5:5
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD5_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD6 pin Input Enable  This bit controls VD6 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(6)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_RANGE                    6:6
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD6_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD7 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(7)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_RANGE                    7:7
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD7_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD8 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_RANGE                    8:8
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD8_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD9 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(9)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_RANGE                    9:9
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD9_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VD10 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(10)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_RANGE                   10:10
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD10_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VD11 pin Input Enable  This bit controls VD7 pin input.
+//   0= Disabled
+//   1= Enabled
+// 12 reserved
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(11)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_RANGE                   11:11
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VD11_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VHS pin Input Enable  This bit controls VHS pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(13)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_RANGE                    13:13
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VHS_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VVS pin Input Enable  This bit controls VVS pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SHIFT                    _MK_SHIFT_CONST(14)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_RANGE                    14:14
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_WOFFSET                  0x0
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VVS_INPUT_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// VGP0 pin Input Enable  This bit controls VGP0 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(15)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_RANGE                   15:15
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP0_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP1 pin Input Enable  This bit controls VGP1 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_RANGE                   16:16
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP1_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP2 pin Input Enable  This bit controls VGP2 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(17)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_RANGE                   17:17
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP2_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP3 pin Input Enable  This bit controls VGP3 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(18)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_RANGE                   18:18
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP3_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP4 pin Input Enable  This bit controls VGP4 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(19)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_RANGE                   19:19
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP4_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP5 pin Input Enable  This bit controls VGP5 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(20)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_RANGE                   20:20
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP5_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+// VGP6 pin Input Enable  This bit controls VGP6 pin input.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SHIFT                   _MK_SHIFT_CONST(21)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SHIFT)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_RANGE                   21:21
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_WOFFSET                 0x0
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_DISABLED                        _MK_ENUM_CONST(0)
+#define VI_PIN_INPUT_ENABLE_0_VGP6_INPUT_ENABLE_ENABLED                 _MK_ENUM_CONST(1)
+
+
+// Register VI_PIN_OUTPUT_ENABLE_0  // VI pins Output Enable
+#define VI_PIN_OUTPUT_ENABLE_0                  _MK_ADDR_CONST(0x5c)
+#define VI_PIN_OUTPUT_ENABLE_0_SECURE                   0x0
+#define VI_PIN_OUTPUT_ENABLE_0_WORD_COUNT                       0x1
+#define VI_PIN_OUTPUT_ENABLE_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_RESET_MASK                       _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_ENABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_READ_MASK                        _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_ENABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffff)
+// VD0 pin Output Enable  This bit controls VD0 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_RANGE                  0:0
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD0_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD1 pin Output Enable  This bit controls VD1 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_RANGE                  1:1
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD1_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD2 pin Output Enable  This bit controls VD2 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_RANGE                  2:2
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD2_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD3 pin Output Enable  This bit controls VD3 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(3)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_RANGE                  3:3
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD3_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD4 pin Output Enable  This bit controls VD4 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(4)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_RANGE                  4:4
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD4_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD5 pin Output Enable  This bit controls VD5 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(5)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_RANGE                  5:5
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD5_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD6 pin Output Enable  This bit controls VD6 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(6)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_RANGE                  6:6
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD6_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD7 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(7)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_RANGE                  7:7
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD7_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD8 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(8)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_RANGE                  8:8
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD8_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD9 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(9)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_RANGE                  9:9
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD9_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VD10 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(10)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_RANGE                 10:10
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD10_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VD11 pin Output Enable  This bit controls VD7 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(11)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_RANGE                 11:11
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VD11_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VSCK pin Output Enable  This bit controls VSCK pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(12)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_RANGE                 12:12
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VSCK_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VHS pin Output Enable  This bit controls VHS pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(13)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_RANGE                  13:13
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VHS_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VVS pin Output Enable  This bit controls VVS pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SHIFT                  _MK_SHIFT_CONST(14)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_FIELD                  (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_RANGE                  14:14
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_WOFFSET                        0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VVS_OUTPUT_ENABLE_ENABLED                        _MK_ENUM_CONST(1)
+
+// VGP0 pin Output Enable  This bit controls VGP0 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(15)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_RANGE                 15:15
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP0_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP1 pin Output Enable  This bit controls VGP1 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_RANGE                 16:16
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP1_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP2 pin Output Enable  This bit controls VGP2 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(17)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_RANGE                 17:17
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP2_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP3 pin Output Enable  This bit controls VGP3 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(18)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_RANGE                 18:18
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP3_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP4 pin Output Enable  This bit controls VGP4 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(19)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_RANGE                 19:19
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP4_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP5 pin Output Enable  This bit controls VGP5 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(20)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_RANGE                 20:20
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP5_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+// VGP6 pin Output Enable  This bit controls VGP6 pin output.
+//   0= Disabled
+//   1= Enabled
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SHIFT                 _MK_SHIFT_CONST(21)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_FIELD                 (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SHIFT)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_RANGE                 21:21
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_WOFFSET                       0x0
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_DISABLED                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_ENABLE_0_VGP6_OUTPUT_ENABLE_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register VI_PIN_INVERSION_0  // VI pins input/output Inversion
+//    0  reserved
+#define VI_PIN_INVERSION_0                      _MK_ADDR_CONST(0x5d)
+#define VI_PIN_INVERSION_0_SECURE                       0x0
+#define VI_PIN_INVERSION_0_WORD_COUNT                   0x1
+#define VI_PIN_INVERSION_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_RESET_MASK                   _MK_MASK_CONST(0x70006)
+#define VI_PIN_INVERSION_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_READ_MASK                    _MK_MASK_CONST(0x70006)
+#define VI_PIN_INVERSION_0_WRITE_MASK                   _MK_MASK_CONST(0x70006)
+// VHS pin Input Inversion   0= VHS input is not inverted
+//      (VHS input is active high)
+//   1= VHS input is inverted
+//      (VHS input is active low)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_SHIFT                       _MK_SHIFT_CONST(1)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VHS_IN_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_RANGE                       1:1
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_WOFFSET                     0x0
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VHS_IN_INVERSION_ENABLED                     _MK_ENUM_CONST(1)
+
+// VVS pin Input Inversion   0= VVS input is not inverted
+//      (VVS input is active high)
+//   1= VVS input is inverted
+//      (VVS input is active low)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_SHIFT                       _MK_SHIFT_CONST(2)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VVS_IN_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_RANGE                       2:2
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_WOFFSET                     0x0
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VVS_IN_INVERSION_ENABLED                     _MK_ENUM_CONST(1)
+
+// VSCK pin Output Inversion   0= VSCK output is not inverted
+//   1= VSCK output is inverted
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_RANGE                     16:16
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_WOFFSET                   0x0
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_DISABLED                  _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VSCK_OUT_INVERSION_ENABLED                   _MK_ENUM_CONST(1)
+
+// VHS pin Output Inversion   0= VHS output is not inverted
+//      (VHS output is active high)
+//   1= VHS output is inverted
+//      (VHS output is active low)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SHIFT                      _MK_SHIFT_CONST(17)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_RANGE                      17:17
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_WOFFSET                    0x0
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VHS_OUT_INVERSION_ENABLED                    _MK_ENUM_CONST(1)
+
+// VVS pin Output Inversion   0= VVS output is not inverted
+//      (VVS output is active high)
+//   1= VVS output is inverted
+//      (VVS output is active low)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SHIFT                      _MK_SHIFT_CONST(18)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SHIFT)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_RANGE                      18:18
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_WOFFSET                    0x0
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_PIN_INVERSION_0_VVS_OUT_INVERSION_ENABLED                    _MK_ENUM_CONST(1)
+
+// This register contains input data when the video camera interface pins are used as
+// general-purpose input pins. The pin data read from this register is not affected by
+// the pin input inversion bits.
+
+// Register VI_PIN_INPUT_DATA_0  // VI pins Input Data
+#define VI_PIN_INPUT_DATA_0                     _MK_ADDR_CONST(0x5e)
+#define VI_PIN_INPUT_DATA_0_SECURE                      0x0
+#define VI_PIN_INPUT_DATA_0_WORD_COUNT                  0x1
+#define VI_PIN_INPUT_DATA_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_READ_MASK                   _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_INPUT_DATA_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// VD0 pin Input Data
+//  (effective if VD0_INPUT_ENABLE is ENABLED)
+//   0= VD0 input low
+//   1= VD0 input high
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_RANGE                        0:0
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD0_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD1 pin Input Data
+//  (effective if VD1_INPUT_ENABLE is ENABLED)
+//   0= VD1 input low
+//   1= VD1 input high
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_RANGE                        1:1
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD1_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD2 pin Input Data
+//  (effective if VD2_INPUT_ENABLE is ENABLED)
+//   0= VD2 input low
+//   1= VD2 input high
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(2)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_RANGE                        2:2
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD2_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD3 pin Input Data
+//  (effective if VD3_INPUT_ENABLE is ENABLED)
+//   0= VD3 input low
+//   1= VD3 input high
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(3)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_RANGE                        3:3
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD3_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD4 pin Input Data
+//  (effective if VD4_INPUT_ENABLE is ENABLED)
+//   0= VD4 input low
+//   1= VD4 input high
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(4)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_RANGE                        4:4
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD4_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD5 pin Input Data
+//  (effective if VD5_INPUT_ENABLE is ENABLED)
+//   0= VD5 input low
+//   1= VD5 input high
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(5)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_RANGE                        5:5
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD5_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD6 pin Input Data
+//  (effective if VD6_INPUT_ENABLE is ENABLED)
+//   0= VD6 input low
+//   1= VD6 input high
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(6)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_RANGE                        6:6
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD6_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD7 pin Input Data
+//  (effective if VD7_INPUT_ENABLE is ENABLED)
+//   0= VD7 input low
+//   1= VD7 input high
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(7)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_RANGE                        7:7
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD7_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD8 pin Input Data
+//  (effective if VD8_INPUT_ENABLE is ENABLED)
+//   0= VD8 input low
+//   1= VD8 input high
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_RANGE                        8:8
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD8_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD9 pin Input Data
+//  (effective if VD9_INPUT_ENABLE is ENABLED)
+//   0= VD9 input low
+//   1= VD9 input high
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(9)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_RANGE                        9:9
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD9_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VD10 pin Input Data
+//  (effective if VD10_INPUT_ENABLE is ENABLED)
+//   0= VD10 input low
+//   1= VD10 input high
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(10)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_RANGE                       10:10
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD10_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VD11 pin Input Data
+//  (effective if VD11_INPUT_ENABLE is ENABLED)
+//   0= VD11 input low
+//   1= VD11 input high
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(11)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_RANGE                       11:11
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VD11_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VSCK pin Input Data
+//  (effective if VSCK_INPUT_ENABLE is ENABLED)
+//   0= VSCK input low
+//   1= VSCK input high
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(12)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_RANGE                       12:12
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VSCK_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VHS pin Input Data
+//  (effective if VHS_INPUT_ENABLE is ENABLED)
+//   0= VHS input low
+//   1= VHS input high
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(13)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_RANGE                        13:13
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VHS_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VVS pin Input Data
+//  (effective if VVS_INPUT_ENABLE is ENABLED)
+//   0= VVS input low
+//   1= VVS input high
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SHIFT                        _MK_SHIFT_CONST(14)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_FIELD                        (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_RANGE                        14:14
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_WOFFSET                      0x0
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VVS_INPUT_DATA_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// VGP0 pin Input Data
+//  (effective if VGP0_INPUT_ENABLE is ENABLED)
+//   0= VGP0 input low
+//   1= VGP0 input high
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(15)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_RANGE                       15:15
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP0_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP1 pin Input Data
+//  (effective if VGP1_INPUT_ENABLE is ENABLED)
+//   0= VGP1 input low
+//   1= VGP1 input high
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(16)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_RANGE                       16:16
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP1_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP2 pin Input Data
+//  (effective if VGP2_INPUT_ENABLE is ENABLED)
+//   0= VGP2 input low
+//   1= VGP2 input high
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(17)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_RANGE                       17:17
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP2_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP3 pin Input Data
+//  (effective if VGP3_INPUT_ENABLE is ENABLED)
+//   0= VGP3 input low
+//   1= VGP3 input high
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(18)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_RANGE                       18:18
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP3_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP4 pin Input Data
+//  (effective if VGP4_INPUT_ENABLE is ENABLED)
+//   0= VGP4 input low
+//   1= VGP4 input high
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(19)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_RANGE                       19:19
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP4_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP5 pin Input Data
+//  (effective if VGP5_INPUT_ENABLE is ENABLED)
+//   0= VGP5 input low
+//   1= VGP5 input high
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(20)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_RANGE                       20:20
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP5_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// VGP6 pin Input Data
+//  (effective if VGP6_INPUT_ENABLE is ENABLED)
+//   0= VGP6 input low
+//   1= VGP6 input high
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SHIFT                       _MK_SHIFT_CONST(21)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_FIELD                       (_MK_MASK_CONST(0x1) << VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SHIFT)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_RANGE                       21:21
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_WOFFSET                     0x0
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_PIN_INPUT_DATA_0_VGP6_INPUT_DATA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// This register contains output data when the video camera interface pins are used as
+// general-purpose output pins. When a bit in this register is written, the data bits can be
+// output on the corresponding pin if the corresponding pin output buffer is enabled and the
+// pin output control select bits are programmed to output the bit in this register.
+// The output signal at the pin IS affected by the corresponding pin output inversion bit.
+
+// Register VI_PIN_OUTPUT_DATA_0  // VI pins Output Data
+#define VI_PIN_OUTPUT_DATA_0                    _MK_ADDR_CONST(0x5f)
+#define VI_PIN_OUTPUT_DATA_0_SECURE                     0x0
+#define VI_PIN_OUTPUT_DATA_0_WORD_COUNT                         0x1
+#define VI_PIN_OUTPUT_DATA_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_READ_MASK                  _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_DATA_0_WRITE_MASK                         _MK_MASK_CONST(0x3fffff)
+// VD0 pin Output Data
+//  (effective if VD0_OUTPUT_ENABLE is ENABLED
+//   and VD0_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_RANGE                      0:0
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD0_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD1 pin Output Data
+//  (effective if VD1_OUTPUT_ENABLE is ENABLED
+//   and VD1_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_RANGE                      1:1
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD1_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD2 pin Output Data
+//  (effective if VD2_OUTPUT_ENABLE is ENABLED
+//   and VD2_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_RANGE                      2:2
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD2_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD3 pin Output Data
+//  (effective if VD3_OUTPUT_ENABLE is ENABLED
+//   and VD3_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(3)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_RANGE                      3:3
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD3_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD4 pin Output Data
+//  (effective if VD4_OUTPUT_ENABLE is ENABLED
+//   and VD4_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(4)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_RANGE                      4:4
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD4_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD5 pin Output Data
+//  (effective if VD5_OUTPUT_ENABLE is ENABLED
+//   and VD5_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(5)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_RANGE                      5:5
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD5_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD6 pin Output Data
+//  (effective if VD6_OUTPUT_ENABLE is ENABLED
+//   and VD6_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(6)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_RANGE                      6:6
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD6_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD7 pin Output Data
+//  (effective if VD7_OUTPUT_ENABLE is ENABLED
+//   and VD7_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_RANGE                      7:7
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD7_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD8 pin Output Data
+//  (effective if VD8_OUTPUT_ENABLE is ENABLED
+//   and VD8_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(8)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_RANGE                      8:8
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD8_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD9 pin Output Data
+//  (effective if VD9_OUTPUT_ENABLE is ENABLED
+//   and VD9_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(9)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_RANGE                      9:9
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD9_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VD10 pin Output Data
+//  (effective if VD10_OUTPUT_ENABLE is ENABLED
+//   and VD10_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(10)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_RANGE                     10:10
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD10_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VD11 pin Output Data
+//  (effective if VD11_OUTPUT_ENABLE is ENABLED
+//   and VD11_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(11)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_RANGE                     11:11
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VD11_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VSCK pin Output Data
+//  (effective if VSCK_OUTPUT_ENABLE is ENABLED
+//   and VSCK_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_RANGE                     12:12
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VSCK_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VHS pin Output Data
+//  (effective if VHS_OUTPUT_ENABLE is ENABLED
+//   and VHS_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(13)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_RANGE                      13:13
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VHS_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VVS pin Output Data
+//  (effective if VVS_OUTPUT_ENABLE is ENABLED
+//   and VVS_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SHIFT                      _MK_SHIFT_CONST(14)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_RANGE                      14:14
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VVS_OUTPUT_DATA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VGP0 pin Output Data
+//  (effective if VGP0_OUTPUT_ENABLE is ENABLED
+//   and VGP0_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(15)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_RANGE                     15:15
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP0_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP1 pin Output Data
+//  (effective if VGP1_OUTPUT_ENABLE is ENABLED
+//   and VGP1_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_RANGE                     16:16
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP1_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP2 pin Output Data
+//  (effective if VGP2_OUTPUT_ENABLE is ENABLED
+//   and VGP2_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(17)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_RANGE                     17:17
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP2_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP3 pin Output Data
+//  (effective if VGP3_OUTPUT_ENABLE is ENABLED
+//   and VGP3_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(18)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_RANGE                     18:18
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP3_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP4 pin Output Data
+//  (effective if VGP4_OUTPUT_ENABLE is ENABLED
+//   and VGP4_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(19)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_RANGE                     19:19
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP4_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP5 pin Output Data
+//  (effective if VGP5_OUTPUT_ENABLE is ENABLED
+//   and VGP5_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(20)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_RANGE                     20:20
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP5_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// VGP6 pin Output Data
+//  (effective if VGP6_OUTPUT_ENABLE is ENABLED
+//   and VGP6_OUTPUT_SELECT is DATA)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SHIFT                     _MK_SHIFT_CONST(21)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SHIFT)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_RANGE                     21:21
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_DATA_0_VGP6_OUTPUT_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_PIN_OUTPUT_SELECT_0  // VI pins Output Select
+// This is the mux select used at the Pad Macro
+// For VCLK, VHSYNC, VVSYNC
+// Selects between the register programmed GPIO outputs (set to 0)
+// and the internally generated viclk, hsync, vsync (set to 1)
+// For VGP1-VGP2
+// Selects between the I^2C outputs (set to 0)
+// and the VI register programmed GPIO outputs (set to 1)
+// For VD0-VD11
+// Reserved for future use
+// data pins output will be driven by GPIO outputs if enabled
+#define VI_PIN_OUTPUT_SELECT_0                  _MK_ADDR_CONST(0x60)
+#define VI_PIN_OUTPUT_SELECT_0_SECURE                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_WORD_COUNT                       0x1
+#define VI_PIN_OUTPUT_SELECT_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_RESET_MASK                       _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_SELECT_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_READ_MASK                        _MK_MASK_CONST(0x3fffff)
+#define VI_PIN_OUTPUT_SELECT_0_WRITE_MASK                       _MK_MASK_CONST(0x3fffff)
+// Pin Output Select VD0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_RANGE                      0:0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD1
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_RANGE                      1:1
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD2
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_RANGE                      2:2
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD3
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SHIFT                      _MK_SHIFT_CONST(3)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_RANGE                      3:3
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd3_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD4
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SHIFT                      _MK_SHIFT_CONST(4)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_RANGE                      4:4
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd4_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD5
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SHIFT                      _MK_SHIFT_CONST(5)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_RANGE                      5:5
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd5_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD6
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SHIFT                      _MK_SHIFT_CONST(6)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_RANGE                      6:6
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd6_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD7
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_RANGE                      7:7
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd7_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD8
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SHIFT                      _MK_SHIFT_CONST(8)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_RANGE                      8:8
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd8_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD9
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SHIFT                      _MK_SHIFT_CONST(9)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_RANGE                      9:9
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd9_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD10
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SHIFT                     _MK_SHIFT_CONST(10)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_RANGE                     10:10
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd10_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VD11
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SHIFT                     _MK_SHIFT_CONST(11)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_RANGE                     11:11
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vd11_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VCLK
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_RANGE                     12:12
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vclk_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VHSYNC
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SHIFT                      _MK_SHIFT_CONST(13)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_RANGE                      13:13
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vhs_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VVSYNC
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SHIFT                      _MK_SHIFT_CONST(14)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_FIELD                      (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_RANGE                      14:14
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_WOFFSET                    0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vvs_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP0
+//  0 = VGP0 output register
+//  1 = refclk
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SHIFT                     _MK_SHIFT_CONST(15)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_RANGE                     15:15
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP1
+//  0 = I^2C SCK pin
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_RANGE                     16:16
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP2
+//  0 = I^2C SDA pin
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SHIFT                     _MK_SHIFT_CONST(17)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_RANGE                     17:17
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP3
+//  0 = VGP3 output register
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SHIFT                     _MK_SHIFT_CONST(18)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_RANGE                     18:18
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP4
+//  0 = VGP4 output register
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SHIFT                     _MK_SHIFT_CONST(19)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_RANGE                     19:19
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp4_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP5
+//  0 = VGP5 output register
+//  1 = 1'b0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SHIFT                     _MK_SHIFT_CONST(20)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_RANGE                     20:20
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp5_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Pin Output Select VGP6   0= select VGP6 register data out
+//   1= select PWM out
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SHIFT                     _MK_SHIFT_CONST(21)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_FIELD                     (_MK_MASK_CONST(0x1) << VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SHIFT)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_RANGE                     21:21
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_WOFFSET                   0x0
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_DATA                      _MK_ENUM_CONST(0)
+#define VI_PIN_OUTPUT_SELECT_0_PIN_OUTPUT_SELECT_vgp6_PWM                       _MK_ENUM_CONST(1)
+
+// raise vectors are received from host. If host is the input source, host will send
+// a raise vector at the end of a line, and VI return it when that has been written to memory.
+// A raise written when decimation or averaging is selected in vi, is not supported.
+// If Video Input Port is the input source, host should program raise vectors to either raise
+// at buffer end or at frame end.
+// Since there are 2 memory outputs for vi, there are two separate raise vectors for buffer/frame.
+
+// Register VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0  // raise vector at buffer end
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0                      _MK_ADDR_CONST(0x61)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_SECURE                       0x0
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_WORD_COUNT                   0x1
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_READ_MASK                    _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_WRITE_MASK                   _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_FIELD                  (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SHIFT)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_RANGE                  4:0
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_WOFFSET                        0x0
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_VECTOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_FIELD                 (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_RANGE                 19:16
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_WOFFSET                       0x0
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0_RAISE_BUFFER_1_CHANNEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0  // raise vector at frame end
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0                       _MK_ADDR_CONST(0x62)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_SECURE                        0x0
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_WORD_COUNT                    0x1
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_READ_MASK                     _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_WRITE_MASK                    _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_FIELD                    (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SHIFT)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_RANGE                    4:0
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_WOFFSET                  0x0
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_VECTOR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_FIELD                   (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_RANGE                   19:16
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_WOFFSET                 0x0
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0_RAISE_FRAME_1_CHANNEL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0  // raise vector at buffer end
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0                     _MK_ADDR_CONST(0x63)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_SECURE                      0x0
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_WORD_COUNT                  0x1
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_READ_MASK                   _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_WRITE_MASK                  _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_FIELD                 (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SHIFT)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_RANGE                 4:0
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_WOFFSET                       0x0
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_FIELD                        (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_RANGE                        19:16
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_WOFFSET                      0x0
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0_RAISE_BUFFER_2_CHANNEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0  // raise vector at frame end
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0                      _MK_ADDR_CONST(0x64)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_SECURE                       0x0
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_WORD_COUNT                   0x1
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RESET_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_READ_MASK                    _MK_MASK_CONST(0x1f)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_WRITE_MASK                   _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SHIFT)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_RANGE                   4:0
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_WOFFSET                 0x0
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SHIFT)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_RANGE                  19:16
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_WOFFSET                        0x0
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0_RAISE_FRAME_2_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_HOST_FIRST_OUTPUT_0  // raise vector when from host
+#define VI_RAISE_HOST_FIRST_OUTPUT_0                    _MK_ADDR_CONST(0x65)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_SECURE                     0x0
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_WORD_COUNT                         0x1
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_READ_MASK                  _MK_MASK_CONST(0x1f)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_WRITE_MASK                         _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_FIELD                  (_MK_MASK_CONST(0x1f) << VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SHIFT)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_RANGE                  4:0
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_WOFFSET                        0x0
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_VECTOR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_FIELD                 (_MK_MASK_CONST(0xf) << VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SHIFT)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_RANGE                 19:16
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_WOFFSET                       0x0
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_FIRST_OUTPUT_0_RAISE_HOST_1_CHANNEL_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_HOST_SECOND_OUTPUT_0  // raise vector when from host
+#define VI_RAISE_HOST_SECOND_OUTPUT_0                   _MK_ADDR_CONST(0x66)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_SECURE                    0x0
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_WORD_COUNT                        0x1
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_READ_MASK                         _MK_MASK_CONST(0x1f)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_WRITE_MASK                        _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_FIELD                 (_MK_MASK_CONST(0x1f) << VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SHIFT)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_RANGE                 4:0
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_WOFFSET                       0x0
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_VECTOR_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SHIFT                        _MK_SHIFT_CONST(16)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_FIELD                        (_MK_MASK_CONST(0xf) << VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SHIFT)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_RANGE                        19:16
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_WOFFSET                      0x0
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_HOST_SECOND_OUTPUT_0_RAISE_HOST_2_CHANNEL_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// EPP receives the raise request via the Simple Stream Video Data bus
+// see arepp.spec for details
+// This raise needs to be written during the horizontal blanking period. (After end of line.)
+// This is only valid if the input source is host.
+
+// Register VI_RAISE_EPP_0  // raise vector at line end
+#define VI_RAISE_EPP_0                  _MK_ADDR_CONST(0x67)
+#define VI_RAISE_EPP_0_SECURE                   0x0
+#define VI_RAISE_EPP_0_WORD_COUNT                       0x1
+#define VI_RAISE_EPP_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_READ_MASK                        _MK_MASK_CONST(0x1f)
+#define VI_RAISE_EPP_0_WRITE_MASK                       _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SHIFT)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_RANGE                   4:0
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_WOFFSET                 0x0
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SHIFT)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_RANGE                  19:16
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_WOFFSET                        0x0
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_EPP_0_RAISE_EPP_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// For Parallel VIP input, limitation for vsync and hsync has to be followed to avoid ISP hang for AP15:
+// SW must always program parallel cameras (including the VIP pattern generator) in a way that
+// avoids simultaneous hsync and vsync active edges. copied from bug:361730
+
+// Register VI_CAMERA_CONTROL_0  // VI camera control bits
+#define VI_CAMERA_CONTROL_0                     _MK_ADDR_CONST(0x68)
+#define VI_CAMERA_CONTROL_0_SECURE                      0x0
+#define VI_CAMERA_CONTROL_0_WORD_COUNT                  0x1
+#define VI_CAMERA_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x7)
+#define VI_CAMERA_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0x7)
+#define VI_CAMERA_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x6)
+// VI camera input module Enable   0= Ignored - use the STOP_CAPTURE to turn off the capturing
+//   1= Enabled
+// Write a 1'b1 to this register to enable
+// the camera interface to start capturing data.
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << VI_CAMERA_CONTROL_0_VIP_ENABLE_SHIFT)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_RANGE                    0:0
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_WOFFSET                  0x0
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_DISABLED                 _MK_ENUM_CONST(0)
+#define VI_CAMERA_CONTROL_0_VIP_ENABLE_ENABLED                  _MK_ENUM_CONST(1)
+
+// Test Mode Enable   0= Disabled
+//   1= Enabled
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SHIFT                      _MK_SHIFT_CONST(1)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_FIELD                      (_MK_MASK_CONST(0x1) << VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SHIFT)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_RANGE                      1:1
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_WOFFSET                    0x0
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_DISABLED                   _MK_ENUM_CONST(0)
+#define VI_CAMERA_CONTROL_0_TEST_MODE_ENABLE_ENABLED                    _MK_ENUM_CONST(1)
+
+// Disables camera capturing VI_ENABLE after the  next end of frame.
+//   0= Disabled
+//   1= Enabled
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_SHIFT                  _MK_SHIFT_CONST(2)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_FIELD                  (_MK_MASK_CONST(0x1) << VI_CAMERA_CONTROL_0_STOP_CAPTURE_SHIFT)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_RANGE                  2:2
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_WOFFSET                        0x0
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_DISABLED                       _MK_ENUM_CONST(0)
+#define VI_CAMERA_CONTROL_0_STOP_CAPTURE_ENABLED                        _MK_ENUM_CONST(1)
+
+// **** Enable bit should be to host together with other module enables in NV flow.
+// **** Test mode is not needed in NV flow but the enable bit can be replaced with debug bus
+//      enable.
+
+// Register VI_VI_ENABLE_0  // VI Enables
+#define VI_VI_ENABLE_0                  _MK_ADDR_CONST(0x69)
+#define VI_VI_ENABLE_0_SECURE                   0x0
+#define VI_VI_ENABLE_0_WORD_COUNT                       0x1
+#define VI_VI_ENABLE_0_RESET_VAL                        _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_RESET_MASK                       _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_READ_MASK                        _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_0_WRITE_MASK                       _MK_MASK_CONST(0x3)
+// First Output to Memory   0= Enabled
+//   1= Disabled
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SHIFT)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_RANGE                     0:0
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_WOFFSET                   0x0
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_DEFAULT                   _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_ENABLED                   _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_0_FIRST_OUTPUT_TO_MEMORY_DISABLED                  _MK_ENUM_CONST(1)
+
+// SW enable flow control for output1
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SHIFT                       _MK_SHIFT_CONST(1)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SHIFT)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_RANGE                       1:1
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_WOFFSET                     0x0
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_0_SW_FLOW_CONTROL_OUT1_ENABLE                      _MK_ENUM_CONST(1)
+
+
+// Register VI_VI_ENABLE_2_0  // VI Enables second output
+#define VI_VI_ENABLE_2_0                        _MK_ADDR_CONST(0x6a)
+#define VI_VI_ENABLE_2_0_SECURE                         0x0
+#define VI_VI_ENABLE_2_0_WORD_COUNT                     0x1
+#define VI_VI_ENABLE_2_0_RESET_VAL                      _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_RESET_MASK                     _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_2_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_READ_MASK                      _MK_MASK_CONST(0x3)
+#define VI_VI_ENABLE_2_0_WRITE_MASK                     _MK_MASK_CONST(0x3)
+// Second Output to Memory   0= Enabled
+//   1= Disabled
+//  Disabling output to memory may be set
+//  if only output to encoder pre-processor
+//  is needed. This will also power-down
+//  all logic which is only used to send
+//  output data to memory.
+//   0= Disabled
+//   1= Enabled
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_FIELD                  (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SHIFT)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_RANGE                  0:0
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_WOFFSET                        0x0
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_DEFAULT                        _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_ENABLED                        _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_2_0_SECOND_OUTPUT_TO_MEMORY_DISABLED                       _MK_ENUM_CONST(1)
+
+// SW enable flow control for output2
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SHIFT                     _MK_SHIFT_CONST(1)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_FIELD                     (_MK_MASK_CONST(0x1) << VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SHIFT)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_RANGE                     1:1
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_WOFFSET                   0x0
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_DISABLE                   _MK_ENUM_CONST(0)
+#define VI_VI_ENABLE_2_0_SW_FLOW_CONTROL_OUT2_ENABLE                    _MK_ENUM_CONST(1)
+
+
+// Register VI_VI_RAISE_0  // VI Enables second output
+#define VI_VI_RAISE_0                   _MK_ADDR_CONST(0x6b)
+#define VI_VI_RAISE_0_SECURE                    0x0
+#define VI_VI_RAISE_0_WORD_COUNT                        0x1
+#define VI_VI_RAISE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RESET_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_RAISE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_READ_MASK                         _MK_MASK_CONST(0x1)
+#define VI_VI_RAISE_0_WRITE_MASK                        _MK_MASK_CONST(0x1)
+// Makes Raises edge triggered not level sensitive  i.e. only return raise at the end of frame, not
+//  in the middle of the v-blank time.
+//   0= Disabled
+//   1= Enabled
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_RAISE_0_RAISE_ON_EDGE_SHIFT)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_RANGE                       0:0
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_WOFFSET                     0x0
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_VI_RAISE_0_RAISE_ON_EDGE_ENABLED                     _MK_ENUM_CONST(1)
+
+// **** Host YUV FIFO offsets.  This register space is used for Host Video Data writes.
+// **** YUV 4:2:0 planar for re-encoding as well as YUV 4:2:2 data
+
+// Register VI_Y_FIFO_WRITE_0  // YUV 4:2:0 Planar Y-FIFO, YUV 4:2:2 non-Planar YUV FIFO
+#define VI_Y_FIFO_WRITE_0                       _MK_ADDR_CONST(0x6c)
+#define VI_Y_FIFO_WRITE_0_SECURE                        0x0
+#define VI_Y_FIFO_WRITE_0_WORD_COUNT                    0x1
+#define VI_Y_FIFO_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_Y_FIFO_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define VI_Y_FIFO_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SHIFT)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_RANGE                     31:0
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_WOFFSET                   0x0
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_Y_FIFO_WRITE_0_Y_FIFO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_U_FIFO_WRITE_0  // YUV 4:2:0 Planar U-FIFO
+#define VI_U_FIFO_WRITE_0                       _MK_ADDR_CONST(0x6d)
+#define VI_U_FIFO_WRITE_0_SECURE                        0x0
+#define VI_U_FIFO_WRITE_0_WORD_COUNT                    0x1
+#define VI_U_FIFO_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_U_FIFO_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define VI_U_FIFO_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << VI_U_FIFO_WRITE_0_U_FIFO_DATA_SHIFT)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_RANGE                     31:0
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_WOFFSET                   0x0
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_U_FIFO_WRITE_0_U_FIFO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_V_FIFO_WRITE_0  // YUV 4:2:0 Planar V-FIFO
+#define VI_V_FIFO_WRITE_0                       _MK_ADDR_CONST(0x6e)
+#define VI_V_FIFO_WRITE_0_SECURE                        0x0
+#define VI_V_FIFO_WRITE_0_WORD_COUNT                    0x1
+#define VI_V_FIFO_WRITE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_RESET_MASK                    _MK_MASK_CONST(0xffffffff)
+#define VI_V_FIFO_WRITE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_READ_MASK                     _MK_MASK_CONST(0xffffffff)
+#define VI_V_FIFO_WRITE_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_FIELD                     (_MK_MASK_CONST(0xffffffff) << VI_V_FIFO_WRITE_0_V_FIFO_DATA_SHIFT)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_RANGE                     31:0
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_WOFFSET                   0x0
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_DEFAULT_MASK                      _MK_MASK_CONST(0xffffffff)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_V_FIFO_WRITE_0_V_FIFO_DATA_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Memory Client Interface Async Fifo Optimization Register
+// Memory Client Interface Fifo Control Register.
+// The registers below allow to optimize the synchronization timing in
+// the memory client asynchronous fifos. When they can be used depend on
+// the client and memory controller clock ratio.
+// Additionally, the RDMC_RDFAST/RDCL_RDFAST fields can increase power
+// consumption if the asynchronous fifo is implemented as a real ram.
+// There is no power impact on latch-based fifos. Flipflop-based fifos
+// do not use these fields.
+// See recommended settings below.
+//
+// !! IMPORTANT !!
+// The register fields can only be changed when the memory client async
+// fifos are empty.
+//
+// The register field ending with WRCL_MCLE2X (if any) can be set to improve
+// async fifo synchronization on the write side by one client clock cycle if
+// the memory controller clock frequency is less or equal to twice the client
+// clock frequency:
+//
+//      mcclk_freq <= 2 * clientclk_freq
+//
+// The register field ending with WRMC_CLLE2X (if any) can be set to improve
+// async fifo synchronization on the write side by one memory controller clock
+// cycle if the client clock frequency is less or equal to twice the memory
+// controller clock frequency:
+//
+//      clientclk_freq <= 2 * mcclk_freq
+//
+// The register field ending with RDMC_RDFAST (if any) can be set to improve async
+// fifo synchronization on the read side by one memory controller clock cycle.
+//
+// !! WARNING !!
+// RDMC_RDFAST can be used along with WRCL_MCLE2X only when:
+//
+//       mcclk_freq <= clientclk_freq
+//
+// The register field ending with RDCL_RDFAST (if any) can be set to improve async
+// fifo synchronization on the read side by one client clock cycle.
+//
+// !! WARNING !!
+// RDCL_RDFAST can be used along with WRMC_CLLE2X only when:
+//
+//       clientclk_freq <= mcclk_freq
+//
+// RECOMMENDED SETTINGS
+// # Client writing to fifo, memory controller reading from fifo
+// - mcclk_freq <= clientclk_freq
+//     You can enable both RDMC_RDFAST and WRCL_CLLE2X. If one of the fifos is
+//     a real ram and power is a concern, you should avoid enabling RDMC_RDFAST.
+// - clientclk_freq < mcclk_freq <= 2 * clientclk_freq
+//     You can enable RDMC_RDFAST or WRCL_MCLE2X, but because the client clock
+//     is slower, you should enable only WRCL_MCLE2X.
+// - 2 * clientclk_freq < mcclk_freq
+//     You can only enable RDMC_RDFAST. If one of the fifos is a real ram and
+//     power is a concern, you should avoid enabling RDMC_RDFAST.
+//
+// # Memory controller writing to fifo, client reading from fifo
+// - clientclk_freq <= mcclk_freq
+//     You can enable both RDCL_RDFAST and WRMC_CLLE2X. If one of the fifos is
+//     a real ram and power is a concern, you should avoid enabling RDCL_RDFAST.
+// - mcclk_freq < clientclk_freq <= 2 * mcclk_freq
+//     You can enable RDCL_RDFAST or WRMC_CLLE2X, but because the memory controller
+//     clock is slower, you should enable only WRMC_CLLE2X.
+// - 2 * mcclk_freq < clientclk_freq
+//     You can only enable RDCL_RDFAST. If one of the fifos is a real ram and
+//     power is a concern, you should avoid enabling RDCL_RDFAST.
+//
+
+// Register VI_VI_MCCIF_FIFOCTRL_0  
+#define VI_VI_MCCIF_FIFOCTRL_0                  _MK_ADDR_CONST(0x6f)
+#define VI_VI_MCCIF_FIFOCTRL_0_SECURE                   0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_WORD_COUNT                       0x1
+#define VI_VI_MCCIF_FIFOCTRL_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define VI_VI_MCCIF_FIFOCTRL_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_READ_MASK                        _MK_MASK_CONST(0xf)
+#define VI_VI_MCCIF_FIFOCTRL_0_WRITE_MASK                       _MK_MASK_CONST(0xf)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_RANGE                       0:0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRCL_MCLE2X_ENABLE                      _MK_ENUM_CONST(1)
+
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SHIFT                       _MK_SHIFT_CONST(1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_RANGE                       1:1
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDMC_RDFAST_ENABLE                      _MK_ENUM_CONST(1)
+
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SHIFT                       _MK_SHIFT_CONST(2)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_RANGE                       2:2
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_WRMC_CLLE2X_ENABLE                      _MK_ENUM_CONST(1)
+
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SHIFT                       _MK_SHIFT_CONST(3)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_FIELD                       (_MK_MASK_CONST(0x1) << VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SHIFT)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_RANGE                       3:3
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_WOFFSET                     0x0
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_INIT_ENUM                   DISABLE
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_DISABLE                     _MK_ENUM_CONST(0)
+#define VI_VI_MCCIF_FIFOCTRL_0_VI_MCCIF_RDCL_RDFAST_ENABLE                      _MK_ENUM_CONST(1)
+
+// Write Coalescing Time-Out Register
+// This register exists only for write clients. Reset value defaults to 
+// to 50 for most clients, but may be different for certain clients.
+// Write coalescing happens inside the memory client.
+// Coalescing means two (NV_MC_MW/2)-bit requests are grouped together in one NV_MC_MW-bit request.
+// The register value indicates how many cycles a first write request is going to wait
+// for a subsequent one for possible coalescing. The coalescing can only happen
+// if the request addresses are compatible. A value of zero means that coalescing is off
+// and requests are sent right away to the memory controller.
+// Write coalescing can have a very significant impact performance when accessing the internal memory,
+// because its memory word is NV_MC_WM-bit wide. Grouping two half-word accesses is
+// much more efficient, because the two accesses would actually have taken three cycles,
+// due to a stall when accessing the same memory bank. It also reduces the number of
+// accessing (one instead of two), freeing up internal memory bandwidth for other accesses.
+// The impact on external memory accesses is not as significant as the burst access is for
+// NV_MC_MW/2 bits. But a coalesced write guarantees two consecutive same page accesses
+// which is good for external memory bandwidth utilization.
+// The write coalescing time-out should be programmed depending on the client behavior.
+// The first write is obviously delayed by an amount of client cycles equal to the time-out value.
+// Note that writes tagged by the client (i.e. the client expects a write response, usually
+// for coherency), and the last write of a block transfer are not delayed.
+// They only have a one-cycle opportunity to get coalesced.
+//
+
+// Register VI_TIMEOUT_WCOAL_VI_0  
+#define VI_TIMEOUT_WCOAL_VI_0                   _MK_ADDR_CONST(0x70)
+#define VI_TIMEOUT_WCOAL_VI_0_SECURE                    0x0
+#define VI_TIMEOUT_WCOAL_VI_0_WORD_COUNT                        0x1
+#define VI_TIMEOUT_WCOAL_VI_0_RESET_VAL                         _MK_MASK_CONST(0x32323232)
+#define VI_TIMEOUT_WCOAL_VI_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define VI_TIMEOUT_WCOAL_VI_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define VI_TIMEOUT_WCOAL_VI_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_FIELD                   (_MK_MASK_CONST(0xff) << VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_RANGE                   7:0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_WOFFSET                 0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_DEFAULT                 _MK_MASK_CONST(0x32)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_DEFAULT_MASK                    _MK_MASK_CONST(0xff)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWSB_WCOAL_TMVAL_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_RANGE                    15:8
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_WOFFSET                  0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x32)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWU_WCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(16)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_RANGE                    23:16
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_WOFFSET                  0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x32)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWV_WCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SHIFT                    _MK_SHIFT_CONST(24)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_FIELD                    (_MK_MASK_CONST(0xff) << VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SHIFT)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_RANGE                    31:24
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_WOFFSET                  0x0
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_DEFAULT                  _MK_MASK_CONST(0x32)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TIMEOUT_WCOAL_VI_0_VIWY_WCOAL_TMVAL_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Memory Client High-Priority Control Register
+// This register exists only for clients with high-priority. Reset values are 0 (disabled).
+// The high-priority should be enabled for hard real-time clients only. The values to program
+// depend on the client bandwidth requirement and the client versus memory controllers clolck ratio.
+// The high-priority is set if the number of entries in the return data fifo is under the threshold.
+// The high-priority assertion can be delayed by a number of memory clock cycles indicated by the timer.
+// This creates an hysteresis effect, avoiding setting the high-priority for very short periods of time,
+// which may or may not be desirable.
+
+// Register VI_MCCIF_VIRUV_HP_0  
+#define VI_MCCIF_VIRUV_HP_0                     _MK_ADDR_CONST(0x71)
+#define VI_MCCIF_VIRUV_HP_0_SECURE                      0x0
+#define VI_MCCIF_VIRUV_HP_0_WORD_COUNT                  0x1
+#define VI_MCCIF_VIRUV_HP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_RESET_MASK                  _MK_MASK_CONST(0x3f000f)
+#define VI_MCCIF_VIRUV_HP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_READ_MASK                   _MK_MASK_CONST(0x3f000f)
+#define VI_MCCIF_VIRUV_HP_0_WRITE_MASK                  _MK_MASK_CONST(0x3f000f)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_FIELD                     (_MK_MASK_CONST(0xf) << VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_RANGE                     3:0
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_WOFFSET                   0x0
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_FIELD                     (_MK_MASK_CONST(0x3f) << VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SHIFT)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_RANGE                     21:16
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_WOFFSET                   0x0
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_DEFAULT_MASK                      _MK_MASK_CONST(0x3f)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HP_0_CBR_VIRUV2MC_HPTM_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Memory Client High-Priority Control Register
+// This register exists only for clients with high-priority. Reset values are 0 (disabled).
+// The high-priority should be enabled for hard real-time clients only. The values to program
+// depend on the client bandwidth requirement and the client versus memory controllers clolck ratio.
+// The high-priority is set if the number of entries in the data fifo is higher than the threshold.
+
+// Register VI_MCCIF_VIWSB_HP_0  
+#define VI_MCCIF_VIWSB_HP_0                     _MK_ADDR_CONST(0x72)
+#define VI_MCCIF_VIWSB_HP_0_SECURE                      0x0
+#define VI_MCCIF_VIWSB_HP_0_WORD_COUNT                  0x1
+#define VI_MCCIF_VIWSB_HP_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_RESET_MASK                  _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_READ_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_WRITE_MASK                  _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_FIELD                     (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_RANGE                     6:0
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_WOFFSET                   0x0
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_DEFAULT_MASK                      _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HP_0_CBW_VIWSB2MC_HPTH_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Memory Client High-Priority Control Register
+// This register exists only for clients with high-priority. Reset values are 0 (disabled).
+// The high-priority should be enabled for hard real-time clients only. The values to program
+// depend on the client bandwidth requirement and the client versus memory controllers clolck ratio.
+// The high-priority is set if the number of entries in the data fifo is higher than the threshold.
+
+// Register VI_MCCIF_VIWU_HP_0  
+#define VI_MCCIF_VIWU_HP_0                      _MK_ADDR_CONST(0x73)
+#define VI_MCCIF_VIWU_HP_0_SECURE                       0x0
+#define VI_MCCIF_VIWU_HP_0_WORD_COUNT                   0x1
+#define VI_MCCIF_VIWU_HP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_FIELD                       (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_RANGE                       6:0
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_WOFFSET                     0x0
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HP_0_CBW_VIWU2MC_HPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Memory Client High-Priority Control Register
+// This register exists only for clients with high-priority. Reset values are 0 (disabled).
+// The high-priority should be enabled for hard real-time clients only. The values to program
+// depend on the client bandwidth requirement and the client versus memory controllers clolck ratio.
+// The high-priority is set if the number of entries in the data fifo is higher than the threshold.
+
+// Register VI_MCCIF_VIWV_HP_0  
+#define VI_MCCIF_VIWV_HP_0                      _MK_ADDR_CONST(0x74)
+#define VI_MCCIF_VIWV_HP_0_SECURE                       0x0
+#define VI_MCCIF_VIWV_HP_0_WORD_COUNT                   0x1
+#define VI_MCCIF_VIWV_HP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_FIELD                       (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_RANGE                       6:0
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_WOFFSET                     0x0
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HP_0_CBW_VIWV2MC_HPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Memory Client High-Priority Control Register
+// This register exists only for clients with high-priority. Reset values are 0 (disabled).
+// The high-priority should be enabled for hard real-time clients only. The values to program
+// depend on the client bandwidth requirement and the client versus memory controllers clolck ratio.
+// The high-priority is set if the number of entries in the data fifo is higher than the threshold.
+
+// Register VI_MCCIF_VIWY_HP_0  
+#define VI_MCCIF_VIWY_HP_0                      _MK_ADDR_CONST(0x75)
+#define VI_MCCIF_VIWY_HP_0_SECURE                       0x0
+#define VI_MCCIF_VIWY_HP_0_WORD_COUNT                   0x1
+#define VI_MCCIF_VIWY_HP_0_RESET_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_RESET_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_READ_MASK                    _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_WRITE_MASK                   _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_FIELD                       (_MK_MASK_CONST(0x7f) << VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SHIFT)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_RANGE                       6:0
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_WOFFSET                     0x0
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_DEFAULT_MASK                        _MK_MASK_CONST(0x7f)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HP_0_CBW_VIWY2MC_HPTH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// CSI Raise vectors
+
+// Register VI_CSI_PPA_RAISE_FRAME_START_0  // CSI Pixel Parser A Raise
+#define VI_CSI_PPA_RAISE_FRAME_START_0                  _MK_ADDR_CONST(0x76)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_SECURE                   0x0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_WORD_COUNT                       0x1
+#define VI_CSI_PPA_RAISE_FRAME_START_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_READ_MASK                        _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_WRITE_MASK                       _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPA
+//   issues a frame start to consumer.
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_RANGE                   4:0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_WOFFSET                 0x0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//   Number of frame start since last raise >= count for raise to be returned
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_FIELD                    (_MK_MASK_CONST(0xff) << VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_RANGE                    15:8
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_WOFFSET                  0x0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_RANGE                  19:16
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_WOFFSET                        0x0
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_START_0_CSI_PPA_RAISE_FRAME_START_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPA_RAISE_FRAME_END_0  // CSI Pixel Parser A Raise
+#define VI_CSI_PPA_RAISE_FRAME_END_0                    _MK_ADDR_CONST(0x77)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_SECURE                     0x0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_WORD_COUNT                         0x1
+#define VI_CSI_PPA_RAISE_FRAME_END_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_READ_MASK                  _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_WRITE_MASK                         _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPA
+//   issues a frame end to consumer.
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_FIELD                       (_MK_MASK_CONST(0x1f) << VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_RANGE                       4:0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_WOFFSET                     0x0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//   Number of frame end since last raise >= count for raise to be returned
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_FIELD                        (_MK_MASK_CONST(0xff) << VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_RANGE                        15:8
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_WOFFSET                      0x0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_FIELD                      (_MK_MASK_CONST(0xf) << VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SHIFT)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_RANGE                      19:16
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_WOFFSET                    0x0
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_RAISE_FRAME_END_0_CSI_PPA_RAISE_FRAME_END_CHANNEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPB_RAISE_FRAME_START_0  // CSI Pixel Parser B Raise
+#define VI_CSI_PPB_RAISE_FRAME_START_0                  _MK_ADDR_CONST(0x78)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_SECURE                   0x0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_WORD_COUNT                       0x1
+#define VI_CSI_PPB_RAISE_FRAME_START_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_READ_MASK                        _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_WRITE_MASK                       _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPB
+//   issues a frame start to consumer.
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SHIFT                   _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_FIELD                   (_MK_MASK_CONST(0x1f) << VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_RANGE                   4:0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_WOFFSET                 0x0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_VECTOR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+//   Number of frame start since last raise >= count for raise to be returned
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SHIFT                    _MK_SHIFT_CONST(8)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_FIELD                    (_MK_MASK_CONST(0xff) << VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_RANGE                    15:8
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_WOFFSET                  0x0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_COUNT_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SHIFT                  _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_FIELD                  (_MK_MASK_CONST(0xf) << VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_RANGE                  19:16
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_WOFFSET                        0x0
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_START_0_CSI_PPB_RAISE_FRAME_START_CHANNEL_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_CSI_PPB_RAISE_FRAME_END_0  // CSI Pixel Parser B Raise
+#define VI_CSI_PPB_RAISE_FRAME_END_0                    _MK_ADDR_CONST(0x79)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_SECURE                     0x0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_WORD_COUNT                         0x1
+#define VI_CSI_PPB_RAISE_FRAME_END_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_READ_MASK                  _MK_MASK_CONST(0xfff1f)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_WRITE_MASK                         _MK_MASK_CONST(0xfff1f)
+//   Raise returned by VI when CSI PPB
+//   issues a frame end to consumer.
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_FIELD                       (_MK_MASK_CONST(0x1f) << VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_RANGE                       4:0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_WOFFSET                     0x0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_VECTOR_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//   Number of frame end since last raise >= count for raise to be returned
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SHIFT                        _MK_SHIFT_CONST(8)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_FIELD                        (_MK_MASK_CONST(0xff) << VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_RANGE                        15:8
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_WOFFSET                      0x0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+//   Raise return channel
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SHIFT                      _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_FIELD                      (_MK_MASK_CONST(0xf) << VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SHIFT)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_RANGE                      19:16
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_WOFFSET                    0x0
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_RAISE_FRAME_END_0_CSI_PPB_RAISE_FRAME_END_CHANNEL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// This register defines the horizontal captured (active) area of the input video source with respect to
+//  horizontal sync. (This is for CSI data.)
+
+// Register VI_CSI_PPA_H_ACTIVE_0  // VI Horizontal Active
+#define VI_CSI_PPA_H_ACTIVE_0                   _MK_ADDR_CONST(0x7a)
+#define VI_CSI_PPA_H_ACTIVE_0_SECURE                    0x0
+#define VI_CSI_PPA_H_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPA_H_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPA_H_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  clock active edges from horizontal
+//  sync active edge to the first horizontal
+//  active pixel. If programmed to 0, the
+//  first active line starts after the first
+//  active clock edge following the horizontal
+//  sync active edge.
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SHIFT)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  H_ACTIVE_START + H_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_H_IN (or 8192). This parameter
+//  should be programmed with an even number
+//  (bit 16 is ignored internally).
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_H_ACTIVE_0_CSI_PPA_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// This register defines the vertical captured (active) area of the input video source with respect to
+//  vertical sync. (This is for CSI data.)
+
+// Register VI_CSI_PPA_V_ACTIVE_0  // Vertical Active
+#define VI_CSI_PPA_V_ACTIVE_0                   _MK_ADDR_CONST(0x7b)
+#define VI_CSI_PPA_V_ACTIVE_0_SECURE                    0x0
+#define VI_CSI_PPA_V_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPA_V_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPA_V_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SHIFT)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  V_ACTIVE_START + V_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_V_IN (or 8192).
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPA_V_ACTIVE_0_CSI_PPA_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// This register defines the horizontal captured (active) area of the input video source with respect to
+//  horizontal sync. (This is for CSI data.)
+
+// Register VI_CSI_PPB_H_ACTIVE_0  // VI Horizontal Active
+#define VI_CSI_PPB_H_ACTIVE_0                   _MK_ADDR_CONST(0x7c)
+#define VI_CSI_PPB_H_ACTIVE_0_SECURE                    0x0
+#define VI_CSI_PPB_H_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPB_H_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPB_H_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Horizontal Active Start (offset to active)
+//  This parameter specifies the number of
+//  clock active edges from horizontal
+//  sync active edge to the first horizontal
+//  active pixel. If programmed to 0, the
+//  first active line starts after the first
+//  active clock edge following the horizontal
+//  sync active edge.
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SHIFT)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Horizontal Active Period
+//  This parameter specifies the number of
+//  pixels in the horizontal active area.
+//  H_ACTIVE_START + H_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_H_IN (or 8192). This parameter
+//  should be programmed with an even number
+//  (bit 16 is ignored internally).
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_H_ACTIVE_0_CSI_PPB_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// This register defines the vertical captured (active) area of the input video source with respect to
+//  vertical sync. (This is for CSI data.)
+
+// Register VI_CSI_PPB_V_ACTIVE_0  // Vertical Active
+#define VI_CSI_PPB_V_ACTIVE_0                   _MK_ADDR_CONST(0x7d)
+#define VI_CSI_PPB_V_ACTIVE_0_SECURE                    0x0
+#define VI_CSI_PPB_V_ACTIVE_0_WORD_COUNT                        0x1
+#define VI_CSI_PPB_V_ACTIVE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_READ_MASK                         _MK_MASK_CONST(0x1fff1fff)
+#define VI_CSI_PPB_V_ACTIVE_0_WRITE_MASK                        _MK_MASK_CONST(0x1fff1fff)
+// Vertical Active Start (offset to active)
+//  This parameter specifies the number of
+//  horizontal sync active edges from vertical
+//  sync active edge to the first vertical
+//  active line. If programmed to 0, the
+//  first active line starts after the first
+//  horizontal sync active edge following
+//  the vertical sync active edge.
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_FIELD                      (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SHIFT)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_RANGE                      12:0
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_WOFFSET                    0x0
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_START_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Vertical Active Period
+//  This parameter specifies the number of
+//  lines in the vertical active area.
+//  V_ACTIVE_START + V_ACTIVE_PERIOD should be
+//  less than 2^NV_VI_V_IN (or 8192).
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(16)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SHIFT)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_RANGE                     28:16
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_CSI_PPB_V_ACTIVE_0_CSI_PPB_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Used only with input from ISP: defines input image horizontal size in pixels
+
+// Register VI_ISP_H_ACTIVE_0  // Used when an image comes from ISP
+#define VI_ISP_H_ACTIVE_0                       _MK_ADDR_CONST(0x7e)
+#define VI_ISP_H_ACTIVE_0_SECURE                        0x0
+#define VI_ISP_H_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_ISP_H_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff)
+#define VI_ISP_H_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff)
+// Horizontal image size in pixels coming out of ISP.
+// Must be an even number (bit 0 is ignored).
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SHIFT)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_RANGE                     12:0
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_ISP_H_ACTIVE_0_ISP_H_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Used only with input from ISP: defines input image vertical size in lines
+
+// Register VI_ISP_V_ACTIVE_0  // Used when an image comes from ISP
+#define VI_ISP_V_ACTIVE_0                       _MK_ADDR_CONST(0x7f)
+#define VI_ISP_V_ACTIVE_0_SECURE                        0x0
+#define VI_ISP_V_ACTIVE_0_WORD_COUNT                    0x1
+#define VI_ISP_V_ACTIVE_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_READ_MASK                     _MK_MASK_CONST(0x1fff)
+#define VI_ISP_V_ACTIVE_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff)
+// Vertical image size in lines coming out of ISP.
+// Must be an even number (bit 0 is ignored).
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SHIFT)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_RANGE                     12:0
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_WOFFSET                   0x0
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_ISP_V_ACTIVE_0_ISP_V_ACTIVE_PERIOD_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Stream raises ("safe to reprogram VI" raises)
+// The I/O resources used by a data stream going through VI are indicated in STREAM_?_RESOURCE_DEFINE register.
+// Once resources are set in this register,
+// and after the start of the following picture,
+// when ALL the stream's resources are done and idle processing that picture,
+// a raise will be generated.
+// It is then safe to reprogram VI's functional units involved in processing that stream.
+//
+// Two simultaneous data streams are supported, and they don't have to be mutually exclusive.
+//
+// When no resources are indicated for a stream, no raise is generated.
+
+// Register VI_STREAM_1_RESOURCE_DEFINE_0  // defines resources used by stream 1.
+// Field definition is: 0 = resource not used; 1 = resource used.
+#define VI_STREAM_1_RESOURCE_DEFINE_0                   _MK_ADDR_CONST(0x80)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECURE                    0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_WORD_COUNT                        0x1
+#define VI_STREAM_1_RESOURCE_DEFINE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_RESET_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_READ_MASK                         _MK_MASK_CONST(0xfff)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_WRITE_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_RANGE                 0:0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_WOFFSET                       0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_VIP_INPUT_1_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_RANGE                        1:1
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_WOFFSET                      0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_INPUT_1_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_RANGE                     2:2
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SHIFT                   _MK_SHIFT_CONST(3)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_RANGE                   3:3
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_WOFFSET                 0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_1_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_RANGE                     4:4
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SHIFT                   _MK_SHIFT_CONST(5)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_RANGE                   5:5
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_WOFFSET                 0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_1_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_RANGE                 6:6
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_WOFFSET                       0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_ISP_INPUT_1_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_FIELD                      (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_RANGE                      7:7
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_WOFFSET                    0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_NOT_USED                   _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_FIRST_OUTPUT_1_USED                       _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_RANGE                     8:8
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_SECOND_OUTPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SHIFT                     _MK_SHIFT_CONST(9)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_RANGE                     9:9
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_WOFFSET                   0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_1_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SHIFT                        _MK_SHIFT_CONST(10)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_RANGE                        10:10
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_WOFFSET                      0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_EPP_OUTPUT_1_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SHIFT                    _MK_SHIFT_CONST(11)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_FIELD                    (_MK_MASK_CONST(0x1) << VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SHIFT)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_RANGE                    11:11
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_WOFFSET                  0x0
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_NOT_USED                 _MK_ENUM_CONST(0)
+#define VI_STREAM_1_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_1_USED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_STREAM_2_RESOURCE_DEFINE_0  // defines resources used by stream 2.
+// Field definition is: 0 = resource not used; 1 = resource used.
+#define VI_STREAM_2_RESOURCE_DEFINE_0                   _MK_ADDR_CONST(0x81)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECURE                    0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_WORD_COUNT                        0x1
+#define VI_STREAM_2_RESOURCE_DEFINE_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_RESET_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_READ_MASK                         _MK_MASK_CONST(0xfff)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_WRITE_MASK                        _MK_MASK_CONST(0xfff)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SHIFT                 _MK_SHIFT_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_RANGE                 0:0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_WOFFSET                       0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_VIP_INPUT_2_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SHIFT                        _MK_SHIFT_CONST(1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_RANGE                        1:1
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_WOFFSET                      0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_INPUT_2_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SHIFT                     _MK_SHIFT_CONST(2)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_RANGE                     2:2
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_CROPPED_INPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SHIFT                   _MK_SHIFT_CONST(3)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_RANGE                   3:3
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_WOFFSET                 0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPA_UNCROPPED_INPUT_2_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_RANGE                     4:4
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_CROPPED_INPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SHIFT                   _MK_SHIFT_CONST(5)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_FIELD                   (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_RANGE                   5:5
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_WOFFSET                 0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_NOT_USED                        _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_CSI_PPB_UNCROPPED_INPUT_2_USED                    _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_FIELD                 (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_RANGE                 6:6
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_WOFFSET                       0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_NOT_USED                      _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_ISP_INPUT_2_USED                  _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SHIFT                      _MK_SHIFT_CONST(7)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_FIELD                      (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_RANGE                      7:7
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_WOFFSET                    0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_NOT_USED                   _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_FIRST_OUTPUT_2_USED                       _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_RANGE                     8:8
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_SECOND_OUTPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SHIFT                     _MK_SHIFT_CONST(9)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_FIELD                     (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_RANGE                     9:9
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_WOFFSET                   0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_NOT_USED                  _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_VSYNC_OUTPUT_2_USED                      _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SHIFT                        _MK_SHIFT_CONST(10)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_FIELD                        (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_RANGE                        10:10
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_WOFFSET                      0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_NOT_USED                     _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_EPP_OUTPUT_2_USED                 _MK_ENUM_CONST(1)
+
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SHIFT                    _MK_SHIFT_CONST(11)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_FIELD                    (_MK_MASK_CONST(0x1) << VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SHIFT)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_RANGE                    11:11
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_WOFFSET                  0x0
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_NOT_USED                 _MK_ENUM_CONST(0)
+#define VI_STREAM_2_RESOURCE_DEFINE_0_HOST_DMA_BUFFER_OUTPUT_2_USED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_RAISE_STREAM_1_DONE_0  // raise vector when all stream 1 resources,
+// as defined by STREAM_1_RESOURCE_DEFINE register,
+// become idle after the start of the following frame.
+#define VI_RAISE_STREAM_1_DONE_0                        _MK_ADDR_CONST(0x82)
+#define VI_RAISE_STREAM_1_DONE_0_SECURE                         0x0
+#define VI_RAISE_STREAM_1_DONE_0_WORD_COUNT                     0x1
+#define VI_RAISE_STREAM_1_DONE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define VI_RAISE_STREAM_1_DONE_0_WRITE_MASK                     _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_FIELD                    (_MK_MASK_CONST(0x1f) << VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SHIFT)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_RANGE                    4:0
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_WOFFSET                  0x0
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_VECTOR_STREAM_1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_FIELD                   (_MK_MASK_CONST(0xf) << VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SHIFT)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_RANGE                   19:16
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_WOFFSET                 0x0
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_1_DONE_0_RAISE_CHANNEL_STREAM_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register VI_RAISE_STREAM_2_DONE_0  // raise vector when all stream 2 resources,
+// as defined by STREAM_2_RESOURCE_DEFINE register,
+// become idle after the start of the following frame
+#define VI_RAISE_STREAM_2_DONE_0                        _MK_ADDR_CONST(0x83)
+#define VI_RAISE_STREAM_2_DONE_0_SECURE                         0x0
+#define VI_RAISE_STREAM_2_DONE_0_WORD_COUNT                     0x1
+#define VI_RAISE_STREAM_2_DONE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_READ_MASK                      _MK_MASK_CONST(0x1f)
+#define VI_RAISE_STREAM_2_DONE_0_WRITE_MASK                     _MK_MASK_CONST(0xf001f)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_FIELD                    (_MK_MASK_CONST(0x1f) << VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SHIFT)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_RANGE                    4:0
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_WOFFSET                  0x0
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_VECTOR_STREAM_2_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SHIFT                   _MK_SHIFT_CONST(16)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_FIELD                   (_MK_MASK_CONST(0xf) << VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SHIFT)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_RANGE                   19:16
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_WOFFSET                 0x0
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_RAISE_STREAM_2_DONE_0_RAISE_CHANNEL_STREAM_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// ISDB-T tuner mode register set
+//   tuner/demodulator mode.
+
+// Register VI_TS_MODE_0  // ISDB-T mode selection register
+#define VI_TS_MODE_0                    _MK_ADDR_CONST(0x84)
+#define VI_TS_MODE_0_SECURE                     0x0
+#define VI_TS_MODE_0_WORD_COUNT                         0x1
+#define VI_TS_MODE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_READ_MASK                  _MK_MASK_CONST(0x3f)
+#define VI_TS_MODE_0_WRITE_MASK                         _MK_MASK_CONST(0x3f)
+// This field indicates the global enable for ISDB-T protocol handling
+#define VI_TS_MODE_0_ENABLE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_TS_MODE_0_ENABLE_FIELD                       (_MK_MASK_CONST(0x1) << VI_TS_MODE_0_ENABLE_SHIFT)
+#define VI_TS_MODE_0_ENABLE_RANGE                       0:0
+#define VI_TS_MODE_0_ENABLE_WOFFSET                     0x0
+#define VI_TS_MODE_0_ENABLE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_ENABLE_DISABLED                    _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_ENABLE_ENABLED                     _MK_ENUM_CONST(1)
+
+// This field determines if input data is in serial or parallel format
+#define VI_TS_MODE_0_INPUT_MODE_SHIFT                   _MK_SHIFT_CONST(1)
+#define VI_TS_MODE_0_INPUT_MODE_FIELD                   (_MK_MASK_CONST(0x1) << VI_TS_MODE_0_INPUT_MODE_SHIFT)
+#define VI_TS_MODE_0_INPUT_MODE_RANGE                   1:1
+#define VI_TS_MODE_0_INPUT_MODE_WOFFSET                 0x0
+#define VI_TS_MODE_0_INPUT_MODE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_INPUT_MODE_PARALLEL                        _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_INPUT_MODE_SERIAL                  _MK_ENUM_CONST(1)
+
+// This field selected the pin configuration used for VD[1]  NONE:     TS_ERROR is tied to 0
+//            TS_PSYNC is tied to 0
+//  TS_ERROR: TS_ERROR is on VD[1]
+//            TS_PSYNC is tied to 0
+//  TS_PSYNC: TS_ERROR is tied to 0
+//            TS_PSYNC is on VD[1]
+#define VI_TS_MODE_0_PROTOCOL_SELECT_SHIFT                      _MK_SHIFT_CONST(2)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_FIELD                      (_MK_MASK_CONST(0x3) << VI_TS_MODE_0_PROTOCOL_SELECT_SHIFT)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_RANGE                      3:2
+#define VI_TS_MODE_0_PROTOCOL_SELECT_WOFFSET                    0x0
+#define VI_TS_MODE_0_PROTOCOL_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_NONE                       _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_TS_ERROR                   _MK_ENUM_CONST(1)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_TS_PSYNC                   _MK_ENUM_CONST(2)
+#define VI_TS_MODE_0_PROTOCOL_SELECT_RESERVED                   _MK_ENUM_CONST(3)
+
+// This field selects the buffer flow control for the Write DMA RDMA:      The RDMA engine will release the buffers back to the WDMA
+//            as the buffers are consumed
+// NONE:      The VI will automatically release the buffer back to the
+//            WMDA after each buffer ready is generated.
+// CPU:       SW needs to write the TS_CPU_FLOW_CTL register to release
+//            each buffer to the WDMA
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_SHIFT                    _MK_SHIFT_CONST(4)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_FIELD                    (_MK_MASK_CONST(0x3) << VI_TS_MODE_0_FLOW_CONTROL_MODE_SHIFT)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_RANGE                    5:4
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_WOFFSET                  0x0
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_RDMA                     _MK_ENUM_CONST(0)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_NONE                     _MK_ENUM_CONST(1)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_CPU                      _MK_ENUM_CONST(2)
+#define VI_TS_MODE_0_FLOW_CONTROL_MODE_RESERVED                 _MK_ENUM_CONST(3)
+
+
+// Register VI_TS_CONTROL_0  // ISDB-T mode control register
+#define VI_TS_CONTROL_0                 _MK_ADDR_CONST(0x85)
+#define VI_TS_CONTROL_0_SECURE                  0x0
+#define VI_TS_CONTROL_0_WORD_COUNT                      0x1
+#define VI_TS_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x8)
+#define VI_TS_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x8)
+#define VI_TS_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x7fff00ff)
+#define VI_TS_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x7fff00ff)
+// This field indicates the polarity of TS_VALID. Only has affect when TS_MODE.ENABLE == ENABLED    LOW indicates that the polarity of TS_VALID is active low.
+//    HIGH indicates that the polarity of TS_VALID is active high.
+#define VI_TS_CONTROL_0_VALID_POLARITY_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_FIELD                    (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_VALID_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_VALID_POLARITY_RANGE                    0:0
+#define VI_TS_CONTROL_0_VALID_POLARITY_WOFFSET                  0x0
+#define VI_TS_CONTROL_0_VALID_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_HIGH                     _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_VALID_POLARITY_LOW                      _MK_ENUM_CONST(1)
+
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_SHIFT                    _MK_SHIFT_CONST(1)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_FIELD                    (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_PSYNC_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_RANGE                    1:1
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_WOFFSET                  0x0
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_HIGH                     _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_PSYNC_POLARITY_LOW                      _MK_ENUM_CONST(1)
+
+#define VI_TS_CONTROL_0_ERROR_POLARITY_SHIFT                    _MK_SHIFT_CONST(2)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_FIELD                    (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_ERROR_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_RANGE                    2:2
+#define VI_TS_CONTROL_0_ERROR_POLARITY_WOFFSET                  0x0
+#define VI_TS_CONTROL_0_ERROR_POLARITY_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_HIGH                     _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_ERROR_POLARITY_LOW                      _MK_ENUM_CONST(1)
+
+#define VI_TS_CONTROL_0_CLK_POLARITY_SHIFT                      _MK_SHIFT_CONST(3)
+#define VI_TS_CONTROL_0_CLK_POLARITY_FIELD                      (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_CLK_POLARITY_SHIFT)
+#define VI_TS_CONTROL_0_CLK_POLARITY_RANGE                      3:3
+#define VI_TS_CONTROL_0_CLK_POLARITY_WOFFSET                    0x0
+#define VI_TS_CONTROL_0_CLK_POLARITY_DEFAULT                    _MK_MASK_CONST(0x1)
+#define VI_TS_CONTROL_0_CLK_POLARITY_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_TS_CONTROL_0_CLK_POLARITY_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_INIT_ENUM                  LOW
+#define VI_TS_CONTROL_0_CLK_POLARITY_HIGH                       _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_CLK_POLARITY_LOW                        _MK_ENUM_CONST(1)
+
+// This field defines how the START of packet condition is determined  PSYNC: PSYNC assertion rising edge
+//  VALID: VALID assertion rising edge
+//  BOTH:  PSYNC && VALID asserted rising edge
+#define VI_TS_CONTROL_0_START_SELECT_SHIFT                      _MK_SHIFT_CONST(4)
+#define VI_TS_CONTROL_0_START_SELECT_FIELD                      (_MK_MASK_CONST(0x3) << VI_TS_CONTROL_0_START_SELECT_SHIFT)
+#define VI_TS_CONTROL_0_START_SELECT_RANGE                      5:4
+#define VI_TS_CONTROL_0_START_SELECT_WOFFSET                    0x0
+#define VI_TS_CONTROL_0_START_SELECT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_START_SELECT_RESERVED                   _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_START_SELECT_PSYNC                      _MK_ENUM_CONST(1)
+#define VI_TS_CONTROL_0_START_SELECT_VALID                      _MK_ENUM_CONST(2)
+#define VI_TS_CONTROL_0_START_SELECT_BOTH                       _MK_ENUM_CONST(3)
+
+// This field determines if VALID is used during BODY packet capture  IGNORE: the VALID signal is ignored during the capture
+//  GATE: the VALID signal gates the capture of BODY data.
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_SHIFT                 _MK_SHIFT_CONST(6)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_FIELD                 (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_BODY_VALID_SELECT_SHIFT)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_RANGE                 6:6
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_WOFFSET                       0x0
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_IGNORE                        _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_BODY_VALID_SELECT_GATE                  _MK_ENUM_CONST(1)
+
+// This field determines is VI should store packets to memory that have been flagged as UPSTREAM_ERROR packets.
+//  DISCARD: Do not store packets in memory
+//  STORE:   Store UPSTREAM_ERROR packets in memory
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SHIFT                 _MK_SHIFT_CONST(7)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_FIELD                 (_MK_MASK_CONST(0x1) << VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SHIFT)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_RANGE                 7:7
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_WOFFSET                       0x0
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_DISCARD                       _MK_ENUM_CONST(0)
+#define VI_TS_CONTROL_0_STORE_UPSTREAM_ERROR_PKTS_STORE                 _MK_ENUM_CONST(1)
+
+// This field stores the number of BODY bytes to capture (including PSYNC)
+#define VI_TS_CONTROL_0_BODY_SIZE_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_TS_CONTROL_0_BODY_SIZE_FIELD                 (_MK_MASK_CONST(0xff) << VI_TS_CONTROL_0_BODY_SIZE_SHIFT)
+#define VI_TS_CONTROL_0_BODY_SIZE_RANGE                 23:16
+#define VI_TS_CONTROL_0_BODY_SIZE_WOFFSET                       0x0
+#define VI_TS_CONTROL_0_BODY_SIZE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_SIZE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_SIZE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_BODY_SIZE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// This field stores the number of FEC bytes to catpure (after the BODY has been captured)
+#define VI_TS_CONTROL_0_FEC_SIZE_SHIFT                  _MK_SHIFT_CONST(24)
+#define VI_TS_CONTROL_0_FEC_SIZE_FIELD                  (_MK_MASK_CONST(0x7f) << VI_TS_CONTROL_0_FEC_SIZE_SHIFT)
+#define VI_TS_CONTROL_0_FEC_SIZE_RANGE                  30:24
+#define VI_TS_CONTROL_0_FEC_SIZE_WOFFSET                        0x0
+#define VI_TS_CONTROL_0_FEC_SIZE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_FEC_SIZE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_FEC_SIZE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_CONTROL_0_FEC_SIZE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register VI_TS_PACKET_COUNT_0  // ISDB-T packet count register
+#define VI_TS_PACKET_COUNT_0                    _MK_ADDR_CONST(0x86)
+#define VI_TS_PACKET_COUNT_0_SECURE                     0x0
+#define VI_TS_PACKET_COUNT_0_WORD_COUNT                         0x1
+#define VI_TS_PACKET_COUNT_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_READ_MASK                  _MK_MASK_CONST(0x1ffff)
+#define VI_TS_PACKET_COUNT_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// This field holds the current value of the received packet counter.  This counter increments
+// in the presence of a new packet, regardless of whether it is flagged as an error
+// The counter can be cleared by writing this register with 0's and can also
+// be preloaded to any value by writing the preload value to the register.
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_FIELD                        (_MK_MASK_CONST(0xffff) << VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SHIFT)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_RANGE                        15:0
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_WOFFSET                      0x0
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// This field is set to OVERFLOW when VALUE passes from 0xFFFF to 0x0000. It stays high until the CPU writes a zero to this bit to reset it.
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SHIFT                       _MK_SHIFT_CONST(16)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_FIELD                       (_MK_MASK_CONST(0x1) << VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SHIFT)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_RANGE                       16:16
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_WOFFSET                     0x0
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_NONE                        _MK_ENUM_CONST(0)
+#define VI_TS_PACKET_COUNT_0_TS_PACKET_COUNT_VALUE_OVERFLOW_OVERFLOW                    _MK_ENUM_CONST(1)
+
+
+// Register VI_TS_ERROR_COUNT_0  // ISDB-T error count register
+#define VI_TS_ERROR_COUNT_0                     _MK_ADDR_CONST(0x87)
+#define VI_TS_ERROR_COUNT_0_SECURE                      0x0
+#define VI_TS_ERROR_COUNT_0_WORD_COUNT                  0x1
+#define VI_TS_ERROR_COUNT_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_READ_MASK                   _MK_MASK_CONST(0x1ffff)
+#define VI_TS_ERROR_COUNT_0_WRITE_MASK                  _MK_MASK_CONST(0x0)
+// This field holds the current value of the error packet counter.  This counter increments in the
+// presence of a packet flagged as error (see TS_ERROR)0000 or a detected protocol violation.
+// The counter can be cleared by writing this register with 0's and can also
+// be preloaded to any value by writing the preload value to the register.
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_FIELD                  (_MK_MASK_CONST(0xffff) << VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SHIFT)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_RANGE                  15:0
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_WOFFSET                        0x0
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// This field is set to OVEFLOW when VALUE passes from 0xFFFF to 0x0000. It stays high until the CPU writes a zero to this bit to reset it.
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SHIFT                 _MK_SHIFT_CONST(16)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_FIELD                 (_MK_MASK_CONST(0x1) << VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SHIFT)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_RANGE                 16:16
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_WOFFSET                       0x0
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_NONE                  _MK_ENUM_CONST(0)
+#define VI_TS_ERROR_COUNT_0_TS_ERROR_COUNT_VALUE_OVERFLOW_OVERFLOW                      _MK_ENUM_CONST(1)
+
+
+// Register VI_TS_CPU_FLOW_CTL_0  // ISDB-T CPU flow control register
+#define VI_TS_CPU_FLOW_CTL_0                    _MK_ADDR_CONST(0x88)
+#define VI_TS_CPU_FLOW_CTL_0_SECURE                     0x0
+#define VI_TS_CPU_FLOW_CTL_0_WORD_COUNT                         0x1
+#define VI_TS_CPU_FLOW_CTL_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_READ_MASK                  _MK_MASK_CONST(0x1)
+#define VI_TS_CPU_FLOW_CTL_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Used only when the FLOW_CONTROL_MODE register is set to CPU
+// SW must write this register to release each buffer back to
+// WDMA.  Failure to write this register when buffers are
+// consumed will result in the WDMA stalling when it consumes all
+// allocated/free buffers.
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SHIFT                       _MK_SHIFT_CONST(0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_FIELD                       (_MK_MASK_CONST(0x1) << VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SHIFT)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_RANGE                       0:0
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_WOFFSET                     0x0
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_TS_CPU_FLOW_CTL_0_BUFFER_RELEASE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// We are using HOST_DMA_WRITE_BUFFER.BUFFER_SIZE (bytes) to hold the number of bytes in a buffer for ISDB-T mode.
+
+// Register VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0  // Video Buffer Set 0 Chroma Buffer Stride.
+// This feature was introduced in SC17,
+// and represents an alternative value to using
+// VB0_BUFFER_STRIDE_C.
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0                     _MK_ADDR_CONST(0x89)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_SECURE                      0x0
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_WORD_COUNT                  0x1
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_RESET_MASK                  _MK_MASK_CONST(0x80000000)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_READ_MASK                   _MK_MASK_CONST(0xbfffffff)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_WRITE_MASK                  _MK_MASK_CONST(0xbfffffff)
+// Chroma buffer stride in bytes
+// 30 reserved
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_FIELD                      (_MK_MASK_CONST(0x3fffffff) << VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SHIFT)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_RANGE                      29:0
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_WOFFSET                    0x0
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// select type of Chroma buffer stride: 0 = Use VB0_BUFFER_STRIDE_C, deriving chroma
+// buffer stride from luma buffer stride
+// (default and backward compatible to SC15).
+// 1 = Use VB0_CHROMA_BUFFER_STRIDE.
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SHIFT                       _MK_SHIFT_CONST(31)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_FIELD                       (_MK_MASK_CONST(0x1) << VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SHIFT)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_RANGE                       31:31
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_WOFFSET                     0x0
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_RATIO                       _MK_ENUM_CONST(0)
+#define VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0_VB0_CHROMA_BUFFER_STRIDE_SELECT_VALUE                       _MK_ENUM_CONST(1)
+
+
+// Register VI_VB0_CHROMA_LINE_STRIDE_FIRST_0  // Video Buffer Set 0 chroma line stride for First Output of planar YUV formats
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0                       _MK_ADDR_CONST(0x8a)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_SECURE                        0x0
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_WORD_COUNT                    0x1
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_RESET_MASK                    _MK_MASK_CONST(0x80000000)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_READ_MASK                     _MK_MASK_CONST(0x80001fff)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_WRITE_MASK                    _MK_MASK_CONST(0x80001fff)
+// Video Buffer Set 0 chroma horizontal size
+//  This parameter specifies the chroma line stride
+//  (in pixels) for lines in the video buffer
+//  set 0.
+//  this parameter
+//  must be programmed as multiple of 4 pixels
+//  (bits 1-0 are ignored).
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_FIELD                     (_MK_MASK_CONST(0x1fff) << VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SHIFT)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_RANGE                     12:0
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_WOFFSET                   0x0
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_H_SIZE_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// select type of Chroma line stride: 0 = Use VB0_H_SIZE_1, deriving chroma line stride from luma line stride (default and backward compatible to SC15).
+// 1 = Use VB0_CHROMA_H_SIZE_1.
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SHIFT                   _MK_SHIFT_CONST(31)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_FIELD                   (_MK_MASK_CONST(0x1) << VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SHIFT)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_RANGE                   31:31
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_WOFFSET                 0x0
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_RATIO                   _MK_ENUM_CONST(0)
+#define VI_VB0_CHROMA_LINE_STRIDE_FIRST_0_VB0_CHROMA_LINE_STRIDE_SELECT_VALUE                   _MK_ENUM_CONST(1)
+
+// this reg. is used for VI2EPP syncpt only.
+// VI will based on num_lines = frame_height/EPP_NUM_OF_BUFFER_PER_FRAME,
+// send vi2epp_trigger for every num_lines
+
+// Register VI_EPP_LINES_PER_BUFFER_0  // number of buffers per output frame in EPP
+#define VI_EPP_LINES_PER_BUFFER_0                       _MK_ADDR_CONST(0x8b)
+#define VI_EPP_LINES_PER_BUFFER_0_SECURE                        0x0
+#define VI_EPP_LINES_PER_BUFFER_0_WORD_COUNT                    0x1
+#define VI_EPP_LINES_PER_BUFFER_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_READ_MASK                     _MK_MASK_CONST(0x1fff)
+#define VI_EPP_LINES_PER_BUFFER_0_WRITE_MASK                    _MK_MASK_CONST(0x1fff)
+// maximum 256 buffers per frame.
+// linesPerBuffer = FLOOR(eppLineCount/eppBufferCount)
+// linesPerBuffer must be > 2
+// eppLineCount must take into account any cropping in EPP.
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_FIELD                        (_MK_MASK_CONST(0x1fff) << VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SHIFT)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_RANGE                        12:0
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_WOFFSET                      0x0
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_EPP_LINES_PER_BUFFER_0_LINES_PER_BUFFER_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_BUFFER_RELEASE_OUTPUT1_0  // write to this register will decrease
+// BUFFER_COUNTER by 1
+#define VI_BUFFER_RELEASE_OUTPUT1_0                     _MK_ADDR_CONST(0x8c)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_SECURE                      0x0
+#define VI_BUFFER_RELEASE_OUTPUT1_0_WORD_COUNT                  0x1
+#define VI_BUFFER_RELEASE_OUTPUT1_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_FIELD                        (_MK_MASK_CONST(0x1) << VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SHIFT)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_RANGE                        0:0
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_WOFFSET                      0x0
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT1_0_BUFFER_RELEASE_OUTPUT1_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_BUFFER_RELEASE_OUTPUT2_0  
+#define VI_BUFFER_RELEASE_OUTPUT2_0                     _MK_ADDR_CONST(0x8d)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_SECURE                      0x0
+#define VI_BUFFER_RELEASE_OUTPUT2_0_WORD_COUNT                  0x1
+#define VI_BUFFER_RELEASE_OUTPUT2_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_READ_MASK                   _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_WRITE_MASK                  _MK_MASK_CONST(0x1)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_FIELD                        (_MK_MASK_CONST(0x1) << VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SHIFT)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_RANGE                        0:0
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_WOFFSET                      0x0
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_BUFFER_RELEASE_OUTPUT2_0_BUFFER_RELEASE_OUTPUT2_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0  // this is a debug register
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0                 _MK_ADDR_CONST(0x8e)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_SECURE                  0x0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_WORD_COUNT                      0x1
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_FIELD                      (_MK_MASK_CONST(0xff) << VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SHIFT)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_RANGE                      7:0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_WOFFSET                    0x0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0_BUFFER_COUNT_OUTPUT1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0  
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0                 _MK_ADDR_CONST(0x8f)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_SECURE                  0x0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_WORD_COUNT                      0x1
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_READ_MASK                       _MK_MASK_CONST(0xff)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_WRITE_MASK                      _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_FIELD                      (_MK_MASK_CONST(0xff) << VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SHIFT)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_RANGE                      7:0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_WOFFSET                    0x0
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0_BUFFER_COUNT_OUTPUT2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// register for SW to write to terminate MC BW
+
+// Register VI_TERMINATE_BW_FIRST_0  // write to this register will terminate
+// MC on BW operation in FIRST output.
+#define VI_TERMINATE_BW_FIRST_0                 _MK_ADDR_CONST(0x90)
+#define VI_TERMINATE_BW_FIRST_0_SECURE                  0x0
+#define VI_TERMINATE_BW_FIRST_0_WORD_COUNT                      0x1
+#define VI_TERMINATE_BW_FIRST_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_READ_MASK                       _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_FIRST_0_WRITE_MASK                      _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SHIFT                        _MK_SHIFT_CONST(0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_FIELD                        (_MK_MASK_CONST(0x1) << VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SHIFT)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_RANGE                        0:0
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_WOFFSET                      0x0
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_FIRST_0_TERMINATE_FIRST_BW_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register VI_TERMINATE_BW_SECOND_0  // write to this register will terminate
+// MC on BW operationn in SECOND output.
+#define VI_TERMINATE_BW_SECOND_0                        _MK_ADDR_CONST(0x91)
+#define VI_TERMINATE_BW_SECOND_0_SECURE                         0x0
+#define VI_TERMINATE_BW_SECOND_0_WORD_COUNT                     0x1
+#define VI_TERMINATE_BW_SECOND_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_RESET_MASK                     _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_SECOND_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_FIELD                      (_MK_MASK_CONST(0x1) << VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SHIFT)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_RANGE                      0:0
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_WOFFSET                    0x0
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_TERMINATE_BW_SECOND_0_TERMINATE_SECOND_BW_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// --------------------------------------------------------------------------
+//
+// Copyright (c) 2004-2005, NVIDIA Corp.
+// All Rights Reserved.
+//
+// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
+// the contents of this file may not be disclosed to third parties, copied or
+// duplicated in any form, in whole or in part, without the prior written
+// permission of NVIDIA Corp.
+//
+// RESTRICTED RIGHTS LEGEND:
+// Use, duplication or disclosure by the Government is subject to restrictions
+// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
+// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
+// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
+// rights reserved under the Copyright Laws of the United States.
+//
+// --------------------------------------------------------------------------
+//
+// Memory Controller Tiling definitions
+//
+//
+//  To enable tiling for a buffer in your module you'll want to include
+//  this spec file and then make use of either the ADD_TILE_MODE_REG_SPEC
+//  or ADD_TILE_MODE_REG_FIELD_SPEC macro.
+//
+//  For the ADD_TILE_MODE_REG_SPEC macro, the regp arg is added to the
+//  register name as a prefix to match the names of the other registers
+//  for this buffer. The fldp is the field name prefix to make the name
+//  unique so it works with arreggen generated reg blocks (e.g.):
+//
+//      // specify how addressing should occur for IB0 buffer
+//      ADD_TILE_MODE_REG_SPEC(IB0, IB0);
+//
+//  There's also a REG_RW_SPEC version, if you need to specify a special
+//  flag (e.g. rws for shadow, or rwt for trigger).
+//  
+//  For the ADD_TILE_MODE_REG_FIELD_SPEC macro, the fldp is the field
+//  name prefix and bitpos arg describes the starting bit position for
+//  this field within another register.
+//
+//  Like the register version, there's a REG_RW_FIELD_SPEC version if
+//  you need to set explicit bits other than "rw".
+//
+//  Note: this requires having at least NV_MC_TILE_MODEWIDTH bits of
+//  space available after bitpos (e.g.) in the register:
+//
+//      ADD_TILE_MODE_REG_FIELD_SPEC(REF, 16)   // This parameter specifies how addressing
+//                                              // for the REF buffer should occur
+//
+
+// Register VI_VB0_FIRST_BUFFER_ADDR_MODE_0  
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0                 _MK_ADDR_CONST(0x92)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_SECURE                  0x0
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_WORD_COUNT                      0x1
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_RESET_MASK                      _MK_MASK_CONST(0x101)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_READ_MASK                       _MK_MASK_CONST(0x101)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_WRITE_MASK                      _MK_MASK_CONST(0x101)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_FIELD                      (_MK_MASK_CONST(0x1) << VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SHIFT)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_RANGE                      0:0
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_WOFFSET                    0x0
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_LINEAR                     _MK_ENUM_CONST(0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_Y1_TILE_MODE_TILED                      _MK_ENUM_CONST(1)
+
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_FIELD                     (_MK_MASK_CONST(0x1) << VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SHIFT)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_RANGE                     8:8
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_WOFFSET                   0x0
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_LINEAR                    _MK_ENUM_CONST(0)
+#define VI_VB0_FIRST_BUFFER_ADDR_MODE_0_UV1_TILE_MODE_TILED                     _MK_ENUM_CONST(1)
+
+
+// Register VI_VB0_SECOND_BUFFER_ADDR_MODE_0  
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0                        _MK_ADDR_CONST(0x93)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_SECURE                         0x0
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_WORD_COUNT                     0x1
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_RESET_MASK                     _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_READ_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_WRITE_MASK                     _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_FIELD                     (_MK_MASK_CONST(0x1) << VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SHIFT)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_RANGE                     0:0
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_WOFFSET                   0x0
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_LINEAR                    _MK_ENUM_CONST(0)
+#define VI_VB0_SECOND_BUFFER_ADDR_MODE_0_Y2_TILE_MODE_TILED                     _MK_ENUM_CONST(1)
+
+//VIP Pattern Generator:
+// The VIP pattern generator is new as of AP15.  When enabled, it overrides the inputs from
+// the attached camera with internally generated pattern data, hsyncs, and vsyncs.  The
+// purpose of the pattern generator is to facilitate regression testing of the VI driver and
+// hardware without constraining the board level design.
+//
+// The pattern generator logic runs on the pd2vi_clock domain.  See the clock controller spec
+// for information on how to enable a loopback from the vi_sensor clock to the pd2vi_clock.
+//
+// The user must program the pattern width, pattern height, and bayer select registers prior to
+// enabling the pattern generator.  It is  illegal to change the values of those registers
+// without first disabling the pattern generator.
+//
+// The pattern generator has no concept of blanking time.  The width and the height of the
+// pattern should correspond to the full hblank+hactive and vblank+vactive
+//
+
+// Register VI_RESERVE_0_0  // reserved register for emergency ...
+// bits[13:0] are reserved for
+// VIP Pattern Gen (Pattern Width)
+#define VI_RESERVE_0_0                  _MK_ADDR_CONST(0x94)
+#define VI_RESERVE_0_0_SECURE                   0x0
+#define VI_RESERVE_0_0_WORD_COUNT                       0x1
+#define VI_RESERVE_0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_0_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  Program to *one less* than the desired
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_0_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_RANGE                     3:0
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  pattern width in clocks. (note that
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_1_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_RANGE                     7:4
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  there are 2 clocker per pixel for YUV422)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_2_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_RANGE                     11:8
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_0_0_nc_RESERVE_0_3_SHIFT)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_RANGE                     15:12
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_WOFFSET                   0x0
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_0_0_nc_RESERVE_0_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_1_0  // reserved register for emergency ...
+// bits[13:0] are reserved for
+// VIP Pattern Gen (Pattern Height)
+#define VI_RESERVE_1_0                  _MK_ADDR_CONST(0x95)
+#define VI_RESERVE_1_0_SECURE                   0x0
+#define VI_RESERVE_1_0_WORD_COUNT                       0x1
+#define VI_RESERVE_1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_1_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+//  Program to *one less* than the desired
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_0_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_RANGE                     3:0
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+//  pattern height in lines
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_1_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_RANGE                     7:4
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_2_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_RANGE                     11:8
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_1_0_nc_RESERVE_1_3_SHIFT)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_RANGE                     15:12
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_WOFFSET                   0x0
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_1_0_nc_RESERVE_1_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_2_0  // reserved register for emergency ...
+// bit 0 is reserved for VIP Pattern Gen Enable
+// bit 1 is reserved for VIP Pattern Gen BayerSelect
+#define VI_RESERVE_2_0                  _MK_ADDR_CONST(0x96)
+#define VI_RESERVE_2_0_SECURE                   0x0
+#define VI_RESERVE_2_0_WORD_COUNT                       0x1
+#define VI_RESERVE_2_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_RESET_MASK                       _MK_MASK_CONST(0xf)
+#define VI_RESERVE_2_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_2_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// 1 for BAYER pattern and 0 for YUV pattern
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_0_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_RANGE                     3:0
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_1_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_RANGE                     7:4
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_2_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_RANGE                     11:8
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_2_0_nc_RESERVE_2_3_SHIFT)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_RANGE                     15:12
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_WOFFSET                   0x0
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_2_0_nc_RESERVE_2_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_3_0  // reserved register for emergency ...
+#define VI_RESERVE_3_0                  _MK_ADDR_CONST(0x97)
+#define VI_RESERVE_3_0_SECURE                   0x0
+#define VI_RESERVE_3_0_WORD_COUNT                       0x1
+#define VI_RESERVE_3_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_3_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_0_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_RANGE                     3:0
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_1_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_RANGE                     7:4
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_2_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_RANGE                     11:8
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_3_0_nc_RESERVE_3_3_SHIFT)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_RANGE                     15:12
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_WOFFSET                   0x0
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_3_0_nc_RESERVE_3_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register VI_RESERVE_4_0  // reserved register for emergency ...
+#define VI_RESERVE_4_0                  _MK_ADDR_CONST(0x98)
+#define VI_RESERVE_4_0_SECURE                   0x0
+#define VI_RESERVE_4_0_WORD_COUNT                       0x1
+#define VI_RESERVE_4_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_READ_MASK                        _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_4_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_SHIFT                     _MK_SHIFT_CONST(0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_0_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_RANGE                     3:0
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_SHIFT                     _MK_SHIFT_CONST(4)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_1_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_RANGE                     7:4
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_1_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_SHIFT                     _MK_SHIFT_CONST(8)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_2_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_RANGE                     11:8
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_2_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_SHIFT                     _MK_SHIFT_CONST(12)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_FIELD                     (_MK_MASK_CONST(0xf) << VI_RESERVE_4_0_nc_RESERVE_4_3_SHIFT)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_RANGE                     15:12
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_WOFFSET                   0x0
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define VI_RESERVE_4_0_nc_RESERVE_4_3_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Memory Client Interface Hysteresis Registers
+// Memory Client Interface Fifo Control Register.
+// The registers below allow to optimize the synchronization timing in
+// the memory client asynchronous fifos. When they can be used depend on
+// the client and memory controller clock ratio.
+// Additionally, the RDMC_RDFAST/RDCL_RDFAST fields can increase power
+// consumption if the asynchronous fifo is implemented as a real ram.
+// There is no power impact on latch-based fifos. Flipflop-based fifos
+// do not use these fields.
+// See recommended settings below.
+//
+// !! IMPORTANT !!
+// The register fields can only be changed when the memory client async
+// fifos are empty.
+//
+// The register field ending with WRCL_MCLE2X (if any) can be set to improve
+// async fifo synchronization on the write side by one client clock cycle if
+// the memory controller clock frequency is less or equal to twice the client
+// clock frequency:
+//
+//      mcclk_freq <= 2 * clientclk_freq
+//
+// The register field ending with WRMC_CLLE2X (if any) can be set to improve
+// async fifo synchronization on the write side by one memory controller clock
+// cycle if the client clock frequency is less or equal to twice the memory
+// controller clock frequency:
+//
+//      clientclk_freq <= 2 * mcclk_freq
+//
+// The register field ending with RDMC_RDFAST (if any) can be set to improve async
+// fifo synchronization on the read side by one memory controller clock cycle.
+//
+// !! WARNING !!
+// RDMC_RDFAST can be used along with WRCL_MCLE2X only when:
+//
+//       mcclk_freq <= clientclk_freq
+//
+// The register field ending with RDCL_RDFAST (if any) can be set to improve async
+// fifo synchronization on the read side by one client clock cycle.
+//
+// !! WARNING !!
+// RDCL_RDFAST can be used along with WRMC_CLLE2X only when:
+//
+//       clientclk_freq <= mcclk_freq
+//
+// RECOMMENDED SETTINGS
+// # Client writing to fifo, memory controller reading from fifo
+// - mcclk_freq <= clientclk_freq
+//     You can enable both RDMC_RDFAST and WRCL_CLLE2X. If one of the fifos is
+//     a real ram and power is a concern, you should avoid enabling RDMC_RDFAST.
+// - clientclk_freq < mcclk_freq <= 2 * clientclk_freq
+//     You can enable RDMC_RDFAST or WRCL_MCLE2X, but because the client clock
+//     is slower, you should enable only WRCL_MCLE2X.
+// - 2 * clientclk_freq < mcclk_freq
+//     You can only enable RDMC_RDFAST. If one of the fifos is a real ram and
+//     power is a concern, you should avoid enabling RDMC_RDFAST.
+//
+// # Memory controller writing to fifo, client reading from fifo
+// - clientclk_freq <= mcclk_freq
+//     You can enable both RDCL_RDFAST and WRMC_CLLE2X. If one of the fifos is
+//     a real ram and power is a concern, you should avoid enabling RDCL_RDFAST.
+// - mcclk_freq < clientclk_freq <= 2 * mcclk_freq
+//     You can enable RDCL_RDFAST or WRMC_CLLE2X, but because the memory controller
+//     clock is slower, you should enable only WRMC_CLLE2X.
+// - 2 * mcclk_freq < clientclk_freq
+//     You can only enable RDCL_RDFAST. If one of the fifos is a real ram and
+//     power is a concern, you should avoid enabling RDCL_RDFAST.
+//
+// Memory Client Hysteresis Control Register
+// This register exists only for clients with hysteresis.
+// BUG 505006: Hysteresis configuration can only be updated when memory traffic is idle.
+// HYST_EN can be used to turn on or off the hysteresis logic.
+// HYST_REQ_TH is the threshold of pending requests required
+//   before allowing them to pass through
+//   (overriden after HYST_REQ_TM cycles).
+// Hysteresis logic will stop holding request after (1<<HYST_TM) cycles
+//   (this should not have to be used and is only a WAR for
+//   unexpected hangs).
+// Deep hysteresis is a second level of hysteresis on a longer time-frame.
+//   DHYST_TH is the size of the read burst (requests are held until there
+//   is space for the entire burst in the return data fifo).
+//   During a burst period, if there are no new requests after
+//   DHYST_TM cycles, then the burst is terminated early.
+
+// Register VI_MCCIF_VIRUV_HYST_0  
+#define VI_MCCIF_VIRUV_HYST_0                   _MK_ADDR_CONST(0x99)
+#define VI_MCCIF_VIRUV_HYST_0_SECURE                    0x0
+#define VI_MCCIF_VIRUV_HYST_0_WORD_COUNT                        0x1
+#define VI_MCCIF_VIRUV_HYST_0_RESET_VAL                         _MK_MASK_CONST(0xcf04ff06)
+#define VI_MCCIF_VIRUV_HYST_0_RESET_MASK                        _MK_MASK_CONST(0xffffffff)
+#define VI_MCCIF_VIRUV_HYST_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HYST_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HYST_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define VI_MCCIF_VIRUV_HYST_0_WRITE_MASK                        _MK_MASK_CONST(0xffffffff)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TM_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TM_FIELD                    (_MK_MASK_CONST(0xff) << VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TM_SHIFT)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TM_RANGE                    7:0
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TM_WOFFSET                  0x0
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TM_DEFAULT                  _MK_MASK_CONST(0x6)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TM_DEFAULT_MASK                     _MK_MASK_CONST(0xff)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TM_SHIFT                       _MK_SHIFT_CONST(8)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TM_FIELD                       (_MK_MASK_CONST(0xff) << VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TM_SHIFT)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TM_RANGE                       15:8
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TM_WOFFSET                     0x0
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TM_DEFAULT                     _MK_MASK_CONST(0xff)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TM_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TM_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TM_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TH_SHIFT                       _MK_SHIFT_CONST(16)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TH_FIELD                       (_MK_MASK_CONST(0xff) << VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TH_SHIFT)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TH_RANGE                       23:16
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TH_WOFFSET                     0x0
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TH_DEFAULT                     _MK_MASK_CONST(0x4)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TH_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TH_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_DHYST_TH_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_TM_SHIFT                        _MK_SHIFT_CONST(24)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_TM_FIELD                        (_MK_MASK_CONST(0xf) << VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_TM_SHIFT)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_TM_RANGE                        27:24
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_TM_WOFFSET                      0x0
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_TM_DEFAULT                      _MK_MASK_CONST(0xf)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_TM_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_TM_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_TM_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TH_SHIFT                    _MK_SHIFT_CONST(28)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TH_FIELD                    (_MK_MASK_CONST(0x7) << VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TH_SHIFT)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TH_RANGE                    30:28
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TH_WOFFSET                  0x0
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TH_DEFAULT                  _MK_MASK_CONST(0x4)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TH_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_REQ_TH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_SHIFT                        _MK_SHIFT_CONST(31)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_FIELD                        (_MK_MASK_CONST(0x1) << VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_SHIFT)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_RANGE                        31:31
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_WOFFSET                      0x0
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_INIT_ENUM                    ENABLE
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_ENABLE                       _MK_ENUM_CONST(1)
+#define VI_MCCIF_VIRUV_HYST_0_CBR_VIRUV2MC_HYST_EN_DISABLE                      _MK_ENUM_CONST(0)
+
+// Memory Client Hysteresis Control Register
+// This register exists only for clients with hysteresis.
+// BUG 505006: Hysteresis configuration can only be updated when memory traffic is idle.
+// HYST_EN can be used to turn on or off the hysteresis logic.
+// HYST_REQ_TH is the threshold of pending requests required
+//   before allowing them to pass through
+//   (overriden after HYST_REQ_TM cycles).
+
+// Register VI_MCCIF_VIWSB_HYST_0  
+#define VI_MCCIF_VIWSB_HYST_0                   _MK_ADDR_CONST(0x9a)
+#define VI_MCCIF_VIWSB_HYST_0_SECURE                    0x0
+#define VI_MCCIF_VIWSB_HYST_0_WORD_COUNT                        0x1
+#define VI_MCCIF_VIWSB_HYST_0_RESET_VAL                         _MK_MASK_CONST(0xc00001ff)
+#define VI_MCCIF_VIWSB_HYST_0_RESET_MASK                        _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWSB_HYST_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HYST_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HYST_0_READ_MASK                         _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWSB_HYST_0_WRITE_MASK                        _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TM_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TM_FIELD                    (_MK_MASK_CONST(0xfff) << VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TM_SHIFT)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TM_RANGE                    11:0
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TM_WOFFSET                  0x0
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TM_DEFAULT                  _MK_MASK_CONST(0x1ff)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TM_DEFAULT_MASK                     _MK_MASK_CONST(0xfff)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TM_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TM_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TH_SHIFT                    _MK_SHIFT_CONST(28)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TH_FIELD                    (_MK_MASK_CONST(0x7) << VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TH_SHIFT)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TH_RANGE                    30:28
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TH_WOFFSET                  0x0
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TH_DEFAULT                  _MK_MASK_CONST(0x4)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TH_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TH_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_REQ_TH_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_SHIFT                        _MK_SHIFT_CONST(31)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_FIELD                        (_MK_MASK_CONST(0x1) << VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_SHIFT)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_RANGE                        31:31
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_WOFFSET                      0x0
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_DEFAULT                      _MK_MASK_CONST(0x1)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_INIT_ENUM                    ENABLE
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_ENABLE                       _MK_ENUM_CONST(1)
+#define VI_MCCIF_VIWSB_HYST_0_CBW_VIWSB2MC_HYST_EN_DISABLE                      _MK_ENUM_CONST(0)
+
+// Memory Client Hysteresis Control Register
+// This register exists only for clients with hysteresis.
+// BUG 505006: Hysteresis configuration can only be updated when memory traffic is idle.
+// HYST_EN can be used to turn on or off the hysteresis logic.
+// HYST_REQ_TH is the threshold of pending requests required
+//   before allowing them to pass through
+//   (overriden after HYST_REQ_TM cycles).
+
+// Register VI_MCCIF_VIWU_HYST_0  
+#define VI_MCCIF_VIWU_HYST_0                    _MK_ADDR_CONST(0x9b)
+#define VI_MCCIF_VIWU_HYST_0_SECURE                     0x0
+#define VI_MCCIF_VIWU_HYST_0_WORD_COUNT                         0x1
+#define VI_MCCIF_VIWU_HYST_0_RESET_VAL                  _MK_MASK_CONST(0xc00001ff)
+#define VI_MCCIF_VIWU_HYST_0_RESET_MASK                         _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWU_HYST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HYST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HYST_0_READ_MASK                  _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWU_HYST_0_WRITE_MASK                         _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TM_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TM_FIELD                      (_MK_MASK_CONST(0xfff) << VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TM_SHIFT)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TM_RANGE                      11:0
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TM_WOFFSET                    0x0
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TM_DEFAULT                    _MK_MASK_CONST(0x1ff)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TM_DEFAULT_MASK                       _MK_MASK_CONST(0xfff)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TH_SHIFT                      _MK_SHIFT_CONST(28)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TH_FIELD                      (_MK_MASK_CONST(0x7) << VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TH_SHIFT)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TH_RANGE                      30:28
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TH_WOFFSET                    0x0
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TH_DEFAULT                    _MK_MASK_CONST(0x4)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_REQ_TH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_SHIFT                  _MK_SHIFT_CONST(31)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_FIELD                  (_MK_MASK_CONST(0x1) << VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_SHIFT)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_RANGE                  31:31
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_WOFFSET                        0x0
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_INIT_ENUM                      ENABLE
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_ENABLE                 _MK_ENUM_CONST(1)
+#define VI_MCCIF_VIWU_HYST_0_CBW_VIWU2MC_HYST_EN_DISABLE                        _MK_ENUM_CONST(0)
+
+// Memory Client Hysteresis Control Register
+// This register exists only for clients with hysteresis.
+// BUG 505006: Hysteresis configuration can only be updated when memory traffic is idle.
+// HYST_EN can be used to turn on or off the hysteresis logic.
+// HYST_REQ_TH is the threshold of pending requests required
+//   before allowing them to pass through
+//   (overriden after HYST_REQ_TM cycles).
+
+// Register VI_MCCIF_VIWV_HYST_0  
+#define VI_MCCIF_VIWV_HYST_0                    _MK_ADDR_CONST(0x9c)
+#define VI_MCCIF_VIWV_HYST_0_SECURE                     0x0
+#define VI_MCCIF_VIWV_HYST_0_WORD_COUNT                         0x1
+#define VI_MCCIF_VIWV_HYST_0_RESET_VAL                  _MK_MASK_CONST(0xc00001ff)
+#define VI_MCCIF_VIWV_HYST_0_RESET_MASK                         _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWV_HYST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HYST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HYST_0_READ_MASK                  _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWV_HYST_0_WRITE_MASK                         _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TM_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TM_FIELD                      (_MK_MASK_CONST(0xfff) << VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TM_SHIFT)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TM_RANGE                      11:0
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TM_WOFFSET                    0x0
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TM_DEFAULT                    _MK_MASK_CONST(0x1ff)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TM_DEFAULT_MASK                       _MK_MASK_CONST(0xfff)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TH_SHIFT                      _MK_SHIFT_CONST(28)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TH_FIELD                      (_MK_MASK_CONST(0x7) << VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TH_SHIFT)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TH_RANGE                      30:28
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TH_WOFFSET                    0x0
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TH_DEFAULT                    _MK_MASK_CONST(0x4)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_REQ_TH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_SHIFT                  _MK_SHIFT_CONST(31)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_FIELD                  (_MK_MASK_CONST(0x1) << VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_SHIFT)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_RANGE                  31:31
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_WOFFSET                        0x0
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_INIT_ENUM                      ENABLE
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_ENABLE                 _MK_ENUM_CONST(1)
+#define VI_MCCIF_VIWV_HYST_0_CBW_VIWV2MC_HYST_EN_DISABLE                        _MK_ENUM_CONST(0)
+
+// Memory Client Hysteresis Control Register
+// This register exists only for clients with hysteresis.
+// BUG 505006: Hysteresis configuration can only be updated when memory traffic is idle.
+// HYST_EN can be used to turn on or off the hysteresis logic.
+// HYST_REQ_TH is the threshold of pending requests required
+//   before allowing them to pass through
+//   (overriden after HYST_REQ_TM cycles).
+
+// Register VI_MCCIF_VIWY_HYST_0  
+#define VI_MCCIF_VIWY_HYST_0                    _MK_ADDR_CONST(0x9d)
+#define VI_MCCIF_VIWY_HYST_0_SECURE                     0x0
+#define VI_MCCIF_VIWY_HYST_0_WORD_COUNT                         0x1
+#define VI_MCCIF_VIWY_HYST_0_RESET_VAL                  _MK_MASK_CONST(0xc00001ff)
+#define VI_MCCIF_VIWY_HYST_0_RESET_MASK                         _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWY_HYST_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HYST_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HYST_0_READ_MASK                  _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWY_HYST_0_WRITE_MASK                         _MK_MASK_CONST(0xf0000fff)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TM_SHIFT                      _MK_SHIFT_CONST(0)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TM_FIELD                      (_MK_MASK_CONST(0xfff) << VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TM_SHIFT)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TM_RANGE                      11:0
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TM_WOFFSET                    0x0
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TM_DEFAULT                    _MK_MASK_CONST(0x1ff)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TM_DEFAULT_MASK                       _MK_MASK_CONST(0xfff)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TM_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TM_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TH_SHIFT                      _MK_SHIFT_CONST(28)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TH_FIELD                      (_MK_MASK_CONST(0x7) << VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TH_SHIFT)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TH_RANGE                      30:28
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TH_WOFFSET                    0x0
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TH_DEFAULT                    _MK_MASK_CONST(0x4)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TH_DEFAULT_MASK                       _MK_MASK_CONST(0x7)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TH_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_REQ_TH_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_SHIFT                  _MK_SHIFT_CONST(31)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_FIELD                  (_MK_MASK_CONST(0x1) << VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_SHIFT)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_RANGE                  31:31
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_WOFFSET                        0x0
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_DEFAULT                        _MK_MASK_CONST(0x1)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_INIT_ENUM                      ENABLE
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_ENABLE                 _MK_ENUM_CONST(1)
+#define VI_MCCIF_VIWY_HYST_0_CBW_VIWY2MC_HYST_EN_DISABLE                        _MK_ENUM_CONST(0)
+
+// CSI register spec
+// --------------------------------------------------------------------------
+// 
+// Copyright (c) 2004, NVIDIA Corp.
+// All Rights Reserved.
+// 
+// This is UNPUBLISHED PROPRIETARY SOURCE CODE of NVIDIA Corp.;
+// the contents of this file may not be disclosed to third parties, copied or
+// duplicated in any form, in whole or in part, without the prior written
+// permission of NVIDIA Corp.
+// 
+// RESTRICTED RIGHTS LEGEND:
+// Use, duplication or disclosure by the Government is subject to restrictions
+// as set forth in subdivision (c)(1)(ii) of the Rights in Technical Data
+// and Computer Software clause at DFARS 252.227-7013, and/or in similar or
+// successor clauses in the FAR, DOD or NASA FAR Supplement. Unpublished -
+// rights reserved under the Copyright Laws of the United States.
+// 
+// --------------------------------------------------------------------------
+// 
+// CSI (MIPI Camera Serial Interface) register definition
+
+// Register CSI_VI_INPUT_STREAM_CONTROL_0  // VI Input Stream Control
+#define CSI_VI_INPUT_STREAM_CONTROL_0                   _MK_ADDR_CONST(0x200)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_SECURE                    0x0
+#define CSI_VI_INPUT_STREAM_CONTROL_0_WORD_COUNT                        0x1
+#define CSI_VI_INPUT_STREAM_CONTROL_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_READ_MASK                         _MK_MASK_CONST(0x80)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_WRITE_MASK                        _MK_MASK_CONST(0x80)
+// VIP Start Frame Generation Don't use vi2csi_vip_vsync to generate start frame
+// (SF), or end frame (EF) markers in the pixel parser
+// output stream.
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SHIFT                  _MK_SHIFT_CONST(7)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_FIELD                  (_MK_MASK_CONST(0x1) << CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SHIFT)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_RANGE                  7:7
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_WOFFSET                        0x0
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_VSYNC_SF                       _MK_ENUM_CONST(0)    // // Pulses on vi2csi_vip_vsync will be used to
+// generate start frame (SF) and end frame (EF) markers
+// in the pixel parser output stream.
+// In AP15, only payload_only mode is supported in
+// the VIP input stream path, and this fields may 
+// always be programmed to VSYNC_SF.
+
+#define CSI_VI_INPUT_STREAM_CONTROL_0_VIP_SF_GEN_NO_VSYNC_SF                    _MK_ENUM_CONST(1)
+
+
+// Reserved address 513 [0x201] 
+// reserved for additional VI Input Stream control register
+// in case it is needed in the future
+
+// Register CSI_HOST_INPUT_STREAM_CONTROL_0  // Host Input Stream Control
+#define CSI_HOST_INPUT_STREAM_CONTROL_0                 _MK_ADDR_CONST(0x202)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_SECURE                  0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_WORD_COUNT                      0x1
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_READ_MASK                       _MK_MASK_CONST(0x1fff018f)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_WRITE_MASK                      _MK_MASK_CONST(0x1fff008f)
+// Host Data Format Data written to Y_FIFO_WRITE port should be in CSI
+// packet format. To indicate end of packet a 1 should
+// be written to HOST_END_OF_PACKET. A 1 should also be
+// written to HOST_END_OF_PACKET before writing the first
+// word of packet data to Y_FIFO_WRITE.
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_FIELD                  (_MK_MASK_CONST(0xf) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_RANGE                  3:0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_WOFFSET                        0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_PAYLOAD_ONLY                   _MK_ENUM_CONST(0)    // // Data written to Y_FIFO_WRITE port should be
+// CSI line payload data only (no header, no footer,
+// and  no short packets). A value of 1 should not
+// be written to HOST_END_OF_PACKET (end of packet
+// pulse only gets generated when a 1 is written to
+// this bit). 
+// First line will be indicated when one of the pixel
+// parsers is first enabled with its 
+// CSI_PPA/B_STREAM_SOURCE set to "HOST".
+// The values in the following PIXEL_STREAM_A/B_CONTROL0 
+// fields, for the pixel parser that is receiving host
+// data, will be ignored;
+// CSI_PPA/B_PACKET_HEADER overridden with "NOT_SENT",
+// CSI_PPA/B_DATA_IDENTIFIER overridden with "DISABLED",
+// CSI_PPA/B_WORD_COUNT_SELECT overridden with "REGISTER".
+// CSI_PPA/B_CRC_CHECK overridden with "DISABLE",
+// CSI_PPA/B_VIRTUAL_CHANNEL_ID,
+// CSI_PPA/B_EMBEDDED_DATA_OPTIONS, and
+// CSI_PPA/B_HEADER_EC_ENABLE.
+// CSI_PPA/B_DATA_TYPE should be programmed with the 
+// 6 bit data type that is to be used to interpret the
+// stream. CSI_PPA/B_WORD_COUNT should be programmed with
+// the number of bytes per line.
+
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_DATA_FORMAT_PACKETS                        _MK_ENUM_CONST(1)
+
+// Host Start Frame Generation Don't use CSI Host Line counter to generate start, or
+// End, of Frame control outputs. This setting should only
+// be used if HOST_DATA_FORMAT is set to PACKETS, and the
+// Host data stream has frame sync packets.
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SHIFT                       _MK_SHIFT_CONST(7)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_FIELD                       (_MK_MASK_CONST(0x1) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_RANGE                       7:7
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_WOFFSET                     0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_LINE_COUNTER                        _MK_ENUM_CONST(0)    // // CSI Host Line counter will be used to generate Frame
+// start and end control. To signal the start of the first
+// frame the pixel parser will send a SF control, and
+// signal start of frame mark, when it is first enabled
+// with Host as its source. This setting should be used 
+// when HOST_DATA_FORMAT is set to PAYLOAD_ONLY.
+
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_SF_GEN_SHORT_PACKETS                       _MK_ENUM_CONST(1)
+
+// Writing this bit with a 1 indicates End of Packet,
+// when CSI Host data is being received in Packet Format.
+// In Packet Format vi2csi_host_hsync is not used to 
+// indicate beginning of packet.
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_FIELD                        (_MK_MASK_CONST(0x1) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_RANGE                        8:8
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_WOFFSET                      0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_END_OF_PACKET_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Host Frame Height
+// Specifies the height of the host frame when the host
+// is supplying CSI format payload only data to one of 
+// the CSI pixel parsers.
+// Programmed Value = number of lines - 1
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_FIELD                 (_MK_MASK_CONST(0x1fff) << CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SHIFT)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_RANGE                 28:16
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_WOFFSET                       0x0
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_HOST_INPUT_STREAM_CONTROL_0_HOST_FRAME_HEIGHT_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Reserved address 515 [0x203] 
+// reserved for additional Host Input Stream control register
+// in case it is needed in the future
+
+// Register CSI_INPUT_STREAM_A_CONTROL_0  // CSI Input Stream A Control
+#define CSI_INPUT_STREAM_A_CONTROL_0                    _MK_ADDR_CONST(0x204)
+#define CSI_INPUT_STREAM_A_CONTROL_0_SECURE                     0x0
+#define CSI_INPUT_STREAM_A_CONTROL_0_WORD_COUNT                         0x1
+#define CSI_INPUT_STREAM_A_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x7f0001)
+#define CSI_INPUT_STREAM_A_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0xff0013)
+#define CSI_INPUT_STREAM_A_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0xff0013)
+#define CSI_INPUT_STREAM_A_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0xff0013)
+// CSI-A Data Lane
+//   0= 1 data lane
+//   1= 2 data lanes
+//   2= 3 data lanes (not supported on SC17 & SC25)
+//   3= 4 data lanes (not supported on SC17 & SC25)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SHIFT)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_RANGE                      1:0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_WOFFSET                    0x0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_DEFAULT                    _MK_MASK_CONST(0x1)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_DATA_LANE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Enables skip packet threshold feature. Skip packet feature is enabled.
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT                   _MK_SHIFT_CONST(4)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_RANGE                   4:4
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_WOFFSET                 0x0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_DISABLE                 _MK_ENUM_CONST(0)    // // Skip packet feature is disabled.     
+
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI-A Skip Packet Threshold
+//  This value is compared against the internal
+//  FIFO that buffer the input streams. A packet
+//  will be skipped (discarded) if the pixel
+//  stream processor is busy (probably due to
+//  padding process of a short line) and the
+//  number of entries in the internal FIFO
+//  exceeds this threshold value. Note that
+//  each entry in the internal FIFO buffer is
+//  four bytes.
+//  To turn off this feature, set the value
+//  to its maximum value (all ones).
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_FIELD                  (_MK_MASK_CONST(0xff) << CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SHIFT)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_RANGE                  23:16
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_WOFFSET                        0x0
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x7f)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0xff)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_A_CONTROL_0_CSI_A_SKIP_PACKET_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 517 [0x205] 
+// reserved for additional Input Stream control register
+// in case it is needed in the future
+
+// Register CSI_PIXEL_STREAM_A_CONTROL0_0  // CSI Pixel Stream A Control 0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0                   _MK_ADDR_CONST(0x206)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_SECURE                    0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_RESET_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_READ_MASK                         _MK_MASK_CONST(0x3b3ffff7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_WRITE_MASK                        _MK_MASK_CONST(0x3b3ffff7)
+// CSI Pixel Parser A Stream Source   Host
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_FIELD                       (_MK_MASK_CONST(0x7) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_RANGE                       2:0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_CSI_A                       _MK_ENUM_CONST(0)    // //   CSI Interface A
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_CSI_B                       _MK_ENUM_CONST(1)    // //   CSI Interface B
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_VI_PORT                     _MK_ENUM_CONST(6)    // //   VI port
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_STREAM_SOURCE_HOST                        _MK_ENUM_CONST(7)
+
+// CSI Pixel Parser A Packet Header processing
+//  This specifies whether packet header is
+//  sent in the beginning of packet or not.      Packet header is sent.
+//      This setting should be used if the
+//      stream source is CSI Interface A or B.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SHIFT                       _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_RANGE                       4:4
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_NOT_SENT                    _MK_ENUM_CONST(0)    // //      Packet header is not sent.
+//      This setting should not be used if the
+//      stream source is CSI Interface A or B.
+//      Unless CSI-A, or CSI-B, is operating in a
+//      stream capture debug mode.
+//      In this case, CSI_PPA_DATA_TYPE specifies
+//      the stream data format and the number
+//      of bytes per line/packet is
+//      specified by CSI_PPA_WORD_COUNT.
+//      This implies that a packet footer
+//      is also not sent.  In this case, no 
+//      packet footer CRC check should be performed.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PACKET_HEADER_SENT                        _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Data Identifier (DI) byte processing
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      Enabled  - Data Identifier byte in
+//      packet header should be compared against
+//      the CSI_PPA_DATA_TYPE and the
+//      CSI_PPA_VIRTUAL_CHANNEL_ID.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SHIFT                     _MK_SHIFT_CONST(5)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_FIELD                     (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_RANGE                     5:5
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_DISABLED                  _MK_ENUM_CONST(0)    // //      Disabled - Data Identifier byte in
+//      packet header should be ignored
+//      (not checked against CSI_PPA_DATA_TYPE
+//      and against CSI_PPA_VIRTUAL_CHANNEL_ID).
+//      In this case, CSI_PPA_DATA_TYPE specifies
+//      the stream data format.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_IDENTIFIER_ENABLED                   _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Word Count Select
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      The number of bytes per line is to be
+//      extracted from Word Count field in the
+//      packet header. Note that if the serial
+//      link is not error free, programming this
+//      bit to HEADER may be dangerous because 
+//      the word count information in the header 
+//      may be corrupted. 
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_RANGE                   6:6
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_REGISTER                        _MK_ENUM_CONST(0)    // //      Word Count in packet header is ignored
+//      and the number of bytes per line/packet
+//      is specified by CSI_PPA_WORD_COUNT. Payload
+//      CRC check will not be valid if the word
+//      count in CSI_PPA_WORD_COUNT is different 
+//      than the count in the packet header.
+//      It is recommended to always program
+//      this bit to REGISTER and always program
+//      CSI_PPA_WORD_COUNT.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_WORD_COUNT_SELECT_HEADER                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Data CRC Check
+//  This parameter specifies whether the last
+//  2 bytes of packet should be treated as
+//  CRC checksum and used to perform CRC check
+//  on the payload data. Note that in case there
+//  are 2 bytes of data CRC at the end of the
+//  packet, the packet word count does not
+//  include the CRC bytes.      Data CRC Check is enabled.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SHIFT                   _MK_SHIFT_CONST(7)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_RANGE                   7:7
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_DISABLE                 _MK_ENUM_CONST(0)    // //      Data CRC Check is disabled regardless
+//      of whether there are CRC checksum at
+//      the end of the packet.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_CRC_CHECK_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Data Type  This is CSI compatible data type as defined
+//  in CSI specification. If the source stream
+//  contains packet headers this value can be compared
+//  to the CSI Data Type value in the 6 LSB of the
+//  CSI Data Identifier (DI) byte. If the source stream
+//  doesn't contain packet headers, or CSI_PPA_DATA_IDENTIFIER
+//  is DISABLED, this value will be used to determine how
+//  the stream will be converted to pixels.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SHIFT                   _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_FIELD                   (_MK_MASK_CONST(0x3f) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RANGE                   13:8
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420_8                        _MK_ENUM_CONST(24)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420_10                       _MK_ENUM_CONST(25)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_LEG_YUV420_8                    _MK_ENUM_CONST(26)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420CSPS_8                    _MK_ENUM_CONST(28)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV420CSPS_10                   _MK_ENUM_CONST(29)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV422_8                        _MK_ENUM_CONST(30)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_YUV422_10                       _MK_ENUM_CONST(31)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB444                  _MK_ENUM_CONST(32)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB555                  _MK_ENUM_CONST(33)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB565                  _MK_ENUM_CONST(34)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB666                  _MK_ENUM_CONST(35)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RGB888                  _MK_ENUM_CONST(36)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW6                    _MK_ENUM_CONST(40)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW7                    _MK_ENUM_CONST(41)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW8                    _MK_ENUM_CONST(42)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW10                   _MK_ENUM_CONST(43)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW12                   _MK_ENUM_CONST(44)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_RAW14                   _MK_ENUM_CONST(45)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT1                 _MK_ENUM_CONST(48)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT2                 _MK_ENUM_CONST(49)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT3                 _MK_ENUM_CONST(50)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_DATA_TYPE_ARB_DT4                 _MK_ENUM_CONST(51)
+
+// CSI Pixel Parser A Virtual Channel Identifier  
+//  This is CSI compatible virtual channel
+//  identifier as defined in CSI specification.
+//  If the source stream contains packet headers
+//  and CSI_PPA_DATA_IDENTIFIER is ENABLED this
+//  value will be compared to the CSI Virtual
+//  Channel Identifier value in the 2 MSB of the
+//  CSI Data Identifier (DI) byte. This value will
+//  be ignored if the source stream doesn't contain
+//  packet headers, or CSI_PPA_DATA_IDENTIFIER is 
+//  DISABLED, then this value will be ignored.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SHIFT                  _MK_SHIFT_CONST(14)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_FIELD                  (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_RANGE                  15:14
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_ONE                    _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_TWO                    _MK_ENUM_CONST(1)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_THREE                  _MK_ENUM_CONST(2)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_VIRTUAL_CHANNEL_ID_FOUR                   _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser A Output Format Options
+//  This parameter specifies options for output data 
+//  format.       Output for storing RAW data to memory through
+//       ISP. Undefined LS color bits for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be zeroed.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_FIELD                       (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_RANGE                       19:16
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_ARBITRARY                   _MK_ENUM_CONST(0)    // //       Output as 8-bit arbitrary data stream
+//       This may be used for compressed JPEG stream
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_PIXEL                       _MK_ENUM_CONST(1)    // //       Output the normal 1 pixel/clock. Undefined 
+//       LS color bits for RGB_666, RGB_565, RGB_555,
+//       and RGB_444, will be zeroed.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_PIXEL_REP                   _MK_ENUM_CONST(2)    // //       Same as PIXEL except MS color bits, for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be 
+//       replicated to their undefined LS bits.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_OUTPUT_FORMAT_OPTIONS_STORE                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser A Embedded Data Options 
+//  This specifies how to deal with embedded
+//  data within the specified input stream
+//  assuming that the CSI_PPA_DATA_TYPE is not
+//  embedded data and assuming that embedded
+//  data is not already processed by other
+//  CSI pixel stream processor.       output embedded data as 8-bpp arbitrary
+//       data stream.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SHIFT                       _MK_SHIFT_CONST(20)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_FIELD                       (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_RANGE                       21:20
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_DISCARD                     _MK_ENUM_CONST(0)    // //       discard (throw away) embedded data
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_EMBEDDED_DATA_OPTIONS_EMBEDDED                    _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Pad Short Line
+//  This specifies how to deal with shorter than
+//  expected line (the number of bytes received
+//  is less than the specified word count)       short line is not padded (will output
+//       less pixels than expected).
+//       This option is not recommended and may
+//       cause other modules that receives CSI
+//       output stream to hang up.
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SHIFT                      _MK_SHIFT_CONST(24)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_RANGE                      25:24
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_WOFFSET                    0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_PAD0S                      _MK_ENUM_CONST(0)    // //       short line is padded by pixel of zeros
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_PAD1S                      _MK_ENUM_CONST(1)    // //       short line is padded by pixel of ones
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_SHORT_LINE_NOPAD                      _MK_ENUM_CONST(2)
+
+// CSI Pixel Parser A Packet Header Error Correction Enable
+//  This parameter specifies whether single bit
+//  errors in the packet header will be
+//  automatically corrected, or not.    Single bit errors in the header will not
+//    be corrected. Header ECC check will still
+//    set header ECC status bits and the packet
+//    will be processed by Pixel Parser A. DISABLE
+//    should not be used when processing interleaved
+//    streams (Same stream going to both PPA and PPB).
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SHIFT                    _MK_SHIFT_CONST(27)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_RANGE                    27:27
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_WOFFSET                  0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_ENABLE                   _MK_ENUM_CONST(0)    // //    Single bit errors in the header will be
+//    automatically corrected.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_HEADER_EC_ENABLE_DISABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Pad Frame
+//  This specifies how to deal with frames that are
+//  shorter (fewer lines) that expected. Short frames
+//  are usually caused by line packets being dropped
+//  because of packet errors. Expected frame height is
+//  specified in PPA_EXP_FRAME_HEIGHT. To do padding the
+//  value in CSI_PPA_WORD_COUNT needs to be set to the
+//  number of input bytes in each line's payload.  Short frames will not be padded out.   
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SHIFT                   _MK_SHIFT_CONST(28)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_FIELD                   (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_RANGE                   29:28
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_PAD0S                   _MK_ENUM_CONST(0)    // //  Lines of all zeros will be used to pad out frames
+//  that are shorter than expected height. 
+//  PPA_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD0S.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_PAD1S                   _MK_ENUM_CONST(1)    // //  Lines of all ones will be used to pad out frames
+//  that are shorter than expected height.      
+//  PPA_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD1S.
+
+#define CSI_PIXEL_STREAM_A_CONTROL0_0_CSI_PPA_PAD_FRAME_NOPAD                   _MK_ENUM_CONST(2)
+
+
+// Register CSI_PIXEL_STREAM_A_CONTROL1_0  // CSI Pixel Stream A Control 1
+#define CSI_PIXEL_STREAM_A_CONTROL1_0                   _MK_ADDR_CONST(0x207)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_SECURE                    0x0
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+// CSI Pixel Parser A Top Field Frame
+//  This parameter specifies the frame number for 
+//  top field detection for interlaced input video
+//  stream. Top Field is indicated when each of the
+//  least significant four bits of the frame number
+//  that has a one in its mask bit matches the 
+//  corresponding bit in this parameter. In other
+//  words, Top Field is detected when the bitwise
+//  AND of  
+// ~(CSI_PPA_TOP_FIELD_FRAME ^ <frame number>) & CSI_PPA_TOP_FIELD_FRAME_MASK
+//  is one. Frame Number is taken from the WC field
+//  of the Frame Start short packet.
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_RANGE                     3:0
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser A Top Field Frame Mask
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_FIELD                        (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SHIFT)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_RANGE                        7:4
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_CONTROL1_0_CSI_PPA_TOP_FIELD_FRAME_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_A_WORD_COUNT_0  // CSI Pixel Stream A Word Count
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0                 _MK_ADDR_CONST(0x208)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_SECURE                  0x0
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_WORD_COUNT                      0x1
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+// CSI Pixel Parser A Word Count
+//  This parameter specifies the number of
+//  bytes per line/packet in the case where
+//  Word Count field in packet header is not
+//  used or where packet header is not sent.
+//  This count does not includes the additional
+//  2 bytes of CRC checksum if data CRC check
+//  is enabled. 
+//  When the input stream comes from a CSI camera
+//  port, this parameter must be programmed when 
+//  CSI_PPA_PAD_SHORT_LINE is set to either PAD0S
+//  or PAD1S, no matter whether CSI_PPA_WORD_COUNT_SELECT
+//  is set to REGISTER or HEADER.
+//  When the input stream comes from the host path
+//  or from the VIP path, and the data mode is
+//  PAYLOAD_ONLY, this count must be programmed.
+// Given a line width of N pixels, the programming 
+//  value of this parameters is as follows
+//  --------------------------------------
+//  data format            value
+//  --------------------------------------
+//  YUV420_8               N bytes
+//  YUV420_10              N/4*5 bytes
+//  LEG_YUV420_8           N/2*3 bytes
+//  YUV422_8               N*2 bytes
+//  YUV422_10              N/2*5 bytes
+//  RGB888                 N*3 bytes 
+//  RGB666                 N/4*9 bytes                 
+//  RGB565                 N*2 bytes
+//  RGB555                 N*2 bytes 
+//  RGB444                 N*2 bytes 
+//  RAW6                   N/4*3 bytes
+//  RAW7                   N/8*7 bytes
+//  RAW8                   N bytes 
+//  RAW10                  N/4*5 bytes
+//  RAW12                  N/2*3 bytes
+//  RAW14                  N/4*7 bytes
+//  ---------------------------------------
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SHIFT)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_RANGE                        15:0
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_WORD_COUNT_0_CSI_PPA_WORD_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_A_GAP_0  // CSI Pixel Stream A Gap
+#define CSI_PIXEL_STREAM_A_GAP_0                        _MK_ADDR_CONST(0x209)
+#define CSI_PIXEL_STREAM_A_GAP_0_SECURE                         0x0
+#define CSI_PIXEL_STREAM_A_GAP_0_WORD_COUNT                     0x1
+#define CSI_PIXEL_STREAM_A_GAP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Minium number of viclk cycles from end of 
+// previous line (Video_control = EL_DATA) to start
+// of next line (Video_control = SL).
+// This parameter is to ensure that minimum H-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the line gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_FIELD                 (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_RANGE                 15:0
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_LINE_MIN_GAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minium number of viclk cycles from end of 
+// frame (Video_control = EF) to start of next
+// frame (Video_control = SF).
+// This parameter is to ensure that minimum V-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the frame gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_RANGE                        31:16
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_GAP_0_PPA_FRAME_MIN_GAP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_PPA_COMMAND_0  // CSI Pixel Parser A Command
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0                  _MK_ADDR_CONST(0x20a)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_SECURE                   0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_WORD_COUNT                       0x1
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_RESET_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_READ_MASK                        _MK_MASK_CONST(0xff17)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_WRITE_MASK                       _MK_MASK_CONST(0xff17)
+// CSI Pixel Parser A Enable
+//  This parameter controls CSI Pixel Parser A
+//  to start or stop receiving data.       reset (disable immediately)
+//  Enabling the pixel Parser does not enable 
+//  the corresponding input source to receive 
+//  data. If Pixel parser is enabled later than
+//  the  corresponding input source, csi will keep
+//  on rejecting incoming stream, till it encounters
+//  a valid SF. 
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_FIELD                     (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_RANGE                     1:0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_NOP                       _MK_ENUM_CONST(0)    // //       no operation
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_ENABLE                    _MK_ENUM_CONST(1)    // //       enable at the next frame start as
+//       specified by the CSI Start Marker
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_DISABLE                   _MK_ENUM_CONST(2)    // //       disable after current frame end and before
+//       next frame start.
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_ENABLE_RST                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser A Single Shot Mode SW should Clear it along with disabling the 
+// CSI_PPA_ENABLE, once a frame is captured
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SHIFT                        _MK_SHIFT_CONST(2)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_RANGE                        2:2
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_DISABLE                      _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_SINGLE_SHOT_ENABLE                       _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A VSYNC Start Marker  start of frame is indicated when VSYNC signal 
+//  is received. When the input stream is from the
+//  VIP path and the data mode is PACKET, then this
+//  field may be programmed to VSYNC.
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SHIFT                 _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_FIELD                 (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_RANGE                 4:4
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_FSPKT                 _MK_ENUM_CONST(0)    // //  Start of frame is indicated when a Frame
+//  Start short packet is received with a frame
+//  number whose least significant four bits are
+//  greater than, or equal to, 
+//  CSI_PPA_START_MARKER_FRAME_MIN and less than,
+//  or equal to, CSI_PPA_START_MARKER_FRAME_MAX.
+//  When the input stream is from a CSI port, or 
+//  from the host path, or from the VIP path and 
+//  the data mode is PAYLOAD_ONLY, then this field
+//  may be programmed to FSPKT.
+
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_VSYNC_START_MARKER_VSYNC                 _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser A Start Marker Minimum
+// Start Frame is indicated when Max condition below
+// is met and the least significant four bits of the
+// frame number are greater than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_RANGE                     11:8
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser A Start Marker Maximum
+// Start Frame is indicated when Min condition above
+// is met and the least significant four bits of the
+// frame number are less than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SHIFT                     _MK_SHIFT_CONST(12)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SHIFT)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_RANGE                     15:12
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPA_COMMAND_0_CSI_PPA_START_MARKER_FRAME_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 523 [0x20b] 
+
+// Reserved address 524 [0x20c] 
+
+// Reserved address 525 [0x20d] 
+
+// Reserved address 526 [0x20e] 
+// reserved for additional Pixel Parser control registers
+// in case it is needed in the future
+
+// Register CSI_INPUT_STREAM_B_CONTROL_0  // CSI Input Stream B Control
+#define CSI_INPUT_STREAM_B_CONTROL_0                    _MK_ADDR_CONST(0x20f)
+#define CSI_INPUT_STREAM_B_CONTROL_0_SECURE                     0x0
+#define CSI_INPUT_STREAM_B_CONTROL_0_WORD_COUNT                         0x1
+#define CSI_INPUT_STREAM_B_CONTROL_0_RESET_VAL                  _MK_MASK_CONST(0x3f0000)
+#define CSI_INPUT_STREAM_B_CONTROL_0_RESET_MASK                         _MK_MASK_CONST(0x7f0013)
+#define CSI_INPUT_STREAM_B_CONTROL_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_READ_MASK                  _MK_MASK_CONST(0x7f0013)
+#define CSI_INPUT_STREAM_B_CONTROL_0_WRITE_MASK                         _MK_MASK_CONST(0x7f0013)
+// CSI-B Data Lane
+//   0= 1 data lane
+//   1= 2 data lanes (not supported on SC17 & SC25)
+//   2= 3 data lanes (not supported on SC17 & SC25)
+//   3= 4 data lanes (not supported on SC17 & SC25)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SHIFT)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_RANGE                      1:0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_WOFFSET                    0x0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_DATA_LANE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Enables skip packet threshold feature. Skip packet feature is enabled.
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT                   _MK_SHIFT_CONST(4)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_FIELD                   (_MK_MASK_CONST(0x1) << CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SHIFT)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_RANGE                   4:4
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_WOFFSET                 0x0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_DISABLE                 _MK_ENUM_CONST(0)    // // Skip packet feature is disabled.     
+
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_ENABLE_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI-B Skip Packet Threshold
+//  This value is compared against the internal
+//  FIFO that buffer the input streams. A packet
+//  will be skipped (discarded) if the pixel
+//  stream processor is busy (probably due to
+//  padding process of a short line) and the
+//  number of entries in the internal FIFO
+//  exceeds this threshold value. Note that
+//  each entry in the internal FIFO buffer is
+//  four bytes.
+//  To turn off this feature, set the value
+//  to its maximum value (all ones).
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_FIELD                  (_MK_MASK_CONST(0x7f) << CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SHIFT)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_RANGE                  22:16
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_WOFFSET                        0x0
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_DEFAULT                        _MK_MASK_CONST(0x3f)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_DEFAULT_MASK                   _MK_MASK_CONST(0x7f)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_INPUT_STREAM_B_CONTROL_0_CSI_B_SKIP_PACKET_THRESHOLD_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Reserved address 528 [0x210] 
+// reserved for additional Input Stream control register
+// in case it is needed in the future
+
+// Register CSI_PIXEL_STREAM_B_CONTROL0_0  // CSI Pixel Stream A Control 0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0                   _MK_ADDR_CONST(0x211)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_SECURE                    0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_RESET_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_READ_MASK                         _MK_MASK_CONST(0x3b3ffff7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_WRITE_MASK                        _MK_MASK_CONST(0x3b3ffff7)
+// CSI Pixel Parser B Stream Source   Host
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_FIELD                       (_MK_MASK_CONST(0x7) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_RANGE                       2:0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_DEFAULT_MASK                        _MK_MASK_CONST(0x7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_CSI_A                       _MK_ENUM_CONST(0)    // //   CSI Interface A
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_CSI_B                       _MK_ENUM_CONST(1)    // //   CSI Interface B
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_VI_PORT                     _MK_ENUM_CONST(6)    // //   VI port
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_STREAM_SOURCE_HOST                        _MK_ENUM_CONST(7)
+
+// CSI Pixel Parser B Packet Header processing
+//  This specifies whether packet header is
+//  sent in the beginning of packet or not.      Packet header is sent.
+//      This setting should be used if the
+//      stream source is CSI Interface A or B.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SHIFT                       _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_RANGE                       4:4
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_NOT_SENT                    _MK_ENUM_CONST(0)    // //      Packet header is not sent.
+//      This setting should not be used if the
+//      stream source is CSI Interface A or B.
+//      Unless CSI-A, or CSI-B, is operating in a
+//      stream capture debug mode.
+//      In this case, CSI_PPB_DATA_TYPE specifies
+//      the stream data format and the number
+//      of bytes per line/packet is
+//      specified by CSI_PPB_WORD_COUNT.
+//      This implies that a packet footer
+//      is also not sent.  In this case, no 
+//      packet footer CRC check should be performed.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PACKET_HEADER_SENT                        _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Data Identifier (DI) byte processing
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      Enabled  - Data Identifier byte in
+//      packet header should be compared against
+//      the CSI_PPB_DATA_TYPE and the
+//      CSI_PPB_VIRTUAL_CHANNEL_ID.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SHIFT                     _MK_SHIFT_CONST(5)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_FIELD                     (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_RANGE                     5:5
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_DISABLED                  _MK_ENUM_CONST(0)    // //      Disabled - Data Identifier byte in
+//      packet header should be ignored
+//      (not checked against CSI_PPB_DATA_TYPE
+//      and against CSI_PPB_VIRTUAL_CHANNEL_ID).
+//      In this case, CSI_PPB_DATA_TYPE specifies
+//      the stream data format.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_IDENTIFIER_ENABLED                   _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Word Count Select
+//  This parameter is effective only if packet
+//  header is sent as part of the stream.      The number of bytes per line is to be
+//      extracted from Word Count field in the
+//      packet header. Note that if the serial
+//      link is not error free, programming this
+//      bit to HEADER may be dangerous because 
+//      the word count information in the header
+//      may be corrupted. 
+//
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_RANGE                   6:6
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_REGISTER                        _MK_ENUM_CONST(0)    // //      Word Count in packet header is ignored
+//      and the number of bytes per line/packet
+//      is specified by CSI_PPB_WORD_COUNT. Payload
+//      CRC check will not be valid if the word
+//      count in CSI_PPB_WORD_COUNT is different 
+//      than the count in the packet header.
+//      It is recommended to always program
+//      this bit to REGISTER and always program
+//      CSI_PPB_WORD_COUNT.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_WORD_COUNT_SELECT_HEADER                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Data CRC Check
+//  This parameter specifies whether the last
+//  2 bytes of packet should be treated as
+//  CRC checksum and used to perform CRC check
+//  on the payload data. Note that in case there
+//  are 2 bytes of data CRC at the end of the
+//  packet, the packet word count does not
+//  include the CRC bytes.      Data CRC Check is enabled.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SHIFT                   _MK_SHIFT_CONST(7)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_RANGE                   7:7
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_DISABLE                 _MK_ENUM_CONST(0)    // //      Data CRC Check is disabled regardless
+//      of whether there are CRC checksum at
+//      the end of the packet.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_CRC_CHECK_ENABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Data Type  This is CSI compatible data type as defined
+//  in CSI specification. If the source stream
+//  contains packet headers this value can be compared
+//  to the CSI Data Type value in the 6 LSB of the
+//  CSI Data Identifier (DI) byte. If the source stream
+//  doesn't contain packet headers, or CSI_PPB_DATA_IDENTIFIER
+//  is DISABLED, this value will be used to determine how
+//  the stream will be converted to pixels.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SHIFT                   _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_FIELD                   (_MK_MASK_CONST(0x3f) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RANGE                   13:8
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420_8                        _MK_ENUM_CONST(24)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420_10                       _MK_ENUM_CONST(25)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_LEG_YUV420_8                    _MK_ENUM_CONST(26)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420CSPS_8                    _MK_ENUM_CONST(28)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV420CSPS_10                   _MK_ENUM_CONST(29)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV422_8                        _MK_ENUM_CONST(30)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_YUV422_10                       _MK_ENUM_CONST(31)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB444                  _MK_ENUM_CONST(32)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB555                  _MK_ENUM_CONST(33)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB565                  _MK_ENUM_CONST(34)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB666                  _MK_ENUM_CONST(35)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RGB888                  _MK_ENUM_CONST(36)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW6                    _MK_ENUM_CONST(40)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW7                    _MK_ENUM_CONST(41)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW8                    _MK_ENUM_CONST(42)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW10                   _MK_ENUM_CONST(43)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW12                   _MK_ENUM_CONST(44)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_RAW14                   _MK_ENUM_CONST(45)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT1                 _MK_ENUM_CONST(48)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT2                 _MK_ENUM_CONST(49)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT3                 _MK_ENUM_CONST(50)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_DATA_TYPE_ARB_DT4                 _MK_ENUM_CONST(51)
+
+// CSI Pixel Parser B Virtual Channel Identifier  
+//  This is CSI compatible virtual channel
+//  identifier as defined in CSI specification.
+//  If the source stream contains packet headers
+//  and CSI_PPB_DATA_IDENTIFIER is ENABLED this
+//  value will be compared to the CSI Virtual
+//  Channel Identifier value in the 2 MSB of the
+//  CSI Data Identifier (DI) byte. This value will
+//  be ignored if the source stream doesn't contain
+//  packet headers, or CSI_PPB_DATA_IDENTIFIER is 
+//  DISABLED, then this value will be ignored.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SHIFT                  _MK_SHIFT_CONST(14)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_FIELD                  (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_RANGE                  15:14
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_ONE                    _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_TWO                    _MK_ENUM_CONST(1)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_THREE                  _MK_ENUM_CONST(2)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_VIRTUAL_CHANNEL_ID_FOUR                   _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser B Output Format Options
+//  This parameter specifies output data format.       Output for storing RAW data to memory through
+//       ISP. Undefined LS color bits for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be zeroed.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_FIELD                       (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_RANGE                       19:16
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_ARBITRARY                   _MK_ENUM_CONST(0)    // //       Output as 8-bit arbitrary data stream
+//       This may be used for compressed JPEG stream
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_PIXEL                       _MK_ENUM_CONST(1)    // //       Output the normal 1 pixel/clock. Undefined 
+//       LS color bits for RGB_666, RGB_565, RGB_555,
+//       and RGB_444, will be zeroed.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_PIXEL_REP                   _MK_ENUM_CONST(2)    // //       Same as PIXEL except MS color bits, for RGB_666, 
+//       RGB_565, RGB_555, and RGB_444, will be 
+//       replicated to their undefined LS bits.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_OUTPUT_FORMAT_OPTIONS_STORE                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser B Embedded Data Options 
+//  This specifies how to deal with embedded
+//  data within the specified input stream
+//  assuming that the CSI_PPB_DATA_TYPE is not
+//  embedded data and assuming that embedded
+//  data is not already processed by other
+//  CSI pixel stream processor.       output embedded data as 8-bpp arbitrary
+//       data stream.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SHIFT                       _MK_SHIFT_CONST(20)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_FIELD                       (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_RANGE                       21:20
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_DISCARD                     _MK_ENUM_CONST(0)    // //       discard (throw away) embedded data
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_EMBEDDED_DATA_OPTIONS_EMBEDDED                    _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Pad Short Line
+//  This specifies how to deal with shorter than
+//  expected line (the number of bytes received
+//  is less than the specified word count)       short line is not padded (will output
+//       less pixels than expected).
+//       This option is not recommended and may
+//       cause other modules that receives CSI
+//       output stream to hang up.
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SHIFT                      _MK_SHIFT_CONST(24)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_RANGE                      25:24
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_WOFFSET                    0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_PAD0S                      _MK_ENUM_CONST(0)    // //       short line is padded by pixel of zeros
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_PAD1S                      _MK_ENUM_CONST(1)    // //       short line is padded by pixel of ones
+//       such that the expected number of output
+//       pixels is correct. Due to the time
+//       required to do the padding, subsequent
+//       line packet maybe discarded and
+//       therefore may cause a short frame
+//       (total number of lines per frame is
+//       less than expected).
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_SHORT_LINE_NOPAD                      _MK_ENUM_CONST(2)
+
+// CSI Pixel Parser B Packet Header Error Correction Enable
+//  This parameter specifies whether single bit
+//  errors in the packet header will be
+//  automatically corrected, or not.    Single bit errors in the header will not
+//    be corrected. Header ECC check will still
+//    set header ECC status bits and the packet
+//    will be processed by Pixel Parser B. DISABLE
+//    should not be used when processing interleaved
+//    streams (Same stream going to both PPA and PPB).
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SHIFT                    _MK_SHIFT_CONST(27)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_FIELD                    (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_RANGE                    27:27
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_WOFFSET                  0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_ENABLE                   _MK_ENUM_CONST(0)    // //    Single bit errors in the header will be
+//    automatically corrected.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_HEADER_EC_ENABLE_DISABLE                  _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Pad Frame
+//  This specifies how to deal with frames that are
+//  shorter (fewer lines) that expected. Short frames
+//  are usually caused by line packets being dropped
+//  because of packet errors. Expected frame height is
+//  specified in PPB_EXP_FRAME_HEIGHT. To do padding the
+//  value in CSI_PPB_WORD_COUNT needs to be set to the
+//  number of input bytes in each lines payload.  Short frames will not be padded out.   
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SHIFT                   _MK_SHIFT_CONST(28)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_FIELD                   (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_RANGE                   29:28
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_WOFFSET                 0x0
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_PAD0S                   _MK_ENUM_CONST(0)    // //  Lines of all zeros will be used to pad out frames
+//  that are shorter than expected height.   
+//  PPB_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD0S.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_PAD1S                   _MK_ENUM_CONST(1)    // //  Lines of all ones will be used to pad out frames
+//  that are shorter than expected height.      
+//  PPB_EXP_FRAME_HEIGHT must be programmed to
+//  an appropriate value if this fields is set to PAD1S.
+
+#define CSI_PIXEL_STREAM_B_CONTROL0_0_CSI_PPB_PAD_FRAME_NOPAD                   _MK_ENUM_CONST(2)
+
+
+// Register CSI_PIXEL_STREAM_B_CONTROL1_0  // CSI Pixel Stream B Control 1
+#define CSI_PIXEL_STREAM_B_CONTROL1_0                   _MK_ADDR_CONST(0x212)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_SECURE                    0x0
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_WORD_COUNT                        0x1
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_RESET_MASK                        _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_READ_MASK                         _MK_MASK_CONST(0xff)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_WRITE_MASK                        _MK_MASK_CONST(0xff)
+// CSI Pixel Parser B Top Field Frame
+//  This parameter specifies the frame number for 
+//  top field detection for interlaced input video
+//  stream. Top Field is indicated when each of the
+//  least significant four bits of the frame number
+//  that has a one in its mask bit matches the 
+//  corresponding bit in this parameter. In other
+//  words, Top Field is detected when the bitwise
+//  AND of  
+// ~(CSI_PPB_TOP_FIELD_FRAME ^ <frame number>) & CSI_PPB_TOP_FIELD_FRAME_MASK
+//  is one. Frame Number is taken from the WC field
+//  of the Frame Start short packet.
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_RANGE                     3:0
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser B Top Field Frame Mask
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_FIELD                        (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SHIFT)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_RANGE                        7:4
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0xf)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_CONTROL1_0_CSI_PPB_TOP_FIELD_FRAME_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_B_WORD_COUNT_0  // CSI Pixel Stream A Word Count
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0                 _MK_ADDR_CONST(0x213)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_SECURE                  0x0
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_WORD_COUNT                      0x1
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_RESET_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_RESET_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_READ_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_WRITE_MASK                      _MK_MASK_CONST(0xffff)
+// CSI Pixel Parser B Word Count
+//  This parameter specifies the number of
+//  bytes per line/packet in the case where
+//  Word Count field in packet header is not
+//  used or where packet header is not sent.
+//  This count does not includes the additional
+//  2 bytes of CRC checksum if data CRC check
+//  is enabled.
+//  When the input stream comes from a CSI camera
+//  port, this parameter must be programmed when 
+//  CSI_PPB_PAD_SHORT_LINE is set to either PAD0S
+//  or PAD1S, no matter whether CSI_PPB_WORD_COUNT_SELECT
+//  is set to REGISTER or HEADER.
+//  When the input stream comes from the host path
+//  or from the VIP path, and the data mode is
+//  PAYLOAD_ONLY, this count must be programmed.
+// Given a line width of N pixels, the programming 
+//  value of this parameters is as follows
+//  --------------------------------------
+//  data format            value
+//  --------------------------------------
+//  YUV420_8               N bytes
+//  YUV420_10              N/4*5 bytes
+//  LEG_YUV420_8           N/2*3 bytes
+//  YUV422_8               N*2 bytes
+//  YUV422_10              N/2*5 bytes
+//  RGB888                 N*3 bytes 
+//  RGB666                 N/4*9 bytes                 
+//  RGB565                 N*2 bytes
+//  RGB555                 N*2 bytes 
+//  RGB444                 N*2 bytes 
+//  RAW6                   N/4*3 bytes
+//  RAW7                   N/8*7 bytes
+//  RAW8                   N bytes 
+//  RAW10                  N/4*5 bytes
+//  RAW12                  N/2*3 bytes
+//  RAW14                  N/4*7 bytes
+//  ---------------------------------------
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SHIFT)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_RANGE                        15:0
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_WORD_COUNT_0_CSI_PPB_WORD_COUNT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_B_GAP_0  // CSI Pixel Stream B Gap
+#define CSI_PIXEL_STREAM_B_GAP_0                        _MK_ADDR_CONST(0x214)
+#define CSI_PIXEL_STREAM_B_GAP_0_SECURE                         0x0
+#define CSI_PIXEL_STREAM_B_GAP_0_WORD_COUNT                     0x1
+#define CSI_PIXEL_STREAM_B_GAP_0_RESET_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_RESET_MASK                     _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_SW_DEFAULT_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_READ_MASK                      _MK_MASK_CONST(0xffffffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_WRITE_MASK                     _MK_MASK_CONST(0xffffffff)
+// Minium number of viclk cycles from end of 
+// previous line (Video_control = EL_DATA) to start
+// of next line (Video_control = SL).
+// This parameter is to ensure that minimum H-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the line gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_FIELD                 (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_RANGE                 15:0
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_DEFAULT_MASK                  _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_LINE_MIN_GAP_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Minium number of viclk cycles from end of 
+// frame (Video_control = EF) to start of next
+// frame (Video_control = SF).
+// This parameter is to ensure that minimum V-blank
+// time requirement of VI/ISP is satisfied.
+// This field takes effect only when the frame gap 
+// of the input stream is less than the specified
+// value.
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_FIELD                        (_MK_MASK_CONST(0xffff) << CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SHIFT)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_RANGE                        31:16
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_DEFAULT_MASK                 _MK_MASK_CONST(0xffff)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_GAP_0_PPB_FRAME_MIN_GAP_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_PPB_COMMAND_0  // CSI Pixel Parser B Command
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0                  _MK_ADDR_CONST(0x215)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_SECURE                   0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_WORD_COUNT                       0x1
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_RESET_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_READ_MASK                        _MK_MASK_CONST(0xff17)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_WRITE_MASK                       _MK_MASK_CONST(0xff17)
+// CSI Pixel Parser B Enable
+//  This parameter controls CSI Pixel Parser B
+//  to start or stop receiving data.       reset (disable immediately)
+//  Enabling the pixel Parser does not enable 
+//  the corresponding input source to receive 
+//  data. If Pixel parser is enabled later than
+//  the  corresponding input source, csi will keep
+//  on rejecting incoming stream, till it encounters
+//  a valid SF.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_FIELD                     (_MK_MASK_CONST(0x3) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_RANGE                     1:0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_DEFAULT_MASK                      _MK_MASK_CONST(0x3)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_NOP                       _MK_ENUM_CONST(0)    // //       no operation
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_ENABLE                    _MK_ENUM_CONST(1)    // //       enable at the next frame start as
+//       specified by the CSI Start Marker
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_DISABLE                   _MK_ENUM_CONST(2)    // //       disable after current frame end and before
+//       next frame start.
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_ENABLE_RST                       _MK_ENUM_CONST(3)
+
+// CSI Pixel Parser B Single Shot Mode SW should Clear it alongwith disabling the 
+// CSI_PPB_ENABLE, once a frame is captured
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SHIFT                        _MK_SHIFT_CONST(2)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_RANGE                        2:2
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_DISABLE                      _MK_ENUM_CONST(0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_SINGLE_SHOT_ENABLE                       _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B VSYNC Start Marker  Start of frame is indicated when VSYNC signal 
+//  is received. When the input stream is from the
+//  VIP path and the data mode is PACKET, then this
+//  field may be programmed to VSYNC.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SHIFT                 _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_FIELD                 (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_RANGE                 4:4
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_WOFFSET                       0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_FSPKT                 _MK_ENUM_CONST(0)    // //      Start of frame is indicated when a Frame
+//    Start short packet is received with a frame
+//    number who's least significant four bits are
+//    greater than, or equal to, 
+//    CSI_PPB_START_MARKER_FRAME_MIN and less than,
+//    or equal to, CSI_PPB_START_MARKER_FRAME_MAX.
+//  When the input stream is from a CSI port, or 
+//  from the host path, or from the VIP path and 
+//  the data mode is PAYLOAD_ONLY, then this field
+//  may be programmed to FSPKT.
+
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_VSYNC_START_MARKER_VSYNC                 _MK_ENUM_CONST(1)
+
+// CSI Pixel Parser B Start Marker Minimum
+// Start Frame is indicated when Max condition below
+// is met and the least significant four bits of the
+// frame number are greater than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_RANGE                     11:8
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MIN_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// CSI Pixel Parser B Start Marker Maximum
+// Start Frame is indicated when Min condition above
+// is met and the least significant four bits of the
+// frame number are less than, or equal to, this value.
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SHIFT                     _MK_SHIFT_CONST(12)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_FIELD                     (_MK_MASK_CONST(0xf) << CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SHIFT)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_RANGE                     15:12
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_WOFFSET                   0x0
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_PPB_COMMAND_0_CSI_PPB_START_MARKER_FRAME_MAX_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Reserved address 534 [0x216] 
+
+// Reserved address 535 [0x217] 
+
+// Reserved address 536 [0x218] 
+
+// Reserved address 537 [0x219] 
+// reserved for additional Pixel Parser control registers
+// in case it is needed in the future
+
+// Register CSI_PHY_CIL_COMMAND_0  // CSI Phy and CIL Command
+#define CSI_PHY_CIL_COMMAND_0                   _MK_ADDR_CONST(0x21a)
+#define CSI_PHY_CIL_COMMAND_0_SECURE                    0x0
+#define CSI_PHY_CIL_COMMAND_0_WORD_COUNT                        0x1
+#define CSI_PHY_CIL_COMMAND_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_RESET_MASK                        _MK_MASK_CONST(0x30003)
+#define CSI_PHY_CIL_COMMAND_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_READ_MASK                         _MK_MASK_CONST(0x30003)
+#define CSI_PHY_CIL_COMMAND_0_WRITE_MASK                        _MK_MASK_CONST(0x30003)
+// CSI A Phy and CIL Enable
+//  This parameter controls CSI A Phy and CIL
+//  receiver to start or stop receiving data.    disable (reset)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_FIELD                        (_MK_MASK_CONST(0x3) << CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SHIFT)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_RANGE                        1:0
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_WOFFSET                      0x0
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_NOP                  _MK_ENUM_CONST(0)    // //    no operation
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_ENABLE                       _MK_ENUM_CONST(1)    // //    enable
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_A_PHY_CIL_ENABLE_DISABLE                      _MK_ENUM_CONST(2)
+
+// CSI B Phy and CIL Enable
+//  This parameter controls CSI B Phy and CIL
+//  receiver to start or stop receiving data.    disable (reset)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_FIELD                        (_MK_MASK_CONST(0x3) << CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SHIFT)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_RANGE                        17:16
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_WOFFSET                      0x0
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_DEFAULT_MASK                 _MK_MASK_CONST(0x3)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_NOP                  _MK_ENUM_CONST(0)    // //    no operation
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_ENABLE                       _MK_ENUM_CONST(1)    // //    enable
+
+#define CSI_PHY_CIL_COMMAND_0_CSI_B_PHY_CIL_ENABLE_DISABLE                      _MK_ENUM_CONST(2)
+
+
+// Register CSI_PHY_CILA_CONTROL0_0  // CSI-A Phy and CIL Control
+#define CSI_PHY_CILA_CONTROL0_0                 _MK_ADDR_CONST(0x21b)
+#define CSI_PHY_CILA_CONTROL0_0_SECURE                  0x0
+#define CSI_PHY_CILA_CONTROL0_0_WORD_COUNT                      0x1
+#define CSI_PHY_CILA_CONTROL0_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILA_CONTROL0_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILA_CONTROL0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILA_CONTROL0_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+// When moving from LP mode to High Speed (LP11->LP01->LP00),
+// this setting determines how many csicil clock cycles (72 MHz
+// lp clock cycles) to wait, after LP00, 
+// before starting to look at the data.
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_FIELD                   (_MK_MASK_CONST(0xf) << CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SHIFT)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_RANGE                   3:0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_WOFFSET                 0x0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_DEFAULT                 _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_THS_SETTLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// The LP signals are sampled using csi_cil_clk.
+// Normally this happens on 2 clock edges assuming
+// the clock is running at least 50 Mhz.  If the
+// clock needs to run slower, then this bit can be
+// SET so that the sampling takes place on a single
+// edge (clock rate is 25 Mhz min).  This sampling
+// may not be as reliable so setting this bit is
+// not recommended.
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SHIFT)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_RANGE                        4:4
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_WOFFSET                      0x0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_SINGLE_SAMPLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// The LP signals should sequence through LP11->LP01->LP00 state,
+// to indicate to CLOCK CIL about the mode switching to HS Rx mode.
+// In case Camera is enabled earlier than CIL , it is highly likely
+// that camera sends this control sequence sooner than cil can detect it.
+// Enabling this bit allows the CLOCK CIL to overlook the LP control sequence
+// and step in HS Rx mode directly looking at LP00 only.
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SHIFT                        _MK_SHIFT_CONST(5)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SHIFT)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_RANGE                        5:5
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_WOFFSET                      0x0
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILA_CONTROL0_0_CILA_BYPASS_LP_SEQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PHY_CILB_CONTROL0_0  // CSI-B Phy and CIL Control
+#define CSI_PHY_CILB_CONTROL0_0                 _MK_ADDR_CONST(0x21c)
+#define CSI_PHY_CILB_CONTROL0_0_SECURE                  0x0
+#define CSI_PHY_CILB_CONTROL0_0_WORD_COUNT                      0x1
+#define CSI_PHY_CILB_CONTROL0_0_RESET_VAL                       _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILB_CONTROL0_0_RESET_MASK                      _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILB_CONTROL0_0_SW_DEFAULT_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_SW_DEFAULT_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_READ_MASK                       _MK_MASK_CONST(0x3f)
+#define CSI_PHY_CILB_CONTROL0_0_WRITE_MASK                      _MK_MASK_CONST(0x3f)
+// When moving from LP mode to High Speed (LP11->LP01->LP00),
+// this setting determines how many  csicil clock cycles (72 MHz
+// lp clock cycles) to wait, after LP00,
+// before starting to look at the data.
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_FIELD                   (_MK_MASK_CONST(0xf) << CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SHIFT)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_RANGE                   3:0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_WOFFSET                 0x0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_DEFAULT                 _MK_MASK_CONST(0x2)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_DEFAULT_MASK                    _MK_MASK_CONST(0xf)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_THS_SETTLE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// see CILA_SINGLE_SAMPLE above
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SHIFT)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_RANGE                        4:4
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_WOFFSET                      0x0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_SINGLE_SAMPLE_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// see CILA_BYPASS_LP_SEQ above
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SHIFT                        _MK_SHIFT_CONST(5)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_FIELD                        (_MK_MASK_CONST(0x1) << CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SHIFT)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_RANGE                        5:5
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_WOFFSET                      0x0
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PHY_CILB_CONTROL0_0_CILB_BYPASS_LP_SEQ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+
+// Reserved address 541 [0x21d] 
+// reserved for additional Input Stream control register
+// in case it is needed in the future
+
+// Register CSI_CSI_PIXEL_PARSER_STATUS_0  // Pixel Parser Status
+// These status bits are cleared to
+// zero when its bit position is written with one. For
+// example write 0x2 to CSI_PIXEL_PARSER_STATUS will 
+// clear only PPA_ILL_WD_CNT.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0                   _MK_ADDR_CONST(0x21e)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_SECURE                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_WORD_COUNT                        0x1
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_READ_MASK                         _MK_MASK_CONST(0xcfffcfff)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// Header Error Corrected, Set when a packet that was
+// processed by PPA has a single bit header error. This error
+// will be detected by the headers ECC, and corrected by
+// it if header error correction is enabled 
+// (CSI_A_HEADER_EC_ENABLE = 0). This flag will be set and 
+// the packet will be processed even if the error is not
+// corrected.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_RANGE                     0:0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_HDR_ERR_COR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Illegal Word Count, set when a line with a word count that
+// doesn't generate an integer number of pixels (Unused bytes
+// at the end of payload) is processed by PPA.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SHIFT                      _MK_SHIFT_CONST(1)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_RANGE                      1:1
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_ILL_WD_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Short Line Processed, Set when a line with a payload that
+// is shorter than its packet header word count is processed
+// by PPA.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SHIFT                    _MK_SHIFT_CONST(2)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_RANGE                    2:2
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PROCESSED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Short Line Packet Dropped, set when a in coming packet
+// gets dropped because the input FIFO level reaches
+// CSI_A_SKIP_PACKET_THRESHOLD when padding a short line.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SHIFT                  _MK_SHIFT_CONST(3)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_RANGE                  3:3
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SL_PKT_DROPPED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PayLoad CRC Error, Set when a packet that was processed by
+// PPA had a payload CRC error.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SHIFT                      _MK_SHIFT_CONST(4)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_RANGE                      4:4
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_PL_CRC_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FIFO Overflow, set when the fifo that is feeding packets
+// to PPA overflows.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SHIFT                       _MK_SHIFT_CONST(5)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_RANGE                       5:5
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_FIFO_OVRF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Stream Error, set when the control output of PPA doesn't
+// follow the correct sequence. The correct sequence for CSI
+// is: SF -> (SL_DATA or EF), SL_DATA -> (DATA or EL_DATA),
+// DATA -> EL_DATA, EL_DATA -> (SL_DATA or EF), EF -> SF.
+// Stream Errors can be caused by receiving a corrupted
+// stream, or a CSI RTL bug.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SHIFT                  _MK_SHIFT_CONST(6)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_RANGE                  6:6
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_STMERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPA receives a short frame. This bit gets
+// set even if CSI_PPA_PAD_FRAME specifies that short frames
+// are to be padded to the correct line length.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SHIFT                     _MK_SHIFT_CONST(7)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_RANGE                     7:7
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SHORT_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPA receives a SF when it is expecting an EF.
+// This happens when EF of the frame gets corrupted before arriving CSI.
+// CSI-PPA will insert a fake EF and the drop the current 
+// frame with Correct SF.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_RANGE                        8:8
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_EXTRA_SF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPA receives a request to output a line
+// that is not in the active part of the frame output. That
+// is after EF and before SF, or before start marker is found.
+// The interframe line will not be outputted by the Pixel 
+// Parser.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SHIFT                 _MK_SHIFT_CONST(9)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_RANGE                 9:9
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_INTERFRAME_LINE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// PPA Spare Status bit. This bit will get set when Pixel Parser
+// A has a line timeout. Line timeout needs to be enabled by setting
+// PPA_ENABLE_LINE_TIMEOUT and programming PPA_MAX_CLOCKS for
+// the MAX clocks between lines.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(10)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_RANGE                  10:10
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PPA Spare Status bit.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(11)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_RANGE                  11:11
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPA_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when header parser A
+// parses a header with a multi bit error. This error will
+// be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(14)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_RANGE                     14:14
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPA_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when header parser B
+// parses a header with a multi bit error. This error will
+// be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.a multi bit error. This error will
+// be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(15)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_RANGE                     15:15
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPB_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Header Error Corrected, set when a packet that was
+// processed by PPB has a single bit header error. This error
+// will be detected by the headers ECC, and corrected by
+// it if header error correction is enabled 
+// (CSI_B_HEADER_EC_ENABLE = 0). This flag will be set and 
+// the packet will be processed even if the error is not
+// corrected.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_RANGE                     16:16
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_HDR_ERR_COR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Illegal Word Count, set when a line with a word count that
+// doesn't generate an integer number of pixels (Unused bytes
+// at the end of payload) is processed by PPB.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SHIFT                      _MK_SHIFT_CONST(17)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_RANGE                      17:17
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_ILL_WD_CNT_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Short Line Processed, Set when a line with a payload that
+// is shorter than its packet header word count is processed
+// by PPB.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SHIFT                    _MK_SHIFT_CONST(18)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_RANGE                    18:18
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PROCESSED_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Short Line Packet Dropped, set when a in coming packet
+// gets dropped because the input FIFO level reaches
+// CSI_B_SKIP_PACKET_THRESHOLD when padding a short line.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SHIFT                  _MK_SHIFT_CONST(19)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_RANGE                  19:19
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SL_PKT_DROPPED_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PayLoad CRC Error, Set when a packet that was processed
+// by PPB had a payload CRC error.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SHIFT                      _MK_SHIFT_CONST(20)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_RANGE                      20:20
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_PL_CRC_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// FIFO Overflow, set when the fifo that is feeding packets
+// to PPB overflows.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SHIFT                       _MK_SHIFT_CONST(21)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_RANGE                       21:21
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_FIFO_OVRF_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Stream Error, set when the control output of PPB doesn't
+// follow the correct sequence. The correct sequence for CSI
+// is: SF -> (SL_DATA or EF), SL_DATA -> (DATA or EL_DATA),
+// DATA -> EL_DATA, EL_DATA -> (SL_DATA or EF), EF -> SF.
+// Stream Errors can be caused by receiving a corrupted
+// stream, or a CSI RTL bug.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SHIFT                  _MK_SHIFT_CONST(22)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_RANGE                  22:22
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_STMERR_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPB receives a short frame. This bit gets
+// set even if CSI_PPB_PAD_FRAME specifies that short frames
+// are to be padded to the correct line length.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SHIFT                     _MK_SHIFT_CONST(23)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_RANGE                     23:23
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SHORT_FRAME_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPB receives a SF when it is expecting an EF. 
+// This happens when EF of the frame gets corrupted before arriving CSI.
+// CSI-PPB will insert a fake EF and the drop the current 
+// frame with Correct SF.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SHIFT                        _MK_SHIFT_CONST(24)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_RANGE                        24:24
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_EXTRA_SF_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Set when CSI-PPB receives a request to output a line
+// that is not in the active part of the frame output. That
+// is after EF and before SF, or before start marker is found.
+// The interframe line will not be outputted by the Pixel 
+// Parser.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SHIFT                 _MK_SHIFT_CONST(25)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_RANGE                 25:25
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_INTERFRAME_LINE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// PPB Spare Status bit. This bit will get set when Pixel Parser
+// B has a line timeout. Line timeout needs to be enabled by setting
+// PPB_ENABLE_LINE_TIMEOUT and programming PPB_MAX_CLOCKS for
+// the MAX clocks between lines.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(26)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_RANGE                  26:26
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// PPB Spare Status bit.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(27)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_RANGE                  27:27
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_PPB_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when the VI port header
+// parser parses a header with a multi bit error. This error
+// will be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(30)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_RANGE                     30:30
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPV_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Uncorrectable Header Error, Set when the Host port header
+// parser parses a header with a multi bit error. This error
+// will be detected by the headers ECC, but can't be corrected.
+// The packet will be discarded.
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SHIFT                     _MK_SHIFT_CONST(31)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_RANGE                     31:31
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_STATUS_0_HPH_UNC_HDR_ERR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CSI_CIL_STATUS_0  // CSI Control and Interface Logic Status
+// These status bits are cleared to
+// zero when its bit position is written with one. For
+// example write 0x2 to CSI_CIL_STATUS will clear only
+// CILA_SOT_MB_ERR.
+#define CSI_CSI_CIL_STATUS_0                    _MK_ADDR_CONST(0x21f)
+#define CSI_CSI_CIL_STATUS_0_SECURE                     0x0
+#define CSI_CSI_CIL_STATUS_0_WORD_COUNT                         0x1
+#define CSI_CSI_CIL_STATUS_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_RESET_MASK                         _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_READ_MASK                  _MK_MASK_CONST(0x1ff81ff)
+#define CSI_CSI_CIL_STATUS_0_WRITE_MASK                         _MK_MASK_CONST(0x0)
+// Start of Transmission Single Bit Error, set when CIL-A 
+// detects a single bit error in one of the 
+// packets Start of Transmission bytes. The packet will be
+// sent to the CSI-A for processing.
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_RANGE                      0:0
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_SB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Start of Transmission Multi Bit Error, set when CIL-A
+// detects a multi bit start of transmission byte error in
+// one of the packets SOT bytes. The packet will be discarded.
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SHIFT                      _MK_SHIFT_CONST(1)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_RANGE                      1:1
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SOT_MB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Sync Escape Error, set when CIL-A detects that the wrong 
+// (non-multiple of 8) number of bits have been received for
+// an Escape Command, or Data Byte.
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SHIFT                    _MK_SHIFT_CONST(2)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_RANGE                    2:2
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SYNC_ESC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Escape Mode Entry Error, set when CIL-A detects an escape
+// mode entry error. The Escape mode command byte will not be
+// received.
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SHIFT                   _MK_SHIFT_CONST(3)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_RANGE                   3:3
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_WOFFSET                 0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_ENTRY_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Control Error, set when CIL-A detects LP state 01 or 10
+// followed by a stop state (LP11) instead of transitioning
+// into the Escape mode or Turn Around mode (LP00).
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_RANGE                        4:4
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_WOFFSET                      0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_CTRL_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Escape Mode Command Received, set when CIL-A receives an
+// Escape Mode Command byte. The Command Byte can be read 
+// from bits 7-0 of ESCAPE_MODE_COMMAND.
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SHIFT                     _MK_SHIFT_CONST(5)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_RANGE                     5:5
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_WOFFSET                   0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_CMD_REC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Escape Mode Data Received, set when CIL-A receives an
+// Escape Mode Data byte. The Data Byte can be read 
+// from bits 7-0 of ESCAPE_MODE_DATA. This status bit will
+// will also be cleared when CILA_ESC_CMD_REC is set.
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SHIFT                    _MK_SHIFT_CONST(6)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_RANGE                    6:6
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_ESC_DATA_REC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CILA Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(7)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_RANGE                  7:7
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// CILA Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(8)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_RANGE                  8:8
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILA_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// MIPI Auto Calibrate done, set when the auto calibrate 
+// sequence for MIPI pad bricks is done.
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SHIFT                   _MK_SHIFT_CONST(15)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_RANGE                   15:15
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_WOFFSET                 0x0
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_MIPI_AUTO_CAL_DONE_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Start of Transmission Single Bit Error, set when CIL-B
+// detects a single bit error in one of the packets start
+// of transmission bytes. The packet will be sent to CSI-B
+// for processing.
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SHIFT                      _MK_SHIFT_CONST(16)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_RANGE                      16:16
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_SB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Start of Transmission Multi Bit Error, set when CIL-B
+// detects a multi bit start of transmission byte error in
+// one of the packets SOT bytes. The packet will be discarded.
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SHIFT                      _MK_SHIFT_CONST(17)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_RANGE                      17:17
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_WOFFSET                    0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SOT_MB_ERR_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Sync Escape Error, set when CIL-B detects that the wrong 
+// (non-multiple of 8) number of bits have been received for
+// an Escape Command, or Data Byte.
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SHIFT                    _MK_SHIFT_CONST(18)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_RANGE                    18:18
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SYNC_ESC_ERR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Escape Mode Entry Error, set when CIL-B detects an Escape
+// Mode Entry Error. The Escape mode command byte will not be
+// received.
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SHIFT                   _MK_SHIFT_CONST(19)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_RANGE                   19:19
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_WOFFSET                 0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_ENTRY_ERR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Control Error, set when CIL-B detects LP state 01 or 10
+// followed by a stop state (LP11) instead of transitioning
+// into the Escape mode or Turn Around mode (LP00)..
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SHIFT                        _MK_SHIFT_CONST(20)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_RANGE                        20:20
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_WOFFSET                      0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_CTRL_ERR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Escape Mode Command Received, set when CIL-B receives an
+// Escape Mode Command byte. The Command Byte can be read 
+// from bits 23-16 of ESCAPE_MODE_COMMAND.
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SHIFT                     _MK_SHIFT_CONST(21)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_RANGE                     21:21
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_WOFFSET                   0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_CMD_REC_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Escape Mode Data Received, set when CIL-B receives an
+// Escape Mode Data byte. The Data Byte can be read 
+// from bits 23-16 of ESCAPE_MODE_DATA. This status bit will
+// will also be cleared when CILB_ESC_CMD_REC is set.
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SHIFT                    _MK_SHIFT_CONST(22)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_RANGE                    22:22
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_WOFFSET                  0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_ESC_DATA_REC_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// CILB Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SHIFT                  _MK_SHIFT_CONST(23)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_RANGE                  23:23
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_1_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// CILB Spare Status bit.
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SHIFT                  _MK_SHIFT_CONST(24)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SHIFT)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_RANGE                  24:24
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_WOFFSET                        0x0
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_STATUS_0_CILB_SPARE_STATUS_2_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0  // CSI Pixel Parser Interrupt Mask
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0                   _MK_ADDR_CONST(0x220)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_SECURE                    0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_WORD_COUNT                        0x1
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_RESET_MASK                        _MK_MASK_CONST(0xcfffcfff)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_READ_MASK                         _MK_MASK_CONST(0xcfffcfff)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_WRITE_MASK                        _MK_MASK_CONST(0xcfffcfff)
+// Interrupt Mask for PPA_HDR_ERR_COR. Generate an interrupt when PPA_HDR_ERR_COR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_RANGE                    0:0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_HDR_ERR_COR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_HDR_ERR_COR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_ILL_WD_CNT. Generate an interrupt when PPA_ILL_WD_CNT
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SHIFT                     _MK_SHIFT_CONST(1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_RANGE                     1:1
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_ILL_WD_CNT
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_ILL_WD_CNT_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SL_PROCESSED. Generate an interrupt when PPA_SL_PROCESSED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_RANGE                   2:2
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SL_PROCESSED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PROCESSED_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SL_PKT_DROPPED. Generate an interrupt when PPA_SL_PKT_DROPPED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SHIFT                 _MK_SHIFT_CONST(3)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_RANGE                 3:3
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SL_PKT_DROPPED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SL_PKT_DROPPED_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_PL_CRC_ERR. Generate an interrupt when PPA_PL_CRC_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(4)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_RANGE                     4:4
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_PL_CRC_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_PL_CRC_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_FIFO_OVRF. Generate an interrupt when PPA_FIFO_OVRF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SHIFT                      _MK_SHIFT_CONST(5)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_RANGE                      5:5
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_FIFO_OVRF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_FIFO_OVRF_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_STMERR. Generate an interrupt when PPA_STMERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SHIFT                 _MK_SHIFT_CONST(6)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_RANGE                 6:6
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_STMERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_STMERR_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SHORT_FRAME. Generate an interrupt when PPA_SHORT_FRAME
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SHIFT                    _MK_SHIFT_CONST(7)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_RANGE                    7:7
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SHORT_FRAME
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SHORT_FRAME_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_EXTRA_SF. Generate an interrupt when PPA_EXTRA_SF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_RANGE                       8:8
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_EXTRA_SF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_EXTRA_SF_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_INTERFRAME_LINE. Generate an interrupt when PPA_INTERFRAME_LINE
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SHIFT                        _MK_SHIFT_CONST(9)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_RANGE                        9:9
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_DISABLED                     _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_INTERFRAME_LINE
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_INTERFRAME_LINE_INT_MASK_ENABLED                      _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SPARE_STATUS_1. Generate an interrupt when PPA_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(10)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_RANGE                 10:10
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPA_SPARE_STATUS_2. Generate an interrupt when PPA_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(11)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_RANGE                 11:11
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPA_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPA_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPA_UNC_HDR_ERR. Generate an interrupt when HPA_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(14)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_RANGE                    14:14
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPA_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPA_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPB_UNC_HDR_ERR. Generate an interrupt when HPB_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(15)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_RANGE                    15:15
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPB_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPB_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_HDR_ERR_COR. Generate an interrupt when PPB_HDR_ERR_COR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_RANGE                    16:16
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_HDR_ERR_COR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_HDR_ERR_COR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_ILL_WD_CNT. Generate an interrupt when PPB_ILL_WD_CNT
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SHIFT                     _MK_SHIFT_CONST(17)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_RANGE                     17:17
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_ILL_WD_CNT
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_ILL_WD_CNT_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SL_PROCESSED. Generate an interrupt when PPB_SL_PROCESSED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SHIFT                   _MK_SHIFT_CONST(18)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_RANGE                   18:18
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SL_PROCESSED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PROCESSED_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SL_PKT_DROPPED. Generate an interrupt when PPB_SL_PKT_DROPPED
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SHIFT                 _MK_SHIFT_CONST(19)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_RANGE                 19:19
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SL_PKT_DROPPED
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SL_PKT_DROPPED_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_PL_CRC_ERR. Generate an interrupt when PPB_PL_CRC_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(20)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_RANGE                     20:20
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_PL_CRC_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_PL_CRC_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_FIFO_OVRF. Generate an interrupt when PPB_FIFO_OVRF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SHIFT                      _MK_SHIFT_CONST(21)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_RANGE                      21:21
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_WOFFSET                    0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_DISABLED                   _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_FIFO_OVRF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_FIFO_OVRF_INT_MASK_ENABLED                    _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_STMERR. Generate an interrupt when PPB_STMERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SHIFT                 _MK_SHIFT_CONST(22)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_RANGE                 22:22
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_STMERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_STMERR_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SHORT_FRAME. Generate an interrupt when PPB_SHORT_FRAME
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SHIFT                    _MK_SHIFT_CONST(23)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_RANGE                    23:23
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SHORT_FRAME
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SHORT_FRAME_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_EXTRA_SF. Generate an interrupt when PPB_EXTRA_SF
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SHIFT                       _MK_SHIFT_CONST(24)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_RANGE                       24:24
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_EXTRA_SF
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_EXTRA_SF_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_INTERFRAME_LINE. Generate an interrupt when PPB_INTERFRAME_LINE
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SHIFT                        _MK_SHIFT_CONST(25)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_RANGE                        25:25
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_WOFFSET                      0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_DISABLED                     _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_INTERFRAME_LINE
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_INTERFRAME_LINE_INT_MASK_ENABLED                      _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SPARE_STATUS_1. Generate an interrupt when PPB_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(26)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_RANGE                 26:26
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for PPB_SPARE_STATUS_2. Generate an interrupt when PPB_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(27)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_RANGE                 27:27
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when PPB_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_PPB_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPV_UNC_HDR_ERR. Generate an interrupt when HPV_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(30)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_RANGE                    30:30
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPV_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPV_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for HPH_UNC_HDR_ERR. Generate an interrupt when HPH_UNC_HDR_ERR
+// is set.
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SHIFT                    _MK_SHIFT_CONST(31)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_RANGE                    31:31
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when HPH_UNC_HDR_ERR
+// is set.
+
+#define CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0_HPH_UNC_HDR_ERR_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+
+// Register CSI_CSI_CIL_INTERRUPT_MASK_0  // CSI Control and Interface Logic Interrupt Mask
+#define CSI_CSI_CIL_INTERRUPT_MASK_0                    _MK_ADDR_CONST(0x221)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_SECURE                     0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_WORD_COUNT                         0x1
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_RESET_MASK                         _MK_MASK_CONST(0x1ff81ff)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_READ_MASK                  _MK_MASK_CONST(0x1ff81ff)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_WRITE_MASK                         _MK_MASK_CONST(0x1ff81ff)
+// Interrupt Mask for CILA_SOT_SB_ERR. Generate an interrupt when CILA_SOT_SB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_RANGE                     0:0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SOT_SB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_SB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SOT_MB_ERR. Generate an interrupt when CILA_SOT_MB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_RANGE                     1:1
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SOT_MB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SOT_MB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SYNC_ESC_ERR. Generate an interrupt when CILA_SYNC_ESC_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_RANGE                   2:2
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SYNC_ESC_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SYNC_ESC_ERR_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_ESC_ENTRY_ERR. Generate an interrupt when CILA_ESC_ENTRY_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SHIFT                  _MK_SHIFT_CONST(3)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_RANGE                  3:3
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_WOFFSET                        0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_ESC_ENTRY_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_ENTRY_ERR_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_CTRL_ERR. Generate an interrupt when CILA_CTRL_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(4)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_RANGE                       4:4
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_CTRL_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_CTRL_ERR_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_ESC_CMD_REC. Generate an interrupt when CILA_ESC_CMD_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SHIFT                    _MK_SHIFT_CONST(5)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_RANGE                    5:5
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_ESC_CMD_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_CMD_REC_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_ESC_DATA_REC. Generate an interrupt when CILA_ESC_DATA_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_RANGE                   6:6
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_ESC_DATA_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_ESC_DATA_REC_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SPARE_STATUS_1. Generate an interrupt when CILA_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(7)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_RANGE                 7:7
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILA_SPARE_STATUS_2. Generate an interrupt when CILA_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(8)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_RANGE                 8:8
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILA_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILA_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for MIPI_AUTO_CAL_DONE. Generate an interrupt when MIPI_AUTO_CAL_DONE
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SHIFT                  _MK_SHIFT_CONST(15)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_RANGE                  15:15
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_WOFFSET                        0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)    // // Don't generate an interrupt when MIPI_AUTO_CAL_DONE
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_MIPI_AUTO_CAL_DONE_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SOT_SB_ERR. Generate an interrupt when CILB_SOT_SB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_RANGE                     16:16
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SOT_SB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_SB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SOT_MB_ERR. Generate an interrupt when CILB_SOT_MB_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SHIFT                     _MK_SHIFT_CONST(17)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_RANGE                     17:17
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_WOFFSET                   0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_DISABLED                  _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SOT_MB_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SOT_MB_ERR_INT_MASK_ENABLED                   _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SYNC_ESC_ERR. Generate an interrupt when CILB_SYNC_ESC_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SHIFT                   _MK_SHIFT_CONST(18)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_RANGE                   18:18
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SYNC_ESC_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SYNC_ESC_ERR_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_ESC_ENTRY_ERR. Generate an interrupt when CILB_ESC_ENTRY_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SHIFT                  _MK_SHIFT_CONST(19)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_RANGE                  19:19
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_WOFFSET                        0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_DISABLED                       _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_ESC_ENTRY_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_ENTRY_ERR_INT_MASK_ENABLED                        _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_CTRL_ERR. Generate an interrupt when CILB_CTRL_ERR
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SHIFT                       _MK_SHIFT_CONST(20)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_FIELD                       (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_RANGE                       20:20
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_WOFFSET                     0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_DISABLED                    _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_CTRL_ERR
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_CTRL_ERR_INT_MASK_ENABLED                     _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_ESC_CMD_REC. Generate an interrupt when CILB_ESC_CMD_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SHIFT                    _MK_SHIFT_CONST(21)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_RANGE                    21:21
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_WOFFSET                  0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_DISABLED                 _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_ESC_CMD_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_CMD_REC_INT_MASK_ENABLED                  _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_ESC_DATA_REC. Generate an interrupt when CILB_ESC_DATA_REC
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SHIFT                   _MK_SHIFT_CONST(22)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_RANGE                   22:22
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_WOFFSET                 0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_DISABLED                        _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_ESC_DATA_REC
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_ESC_DATA_REC_INT_MASK_ENABLED                 _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SPARE_STATUS_1. Generate an interrupt when CILB_SPARE_STATUS_1
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SHIFT                 _MK_SHIFT_CONST(23)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_RANGE                 23:23
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SPARE_STATUS_1
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_1_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+// Interrupt Mask for CILB_SPARE_STATUS_2. Generate an interrupt when CILB_SPARE_STATUS_2
+// is set.
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SHIFT)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_RANGE                 24:24
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_WOFFSET                       0x0
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_DISABLED                      _MK_ENUM_CONST(0)    // // Don't generate an interrupt when CILB_SPARE_STATUS_2
+// is set.
+
+#define CSI_CSI_CIL_INTERRUPT_MASK_0_CILB_SPARE_STATUS_2_INT_MASK_ENABLED                       _MK_ENUM_CONST(1)
+
+
+// Register CSI_CSI_READONLY_STATUS_0  // CSI Read Only Status, this register is used to return
+// CSI read only status.
+#define CSI_CSI_READONLY_STATUS_0                       _MK_ADDR_CONST(0x222)
+#define CSI_CSI_READONLY_STATUS_0_SECURE                        0x0
+#define CSI_CSI_READONLY_STATUS_0_WORD_COUNT                    0x1
+#define CSI_CSI_READONLY_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_READ_MASK                     _MK_MASK_CONST(0xff)
+#define CSI_CSI_READONLY_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// One only when Pixel Parser A is capturing frame data.
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_RANGE                  0:0
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_WOFFSET                        0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPA_ACTIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// One only when Pixel Parser B is capturing frame data.
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SHIFT                  _MK_SHIFT_CONST(1)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_RANGE                  1:1
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_WOFFSET                        0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_PPB_ACTIVE_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Reads back CSI's interrupt line. This is being used test
+// the CSI logic that generates interrupt.
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_RANGE                   2:2
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SHIFT                   _MK_SHIFT_CONST(3)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_RANGE                   3:3
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE3_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SHIFT                   _MK_SHIFT_CONST(4)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_RANGE                   4:4
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE4_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SHIFT                   _MK_SHIFT_CONST(5)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_RANGE                   5:5
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE5_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SHIFT                   _MK_SHIFT_CONST(6)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_RANGE                   6:6
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE6_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Spare Read Only status bit
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SHIFT                   _MK_SHIFT_CONST(7)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SHIFT)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_RANGE                   7:7
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_WOFFSET                 0x0
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CSI_READONLY_STATUS_0_CSI_RO_SPARE7_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_ESCAPE_MODE_COMMAND_0  // Escape Mode Command, this register is used to receive
+// escape mode command bytes from CIL-A and CIL-B.
+#define CSI_ESCAPE_MODE_COMMAND_0                       _MK_ADDR_CONST(0x223)
+#define CSI_ESCAPE_MODE_COMMAND_0_SECURE                        0x0
+#define CSI_ESCAPE_MODE_COMMAND_0_WORD_COUNT                    0x1
+#define CSI_ESCAPE_MODE_COMMAND_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_READ_MASK                     _MK_MASK_CONST(0xff00ff)
+#define CSI_ESCAPE_MODE_COMMAND_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// CIL-A Escape Mode Command Byte, this is the 8 bit entry
+// command that was received, by CIL-A, during the last 
+// escape Mode sequence. CIL-A monitors Byte Lane 0, only,
+// for escape mode sequences. This command byte can only 
+// be  assummed to be valid when CILA_ESC_CMD_REC status
+// bit is set.
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_FIELD                       (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_RANGE                       7:0
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_WOFFSET                     0x0
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILA_ESC_CMD_BYTE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// CIL-B Escape Mode Command Byte, this is the 8 bit entry
+// command that was received, by CIL-B, during the last 
+// escape Mode sequence. This command byte can only be 
+// assummed to be valid when CILB_ESC_CMD_REC status bit
+// is set.
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_FIELD                       (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_RANGE                       23:16
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_WOFFSET                     0x0
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_COMMAND_0_CILB_ESC_CMD_BYTE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CSI_ESCAPE_MODE_DATA_0  // Escape Mode Data, this register is used to receive
+// escape mode data bytes from CIL-A and CIL-B.
+#define CSI_ESCAPE_MODE_DATA_0                  _MK_ADDR_CONST(0x224)
+#define CSI_ESCAPE_MODE_DATA_0_SECURE                   0x0
+#define CSI_ESCAPE_MODE_DATA_0_WORD_COUNT                       0x1
+#define CSI_ESCAPE_MODE_DATA_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_RESET_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_READ_MASK                        _MK_MASK_CONST(0xff00ff)
+#define CSI_ESCAPE_MODE_DATA_0_WRITE_MASK                       _MK_MASK_CONST(0x0)
+// CIL-A Escape Mode Data Byte, when read this field returns
+// the last Escape Mode Data byte that was received by CIL-A.
+// Escape Mode Data bytes are the bytes that are received
+// in Escape Mode after receiving the Escape Mode Command.
+// These bytes can be used to implement MIPI's CSI Specs Low
+// Power Data Transmition. This field is only valid when 
+// the status bit, CILA_ESC_DATA_REC, is set, and will be
+// overwritten by the next Escape Mode data byte if not read
+// before the next byte come in.
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_FIELD                 (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_RANGE                 7:0
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_WOFFSET                       0x0
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILA_ESC_DATA_BYTE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// CIL-B Escape Mode Data Byte, when read this field returns
+// the last Escape Mode Data byte that was received by CIL-B.
+// Escape Mode Data bytes are the bytes that are received
+// in Escape Mode after receiving the Escape Mode Command.
+// These bytes can be used to implement MIPI's CSI Specs Low
+// Power Data Transmition. This field is only valid when 
+// the status bit, CILB_ESC_DATA_REC, is set, and will be
+// overwritten by the next Escape Mode data byte if not read
+// before the next byte come in.
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_FIELD                 (_MK_MASK_CONST(0xff) << CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SHIFT)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_RANGE                 23:16
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_WOFFSET                       0x0
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_ESCAPE_MODE_DATA_0_CILB_ESC_DATA_BYTE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILA_PAD_CONFIG0_0  // CIL-A Pad Configuration 0
+#define CSI_CILA_PAD_CONFIG0_0                  _MK_ADDR_CONST(0x225)
+#define CSI_CILA_PAD_CONFIG0_0_SECURE                   0x0
+#define CSI_CILA_PAD_CONFIG0_0_WORD_COUNT                       0x1
+#define CSI_CILA_PAD_CONFIG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_RESET_MASK                       _MK_MASK_CONST(0x77f1777f)
+#define CSI_CILA_PAD_CONFIG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_READ_MASK                        _MK_MASK_CONST(0x77f1777f)
+#define CSI_CILA_PAD_CONFIG0_0_WRITE_MASK                       _MK_MASK_CONST(0x77f1777f)
+// Power down for each data bit, including drivers,
+// receivers and contention detectors
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_FIELD                      (_MK_MASK_CONST(0x3) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_RANGE                      1:0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_WOFFSET                    0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Power down for clock bit, including drivers, 
+// receivers and contention detectors
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SHIFT                  _MK_SHIFT_CONST(2)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_RANGE                  2:2
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_WOFFSET                        0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PDIO_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// HS driver preemphasis enable,1= preemphasis enabled
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SHIFT                 _MK_SHIFT_CONST(3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_RANGE                 3:3
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_PREEMP_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clock bit input delay trimmer, each tap delays 20ps
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SHIFT                  _MK_SHIFT_CONST(4)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_FIELD                  (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_RANGE                  6:4
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_WOFFSET                        0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJCLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// bit 0 input delay trimmer, each tap delays 20ps
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_FIELD                    (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_RANGE                    10:8
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_WOFFSET                  0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// bit 1 input delay trimmer, each tap delays 20ps
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SHIFT                    _MK_SHIFT_CONST(12)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_FIELD                    (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_RANGE                    14:12
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_WOFFSET                  0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_INADJ1_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Increase bandwidth of differential receiver
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_RANGE                 16:16
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_BANDWD_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Driver pull up impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SHIFT                   _MK_SHIFT_CONST(20)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_RANGE                   21:20
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_WOFFSET                 0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPUPADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Driver pull down impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SHIFT                   _MK_SHIFT_CONST(22)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_RANGE                   23:22
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_WOFFSET                 0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_LPDNADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pull up slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_RANGE                 26:24
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWUPADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Pull down slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SHIFT                 _MK_SHIFT_CONST(28)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SHIFT)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_RANGE                 30:28
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_WOFFSET                       0x0
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG0_0_PAD_CILA_SLEWDNADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILA_PAD_CONFIG1_0  // CIL-A Pad Configuration 4
+#define CSI_CILA_PAD_CONFIG1_0                  _MK_ADDR_CONST(0x226)
+#define CSI_CILA_PAD_CONFIG1_0_SECURE                   0x0
+#define CSI_CILA_PAD_CONFIG1_0_WORD_COUNT                       0x1
+#define CSI_CILA_PAD_CONFIG1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_CILA_PAD_CONFIG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CSI_CILA_PAD_CONFIG1_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Spare bits for CILA Config
+// PAD_CILA_SPARE[15] is being used to disable 
+// the CSI-A RTL code that blocks fifo pushs 
+// that are past the end of the line packet.
+// 0: disabled, 1: push blocking enabled
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_FIELD                     (_MK_MASK_CONST(0xffff) << CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SHIFT)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RANGE                     15:0
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_WOFFSET                   0x0
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Spare Read only bits for CILA Config
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_FIELD                  (_MK_MASK_CONST(0xffff) << CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SHIFT)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_RANGE                  31:16
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_WOFFSET                        0x0
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_PAD_CONFIG1_0_PAD_CILA_SPARE_RO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILB_PAD_CONFIG0_0  // CIL-B Pad Configuration 0
+#define CSI_CILB_PAD_CONFIG0_0                  _MK_ADDR_CONST(0x227)
+#define CSI_CILB_PAD_CONFIG0_0_SECURE                   0x0
+#define CSI_CILB_PAD_CONFIG0_0_WORD_COUNT                       0x1
+#define CSI_CILB_PAD_CONFIG0_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_RESET_MASK                       _MK_MASK_CONST(0x77f1077d)
+#define CSI_CILB_PAD_CONFIG0_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_READ_MASK                        _MK_MASK_CONST(0x77f1077d)
+#define CSI_CILB_PAD_CONFIG0_0_WRITE_MASK                       _MK_MASK_CONST(0x77f1077d)
+// Power down for each data bit, including drivers,
+// receivers and contention detectors
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_RANGE                      0:0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_WOFFSET                    0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Power down for clock bit, including drivers, 
+// receivers and contention detectors
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SHIFT                  _MK_SHIFT_CONST(2)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_RANGE                  2:2
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_WOFFSET                        0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PDIO_CLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// HS driver preemphasis enable,1= preemphasis enabled
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SHIFT                 _MK_SHIFT_CONST(3)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_RANGE                 3:3
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_PREEMP_EN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clock bit input delay trimmer, each tap delays 20ps
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SHIFT                  _MK_SHIFT_CONST(4)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_FIELD                  (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_RANGE                  6:4
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_WOFFSET                        0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_DEFAULT_MASK                   _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJCLK_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// bit 0 input delay trimmer, each tap delays 20ps
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_FIELD                    (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_RANGE                    10:8
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_WOFFSET                  0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_DEFAULT_MASK                     _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_INADJ0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+
+// Increase bandwidth of differential receiver
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_RANGE                 16:16
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_DEFAULT_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_BANDWD_IN_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Driver pull up impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SHIFT                   _MK_SHIFT_CONST(20)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_RANGE                   21:20
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_WOFFSET                 0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPUPADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Driver pull down impedance control
+// 00 -> 130ohm, default
+// 01 -> 110ohm
+// 10 -> 130ohm, same as 00
+// 11 -> 150ohm
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SHIFT                   _MK_SHIFT_CONST(22)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_FIELD                   (_MK_MASK_CONST(0x3) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_RANGE                   23:22
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_WOFFSET                 0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_DEFAULT_MASK                    _MK_MASK_CONST(0x3)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_LPDNADJ_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Pull up slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_RANGE                 26:24
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWUPADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Pull down slew rate adjust, default 000
+// From 000 -> 011, slew rate increases
+// 100 is the same as 000
+// From 100->111, skew rate decreases.
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SHIFT                 _MK_SHIFT_CONST(28)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_FIELD                 (_MK_MASK_CONST(0x7) << CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SHIFT)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_RANGE                 30:28
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_WOFFSET                       0x0
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_DEFAULT_MASK                  _MK_MASK_CONST(0x7)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG0_0_PAD_CILB_SLEWDNADJ_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILB_PAD_CONFIG1_0  // CIL-B Pad Configuration 4
+#define CSI_CILB_PAD_CONFIG1_0                  _MK_ADDR_CONST(0x228)
+#define CSI_CILB_PAD_CONFIG1_0_SECURE                   0x0
+#define CSI_CILB_PAD_CONFIG1_0_WORD_COUNT                       0x1
+#define CSI_CILB_PAD_CONFIG1_0_RESET_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_RESET_MASK                       _MK_MASK_CONST(0xffff)
+#define CSI_CILB_PAD_CONFIG1_0_SW_DEFAULT_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_READ_MASK                        _MK_MASK_CONST(0xffffffff)
+#define CSI_CILB_PAD_CONFIG1_0_WRITE_MASK                       _MK_MASK_CONST(0xffff)
+// Spare bits for CILB Config
+// PAD_CILB_SPARE[15] is being used to disable 
+// the CSI-B RTL code that blocks fifo pushs 
+// that are past the end of the line packet.
+// 0: disabled, 1: push blocking enabled
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_FIELD                     (_MK_MASK_CONST(0xffff) << CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SHIFT)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RANGE                     15:0
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_WOFFSET                   0x0
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_DEFAULT_MASK                      _MK_MASK_CONST(0xffff)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Spare Read only bits for CILB Config
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_FIELD                  (_MK_MASK_CONST(0xffff) << CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SHIFT)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_RANGE                  31:16
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_WOFFSET                        0x0
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_PAD_CONFIG1_0_PAD_CILB_SPARE_RO_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CIL_PAD_CONFIG0_0  // CIL Pad Configuration 0
+#define CSI_CIL_PAD_CONFIG0_0                   _MK_ADDR_CONST(0x229)
+#define CSI_CIL_PAD_CONFIG0_0_SECURE                    0x0
+#define CSI_CIL_PAD_CONFIG0_0_WORD_COUNT                        0x1
+#define CSI_CIL_PAD_CONFIG0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_RESET_MASK                        _MK_MASK_CONST(0xff73)
+#define CSI_CIL_PAD_CONFIG0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_READ_MASK                         _MK_MASK_CONST(0xff73)
+#define CSI_CIL_PAD_CONFIG0_0_WRITE_MASK                        _MK_MASK_CONST(0xff73)
+// Bypass bang gap voltage reference
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_RANGE                     0:0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_WOFFSET                   0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VBYPASS_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// Power down voltage regulator, 1=power down
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SHIFT                      _MK_SHIFT_CONST(1)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_RANGE                      1:1
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_WOFFSET                    0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_PDVREG_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// VAUXP level adjustment
+// 00 -> no adjustment, default
+// 01 -> 105% 
+// 10 -> 110% 
+// 11 -> 115%
+// 100 -> no adjustment
+// 101 -> 95%
+// 110 -> 90%
+// 111 -> 85%
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_FIELD                        (_MK_MASK_CONST(0x7) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_RANGE                        6:4
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_WOFFSET                      0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_DEFAULT_MASK                 _MK_MASK_CONST(0x7)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_VADJ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Spare bit for CIL BIAS Config
+// PAD_CIL_SPARE[7] is used is being used to flush VI's
+// Y-FIFO when it is being use as a stream source for 
+// one of the Pixel Parsers. Setting PAD_CIL_SPARE[7]
+// to 1 will hold vi2csi_host_stall low. Which will
+// force VI's Y-FIFO to be purged. PAD_CIL_SPARE[7]
+// must be low for the pixel parser to receive source
+// data from VI's Y-FIFO. 
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_FIELD                       (_MK_MASK_CONST(0xff) << CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SHIFT)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_RANGE                       15:8
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_WOFFSET                     0x0
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_DEFAULT_MASK                        _MK_MASK_CONST(0xff)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CIL_PAD_CONFIG0_0_PAD_CIL_SPARE_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILA_MIPI_CAL_CONFIG_0  // Calibration settings for CIL-A mipi pads
+#define CSI_CILA_MIPI_CAL_CONFIG_0                      _MK_ADDR_CONST(0x22a)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_SECURE                       0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_WORD_COUNT                   0x1
+#define CSI_CILA_MIPI_CAL_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x2a200000)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0xff3f1f1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0xff3f1f1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x7f3f1f1f)
+// 2's complement offset for TERMADJ going to channel A
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_RANGE                       4:0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_WOFFSET                     0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPUADJ going to channel A
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_RANGE                       12:8
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_WOFFSET                     0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPDADJ going to channel A
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_RANGE                       20:16
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_WOFFSET                     0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSA_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Select the CSIA PADS for auto calibration.
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_SELA_SHIFT                  _MK_SHIFT_CONST(21)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_SELA_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_SELA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_SELA_RANGE                  21:21
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_SELA_WOFFSET                        0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_SELA_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_SELA_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_SELA_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_SELA_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Auto Cal calibration step prescale:
+// Set to 00 when calibration step should be 0.1 us
+// Set to 01 when calibration step should be 0.5 us
+// Set to 10 when calibration step should be 1.0 us
+// Set to 11 when calibration step should be 1.5 us
+// this will keep the mipi bias cal step between 0.1-1.5 usec
+// Default set for 1.0 us calibraiton step.
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SHIFT                      _MK_SHIFT_CONST(24)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_FIELD                      (_MK_MASK_CONST(0x3) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_RANGE                      25:24
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_WOFFSET                    0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_DEFAULT                    _MK_MASK_CONST(0x2)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_DEFAULT_MASK                       _MK_MASK_CONST(0x3)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_PRESCALE_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// The DRIVRY & TERMRY signals coming from MIPI Pads are
+// utilized by Calibration state machine for PAD Calibration.
+// The drivry/termry comes from a noisy analog source 
+// and it could have some glitches.
+// The filter in calibsm is sensitive to these noises.
+// If the calibration done status does not show up, we
+// can change the sensitivity of the filter through these bits.
+// Ideally this has to be programmed in a range from 10 to 15.
+// For the case when MIPI_CAL_PRESCALE = 2'b00, this needs to be
+// programmed between 2 to 5.
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SHIFT                     _MK_SHIFT_CONST(26)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_FIELD                     (_MK_MASK_CONST(0xf) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_RANGE                     29:26
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_WOFFSET                   0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_DEFAULT                   _MK_MASK_CONST(0xa)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_DEFAULT_MASK                      _MK_MASK_CONST(0xf)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_NOISE_FLT_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+
+// When 0 (normal operation), use the above registers
+// as an offset to the Calibration State machine setting
+// for channel A TERMADJ/HSPUADJ/HSPDADJ values to the 
+// Mipi Pads. When 1, use the register values above as
+// the actual value going to channel A TERMADJ/HSPUADJ/HSPDADJ
+// on the Mipi Pads.
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SHIFT                      _MK_SHIFT_CONST(30)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_RANGE                      30:30
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_WOFFSET                    0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEA_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Writting a one to this bit starts the Calibration State
+// machine.  This bit must be set even if both overrides
+// set in order to latch in the over ride value
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SHIFT                      _MK_SHIFT_CONST(31)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SHIFT)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_RANGE                      31:31
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_WOFFSET                    0x0
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILA_MIPI_CAL_CONFIG_0_MIPI_CAL_STARTCAL_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CILB_MIPI_CAL_CONFIG_0  // Calibration settings for CIL-B mipi pads
+#define CSI_CILB_MIPI_CAL_CONFIG_0                      _MK_ADDR_CONST(0x22b)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_SECURE                       0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_WORD_COUNT                   0x1
+#define CSI_CILB_MIPI_CAL_CONFIG_0_RESET_VAL                    _MK_MASK_CONST(0x200000)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_RESET_MASK                   _MK_MASK_CONST(0x403f1f1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_SW_DEFAULT_VAL                       _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_READ_MASK                    _MK_MASK_CONST(0x403f1f1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_WRITE_MASK                   _MK_MASK_CONST(0x403f1f1f)
+// 2's complement offset for TERMADJ going to channel B
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_RANGE                       4:0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_WOFFSET                     0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPUADJ going to channel B
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SHIFT                       _MK_SHIFT_CONST(8)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_RANGE                       12:8
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_WOFFSET                     0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPDADJ going to channel B
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SHIFT                       _MK_SHIFT_CONST(16)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_FIELD                       (_MK_MASK_CONST(0x1f) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_RANGE                       20:16
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_WOFFSET                     0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_DEFAULT_MASK                        _MK_MASK_CONST(0x1f)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSB_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Select the CSIB PADS for auto calibration.
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_SELB_SHIFT                  _MK_SHIFT_CONST(21)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_SELB_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_SELB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_SELB_RANGE                  21:21
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_SELB_WOFFSET                        0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_SELB_DEFAULT                        _MK_MASK_CONST(0x1)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_SELB_DEFAULT_MASK                   _MK_MASK_CONST(0x1)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_SELB_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_SELB_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// When 0 (normal operation), use the above registers
+// as an offset to the Calibration State machine setting
+// for channel B TERMADJ/HSPUADJ/HSPDADJ values to the 
+// Mipi Pads. When 1, use the register values above as
+// the actual value going to channel B TERMADJ/HSPUADJ/HSPDADJ
+// on the Mipi Pads.
+// Writting a one to Bit 31 of CILA_MIPI_CAL_CONFIG 
+// (MIPI_CAL_STARTCAL) starts the Calibration State
+// machine.
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SHIFT                      _MK_SHIFT_CONST(30)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_FIELD                      (_MK_MASK_CONST(0x1) << CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SHIFT)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_RANGE                      30:30
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_WOFFSET                    0x0
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CILB_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDEB_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CSI_CIL_MIPI_CAL_STATUS_0  // CIL MIPI Calibrate Status
+#define CSI_CIL_MIPI_CAL_STATUS_0                       _MK_ADDR_CONST(0x22c)
+#define CSI_CIL_MIPI_CAL_STATUS_0_SECURE                        0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_WORD_COUNT                    0x1
+#define CSI_CIL_MIPI_CAL_STATUS_0_RESET_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_RESET_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_READ_MASK                     _MK_MASK_CONST(0x38000ff1)
+#define CSI_CIL_MIPI_CAL_STATUS_0_WRITE_MASK                    _MK_MASK_CONST(0x0)
+// One when auto calibrate is active.
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SHIFT                 _MK_SHIFT_CONST(0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_RANGE                 0:0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_WOFFSET                       0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_ACTIVE_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Termination code generated by MIPI auto Calibrate.
+// Valid only after auto calibrate sequence has 
+// completed (MIPI_CAL_ACTIVE == 0).
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_FIELD                        (_MK_MASK_CONST(0xf) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_RANGE                        7:4
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_WOFFSET                      0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_TERMADJ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Driver code generated by MIPI auto Calibrate.
+// Valid only after auto calibrate sequence has 
+// completed (MIPI_CAL_ACTIVE == 0).
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_FIELD                        (_MK_MASK_CONST(0xf) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_RANGE                        11:8
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_WOFFSET                      0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_CAL_DRIVADJ_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// MIPI Auto Calibrate done for CSI,
+// set when the auto calibrate 
+// sequence for CSI pad bricks is done.
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIA_SHIFT                 _MK_SHIFT_CONST(27)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIA_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIA_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIA_RANGE                 27:27
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIA_WOFFSET                       0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIA_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIA_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIA_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIA_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// MIPI Auto Calibrate done for CSI,
+// set when the auto calibrate 
+// sequence for CSI pad bricks is done.
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIB_SHIFT                 _MK_SHIFT_CONST(28)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIB_FIELD                 (_MK_MASK_CONST(0x1) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIB_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIB_RANGE                 28:28
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIB_WOFFSET                       0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIB_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIB_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIB_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_CSIB_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// MIPI Auto Calibrate done for DSI,
+// set when the auto calibrate 
+// sequence for DSI pad bricks is done.
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_DSI_SHIFT                  _MK_SHIFT_CONST(29)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_DSI_FIELD                  (_MK_MASK_CONST(0x1) << CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_DSI_SHIFT)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_DSI_RANGE                  29:29
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_DSI_WOFFSET                        0x0
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_DSI_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_DSI_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_DSI_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_CIL_MIPI_CAL_STATUS_0_MIPI_AUTO_CAL_DONE_DSI_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+// Second-level clock enable override register
+//
+// This can override the 2nd level clock enables in case of malfunction.
+// Only exposed to software when needed.
+//
+
+// Register CSI_CLKEN_OVERRIDE_0  
+#define CSI_CLKEN_OVERRIDE_0                    _MK_ADDR_CONST(0x22d)
+#define CSI_CLKEN_OVERRIDE_0_SECURE                     0x0
+#define CSI_CLKEN_OVERRIDE_0_WORD_COUNT                         0x1
+#define CSI_CLKEN_OVERRIDE_0_RESET_VAL                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_RESET_MASK                         _MK_MASK_CONST(0x3fff)
+#define CSI_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                     _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_READ_MASK                  _MK_MASK_CONST(0x3fff)
+#define CSI_CLKEN_OVERRIDE_0_WRITE_MASK                         _MK_MASK_CONST(0x3fff)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_FIELD                        (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_RANGE                        0:0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_WOFFSET                      0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_DEFAULT_MASK                 _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_INIT_ENUM                    CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_CLK_GATED                    _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CLKEN_OVR_CLK_ALWAYS_ON                        _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_RANGE                    1:1
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_DBG_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SHIFT                     _MK_SHIFT_CONST(2)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_RANGE                     2:2
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_WOFFSET                   0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_INIT_ENUM                 CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_CLK_GATED                 _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FV_CLKEN_OVR_CLK_ALWAYS_ON                     _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SHIFT                     _MK_SHIFT_CONST(3)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_RANGE                     3:3
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_WOFFSET                   0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_INIT_ENUM                 CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_CLK_GATED                 _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FA_CLKEN_OVR_CLK_ALWAYS_ON                     _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SHIFT                     _MK_SHIFT_CONST(4)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_FIELD                     (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_RANGE                     4:4
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_WOFFSET                   0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_DEFAULT_MASK                      _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SW_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_INIT_ENUM                 CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_CLK_GATED                 _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_FB_CLKEN_OVR_CLK_ALWAYS_ON                     _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(5)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_RANGE                    5:5
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPV_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(6)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_RANGE                    6:6
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPA_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(7)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_RANGE                    7:7
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPB_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_RANGE                    8:8
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_HPH_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(9)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_RANGE                    9:9
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPA_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(10)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_RANGE                    10:10
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_PPB_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SHIFT                   _MK_SHIFT_CONST(11)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_RANGE                   11:11
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_WOFFSET                 0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_INIT_ENUM                       CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_CLK_GATED                       _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILA_CLKEN_OVR_CLK_ALWAYS_ON                   _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SHIFT                   _MK_SHIFT_CONST(12)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_FIELD                   (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_RANGE                   12:12
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_WOFFSET                 0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_INIT_ENUM                       CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_CLK_GATED                       _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CILB_CLKEN_OVR_CLK_ALWAYS_ON                   _MK_ENUM_CONST(1)
+
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SHIFT                    _MK_SHIFT_CONST(13)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_FIELD                    (_MK_MASK_CONST(0x1) << CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SHIFT)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_RANGE                    13:13
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_WOFFSET                  0x0
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_DEFAULT_MASK                     _MK_MASK_CONST(0x1)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SW_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_SW_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_CLK_GATED                        _MK_ENUM_CONST(0)
+#define CSI_CLKEN_OVERRIDE_0_CSI_CIL_CLKEN_OVR_CLK_ALWAYS_ON                    _MK_ENUM_CONST(1)
+
+
+// Register CSI_DEBUG_CONTROL_0  // Debug Control
+#define CSI_DEBUG_CONTROL_0                     _MK_ADDR_CONST(0x22e)
+#define CSI_DEBUG_CONTROL_0_SECURE                      0x0
+#define CSI_DEBUG_CONTROL_0_WORD_COUNT                  0x1
+#define CSI_DEBUG_CONTROL_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_RESET_MASK                  _MK_MASK_CONST(0x1)
+#define CSI_DEBUG_CONTROL_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_READ_MASK                   _MK_MASK_CONST(0xffffff7d)
+#define CSI_DEBUG_CONTROL_0_WRITE_MASK                  _MK_MASK_CONST(0x7f7f7f01)
+// Debug Enable Second level CSI Debug clock is enabled. Debug counters
+// 2, 1 & 0 are powered up.
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DEBUG_EN_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_RANGE                      0:0
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_DEFAULT_MASK                       _MK_MASK_CONST(0x1)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_DISABLED                   _MK_ENUM_CONST(0)    // // Debug counters 2, 1 & 0 are powered down. Second level
+// CSI Debug clock is disabled.
+
+#define CSI_DEBUG_CONTROL_0_DEBUG_EN_ENABLED                    _MK_ENUM_CONST(1)
+
+// When CSI-A is operating in a "Header Not Sent mode",
+// writting a 1 to this bit indicates start frame (SF)
+// or end frame (EF) control code. After the pixel parser 
+// is enabled, writing a 1 to this bit will start frame 
+// capture and send start frame (SF) control code. Writing
+// a 1 to this bit again will stop frame capture and send
+// end frame (EF) control code. "Header Not Sent mode" can 
+// be used as a debug mode to capture what the sensor
+// is sending without interpeting the packets. Writing a
+// 1 to this bit continually will generate SF and EF control
+// codes. Note that a wait for MISC_CSI_PPA_FRAME_END syncpt
+// is needed between an EF trigger for the current frame and 
+// an SF trigger for the next frame.
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SHIFT                   _MK_SHIFT_CONST(2)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_FIELD                   (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_RANGE                   2:2
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_WOFFSET                 0x0
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIA_DBG_SF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// When CSI-B is operating in a "Header Not Sent mode",
+// writting a 1 to this bit indicates start frame (SF)
+// or end frame (EF) control code. After the pixel parser 
+// is enabled, writing a 1 to this bit will start frame 
+// capture and send start frame (SF) control code. Writing
+// a 1 to this bit again will stop frame capture and send
+// end frame (EF) control code. "Header Not Sent mode" can 
+// be used as a debug mode to capture what the sensor
+// is sending without interpeting the packets. Writing a
+// 1 to this bit continually will generate SF and EF control
+// codes. Note that a wait for MISC_CSI_PPB_FRAME_END syncpt
+// is needed between an EF trigger for the current frame and 
+// an SF trigger for the next frame.
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SHIFT                   _MK_SHIFT_CONST(3)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_FIELD                   (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_RANGE                   3:3
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_WOFFSET                 0x0
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CSIB_DBG_SF_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// Clear Debug Counter 0, write a one to this bit to clear
+// debug counter 0 and dbg_cnt_rolled_0.
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SHIFT                 _MK_SHIFT_CONST(4)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_FIELD                 (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_RANGE                 4:4
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clear Debug Counter 1, write a one to this bit to clear
+// debug counter 1 and dbg_cnt_rolled_1.
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SHIFT                 _MK_SHIFT_CONST(5)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_FIELD                 (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_RANGE                 5:5
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Clear Debug Counter 2, write a one to this bit to clear
+// debug counter 2 and dbg_cnt_rolled_2.
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SHIFT                 _MK_SHIFT_CONST(6)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_FIELD                 (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SHIFT)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_RANGE                 6:6
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_CLR_DBG_CNT_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Debug Count Select 0, this field selects what will be 
+// counted by debug counter 0.
+// Encodings 00 to 31 selects the set signal for one of 
+// the CSI_PIXEL_PARSER_STATUS register bits. In this case
+// the select encoding of this field is the same as the
+// bit position, in CSI_PIXEL_PARSER_STATUS, of the status
+// bit who's set signal will be used to increment DBG_CNT_0.
+// Encodings 32 to 63 selects the set signal for one of 
+// the CSI_CIL_STATUS status bits. The least significant 
+// 5 bits of this select field give the bit position, in
+// CSI_CIL_STATUS, of the status bit whos set signal pluses
+// will be counted by dbg_cnt_0. Selections for encodings 64
+// to 127 are given below: 
+// 64 - PPA Line packets processed
+// 65 - PPA short packets processed
+// 66 - Total packets processed by PPA
+// 67 - PPA Frame Starts Outputted
+// 68 - PPA Frame Ends Outputted
+// 69 - Reserved encoding
+// 70 - PPB Line packets processed
+// 71 - PPB short packets processed
+// 72 - Total packets processed by PPB
+// 73 - PPB Frame Starts Outputted
+// 74 - PPB Frame Ends Outputted
+// 75 - Reserved encoding
+// 76 - HPA Headers Parsed
+// 77 - HPA Headers Parsed with no ECC Errors
+// 78 - HPB Headers Parsed
+// 79 - HPB Headers Parsed with no ECC Errors
+// 80 - HPV Headers Parsed
+// 81 - HPV Headers Parsed with no ECC Errors
+// 82 - HPH Headers Parsed
+// 83 - HPH Headers Parsed with no ECC Errors
+// 84 - 32 bit words read from vi2csi_host_data
+// 85 to 127 - Reserved encodings
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SHIFT                 _MK_SHIFT_CONST(8)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_FIELD                 (_MK_MASK_CONST(0x7f) << CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_RANGE                 14:8
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Set when dbg_cnt_0 is incremented past max count, cleared
+// when clr_dbg_cnt_0 is written with a value of 1.
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SHIFT                      _MK_SHIFT_CONST(15)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_RANGE                      15:15
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_0_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Debug Count Select 1, this field selects what will be 
+// counted by debug counter 1.
+// Encodings 00 to 31 selects the set signal for one of 
+// the CSI_PIXEL_PARSER_STATUS register bits. In this case
+// the select encoding of this field is the same as the
+// bit position, in CSI_PIXEL_PARSER_STATUS, of the status
+// bit who's set signal will be used to increment DBG_CNT_0.
+// Encodings 32 to 63 selects the set signal for one of 
+// the CSI_CIL_STATUS status bits. The least significant 
+// 5 bits of this select field give the bit position, in
+// CSI_CIL_STATUS, of the status bit whos set signal pluses
+// will be counted by dbg_cnt_0. Selections for encodings 64
+// to 127 are given below: 
+// 64 - PPA Line packets processed
+// 65 - PPA short packets processed
+// 66 - Total packets processed by PPA
+// 67 - PPA Frame Starts Outputted
+// 68 - PPA Frame Ends Outputted
+// 69 - Reserved encoding
+// 70 - PPB Line packets processed
+// 71 - PPB short packets processed
+// 72 - Total packets processed by PPB
+// 73 - PPB Frame Starts Outputted
+// 74 - PPB Frame Ends Outputted
+// 75 - Reserved encoding
+// 76 - HPA Headers Parsed
+// 77 - HPA Headers Parsed with no ECC Errors
+// 78 - HPB Headers Parsed
+// 79 - HPB Headers Parsed with no ECC Errors
+// 80 - HPV Headers Parsed
+// 81 - HPV Headers Parsed with no ECC Errors
+// 82 - HPH Headers Parsed
+// 83 - HPH Headers Parsed with no ECC Errors
+// 84 - 32 bit words read from vi2csi_host_data
+// 85 to 127 - Reserved encodings
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SHIFT                 _MK_SHIFT_CONST(16)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_FIELD                 (_MK_MASK_CONST(0x7f) << CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_RANGE                 22:16
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_1_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Set when dbg_cnt_1 is incremented past max count, cleared
+// when clr_dbg_cnt_1 is written with a value of 1.
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SHIFT                      _MK_SHIFT_CONST(23)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_RANGE                      23:23
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_1_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+// Debug Count Select 2, this field selects what will be 
+// counted by debug counter 2.
+// Encodings 00 to 31 selects the set signal for one of 
+// the CSI_PIXEL_PARSER_STATUS register bits. In this case
+// the select encoding of this field is the same as the
+// bit position, in CSI_PIXEL_PARSER_STATUS, of the status
+// bit who's set signal will be used to increment DBG_CNT_0.
+// Encodings 32 to 63 selects the set signal for one of 
+// the CSI_CIL_STATUS status bits. The least significant 
+// 5 bits of this select field give the bit position, in
+// CSI_CIL_STATUS, of the status bit whos set signal pluses
+// will be counted by dbg_cnt_0. Selections for encodings 64
+// to 127 are given below: 
+// 64 - PPA Line packets processed
+// 65 - PPA short packets processed
+// 66 - Total packets processed by PPA
+// 67 - PPA Frame Starts Outputted
+// 68 - PPA Frame Ends Outputted
+// 69 - Reserved encoding
+// 70 - PPB Line packets processed
+// 71 - PPB short packets processed
+// 72 - Total packets processed by PPB
+// 73 - PPB Frame Starts Outputted
+// 74 - PPB Frame Ends Outputted
+// 75 - Reserved encoding
+// 76 - HPA Headers Parsed
+// 77 - HPA Headers Parsed with no ECC Errors
+// 78 - HPB Headers Parsed
+// 79 - HPB Headers Parsed with no ECC Errors
+// 80 - HPV Headers Parsed
+// 81 - HPV Headers Parsed with no ECC Errors
+// 82 - HPH Headers Parsed
+// 83 - HPH Headers Parsed with no ECC Errors
+// 84 - 32 bit words read from vi2csi_host_data
+// 85 to 127 - Reserved encodings
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SHIFT                 _MK_SHIFT_CONST(24)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_FIELD                 (_MK_MASK_CONST(0x7f) << CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_RANGE                 30:24
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_WOFFSET                       0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_DEFAULT                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_DEFAULT_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SW_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_SEL_2_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+
+// Set when dbg_cnt_2 is incremented past max count, cleared
+// when clr_dbg_cnt_2 is written with a value of 1.
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SHIFT                      _MK_SHIFT_CONST(31)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_FIELD                      (_MK_MASK_CONST(0x1) << CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SHIFT)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_RANGE                      31:31
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_WOFFSET                    0x0
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_DEFAULT                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SW_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_CONTROL_0_DBG_CNT_ROLLED_2_SW_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DEBUG_COUNTER_0_0  // Debug Counter 0, this register can be used to count 
+// error conditions or packets processed.
+#define CSI_DEBUG_COUNTER_0_0                   _MK_ADDR_CONST(0x22f)
+#define CSI_DEBUG_COUNTER_0_0_SECURE                    0x0
+#define CSI_DEBUG_COUNTER_0_0_WORD_COUNT                        0x1
+#define CSI_DEBUG_COUNTER_0_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define CSI_DEBUG_COUNTER_0_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// When read returns the value of debug counter 0.
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SHIFT)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_RANGE                   31:0
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_WOFFSET                 0x0
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_0_0_DBG_CNT_0_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DEBUG_COUNTER_1_0  // Debug Counter 1, this register can be used to count 
+// error conditions or packets processed.
+#define CSI_DEBUG_COUNTER_1_0                   _MK_ADDR_CONST(0x230)
+#define CSI_DEBUG_COUNTER_1_0_SECURE                    0x0
+#define CSI_DEBUG_COUNTER_1_0_WORD_COUNT                        0x1
+#define CSI_DEBUG_COUNTER_1_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define CSI_DEBUG_COUNTER_1_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// When read returns the value of debug counter 1.
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SHIFT)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_RANGE                   31:0
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_WOFFSET                 0x0
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_1_0_DBG_CNT_1_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DEBUG_COUNTER_2_0  // Debug Counter 2, this register can be used to count 
+// error conditions or packets processed.
+#define CSI_DEBUG_COUNTER_2_0                   _MK_ADDR_CONST(0x231)
+#define CSI_DEBUG_COUNTER_2_0_SECURE                    0x0
+#define CSI_DEBUG_COUNTER_2_0_WORD_COUNT                        0x1
+#define CSI_DEBUG_COUNTER_2_0_RESET_VAL                         _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_RESET_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_SW_DEFAULT_VAL                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_SW_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_READ_MASK                         _MK_MASK_CONST(0xffffffff)
+#define CSI_DEBUG_COUNTER_2_0_WRITE_MASK                        _MK_MASK_CONST(0x0)
+// When read returns the value of debug counter 2.
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SHIFT                   _MK_SHIFT_CONST(0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_FIELD                   (_MK_MASK_CONST(0xffffffff) << CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SHIFT)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_RANGE                   31:0
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_WOFFSET                 0x0
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_DEFAULT                 _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_DEFAULT_MASK                    _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DEBUG_COUNTER_2_0_DBG_CNT_2_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0  // CSI Pixel Stream A Expected Frame
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0                     _MK_ADDR_CONST(0x232)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_SECURE                      0x0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_WORD_COUNT                  0x1
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_READ_MASK                   _MK_MASK_CONST(0x1ffffff1)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_WRITE_MASK                  _MK_MASK_CONST(0x1ffffff1)
+// When set to one enables checking of the time between
+// start line requests from the Header Parser to CSI-PPA.
+// A fake EF will be outputted by CSI-PPA if this time 
+// between line starts exceeds the value in 
+// MAX_CLOCKS_BETWEEN_LINES. Padding lines can be inserted
+// before the fake EF, if the number of lines outputted,
+// when the fake EF is generated is less than the expected
+// frame height. The type of padding is specified using
+// CSI_PPA_PAD_FRAME.
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SHIFT)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_RANGE                       0:0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_ENABLE_LINE_TIMEOUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Maximum Number of viclk clock cycles between line
+// start requests. The value in this field is in terms
+// of 256 viclk clock cycles.
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_FIELD                        (_MK_MASK_CONST(0xfff) << CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SHIFT)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_RANGE                        15:4
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_MAX_CLOCKS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// CSI-PPA Expected Frame Height
+// Specifies the expected height of the CSI-PPA frame 
+// output. Padding out of frames that are shorter
+// than this expected height can be specified using
+// CSI_PPA_PAD_FRAME. If CSI_PPA_PAD_FRAME is set to
+// PAD0S or PAD1S, this parameter must be programmed.
+// If CSI_PPA_PAD_FRAME is set to NOPAD, this parameter
+// may not be programmed. 
+// Programmed Value = number of lines
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_FIELD                  (_MK_MASK_CONST(0x1fff) << CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SHIFT)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_RANGE                  28:16
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0_PPA_EXP_FRAME_HEIGHT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0  // CSI Pixel Stream B Expected Frame
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0                     _MK_ADDR_CONST(0x233)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_SECURE                      0x0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_WORD_COUNT                  0x1
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_RESET_VAL                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_RESET_MASK                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_SW_DEFAULT_VAL                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_READ_MASK                   _MK_MASK_CONST(0x1ffffff1)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_WRITE_MASK                  _MK_MASK_CONST(0x1ffffff1)
+// When set to one enables checking of the time between
+// start line requests from the Header Parser to CSI-PPB.
+// A fake EF will be outputted by CSI-PPB if this time 
+// between line starts exceeds the value in 
+// MAX_CLOCKS_BETWEEN_LINES. Padding lines can be inserted
+// before the fake EF, if the number of lines outputted,
+// when the fake EF is generated is less than the expected
+// frame height. The type of padding is specified using
+// CSI_PPB_PAD_FRAME.
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SHIFT                       _MK_SHIFT_CONST(0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_FIELD                       (_MK_MASK_CONST(0x1) << CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SHIFT)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_RANGE                       0:0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_WOFFSET                     0x0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_ENABLE_LINE_TIMEOUT_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+// Maximum Number of viclk clock cycles between line
+// start requests. The value in this field is in terms
+// of 256 viclk clock cycles.
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SHIFT                        _MK_SHIFT_CONST(4)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_FIELD                        (_MK_MASK_CONST(0xfff) << CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SHIFT)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_RANGE                        15:4
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_WOFFSET                      0x0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_MAX_CLOCKS_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// CSI-PPB Expected Frame Height
+// Specifies the expected height of the CSI-PPB frame 
+// output. Padding out of frames that are shorter
+// than this expected height can be specified using
+// CSI_PPB_PAD_FRAME. If CSI_PPB_PAD_FRAME is set to
+// PAD0S or PAD1S, this parameter must be programmed.
+// If CSI_PPB_PAD_FRAME is set to NOPAD, this parameter
+// may not be programmed.
+// Programmed Value = number of lines
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SHIFT                  _MK_SHIFT_CONST(16)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_FIELD                  (_MK_MASK_CONST(0x1fff) << CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SHIFT)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_RANGE                  28:16
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_WOFFSET                        0x0
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_DEFAULT                        _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_DEFAULT_MASK                   _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SW_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0_PPB_EXP_FRAME_HEIGHT_SW_DEFAULT_MASK                        _MK_MASK_CONST(0x0)
+
+
+// Register CSI_DSI_MIPI_CAL_CONFIG_0  // Calibration settings for DSI mipi pad
+#define CSI_DSI_MIPI_CAL_CONFIG_0                       _MK_ADDR_CONST(0x234)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_SECURE                        0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_WORD_COUNT                    0x1
+#define CSI_DSI_MIPI_CAL_CONFIG_0_RESET_VAL                     _MK_MASK_CONST(0x200000)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_RESET_MASK                    _MK_MASK_CONST(0x403f1f1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_SW_DEFAULT_VAL                        _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_SW_DEFAULT_MASK                       _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_READ_MASK                     _MK_MASK_CONST(0x403f1f1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_WRITE_MASK                    _MK_MASK_CONST(0x403f1f1f)
+// 2's complement offset for TERMADJ
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SHIFT                        _MK_SHIFT_CONST(0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_FIELD                        (_MK_MASK_CONST(0x1f) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_RANGE                        4:0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_WOFFSET                      0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_TERMOSD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPUADJ
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SHIFT                        _MK_SHIFT_CONST(8)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_FIELD                        (_MK_MASK_CONST(0x1f) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_RANGE                        12:8
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_WOFFSET                      0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPUOSD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// 2's complement offset for HSPDADJ
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SHIFT                        _MK_SHIFT_CONST(16)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_FIELD                        (_MK_MASK_CONST(0x1f) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_RANGE                        20:16
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_WOFFSET                      0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_DEFAULT_MASK                 _MK_MASK_CONST(0x1f)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SW_DEFAULT                   _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_HSPDOSD_SW_DEFAULT_MASK                      _MK_MASK_CONST(0x0)
+
+// Select the DSI PADS for auto calibration.
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_SELD_SHIFT                   _MK_SHIFT_CONST(21)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_SELD_FIELD                   (_MK_MASK_CONST(0x1) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_SELD_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_SELD_RANGE                   21:21
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_SELD_WOFFSET                 0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_SELD_DEFAULT                 _MK_MASK_CONST(0x1)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_SELD_DEFAULT_MASK                    _MK_MASK_CONST(0x1)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_SELD_SW_DEFAULT                      _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_SELD_SW_DEFAULT_MASK                 _MK_MASK_CONST(0x0)
+
+// When 0 (normal operation), use the above registers
+// as an offset to the Calibration State machine setting
+// for TERMADJ/HSPUADJ/HSPDADJ values to the 
+// Mipi Pads. When 1, use the register values above as
+// the actual value going to TERMADJ/HSPUADJ/HSPDADJ
+// on the Mipi Pads.
+// Writting a one to Bit 31 of CILA_MIPI_CAL_CONFIG 
+// (MIPI_CAL_STARTCAL) starts the Calibration State
+// machine.
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SHIFT                       _MK_SHIFT_CONST(30)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_FIELD                       (_MK_MASK_CONST(0x1) << CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SHIFT)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_RANGE                       30:30
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_WOFFSET                     0x0
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_DEFAULT                     _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_DEFAULT_MASK                        _MK_MASK_CONST(0x1)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SW_DEFAULT                  _MK_MASK_CONST(0x0)
+#define CSI_DSI_MIPI_CAL_CONFIG_0_MIPI_CAL_OVERIDED_SW_DEFAULT_MASK                     _MK_MASK_CONST(0x0)
+
+//Interface packets
+//SENSOR2CIL
+
+// Packet SENSOR2CIL_PKT
+#define SENSOR2CIL_PKT_SIZE 10
+
+// Data
+#define SENSOR2CIL_PKT_BYTE_SHIFT                       _MK_SHIFT_CONST(0)
+#define SENSOR2CIL_PKT_BYTE_FIELD                       (_MK_MASK_CONST(0xff) << SENSOR2CIL_PKT_BYTE_SHIFT)
+#define SENSOR2CIL_PKT_BYTE_RANGE                       _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define SENSOR2CIL_PKT_BYTE_ROW                 0
+
+// Start of frame
+#define SENSOR2CIL_PKT_SOT_SHIFT                        _MK_SHIFT_CONST(8)
+#define SENSOR2CIL_PKT_SOT_FIELD                        (_MK_MASK_CONST(0x1) << SENSOR2CIL_PKT_SOT_SHIFT)
+#define SENSOR2CIL_PKT_SOT_RANGE                        _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8)
+#define SENSOR2CIL_PKT_SOT_ROW                  0
+
+// End of frame
+#define SENSOR2CIL_PKT_EOT_SHIFT                        _MK_SHIFT_CONST(9)
+#define SENSOR2CIL_PKT_EOT_FIELD                        (_MK_MASK_CONST(0x1) << SENSOR2CIL_PKT_EOT_SHIFT)
+#define SENSOR2CIL_PKT_EOT_RANGE                        _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9)
+#define SENSOR2CIL_PKT_EOT_ROW                  0
+
+//CIL2CSI
+
+// Packet CIL2CSI_PKT
+#define CIL2CSI_PKT_SIZE 8
+
+// Data
+#define CIL2CSI_PKT_BYTE_SHIFT                  _MK_SHIFT_CONST(0)
+#define CIL2CSI_PKT_BYTE_FIELD                  (_MK_MASK_CONST(0xff) << CIL2CSI_PKT_BYTE_SHIFT)
+#define CIL2CSI_PKT_BYTE_RANGE                  _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CIL2CSI_PKT_BYTE_ROW                    0
+
+//VI2CSI_HOST
+
+// Packet VI2CSI_HOST_PKT
+#define VI2CSI_HOST_PKT_SIZE 33
+
+// Data
+#define VI2CSI_HOST_PKT_HOSTDATA_SHIFT                  _MK_SHIFT_CONST(0)
+#define VI2CSI_HOST_PKT_HOSTDATA_FIELD                  (_MK_MASK_CONST(0xffffffff) << VI2CSI_HOST_PKT_HOSTDATA_SHIFT)
+#define VI2CSI_HOST_PKT_HOSTDATA_RANGE                  _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(0)
+#define VI2CSI_HOST_PKT_HOSTDATA_ROW                    0
+
+// End of packet tag, 0: end of packet, 1: valid packet data
+#define VI2CSI_HOST_PKT_TAG_SHIFT                       _MK_SHIFT_CONST(32)
+#define VI2CSI_HOST_PKT_TAG_FIELD                       (_MK_MASK_CONST(0x1) << VI2CSI_HOST_PKT_TAG_SHIFT)
+#define VI2CSI_HOST_PKT_TAG_RANGE                       _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32)
+#define VI2CSI_HOST_PKT_TAG_ROW                 0
+
+// VI2CSI_VIP
+
+// Packet VI2CSI_VIP_PKT
+#define VI2CSI_VIP_PKT_SIZE 16
+
+// Data
+#define VI2CSI_VIP_PKT_VIPDATA_SHIFT                    _MK_SHIFT_CONST(0)
+#define VI2CSI_VIP_PKT_VIPDATA_FIELD                    (_MK_MASK_CONST(0xffff) << VI2CSI_VIP_PKT_VIPDATA_SHIFT)
+#define VI2CSI_VIP_PKT_VIPDATA_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(0)
+#define VI2CSI_VIP_PKT_VIPDATA_ROW                      0
+
+//SENSOR2CIL_TIMING
+
+// Packet SENSOR2CIL_TIMING_PKT
+#define SENSOR2CIL_TIMING_PKT_SIZE 73
+
+// 
+#define SENSOR2CIL_TIMING_PKT_LPX_SHIFT                 _MK_SHIFT_CONST(0)
+#define SENSOR2CIL_TIMING_PKT_LPX_FIELD                 (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_LPX_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_LPX_RANGE                 _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define SENSOR2CIL_TIMING_PKT_LPX_ROW                   0
+
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_SHIFT                  _MK_SHIFT_CONST(8)
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_FIELD                  (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_PREPARE_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_RANGE                  _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define SENSOR2CIL_TIMING_PKT_HS_PREPARE_ROW                    0
+
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_SHIFT                     _MK_SHIFT_CONST(16)
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_FIELD                     (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_ZERO_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define SENSOR2CIL_TIMING_PKT_HS_ZERO_ROW                       0
+
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_SHIFT                    _MK_SHIFT_CONST(24)
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_FIELD                    (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_TRAIL_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define SENSOR2CIL_TIMING_PKT_HS_TRAIL_ROW                      0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_SHIFT                    _MK_SHIFT_CONST(32)
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_FIELD                    (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_ZERO_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_RANGE                    _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define SENSOR2CIL_TIMING_PKT_CLK_ZERO_ROW                      0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_SHIFT                     _MK_SHIFT_CONST(40)
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_FIELD                     (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_PRE_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_RANGE                     _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(40)
+#define SENSOR2CIL_TIMING_PKT_CLK_PRE_ROW                       0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_SHIFT                    _MK_SHIFT_CONST(48)
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_FIELD                    (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_POST_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_RANGE                    _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(48)
+#define SENSOR2CIL_TIMING_PKT_CLK_POST_ROW                      0
+
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_SHIFT                   _MK_SHIFT_CONST(56)
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_FIELD                   (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_CLK_TRAIL_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_RANGE                   _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(56)
+#define SENSOR2CIL_TIMING_PKT_CLK_TRAIL_ROW                     0
+
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_SHIFT                     _MK_SHIFT_CONST(64)
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_FIELD                     (_MK_MASK_CONST(0xff) << SENSOR2CIL_TIMING_PKT_HS_EXIT_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_RANGE                     _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define SENSOR2CIL_TIMING_PKT_HS_EXIT_ROW                       0
+
+// default to use RTL internal
+#define SENSOR2CIL_TIMING_PKT_RANDOM_SHIFT                      _MK_SHIFT_CONST(72)
+#define SENSOR2CIL_TIMING_PKT_RANDOM_FIELD                      (_MK_MASK_CONST(0x1) << SENSOR2CIL_TIMING_PKT_RANDOM_SHIFT)
+#define SENSOR2CIL_TIMING_PKT_RANDOM_RANGE                      _MK_SHIFT_CONST(72):_MK_SHIFT_CONST(72)
+#define SENSOR2CIL_TIMING_PKT_RANDOM_ROW                        0
+
+//SENSOR2CIL_COMMAND
+
+// Packet SENSOR2CIL_COMMAND_PKT
+#define SENSOR2CIL_COMMAND_PKT_SIZE 33
+
+// 
+// NO_OP    =0x0,   
+// ESC_ULPS =0x1, // escape mode: ultra low power state
+// ESC_LPDT =0x2, // escape mode: low power data transmission
+// ESC_RAR  =0x3, // escape mode: remote application reset
+// SOT_ERR  =0x4  // use SOT_CODE for SOT error injection
+// FR_HSCLK =0x5  // set high speed clock free running
+#define SENSOR2CIL_COMMAND_PKT_CMD_SHIFT                        _MK_SHIFT_CONST(0)
+#define SENSOR2CIL_COMMAND_PKT_CMD_FIELD                        (_MK_MASK_CONST(0x1f) << SENSOR2CIL_COMMAND_PKT_CMD_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_CMD_RANGE                        _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define SENSOR2CIL_COMMAND_PKT_CMD_ROW                  0
+
+// sot or escape delay in esc mode
+#define SENSOR2CIL_COMMAND_PKT_PARAM_SHIFT                      _MK_SHIFT_CONST(5)
+#define SENSOR2CIL_COMMAND_PKT_PARAM_FIELD                      (_MK_MASK_CONST(0xff) << SENSOR2CIL_COMMAND_PKT_PARAM_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_PARAM_RANGE                      _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(5)
+#define SENSOR2CIL_COMMAND_PKT_PARAM_ROW                        0
+
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_SHIFT                 _MK_SHIFT_CONST(13)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_FIELD                 (_MK_MASK_CONST(0xff) << SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_RANGE                 _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(13)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_ENTRY_SEQ_ROW                   0
+
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_SHIFT                      _MK_SHIFT_CONST(21)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_FIELD                      (_MK_MASK_CONST(0xff) << SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_RANGE                      _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(21)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_CODE_ROW                        0
+
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_SHIFT                     _MK_SHIFT_CONST(29)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_FIELD                     (_MK_MASK_CONST(0xf) << SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_SHIFT)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_RANGE                     _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(29)
+#define SENSOR2CIL_COMMAND_PKT_ESC_MODE_WIDTH_ROW                       0
+
+//Internal packets
+
+// Packet CSI_HEADER
+#define CSI_HEADER_SIZE 32
+
+// Data type in packet
+#define CSI_HEADER_DATA_TYPE_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_HEADER_DATA_TYPE_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_HEADER_DATA_TYPE_SHIFT)
+#define CSI_HEADER_DATA_TYPE_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define CSI_HEADER_DATA_TYPE_ROW                        0
+
+// Virtual channel number
+#define CSI_HEADER_VIRTUAL_CHANNEL_SHIFT                        _MK_SHIFT_CONST(6)
+#define CSI_HEADER_VIRTUAL_CHANNEL_FIELD                        (_MK_MASK_CONST(0x3) << CSI_HEADER_VIRTUAL_CHANNEL_SHIFT)
+#define CSI_HEADER_VIRTUAL_CHANNEL_RANGE                        _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(6)
+#define CSI_HEADER_VIRTUAL_CHANNEL_ROW                  0
+
+// Number of bytes in packet payload
+#define CSI_HEADER_WORD_COUNT_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_HEADER_WORD_COUNT_FIELD                     (_MK_MASK_CONST(0xffff) << CSI_HEADER_WORD_COUNT_SHIFT)
+#define CSI_HEADER_WORD_COUNT_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(8)
+#define CSI_HEADER_WORD_COUNT_ROW                       0
+
+// Error correction code for packet
+#define CSI_HEADER_ECC_SHIFT                    _MK_SHIFT_CONST(24)
+#define CSI_HEADER_ECC_FIELD                    (_MK_MASK_CONST(0xff) << CSI_HEADER_ECC_SHIFT)
+#define CSI_HEADER_ECC_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_HEADER_ECC_ROW                      0
+
+
+// Packet CSI_RAISE
+#define CSI_RAISE_SIZE 20
+
+#define CSI_RAISE_VECTOR_SHIFT                  _MK_SHIFT_CONST(0)
+#define CSI_RAISE_VECTOR_FIELD                  (_MK_MASK_CONST(0x1f) << CSI_RAISE_VECTOR_SHIFT)
+#define CSI_RAISE_VECTOR_RANGE                  _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define CSI_RAISE_VECTOR_ROW                    0
+
+#define CSI_RAISE_COUNT_SHIFT                   _MK_SHIFT_CONST(8)
+#define CSI_RAISE_COUNT_FIELD                   (_MK_MASK_CONST(0xff) << CSI_RAISE_COUNT_SHIFT)
+#define CSI_RAISE_COUNT_RANGE                   _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAISE_COUNT_ROW                     0
+
+#define CSI_RAISE_CHID_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSI_RAISE_CHID_FIELD                    (_MK_MASK_CONST(0xf) << CSI_RAISE_CHID_SHIFT)
+#define CSI_RAISE_CHID_RANGE                    _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(16)
+#define CSI_RAISE_CHID_ROW                      0
+
+
+// Packet CSI_GENERIC_BYTE
+#define CSI_GENERIC_BYTE_SIZE 72
+
+#define CSI_GENERIC_BYTE_BYTE0_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_GENERIC_BYTE_BYTE0_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE0_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE0_RANGE                    _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_GENERIC_BYTE_BYTE0_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE1_SHIFT                    _MK_SHIFT_CONST(8)
+#define CSI_GENERIC_BYTE_BYTE1_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE1_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE1_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_GENERIC_BYTE_BYTE1_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE2_SHIFT                    _MK_SHIFT_CONST(16)
+#define CSI_GENERIC_BYTE_BYTE2_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE2_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE2_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSI_GENERIC_BYTE_BYTE2_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE3_SHIFT                    _MK_SHIFT_CONST(24)
+#define CSI_GENERIC_BYTE_BYTE3_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE3_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE3_RANGE                    _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_GENERIC_BYTE_BYTE3_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE4_SHIFT                    _MK_SHIFT_CONST(32)
+#define CSI_GENERIC_BYTE_BYTE4_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE4_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE4_RANGE                    _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(32)
+#define CSI_GENERIC_BYTE_BYTE4_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE5_SHIFT                    _MK_SHIFT_CONST(40)
+#define CSI_GENERIC_BYTE_BYTE5_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE5_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE5_RANGE                    _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(40)
+#define CSI_GENERIC_BYTE_BYTE5_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE6_SHIFT                    _MK_SHIFT_CONST(48)
+#define CSI_GENERIC_BYTE_BYTE6_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE6_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE6_RANGE                    _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(48)
+#define CSI_GENERIC_BYTE_BYTE6_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE7_SHIFT                    _MK_SHIFT_CONST(56)
+#define CSI_GENERIC_BYTE_BYTE7_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE7_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE7_RANGE                    _MK_SHIFT_CONST(63):_MK_SHIFT_CONST(56)
+#define CSI_GENERIC_BYTE_BYTE7_ROW                      0
+
+#define CSI_GENERIC_BYTE_BYTE8_SHIFT                    _MK_SHIFT_CONST(64)
+#define CSI_GENERIC_BYTE_BYTE8_FIELD                    (_MK_MASK_CONST(0xff) << CSI_GENERIC_BYTE_BYTE8_SHIFT)
+#define CSI_GENERIC_BYTE_BYTE8_RANGE                    _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(64)
+#define CSI_GENERIC_BYTE_BYTE8_ROW                      0
+
+
+// Packet CSI_RGB_666
+#define CSI_RGB_666_SIZE 72
+
+#define CSI_RGB_666_B0_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_RGB_666_B0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B0_SHIFT)
+#define CSI_RGB_666_B0_RANGE                    _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define CSI_RGB_666_B0_ROW                      0
+
+#define CSI_RGB_666_G0_SHIFT                    _MK_SHIFT_CONST(6)
+#define CSI_RGB_666_G0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G0_SHIFT)
+#define CSI_RGB_666_G0_RANGE                    _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(6)
+#define CSI_RGB_666_G0_ROW                      0
+
+#define CSI_RGB_666_R0_SHIFT                    _MK_SHIFT_CONST(12)
+#define CSI_RGB_666_R0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R0_SHIFT)
+#define CSI_RGB_666_R0_RANGE                    _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(12)
+#define CSI_RGB_666_R0_ROW                      0
+
+#define CSI_RGB_666_B1_SHIFT                    _MK_SHIFT_CONST(18)
+#define CSI_RGB_666_B1_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B1_SHIFT)
+#define CSI_RGB_666_B1_RANGE                    _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(18)
+#define CSI_RGB_666_B1_ROW                      0
+
+#define CSI_RGB_666_G1_SHIFT                    _MK_SHIFT_CONST(24)
+#define CSI_RGB_666_G1_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G1_SHIFT)
+#define CSI_RGB_666_G1_RANGE                    _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(24)
+#define CSI_RGB_666_G1_ROW                      0
+
+#define CSI_RGB_666_R1_SHIFT                    _MK_SHIFT_CONST(30)
+#define CSI_RGB_666_R1_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R1_SHIFT)
+#define CSI_RGB_666_R1_RANGE                    _MK_SHIFT_CONST(35):_MK_SHIFT_CONST(30)
+#define CSI_RGB_666_R1_ROW                      0
+
+#define CSI_RGB_666_B2_SHIFT                    _MK_SHIFT_CONST(36)
+#define CSI_RGB_666_B2_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B2_SHIFT)
+#define CSI_RGB_666_B2_RANGE                    _MK_SHIFT_CONST(41):_MK_SHIFT_CONST(36)
+#define CSI_RGB_666_B2_ROW                      0
+
+#define CSI_RGB_666_G2_SHIFT                    _MK_SHIFT_CONST(42)
+#define CSI_RGB_666_G2_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G2_SHIFT)
+#define CSI_RGB_666_G2_RANGE                    _MK_SHIFT_CONST(47):_MK_SHIFT_CONST(42)
+#define CSI_RGB_666_G2_ROW                      0
+
+#define CSI_RGB_666_R2_SHIFT                    _MK_SHIFT_CONST(48)
+#define CSI_RGB_666_R2_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R2_SHIFT)
+#define CSI_RGB_666_R2_RANGE                    _MK_SHIFT_CONST(53):_MK_SHIFT_CONST(48)
+#define CSI_RGB_666_R2_ROW                      0
+
+#define CSI_RGB_666_B3_SHIFT                    _MK_SHIFT_CONST(54)
+#define CSI_RGB_666_B3_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_B3_SHIFT)
+#define CSI_RGB_666_B3_RANGE                    _MK_SHIFT_CONST(59):_MK_SHIFT_CONST(54)
+#define CSI_RGB_666_B3_ROW                      0
+
+#define CSI_RGB_666_G3_SHIFT                    _MK_SHIFT_CONST(60)
+#define CSI_RGB_666_G3_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_G3_SHIFT)
+#define CSI_RGB_666_G3_RANGE                    _MK_SHIFT_CONST(65):_MK_SHIFT_CONST(60)
+#define CSI_RGB_666_G3_ROW                      0
+
+#define CSI_RGB_666_R3_SHIFT                    _MK_SHIFT_CONST(66)
+#define CSI_RGB_666_R3_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_666_R3_SHIFT)
+#define CSI_RGB_666_R3_RANGE                    _MK_SHIFT_CONST(71):_MK_SHIFT_CONST(66)
+#define CSI_RGB_666_R3_ROW                      0
+
+
+// Packet CSI_RGB_565
+#define CSI_RGB_565_SIZE 16
+
+#define CSI_RGB_565_B0_SHIFT                    _MK_SHIFT_CONST(0)
+#define CSI_RGB_565_B0_FIELD                    (_MK_MASK_CONST(0x1f) << CSI_RGB_565_B0_SHIFT)
+#define CSI_RGB_565_B0_RANGE                    _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0)
+#define CSI_RGB_565_B0_ROW                      0
+
+#define CSI_RGB_565_G0_SHIFT                    _MK_SHIFT_CONST(5)
+#define CSI_RGB_565_G0_FIELD                    (_MK_MASK_CONST(0x3f) << CSI_RGB_565_G0_SHIFT)
+#define CSI_RGB_565_G0_RANGE                    _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(5)
+#define CSI_RGB_565_G0_ROW                      0
+
+#define CSI_RGB_565_R0_SHIFT                    _MK_SHIFT_CONST(11)
+#define CSI_RGB_565_R0_FIELD                    (_MK_MASK_CONST(0x1f) << CSI_RGB_565_R0_SHIFT)
+#define CSI_RGB_565_R0_RANGE                    _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(11)
+#define CSI_RGB_565_R0_ROW                      0
+
+
+// Packet CSI_RAW_6
+#define CSI_RAW_6_SIZE 24
+
+#define CSI_RAW_6_S0_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_RAW_6_S0_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S0_SHIFT)
+#define CSI_RAW_6_S0_RANGE                      _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define CSI_RAW_6_S0_ROW                        0
+
+#define CSI_RAW_6_S1_SHIFT                      _MK_SHIFT_CONST(6)
+#define CSI_RAW_6_S1_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S1_SHIFT)
+#define CSI_RAW_6_S1_RANGE                      _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(6)
+#define CSI_RAW_6_S1_ROW                        0
+
+#define CSI_RAW_6_S2_SHIFT                      _MK_SHIFT_CONST(12)
+#define CSI_RAW_6_S2_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S2_SHIFT)
+#define CSI_RAW_6_S2_RANGE                      _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(12)
+#define CSI_RAW_6_S2_ROW                        0
+
+#define CSI_RAW_6_S3_SHIFT                      _MK_SHIFT_CONST(18)
+#define CSI_RAW_6_S3_FIELD                      (_MK_MASK_CONST(0x3f) << CSI_RAW_6_S3_SHIFT)
+#define CSI_RAW_6_S3_RANGE                      _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(18)
+#define CSI_RAW_6_S3_ROW                        0
+
+
+// Packet CSI_RAW_7
+#define CSI_RAW_7_SIZE 56
+
+#define CSI_RAW_7_S0_SHIFT                      _MK_SHIFT_CONST(0)
+#define CSI_RAW_7_S0_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S0_SHIFT)
+#define CSI_RAW_7_S0_RANGE                      _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(0)
+#define CSI_RAW_7_S0_ROW                        0
+
+#define CSI_RAW_7_S1_SHIFT                      _MK_SHIFT_CONST(7)
+#define CSI_RAW_7_S1_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S1_SHIFT)
+#define CSI_RAW_7_S1_RANGE                      _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(7)
+#define CSI_RAW_7_S1_ROW                        0
+
+#define CSI_RAW_7_S2_SHIFT                      _MK_SHIFT_CONST(14)
+#define CSI_RAW_7_S2_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S2_SHIFT)
+#define CSI_RAW_7_S2_RANGE                      _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(14)
+#define CSI_RAW_7_S2_ROW                        0
+
+#define CSI_RAW_7_S3_SHIFT                      _MK_SHIFT_CONST(21)
+#define CSI_RAW_7_S3_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S3_SHIFT)
+#define CSI_RAW_7_S3_RANGE                      _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(21)
+#define CSI_RAW_7_S3_ROW                        0
+
+#define CSI_RAW_7_S4_SHIFT                      _MK_SHIFT_CONST(28)
+#define CSI_RAW_7_S4_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S4_SHIFT)
+#define CSI_RAW_7_S4_RANGE                      _MK_SHIFT_CONST(34):_MK_SHIFT_CONST(28)
+#define CSI_RAW_7_S4_ROW                        0
+
+#define CSI_RAW_7_S5_SHIFT                      _MK_SHIFT_CONST(35)
+#define CSI_RAW_7_S5_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S5_SHIFT)
+#define CSI_RAW_7_S5_RANGE                      _MK_SHIFT_CONST(41):_MK_SHIFT_CONST(35)
+#define CSI_RAW_7_S5_ROW                        0
+
+#define CSI_RAW_7_S6_SHIFT                      _MK_SHIFT_CONST(42)
+#define CSI_RAW_7_S6_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S6_SHIFT)
+#define CSI_RAW_7_S6_RANGE                      _MK_SHIFT_CONST(48):_MK_SHIFT_CONST(42)
+#define CSI_RAW_7_S6_ROW                        0
+
+#define CSI_RAW_7_S7_SHIFT                      _MK_SHIFT_CONST(49)
+#define CSI_RAW_7_S7_FIELD                      (_MK_MASK_CONST(0x7f) << CSI_RAW_7_S7_SHIFT)
+#define CSI_RAW_7_S7_RANGE                      _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(49)
+#define CSI_RAW_7_S7_ROW                        0
+
+
+// Packet CSI_RAW_10
+#define CSI_RAW_10_SIZE 40
+
+#define CSI_RAW_10_S0_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_RAW_10_S0_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S0_SHIFT)
+#define CSI_RAW_10_S0_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_RAW_10_S0_ROW                       0
+
+#define CSI_RAW_10_S1_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_RAW_10_S1_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S1_SHIFT)
+#define CSI_RAW_10_S1_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAW_10_S1_ROW                       0
+
+#define CSI_RAW_10_S2_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_RAW_10_S2_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S2_SHIFT)
+#define CSI_RAW_10_S2_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSI_RAW_10_S2_ROW                       0
+
+#define CSI_RAW_10_S3_SHIFT                     _MK_SHIFT_CONST(24)
+#define CSI_RAW_10_S3_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_10_S3_SHIFT)
+#define CSI_RAW_10_S3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_RAW_10_S3_ROW                       0
+
+#define CSI_RAW_10_L0_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSI_RAW_10_L0_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L0_SHIFT)
+#define CSI_RAW_10_L0_RANGE                     _MK_SHIFT_CONST(33):_MK_SHIFT_CONST(32)
+#define CSI_RAW_10_L0_ROW                       0
+
+#define CSI_RAW_10_L1_SHIFT                     _MK_SHIFT_CONST(34)
+#define CSI_RAW_10_L1_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L1_SHIFT)
+#define CSI_RAW_10_L1_RANGE                     _MK_SHIFT_CONST(35):_MK_SHIFT_CONST(34)
+#define CSI_RAW_10_L1_ROW                       0
+
+#define CSI_RAW_10_L2_SHIFT                     _MK_SHIFT_CONST(36)
+#define CSI_RAW_10_L2_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L2_SHIFT)
+#define CSI_RAW_10_L2_RANGE                     _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(36)
+#define CSI_RAW_10_L2_ROW                       0
+
+#define CSI_RAW_10_L3_SHIFT                     _MK_SHIFT_CONST(38)
+#define CSI_RAW_10_L3_FIELD                     (_MK_MASK_CONST(0x3) << CSI_RAW_10_L3_SHIFT)
+#define CSI_RAW_10_L3_RANGE                     _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(38)
+#define CSI_RAW_10_L3_ROW                       0
+
+
+// Packet CSI_RAW_12
+#define CSI_RAW_12_SIZE 24
+
+#define CSI_RAW_12_S0_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_RAW_12_S0_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_12_S0_SHIFT)
+#define CSI_RAW_12_S0_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_RAW_12_S0_ROW                       0
+
+#define CSI_RAW_12_S1_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_RAW_12_S1_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_12_S1_SHIFT)
+#define CSI_RAW_12_S1_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAW_12_S1_ROW                       0
+
+#define CSI_RAW_12_L0_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_RAW_12_L0_FIELD                     (_MK_MASK_CONST(0xf) << CSI_RAW_12_L0_SHIFT)
+#define CSI_RAW_12_L0_RANGE                     _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(16)
+#define CSI_RAW_12_L0_ROW                       0
+
+#define CSI_RAW_12_L1_SHIFT                     _MK_SHIFT_CONST(20)
+#define CSI_RAW_12_L1_FIELD                     (_MK_MASK_CONST(0xf) << CSI_RAW_12_L1_SHIFT)
+#define CSI_RAW_12_L1_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(20)
+#define CSI_RAW_12_L1_ROW                       0
+
+
+// Packet CSI_RAW_14
+#define CSI_RAW_14_SIZE 56
+
+#define CSI_RAW_14_S0_SHIFT                     _MK_SHIFT_CONST(0)
+#define CSI_RAW_14_S0_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S0_SHIFT)
+#define CSI_RAW_14_S0_RANGE                     _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0)
+#define CSI_RAW_14_S0_ROW                       0
+
+#define CSI_RAW_14_S1_SHIFT                     _MK_SHIFT_CONST(8)
+#define CSI_RAW_14_S1_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S1_SHIFT)
+#define CSI_RAW_14_S1_RANGE                     _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8)
+#define CSI_RAW_14_S1_ROW                       0
+
+#define CSI_RAW_14_S2_SHIFT                     _MK_SHIFT_CONST(16)
+#define CSI_RAW_14_S2_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S2_SHIFT)
+#define CSI_RAW_14_S2_RANGE                     _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16)
+#define CSI_RAW_14_S2_ROW                       0
+
+#define CSI_RAW_14_S3_SHIFT                     _MK_SHIFT_CONST(24)
+#define CSI_RAW_14_S3_FIELD                     (_MK_MASK_CONST(0xff) << CSI_RAW_14_S3_SHIFT)
+#define CSI_RAW_14_S3_RANGE                     _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(24)
+#define CSI_RAW_14_S3_ROW                       0
+
+#define CSI_RAW_14_L0_SHIFT                     _MK_SHIFT_CONST(32)
+#define CSI_RAW_14_L0_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L0_SHIFT)
+#define CSI_RAW_14_L0_RANGE                     _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(32)
+#define CSI_RAW_14_L0_ROW                       0
+
+#define CSI_RAW_14_L1_SHIFT                     _MK_SHIFT_CONST(38)
+#define CSI_RAW_14_L1_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L1_SHIFT)
+#define CSI_RAW_14_L1_RANGE                     _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(38)
+#define CSI_RAW_14_L1_ROW                       0
+
+#define CSI_RAW_14_L2_SHIFT                     _MK_SHIFT_CONST(44)
+#define CSI_RAW_14_L2_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L2_SHIFT)
+#define CSI_RAW_14_L2_RANGE                     _MK_SHIFT_CONST(49):_MK_SHIFT_CONST(44)
+#define CSI_RAW_14_L2_ROW                       0
+
+#define CSI_RAW_14_L3_SHIFT                     _MK_SHIFT_CONST(50)
+#define CSI_RAW_14_L3_FIELD                     (_MK_MASK_CONST(0x3f) << CSI_RAW_14_L3_SHIFT)
+#define CSI_RAW_14_L3_RANGE                     _MK_SHIFT_CONST(55):_MK_SHIFT_CONST(50)
+#define CSI_RAW_14_L3_ROW                       0
+
+//defines, used by CSI CModel
+//CSI-2 Data Types
+// SSP = Synchronization Short Packet
+#define CSI_DT_SSP_FS   0
+// Frame Start
+#define CSI_DT_SSP_FE   1
+// Frame End
+#define CSI_DT_SSP_LS   2
+// Line Start
+#define CSI_DT_SSP_LE   3
+// Line End
+#define CSI_DT_SSP_R1   4
+// Reserved 1
+#define CSI_DT_SSP_R2   5
+// Reserved 2
+#define CSI_DT_SSP_R3   6
+// Reserved 3
+#define CSI_DT_SSP_R4   7
+// Reserved 4
+// GSP = Generic Short Packet
+#define CSI_DT_GSP_G1   8
+// Generic Short Packet Code 1
+#define CSI_DT_GSP_G2   9
+// Generic Short Packet Code 2
+#define CSI_DT_GSP_G3   10
+// Generic Short Packet Code 3
+#define CSI_DT_GSP_G4   11
+// Generic Short Packet Code 4
+#define CSI_DT_GSP_G5   12
+// Generic Short Packet Code 5
+#define CSI_DT_GSP_G6   13
+// Generic Short Packet Code 6
+#define CSI_DT_GSP_G7   14
+// Generic Short Packet Code 7
+#define CSI_DT_GSP_G8   15
+// Generic Short Packet Code 8
+// GED = Generic 8-bit Data
+#define CSI_DT_GED_NULL 16
+// Null 
+#define CSI_DT_GED_BLANK        17
+// Blanking Data 
+#define CSI_DT_GED_ED   18
+// Embedded 8-bit non Image Data
+#define CSI_DT_GED_R1   19
+// Reserved
+#define CSI_DT_GED_R2   20
+// Reserved
+#define CSI_DT_GED_R3   21
+// Reserved
+#define CSI_DT_GED_R4   22
+// Reserved
+#define CSI_DT_GED_R5   23
+// Reserved
+// YUV = YUV Image Data Types
+#define CSI_DT_YUV_420_8        24
+// YUV420 8-bit
+#define CSI_DT_YUV_420_10       25
+// YUV420 10-bit
+#define CSI_DT_YUV_420_L_8      26
+// Legacy YUV420 8-bit
+#define CSI_DT_YUV_R1   27
+// Reserved
+#define CSI_DT_YUV_420_CSPS_8   28
+// YUV420 8-bit (Chroma Shifted Pixel Sampling)
+#define CSI_DT_YUV_420_CSPS_10  29
+// YUV420 10-bit (Chroma Shifted Pixel Sampling)
+#define CSI_DT_YUV_422_8        30
+// YUV422 8-bit
+#define CSI_DT_YUV_422_10       31
+// YUV422 10-bit
+// RGB = RGB Image Data Types
+#define CSI_DT_RGB_444  32
+// RGB444
+#define CSI_DT_RGB_555  33
+// RGB555
+#define CSI_DT_RGB_565  34
+// RGB565
+#define CSI_DT_RGB_666  35
+// RGB666
+#define CSI_DT_RGB_888  36
+// RGB888
+#define CSI_DT_RGB_R1   37
+// Reserved
+#define CSI_DT_RGB_R2   38
+// Reserved
+#define CSI_DT_RGB_R3   39
+// Reserved
+// RAW Image Data Types
+#define CSI_DT_RAW_6    40
+// RAW6
+#define CSI_DT_RAW_7    41
+// RAW7
+#define CSI_DT_RAW_8    42
+// RAW8
+#define CSI_DT_RAW_10   43
+// RAW10
+#define CSI_DT_RAW_12   44
+// RAW12
+#define CSI_DT_RAW_14   45
+// RAW14
+#define CSI_DT_RAW_R1   46
+// Reserved
+#define CSI_DT_RAW_R2   47
+// Reserved
+// UED = User Defined 8-bit Data
+#define CSI_DT_UED_U1   48
+// User Defined 8-bit Data Type 1
+#define CSI_DT_UED_U2   49
+// User Defined 8-bit Data Type 2
+#define CSI_DT_UED_U3   50
+// User Defined 8-bit Data Type 3
+#define CSI_DT_UED_U4   51
+// User Defined 8-bit Data Type 4
+#define CSI_DT_UED_R1   52
+// Reserved
+#define CSI_DT_UED_R2   53
+// Reserved
+#define CSI_DT_UED_R3   54
+// Reserved
+#define CSI_DT_UED_R4   55
+// Reserved
+//   Below packet enums are used by the csi RTL code. Their encodings
+// should match that of the defines above. The RTL code can't use the 
+// defines directly because they don't have 6'd in front of them. 
+// Without it verilint gives a warning for every line that uses them.
+
+// Packet D
+#define D_SIZE 6
+
+// SSP = Synchronization Short Packet
+// Reserved
+#define D_T_SHIFT                       _MK_SHIFT_CONST(0)
+#define D_T_FIELD                       (_MK_MASK_CONST(0x3f) << D_T_SHIFT)
+#define D_T_RANGE                       _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(0)
+#define D_T_ROW                 0
+#define D_T_SSP_FS                      _MK_ENUM_CONST(0)    // // Frame Start
+
+#define D_T_SSP_FE                      _MK_ENUM_CONST(1)    // // Frame End
+
+#define D_T_SSP_LS                      _MK_ENUM_CONST(2)    // // Line Start
+
+#define D_T_SSP_LE                      _MK_ENUM_CONST(3)    // // Line End
+
+#define D_T_SSP_R1                      _MK_ENUM_CONST(4)    // // Reserved 1
+
+#define D_T_SSP_R2                      _MK_ENUM_CONST(5)    // // Reserved 2
+
+#define D_T_SSP_R3                      _MK_ENUM_CONST(6)    // // Reserved 3
+
+#define D_T_SSP_R4                      _MK_ENUM_CONST(7)    // // Reserved 4
+// GSP = Generic Short Packet
+
+#define D_T_GSP_G1                      _MK_ENUM_CONST(8)    // // Generic Short Packet Code 1
+
+#define D_T_GSP_G2                      _MK_ENUM_CONST(9)    // // Generic Short Packet Code 2
+
+#define D_T_GSP_G3                      _MK_ENUM_CONST(10)    // // Generic Short Packet Code 3
+
+#define D_T_GSP_G4                      _MK_ENUM_CONST(11)    // // Generic Short Packet Code 4
+
+#define D_T_GSP_G5                      _MK_ENUM_CONST(12)    // // Generic Short Packet Code 5
+
+#define D_T_GSP_G6                      _MK_ENUM_CONST(13)    // // Generic Short Packet Code 6
+
+#define D_T_GSP_G7                      _MK_ENUM_CONST(14)    // // Generic Short Packet Code 7
+
+#define D_T_GSP_G8                      _MK_ENUM_CONST(15)    // // Generic Short Packet Code 8
+// GED = Generic 8-bit Data
+
+#define D_T_GED_NULL                    _MK_ENUM_CONST(16)    // // Null 
+
+#define D_T_GED_BLANK                   _MK_ENUM_CONST(17)    // // Blanking Data 
+
+#define D_T_GED_ED                      _MK_ENUM_CONST(18)    // // Embedded 8-bit non Image Data
+
+#define D_T_GED_R1                      _MK_ENUM_CONST(19)    // // Reserved
+
+#define D_T_GED_R2                      _MK_ENUM_CONST(20)    // // Reserved
+
+#define D_T_GED_R3                      _MK_ENUM_CONST(21)    // // Reserved
+
+#define D_T_GED_R4                      _MK_ENUM_CONST(22)    // // Reserved
+
+#define D_T_GED_R5                      _MK_ENUM_CONST(23)    // // Reserved
+// YUV = YUV Image Data Types
+
+#define D_T_YUV_420_8                   _MK_ENUM_CONST(24)    // // YUV420 8-bit
+
+#define D_T_YUV_420_10                  _MK_ENUM_CONST(25)    // // YUV420 10-bit
+
+#define D_T_YUV_420_L_8                 _MK_ENUM_CONST(26)    // // Legacy YUV420 8-bit
+
+#define D_T_YUV_R1                      _MK_ENUM_CONST(27)    // // Reserved
+
+#define D_T_YUV_420_CSPS_8                      _MK_ENUM_CONST(28)    // // YUV420 8-bit (Chroma Shifted Pixel Sampling)
+
+#define D_T_YUV_420_CSPS_10                     _MK_ENUM_CONST(29)    // // YUV420 10-bit (Chroma Shifted Pixel Sampling)
+
+#define D_T_YUV_422_8                   _MK_ENUM_CONST(30)    // // YUV422 8-bit
+
+#define D_T_YUV_422_10                  _MK_ENUM_CONST(31)    // // YUV422 10-bit
+// RGB = RGB Image Data Types
+
+#define D_T_RGB_444                     _MK_ENUM_CONST(32)    // // RGB444
+
+#define D_T_RGB_555                     _MK_ENUM_CONST(33)    // // RGB555
+
+#define D_T_RGB_565                     _MK_ENUM_CONST(34)    // // RGB565
+
+#define D_T_RGB_666                     _MK_ENUM_CONST(35)    // // RGB666
+
+#define D_T_RGB_888                     _MK_ENUM_CONST(36)    // // RGB888
+
+#define D_T_RGB_R1                      _MK_ENUM_CONST(37)    // // Reserved
+
+#define D_T_RGB_R2                      _MK_ENUM_CONST(38)    // // Reserved
+
+#define D_T_RGB_R3                      _MK_ENUM_CONST(39)    // // Reserved
+// RAW Image Data Types
+
+#define D_T_RAW_6                       _MK_ENUM_CONST(40)    // // RAW6
+
+#define D_T_RAW_7                       _MK_ENUM_CONST(41)    // // RAW7
+
+#define D_T_RAW_8                       _MK_ENUM_CONST(42)    // // RAW8
+
+#define D_T_RAW_10                      _MK_ENUM_CONST(43)    // // RAW10
+
+#define D_T_RAW_12                      _MK_ENUM_CONST(44)    // // RAW12
+
+#define D_T_RAW_14                      _MK_ENUM_CONST(45)    // // RAW14
+
+#define D_T_RAW_R1                      _MK_ENUM_CONST(46)    // // Reserved
+
+#define D_T_RAW_R2                      _MK_ENUM_CONST(47)    // // Reserved
+// UED = User Defined 8-bit Data
+
+#define D_T_UED_U1                      _MK_ENUM_CONST(48)    // // User Defined 8-bit Data Type 1
+
+#define D_T_UED_U2                      _MK_ENUM_CONST(49)    // // User Defined 8-bit Data Type 2
+
+#define D_T_UED_U3                      _MK_ENUM_CONST(50)    // // User Defined 8-bit Data Type 3
+
+#define D_T_UED_U4                      _MK_ENUM_CONST(51)    // // User Defined 8-bit Data Type 4
+
+#define D_T_UED_R1                      _MK_ENUM_CONST(52)    // // Reserved
+
+#define D_T_UED_R2                      _MK_ENUM_CONST(53)    // // Reserved
+
+#define D_T_UED_R3                      _MK_ENUM_CONST(54)    // // Reserved
+
+#define D_T_UED_R4                      _MK_ENUM_CONST(55)
+
+// packet CSI_DT
+
+//
+// REGISTER LIST
+//
+#define LIST_ARVI_REGS(_op_) \
+_op_(VI_OUT_1_INCR_SYNCPT_0) \
+_op_(VI_OUT_1_INCR_SYNCPT_CNTRL_0) \
+_op_(VI_OUT_1_INCR_SYNCPT_ERROR_0) \
+_op_(VI_OUT_2_INCR_SYNCPT_0) \
+_op_(VI_OUT_2_INCR_SYNCPT_CNTRL_0) \
+_op_(VI_OUT_2_INCR_SYNCPT_ERROR_0) \
+_op_(VI_MISC_INCR_SYNCPT_0) \
+_op_(VI_MISC_INCR_SYNCPT_CNTRL_0) \
+_op_(VI_MISC_INCR_SYNCPT_ERROR_0) \
+_op_(VI_CONT_SYNCPT_OUT_1_0) \
+_op_(VI_CONT_SYNCPT_OUT_2_0) \
+_op_(VI_CONT_SYNCPT_VIP_VSYNC_0) \
+_op_(VI_CONT_SYNCPT_VI2EPP_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPA_FRAME_START_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPA_FRAME_END_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPB_FRAME_START_0) \
+_op_(VI_CONT_SYNCPT_CSI_PPB_FRAME_END_0) \
+_op_(VI_CTXSW_0) \
+_op_(VI_INTSTATUS_0) \
+_op_(VI_VI_INPUT_CONTROL_0) \
+_op_(VI_VI_CORE_CONTROL_0) \
+_op_(VI_VI_FIRST_OUTPUT_CONTROL_0) \
+_op_(VI_VI_SECOND_OUTPUT_CONTROL_0) \
+_op_(VI_HOST_INPUT_FRAME_SIZE_0) \
+_op_(VI_HOST_H_ACTIVE_0) \
+_op_(VI_HOST_V_ACTIVE_0) \
+_op_(VI_VIP_H_ACTIVE_0) \
+_op_(VI_VIP_V_ACTIVE_0) \
+_op_(VI_VI_PEER_CONTROL_0) \
+_op_(VI_VI_DMA_SELECT_0) \
+_op_(VI_HOST_DMA_WRITE_BUFFER_0) \
+_op_(VI_HOST_DMA_BASE_ADDRESS_0) \
+_op_(VI_HOST_DMA_WRITE_BUFFER_STATUS_0) \
+_op_(VI_HOST_DMA_WRITE_PEND_BUFCOUNT_0) \
+_op_(VI_VB0_START_ADDRESS_FIRST_0) \
+_op_(VI_VB0_BASE_ADDRESS_FIRST_0) \
+_op_(VI_VB0_START_ADDRESS_U_0) \
+_op_(VI_VB0_BASE_ADDRESS_U_0) \
+_op_(VI_VB0_START_ADDRESS_V_0) \
+_op_(VI_VB0_BASE_ADDRESS_V_0) \
+_op_(VI_VB0_SCRATCH_ADDRESS_UV_0) \
+_op_(VI_FIRST_OUTPUT_FRAME_SIZE_0) \
+_op_(VI_VB0_COUNT_FIRST_0) \
+_op_(VI_VB0_SIZE_FIRST_0) \
+_op_(VI_VB0_BUFFER_STRIDE_FIRST_0) \
+_op_(VI_VB0_START_ADDRESS_SECOND_0) \
+_op_(VI_VB0_BASE_ADDRESS_SECOND_0) \
+_op_(VI_SECOND_OUTPUT_FRAME_SIZE_0) \
+_op_(VI_VB0_COUNT_SECOND_0) \
+_op_(VI_VB0_SIZE_SECOND_0) \
+_op_(VI_VB0_BUFFER_STRIDE_SECOND_0) \
+_op_(VI_H_LPF_CONTROL_0) \
+_op_(VI_H_DOWNSCALE_CONTROL_0) \
+_op_(VI_V_DOWNSCALE_CONTROL_0) \
+_op_(VI_CSC_Y_0) \
+_op_(VI_CSC_UV_R_0) \
+_op_(VI_CSC_UV_G_0) \
+_op_(VI_CSC_UV_B_0) \
+_op_(VI_CSC_ALPHA_0) \
+_op_(VI_HOST_VSYNC_0) \
+_op_(VI_COMMAND_0) \
+_op_(VI_HOST_FIFO_STATUS_0) \
+_op_(VI_INTERRUPT_MASK_0) \
+_op_(VI_INTERRUPT_TYPE_SELECT_0) \
+_op_(VI_INTERRUPT_POLARITY_SELECT_0) \
+_op_(VI_INTERRUPT_STATUS_0) \
+_op_(VI_VIP_INPUT_STATUS_0) \
+_op_(VI_VIDEO_BUFFER_STATUS_0) \
+_op_(VI_SYNC_OUTPUT_0) \
+_op_(VI_VVS_OUTPUT_DELAY_0) \
+_op_(VI_PWM_CONTROL_0) \
+_op_(VI_PWM_SELECT_PULSE_A_0) \
+_op_(VI_PWM_SELECT_PULSE_B_0) \
+_op_(VI_PWM_SELECT_PULSE_C_0) \
+_op_(VI_PWM_SELECT_PULSE_D_0) \
+_op_(VI_VI_DATA_INPUT_CONTROL_0) \
+_op_(VI_PIN_INPUT_ENABLE_0) \
+_op_(VI_PIN_OUTPUT_ENABLE_0) \
+_op_(VI_PIN_INVERSION_0) \
+_op_(VI_PIN_INPUT_DATA_0) \
+_op_(VI_PIN_OUTPUT_DATA_0) \
+_op_(VI_PIN_OUTPUT_SELECT_0) \
+_op_(VI_RAISE_VIP_BUFFER_FIRST_OUTPUT_0) \
+_op_(VI_RAISE_VIP_FRAME_FIRST_OUTPUT_0) \
+_op_(VI_RAISE_VIP_BUFFER_SECOND_OUTPUT_0) \
+_op_(VI_RAISE_VIP_FRAME_SECOND_OUTPUT_0) \
+_op_(VI_RAISE_HOST_FIRST_OUTPUT_0) \
+_op_(VI_RAISE_HOST_SECOND_OUTPUT_0) \
+_op_(VI_RAISE_EPP_0) \
+_op_(VI_CAMERA_CONTROL_0) \
+_op_(VI_VI_ENABLE_0) \
+_op_(VI_VI_ENABLE_2_0) \
+_op_(VI_VI_RAISE_0) \
+_op_(VI_Y_FIFO_WRITE_0) \
+_op_(VI_U_FIFO_WRITE_0) \
+_op_(VI_V_FIFO_WRITE_0) \
+_op_(VI_VI_MCCIF_FIFOCTRL_0) \
+_op_(VI_TIMEOUT_WCOAL_VI_0) \
+_op_(VI_MCCIF_VIRUV_HP_0) \
+_op_(VI_MCCIF_VIWSB_HP_0) \
+_op_(VI_MCCIF_VIWU_HP_0) \
+_op_(VI_MCCIF_VIWV_HP_0) \
+_op_(VI_MCCIF_VIWY_HP_0) \
+_op_(VI_CSI_PPA_RAISE_FRAME_START_0) \
+_op_(VI_CSI_PPA_RAISE_FRAME_END_0) \
+_op_(VI_CSI_PPB_RAISE_FRAME_START_0) \
+_op_(VI_CSI_PPB_RAISE_FRAME_END_0) \
+_op_(VI_CSI_PPA_H_ACTIVE_0) \
+_op_(VI_CSI_PPA_V_ACTIVE_0) \
+_op_(VI_CSI_PPB_H_ACTIVE_0) \
+_op_(VI_CSI_PPB_V_ACTIVE_0) \
+_op_(VI_ISP_H_ACTIVE_0) \
+_op_(VI_ISP_V_ACTIVE_0) \
+_op_(VI_STREAM_1_RESOURCE_DEFINE_0) \
+_op_(VI_STREAM_2_RESOURCE_DEFINE_0) \
+_op_(VI_RAISE_STREAM_1_DONE_0) \
+_op_(VI_RAISE_STREAM_2_DONE_0) \
+_op_(VI_TS_MODE_0) \
+_op_(VI_TS_CONTROL_0) \
+_op_(VI_TS_PACKET_COUNT_0) \
+_op_(VI_TS_ERROR_COUNT_0) \
+_op_(VI_TS_CPU_FLOW_CTL_0) \
+_op_(VI_VB0_CHROMA_BUFFER_STRIDE_FIRST_0) \
+_op_(VI_VB0_CHROMA_LINE_STRIDE_FIRST_0) \
+_op_(VI_EPP_LINES_PER_BUFFER_0) \
+_op_(VI_BUFFER_RELEASE_OUTPUT1_0) \
+_op_(VI_BUFFER_RELEASE_OUTPUT2_0) \
+_op_(VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT1_0) \
+_op_(VI_DEBUG_FLOW_CONTROL_COUNTER_OUTPUT2_0) \
+_op_(VI_TERMINATE_BW_FIRST_0) \
+_op_(VI_TERMINATE_BW_SECOND_0) \
+_op_(VI_VB0_FIRST_BUFFER_ADDR_MODE_0) \
+_op_(VI_VB0_SECOND_BUFFER_ADDR_MODE_0) \
+_op_(VI_RESERVE_0_0) \
+_op_(VI_RESERVE_1_0) \
+_op_(VI_RESERVE_2_0) \
+_op_(VI_RESERVE_3_0) \
+_op_(VI_RESERVE_4_0) \
+_op_(VI_MCCIF_VIRUV_HYST_0) \
+_op_(VI_MCCIF_VIWSB_HYST_0) \
+_op_(VI_MCCIF_VIWU_HYST_0) \
+_op_(VI_MCCIF_VIWV_HYST_0) \
+_op_(VI_MCCIF_VIWY_HYST_0) \
+_op_(CSI_VI_INPUT_STREAM_CONTROL_0) \
+_op_(CSI_HOST_INPUT_STREAM_CONTROL_0) \
+_op_(CSI_INPUT_STREAM_A_CONTROL_0) \
+_op_(CSI_PIXEL_STREAM_A_CONTROL0_0) \
+_op_(CSI_PIXEL_STREAM_A_CONTROL1_0) \
+_op_(CSI_PIXEL_STREAM_A_WORD_COUNT_0) \
+_op_(CSI_PIXEL_STREAM_A_GAP_0) \
+_op_(CSI_PIXEL_STREAM_PPA_COMMAND_0) \
+_op_(CSI_INPUT_STREAM_B_CONTROL_0) \
+_op_(CSI_PIXEL_STREAM_B_CONTROL0_0) \
+_op_(CSI_PIXEL_STREAM_B_CONTROL1_0) \
+_op_(CSI_PIXEL_STREAM_B_WORD_COUNT_0) \
+_op_(CSI_PIXEL_STREAM_B_GAP_0) \
+_op_(CSI_PIXEL_STREAM_PPB_COMMAND_0) \
+_op_(CSI_PHY_CIL_COMMAND_0) \
+_op_(CSI_PHY_CILA_CONTROL0_0) \
+_op_(CSI_PHY_CILB_CONTROL0_0) \
+_op_(CSI_CSI_PIXEL_PARSER_STATUS_0) \
+_op_(CSI_CSI_CIL_STATUS_0) \
+_op_(CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK_0) \
+_op_(CSI_CSI_CIL_INTERRUPT_MASK_0) \
+_op_(CSI_CSI_READONLY_STATUS_0) \
+_op_(CSI_ESCAPE_MODE_COMMAND_0) \
+_op_(CSI_ESCAPE_MODE_DATA_0) \
+_op_(CSI_CILA_PAD_CONFIG0_0) \
+_op_(CSI_CILA_PAD_CONFIG1_0) \
+_op_(CSI_CILB_PAD_CONFIG0_0) \
+_op_(CSI_CILB_PAD_CONFIG1_0) \
+_op_(CSI_CIL_PAD_CONFIG0_0) \
+_op_(CSI_CILA_MIPI_CAL_CONFIG_0) \
+_op_(CSI_CILB_MIPI_CAL_CONFIG_0) \
+_op_(CSI_CIL_MIPI_CAL_STATUS_0) \
+_op_(CSI_CLKEN_OVERRIDE_0) \
+_op_(CSI_DEBUG_CONTROL_0) \
+_op_(CSI_DEBUG_COUNTER_0_0) \
+_op_(CSI_DEBUG_COUNTER_1_0) \
+_op_(CSI_DEBUG_COUNTER_2_0) \
+_op_(CSI_PIXEL_STREAM_A_EXPECTED_FRAME_0) \
+_op_(CSI_PIXEL_STREAM_B_EXPECTED_FRAME_0) \
+_op_(CSI_DSI_MIPI_CAL_CONFIG_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_VI 0x00000000
+#define BASE_ADDRESS_CSI        0x00000200
+
+//
+// ARVI REGISTER BANKS
+//
+
+#define VI0_FIRST_REG 0x0000 // VI_OUT_1_INCR_SYNCPT_0
+#define VI0_LAST_REG 0x0002 // VI_OUT_1_INCR_SYNCPT_ERROR_0
+#define VI1_FIRST_REG 0x0008 // VI_OUT_2_INCR_SYNCPT_0
+#define VI1_LAST_REG 0x000a // VI_OUT_2_INCR_SYNCPT_ERROR_0
+#define VI2_FIRST_REG 0x0010 // VI_MISC_INCR_SYNCPT_0
+#define VI2_LAST_REG 0x0012 // VI_MISC_INCR_SYNCPT_ERROR_0
+#define VI3_FIRST_REG 0x0018 // VI_CONT_SYNCPT_OUT_1_0
+#define VI3_LAST_REG 0x009d // VI_MCCIF_VIWY_HYST_0
+#define CSI0_FIRST_REG 0x0200 // CSI_VI_INPUT_STREAM_CONTROL_0
+#define CSI0_LAST_REG 0x0200 // CSI_VI_INPUT_STREAM_CONTROL_0
+#define CSI1_FIRST_REG 0x0202 // CSI_HOST_INPUT_STREAM_CONTROL_0
+#define CSI1_LAST_REG 0x0202 // CSI_HOST_INPUT_STREAM_CONTROL_0
+#define CSI2_FIRST_REG 0x0204 // CSI_INPUT_STREAM_A_CONTROL_0
+#define CSI2_LAST_REG 0x0204 // CSI_INPUT_STREAM_A_CONTROL_0
+#define CSI3_FIRST_REG 0x0206 // CSI_PIXEL_STREAM_A_CONTROL0_0
+#define CSI3_LAST_REG 0x020a // CSI_PIXEL_STREAM_PPA_COMMAND_0
+#define CSI4_FIRST_REG 0x020f // CSI_INPUT_STREAM_B_CONTROL_0
+#define CSI4_LAST_REG 0x020f // CSI_INPUT_STREAM_B_CONTROL_0
+#define CSI5_FIRST_REG 0x0211 // CSI_PIXEL_STREAM_B_CONTROL0_0
+#define CSI5_LAST_REG 0x0215 // CSI_PIXEL_STREAM_PPB_COMMAND_0
+#define CSI6_FIRST_REG 0x021a // CSI_PHY_CIL_COMMAND_0
+#define CSI6_LAST_REG 0x021c // CSI_PHY_CILB_CONTROL0_0
+#define CSI7_FIRST_REG 0x021e // CSI_CSI_PIXEL_PARSER_STATUS_0
+#define CSI7_LAST_REG 0x0234 // CSI_DSI_MIPI_CAL_CONFIG_0
+
+#ifndef _MK_SHIFT_CONST
+  #define _MK_SHIFT_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_MASK_CONST
+  #define _MK_MASK_CONST(_constant_) _constant_
+#endif
+#ifndef _MK_ENUM_CONST
+  #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL)
+#endif
+#ifndef _MK_ADDR_CONST
+  #define _MK_ADDR_CONST(_constant_) _constant_
+#endif
+
+#endif // ifndef ___ARVI_H_INC_
diff --git a/arch/arm/mach-tegra/nv/include/ap20/dev_ap_pcie2_pads.h b/arch/arm/mach-tegra/nv/include/ap20/dev_ap_pcie2_pads.h
new file mode 100644
index 000000000000..d0a4907e72c6
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/dev_ap_pcie2_pads.h
@@ -0,0 +1,466 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef ___DEV_AP_PCIE2_PADS_H_INC_
+#define ___DEV_AP_PCIE2_PADS_H_INC_
+
+#define NV_PROJ__PCIE2_PADS                            0x000000BC:0x00000098 /* RW--D */
+#define NV_PROJ__PCIE2_PADS_CTL_SEL_0                         0x00000098 /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT                   31:0 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_DEFAULT     0xFFFFFFFF /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_NO_LANES    0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_LANES_31_0  0xFFFFFFFF /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_SEL_0_LANE_SELECT_MASK        0x0000001C /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_SEL_1                         0x0000009C /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT                   31:0 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT_DEFAULT     0xFFFFFFFF /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT_NO_LANES    0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_SEL_1_LANE_SELECT_LANES_63_32 0xFFFFFFFF /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1                             0x000000A0 /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_CTL_1_IDDQ_1L                            0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_IDDQ_1L_DEFAULT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P                         1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P_DEFAULT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P_PD               0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_1P_NOT_PD           0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P                    3:3 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P_DEFAULT     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P_ENABLE      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_CKBUFPD_OVRD_1P_DISABLE     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L                        5:4 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_DEFAULT         0x00000003 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_ACTIVE          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_PARTIAL         0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_SLUMBER         0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_SLEEP_1L_DISABLED        0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L                      6:6 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L_DEFAULT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L_ENABLE        0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_EN_1L_DISABLE       0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L                     7:7 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L_DEFAULT      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L_ENABLE       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_PWR_OVRD_1L_DISABLE      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L                        9:8 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_DEFAULT         0x00000003 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_ACTIVE          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_PARTIAL         0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_SLUMBER         0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_SLEEP_1L_DISABLED        0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L                    10:10 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L_DEFAULT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L_ENABLE        0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_DATA_EN_1L_DISABLE       0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L                   11:11 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L_DEFAULT      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L_ENABLE       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_PWR_OVRD_1L_DISABLE      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L                       13:12 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_DEFAULT          0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_PLL_05X          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_PLL_1X           0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RATE_1L_PLL_2X           0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L                       15:14 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_DEFAULT          0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_PLL_05X          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_PLL_1X           0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_RATE_1L_PLL_2X           0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_STAT_IDLE_1L                  16:16 /* R--VF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_STAT_IDLE_1L_IDLE        0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_RX_STAT_IDLE_1L_SIG_PRESENT 0x00000000 /* R---V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_STAT_PRESENT_1L               17:17 /* R--VF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_STAT_PRESENT_1L_RX_PRSNT 0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_STAT_PRESENT_1L_RX_ABSNT 0x00000000 /* R---V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS                       19:19 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS_DEFAULT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS_ENABLE           0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_RDET_GS_DISABLE          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P                      21:20 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_RD2REGOUT       0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_WR2REGOUT       0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_RD2RXOUT        0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NED_MODE_1P_WR2RXOUT        0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS                      22:22 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS_ENABLE          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NED_LOOP_GS_DISABLE         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS                      23:23 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS_ENABLE          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_NEA_LOOP_GS_DISABLE         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P                      26:24 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_CDR_CLK         0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_CDR_DATA        0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_IDLE_DET        0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_MODE_1P_RX_AMP          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS                      27:27 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS_ENABLE          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FEA_LOOP_GS_DISABLE         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS                     30:28 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_DEFAULT        0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_INVERITNG_17C  0x00000005 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_STATIC_01F     0x00000004 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_INVERITNG_333  0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_STATIC_155     0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_PRBS_27_1      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_TX_DATA_MODE_GS_NORMAL         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS                      31:31 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS_ENABLE          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_1_FED_LOOP_GS_DISABLE         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_2                             0x000000A4 /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_CTL_2_CDR_CNTL_1P                        7:0 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_2_CDR_CNTL_1P_DEFAULT         0x00000010 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_2_MISC_CNTL_1P                      11:8 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_2_MISC_CNTL_1P_DEFAULT        0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_2_TX_RDET_T_1P                     13:12 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_2_TX_RDET_T_1P_DEFAULT        0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P                     15:14 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_DEFAULT        0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_70_MVPPD       0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_120_MVPPD      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_2_RX_IDLE_T_1P_100_MVPPD      0x00000000 /* RW--V */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_TX_DIV_1L                       17:16 /* RWIVF */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_TX_DIV_1L_DEFAULT          0x00000000 /* RWI-V */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_TX_DIV_1L_NORMAL           0x00000000 /* RW--V */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_DIV_1L                       19:18 /* RWIVF */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_DIV_1L_DEFAULT          0x00000000 /* RWI-V */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_DIV_1L_NORMAL           0x00000000 /* RW--V */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_OUT_1L                   20:20 /* RWIVF */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_OUT_1L_DEFAULT      0x00000000 /* RWI-V */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_IN_1L                    21:21 /* R--VF */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_DIR_1L                   22:22 /* RWIVF */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_DIR_1L_DEFAULT      0x00000000 /* RWI-V */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_EN_1L                    23:23 /* RWIVF */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_TX_BYP_EN_1L_DEFAULT       0x00000000 /* RWI-V */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_OUT_1L                   24:24 /* RWIVF */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_OUT_1L_DEFAULT      0x00000000 /* RWI-V */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_IN_1L                    25:25 /* R--VF */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_DIR_1L                   26:26 /* RWIVF */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_DIR_1L_DEFAULT      0x00000000 /* RWI-V */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_EN_1L                    27:27 /* RWIVF */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_EN_1L_DEFAULT       0x00000000 /* RWI-V */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_MODE_1L                  28:28 /* RWIVF */
+#define  NV_PROJ__PCIE2_PADS_CTL_2_RX_BYP_MODE_1L_DEFAULT     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4                             0x000000A8 /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS                     0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS_DEFAULT      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS_BYPASS       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_RX_IDLE_BYP_GS_NORMAL       0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS                     1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS_DEFAULT      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS_BYPASS       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_RDET_BYP_GS_NORMAL       0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P                     6:4 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_DEFAULT      0x00000002 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_MIN          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_CENTERED     0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SEL_LOAD_1P_MAX          0x00000004 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS                         7:7 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS_DEFAULT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS_ENABLE           0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_SYNC_GS_DISABLE          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS                    8:8 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS_DEFAULT     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS_ENABLE      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_RX_CDR_RESET_GS_DISABLE     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS                   12:12 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS_DEFAULT      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS_ENABLE       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_CHK_EN_GS_DISABLE      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_ERROR_1L                    13:13 /* R--VF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_ERROR_1L_ERROR         0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_PRBS_ERROR_1L_NO_ERROR      0x00000000 /* R---V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS                      19:16 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS_ENABLE          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_TEST_GS_DISABLE         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_MODE_1P                      23:20 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_CDR_MODE_1P_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_TERM_1P                       24:24 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_TX_TERM_1P_DEFAULT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_RX_TERM_1P                       25:25 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_RX_TERM_1P_DEFAULT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_SPARE_IN_GS                      29:28 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_4_SPARE_IN_GS_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_4_SPARE_OUT_1L                     31:30 /* R--VF */
+#define NV_PROJ__PCIE2_PADS_CTL_5                             0x000000AC /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C                       5:0 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C_DEFAULT        0x00000020 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C_1150_MVPPD     0x00000026 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C_1000_MVPPD     0x00000020 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C__500_MVPPD     0x0000000C /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_AMP_R1_1C__200_MVPPD     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_CMADJ_R1_1C                    11:8 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_CMADJ_R1_1C_DEFAULT      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C                    16:12 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_DEFAULT       0x0000000E /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_DISABLE       0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_37DB          0x0000000E /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_R1_1C_60DB          0x00000014 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_PRE_R1_1C                19:17 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_5_TX_PEAK_PRE_R1_1C_DEFAULT   0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C                      30:28 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C_NO_EQ           0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_5_RX_EQ_R1_1C_MAX_EQ          0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6                             0x000000B0 /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C                       5:0 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C_DEFAULT        0x00000020 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C_1150_MVPPD     0x00000026 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C_1000_MVPPD     0x00000020 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C__500_MVPPD     0x0000000C /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_AMP_R2_1C__200_MVPPD     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_CMADJ_R2_1C                    11:8 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_CMADJ_R2_1C_DEFAULT      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C               16:12 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_DEFAULT  0x0000000E /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_DISABLE  0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_37DB     0x0000000E /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL1_1C_60DB     0x00000014 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL1_1C              19:17 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL1_1C_DEFAULT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C               24:20 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_DEFAULT  0x00000014 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_DISABLE  0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_37DB     0x0000000E /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_R2_SEL0_1C_60DB     0x00000014 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL0_1C              27:25 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_6_TX_PEAK_PRE_R2_SEL0_1C_DEFAULT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C                      30:28 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C_NO_EQ           0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_CTL_6_RX_EQ_R2_1C_MAX_EQ          0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_SEL                           0x000000B4 /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT                      31:0 /* RWIVF */
+#define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT_DEFAULT        0xFFFFFFFF /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT_NO_PLLS        0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_SEL_PLL_SELECT_PLLS_31_0      0xFFFFFFFF /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1                             0x000000B8 /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM                 0:0 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM_DEFAULT  0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM_ENABLED  0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_IDDQ_MODE_B4SM_DISABLED 0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM                       1:1 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM_DEFAULT        0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM_ASSERT         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_RST_B4SM_DEASSERT       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST                        2:2 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST_DEFAULT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST_HOLD            0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_RST_RELEASE         0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R                      4:4 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R_DEFAULT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R_DISABLED      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_R_ENABLED       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L                      5:5 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L_DEFAULT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L_DISABLED      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_L_ENABLED       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M                      6:6 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M_DEFAULT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M_INDEPENDENT   0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_M_SHARED        0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD                   7:7 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD_DEFAULT    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD_DISABLED   0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_CKBUFPD_OVRD_ENABLED    0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_LOCKDET                        8:8 /* R--VF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_LOCKDET_NOT_LOCKED      0x00000000 /* R---V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_LOCKDET_LOCKED          0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL                  14:12 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DEFAULT     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV10       0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV9        0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV8        0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV7        0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_SEL_DIV3        0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN                   15:15 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN_DEFAULT      0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN_DISABLED     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK_EN_ENABLED      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL                   17:16 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_DEFAULT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_INTERNAL_CML  0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_INTERNAL_CMOS 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_SEL_EXTERNAL      0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV                   19:18 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_DEFAULT      0x00000002 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_10X          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_20X          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_25X          0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLK_DIV_30X          0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL                 20:20 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL_DEFAULT    0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL_DIV10      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_SEL_DIV5       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN                  21:21 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN_DEFAULT     0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN_DISABLED    0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TXCLKREF_EN_ENABLED     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN                 22:22 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN_DEFAULT    0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN_DISABLED   0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_REFCLKBUF_EN_ENABLED    0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN                23:23 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN_DEFAULT   0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN_DISABLED  0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XDIGCLK4P5_EN_ENABLED   0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL                  26:24 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_DEFAULT     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_DIV10       0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_DIV5        0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_XDIGCLK     0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_REFCLK      0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_SEL_LFBCLK      0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN                   27:27 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN_DEFAULT      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN_DISABLED     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_TCLKOUT_EN_ENABLED      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100                 28:28 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100_DEFAULT    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100_DISABLED   0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_XREF_TERM100_ENABLED    0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON                       29:29 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON_DEFAULT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON_DISABLED         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_EMU_ON_ENABLED          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN                    31:31 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN_DEFAULT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN_DISABLED      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL1_PLL_BYPASS_EN_ENABLED       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2                             0x000000BC /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE                      4:0 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_DEFAULT       0x0000000E /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_MAX_R         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_NOMINAL_R     0x0000000E /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_CODE_MIN_R         0x0000001F /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS                    7:7 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS_DEFAULT     0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS_DISABLED    0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_BYPASS_ENABLED     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_VAL                      12:8 /* R--VF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_VAL_MAX_R          0x00000000 /* R---V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_VAL_MIN_R          0x0000001F /* R---V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET                   14:14 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET_DEFAULT      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET_DISABLED     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_RESET_ENABLED      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_DONE                    15:15 /* R--VF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_DONE_FALSE         0x00000000 /* R---V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_RCAL_DONE_TRUE          0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL                    17:16 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_DEFAULT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_NORMAL        0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_POS_COEFF     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_NEG_COEFF     0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_BGAP_CNTL_NORMAL_PLUS   0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL                      22:20 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_DEFAULT         0x00000004 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_15UA            0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_17P5UA          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_20UA            0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_22P5UA          0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_25UA            0x00000005 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_27P5UA          0x00000006 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_CP_CNTL_30UA            0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_MISC_CNTL                    27:24 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL2_PLL_MISC_CNTL_DEFAULT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3                             0x000000C0 /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ                         0:0 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ_DEFAULT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ_DISABLED         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_IDDQ_ENABLED          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST                          1:1 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST_DEFAULT           0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST_ASSERT            0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_RST_DEASSERT          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE                         4:4 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE_DEFAULT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE_PCIE             0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_MODE_DISPLAY          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_LOCKDET                      8:8 /* R--VF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_LOCKDET_NOT_LOCKED    0x00000000 /* R---V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_LOCKDET_LOCKED        0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL                26:24 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_DEFAULT   0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_DIV5      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_DIV10     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_REFCLK    0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_LFBCLK    0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_TXCLKREF  0x00000006 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_SEL_TKOUT_IN  0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN                 27:27 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN_DEFAULT    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN_DISABLED   0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_TCLKOUT_EN_ENABLED    0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN                  31:31 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN_DEFAULT     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN_DISABLED    0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL3_DPLL0_BYPASS_EN_ENABLED     0x00000001 /* RW--V */ 
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4                             0x000000C4 /* RW-4R */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ                         0:0 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ_DEFAULT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ_DISABLED         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_IDDQ_ENABLED          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST                          1:1 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST_DEFAULT           0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST_ASSERT            0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_RST_DEASSERT          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE                         4:4 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE_DEFAULT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE_PCIE             0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_MODE_DISPLAY          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_LOCKDET                      8:8 /* R--VF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_LOCKDET_NOT_LOCKED    0x00000000 /* R---V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_LOCKDET_LOCKED        0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL                26:24 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_DEFAULT   0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_DIV5      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_DIV10     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_REFCLK    0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_LFBCLK    0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_TXCLKREF  0x00000006 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_SEL_TKOUT_IN  0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN                 27:27 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN_DEFAULT    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN_DISABLED   0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_TCLKOUT_EN_ENABLED    0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN                  31:31 /* RWIUF */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN_DEFAULT     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN_DISABLED    0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_PADS_PLL_CTL4_DPLL1_BYPASS_EN_ENABLED     0x00000001 /* RW--V */
+
+#endif // ifndef ___DEV_AP_PCIE2_PADS_H_INC_
+
diff --git a/arch/arm/mach-tegra/nv/include/ap20/dev_ap_pcie2_root_port.h b/arch/arm/mach-tegra/nv/include/ap20/dev_ap_pcie2_root_port.h
new file mode 100644
index 000000000000..4f5e823383dd
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/dev_ap_pcie2_root_port.h
@@ -0,0 +1,2085 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef ___DEV_AP_PCIE2_ROOT_PORT_H_INC_
+#define ___DEV_AP_PCIE2_ROOT_PORT_H_INC_
+
+#define NV_PROJ__PCIE2_RP                                0x00000FFF:0x00000000 /* RW--D */
+#define NV_PROJ__PCIE2_RP_DEV_ID                                    0x00000000 /* R--4R */
+#define NV_PROJ__PCIE2_RP_DEV_ID_VENDOR_ID                                15:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEV_ID_VENDOR_ID_NVIDIA                   0x000010DE /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_ID_DEVICE_ID                               31:16 /* R--VF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL                                  0x00000004 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_IO_SPACE                                0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_IO_SPACE_DISABLED                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_IO_SPACE_ENABLED                 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_MEMORY_SPACE                            1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_MEMORY_SPACE_DISABLED            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_MEMORY_SPACE_ENABLED             0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_BUS_MASTER                              2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_BUS_MASTER_DISABLED              0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_BUS_MASTER_ENABLED               0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SPECIAL_CYCLE                           3:3 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SPECIAL_CYCLE_DISABLED           0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SPECIAL_CYCLE_ENABLED            0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_WRITE_AND_INVAL                         4:4 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_WRITE_AND_INVAL_DISABLED         0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_WRITE_AND_INVAL_ENABLED          0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_PALETTE_SNOOP                           5:5 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_PALETTE_SNOOP_DISABLED           0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_PALETTE_SNOOP_ENABLED            0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_PERR                                    6:6 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_PERR_DISABLED                    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_PERR_ENABLED                     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_STEP                                    7:7 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_STEP_DISABLED                    0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_STEP_ENABLED                     0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SERR                                    8:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SERR_DISABLED                    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SERR_ENABLED                     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_BACK2BACK                               9:9 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_BACK2BACK_DISABLED               0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_BACK2BACK_ENABLED                0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_DISABLE                          10:10 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_DISABLE_INIT                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_DISABLE_YES                 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_DISABLE_NO                  0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_STATUS                           19:19 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_STATUS_NOT_ACTIVE           0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_INTR_STATUS_ACTIVE               0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_CAPLIST                               20:20 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_CAPLIST_PRESENT                  0x00000001 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_CAPLIST_NOT_PRESENT              0x00000000 /* ----V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_66MHZ                                 21:21 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_66MHZ_INCAPABLE                  0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_66MHZ_CAPABLE                    0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_FAST_BACK2BACK                        23:23 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_FAST_BACK2BACK_INCAPABLE         0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_FAST_BACK2BACK_CAPABLE           0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_MASTER_DATA_PERR                      24:24 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_MASTER_DATA_PERR_NOT_ACTIVE      0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_MASTER_DATA_PERR_ACTIVE          0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_MASTER_DATA_PERR_SET             0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_DEVSEL_TIMING                         26:25 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_DEVSEL_TIMING_FAST               0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_DEVSEL_TIMING_MEDIUM             0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_DEVSEL_TIMING_SLOW               0x00000002 /* ----V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_TARGET                       27:27 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_TARGET_NO_ABORT         0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_TARGET_ABORT            0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_TARGET_SET              0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_TARGET                       28:28 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_TARGET_NO_ABORT         0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_TARGET_ABORT            0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_TARGET_SET              0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_MASTER                       29:29 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_MASTER_NO_ABORT         0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_MASTER_ABORT            0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_RECEIVED_MASTER_SET              0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_SERR                         30:30 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_SERR_NOT_ACTIVE         0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_SERR_ACTIVE             0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_SIGNALED_SERR_SET                0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_DETECTED_PERR                         31:31 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_DETECTED_PERR_NOT_ACTIVE         0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_DETECTED_PERR_ACTIVE             0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_DEV_CTRL_DETECTED_PERR_SET                0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_REV_CC                                    0x00000008 /* R--4R */
+#define NV_PROJ__PCIE2_RP_REV_CC_REVISION_ID                               7:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_REV_CC_CLASS_CODE                               31:8 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_REV_CC_CLASS_CODE_P2P                     0x00060400 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MISC_1                                    0x0000000C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_MISC_1_CACHE_LINE_SIZE                           7:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_MISC_1_CACHE_LINE_SIZE_0_BYTES            0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_MISC_1_PLATENCY_TIMER                          15:11 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MISC_1_PLATENCY_TIMER_0_CLOCKS            0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE0                            22:16 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE0_NON_BRIDGE            0x00000000 /* ----V */
+#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE0_P2P_BRIDGE            0x00000001 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE1                            23:23 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE1_SINGLEFUNC            0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MISC_1_HEADER_TYPE1_MULTIFUNC             0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_MISC_1_BIST                                    31:24 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MISC_1_BIST_ZERO                          0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_BAR_0                                     0x00000010 /* C--4R */
+#define NV_PROJ__PCIE2_RP_BAR_0_RESERVED                                  31:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_BAR_0_RESERVED_0                          0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_BAR_1                                     0x00000014 /* C--4R */
+#define NV_PROJ__PCIE2_RP_BAR_1_RESERVED                                  31:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_BAR_1_RESERVED_0                          0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_BN_LT                                     0x00000018 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_BN_LT_PRI_BUS_NUMBER                             7:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_BN_LT_PRI_BUS_NUMBER_0                    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_BN_LT_SEC_BUS_NUMBER                            15:8 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_BN_LT_SEC_BUS_NUMBER_0                    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_BN_LT_SEC_BUS_NUMBER_1                    0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_BN_LT_SEC_BUS_NUMBER_2                    0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_BN_LT_SEC_BUS_NUMBER_255                  0x000000ff /* RW--V */
+#define NV_PROJ__PCIE2_RP_BN_LT_SUB_BUS_NUMBER                           23:16 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_BN_LT_SUB_BUS_NUMBER_0                    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_BN_LT_SUB_BUS_NUMBER_1                    0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_BN_LT_SUB_BUS_NUMBER_2                    0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_BN_LT_SUB_BUS_NUMBER_255                  0x000000ff /* RW--V */
+#define NV_PROJ__PCIE2_RP_BN_LT_SLATENCY_TIMER                           31:27 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_BN_LT_SLATENCY_TIMER_0_CLOCKS             0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS                                  0x0000001C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_SUPPORT                         3:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_SUPPORT_16               0x00000000 /* ----V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_SUPPORT_32               0x00000001 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE                                 7:4 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_ADDRESS_0                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_ADDRESS_256              0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_ADDRESS_512              0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_BASE_ADDRESS_64K              0x0000000f /* RW--V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_SUPPORT                       11:8 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_SUPPORT_16              0x00000000 /* ----V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_SUPPORT_32              0x00000001 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT                              15:12 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_ADDRESS_0               0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_ADDRESS_256             0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_ADDRESS_512             0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_IO_LIMIT_ADDRESS_64K             0x0000000f /* RW--V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_66MHZ                                 21:21 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_66MHZ_INCAPABLE                  0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_66MHZ_CAPABLE                    0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_FAST_BACK2BACK                        23:23 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_FAST_BACK2BACK_INCAPABLE         0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_FAST_BACK2BACK_CAPABLE           0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_MASTER_DATA_PERR                      24:24 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_MASTER_DATA_PERR_NOT_ACTIVE      0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_MASTER_DATA_PERR_ACTIVE          0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_DEVSEL_TIMING                         26:25 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_DEVSEL_TIMING_FAST               0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_DEVSEL_TIMING_MEDIUM             0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_DEVSEL_TIMING_SLOW               0x00000002 /* ----V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_SIGNALED_TARGET                       27:27 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_SIGNALED_TARGET_NO_ABORT         0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_SIGNALED_TARGET_ABORT            0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_SIGNALED_TARGET_SET              0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_TARGET                       28:28 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_TARGET_NO_ABORT         0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_TARGET_ABORT            0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_TARGET_SET              0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_MASTER                       29:29 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_MASTER_NO_ABORT         0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_MASTER_ABORT            0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_MASTER_SET              0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_SERR                         30:30 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_SERR_NOT_ACTIVE         0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_SERR_ACTIVE             0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_RECEIVED_SERR_SET                0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_DETECTED_PERR                         31:31 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_DETECTED_PERR_NOT_ACTIVE         0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_DETECTED_PERR_ACTIVE             0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_IO_BL_SS_DETECTED_PERR_SET                0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_MEM_BL                                    0x00000020 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_BASE                                 15:4 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_BASE_ADDRESS_0                 0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_BASE_ADDRESS_1MEG              0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_BASE_ADDRESS_2MEG              0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_BASE_ADDRESS_4GIG              0x00000fff /* RW--V */
+#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_LIMIT                               31:20 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_LIMIT_ADDRESS_0                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_LIMIT_ADDRESS_1MEG             0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_LIMIT_ADDRESS_2MEG             0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MEM_BL_MEM_LIMIT_ADDRESS_4GIG             0x00000fff /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRE_BL                                    0x00000024 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRE_BL_B64BIT                                    3:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PRE_BL_B64BIT_YES                         0x00000001 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_BASE                        15:4 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_BASE_ADDRESS_0        0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_BASE_ADDRESS_1MEG     0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_BASE_ADDRESS_2MEG     0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_BASE_ADDRESS_4GIG     0x00000fff /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRE_BL_L64BIT                                  19:16 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PRE_BL_L64BIT_YES                         0x00000001 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_LIMIT                      31:20 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_LIMIT_ADDRESS_0       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_LIMIT_ADDRESS_1MEG    0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_LIMIT_ADDRESS_2MEG    0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRE_BL_PREFETCH_MEM_LIMIT_ADDRESS_4GIG    0x00000fff /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRE_BU32                                  0x00000028 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRE_BU32_BASE_UPPER_BITS                        31:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_PRE_BU32_BASE_UPPER_BITS_0                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRE_LU32                                  0x0000002C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRE_LU32_LIMIT_UPPER_BITS                       31:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_PRE_LU32_LIMIT_UPPER_BITS_0               0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_U16                                 0x00000030 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_IO_BL_U16_BASE_UPPER_BITS                       15:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_IO_BL_U16_BASE_UPPER_BITS_0               0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_IO_BL_U16_LIMIT_UPPER_BITS                     31:16 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_IO_BL_U16_LIMIT_UPPER_BITS_0              0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CAP_PTR                                   0x00000034 /* C--4R */
+#define NV_PROJ__PCIE2_RP_CAP_PTR_CAP_PTR                                  7:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_CAP_PTR_CAP_PTR_PM                        0x00000040 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_ROM_BA                                    0x00000038 /* C--4R */
+#define NV_PROJ__PCIE2_RP_ROM_BA_RESERVED                                 31:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_ROM_BA_RESERVED_0                         0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR                                  0x0000003C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_LINE                               7:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_LINE_IRQ0                   0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_LINE_IRQ1                   0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_LINE_IRQ15                  0x0000000F /* RW--V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_LINE_UNKNOWN                0x000000FF /* RW--V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN                               15:8 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN_NONE                    0x00000000 /* ----V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN_INTA                    0x00000001 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN_INTB                    0x00000002 /* ----V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN_INTC                    0x00000003 /* ----V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_INTR_PIN_INTD                    0x00000004 /* ----V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_PERR_RESP                             16:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_PERR_RESP_DISABLED               0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_PERR_RESP_ENABLED                0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_SERR_FORWARD                          17:17 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_SERR_FORWARD_DISABLED            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_SERR_FORWARD_ENABLED             0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_ISA_ADDRESS                           18:18 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_ISA_ADDRESS_DISABLED             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_ISA_ADDRESS_ENABLED              0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_ADDRESS                           19:19 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_ADDRESS_DISABLED             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_ADDRESS_ENABLED              0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_16BITIO                           20:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_16BITIO_DISABLED             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_VGA_16BITIO_ENABLED              0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_MABORT                                21:21 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_MABORT_DISABLED                  0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_MABORT_ENABLED                   0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_SB_RESET                              22:22 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_SB_RESET_DISABLED                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_SB_RESET_ENABLED                 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_FAST_B2B                              23:23 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_FAST_B2B_DISABLED                0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_FAST_B2B_ENABLED                 0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_PRIMARY_DIS_TIMER                     24:24 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_PRIMARY_DIS_TIMER_LONG           0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_PRIMARY_DIS_TIMER_SHORT          0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_SECONDARY_DIS_TIMER                   25:25 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_SECONDARY_DIS_TIMER_LONG         0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_SECONDARY_DIS_TIMER_SHORT        0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_STATUS                      26:26 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_STATUS_NOT_ACTIVE      0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_STATUS_ACTIVE          0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_SERR                        27:27 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_SERR_DISABLED          0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_INTR_BCR_DIS_TIMER_SERR_ENABLED           0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_SS_0                                      0x00000040 /* R--4R */
+#define NV_PROJ__PCIE2_RP_SS_0_NEXT_PTR                                   15:8 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_SS_0_NEXT_PTR_PM                                0x48 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_SS_0_CAP_ID                                      7:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_SS_0_CAP_ID_SS                                  0x0D /* C-I-V */
+#define NV_PROJ__PCIE2_RP_SS_1                                      0x00000044 /* R--4R */
+#define NV_PROJ__PCIE2_RP_SS_1_SSID                                      31:16 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_SS_1_SSID_INIT                                  0x0  /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SS_1_SSVID                                      15:0 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_SS_1_SSVID_INIT                               0x10DE /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PM_0                                      0x00000048 /* R--4R */
+#define NV_PROJ__PCIE2_RP_PM_0_PME_SUPPORT                               31:27 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_0_PME_SUPPORT_YES                      0x0000001F /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_0_PME_SUPPORT_NO                       0x00000000 /* ----V */
+#define NV_PROJ__PCIE2_RP_PM_0_D2_SUPPORT                                26:26 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_0_D2_SUPPORT_YES                       0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_PM_0_D2_SUPPORT_NO                        0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_0_D1_SUPPORT                                25:25 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_0_D1_SUPPORT_YES                       0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_PM_0_D1_SUPPORT_NO                        0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_0_AUX_CURRENT                               24:22 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_0_AUX_CURRENT_0                        0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_0_DEV_SPEC_INIT                             21:21 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_0_DEV_SPEC_INIT_NOT_NEEDED             0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_0_DEV_SPEC_INIT_NEEDED                 0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_PM_0_PME_CLOCK                                 19:19 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_0_PME_CLOCK_NOT_NEEDED                 0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_0_PME_CLOCK_NEEDED                     0x00000001 /* ----V */
+#define NV_PROJ__PCIE2_RP_PM_0_PCIPM_REV                                 18:16 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_0_PCIPM_REV_12                         0x00000003 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_0_PCIPM_REV_11                         0x00000002 /* ----V */
+#define NV_PROJ__PCIE2_RP_PM_0_NEXT_PTR                                   15:8 /* R--VF */
+#define NV_PROJ__PCIE2_RP_PM_0_CAP_ID                                      7:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_0_CAP_ID_PM                            0x00000001 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_1                                      0x0000004C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA                                  31:24 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA_UNS                         0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_BPCC                                  23:23 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_BPCC_UNS                         0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_B2B3                                  22:22 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_B2B3_UNS                         0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_STATUS                                15:15 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_STATUS_NOT_ACTIVE                0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_STATUS_ACTIVE                    0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_STATUS_SET                       0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA_SCALE                            14:13 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA_SCALE_UNS                   0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA_SEL                               12:9 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_DATA_SEL_UNS                     0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PM_1_PME                                         8:8 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_DISABLE                          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PM_1_PME_ENABLE                           0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PM_1_PWR_STATE                                   1:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PM_1_PWR_STATE_D0                         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PM_1_PWR_STATE_D1                         0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PM_1_PWR_STATE_D2                         0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PM_1_PWR_STATE_D3HOT                      0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL                                    0x00000050 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_RSVD                                    31:24 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_RSVD_0                             0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_64BIT_CAP                               23:23 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_64BIT_CAP_TRUE                     0x00000001 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_EN                                 22:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_EN_CODE0                      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_EN_CODE2                      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_EN_CODE4                      0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_EN_CODE8                      0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_CAP                                19:17 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_MULT_CAP_CODE2                     0x00000001 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_MSI                                     16:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_MSI_DISABLE                        0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_MSI_ENABLE                         0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_NEXT_PTR                                 15:8 /* R--VF */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_NEXT_PTR_MSIMAP                    0x00000060 /* R---V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_NEXT_PTR_PCIEXP                    0x00000080 /* R---V */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_CAP_ID                                    7:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MSI_CTRL_CAP_ID_MSI                         0x00000005 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MSI_LOW_ADDR                                 0x00000054 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_MSI_LOW_ADDR_DWORD                                 31:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_MSI_LOW_ADDR_DWORD_0                         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MSI_LOW_ADDR_RSVD                                   1:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MSI_LOW_ADDR_RSVD_0                          0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MSI_UPPER_ADDR                              0x00000058 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_MSI_UPPER_ADDR_DWORD                              31:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_MSI_UPPER_ADDR_DWORD_0                      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MSI_DATA                                    0x0000005C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_MSI_DATA_RSVD                                    31:16 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MSI_DATA_RSVD_0                             0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MSI_DATA_NON_RSVD                                 15:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_MSI_DATA_NON_RSVD_0                         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MSIMAP_0                                    0x00000060 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_ID                                    7:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_ID_LDT                         0x00000008 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_PTR                                  15:8 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_PTR_PCIEXP                     0x00000080 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MSIMAP_0_XLATE_ENABLE                            16:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_MSIMAP_0_XLATE_ENABLE_DEFAULT               0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_TYPE                                31:27 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_MSIMAP_0_CAP_TYPE_MSI                       0x00000015 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_MSIMAP_1                                    0x00000064 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_MSIMAP_1_ADDRESS_LOWER                           31:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_MSIMAP_1_ADDRESS_LOWER_DEFAULT              0x00000FEE /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MSIMAP_2                                    0x00000068 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_MSIMAP_2_ADDRESS_UPPER                            31:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_MSIMAP_2_ADDRESS_UPPER_DEFAULT              0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY                               0x00000080 /* R--4R */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID                   7:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_LIST_CAPABILITY_ID_INIT       0x00000010 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR            15:8 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_LIST_NEXT_CAPABILITY_PTR_INIT 0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_VERSION                            19:16 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_VERSION_INIT                  0x00000002 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_VERSION_1                     0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_VERSION_2                     0x00000002 /* R---V */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE                   23:20 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_DEVICE_PORT_TYPE_INIT         0x00000004 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED                   24:24 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_SLOT_IMPLEMENTED_INIT         0x00000001 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER           29:25 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_PCI_EXPRESS_CAPABILITY_INTERRUPT_MESSAGE_NUMBER_ZERO 0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY                         		  0x00000084 /* R--4R */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE                       	 2:0 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_INIT   		  0x00000001 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED    	         4:3 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED_INIT	  0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE        	         5:5 /* R--VF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ENDPOINT_L0S_ACCEPTABLE_LATENCY              8:6 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ENDPOINT_L0S_ACCEPTABLE_LATENCY_INIT  0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ENDPOINT_L1_ACCEPTABLE_LATENCY              11:9 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ENDPOINT_L1_ACCEPTABLE_LATENCY_INIT   0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ATTENTION_BUTTON_PRESENT                   12:12 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ATTENTION_BUTTON_PRESENT_INIT         0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ATTENTION_INDICATOR_PRESENT  	       13:13 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ATTENTION_INDICATOR_PRESENT_INIT      0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_POWER_INDICATOR_PRESENT      	       14:14 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_POWER_INDICATOR_PRESENT_INIT          0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING                   15:15 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING_INIT                0x1 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE            25:18 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE_INIT  0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE            27:26 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE_INIT  0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS                                    0x00000088 /* RWI4R */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE               0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE_INIT   0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE          1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE_INIT     0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE              2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE_INIT  0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE               3:3 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE_INIT   0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING                   4:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT       0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE                          7:5 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_INIT              0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE                 8:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE                  9:9 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE_INIT      0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE               10:10 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE_INIT     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP                         11:11 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP_INIT               0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE                   14:12 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE_INIT         0x00000002 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED                     16:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_INIT           0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_SET            0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED                17:17 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_INIT      0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_SET       0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED                    18:18 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_INIT          0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_SET           0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED                 19:19 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_INIT       0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_SET        0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED                      20:20 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED_INIT            0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING                    21:21 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING_INIT          0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LINK_CAPABILITIES                                     0x0000008C /* R--4R */
+#define NV_PROJ__PCIE2_RP_LINK_CAPABILITIES_LINKCAP                                   31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS                                        0x00000090 /* RWI4R */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL                  1:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_INIT      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY                      3:3 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_INIT          0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_LINK_DISABLE                                  4:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_LINK_DISABLE_INIT                      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_RETRAIN_LINK                                  5:5 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_RETRAIN_LINK_INIT                      0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION                    6:6 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION_INIT        0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_EXTENDED_SYNCH                                7:7 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_EXTENDED_SYNCH_INIT                    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_CLOCK_PM                                      8:8 /* C--VF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_CLOCK_PM_DEFAULT                       0x00000000 /* C---V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_HW_AUTO_WIDTH_DISABLE                         9:9 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_HW_AUTO_WIDTH_DISABLE_DEFAULT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT_INT_EN                        10:10 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT_INT_EN_INIT              0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH_INT_EN                       11:11 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH_INT_EN_INIT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_LINKSTAT                                    29:16 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT                               30:30 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT_TRUE                            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT_FALSE                           0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_BW_MANAGEMENT_SET                             0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH                              31:31 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH_TRUE                           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH_FALSE                          0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_AUTO_BANDWIDTH_SET                            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES                                                0x00000094 /* R--4R */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_ATTENTION_BUTTON_PRESENT                              0:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_POWER_CONTROLLER_PRESENT                              1:1 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_MRL_SENSOR_PRESENT                                    2:2 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_ATTENTION_INDICATOR_PRESENT                           3:3 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_POWER_INDICATOR_PRESENT                               4:4 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_HOT_PLUG_SURPRISE                                     5:5 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_HOT_PLUG_CAPABLE                                      6:6 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_VALUE                               14:7 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_SLOT_POWER_LIMIT_SCALE                              16:15 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_ELECTROMECHANICAL_INTERLOCK_PRESENT                 17:17 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_NO_CMD_COMPLETED_SUPPORT                            18:18 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_PHYSICAL_SLOT_NUMBER                                31:19 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS                                        0x00000098 /* RWI4R */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE                    0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_ENABLE_INIT        0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE                   1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_ENABLE_INIT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE                     2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_ENABLE_INIT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE                3:3 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_ENABLE_INIT    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE            4:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INTERRUPT_ENABLE_INIT       0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE                     5:5 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HOT_PLUG_INTERRUPT_ENABLE_INIT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL                        7:6 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_INDICATOR_CONTROL_INIT            0x00000003 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL                       9:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_INDICATOR_CONTROL_INIT           0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL                    10:10 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_CONTROLLER_CONTROL_INIT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL         11:11 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_CONTROL_INIT 0x000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_DL_LAYER_STATE_CHANGED_ENABLE               12:12 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_DL_LAYER_STATE_CHANGED_ENABLE_INIT     0x00000000 /* RWI-V */       
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED                         16:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_INIT               0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ATTN_BUTTON_PRESSED_SET                0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED                        17:17 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_INIT              0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_POWER_FAULT_DETECTED_SET               0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED                          18:18 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_INIT                0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_CHANGED_SET                 0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED                     19:19 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_INIT           0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_CHANGED_SET            0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_COMMAND_COMPLETED                           20:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_INIT                 0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_COMMAND_COMPLETED_SET                  0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE                            21:21 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_MRL_SENSOR_STATE_INIT                  0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE                       22:22 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_PRESENCE_DETECT_STATE_YES              0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATE           23:23 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_ELECTROMECHANICAL_INTERLOCK_STATE_YES  0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_DL_LAYER_STATE_CHANGED                      24:24 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_DL_LAYER_STATE_CHANGED_INIT           0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_DL_LAYER_STATE_CHANGED_SET            0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RCR                                       0x0000009C /* RWI4R */
+#define NV_PROJ__PCIE2_RP_RCR_SERR_COR                                     0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_RCR_SERR_COR_DIS                          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RCR_SERR_NONFAT                                  1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_RCR_SERR_NONFAT_DIS                       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RCR_SERR_FAT                                     2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_RCR_SERR_FAT_DIS                          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RCR_PME_INT                                      3:3 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_RCR_PME_INT_DIS                           0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RSR                                       0x000000A0 /* RWI4R */
+#define NV_PROJ__PCIE2_RP_RSR_REQID                                       15:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_RSR_PMESTAT                                    16:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_RSR_PMESTAT_NOT_ACTIVE                    0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RSR_PMESTAT_ACTIVE                        0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_RSR_PMESTAT_SET                           0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RSR_PMEPEND                                    17:17 /* R--VF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2                      0x000000A4 /* C-I4R */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_CPL_TO_RANGES_SUP           3:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_CPL_TO_RANGES_SUP_0  0x00000003 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_CPL_TO_DIS_SUP              4:4 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_CPL_TO_DIS_SUP_0     0x00000001 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_RESERVED                   31:5 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CAPABILITIES_2_RESERVED_0           0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2                                    0x000000A8 /* RWI4R */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE                              3:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE_RANGE_A_LO            0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE_RANGE_A_HI            0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE_RANGE_B_LO            0x00000005 /* RW--V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE_RANGE_B_HI            0x00000006 /* RW--V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_VALUE_DEFAULT               0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_DISABLE                            4:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_CPL_TO_DISABLE_DEFAULT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_RESERVED                                 31:5 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_DEVICE_CONTROL_STATUS_2_RESERVED_0                         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CAPABILITIES_2                     0x000000AC /* C--4R */
+#define NV_PROJ__PCIE2_RP_LINK_CAPABILITIES_2_BITS                      31:0 /* C--VF */
+#define NV_PROJ__PCIE2_RP_LINK_CAPABILITIES_2_BITS_0              0x00000000 /* C---V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2				           0x000000B0 /* RWI4R */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED                         3:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_GEN2_DIS         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_2P5              0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_5P0              0x00000002 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE                          4:4 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE_INIT              0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE                     5:5 /* C--VF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE_INIT         0x00000000 /* C---V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_SELECTABLE_DEEMPHASIS                     6:6 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN                           9:7 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN_INIT               0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_ENTER_MODIFIED_COMPLIANCE	        10:10 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_ENTER_MODIFIED_COMPLIANCE_INIT     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS                          11:11 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS_INIT                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_COMPLIANCE_DEEMPHASIS                   12:12 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_COMPLIANCE_DEEMPHASIS_INIT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_RESERVED_CONTROL                        15:13 /* C--VF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_RESERVED_CONTROL_DEFAULT           0x00000000 /* C---V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_CURRENT_DEEMPHASIS_LEVEL                16:16 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_CURRENT_DEEMPHASIS_LEVEL_3P5       0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_CURRENT_DEEMPHASIS_LEVEL_6         0x00000000 /* R---V */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_RESERVED_STATUS                         31:17 /* C--VF */
+#define NV_PROJ__PCIE2_RP_LINK_CONTROL_STATUS_2_RESERVED_STATUS_DEFAULT            0x00000000 /* C---V */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_2                     0x000000B4 /* C--4R */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_2_BITS                      31:0 /* C--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CAPABILITIES_2_BITS_0              0x00000000 /* C---V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_2	               0x000000B8 /* C--4R */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_2_BITS                 31:0 /* C--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_2_BITS_0	       0x00000000 /* C---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP                                   0x00000100 /* R--4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ID                                      15:0 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ID_AER                                0x0001 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_VERSION                                19:16 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_VERSION_1                                0x1 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_NEXT_PTR                               31:20 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_NEXT_PTR_NONE                          0x000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR                             0x00000104 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_TRAINING_ERR                       0:0 /* C--VF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_TRAINING_ERR_DEFAULT               0x0 /* C---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_DLINK_PROTO_ERR                    4:4 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_DLINK_PROTO_ERR_FALSE              0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_DLINK_PROTO_ERR_TRUE               0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_DLINK_PROTO_ERR_CLEAR              0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_POS_TLP                          12:12 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_POS_TLP_FALSE                      0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_POS_TLP_TRUE                       0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_POS_TLP_CLEAR                      0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_FC_PROTO_ERR                     13:13 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_FC_PROTO_ERR_DEFAULT               0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_FC_PROTO_ERR_TRUE                  0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_FC_PROTO_ERR_CLEAR                 0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_TO                          14:14 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_TO_FALSE                      0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_TO_TRUE                       0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_TO_CLEAR                      0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_ABORT                       15:15 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_ABORT_FALSE                   0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_ABORT_TRUE                    0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_COMP_ABORT_CLEAR                   0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNEXP_COMP                       16:16 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNEXP_COMP_FALSE                   0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNEXP_COMP_TRUE                    0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNEXP_COMP_CLEAR                   0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_RCV_OVFL                         17:17 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_RCV_OVFL_FALSE                     0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_RCV_OVFL_TRUE                      0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_RCV_OVFL_CLEAR                     0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MF_TLP                           18:18 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MF_TLP_FALSE                       0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MF_TLP_TRUE                        0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MF_TLP_CLEAR                       0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_ECRC_ERR                         19:19 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_ECRC_ERR_FALSE                     0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_ECRC_ERR_TRUE                      0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_ECRC_ERR_CLEAR                     0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNSUP_REQ_ERR                    20:20 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNSUP_REQ_ERR_FALSE                0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNSUP_REQ_ERR_TRUE                 0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_UNSUP_REQ_ERR_CLEAR                0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK                          0x00000108 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_TRAINING_ERR                     0:0 /* C--VF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_TRAINING_ERR_DEFAULT            0x0 /* C---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_DLINK_PROTO_ERR                 4:4 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_DLINK_PROTO_ERR_NOT_MASKED      0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_DLINK_PROTO_ERR_MASKED          0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_POS_TLP                       12:12 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_POS_TLP_NOT_MASKED              0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_POS_TLP_MASKED                  0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_FC_PROTO_ERR                  13:13 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_FC_PROTO_ERR_NOT_MASKED         0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_FC_PROTO_ERR_MASKED             0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_TO                       14:14 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_TO_NOT_MASKED              0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_TO_MASKED                  0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_ABORT                    15:15 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_ABORT_NOT_MASKED           0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_COMP_ABORT_MASKED               0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNEXP_COMP                    16:16 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNEXP_COMP_NOT_MASKED           0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNEXP_COMP_MASKED               0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_RCV_OVFL                      17:17 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_RCV_OVFL_NOT_MASKED             0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_RCV_OVFL_MASKED                 0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_MF_TLP                        18:18 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_MF_TLP_NOT_MASKED               0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_MF_TLP_MASKED                   0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_ECRC_ERR                      19:19 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_ECRC_ERR_NOT_MASKED             0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_ECRC_ERR_MASKED                 0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNSUP_REQ_ERR                 20:20 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNSUP_REQ_ERR_NOT_MASKED        0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_MK_UNSUP_REQ_ERR_MASKED            0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR                        0x0000010C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_TRAINING_ERR                  0:0 /* C--VF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_TRAINING_ERR_NON_FATAL        0x0 /* ----V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_TRAINING_ERR_FATAL            0x1 /* C---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_DLINK_PROTO_ERR               4:4 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_DLINK_PROTO_ERR_NON_FATAL     0x0 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_DLINK_PROTO_ERR_FATAL         0x1 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_POS_TLP                     12:12 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_POS_TLP_NON_FATAL             0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_POS_TLP_FATAL                 0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_FC_PROTO_ERR                13:13 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_FC_PROTO_ERR_NON_FATAL        0x0 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_FC_PROTO_ERR_FATAL            0x1 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_TO                     14:14 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_TO_NON_FATAL             0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_TO_FATAL                 0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_ABORT                  15:15 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_ABORT_NON_FATAL          0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_COMP_ABORT_FATAL              0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNEXP_COMP                  16:16 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNEXP_COMP_NON_FATAL          0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNEXP_COMP_FATAL              0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_RCV_OVFL                    17:17 /* RWCVF */  
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_RCV_OVFL_NON_FATAL            0x0 /* RW--V */  
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_RCV_OVFL_FATAL                0x1 /* RWI-V */  
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_MF_TLP                      18:18 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_MF_TLP_NON_FATAL              0x0 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_MF_TLP_FATAL                  0x1 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_ECRC_ERR                    19:19 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_ECRC_ERR_NON_FATAL            0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_ECRC_ERR_FATAL                0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNSUP_REQ_ERR               20:20 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNSUP_REQ_ERR_NON_FATAL       0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_UCERR_SEVR_UNSUP_REQ_ERR_FATAL           0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR                              0x00000110 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RCV_ERR                             0:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RCV_ERR_FALSE                       0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RCV_ERR_TRUE                        0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RCV_ERR_CLEAR                       0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_TLP                             6:6 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_TLP_FALSE                       0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_TLP_TRUE                        0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_TLP_CLEAR                       0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_DLLP                            7:7 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_DLLP_FALSE                      0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_DLLP_TRUE                       0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_BAD_DLLP_CLEAR                      0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_RLOV                           8:8 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_RLOV_FALSE                     0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_RLOV_TRUE                      0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_RLOV_CLEAR                     0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_TO                           12:12 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_TO_FALSE                       0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_TO_TRUE                        0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_RPLY_TO_CLEAR                       0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_ADVISORY_NF                       13:13 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_ADVISORY_NF_FALSE                   0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_ADVISORY_NF_TRUE                    0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_ADVISORY_NF_CLEAR                   0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK                           0x00000114 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RCV_ERR                          0:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RCV_ERR_NOT_MASKED               0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RCV_ERR_MASKED                   0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_TLP                          6:6 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_TLP_NOT_MASKED               0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_TLP_MASKED                   0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_DLLP                         7:7 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_DLLP_NOT_MASKED              0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_BAD_DLLP_MASKED                  0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_RLOV                        8:8 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_RLOV_NOT_MASKED             0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_RLOV_MASKED                 0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_TO                        12:12 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_TO_NOT_MASKED               0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_RPLY_TO_MASKED                   0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_ADVISORY_NF                    13:13 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_ADVISORY_NF_NOT_MASKED           0x0 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_CERR_MK_ADVISORY_NF_MASKED               0x1 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL                  0x00000118 /* R--4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ERR_PTR                 4:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_GEN_CAP            5:5 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_GEN_CAP_TRUE       0x1 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_GEN_EN             6:6 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_GEN_EN_FALSE       0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_GEN_EN_TRUE        0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_CHK_CAP            7:7 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_CHK_CAP_TRUE       0x1 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_CHK_EN             8:8 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_CHK_EN_FALSE       0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ADV_ERR_CAP_CNTL_ECRC_CHK_EN_TRUE        0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW0                       0x0000011C /* R--4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW0_0                           31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW1                       0x00000120 /* R--4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW1_1                           31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW2                       0x00000124 /* R--4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW2_2                           31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW3                       0x00000128 /* R--4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_HDR_LOG_DW3_3                           31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD                           0x0000012C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_COR_ERR_RPT_EN                   0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_COR_ERR_RPT_EN_FALSE             0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_COR_ERR_RPT_EN_TRUE              0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_NONFATAL_ERR_RPT_EN              1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_NONFATAL_ERR_RPT_EN_FALSE        0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_NONFATAL_ERR_RPT_EN_TRUE         0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_FATAL_ERR_RPT_EN                 2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_FATAL_ERR_RPT_EN_FALSE           0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_CMD_FATAL_ERR_RPT_EN_TRUE            0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS                           0x00000130 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_COR_RCVD                         0:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_COR_RCVD_FALSE                   0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_COR_RCVD_TRUE                    0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_COR_RCVD_CLEAR                   0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_COR_RCVD                    1:1 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_COR_RCVD_FALSE              0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_COR_RCVD_TRUE               0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_COR_RCVD_CLEAR              0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_UNCOR_RCVD                       2:2 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_UNCOR_RCVD_FALSE                 0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_UNCOR_RCVD_TRUE                  0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_UNCOR_RCVD_CLEAR                 0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_UNCOR_RCVD                  3:3 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_UNCOR_RCVD_FALSE            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_UNCOR_RCVD_TRUE             0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_MULT_UNCOR_RCVD_CLEAR            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FIRST_FATAL_RCVD                 4:4 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FIRST_FATAL_RCVD_FALSE           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FIRST_FATAL_RCVD_TRUE            0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FIRST_FATAL_RCVD_CLEAR           0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_NONFATAL_RCVD                    5:5 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_NONFATAL_RCVD_FALSE              0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_NONFATAL_RCVD_TRUE               0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_NONFATAL_RCVD_CLEAR              0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FATAL_RCVD                       6:6 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FATAL_RCVD_FALSE                 0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FATAL_RCVD_TRUE                  0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_FATAL_RCVD_CLEAR                 0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_STS_ADV_ERR_INTR_MSG_NUM           31:27 /* R--VF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_ID                            0x00000134 /* R--4R */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_ID_ERR_COR                          15:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_ID_ERR_COR_DEFAULT                0x0000 /* R---V */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_ID_ERR_UNCOR                       31:16 /* R--VF */
+#define NV_PROJ__PCIE2_RP_ERPTCAP_ERR_ID_ERR_UNCOR_DEFAULT              0x0000 /* R---V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0                                      0x00000494 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_DL_TIMERS_DISABLE                      0:0 /* RWIVF */ 
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_DL_TIMERS_DISABLE_INIT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_UPDATE_FC_THRESHOLD                    9:1 /* RWIVF */ 
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_UPDATE_FC_THRESHOLD_INIT        0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_ACK_TIMER_LIMIT                      18:10 /* RWIVF */ 
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_ACK_TIMER_LIMIT_INIT            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_REPLAY_TIMER_LIMIT                   29:19 /* RWIVF */ 
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DL_0_GEN2_REPLAY_TIMER_LIMIT_INIT         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_DBG0                                       0x00000D00 /* RWC4R */
+#define NV_PROJ__PCIE2_RP_DBG0_CTL                                         31:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_DBG0_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DBG1                                       0x00000D04 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_DBG1_CTL                                         31:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_DBG1_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DBG2                                       0x00000D08 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_DBG2_CTL                                         31:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_DBG2_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DBG3                                       0x00000D0C /* RWC4R */
+#define NV_PROJ__PCIE2_RP_DBG3_CTL                                         31:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_DBG3_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DBG4                                       0x00000D10 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_DBG4_CTL                                         31:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_DBG4_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DBG5                                       0x00000D14 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_DBG5_CTL                                         29:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_DBG5_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DBG5_CG_EN                                      30:30 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_DBG5_CG_EN_INIT                                   0x0 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DBG5_LOW_POWER_MODE                             31:31 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_DBG5_LOW_POWER_MODE_INIT                          0x1 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_DBG_RD_BACK_LO                             0x00000D18 /* R--4R */
+#define NV_PROJ__PCIE2_RP_DBG_RD_BACK_LO_VALUE                             31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_DBG_RD_BACK_HI                             0x00000D1C /* R--4R */
+#define NV_PROJ__PCIE2_RP_DBG_RD_BACK_HI_VALUE                             31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LANE_DBG0                                       0x00000D20 /* RWC4R */
+#define NV_PROJ__PCIE2_RP_LANE_DBG0_CTL                                         31:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LANE_DBG0_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LANE_DBG1                                       0x00000D24 /* RWC4R */
+#define NV_PROJ__PCIE2_RP_LANE_DBG1_CTL                                         31:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LANE_DBG1_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LANE_DBG2                                       0x00000D28 /* RWC4R */
+#define NV_PROJ__PCIE2_RP_LANE_DBG2_CTL                                         31:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LANE_DBG2_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LANE_DBG3                                       0x00000D2C /* RWC4R */
+#define NV_PROJ__PCIE2_RP_LANE_DBG3_CTL                                         31:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LANE_DBG3_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LANE_DBG4                                       0x00000D30 /* RWC4R */
+#define NV_PROJ__PCIE2_RP_LANE_DBG4_CTL                                         31:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LANE_DBG4_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LANE_DBG5                                       0x00000D34 /* RWC4R */
+#define NV_PROJ__PCIE2_RP_LANE_DBG5_CTL                                         29:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LANE_DBG5_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LANE_DBG5_CG_EN                                      30:30 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LANE_DBG5_CG_EN_INIT                                   0x0 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LANE_DBG5_LOW_POWER_MODE                             31:31 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LANE_DBG5_LOW_POWER_MODE_INIT                          0x1 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LANE_DBG_RD_BACK_LO                             0x00000D38 /* R--4R */    
+#define NV_PROJ__PCIE2_RP_LANE_DBG_RD_BACK_LO_VALUE	                            31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LANE_DBG_RD_BACK_HI                             0x00000D3C /* R--4R */    
+#define NV_PROJ__PCIE2_RP_LANE_DBG_RD_BACK_HI_VALUE                             31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LINK_DBG0                                       0x00000D40 /* RWC4R */
+#define NV_PROJ__PCIE2_RP_LINK_DBG0_CTL                                         31:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_DBG0_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LINK_DBG1                                       0x00000D44 /* RWC4R */
+#define NV_PROJ__PCIE2_RP_LINK_DBG1_CTL                                         29:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_DBG1_CTL_INIT                              0x00000000 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LINK_DBG1_CG_EN                                      30:30 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_DBG1_CG_EN_INIT                                   0x0 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LINK_DBG1_LOW_POWER_MODE                             31:31 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LINK_DBG1_LOW_POWER_MODE_INIT                          0x1 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_LINK_DBG_RD_BACK_LO                             0x00000D48 /* R--4R */    
+#define NV_PROJ__PCIE2_RP_LINK_DBG_RD_BACK_LO_VALUE                             31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LINK_DBG_RD_BACK_HI                             0x00000D4C /* R--4R */    
+#define NV_PROJ__PCIE2_RP_LINK_DBG_RD_BACK_HI_VALUE                             31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_RXL_DBG_RD_BACK                                0x00000D50 /* R--4R */
+#define NV_PROJ__PCIE2_RP_RXL_DBG_RD_BACK_VALUE				       31:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA                                       0x00000D54 /* RWC4R */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFI2UBFI                                     0:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFI2UBFI_INIT                         0x00000001 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFIRSP                                       1:1 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFIRSP_INIT                           0x00000001 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFIREQ                                       2:2 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_DFIREQ_INIT                           0x00000001 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_PCA                                          3:3 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_PCA_INIT                              0x00000001 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_UBFI2DFI_NTT                                 4:4 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_UBFI2DFI_NTT_INIT                     0x00000001 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_CMDQ2UFARB                                   5:5 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_CMDQ2UFARB_INIT                       0x00000001 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_TXBA2DFI_WR                                  6:6 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_TXBA2DFI_WR_INIT                      0x00000001 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_UBFI2DFI_P2P                                 7:7 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_UBFI2DFI_P2P_INIT                     0x00000001 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_UFA2WRR_PWTOP                                8:8 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PIPE_CYA_UFA2WRR_PWTOP_INIT                    0x00000001 /* RWC-V */
+#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT	       			   0x00000E00 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_NP				  7:0 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_NP_INIT				  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_PW                                15:8 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_PW_INIT                            0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_CPL                              23:16 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_RX_HDR_LIMIT_CPL_INIT                           0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT				   0x00000E04 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_NP				  7:0 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_NP_INIT				  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_PW                               19:8 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_PW_INIT                           0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_CPL                             27:20 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_RX_DATA_LIMIT_CPL_INIT                          0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT				   0x00000E08 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_NP				  7:0 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_NP_INIT				  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_PW                                15:8 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_PW_INIT                            0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_CPL                              23:16 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_CPL_INIT                           0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_NPT                              31:24 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_TX_HDR_LIMIT_NPT_INIT                           0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_DATA_LIMIT				   0x00000E0C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_TX_DATA_LIMIT_NP				  7:0 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_TX_DATA_LIMIT_NP_INIT				  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_DATA_LIMIT_PW                               15:8 /* RWCUF */
+#define NV_PROJ__PCIE2_RP_TX_DATA_LIMIT_PW_INIT                           0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_UFPCI					   0x00000E10 /* RW-4R */	
+#define NV_PROJ__PCIE2_RP_UFPCI_PW_STARV_COUNT				  4:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_UFPCI_PW_STARV_COUNT_INIT		          0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_UFPCI_PW_PRI_OVR_COUNT			  9:5 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_UFPCI_PW_PRI_OVR_COUNT_INIT		          0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_UFPCI_WRR_GRANT_BURST				11:10 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_UFPCI_WRR_GRANT_BURST_INIT			  0x1 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_UFPCI_REQ_PEND_PERIOD				19:12 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_UFPCI_REQ_PEND_PERIOD_INIT                      0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_UFPCI_ISONP2HPISO                             20:20 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_UFPCI_ISONP2HPISO_INIT                          0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_UFPCI_ISOPW2HPISO                             21:21 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_UFPCI_ISOPW2HPISO_INIT                          0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0                                    0x00000E14 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_MISC0_ENABLE_CLUMPING                           0:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_ENABLE_CLUMPING_INIT	                  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_NATIVE_P2P_ENABLE			  1:1 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_NATIVE_P2P_ENABLE_INIT	                  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_ISO_NP_ENABLE		                  2:2 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_ISO_NP_ENABLE_INIT                        0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_ISO_PW_ENABLE		                  3:3 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_ISO_PW_ENABLE_INIT                        0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_BURST_SIZE		                 19:4 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_BURST_SIZE_INIT                      0xFF /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_RXL_CLEAR_DROP 			        20:20 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_RXL_CLEAR_DROP_INIT	                  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_AUTO_XCLK_FREQ_EN 			21:21 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_AUTO_XCLK_FREQ_EN_INIT	                  0x1 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_NISONC2HPISO				23:23 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_NISONC2HPISO_INIT			  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_A					24:24 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_A_INIT				  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_A__PROD				  0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_B					25:25 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_B_INIT				  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_B__PROD				  0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_C					26:26 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_C_INIT				  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_C__PROD				  0x0 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_D					27:27 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_D_INIT				  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_D__PROD				  0x0 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_E					28:28 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_E_INIT				  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_E__PROD				  0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_F					29:29 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_F_INIT				  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_F__PROD				  0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_SMALL_ISA_HOLE   			30:30 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_SMALL_ISA_HOLE_INIT                   0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_MISC0_P2P_SMALL_ISA_HOLE__PROD                  0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_MISC0_SHORT_RXL_TIMER 			31:31 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_MISC0_SHORT_RXL_TIMER_INIT 			  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TXBA0                                    0x00000E18 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_TXBA0_REPLAY_BUF_LIMIT		          8:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TXBA0_REPLAY_BUF_LIMIT_INIT                     0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_DISABLE                        9:9 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_DISABLE_INIT                   0x1 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_UPTO_32DW                    10:10 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_UPTO_32DW_INIT                 0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_UPTO_64DW                    11:11 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TXBA0_CMPL_MERGE_UPTO_64DW_INIT                 0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TXBA0_USE_REPLAY_TIMER_OFFSET                 12:12 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TXBA0_USE_REPLAY_TIMER_OFFSET_INIT	          0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TXBA0_USE_REPLAY_TIMER_OFFSET__PROD	          0x1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_TXBA0_REPLAY_TIMER_EXPIRY                     31:16 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TXBA0_REPLAY_TIMER_EXPIRY_INIT	          0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TXBA0_REPLAY_TIMER_EXPIRY__PROD	         0x64 /* RW--V */
+#define NV_PROJ__PCIE2_RP_TXBA1                                    0x00000E1C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_TXBA1_PW_OVER_CM_BURST                          3:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TXBA1_PW_OVER_CM_BURST_INIT                     0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TXBA1_CM_OVER_PW_BURST                          7:4 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TXBA1_CM_OVER_PW_BURST_INIT                     0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TXBA1_CMPL_MERGE_THRESHOLD                     15:8 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TXBA1_CMPL_MERGE_THRESHOLD_INIT                 0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_FORCEFC				   0x00000E20 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_FORCEFC_PWH_UNRET_THRESH			  7:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_FORCEFC_PWH_UNRET_THRESH_INIT                   0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_FORCEFC_PWD_UNRET_THRESH                       15:8 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_FORCEFC_PWD_UNRET_THRESH_INIT                   0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_FORCEFC_NPH_UNRET_THRESH			23:16 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_FORCEFC_NPH_UNRET_THRESH_INIT                   0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_FORCEFC_NPD_UNRET_THRESH                      31:24 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_FORCEFC_NPD_UNRET_THRESH_INIT                   0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TIMEOUT0 				    0x00000E24 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_PWRUP			           7:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_PWRUP_INIT			   0xD /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_PWRUP_CM                           23:8 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_PWRUP_CM_INIT                      0x14 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_SPDCHNG_GEN2                      31:24 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TIMEOUT0_PAD_SPDCHNG_GEN2_INIT                   0xD /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TIMEOUT1                                  0x00000E28 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_TIMEOUT1_PAD_SPDCHNG_GEN1                       15:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TIMEOUT1_PAD_SPDCHNG_GEN1_INIT                 0x2E8 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TIMEOUT1_RCVRY_SPD_SUCCESS_EIDLE               23:16 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TIMEOUT1_RCVRY_SPD_SUCCESS_EIDLE_INIT           0x14 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TIMEOUT1_RCVRY_SPD_UNSUCCESS_EIDLE             31:24 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_TIMEOUT1_RCVRY_SPD_UNSUCCESS_EIDLE_INIT         0x96 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR			    0x00000E2C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_DBUF                    0:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_DBUF_FALSE	           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_DBUF_TRUE               0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_DBUF_CLEAR              0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_HBUF                    1:1 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_HBUF_FALSE	           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_HBUF_TRUE               0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_CMPL_HBUF_CLEAR              0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY                       2:2 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_FALSE	           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_TRUE                  0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_CLEAR                 0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID0                3:3 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID0_FALSE          0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID0_TRUE           0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID0_CLEAR          0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID1                4:4 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID1_FALSE          0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID1_TRUE           0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REPLAY_SEQID1_CLEAR          0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF                     5:5 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_FALSE	           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_TRUE                0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_CLEAR               0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF                     6:6 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_FALSE	           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_TRUE                0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_CLEAR               0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_NP_SIDEQ                 7:7 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_NP_SIDEQ_FALSE           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_NP_SIDEQ_TRUE            0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_NP_SIDEQ_CLEAR           0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_PW_SIDEQ                 8:8 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_PW_SIDEQ_FALSE           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_PW_SIDEQ_TRUE            0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_PW_SIDEQ_CLEAR           0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_UCFIFO                       9:9 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_UCFIFO_FALSE                 0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_UCFIFO_TRUE                  0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_UCFIFO_CLEAR                 0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO1                  10:10 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO1_FALSE              0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO1_TRUE               0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO1_CLEAR              0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO2                  11:11 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO2_FALSE              0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO2_TRUE               0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_TLP_FIFO2_CLEAR              0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_DBUF                       12:12 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_DBUF_FALSE                   0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_DBUF_TRUE                    0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_DBUF_CLEAR                   0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_HBUF                       13:13 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_HBUF_FALSE                   0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_HBUF_TRUE                    0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_RX_HBUF_CLEAR                   0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO1                    14:14 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO1_FALSE                0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO1_TRUE                 0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO1_CLEAR                0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO2                    15:15 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO2_FALSE                0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO2_TRUE                 0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_DCFIFO2_CLEAR                0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_ADR               16:16 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_ADR_FALSE	   0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_ADR_TRUE            0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_DBUF_ADR_CLEAR           0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_ADR               17:17 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_ADR_FALSE           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_ADR_TRUE            0x1 /* R---V */
+#define NV_PROJ__PCIE2_RP_RAM_PARITY_ERROR_TX_REQ_HBUF_ADR_CLEAR           0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR		    0x00000E30 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_CMPL_DBUF              0:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_CMPL_DBUF_INIT         0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_CMPL_HBUF              1:1 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_CMPL_HBUF_INIT         0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY                 2:2 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY_INIT            0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY_SEQID0          3:3 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY_SEQID0_INIT     0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY_SEQID1          4:4 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REPLAY_SEQID1_INIT     0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_DBUF               5:5 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_DBUF_INIT          0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF               6:6 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF_INIT          0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_NP_LEN             7:7 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_NP_LEN_INIT        0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_PW_LEN             8:8 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_PW_LEN_INIT        0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_UCFIFO                 9:9 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_UCFIFO_INIT            0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_TXTF_FIFO1           10:10 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_TXTF_FIFO1_INIT        0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_TXTF_FIFO2           11:11 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_TXTF_FIFO2_INIT        0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_DBUF0                12:12 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_DBUF0_INIT             0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_DBUF1                13:13 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_DBUF1_INIT             0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_HBUF                 14:14 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_RX_HBUF_INIT              0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_DBUF_ADR         16:16 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_DBUF_ADR_INIT      0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF_ADR         17:17 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF_ADR_INIT      0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF0            18:18 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_RAM_FORCE_PARITY_ERROR_TX_REQ_HBUF0_INIT         0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRBS					    0x00000E34 /* R--4R */
+#define NV_PROJ__PCIE2_RP_PRBS_ERR_COUNT_OVERFLOW  			  15:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_PRBS_LOCKED					 31:16 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LANE_PRBS_ERR                             0x00000E38 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_LANE_PRBS_ERR_SELECT                             3:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_LANE_PRBS_ERR_SELECT_INIT                        0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LANE_PRBS_ERR_COUNT				 31:16 /* R--VF */
+#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_0			    0x00000E3C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_0_L0_LPBK		          15:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_0_L0_LPBK_INIT                   0x80 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_0_RCVRCFG_SUC_SPEED             31:16 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_0_RCVRCFG_SUC_SPEED_INIT        0x500 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_1                          0x00000E40 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_1_UNSUC_SPEED_GEN1               15:0 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_1_UNSUC_SPEED_GEN1_INIT         0x7D0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_1_UNSUC_SPEED_GEN2              31:16 /* RWIUF */
+#define NV_PROJ__PCIE2_RP_EIDLE_INFER_TO_1_UNSUC_SPEED_GEN2_INIT        0x3E80 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG				     0x00000E44 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM0                             0:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM0_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM0_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM1                             1:1 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM1_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM1_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM2                             2:2 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM2_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM2_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM3                             3:3 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM3_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM3_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM4                             4:4 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM4_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM4_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM5                             5:5 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM5_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM5_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM6                             6:6 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM6_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM6_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM7                             7:7 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM7_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM7_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM8                             8:8 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM8_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM8_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM9                             9:9 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM9_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM9_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM10                          10:10 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM10_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM10_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM11                          11:11 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM11_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM11_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM12                          12:12 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM12_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM12_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM13                          13:13 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM13_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM13_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM14                          14:14 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM14_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM14_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM15                          15:15 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM15_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM15_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM16                          16:16 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM16_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM16_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM17                          17:17 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM17_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM17_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM18                          18:18 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM18_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM18_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM19                          19:19 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM19_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM19_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM20                          20:20 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM20_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM20_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM21                          21:21 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM21_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM21_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM22                          22:22 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM22_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM22_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM23                          23:23 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM23_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM23_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM24                          24:24 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM24_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM24_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM25                          25:25 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM25_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM25_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM26                          26:26 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM26_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM26_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM27                          27:27 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM27_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM27_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM28                          28:28 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM28_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM28_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM29                          29:29 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM29_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM29_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM30                          30:30 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM30_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM30_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM31                          31:31 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM31_INIT		            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_DBGREG_LINKFSM31_CLEAR		            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS		                     0x00000E48 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_LCRC_ERR                              0:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_LCRC_ERR_INIT                         0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_LCRC_ERR_CLEAR                        0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_FRAMING_ERR                           1:1 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_FRAMING_ERR_INIT                      0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_FRAMING_ERR_CLEAR                     0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_HDR_ERR                   2:2 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_HDR_ERR_INIT              0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_HDR_ERR_CLEAR             0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_HDR_ERR                   3:3 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_HDR_ERR_INIT              0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_HDR_ERR_CLEAR             0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_HDR_ERR                  4:4 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_HDR_ERR_INIT             0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_HDR_ERR_CLEAR            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_DATA_ERR                  5:5 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_DATA_ERR_INIT             0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_NP_DATA_ERR_CLEAR            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_DATA_ERR                  6:6 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_DATA_ERR_INIT             0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_PW_DATA_ERR_CLEAR            0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_DATA_ERR                 7:7 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_DATA_ERR_INIT            0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_CPL_DATA_ERR_CLEAR           0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISONP_HDR_ERR                8:8 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISONP_HDR_ERR_INIT           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISONP_HDR_ERR_CLEAR          0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_HDR_ERR                9:9 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_HDR_ERR_INIT           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_HDR_ERR_CLEAR          0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_DATA_ERR             10:10 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_DATA_ERR_INIT          0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REC_OVFL_ISOPW_DATA_ERR_CLEAR         0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_TOO_MANY_CREDITS_ERR             11:11 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_TOO_MANY_CREDITS_ERR_INIT          0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_TOO_MANY_CREDITS_ERR_CLEAR         0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_UPDATE_FC_ERR                    12:12 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_UPDATE_FC_ERR_INIT                 0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CD_UPDATE_FC_ERR_CLEAR                0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_TOO_MANY_CREDITS_ERR             13:13 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_TOO_MANY_CREDITS_ERR_INIT          0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_TOO_MANY_CREDITS_ERR_CLEAR         0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_UPDATE_FC_ERR                    14:14 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_UPDATE_FC_ERR_INIT                 0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_CH_UPDATE_FC_ERR_CLEAR                0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_TOO_MANY_CREDITS_ERR            15:15 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_TOO_MANY_CREDITS_ERR_INIT         0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_TOO_MANY_CREDITS_ERR_CLEAR        0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_UPDATE_FC_ERR                   16:16 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_UPDATE_FC_ERR_INIT                0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPD_UPDATE_FC_ERR_CLEAR               0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_TOO_MANY_CREDITS_ERR            17:17 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_TOO_MANY_CREDITS_ERR_INIT         0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_TOO_MANY_CREDITS_ERR_CLEAR        0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_UPDATE_FC_ERR                   18:18 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_UPDATE_FC_ERR_INIT                0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_NPH_UPDATE_FC_ERR_CLEAR               0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_TOO_MANY_CREDITS_ERR            19:19 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_TOO_MANY_CREDITS_ERR_INIT         0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_TOO_MANY_CREDITS_ERR_CLEAR        0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_UPDATE_FC_ERR                   20:20 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_UPDATE_FC_ERR_INIT                0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWD_UPDATE_FC_ERR_CLEAR               0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_TOO_MANY_CREDITS_ERR            21:21 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_TOO_MANY_CREDITS_ERR_INIT         0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_TOO_MANY_CREDITS_ERR_CLEAR        0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_UPDATE_FC_ERR                   22:22 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_UPDATE_FC_ERR_INIT                0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_PWH_UPDATE_FC_ERR_CLEAR               0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_ROLLOVER_ERR                 23:23 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_ROLLOVER_ERR_INIT              0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_ROLLOVER_ERR_CLEAR             0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_STARTED_ERR                  24:24 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_STARTED_ERR_INIT               0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_STARTED_ERR_CLEAR              0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_8B10B_ERR                           25:25 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_8B10B_ERR_INIT                        0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_8B10B_ERR_CLEAR                       0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DLLP_CRC_ERR                        26:26 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DLLP_CRC_ERR_INIT                     0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DLLP_CRC_ERR_CLEAR                    0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_TRAINING_ERR                        27:27 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_TRAINING_ERR_INIT                     0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_TRAINING_ERR_CLEAR                    0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DESKEW_ERR                          28:28 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DESKEW_ERR_INIT                       0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_DESKEW_ERR_CLEAR                      0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_SA_ERR                              29:29 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_SA_ERR_INIT                           0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_SA_ERR_CLEAR                          0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_TIMER_EXPIRED_ERR            30:30 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_TIMER_EXPIRED_ERR_INIT         0x0 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_ERRSTS_REPLAY_TIMER_EXPIRED_ERR_CLEAR        0x1 /* -W--C */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL                                 0x00000E4C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_STORE_EN                               0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_STORE_EN_INIT                   0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_STORE_EN_CLEAR                  0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_STORE_EN_SET                    0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_WRAP_EN                                1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_WRAP_EN_INIT                    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_WRAP_EN_CLEAR                   0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_WRAP_EN_SET                     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_CLEAR_RAM                              2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_CLEAR_RAM_INIT                  0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_ON_EVENT                          3:3 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_ON_EVENT_INIT              0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_LTSSM_MAJOR                       7:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_LTSSM_MAJOR_INIT           0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_PTX_LTSSM_MINOR                  10:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_PTX_LTSSM_MINOR_INIT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_PRX_LTSSM_MINOR                 13:11 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_CONTROL_TRIG_PRX_LTSSM_MINOR_INIT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS                                  0x00000E50 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_RAM_FULL                                0:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_WRITE_PTR                               5:1 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_READ_ADDR                              10:6 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_READ_ADDR_INIT                   0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_READ_DATA_VALID                       11:11 /* R--VF */
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_LTSSM_MAJOR                           15:12 /* R--VF */      
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_PTX_LTSSM_MINOR                       18:16 /* R--VF */      
+#define NV_PROJ__PCIE2_RP_LTSSM_TRACE_STATUS_PRX_LTSSM_MINOR                       21:19 /* R--VF */      
+#define NV_PROJ__PCIE2_RP_VEND_XP                                   0x00000F00 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP_EMULATION                                0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_EMULATION_OFF                     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_EMULATION_ON                      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PRBS_EN                                  1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PRBS_EN_DISABLED                  0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PRBS_EN_ENABLED                   0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PRBS_STAT                               17:2 /* R--VF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_UPDATE_FC_THRESHOLD                    25:18 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_UPDATE_FC_THRESHOLD_INIT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_UPDATE_FC_THRESHOLD__PROD         0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_TRAIN_ERR_ENABLE                       26:26 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_TRAIN_ERR_ENABLE_INIT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_TRAIN_ERR_ENABLE__PROD            0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_ACK                      27:27 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_ACK_INIT            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_ACK__PROD           0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_UPDATEFC                 28:28 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_UPDATEFC_INIT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_OPPORTUNISTIC_UPDATEFC__PROD      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_INTERLEAVE_DLLPS                       29:29 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_INTERLEAVE_DLLPS_INIT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_INTERLEAVE_DLLPS__PROD            0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_DL_UP                                  30:30 /* R--VF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_FORCE_COMPLIANCE			 31:31 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_FORCE_COMPLIANCE_INIT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP1                                  0x00000F04 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_MAXWIDTH                         5:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_MAXWIDTH_INIT            0x000000010 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_GEN2_LINK_UPGRADE                6:6 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_GEN2_LINK_UPGRADE_INIT    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_EN                               7:7 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_EN_ZERO                   0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_GEN2_WAIT_FOR_FIRST_EIES             8:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_RNCTRL_GEN2_WAIT_FOR_FIRST_EIES_INIT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_ACK_TIMER_LIMIT                       18:10 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_ACK_TIMER_LIMIT_INIT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_ACK_TIMER_LIMIT__PROD            0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_CYA                                   26:19 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_CYA_INIT                         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_CYA__PROD                        0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_FORCE_UPSTREAM_NONCOH                 27:27 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_FORCE_UPSTREAM_NONCOH_INIT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_FORCE_UPSTREAM_NONCOH_ENABLED    0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP1_FORCE_UPSTREAM_NONCOH_DISABLED   0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP2                                  0x00000F08 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_ACK_WAKE                            7:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_ACK_WAKE_INIT                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_ACK_WAKE__PROD               0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_THRESHOLD                          17:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_THRESHOLD_INIT               0x000003FF /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_THRESHOLD__PROD              0x000003FF /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_THRESHOLD_REMOTE_NFTS        0x000003FF /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_UPDATE_WAKE                       31:24 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_UPDATE_WAKE_INIT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP2_L0S_UPDATE_WAKE__PROD            0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT                                      0x00000F0C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND                                 9:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_DEFAULT                  0x000000FA /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_250                      0x000000FA /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_278                      0x00000116 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_313                      0x00000139 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_357                      0x00000165 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_417                      0x000001A1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_500                      0x000001F4 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND_555                      0x0000022B /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_MICROSECOND__PROD_C_FPGA             0x000000FA /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_100MS_DFPCI                               31:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_100MS_DFPCI_333                      0x00000030 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_100MS_DFPCI_250                      0x00000018 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_TIMEOUT_100MS_DFPCI__PROD                    0x00000018 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_CMN                               0x00000F14 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XV_CMN_ISO2TC_MAP                         31:29 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XV_CMN_ISO2TC_MAP_7                  0x00000007 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XV_CMN_ISO2TC_MAP__PROD              0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT                           0x00000F18 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_ENABLE                           0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_ENABLE_INIT                      0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_DUTY_CYCLE                       3:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_DUTY_CYCLE_INIT                  0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_PERIOD                          15:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_THERM_MGMT_PERIOD_INIT                      0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP                           0x00000F20 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_BUTTON_PRESENT         0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_BUTTON_PRESENT_INIT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_BUTTON_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_CONTROLLER_PRESENT         1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_CONTROLLER_PRESENT_INIT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_CONTROLLER_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_MRL_SENSOR_PRESENT               2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_MRL_SENSOR_PRESENT_INIT   0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_MRL_SENSOR_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_INDICATOR_PRESENT      3:3 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_INDICATOR_PRESENT_INIT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ATTENTION_INDICATOR_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_INDICATOR_PRESENT          4:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_INDICATOR_PRESENT_INIT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_POWER_INDICATOR_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_SURPRISE                5:5 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_SURPRISE_INIT    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_SURPRISE__PROD_C_HPC 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_CAPABLE                 6:6 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_CAPABLE_INIT     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_HOT_PLUG_CAPABLE__PROD_C_HPC 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_VALUE          14:7 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_VALUE_INIT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_VALUE__PROD_C 0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_SCALE         16:15 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_SCALE_INIT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_SLOT_POWER_LIMIT_SCALE__PROD_C 0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ELECTROMECH_INTERLOCK_PRESENT 17:17 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ELECTROMECH_INTERLOCK_PRESENT_INIT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_ELECTROMECH_INTERLOCK_PRESENT__PROD_C_HPC 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_NO_CMD_COMPLETED_SUPPORT           18:18 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_NO_CMD_COMPLETED_SUPPORT_INIT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_NO_CMD_COMPLETED_SUPPORT__PROD 0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_PHYSICAL_SLOT_NUMBER           31:19 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_PHYSICAL_SLOT_NUMBER_INIT 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SLOT_STRAP_PHYSICAL_SLOT_NUMBER__PROD_C 0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0                                 0x00000F44 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_PASSPW_RO                              1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_PASSPW_RO_NOT                   0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_PASSPW_RO__PROD                 0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_PASSPW_RO_YES                   0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_GPU_NISONC2HPISO                       2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_GPU_NISONC2HPISO_EN             0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_GPU_NISONC2HPISO__PROD          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_GPU_NISONC2HPISO_DIS            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_DFPCI_ERR                         3:3 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_DFPCI_ERR_NO               0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_DFPCI_ERR_YES              0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_DFPCI_ERR__PROD            0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_IGNORE_BME                             4:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_IGNORE_BME_NO                   0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_IGNORE_BME__PROD                0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_IGNORE_BME_YES                  0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_ADR64                                  5:5 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_ADR64_EN                        0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_ADR64__PROD                     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_ADR64_DIS                       0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_MAX_PAYLOAD_SIZE                       8:6 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_MAX_PAYLOAD_SIZE_INIT           0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_MAX_PAYLOAD_SIZE_4KB            0x00000005 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_MAX_PAYLOAD_SIZE_AUTO           0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_ALL_MODE                          9:9 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_ALL_MODE_INIT              0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_ALL_MODE_YES               0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DROP_ALL_MODE_NO                0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_UR_PW_DROP_ALL_MODE                  10:10 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_UR_PW_DROP_ALL_MODE_INIT        0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_UR_PW_DROP_ALL_MODE_YES         0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_UR_PW_DROP_ALL_MODE_NO          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_FINISH_PKT_ON_RCVRY_EN               11:11 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_FINISH_PKT_ON_RCVRY_EN_INIT     0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DSK_RESET_PULSE_WIDTH                15:12 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DSK_RESET_PULSE_WIDTH_INIT      0x00000008 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_NATIVE_P2P_STARVE_COUNT              23:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_NATIVE_P2P_STARVE_COUNT_INIT    0x00000000 /* RWI-V */        
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_NATIVE_P2P_STARVE_COUNT__PROD   0x00000004 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_UP_NC2C                              29:29 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_UP_NC2C_EN                      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_UP_NC2C__PROD                   0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_UP_NC2C_DIS                     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_FORCE_RETRY_POSSIBLE                 30:30 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_FORCE_RETRY_POSSIBLE_NO         0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_FORCE_RETRY_POSSIBLE_YES        0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DISABLE_CRS                          31:31 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DISABLE_CRS_INIT                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA0_DISABLE_CRS__PROD               0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1                                 0x00000F48 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_BLOCK_P2P_ONLY                     0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_BLOCK_P2P_ONLY_EN           0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_BLOCK_P2P_ONLY__PROD        0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_BLOCK_P2P_ONLY_DIS          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_TC2ISO_MAP                             3:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_TC2ISO_MAP_7                    0x00000007 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_TC2ISO_MAP__PROD                0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_ACCEPT_MSGD1                           4:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_ACCEPT_MSGD1_DIS                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_ACCEPT_MSGD1_EN                 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_ACCEPT_MSGD1__PROD              0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSI_CAP                         12:12 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSI_CAP_DIS                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSI_CAP_EN                 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSI_CAP__PROD              0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_ERPT                                 13:13 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_ERPT_EN                         0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_ERPT_DIS                        0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_ERPT__PROD                      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_ISO2NISO                         14:14 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_ISO2NISO_EN                 0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_ISO2NISO_DIS                0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_P2P_ISO2NISO__PROD              0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_LINKACTV_REPORTING                   15:15 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_LINKACTV_REPORTING_CAPABLE      0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_LINKACTV_REPORTING_NOT_CAPABLE  0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_LINKACTV_REPORTING__PROD        0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSIMAP                          16:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSIMAP_DIS                 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSIMAP_EN                  0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA1_HIDE_MSIMAP__PROD               0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST                                                     0x00000F4C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL                                                      31:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_INIT                                           0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL__PROD                                          0x10000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN                                 0x00000F50 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_L1                                     0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_L1_EN                           0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_L1_DIS                          0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_L1__PROD                        0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC                                1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC_EN                      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC_DIS                     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DYNAMIC__PROD                   0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED                               2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED_EN                     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED_DIS                    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_DISABLED__PROD                  0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1                          4:3 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L0                0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1                0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1P               0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_L1_L1PP              0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC                     6:5 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L0           0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1           0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1P          0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC_L1PP         0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_SLEEP_MODE_DYNAMIC__PROD        0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MINIMUM                               14:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MINIMUM_INIT                    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND                          25:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_DEFAULT             0x000000FA /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_278                 0x00000116 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_312                 0x00000138 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_333                 0x0000014D /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_357                 0x00000165 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_417                 0x000001A1 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_500                 0x000001F4 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_MICROSECOND_555                 0x0000022B /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_XVR_USE_DFPCI_DATA_UNINTR            26:26 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_XVR_USE_DFPCI_DATA_UNINTR_INIT  0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_PAD_PWRDN_XVR_USE_DFPCI_DATA_UNINTR__PROD 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_FTS                                       0x00000F54 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_N_FTS                                        7:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_N_FTS_INIT                            0x0000001F /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_N_FTS__PROD                           0x0000001F /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_N_FTS_REMOTE                                15:8 /* R--VF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_DETECT_START                               25:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_DETECT_START_INIT                     0x00000040 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_FTS_DETECT_START__PROD                    0x00000040 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0                                    0x00000F58 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_8B10B_ERRORS_LC                           0:0 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_8B10B_ERRORS_LC_INIT               0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_8B10B_ERRORS_INF                          4:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_8B10B_ERRORS_INF_INIT              0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_CRC_ERRORS_LC                             8:8 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_CRC_ERRORS_LC_INIT                 0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_CRC_ERRORS_INF                          12:12 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_CRC_ERRORS_INF_INIT                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_NAKS_RCVD_LC                            16:16 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_NAKS_RCVD_LC_INIT                  0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_NAKS_RCVD_INF                           20:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_NAKS_RCVD_INF_INIT                 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_FAILED_L0S_EXITS_LC                     24:24 /* C-IVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_FAILED_L0S_EXITS_LC_INIT           0x00000000 /* C-I-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_FAILED_L0S_EXITS_INF                    28:28 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS0_FAILED_L0S_EXITS_INF_INIT          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS1                                    0x00000F5C /* R--4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS1_8B10B_ERRORS                              7:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS1_CRC_ERRORS                               15:8 /* R--VF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS1_NAKS_RCVD                               23:16 /* R--VF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_STATS1_FAILED_L0S_EXITS                        31:24 /* R--VF */
+#define NV_PROJ__PCIE2_RP_VEND_ERROR_COUNT                                  0x00000F60 /* R--4R */
+#define NV_PROJ__PCIE2_RP_VEND_ERROR_COUNT_LCRC_ERR                                7:0 /* R--VF */
+#define NV_PROJ__PCIE2_RP_VEND_ERROR_COUNT_BAD_TLP                                15:8 /* R--VF */
+#define NV_PROJ__PCIE2_RP_VEND_ERROR_COUNT_REPLAY                                23:16 /* R--VF */
+#define NV_PROJ__PCIE2_RP_CFG_MISC                                        0x00000F64 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_CFG_MISC_MUTE_IDLE                                     7:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_CFG_MISC_MUTE_IDLE_MIN                          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CFG_MISC_MUTE_IDLE_MAX                          0x000000FF /* RW--V */
+#define NV_PROJ__PCIE2_RP_CFG_MISC_MUTE_IDLE__PROD                        0x0000001F /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY                            0x00000F68 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_THRESHOLD            19:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_THRESHOLD_2500 0x000009C4 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_WINDOW              30:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_WINDOW_100US   0x00000064 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_ENABLE              31:31 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_INIT_RECOVERY_8B10B_ERROR_ENABLE_INIT    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2                                       0x00000F6C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_SPEED_CHANGE                                 0:0 /* CWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_SPEED_CHANGE_ZERO                     0x00000000 /* CWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ADVERTISED_RATE_CHANGE                       1:1 /* CWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ADVERTISED_RATE_CHANGE_ZERO           0x00000000 /* CWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE                      2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE_DISABLED      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_DEEMPHASIS_OVERRIDE_ENABLED       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_TX_MARGIN_OVERRIDE                       3:3 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_TX_MARGIN_OVERRIDE_DISABLED       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_CYA_TX_MARGIN_OVERRIDE_ENABLED        0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED                            7:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED_2P5                 0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_TARGET_LINK_SPEED_5P0                 0x00000002 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED                         11:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_2P5               0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_5P0_2P5           0x00000002 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE                 15:12 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_2P5        0x00000001 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DATA_RATE_SUPPORTED_REMOTE_5P0_2P5    0x00000002 /* R---V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_AUTONOMOUS_CHANGE	                     16:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_AUTONOMOUS_CHANGE_INIT                0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_POLLING_PREDETERMINED_LANES                17:17 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_POLLING_PREDETERMINED_LANES_DISABLE   0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ENFORCE_DEEMPHASIS                         18:18 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ENFORCE_DEEMPHASIS_INIT               0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DEEMPHASIS_STRAP                           19:19 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_DEEMPHASIS_STRAP_INIT                 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_N_EIE_SYMBOLS		                     23:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_N_EIE_SYMBOLS_INIT	                0x00000006 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_RECOVERY_SPEED_TIMEOUT_ADJ                 26:24 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_RECOVERY_SPEED_TIMEOUT_ADJ_INIT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ALLOW_SPEED_CHANGE_FROM_L1                 27:27 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_ALLOW_SPEED_CHANGE_FROM_L1_INIT       0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_SURPRISE_IDLE_USE_STAT_IDLE                28:28 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_SURPRISE_IDLE_USE_STAT_IDLE_INIT      0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_EIDLE_INFERENCE_EN                         29:29 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_EIDLE_INFERENCE_EN_INIT               0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_REV2P0_COMPLIANCE_DIS                      30:30 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_REV2P0_COMPLIANCE_DIS_INIT            0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_REV2P0_COMPLIANCE_DIS__PROD           0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_LCTRL_2_UPCONFIGURE_CAPABLE                        31:31 /* R--VF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_PAD_PWRUP                                  0x00000F74 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_PAD_PWRUP_PMRX_PWRUP_THRESHOLD                  23:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_PAD_PWRUP_PMRX_PWRUP_THRESHOLD_INIT        0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_GEN2_PAD_PWRDN                             0x00000F78 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_GEN2_PAD_PWRDN_MICROSECOND                     25:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_GEN2_PAD_PWRDN_MICROSECOND_277             0x00000115 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_GEN2_PAD_PWRDN_MICROSECOND_555             0x0000022B /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_GEN2_PAD_PWRDN_MICROSECOND_500             0x000001F4 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_REASONS                         0x00000F84 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_REASONS_VALUE                         31:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_REASONS_VALUE_INIT              0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_REASONS_VALUE_REC_ALL           0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_REASONS_VALUE_REC_NEXT          0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_COUNT                            0x00000F88 /* R--4R */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_COUNT_VALUE                            31:0 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_RECOVERY_COUNT_VALUE_INIT                 0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2                                        0x00000F8C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_DIS_MA_TA_EP_MERGE                            1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_DIS_MA_TA_EP_MERGE_ON                  0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_DIS_MA_TA_EP_MERGE_OFF                 0x00000000 /* RWI-V */    
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_DEV_CAP_EXTENDED_TAG_FIELD_SIZE               2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_DEV_CAP_EXTENDED_TAG_FIELD_SIZE_8B     0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_DEV_CAP_EXTENDED_TAG_FIELD_SIZE_5B     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_PROTOCOL_DISABLE		       4:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_PROTOCOL_DISABLE_OFF		0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_PROTOCOL_DISABLE_ON		0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_SPEED_DISABLE			       5:5 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_SPEED_DISABLE_ON		0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_GEN2_SPEED_DISABLE_OFF		0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_PCA_ENABLE			               7:7 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_PCA_ENABLE_ON		        0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_PCA_ENABLE_OFF			0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_NMI                        8:8 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_NMI_FALSE           0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_NMI_TRUE           	0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_NMI_CLEAR          	0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_PME                        9:9 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_PME_FALSE           0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_PME_TRUE           	0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_ERR_STS_HOTPLUG_PME_CLEAR          	0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_SLOT_IMPLEMENTED                         11:11 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_SLOT_IMPLEMENTED_INIT               0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_SLOT_IMPLEMENTED_YES                0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_SLOT_IMPLEMENTED_NO                 0x00000000 /* RW--V */    
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_FUSE_GEN2_PROTOCOL_DISABLE	            12:12 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_FUSE_GEN2_PROTOCOL_DISABLE_ON      0x00000001 /* R---V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_FUSE_GEN2_PROTOCOL_DISABLE_OFF     0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_SHADOW_LINK_BW_NOTIFY_CAP               13:13 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_SHADOW_LINK_BW_NOTIFY_CAP_EN       0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_SHADOW_LINK_BW_NOTIFY_CAP_DIS      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_DIS                       16:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_DIS_TRUE             0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_DIS_FALSE            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_DIS                      17:17 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_DIS_TRUE            0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_DIS_FALSE           0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_INT_EN_DIS	             18:18 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_INT_EN_DIS_TRUE      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_AUTO_BANDWIDTH_INT_EN_DIS_FALSE     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_INT_EN_DIS                 19:19 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_INT_EN_DIS_TRUE       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_BW_MANAGEMENT_INT_EN_DIS_FALSE      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_HW_AUTO_WIDTH_DISABLE_DIS	             20:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_HW_AUTO_WIDTH_DISABLE_DIS_TRUE      0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_HW_AUTO_WIDTH_DISABLE_DIS_FALSE     0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_BLOCK_UP_TRANSACTIONS_ON_ERR                21:21 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_BLOCK_UP_TRANSACTIONS_ON_ERR_EN        0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_BLOCK_UP_TRANSACTIONS_ON_ERR_DIS       0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_UNBLOCK_UP_TRANSACTIONS	                22:22 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_UNBLOCK_UP_TRANSACTIONS_FALSE          0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_UNBLOCK_UP_TRANSACTIONS_TRUE           0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_IGNORE_ATTENTION_BUTTON_MSG	                23:23 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_IGNORE_ATTENTION_BUTTON_MSG_FALSE      0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_IGNORE_ATTENTION_BUTTON_MSG_TRUE       0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_COMPLIANCE_X8_DELAY                         24:24 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_CYA2_COMPLIANCE_X8_DELAY_INIT                      0x0 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG                                   0x00000F94 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG_LOW_PWR_DURATION                         1:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG_LOW_PWR_DURATION_TX_L0S           0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG_LOW_PWR_DURATION_RX_L0S           0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG_LOW_PWR_DURATION_L1               0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_CONFIG_LOW_PWR_DURATION_IDLE             0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DURATION_IN_LOW_PWR_100NS                 0x00000F98 /* R-I4R */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DURATION_IN_LOW_PWR_100NS_VALUE                 31:0 /* R-IVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_DURATION_IN_LOW_PWR_100NS_VALUE_INIT      0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT				    0x00000F9C /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD     		          12:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_INIT		    0x00000569 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_250                 0x000004E2 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_278                 0x00000569 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_313                 0x0000061A /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_357                 0x000006F5 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_417                 0x00000821 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_500                 0x000009BF /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_555                 0x00000AD2 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2     	         25:13 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_INIT	    0x00000569 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_250            0x00000271 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_278            0x000002B4 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_313            0x0000030D /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_357            0x0000037A /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_417            0x00000410 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_500            0x000004DF /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_SKP_TIMEOUT_THRESHOLD_GEN2_555            0x00000569 /* RW--V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_EIDLE_INFERENCE_TIMEOUT		 0x00000FA0 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_EIDLE_INFERENCE_TIMEOUT_A		       15:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_EIDLE_INFERENCE_TIMEOUT_A_INIT	 0x0000008F /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_EIDLE_INFERENCE_TIMEOUT_B		      31:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_XP_EIDLE_INFERENCE_TIMEOUT_B_INIT	 0x000006F2 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC                    0x00000FA4 /* RWI4R */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_COMMAND                 31:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_COMMAND_INIT       0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE                    15:8 /* R--VF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE7             7:7 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE7_INIT 0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE7_SET  0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE6             6:6 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE6_INIT 0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE6_SET  0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE5             5:5 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE5_INIT 0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE5_SET  0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE4             4:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE4_INIT 0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE4_SET  0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE3             3:3 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE3_INIT 0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE3_SET  0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE2             2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE2_INIT 0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE2_SET  0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE1             1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE1_INIT 0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE1_SET  0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE0             0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE0_INIT 0x00000000 /* R-I-V */
+#define NV_PROJ__PCIE2_RP_SLOT_CONTROL_STATUS_HPC_STATE_CHANGE0_SET  0x00000001 /* -W--C */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0                                  0x00000FA8 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_0                                  3:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_0_INIT                      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_1                                  7:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_1_INIT                      0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_2                                 11:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_2_INIT                      0x00000002 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_3                                15:12 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_3_INIT                      0x00000003 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_4                                19:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_4_INIT                      0x00000004 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_5                                23:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_5_INIT                      0x00000005 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_6                                27:24 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_6_INIT                      0x00000006 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_7                                31:28 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP0_LANE_7_INIT                      0x00000007 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1                                  0x00000FAC /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_8                                  3:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_8_INIT                      0x00000008 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_9                                  7:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_9_INIT                      0x00000009 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_10                                11:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_10_INIT                     0x0000000A /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_11                               15:12 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_11_INIT                     0x0000000B /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_12                               19:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_12_INIT                     0x0000000C /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_13                               23:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_13_INIT                     0x0000000D /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_14                               27:24 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_14_INIT                     0x0000000E /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_15                               31:28 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_LANEMAP1_LANE_15_INIT                     0x0000000F /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SHADOW_SS_1                                  0x00000FB0 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_SHADOW_SS_1_SSID                                  31:16 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_VEND_SHADOW_SS_1_SSID_INIT                              0x0  /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_SHADOW_SS_1_SSVID                                  15:0 /* RWCVF */
+#define NV_PROJ__PCIE2_RP_VEND_SHADOW_SS_1_SSVID_INIT                           0x10DE /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP                       0x00000FB4 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE0                        5:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE0_INIT            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE1                       13:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE1_INIT            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE2                      21:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE2_INIT            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE3                      29:24 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP0_TX_AMP_CODE3_INIT            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP                      0x00000FB8 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE4                        5:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE4_INIT            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE5                       13:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE5_INIT            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE6                      21:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE6_INIT            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE7                      29:24 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_TX_MARGIN_MAP1_TX_AMP_CODE7_INIT            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CTL_2                                 0x00000FBC /* RW-4R */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R0_1C                          18:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R0_1C_DEFAULT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R0_1C_NO_EQ		0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R0_1C_MAX_EQ		0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R1_1C                          22:20 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R1_1C_DEFAULT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R1_1C_NO_EQ		0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R1_1C_MAX_EQ		0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R2_1C                          26:24 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R2_1C_DEFAULT             0x00000003 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R2_1C_NO_EQ		0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_2_RX_EQ_R2_1C_MAX_EQ		0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3                             0x00000FC0 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C                       5:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C_DEFAULT        0x0000000C /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C_1150_MVPPD     0x0000000F /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C_1100_MVPPD     0x0000000E /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C_1050_MVPPD     0x0000000D /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C_1000_MVPPD     0x0000000C /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__950_MVPPD     0x0000000B /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__900_MVPPD     0x0000000A /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__850_MVPPD     0x00000009 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__800_MVPPD     0x00000008 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__750_MVPPD     0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__700_MVPPD     0x00000006 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__650_MVPPD     0x00000005 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__600_MVPPD     0x00000004 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__550_MVPPD     0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__500_MVPPD     0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__450_MVPPD     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R0_1C__400_MVPPD     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C                     12:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C_DEFAULT       0x0000000A /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C_MAX           0x0000000F /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C_DISABLE       0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C_36DB          0x0000000A /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R0_1C_6DB           0x0000000F /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C                     21:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C_DEFAULT        0x0000000C /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C_1150_MVPPD     0x0000000F /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C_1100_MVPPD     0x0000000E /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C_1050_MVPPD     0x0000000D /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C_1000_MVPPD     0x0000000C /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__950_MVPPD     0x0000000B /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__900_MVPPD     0x0000000A /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__850_MVPPD     0x00000009 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__800_MVPPD     0x00000008 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__750_MVPPD     0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__700_MVPPD     0x00000006 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__650_MVPPD     0x00000005 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__600_MVPPD     0x00000004 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__550_MVPPD     0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__500_MVPPD     0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__450_MVPPD     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_AMP_R1_1C__400_MVPPD     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C                    27:23 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C_DEFAULT       0x0000000A /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C_MAX           0x0000000F /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C_DISABLE       0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C_36DB          0x0000000A /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_3_TX_PEAK_R1_1C_6DB           0x0000000F /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4                             0x00000FC4 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C                       5:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C_DEFAULT        0x0000000C /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C_1150_MVPPD     0x0000000F /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C_1100_MVPPD     0x0000000E /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C_1050_MVPPD     0x0000000D /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C_1000_MVPPD     0x0000000C /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__950_MVPPD     0x0000000B /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__900_MVPPD     0x0000000A /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__850_MVPPD     0x00000009 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__800_MVPPD     0x00000008 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__750_MVPPD     0x00000007 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__700_MVPPD     0x00000006 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__650_MVPPD     0x00000005 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__600_MVPPD     0x00000004 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__550_MVPPD     0x00000003 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__500_MVPPD     0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__450_MVPPD     0x00000001 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_AMP_R2_1C__400_MVPPD     0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C                     12:8 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C_DEFAULT       0x0000000F /* RWI-V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C_MAX           0x0000000F /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C_DISABLE       0x00000000 /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C_36DB          0x0000000A /* RW--V */
+#define NV_PROJ__PCIE2_RP_CTL_4_TX_PEAK_R2_1C_6DB           0x0000000F /* RW--V */
+#define NV_PROJ__PCIE2_RP_TIMEOUT2                                       0x00000FC8 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_TIMEOUT2_MIN_L1_L2_IDLE_TIME  		        4:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_TIMEOUT2_MIN_L1_L2_IDLE_TIME_INIT	         0x0000000A /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_MISC                       		   0x00000FCC /* RW-4R */
+#define NV_PROJ__PCIE2_RP_PRIV_MISC_PRSNT_MAP                                     3:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_MISC_PRSNT_MAP_INIT	                   0x0000000F /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD                    22:16 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_THRESHOLD_INIT          0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE                       23:23 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE_INIT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD                     30:24 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_THRESHOLD_INIT           0x00000003 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE                        31:31 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE_INIT              0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2                                    0x00000FD0 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_SHORT_LINK_TIMERS                         0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_SHORT_LINK_TIMERS_INIT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_EIDLE_ENTRY                        1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_EIDLE_ENTRY_INIT            0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_EIDLE_EXIT                         2:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_EIDLE_EXIT_INIT             0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_MIN_EIDLE                          3:3 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_MIN_EIDLE_INIT              0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_SPEED                              7:4 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_SPEED_2P5                   0x00000001 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_TXCHAR_SPEED_5P0                   0x00000002 /* RW--V */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_OVERRIDE_JTAG                           31:31 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP_BIST_CTRL_2_OVERRIDE_JTAG_INIT                 0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_VEND_XP3                                               0x00000FD4 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_VEND_XP3_SA_ERROR_LIMIT                                       7:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_VEND_XP3_SA_ERROR_LIMIT_INIT                           0x00000003 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_XP_CYA_1                                            0x00000FD8 /* RW-4R */
+#define NV_PROJ__PCIE2_RP_XP_CYA_1_FORCE_SA_IN_CONFIG                                0:0 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_XP_CYA_1_FORCE_SA_IN_CONFIG_INIT                    0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_XP_CYA_1_LWLO_HUNT_ON_BAD_TS1                              1:1 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_XP_CYA_1_LWLO_HUNT_ON_BAD_TS1_INIT                  0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_XP_CYA_1_IDLE_TO_L0_DELAY                                  5:2 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_XP_CYA_1_IDLE_TO_L0_DELAY_INIT                      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_XP_CYA_1_RESET_LANE_ENABLE_ORIG_IN_DETECT                  6:6 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_XP_CYA_1_RESET_LANE_ENABLE_ORIG_IN_DETECT_INIT      0x00000000 /* RWI-V */
+#define NV_PROJ__PCIE2_RP_XP_CYA_1_SPARE                                            31:7 /* RWIVF */
+#define NV_PROJ__PCIE2_RP_XP_CYA_1_SPARE_INIT                                 0x00000000 /* RWI-V */
+
+#endif // ___DEV_AP_PCIE2_ROOT_PORT_H_INC_
+
diff --git a/arch/arm/mach-tegra/nv/include/ap20/nvboot_pmc_scratch_map.h b/arch/arm/mach-tegra/nv/include/ap20/nvboot_pmc_scratch_map.h
new file mode 100644
index 000000000000..7f687a75b0b0
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/nvboot_pmc_scratch_map.h
@@ -0,0 +1,852 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * Defines fields in the PMC scratch registers used by the Boot ROM code.
+ */
+
+#ifndef INCLUDED_NVBOOT_PMC_SCRATCH_MAP_H
+#define INCLUDED_NVBOOT_PMC_SCRATCH_MAP_H
+
+// Special definition for the subset of EMC_FBIO_SPARE restored in WB0.
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_RANGE        31:24
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_SHIFT        _MK_SHIFT_CONST(24)
+#define EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH0_0_WARM_BOOT0_FLAG_RANGE        0:0
+#define APBDEV_PMC_SCRATCH0_0_WARM_BOOT0_FLAG_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH0_0_WARM_BOOT0_FLAG_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+/**
+ * MEMORY_TYPE:
+ *   Source: SDRAM[n].MemoryType
+ *   Desc:   An enumerated constant that identifies the type of SDRAM
+ *     (DDR, DDR2, LPDDR, LPDDR2), as the initialization sequence is different
+ *     for each of them. DDR is only valid for FPGA emulation, but the
+ *     Boot ROM code does not make this distinction.
+ */
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVM_RANGE        4:0
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVM_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVM_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVN_RANGE        14:5
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVN_SHIFT        _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVN_DEFAULT_MASK _MK_MASK_CONST(0x000003FF)
+
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVP_RANGE        17:15
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVP_SHIFT        _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_BASE_PLLM_DIVP_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_LFCON_RANGE        21:18
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_LFCON_SHIFT        _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_LFCON_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_CPCON_RANGE        25:22
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_CPCON_SHIFT        _MK_SHIFT_CONST(22)
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_PLLM_MISC_CPCON_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_RANGE        26:26
+#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_SHIFT        _MK_SHIFT_CONST(26)
+#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGAPADCTRL_0_CFG2TMC_XM2CFGA_PREEMP_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_RANGE        27:27
+#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_SHIFT        _MK_SHIFT_CONST(27)
+#define APBDEV_PMC_SCRATCH2_0_APB_MISC_GP_XM2CFGDPADCTRL_0_CFG2TMC_XM2CFGD_SCHMT_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_OSC_CTRL_XOBP_RANGE        28:28
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_OSC_CTRL_XOBP_SHIFT        _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_SCRATCH2_0_CLK_RST_OSC_CTRL_XOBP_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH2_0_MEMORY_TYPE_RANGE        31:29
+#define APBDEV_PMC_SCRATCH2_0_MEMORY_TYPE_SHIFT        _MK_SHIFT_CONST(29)
+#define APBDEV_PMC_SCRATCH2_0_MEMORY_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVM_RANGE        4:0
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVM_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVM_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVN_RANGE        14:5
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVN_SHIFT        _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVN_DEFAULT_MASK _MK_MASK_CONST(0x000003FF)
+
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVP_RANGE        17:15
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVP_SHIFT        _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_BASE_PLLX_DIVP_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_LFCON_RANGE        21:18
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_LFCON_SHIFT        _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_LFCON_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_CPCON_RANGE        25:22
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_CPCON_SHIFT        _MK_SHIFT_CONST(22)
+#define APBDEV_PMC_SCRATCH3_0_CLK_RST_PLLX_MISC_CPCON_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_RANGE        26:26
+#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_SHIFT        _MK_SHIFT_CONST(26)
+#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL_0_CFG2TMC_XM2CFGC_SCHMT_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_RANGE        30:27
+#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_SHIFT        _MK_SHIFT_CONST(27)
+#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_RANGE        31:31
+#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_SHIFT        _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SCRATCH3_0_APB_MISC_GP_XM2CLKCFGPADCTRL_0_CFG2TMC_XM2CLKCFG_PREEMP_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+
+/**
+ * PLLM_STABLE_TIME:
+ *   Source: SDRAM[n].PllMStableTime
+ *   Dest: SDRAM initialization code
+ *   Desc: Time to wait for PLLM to become stable, in microseconds.  Overrides
+ *     internal stabilization time values.
+ * PLLX_STABLE_TIME:
+ *   Source: SDRAM[n].PllXStableTime
+ *   Dest: PLLX initialization code for WB0
+ *   Desc: Time to wait for PLLM to become stable, in microseconds.  Overrides
+ *     internal stabilization time values.
+ * EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0:
+ *   Source: SDRAM[n].EmcFbioSpare (upper 8 bits)
+ *   Dest: Upper 8 bits of EMC_FBIO_SPARE
+ *   Desc: To avoid wasting all 32-bits of PMC scratch for spare bits for
+ *     some future use, only the upper 8 bits are preserved.
+ */
+#define APBDEV_PMC_SCRATCH4_0_EMC_CLOCK_DIVIDER_RANGE        7:0
+#define APBDEV_PMC_SCRATCH4_0_EMC_CLOCK_DIVIDER_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH4_0_EMC_CLOCK_DIVIDER_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH4_0_PLLM_STABLE_TIME_RANGE        15:8
+#define APBDEV_PMC_SCRATCH4_0_PLLM_STABLE_TIME_SHIFT        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_SCRATCH4_0_PLLM_STABLE_TIME_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH4_0_PLLX_STABLE_TIME_RANGE        23:16
+#define APBDEV_PMC_SCRATCH4_0_PLLX_STABLE_TIME_SHIFT        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SCRATCH4_0_PLLX_STABLE_TIME_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH4_0_EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_RANGE        31:24
+#define APBDEV_PMC_SCRATCH4_0_EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH4_0_EMC_FBIO_SPARE_0_CFG_FBIO_SPARE_WB0_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+
+#define APBDEV_PMC_SCRATCH5_0_EMC_RC_0_RC_RANGE        5:0
+#define APBDEV_PMC_SCRATCH5_0_EMC_RC_0_RC_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH5_0_EMC_RC_0_RC_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH5_0_EMC_RFC_0_RFC_RANGE        14:6
+#define APBDEV_PMC_SCRATCH5_0_EMC_RFC_0_RFC_SHIFT        _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_SCRATCH5_0_EMC_RFC_0_RFC_DEFAULT_MASK _MK_MASK_CONST(0x000001FF)
+
+#define APBDEV_PMC_SCRATCH5_0_EMC_RAS_0_RAS_RANGE        20:15
+#define APBDEV_PMC_SCRATCH5_0_EMC_RAS_0_RAS_SHIFT        _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_SCRATCH5_0_EMC_RAS_0_RAS_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH5_0_EMC_RP_0_RP_RANGE        26:21
+#define APBDEV_PMC_SCRATCH5_0_EMC_RP_0_RP_SHIFT        _MK_SHIFT_CONST(21)
+#define APBDEV_PMC_SCRATCH5_0_EMC_RP_0_RP_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH5_0_EMC_R2W_0_R2W_RANGE        31:27
+#define APBDEV_PMC_SCRATCH5_0_EMC_R2W_0_R2W_SHIFT        _MK_SHIFT_CONST(27)
+#define APBDEV_PMC_SCRATCH5_0_EMC_R2W_0_R2W_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+
+#define APBDEV_PMC_SCRATCH6_0_EMC_W2R_0_W2R_RANGE        4:0
+#define APBDEV_PMC_SCRATCH6_0_EMC_W2R_0_W2R_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH6_0_EMC_W2R_0_W2R_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH6_0_EMC_R2P_0_R2P_RANGE        9:5
+#define APBDEV_PMC_SCRATCH6_0_EMC_R2P_0_R2P_SHIFT        _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_SCRATCH6_0_EMC_R2P_0_R2P_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH6_0_EMC_W2P_0_W2P_RANGE        14:10
+#define APBDEV_PMC_SCRATCH6_0_EMC_W2P_0_W2P_SHIFT        _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_SCRATCH6_0_EMC_W2P_0_W2P_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH6_0_EMC_RD_RCD_0_RD_RCD_RANGE        20:15
+#define APBDEV_PMC_SCRATCH6_0_EMC_RD_RCD_0_RD_RCD_SHIFT        _MK_SHIFT_CONST(15)
+#define APBDEV_PMC_SCRATCH6_0_EMC_RD_RCD_0_RD_RCD_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH6_0_EMC_WR_RCD_0_WR_RCD_RANGE        26:21
+#define APBDEV_PMC_SCRATCH6_0_EMC_WR_RCD_0_WR_RCD_SHIFT        _MK_SHIFT_CONST(21)
+#define APBDEV_PMC_SCRATCH6_0_EMC_WR_RCD_0_WR_RCD_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH6_0_EMC_RRD_0_RRD_RANGE        30:27
+#define APBDEV_PMC_SCRATCH6_0_EMC_RRD_0_RRD_SHIFT        _MK_SHIFT_CONST(27)
+#define APBDEV_PMC_SCRATCH6_0_EMC_RRD_0_RRD_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+
+#define APBDEV_PMC_SCRATCH7_0_EMC_REXT_0_REXT_RANGE        3:0
+#define APBDEV_PMC_SCRATCH7_0_EMC_REXT_0_REXT_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH7_0_EMC_REXT_0_REXT_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH7_0_EMC_WDV_0_WDV_RANGE        7:4
+#define APBDEV_PMC_SCRATCH7_0_EMC_WDV_0_WDV_SHIFT        _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_SCRATCH7_0_EMC_WDV_0_WDV_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH7_0_EMC_QUSE_0_QUSE_RANGE        11:8
+#define APBDEV_PMC_SCRATCH7_0_EMC_QUSE_0_QUSE_SHIFT        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_SCRATCH7_0_EMC_QUSE_0_QUSE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH7_0_EMC_QRST_0_QRST_RANGE        15:12
+#define APBDEV_PMC_SCRATCH7_0_EMC_QRST_0_QRST_SHIFT        _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_SCRATCH7_0_EMC_QRST_0_QRST_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH7_0_EMC_QSAFE_0_QSAFE_RANGE        19:16
+#define APBDEV_PMC_SCRATCH7_0_EMC_QSAFE_0_QSAFE_SHIFT        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SCRATCH7_0_EMC_QSAFE_0_QSAFE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH7_0_EMC_RDV_0_RDV_RANGE        24:20
+#define APBDEV_PMC_SCRATCH7_0_EMC_RDV_0_RDV_SHIFT        _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_SCRATCH7_0_EMC_RDV_0_RDV_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH7_0_EMC_PCHG2PDEN_0_PCHG2PDEN_RANGE        29:25
+#define APBDEV_PMC_SCRATCH7_0_EMC_PCHG2PDEN_0_PCHG2PDEN_SHIFT        _MK_SHIFT_CONST(25)
+#define APBDEV_PMC_SCRATCH7_0_EMC_PCHG2PDEN_0_PCHG2PDEN_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_USE_ADDR_CLK_RANGE        30:30
+#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_USE_ADDR_CLK_SHIFT        _MK_SHIFT_CONST(30)
+#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_USE_ADDR_CLK_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_RANGE        31:31
+#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_SHIFT        _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SCRATCH7_0_EMC_CFG_2_0_CLKCHANGE_SR_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+
+#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_LO_RANGE        4:0
+#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_LO_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_LO_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_RANGE        15:5
+#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_SHIFT        _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_SCRATCH8_0_EMC_REFRESH_0_REFRESH_DEFAULT_MASK _MK_MASK_CONST(0x000007FF)
+
+#define APBDEV_PMC_SCRATCH8_0_EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_RANGE        19:16
+#define APBDEV_PMC_SCRATCH8_0_EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_SHIFT        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SCRATCH8_0_EMC_BURST_REFRESH_NUM_0_BURST_REFRESH_NUM_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2WR_0_PDEX2WR_RANGE        23:20
+#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2WR_0_PDEX2WR_SHIFT        _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2WR_0_PDEX2WR_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2RD_0_PDEX2RD_RANGE        27:24
+#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2RD_0_PDEX2RD_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH8_0_EMC_PDEX2RD_0_PDEX2RD_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH8_0_EMC_TCLKSTABLE_0_TCLKSTABLE_RANGE        31:28
+#define APBDEV_PMC_SCRATCH8_0_EMC_TCLKSTABLE_0_TCLKSTABLE_SHIFT        _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_SCRATCH8_0_EMC_TCLKSTABLE_0_TCLKSTABLE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+
+#define APBDEV_PMC_SCRATCH9_0_EMC_ACT2PDEN_0_ACT2PDEN_RANGE        4:0
+#define APBDEV_PMC_SCRATCH9_0_EMC_ACT2PDEN_0_ACT2PDEN_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH9_0_EMC_ACT2PDEN_0_ACT2PDEN_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH9_0_EMC_AR2PDEN_0_AR2PDEN_RANGE        9:5
+#define APBDEV_PMC_SCRATCH9_0_EMC_AR2PDEN_0_AR2PDEN_SHIFT        _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_SCRATCH9_0_EMC_AR2PDEN_0_AR2PDEN_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH9_0_EMC_RW2PDEN_0_RW2PDEN_RANGE        15:10
+#define APBDEV_PMC_SCRATCH9_0_EMC_RW2PDEN_0_RW2PDEN_SHIFT        _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_SCRATCH9_0_EMC_RW2PDEN_0_RW2PDEN_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH9_0_EMC_TXSR_0_TXSR_RANGE        27:16
+#define APBDEV_PMC_SCRATCH9_0_EMC_TXSR_0_TXSR_SHIFT        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SCRATCH9_0_EMC_TXSR_0_TXSR_DEFAULT_MASK _MK_MASK_CONST(0x00000FFF)
+
+#define APBDEV_PMC_SCRATCH9_0_EMC_TCKE_0_TCKE_RANGE        31:28
+#define APBDEV_PMC_SCRATCH9_0_EMC_TCKE_0_TCKE_SHIFT        _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_SCRATCH9_0_EMC_TCKE_0_TCKE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+
+#define APBDEV_PMC_SCRATCH10_0_EMC_TRPAB_0_TRPAB_RANGE        5:0
+#define APBDEV_PMC_SCRATCH10_0_EMC_TRPAB_0_TRPAB_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH10_0_EMC_TRPAB_0_TRPAB_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH10_0_EMC_TCLKSTOP_0_TCLKSTOP_RANGE        9:6
+#define APBDEV_PMC_SCRATCH10_0_EMC_TCLKSTOP_0_TCLKSTOP_SHIFT        _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_SCRATCH10_0_EMC_TCLKSTOP_0_TCLKSTOP_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH10_0_EMC_TREFBW_0_TREFBW_RANGE        23:10
+#define APBDEV_PMC_SCRATCH10_0_EMC_TREFBW_0_TREFBW_SHIFT        _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_SCRATCH10_0_EMC_TREFBW_0_TREFBW_DEFAULT_MASK _MK_MASK_CONST(0x00003FFF)
+
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_MUX_RANGE        24:24
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_MUX_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_MUX_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_WRITE_MUX_RANGE        25:25
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_WRITE_MUX_SHIFT        _MK_SHIFT_CONST(25)
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_WRITE_MUX_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_FORCE_UPDATE_RANGE        26:26
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_FORCE_UPDATE_SHIFT        _MK_SHIFT_CONST(26)
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_FORCE_UPDATE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_MRS_WAIT_RANGE        27:27
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_MRS_WAIT_SHIFT        _MK_SHIFT_CONST(27)
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_MRS_WAIT_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_PERIODIC_QRST_RANGE        28:28
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_PERIODIC_QRST_SHIFT        _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_PERIODIC_QRST_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_DQM_CTRL_RANGE        29:29
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_DQM_CTRL_SHIFT        _MK_SHIFT_CONST(29)
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_READ_DQM_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_AP_REQ_BUSY_CTRL_RANGE        30:30
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_AP_REQ_BUSY_CTRL_SHIFT        _MK_SHIFT_CONST(30)
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_AP_REQ_BUSY_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_CFG_PRIORITY_RANGE        31:31
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_CFG_PRIORITY_SHIFT        _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SCRATCH10_0_EMC_DBG_0_CFG_PRIORITY_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+
+// Note: 1 bit is reserved.
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_RANGE        1:0
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_0_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_RANGE        3:2
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_SHIFT        _MK_SHIFT_CONST(2)
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_1_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_RANGE        5:4
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_SHIFT        _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_2_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_RANGE        7:6
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_SHIFT        _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_DQSIB_DLY_MSB_0_CFG_DQSIB_DLY_MSB_BYTE_3_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_RANGE        9:8
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_SHIFT        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_0_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_RANGE        11:10
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_SHIFT        _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_1_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_RANGE        13:12
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_SHIFT        _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_2_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_RANGE        15:14
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_SHIFT        _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_SCRATCH11_0_EMC_FBIO_QUSE_DLY_MSB_0_CFG_QUSE_DLY_MSB_BYTE_3_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH11_0_EMC_TFAW_0_TFAW_RANGE        21:16
+#define APBDEV_PMC_SCRATCH11_0_EMC_TFAW_0_TFAW_SHIFT        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SCRATCH11_0_EMC_TFAW_0_TFAW_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH11_0_EMC_QUSE_EXTRA_0_QUSE_EXTRA_RANGE        25:22
+#define APBDEV_PMC_SCRATCH11_0_EMC_QUSE_EXTRA_0_QUSE_EXTRA_SHIFT        _MK_SHIFT_CONST(22)
+#define APBDEV_PMC_SCRATCH11_0_EMC_QUSE_EXTRA_0_QUSE_EXTRA_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_RANGE        29:26
+#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_SHIFT        _MK_SHIFT_CONST(26)
+#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_RANGE        30:30
+#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_SHIFT        _MK_SHIFT_CONST(30)
+#define APBDEV_PMC_SCRATCH11_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQ_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_RANGE        7:0
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_0_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_RANGE        15:8
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_SHIFT        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_1_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_RANGE        23:16
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_SHIFT        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_2_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_RANGE        31:24
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH12_0_EMC_FBIO_DQSIB_DLY_0_CFG_DQSIB_DLY_BYTE_3_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_RANGE        7:0
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_0_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_RANGE        15:8
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_SHIFT        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_1_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_RANGE        23:16
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_SHIFT        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_2_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_RANGE        31:24
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH13_0_EMC_FBIO_QUSE_DLY_0_CFG_QUSE_DLY_BYTE_3_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+
+// Note: 2 bits are reserved.
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_RANGE        5:0
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA0_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_RANGE        11:6
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_SHIFT        _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA1_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_RANGE        17:12
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_SHIFT        _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA2_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_RANGE        23:18
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_SHIFT        _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_DATA3_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_RANGE        29:24
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH14_0_EMC_CFG_CLKTRIM_0_0_CFG_MCLK_ADDR_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG1_0_CFG_DEN_EARLY_RANGE        0:0
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG1_0_CFG_DEN_EARLY_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG1_0_CFG_DEN_EARLY_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG6_0_CFG_QUSE_LATE_RANGE        3:1
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG6_0_CFG_QUSE_LATE_SHIFT        _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG6_0_CFG_QUSE_LATE_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_TYPE_RANGE        5:4
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_TYPE_SHIFT        _MK_SHIFT_CONST(4)
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_WIDTH_RANGE        6:6
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_WIDTH_SHIFT        _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DRAM_WIDTH_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_RANGE        7:7
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_SHIFT        _MK_SHIFT_CONST(7)
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DIFFERENTIAL_DQS_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_CTT_TERMINATION_RANGE        8:8
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_CTT_TERMINATION_SHIFT        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_CTT_TERMINATION_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_RANGE        13:9
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_SHIFT        _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PU_OFFSET_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_RANGE        18:14
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_SHIFT        _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_PD_OFFSET_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_RANGE        28:19
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_SHIFT        _MK_SHIFT_CONST(19)
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_STEP_DEFAULT_MASK _MK_MASK_CONST(0x000003FF)
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_RANGE        29:29
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_SHIFT        _MK_SHIFT_CONST(29)
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_RANGE        30:30
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_SHIFT        _MK_SHIFT_CONST(30)
+#define APBDEV_PMC_SCRATCH15_0_EMC_AUTO_CAL_CONFIG_0_AUTO_CAL_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DQS_PULLD_RANGE        31:31
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DQS_PULLD_SHIFT        _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SCRATCH15_0_EMC_FBIO_CFG5_0_DQS_PULLD_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+
+#define APBDEV_PMC_SCRATCH16_0_EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_RANGE        27:0
+#define APBDEV_PMC_SCRATCH16_0_EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH16_0_EMC_AUTO_CAL_INTERVAL_0_AUTO_CAL_INTERVAL_DEFAULT_MASK _MK_MASK_CONST(0x0FFFFFFF)
+
+#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_RANGE        28:28
+#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_SHIFT        _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_REQ_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_RANGE        29:29
+#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_SHIFT        _MK_SHIFT_CONST(29)
+#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_CLKCHANGE_PD_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_PIN_CONFIG_RANGE        31:30
+#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_PIN_CONFIG_SHIFT        _MK_SHIFT_CONST(30)
+#define APBDEV_PMC_SCRATCH16_0_EMC_CFG_2_0_PIN_CONFIG_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_COLWIDTH_RANGE        2:0
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_COLWIDTH_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_COLWIDTH_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_BANKWIDTH_RANGE        4:3
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_BANKWIDTH_SHIFT        _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_BANKWIDTH_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_DEVSIZE_RANGE        8:5
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_DEVSIZE_SHIFT        _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_DEVSIZE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_NUMDEV_RANGE        10:9
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_NUMDEV_SHIFT        _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_SCRATCH17_0_EMC_ADR_CFG_0_EMEM_NUMDEV_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_EN_RANGE        11:11
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_EN_SHIFT        _MK_SHIFT_CONST(11)
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_CYCLES_RANGE        19:12
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_CYCLES_SHIFT        _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_PRE_IDLE_CYCLES_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_CLEAR_AP_PREV_SPREQ_RANGE        20:20
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_CLEAR_AP_PREV_SPREQ_SHIFT        _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_CLEAR_AP_PREV_SPREQ_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_RD_RANGE        21:21
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_RD_SHIFT        _MK_SHIFT_CONST(21)
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_RD_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_WR_RANGE        22:22
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_WR_SHIFT        _MK_SHIFT_CONST(22)
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_AUTO_PRE_WR_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_ACPD_RANGE        23:23
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_ACPD_SHIFT        _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_ACPD_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_RANGE        24:24
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_PDSR_ONLY_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_RANGE        25:25
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_SHIFT        _MK_SHIFT_CONST(25)
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_0_DRAM_CLKSTOP_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_RANGE        26:26
+#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_SHIFT        _MK_SHIFT_CONST(26)
+#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_RANGE        27:27
+#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_SHIFT        _MK_SHIFT_CONST(27)
+#define APBDEV_PMC_SCRATCH17_0_MC_LOWLATENCY_CONFIG_0_MPCORER_LL_SEND_BOTH_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_RANGE        29:28
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_SHIFT        _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOCK_LIMIT_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_RANGE        31:30
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_SHIFT        _MK_SHIFT_CONST(30)
+#define APBDEV_PMC_SCRATCH17_0_EMC_CFG_DIG_DLL_0_CFG_DLL_MODE_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+
+#define APBDEV_PMC_SCRATCH18_0_EMC_CTT_TERM_CTRL_0_TERM_DRVUP_RANGE        4:0
+#define APBDEV_PMC_SCRATCH18_0_EMC_CTT_TERM_CTRL_0_TERM_DRVUP_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH18_0_EMC_CTT_TERM_CTRL_0_TERM_DRVUP_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_RANGE        7:5
+#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_SHIFT        _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_COLWIDTH_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_RANGE        9:8
+#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_SHIFT        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_BANKWIDTH_DEFAULT_MASK _MK_MASK_CONST(0x00000003)
+
+#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_RANGE        13:10
+#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_SHIFT        _MK_SHIFT_CONST(10)
+#define APBDEV_PMC_SCRATCH18_0_EMC_ADR_CFG_1_0_EMEM1_DEVSIZE_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_RANGE        17:14
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_SHIFT        _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2COMPPADCTRL_0_CFG2TMC_XM2COMP_VREF_SEL_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_RANGE        20:18
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_SHIFT        _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVUP_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_RANGE        23:21
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_SHIFT        _MK_SHIFT_CONST(21)
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_CAL_DRVDN_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_RANGE        26:24
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VAUXP_LEVEL_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_RANGE        29:27
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_SHIFT        _MK_SHIFT_CONST(27)
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_VCLAMP_LEVEL_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_RANGE        30:30
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_SHIFT        _MK_SHIFT_CONST(30)
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_PWRGND_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_RANGE        31:31
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_SHIFT        _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SCRATCH18_0_APB_MISC_GP_XM2VTTGENPADCTRL_0_CFG2TMC_XM2VTTGEN_SHORT_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+
+#define APBDEV_PMC_SCRATCH19_0_MC_EMEM_CFG_0_EMEM_SIZE_KB_RANGE        21:0
+#define APBDEV_PMC_SCRATCH19_0_MC_EMEM_CFG_0_EMEM_SIZE_KB_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH19_0_MC_EMEM_CFG_0_EMEM_SIZE_KB_DEFAULT_MASK _MK_MASK_CONST(0x003FFFFF)
+
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_EN_RANGE        22:22
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_EN_SHIFT        _MK_SHIFT_CONST(22)
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_RANGE        23:23
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_SHIFT        _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLI_TRIMMER_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_RANGE        24:24
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_RANGE        25:25
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_SHIFT        _MK_SHIFT_CONST(25)
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_USE_SINGLE_DLL_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_RANGE        26:26
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_SHIFT        _MK_SHIFT_CONST(26)
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_PERBYTE_TRIMMER_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_RANGE        27:27
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_SHIFT        _MK_SHIFT_CONST(27)
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_LOWSPEED_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_RANGE        31:28
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_SHIFT        _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_SCRATCH19_0_EMC_CFG_DIG_DLL_0_CFG_DLL_UDSET_DEFAULT_MASK _MK_MASK_CONST(0x0000000F)
+
+
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_RANGE        5:0
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS0_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_RANGE        11:6
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_SHIFT        _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS1_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_RANGE        17:12
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_SHIFT        _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS2_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_RANGE        23:18
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_SHIFT        _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_DQS3_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_RANGE        29:24
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH20_0_EMC_CFG_CLKTRIM_1_0_CFG_MCLK_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_RANGE        30:30
+#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_SHIFT        _MK_SHIFT_CONST(30)
+#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_VREF_DQS_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_RANGE        31:31
+#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_SHIFT        _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SCRATCH20_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_CTT_HIZ_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_RANGE        5:0
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ0_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_RANGE        11:6
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_SHIFT        _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ1_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_RANGE        17:12
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_SHIFT        _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ2_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_RANGE        23:18
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_SHIFT        _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_DQ3_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_RANGE        29:24
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH21_0_EMC_CFG_CLKTRIM_2_0_CFG_CMD_CLKTRIM_DEFAULT_MASK _MK_MASK_CONST(0x0000003F)
+
+#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_RANGE        30:30
+#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_SHIFT        _MK_SHIFT_CONST(30)
+#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_PREEMP_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_RANGE        31:31
+#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_SHIFT        _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SCRATCH21_0_APB_MISC_GP_XM2CFGCPADCTRL2_0_CFG2TMC_XM2CFGC_RX_FT_REC_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+
+// Note: 1 bit reserved
+#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_RANGE        4:0
+#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_MULT_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_RANGE        19:5
+#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_SHIFT        _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_SCRATCH22_0_EMC_DLL_XFORM_DQS_0_XFORM_DQS_OFFS_DEFAULT_MASK _MK_MASK_CONST(0x00007FFF)
+
+#define APBDEV_PMC_SCRATCH22_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_RANGE        29:20
+#define APBDEV_PMC_SCRATCH22_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_SHIFT        _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_SCRATCH22_0_EMC_CFG_DIG_DLL_0_CFG_DLL_OVERRIDE_VAL_DEFAULT_MASK _MK_MASK_CONST(0x000003FF)
+
+#define APBDEV_PMC_SCRATCH22_0_MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_RANGE        30:30
+#define APBDEV_PMC_SCRATCH22_0_MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_SHIFT        _MK_SHIFT_CONST(30)
+#define APBDEV_PMC_SCRATCH22_0_MC_LOWLATENCY_CONFIG_0_LL_DRAM_INTERLEAVE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+
+// Note: 2 bits reserved
+#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_RANGE        4:0
+#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_MULT_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_RANGE        19:5
+#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_SHIFT        _MK_SHIFT_CONST(5)
+#define APBDEV_PMC_SCRATCH23_0_EMC_DLL_XFORM_QUSE_0_XFORM_QUSE_OFFS_DEFAULT_MASK _MK_MASK_CONST(0x00007FFF)
+
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_WR_DELAY_RANGE        22:20
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_WR_DELAY_SHIFT        _MK_SHIFT_CONST(20)
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_WR_DELAY_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_B4_WRITE_RANGE        23:23
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_B4_WRITE_SHIFT        _MK_SHIFT_CONST(23)
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ODT_B4_WRITE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_RANGE        24:24
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_WRITE_0_ENABLE_ODT_DURING_WRITE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_RD_DELAY_RANGE        27:25
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_RD_DELAY_SHIFT        _MK_SHIFT_CONST(25)
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_RD_DELAY_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_B4_READ_RANGE        28:28
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_B4_READ_SHIFT        _MK_SHIFT_CONST(28)
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_ODT_B4_READ_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_RANGE        29:29
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_SHIFT        _MK_SHIFT_CONST(29)
+#define APBDEV_PMC_SCRATCH23_0_EMC_ODT_READ_0_DISABLE_ODT_DURING_READ_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+
+/**
+ * AHB_ARBITRATION_XBAR_CTRL:
+ *  Source: SDRAM[n].AhbArbitrationXbarCtrl
+ *  Dest: AHB_ARBITRATION_XBAR_CTRL
+ *  Desc: Note: Only bits 0, 1, and 16 are actually used in this scratch
+ *    register. However, the Boot ROM copies the entire 32 bits to
+ *    AHB_ARBITRATION_XBAR_CTRL.  The 3 single-bit definitions are provided
+ *    for convenience/reference.
+ */
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_RANGE        0:0
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_POST_DIS_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_RANGE        1:1
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_SHIFT        _MK_SHIFT_CONST(1)
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_HOLD_DIS_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_RANGE        16:16
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_SHIFT        _MK_SHIFT_CONST(16)
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_0_MEM_INIT_DONE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_RANGE        31:0
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH25_0_AHB_ARBITRATION_XBAR_CTRL_DEFAULT_MASK _MK_MASK_CONST(0xFFFFFFFF)
+
+#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_RANGE        23:0
+#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_REF_CNT_0_ZCAL_REF_INTERVAL_DEFAULT_MASK _MK_MASK_CONST(0x00FFFFFF)
+
+#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_RANGE        31:24
+#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_SHIFT        _MK_SHIFT_CONST(24)
+#define APBDEV_PMC_SCRATCH35_0_EMC_ZCAL_WAIT_CNT_0_ZCAL_WAIT_CNT_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+
+// Note: 2 bits are reserved.
+#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_RANGE        7:0
+#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_OP_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_RANGE        15:8
+#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_SHIFT        _MK_SHIFT_CONST(8)
+#define APBDEV_PMC_SCRATCH36_0_EMC_ZCAL_MRW_CMD_0_ZQ_MRW_MA_DEFAULT_MASK _MK_MASK_CONST(0x000000FF)
+
+// bits [17:16] reserved
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_SLOPE_RANGE        20:18
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_SLOPE_SHIFT        _MK_SHIFT_CONST(18)
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_SLOPE_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OFFSET_RANGE        25:21
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OFFSET_SHIFT        _MK_SHIFT_CONST(21)
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OFFSET_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_DRVDN_RANGE        30:26
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_DRVDN_SHIFT        _MK_SHIFT_CONST(26)
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_DRVDN_DEFAULT_MASK _MK_MASK_CONST(0x0000001F)
+
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_RANGE        31:31
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_SHIFT        _MK_SHIFT_CONST(31)
+#define APBDEV_PMC_SCRATCH36_0_EMC_CTT_TERM_CTRL_0_TERM_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+
+// Scratch registers 37, 38, and 39 are reserved for SW.
+
+// The last three scratch registers are reseved for HW ECO's.
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_RANGE        2:0
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_SHIFT        _MK_SHIFT_CONST(0)
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD3_DLYIN_TRM_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_RANGE        5:3
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_SHIFT        _MK_SHIFT_CONST(3)
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD2_DLYIN_TRM_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_RANGE        8:6
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_SHIFT        _MK_SHIFT_CONST(6)
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD1_DLYIN_TRM_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_RANGE        11:9
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_SHIFT        _MK_SHIFT_CONST(9)
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD0_DLYIN_TRM_DEFAULT_MASK _MK_MASK_CONST(0x00000007)
+
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_RANGE        12:12
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_SHIFT        _MK_SHIFT_CONST(12)
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_CTT_HIZ_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_RANGE        13:13
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_SHIFT        _MK_SHIFT_CONST(13)
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_PREEMP_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_RANGE        14:14
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_SHIFT        _MK_SHIFT_CONST(14)
+#define APBDEV_PMC_SCRATCH40_0_APB_MISC_GP_XM2CFGDPADCTRL2_0_CFG2TMC_XM2CFGD_RX_FT_REC_EN_DEFAULT_MASK _MK_MASK_CONST(0x00000001)
+
+#endif // INCLUDED_NVBOOT_APBDEV_PMC_SCRATCH_MAP_H
diff --git a/arch/arm/mach-tegra/nv/include/ap20/project_relocation_table.h b/arch/arm/mach-tegra/nv/include/ap20/project_relocation_table.h
new file mode 100644
index 000000000000..2276060dd560
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/ap20/project_relocation_table.h
@@ -0,0 +1,586 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef PROJECT_AP15_RELOCATION_TABLE_SPEC_INC
+#define PROJECT_AP15_RELOCATION_TABLE_SPEC_INC
+
+// ------------------------------------------------------------
+//    hw nvdevids
+// ------------------------------------------------------------
+// Memory Aperture: Internal Memory
+#define NV_DEVID_IMEM                            1
+
+// Memory Aperture: External Memory
+#define NV_DEVID_EMEM                            2
+
+// Memory Aperture: TCRAM
+#define NV_DEVID_TCRAM                           3
+
+// Memory Aperture: IRAM
+#define NV_DEVID_IRAM                            4
+
+// Memory Aperture: NOR FLASH
+#define NV_DEVID_NOR                             5
+
+// Memory Aperture: EXIO
+#define NV_DEVID_EXIO                            6
+
+// Memory Aperture: GART
+#define NV_DEVID_GART                            7
+
+// Device Aperture: Graphics Host (HOST1X)
+#define NV_DEVID_HOST1X                          8
+
+// Device Aperture: ARM PERIPH registers
+#define NV_DEVID_ARM_PERIPH                      9
+
+// Device Aperture: MSELECT
+#define NV_DEVID_MSELECT                         10
+
+// Device Aperture: memory controller
+#define NV_DEVID_MC                              11
+
+// Device Aperture: external memory controller
+#define NV_DEVID_EMC                             12
+
+// Device Aperture: video input
+#define NV_DEVID_VI                              13
+
+// Device Aperture: encoder pre-processor
+#define NV_DEVID_EPP                             14
+
+// Device Aperture: video encoder
+#define NV_DEVID_MPE                             15
+
+// Device Aperture: 3D engine
+#define NV_DEVID_GR3D                            16
+
+// Device Aperture: 2D + SBLT engine
+#define NV_DEVID_GR2D                            17
+
+// Device Aperture: Image Signal Processor
+#define NV_DEVID_ISP                             18
+
+// Device Aperture: DISPLAY
+#define NV_DEVID_DISPLAY                         19
+
+// Device Aperture: UPTAG
+#define NV_DEVID_UPTAG                           20
+
+// Device Aperture - SHR_SEM
+#define NV_DEVID_SHR_SEM                         21
+
+// Device Aperture - ARB_SEM
+#define NV_DEVID_ARB_SEM                         22
+
+// Device Aperture - ARB_PRI
+#define NV_DEVID_ARB_PRI                         23
+
+// Obsoleted for AP15
+#define NV_DEVID_PRI_INTR                        24
+
+// Obsoleted for AP15
+#define NV_DEVID_SEC_INTR                        25
+
+// Device Aperture: Timer Programmable
+#define NV_DEVID_TMR                             26
+
+// Device Aperture: Clock and Reset
+#define NV_DEVID_CAR                             27
+
+// Device Aperture: Flow control
+#define NV_DEVID_FLOW                            28
+
+// Device Aperture: Event
+#define NV_DEVID_EVENT                           29
+
+// Device Aperture: AHB DMA
+#define NV_DEVID_AHB_DMA                         30
+
+// Device Aperture: APB DMA
+#define NV_DEVID_APB_DMA                         31
+
+// Device Aperture: COP Cache Controller
+#define NV_DEVID_COP_CACHE                       32
+
+// Obsolete - use COP_CACHE
+#define NV_DEVID_CC                              32
+
+// Obsolete - use COP_CACHE
+#define NV_DEVID_SYS_REG                         32
+
+// Device Aperture: System Statistic monitor
+#define NV_DEVID_STAT                            33
+
+// Device Aperture: GPIO
+#define NV_DEVID_GPIO                            34
+
+// Device Aperture: Vector Co-Processor 2
+#define NV_DEVID_VCP                             35
+
+// Device Aperture: Arm Vectors
+#define NV_DEVID_VECTOR                          36
+
+// Device: MEM
+#define NV_DEVID_MEM                             37
+
+// Obsolete - use VDE
+#define NV_DEVID_SXE                             38
+
+// Device Aperture: video decoder
+#define NV_DEVID_VDE                             38
+
+// Obsolete - use VDE
+#define NV_DEVID_BSEV                            39
+
+// Obsolete - use VDE
+#define NV_DEVID_MBE                             40
+
+// Obsolete - use VDE
+#define NV_DEVID_PPE                             41
+
+// Obsolete - use VDE
+#define NV_DEVID_MCE                             42
+
+// Obsolete - use VDE
+#define NV_DEVID_TFE                             43
+
+// Obsolete - use VDE
+#define NV_DEVID_PPB                             44
+
+// Obsolete - use VDE
+#define NV_DEVID_VDMA                            45
+
+// Obsolete - use VDE
+#define NV_DEVID_UCQ                             46
+
+// Device Aperture: BSEA (now in AVP cluster)
+#define NV_DEVID_BSEA                            47
+
+// Obsolete - use VDE
+#define NV_DEVID_FRAMEID                         48
+
+// Device Aperture: Misc regs
+#define NV_DEVID_MISC                            49
+
+// Device Aperture: AC97
+#define NV_DEVID_AC97                            50
+
+// Device Aperture: S/P-DIF
+#define NV_DEVID_SPDIF                           51
+
+// Device Aperture: I2S
+#define NV_DEVID_I2S                             52
+
+// Device Aperture: UART
+#define NV_DEVID_UART                            53
+
+// Device Aperture: VFIR
+#define NV_DEVID_VFIR                            54
+
+// Device Aperture: NAND Flash Controller
+#define NV_DEVID_NANDCTRL                        55
+
+// Obsolete - use NANDCTRL
+#define NV_DEVID_NANDFLASH                       55
+
+// Device Aperture: HSMMC
+#define NV_DEVID_HSMMC                           56
+
+// Device Aperture: XIO
+#define NV_DEVID_XIO                             57
+
+// Device Aperture: PWFM
+#define NV_DEVID_PWFM                            58
+
+// Device Aperture: MIPI
+#define NV_DEVID_MIPI_HS                         59
+
+// Device Aperture: I2C
+#define NV_DEVID_I2C                             60
+
+// Device Aperture: TWC
+#define NV_DEVID_TWC                             61
+
+// Device Aperture: SLINK
+#define NV_DEVID_SLINK                           62
+
+// Device Aperture: SLINK4B
+#define NV_DEVID_SLINK4B                         63
+
+// Device Aperture: SPI
+#define NV_DEVID_SPI                             64
+
+// Device Aperture: DVC
+#define NV_DEVID_DVC                             65
+
+// Device Aperture: RTC
+#define NV_DEVID_RTC                             66
+
+// Device Aperture: KeyBoard Controller
+#define NV_DEVID_KBC                             67
+
+// Device Aperture: PMIF
+#define NV_DEVID_PMIF                            68
+
+// Device Aperture: FUSE
+#define NV_DEVID_FUSE                            69
+
+// Device Aperture: L2 Cache Controller
+#define NV_DEVID_CMC                             70
+
+// Device Apertuer: NOR FLASH Controller
+#define NV_DEVID_NOR_REG                         71
+
+// Device Aperture: EIDE
+#define NV_DEVID_EIDE                            72
+
+// Device Aperture: USB
+#define NV_DEVID_USB                             73
+
+// Device Aperture: SDIO
+#define NV_DEVID_SDIO                            74
+
+// Device Aperture: TVO
+#define NV_DEVID_TVO                             75
+
+// Device Aperture: DSI
+#define NV_DEVID_DSI                             76
+
+// Device Aperture: HDMI
+#define NV_DEVID_HDMI                            77
+
+// Device Aperture: Third Interrupt Controller extra registers
+#define NV_DEVID_TRI_INTR                        78
+
+// Device Aperture: Common Interrupt Controller
+#define NV_DEVID_ICTLR                           79
+
+// Non-Aperture Interrupt: DMA TX interrupts
+#define NV_DEVID_DMA_TX_INTR                     80
+
+// Non-Aperture Interrupt: DMA RX interrupts
+#define NV_DEVID_DMA_RX_INTR                     81
+
+// Non-Aperture Interrupt: SW reserved interrupt
+#define NV_DEVID_SW_INTR                         82
+
+// Non-Aperture Interrupt: CPU PMU Interrupt
+#define NV_DEVID_CPU_INTR                        83
+
+// Device Aperture: Timer Free Running MicroSecond
+#define NV_DEVID_TMRUS                           84
+
+// Device Aperture: Interrupt Controller ARB_GNT Registers
+#define NV_DEVID_ICTLR_ARBGNT                    85
+
+// Device Aperture: Interrupt Controller DMA Registers
+#define NV_DEVID_ICTLR_DRQ                       86
+
+// Device Aperture: AHB DMA Channel
+#define NV_DEVID_AHB_DMA_CH                      87
+
+// Device Aperture: APB DMA Channel
+#define NV_DEVID_APB_DMA_CH                      88
+
+// Device Aperture: AHB Arbitration Controller
+#define NV_DEVID_AHB_ARBC                        89
+
+// Obsolete - use AHB_ARBC
+#define NV_DEVID_AHB_ARB_CTRL                    89
+
+// Device Aperture: AHB/APB Debug Bus Registers
+#define NV_DEVID_AHPBDEBUG                       91
+
+// Device Aperture: Secure Boot Register
+#define NV_DEVID_SECURE_BOOT                     92
+
+// Device Aperture: SPROM
+#define NV_DEVID_SPROM                           93
+
+// Memory Aperture: AHB external memory remapping
+#define NV_DEVID_AHB_EMEM                        94
+
+// Non-Aperture Interrupt: External PMU interrupt
+#define NV_DEVID_PMU_EXT                         95
+
+// Device Aperture: AHB EMEM to MC Flush Register
+#define NV_DEVID_PPCS                            96
+
+// Device Aperture: MMU TLB registers for COP/AVP
+#define NV_DEVID_MMU_TLB                         97
+
+// Device Aperture: OVG engine
+#define NV_DEVID_VG                              98
+
+// Device Aperture: CSI
+#define NV_DEVID_CSI                             99
+
+// Device ID for COP
+#define NV_DEVID_AVP                             100
+
+// Device ID for MPCORE
+#define NV_DEVID_CPU                             101
+
+// Device Aperture: ULPI controller
+#define NV_DEVID_ULPI                            102
+
+// Device Aperture: ARM CONFIG registers
+#define NV_DEVID_ARM_CONFIG                      103
+
+// Device Aperture: ARM PL310 (L2 controller)
+#define NV_DEVID_ARM_PL310                       104
+
+// Device Aperture: PCIe
+#define NV_DEVID_PCIE                            105
+
+// Device Aperture: OWR (one wire)
+#define NV_DEVID_OWR                             106
+
+// Device Aperture: AVPUCQ
+#define NV_DEVID_AVPUCQ                          107
+
+// Device Aperture: AVPBSEA (obsolete)
+#define NV_DEVID_AVPBSEA                         108
+
+// Device Aperture: Sync NOR
+#define NV_DEVID_SNOR                            109
+
+// Device Aperture: SDMMC
+#define NV_DEVID_SDMMC                           110
+
+// Device Aperture: KFUSE
+#define NV_DEVID_KFUSE                           111
+
+// Device Aperture: CSITE
+#define NV_DEVID_CSITE                           112
+
+// Non-Aperture Interrupt: ARM Interprocessor Interrupt
+#define NV_DEVID_ARM_IPI                         113
+
+// Device Aperture: ARM Interrupts 0-31
+#define NV_DEVID_ARM_ICTLR                       114
+
+// Device Aperture: IOBIST
+#define NV_DEVID_IOBIST                          115
+
+// Device Aperture: SPEEDO
+#define NV_DEVID_SPEEDO                          116
+
+// Device Aperture: LA
+#define NV_DEVID_LA                              117
+
+// Device Aperture: VS
+#define NV_DEVID_VS                              118
+
+// Device Aperture: VCI
+#define NV_DEVID_VCI                             119
+
+// Device Aperture: APBIF
+#define NV_DEVID_APBIF                           120
+
+// Device Aperture: AHUB
+#define NV_DEVID_AHUB                            121
+
+// Device Aperture: DAM
+#define NV_DEVID_DAM                             122
+
+// ------------------------------------------------------------
+//    hw powergroups
+// ------------------------------------------------------------
+// Always On
+#define NV_POWERGROUP_AO                         0
+
+// Main
+#define NV_POWERGROUP_NPG                        1
+
+// CPU related blocks
+#define NV_POWERGROUP_CPU                        2
+
+// 3D graphics
+#define NV_POWERGROUP_TD                         3
+
+// Video encode engine blocks
+#define NV_POWERGROUP_VE                         4
+
+// PCIe
+#define NV_POWERGROUP_PCIE                       5
+
+// Video decoder
+#define NV_POWERGROUP_VDE                        6
+
+// MPEG encoder
+#define NV_POWERGROUP_MPE                        7
+
+// SW define for Power Group maximum
+#define NV_POWERGROUP_MAX                        8
+
+// non-mapped power group
+#define NV_POWERGROUP_INVALID                    0xffff
+
+// SW table for mapping power group define to register enums (NV_POWERGROUP_INVALID = no mapping)
+//  use as 'int table[NV_POWERGROUP_MAX] = { NV_POWERGROUP_ENUM_TABLE }'
+#define NV_POWERGROUP_ENUM_TABLE                 NV_POWERGROUP_INVALID, NV_POWERGROUP_INVALID, 0, 1, 2, 3, 4, 6
+
+// ------------------------------------------------------------
+//    relocation table data (stored in boot rom)
+// ------------------------------------------------------------
+// relocation table pointer stored at NV_RELOCATION_TABLE_OFFSET
+#define NV_RELOCATION_TABLE_PTR_OFFSET 64
+#define NV_RELOCATION_TABLE_SIZE  628
+#define NV_RELOCATION_TABLE_INIT \
+          0x00000001, 0x00020010, 0x00000000, 0x40000000, 0x00711010, \
+          0x00000000, 0x00000000, 0x00711010, 0x00000000, 0x00000000, \
+          0x00711010, 0x00000000, 0x00000000, 0x00711010, 0x00000000, \
+          0x00000000, 0x00711010, 0x00000000, 0x00000000, 0x00711010, \
+          0x00000000, 0x00000000, 0x00711010, 0x00000000, 0x00000000, \
+          0x00711010, 0x00000000, 0x00000000, 0x00711010, 0x00000000, \
+          0x00000000, 0x00531010, 0x00000000, 0x00000000, 0x00711010, \
+          0x00000000, 0x00000000, 0x00711010, 0x00000000, 0x00000000, \
+          0x005f1010, 0x00000000, 0x00000000, 0x00711010, 0x00000000, \
+          0x00000000, 0x00531010, 0x00000000, 0x00000000, 0x00711010, \
+          0x00000000, 0x00000000, 0x00711010, 0x00000000, 0x00000000, \
+          0x00711010, 0x00000000, 0x00000000, 0x00711010, 0x00000000, \
+          0x00000000, 0x00521010, 0x00000000, 0x00000000, 0x00041110, \
+          0x40000000, 0x00010000, 0x00041110, 0x40010000, 0x00010000, \
+          0x00041110, 0x40020000, 0x00010000, 0x00041110, 0x40030000, \
+          0x00010000, 0x00081010, 0x50000000, 0x00024000, 0x00091020, \
+          0x50040000, 0x00002000, 0x00721020, 0x50041000, 0x00001000, \
+          0x000a1020, 0x50042000, 0x00001000, 0x00681020, 0x50043000, \
+          0x00001000, 0x000f1270, 0x54040000, 0x00040000, 0x000d1140, \
+          0x54080000, 0x00040000, 0x00631140, 0x54080000, 0x00040000, \
+          0x000e1040, 0x540c0000, 0x00040000, 0x00121040, 0x54100000, \
+          0x00040000, 0x00111010, 0x54140000, 0x00040000, 0x00101230, \
+          0x54180000, 0x00040000, 0x00131310, 0x54200000, 0x00040000, \
+          0x00131310, 0x54240000, 0x00040000, 0x004d1210, 0x54280000, \
+          0x00040000, 0x004b1110, 0x542c0000, 0x00040000, 0x004c1010, \
+          0x54300000, 0x00040000, 0x00071110, 0x58000000, 0x02000000, \
+          0x00141010, 0x60000000, 0x00001000, 0x00151010, 0x60001000, \
+          0x00001000, 0x00161010, 0x60002000, 0x00001000, 0x00171010, \
+          0x60003000, 0x00001000, 0x004f1010, 0x60004000, 0x00000040, \
+          0x00551010, 0x60004040, 0x000000c0, 0x004f1110, 0x60004100, \
+          0x00000040, 0x00561010, 0x60004140, 0x00000008, 0x00561110, \
+          0x60004148, 0x00000008, 0x004f1210, 0x60004200, 0x00000040, \
+          0x004f1310, 0x60004300, 0x00000040, 0x001a1010, 0x60005000, \
+          0x00000008, 0x001a1010, 0x60005008, 0x00000008, 0x00541010, \
+          0x60005010, 0x00000040, 0x001a1010, 0x60005050, 0x00000008, \
+          0x001a1010, 0x60005058, 0x00000008, 0x001b1210, 0x60006000, \
+          0x00001000, 0x001c1010, 0x60007000, 0x0000001c, 0x001e1110, \
+          0x60008000, 0x00002000, 0x00571010, 0x60009000, 0x00000020, \
+          0x00571010, 0x60009020, 0x00000020, 0x00571010, 0x60009040, \
+          0x00000020, 0x00571010, 0x60009060, 0x00000020, 0x001f1010, \
+          0x6000a000, 0x00002000, 0x00581010, 0x6000b000, 0x00000020, \
+          0x00581010, 0x6000b020, 0x00000020, 0x00581010, 0x6000b040, \
+          0x00000020, 0x00581010, 0x6000b060, 0x00000020, 0x00581010, \
+          0x6000b080, 0x00000020, 0x00581010, 0x6000b0a0, 0x00000020, \
+          0x00581010, 0x6000b0c0, 0x00000020, 0x00581010, 0x6000b0e0, \
+          0x00000020, 0x00581010, 0x6000b100, 0x00000020, 0x00581010, \
+          0x6000b120, 0x00000020, 0x00581010, 0x6000b140, 0x00000020, \
+          0x00581010, 0x6000b160, 0x00000020, 0x00581010, 0x6000b180, \
+          0x00000020, 0x00581010, 0x6000b1a0, 0x00000020, 0x00581010, \
+          0x6000b1c0, 0x00000020, 0x00581010, 0x6000b1e0, 0x00000020, \
+          0x00201010, 0x6000c000, 0x00000400, 0x00591010, 0x6000c004, \
+          0x0000010c, 0x005b1010, 0x6000c150, 0x000000a6, 0x005c1010, \
+          0x6000c200, 0x00000004, 0x00211010, 0x6000c400, 0x00000400, \
+          0x00222010, 0x6000d000, 0x00000880, 0x00222010, 0x6000d080, \
+          0x00000880, 0x00222010, 0x6000d100, 0x00000880, 0x00222010, \
+          0x6000d180, 0x00000880, 0x00222010, 0x6000d200, 0x00000880, \
+          0x00222010, 0x6000d280, 0x00000880, 0x00222010, 0x6000d300, \
+          0x00000880, 0x00231010, 0x6000e000, 0x00001000, 0x00241010, \
+          0x6000f000, 0x00001000, 0x006b1010, 0x60010000, 0x00000100, \
+          0x002f1110, 0x60011000, 0x00001000, 0x00261260, 0x6001a000, \
+          0x00003c00, 0x00312010, 0x70000000, 0x00001000, 0x00731010, \
+          0x70001000, 0x00000100, 0x00731010, 0x70001100, 0x00000100, \
+          0x00731010, 0x70001300, 0x00000100, 0x00731010, 0x70001400, \
+          0x00000100, 0x00731010, 0x70001800, 0x00000200, 0x00741010, \
+          0x70001f00, 0x00000008, 0x00741010, 0x70001f08, 0x00000008, \
+          0x00321110, 0x70002000, 0x00000200, 0x00331010, 0x70002400, \
+          0x00000200, 0x00341110, 0x70002800, 0x00000100, 0x00341110, \
+          0x70002a00, 0x00000100, 0x00351210, 0x70006000, 0x00000040, \
+          0x00351210, 0x70006040, 0x00000040, 0x00361010, 0x70006100, \
+          0x00000100, 0x00351210, 0x70006200, 0x00000100, 0x00351210, \
+          0x70006300, 0x00000100, 0x00351210, 0x70006400, 0x00000100, \
+          0x00371210, 0x70008000, 0x00000100, 0x00381010, 0x70008500, \
+          0x00000100, 0x00391010, 0x70008a00, 0x00000200, 0x006d1010, \
+          0x70009000, 0x00001000, 0x003a1010, 0x7000a000, 0x00000100, \
+          0x003b1010, 0x7000b000, 0x00000100, 0x003c1210, 0x7000c000, \
+          0x00000100, 0x003d1010, 0x7000c100, 0x00000100, 0x00401010, \
+          0x7000c380, 0x00000080, 0x003c1210, 0x7000c400, 0x00000100, \
+          0x003c1210, 0x7000c500, 0x00000100, 0x006a1010, 0x7000c600, \
+          0x00000050, 0x00411110, 0x7000d000, 0x00000200, 0x003e1110, \
+          0x7000d400, 0x00000200, 0x003e1110, 0x7000d600, 0x00000200, \
+          0x003e1110, 0x7000d800, 0x00000200, 0x003e1110, 0x7000da00, \
+          0x00000200, 0x00421100, 0x7000e000, 0x00000100, 0x00431100, \
+          0x7000e200, 0x00000100, 0x00441200, 0x7000e400, 0x00000200, \
+          0x000b1110, 0x7000f000, 0x00000400, 0x000c1210, 0x7000f400, \
+          0x00000400, 0x00451110, 0x7000f800, 0x00000400, 0x006f1010, \
+          0x7000fc00, 0x00000400, 0x00751010, 0x70010000, 0x00002000, \
+          0x00701010, 0x70040000, 0x00040000, 0x00691050, 0x80000000, \
+          0x40000000, 0x005e1010, 0x80000000, 0x40000000, 0x00481010, \
+          0xc3000000, 0x01000000, 0x00601010, 0xc4000000, 0x00010000, \
+          0x00491510, 0xc5000000, 0x00004000, 0x00491610, 0xc5004000, \
+          0x00004000, 0x00491710, 0xc5008000, 0x00004000, 0x006e2010, \
+          0xc8000000, 0x00000200, 0x006e2010, 0xc8000200, 0x00000200, \
+          0x006e2010, 0xc8000400, 0x00000200, 0x006e2010, 0xc8000600, \
+          0x00000200, 0x00051110, 0xd0000000, 0x10000000, 0x00060010, \
+          0xe0000000, 0x08000000, 0x00060010, 0xe8000000, 0x08000000, \
+          0x00611010, 0xf000f000, 0x00001000, 0x00000000, 0x81b00108, \
+          0x81b0020e, 0x81b00306, 0x81b0040f, 0x81b0050a, 0x81b00601, \
+          0x81b00707, 0x81b00804, 0x81b0090b, 0x83100a19, 0x81b00b0d, \
+          0x81b00c00, 0x83400d16, 0x81b00e03, 0x83100f18, 0x81b01005, \
+          0x81b01109, 0x81b01202, 0x81b0130c, 0x8340141f, 0xc3401900, \
+          0xa3401901, 0xc3401902, 0xa3401903, 0x83401e04, 0x83401f05, \
+          0x83402106, 0x83402207, 0x83402308, 0x83402509, 0x8340260a, \
+          0x8340270b, 0x8340280c, 0xa2f02c04, 0xc2f02c05, 0xc2f02c06, \
+          0xa2f02c07, 0xa2f02d1c, 0xc2f02d1d, 0x8310321e, 0x8310331f, \
+          0x82f03600, 0x82f03701, 0x83103909, 0x83103a0a, 0xa3103c0b, \
+          0xc3103c0c, 0xa2f03d1b, 0xc3103d1d, 0xa2f0421a, 0xc310421c, \
+          0x83105716, 0x83105800, 0x83105901, 0x83105a02, 0x83105b03, \
+          0x83105c17, 0x83405d17, 0x83405e19, 0x82f05f19, 0x82f06112, \
+          0x82f0620b, 0x82f06309, 0x82f0630a, 0x82f0630c, 0x82f06308, \
+          0x82f06311, 0x83406410, 0x83406418, 0x83406c11, 0x83206c00, \
+          0x83206c12, 0x83306c00, 0x83306c12, 0x83106d0d, 0x83206d03, \
+          0x83206d04, 0x83306d03, 0x83306d04, 0x82f06e0d, 0x83206e02, \
+          0x83206e01, 0x83306e01, 0x83306e02, 0x82f06f03, 0x83206f06, \
+          0x83206f05, 0x83306f05, 0x83306f06, 0x83107004, 0x83207008, \
+          0x83307008, 0x83107105, 0x83207109, 0x83307109, 0x83107214, \
+          0x83207211, 0x83307211, 0x8310730e, 0x8320730a, 0x8330730a, \
+          0x8340741a, 0x8320740e, 0x8330740e, 0x8340751b, 0x8320750f, \
+          0x8330750f, 0x82f07618, 0x82f07716, 0x82f07810, 0x83507900, \
+          0x83107b0f, 0x83107c06, 0x83207c0c, 0x83307c0c, 0x83107d08, \
+          0x83207d0b, 0x83307d0b, 0x83107e07, 0x83207e07, 0x83307e07, \
+          0x83407f14, 0x83207f0d, 0x83307f0d, 0x8340801c, 0x83208010, \
+          0x83308010, 0x82f0811e, 0x83108215, 0x8310831b, 0x83408412, \
+          0x83408513, 0x8340861d, 0x82f08702, 0x83408815, 0x83408a0d, \
+          0x83408b0e, 0x83509002, 0x83509003, 0x83509004, 0x82f09217, \
+          0x82f09414, 0x82f09515, 0x83509601, 0x82f0970e, 0x82f0980f, \
+          0x82f09913, 0x82f09a1f, 0x00000000
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/avp.h b/arch/arm/mach-tegra/nv/include/avp.h
new file mode 100644
index 000000000000..249a28cd44db
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/avp.h
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_AVP_H
+#define INCLUDED_AVP_H
+
+#include "ap15/arictlr.h"
+#include "ap15/artimer.h"
+// FIXME: get the ararmev header
+
+// 3 controllers in contiguous memory starting at INTERRUPT_BASE, each
+// controller's aperture is INTERRUPT_SIZE large
+#define INTERRUPT_BASE 0x60004000
+#define INTERRUPT_SIZE 0x100
+#define INTERRUPT_NUM_CONTROLLERS 3
+
+#define INTERRUPT_PENDING( ctlr ) \
+    (INTERRUPT_BASE + ((ctlr) * INTERRUPT_SIZE) + ICTLR_VIRQ_COP_0)
+
+#define INTERRUPT_SET( ctlr ) \
+    (INTERRUPT_BASE + ((ctlr) * INTERRUPT_SIZE) + ICTLR_COP_IER_SET_0)
+
+#define INTERRUPT_CLR( ctlr ) \
+    (INTERRUPT_BASE + ((ctlr) * INTERRUPT_SIZE) + ICTLR_COP_IER_CLR_0)
+
+#define OSC_CTRL        ( 0x60006000 + 0x50 )
+#define OSC_FREQ_DET    ( 0x60006000 + 0x58 )
+#define OSC_DET_STATUS  ( 0x60006000 + 0x5C )
+
+#define TIMER_USEC      ( 0x60005010 )
+#define TIMER_CFG       ( 0x60005014 )
+#define TIMER_0_BASE    ( 0x60005000 )
+#define TIMER_0         ( TIMER_0_BASE + TIMER_TMR_PTV_0 )
+#define TIMER_0_CLEAR   ( TIMER_0_BASE + TIMER_TMR_PCR_0 )
+#define TIMER_1_BASE    ( 0x60005008 )
+#define TIMER_1         ( TIMER_1_BASE + TIMER_TMR_PTV_0 )
+#define TIMER_1_CLEAR   ( TIMER_1_BASE + TIMER_TMR_PCR_0 )
+
+#define CLOCK_RST_LO    (0x60006004)
+#define CLOCK_CTLR_HI   (0x60006014)
+#define CLOCK_CTLR_LO   (0x60006010)
+
+#define CACHE_CTLR      (0x6000C000)
+#define CACHE_CONTROL_0         (0x0)
+
+#define PPI_INTR_ID_TIMER_0     (0)
+#define PPI_INTR_ID_TIMER_1     (1)
+#define PPI_INTR_ID_TIMER_2     (9)
+#define PPI_INTR_ID_TIMER_3     (10)
+
+/* flow controller */
+#define FLOW_CONTROLLER     (0x60007004)
+
+/* exception vectors */
+#define VECTOR_BASE             ( 0x6000F200 )
+#define VECTOR_RESET            ( VECTOR_BASE + 0 )
+#define VECTOR_UNDEF            ( VECTOR_BASE + 4 )
+#define VECTOR_SWI              ( VECTOR_BASE + 8 )
+#define VECTOR_PREFETCH_ABORT   ( VECTOR_BASE + 12 )
+#define VECTOR_DATA_ABORT       ( VECTOR_BASE + 16 )
+#define VECTOR_IRQ              ( VECTOR_BASE + 24 )
+#define VECTOR_FIQ              ( VECTOR_BASE + 28 )
+
+#define MODE_DISABLE_INTR 0xc0
+#define MODE_USR 0x10
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_ABT 0x17
+#define MODE_UND 0x1B
+#define MODE_SYS 0x1F
+
+#define AP15_CACHE_LINE_SIZE            32
+
+#define AP15_APB_L2_CACHE_BASE 0x7000e800 
+#define AP15_APB_CLK_RST_BASE  0x60006000
+#define AP15_APB_MISC_BASE     0x70000000
+
+#define AP10_APB_CLK_RST_BASE  0x60006000
+#define AP10_APB_MISC_BASE     0x70000000
+
+#define MMU_TLB_BASE              0xf000f000
+#define MMU_TLB_CACHE_WINDOW_0    0x40
+#define MMU_TLB_CACHE_OPTIONS_0   0x44
+
+#define AP15_PINMUX_CFG_CTL_0   0x70000024
+#define AP15_AVP_JTAG_ENABLE    0xC0
+
+#define PMC_SCRATCH22_REG_LP0   0x7000e4a8
+
+#define AVP_WDT_RESET   0x2F00BAD0
+
+/* Cached to uncached offset for AVP
+ *
+ * Hardware has uncached remap aperture for AVP as AVP doesn't have MMU
+ * but still has cache (named COP cache).
+ *
+ * This aperture moved between AP15 and AP20.
+ */
+#define AP15_CACHED_TO_UNCACHED_OFFSET 0x90000000
+#define AP20_CACHED_TO_UNCACHED_OFFSET 0x80000000
+
+#define APXX_EXT_MEM_START      0x00000000
+#define APXX_EXT_MEM_END        0x40000000
+
+#define APXX_MMIO_START         0x40000000
+#define APXX_MMIO_END           0xFFF00000
+
+#define TXX_EXT_MEM_START       0x80000000
+#define TXX_EXT_MEM_END         0xc0000000
+
+#define TXX_MMIO_START          0x40000000
+#define TXX_MMIO_END            0x80000000
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/linux/nvec_ioctls.h b/arch/arm/mach-tegra/nv/include/linux/nvec_ioctls.h
new file mode 100644
index 000000000000..ecc50d0436d0
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/linux/nvec_ioctls.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NVEC_IOCTLS_H
+#define NVEC_IOCTLS_H
+
+
+/* When we trap into the kernel, the majority of the ioctls
+ * are handled by the Generic handler, which is automatically
+ * generated by the IDL compiler.  
+ *
+ */
+
+typedef enum
+{
+    NvECKernelIoctls_Generic = 8000,
+    NvECKernelIoctls_ForceWord = 0x7FFFFFFF,
+} NvECKernelIoctls;
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/linux/nvos_ioctl.h b/arch/arm/mach-tegra/nv/include/linux/nvos_ioctl.h
new file mode 100644
index 000000000000..63aacd93b1c0
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/linux/nvos_ioctl.h
@@ -0,0 +1,115 @@
+/*
+ * arch/arm/mach-tegra/include/linux/nvos_ioctl.h
+ *
+ * structure declarations for NvOs user-space ioctls
+ *
+ * Copyright (c) 2009, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/ioctl.h>
+#include "nvos.h"
+#include "nvcommon.h"
+
+#ifndef NVOS_LINUX_IOCTLS_H
+#define NVOS_LINUX_IOCTLS_H
+
+typedef struct
+{
+    NvU32 IoctlCode;
+    NvU32 InBufferSize;
+    NvU32 InOutBufferSize;
+    NvU32 OutBufferSize;
+    void *pBuffer;
+} NV_ALIGN(4) NvOsIoctlParams;
+
+typedef struct
+{
+    NvOsSemaphoreHandle sem;
+    NvU32 value;
+    NvError error;
+} NV_ALIGN(4) NvOsSemaphoreIoctlParams;
+
+typedef struct
+{
+    NvOsSemaphoreHandle hOrig;
+    NvOsSemaphoreHandle hNew;
+    NvError             Error;
+} NV_ALIGN(4) NvOsSemaphoreUnmarshalParams;
+
+typedef struct
+{
+    NvOsSemaphoreHandle hOrig;
+    NvOsSemaphoreHandle hNew;
+    NvError             Error;
+} NV_ALIGN(4) NvOsSemaphoreCloneParams;
+
+typedef struct
+{
+    NvU32 nIrqs;
+    const NvU32 *Irqs;
+    NvOsSemaphoreHandle *SemaphoreList;
+    NvError errCode;
+    NvUPtr  kernelHandle;
+} NV_ALIGN(4) NvOsInterruptRegisterParams;
+
+typedef struct
+{
+    NvUPtr  handle;
+    NvU32   arg;
+    NvError errCode;
+} NV_ALIGN(4) NvOsInterruptOpParams;
+
+typedef struct
+{
+    NvUPtr handle;
+    NvU32 mask;
+} NV_ALIGN(4) NvOsInterruptMaskParams;
+
+typedef struct
+{
+    NvU32 size;
+    char *text;
+} NV_ALIGN(4) NvOsDebugStringParams;
+
+typedef struct
+{
+    NvOsPhysAddr base;
+    NvU32 size;
+} NV_ALIGN(4) NvOsMemRangeParams;
+
+#define NV_IOCTL_SEMAPHORE_CREATE   _IOWR('N', 0x20, NvOsSemaphoreIoctlParams)
+#define NV_IOCTL_SEMAPHORE_DESTROY  _IOW('N', 0x21, NvOsSemaphoreHandle)
+#define NV_IOCTL_SEMAPHORE_CLONE \
+    _IOWR('N', 0x22, NvOsSemaphoreCloneParams)
+#define NV_IOCTL_SEMAPHORE_UNMARSHAL \
+    _IOWR('N', 0x23, NvOsSemaphoreUnmarshalParams)
+#define NV_IOCTL_SEMAPHORE_SIGNAL   _IOW('N', 0x24, NvOsSemaphoreHandle)
+#define NV_IOCTL_SEMAPHORE_WAIT     _IOW('N', 0x25, NvOsSemaphoreHandle)
+#define NV_IOCTL_SEMAPHORE_WAIT_TIMEOUT \
+    _IOW('N', 0x26, NvOsSemaphoreIoctlParams)
+#define NV_IOCTL_INTERRUPT_REGISTER \
+    _IOWR('N', 0x27, NvOsInterruptRegisterParams)
+#define NV_IOCTL_INTERRUPT_UNREGISTER   _IOWR('N', 0x28, NvOsInterruptOpParams)
+#define NV_IOCTL_INTERRUPT_ENABLE       _IOWR('N', 0x29, NvOsInterruptOpParams)
+#define NV_IOCTL_INTERRUPT_DONE         _IOWR('N', 0x2A, NvOsInterruptOpParams)
+#define NV_IOCTL_INTERRUPT_MASK     _IOWR('N', 0x2B, NvOsInterruptOpParams)
+#define NV_IOCTL_GLOBAL_LOCK        _IO('N', 0x2C)
+#define NV_IOCTL_GLOBAL_UNLOCK      _IO('N', 0x2D)
+#define NV_IOCTL_DEBUG_STRING       _IOW('N', 0x2E, NvOsDebugStringParams)
+#define NV_IOCTL_MEMORY_RANGE       _IOW('N', 0x2F, NvOsMemRangeParams)
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/linux/nvrpc_ioctl.h b/arch/arm/mach-tegra/nv/include/linux/nvrpc_ioctl.h
new file mode 100755
index 000000000000..594e1f5d4e94
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/linux/nvrpc_ioctl.h
@@ -0,0 +1,102 @@
+/*
+ * arch/arm/mach-tegra/include/linux/nvrpc_ioctl.h
+ *
+ * structure declarations for nvrpc user-space ioctls
+ *
+ * Copyright (c) 2009-2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#if !defined(__KERNEL__)
+#define __user
+#endif
+
+#ifndef _MACH_TEGRA_NVRPC_IOCTL_H_
+#define _MACH_TEGRA_NVRPC_IOCTL_H_
+
+struct nvrpc_handle_param {
+	__u32 handle;
+	__u32 param;
+	__u32 ret_val;              /* operation status */
+};
+
+struct nvrpc_open_params {
+	__u32 rm_handle;            /* rm device handle */
+	__u32 port_name_size;       /* port name buffer size */
+	__u32 sem;                  /* receive semaphore handle */
+	__u32 transport_handle;     /* transport handle */
+	__u32 ret_val;              /* operation status */
+	unsigned long port_name;    /* port name */
+};
+
+struct nvrpc_set_queue_depth_params {
+	__u32 transport_handle;     /* transport handle */
+	__u32 max_queue_depth;      /* maximum number of message in Queue */
+	__u32 max_message_size;     /* maximum size of the message in bytes */
+	__u32 ret_val;              /* operation status */
+};
+
+struct nvrpc_msg_params {
+	__u32 transport_handle;     /* transport handle */
+	__u32 max_message_size;     /* maximum size of the message in bytes */
+	__u32 params;               /* timeout in ms */
+	__u32 ret_val;              /* operation status */
+	unsigned long msg_buffer;
+};
+
+#define NVRPC_IOC_MAGIC 'N'
+
+#define NVRPC_IOCTL_INIT                    \
+	_IOWR(NVRPC_IOC_MAGIC, 0x30, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_OPEN                    \
+	_IOWR(NVRPC_IOC_MAGIC, 0x31, struct nvrpc_open_params)
+#define NVRPC_IOCTL_GET_PORTNAME            \
+	_IOWR(NVRPC_IOC_MAGIC, 0x32, struct nvrpc_open_params)
+#define NVRPC_IOCTL_CLOSE                   \
+	_IOWR(NVRPC_IOC_MAGIC, 0x33, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_DEINIT                   \
+	_IOWR(NVRPC_IOC_MAGIC, 0x34, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_WAIT_FOR_CONNECT        \
+	_IOWR(NVRPC_IOC_MAGIC, 0x35, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_CONNECT                 \
+	_IOWR(NVRPC_IOC_MAGIC, 0x36, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_SET_QUEUE_DEPTH         \
+	_IOWR(NVRPC_IOC_MAGIC, 0x37, struct nvrpc_set_queue_depth_params)
+#define NVRPC_IOCTL_SEND_MSG                \
+	_IOWR(NVRPC_IOC_MAGIC, 0x38, struct nvrpc_msg_params)
+#define NVRPC_IOCTL_SEND_MSG_LP0            \
+	_IOWR(NVRPC_IOC_MAGIC, 0x39, struct nvrpc_msg_params)
+#define NVRPC_IOCTL_RECV_MSG           \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3A, struct nvrpc_msg_params)
+#define NVRPC_IOCTL_XPC_INIT                \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3B, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_ACQUIRE             \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3C, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_RELEASE             \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3D, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_GET_MSG             \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3E, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_SEND_MSG            \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3F, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_DESTROY             \
+	_IOWR(NVRPC_IOC_MAGIC, 0x40, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_CREATE              \
+	_IOWR(NVRPC_IOC_MAGIC, 0x41, struct nvrpc_handle_param)
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/mach/nvrm_linux.h b/arch/arm/mach-tegra/nv/include/mach/nvrm_linux.h
new file mode 100644
index 000000000000..cdf00221dc48
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/mach/nvrm_linux.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2008-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*  This header file defines shared structures used by Linux drivers
+ *  integrating with Tegra NvRM.
+ */
+
+#ifndef INCLUDED_nvrm_linux_H
+#define INCLUDED_nvrm_linux_H
+
+/* nvcommon.h exepcts NV_DEBUG to be defined */
+#ifndef NV_DEBUG
+#ifdef DEBUG
+#define NV_DEBUG DEBUG
+#else
+#define NV_DEBUG 0
+#endif
+#endif 
+
+#include <nvrm_init.h>
+#include <nvrm_i2c.h>
+#include <nvrm_owr.h>
+#include <nvrm_gpio.h>
+#include <nvodm_query_pinmux.h>
+#include <nvodm_query.h>
+#include "nvddk_usbphy.h"
+
+extern NvRmDeviceHandle s_hRmGlobal;
+extern NvRmGpioHandle s_hGpioGlobal;
+
+int tegra_get_partition_info_by_name(const char *PartName,
+	NvU64 *pSectorStart, NvU64 *pSectorLength, NvU32 *pSectorSize);
+
+int tegra_get_partition_info_by_num(int PartitionNum, char **pName,
+	NvU64 *pSectorStart, NvU64 *pSectorEnd, NvU32 *pSectorSize);
+
+int tegra_was_boot_device(const char *pBootDev);
+
+NvU32 NvRmDmaUnreservedChannels(void);
+
+#ifndef CONFIG_SERIAL_TEGRA_UARTS
+#define TEGRA_SYSTEM_DMA_CH_UART 0
+#else
+#define TEGRA_SYSTEM_DMA_CH_UART (2*CONFIG_SERIAL_TEGRA_UARTS)
+#endif
+
+#ifdef CONFIG_TEGRA_SYSTEM_DMA
+#define TEGRA_SYSTEM_DMA_CH_NUM (1 + TEGRA_SYSTEM_DMA_CH_UART)
+#else
+#define TEGRA_SYSTEM_DMA_CH_NUM (0)
+#endif
+
+/* DMA channels available to system DMA driver */
+#define TEGRA_SYSTEM_DMA_CH_MIN NvRmDmaUnreservedChannels()
+#define TEGRA_SYSTEM_DMA_CH_MAX \
+	(TEGRA_SYSTEM_DMA_CH_MIN+TEGRA_SYSTEM_DMA_CH_NUM)
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/mach/nvrpc.h b/arch/arm/mach-tegra/nv/include/mach/nvrpc.h
new file mode 100755
index 000000000000..594e1f5d4e94
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/mach/nvrpc.h
@@ -0,0 +1,102 @@
+/*
+ * arch/arm/mach-tegra/include/linux/nvrpc_ioctl.h
+ *
+ * structure declarations for nvrpc user-space ioctls
+ *
+ * Copyright (c) 2009-2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#if !defined(__KERNEL__)
+#define __user
+#endif
+
+#ifndef _MACH_TEGRA_NVRPC_IOCTL_H_
+#define _MACH_TEGRA_NVRPC_IOCTL_H_
+
+struct nvrpc_handle_param {
+	__u32 handle;
+	__u32 param;
+	__u32 ret_val;              /* operation status */
+};
+
+struct nvrpc_open_params {
+	__u32 rm_handle;            /* rm device handle */
+	__u32 port_name_size;       /* port name buffer size */
+	__u32 sem;                  /* receive semaphore handle */
+	__u32 transport_handle;     /* transport handle */
+	__u32 ret_val;              /* operation status */
+	unsigned long port_name;    /* port name */
+};
+
+struct nvrpc_set_queue_depth_params {
+	__u32 transport_handle;     /* transport handle */
+	__u32 max_queue_depth;      /* maximum number of message in Queue */
+	__u32 max_message_size;     /* maximum size of the message in bytes */
+	__u32 ret_val;              /* operation status */
+};
+
+struct nvrpc_msg_params {
+	__u32 transport_handle;     /* transport handle */
+	__u32 max_message_size;     /* maximum size of the message in bytes */
+	__u32 params;               /* timeout in ms */
+	__u32 ret_val;              /* operation status */
+	unsigned long msg_buffer;
+};
+
+#define NVRPC_IOC_MAGIC 'N'
+
+#define NVRPC_IOCTL_INIT                    \
+	_IOWR(NVRPC_IOC_MAGIC, 0x30, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_OPEN                    \
+	_IOWR(NVRPC_IOC_MAGIC, 0x31, struct nvrpc_open_params)
+#define NVRPC_IOCTL_GET_PORTNAME            \
+	_IOWR(NVRPC_IOC_MAGIC, 0x32, struct nvrpc_open_params)
+#define NVRPC_IOCTL_CLOSE                   \
+	_IOWR(NVRPC_IOC_MAGIC, 0x33, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_DEINIT                   \
+	_IOWR(NVRPC_IOC_MAGIC, 0x34, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_WAIT_FOR_CONNECT        \
+	_IOWR(NVRPC_IOC_MAGIC, 0x35, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_CONNECT                 \
+	_IOWR(NVRPC_IOC_MAGIC, 0x36, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_SET_QUEUE_DEPTH         \
+	_IOWR(NVRPC_IOC_MAGIC, 0x37, struct nvrpc_set_queue_depth_params)
+#define NVRPC_IOCTL_SEND_MSG                \
+	_IOWR(NVRPC_IOC_MAGIC, 0x38, struct nvrpc_msg_params)
+#define NVRPC_IOCTL_SEND_MSG_LP0            \
+	_IOWR(NVRPC_IOC_MAGIC, 0x39, struct nvrpc_msg_params)
+#define NVRPC_IOCTL_RECV_MSG           \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3A, struct nvrpc_msg_params)
+#define NVRPC_IOCTL_XPC_INIT                \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3B, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_ACQUIRE             \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3C, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_RELEASE             \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3D, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_GET_MSG             \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3E, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_SEND_MSG            \
+	_IOWR(NVRPC_IOC_MAGIC, 0x3F, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_DESTROY             \
+	_IOWR(NVRPC_IOC_MAGIC, 0x40, struct nvrpc_handle_param)
+#define NVRPC_IOCTL_XPC_CREATE              \
+	_IOWR(NVRPC_IOC_MAGIC, 0x41, struct nvrpc_handle_param)
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvassert.h b/arch/arm/mach-tegra/nv/include/nvassert.h
new file mode 100644
index 000000000000..53b0afd83cb1
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvassert.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+#ifndef INCLUDED_NVASSERT_H
+#define INCLUDED_NVASSERT_H
+
+#include "nvcommon.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/** NvOsBreakPoint - break into debugger.
+ * @param  file is the file name (usually from the built-in __FILE__ macro)
+ * in which the debug assertion message is to refer. If NULL, no debug assertion
+ * message is printed.
+ * @param line is the line number within 'file' at which the assertion occurred.
+ * @param condition is the assertion condition that failed. If NULL, no condition
+ * string will be displayed.
+ */
+void
+NvOsBreakPoint(const char* file, NvU32 line, const char* condition);
+
+/**
+ * Macro to break into debugger without printing an assertion message.
+ */
+#define NV_OS_BREAK_POINT() NvOsBreakPoint(NULL, 0, NULL)
+
+
+/**
+ * Runtime condition check with break into debugger if the assert fails.
+ * Compiles out in release builds.
+ *
+ * We provide two variants of assert: one that prints out the failing assert
+ * condition (the "#x" string in the macro), and another that doesn't.  By
+ * default, we print the condition string in x86 builds only.  The assumption
+ * is that x86 systems have boatloads of memory and can afford to put all these
+ * extra strings in the binary, whereas other systems are our target systems
+ * and tend to have less memory available.  Also, we want to be careful about
+ * anything that might make it take too long to transfer system images over to
+ * the target system.
+ *
+ * We also allow individual developers to override this default behavior,
+ * either globally or on a per-source-file basis.  To do this, set
+ * NV_ASSERT_PROVIDE_CONDITION_STRING to either 0 or 1, either in your own
+ * source code, in your own makefile, or by uncommenting the lines below.
+ */
+
+#if !defined(NV_ASSERT)
+#if NV_DEBUG
+
+// Uncomment me to override default assert behavior
+//#define NV_ASSERT_PROVIDE_CONDITION_STRING 0
+//#define NV_ASSERT_PROVIDE_CONDITION_STRING 1
+
+// Default behavior: provide condition string in x86 builds only
+#if !defined(NV_ASSERT_PROVIDE_CONDITION_STRING)
+#if NVCPU_IS_X86
+#define NV_ASSERT_PROVIDE_CONDITION_STRING 1
+#else
+#define NV_ASSERT_PROVIDE_CONDITION_STRING 0
+#endif
+#endif
+
+#if NV_ASSERT_PROVIDE_CONDITION_STRING
+#define NV_ASSERT(x) \
+    do { \
+        if (!(x)) \
+        { \
+            /* print message and break into the debugger */ \
+            NvOsBreakPoint(__FILE__, __LINE__, #x); \
+        } \
+    } while( 0 )
+#else // NV_ASSERT_PROVIDE_CONDITION_STRING
+#define NV_ASSERT(x) \
+    do { \
+        if (!(x)) \
+        { \
+            /* print message and break into the debugger */ \
+            NvOsBreakPoint(__FILE__, __LINE__, NULL); \
+        } \
+    } while( 0 )
+#endif // NV_ASSERT_PROVIDE_CONDITION_STRING
+
+#else // NV_DEBUG
+#define NV_ASSERT(x) do {} while(0)
+#endif // NV_DEBUG
+#endif //!defined(NV_ASSERT)
+
+/**
+ * NV_CT_ASSERT: compile-time assert for constant values.
+ *
+ * This works by declaring a function with an array parameter.  If the
+ * assert condition is true, then the array size will be 1, otherwise
+ * the array size will be -1, which will generate a compilation error.
+ *
+ * No code should be generated by this macro.
+ *
+ * Three levels of macros are needed to properly expand the line number.
+ *
+ * This macro was taken in spirit from:
+ *     //sw/main/drivers/common/inc/nvctassert.h
+ */
+#define NV_CT_ASSERT( x )            NV_CT_ASSERT_I( x, __LINE__ )
+#define NV_CT_ASSERT_I( x,line )     NV_CT_ASSERT_II( x, line )
+#define NV_CT_ASSERT_II( x, line ) \
+    void compile_time_assertion_failed_in_line_##line( \
+        int _compile_time_assertion_failed_in_line_##line[(x) ? 1 : -1])
+
+/**
+ * A macro to assert (rather than check) that something succeeded.  The use of
+ * this macro is strongly discouraged in any production-worthy code.  It is,
+ * however, a step up from ignoring the NvError return code of a function, and
+ * it is trivial to use and harmless to your release builds.  If everyone uses
+ * it, it also makes it easy to search the tree for missing error handling code.
+ *
+ * In this macro, we don't worry about the stack space wasted from multiple
+ * NvError locals in a single function -- production-quality code shouldn't be
+ * using this macro in the first place.
+ */
+#if NV_DEBUG
+#define NV_ASSERT_SUCCESS(expr) \
+    do \
+    { \
+        NvError AssertSuccessError = (expr); \
+        NV_ASSERT(AssertSuccessError == NvSuccess); \
+    } while (0)
+#else
+#define NV_ASSERT_SUCCESS(expr) \
+    do \
+    { \
+        (void)(expr); \
+    } while (0)
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_NVASSERT_H
diff --git a/arch/arm/mach-tegra/nv/include/nvbootargs.h b/arch/arm/mach-tegra/nv/include/nvbootargs.h
new file mode 100644
index 000000000000..908c26f0ea52
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvbootargs.h
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVBOOTARGS_H
+#define INCLUDED_NVBOOTARGS_H
+
+/**
+ * This defines the basic bootarg structure and keys for use with
+ * NvOsBootArgGet and NvOsBootArgSet.
+ */
+
+#include "nvcommon.h"
+
+/** 
+ * The maximum number of memory handles that may be preserved across the
+ * bootloader-to-OS transition.  @see NvRmBootArg_PreservedMemHandle.
+ */
+#define NV_BOOTARGS_MAX_PRESERVED_MEMHANDLES 3
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* accessor for various boot arg classes, see NvOsBootArg* */
+typedef enum
+{
+    NvBootArgKey_Rm = 0x1,
+    NvBootArgKey_Display,
+    NvBootArgKey_Framebuffer,
+    NvBootArgKey_ChipShmoo,
+    NvBootArgKey_ChipShmooPhys,
+    NvBootArgKey_Carveout,
+    NvBootArgKey_WarmBoot,
+    NvBootArgKey_PreservedMemHandle_0 = 0x10000,
+    NvBootArgKey_PreservedMemHandle_Num = (NvBootArgKey_PreservedMemHandle_0 +
+                                         NV_BOOTARGS_MAX_PRESERVED_MEMHANDLES),
+    NvBootArgKey_Force32 = 0x7FFFFFFF,
+} NvBootArgKey;
+
+/**
+ * Resource Manager boot args.
+ *
+ * Nothing here yet.
+ */
+typedef struct NvBootArgsRmRec
+{
+    NvU32 reserved;
+} NvBootArgsRm;
+
+/**
+ * Carveout boot args, which define the physical memory location of the GPU
+ * carved-out memory region(s).
+ */
+typedef struct NvBootArgsCarveoutRec
+{
+    NvUPtr base;
+    NvU32 size;
+} NvBootArgsCarveout;
+
+/**
+ * Warmbootloader boot args. This structure only contains
+ * a mem handle key to preserve the warm bootloader
+ * across the bootloader->os transition
+ */
+typedef struct NvBootArgsWarmbootRec
+{
+    NvU32 MemHandleKey;
+} NvBootArgsWarmboot;
+
+/**
+ * PreservedMemHandle boot args, indexed by PreservedMemHandle_0 + n.
+ * All values n from 0 to the first value which does not return NvSuccess will
+ * be quered at RM initialization in the OS environment.  If present, a new
+ * memory handle for the physical region specified will be created.
+ * This allows physical memory allocations (e.g., for framebuffers) to persist
+ * between the bootloader and operating system.  Only carveout and IRAM
+ * allocations may be preserved with this interface.
+ */
+typedef struct NvBootArgsPreservedMemHandleRec
+{
+    NvUPtr  Address;
+    NvU32   Size;
+} NvBootArgsPreservedMemHandle;
+
+
+/**
+ * Display boot args, indexed by NvBootArgKey_Display.
+ *
+ * The bootloader may have a splash screen. This will flag which controller
+ * and device was used for the splash screen so the device will not be
+ * reinitialized (which causes visual artifacts).
+ */
+typedef struct NvBootArgsDisplayRec
+{
+    /* which controller is initialized */
+    NvU32 Controller;
+
+    /* index into the ODM device list of the boot display device */
+    NvU32 DisplayDeviceIndex;
+
+    /* set to NV_TRUE if the display has been initialized */
+    NvBool bEnabled;
+} NvBootArgsDisplay;
+
+/**
+ * Framebuffer boot args, indexed by NvBootArgKey_Framebuffer
+ *
+ * A framebuffer may be shared between the bootloader and the
+ * operating system display driver.  When this key is present,
+ * a preserved memory handle for the framebuffer must also
+ * be present, to ensure that no display corruption occurs
+ * during the transition.
+ */
+typedef struct NvBootArgsFramebufferRec
+{
+    /*  The key used for accessing the preserved memory handle */
+    NvU32 MemHandleKey;
+    /*  Total memory size of the framebuffer */
+    NvU32 Size;
+    /*  Color format of the framebuffer, cast to a U32  */
+    NvU32 ColorFormat;
+    /*  Width of the framebuffer, in pixels  */
+    NvU16 Width;
+    /*  Height of each surface in the framebuffer, in pixels  */
+    NvU16 Height;
+    /*  Pitch of a framebuffer scanline, in bytes  */
+    NvU16 Pitch;
+    /*  Surface layout of the framebuffer, cast to a U8 */
+    NvU8  SurfaceLayout;
+    /*  Number of contiguous surfaces of the same height in the
+     *  framebuffer, if multi-buffering.  Each surface is
+     *  assumed to begin at Pitch * Height bytes from the
+     *  previous surface.  */
+    NvU8  NumSurfaces;
+} NvBootArgsFramebuffer;
+
+/**
+ * Chip chatcterization shmoo data indexed by NvBootArgKey_ChipShmoo
+ */
+typedef struct NvBootArgsChipShmooRec
+{
+    // The key used for accessing the preserved memory handle of packed
+    // charcterization tables 
+    NvU32 MemHandleKey;
+
+    // Offset and size of each unit in the packed buffer
+    NvU32 CoreShmooVoltagesListOffset;
+    NvU32 CoreShmooVoltagesListSize;
+
+    NvU32 CoreScaledLimitsListOffset;
+    NvU32 CoreScaledLimitsListSize;
+
+    NvU32 OscDoublerListOffset;
+    NvU32 OscDoublerListSize;
+
+    NvU32 SKUedLimitsOffset;
+    NvU32 SKUedLimitsSize;
+
+    NvU32 CpuShmooVoltagesListOffset;
+    NvU32 CpuShmooVoltagesListSize;
+
+    NvU32 CpuScaledLimitsOffset;
+    NvU32 CpuScaledLimitsSize;
+
+    // Misc charcterization settings
+    NvU16 CoreCorner;
+    NvU16 CpuCorner;
+    NvU32 Dqsib;
+    NvU32 SvopLowVoltage;
+    NvU32 SvopLowSetting;
+    NvU32 SvopHighSetting;
+} NvBootArgsChipShmoo;
+
+/**
+ * Chip chatcterization shmoo data indexed by NvBootArgKey_ChipShmooPhys
+ */
+typedef struct NvBootArgsChipShmooPhysRec
+{
+    NvU32 PhysShmooPtr;
+    NvU32 Size;
+} NvBootArgsChipShmooPhys;
+
+#define NVBOOTARG_NUM_PRESERVED_HANDLES (NvBootArgKey_PreservedMemHandle_Num - \
+                                         NvBootArgKey_PreservedMemHandle_0)
+
+/**
+ * OS-agnostic bootarg structure.
+ */
+typedef struct NvBootArgsRec
+{
+    NvBootArgsRm RmArgs;
+    NvBootArgsDisplay DisplayArgs;
+    NvBootArgsFramebuffer FramebufferArgs;
+    NvBootArgsChipShmoo ChipShmooArgs;
+    NvBootArgsChipShmooPhys ChipShmooPhysArgs;
+    NvBootArgsWarmboot WarmbootArgs;
+    NvBootArgsPreservedMemHandle MemHandleArgs[NVBOOTARG_NUM_PRESERVED_HANDLES];
+} NvBootArgs;
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_NVBOOTARGS_H
diff --git a/arch/arm/mach-tegra/nv/include/nvcolor.h b/arch/arm/mach-tegra/nv/include/nvcolor.h
new file mode 100644
index 000000000000..da1218197cd3
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvcolor.h
@@ -0,0 +1,471 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVCOLOR_H
+#define INCLUDED_NVCOLOR_H
+
+/*
+ * We provide a very generic, orthogonal way to specify color formats.  There
+ * are four steps in specifying a color format:
+ * 1. What is the data type of the color components?
+ * 2. How are the color components packed into words of memory?
+ * 3. How are those color components swizzled into an (x,y,z,w) color vector?
+ * 4. How is that vector interpreted as a color?
+ *
+ * These correspond to NvColorDataType, NvColorComponentPacking,
+ * NV_COLOR_SWIZZLE_*, and NvColorSpace, respectively.
+ *
+ * First, you need to understand NVIDIA's standard way of describing color
+ * units (used in several business units within NVIDIA).  Within a word, color
+ * components are ordered from most-significant bit to least-significant bit.
+ * Words are separated by underscores.  For example:
+ *
+ * A8R8B8G8 = a single 32-bit word containing 8 bits alpha, 8 bits red, 8 bits
+ * green, 8 bits blue.
+ *
+ * In little endian:  Byte      3  ||   2  ||   1  ||   0
+ *                    Bits 31                              0
+ *                          AAAAAAAARRRRRRRRGGGGGGGGBBBBBBBB
+ *
+ * In big endian:     Byte      0  ||   1  ||   2  ||   3
+ *                    Bits 31                              0
+ *                          AAAAAAAARRRRRRRRGGGGGGGGBBBBBBBB
+ *
+ * R8_G8_B8_A8 = four consecutive 8-bit words, consisting the red, green, blue,
+ * and alpha components (in that order).
+ *
+ * In little endian:  Byte      0  ||   1  ||   2  ||   3
+ *                    Bits  76543210765432107654321076543210
+ *                          RRRRRRRRGGGGGGGGBBBBBBBBAAAAAAAA
+ *
+ * In big endian:     Byte      0  ||   1  ||   2  ||   3
+ *                    Bits  76543210765432107654321076543210
+ *                          RRRRRRRRGGGGGGGGBBBBBBBBAAAAAAAA
+ *
+ * R5G6B5 = a single 16-bit word containing 5 bits red, 6 bits green, 5 bits
+ * blue.
+ *
+ * In little endian:  Byte      1  ||   0
+ *                    Bits 15              0
+ *                          RRRRRGGGGGGBBBBB
+ *
+ * In big endian:     Byte      0  ||   1
+ *                    Bits 15              0
+ *                          RRRRRGGGGGGBBBBB
+ *
+ * In cases where a word is less than 8 bits (e.g. an A1 1-bit alpha mask
+ * bitmap), pixels are ordered from LSB to MSB within a word.  That is, the LSB
+ * of the byte is the pixel at x%8 == 0, while the MSB of the byte is the pixel
+ * at x%8 == 7.
+ *
+ * Also, note equivalences such as the following.
+ *
+ * In little endian: R8_G8_B8_A8 = A8B8G8R8.
+ * In big endian:    R8_G8_B8_A8 = R8G8B8A8.
+ *
+ * Some YUV "422" formats have different formats for pixels whose X is even vs.
+ * those whose X is odd.  Every pixel contains a Y component, while (for
+ * example) only even pixels might contain a U component and only odd pixels
+ * might contain a V component.  Such formats use a double-underscore to
+ * separate the even pixels from the odd pixels.  For example, the format just
+ * described might be referred to as Y8_U8__Y8_V8.
+ *
+ * Here is how we would we go about mapping a color format (say, R5G6B5) to the
+ * NvColorFormat enums.
+ *
+ * 1. Remove the color information and rename the component R,G,B to generic
+ * names X,Y,Z.  Our NvColorComponentPacking is therefore X5Y6Z5.
+ *
+ * 2. Pick the appropriate color space.  This is plain old RGBA, so we pick
+ * NvColorSpace_LinearRGBA.
+ *
+ * 3. Determine what swizzle to use.  We need R=X, G=Y, B=Z, and A=1, so we
+ * pick the "XYZ1" swizzle.
+ *
+ * 4. Pick the data type of the color components. This is just plain integers,
+ * so NvColorDataType_Integer is our choice.
+ */
+
+/**
+ * We provide a flexible way to map the input vector (x,y,z,w) to an output
+ * vector (x',y',z',w').  Each output component can select any of the input
+ * components or the constants zero or one.  For example, the swizzle "XXX1"
+ * can be used to create a luminance pixel from the input x component, while
+ * the swizzle "ZYXW" swaps the X and Z components (converts between RGBA and
+ * BGRA).
+ */
+#define NV_COLOR_SWIZZLE_X 0
+#define NV_COLOR_SWIZZLE_Y 1
+#define NV_COLOR_SWIZZLE_Z 2
+#define NV_COLOR_SWIZZLE_W 3
+#define NV_COLOR_SWIZZLE_0 4
+#define NV_COLOR_SWIZZLE_1 5
+
+#define NV_COLOR_MAKE_SWIZZLE(x,y,z,w) \
+    ((NV_COLOR_SWIZZLE_##x) | ((NV_COLOR_SWIZZLE_##y) << 3) | \
+     ((NV_COLOR_SWIZZLE_##z) << 6) | ((NV_COLOR_SWIZZLE_##w) << 9))
+
+#define NV_COLOR_SWIZZLE_GET_X(swz) (((swz)     ) & 7)
+#define NV_COLOR_SWIZZLE_GET_Y(swz) (((swz) >> 3) & 7)
+#define NV_COLOR_SWIZZLE_GET_Z(swz) (((swz) >> 6) & 7)
+#define NV_COLOR_SWIZZLE_GET_W(swz) (((swz) >> 9) & 7)
+
+#define NV_COLOR_SWIZZLE_XYZW NV_COLOR_MAKE_SWIZZLE(X,Y,Z,W)
+#define NV_COLOR_SWIZZLE_ZYXW NV_COLOR_MAKE_SWIZZLE(Z,Y,X,W)
+#define NV_COLOR_SWIZZLE_WZYX NV_COLOR_MAKE_SWIZZLE(W,Z,Y,X)
+#define NV_COLOR_SWIZZLE_YZWX NV_COLOR_MAKE_SWIZZLE(Y,Z,W,X)
+#define NV_COLOR_SWIZZLE_XYZ1 NV_COLOR_MAKE_SWIZZLE(X,Y,Z,1)
+#define NV_COLOR_SWIZZLE_YZW1 NV_COLOR_MAKE_SWIZZLE(Y,Z,W,1)
+#define NV_COLOR_SWIZZLE_XXX1 NV_COLOR_MAKE_SWIZZLE(X,X,X,1)
+#define NV_COLOR_SWIZZLE_XZY1 NV_COLOR_MAKE_SWIZZLE(X,Z,Y,1)
+#define NV_COLOR_SWIZZLE_ZYX1 NV_COLOR_MAKE_SWIZZLE(Z,Y,X,1)
+#define NV_COLOR_SWIZZLE_WZY1 NV_COLOR_MAKE_SWIZZLE(W,Z,Y,1)
+#define NV_COLOR_SWIZZLE_X000 NV_COLOR_MAKE_SWIZZLE(X,0,0,0)
+#define NV_COLOR_SWIZZLE_0X00 NV_COLOR_MAKE_SWIZZLE(0,X,0,0)
+#define NV_COLOR_SWIZZLE_00X0 NV_COLOR_MAKE_SWIZZLE(0,0,X,0)
+#define NV_COLOR_SWIZZLE_000X NV_COLOR_MAKE_SWIZZLE(0,0,0,X)
+#define NV_COLOR_SWIZZLE_0XY0 NV_COLOR_MAKE_SWIZZLE(0,X,Y,0)
+#define NV_COLOR_SWIZZLE_XXXY NV_COLOR_MAKE_SWIZZLE(X,X,X,Y)
+#define NV_COLOR_SWIZZLE_YYYX NV_COLOR_MAKE_SWIZZLE(Y,Y,Y,X)
+
+/**
+ * This macro extracts the number of bits per pixel out of an NvColorFormat or
+ * NvColorComponentPacking.
+ */
+#define NV_COLOR_GET_BPP(fmt) (((NvU32)(fmt)) >> 24)
+
+/**
+ * This macro encodes the number of bits per pixel into an
+ * NvColorComponentPacking enum.
+ */
+#define NV_COLOR_SET_BPP(bpp) ((bpp) << 24)
+
+/**
+ * NvColorComponentPacking enumerates the possible ways to pack color
+ * components into words in memory.
+ */
+typedef enum
+{
+    NvColorComponentPacking_X1              = 0x01 | NV_COLOR_SET_BPP(1),
+    NvColorComponentPacking_X2              = 0x02 | NV_COLOR_SET_BPP(2),
+    NvColorComponentPacking_X4              = 0x03 | NV_COLOR_SET_BPP(4),
+    NvColorComponentPacking_X8              = 0x04 | NV_COLOR_SET_BPP(8),
+    NvColorComponentPacking_X3Y3Z2          = 0x05 | NV_COLOR_SET_BPP(8),
+    NvColorComponentPacking_Y4X4            = 0x06 | NV_COLOR_SET_BPP(8),
+    NvColorComponentPacking_X16             = 0x07 | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X4Y4Z4W4        = 0x08 | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X1Y5Z5W5        = 0x09 | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X5Y6Z5          = 0x0A | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X8_Y8           = 0x0B | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X8_Y8__X8_Z8    = 0x0C | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_Y8_X8__Z8_X8    = 0x0D | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_Y6X10           = 0x0E | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_Y4X12           = 0x0F | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_Y2X14           = 0x10 | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X5Y5Z5W1        = 0x11 | NV_COLOR_SET_BPP(16),
+    NvColorComponentPacking_X8_Y8_Z8        = 0x12 | NV_COLOR_SET_BPP(24),
+    NvColorComponentPacking_X32             = 0x13 | NV_COLOR_SET_BPP(32),
+    NvColorComponentPacking_X8Y8Z8W8        = 0x14 | NV_COLOR_SET_BPP(32),
+    NvColorComponentPacking_X11Y11Z10       = 0x15 | NV_COLOR_SET_BPP(32),
+    NvColorComponentPacking_X16Y16          = 0x16 | NV_COLOR_SET_BPP(32),
+    NvColorComponentPacking_X16_Y16         = 0x17 | NV_COLOR_SET_BPP(32),
+    NvColorComponentPacking_X16_Y16_Z16     = 0x18 | NV_COLOR_SET_BPP(48),
+    NvColorComponentPacking_X16_Y16_Z16_W16 = 0x19 | NV_COLOR_SET_BPP(64),
+    NvColorComponentPacking_X16Y16Z16W16    = 0x20 | NV_COLOR_SET_BPP(64),
+    NvColorComponentPacking_X32_Y32         = 0x21 | NV_COLOR_SET_BPP(64),
+    NvColorComponentPacking_X32_Y32_Z32     = 0x22 | NV_COLOR_SET_BPP(96),
+    NvColorComponentPacking_X32_Y32_Z32_W32 = 0x23 | NV_COLOR_SET_BPP(128),
+    NvColorComponentPacking_X32Y32Z32W32    = 0x24 | NV_COLOR_SET_BPP(128),
+
+    NvColorComponentPacking_Force32 = 0x7FFFFFFF
+} NvColorComponentPacking;
+
+/**
+ * NvColorDataType defines the data type of color components.
+ *
+ * The default datatype of color components is 'Integer' which should be used
+ * when the color value is to be intepreted as an integer value ranging from 0
+ * to the maximum value representable by the width of the components (as
+ * specified by the packing of the component). Use 'Integer' also when the
+ * interpretation of color value bits is not known, does not matter or is
+ * context dependent.
+ *
+ * A data type of 'Float' indicates that float values are stored in the
+ * components of the color. The combination of data type 'Float' and the
+ * bit width of the component packing defines the final data format of the
+ * individual component.
+ *
+ * The list below defines the accepted combinations, when adding new
+ * float formats please add an entry into this list.
+ *
+ * - DataType = Float, Component bit width = 32:
+ *      A IEEE 754 single precision float (binary32) with 1 sign bit,
+ *      8 exponent bits and 23 mantissa bits.
+ *
+ * - DataType = Float, Component bit width = 16:
+ *      A IEEE 754 half precision float (binary16) with 1 sign bit,
+ *      5 exponent bits and 10 mantissa bits.
+ *
+ * - DataType = Float, Component bit width = 10:
+ *      An unsigned nvfloat with 5 exponent bits and 5 mantissa bits.
+ *
+ * - DataType = Float, Component bit width = 11:
+ *      An unsigned nvfloat with 5 exponent bits and 6 mantissa bits.
+ *
+ */
+typedef enum
+{
+    NvColorDataType_Integer     = 0x0,
+    NvColorDataType_Float       = 0x1,
+
+    NvColorDataType_Force32 = 0x7FFFFFFF    
+} NvColorDataType;
+
+/**
+ * NvColorSpace defines a number of ways of interpreting an (x,y,z,w) tuple as
+ * a color.  The most common and basic is linear RGBA, which simply maps X->R,
+ * Y->G, Z->B, and W->A, but various other color spaces also exist.
+ *
+ * Some future candidates for expansion are premultiplied alpha formats and
+ * Z/stencil formats.  They have been omitted for now until there is a need.
+ */
+typedef enum
+{
+    /** Linear RGBA color space. */
+    NvColorSpace_LinearRGBA = 1,
+
+    /** sRGB color space with linear alpha. */
+    NvColorSpace_sRGB,
+
+    /** Paletted/color index color space. (data is meaningless w/o the palette)
+     */
+    NvColorSpace_ColorIndex,
+
+    /** YCbCr ITU-R BT.601 color space. */
+    NvColorSpace_YCbCr601,
+
+    /** YCbCr ITU-R BT.601 color space with range reduced YCbCr for VC1 decoded
+     *  surfaces. If picture layer of VC1 bit stream has RANGEREDFRM bit set,
+     *  decoded YUV data has to be scaled up (range expanded). 
+     * For this type of surface, clients should range expand Y,Cb,Cr as follows:
+     * Y  = clip( (( Y-128)*2) + 128 ); 
+     * Cb = clip( ((Cb-128)*2) + 128 ); 
+     * Cr = clip( ((Cr-128)*2) + 128 ); 
+     */
+    NvColorSpace_YCbCr601_RR,
+
+    /** YCbCr ITU-R BT.709 color space. */
+    NvColorSpace_YCbCr709,
+
+    /**
+     * Bayer format with the X component mapped to samples as follows.
+     *   span 1: R G R G R G R G
+     *   span 2: G B G B G B G B
+     * (Y,Z,W are discarded.)
+     */
+    NvColorSpace_BayerRGGB,
+
+    /**
+     * Bayer format with the X component mapped to samples as follows.
+     *   span 1: B G B G B G B G
+     *   span 2: G R G R G R G R
+     * (Y,Z,W are discarded.)
+     */
+    NvColorSpace_BayerBGGR,
+
+    /**
+     * Bayer format with the X component mapped to samples as follows.
+     *   span 1: G R G R G R G R
+     *   span 2: B G B G B G B G
+     * (Y,Z,W are discarded.)
+     */
+    NvColorSpace_BayerGRBG,
+
+    /**
+     * Bayer format with the X component mapped to samples as follows.
+     *   span 1: G B G B G B G B
+     *   span 2: R G R G R G R G
+     * (Y,Z,W are discarded.)
+     */
+    NvColorSpace_BayerGBRG,
+
+    /**
+     * Noncolor data (for example depth, stencil, coverage). 
+     */
+    NvColorSpace_NonColor,
+
+    NvColorSpace_Force32 = 0x7FFFFFFF
+} NvColorSpace;
+
+/**
+ * NV_COLOR_MAKE_FORMAT_XXX macros build NvColor values out of the
+ * constituent parts.
+ *
+ * NV_COLOR_MAKE_FORMAT_GENERIC is the generic form that accepts
+ * the NvColorDataType of the format as the fourth parameter.
+ *
+ * NV_COLOR_MAKE_FORMAT is used to build DataType = Integer formats.
+ * This special case macro exists because integer formats are the
+ * overwhelming majority and for retaining backwards compatibility with
+ * code written before addition of NvColor data types.
+ */
+
+#define NV_COLOR_MAKE_FORMAT_GENERIC(ColorSpace, Swizzle, ComponentPacking, DataType) \
+    (((NvColorSpace_##ColorSpace) << 20) | \
+     ((NV_COLOR_SWIZZLE_##Swizzle) << 8) | \
+     ((NvColorDataType_##DataType) << 6) |  \
+     (NvColorComponentPacking_##ComponentPacking))
+
+#define NV_COLOR_MAKE_FORMAT(ColorSpace, Swizzle, ComponentPacking) \
+    NV_COLOR_MAKE_FORMAT_GENERIC(ColorSpace, Swizzle, ComponentPacking, Integer)
+
+#define NV_COLOR_GET_COLOR_SPACE(fmt) ((NvU32)(((fmt) >> 20) & 0xF))
+#define NV_COLOR_GET_SWIZZLE(fmt) ((NvU32)(((fmt) >> 8) & 0xFFF))
+#define NV_COLOR_GET_COMPONENT_PACKING(fmt) ((NvU32)((fmt) & 0xFF00003F))
+#define NV_COLOR_GET_DATA_TYPE(fmt) ((NvU32)(((fmt) >> 6) & 0x3))
+
+/**
+ * Each value of NvColorFormat represents a way of laying out pixels in memory.
+ * Some of the most common color formats are listed here, but other formats can
+ * be constructed freely using NV_COLOR_MAKE_FORMAT, so you should generally
+ * use NV_COLOR_GET_* to extract out the constituent parts of the color format
+ * if if you want to provide fully general color format support.  (There is no
+ * requirement, of course, that any particular API must support all conceivable
+ * color formats.)
+ */
+typedef enum
+{
+    /**
+     * In some cases we don't know or don't care about the color format of a
+     * block of data.  This value can be used as a placeholder.  It is
+     * guaranteed that this value (zero) will never collide with any real color
+     * format, based on the way that we construct color format enums.
+     */
+    NvColorFormat_Unspecified = 0,
+
+    // RGBA color formats
+    NvColorFormat_R3G3B2   = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZ1, X3Y3Z2),
+    NvColorFormat_A4R4G4B4 = NV_COLOR_MAKE_FORMAT(LinearRGBA, YZWX, X4Y4Z4W4),
+    NvColorFormat_R4G4B4A4 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZW, X4Y4Z4W4),
+    NvColorFormat_A1R5G5B5 = NV_COLOR_MAKE_FORMAT(LinearRGBA, YZWX, X1Y5Z5W5),
+    NvColorFormat_R5G5B5A1 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZW, X5Y5Z5W1),
+    NvColorFormat_R5G6B5   = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZ1, X5Y6Z5),
+    NvColorFormat_R8_G8_B8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZ1, X8_Y8_Z8),
+    NvColorFormat_B8_G8_R8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, ZYX1, X8_Y8_Z8),
+    NvColorFormat_A8R8G8B8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, YZWX, X8Y8Z8W8),
+    NvColorFormat_A8B8G8R8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, WZYX, X8Y8Z8W8),
+    NvColorFormat_R8G8B8A8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZW, X8Y8Z8W8),
+    NvColorFormat_B8G8R8A8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, ZYXW, X8Y8Z8W8),
+    NvColorFormat_X8R8G8B8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, YZW1, X8Y8Z8W8),
+    NvColorFormat_R8G8B8X8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XYZ1, X8Y8Z8W8),
+    NvColorFormat_X8B8G8R8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, WZY1, X8Y8Z8W8),
+    NvColorFormat_B8G8R8X8 = NV_COLOR_MAKE_FORMAT(LinearRGBA, ZYX1, X8Y8Z8W8),
+    
+    NvColorFormat_Float_B10G11R11     = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, ZYX1, X11Y11Z10, Float),
+    NvColorFormat_Float_A16B16G16R16  = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, WZYX, X16Y16Z16W16, Float),
+    NvColorFormat_Float_X16B16G16R16  = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, WZY1, X16Y16Z16W16, Float),   
+    
+    // Luminance color formats
+    NvColorFormat_L1  = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X1),
+    NvColorFormat_L2  = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X2),
+    NvColorFormat_L4  = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X4),
+    NvColorFormat_L8  = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X8),
+    NvColorFormat_L16 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X16),
+    NvColorFormat_L32 = NV_COLOR_MAKE_FORMAT(LinearRGBA, XXX1, X32),
+    
+    NvColorFormat_Float_L16     = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, XXX1, X16, Float),
+    NvColorFormat_Float_A16L16  = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, YYYX, X16Y16, Float),
+
+    // Alpha color formats
+    NvColorFormat_A1  = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X1),
+    NvColorFormat_A2  = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X2),
+    NvColorFormat_A4  = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X4),
+    NvColorFormat_A8  = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X8),
+    NvColorFormat_A16 = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X16),
+    NvColorFormat_A32 = NV_COLOR_MAKE_FORMAT(LinearRGBA, 000X, X32),
+    
+    NvColorFormat_Float_A16 = NV_COLOR_MAKE_FORMAT_GENERIC(LinearRGBA, 000X, X16, Float),
+
+    // Color index formats
+    NvColorFormat_I1 = NV_COLOR_MAKE_FORMAT(ColorIndex, X000, X1),
+    NvColorFormat_I2 = NV_COLOR_MAKE_FORMAT(ColorIndex, X000, X2),
+    NvColorFormat_I4 = NV_COLOR_MAKE_FORMAT(ColorIndex, X000, X4),
+    NvColorFormat_I8 = NV_COLOR_MAKE_FORMAT(ColorIndex, X000, X8),
+
+    // YUV interleaved color formats
+    NvColorFormat_Y8_U8_V8 = NV_COLOR_MAKE_FORMAT(YCbCr601, XYZ1, X8_Y8_Z8),
+    NvColorFormat_UYVY     = NV_COLOR_MAKE_FORMAT(YCbCr601, XYZ1, Y8_X8__Z8_X8),
+    NvColorFormat_VYUY     = NV_COLOR_MAKE_FORMAT(YCbCr601, XZY1, Y8_X8__Z8_X8),
+    NvColorFormat_YUYV     = NV_COLOR_MAKE_FORMAT(YCbCr601, XYZ1, X8_Y8__X8_Z8),
+    NvColorFormat_YVYU     = NV_COLOR_MAKE_FORMAT(YCbCr601, XZY1, X8_Y8__X8_Z8),
+
+    // YUV planar color formats
+    NvColorFormat_Y8       = NV_COLOR_MAKE_FORMAT(YCbCr601, X000, X8),
+    NvColorFormat_U8       = NV_COLOR_MAKE_FORMAT(YCbCr601, 0X00, X8),
+    NvColorFormat_V8       = NV_COLOR_MAKE_FORMAT(YCbCr601, 00X0, X8),
+    NvColorFormat_U8_V8    = NV_COLOR_MAKE_FORMAT(YCbCr601, 0XY0, X8_Y8),
+
+    // Range Reduced YUV planar color formats
+    NvColorFormat_Y8_RR    = NV_COLOR_MAKE_FORMAT(YCbCr601_RR, X000, X8),
+    NvColorFormat_U8_RR    = NV_COLOR_MAKE_FORMAT(YCbCr601_RR, 0X00, X8),
+    NvColorFormat_V8_RR    = NV_COLOR_MAKE_FORMAT(YCbCr601_RR, 00X0, X8),
+    NvColorFormat_U8_V8_RR = NV_COLOR_MAKE_FORMAT(YCbCr601_RR, 0XY0, X8_Y8),
+
+    // Bayer color formats
+    NvColorFormat_Bayer8RGGB    = NV_COLOR_MAKE_FORMAT(BayerRGGB, X000, X8),
+    NvColorFormat_Bayer8BGGR    = NV_COLOR_MAKE_FORMAT(BayerBGGR, X000, X8),
+    NvColorFormat_Bayer8GRBG    = NV_COLOR_MAKE_FORMAT(BayerGRBG, X000, X8),
+    NvColorFormat_Bayer8GBRG    = NV_COLOR_MAKE_FORMAT(BayerGBRG, X000, X8),
+    NvColorFormat_X6Bayer10RGGB = NV_COLOR_MAKE_FORMAT(BayerRGGB, X000, Y6X10),
+    NvColorFormat_X6Bayer10BGGR = NV_COLOR_MAKE_FORMAT(BayerBGGR, X000, Y6X10),
+    NvColorFormat_X6Bayer10GRBG = NV_COLOR_MAKE_FORMAT(BayerGRBG, X000, Y6X10),
+    NvColorFormat_X6Bayer10GBRG = NV_COLOR_MAKE_FORMAT(BayerGBRG, X000, Y6X10),
+    NvColorFormat_X4Bayer12RGGB = NV_COLOR_MAKE_FORMAT(BayerRGGB, X000, Y4X12),
+    NvColorFormat_X4Bayer12BGGR = NV_COLOR_MAKE_FORMAT(BayerBGGR, X000, Y4X12),
+    NvColorFormat_X4Bayer12GRBG = NV_COLOR_MAKE_FORMAT(BayerGRBG, X000, Y4X12),
+    NvColorFormat_X4Bayer12GBRG = NV_COLOR_MAKE_FORMAT(BayerGBRG, X000, Y4X12),
+    NvColorFormat_X2Bayer14RGGB = NV_COLOR_MAKE_FORMAT(BayerRGGB, X000, Y2X14),
+    NvColorFormat_X2Bayer14BGGR = NV_COLOR_MAKE_FORMAT(BayerBGGR, X000, Y2X14),
+    NvColorFormat_X2Bayer14GRBG = NV_COLOR_MAKE_FORMAT(BayerGRBG, X000, Y2X14),
+    NvColorFormat_X2Bayer14GBRG = NV_COLOR_MAKE_FORMAT(BayerGBRG, X000, Y2X14),
+    NvColorFormat_Bayer16RGGB   = NV_COLOR_MAKE_FORMAT(BayerRGGB, X000, X16),
+    NvColorFormat_Bayer16BGGR   = NV_COLOR_MAKE_FORMAT(BayerBGGR, X000, X16),
+    NvColorFormat_Bayer16GRBG   = NV_COLOR_MAKE_FORMAT(BayerGRBG, X000, X16),
+    NvColorFormat_Bayer16GBRG   = NV_COLOR_MAKE_FORMAT(BayerGBRG, X000, X16),
+    
+    // Non color formats
+    NvColorFormat_X4C4          = NV_COLOR_MAKE_FORMAT(NonColor, X000, Y4X4),   // VCAA
+    
+    NvColorFormat_Force32 = 0x7FFFFFFF
+} NvColorFormat;
+
+#endif // INCLUDED_NVCOLOR_H
diff --git a/arch/arm/mach-tegra/nv/include/nvcommon.h b/arch/arm/mach-tegra/nv/include/nvcommon.h
new file mode 100644
index 000000000000..4936555d80a4
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvcommon.h
@@ -0,0 +1,368 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#ifndef INCLUDED_NVCOMMON_H
+#define INCLUDED_NVCOMMON_H
+
+// Include headers that provide NULL, size_t, offsetof, and [u]intptr_t.  In
+// the event that the toolchain doesn't provide these, provide them ourselves.
+#include <stddef.h>
+#if defined(_WIN32_WCE)
+typedef int          intptr_t;
+typedef unsigned int uintptr_t;
+#elif (defined(__linux__) && !defined(__KERNEL__)) || defined(__arm)
+#include <stdint.h>
+#endif
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/** 
+ * @defgroup nvcommon Common Declarations
+ * 
+ * nvcommon.h contains standard definitions used by various interfaces
+ * 
+ * @{
+ */
+
+
+/**
+ * If an OS DEFINE is not set, it should be set to 0
+ */
+#ifndef NV_OS_CE_500
+#define NV_OS_CE_500 0
+#endif
+#ifndef NV_OS_CE_600
+#define NV_OS_CE_600 0
+#endif
+#ifndef NV_OS_WM_600
+#define NV_OS_WM_600 0
+#endif
+#ifndef NV_OS_700
+#define NV_OS_700 0
+#endif
+
+
+// OS-related #define's
+#if defined(_WIN32)
+  #define NVOS_IS_WINDOWS 1
+  #if defined(_WIN32_WCE)
+    #define NVOS_IS_WINDOWS_CE 1
+  #endif
+#elif defined(__linux__)
+  #define NVOS_IS_LINUX 1
+  #define NVOS_IS_UNIX 1
+  #if defined(__KERNEL__)
+    #define NVOS_IS_LINUX_KERNEL 1
+  #endif
+#elif defined(__arm__)  && defined(__ARM_EABI__)
+    /* GCC arm eabi compiler, potentially used for kernel compilation without
+     * __linux__, but also for straight EABI (AOS) executable builds */
+#  if defined(__KERNEL__)
+#    define NVOS_IS_LINUX 1
+#    define NVOS_IS_UNIX 1
+#    define NVOS_IS_LINUX_KERNEL 1
+#  endif
+    /* Nothing to define for AOS */
+#elif defined(__arm) 
+  // For ARM RVDS compiler, we don't know the final target OS at compile time
+#else
+  #error Unknown OS
+#endif
+
+#if !defined(NVOS_IS_WINDOWS)
+#define NVOS_IS_WINDOWS 0
+#endif
+#if !defined(NVOS_IS_WINDOWS_CE)
+#define NVOS_IS_WINDOWS_CE 0
+#endif
+#if !defined(NVOS_IS_LINUX)
+#define NVOS_IS_LINUX 0
+#endif
+#if !defined(NVOS_IS_UNIX)
+#define NVOS_IS_UNIX 0
+#endif
+#if !defined(NVOS_IS_LINUX_KERNEL) 
+#define NVOS_IS_LINUX_KERNEL 0
+#endif
+
+// CPU-related #define's 
+#if defined(_M_IX86) || defined(__i386__)
+#define NVCPU_IS_X86 1 // any IA32 machine (not AMD64)
+#define NVCPU_MIN_PAGE_SHIFT 12
+#elif defined(_M_ARM) || defined(__arm__)
+#define NVCPU_IS_ARM 1
+#define NVCPU_MIN_PAGE_SHIFT 12
+#else
+#error Unknown CPU
+#endif
+#if !defined(NVCPU_IS_X86)
+#define NVCPU_IS_X86 0
+#endif
+#if !defined(NVCPU_IS_ARM)
+#define NVCPU_IS_ARM 0
+#endif
+
+#if (NVCPU_IS_X86 && NVOS_IS_WINDOWS)
+#define NVOS_IS_WINDOWS_X86 1
+#else
+#define NVOS_IS_WINDOWS_X86 0
+#endif
+
+// The minimum page size can be determined from the minimum page shift
+#define NVCPU_MIN_PAGE_SIZE (1 << NVCPU_MIN_PAGE_SHIFT)
+
+// We don't currently support any big-endian CPUs
+#define NVCPU_IS_BIG_ENDIAN 0
+
+// We don't currently support any 64-bit CPUs
+#define NVCPU_IS_64_BITS 0
+
+// Explicitly sized signed and unsigned ints
+typedef unsigned char      NvU8;  // 0 to 255
+typedef unsigned short     NvU16; // 0 to 65535
+typedef unsigned int       NvU32; // 0 to 4294967295
+typedef unsigned long long NvU64; // 0 to 18446744073709551615
+typedef signed char        NvS8;  // -128 to 127
+typedef signed short       NvS16; // -32768 to 32767
+typedef signed int         NvS32; // -2147483648 to 2147483647
+typedef signed long long   NvS64; // 2^-63 to 2^63-1
+
+// Explicitly sized floats
+typedef float              NvF32; // IEEE Single Precision (S1E8M23)
+typedef double             NvF64; // IEEE Double Precision (S1E11M52)
+
+// Min/Max values for NvF32
+#define NV_MIN_F32  (1.1754944e-38f)
+#define NV_MAX_F32  (3.4028234e+38f)
+
+// Boolean type
+enum { NV_FALSE = 0, NV_TRUE = 1 };
+typedef NvU8 NvBool;
+
+// Pointer-sized signed and unsigned ints
+#if NVCPU_IS_64_BITS
+typedef NvU64 NvUPtr;
+typedef NvS64 NvSPtr;
+#else
+typedef NvU32 NvUPtr;
+typedef NvS32 NvSPtr;
+#endif
+
+// Function attributes are lumped in here too
+// INLINE - Make the function inline
+// NAKED - Create a function without a prologue or an epilogue.
+#if NVOS_IS_WINDOWS
+
+#define NV_INLINE __inline
+#define NV_FORCE_INLINE __forceinline
+#define NV_NAKED __declspec(naked)
+
+#elif defined(__GNUC__)
+
+#define NV_INLINE __inline__
+#define NV_FORCE_INLINE __attribute__((always_inline)) __inline__
+#define NV_NAKED __attribute__((naked))
+
+#elif defined(__arm) // ARM RVDS compiler
+
+#define NV_INLINE __inline
+#define NV_FORCE_INLINE __forceinline
+#define NV_NAKED __asm
+
+#else
+#error Unknown compiler
+#endif
+
+// Symbol attributes.
+// ALIGN - Variable declaration to a particular # of bytes (should always be a
+//         power of two)
+// WEAK  - Define the symbol weakly so it can be overridden by the user.
+#if NVOS_IS_WINDOWS
+#define NV_ALIGN(size) __declspec(align(size))
+#define NV_WEAK  
+#elif defined(__GNUC__)
+#define NV_ALIGN(size) __attribute__ ((aligned (size)))
+#define NV_WEAK __attribute__((weak))    
+#elif defined(__arm)
+#define NV_ALIGN(size) __align(size)
+#define NV_WEAK __weak    
+#else
+#error Unknown compiler
+#endif
+
+/**
+ * This macro wraps its argument with the equivalent of "#if NV_DEBUG", but
+ * also can be used where "#ifdef"'s can't, like inside a macro.
+ */
+#if NV_DEBUG
+#define NV_DEBUG_CODE(x) x
+#else
+#define NV_DEBUG_CODE(x)
+#endif
+
+/** Macro for determining the size of an array */
+#define NV_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+/** Macro for taking min or max of a pair of numbers */
+#define NV_MIN(a,b) (((a) < (b)) ? (a) : (b))
+#define NV_MAX(a,b) (((a) > (b)) ? (a) : (b))
+
+/**
+ * By convention, we use this value to represent an infinite wait interval in
+ * APIs that expect a timeout argument.  A value of zero should not be
+ * interpreted as infinite -- it should be interpreted as "time out immediately
+ * and simply check whether the event has already happened."
+ */
+#define NV_WAIT_INFINITE 0xFFFFFFFF
+
+// Macro to help with MSVC Code Analysis false positives
+#if defined(_PREFAST_)
+#define NV_ANALYSIS_ASSUME(x) __analysis_assume(x)
+#else
+#define NV_ANALYSIS_ASSUME(x)
+#endif
+
+#if NVOS_IS_LINUX_KERNEL
+// for do_div divide macro
+#include <asm/div64.h>
+#endif
+
+/**
+ * Performs the 64-bit division and returns the quotient.
+ *
+ * If the divisor is 0, returns 0.
+ *
+ * It is not gauranteed to have 64-bit divide on all the platforms. So, 
+ * portable code should call this function instead of using / % operators on 
+ * 64-bit variables.
+ */
+static NV_FORCE_INLINE  NvU64
+NvDiv64Inline(NvU64 dividend, NvU32 divisor) 
+{
+    if (!divisor) return 0;
+#if NVOS_IS_LINUX_KERNEL
+    /* Linux kernel cannot resolve compiler generated intrinsic for 64-bit divide
+     * Use OS defined wrappers instead */
+    do_div(dividend, divisor);
+    return dividend;
+#else
+    return dividend / divisor;
+#endif
+}
+
+#define NvDiv64(dividend, divisor) NvDiv64Inline(dividend, divisor)
+
+/**
+ * Union that can be used to view a 32-bit word as your choice of a 32-bit
+ * unsigned integer, a 32-bit signed integer, or an IEEE single-precision
+ * float.  Here is an example of how you might use it to extract the (integer)
+ * bitwise representation of a floating-point number:
+ *   NvData32 data;
+ *   data.f = 1.0f;
+ *   printf("%x", data.u);
+ */
+typedef union NvData32Rec
+{
+    NvU32 u;
+    NvS32 i;
+    NvF32 f;
+} NvData32;
+
+/**
+ * This structure is used to determine a location on a 2-dimensional object,
+ * where the coordinate (0,0) is located at the top-left of the object.  The
+ * values of x and y are in pixels.
+ */
+typedef struct NvPointRec
+{
+    /** horizontal location of the point */
+    NvS32 x;
+
+    /** vertical location of the point */
+    NvS32 y;
+} NvPoint;
+
+/**
+ * This structure is used to define a 2-dimensional rectangle where the
+ * rectangle is bottom right exclusive (that is, the right most column, and the
+ * bottom row of the rectangle is not included).
+ */
+typedef struct NvRectRec
+{
+    /** left column of a rectangle */
+    NvS32 left;
+
+    /** top row of a rectangle*/
+    NvS32 top;
+
+    /** right column of a rectangle */
+    NvS32 right;
+
+    /** bottom row of a rectangle */
+    NvS32 bottom;        
+} NvRect;
+
+/**
+ * This structure is used to define a 2-dimensional rectangle
+ * relative to some containing rectangle.
+ * Rectangle coordinates are normalized to [-1.0...+1.0] range
+ */
+typedef struct NvRectF32Rec
+{
+    NvF32 left;
+    NvF32 top;
+    NvF32 right;
+    NvF32 bottom;        
+} NvRectF32;
+
+/**
+ * This structure is used to define a 2-dimensional surface where the surface is
+ * determined by it's height and width in pixels.
+ */
+typedef struct NvSizeRec
+{
+    /* width of the surface in pixels */
+    NvS32 width;
+
+    /* height of the surface in pixels */
+    NvS32 height;
+} NvSize;
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_NVCOMMON_H
diff --git a/arch/arm/mach-tegra/nv/include/nvddk_kbc.h b/arch/arm/mach-tegra/nv/include/nvddk_kbc.h
new file mode 100644
index 000000000000..153a569fa736
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvddk_kbc.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Driver Development Kit:
+ *           Key Board Controller (KBC) Interface</b>
+ *
+ * @b Description: Declares interface for the KBC DDK module.
+ *
+ */
+
+#ifndef INCLUDED_NVDDK_KBC_H
+#define INCLUDED_NVDDK_KBC_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+#include "nvcommon.h"
+#include "nvos.h"
+
+/**
+ * @defgroup nvddk_kbc Keyboard Controller Interface
+ * 
+ * This is the interface to a hardware keyboard controller. 
+ * This keeps track of the keys that are pressed. Only one
+ * client is allowed at a time.
+ * 
+ * @ingroup nvddk_modules
+ * @{
+ */
+
+/** 
+ * An opaque context to the NvDdkKbcRec interface.
+ */
+typedef struct NvDdkKbcRec *NvDdkKbcHandle;
+
+typedef enum
+{
+
+    /// Indicates the key press event.
+    NvDdkKbcKeyEvent_KeyPress = 1,
+
+    /// Indicates the key release event.
+    NvDdkKbcKeyEvent_KeyRelease,
+
+    /// Indicates key event none.
+    NvDdkKbcKeyEvent_None,
+    NvDdkKbcKeyEvent_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvDdkKbcKeyEvent_Force32 = 0x7FFFFFFF
+} NvDdkKbcKeyEvent;
+
+/**
+ * Initializes the keyboard controller.
+ * It allocates resources such as memory, mutexes, and sets up the 
+ * KBC handle.
+ *
+ * @param hDevice Handle to the Rm device that is required by NvDDK
+ * to acquire the resources from RM.
+ * @param phKbc A pointer to the KBC handle where the
+ *       allocated handle is stored. The memory for the handle is
+ *       allocated inside this API.
+ *
+ * @retval NvSuccess Open is successful.
+ */
+ NvError NvDdkKbcOpen( 
+    NvRmDeviceHandle hDevice,
+    NvDdkKbcHandle * phKbc );
+
+/**
+ * Releases the KBC handle and releases any resources that 
+ *   are acquired during the NvDdkKbcOpen() call.
+ * 
+ * @param hKbc A KBC handle that is allocated by NvDdkKbcOpen().
+ */
+
+ void NvDdkKbcClose( 
+    NvDdkKbcHandle hKbc );
+
+/**
+ * Enables the keyboard controller. This must be called once to 
+ *      receive the key events.
+ *
+ * @param hKbc A KBC handle that is allocated by NvDdkKbcOpen().
+ * @param SemaphoreId Semaphore to be signaled on any key event.
+ *
+ * @retval NvSuccess KBC is enabled successfully.
+ */
+ NvError NvDdkKbcStart( 
+    NvDdkKbcHandle hKbc,
+    NvOsSemaphoreHandle SemaphoreId );
+
+/**
+ * Disables the keyboard controller. This must be called to 
+ * stop receiving the key events.
+ *
+ * @param hKbc A KBC handle that is allocated by NvDdkKbcOpen().
+ *
+ * @retval NvSuccess KBC is disabled successfully.
+ */
+ NvError NvDdkKbcStop( 
+    NvDdkKbcHandle hKbc );
+
+/**
+ * Sets the repeat time period at which rows must be scanned for key
+ * events.
+ *  
+ * @param hKbc A KBC handle that is allocated by NvDdkKbcOpen().
+ * @param RepeatTimeMs Repeat time period in milliseconds.
+ */
+ void NvDdkKbcSetRepeatTime( 
+    NvDdkKbcHandle hKbc,
+    NvU32 RepeatTimeMs );
+
+/**
+ * Gets the key events. After calling this function, the caller must sleep 
+ * for the amount of time returned by this function before calling it again.
+ * If the return value is 0, then the client must wait on sema before
+ * calling this function again.
+ *
+ * @param hKbc A KBC handle that is allocated by NvDdkKbcOpen().
+ * @param pKeyCount The returned key events count.
+ * @param pKeyCodes The returned key codes.
+ * @param pKeyEvents The returned key events( press/release).
+ *
+ * @return Wait time in milliseconds.
+ */
+ NvU32 NvDdkKbcGetKeyEvents( 
+    NvDdkKbcHandle hKbc,
+    NvU32 * pKeyCount,
+    NvU32 * pKeyCodes,
+    NvDdkKbcKeyEvent * pKeyEvents );
+
+/**
+ * Part of static power management, the client must call this API to put
+ * the KBC controller into suspend state. This API is a mechanism for the
+ * client to augment OS power management policy. The h/w context of the KBC
+ * controller is saved, clock is disabled, and power is also disabled
+ * to the controller.
+ *
+ * @param hKbc A KBC handle that is allocated by NvDdkKbcOpen().
+ * @retval NvSuccess If successful, or the appropriate error code.
+ */ 
+ NvError NvDdkKbcSuspend( 
+    NvDdkKbcHandle hKbc );
+
+/**
+ * Part of static power management, the client must call this API to
+ * wake up the KBC controller from a suspended state. This API is
+ * a mechanism for the client to augment OS power management policy.
+ * The h/w context of the KBC controller is restored, clock is enabled,
+ * and power is also enabled to the controller.
+ *
+ * @param hKbc A KBC handle that is allocated by NvDdkKbcOpen().
+ * @retval NvSuccess If successful, or the appropriate error code.
+ */ 
+ NvError NvDdkKbcResume( 
+    NvDdkKbcHandle hKbc );
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvddk_nand.h b/arch/arm/mach-tegra/nv/include/nvddk_nand.h
new file mode 100644
index 000000000000..84d963b02d40
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvddk_nand.h
@@ -0,0 +1,599 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b> NVIDIA Driver Development Kit: NAND Flash Controller Interface</b>
+ *
+ * @b Description: This file declares the interface for the NAND module.
+ */
+
+#ifndef INCLUDED_NVDDK_NAND_H
+#define INCLUDED_NVDDK_NAND_H
+
+/**
+ * @defgroup nvddk_nand NAND Flash Controller Interface
+ *
+ * This driver provides the interface to access external NAND flash devices
+ * that are interfaced to the SOC.
+ * It provides the APIs to access the NAND flash physically (in raw block number
+ * and page numbers) and logically (in logical block number through 
+ * block device interface).
+ * It does not support any software ECC algorithms. It makes use of hardware ECC 
+ * features supported by NAND Controller for validating the data.
+ * It supports accessing NAND flash devices in interleave mode.
+ *
+ * @ingroup nvddk_modules
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_init.h"
+#include "nvodm_query_nand.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * NvDdkNandHandle is an opaque context to the NvDdkNandRec interface.
+ */
+typedef struct NvDdkNandRec *NvDdkNandHandle;
+
+
+enum{ MAX_NAND_SUPPORTED = 8};
+
+
+/**
+ * NAND flash device information.
+ */
+typedef struct
+{
+    /// Vendor ID.
+    NvU8 VendorId;
+    /// Device ID.
+    NvU8 DeviceId;
+    /**
+     * Redundant area size per page to write any tag information. This will
+     * be calculated as:
+     * <pre>    TagSize = spareAreaSize - mainAreaEcc - SpareAreaEcc </pre>
+     * Shim layer is always supposed to request in multiples
+     * of this number when spare area operations are requested.
+     */
+    NvU8 TagSize;
+    /// Bus width of the chip: can be 8- or 16-bit.
+    NvU8 BusWidth;
+    /// Page size in bytes, includes only data area, no redundant area.
+    NvU32 PageSize;
+    /// Number of Pages per block.
+    NvU32 PagesPerBlock;
+    /// Total number of blocks that are present in the NAND flash device.
+    NvU32 NoOfBlocks;
+    /**
+     * Holds the zones per flash device--minimum value possible is 1.
+     * Zone is a group of contiguous blocks among which internal copy back can 
+     * be performed, if the chip supports copy-back operation.
+     * Zone is also referred as plane or district by some flashes.
+     */
+    NvU32 ZonesPerDevice;
+    /**
+     * Total device capacity in kilobytes.
+     * Includes only data area, no redundant area.
+     */
+    NvU32 DeviceCapacityInKBytes;
+    /// Interleave capability of the flash.
+    NvOdmNandInterleaveCapability InterleaveCapability;
+    /// Device type: SLC or MLC.
+    NvOdmNandFlashType NandType;
+    /// Number of NAND flash devices present on the board.
+    NvU8 NumberOfDevices;
+    // Size of Spare area
+    NvU32 NumSpareAreaBytes;
+    // Offset of Tag data in the spare area.
+    NvU32 TagOffset;
+}NvDdkNandDeviceInfo;
+
+/**
+ * Information related to a physical block.
+ */
+typedef struct 
+{
+    /// Tag information of the block.
+    NvU8* pTagBuffer;
+    /// Number of bytes to copy in tag buffer.
+    NvU32 TagBufferSize;
+    /// Determines whether the block is factory good block or not. 
+    /// - NV_TRUE if factory good block.
+    /// - NV_FALSE if factory bad block.
+    NvBool IsFactoryGoodBlock;
+    /// Gives the lock status of the block.
+    NvBool IsBlockLocked;
+}NandBlockInfo;
+
+
+/**
+ * NAND DDK capabilities.
+ */
+typedef struct
+{
+    /**
+     * Flag indicating whether or not ECC is supported by the driver.
+     * NV_TRUE means it supports ECC, else not supported.
+     */
+    NvBool IsEccSupported;
+    /**
+     * Flag indicating whether or not interleaving operation is
+     * supported by the driver.
+     * NV_TRUE means it supports interleaving, else not supported.
+     */
+    NvBool IsInterleavingSupported;
+    /// Whether the command queue mode is supported by the SOC.
+    NvBool IsCommandQueueModeSupported;
+    /// Whether EDO mode is suported by the SOC.
+    NvBool IsEdoModeSupported;
+    /// Number of ECC parity bytes per spare area.
+    NvU8 TagEccParitySize;
+    /// Total number of NAND devices supported by SOC.
+    NvU32 NumberOfDevicesSupported;
+    /// Maximum data size that DMA can transfer.
+    NvU32 MaxDataTransferSize;
+    /// NAND controller default timing register value.
+    NvU32 ControllerDefaultTiming;
+    NvBool IsBCHEccSupported;
+}NvDdkNandDriverCapabilities;
+
+/**
+ * The structure for locking of required NAND flash pages.
+ */
+typedef struct
+{
+    /// Device number of the flash being protected by lock feature.
+    NvU8 DeviceNumber;
+    /// Starting page number, from where NAND lock feature should protect data.
+    NvU32 StartPageNumber;
+    /// Ending page number, up to where NAND lock feature should protect data.
+    NvU32 EndPageNumber;
+}LockParams;
+
+/*
+ * Macro to get expression for modulo value that is power of 2
+ * Expression: DIVIDEND % (pow(2, Log2X))
+ */
+#define MACRO_MOD_LOG2NUM(DIVIDEND, Log2X) \
+            ((DIVIDEND) & ((1 << (Log2X)) - 1))
+
+/*
+ * Macro to get expression for multiply by number which is power of 2
+ * Expression: VAL * (1 << Log2Num)
+ */
+#define MACRO_POW2_LOG2NUM(Log2Num) \
+            (1 << (Log2Num))
+
+/*
+ * Macro to get expression for multiply by number which is power of 2
+ * Expression: VAL * (1 << Log2Num)
+ */
+#define MACRO_MULT_POW2_LOG2NUM(VAL, Log2Num) \
+            ((VAL) << (Log2Num))
+
+/*
+ * Macro to get expression for div by number that is power of 2
+ * Expression: VAL / (1 << Log2Num)
+ */
+#define MACRO_DIV_POW2_LOG2NUM(VAL, Log2Num) \
+            ((VAL) >> (Log2Num))
+
+/**
+ * Initializes the NAND Controller and returns a created handle to the client.
+ * Only one instance of the handle can be created.
+ *
+ * @pre NAND client must call this API first before calling any further NAND APIs.
+ *
+ * @param hRmDevice Handle to RM device.
+ * @param phNand Returns the created handle.
+ *
+ * @retval NvSuccess Initialization is successful.
+ * @retval NvError_AlreadyAllocated The NAND device is already in use.
+ */
+NvError NvDdkNandOpen(NvRmDeviceHandle hRmDevice, NvDdkNandHandle *phNand);
+
+/**
+ * Closes the NAND controller and frees the handle.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ *
+ */
+void NvDdkNandClose(NvDdkNandHandle hNand);
+
+/**
+ * Reads the data from the selected NAND device(s) synchronously.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ * @param StartDeviceNum The Device number, which read operation has to be 
+ *      started from. It starts from value '0'.
+ * @param pPageNumbers A pointer to an array containing page numbers for
+ *      each NAND Device. If there are (n + 1) NAND Devices, then 
+ *      array size should be (n + 1).
+ *      - pPageNumbers[0] gives page number to access in NAND Device 0.
+ *      - pPageNumbers[1] gives page number to access in NAND Device 1.
+ *      - ....................................
+ *      - pPageNumbers[n] gives page number to access in NAND Device n.
+ *      
+ *      If NAND Device 'n' should not be accessed, fill pPageNumbers[n] as 
+ *      0xFFFFFFFF.
+ *      If the read starts from NAND Device 'n', all the page numbers 
+ *      in the array should correspond to the same row, even though we don't 
+ *      access the same row pages for '0' to 'n-1' Devices.
+ * @param pDataBuffer A pointer to read the page data into. The size of buffer 
+ *      should be (*pNoOfPages * PageSize).
+ * @param pTagBuffer Pointer to read the tag data into. The size of buffer 
+ *      should be (*pNoOfPages * TagSize).
+ * @param pNoOfPages The number of pages to read. This count should include 
+ *      only valid page count. Consder that total NAND devices present is 4,
+ *      Need to read 1 page from Device1 and 1 page from Device3. In this case,
+ *      \a StartDeviceNum should be 1 and Number of pages should be 2. 
+ *      \a pPageNumbers[0] and \a pPageNumbers[2] should have 0xFFFFFFFF.
+ *      \a pPageNumbers[1] and \a pPageNumbers[3] should have valid page numbers.
+ *      The same pointer returns the number of pages read successfully.
+ * @param IgnoreEccError If set to NV_TRUE, it ignores the ECC error and 
+ *      continues to read the subsequent pages with out aborting read operation.
+ *      This is required during bad block replacements.
+ *
+ * @retval NvSuccess NAND read operation completed successfully.
+ * @retval NvError_NandReadEccFailed Indicates NAND read encountered ECC 
+ *      errors that cannot be corrected.
+ * @retval NvError_NandErrorThresholdReached Indicates NAND read encountered 
+ *      correctable ECC errors and they are equal to the threshold value set.
+ * @retval NvError_NandOperationFailed NAND read operation failed.
+ */
+NvError
+NvDdkNandRead(
+    NvDdkNandHandle hNand,
+    NvU8 StartDeviceNum,
+    NvU32* pPageNumbers,
+    NvU8* const pDataBuffer,
+    NvU8* const pTagBuffer,
+    NvU32 *pNoOfPages,
+    NvBool IgnoreEccError);
+
+/**
+ * Writes the data to the selected NAND device(s) synchronously.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ * @param StartDeviceNum The device number, which write operation has to be 
+ *      started from. It starts from value '0'.
+ * @param pPageNumbers A pointer to an array containing page numbers for
+ *      each NAND Device. If there are (n + 1) NAND Devices, then 
+ *      array size should be (n + 1).
+ *      - pPageNumbers[0] gives page number to access in NAND Device 0.
+ *      - pPageNumbers[1] gives page number to access in NAND Device 1.
+ *      - ....................................
+ *      - pPageNumbers[n] gives page number to access in NAND Device n.
+ *      
+ *      If NAND Device 'n' should not be accessed, fill \a pPageNumbers[n] as 
+ *      0xFFFFFFFF.
+ *      If the read starts from NAND device 'n', all the page numbers 
+ *      in the array should correspond to the same row, even though we don't 
+ *      access the same row pages for '0' to 'n-1' Devices.
+ * @param pDataBuffer A pointer to read the page data into. The size of buffer 
+ *      should be (*pNoOfPages * PageSize).
+ * @param pTagBuffer Pointer to read the tag data into. The size of buffer 
+ *      should be (*pNoOfPages * TagSize).
+ * @param pNoOfPages The number of pages to write. This count should include 
+ *      only valid page count. Consder that total NAND devices present is 4,
+ *      Need to write 1 page to Device1 and 1 page to Device3. In this case,
+ *      \a StartDeviceNum should be 1 and Number of pages should be 2.
+ *      \a pPageNumbers[0] and \a pPageNumbers[2] should have 0xFFFFFFFF.
+ *      \a pPageNumbers[1] and \a pPageNumbers[3] should have valid page numbers.
+ *      The same pointer returns the number of pages written successfully.
+ * 
+ * @retval NvSuccess Operation completed successfully.
+ * @retval NvError_NandOperationFailed Operation failed.
+ */
+NvError
+NvDdkNandWrite(
+    NvDdkNandHandle hNand,
+    NvU8 StartDeviceNum,
+    NvU32* pPageNumbers,
+    const NvU8* pDataBuffer,
+    const NvU8* pTagBuffer,
+    NvU32 *pNoOfPages);
+
+/**
+ * Erases the selected blocks from the NAND device(s) synchronously.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ * @param StartDeviceNum The Device number, which erase operation has to be 
+ *      started from. It starts from value '0'.
+ * @param pPageNumbers A pointer to an array containing page numbers for
+ *      each NAND Device. If there are (n + 1) NAND Devices, then 
+ *      array size should be (n + 1).
+ *      - pPageNumbers[0] gives page number to access in NAND Device 0.
+ *      - pPageNumbers[1] gives page number to access in NAND Device 1.
+ *      - ....................................
+ *      - pPageNumbers[n] gives page number to access in NAND Device n.
+ *      
+ *      If NAND Device 'n' should not be accessed, fill pPageNumbers[n] as 
+ *      0xFFFFFFFF.
+ *      If the read starts from NAND device 'n', all the page numbers 
+ *      in the array should correspond to the same row, even though we don't 
+ *      access the same row pages for '0' to 'n-1' Devices.
+ * @param pNumberOfBlocks The number of blocks to erase. This count should include 
+ *      only valid block count. Consder that total NAND devices present is 4,
+ *      Need to erase 1 block from Device1 and 1 block from Device3. In this case,
+ *      \a StartDeviceNum should be 1 and Number of blocks should be 2.
+ *      \a pPageNumbers[0] and \a pPageNumbers[2] should have 0xFFFFFFFF.
+ *      \a pPageNumbers[1] and \a pPageNumbers[3] should have valid page numbers
+ *      corresponding to blocks.
+ *      The same pointer returns the number of blocks erased successfully.
+ *
+ * @retval NvSuccess Operation completed successfully.
+ * @retval NvError_NandOperationFailed Operation failed.
+ */
+NvError
+NvDdkNandErase(
+    NvDdkNandHandle hNand,
+    NvU8 StartDeviceNum,
+    NvU32* pPageNumbers,
+    NvU32* pNumberOfBlocks);
+
+/**
+ * Copies the data in the source page(s) to the destination page(s) 
+ *      synchronously.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ * @param SrcStartDeviceNum The device number, from which data has to be read 
+ *      for the copy back operation. It starts from value '0'.
+ * @param DstStartDeviceNum The device number, to which data has to be copied 
+ *      for the copy back operation. It starts from value '0'.
+ * @param pSrcPageNumbers A pointer to an array containing page numbers for
+ *      each NAND Device. If there are (n + 1) NAND Devices, then 
+ *      array size should be (n + 1).
+ *      - pSrcPageNumbers[0] gives page number to access in NAND Device 0.
+ *      - pSrcPageNumbers[1] gives page number to access in NAND Device 1.
+ *      - ....................................
+ *      - pSrcPageNumbers[n] gives page number to access in NAND Device n.
+ *     
+ *      If NAND Device 'n' should not be accessed, fill \a pSrcPageNumbers[n] as 
+ *      0xFFFFFFFF.
+ *      If the copy-back starts from NAND devices 'n', all the page numbers 
+ *      in the array should correspond to the same row, even though we don't 
+ *      access the same row pages for '0' to 'n-1' Devices.
+ * @param pDestPageNumbers A pointer to an array containing page numbers for
+ *      each NAND Device. If there are (n + 1) NAND Devices, then 
+ *      array size should be (n + 1).
+ *      - pDestPageNumbers[0] gives page number to access in NAND Device 0.
+ *      - pDestPageNumbers[1] gives page number to access in NAND Device 1.
+ *      - ....................................
+ *      - pDestPageNumbers[n] gives page number to access in NAND Device n.
+ *     
+ *      If NAND Device 'n' should not be accessed, fill \a pDestPageNumbers[n] as 
+ *      0xFFFFFFFF.
+ *      If the Copy-back starts from Interleave column 'n', all the page numbers 
+ *      in the array should correspond to the same row, even though we don't 
+ *      access the same row pages for '0' to 'n-1' Devices.
+ * @param pNoOfPages The number of pages to copy-back. This count should include 
+ *      only valid page count. Consider that total NAND devices present is 4,
+ *      Need to Copy-back 1 page from Device1 and 1 page from Device3. In this 
+ *      case, \a StartDeviceNum should be 1 and Number of pages should be 2.
+ *      \a pSrcPageNumbers[0], \a pSrcPageNumbers[2], \a pDestPageNumbers[0] and 
+ *      \a pDestPageNumbers[2] should have 0xFFFFFFFF. \a pSrcPageNumbers[1], 
+ *      \a pSrcPageNumbers[3], \a pDestPageNumbers[1] and \a pDestPageNumbers[3]
+ *      should have valid page numbers.
+ *      The same pointer returns the number of pages copied-back successfully.
+ * @param IgnoreEccError NV_TRUE to ingnore ECC errors, NV_FALSE otherwise.
+ * 
+ * @retval NvSuccess Operation completed successfully
+ * @retval NvError_NandOperationFailed Operation failed.
+ */
+NvError
+NvDdkNandCopybackPages(
+    NvDdkNandHandle hNand,
+    NvU8 SrcStartDeviceNum,
+    NvU8 DstStartDeviceNum,
+    NvU32* pSrcPageNumbers,
+    NvU32* pDestPageNumbers,
+    NvU32 *pNoOfPages,
+    NvBool IgnoreEccError);
+
+/**
+ * Gets the NAND flash device information.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ * @param DeviceNumber NAND flash device number.
+ * @param pDeviceInfo Returns the device information.
+ *
+ * @retval NvSuccess Operation completed successfully.
+ * @retval NvError_NandOperationFailed NAND copy back operation failed.
+ */
+ NvError
+ NvDdkNandGetDeviceInfo(
+    NvDdkNandHandle hNand,
+    NvU8 DeviceNumber,
+    NvDdkNandDeviceInfo* pDeviceInfo);
+
+/**
+ * Locks the specified NAND flash pages.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ * @param pFlashLockParams A pointer to the range of pages to be locked.
+ */
+void 
+NvDdkNandSetFlashLock(
+    NvDdkNandHandle hNand,
+    LockParams* pFlashLockParams);
+
+/**
+ * Returns the details of the locked apertures, like device number, starting 
+ * page number, ending page number of the region locked.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ * @param pFlashLockParams A pointer to first array element of \a LockParams type 
+ * with eight elements in the array. 
+ * Check if \a pFlashLockParams[i].DeviceNumber == 0xFF, then that aperture is 
+ * free to use for locking.
+ */
+void 
+NvDdkNandGetLockedRegions(
+    NvDdkNandHandle hNand,
+    LockParams* pFlashLockParams);
+/**
+ * Releases all regions that were locked using NvDdkNandSetFlashLock API.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ */
+void NvDdkNandReleaseFlashLock(NvDdkNandHandle hNand);
+
+/**
+ * Gets the NAND driver capabilities.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ * @param pNandDriverCapabilities Returns the capabilities.
+ *
+ */
+void
+NvDdkNandGetCapabilities(
+    NvDdkNandHandle hNand,
+    NvDdkNandDriverCapabilities* pNandDriverCapabilities);
+
+/**
+ * Gives the block specific information such as tag information, lock status, block good/bad.
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ * @param DeviceNumber Device number in which the requested block exists.
+ * @param BlockNumber Requested physical block number.
+ * @param pBlockInfo Return the block information.
+ * @param SkippedBytesReadEnable NV_TRUE enables reading skipped bytes.
+ *
+ * @retval NvSuccess Success
+ */
+NvError
+NvDdkNandGetBlockInfo(
+    NvDdkNandHandle hNand,
+    NvU32 DeviceNumber,
+    NvU32 BlockNumber,
+    NandBlockInfo* pBlockInfo,
+    NvBool SkippedBytesReadEnable);
+
+/**
+ * Part of static power management, call this API to put the NAND controller
+ * into suspend state. This API is a mechanism for client to augment OS
+ * power management policy.
+ *
+ * The h/w context of the NAND controller is saved. Clock is disabled and power
+ * is also disabled to the controller.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ *
+ * @retval NvSuccess Success
+ * @retval NvError_BadParameter Invalid input parameter value
+ */
+NvError NvDdkNandSuspend(NvDdkNandHandle hNand);
+
+/**
+ * Part of static power management, call this API to wake the NAND controller
+ * from suspend state. This API is a mechanism for client to augment OS power
+ * management policy.
+ *
+ * The h/w context of the NAND controller is restored. Clock is enabled and power
+ * is also enabled to the controller
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ *
+ * @retval NvSuccess Success
+ * @retval NvError_BadParameter Invalid input parameter value
+ */
+NvError NvDdkNandResume(NvDdkNandHandle hNand);
+
+/**
+ * Part of local power management of the driver. Call this API to turn off the 
+ * clocks required for NAND controller operation.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ *
+ * @retval NvSuccess Success
+ * @retval NvError_BadParameter Invalid input parameter value
+ */
+NvError NvDdkNandSuspendClocks(NvDdkNandHandle hNand);
+
+/**
+ * Part of local power management of the driver. Call this API to turn on the 
+ * clocks required for NAND controller operation.
+ *
+ * @param hNand Handle to the NAND, which is returned by NvDdkNandOpen().
+ *
+ * @retval NvSuccess Success
+ * @retval NvError_BadParameter Invalid input parameter value
+ */
+NvError NvDdkNandResumeClocks(NvDdkNandHandle hNand);
+
+/**
+ *  API to read to the spare area.
+ */
+NvError
+NvDdkNandReadSpare(
+    NvDdkNandHandle hNand,
+    NvU8 StartDeviceNum,
+    NvU32* pPageNumbers,
+    NvU8* const pSpareBuffer,
+    NvU8 OffsetInSpareAreaInBytes,
+    NvU8 NumSpareAreaBytes);
+
+/**
+ *  API to write to the spare area. Use this API with caution, as there is a
+ *  risk of overriding the factory bad block data.
+ */
+NvError
+NvDdkNandWriteSpare(
+    NvDdkNandHandle hNand,
+    NvU8 StartDeviceNum,
+    NvU32* pPageNumbers,
+    NvU8* const pSpareBuffer,
+    NvU8 OffsetInSpareAreaInBytes,
+    NvU8 NumSpareAreaBytes);
+
+/*
+ * Functions shared between Ddk Nand, block driver and FTL code
+ */
+// Function to compare buffer contents
+NvU32 NandUtilMemcmp(const void *pSrc, const void *pDst, NvU32 Size);
+
+// Simple function to get log2, assumed value power of 2, else return 
+// log2 for immediately smaller number
+NvU8 NandUtilGetLog2(NvU32 Val);
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+#endif // INCLUDED_NVDDK_NAND_H
diff --git a/arch/arm/mach-tegra/nv/include/nvddk_uart.h b/arch/arm/mach-tegra/nv/include/nvddk_uart.h
new file mode 100644
index 000000000000..68e98839c563
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvddk_uart.h
@@ -0,0 +1,627 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Driver Development Kit: UART Driver Interface</b>
+ *
+ * @b Description: This file defines the interface to the UART driver.
+ */
+
+#ifndef INCLUDED_NVDDK_UART_H
+#define INCLUDED_NVDDK_UART_H
+
+/**
+ * @defgroup nvddk_uart UART Driver Interface
+ * 
+ * This is the Universal Asynchronous Receiver Transmitter (UART) interface.
+ * There may be more than one UART in the SOC, which communicate with other 
+ * systems. This interface provides the communication channel configuration,
+ * basic data transfer (receive and transmit) and hardware flow control (modem
+ * flow control).
+ * This driver does not support any software protocols, like IrDA SIR protocol.
+ * 
+ * @ingroup nvddk_modules
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_init.h"
+#include "nvrm_module.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/** Opaque context to the NvDdkUartRec interface.
+ */
+typedef struct NvDdkUartRec *NvDdkUartHandle;
+
+
+/**
+ * Defines the UART communication signal configuration for parity bit.
+ */
+typedef enum 
+{
+    /// Specifies parity to be none.
+    NvDdkUartParity_None = 0x1,
+    /// Specifies parity to be odd.
+    NvDdkUartParity_Odd,
+    /// Specifies even parity to be even.
+    NvDdkUartParity_Even,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvDdkUartParity_Force32 = 0x7FFFFFFF
+} NvDdkUartParity;
+
+/**
+ * Defines the UART communication signal configuration for stop bit.
+ */
+typedef enum 
+{
+    /// Specifies stop bit 1, word length can be 5, 6, 7, or 8.
+    NvDdkUartStopBit_1= 0x1,
+    /// Specifies stop bit 2, word length can be 6, 7, or 8.
+    NvDdkUartStopBit_2,
+    /// Specifies stop bit 1.5, word length should be 5 only.
+    NvDdkUartStopBit_1_5,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvDdkUartStopBit_Force32 = 0x7FFFFFFF
+} NvDdkUartStopBit;
+
+/**
+ * Defines the UART modem signal name to get/set the status/value.
+ */
+typedef enum 
+{
+    /// Specifies a modem signal name of RxD.
+    NvDdkUartSignalName_Rxd = 0x1,
+    /// Specifies a modem signal name of TxD.
+    NvDdkUartSignalName_Txd = 0x2,
+    /// Specifies a modem signal name of RTS.
+    NvDdkUartSignalName_Rts = 0x4,
+    /// Specifies a modem signal name of CTS.
+    NvDdkUartSignalName_Cts = 0x8,
+    /// Specifies a modem signal name of DTR.
+    NvDdkUartSignalName_Dtr = 0x10,
+    /// Specifies a modem signal name of DSR.
+    NvDdkUartSignalName_Dsr = 0x20,
+    /// Specifies a modem signal name for ring indicator.
+    NvDdkUartSignalName_Ri = 0x40,
+    /// Specifies a modem signal name for carrier detect.
+    NvDdkUartSignalName_Cd = 0x80,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvDdkUartSignalName_Force32 = 0x7FFFFFFF
+} NvDdkUartSignalName;
+
+/**
+ * Defines the HW flow control signal states and their behavior.
+ * This is applicable for the modem flow control signal, like RTS, CTS, DSR, DTR,
+ * RI, and CD.
+ * The handshake flow control is configured for the RTS and CTS. When RTS and CTS 
+ * lines are set for the handshake the driver will transfer the data based on 
+ * status of the line.
+ */
+typedef enum
+{
+    /// Disable the flow control. The output signal state will be low.
+    NvDdkUartFlowControl_Disable = 0x1,
+    
+    /// Enable the flow control. The output signal state will be high.
+    NvDdkUartFlowControl_Enable,
+    
+    /// Enable the handshake of the flow control line. 
+    /// This is applicable for the RTS and CTS line. 
+    /// For RTS line, when the buffer is full or UART driver is not able to 
+    /// receive the data, it will deactivate the line.
+    /// For CTS line, the data is transmitted only when the CTS line is active,
+    /// otherwise it will not send the data.
+    NvDdkUartFlowControl_Handshake,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvDdkUartFlowControl_Force32 = 0x7FFFFFFF    
+} NvDdkUartFlowControl;
+
+ /**
+ * Combines the UART port configuration parameter, like baud rate,
+ * parity, data length, stop bit, IrDA modulation, and interfacing type.
+ */
+typedef struct
+{
+    /// Holds the baud rate. Baudrate should be in the bps (bit per second).
+    NvU32 UartBaudRate;
+
+    /// Holds the parity bit. This can be even, odd, or none.
+    NvDdkUartParity UartParityBit;
+    
+    /// Holds the data length in number of bits per UART asynchronous frame.
+    /// This is number of bits between start and stop bit of UART asynch frame.
+    /// The valid length are 5,6,7, and 8.
+    NvU8 UartDataLength;
+    
+    /// Holds the stop bit.
+    /// The UART controller does not support all stop bits with all data
+    /// lengths (16550 compatible UART). 
+    /// The valid combinations are:
+    /// 1 stop bit for data length 5, 6, 7, or 8.
+    /// 1.5 stop bit for data length 5.
+    /// 2 stop bit for data length 6, 7, or 8.
+    NvDdkUartStopBit UartStopBit;
+    
+    /// Holds whether IrDA signal modulation is enabled or not.
+    NvBool IsEnableIrdaModulation;
+} NvDdkUartConfiguarations;
+
+/**
+ * Opens the UART channel and creates the handle of UART. This function 
+ * allocates the memory/OS resources for the requested UART channel and 
+ * returns the handle to the client. The client will call other API by 
+ * passing this handle. 
+ * This initializes the UART controller.
+ *
+ * @param hDevice Handle to the Rm device that is required by DDK to acquire 
+ * the resources from RM.
+  * @param ChannelId Specifies the UART channel ID for which context handle is 
+ * required. Valid instance ID start from 0.
+ * @param phUart A pointer to the UART handle where the allocated handle pointer
+ * will be stored.
+ *
+ * @retval NvSuccess Indicates the controller successfully initialized.
+ * @retval NvError_InsufficientMemory Indicates that function fails to allocate
+ * the memory for handle.
+ * @retval NvError_AlreadyOpen Indicates a channel is already open and so it 
+ * returns the NULL handle.
+ * @retval NvError_BadValue Indicates that the channel ID is not valid. It may
+ * be more than supported channel ID.
+ * @retval NvError_MemoryMapFailed Indicates that the memory mapping for 
+ * controller register failed.
+ * @retval NvError_MutexCreateFailed Indicates that the creation of mutex
+ * failed. Mutex is required to provide the thread safety.
+ * @retval NvError_SemaphoreCreateFailed Indicates that the creation of
+ * semaphore failed. Semaphore is required to provide the synchronous
+ * operation.
+ */
+NvError 
+NvDdkUartOpen(
+    NvRmDeviceHandle hDevice,
+    NvU32 ChannelId, 
+    NvDdkUartHandle *phUart);
+
+/**
+ * Deinitialize the UART controller and release the UART handle. This
+ * frees the memory/OS resources which is allocated for the UART driver related
+ * to this channel ID. After calling this API by client, client should not call
+ * any other APIs related to this handle.
+ *
+ * @param hUart Handle to the UART which is allocated from Open().
+ */
+void NvDdkUartClose(NvDdkUartHandle hUart);
+
+
+/**
+ *  Sets the different UART port configuration. It will set the
+ * baud rate, parity bit, data length, stop bit, line interfacing type, Irda
+ * modulation, flow control. It returns the related error if any of the
+ * parameter is out of range or not supported.
+ *
+ * The baud rate should be less than the supported maximum baudrate.
+ * The UART controller does not support all stop bits  with all data lengths
+ * (16550 compatible UART). The valid combinations are:
+ * - 1 stop bit for data length 5, 6, 7, or 8
+ * - 1.5 stop bit for data length 5
+ * - 2 stop bit for data length 6, 7, or 8
+ *
+ * @note It is recommended that client first call the
+ * NvDdkUartGetConfiguration() to get the current setting and change only those
+ * parameters that are required to change. Do not touch the other parameters and
+ * then call this function.
+ *
+ * @param hUart Handle to the UART.
+ * @param pUartDriverConfiguration A pointer to the structure where the settings 
+ * are stored.
+ * 
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotInitialized Indicates that the UART channel is not opened.
+ * @retval NvError_BadValue Indicates that illegal value specified for the
+ * parameter.
+ * The possible cases for this error are:
+ * - The data length is illegal, e.g. it is not 5,6,7, or 8.
+ * - The stop bit restriction is not matching with the data length.
+ * - The baud rate is more than maximum supported baud rate.
+ * @retval NvError_NotSupported There may be many case to return this error. 
+ * Possible cases are:
+ * - Requested baudrate is not supported because of the it may be not 
+ *          possible to set the correct timing related to this  baud rate.
+ * -  The requested parity bit is not supported.
+ */
+NvError 
+NvDdkUartSetConfiguration(
+    NvDdkUartHandle hUart, 
+    const NvDdkUartConfiguarations* const pUartDriverConfiguration);
+
+/**
+ *  Gets the UART port configuration parameter which is configured.
+ * Client can get the configuration parameter after calling this function.
+ *
+ * @note If client wants to set any port parameter, it is better to first call
+ * this function for getting the default value and then change the desired
+ * parameter with new value and call the NvDdkUartSetConfiguration().
+ *
+ * @param hUart Handle to the UART.
+ * @param pUartDriverConfiguration A pointer to the structure where the
+ * information will be stored.
+ * 
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotInitialized Indicates that the UART channel is not opened.
+ * @retval NvError_BadValue Indicates that illegal value specified for the
+ * parameter.
+ */
+NvError 
+NvDdkUartGetConfiguration(
+    NvDdkUartHandle hUart, 
+    NvDdkUartConfiguarations* const pUartDriverConfiguration);
+
+/**
+ *  Start the read opeartion from the HW and store the receive data in 
+ * the local buffer created locally at the driver level with the buffer size.
+ * This function will create the local buffer for the receive
+ * data as requested by client. The receive data will be stored in this local 
+ * buffer if there is no read call from client side and data arrived. When 
+ * client makes the read call, it will first copied the data from the local buffer 
+ * to the requested buffer and then it will wait for reading the remaining 
+ * data (if requested number of bytes was not available on the local buffer).  
+ *
+ * It will also signal the semaphore \a hRxEventSema if the number of bytes 
+ * available in the local buffer changes from 0 to any value and if there is no
+ * read call. Means if there is no read call and there is no data available on 
+ * the local buffer and when data arrives, the data will be copied into the 
+ * local buffer and it signals the semaphore. This will be use by the client 
+ * that data are available in the local buffer, and so client can made the read 
+ * call.
+ *
+ * It also notifies to the client by signalling the semaphore \a hRxEventSema
+ * if there is any error or break condition received in the receive line.
+ *
+ * @param hUart Handle to the UART.
+ * @param hRxEventSema The semaphore ID which is signalled if any data is 
+ * recevived or there is any error in the receive flow.
+ * @param BufferSize Size of the local buffer where received data will be 
+ * buffered.
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotInitialized Indicates that the UART channel is not opened.
+ * @retval NvError_BadValue Indicates that illegal value specified for the local
+ * \a BufferSize.
+ * @retval NvError_InsufficientMemory Indicates that it is not able to create
+ * the memory for requested size.
+ */
+
+NvError
+NvDdkUartStartReadOnBuffer(
+    NvDdkUartHandle hUart,
+    NvOsSemaphoreHandle hRxEventSema,
+    NvU32 BufferSize);
+    
+/**
+ *  Clears the receive buffer. All data will be cleared and the 
+ * counter which keeps the number of bytes available will be reset to 0.
+ *
+ * @param hUart Handle to the UART.
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotInitialized Indicates that the UART channel is not opened.
+ * @retval NvError_NotSupported Indicates that this feature is not supported.
+ */
+NvError NvDdkUartClearReceiveBuffer(NvDdkUartHandle hUart);
+
+/**
+ *  Update the local buffer if the data arrives in the UART.
+ * This API reads the data from HW FIFO to the local buffer once the data has
+ * arrived. This also returns the number of bytes available in the FIFO.
+ * This API should be called once the client gets the notification from the DDK.
+ *
+ * @param hUart Handle to the UART.
+ * @param pAvailableBytes Returns the number of bytes available in the local
+ * buffer.
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotInitialized Indicates that the UART channel is not opened.
+ * @retval NvError_NotSupported Indicates that this feature is not supported.
+ */
+NvError 
+NvDdkUartUpdateReceiveBuffer(
+    NvDdkUartHandle hUart, 
+    NvU32 *pAvailableBytes);
+
+/**
+ *  Starts the data receiving with the buffer provided. This is blocking
+ * type.
+ *
+ * First it copies the available data from the local buffer to the client
+ * buffer, and if bytes are remaining to read then:
+ * - It will wait for reading the remaining data (synchronous ops), or 
+ * - keep reading from the UART channel to the client buffer and signal
+ *    when there is no remaining data (async ops) or 
+ * - no more reading of the remaining data in the client buffer (read only
+ *         from local buffer).
+ *
+ * If non-zero timeout is selected then it will wait maximum for a given
+ * timeout for reading the data from channel. It can also wait for forever
+ * based on the argument passed. 
+ * If zero timeout is selected then it just copies from local buffer to the 
+ * client buffer with available number of bytes (if it is less than the 
+ * requested size) or requested number of bytes (if available data is more 
+ * than the requested size) and immediately return. 
+ *
+ * @note If previous read is going on then this read call will return an error.
+ *
+ * @param hUart Handle to the UART.
+ * @param pReceiveBuffer A pointer to the receive buffer where data
+ * will be stored.
+ * @param BytesRequested Number of bytes need to be read.
+ * @param pBytesRead A pointer to the variable that stores the number of bytes
+ * requested to read when it is called and stores the actual number of bytes
+ * read when return from the function.
+ * @param WaitTimeoutMs The time needed to wait in milliseconds. If
+ * it is zero then it will be returned immediately with reading the 
+ * number of bytes available in local buffer.
+ * If is non-zero, then it will wait for a requested timeout. If it is
+ * ::NV_WAIT_INFINITE then it will wait for infinitely until the transaction
+ * completes.
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotInitialized Indicates that the UART channel is not opened.
+ * @retval NvError_Timeout Indicates the operation is not completed in a given
+ * timeout.
+ * @retval NvError_UartOverrun Indicates that overrun error occur during
+ * receiving of the data.
+ * @retval NvError_UartFifo Indicates the operation is not completed because of
+ * FIFO error.
+ * @retval NvError_UartBreakReceived Indicates the break condition received.
+ * @retval NvError_UartFraming Indicates the operation is not completed due to 
+ * framing error.
+ * @retval NvError_UartParity Indicates the operation is  not completed due to
+ * parity error.
+ * @retval NvError_InvalidState Indicates that the last read call is not
+ * completed/stopped. 
+ */
+NvError
+NvDdkUartRead(
+    NvDdkUartHandle hUart,
+    NvU8 *pReceiveBuffer,
+    NvU32 BytesRequested,
+    NvU32 *pBytesRead,
+    NvU32 WaitTimeoutMs);
+
+/**
+ * Stops the read operation. The NvDdkUartRead() will be aborted.
+ * The DDK will keep reading the data from the external interface to the local 
+ * buffer and it will not be cleared.
+ *
+ * @param hUart Handle to the UART.
+ *
+ */
+void NvDdkUartStopRead( NvDdkUartHandle hUart); 
+
+
+/**
+ *  Starts the data transfer with the buffer provided. This is blocking
+ * type call. If zero timeout is selected then it will return immediately 
+ * without transferring any data.
+ * 
+ * @param hUart Handle to the UART.
+ * @param pTransmitBuffer A pointer to the transmit buffer where transmitted
+ * data are available.
+ * @param BytesRequested Number of bytes to be sent.
+ * @param pBytesWritten A pointer to the variable that stores the number of
+ * bytes requested to transmit when it is called and stores the actual number of
+ * bytes transmitted when returning from the function.
+ * @param WaitTimeoutMs The time need to wait in milliseconds. If
+ * it is zero then it will be returned immediately without sending any data.
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotInitialized Indicates that the UART channel is not opened.
+ * @retval NvError_Timeout Indicates the operation is not completed in a given
+ * timeout.
+ * @retval NvError_UartTransmit Indicates that a transmit error happened during 
+ * sending of the data.
+ * @retval NvError_InvalidState Indicates that there is already write call made
+ * that is not completed yet.
+ */
+NvError 
+NvDdkUartWrite(
+    NvDdkUartHandle hUart,   
+    NvU8 *pTransmitBuffer,
+    NvU32 BytesRequested,
+    NvU32 *pBytesWritten,
+    NvU32 WaitTimeoutMs);
+
+/**
+ *  Stops the write operation. No more data will be transmitted from the 
+ * buffer, which was passed with the function NvDdkUartWrite().
+ *
+ * @param hUart Handle to the UART provided after getting the channel.
+ */
+void NvDdkUartStopWrite( NvDdkUartHandle hUart); 
+
+/**
+ *  Gets the current transfer status at the UART channel. This API
+ * returns the number of bytes remaining to send on the channel, transmit status,
+ * number of bytes available in the rx buffer, and receive status.
+ * This API returns the status at the calling time and after calling this API,
+ * the data may be changed as data transfer may be still going on.
+ * This is just polling type query about the data transfer status.
+ *
+ * @param hUart Handle to the UART provided after getting the channel.
+ * @param pTxBytesToRemain A pointer to variable where number of bytes remaining
+ * to transfer is stored.
+ * @param pTxStatus A pointer to variable where tramsit status is stored.
+ * @param pRxBytesAvailable A pointer to variable where number of bytes available 
+ * in rx buffer is returned.
+ * @param pRxStatus A pointer to variable where receive status is returned.
+ *
+ */
+void 
+NvDdkUartGetTransferStatus(
+    NvDdkUartHandle hUart,
+    NvU32 *pTxBytesToRemain,
+    NvError *pTxStatus,
+    NvU32 *pRxBytesAvailable,
+    NvError *pRxStatus);
+
+
+/**
+ * Starts/stops sending the break signal from the channel. 
+ * The break siganl can be started by calling this function with \a IsStart = NV_TRUE,
+ * and it can be stopped by calling this API with \a isStart = NV_FALSE.
+ *
+ * @param hUart Handle to the UART.
+ * @param IsStart NV_TRUE to start sending the break signal, or NV_FALSE to stop.
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotInitialized Indicates that the UART channel is not opened.
+ * @retval NvError_NotSupported Indicates that this feature is not supported.
+ */
+NvError NvDdkUartSetBreakSignal(NvDdkUartHandle hUart, NvBool IsStart);
+
+/**
+ * Sets the flow control signal to be disabled, enabled, or in handshake mode.
+ *
+ * @param hUart Handle to the UART.
+ * @param SignalName Specifies the name of the signal to set.
+ * @param FlowControl Specifies whether this is disabled, enable, or in handshake 
+ * mode.
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotInitialized Indicates that the UART channel is not opened.
+ * @retval NvError_NotSupported Indicates that requested functionality is not 
+ * supported for given signal.
+ * @retval NvError_BadValue Indicates that illegal value specified for the
+ * parameter. This may be because the signal name is not valid for this operation.
+ */
+NvError 
+NvDdkUartSetFlowControlSignal(
+    NvDdkUartHandle hUart, 
+    NvDdkUartSignalName SignalName, 
+    NvDdkUartFlowControl FlowControl);
+
+/**
+ * Gets the flow control signal level. This will tell the actual level of
+ * the signal on the UART pins.
+ * This API can be called by more than one signal name by ORing them.
+ * The state of the signal (high or low) can be determined by the position of the
+ * bit state.
+ *
+ * @param hUart Handle to the UART.
+ * @param SignalName Specifies the name of the signal whose status need to be 
+ * queried. Can be more than one signal name by ORing them.
+ * @param pSignalState The state of the signal. The 1 in corresponding location
+ * shows that state is high, otherwise it shows as low.
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotInitialized Indicates that the UART channel is not opened.
+ * @retval NvError_NotSupported Indicates that requested functionality is not 
+ * supported for given signal.
+ * @retval NvError_BadValue Indicates an illegal value was specified for the
+ * parameter. This may be because the signal name is not valid for this operation.
+ */
+NvError 
+NvDdkUartGetFlowControlSignalLevel(
+    NvDdkUartHandle hUart, 
+    NvDdkUartSignalName SignalName,
+    NvU32 *pSignalState);
+
+typedef void (*NvDdkUartSignalChangeCallback)(void *args);
+
+/**
+ * Registers a callback funciton for the modem signal state change. 
+ * Whenever the modem signal change, this API is called.
+ * Callback typically will call NvDdkUartGetFlowControlSignalLevel() for 
+ * finding the signal status.
+ *
+ * Clients can pass NULL callback function for unregistering the signal
+ * change.
+ *
+ * The callback function is called from the ISR/IST.
+ *
+ * @param hUart Handle to the UART.
+ * @param SignalName Specifies the name of the signal to observe.
+ * @param Callback Callback function which is called from ISR/IST of DDK whenever 
+ * signal change is detected by the DDK.
+ * @param args Argument to the signal change handler.
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotInitialized Indicates that the UART channel is not opened.
+ * @retval NvError_NotSupported Indicates that requested functionality is not 
+ * supported.
+ * @retval NvError_BadValue Indicates that an illegal value was specified for the
+ * parameter. 
+ */
+NvError 
+NvDdkUartRegisterModemSignalChange(
+    NvDdkUartHandle hUart, 
+    NvDdkUartSignalName SignalName,
+    NvDdkUartSignalChangeCallback Callback,
+    void *args);
+
+/**
+ * Power mode suspend the UART controller. 
+ *
+ * @param hUart Handle to the UART.
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotSupported Indicates that requested functionality is not 
+ * supported.
+ */
+NvError NvDdkUartSuspend(NvDdkUartHandle hUart);
+
+/**
+ * Power mode resume the UART controller. This will resume the controller
+ * from the suspend states.
+ *
+ * @param hUart Handle to the UART.
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotSupported Indicates that requested functionality is not 
+ * supported.
+ */
+NvError NvDdkUartResume(NvDdkUartHandle hUart);
+
+
+/** @} */
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_NVDDK_UART_H 
diff --git a/arch/arm/mach-tegra/nv/include/nvddk_usbphy.h b/arch/arm/mach-tegra/nv/include/nvddk_usbphy.h
new file mode 100755
index 000000000000..ef1be673e8d4
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvddk_usbphy.h
@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *           NvDDK USB PHY functions</b>
+ *
+ * @b Description: Defines USB PHY private functions
+ *
+ */
+
+#ifndef INCLUDED_NVDDK_USBPHY_H
+#define INCLUDED_NVDDK_USBPHY_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+#include "nvos.h"
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+/**
+ * Opaque handle to a Usb phy device.
+ */
+typedef struct NvDdkUsbPhyRec *NvDdkUsbPhyHandle;
+
+
+/**
+ * Enum defining USB Phy-specific IOCTL types.
+ */
+typedef enum
+{
+    /**
+     * Gets the USB VBUS status.
+     *
+     * @par Inputs:
+     * None.
+     *
+     * @par Outputs:
+     * ::NvDdkUsbPhyIoctl_VBusStatusOutputArgs.
+     *
+     * @retval NvError_Success 
+     * @retval NvError_BadParameter Output Argument is invalid.
+     */
+    NvDdkUsbPhyIoctlType_VBusStatus,
+
+    /**
+     * Configures the VBUS Interrupt.
+     *
+     * @par Inputs:
+     * ::NvDdkUsbPhyIoctl_VBusInterruptInputArgs.
+     *
+     * @par Outputs:
+     * None.
+     *
+     * @retval NvError_Success 
+     * @retval NvError_BadParameter Input Argument is invalid.
+     */
+    NvDdkUsbPhyIoctlType_VBusInterrupt,
+
+    /**
+     * Gets the USB ID pin status.
+     *
+     * @par Inputs:
+     * None.
+     *
+     * @par Outputs:
+     * ::NvDdkUsbPhyIoctl_IdPinStatusOutputArgs.
+     *
+     * @retval NvError_Success 
+     * @retval NvError_BadParameter Output Argument is invalid.
+     */
+    NvDdkUsbPhyIoctlType_IdPinStatus,
+
+    /**
+     * Configures the USB Id pin Interrupt.
+     *
+     * @par Inputs:
+     * ::NvDdkUsbPhyIoctl_IdPinInterruptInputArgs.
+     *
+     * @par Outputs:
+     * None.
+     *
+     * @retval NvError_Success 
+     * @retval NvError_BadParameter Input Argument is invalid.
+     */
+    NvDdkUsbPhyIoctlType_IdPinInterrupt,
+
+    /**
+     * Gets the USB Dedicated charger status.
+     *
+     * @par Inputs:
+     * None.
+     *
+     * @par Outputs:
+     * ::NvDdkUsbPhyIoctl_DedicatedChargerStatusOutputArgs.
+     *
+     * @retval NvError_Success 
+     * @retval NvError_BadParameter Output Argument is invalid.
+     */
+    NvDdkUsbPhyIoctlType_DedicatedChargerStatus,
+
+    /**
+     * Configures the USB dedicated charger detection.
+     *
+     * @par Inputs:
+     * ::NvDdkUsbPhyIoctl_DedicatedChargerDetectionInputArgs.
+     *
+     * @par Outputs:
+     * None.
+     *
+     * @retval NvError_Success 
+     * @retval NvError_BadParameter Input Argument is invalid.
+     */
+    NvDdkUsbPhyIoctlType_DedicatedChargerDetection,
+
+     /**
+     * Configures the Busy hints for the USB controller
+     *
+     * @par Inputs:
+    * ::NvDdkUsbPhyIoctl_UsbBusyHintsOnOffInputArgs.
+    *
+     * @par Outputs:
+     * None.
+     *
+     * @retval NvError_Success 
+     * @retval NvError_BadParameter Input Argument is invalid.
+     */
+    NvDdkUsbPhyIoctlType_UsbBusyHintsOnOff,
+
+
+    NvDdkUsbPhyIoctlType_Num,
+    /**
+     * Ignore -- Forces compilers to make 32-bit enums.
+     */
+    NvDdkUsbPhyIoctlType_Force32 = 0x7FFFFFFF
+} NvDdkUsbPhyIoctlType;
+
+/**
+ * VBUS status IOCTL output arguments.
+ */
+typedef struct NvDdkUsbPhyIoctl_VBusStatusOutputArgsRec
+{
+    // VBUS status: If Set to NV_TRUE VBUS is detected else VBUS is not detected.
+    NvBool VBusDetected;
+} NvDdkUsbPhyIoctl_VBusStatusOutputArgs;
+
+/**
+ * VBUS Interrupt configuration IOCTL input arguments.
+ */
+typedef struct NvDdkUsbPhyIoctl_VBusInterruptInputArgsRec
+{
+    // VBUS Interrupt: If Set to NV_TRUE VBUS interrupt is enabled else disabled.
+    NvBool EnableVBusInterrupt;
+} NvDdkUsbPhyIoctl_VBusInterruptInputArgs;
+
+/**
+ * USB Id pin status IOCTL output arguments.
+ */
+typedef struct NvDdkUsbPhyIoctl_IdPinStatusOutputArgsRec
+{
+    // VBUS status: If Set to NV_TRUE Id pin is low else Id pin is high.
+    NvBool IdPinSetToLow;
+} NvDdkUsbPhyIoctl_IdPinStatusOutputArgs;
+
+/*
+ * USB Id pin Interrupt configuration IOCTL input arguments.
+ */
+typedef struct NvDdkUsbPhyIoctl_IdPinInterruptInputArgsRec
+{
+    // VBUS Interrupt: If Set to NV_TRUE Id pin interrupt is enabled else disabled.
+    NvBool EnableIdPinInterrupt;
+} NvDdkUsbPhyIoctl_IdPinInterruptInputArgs;
+
+
+/**
+ * USB dedicated charger status IOCTL output arguments.
+ */
+typedef struct NvDdkUsbPhyIoctl_DedicatedChargerStatusOutputArgsRec
+{
+    // Dedicated Charger status: If Set to NV_TRUE charger is detected else Id not detected.
+    NvBool ChargerDetected;
+} NvDdkUsbPhyIoctl_DedicatedChargerStatusOutputArgs;
+
+/*
+ * USB dedicated charger configuration IOCTL input arguments.
+ */
+typedef struct NvDdkUsbPhyIoctl_DedicatedChargerDetectionInputArgsRec
+{
+    // Charger Interrupt: If Set to NV_TRUE charger interrupt is enabled else disabled.
+    NvBool EnableChargerInterrupt;
+    // Charger detection: If set to NV_TRUE enables the charger detection else disables.
+    NvBool EnableChargerDetection;
+} NvDdkUsbPhyIoctl_DedicatedChargerDetectionInputArgs;
+
+
+
+/**
+ * USB busy hints configuration IOCTL input arguments.
+ */
+typedef struct NvDdkUsbPhyIoctl_UsbBusyHintsOnOffInputArgsRec
+{
+    // Busy hints on/off: If set to NV_TRUE enables the busy hintson else disables.
+    NvBool OnOff;
+    // Requested boost duration in milliseconds.
+    // if BoostDurationMs = NV_WAIT_INFINITE, then busy hints will be on untill
+    // busy hints are off. This is valid only if OnOff = NV_TRUE
+    NvU32 BoostDurationMs;
+} NvDdkUsbPhyIoctl_UsbBusyHintsOnOffInputArgs;
+
+
+/**
+ * Opens the Usb Phy, allocates the resources and initializes the phy.
+ *
+ * @param hRmDevice Handle to the Rm device, which is required to 
+ * acquire the resources from RM.
+ * @param Instance Instance of specific device.
+ * @param hUsbPhy returns the USB phy handle.
+ *
+ * @retval NvSuccess
+ * @retval NvError_Timeout If phy clock is not stable in expected time.
+ */
+NvError NvDdkUsbPhyOpen(
+    NvRmDeviceHandle hRm, 
+    NvU32 Instance, 
+    NvDdkUsbPhyHandle *hUsbPhy);
+
+/**
+ * Power down the Phy safely and release all the resources allocated.
+ *
+ * @param hUsbPhy Handle acquired during the NvDdkUsbPhyOpen() call.
+ *
+ */
+void NvDdkUsbPhyClose(NvDdkUsbPhyHandle hUsbPhy);
+
+/**
+ * Powers up the device. It could be taking out of low power mode or 
+ * reinitializing.
+ *
+ * @param hUsbPhy Handle acquired during the NvDdkUsbPhyOpen() call.
+ * @param IsHostMode indicates the host mode or not.
+ * @param IsDpd  Deep sleep power up or not .
+ *
+ * @retval NvSuccess
+ * @retval NvError_Timeout If phy clock is not stable in expected time.
+ */
+NvError NvDdkUsbPhyPowerUp(NvDdkUsbPhyHandle hUsbPhy, NvBool IsHostMode, NvBool IsDpd);
+
+/**
+ * Powers down the PHY. It could be low power mode or shutdown.
+ *
+ * @param hUsbPhy Handle acquired during the NvDdkUsbPhyOpen() call.
+ * @param IsHostMode indicates the host mode or not.
+ * @param IsDpd Handle Deep sleep power down or not .
+ *
+ * @retval NvSuccess
+ */
+NvError NvDdkUsbPhyPowerDown(NvDdkUsbPhyHandle hUsbPhy, NvBool IsHostMode, NvBool IsDpd);
+
+/**
+ * Perform an I/O control operation on the device.
+ *
+ * @param hBlockDev Handle acquired during the NvDdkXxxBlockDevOpen() call.
+ * @param IoctlType Type of control operation to perform.
+ * @param InputArgs A pointer to input arguments buffer.
+ * @param OutputArgs A pointer to output arguments buffer.
+ *
+ * @retval NvError_Success IOCTL is successful.
+ * @retval NvError_NotSupported \a Opcode is not recognized.
+ * @retval NvError_InvalidParameter \a InputArgs or \a OutputArgs is
+ *   incorrect.
+ */
+NvError NvDdkUsbPhyIoctl(
+    NvDdkUsbPhyHandle hUsbPhy,
+    NvDdkUsbPhyIoctlType IoctlType,
+    const void *InputArgs,
+    void *OutputArgs);
+
+/**
+ * Waits until Phy clock is stable.
+ *
+ * @param hUsbPhy Handle acquired during the NvDdkUsbPhyOpen() call.
+ *
+ * @retval NvSuccess If phy clock is stable.
+ * @retval NvError_Timeout If phy clock is not stable in expected time.
+ */
+NvError NvDdkUsbPhyWaitForStableClock(NvDdkUsbPhyHandle hUsbPhy);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @}*/
+#endif // INCLUDED_NVDDK_USBPHY_H
+
diff --git a/arch/arm/mach-tegra/nv/include/nvec.h b/arch/arm/mach-tegra/nv/include/nvec.h
new file mode 100644
index 000000000000..4bd934f74a71
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvec.h
@@ -0,0 +1,1428 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvec_H
+#define INCLUDED_nvec_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+/**
+ * @file nvec.h
+ * @brief <b> Nv Embedded Controller (EC) Interface.</b>
+ *
+ * @b Description: This file declares the interface for communicating with
+ *    an Embedded Controller (EC).
+ *
+ * Usage:
+ *
+ * The EC Interface (ECI) handles communication of packets the AP and EC.
+ *
+ * Multiple AP clients are allowed to communicate with the EC concurrently.
+ * Each client opens its own channel by invoking NvEcOpen(), where the
+ * InstanceId parameter specifies which EC to communicate with.  Typically,
+ * only a single EC instance will be present.
+ *
+ * Three types of packets are supported --
+ *
+ * * Request Packets -- sent from AP to EC
+ * * Response Packets -- sent from EC to AP
+ * * Event Packets -- sent from EC to AP
+ *
+ * There is a one-to-one correspondence between Request Packets and Response
+ * Packets.  For every Request Packet sent from the AP to the EC, there will be
+ * one and only one corresponding Response Packet sent from the EC back to the
+ * AP.
+ *
+ * Event Packets, on the other hand, are unsolicited and can be sent by the 
+ * EC at any time.
+ *
+ * See below for detailed information about the format and content of the
+ * packet types.
+ * 
+ * Since Requests and Responses are always paired, the ECI treats the process of
+ * sending a Request and waiting for the corresponding Response as a single
+ * operation.  The NvEcSendRequest() routine carries out this operation.
+ * Normally the routine will block until after the Request is sent and the
+ * Response received; however, certain error conditions can cause the routine to
+ * return early, e.g., request transmit errors, response timeout errors, etc.
+ *
+ * Event packets are treated differently than Requests and Responses since they
+ * can occur asynchronously with respect to other AP activities.  In a sense,
+ * Events are similar to interrupts.  Several types of events are supported,
+ * e.g., keyboard events, ps/2 device events, gpio events, etc.  The client
+ * wishing to receive Event Packets must first register for the desired event
+ * types by invoking the NvEcRegisterForEvents() routine.  The client also
+ * provides a semaphore when registering.  The ECI will signal the semaphore
+ * when an event of the specified type arrives.
+ *
+ * Next, the client blocks on the semaphore, waiting for an event to arrive.
+ * When an event arrives, the ECI will signal the semaphore and hold the Event
+ * Packet until it is retrieved by the client.  Since the ECI will have signaled
+ * the semaphore, the client will become unblocked and can retrieve the pending
+ * Event Packet using the NvEcGetEvent() routine.  If the client fails to
+ * retrieve the event, any event buffering capability within the ECI will
+ * eventually become exhausted and the ECI will be forced to stall the
+ * communications channel between the AP and EC, thereby impacting all of the
+ * the ECI clients in the system.  Finally, the client can call
+ * NvEcUnregisterForEvents() to unregister when it no longer wishes to receive
+ * events.  Note that events are discarded if no client is registered to receive
+ * them.
+ *
+ * Generally, packets will be truncated to fit within the bounds of client-
+ * supplied buffers and no error will be reported; however, if the client buffer
+ * is too small to hold even a minimum-size packet (i.e., a packet with no
+ * payload) then an error will be reported and the buffer contents will be
+ * undefined.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+
+/**
+ * A type-safe handle for EC
+ */
+
+typedef struct NvEcRec *NvEcHandle;
+
+/**
+ * A type-safe handle for EC Event Registration
+ */
+
+typedef struct NvEcEventRegistrationRec *NvEcEventRegistrationHandle;
+
+/**
+ * Packet definitions
+ *
+ * Defines format of request, response, and event packets sent between the AP
+ * and the EC.
+ *
+ * Note that the first element of any packet is the packet type, so given any
+ * unknown packet it is possible to determine its type (request, response, or
+ * event).  From there, the remainder of the packet can be decoded using the
+ * structure definition -- NvEcRequest, NvEcResponse, or NvEcEvent.
+ *
+ * For example, a keyboard request would have a packet type of Request/Response
+ * and a request/response type of Keyboard.  The response to a keyboard request
+ * would have a packet type of Response and a request/response type of Keyboard.
+ * Finally, a keyboard event would have a packet type of Event and an event type
+ * of Keyboard.
+ *
+ * Request operations are specified as a combination of a request type and a
+ * request sub-type.  Since every request has a corresponding response, requests
+ * and responses have a common set of types and sub-types.
+ *
+ * There is a separate set of types for event packets, and events do not have a
+ * sub-type.
+ *
+ * Note that these are the packet formats as presented to clients of the NvEc
+ * API.  Actual format of data communicated between AP and EC may differ at the
+ * transport level.
+ */ 
+#define NVEC_MAX_PAYLOAD_BYTES (30)
+
+/**
+ * Packet types
+ */
+
+typedef enum
+{
+    NvEcPacketType_Request,
+    NvEcPacketType_Response,
+    NvEcPacketType_Event,
+    NvEcPacketType_Num,
+    NvEcPacketType_Force32 = 0x7FFFFFFF
+} NvEcPacketType;
+
+/**
+ * Request/response types
+ *
+ * Each request has a corresponding response, so they share a common set of types.
+ */
+
+typedef enum
+{
+    NvEcRequestResponseType_System = 1,
+    NvEcRequestResponseType_Battery,
+    NvEcRequestResponseType_Gpio,
+    NvEcRequestResponseType_Sleep,
+    NvEcRequestResponseType_Keyboard,
+    NvEcRequestResponseType_AuxDevice,
+    NvEcRequestResponseType_Control,
+    NvEcRequestResponseType_OEM0 = 0xd,
+    NvEcRequestResponseType_OEM1,
+    NvEcRequestResponseType_Num,
+    NvEcRequestResponseType_Force32 = 0x7FFFFFFF
+} NvEcRequestResponseType;
+
+/**
+ * Request/response sub-types
+ *
+ * Each request has a corresponding response, so they share a common set of
+ * sub-types.
+ */
+
+typedef enum
+{
+    NvEcRequestResponseSubtype_None,
+    NvEcRequestResponseSubtype_Num,
+    NvEcRequestResponseSubtype_Force32 = 0x7FFFFFFF
+} NvEcRequestResponseSubtype;
+
+/**
+ * Event types
+ */
+
+typedef enum
+{
+    NvEcEventType_Keyboard,
+    NvEcEventType_AuxDevice0,
+    NvEcEventType_AuxDevice1,
+    NvEcEventType_AuxDevice2,
+    NvEcEventType_AuxDevice3,
+    NvEcEventType_System,
+    NvEcEventType_GpioScalar,
+    NvEcEventType_GpioVector,
+    NvEcEventType_Battery,
+    NvEcEventType_OEM0 = 0xd,
+    NvEcEventType_OEM1,
+    NvEcEventType_Num,
+    NvEcEventType_Force32 = 0x7FFFFFFF
+} NvEcEventType;
+
+/**
+ * Supported status codes
+ */
+
+typedef enum
+{
+    NvEcStatus_Success,
+    NvEcStatus_TimeOut,
+    NvEcStatus_Parity,
+    NvEcStatus_Unavailable,
+    NvEcStatus_InvalidCommand,
+    NvEcStatus_InvalidSize,
+    NvEcStatus_InvalidParameter,
+    NvEcStatus_UnsupportedConfiguration,
+    NvEcStatus_ChecksumFailure,
+    NvEcStatus_WriteFailure,
+    NvEcStatus_ReadFailure,
+    NvEcStatus_Overflow,
+    NvEcStatus_Underflow,
+    NvEcStatus_InvalidState,
+    NvEcStatus_OEM0 = 0xd0,
+    NvEcStatus_OEM1,
+    NvEcStatus_OEM2,
+    NvEcStatus_OEM3,
+    NvEcStatus_OEM4,
+    NvEcStatus_OEM5,
+    NvEcStatus_OEM6,
+    NvEcStatus_OEM7,
+    NvEcStatus_OEM8,
+    NvEcStatus_OEM9,
+    NvEcStatus_OEM10,
+    NvEcStatus_OEM11,
+    NvEcStatus_OEM12,
+    NvEcStatus_OEM13,
+    NvEcStatus_OEM14,
+    NvEcStatus_OEM15,
+    NvEcStatus_OEM16,
+    NvEcStatus_OEM17,
+    NvEcStatus_OEM18,
+    NvEcStatus_OEM19,
+    NvEcStatus_OEM20,
+    NvEcStatus_OEM21,
+    NvEcStatus_OEM22,
+    NvEcStatus_OEM23,
+    NvEcStatus_OEM24,
+    NvEcStatus_OEM25,
+    NvEcStatus_OEM26,
+    NvEcStatus_OEM27,
+    NvEcStatus_OEM28,
+    NvEcStatus_OEM29,
+    NvEcStatus_OEM30,
+    NvEcStatus_OEM31,
+    NvEcStatus_UnspecifiedError = 0xff,
+    NvEcStatus_Num,
+    NvEcStatus_Force32 = 0x7FFFFFFF
+} NvEcStatus;
+
+/**
+ * EC Request Packet
+ */
+
+typedef struct NvEcRequestRec
+{
+    NvEcPacketType PacketType;
+    NvEcRequestResponseType RequestType;
+    NvEcRequestResponseSubtype RequestSubtype;
+    NvU32 RequestorTag;
+    NvU32 NumPayloadBytes;
+    NvU8 Payload[30];
+} NvEcRequest;
+
+#define NVEC_MIN_REQUEST_SIZE (offsetof(struct NvEcRequestRec, Payload[0]))
+
+/**
+ * EC Response Packet
+ */
+
+typedef struct NvEcResponseRec
+{
+    NvEcPacketType PacketType;
+    NvEcRequestResponseType ResponseType;
+    NvEcRequestResponseSubtype ResponseSubtype;
+    NvU32 RequestorTag;
+    NvEcStatus Status;
+    NvU32 NumPayloadBytes;
+    NvU8 Payload[30];
+} NvEcResponse;
+
+#define NVEC_MIN_RESPONSE_SIZE (offsetof(struct NvEcResponseRec, Payload[0]))
+
+/**
+ * EC Event Packet
+ */
+
+typedef struct NvEcEventRec
+{
+    NvEcPacketType PacketType;
+    NvEcEventType EventType;
+    NvEcStatus Status;
+    NvU32 NumPayloadBytes;
+    NvU8 Payload[30];
+} NvEcEvent;
+
+#define NVEC_MIN_EVENT_SIZE (offsetof(struct NvEcEventRec, Payload[0]))
+
+/**
+ * EC power states
+ */
+
+typedef enum
+{
+    NvEcPowerState_PowerDown,
+    NvEcPowerState_Suspend,
+    NvEcPowerState_Restart,
+    NvEcPowerState_Num,
+    NvEcPowerState_Force32 = 0x7FFFFFFF
+} NvEcPowerState;
+
+/**
+ * Initialize and open a channel to the Embedded Controller (EC). This routine
+ * allocates the handle for the EC channel and returns it to the caller.
+ *
+ * @param phEc pointer to location where EC channel handles is to be stored
+ * @param InstanceId instance of EC to which a channel is to be opened
+ *
+ * @retval NvSuccess Channel has been successfully opened.
+ * @retval NvError_InsufficientMemory Routine was unable to allocate memory.
+ * @retval NvError_AlreadyAllocated Maximum number of channels have already
+ *         been opened
+ * @retval NvError_NotSupported InstanceId is invalid
+ */
+
+ NvError NvEcOpen( 
+    NvEcHandle * phEc,
+    NvU32 InstanceId );
+
+/**
+ * Closes and de-initializes a channel to the Embedded Controller (EC).  Also,
+ * frees memory allocated for the handle.
+ *
+ * @param hEc handle for EC channel
+ *
+ * @retval none
+ */
+
+ void NvEcClose( 
+    NvEcHandle hEc );
+
+/**
+ * Send a request to the EC.  Then wait for the EC's response and return it to
+ * the caller.  This routine blocks until the EC's response is received.  The
+ * response is only valid if NvSuccess is returned.
+ *
+ * The request or response can fail due to time-out errors or transmission
+ * errors.
+ *
+ * If the EC sends a larger response packet than will fit in the provided
+ * buffer, the response will be truncated to fit within the available buffer and
+ * no error will be returned.
+ *
+ * @param hEc handle for EC channel
+ * @param pRequest pointer to buffer containing EC request
+ * @param pResponse pointer to buffer where EC response is to be stored
+ * @param RequestSize length of EC request buffer, in bytes
+ * @param ResponseSize length of EC response buffer, in bytes
+ *
+ * @retval NvSuccess Request was successfully sent to EC and a corresponding
+ *         response was successfully received from the EC
+ * @retval NvError_TimeOut EC failed to respond within required time interval
+ * @retval NvError_InvalidSize Request or Response buffer is too small to hold
+ *         minimum-size packet
+ * @retval NvError_BadSize Request or response size is incorrect
+ * @retval NvError_I2cWriteFailed Transmission error while sending request
+ * @retval NvError_I2cReadFailed Transmission error while receiving request
+ */
+
+ NvError NvEcSendRequest( 
+    NvEcHandle hEc,
+    NvEcRequest * pRequest,
+    NvEcResponse * pResponse,
+    NvU32 RequestSize,
+    NvU32 ResponseSize );
+
+/**
+ * Register the caller to receive certain types of events from the EC.
+ *
+ * The caller provides a list of the types of events to be received.
+ * Registering for an event type guarantees that all event packets of the
+ * specified type are delivered to the caller.  If the caller fails to retrieve
+ * the event packet (via NvEcGetEvent), then EC communications will generally be
+ * stalled until such time as a buffer is provided.  Thus, an ill-behaved client
+ * can impact systemwide performance.
+ *
+ * To avoid stalling EC communications, the caller can also provide a hint as to
+ * the amount of buffering that may be needed to account for any expected
+ * "burstiness" in the arrival of events.  This allows stalling to be delayed
+ * until all buffers have been exhaused.  Both the number of buffers and the
+ * size of each buffer is specified.  Event Packets larger than the specified
+ * buffer size will be truncated to fit and no error will be reported.
+ *
+ * Finally, the caller provides a semaphore, which is to be signaled when an
+ * event (of the specified type) arrives.  The caller can then wait on the
+ * semaphore, so as to block until an event occurs.  The semaphone must be
+ * initialized to zero before being passed to this routine.
+ *
+ * @param hEc handle for EC channel
+ * @param phEcEventRegistration pointer to location where EC Event Registration
+ *        handle is to be stored
+ * @param hSema handle for semaphore used to notify caller that an event has
+ *        arrived.  Semaphore must be initialized to zero.
+ * @param NumEventTypes number of entries in pEventTypes array
+ * @param pEventTypes pointer to an array of EC event types to be reported to
+ *        the caller
+ * @param NumEventPackets number of event packets to buffer (hint)
+ * @param EventPacketSize size of each event packet buffer (hint), in bytes
+ *
+ * @retval NvSuccess Registration for events was successful
+ * @retval NvError_InsufficientMemory Routine was unable to allocate memory.
+ * @retval NvError_BadParameter Invalid event type specified
+ * @retval NvError_AlreadyAllocated Client has already registered for the 
+ *         specified event type
+ * @retval NvError_InvalidSize Buffer is too small to hold minimum-size Event
+ *         Packet
+ */
+
+ NvError NvEcRegisterForEvents( 
+    NvEcHandle hEc,
+    NvEcEventRegistrationHandle * phEcEventRegistration,
+    NvOsSemaphoreHandle hSema,
+    NvU32 NumEventTypes,
+    NvEcEventType * pEventTypes,
+    NvU32 NumEventPackets,
+    NvU32 EventPacketSize );
+
+/**
+ * Retrieve pending Event Packet by copying contents into user-supplied buffer.
+ *
+ * If the user-supplied buffer is too small to hold the full payload of the
+ * Event Packet, then the payload will be truncated and no error will be
+ * returned.
+ *
+ * @param hEcEventRegistration EC Event Registration handle
+ * @param pEvent pointer to buffer where EC event is to be stored
+ * @param EventSize length of EC event buffer, in bytes
+ * 
+ * @retval NvSuccess Event Packet retrieved successfully
+ * @retval NvError_InvalidSize Buffer is too small to hold minimum-size Event
+ *         Packet
+ * @retval NvError_BadParameter Invalid handle
+ * @retval NvError_InvalidAddress Null buffer pointer
+ * @retval NvError_InvalidState No Event Packets available
+ */
+
+ NvError NvEcGetEvent( 
+    NvEcEventRegistrationHandle hEcEventRegistration,
+    NvEcEvent * pEvent,
+    NvU32 EventSize );
+
+/**
+ * Unregister the caller so that events previously registered for will no longer
+ * be received.
+ *
+ * @param hEcEventRegistration EC Event Registration handle
+ *
+ * @retval NvSuccess Caller successfully unregistered from specified events
+ * @retval NvError_BadParameter Invalid handle
+ */
+
+ NvError NvEcUnregisterForEvents( 
+    NvEcEventRegistrationHandle hEcEventRegistration );
+
+/**
+ * Configure driver and EC for new power state (suspend, powerdown, or restart)
+ *
+ * @param PowerState desired new power state
+ *
+ * @retval NvSuccess .
+ */
+
+ NvError NvEcPowerSuspend( 
+    NvEcPowerState PowerState );
+
+/**
+ * Power Resume.
+ *
+ * @param none
+ *
+ * @retval NvSuccess .
+ */
+
+ NvError NvEcPowerResume( 
+    void  );
+
+/*******************************************************************************
+ *
+ * Request/Response details
+ *
+ */
+
+ /**
+  * Variable-length strings
+  *
+  * Variable-length strings in Response Packets may not be null-terminated.
+  * Maximum length for variable-length strings is defined below.
+  */
+
+#define NVEC_MAX_RESPONSE_STRING_SIZE  30
+
+/**
+ * Byte ordering
+ * 
+ * Multi-byte integers in the payload section of Request, Response, and Event
+ * Packets are treated as byte arrays.  The bytes are stored in little-endian
+ * order (least significant byte first, most significant byte last).
+ */
+
+/*******************************************************************************
+ *
+ * System Request/Response details
+ *
+ */
+
+/**
+ * System subtypes
+ */
+
+typedef enum
+{
+    NvEcSystemSubtype_GetStatus,
+    NvEcSystemSubtype_ConfigureEventReporting,
+    NvEcSystemSubtype_AcknowledgeSystemStatus,
+    NvEcSystemSubtype_ConfigureWake = 0xfd,
+
+    NvEcSystemSubtype_Num,
+    NvEcSystemSubtype_Max = 0x7fffffff
+} NvEcSystemSubtype;
+
+/**
+ * System payload data structures
+ */
+
+typedef struct NvEcSystemGetStateResponsePayloadRec
+{
+    NvU8 State[2];     // see NVEC_SYSTEM_STATE* #define's
+    NvU8 OemState[2];
+} NvEcSystemGetStateResponsePayload;
+
+#define NVEC_SYSTEM_STATE0_0_EC_RESET_RANGE                             4:4      
+#define NVEC_SYSTEM_STATE0_0_AP_POWERDOWN_NOW_RANGE                     3:3
+#define NVEC_SYSTEM_STATE0_0_AP_SUSPEND_NOW_RANGE                       2:2
+#define NVEC_SYSTEM_STATE0_0_AP_RESTART_NOW_RANGE                       1:1
+
+#define NVEC_SYSTEM_STATE1_0_AC_RANGE                                   0:0
+#define NVEC_SYSTEM_STATE1_0_AC_NOT_PRESENT                             0x0
+#define NVEC_SYSTEM_STATE1_0_AC_PRESENT                                 0x1
+
+typedef struct NvEcSystemConfigureEventReportingRequestPayloadRec
+{
+    NvU8 ReportEnable;     // see NVEC_SYSTEM_REPORT_ENABLE* #define's
+    NvU8 SystemStateMask[2];     // see NVEC_SYSTEM_STATE* #define's
+    NvU8 OemStateMask[2];
+} NvEcSystemConfigureEventReportingRequestPayload;
+
+#define NVEC_SYSTEM_REPORT_ENABLE_0_ACTION_RANGE                        7:0
+#define NVEC_SYSTEM_REPORT_ENABLE_0_ACTION_DISABLE                      0x0
+#define NVEC_SYSTEM_REPORT_ENABLE_0_ACTION_ENABLE                       0x1
+
+typedef struct NvEcSystemAcknowledgeSystemStatusRequestPayloadRec
+{
+    NvU8 SystemStateMask[2];     // see NVEC_SYSTEM_STATE* #define's
+    NvU8 OemStateMask[2];
+} NvEcSystemAcknowledgeSystemStatusRequestPayload;
+
+typedef struct NvEcSystemConfigureWakeRequestPayloadRec
+{
+    NvU8 WakeEnable;     // see NVEC_SYSTEM_WAKE_ENABLE* #define's
+    NvU8 SystemStateMask[2];     // see NVEC_SYSTEM_STATE* #define's
+    NvU8 OemStateMask[2];
+} NvEcSystemConfigureWakeRequestPayload;
+
+#define NVEC_SYSTEM_WAKE_ENABLE_0_ACTION_RANGE                          7:0
+#define NVEC_SYSTEM_WAKE_ENABLE_0_ACTION_DISABLE                        0x0
+#define NVEC_SYSTEM_WAKE_ENABLE_0_ACTION_ENABLE                         0x1
+
+
+/*******************************************************************************
+ *
+ * Battery Request/Response details
+ *
+ */
+
+/**
+ * Battery subtypes
+ */
+
+typedef enum
+{
+    NvEcBatterySubtype_GetSlotStatus,
+    NvEcBatterySubtype_GetVoltage,
+    NvEcBatterySubtype_GetTimeRemaining,
+    NvEcBatterySubtype_GetCurrent,
+    NvEcBatterySubtype_GetAverageCurrent,
+    NvEcBatterySubtype_GetAveragingTimeInterval,
+    NvEcBatterySubtype_GetCapacityRemaining,
+    NvEcBatterySubtype_GetLastFullChargeCapacity,
+    NvEcBatterySubtype_GetDesignCapacity,
+    NvEcBatterySubtype_GetCriticalCapacity,
+    NvEcBatterySubtype_GetTemperature,
+    NvEcBatterySubtype_GetManufacturer,
+    NvEcBatterySubtype_GetModel,
+    NvEcBatterySubtype_GetType,
+    NvEcBatterySubtype_GetRemainingCapacityAlarm,
+    NvEcBatterySubtype_SetRemainingCapacityAlarm,
+    NvEcBatterySubtype_SetConfiguration,
+    NvEcBatterySubtype_GetConfiguration,
+    NvEcBatterySubtype_ConfigureEventReporting,
+    NvEcBatterySubtype_ConfigureWake = 0x1d,
+
+    NvEcBatterySubtype_Num,
+    NvEcBatterySubtype_Max = 0x7fffffff
+} NvEcBatterySubtype;
+
+#define NVEC_SUBTYPE_0_BATTERY_SLOT_RANGE                               7:4
+#define NVEC_SUBTYPE_0_BATTERY_INFO_RANGE                               3:0
+
+/**
+ * Battery payload data structures
+ */
+
+typedef struct NvEcBatteryGetSlotStatusResponsePayloadRec
+{
+    NvU8 SlotStatus;     // see NVEC_BATTERY_SLOT_STATUS* #define's
+    NvU8 CapacityGauge;
+} NvEcBatteryGetSlotStatusResponsePayload;
+
+#define NVEC_BATTERY_SLOT_STATUS_0_CRITICAL_CAPACITY_ALARM_RANGE        3:3
+#define NVEC_BATTERY_SLOT_STATUS_0_CRITICAL_CAPACITY_ALARM_UNSET        0x0
+#define NVEC_BATTERY_SLOT_STATUS_0_CRITICAL_CAPACITY_ALARM_SET          0x1
+
+#define NVEC_BATTERY_SLOT_STATUS_0_CHARGING_STATE_RANGE                 2:1
+#define NVEC_BATTERY_SLOT_STATUS_0_CHARGING_STATE_IDLE                  0x0
+#define NVEC_BATTERY_SLOT_STATUS_0_CHARGING_STATE_CHARGING              0x1
+#define NVEC_BATTERY_SLOT_STATUS_0_CHARGING_STATE_DISCHARGING           0x2
+
+#define NVEC_BATTERY_SLOT_STATUS_0_PRESENT_STATE_RANGE                  0:0
+#define NVEC_BATTERY_SLOT_STATUS_0_PRESENT_STATE_NOT_PRESENT            0x0
+#define NVEC_BATTERY_SLOT_STATUS_0_PRESENT_STATE_PRESENT                0x1
+
+typedef struct NvEcBatteryGetVoltageResponsePayloadRec
+{
+    NvU8 PresentVoltage[2];     // 16-bit unsigned value, in mV
+} NvEcBatteryGetVoltageResponsePayload;
+
+typedef struct NvEcBatteryGetTimeRemainingResponsePayloadRec
+{
+    NvU8 TimeRemaining[2];     // 16-bit unsigned value, in minutes
+} NvEcBatteryGetTimeRemainingResponsePayload;
+
+typedef struct NvEcBatteryGetCurrentResponsePayloadRec
+{
+    NvU8 PresentCurrent[2];     // 16-bit signed value, in mA
+} NvEcBatteryGetCurrentResponsePayload;
+
+typedef struct NvEcBatteryGetAverageCurrentResponsePayloadRec
+{
+    NvU8 AverageCurrent[2];     // 16-bit signed value, in mA
+} NvEcBatteryGetAverageCurrentResponsePayload;
+
+typedef struct NvEcBatteryGetAveragingTimeIntervalResponsePayloadRec
+{
+    NvU8 TimeInterval[2];     // 16-bit unsigned value, in msec
+} NvEcBatteryGetAveragingTimeIntervalResponsePayload;
+
+typedef struct NvEcBatteryGetCapacityRemainingResponsePayloadRec
+{
+    NvU8 CapacityRemaining[2];     // 16-bit unsigned value, in mAh or 10mWh
+} NvEcBatteryGetCapacityRemainingResponsePayload;
+
+typedef struct NvEcBatteryGetLastFullChargeCapacityResponsePayloadRec
+{
+    NvU8 LastFullChargeCapacity[2];     // 16-bit unsigned value, in mAh or 10mWh
+} NvEcBatteryGetLastFullChargeCapacityResponsePayload;
+
+typedef struct NvEcBatteryGetDesignCapacityResponsePayloadRec
+{
+    NvU8 DesignCapacity[2];     // 16-bit unsigned value, in mAh or 10mWh
+} NvEcBatteryGetDesignCapacityResponsePayload;
+
+typedef struct NvEcBatteryGetCriticalCapacityResponsePayloadRec
+{
+    NvU8 CriticalCapacity[2];     // 16-bit unsigned value, in mAh or 10mWh
+} NvEcBatteryGetCriticalCapacityResponsePayload;
+
+typedef struct NvEcBatteryGetTemperatureResponsePayloadRec
+{
+    NvU8 Temperature[2];     // 16-bit unsigned value, in 0.1 degrees Kelvin
+} NvEcBatteryGetTemperatureResponsePayload;
+
+typedef struct NvEcBatteryGetManufacturerResponsePayloadRec
+{
+    char Manufacturer[NVEC_MAX_RESPONSE_STRING_SIZE];
+} NvEcBatteryGetManufacturerResponsePayload;
+
+typedef struct NvEcBatteryGetModelResponsePayloadRec
+{
+    char Model[NVEC_MAX_RESPONSE_STRING_SIZE];
+} NvEcBatteryGetModelResponsePayload;
+
+typedef struct NvEcBatteryGetTypeResponsePayloadRec
+{
+    char Type[NVEC_MAX_RESPONSE_STRING_SIZE];
+} NvEcBatteryGetTypeResponsePayload;
+
+typedef struct NvEcBatterySetRemainingCapacityAlarmRequestPayloadRec
+{
+    NvU8 CapacityThreshold[2];     // 16-bit unsigned value, in mAh or 10mWh
+} NvEcBatterySetRemainingCapacityAlarmRequestPayload;
+
+typedef struct NvEcBatteryGetRemainingCapacityAlarmResponsePayloadRec
+{
+    NvU8 CapacityThreshold[2];     // 16-bit unsigned value, in mAh or 10mWh
+} NvEcBatteryGetRemainingCapacityAlarmResponsePayload;
+
+typedef struct NvEcBatterySetConfigurationRequestPayloadRec
+{
+    NvU8 Configuration;     // see NVEC_BATTERY_CONFIGURATION* #define's
+} NvEcBatterySetConfigurationRequestPayload;
+
+#define NVEC_BATTERY_CONFIGURATION_0_CAPACITY_UNITS_RANGE               0:0
+#define NVEC_BATTERY_CONFIGURATION_0_CAPACITY_UNITS_MAH                 0x0
+#define NVEC_BATTERY_CONFIGURATION_0_CAPACITY_UNITS_10MWH               0x1
+
+typedef struct NvEcBatteryGetConfigurationResponsePayloadRec
+{
+    NvU8 Configuration;     // see NVEC_BATTERY_CONFIGURATION* #define's
+} NvEcBatteryGetConfigurationResponsePayload;
+
+typedef struct NvEcBatteryConfigureEventReportingRequestPayloadRec
+{
+    NvU8 ReportEnable;     // see NVEC_BATTERY_REPORT_ENABLE* #define's
+    NvU8 EventTypes;     // see NVEC_BATTERY_EVENT_TYPE* #define's
+} NvEcBatteryConfigureEventReportingRequestPayload;
+
+#define NVEC_BATTERY_REPORT_ENABLE_0_ACTION_RANGE                       7:0
+#define NVEC_BATTERY_REPORT_ENABLE_0_ACTION_DISABLE                     0x0
+#define NVEC_BATTERY_REPORT_ENABLE_0_ACTION_ENABLE                      0x1
+
+#define NVEC_BATTERY_EVENT_TYPE_0_REMAINING_CAPACITY_ALARM_RANGE        2:2
+#define NVEC_BATTERY_EVENT_TYPE_0_REMAINING_CAPACITY_ALARM_ENABLE       0x0
+#define NVEC_BATTERY_EVENT_TYPE_0_REMAINING_CAPACITY_ALARM_DISABLE      0x1
+
+#define NVEC_BATTERY_EVENT_TYPE_0_CHARGING_STATE_RANGE                  1:1
+#define NVEC_BATTERY_EVENT_TYPE_0_CHARGING_STATE_ENABLE                 0x0
+#define NVEC_BATTERY_EVENT_TYPE_0_CHARGING_STATE_DISABLE                0x1
+
+#define NVEC_BATTERY_EVENT_TYPE_0_PRESENT_STATE_RANGE                   0:0
+#define NVEC_BATTERY_EVENT_TYPE_0_PRESENT_STATE_ENABLE                  0x0
+#define NVEC_BATTERY_EVENT_TYPE_0_PRESENT_STATE_DISABLE                 0x1
+
+typedef struct NvEcBatteryConfigureWakeRequestPayloadRec
+{
+    NvU8 WakeEnable;     // see NVEC_BATTERY_WAKE_ENABLE* #define's
+    NvU8 EventTypes;     // see NVEC_BATTERY_EVENT_TYPE* #define's
+} NvEcBatteryConfigureWakeRequestPayload;
+
+#define NVEC_BATTERY_WAKE_ENABLE_ACTION_RANGE                           7:0
+#define NVEC_BATTERY_WAKE_ENABLE_ACTION_DISABLE                         0x0
+#define NVEC_BATTERY_WAKE_ENABLE_ACTION_ENABLE                          0x1
+
+/*******************************************************************************
+ *
+ * Gpio Request/Response details
+ *
+ */
+
+/**
+ * Gpio subtypes
+ */
+
+typedef enum
+{
+    NvEcGpioSubtype_ConfigurePin,
+    NvEcGpioSubtype_SetPinScalar,
+    NvEcGpioSubtype_GetPinScalar,
+    NvEcGpioSubtype_ConfigureEventReportingScalar,
+    NvEcGpioSubtype_AcknowledgeEventReportScalar,
+
+    NvEcGpioSubtype_GetEventReportScalar = 0x6,
+
+    NvEcGpioSubtype_ConfigureWakeScalar = 0x1d,
+
+    NvEcGpioSubtype_SetPinVector = 0x21,
+    NvEcGpioSubtype_GetPinVector,
+    NvEcGpioSubtype_ConfigureEventReportingVector,
+    NvEcGpioSubtype_AcknowledgeEventReportVector,
+
+    NvEcGpioSubtype_GetEventReportVector = 0x26,
+
+    NvEcGpioSubtype_ConfigureWakeVector = 0x3d,
+
+    NvEcGpioSubtype_Num,
+    NvEcGpioSubtype_Max = 0x7fffffff
+} NvEcGpioSubtype;
+
+/**
+ * Gpio payload data structures
+ */
+
+typedef struct NvEcGpioConfigurePinRequestPayloadRec
+{
+    NvU8 Configuration[2];     // see NVEC_GPIO_CONFIGURATION* #define's
+    NvU8 LogicalPinNumber;
+} NvEcGpioConfigurePinRequestPayload;
+
+#define NVEC_GPIO_CONFIGURATION0_0_MODE_RANGE                           7:5
+#define NVEC_GPIO_CONFIGURATION0_0_MODE_INPUT                           0x0
+#define NVEC_GPIO_CONFIGURATION0_0_MODE_OUTPUT                          0x1
+#define NVEC_GPIO_CONFIGURATION0_0_MODE_TRISTATE                        0x2
+#define NVEC_GPIO_CONFIGURATION0_0_MODE_UNUSED                          0x3
+
+#define NVEC_GPIO_CONFIGURATION0_0_EVENT_TRIGGER_TYPE_RANGE             4:2
+#define NVEC_GPIO_CONFIGURATION0_0_EVENT_TRIGGER_TYPE_NONE              0x0
+#define NVEC_GPIO_CONFIGURATION0_0_EVENT_TRIGGER_TYPE_RISING_EDGE       0x1
+#define NVEC_GPIO_CONFIGURATION0_0_EVENT_TRIGGER_TYPE_FALLING_EDGE      0x2
+#define NVEC_GPIO_CONFIGURATION0_0_EVENT_TRIGGER_TYPE_ANY_EDGE          0x3
+#define NVEC_GPIO_CONFIGURATION0_0_EVENT_TRIGGER_TYPE_LO_LEVEL          0x4
+#define NVEC_GPIO_CONFIGURATION0_0_EVENT_TRIGGER_TYPE_HI_LEVEL          0x5
+#define NVEC_GPIO_CONFIGURATION0_0_EVENT_TRIGGER_TYPE_LEVEL_CHANGE      0x6
+
+#define NVEC_GPIO_CONFIGURATION0_0_PULL_RANGE                           1:0
+#define NVEC_GPIO_CONFIGURATION0_0_PULL_NONE                            0x0
+#define NVEC_GPIO_CONFIGURATION0_0_PULL_DOWN                            0x1
+#define NVEC_GPIO_CONFIGURATION0_0_PULL_UP                              0x2
+
+#define NVEC_GPIO_CONFIGURATION0_0_OUTPUT_DRIVE_TYPE_RANGE              7:6
+#define NVEC_GPIO_CONFIGURATION0_0_OUTPUT_DRIVE_TYPE_PUSH_PULL          0x0
+#define NVEC_GPIO_CONFIGURATION0_0_OUTPUT_DRIVE_TYPE_OPEN_DRAIN         0x1
+
+#define NVEC_GPIO_CONFIGURATION0_0_SCHMITT_TRIGGER_RANGE                5:5
+#define NVEC_GPIO_CONFIGURATION0_0_SCHMITT_TRIGGER_DISABLE              0x0
+#define NVEC_GPIO_CONFIGURATION0_0_SCHMITT_TRIGGER_ENABLE               0x1
+
+/**
+ * GPIO scalar payload data structures
+ */
+
+typedef struct NvEcGpioSetPinScalarRequestPayloadRec
+{
+    NvU8 DriveLevel;     // see NVEC_GPIO_DRIVE_LEVEL* #define's
+    NvU8 LogicalPinNumber;
+} NvEcGpioSetPinScalarRequestPayload;
+
+#define NVEC_GPIO_DRIVE_LEVEL_0_DRIVE_LEVEL_RANGE                       0:0
+#define NVEC_GPIO_DRIVE_LEVEL_0_DRIVE_LEVEL_LOGICAL_LO                  0x0
+#define NVEC_GPIO_DRIVE_LEVEL_0_DRIVE_LEVEL_LOGICAL_HI                  0x1
+
+typedef struct NvEcGpioGetPinScalarRequestPayloadRec
+{
+    NvU8 LogicalPinNumber;
+} NvEcGpioGetPinScalarRequestPayload;
+
+typedef struct NvEcGpioGetPinScalarResponsePayloadRec
+{
+    NvU8 DriveLevel;     // see NVEC_GPIO_DRIVE_LEVEL* #define's
+} NvEcGpioGetPinScalarResponsePayload;
+
+typedef struct NvEcGpioConfigureEventReportingScalarRequestPayloadRec
+{
+    NvU8 ReportEnable;     // 0x0 to disable, 0x1 to enable
+    NvU8 LogicalPinNumber;
+} NvEcGpioConfigureEventReportingScalarRequestPayload;
+
+typedef struct NvEcGpioAcknowledgeEventReportScalarRequestPayloadRec
+{
+    NvU8 LogicalPinNumber;
+} NvEcGpioAcknowledgeEventReportScalarRequestPayload;
+
+typedef struct NvEcGpioGetEventReportScalarRequestPayloadRec
+{
+    NvU8 LogicalPinNumber;
+} NvEcGpioGetEventReportScalarRequestPayload;
+
+typedef struct NvEcGpioGetEventReportScalarResponsePayloadRec
+{
+    NvU8 TriggerStatus;     // see NVEC_GPIO_TRIGGER_STATUS* #define's
+} NvEcGpioGetEventReportScalarResponsePayload;
+
+#define NVEC_GPIO_TRIGGER_STATUS_0_TRIGGER_STATUS_RANGE                 0:0
+#define NVEC_GPIO_TRIGGER_STATUS_0_TRIGGER_STATUS_NO_EVENT_DETECTED     0x0
+#define NVEC_GPIO_TRIGGER_STATUS_0_TRIGGER_STATUS_EVENT_DETECTED        0x1
+
+typedef struct NvEcGpioConfigureWakeScalarRequestPayloadRec
+{
+    NvU8 WakeEnable;     // 0x0 to disable, 0x1 to enable
+    NvU8 LogicalPinNumber;
+} NvEcGpioConfigureWakeScalarRequestPayload;
+
+/**
+ * GPIO vector payload data structures
+ */
+
+#define NVEC_GPIO_MAX_BIT_VECTOR_BYTES   24
+
+typedef struct NvEcGpioSetPinVectorRequestPayloadRec
+{
+    NvU8 DriveLevel;     // see NVEC_GPIO_DRIVE_LEVEL* #define's
+    NvU8 PinSelectionBitVector[NVEC_GPIO_MAX_BIT_VECTOR_BYTES];
+} NvEcGpioSetPinVectorRequestPayload;
+
+typedef struct NvEcGpioGetPinVectorRequestPayloadRec
+{
+    NvU8 PinSelectionBitVector[NVEC_GPIO_MAX_BIT_VECTOR_BYTES];
+} NvEcGpioGetPinVectorRequestPayload;
+
+typedef struct NvEcGpioGetPinVectorResponsePayloadRec
+{
+    NvU8 DriveLevelBitVector[NVEC_GPIO_MAX_BIT_VECTOR_BYTES];
+} NvEcGpioGetPinVectorResponsePayload;
+
+typedef struct NvEcGpioConfigureEventReportingVectorRequestPayloadRec
+{
+    NvU8 ReportEnable;     // see NVEC_GPIO_REPORT_ENABLE* #define's
+    NvU8 PinSelectionBitVector[NVEC_GPIO_MAX_BIT_VECTOR_BYTES];
+} NvEcGpioConfigureEventReportingVectorRequestPayload;
+
+#define NVEC_GPIO_REPORT_ENABLE_0_ACTION_RANGE                          7:0
+#define NVEC_GPIO_REPORT_ENABLE_0_ACTION_DISABLE                        0x0
+#define NVEC_GPIO_REPORT_ENABLE_0_ACTION_ENABLE                         0x1
+
+typedef struct NvEcGpioAcknowledgeEventReportVectorRequestPayloadRec
+{
+    NvU8 PinSelectionBitVector[NVEC_GPIO_MAX_BIT_VECTOR_BYTES];
+} NvEcGpioAcknowledgeEventReportVectorRequestPayload;
+
+typedef struct NvEcGpioGetEventReportVectorRequestPayloadRec
+{
+    NvU8 PinSelectionBitVector[NVEC_GPIO_MAX_BIT_VECTOR_BYTES];
+} NvEcGpioGetEventReportVectorRequestPayload;
+
+typedef struct NvEcGpioGetEventReportVectorResponsePayloadRec
+{
+    NvU8 TriggerStatusBitVector[NVEC_GPIO_MAX_BIT_VECTOR_BYTES];
+} NvEcGpioGetEventReportVectorResponsePayload;
+
+typedef struct NvEcGpioConfigureWakeVectorRequestPayloadRec
+{
+    NvU8 WakeEnable;     // see NVEC_GPIO_WAKE_ENABLE* #define's
+    NvU8 PinSelectionBitVector[NVEC_GPIO_MAX_BIT_VECTOR_BYTES];
+} NvEcGpioConfigureWakeVectorRequestPayload;
+
+#define NVEC_GPIO_WAKE_ENABLE_0_ACTION_RANGE                            7:0
+#define NVEC_GPIO_WAKE_ENABLE_0_ACTION_DISABLE                          0x0
+#define NVEC_GPIO_WAKE_ENABLE_0_ACTION_ENABLE                           0x1
+
+/*******************************************************************************
+ *
+ * Sleep Request/Response details
+ *
+ */
+
+/**
+ * Sleep subtypes
+ */
+
+typedef enum
+{
+    NvEcSleepSubtype_GlobalConfigureEventReporting,
+
+    NvEcSleepSubtype_ApPowerDown = 0x1,
+    NvEcSleepSubtype_ApSuspend = 0x2,
+    NvEcSleepSubtype_ApRestart = 0x3,
+
+    NvEcSleepSubtype_Num,
+    NvEcSleepSubtype_Max = 0x7fffffff
+} NvEcSleepSubtype;
+
+/**
+ * Sleep payload data structures
+ */
+
+typedef struct NvEcSleepGlobalConfigureEventReportingRequestPayloadRec
+{
+    NvU8 GlobalReportEnable;     // see NVEC_SLEEP_GLOBAL_REPORT_ENABLE* #define's
+} NvEcSleepGlobalConfigureEventReportingRequestPayload;
+
+#define NVEC_SLEEP_GLOBAL_REPORT_ENABLE_0_ACTION_RANGE                  7:0
+#define NVEC_SLEEP_GLOBAL_REPORT_ENABLE_0_ACTION_DISABLE                0x0
+#define NVEC_SLEEP_GLOBAL_REPORT_ENABLE_0_ACTION_ENABLE                 0x1
+
+/*******************************************************************************
+ *
+ * Keyboard Request/Response details
+ *
+ */
+
+/**
+ * Keyboard subtypes
+ */
+
+typedef enum
+{
+    NvEcKeyboardSubtype_ConfigureWake = 0x3,
+    NvEcKeyboardSubtype_ConfigureWakeKeyReport,
+
+    NvEcKeyboardSubtype_Reset = 0xff,
+    NvEcKeyboardSubtype_Enable = 0xf4,
+    NvEcKeyboardSubtype_Disable = 0xf5,
+    NvEcKeyboardSubtype_SetScanCodeSet = 0xf1,
+    NvEcKeyboardSubtype_GetScanCodeSet = 0xf0,
+    NvEcKeyboardSubtype_SetLeds = 0xed,
+
+    NvEcKeyboardSubtype_Num,
+    NvEcKeyboardSubtype_Max = 0x7fffffff
+} NvEcKeyboardSubtype;
+
+/**
+ * Keyboard payload data structures
+ */
+
+typedef struct NvEcKeyboardConfigureWakeRequestPayloadRec
+{
+    NvU8 WakeEnable;     // see NVEC_KEYBOARD_WAKE_ENABLE* #define's
+    NvU8 EventTypes;     // see NVEC_KEYBOARD_EVENT_TYPE* #define's
+} NvEcKeyboardConfigureWakeRequestPayload;
+
+#define NVEC_KEYBOARD_WAKE_ENABLE_0_ACTION_RANGE                        7:0
+#define NVEC_KEYBOARD_WAKE_ENABLE_0_ACTION_DISABLE                      0x0
+#define NVEC_KEYBOARD_WAKE_ENABLE_0_ACTION_ENABLE                       0x1
+
+#define NVEC_KEYBOARD_EVENT_TYPE_0_SPECIAL_KEY_PRESS_RANGE              1:1
+#define NVEC_KEYBOARD_EVENT_TYPE_0_SPECIAL_KEY_PRESS_DISABLE            0x0
+#define NVEC_KEYBOARD_EVENT_TYPE_0_SPECIAL_KEY_PRESS_ENABLE             0x1
+
+#define NVEC_KEYBOARD_EVENT_TYPE_0_ANY_KEY_PRESS_RANGE                  0:0
+#define NVEC_KEYBOARD_EVENT_TYPE_0_ANY_KEY_PRESS_DISABLE                0x0
+#define NVEC_KEYBOARD_EVENT_TYPE_0_ANY_KEY_PRESS_ENABLE                 0x1
+
+typedef struct NvEcKeyboardConfigureWakeKeyReportingRequestPayloadRec
+{
+    NvU8 ReportWakeKey;     // see NVEC_KEYBOARD_REPORT_WAKE_KEY* #define's
+} NvEcKeyboardConfigureWakeKeyReportingRequestPayload;
+
+#define NVEC_KEYBOARD_REPORT_WAKE_KEY_0_ACTION_RANGE                    7:0
+#define NVEC_KEYBOARD_REPORT_WAKE_KEY_0_ACTION_DISABLE                  0x0
+#define NVEC_KEYBOARD_REPORT_WAKE_KEY_0_ACTION_ENABLE                   0x1
+
+typedef struct NvEcKeyboardSetScanCodeSetRequestPayloadRec
+{
+    NvU8 ScanSet;
+} NvEcKeyboardSetScanCodeSetRequestPayload;
+
+typedef struct NvEcKeyboardGetScanCodeSetResponsePayloadRec
+{
+    NvU8 ScanSet;
+} NvEcKeyboardGetScanCodeSetResponsePayload;
+
+typedef struct NvEcKeyboardSetLedsRequestPayloadRec
+{
+    NvU8 LedFlag;     // see NVEC_KEYBOARD_SET_LEDS* #define's
+} NvEcKeyboardSetLedsRequestPayload;
+
+#define NVEC_KEYBOARD_SET_LEDS_0_SCROLL_LOCK_LED_RANGE    2:2
+#define NVEC_KEYBOARD_SET_LEDS_0_SCROLL_LOCK_LED_ON       0x1
+#define NVEC_KEYBOARD_SET_LEDS_0_SCROLL_LOCK_LED_OFF      0x0
+
+#define NVEC_KEYBOARD_SET_LEDS_0_NUM_LOCK_LED_RANGE       1:1
+#define NVEC_KEYBOARD_SET_LEDS_0_NUM_LOCK_LED_ON          0x1
+#define NVEC_KEYBOARD_SET_LEDS_0_NUM_LOCK_LED_OFF         0x0
+
+#define NVEC_KEYBOARD_SET_LEDS_0_CAPS_LOCK_LED_RANGE      0:0
+#define NVEC_KEYBOARD_SET_LEDS_0_CAPS_LOCK_LED_ON         0x1
+#define NVEC_KEYBOARD_SET_LEDS_0_CAPS_LOCK_LED_OFF        0x0
+
+
+/*******************************************************************************
+ *
+ * AuxDevice Request/Response details
+ *
+ */
+
+/**
+ * AuxDevice subtypes
+ *
+ * Note that for AuxDevice's the subtype setting contains two bit-fields which
+ * encode the following information --
+ * * port id on which operation is to be performed
+ * * operation subtype to perform
+ */
+
+typedef enum
+{
+    NvEcAuxDeviceSubtype_Reset,
+    NvEcAuxDeviceSubtype_SendCommand,
+    NvEcAuxDeviceSubtype_ReceiveBytes,
+    NvEcAuxDeviceSubtype_AutoReceiveBytes,
+    NvEcAuxDeviceSubtype_CancelAutoReceive,
+    NvEcAuxDeviceSubtype_SetCompression,
+
+    NvEcAuxDeviceSubtype_ConfigureWake = 0x3d,
+
+    NvEcAuxDeviceSubtype_Num,
+    NvEcAuxDeviceSubtype_Max = 0x7fffffff
+} NvEcAuxDeviceSubtype;
+
+#define NVEC_SUBTYPE_0_AUX_PORT_ID_RANGE           7:6
+
+#define NVEC_SUBTYPE_0_AUX_PORT_ID_0               0x0
+#define NVEC_SUBTYPE_0_AUX_PORT_ID_1               0x1
+#define NVEC_SUBTYPE_0_AUX_PORT_ID_2               0x2
+#define NVEC_SUBTYPE_0_AUX_PORT_ID_3               0x3
+
+#define NVEC_SUBTYPE_0_AUX_PORT_SUBTYPE_RANGE      5:0
+
+/**
+ * AuxDevice payload data structures
+ */
+
+typedef struct NvEcAuxDeviceSendCommandRequestPayloadRec
+{
+    NvU8 Operation;
+    NvU8 NumBytesToReceive;
+} NvEcAuxDeviceSendCommandRequestPayload;
+
+typedef struct NvEcAuxDeviceReceiveBytesRequestPayloadRec
+{
+    NvU8 NumBytesToReceive;
+} NvEcAuxDeviceReceiveBytesRequestPayload;
+
+typedef struct NvEcAuxDeviceAutoReceiveBytesRequestPayloadRec
+{
+    NvU8 NumBytesToReceive;
+} NvEcAuxDeviceAutoReceiveBytesRequestPayload;
+
+typedef struct NvEcAuxDeviceSetCompressionRequestPayloadRec
+{
+    NvU8 CompressionEnable;     // see NVEC_AUX_DEVICE_SET_COMPRESSION* #define's
+} NvEcAuxDeviceSetCompressionRequestPayload;
+
+#define NVEC_AUX_DEVICE_COMPRESSION_ENABLE_0_ACTION_RANGE               0:0
+#define NVEC_AUX_DEVICE_COMPRESSION_ENABLE_0_ACTION_DISABLE             0x0
+#define NVEC_AUX_DEVICE_COMPRESSION_ENABLE_0_ACTION_ENABLE              0x1
+
+typedef struct NvEcAuxDeviceConfigureWakeRequestPayloadRec
+{
+    NvU8 WakeEnable;     // see NVEC_AUX_DEVICE_WAKE_ENABLE* #define's
+    NvU8 EventTypes;     // see NVEC_AUX_DEVICE_EVENT_TYPE* #define's
+} NvEcAuxDeviceConfigureWakeRequestPayload;
+
+#define NVEC_AUX_DEVICE_WAKE_ENABLE_0_ACTION_RANGE                      7:0
+#define NVEC_AUX_DEVICE_WAKE_ENABLE_0_ACTION_DISABLE                    0x0
+#define NVEC_AUX_DEVICE_WAKE_ENABLE_0_ACTION_ENABLE                     0x1
+
+#define NVEC_AUX_DEVICE_EVENT_TYPE_0_ANY_EVENT_RANGE                    0:0
+#define NVEC_AUX_DEVICE_EVENT_TYPE_0_ANY_EVENT_DISABLE                  0x0
+#define NVEC_AUX_DEVICE_EVENT_TYPE_0_ANY_EVENT_ENABLE                   0x1
+
+
+/*******************************************************************************
+ *
+ * Control Request/Response details
+ *
+ */
+
+/**
+ * Control subtypes
+ */
+
+typedef enum
+{
+    NvEcControlSubtype_Reset,
+    NvEcControlSubtype_SelfTest,
+    NvEcControlSubtype_NoOperation,
+
+    NvEcControlSubtype_GetSpecVersion = 0x10,
+    NvEcControlSubtype_GetCapabilities,
+    NvEcControlSubtype_GetConfiguration,
+    NvEcControlSubtype_GetProductName = 0x14,
+    NvEcControlSubtype_GetFirmwareVersion,
+
+    NvEcControlSubtype_InitializeGenericConfiguration = 0x20,
+    NvEcControlSubtype_SendGenericConfigurationBytes,
+    NvEcControlSubtype_FinalizeGenericConfiguration,
+
+    NvEcControlSubtype_InitializeFirmwareUpdate = 0x30,
+    NvEcControlSubtype_SendFirmwareBytes,
+    NvEcControlSubtype_FinalizeFirmwareUpdate,
+    NvEcControlSubtype_PollFirmwareUpdate,
+
+    NvEcControlSubtype_GetFirmwareSize = 0x40,
+    NvEcControlSubtype_ReadFirmwareBytes,
+
+    NvEcControlSubtype_Num,
+    NvEcControlSubtype_Max = 0x7fffffff
+} NvEcControlSubtype;
+
+/**
+ * Control payload data structures
+ */
+
+typedef struct NvEcControlGetSpecVersionResponsePayloadRec
+{
+    NvU8 Version;
+} NvEcControlGetSpecVersionResponsePayload;
+
+// extract 4-bit major version number from 8-bit version number
+#define NVEC_SPEC_VERSION_MAJOR(x)  (((x)>>4) & 0xf)
+
+// extract 4-bit minor version number from 8-bit version number
+#define NVEC_SPEC_VERSION_MINOR(x)  ((x) & 0xf)
+
+// assemble 8-bit version number from 4-bit major version number
+// and 4-bit minor version number
+#define NVEC_SPEC_VERSION(major, minor)  ((((major)&0xf) << 4) | ((minor)&0xf))
+
+#define NVEC_SPEC_VERSION_1_0  NVEC_SPEC_VERSION(1,0)
+
+typedef struct NvEcControlGetCapabilitiesResponsePayloadRec
+{
+    NvU8 Capabilities[2];     // see NVEC_CONTROL_CAPABILITIES* #define's
+    NvU8 OEMCapabilities[2];
+} NvEcControlGetCapabilitiesResponsePayload;
+
+#define NVEC_CONTROL_CAPABILITIES0_0_FIXED_SIZE_EVENT_PACKET_RANGE          4:4
+#define NVEC_CONTROL_CAPABILITIES0_0_FIXED_SIZE_EVENT_PACKET_NOT_SUPPORTED  0x0
+#define NVEC_CONTROL_CAPABILITIES0_0_FIXED_SIZE_EVENT_PACKET_SUPPORTED      0x1
+
+#define NVEC_CONTROL_CAPABILITIES0_0_NON_EC_WAKE_RANGE                      3:3
+#define NVEC_CONTROL_CAPABILITIES0_0_NON_EC_WAKE_NOT_SUPPORTED              0x0
+#define NVEC_CONTROL_CAPABILITIES0_0_NON_EC_WAKE_SUPPORTED                  0x1
+
+#define NVEC_CONTROL_CAPABILITIES0_0_GENERIC_CONFIGURATION_RANGE            0:0
+#define NVEC_CONTROL_CAPABILITIES0_0_GENERIC_CONFIGURATION_NOT_SUPPORTED    0x0
+#define NVEC_CONTROL_CAPABILITIES0_0_GENERIC_CONFIGURATION_SUPPORTED        0x1
+
+typedef struct NvEcControlGetConfigurationResponsePayloadRec
+{
+    NvU8 Configuration[2];     // see NVEC_CONTROL_CONFIGURATION* #define's
+    NvU8 OEMConfiguration[2];
+} NvEcControlGetConfigurationResponsePayload;
+
+#define NVEC_CONTROL_CONFIGURATION0_0_NUM_AUX_DEVICE_PORTS_RANGE        5:4
+#define NVEC_CONTROL_CONFIGURATION0_0_NUM_BATTERY_SLOTS_RANGE           3:0
+
+typedef struct NvEcControlGetProductNameResponsePayloadRec
+{
+    char ProductName[NVEC_MAX_RESPONSE_STRING_SIZE];
+} NvEcControlGetProductNameResponsePayload;
+
+typedef struct NvEcControlGetFirmwareVersionResponsePayloadRec
+{
+    NvU8 VersionMinor[2];
+    NvU8 VersionMajor[2];
+} NvEcControlGetFirmwareVersionResponsePayload;
+
+typedef struct NvEcControlInitializeGenericConfigurationRequestPayloadRec
+{
+    NvU8 ConfigurationId[4];
+} NvEcControlInitializeGenericConfigurationRequestPayload;
+
+typedef struct NvEcControlSendGenericConfigurationBytesResponsePayloadRec
+{
+    NvU8 NumBytes[4];
+} NvEcControlSendGenericConfigurationBytesResponsePayload;
+
+typedef struct NvEcControlSendFirmwareBytesResponsePayloadRec
+{
+    NvU8 NumBytes[4];
+} NvEcControlSendFirmwareBytesResponsePayload;
+
+typedef struct NvEcControlPollFirmwareUpdateResponsePayloadRec
+{
+    NvU8 Flag;     // see NVEC_CONTROL_POLL_FIRMWARE_UPDATE* #define's
+} NvEcControlPollFirmwareUpdateResponsePayload;
+
+#define NVEC_CONTROL_POLL_FIRMWARE_UPDATE_0_FLAG_RANGE                      7:0
+#define NVEC_CONTROL_POLL_FIRMWARE_UPDATE_0_FLAG_BUSY                       0x0
+#define NVEC_CONTROL_POLL_FIRMWARE_UPDATE_0_FLAG_READY                      0x1
+
+typedef struct NvEcControlGetFirmwareSizeResponsePayloadRec
+{
+    NvU8 NumBytes[4];
+} NvEcControlGetFirmwareSizeResponsePayload;
+
+
+/*******************************************************************************
+ *
+ * Keyboard Event details
+ *
+ */
+
+// there are no predefined structures for payload content; only the higher-level
+// keyboard driver will know how to interpret the payload data
+
+/*******************************************************************************
+ *
+ * Auxiliary Device Event details
+ *
+ */
+
+// there are no predefined structures for payload content; only the higher-level
+// auxiliary device driver will know how to interpret the payload data
+
+/*******************************************************************************
+ *
+ * System Event details
+ *
+ */
+
+typedef struct NvEcSystemEventPayloadRec
+{
+    NvU8 State[2];     // see NVEC_SYSTEM_STATE* #define's
+    NvU8 OEMState[2];
+} NvEcSystemEventPayload;
+
+/*******************************************************************************
+ *
+ * GPIO Scalar Event details
+ *
+ */
+
+typedef struct NvEcGpioScalarEventPayloadRec
+{
+    NvU8 LogicalPinNumber;
+} NvEcGpioScalarEventPayload;
+
+/*******************************************************************************
+ *
+ * GPIO Vector Event details
+ *
+ */
+
+typedef struct NvEcGpioVectorEventPayloadRec
+{
+    NvU8 TriggerStatusBitVector[NVEC_GPIO_MAX_BIT_VECTOR_BYTES];
+} NvEcGpioVectorEventPayload;
+
+/*******************************************************************************
+ *
+ * Battery Event details
+ *
+ */
+
+typedef struct NvEcBatteryEventPayloadRec
+{
+    NvU8 SlotNumber;
+    NvU8 SlotStatus;     // see NVEC_BATTERY_SLOT_STATUS* #define's
+} NvEcBatteryEventPayload;
+
+
+/*******************************************************************************
+ *
+ * Generic Configuration Package Header
+ *
+ */
+
+typedef struct NvEcGenericConfigurationPackageHeaderRec
+{
+    NvU8 MagicNumber[4];     // see NVEC_GENERIC_CONFIGURATION_MAGIC* #define's
+    NvU8 SpecVersion;
+    NvU8 Reserved0;
+    char ProductName[NVEC_MAX_RESPONSE_STRING_SIZE];
+    NvU8 FirmwareVersionMinor[2];
+    NvU8 FirmwareVersionMajor[2];
+    NvU8 ConfigurationID[4];
+    NvU8 BodyLength[4];
+    NvU8 Checksum[4];     // CRC-32 from IEEE 802.3
+} NvEcGenericConfigurationPackageHeader;
+
+#define NVEC_GENERIC_CONFIGURATION_MAGIC_HEADER_NUMBER_BYTE_0 'c'
+#define NVEC_GENERIC_CONFIGURATION_MAGIC_HEADER_NUMBER_BYTE_1 'n'
+#define NVEC_GENERIC_CONFIGURATION_MAGIC_HEADER_NUMBER_BYTE_2 'f'
+#define NVEC_GENERIC_CONFIGURATION_MAGIC_HEADER_NUMBER_BYTE_3 'g'
+
+/*******************************************************************************
+ *
+ * Firmware Update Package Header
+ *
+ */
+
+typedef struct NvEcFirmwareUpdatePackageHeaderRec
+{
+    NvU8 MagicNumber[4];     // see NVEC_FIRMWARE_UPDATE_MAGIC* #define's
+    NvU8 SpecVersion;
+    NvU8 Reserved0;
+    char ProductName[NVEC_MAX_RESPONSE_STRING_SIZE];
+    NvU8 FirmwareVersionMinor[2];
+    NvU8 FirmwareVersionMajor[2];
+    NvU8 BodyLength[4];
+    NvU8 Checksum[4];     // CRC-32 from IEEE 802.3
+} NvEcFirmwareUpdatePackageHeader;
+
+#define NVEC_FIRMWARE_UPDATE_HEADER_MAGIC_NUMBER_BYTE_0 'u'
+#define NVEC_FIRMWARE_UPDATE_HEADER_MAGIC_NUMBER_BYTE_1 'p'
+#define NVEC_FIRMWARE_UPDATE_HEADER_MAGIC_NUMBER_BYTE_2 'd'
+#define NVEC_FIRMWARE_UPDATE_HEADER_MAGIC_NUMBER_BYTE_3 't'
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvec_device.h b/arch/arm/mach-tegra/nv/include/nvec_device.h
new file mode 100644
index 000000000000..71c1f761906b
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvec_device.h
@@ -0,0 +1,81 @@
+/*

+ * Copyright (c) 2010 NVIDIA Corporation.

+ * All rights reserved.

+ *

+ * Redistribution and use in source and binary forms, with or without

+ * modification, are permitted provided that the following conditions are met:

+ *

+ * Redistributions of source code must retain the above copyright notice,

+ * this list of conditions and the following disclaimer.

+ *

+ * Redistributions in binary form must reproduce the above copyright notice,

+ * this list of conditions and the following disclaimer in the documentation

+ * and/or other materials provided with the distribution.

+ *

+ * Neither the name of the NVIDIA Corporation nor the names of its contributors

+ * may be used to endorse or promote products derived from this software

+ * without specific prior written permission.

+ *

+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"

+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE

+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE

+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE

+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR

+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF

+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS

+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN

+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)

+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE

+ * POSSIBILITY OF SUCH DAMAGE.

+ *

+ */

+

+#ifndef INCLUDED_NVEC_DEVICE_H

+#define INCLUDED_NVEC_DEVICE_H

+

+

+#if defined(__cplusplus)

+extern "C"

+{

+#endif

+

+#define nvec_get_drvdata(f)     dev_get_drvdata(&(f)->dev)

+#define nvec_set_drvdata(f,d)   dev_set_drvdata(&(f)->dev, d)

+

+struct nvec_driver;

+

+struct nvec_device {

+	char *name;

+	struct device		*parent;

+	struct device dev;

+	struct bus_type	*bus;		/* type of bus device is on */

+	struct nvec_driver *driver;	/* which driver has allocated this

+					   device */

+};

+

+extern int nvec_register_device(struct nvec_device *pdev);

+extern void nvec_unregister_device(struct nvec_device *pdev);

+

+/*

+ * NVEC function device driver

+ */

+struct nvec_driver {

+	char *name;

+	struct device_driver driver;

+	struct device dev;

+

+	int (*probe)(struct nvec_device *);

+	void (*remove)(struct nvec_device *);

+

+	int (*suspend)(struct nvec_device *dev, pm_message_t state);

+	int (*resume)(struct nvec_device *dev);

+};

+

+extern int nvec_register_driver(struct nvec_driver *);

+extern void nvec_unregister_driver(struct nvec_driver *);

+

+#if defined(__cplusplus)

+}

+#endif

+

+#endif // INCLUDED_NVEC_DEVICE_H

diff --git a/arch/arm/mach-tegra/nv/include/nverror.h b/arch/arm/mach-tegra/nv/include/nverror.h
new file mode 100644
index 000000000000..8aa4ae9ce452
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nverror.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVERROR_H
+#define INCLUDED_NVERROR_H
+
+/** 
+ * @defgroup nverror Error Handling
+ * 
+ * nverror.h contains our error code enumeration and helper macros.
+ * 
+ * @{
+ */
+
+/**
+ * The NvError enumeration contains ALL return / error codes.  Error codes
+ * are specifically explicit to make it easy to identify where an error
+ * came from.  
+ * 
+ * All error codes are derived from the macros in nverrval.h.
+ * @ingroup nv_errors 
+ */
+typedef enum
+{
+#define NVERROR(_name_, _value_, _desc_) NvError_##_name_ = _value_,
+    /* header included for macro expansion of error codes */
+    #include "nverrval.h"
+#undef NVERROR
+
+    // An alias for success
+    NvSuccess = NvError_Success,
+
+    NvError_Force32 = 0x7FFFFFFF
+} NvError;
+
+/**
+ * A helper macro to check a function's error return code and propagate any
+ * errors upward.  This assumes that no cleanup is necessary in the event of
+ * failure.  This macro does not locally define its own NvError variable out of
+ * fear that this might burn too much stack space, particularly in debug builds
+ * or with mediocre optimizing compilers.  The user of this macro is therefore
+ * expected to provide their own local variable "NvError e;".
+ */
+#define NV_CHECK_ERROR(expr) \
+    do \
+    { \
+        e = (expr); \
+        if (e != NvSuccess) \
+            return e; \
+    } while (0)
+
+/**
+ * A helper macro to check a function's error return code and, if an error
+ * occurs, jump to a label where cleanup can take place.  Like NV_CHECK_ERROR,
+ * this macro does not locally define its own NvError variable.  (Even if we
+ * wanted it to, this one can't, because the code at the "fail" label probably
+ * needs to do a "return e;" to propagate the error upwards.)
+ */
+#define NV_CHECK_ERROR_CLEANUP(expr) \
+    do \
+    { \
+        e = (expr); \
+        if (e != NvSuccess) \
+            goto fail; \
+    } while (0)
+
+
+/**
+ * Prints err if it is an error (does nothing if err==NvSuccess).
+ * Always returns err unchanged
+ * never prints anything if err==NvSuccess)
+ *
+ * NOTE: Do not use this with errors that are expected to occur under normal
+ * situations.
+ *
+ * @param err - the error to return
+ * @returns err
+ */
+#define NV_SHOW_ERRORS  NV_DEBUG
+#if     NV_SHOW_ERRORS
+#define NV_SHOW_ERROR(err)  NvOsShowError(err,__FILE__,__LINE__)
+#else
+#define NV_SHOW_ERROR(err)  (err)
+#endif
+
+
+/** @} */
+
+#endif // INCLUDED_NVERROR_H
diff --git a/arch/arm/mach-tegra/nv/include/nverrval.h b/arch/arm/mach-tegra/nv/include/nverrval.h
new file mode 100755
index 000000000000..8be2cbf92093
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nverrval.h
@@ -0,0 +1,383 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * nverrval.h is a header used for macro expansion of the errors defined for
+ * the Nv methods & interfaces.
+ *
+ * This header is NOT protected from being included multiple times, as it is
+ * used for C pre-processor macro expansion of error codes, and the
+ * descriptions of those error codes.
+ *
+ * Each error code has a unique name, description and value to make it easier
+ * for developers to identify the source of a failure.  Thus there are no
+ *generic or unknown error codes.
+ */
+
+/**
+* @defgroup nv_errors NVIDIA Error Codes
+*
+* Provides return error codes for functions.
+*
+* @ingroup nvodm_errors
+* @{
+*/
+
+/** common error codes */
+NVERROR(Success,                            0x00000000, "success")
+NVERROR(NotImplemented,                     0x00000001, "method or interface is not implemented")
+NVERROR(NotSupported,                       0x00000002, "requested operation is not supported")
+NVERROR(NotInitialized,                     0x00000003, "method or interface is not initialized")
+NVERROR(BadParameter,                       0x00000004, "bad parameter to method or interface")
+NVERROR(Timeout,                            0x00000005, "not completed in the expected time")
+NVERROR(InsufficientMemory,                 0x00000006, "insufficient system memory")
+NVERROR(ReadOnlyAttribute,                  0x00000007, "cannot write a read-only attribute")
+NVERROR(InvalidState,                       0x00000008, "module is in invalid state to perform the requested operation")
+NVERROR(InvalidAddress,                     0x00000009, "invalid address")
+NVERROR(InvalidSize,                        0x0000000A, "invalid size")
+NVERROR(BadValue,                           0x0000000B, "illegal value specified for parameter")
+NVERROR(AlreadyAllocated,                   0x0000000D, "resource has already been allocated")
+NVERROR(Busy,                               0x0000000E, "busy, try again")
+NVERROR(ModuleNotPresent,                   0x000a000E, "hw module is not peresent")
+NVERROR(ResourceError,                      0x0000000F, "clock, power, or pinmux resource error")
+NVERROR(CountMismatch,                      0x00000010, "Encounter Error on count mismatch")
+
+/* surface specific error codes */
+NVERROR(InsufficientVideoMemory,            0x00010000, "insufficient video memory")
+NVERROR(BadSurfaceColorScheme,              0x00010001, "this surface scheme is not supported in the current controller")
+NVERROR(InvalidSurface,                     0x00010002, "invalid surface")
+NVERROR(SurfaceNotSupported,                0x00010003, "surface is not supported")
+
+/* display specific error codes */
+NVERROR(DispInitFailed,                     0x00020000, "display initialization failed")
+NVERROR(DispAlreadyAttached,                0x00020001, "the display is already attached to a controller")
+NVERROR(DispTooManyDisplays,                0x00020002, "the controller has too many displays attached")
+NVERROR(DispNoDisplaysAttached,             0x00020003, "the controller does not have an attached display")
+NVERROR(DispModeNotSupported,               0x00020004, "the mode is not supported by the display or controller")
+NVERROR(DispNotFound,                       0x00020005, "the requested display was not found")
+NVERROR(DispAttachDissallowed,              0x00020006, "the display cannot attach to the given controller")
+NVERROR(DispTypeNotSupported,               0x00020007, "display type not supported")
+NVERROR(DispAuthenticationFailed,           0x00020008, "display authenication failed")
+NVERROR(DispNotAttached,                    0x00020009, "display not attached")
+NVERROR(DispSamePwrState,                   0x0002000A, "display already in requested power state")
+NVERROR(DispEdidFailure,                    0x0002000B, "edid read/parsing failure")
+
+/* NvOs error codes */
+NVERROR(FileWriteFailed,                    0x00030000, "the file write operation failed")
+NVERROR(FileReadFailed,                     0x00030001, "the file read operation failed")
+NVERROR(EndOfFile,                          0x00030002, "the end of file has been reached")
+NVERROR(FileOperationFailed,                0x00030003, "the file operation has failed")
+NVERROR(DirOperationFailed,                 0x00030004, "the directory operation has failed")
+NVERROR(EndOfDirList,                       0x00030005, "there are no more entries in the directory")
+NVERROR(ConfigVarNotFound,                  0x00030006, "the configuration variable is not present")
+NVERROR(InvalidConfigVar,                   0x00030007, "the configuration variable is corrupted")
+NVERROR(LibraryNotFound,                    0x00030008, "the dynamic library was not found for open")
+NVERROR(SymbolNotFound,                     0x00030009, "the symbol in a dyanmic library was not found")
+NVERROR(MemoryMapFailed,                    0x0003000a, "the memory mapping operation failed")
+NVERROR(IoctlFailed,                        0x0003000f, "the ioctl failed")
+NVERROR(AccessDenied,                       0x00030010, "the pointer is invalid or require additional privileges for access")
+NVERROR(DeviceNotFound,                     0x00030011, "requested device is not found")
+NVERROR(KernelDriverNotFound,               0x00030012, "kernel driver not found")
+NVERROR(FileNotFound,                       0x00030013, "File or directory not found")
+
+/* I/O devices */
+NVERROR(SpiReceiveError,                    0x00040000, "spi receive error" )
+NVERROR(SpiTransmitError,                   0x00040001, "spi transmit error" )
+NVERROR(HsmmcCardNotPresent,                0x00041000, "hsmmc card not present")
+NVERROR(HsmmcControllerBusy,                0x00041001, "hsmmc controller is busy")
+NVERROR(HsmmcAutoDetectCard,                0x00041002, "auto detect the card in hsmmc slot")
+NVERROR(SdioCardNotPresent,                 0x00042000, "sdio card not present")
+NVERROR(SdioInstanceTaken,                  0x00042001, "Instance unavailable or in use")
+NVERROR(SdioControllerBusy,                 0x00042002, "controller is busy")
+NVERROR(SdioReadFailed,                     0x00042003, "read transaction has failed")
+NVERROR(SdioWriteFailed,                    0x00042004, "write transaction has failed")
+NVERROR(SdioBadBlockSize,                   0x00042005, "bad block size")
+NVERROR(SdioClockNotConfigured,             0x00042006, "Clock is not configured")
+NVERROR(SdioSdhcPatternIntegrityFailed,     0x00042007, "SDHC Check pattern integrity failed")
+NVERROR(SdioCommandFailed,                  0x00042008, "command failed to execute")
+NVERROR(SdioCardAlwaysPresent,              0x00042009, "sdio card is soldered")
+NVERROR(SdioAutoDetectCard,                 0x0004200a, "auto detect the sd card")
+NVERROR(UsbInvalidEndpoint,                 0x00043000, "usb invalid endpoint")
+NVERROR(UsbfTxfrActive,                     0x00043001, "The endpoint has an active transfer in progress.")
+NVERROR(UsbfTxfrComplete,                   0x00043002, "The endpoint has a completed transfer that has not been cleared.")
+NVERROR(UsbfTxfrFail,                       0x00043003, "The endpoint transfer is failed.")
+NVERROR(UsbfEpStalled,                      0x00043004, "The endpoint has been placed in a halted or stalled state.")
+NVERROR(UsbfCableDisConnected,              0x00043005, "usb cable disconnected")
+NVERROR(UartOverrun,                        0x00044000, "overrun occurred when receiving the data")
+NVERROR(UartFraming,                        0x00044001, "data received had framing error")
+NVERROR(UartParity,                         0x00044002, "data received had parity error")
+NVERROR(UartBreakReceived,                  0x00044004, "received break signal")
+NVERROR(I2cReadFailed,                      0x00045000, "Failed to read data through I2C")
+NVERROR(I2cWriteFailed,                     0x00045001, "Failed to write data through I2C")
+NVERROR(I2cDeviceNotFound,                  0x00045003, "Slave Device Not Found")
+NVERROR(I2cInternalError,                   0x00045004, "The controller reports the error during transaction like fifo overrun, underrun")
+NVERROR(I2cArbitrationFailed,               0x00045005, "Master does not able to get the control of bus")
+NVERROR(IdeHwError,                         0x00046000, "Ide HW error")
+NVERROR(IdeReadError,                       0x00046001, "Ide read error")
+NVERROR(IdeWriteError,                      0x00046002, "Ide write error")
+
+/* OWR error codes */
+NVERROR(OwrReadFailed,                      0x00047000, "OWR data reading failed")
+NVERROR(OwrWriteFailed,                     0x00047001, "OWR data write failed")
+NVERROR(OwrBitTransferFailed,               0x00047002, "OWR bit transfer failed")
+NVERROR(OwrInvalidOffset,                   0x00047003, "OWR invalid offset")
+
+/* Nv2D error codes */
+NVERROR(InvalidOperation,                   0x00050000, "invalid operation")
+
+/* NvRm error codes */
+NVERROR(RmInitFailed,                       0x00060000, "rm failed to initialize")
+NVERROR(RmChannelInitFailure,               0x00060001, "channel init failed")
+NVERROR(RmStreamInitFailure,                0x00060002, "stream init failed")
+NVERROR(RmSyncPointAllocFailure,            0x00060003, "sync point alloc failed")
+NVERROR(ResourceAlreadyInUse,               0x00060004, "resource already in use")
+NVERROR(DmaBusy,                            0x00061000, "the dma channel is busy and not able to take any more request")
+NVERROR(InvalidSourceId,                    0x00061001, "invalid source id")
+NVERROR(DmaChannelNotAvailable,             0x00061002, "dma channel not available")
+
+/* NvIsp error codes */
+NVERROR(NoConnectedImager,                  0x00070001, "no imager connected")
+NVERROR(UnsupportedResolution,              0x00070002, "unsupported resolution")
+NVERROR(I2CCommunicationError,              0x00070003, "i2c communication failed")
+NVERROR(IspConfigFileParseError,            0x00070004, "isp config file parse error")
+NVERROR(TooDark,                            0x00070006, "image too dark for 3A operation")
+NVERROR(InvalidIspConfigAttribute,          0x00070007, "invalid isp config attribute")
+NVERROR(InvalidIspConfigAttributeElement,   0x00070008, "invalid isp config attribute element")
+NVERROR(IspConfigSyntaxError,               0x00070009, "isp config syntax error")
+NVERROR(ImagerVersionNotSupported,          0x0007000A, "imager version not supported")
+NVERROR(CorruptedBuffer,                    0x0007000B, "buffer is corrupted")
+
+
+/* NvTest error codes */
+NVERROR(TestApplicationFailed,              0x00080000, "the test application failed")
+NVERROR(TestNoUserInput,                    0x00080001, "no user input available")
+NVERROR(TestCommandLineError,               0x00080002, "command line parsing error")
+NVERROR(TestDataVerificationFailed,         0x00080003, "Data verification failed error")
+NVERROR(TestServerFileReadFailed,           0x00081000, "reading the test file failed")
+NVERROR(TestServerInvalidAddress,           0x00081001, "invalid connection address")
+NVERROR(TestServerMemoryLimitExceeded,      0x00081002, "target memory limit exceeded")
+
+/* NvCam error codes */
+NVERROR(ColorFormatNotSupported,            0x00090006, "color format not supported")
+
+/* Transport error codes */
+NVERROR(TransportPortAlreadyExist,          0x000A0001, "The port name already exist.")
+NVERROR(TransportMessageBoxEmpty,           0x000A0003, "Received Message box empty.")
+NVERROR(TransportMessageBoxFull,            0x000A0004, "Message box is full and not able to send the message.")
+NVERROR(TransportConnectionFailed,          0x000A0006, "Making connection to port is failed.")
+NVERROR(TransportNotConnected,              0x000A0007, "Port is not connected.")
+
+/* Nand error codes */
+NVERROR(NandReadFailed,                     0x000B0000, "Nand Read failed")
+NVERROR(NandProgramFailed,                  0x000B0001, "Nand Program failed")
+NVERROR(NandEraseFailed,                    0x000B0002, "Nand Erase failed")
+NVERROR(NandCopyBackFailed,                 0x000B0003, "Nand Copy back failed")
+NVERROR(NandOperationFailed,                0x000B0004, "requested Nand operation failed")
+NVERROR(NandBusy,                           0x000B0005, "Nand operation incomplete and is busy")
+NVERROR(NandNotOpened,                      0x000B0006, "Nand driver not opened")
+NVERROR(NandAlreadyOpened,                  0x000B0007, "Nand driver is already opened")
+NVERROR(NandBadOperationRequest,            0x000B0008, "status for wrong nand operation is requested ")
+NVERROR(NandCommandQueueError,              0x000B0009, "Command queue error occured ")
+NVERROR(NandReadEccFailed,                  0x000B0010, "Read with ECC resulted in uncorrectable errors")
+NVERROR(NandFlashNotSupported,              0x000B0011, "Nand flash on board is not supported by the ddk")
+NVERROR(NandLockFailed,                     0x000B0012, "Nand flash lock feature failed")
+NVERROR(NandErrorThresholdReached,          0x000B0013, "Ecc errors reached the threshold set")
+NVERROR(NandWriteFailed,                    0x000B0014, "Nand Write failed")
+NVERROR(NandBadBlock,                       0x000B0015, "Indicates a bad block on media")
+NVERROR(NandBadState,                       0x000B0016, "Indicates an invalid state")
+NVERROR(NandBlockIsLocked,                  0x000B0017, "Indicates the block is locked")
+NVERROR(NandNoFreeBlock,                    0x000B0018, "Indicates there is no free block in the flash")
+NVERROR(NandTTFailed,                       0x000B0019, "Nand TT Failure")
+NVERROR(NandTLFailed,                       0x000B001A, "Nand TL Failure")
+NVERROR(NandTLNoBlockAssigned,              0x000B001B, "Nand TL No Block Assigned")
+
+/* nvwinsys error codes */
+NVERROR(WinSysBadDisplay,                   0x000C0000, "bad display specified")
+NVERROR(WinSysNoDevice,                     0x000C0001, "no device found")
+NVERROR(WinSysBadDrawable,                  0x000C0002, "bad drawable")
+
+/* nvblserver error codes */
+NVERROR(BLServerFileReadFailed,             0x000D0000, "reading the bootloader file failed")
+NVERROR(BLServerInvalidAddress,             0x000D0001, "invalid connection address")
+NVERROR(BLServerInvalidElfFile,             0x000D0002, "invalid elf file")
+NVERROR(BLServerConnectionFailed,           0x000D0003, "connection with target failed")
+NVERROR(BLServerMemoryLimitExceeded,        0x000D0005, "target memory limit exceeded")
+
+/* NvMM Audio Mixer error codes */
+NVERROR(AudioMixerPinTypeNotSupported,      0x000E0000, "Pin type is not supported")
+NVERROR(AudioMixerDirectionNotSupported,    0x000E0001, "Pin direction is not supported")
+NVERROR(AudioMixerNoMorePinsAvailable,      0x000E0002, "No more pins are available")
+NVERROR(AudioMixerBadPinNumber,             0x000E0003, "Bad pin number")
+
+/* NvMM Video Encoder error codes */
+NVERROR(VideoEncResolutionNotSupported,     0x000E1000, "Resolution parameters must be multiple of 16")
+
+/* NvMM JPEG Encoder error codes */
+NVERROR(JPEGEncHWError,                     0x000E2000, "HW encountered some error in Encoding: either ICQ is full or MEMDMA is busy")
+
+/* NvMM Video Decoder error codes */
+NVERROR(VideoDecRetainLock,                    0x000E3001, "Keep the HW lock with the decoder")
+NVERROR(VideoDecMataDataFound,                 0x000E3002, "Decoder has decoded Mata Data Information")
+NVERROR(VideoDecFrameDecoded,                  0x000E3004, "Decoder has decoded one complete Frame")
+NVERROR(VideoDecDecodedPartialFrame,           0x000E3008, "Decoder has decoded Frame Partially")
+NVERROR(VideoDecInsufficientBitstream,         0x000E3010, "unable to decode because of unavailablity of bitstream for decoding")
+NVERROR(VideoDecOutputSurfaceUnavailable,      0x000E3020, "Output surface is unavailable for storing current decoded frame")
+NVERROR(VideoDecUnsupportedStreamFormat,       0x000E3040, "Given i/p Stream format is not supported by Video Decoder")
+NVERROR(VideoDecFrameDecodedPlusVideoDecEvent, 0x000E3080, "Decoder has decoded one complete frame and need to send event to client")
+NVERROR(VideoDecFailed,                        0x000E3100, "Failed to decode")
+NVERROR(VideoDecDecodingComplete,              0x000E3200, "Decoder has finished decoding")
+NVERROR(VideoDecProvideNextIPBuffer,           0x000E3400, "Decoder is still using current buffer,mean while provide next ip buffer")
+NVERROR(VideoDecProvideCurrentIPBuffer,        0x000E3800, "provide Current ip buffer again")
+
+/* Vibrate shim error codes */
+NVERROR(PipeNotConnected,                      0x000F0000, "Indicates that there are no readers attached to the message queue")
+NVERROR(ReadQNotCreated,                       0x000F0001, "Some error creating the read message Q")
+
+/* Content Parser, Writer, Pipe error codes */
+NVERROR(ParserEndOfStream,                  0x00100000, "the end of stream has been reached")
+NVERROR(ParserFailedToGetData,              0x00100001, "Could not get data because of some Error")
+NVERROR(InSufficientBufferSize,             0x00100002, "InSufficientBufferSize for parser to read data")
+NVERROR(ParserReadFailure,                  0x00100003, "Encounter Error on parser reads")
+NVERROR(ParserOpenFailure,                  0x00100004, "Encounter Error on parser open")
+NVERROR(UnSupportedStream,                  0x00100005, "Error for Unsupported streams")
+NVERROR(ParserFailure,                      0x00100006, "Fail to Parse the file. Or General/logical Error encounter on other parser failures")
+NVERROR(ParserHeaderDecodeNotComplete,      0x00100007, "Could not get data because Header Decode is not complete")
+NVERROR(ParserCloseFailure,                 0x00100008, "Encounter Error on parser close")
+NVERROR(ParserMarkerHit,                    0x00100009, "Parser Marker HIT")
+NVERROR(ParserCorruptedStream,              0x0010000A, "Encounter error on corrupted Parser stream")
+NVERROR(ParserDRMLicenseNotFound,           0x0010000B, "DRM License Not Found")
+NVERROR(ParserDRMFailure,                   0x0010000C, "DRM Functionality Failed")
+NVERROR(ParserSeekUnSupported,              0x0010000D, "Seek UnSupported dueto non-index rntries etc., ")
+NVERROR(ParserTrickModeUnSupported,         0x0010000E, "Seek UnSupported dueto non-index rntries etc., ")
+NVERROR(ParserCoreNotCreated,               0x0010000F, "Core not created ")
+NVERROR(UnSupported_VideoStream,            0x00100010, "Error for Unsupported streams")
+NVERROR(UnSupported_AudioStream,            0x00100011, "Error for Unsupported streams")
+NVERROR(WriterOpenFailure,                  0x00101001, "Encounter Error on writer open")
+NVERROR(WriterUnsupportedStream,            0x00101002, "Error for Unsupported streams in writer")
+NVERROR(WriterUnsupportedUserData,          0x00101003, "Error Unsupported user data  set in writer")
+NVERROR(WriterFileSizeLimitExceeded,        0x00101004, "File size limit exceeded in writer")
+NVERROR(WriterInsufficientMemory,           0x00101005, "Insufficient memory in writer")
+NVERROR(WriterFailure,                      0x00101006, "General/logical Error encounter on other writer failures")
+NVERROR(WriterCloseFailure,                 0x00101007, "Encounter Error on writer close")
+NVERROR(WriterInitFailure,                  0x00101008, "Writer Init Failed")
+NVERROR(WriterFileWriteLimitExceeded,       0x00101009, "File Write limit exceeded in writer")
+NVERROR(ContentPipeNoData,                  0x00102001, "Data not available")
+NVERROR(ContentPipeNoFreeBuffers,           0x00102002, "No free buffers")
+NVERROR(ContentPipeSpareAreaInUse,          0x00102003, "Spare buffer is in use")
+NVERROR(ContentPipeEndOfStream,             0x00102004, "End of stream reached")
+NVERROR(ContentPipeNotReady,                0x00102005, "Not Ready")
+NVERROR(ContentPipeInNonCachingMode,        0x00102006, "In non-caching mode")
+NVERROR(ContentPipeInsufficientMemory,      0x00102007, "Insufficient memory in ContentPipe")
+NVERROR(ContentPipeNotInvalidated,          0x00102008, "ContentPipe memory is not invalidated")
+
+NVERROR(UnSupportedMetadata,                0x00102009, "UnSupportedMetadata")
+NVERROR(MetadataSuccess,                    0x0010200A, "Successfully Extracted the Metadata key")
+NVERROR(MetadataFailure,                    0x0010200B, "Error Encountered during Meta data Extraction")
+NVERROR(NewMetaDataAvailable,               0x0010200C, "NewMetaDataAvailable")
+
+/* TrackList error codes */
+NVERROR(TrackListInvalidTrackIndex,         0x00110001, "Invalid track number")
+NVERROR(TrackListError,                     0x00110002, "Error encounterd in TrackList Operation")
+NVERROR(TrackListItemStillPlayingError,     0x00110003, " Track list item is currently playing")
+NVERROR(TrackListNotPlaying,                0x00110004, " Track list is not playing")
+
+/* nv3p error codes */
+NVERROR(Nv3pUnrecoverableProtocol,          0x00120000, "unrecoverable protocol error")
+NVERROR(Nv3pBadPacketType,                  0x00120001, "bad packet type")
+NVERROR(Nv3pPacketNacked,                   0x00120002, "packet was nacked")
+NVERROR(Nv3pBadReceiveLength,               0x00120003, "bad receive length")
+NVERROR(Nv3pBadReturnData,                  0x00120004, "bad return data")
+
+/* AES error codes */
+NVERROR(AesClearSbkFailed,                  0x00130000, "AES clear Secure Boot Key Failed")
+NVERROR(AesLockSskFailed,                   0x00130001, "AES Lock Secure Storage Key Failed")
+NVERROR(AesDisableCryptoFailed,             0x00130002, "AES disable crypto failed")
+
+/* Block Driver error codes */
+/* generic error codes */
+NVERROR(BlockDriverIllegalIoctl,            0x00140001, "Block Driver illegal IOCTL invoked")
+NVERROR(BlockDriverOverlappedPartition,     0x00140002, "Block Driver partition overlap")
+NVERROR(BlockDriverNoPartition,             0x00140003, "Block Driver IOCTL call needs partition create")
+NVERROR(BlockDriverIllegalPartId,           0x00140004, "Block Driver operation using illegal partition ID")
+NVERROR(BlockDriverWriteVerifyFailed,       0x00140005, "Block Driver write data comparison failed")
+/* Nand specific block driver errors */
+NVERROR(NandBlockDriverEraseFailure,        0x00140011, "Nand Block Driver erase failed")
+NVERROR(NandBlockDriverWriteFailure,        0x00140012, "Nand Block Driver write failed")
+NVERROR(NandBlockDriverReadFailure,         0x00140013, "Nand Block Driver read failed")
+NVERROR(NandBlockDriverLockFailure,         0x00140014, "Nand Block Driver lock failed")
+NVERROR(NandRegionIllegalAddress,           0x00140015, "Nand Block Driver sector access illegal")
+NVERROR(NandRegionTableOpFailure,           0x00140016, "Nand Block Driver region operation failed")
+NVERROR(NandBlockDriverMultiInterleave,     0x00140017, "Nand Block Driver multiple interleave modes")
+NVERROR(NandTagAreaSearchFailure,           0x0014001c, "Nand Block Driver tag area search failed")
+/* EMMC specific block driver errors */
+NVERROR(EmmcBlockDriverLockNotSupported,    0x00140101, "EMMC Block Driver Lock operation not supported")
+NVERROR(EmmcBlockDriverLockUnaligned,       0x00140102, "EMMC Block Driver Lock area size or location unaligned")
+NVERROR(EmmcBlockDriverIllegalStateRead,    0x00140103, "EMMC Block Driver Read when state is not TRANS")
+NVERROR(EmmcBlockDriverIllegalStateWrite,   0x00140104, "EMMC Block Driver Write when state is not TRANS")
+NVERROR(EmmcCommandFailed,                  0x00140105, "EMMC Block Driver command failed to execute")
+NVERROR(EmmcReadFailed,                     0x00140106, "EMMC Block Driver Read failed")
+NVERROR(EmmcWriteFailed,                    0x00140107, "EMMC Block Driver Write failed")
+NVERROR(EmmcBlockDriverEraseFailure,        0x00140108, "Emmc Block Driver erase failed")
+NVERROR(EmmcBlockDriverIllegalAddress,      0x00140109, "Emmc Block Driver address is illegal or misaligned")
+NVERROR(EmmcBlockDriverLockFailure,         0x0014010A, "Emmc Block Driver lock failed")
+NVERROR(EmmcBlockDriverBlockIsLocked,       0x0014010B, "Emmc Block Driver Accessed block is locked")
+/* Mipi Hsi error codes */
+NVERROR(MipiHsiTxFifoEmpty,                 0x00140200, "TX_FIFO_CNT in Status and Interrupt Identification Register is zero")
+NVERROR(MipiHsiRxFifoEmpty,                 0x00140201, "RX_FIFO_CNT in Status and Interrupt Identification Register is zero")
+NVERROR(MipiHsiBusy,                        0x00140202, "Mipi Hsi controller is busy")
+NVERROR(MipiHsiHandleNotConfigured,         0x00140203, "Mipi Hsi handle is not configured")
+NVERROR(MipiHsiTransmitError,               0x00140204, "Mipi Hsi transmit error - check the write function ")
+NVERROR(MipiHsiReceiveError,                0x00140205, "Mipi Hsi receive error - check the read function")
+NVERROR(MipiHsiTransferIncomplete,          0x00140206, "Mipi Hsi requested number of packets are not transferred")
+
+/* Shader compiler error codes */
+NVERROR(SCCompileFail,                      0x00150000, "Source shader compilation failed")
+
+/* Drm error codes */
+NVERROR(DrmFailure,                         0x00160000, "Drm - Failed")
+NVERROR(DrmInvalidArg,                      0x00160001, "Drm Invalid arguments passed")
+NVERROR(DrmOutOfMemory,                     0x00160002, "Drm-Memory insufficent")
+NVERROR(DrmFileNotFound,                    0x00160003, "Drm - File not found")
+NVERROR(DrmBufferTooSmall,                  0x00160004, "Drm- Buffer size passed is too small")
+NVERROR(DrmInvalidLicense,                  0x00160005, "Drm - Invalid license")
+NVERROR(DrmLicenseExpired,                  0x00160006, "Drm- License expired")
+NVERROR(DrmRightsNotAvailable,              0x00160007, "Drm-Right are not available")
+NVERROR(DrmLicenseNotFound,                 0x00160008, "Drm - License it not found")
+NVERROR(DrmInvalidBindId,                   0x00160009, "Drm - Invalid Bind Id ")
+NVERROR(DrmVersionNotSupported,             0x0016000a, "Drm-Unsupported Version")
+NVERROR(DrmMeteringNotSupported,            0x0016000b, "Drm- Metering is not supported")
+NVERROR(DrmDecryptionFailed,                0x0016000c, "Drm- Decryption failed")
+/* System Update error codes */
+NVERROR(SysUpdateInvalidBLVersion,          0x00170000, "NvSysUpdate - InvalidBL Version")
+
+/** @} */
+/* ^^^ ADD ALL NEW ERRORS RIGHT ABOVE HERE ^^^ */
diff --git a/arch/arm/mach-tegra/nv/include/nvfw.h b/arch/arm/mach-tegra/nv/include/nvfw.h
new file mode 100644
index 000000000000..e6b496b5d6e0
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvfw.h
@@ -0,0 +1,54 @@
+/*
+ * arch/arm/mach-tegra/include/linux/nvfw_ioctl.h
+ *
+ * structure declarations for nvfw ioctls
+ *
+ * Copyright (c) 2009, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/ioctl.h>
+
+#if !defined(__KERNEL__)
+#define __user
+#endif
+
+#ifndef _MACH_TEGRA_NVFW_IOCTL_H_
+#define _MACH_TEGRA_NVFW_IOCTL_H_
+
+struct nvfw_load_handle {
+	const char *filename;
+	int length;
+	void *args;
+	int argssize;
+	int greedy;
+	void *handle;
+};
+
+struct nvfw_get_proc_address_handle {
+	const char *symbolname;
+	int length;
+	void *address;
+	void *handle;
+};
+
+#define NVFW_IOC_MAGIC 'N'
+#define NVFW_IOC_LOAD_LIBRARY     _IOWR(NVFW_IOC_MAGIC, 0x50, struct nvfw_load_handle)
+#define NVFW_IOC_LOAD_LIBRARY_EX  _IOWR(NVFW_IOC_MAGIC, 0x51, struct nvfw_load_handle)
+#define NVFW_IOC_FREE_LIBRARY     _IOW (NVFW_IOC_MAGIC, 0x52, struct nvfw_load_handle)
+#define NVFW_IOC_GET_PROC_ADDRESS _IOWR(NVFW_IOC_MAGIC, 0x53, struct nvfw_load_handle)
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvidlcmd.h b/arch/arm/mach-tegra/nv/include/nvidlcmd.h
new file mode 100644
index 000000000000..510920d4b207
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvidlcmd.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVIDLCMD_H
+#define INCLUDED_NVIDLCMD_H
+
+#include "nvos.h"
+#include "nvreftrack.h"
+
+// name of the master FIFO socket on systems which use the master FIFO
+#define NVRM_DAEMON_SOCKNAME "/dev/nvrm_daemon"
+
+#define NV_DAEMON_MODULES(F) \
+    F(NvRmGraphics) \
+    F(NvMM) \
+    F(NvDDKAudio) \
+    F(NvDispMgr)
+
+#define NV_KERNEL_MODULES(F) \
+    F(NvRm) \
+    F(NvECPackage) \
+    F(NvStorManager) \
+    F(NvVib)
+
+// These codes are sent to the daemon to initiate commands from each module.
+typedef enum NvRmDaemonCodeEnum
+{
+    NvRmDaemonCode_FifoCreate   =   0x281e0001,
+    NvRmDaemonCode_FifoDelete,
+
+#define F(X) NvRmDaemonCode_##X,
+    NV_DAEMON_MODULES(F)
+#undef F
+    NvRmDaemonCode_Garbage      =   0xdeadbeef,
+
+    NvRmDaemonCode_Force32      =   0x7FFFFFFF
+} NvRmDaemonCode;
+
+/* Defines a pair of objects for transferring data to and from the daemon.
+ * FifoIn is used to read data from the daemon; FifoOut is used to write data
+ * to the daemon
+ */
+typedef struct NvIdlFifoPairRec
+{
+    void *FifoIn;
+    void *FifoOut;
+} NvIdlFifoPair;
+
+
+/* These functions are called by the IDL-generated code:
+ *
+ * *_NvIdlGetIoctlCode() - get code to use to identify module
+ * *_NvIdlGetFifos()     - get a fifo pair for communication
+ * *_NvIdlReleaseFifos() - get a fifo pair for communication
+ * *_NvIdlGetIoctlFile() - get the file to use for ioctl
+ */
+
+#define NV_IDL_DECLS_STUB(pfx) \
+        NvU32          pfx##_NvIdlGetIoctlCode(void); \
+        NvOsFileHandle pfx##_NvIdlGetIoctlFile(void);
+    
+#define NV_IDL_DECLS_DISPATCH_KERNEL(pfx) \
+        NvError pfx##_Dispatch( \
+                    void *InBuffer, \
+                    NvU32 InSize, \
+                    void *OutBuffer, \
+                    NvU32 OutSize, \
+                    NvDispatchCtx* Ctx);
+
+#if NVOS_IS_LINUX
+#define NV_IDL_DECLS_DISPATCH_DAEMON(pfx) \
+        NvError pfx##_Dispatch( \
+            void* hFifoIn, \
+            void* hFifoOut, \
+            NvDispatchCtx* Ctx);
+#else
+#define NV_IDL_DECLS_DISPATCH_DAEMON(p) \
+        NV_IDL_DECLS_DISPATCH_KERNEL(p)
+#endif
+
+#define F(X) NV_IDL_DECLS_STUB(X)
+NV_DAEMON_MODULES(F)
+NV_KERNEL_MODULES(F)
+#undef F
+
+#define F(X) NV_IDL_DECLS_DISPATCH_DAEMON(X)
+NV_DAEMON_MODULES(F)
+#undef F
+
+#define F(X) NV_IDL_DECLS_DISPATCH_KERNEL(X)
+NV_KERNEL_MODULES(F)
+#undef F
+
+/* utility functions called by stubs & dispatchers for transferring data
+ * over FIFO objects. semantics are identical to NvOsFread / NvOsFwrite */
+NvError NvIdlHelperFifoRead(void *fifo, void *ptr, size_t len, size_t *read);
+NvError NvIdlHelperFifoWrite(void *fifo, const void *ptr, size_t len);
+
+/* utility functions called by stub helpers to allocate and free FIFOs */
+NvError NvIdlHelperGetFifoPair(NvIdlFifoPair **pFifo);
+void    NvIdlHelperReleaseFifoPair(NvIdlFifoPair *pFifo);
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvio.h b/arch/arm/mach-tegra/nv/include/nvio.h
new file mode 100644
index 000000000000..f5d5e51edcac
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvio.h
@@ -0,0 +1,13 @@
+#define tegra_apertures(_aperture)                      \
+        _aperture(IRAM,         0x40000000, SZ_1M)      \
+        _aperture(HOST1X,       0x50000000, SZ_1M)      \
+        _aperture(PPSB,         0x60000000, SZ_1M)      \
+        _aperture(APB,          0x70000000, SZ_1M)      \
+        _aperture(USB,          0xC5000000, SZ_1M)      \
+        _aperture(SDIO,         0xC8000000, SZ_1M)
+
+/* remaps USB to 0xFE9xxxxx, SDIO to 0xFECxxxxx, and everything else to
+ * 0xFEnxxxxx, where n is the most significant nybble */
+#define tegra_munge_pa(_pa)                                             \
+        (((((_pa)&0x70000000UL)>>8) + (((_pa)&0x0F000000UL)>>4)) |      \
+         ((_pa)&0xFFFFFUL) | 0xFE000000UL )
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_accelerometer.h b/arch/arm/mach-tegra/nv/include/nvodm_accelerometer.h
new file mode 100644
index 000000000000..54efabc240e5
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_accelerometer.h
@@ -0,0 +1,414 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Accelerometer Interface</b>
+ *
+ * @b Description: Defines the ODM interface for accelerometer devices.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_ACCELEROMETER_H
+#define INCLUDED_NVODM_ACCELEROMETER_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+#include "nvassert.h"
+
+/**
+ * @defgroup nvodm_accelerometer Accelerometer Adapation Interface
+ *
+ * This is the accelerometer ODM adaptation interface.  Currently, only 3-axis
+ * accelerometers are supported by this interface.
+ *
+ * This section shows the calls made by the NVIDIA&reg; Driver Development Kit
+ * (DDK) accelerometer. 
+ *
+ * @par Physical Accelerometer
+ * 
+ * All applications share the same physical accelerometer.
+ *
+ * @par Sample Rate
+ *
+ * Every application has its own sample rate in Hz (samples/second).
+ * You can set the sample rate with the NvOdmAccelSetSampleRate() function,
+ * or you can request the sample rate using the NvOdmAccelGetSampleRate()
+ * function.
+ *
+ *
+ * @par	Motion/Tap Interrupt Trigger
+ * 
+ * Applications can decide to accept motion/tap interrupts in NvOdmAccelOpen().
+ * The motion/tap interrupt threshold is set by the driver. The application
+ * can get a message queue name by \c NvOdmAccelOpen, and then use the name to
+ * create a Windows message queue. Then the application can read interrupt
+ * information from the queue.
+ *
+ * See also <a class="el" href="group__nvodm__example__accel.html">Examples: 
+ * Accelerometer</a>
+ * 
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+/**
+ *  @brief Opaque handle to the vibrate device.
+ */
+typedef struct NvOdmAccelRec *NvOdmAcrDeviceHandle;
+
+/**
+ * Defines interrupt events that accelerometers may generate during
+ * operation.
+ */
+
+typedef enum
+{
+    /// Indicates that no interrupt has been generated (this value is returned
+    /// when interrupt time-outs occur).
+    NvOdmAccelInt_None = 0,
+
+    /// Indicates that an interrupt has been generated due to motion across
+    /// any axis crossing the specified threshold level.
+    NvOdmAccelInt_MotionThreshold,
+
+    /// Indicates that an interrupt has been generated due to a swinging
+    /// (forward and back motion) ocurring within the specified time threshold.
+    NvOdmAccelInt_TapThreshold,
+
+    /// Indicates that an interrupt has been generated due to detection of
+    /// linear freefall motion.
+    NvOdmAccelInt_Freefall,
+
+    NvOdmAccelInt_Num,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmAccelInt_Force32 = 0x7fffffffUL,
+} NvOdmAccelIntType;
+
+/**
+ * Defines axis types for accelerometer. Interrupts are trigger by the axis.
+ * An interrupt is triggered for enabled interrupts whenever a forced value
+ * on an axis is greater than the threshold.
+ */
+typedef enum {
+    NvOdmAccelAxis_None = 0x0,
+    NvOdmAccelAxis_X = 0x1,
+    NvOdmAccelAxis_Y = 0x2,
+    NvOdmAccelAxis_Z = 0x4,
+    NvOdmAccelAxis_All = 0x7,
+    NvOdmAccelAxis_Force32 = 0x7fffffffUL,
+} NvOdmAccelAxisType;
+
+/**
+ * Defines the accelerometer power state.
+ */
+typedef enum {
+   /// Specifies the accelerometer is working normally -- sample rate is high.
+   NvOdmAccelPower_Fullrun = 0,
+   /// Specifies the accelerometer is working normally -- sample rate is lower
+   /// than \c NvOdmAccelPower_Fullrun.
+   NvOdmAccelPower_Low,
+   /// Specifies the accelerometer is not working, but the power supply is there.
+   NvOdmAccelPower_Standby,
+   /// Specifies the accelerometer is not working, and there is no power supply
+   /// to the device.
+   NvOdmAccelPower_Off,
+   NvOdmAccelPower_None,
+   /// Ignore -- Forces compilers to make 32-bit enums.
+   NvOdmAccelPower_Force32 =0x7fffffffUL,
+} NvOdmAccelPowerType;
+
+/**
+ * Holds device-specific accelerometer capabilities.
+ */
+typedef struct NvOdmAccelCapsRec
+{
+    ///  Holds the maximum force in g-force (\em g) registered by this
+    ///  accelerometer.
+    ///  The value is in increments of 1000. For example, when the maximum
+    ///  force is 2 \em g, the value should return 2000.
+    NvU32 MaxForceInGs;
+
+    ///  Holds the size of the register for the g-force values in bits.
+    ///  This is to specify the resolution of the force value range.
+    NvU32 ForceResolution;
+
+    ///  Holds the number of motion thresholds that clients may use to generate
+    ///  interrupts. 0 indicates that no threshold motion interrupts
+    ///  are supported.
+    NvU32 NumMotionThresholds;
+
+    ///  Holds the maximum amount of time in microseconds (Usecs) that may
+    ///  be specified as the threshold for a tap-style interrupt. 0
+    ///  indicates that tap interrupts are not supported by the accelerometer.
+    NvU32 MaxTapTimeDeltaInUs;
+
+    ///  Holds TRUE if the accelerometer can generate an interrupt when
+    ///  linear free-fall motion is detected.
+    NvBool SupportsFreefallInt;
+
+    ///  Holds the maximum sample rate the accelerometer supports.
+    NvU32 MaxSampleRate;
+
+    ///  Holds the minimum sample rate the accelerometer supports.
+    NvU32 MinSampleRate;
+} NvOdmAccelerometerCaps;
+
+///  Opaque handle to an accelerometer object.
+typedef struct NvOdmAccelRec *NvOdmAccelHandle;
+
+
+/**
+ * Initializes the accelerometer and allocates resources used by the ODM
+ * adaptation driver.
+ *
+ * @return A handle to the accelerometer if initialization is successful, or
+ *         NULL if unsuccessful or no accelerometer exists.
+ */
+NvBool
+NvOdmAccelOpen(NvOdmAccelHandle* hDevice);
+
+/**
+ * Disables the accelerometer and frees any resources used by the driver.
+ *
+ * @param hDevice The accelerometer handle.
+ */
+void
+NvOdmAccelClose(NvOdmAccelHandle hDevice);
+
+/**
+ * Sets the threshold value in g-force (\em g) for interrupt types that are
+ * triggered at g-force thresholds, such as NvOdmAccelInt_MotionThreshold().
+ * The threshold is applied to all 3 axes on the accelerometer. This does not
+ * enable or disable the specified interrupt.
+ *
+ * @param hDevice The accelerometer handle.
+ * @param IntType The type of interrupt being configured (::NvOdmAccelIntType).
+ * @param IntNum For accelerometers that support multiple interrupt thresholds
+ *               (::NvOdmAccelerometerCaps), specifies which threshold to
+ *               configure. If the accelerometer supports a single threshold for
+ *               the specified interrupt type, this parameter should be 0.
+ * @param Threshold The desired threshold value, in g-forces. If this value is
+ *                  outside of the accelerometer's supported range, it will be
+ *                  clamped to the maximum supported value. If the accelerometer
+ *                  does not have enough precision to support the exact value
+ *                  specified, the threshold will be rounded to the nearest
+ *                  supported value. The value is by increments of 1000.
+ *                  For example, when the maximum force is 2 \em g, the value
+ *                  should return 2000.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmAccelSetIntForceThreshold(NvOdmAccelHandle  hDevice,
+                               NvOdmAccelIntType IntType,
+                               NvU32             IntNum,
+                               NvU32             Threshold);
+
+/**
+ * Sets the threshold value in microseconds (Usecs) for interrupt types that
+ * are triggered at time thresholds. This does not enable or disable the
+ * specified interrupt.
+ *
+ * Sets the threshold value in g-force (\em g) for interrupt types that are
+ * triggered at g-force thresholds, such as NvOdmAccelInt_MotionThreshold().
+ * The threshold is applied to all 3 axes on the accelerometer. This does not
+ * enable or disable the specified interrupt.
+ *
+ * @param hDevice The accelerometer handle.
+ * @param IntType The type of interrupt being configured (::NvOdmAccelIntType).
+ * @param IntNum For accelerometers that support multiple interrupt thresholds
+ *               (::NvOdmAccelerometerCaps), specifies which threshold to
+ *               configure. If the accelerometer supports a single threshold for
+ *               the specified interrupt type, this parameter should be 0.
+ * @param Threshold The desired threshold value in microseconds. If this value
+ *                  is outside of the accelerometer's supported range, it will be
+ *                  clamped to the maximum supported value.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmAccelSetIntTimeThreshold(NvOdmAccelHandle  hDevice,
+                              NvOdmAccelIntType IntType,
+                              NvU32             IntNum,
+                              NvU32             Threshold);
+
+
+/**
+ * Enables/disables the specified interrupt source. If the interrupt
+ * thresholds were not set prior to enabling the interrupt, the ODM-defined
+ * default values are used. If enabling a previously-enabled interrupt,
+ * or disabling a previously-disabled interrupt, this function returns
+ * silently.
+ *
+ * @param hDevice The accelerometer handle.
+ * @param IntType The type of interrupt being configured (::NvOdmAccelIntType).
+ * @param IntAxis The axis interrupt type (::NvOdmAccelAxisType).
+ * @param IntNum For accelerometers that support multiple interrupt thresholds
+ *               (::NvOdmAccelerometerCaps), specifies which threshold to
+ *               configure. If the accelerometer supports a single threshold for
+ *               the specified interrupt type, this parameter should be 0.
+ * @param Toggle NV_TRUE specifies to enable the interrupt source, NV_FALSE to
+ *               disable.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmAccelSetIntEnable(NvOdmAccelHandle  hDevice,
+                           NvOdmAccelIntType  IntType,
+                           NvOdmAccelAxisType IntAxis,
+                           NvU32              IntNum,
+                           NvBool             Toggle);
+
+/**
+ * Waits for any enabled interrupt, and returns the type of interrupt to the
+ * caller. If multiple interrupts occur simultaneously, returns each
+ * separately.
+ *
+ * @param hDevice The accelerometer handle.
+ * @param IntType The type of the interrupt that has been generated
+ *         (::NvOdmAccelIntType).  If no interrupt occurs before the timeout
+ *         interval expires, or no interrupts are enabled, returns
+ *         ::NvOdmAccelInt_None.
+ * @param IntMotionAxis The axis that triggered the motion interrupt (::NvOdmAccelAxisType).
+ *         If no interrupt occurs before the timeout interval expires, or no
+ *         interrupts are enabled, returns ::NvOdmAccelAxis_None.
+ * @param IntTapAxis The axis that triggered the tap interrupt (::NvOdmAccelAxisType).
+ *         If no interrupt occurs before the timeout interval expires, or no
+ *         interrupts are enabled, returns ::NvOdmAccelAxis_None.
+ */
+
+void
+NvOdmAccelWaitInt(NvOdmAccelHandle    hDevice,
+                  NvOdmAccelIntType  *IntType,
+                  NvOdmAccelAxisType *IntMotionAxis,
+                  NvOdmAccelAxisType *IntTapAxis);
+
+/**
+ * Signals the waiting semaphore.
+ *
+ * @param hDevice The accelerometer handle.
+ */
+void
+NvOdmAccelSignal(NvOdmAccelHandle hDevice);
+
+
+/**
+ * Returns the current acceleration data in g-forces (\em g) as measured
+ * by the accelerometer.
+ *
+ * To allow higher-level software to be written independently of the
+ * precision and physical orientation of the accelerometer, the values
+ * returned by this function must be normalized by the adaptation to the
+ * following coordinate system:
+ *
+ * - Upright -- when the device is held upright with the primary display
+ * facing the user, the returned acceleration should be (0, 1, 0).
+ * - 90% rotation -- when the device is rotated 90 degrees clockwise, so that
+ * the left edge of the primary display is pointing up, the returned acceleration
+ * should be (1, 0, 0).
+ * - Flat face up -- when the device is laid flat, like on a desk, with
+ * the primary display face-up, the returned acceleration should be
+ * (0, 0, 1).
+ *
+ * @param [in] hDevice The accelerometer handle.
+ * @param [out] AccelX Measured acceleration along the X axis. The value is by
+ *         increments of 1000. For example, 1 \em g is equal to 1000.
+ * @param [out] AccelY Measured acceleration along the Y axis. The value is by
+ *         increments of 1000. For example, 1 \em g is equal to 1000.
+ * @param [out] AccelZ Measured acceleration along the Z axis. The value is by
+ *         increments of 1000. For example, 1 \em g is equal to 1000.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmAccelGetAcceleration(NvOdmAccelHandle hDevice,
+                          NvS32           *AccelX,
+                          NvS32           *AccelY,
+                          NvS32           *AccelZ);
+
+/**
+ * Gets the accelerometer's character.
+ *
+ * @param hDevice The accelerometer handle.
+ * @return The accelerometer's character.
+ */
+NvOdmAccelerometerCaps
+NvOdmAccelGetCaps(NvOdmAccelHandle hDevice);
+
+
+/**
+ * Sets the accelerometer's power state.
+ *
+ * @param hDevice The accelerometer handle.
+ * @param PowerState  The accelerometer power state to set.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmAccelSetPowerState(NvOdmAccelHandle hDevice, NvOdmAccelPowerType PowerState);
+
+
+/**
+ * Sets the accelerometer's current sample rate state.
+ *
+ * @param hDevice The accelerometer handle.
+ * @param SampleRate  The ::NvOdmAccelPowerType accelerometer
+ *         sample rate in Hz (samples/second); if there
+ *         is none suitable, the nearest sample rate is set.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmAccelSetSampleRate(NvOdmAccelHandle hDevice, NvU32 SampleRate);
+
+/**
+ * Gets the accelerometer's current sample rate state.
+ *
+ * @param hDevice The accelerometer handle.
+ * @param pSampleRate  The ::NvOdmAccelPowerType accelerometer
+ *          sample rate in Hz (samples/second); if there
+ *          is none suitable, the nearest sample rate is set.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmAccelGetSampleRate(NvOdmAccelHandle hDevice, NvU32* pSampleRate);
+
+
+#if defined(__cplusplus)
+}
+#endif
+/** @} */
+#endif // INCLUDED_NVODM_ACCELEROMETER_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_battery.h b/arch/arm/mach-tegra/nv/include/nvodm_battery.h
new file mode 100644
index 000000000000..4dba0edc1c48
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_battery.h
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Battery Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for
+ *    Embedded Controller (EC) based battery interface.
+ *    Note that this doesn't use PMU interface.
+ *    EC Interface is used to get battery and power supply
+ *    information and configure for events.
+ *    Battery charging is taken care by EC firmware itself.
+ */
+
+#ifndef INCLUDED_NVODM_BATTERY_H
+#define INCLUDED_NVODM_BATTERY_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+
+/**
+ * @defgroup nvodm_battery_group Battery Adaptation Interface 
+ *
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+/**
+ * Defines an opaque handle that exists for each battery device in the
+ * system, each of which is defined by the customer implementation.
+ */
+typedef struct NvOdmBatteryDeviceRec *NvOdmBatteryDeviceHandle;
+
+/**
+ * Defines the AC status.
+ */
+typedef enum
+{
+    /// Specifies AC is offline.
+    NvOdmBatteryAcLine_Offline,
+
+    /// Specifies AC is online.
+    NvOdmBatteryAcLine_Online,
+
+    /// Specifies backup power.
+    NvOdmBatteryAcLine_BackupPower,
+
+    NvOdmBatteryAcLine_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmBatteryAcLine_Force32 = 0x7FFFFFFF
+}NvOdmBatteryAcLineStatus;
+
+/**
+ * Defines the battery events.
+ */
+typedef enum
+{
+    /// Indicates battery present state.
+    NvOdmBatteryEventType_Present = 0x01,
+
+    /// Indicates idle state.
+    NvOdmBatteryEventType_Idle = 0x02,
+
+    /// Indicates charging state.
+    NvOdmBatteryEventType_Charging = 0x04,
+
+    /// Indicates disharging state.
+    NvOdmBatteryEventType_Disharging = 0x08,
+
+    /// Indicates remaining capacity alarm set.
+    NvOdmBatteryEventType_RemainingCapacityAlarm = 0x10,
+
+    NvOdmBatteryEventType_Num = 0x20,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmBatteryEventType_Force32 = 0x7FFFFFFF
+}NvOdmBatteryEventType;
+
+/** @name Battery Status Defines */
+/*@{*/
+
+#define NVODM_BATTERY_STATUS_HIGH               0x01
+#define NVODM_BATTERY_STATUS_LOW                0x02
+#define NVODM_BATTERY_STATUS_CRITICAL           0x04
+#define NVODM_BATTERY_STATUS_CHARGING           0x08
+#define NVODM_BATTERY_STATUS_DISCHARGING        0x10
+#define NVODM_BATTERY_STATUS_IDLE               0x20
+#define NVODM_BATTERY_STATUS_VERY_CRITICAL      0x40
+#define NVODM_BATTERY_STATUS_NO_BATTERY         0x80
+#define NVODM_BATTERY_STATUS_UNKNOWN            0xFF
+
+/*@}*/
+/** @name Battery Data Defines */
+/*@{*/
+#define NVODM_BATTERY_DATA_UNKNOWN              0x7FFFFFFF
+
+/*@}*/
+/**
+ * Defines battery instances.
+ */
+typedef enum
+{
+    /// Specifies main battery.
+    NvOdmBatteryInst_Main,
+
+    /// Specifies backup battery.
+    NvOdmBatteryInst_Backup,
+
+    NvOdmBatteryInst_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmBatteryInst_Force32 = 0x7FFFFFFF
+    
+}NvOdmBatteryInstance;
+
+/**
+ * Defines battery data.
+ */
+typedef struct NvOdmBatteryDataRec
+{
+    /// Specifies battery life percent.
+    NvU32 BatteryLifePercent;
+
+    /// Specifies battery lifetime.
+    NvU32 BatteryLifeTime;
+
+    /// Specifies voltage.
+    NvU32 BatteryVoltage;
+
+    /// Specifies battery current.
+    NvS32 BatteryCurrent;
+
+    /// Specifies battery average current.
+    NvS32 BatteryAverageCurrent;
+
+    /// Specifies battery interval.
+    NvU32 BatteryAverageInterval;
+
+    /// Specifies the mAH consumed.
+    NvU32 BatteryMahConsumed;
+
+    /// Specifies battery temperature.
+    NvU32 BatteryTemperature;
+
+    /// Specifies battery remaining capacity.
+    NvU32 BatteryRemainingCapacity;
+
+    /// Specifies battery last charge full capacity.
+    NvU32 BatteryLastChargeFullCapacity;
+
+    /// Specifies battery critical capacity.
+    NvU32 BatteryCriticalCapacity;
+
+}NvOdmBatteryData;
+
+/**
+ * Defines battery chemistry.
+ */
+typedef enum
+{
+    /// Specifies an alkaline battery.
+    NvOdmBatteryChemistry_Alkaline,
+
+    /// Specifies a nickel-cadmium (NiCd) battery.
+    NvOdmBatteryChemistry_NICD,
+
+    /// Specifies a nickel-metal hydride (NiMH) battery.
+    NvOdmBatteryChemistry_NIMH,
+
+    /// Specifies a lithium-ion (Li-ion) battery.
+    NvOdmBatteryChemistry_LION,
+
+    /// Specifies a lithium-ion polymer (Li-poly) battery.
+    NvOdmBatteryChemistry_LIPOLY,
+
+    /// Specifies a zinc-air battery.
+    NvOdmBatteryChemistry_XINCAIR,
+
+    NvOdmBatteryChemistry_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmBatteryChemistry_Force32 = 0x7FFFFFFF
+}NvOdmBatteryChemistry;
+
+/**
+ * Opens the handle for battery ODM.
+ *
+ * @param hDevice A pointer to the handle to the battery ODM.
+ * @param hOdmSemaphore Battery events signal this registered semaphore.
+ *                      Can Pass NULL if events are not needed by client.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmBatteryDeviceOpen(NvOdmBatteryDeviceHandle *hDevice,
+                              NvOdmOsSemaphoreHandle *hOdmSemaphore);
+
+/**
+ * Closes the handle for battery ODM.
+ *
+ * @param hDevice A handle to the battery ODM.
+ */
+void NvOdmBatteryDeviceClose(NvOdmBatteryDeviceHandle hDevice);
+
+/**
+ * Gets the AC line status.
+ *
+ * @param hDevice A handle to the EC.
+ * @param pStatus A pointer to the AC line
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmBatteryGetAcLineStatus(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryAcLineStatus *pStatus);
+
+
+/**
+ * Gets the battery status.
+ *
+ * @param hDevice A handle to the EC.
+ * @param batteryInst The battery type.
+ * @param pStatus A pointer to the battery
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmBatteryGetBatteryStatus(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance batteryInst,
+       NvU8 *pStatus);
+
+/**
+ * Gets the battery data.
+ *
+ * @param hDevice A handle to the EC.
+ * @param batteryInst The battery type.
+ * @param pData A pointer to the battery
+ *  data returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmBatteryGetBatteryData(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance batteryInst,
+       NvOdmBatteryData *pData);
+
+
+/**
+ * Gets the battery full lifetime.
+ *
+ * @param hDevice A handle to the EC.
+ * @param batteryInst The battery type.
+ * @param pLifeTime A pointer to the battery
+ *  full lifetime returned by the ODM.
+ * 
+ */
+void NvOdmBatteryGetBatteryFullLifeTime(
+     NvOdmBatteryDeviceHandle hDevice,
+     NvOdmBatteryInstance batteryInst,
+     NvU32 *pLifeTime);
+
+/**
+ * Gets the battery chemistry.
+ *
+ * @param hDevice A handle to the EC.
+ * @param batteryInst The battery type.
+ * @param pChemistry A pointer to the battery
+ *  chemistry returned by the ODM.
+ * 
+ */
+void NvOdmBatteryGetBatteryChemistry(
+     NvOdmBatteryDeviceHandle hDevice,
+     NvOdmBatteryInstance batteryInst,
+     NvOdmBatteryChemistry *pChemistry);
+
+/**
+ * Gets the battery event.
+ *
+ * @param hDevice A handle to the EC.
+ * @param pBatteryEvent A pointer to the battery events.
+ * 
+ */
+void NvOdmBatteryGetEvent(
+     NvOdmBatteryDeviceHandle hDevice,
+     NvU8   *pBatteryEvent);
+
+
+/**
+ * Gets the battery manufacturer.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pBatteryManufacturer [OUT] A pointer to the battery manufacturer.
+ */
+NvBool NvOdmBatteryGetManufacturer(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU8 *pBatteryManufacturer);
+
+/**
+ * Gets the battery model.
+ *
+ * @param hDevice [IN] A handle to the EC.
+ * @param BatteryInst [IN] The battery type.
+ * @param pBatteryModel [OUT] A pointer to the battery model.
+ */
+NvBool NvOdmBatteryGetModel(
+       NvOdmBatteryDeviceHandle hDevice,
+       NvOdmBatteryInstance BatteryInst,
+       NvU8 *pBatteryModel);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_BATTERY_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_gpio_ext.h b/arch/arm/mach-tegra/nv/include/nvodm_gpio_ext.h
new file mode 100644
index 000000000000..6004963b8b6d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_gpio_ext.h
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         External GPIO Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for GPIO
+ *    pins that are sourced from off-chip peripherals.
+ */
+
+#ifndef INCLUDED_NVODM_GPIO_EXT_H
+#define INCLUDED_NVODM_GPIO_EXT_H
+
+#include "nvcommon.h"
+#include "nvodm_services.h"
+
+/**
+ * @defgroup nvodm_gpio_ext External GPIO Interface
+ *
+ * Your clients do not use the API functions defined here. Instead, they
+ * make use of the ::NvOdmExternalGpioPort enumeration, which defines 
+ * logical GPIO ports that may be included in the Peripheral DB entries.
+ * The ODM developer is responsible to write the external GPIO handler in
+ * your ODM Adaptation implementation.
+ * 
+ * This feature makes it possible to treat GPIOs sourced from an external
+ * peripheral as if they came from the Tegra application processor itself
+ * (thus, allowing for the use of the NvOdmGpio* functions). This makes
+ * it possible for some adaptation client implementations to remain
+ * unchanged if the pin gets moved from an external to an internal device.
+ *
+ * For instance, the PMU sources a GPIO pin for the backlight, but the
+ * display adaptation just requests the GPIO for this function from the
+ * Peripheral DB. The PMU adaptation implements the actual handling of
+ * the external GPIO. As an alternative, the backlight could be switched
+ * on or off via a GPIO pin from the chip. In that case, the peripheral
+ * DB will get updated, but the display adaptation can remain unchanged,
+ * which is the advantage of this feature.
+ *
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+/** External GPIO device context. */
+typedef struct GpioExtDeviceRec* NvOdmGpioExtHandle;
+
+/**
+ * @brief Defines the external GPIO ports.  These definitions 
+ *        are generic placeholders, as they map to off-chip
+ *        GPIOs as defined by the ODM. The ODM is
+ *        responsible for documenting and using these
+ *        pre-defined ports consistently between their
+ *        adaptation client and their implementation of the
+ *        Peripheral Discovery DB entries.
+ */
+typedef enum {
+    NVODM_GPIO_EXT_PORT_0 = 0xD0,
+    NVODM_GPIO_EXT_PORT_1,
+    NVODM_GPIO_EXT_PORT_2,
+    NVODM_GPIO_EXT_PORT_3,
+    NVODM_GPIO_EXT_PORT_4,
+    NVODM_GPIO_EXT_PORT_5,
+    NVODM_GPIO_EXT_PORT_6,
+    NVODM_GPIO_EXT_PORT_7,
+    NVODM_GPIO_EXT_PORT_8,
+    NVODM_GPIO_EXT_PORT_9,
+    NVODM_GPIO_EXT_PORT_A,
+    NVODM_GPIO_EXT_PORT_B,
+    NVODM_GPIO_EXT_PORT_C,
+    NVODM_GPIO_EXT_PORT_D,
+    NVODM_GPIO_EXT_PORT_E,
+    NVODM_GPIO_EXT_PORT_F,
+} NvOdmExternalGpioPort;
+
+/**
+ * This is an ODM-specific adaptation that writes the output 
+ * state of external (off-chip) GPIO pins for the specified 
+ * port. This function is not called directly by the client 
+ * that uses the external GPIOs, but rather called indirectly 
+ * via NvOdmGpioSetState().
+ *
+ * @sa NvOdmGpioOpen(), NvOdmExternalGpioReadPins()
+ *
+ * @param Port The specified external GPIO port.
+ * @param Pin The specified GPIO pin.
+ * @param PinValue The pin state to set. 0 means drive low, 1 means drive high.
+ */
+void
+NvOdmExternalGpioWritePins(
+    NvU32 Port,
+    NvU32 Pin,
+    NvU32 PinValue);
+
+/**
+ * This is an ODM-specific adaptation that reads the output 
+ * state of external (off-chip) GPIO pins for the specified 
+ * port. This function is not called directly by the client 
+ * that uses the external GPIOs, but rather called indirectly 
+ * via NvOdmGpioGetState(). 
+ *
+ * @sa NvOdmGpioOpen(), NvOdmExternalGpioWritePins()
+ *  
+ * @param Port The specified external GPIO port.
+ * @param Pin The specified GPIO pin. 
+ *  
+ * @return The current state of the specified port+pin.
+ */
+NvU32
+NvOdmExternalGpioReadPins(
+    NvU32 Port,
+    NvU32 Pin);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+#endif  // INCLUDED_NVODM_GPIO_EXT_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_kbc.h b/arch/arm/mach-tegra/nv/include/nvodm_kbc.h
new file mode 100644
index 000000000000..db8da306a3ed
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_kbc.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         KBC Adaptation Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for KBC keypad.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_KBC_H
+#define INCLUDED_NVODM_KBC_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+
+/**
+ * @defgroup nvodm_kbc Keyboard Controller Adaptation Interface
+ * This is the keyboard controller (KBC) ODM adaptation interface.
+ * See also the \link nvodm_query_kbc ODM Query KBC Interface\endlink.
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+/**
+ * This API takes the keys that have been pressed as input and filters out the
+ * the keys that may have been caused due to ghosting effect and key roll-over.
+ *
+ * @note The row and column numbers of the keys that have been left after the 
+ * filtering are stored in the \a pRows and \a pCols arrays. The extra keys must be 
+ * deleted from the array.
+ *
+ * @param pRows A pointer to the array of the row numbers of the keys that have 
+ * been detected. This array contains \a NumOfKeysPressed elements.
+ *
+ * @param pCols A pointer to the array of the column numbers of the keys that have 
+ * been detected. This array contains \a NumOfKeysPressed elements. 
+ * 
+ * @param NumOfKeysPressed The number of key presses that have been detected by 
+ * the driver.
+ *
+ * @return The number of keys pressed after the filter has been applied.
+ *
+*/
+NvU32
+NvOdmKbcFilterKeys(
+    NvU32 *pRows,
+    NvU32 *pCols,
+    NvU32 NumOfKeysPressed);
+
+
+#if defined(__cplusplus)
+    }
+#endif
+    
+/** @} */
+    
+#endif // INCLUDED_NVODM_KBC_H
+
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_kbc_keymapping.h b/arch/arm/mach-tegra/nv/include/nvodm_kbc_keymapping.h
new file mode 100644
index 000000000000..1cc64fd0b4d6
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_kbc_keymapping.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Keyboard Controller virtula key mapping</b>
+ *
+ * @b Description: Defines the ODM keyboard mapping to the platform 
+ *                  specific.
+ */
+
+#ifndef INCLUDED_NVODM_KBC_KEYMAPPING_H
+#define INCLUDED_NVODM_KBC_KEYMAPPING_H
+
+#include "nvcommon.h"
+
+struct NvOdmKeyVirtTableDetail
+{   
+    NvU32 StartScanCode;
+    NvU32 EndScanCode;
+    NvU32 *pVirtualKeyTable;
+};
+
+/**
+ * Get the virtual key table list with start and end scan code address.
+ * @param pVirtKeyTableList Pointer to the structure of the virtual key table 
+ * list.
+ * @retval Return the Number of entry on the list.
+ * 
+ */
+NvU32 
+NvOdmKbcKeyMappingGetVirtualKeyMappingList(
+    const struct NvOdmKeyVirtTableDetail ***pVirtKeyTableList);
+
+
+/** @} */
+#endif // INCLUDED_NVODM_KBC_KEYMAPPING_H
+
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_keyboard.h b/arch/arm/mach-tegra/nv/include/nvodm_keyboard.h
new file mode 100644
index 000000000000..7192141cbaa3
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_keyboard.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Keyboard Interface</b>
+ *
+ * @b Description: Defines the interface for the ODM keyboard.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_KEYBOARD_H
+#define INCLUDED_NVODM_KEYBOARD_H
+
+#include "nvodm_services.h"
+
+/**
+ * @defgroup nvodm_keyboard ODM Keyboard Interface
+ *
+ * This is the interface for the ODM keyboard. See also the
+ * \link nvodm_kbc Keyboard Controller Adaptation Interface\endlink and
+ * the \link nvodm_query_kbc ODM Query KBC Interface\endlink.
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+/**
+ * Initializes the ODM keyboard.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmKeyboardInit(void);
+
+/**
+ * Releases the ODM keyboard resources that were acquired during the 
+ * call to NvOdmKeyboardInit().
+ */
+void NvOdmKeyboardDeInit(void);
+
+/// Defines the scan code break flag.
+#define NV_ODM_SCAN_CODE_FLAG_BREAK (0x1)
+
+/// Defines the scan code make flag.
+#define NV_ODM_SCAN_CODE_FLAG_MAKE  (0x2)
+
+/** 
+ * Gets the key data from the ODM keyboard. This function must be called in
+ * an infinite loop to continue receiving the key scan codes.
+ *
+ * @param pKeyScanCode A pointer to the returned scan code of the key.
+ * @param pScanCodeFlags A pointer to the returned value specifying scan code
+ *  make/break flags (may be ORed for special code that combines make and
+ *  break sequences).
+ * @param Timeout (Optional) Specifies the timeout in msec. Can be set
+ *  to zero if no timeout needs to be used.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */ 
+NvBool NvOdmKeyboardGetKeyData(NvU32 *pKeyScanCode, NvU8 *pScanCodeFlags, NvU32 Timeout);
+
+/**
+ * Initializes the hold switch.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmHoldSwitchInit(void);
+
+/**
+ * Releases all the resources allocated during the initialization of the hold 
+ * switch.
+ */
+void NvOdmHoldSwitchDeInit(void);
+
+/**
+ * Toggles LEDs on the keyboard.
+ * @param LedId The LEDs to toggle.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmKeyboardToggleLights(NvU32 LedId);
+
+/**
+ * Keyboard power handler.
+ * @param PowerDown Flag to indicate power down or power up.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmKeyboardPowerHandler(NvBool PowerDown);
+
+/** @} */
+
+#endif // INCLUDED_NVODM_KEYBOARD_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_keylist_reserved.h b/arch/arm/mach-tegra/nv/include/nvodm_keylist_reserved.h
new file mode 100644
index 000000000000..036eb390bef6
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_keylist_reserved.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Reserved Key ID Definition</b>
+ *
+ * @b Description: Defines the reserved key IDs for the default keys provided
+ *                 by the ODM key/value list service.
+ */
+
+#ifndef INCLUDED_NVODM_KEYLIST_RESERVED_H
+#define INCLUDED_NVODM_KEYLIST_RESERVED_H
+
+/**
+ * @addtogroup nvodm_services
+ * @{
+ */
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * Defines the list of reserved key IDs for the ODM key/value list service.
+ * These keys may be read by calling NvOdmServicesGetKeyValue(), but they
+ * may not be modified.
+ */
+enum 
+{
+    /// Specifies the starting range of key IDs reserved for use by NVIDIA.
+    NvOdmKeyListId_ReservedAreaStart = 0x6fff0000UL,
+
+    /** Returns the value stored in the CustomerOption field of the BCT,
+     *  which was specified when the device was flashed. If no value was
+     *  specified when flashing, a default value of 0 will be returned. */
+    NvOdmKeyListId_ReservedBctCustomerOption = NvOdmKeyListId_ReservedAreaStart,
+
+    /// Specifes the last ID of the reserved key area.
+    NvOdmKeyListId_ReservedAreaEnd = 0x6ffffffeUL
+
+};
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_modules.h b/arch/arm/mach-tegra/nv/include/nvodm_modules.h
new file mode 100644
index 000000000000..cd107c8214ef
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_modules.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         I/O Module Definitions</b>
+ *
+ * @b Description: Defines all of the I/O module types (buses, I/Os, etc.)
+ *                 that may exist on an application processor.
+ */
+
+#ifndef INCLUDED_NVODM_MODULES_H
+#define INCLUDED_NVODM_MODULES_H
+
+/**
+ * @addtogroup nvodm_services
+ * @{
+ */
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * Defines I/O module types.
+ * Application processors provide a multitude of interfaces for connecting
+ * to external peripheral devices. These take the forms of individual pins
+ * (such as GPIOs), buses (such as USB), and power rails. Each interface
+ * may have zero, one, or multiple instantiations on the application processor;
+ * see the technical notes to determine the availability of interconnects for
+ * your platform.
+ */
+typedef enum
+{
+    NvOdmIoModule_Ata,
+    NvOdmIoModule_Crt,
+    NvOdmIoModule_Csi,
+    NvOdmIoModule_Dap,
+    NvOdmIoModule_Display,
+    NvOdmIoModule_Dsi,
+    NvOdmIoModule_Gpio,
+    NvOdmIoModule_Hdcp,
+    NvOdmIoModule_Hdmi,
+    NvOdmIoModule_Hsi,
+    NvOdmIoModule_Hsmmc,
+    NvOdmIoModule_I2s,
+    NvOdmIoModule_I2c,
+    NvOdmIoModule_I2c_Pmu,
+    NvOdmIoModule_Kbd,
+    NvOdmIoModule_Mio,
+    NvOdmIoModule_Nand,
+    NvOdmIoModule_Pwm,
+    NvOdmIoModule_Sdio,
+    NvOdmIoModule_Sflash,
+    NvOdmIoModule_Slink,
+    NvOdmIoModule_Spdif,
+    NvOdmIoModule_Spi,
+    NvOdmIoModule_Twc,
+    NvOdmIoModule_Tvo,
+    NvOdmIoModule_Uart,
+    NvOdmIoModule_Usb,
+    NvOdmIoModule_Vdd,
+    NvOdmIoModule_VideoInput,
+    NvOdmIoModule_Xio,
+    NvOdmIoModule_ExternalClock,
+    NvOdmIoModule_Ulpi,
+    NvOdmIoModule_OneWire,
+    NvOdmIoModule_SyncNor,
+    NvOdmIoModule_PciExpress,
+    NvOdmIoModule_Trace,
+    NvOdmIoModule_Tsense,
+    NvOdmIoModule_BacklightPwm,
+
+    NvOdmIoModule_Num,
+    NvOdmIoModule_Force32 = 0x7fffffffUL
+} NvOdmIoModule;
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif  // INCLUDED_NVODM_MODULES_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_mouse.h b/arch/arm/mach-tegra/nv/include/nvodm_mouse.h
new file mode 100644
index 000000000000..0e9c58c61543
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_mouse.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Touch Pad Sensor Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for touch pad sensor devices.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_MOUSE_H
+#define INCLUDED_NVODM_MOUSE_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+#include "nverror.h"
+
+/**
+ * @defgroup nvodm_mouse Mouse Adaptation Interface
+ *
+ * This is the mouse ODM adaptation interface.
+ *
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+
+/**
+ * Defines an opaque handle that exists for each mouse device in the
+ * system, each of which is defined by the customer implementation.
+ */
+typedef struct NvOdmMouseDeviceRec *NvOdmMouseDeviceHandle;
+
+
+/**
+ * Gets a handle to the mouse in the system.
+ *
+ * @param hDevice A pointer to the handle of the mouse.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmMouseDeviceOpen( NvOdmMouseDeviceHandle *hDevice );
+
+/**
+ * Hooks up the interrupt handle to the GPIO interrupt and enables the interrupt.
+ *
+ * @param hDevice The handle to the mouse.
+ * @param hInterruptSemaphore A handle to hook up the interrupt.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmMouseEnableInterrupt(NvOdmMouseDeviceHandle hDevice, NvOdmOsSemaphoreHandle hInterruptSemaphore);
+
+/**
+ * Un-registers the interrupt.
+ *
+ * @param hDevice The handle to the mouse.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmMouseDisableInterrupt(NvOdmMouseDeviceHandle hDevice);
+
+/**
+ * Returns the event response information.
+ *
+ * @param hDevice A handle to the mouse.
+ * @param NumPayLoad A pointer to the number of bytes in the returned payload.
+ * @param PayLoadBuf A pointer to the returned payload buffer.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmMouseGetEventInfo(NvOdmMouseDeviceHandle hDevice, NvU32 *NumPayLoad, NvU8 *PayLoadBuf);
+
+/**
+ *  Releases the mouse handle.
+ *
+ * @param hDevice The mouse handle to be released. If
+ *     NULL, this API has no effect.
+ */
+void NvOdmMouseDeviceClose(NvOdmMouseDeviceHandle hDevice);
+
+/**
+ *  Sends the commands to HW in a form of request packet.
+ *
+ * @param hDevice A handle to the mouse.
+ * @param cmd The command to send.
+ * @param ExpectedResponseSize The size expected in the response.
+ * @param NumPayLoad A pointer to the number of bytes in the payload.
+ * @param PayLoadBuf A pointer to the payload buffer.
+ */
+NvBool
+NvOdmMouseSendRequest(
+    NvOdmMouseDeviceHandle hDevice, 
+    NvU32 cmd,
+    NvU32 ExpectedResponseSize,
+    NvU32 *NumPayLoad,
+    NvU8 *PayLoadBuf);
+
+/**
+ * Enables the EC to stream data from the mouse.
+ *
+ * @param hDevice A handle to the mouse.
+ * @param NumBytesPerSample Number of payload bytes to be sent in each event
+ *        packet.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmMouseStartStreaming(
+    NvOdmMouseDeviceHandle hDevice,
+    NvU32 NumBytesPerSample);
+
+/**
+ *  Suspends power for mouse.
+ *
+ * @param hDevice A handle to the mouse.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmMousePowerSuspend(NvOdmMouseDeviceHandle hDevice);
+
+/**
+ *  Resumes power for mouse.
+ *
+ * @param hDevice A handle to the mouse.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+*/
+NvBool NvOdmMousePowerResume(NvOdmMouseDeviceHandle hDevice);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_MOUSE_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_pmu.h b/arch/arm/mach-tegra/nv/include/nvodm_pmu.h
new file mode 100644
index 000000000000..2b768edbe5b4
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_pmu.h
@@ -0,0 +1,468 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Power Management Unit Interface</b>
+ *
+ * @b Description: Defines the ODM interface for NVIDIA PMU devices.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_PMU_H
+#define INCLUDED_NVODM_PMU_H
+
+#include "nvcommon.h"
+#include "nvodm_query.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * @defgroup nvodm_pmu Power Management Unit Adaptation Interface 
+ *   
+ * This is the power management unit (PMU) ODM adaptation interface, which
+ * handles the abstraction of external power management devices.
+ * For NVIDIA&reg; Driver Development Kit (DDK) clients, PMU is a 
+ * set of voltages used to provide power to the SoC or to monitor low battery 
+ * conditions. The API allows DDK clients to determine whether the
+ * particular voltage is supported by the ODM platform, retrieve the
+ * capabilities of PMU, and get/set voltage levels at runtime. 
+ * On systems without power a management device, APIs should be dummy implemented.
+ *
+ * All voltage rails are referenced using ODM-assigned unsigned integers. ODMs
+ * may select any convention for assigning these values; however, the values
+ * accepted as input parameters by the PMU ODM adaptation interface must
+ * match the values stored in the address field of ::NvOdmIoModule_Vdd buses
+ * defined in the Peripheral Discovery ODM adaptation.
+ * 
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+
+/**
+ * Defines an opaque handle that exists for each PMU device in the
+ * system, each of which is defined by the customer implementation.
+ */
+typedef struct NvOdmPmuDeviceRec *NvOdmPmuDeviceHandle;
+
+/**
+ * Combines information for the particular PMU Vdd rail.
+ */
+typedef struct NvOdmPmuVddRailCapabilitiesRec
+{
+    /// Specifies ODM protection attribute; if \c NV_TRUE PMU hardware
+    ///  or ODM Kit would protect this voltage from being changed by NvDdk client.
+    NvBool OdmProtected;
+
+    /// Specifies the minimum voltage level in mV.
+    NvU32 MinMilliVolts;
+
+    /// Specifies the step voltage level in mV.
+    NvU32 StepMilliVolts;
+
+    /// Specifies the maximum voltage level in mV.
+    NvU32 MaxMilliVolts;
+
+    /// Specifies the request voltage level in mV.
+    NvU32 requestMilliVolts;
+} NvOdmPmuVddRailCapabilities;
+
+/// Special level to indicate voltage plane is turned off.
+#define ODM_VOLTAGE_OFF (0UL)
+
+/// Special level to enable voltage plane on/off control
+///  by the external signal (e.g., low power request from SoC).
+#define ODM_VOLTAGE_ENABLE_EXT_ONOFF (0xFFFFFFFFUL)
+
+/// Special level to disable voltage plane on/off control
+///  by the external signal (e.g., low power request from SoC).
+#define ODM_VOLTAGE_DISABLE_EXT_ONOFF (0xFFFFFFFEUL)
+
+/**
+ * Gets capabilities for the specified PMU voltage.
+ *
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pCapabilities A pointer to the targeted
+ *  capabilities returned by the ODM.
+ * 
+ */
+void
+NvOdmPmuGetCapabilities(
+    NvU32 vddId,
+    NvOdmPmuVddRailCapabilities* pCapabilities);
+
+
+/**
+ * Gets current voltage level for the specified PMU voltage.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pMilliVolts A pointer to the voltage level returned
+ *  by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuGetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32* pMilliVolts);
+
+
+/**
+ * Sets new voltage level for the specified PMU voltage.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param MilliVolts The new voltage level to be set in millivolts (mV).
+ * - Set to ::ODM_VOLTAGE_OFF to turn off the target voltage.
+ * - Set to ::ODM_VOLTAGE_ENABLE_EXT_ONOFF to enable external control of
+ *   target voltage.
+ * - Set to ::ODM_VOLTAGE_DISABLE_EXT_ONOFF to disable external control of
+ *   target voltage.
+ * @param pSettleMicroSeconds A pointer to the settling time in microseconds (uS),
+ *  which is the time for supply voltage to settle after this function 
+ *  returns; this may or may not include PMU control interface transaction time, 
+ *  depending on the ODM implementation. If NULL this parameter is ignored, and the
+ *  function must return only after the supply voltage has settled.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuSetVoltage(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32 MilliVolts,
+    NvU32* pSettleMicroSeconds);
+
+/**
+ * Gets a handle to the PMU in the system.
+ *
+ * @param hDevice A pointer to the handle of the PMU.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuDeviceOpen( NvOdmPmuDeviceHandle *hDevice );
+
+
+/**
+ *  Releases the PMU handle. 
+ *
+ * @param hDevice The PMU handle to be released. If 
+ *     NULL, this API has no effect.
+ */
+void NvOdmPmuDeviceClose(NvOdmPmuDeviceHandle hDevice);
+
+
+/**
+ * Defines AC status.
+ */
+typedef enum
+{
+    /// Specifies AC is offline.
+    NvOdmPmuAcLine_Offline,
+
+    /// Specifies AC is online.
+    NvOdmPmuAcLine_Online,
+
+    /// Specifies backup power.
+    NvOdmPmuAcLine_BackupPower,
+
+    NvOdmPmuAcLine_Num,
+    NvOdmPmuAcLine_Force32 = 0x7FFFFFFF
+}NvOdmPmuAcLineStatus;
+
+/** @name Battery Status Defines */
+/*@{*/
+
+#define NVODM_BATTERY_STATUS_HIGH               0x01
+#define NVODM_BATTERY_STATUS_LOW                0x02
+#define NVODM_BATTERY_STATUS_CRITICAL           0x04
+#define NVODM_BATTERY_STATUS_CHARGING           0x08
+#define NVODM_BATTERY_STATUS_NO_BATTERY         0x80
+#define NVODM_BATTERY_STATUS_UNKNOWN            0xFF
+
+/*@}*/
+/** @name Battery Data Defines */
+/*@{*/
+#define NVODM_BATTERY_DATA_UNKNOWN              0x7FFFFFFF
+
+/*@}*/
+/**
+ * Defines battery instances.
+ */
+typedef enum
+{
+    /// Specifies main battery.
+    NvOdmPmuBatteryInst_Main,
+
+    /// Specifies backup battery.
+    NvOdmPmuBatteryInst_Backup,
+
+    NvOdmPmuBatteryInst_Num,
+    NvOdmPmuBatteryInst_Force32 = 0x7FFFFFFF
+    
+}NvOdmPmuBatteryInstance;
+
+/**
+ * Defines battery data.
+ */
+typedef struct NvOdmPmuBatteryDataRec
+{
+    /// Specifies battery life percent.
+    NvU32 batteryLifePercent;
+
+    /// Specifies battery life time.
+    NvU32 batteryLifeTime;
+
+    /// Specifies voltage.
+    NvU32 batteryVoltage;
+
+    /// Specifies battery current.
+    NvS32 batteryCurrent;
+
+    /// Specifies battery average current.
+    NvS32 batteryAverageCurrent;
+
+    /// Specifies battery interval.
+    NvU32 batteryAverageInterval;
+
+    /// Specifies the mAH consumed.
+    NvU32 batteryMahConsumed;
+
+    /// Specifies battery temperature.
+    NvU32 batteryTemperature;
+    
+}NvOdmPmuBatteryData;
+
+/**
+ * Defines battery chemistry.
+ */
+typedef enum
+{
+    /// Specifies an alkaline battery.
+    NvOdmPmuBatteryChemistry_Alkaline,
+
+    /// Specifies a nickel-cadmium (NiCd) battery.
+    NvOdmPmuBatteryChemistry_NICD,
+
+    /// Specifies a nickel-metal hydride (NiMH) battery.
+    NvOdmPmuBatteryChemistry_NIMH,
+
+    /// Specifies a lithium-ion (Li-ion) battery.
+    NvOdmPmuBatteryChemistry_LION,
+
+    /// Specifies a lithium-ion polymer (Li-poly) battery.
+    NvOdmPmuBatteryChemistry_LIPOLY,
+
+    /// Specifies a zinc-air battery.
+    NvOdmPmuBatteryChemistry_XINCAIR,
+
+    NvOdmPmuBatteryChemistry_Num,
+    NvOdmPmuBatteryChemistry_Force32 = 0x7FFFFFFF
+}NvOdmPmuBatteryChemistry;
+
+/**
+ * Gets the AC line status.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param pStatus A pointer to the AC line
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool 
+NvOdmPmuGetAcLineStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuAcLineStatus *pStatus);
+
+
+/**
+ * Gets the battery status.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param batteryInst The battery type.
+ * @param pStatus A pointer to the battery
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool 
+NvOdmPmuGetBatteryStatus(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU8 *pStatus);
+
+/**
+ * Gets the battery data.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param batteryInst The battery type.
+ * @param pData A pointer to the battery
+ *  data returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuGetBatteryData(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryData *pData);
+
+
+/**
+ * Gets the battery full life time.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param batteryInst The battery type.
+ * @param pLifeTime A pointer to the battery
+ *  full life time returned by the ODM.
+ * 
+ */
+void
+NvOdmPmuGetBatteryFullLifeTime(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvU32 *pLifeTime);
+
+
+/**
+ * Gets the battery chemistry.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param batteryInst The battery type.
+ * @param pChemistry A pointer to the battery
+ *  chemistry returned by the ODM.
+ * 
+ */
+void
+NvOdmPmuGetBatteryChemistry(
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuBatteryInstance batteryInst,
+    NvOdmPmuBatteryChemistry *pChemistry);
+
+
+/** 
+* Defines the charging path. 
+*/ 
+typedef enum 
+{ 
+    /// Specifies external wall plug charger.
+    NvOdmPmuChargingPath_MainPlug, 
+ 
+    /// Specifies external USB bus charger.
+    NvOdmPmuChargingPath_UsbBus, 
+ 
+    NvOdmPmuChargingPath_Num, 
+    /// Ignore. Forces compilers to make 32-bit enums.
+    NvOdmPmuChargingPath_Force32 = 0x7FFFFFFF 
+ 
+}NvOdmPmuChargingPath; 
+
+/// Special level to indicate dumb charger current limit.
+#define NVODM_DUMB_CHARGER_LIMIT (0xFFFFFFFFUL)
+
+/// Special level to indicate USB Host mode current limit.
+#define NVODM_USB_HOST_MODE_LIMIT (0x80000000UL)
+
+/** 
+* Sets the charging current limit. 
+* 
+* @param hDevice A handle to the PMU. 
+* @param chargingPath The charging path. 
+* @param chargingCurrentLimitMa The charging current limit in mA. 
+* @param ChargerType The charger type.
+* @return NV_TRUE if successful, or NV_FALSE otherwise. 
+*/ 
+NvBool 
+NvOdmPmuSetChargingCurrent( 
+    NvOdmPmuDeviceHandle hDevice, 
+    NvOdmPmuChargingPath chargingPath, 
+    NvU32 chargingCurrentLimitMa,
+    NvOdmUsbChargerType ChargerType); 
+
+
+/**
+ * Handles the PMU interrupt.
+ *
+ * @param hDevice A handle to the PMU.
+ */
+void NvOdmPmuInterruptHandler( NvOdmPmuDeviceHandle  hDevice);
+
+/**
+ * Gets the count in seconds of the current external RTC (in PMU).
+ *
+ * @param hDevice A handle to the PMU.
+ * @param Count A pointer to where to return the current counter in sec.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise. 
+ */
+NvBool
+NvOdmPmuReadRtc(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32* Count);
+
+/**
+ * Updates current RTC value.
+ *
+ * @param hDevice A handle to the PMU.
+ * @param Count data with which to update the current counter in sec.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuWriteRtc(
+    NvOdmPmuDeviceHandle hDevice,
+    NvU32 Count);
+
+/**
+ * Returns whether or not the RTC is initialized.
+ *
+ * @param hDevice A handle to the PMU.
+  * @return NV_TRUE if initialized, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmPmuIsRtcInitialized(
+    NvOdmPmuDeviceHandle hDevice);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_PMU_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_query.h b/arch/arm/mach-tegra/nv/include/nvodm_query.h
new file mode 100644
index 000000000000..a7656cfc7cae
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_query.h
@@ -0,0 +1,1382 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         ODM Query API</b>
+ *
+ * @b Description: Defines a set of query functions for ODMs that may be
+ *                 accessed at boot-time, runtime, or anywhere in between.
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_H
+#define INCLUDED_NVODM_QUERY_H
+
+/**
+ * @defgroup groupODMQueryAPI ODM Query API
+ * @ingroup nvodm_query
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvodm_modules.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * Defines the memory types for which configuration data may be retrieved.
+ */
+typedef enum
+{
+    /// Specifies SDRAM memory; target memory for runtime image and heap.
+    NvOdmMemoryType_Sdram,
+
+    /// Specifies NAND ROM; storage (may include the bootloader).
+    NvOdmMemoryType_Nand,
+
+    /// Specifies NOR ROM; storage (may include the bootloader).
+    NvOdmMemoryType_Nor,
+
+    /// Specifies EEPROM; storage (may include the bootloader).
+    NvOdmMemoryType_I2CEeprom,
+
+    /// Specifies HSMMC NAND; storage (may include the bootloader).
+    NvOdmMemoryType_Hsmmc,
+
+    /// Memory mapped I/O device.
+    NvOdmMemoryType_Mio,
+
+    /// Specifies DPRAM memory
+    NvOdmMemoryType_Dpram,
+
+    NvOdmMemoryType_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmMemoryType_Force32 = 0x7FFFFFFF
+} NvOdmMemoryType;
+
+/**
+ * Defines the devices that can serve as the debug console.
+ */
+typedef enum
+{
+    /// Specifies that the debug console is undefined.
+    NvOdmDebugConsole_Undefined,
+
+    /// Specifies that no debug console is to be used.
+    NvOdmDebugConsole_None,
+
+    /// Specifies that the ARM Debug Communication Channel
+    /// (Dcc) port is the debug console
+    NvOdmDebugConsole_Dcc,
+
+    /// Specifies that UART-A is the debug console.
+    NvOdmDebugConsole_UartA,
+
+    /// Specifies that UART-B is the debug console.
+    NvOdmDebugConsole_UartB,
+
+    /// Specifies that UART-C is the debug console.
+    NvOdmDebugConsole_UartC,
+
+    /// Specifies that UART-D is the debug console (not available on AP15/AP16).
+    NvOdmDebugConsole_UartD,
+
+    /// Specifies that UART-E is the debug console (not available on AP15/AP16).
+    NvOdmDebugConsole_UartE,
+
+    NvOdmDebugConsole_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmDebugConsole_Force32 = 0x7FFFFFFF
+} NvOdmDebugConsole;
+
+
+/**
+ * Defines the devices that can serve as the download transport.
+ */
+typedef enum
+{
+    /// Specifies that the download transport is undefined.
+    NvOdmDownloadTransport_Undefined = 0,
+
+    /// Specifies that no download transport device is to be used.
+    NvOdmDownloadTransport_None,
+
+    /// Specifies that an ODM-specific external Ethernet adapter
+    /// is the download transport device.
+    NvOdmDownloadTransport_MioEthernet,
+
+    /// Deprecated name -- retained for backward compatibility.
+    NvOdmDownloadTransport_Ethernet = NvOdmDownloadTransport_MioEthernet,
+
+    /// Specifies that USB is the download transport device.
+    NvOdmDownloadTransport_Usb,
+
+    /// Specifies that SPI (Ethernet) is the download transport device.
+    NvOdmDownloadTransport_SpiEthernet,
+
+    /// Deprecated name -- retained for backward compatibility.
+    NvOdmDownloadTransport_Spi = NvOdmDownloadTransport_SpiEthernet,
+
+    /// Specifies that UART-A is the download transport device.
+    NvOdmDownloadTransport_UartA,
+
+    /// Specifies that UART-B is the download transport device.
+    NvOdmDownloadTransport_UartB,
+
+    /// Specifies that UART-C is the download transport device.
+    NvOdmDownloadTransport_UartC,
+
+    /// Specifies that UART-D is the download transport device (not available on AP15/AP16).
+    NvOdmDownloadTransport_UartD,
+
+    /// Specifies that UART-E is the download transport device (not available on AP15/AP16).
+    NvOdmDownloadTransport_UartE,
+
+    NvOdmDownloadTransport_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmDownloadTransport_Force32 = 0x7FFFFFFF
+} NvOdmDownloadTransport;
+
+/** 
+ * Contains information and settings for the display (such as the default 
+ * backlight intensity level). 
+ */ 
+typedef struct 
+{ 
+    /// Default backlight intensity (scaled from 0 to 255). 
+    NvU8 BacklightIntensity; 
+} NvOdmQueryDisplayInfo; 
+
+/**
+ * Defines the SPI signal mode for SPI communications to the device.
+ */
+typedef enum
+{
+    /// Specifies the invalid signal mode.
+    NvOdmQuerySpiSignalMode_Invalid = 0x0,
+
+    /// Specifies mode 0 (CPOL=0, CPHA=0) of SPI controller.
+    NvOdmQuerySpiSignalMode_0,
+
+    /// Specifies mode 1 (CPOL=0, CPHA=1) of SPI controller.
+    NvOdmQuerySpiSignalMode_1,
+
+    /// Specifies mode 2 (CPOL=1, CPHA=0) of SPI controller.
+    NvOdmQuerySpiSignalMode_2,
+
+    /// Specifies mode 3 (CPOL=1, CPHA=1) of SPI controller.
+    NvOdmQuerySpiSignalMode_3,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQuerySpiSignalMode_Force32 = 0x7FFFFFFF
+} NvOdmQuerySpiSignalMode;
+
+/**
+ * Holds the SPI device information.
+ */
+typedef struct
+{
+    /// Holds the signal mode for the SPI interfacing.
+    NvOdmQuerySpiSignalMode SignalMode;
+
+    /// If this is NV_TRUE, then this device's chip select is an active-low signal
+    /// (the device is selected by driving its chip select line low). If this
+    /// is NV_FALSE, then this device's chip select is an active-high signal.
+    NvBool ChipSelectActiveLow;
+
+    /// If this is NV_TRUE, then this device is an SPI slave.
+    NvBool IsSlave;
+} NvOdmQuerySpiDeviceInfo;
+
+/**
+ * Defines the SPI signal state in idle state, i.e., when no transaction is going on.
+ */
+typedef struct
+{
+    /// Specifies the signal idle state, whether it is normal or tristate.
+    NvBool IsTristate;
+
+    /// Specifies the signal mode for idle state.
+    NvOdmQuerySpiSignalMode SignalMode;
+
+    /// Specifies the idle state data out level.
+    NvBool IsIdleDataOutHigh;
+
+} NvOdmQuerySpiIdleSignalState;
+
+/**
+ * Defines the SDIO slot usage.
+ */
+typedef enum
+{
+    /** Unused interface. */
+    NvOdmQuerySdioSlotUsage_unused = 0x0,
+
+    /** Specifies a Wireless LAN device. */
+    NvOdmQuerySdioSlotUsage_wlan = 0x1,
+
+    /** Specifies the boot slot (contains the operating system code,
+     *  typically populated by an eMMC). */
+    NvOdmQuerySdioSlotUsage_Boot = 0x2,
+    
+    /** Specifies the media slot, used for user data like audio/video/images. */
+    NvOdmQuerySdioSlotUsage_Media = 0x4,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmQuerySdioSlotUsage_Force32 = 0x7FFFFFFF,
+
+} NvOdmQuerySdioSlotUsage;
+
+/**
+ * Holds the SDIO interface properties.
+ */
+typedef struct
+{
+    /// Holds a flag indicating whether or not the eMMC card connected to the
+    /// SDIO interface is pluggable on the board.
+    ///
+    /// @note If a GPIO is already assigned by NvOdmGpioPinGroup::NvOdmGpioPinGroup_Sdio,
+    /// then this value is ignored. 
+    ///
+    /// If this is NV_TRUE, the eMMC card is pluggable on the board.
+    /// If this is NV_FALSE, the eMMC card is fixed permanently (or soldered) on the board.
+    /// For more information, see NvDdkSdioIsCardInserted().
+    NvBool IsCardRemovable;
+
+    /// Holds SDIO card HW settling time after reset, i.e., before reading the OCR.
+    NvU32 SDIOCardSettlingDelayMSec;
+
+    /// Indicates to the driver whether the card must be re-enumerated after returning
+    /// from suspend or deep sleep modes, because of power loss to the card during those
+    /// modes. NV_TRUE means that the card is powered even though the device enters
+    /// suspend or deep sleep mode, and there is no need to re-enumerate the card after
+    /// returning from suspend/deep sleep.
+    NvBool AlwaysON;
+
+    /// Indicates the tap delay to adjust the track delay on the PCB/Boards from SOC to connector.
+    NvU32 TapDelay;
+
+    /// Defines what the slot is used for.
+    NvOdmQuerySdioSlotUsage usage;
+
+} NvOdmQuerySdioInterfaceProperty;
+
+/**
+ * Defines the bus width used by the HSMMC controller on the platform.
+ */
+typedef enum
+{
+    /// Specifies the invalid bus width.
+    NvOdmQueryHsmmcBusWidth_Invalid = 0x0,
+
+    /// Specifies 4-bit wide bus.
+    NvOdmQueryHsmmcBusWidth_FourBitWide,
+
+    /// Specifies 8-bit wide bus.
+    NvOdmQueryHsmmcBusWidth_EightBitWide,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQueryHsmmcBusWidth_Force32 = 0x7FFFFFFF
+} NvOdmQueryHsmmcBusWidth;
+
+/**
+ * Holds the HSMMC interface properties.
+ */
+typedef struct
+{
+    /// Holds a flag to indicate whether or not the eMMC card connected to
+    /// the HSMMC interface is pluggable on the board. Set this to NV_TRUE
+    /// if the eMMC card is pluggable on the board. If the eMMC card is fixed
+    /// permanently (or soldered) on the board, then set this variable to NV_FALSE.
+    ///
+    /// @note If a GPIO is already assigned by NvOdmGpioPinGroup::NvOdmGpioPinGroup_Hsmmc,
+    /// then this value is ignored. 
+    /// For more information, see NvDdkHsmmcIsCardInserted().
+    NvBool IsCardRemovable;
+
+    /// Holds the bus width supported by the platform for the HSMMC controller.
+    NvOdmQueryHsmmcBusWidth Buswidth;
+} NvOdmQueryHsmmcInterfaceProperty;
+
+/**
+* Defines the OWR device details.
+*/ 
+typedef struct
+{
+    /** Flag to indicate if the "Byte transfer mode" is supported for the given
+     *  OWR device. If not supported for a given device, the driver uses
+     *  "Bit transfer mode" for reading/writing data to the device.
+     */
+    NvBool IsByteModeSupported;
+
+    /** Read data setup, Tsu = N owr clks, Range = tsu < 1. */
+    NvU32 Tsu;
+    /** Release 1-wire time, Trelease = N owr clks, Range = 0 <= trelease < 45. */
+    NvU32 TRelease;
+    /**  Read data valid time, Trdv = N+1 owr clks, Range = Exactly 15. */
+    NvU32 TRdv;
+    /** Write zero time low, Tlow0 = N+1 owr clks, Range = 60 <= tlow0 < tslot < 120. */
+    NvU32 TLow0;
+    /** Write one time low, or TLOWR both are same Tlow1 = N+1 owr clks, 
+     *  Range = 1 <= tlow1 < 15 TlowR = N+1 owr clks, Range = 1 <= tlowR < 15.
+     */
+    NvU32 TLow1;        
+    /** Active time slot for write or read data, Tslot = N+1 owr clks, 
+     *  Range = 60 <= tslot < 120.
+     */
+    NvU32 TSlot;
+
+
+    /** ::PRESENCE_DETECT_LOW Tpdl = N owr clks, Range = 60 <= tpdl < 240.  */
+    NvU32 Tpdl;
+    /** ::PRESENCE_DETECT_HIGH Tpdh = N+1 owr clks, Range = 15 <= tpdh < 60.  */
+    NvU32 Tpdh;
+    /** ::RESET_TIME_LOW Trstl = N+1 owr clks, Range = 480 <= trstl < infinity.  */
+    NvU32 TRstl;        
+    /** ::RESET_TIME_HIGH, Trsth = N+1 owr clks, Range = 480 <= trsth < infinity.  */
+    NvU32 TRsth;            
+
+    /** Program pulse width, Tpp = N owr clks Range = 480 to 5000.  */
+    NvU32 Tpp;
+    /** Program voltage fall time, Tfp = N owr clks Range = 0.5 to 5. */
+    NvU32 Tfp;
+    /** Program voltage rise time, Trp = N owr clks Range = 0.5 to 5. */
+    NvU32 Trp;
+    /** Delay to verify, Tdv = N owr clks, Range = > 5.  */
+    NvU32 Tdv;    
+    /** Delay to program, Tpd = N+1 owr clks, Range = > 5. */
+    NvU32 Tpd;
+
+    /** Should be less than or equal to (tlow1 - 6) clks, 6 clks are used for Deglitch,
+     *  if Deglitch bypassed it is 3 clks.
+     */
+    NvU32 ReadDataSampleClk;
+    /** Should be less than or equal to (tpdl - 6) clks, 6 clks are used for dglitch,
+     *  if Deglitch bypassed it is 3 clks.
+     */
+    NvU32 PresenceSampleClk;
+
+    /** OWR device memory address size. */
+    NvU32 AddressSize;
+    /** OWR device Memory size. */
+    NvU32 MemorySize;
+} NvOdmQueryOwrDeviceInfo;
+
+/**
+ * Defines the functional mode for the I2S channel.
+ */
+typedef enum
+{
+    /// Specifies the I2S controller will generate the clock.
+    NvOdmQueryI2sMode_Master = 1,
+
+    /// Specifies the I2S controller will not generate the clock;
+    /// the audio codec will generate the clock.
+    NvOdmQueryI2sMode_Slave,
+
+    /// Specifies the I2S communication is internal to audio codec.
+    NvOdmQueryI2sMode_Internal,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQueryI2sMode_Force32 = 0x7FFFFFFF
+} NvOdmQueryI2sMode;
+
+/**
+ * Defines the left and right channel data selection control for the audio.
+ */
+typedef enum
+{
+    /// Specifies the left channel when left/right line control signal is low.
+    NvOdmQueryI2sLRLineControl_LeftOnLow = 1,
+
+    /// Specifies the right channel when left/right line control signal is low.
+    NvOdmQueryI2sLRLineControl_RightOnLow,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQueryI2sLRLineControl_Force32 = 0x7FFFFFFF
+} NvOdmQueryI2sLRLineControl;
+
+/**
+ * Defines the possible I2S data communication formats with the audio codec.
+ */
+typedef enum
+{
+    /// Specifies the I2S format for data communication.
+    NvOdmQueryI2sDataCommFormat_I2S = 0x1,
+
+    /// Specifies right-justified format for data communication.
+    NvOdmQueryI2sDataCommFormat_RightJustified,
+
+    /// Specifies left-justified format for data communication.
+    NvOdmQueryI2sDataCommFormat_LeftJustified,
+
+    /// Specifies DSP format for data communication.
+    NvOdmQueryI2sDataCommFormat_Dsp,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQueryI2sDataCommFormat_Force32 = 0x7FFFFFFF
+} NvOdmQueryI2sDataCommFormat;
+
+
+/**
+ * Combines the one-time configuration property for the I2S interface with
+ * audio codec.
+ */
+typedef struct
+{
+    /// Holds the I2S controller functional mode.
+    NvOdmQueryI2sMode Mode;
+
+    /// Holds the left and right channel control.
+    NvOdmQueryI2sLRLineControl I2sLRLineControl;
+
+    /// Holds the information about the I2S data communication format.
+    NvOdmQueryI2sDataCommFormat  I2sDataCommunicationFormat;
+
+    /// Specifies the codec needs a fixed MCLK when I2s acts as Master
+    NvBool IsFixedMCLK;
+
+    /// Specifies the Fixed MCLK Frequency in Khz.
+    /// Supports only three fixed frequencies: 11289, 12288, and 12000.
+    NvU32  FixedMCLKFrequency;
+    
+} NvOdmQueryI2sInterfaceProperty;
+
+/**
+ * Defines the left and right channel data selection control.
+ */
+typedef enum
+{
+    /// Specifies the left channel when left/right line control signal is low.
+    NvOdmQuerySpdifDataCaptureControl_FromLeft = 1,
+
+    /// Specifies the right channel when left/right line control signal is low.
+    NvOdmQuerySpdifDataCaptureControl_FromRight,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQuerySpdifDataCaptureControl_Force32 = 0x7FFFFFFF
+} NvOdmQuerySpdifDataCaptureControl;
+
+/**
+ * Combines the one time configuration property for the SPDIF interface.
+ */
+typedef struct NvOdmQuerySpdifInterfacePropertyRec
+{
+    /// Holds the left and right channel control.
+    NvOdmQuerySpdifDataCaptureControl SpdifDataCaptureControl;
+} NvOdmQuerySpdifInterfaceProperty;
+
+/**
+ * Combines the one-time configuration property for the AC97 interface.
+ */
+typedef struct
+{
+    /// Identifies whether secondary codec is available.
+    NvBool IsSecondoaryCodecAvailable;
+
+    /// Identifies whether left/right surround sound is enabled.
+    NvBool IsLRSurroundSoundEnable;
+
+    /// Identifies whether LFE is enabled.
+    NvBool IsLFEEnable;
+
+    /// Identifies whether center speaker is enabled.
+    NvBool IsCenterSpeakerEnable;
+
+    /// Identifies whether left right PCM is enabled.
+    NvBool IsLRPcmEnable;
+} NvOdmQueryAc97InterfaceProperty;
+
+/**
+ * Combines the one-time configuration property for the audio codec interfaced
+ * by I2S.
+ */
+typedef struct
+{
+    /// Holds whether the audio codec is in master mode or in slave mode.
+    NvBool IsCodecMasterMode;
+
+    /// Holds the dap port index used to connect to the codec.
+    NvU32  DapPortIndex;
+
+    /// Holds the device address if it is an I2C interface, else the chip
+    /// select ID if it is an SPI interface.
+    NvU32 DeviceAddress;
+
+    /// Tells whether it is the USB mode or normal mode of interfacing for the
+    /// audio codec.
+    NvU32 IsUsbMode;
+
+    /// Holds the left and right channel control.
+    NvOdmQueryI2sLRLineControl I2sCodecLRLineControl;
+
+    /// Holds the information about the I2S data communication format.
+    NvOdmQueryI2sDataCommFormat  I2sCodecDataCommFormat;
+} NvOdmQueryI2sACodecInterfaceProp;
+
+/**
+ * Defines the oscillator source.
+ */
+typedef enum
+{
+    /// Specifies the cyrstal oscillator as the clock source.
+    NvOdmQueryOscillator_Xtal = 1,
+
+    /// Specifies an external clock source (bypass mode).
+    NvOdmQueryOscillator_External,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmQueryOscillator_Force32 = 0x7FFFFFFF
+} NvOdmQueryOscillator;
+
+/**
+ *  Defines the wakeup polarity.
+ */
+typedef enum
+{
+    NvOdmWakeupPadPolarity_Low = 0,
+    NvOdmWakeupPadPolarity_High,
+    NvOdmWakeupPadPolarity_AnyEdge,
+    NvOdmWakeupPadPolarity_Force32 = 0x7FFFFFFF
+} NvOdmWakeupPadPolarity;
+
+/** Defines the wakeup pad attributes. */
+typedef struct
+{
+    /// Specifies to enable this pad as wakeup or not.
+    NvBool  enable;
+
+    /// Specifies the wake up pad number. Valid values for AP15 are 0 to 15.
+    NvU32   WakeupPadNumber;
+
+    /// Specifies wake up polarity.
+    NvOdmWakeupPadPolarity Polarity;
+
+} NvOdmWakeupPadInfo;
+
+/**
+ * Defines the index for possible connection based on the use case.
+ */
+typedef enum
+{
+    /// Specifies the default music path.
+    NvOdmDapConnectionIndex_Music_Path = 0,
+
+    /// Specifies the voice call without Bluetooth.
+    NvOdmDapConnectionIndex_VoiceCall_NoBlueTooth = 1,
+    
+    /// Specifies the HD radio.
+    NvOdmDapConnectionIndex_HD_Radio,
+
+    /// Specifies the voice call with Bluetooth.
+    NvOdmDapConnectionIndex_VoiceCall_WithBlueTooth,
+
+    /// Specifies the Bluetooth to codec.
+    NvOdmDapConnectionIndex_BlueTooth_Codec,
+
+    /// Specifies DAC1-to-DAP2 bypass, used for h/w verification.
+    NvOdmDapConnectionIndex_DAC1_DAP2,
+
+    /// Specifies DAC1-to-DAP3 bypass, used for h/w verification.
+    NvOdmDapConnectionIndex_DAC1_DAP3,
+
+    /// Specifies DAC1-to-DAP4 bypass, used for h/w verification.
+    NvOdmDapConnectionIndex_DAC1_DAP4,
+
+    /// Specifies DAC2-to-DAP2 bypass, used for hardware verification.
+    NvOdmDapConnectionIndex_DAC2_DAP2,
+
+    /// Specifies DAC2-to-DAP3 bypass, used for hardware verification.
+    NvOdmDapConnectionIndex_DAC2_DAP3,
+
+    /// Specifies DAC2-to-DAP4 bypass, used for hardware verification.
+    NvOdmDapConnectionIndex_DAC2_DAP4,
+
+    /// Specifies a custom type connection.
+    NvOdmDapConnectionIndex_Custom,
+
+    /// Specifies unknown.
+    NvOdmDapConnectionIndex_Unknown,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmDapConnectionIndex_Force32 = 0x7FFFFFFF
+
+}NvOdmDapConnectionIndex;
+
+/**
+ * Defines the DAP port source and destination enumerations.
+ */
+typedef enum
+{
+    /// NONE DAP port - no connection.
+    NvOdmDapPort_None = 0,
+
+    /// Specifies DAP port 1.
+    NvOdmDapPort_Dap1,
+
+    /// Specifies DAP port 2.
+    NvOdmDapPort_Dap2,
+
+    /// Specifies DAP port 3.
+    NvOdmDapPort_Dap3,
+
+    /// Specifies DAP port 4.
+    NvOdmDapPort_Dap4,
+
+    /// Specifies DAP port 5.
+    NvOdmDapPort_Dap5,
+
+    /// Specifies I2S DAP port 1.
+    NvOdmDapPort_I2s1,
+
+    /// Specifies I2S DAP port 2.
+    NvOdmDapPort_I2s2,
+
+    /// Specifies AC97 DAP port.
+    NvOdmDapPort_Ac97,
+
+    /// Specifies baseband DAP port.
+    NvOdmDapPort_BaseBand,
+
+    /// Specifies Bluetooth DAP port.
+    NvOdmDapPort_BlueTooth,
+
+    /// Specifies media type DAP port.
+    NvOdmDapPort_MediaType,
+
+    /// Specifies voice type DAP port.
+    NvOdmDapPort_VoiceType,
+
+    /// Specifies high fidelity codec DAP port.
+    NvOdmDapPort_HifiCodecType,
+
+    /// Specifies voice codec DAP port.
+    NvOdmDapPort_VoiceCodecType,
+    
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmDapPort_Force32 = 0x7FFFFFFF
+} NvOdmDapPort;
+
+#define NvOdmDapPort_Max NvOdmDapPort_Dap5+1
+/**
+ * Combines the one-time configuration property for DAP device wired to the DAP port.
+ * Currently define only for best suited values. If the device can support more ranges,
+ * you have to consider it accordingly.
+ */
+typedef struct NvOdmDapDevicePropertyRec
+{
+    /// Specifies the number of channels, such as 2 for stereo.
+    NvU32 NumberOfChannels;
+
+    /// Specifies the number of bits per sample, such as 8 or 16 bits.
+    NvU32 NumberOfBitsPerSample;
+
+    /// Specifies the sampling rate in Hz, such as 8000 for 8 kHz, 44100
+    /// for 44.1 kHz.
+    NvU32 SamplingRateInHz;
+
+    /// Holds the information DAP port data communication format.
+    NvOdmQueryI2sDataCommFormat  DapPortCommunicationFormat;
+
+}NvOdmDapDeviceProperty;
+
+/**
+*  Defines the connection line and connection table.
+*/
+typedef struct NvOdmQueryDapPortConnectionLinesRec
+{
+    /// Specifies the source for the connection line.
+    NvOdmDapPort Source;
+
+    /// Specifies the destination for the connection line.
+    NvOdmDapPort Destination;
+
+    /// Specifies the source to act as master or slave.
+    NvBool       IsSourceMaster;
+
+}NvOdmQueryDapPortConnectionLines;
+
+/**
+*  Increases the maximum connection line based on use case connection needed.
+*/
+#define NVODM_MAX_CONNECTIONLINES 8
+
+/**
+*    Defines the DAP port connection.
+*/
+typedef struct NvOdmQueryDapPortConnectionRec
+{
+    /// Specifie the connection use case from the enum provided.
+    NvU32 UseIndex;
+
+    /// Specifies the number of connection line for the table.
+    NvU32 NumofEntires;
+
+    /// Specifies the connection lines for the table.
+    NvOdmQueryDapPortConnectionLines DapPortConnectionLines[NVODM_MAX_CONNECTIONLINES];
+
+}NvOdmQueryDapPortConnection;
+/**
+ * Combines the one-time configuration property for DAP port setting.
+ */
+typedef struct NvOdmQueryDapPortPropertyRec
+{
+    /// Specifies the source for the DAP port.
+    NvOdmDapPort DapSource;
+
+    /// Specifies the destination for the DAP port.
+    NvOdmDapPort DapDestination;
+
+    /// Specified the property of device wired to DAP port.
+    NvOdmDapDeviceProperty DapDeviceProperty;
+
+} NvOdmQueryDapPortProperty;
+
+/**
+ *  Defines ODM interrupt polarity.
+ */
+typedef enum
+{
+    NvOdmInterruptPolarity_Low = 1,
+    NvOdmInterruptPolarity_High,
+    NvOdmInterruptPolarity_Force32 = 0x7FFFFFFF
+} NvOdmInterruptPolarity;
+
+/**
+ *  Defines core power request polarity, as required by a PMU.
+ */
+typedef enum
+{
+  NvOdmCorePowerReqPolarity_Low,
+  NvOdmCorePowerReqPolarity_High,
+  NvOdmCorePowerReqPolarity_Force32 = 0x7FFFFFFF
+}NvOdmCorePowerReqPolarity;
+
+/**
+ *  Defines system clock request polarity, as required by the clock source.
+ */
+typedef enum
+{
+  NvOdmSysClockReqPolarity_Low,
+  NvOdmSysClockReqPolarity_High,
+  NvOdmSysClockReqPolarity_Force32 = 0x7FFFFFFF
+}NvOdmSysClockReqPolarity;
+
+
+/**
+ * Combines PMU configuration properties.
+ */
+typedef struct NvOdmPmuPropertyRec
+{
+    /// Specifies if PMU interrupt is connected to SoC.
+    NvBool IrqConnected;
+
+    /// Specifies the time required for power to be stable (in 32 kHz counts).
+    NvU32   PowerGoodCount;
+
+    /// Specifies the PMU interrupt polarity.
+    NvOdmInterruptPolarity IrqPolarity;
+
+    /// Specifies the core power request signal polarity.
+    NvOdmCorePowerReqPolarity CorePowerReqPolarity;
+
+    /// Specifies the system clock request signal polarity.
+    NvOdmSysClockReqPolarity SysClockReqPolarity;
+
+    /// Specifies whether or not only one power request input on PMU is available. 
+    /// Relevant for SoCs with separate CPU and core power request outputs:
+    /// - NV_TRUE specifies PMU has single power request input, in this case SoC 
+    /// CPU and core power requests must be combined by external logic with
+    /// proper pull-up/pull-down.
+    /// - NV_FALSE specifies PMU has at least two power request inputs, in this
+    /// case SoC CPU and core power requests are connected separately to
+    /// the respective PMU inputs.
+    NvBool CombinedPowerReq;
+
+    /// Specifies the time required for CPU power to be stable (in US).
+    /// Relevant for SoC with separate CPU and core power request outputs.
+    NvU32 CpuPowerGoodUs;
+
+    /// Specifies whether or not CPU voltage will switch back to OTP (default)
+    /// value after CPU request on-off-on transition (typically this transition
+    /// happens on entry/exit to/from low power states). Relevant for SoCs with
+    /// separate CPU and core power request outputs:
+    /// - NV_TRUE specifies PMU will switch CPU voltage to default level after
+    /// CPU request  on-off-on transition. This PMU mode is not compatible with
+    /// DVFS core voltage scaling, which will be disabled in this case.
+    /// - NV_FALSE specifies PMU will restore CPU voltage after CPU request
+    ///  on-off-on transition to the level it has just before the transition
+    /// happens. In this case DVFS core voltage scaling can be enabled.
+    NvBool  VCpuOTPOnWakeup;
+
+    /// Specifies PMU Core and CPU voltage regulation accuracy in percent
+    NvU32 AccuracyPercent;
+
+} NvOdmPmuProperty;
+
+/**
+ *  Defines SOC power states.
+ */
+typedef enum
+{
+  /// State where power to non-always-on (non-AO) partitions are
+  /// removed, and double-data rate (DDR) SDRAM is in self-refresh
+  /// mode. Wake up by any enabled \a external event/interrupt.
+  NvOdmSocPowerState_DeepSleep,
+
+  /// State where the CPU is halted by the flow controller and power
+  /// is gated, plus DDR is in self-refresh. Wake up by any enabled interrupt.
+  NvOdmSocPowerState_Suspend,
+
+  /// Specifies to disable the SOC power state.
+  NvOdmSocPowerState_Active,
+
+  /// Ignore -- Forces compilers to make 32-bit enums.
+  NvOdmSocPowerState_Force32 = 0x7FFFFFFFUL
+
+} NvOdmSocPowerState;
+
+/**
+ *  SOC power state information.
+ */
+typedef struct NvOdmSocPowerStateInfoRec
+{
+    // Specifies the lowest supported power state.
+    NvOdmSocPowerState LowestPowerState;
+
+    // Specifies the idle time (in Msecs) threshold to enter the power state.
+    NvU32 IdleThreshold;
+
+} NvOdmSocPowerStateInfo;
+
+/**  External interface type for USB controllers */
+typedef enum
+{
+    /// Specifies the USB controller is connected to a standard UTMI interface
+    /// (only valid for ::NvOdmIoModule_Usb).
+    NvOdmUsbInterfaceType_Utmi = 1,
+
+    /// Specifies the USB controller is connected to a phy-less ULPI interface
+    /// (only valid for ::NvOdmIoModule_Ulpi).
+    NvOdmUsbInterfaceType_UlpiNullPhy,
+
+    /// Specifies the USB controller is connected to a ULPI interface that has an
+    /// external phy (only valid for \c NvOdmIoModule_Ulpi).
+    NvOdmUsbInterfaceType_UlpiExternalPhy,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmUsbInterfaceType_Force32 = 0x7FFFFFFFUL
+
+} NvOdmUsbInterfaceType;
+
+
+/** Defines the USB line states. */ 
+typedef enum 
+{
+    /// Specifies USB host based charging type.
+    NvOdmUsbChargerType_UsbHost = 0,
+
+    /// Specifies charger type 0, USB compliant charger, when D+ and D- are at low voltage.
+    NvOdmUsbChargerType_SE0 = 1,
+
+    /// Specifies charger type 1, when D+ is high and D- is low.
+    NvOdmUsbChargerType_SJ = 2,
+
+    /// Specifies charger type 2, when D+ is low and D- is high.
+    NvOdmUsbChargerType_SK = 4,
+
+    /// Specifies charger type 3, when D+ and D- are at high voltage.
+    NvOdmUsbChargerType_SE1 = 8,
+
+    /// Specifies charger type 4, D+ and D- are undefined.
+    /// @note If dummy charger is selected, then charger type will be always 
+    /// dummy and other type chargers are detected but treated as dummy.
+    NvOdmUsbChargerType_Dummy = 0x10,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmUsbChargerType_Force32 = 0x7FFFFFFF,
+} NvOdmUsbChargerType;
+
+/** Defines the USB mode for the instance. */ 
+typedef enum 
+{
+    /// Specifies the instance is not present or cannot be used for USB.
+    NvOdmUsbModeType_None = 0,
+
+    /// Specifies the instance as USB host.
+    NvOdmUsbModeType_Host = 1,
+
+    /// Specifies the instance as USB Device.
+    NvOdmUsbModeType_Device = 2,
+
+    /// Specifies the instance as USB OTG.
+    NvOdmUsbModeType_OTG= 4,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmUsbModeType_Force32 = 0x7FFFFFFF,
+} NvOdmUsbModeType;
+
+/** Defines the USB ID pin detection type. */ 
+typedef enum 
+{
+    /// Specifies there is no ID pin detection mechanism.
+    NvOdmUsbIdPinType_None = 0,
+
+    /// Specifies ID pin detection is done with GPIO.
+    NvOdmUsbIdPinType_Gpio= 1,
+
+    /// Specifies ID pin detection is done with cable ID.
+    NvOdmUsbIdPinType_CableId= 2,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmUsbIdPinType_Force32 = 0x7FFFFFFF,
+} NvOdmUsbIdPinType;
+
+/** Defines the USB connectors multiplex type. */ 
+typedef enum 
+{
+    /// Specifies there is no connectors mux  mechanism
+   NvOdmUsbConnectorsMuxType_None = 0,
+
+    /// Specifies microAB/TypeA mux is available. 
+    NvOdmUsbConnectorsMuxType_MicroAB_TypeA= 1,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmUsbConnectorsMuxType_Force32 = 0x7FFFFFFF,
+} NvOdmUsbConnectorsMuxType;
+
+/**
+ *  Defines the USB trimmer control values. Keep all values zero unless the
+ *  default trimmer values programmed in DDK do not work on the customer board.
+ */
+typedef struct NvOdmUsbTrimmerCtrlRec
+{
+    /// Programmable delay on the Shadow ULPI Clock (0 ~ 31)
+    NvU8 UlpiShadowClkDelay;
+
+    /// Programmable delay on the ULPI Clock out (0 ~ 31)
+    NvU8 UlpiClockOutDelay;
+
+    /// ULPI Data Trimmer Value (0 ~ 7)
+    NvU8 UlpiDataTrimmerSel;
+
+    /// ULPI STP/DIR/NXT Trimmer Value (0 ~ 7)
+    NvU8 UlpiStpDirNxtTrimmerSel;
+} NvOdmUsbTrimmerCtrl;
+
+/**  Defines USB interface properties. */
+typedef struct NvOdmUsbPropertyRec
+{
+    ///  Specifies the USB controller's external interface type.
+    ///  @see NvOdmUsbInterfaceType
+    NvOdmUsbInterfaceType UsbInterfaceType;
+
+    /// Specifies the charger types supported on this interface.
+    /// If dummy charger is selected then other type chargers are detected as dummy.
+    /// @see NvOdmUsbChargerType
+    NvU32 SupportedChargers;
+
+    /// Specifies the time required to wait before checking for the line status.
+    /// @see NvOdmUsbChargerType
+    NvU32 ChargerDetectTimeMs;
+
+    /// Specifies internal PHY to use as source for VBUS detection in the low power mode.
+    /// Set to NV_TRUE to use internal PHY for VBUS detection.
+    /// Set to NV_FALSE to use PMU interrupt for VBUS detection.
+    NvBool UseInternalPhyWakeup;
+
+    /// Specifies the USB mode for the instance.
+    /// @see NvOdmUsbModeType
+    NvU32 UsbMode;
+
+    /// Specifies the USB ID pin detection type.
+    /// @see NvOdmUsbIdPinType
+    NvU32 IdPinDetectionType;
+
+    /// Specifies the USB connectors multiplex type.
+    /// @see NvOdmUsbConnectorsMuxType
+    NvOdmUsbConnectorsMuxType   ConMuxType;
+
+    /// Specifies Usb rail to  power off or not  in the deep sleep mode.
+    /// Set to NV_TRUE to specify usb rail power off in the deep sleep
+    /// Set to NV_FALSE to specify usb rail can not be power off in the deep sleep
+    NvBool UsbRailPoweOffInDeepSleep;
+
+    /// Specifies the USB trimmer values. The default value will be used if all values are zeros.
+    /// @see NvOdmUsbTrimmerCtrl
+    NvOdmUsbTrimmerCtrl TrimmerCtrl;
+} NvOdmUsbProperty;
+
+/** Defines wakeup sources. */
+typedef enum
+{
+    NvOdmGpioWakeupSource_Invalid = 0,
+    NvOdmGpioWakeupSource_RIL,
+    NvOdmGpioWakeupSource_UART,
+    NvOdmGpioWakeupSource_BluetoothIrq,
+    NvOdmGpioWakeupSource_HDMIDetection,
+    NvOdmGpioWakeupSource_USB,
+    NvOdmGpioWakeupSource_Lid,
+    NvOdmGpioWakeupSource_AudioIrq,
+    NvOdmGpioWakeupSource_ACCIrq,
+    NvOdmGpioWakeupSource_HSMMCCardDetect,
+    NvOdmGpioWakeupSource_SdioDat1,
+    NvOdmGpioWakeupSource_SdioCardDetect,
+    NvOdmGpioWakeupSource_KBC,
+    NvOdmGpioWakeupSource_PWR,
+    NvOdmGpioWakeupSource_BasebandModem,
+    NvOdmGpioWakeupSource_DVI,
+    NvOdmGpioWakeupSource_GpsOnOff,
+    NvOdmGpioWakeupSource_GpsInterrupt,
+    NvOdmGpioWakeupSource_Accelerometer,
+    NvOdmGpioWakeupSource_HeadsetDetect,
+    NvOdmGpioWakeupSource_PenInterrupt,
+    NvOdmGpioWakeupSource_WlanInterrupt,
+    NvOdmGpioWakeupSource_UsbVbus,
+    NvOdmGpioWakeupSource_Force32 = 0x7FFFFFFF,
+} NvOdmGpioWakeupSource;
+
+/**
+ * Gets the total memory size for the specified memory type.
+ *
+ * @note The implementation of this function must not make reference to
+ * any global or static variables of any kind whatsoever.
+ *
+ * @param MemType Specifies the memory type.
+ *
+ * @return The memory size (in bytes), or 0 if no memory of that type exists.
+ */
+NvU32 NvOdmQueryMemSize(NvOdmMemoryType MemType);
+
+/**
+ * Gets the memory occupied by the secure region. Must be 1 MB aligned.
+ *
+ * @returns The memory occupied (in bytes).
+ */
+NvU32 NvOdmQuerySecureRegionSize(void);
+
+/**
+ * Gets the size of the carveout region.
+ *
+ * The carveout memory region is contiguous physical memory used by some
+ * software modules instead of allocating memory from the OS heap. This memory
+ * is separate from the operating system's heap.
+ *
+ * The carveout memory region is useful because the OS heap often becomes
+ * fragmented after boot time, making it difficult to obtain physically
+ * contiguous memory.
+ */
+NvU32 NvOdmQueryCarveoutSize(void);
+
+/**
+ * Gets the port to use as the debug console.
+ *
+ * @return The debug console ID.
+ */
+NvOdmDebugConsole NvOdmQueryDebugConsole(void);
+
+/**
+ * Gets the device to use as the download transport.
+ *
+ * @return The download transport device ID.
+ */
+NvOdmDownloadTransport NvOdmQueryDownloadTransport(void);
+
+/**
+ * Gets the null-terminated device name prefix string (i.e., that
+ * part of a device name that is common to all devices of this type).
+ *
+ * @return The device name prefix string.
+ */
+const NvU8* NvOdmQueryDeviceNamePrefix(void);
+
+/** 
+ * Gets the configuration info for the display. 
+ * 
+ * @param Instance The instance number of the display controller. 
+ * @return A pointer to the structure containing the display information. 
+ */
+const NvOdmQueryDisplayInfo * 
+NvOdmQueryGetDisplayInfo(
+    NvU32 Instance); 
+
+/**
+ * Gets the interfacing properties of the device connected to a given chip
+ * select on a given SPI controller.
+ *
+ * @param OdmIoModule The ODM I/O module name, such as SPI, S-LINK, or S-Flash.
+ * @param ControllerId The SPI instance ID.
+ * @param ChipSelect The chip select ID from the connected device.
+ *
+ * @return A pointer to a structure describing the device's properties.
+ */
+const NvOdmQuerySpiDeviceInfo *
+NvOdmQuerySpiGetDeviceInfo(
+    NvOdmIoModule OdmIoModule,
+    NvU32 ControllerId,
+    NvU32 ChipSelect);
+
+
+/**
+ * Gets the default signal level of the SPI interfacing lines.
+ * This indicates whether signal lines are in the tristate or not, and if not,
+ * then indicates what is the normal state of the SCLK and data out line.
+ * This state is set once the transaction is completed.
+ * During the transaction, the chip-specific setting is done.
+ *
+ * @param OdmIoModule The ODM I/O module name, such as SPI, S-LINK, or S-Flash.
+ * @param ControllerId The SPI instance ID.
+ *
+ * @return A pointer to a structure describing the idle signal state.
+ */
+const NvOdmQuerySpiIdleSignalState *
+NvOdmQuerySpiGetIdleSignalState(
+    NvOdmIoModule OdmIoModule,
+    NvU32 ControllerId);
+
+/**
+ * Gets the S/PDIF interfacing property parameters with the audio codec that
+ * are set for the data transfer.
+ *
+ * @param SpdifInstanceId The S/PDIF controller instance ID.
+ *
+ * @return A pointer to a structure describing the I2S interface properties.
+ */
+const NvOdmQuerySpdifInterfaceProperty *
+NvOdmQuerySpdifGetInterfaceProperty(
+    NvU32 SpdifInstanceId);
+
+ /**
+ * Gets the I2S interfacing property parameter, which is set for
+ * the data transfer.
+ *
+ * @param I2sInstanceId The I2S controller instance ID.
+ *
+ * @return A pointer to a structure describing the I2S interface properties.
+ *
+ */
+const NvOdmQueryI2sInterfaceProperty *
+NvOdmQueryI2sGetInterfaceProperty(
+    NvU32 I2sInstanceId);
+
+/**
+ * Gets the AC97 interfacing property with AC97 codec parameters that are set
+ * for the data transfer.
+ *
+ * @param Ac97InstanceId The instance ID for the AC97 cotroller.
+ *
+ * @return A pointer to a structure describing the AC97 interface properties.
+ *
+ */
+const NvOdmQueryAc97InterfaceProperty *
+NvOdmQueryAc97GetInterfaceProperty(
+    NvU32 Ac97InstanceId);
+
+/**
+ * Gets the DAP port property.
+ *
+ * This shows how the DAP connection is made along with
+ * the format and mode it supports.
+ *
+ * @param DapPortId The DAP port.
+ *
+ * @return A pointer to a structure holding the DAP port connection properties.
+ */
+const NvOdmQueryDapPortProperty *
+NvOdmQueryDapPortGetProperty(
+    NvU32 DapPortId);
+
+/**
+ * Gets the DAP port connection table.
+ *
+ * This shows how the connections are made along with
+ * the use case.
+ *
+ * @param ConnectionIndex The index to ConnectionTable based on the use case.
+ *
+ * @return A pointer to a structure holding the connection lines.
+ */
+const NvOdmQueryDapPortConnection*
+NvOdmQueryDapPortGetConnectionTable(
+    NvU32 ConnectionIndex);
+
+/**
+ * Gets the I2S audio codec interfacing property.
+ *
+ * @param AudioCodecId The instance ID or the audio codec cotroller.
+ *
+ * @return A pointer to a structure describing the audio codec interface
+ *           properties.
+ */
+const NvOdmQueryI2sACodecInterfaceProp *
+NvOdmQueryGetI2sACodecInterfaceProperty(
+    NvU32 AudioCodecId);
+
+/**
+ * Gets the oscillator source.
+ *
+ * @see NvOdmQueryOscillator
+ *
+ * @return The oscillator source.
+ */
+NvOdmQueryOscillator NvOdmQueryGetOscillatorSource(void);
+
+/**
+ * Gets the oscillator drive strength setting.
+ *
+ * @return The oscillator drive strength setting.
+ */
+NvU32 NvOdmQueryGetOscillatorDriveStrength(void);
+
+/**
+ * Gets the null-terminated device manufacturer string.
+ *
+ * @return A pointer to the device manufacturer string.
+ */
+const NvU8* NvOdmQueryManufacturer(void);
+
+/**
+ * Gets the null-terminated device model string.
+ *
+ * @return A pointer to the device model string.
+ */
+const NvU8* NvOdmQueryModel(void);
+
+/**
+ * Gets the null-terminated device platform string.
+ *
+ * @return A pointer to the device platform string.
+ */
+const NvU8* NvOdmQueryPlatform(void);
+
+/**
+ * Gets the null-terminated device project name string.
+ *
+ * @return A pointer to the device project name string.
+ */
+const NvU8* NvOdmQueryProjectName(void);
+
+/**
+ * Gets the wake pads configuration table.
+ *
+ * @param entries A pointer to a variable that this function sets to the
+ * number of entries in the configuration table.
+ *
+ * @return A pointer to the configuration table.
+ */
+const NvOdmWakeupPadInfo *NvOdmQueryGetWakeupPadTable(NvU32 *entries);
+
+/**
+ * Gets the external PMU property.
+ *
+ * @param pPmuProperty A pointer to the returned PMU property structure.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmQueryGetPmuProperty(NvOdmPmuProperty* pPmuProperty);
+
+/**
+ * Gets the lowest SOC power state info supported by the ODM.
+ *
+ * @return A pointer to the NvOdmSocPowerStateInfo structure
+ */
+const NvOdmSocPowerStateInfo* NvOdmQueryLowestSocPowerState(void);
+
+/**
+ * Returns the type of the USB interface based on module ID and
+ * instance. The \a Module and \a Instance parameter are identical to the
+ * \a IoModule parameter and array index, respectively, used in the 
+ * NvOdmQueryPinMux() and NvOdmQueryClockLimits() APIs.
+ *
+ * @return The properties structure for the USB interface.
+ */
+const NvOdmUsbProperty*
+NvOdmQueryGetUsbProperty(NvOdmIoModule Module, NvU32 Instance);
+
+/**
+ * Gets the interface properties of the SDIO controller.
+ *
+ * @param Instance The instance number of the SDIO controller.
+ * @return A pointer to the structure containing the SDIO interface property.
+ */
+ 
+const NvOdmQuerySdioInterfaceProperty*
+NvOdmQueryGetSdioInterfaceProperty(
+        NvU32 Instance);
+
+/**
+ * Gets the interface properties of the HSMMC controller.
+ *
+ * @param Instance The instance number of the HSMMC controller.
+ * @return A pointer to the structure containing the HSMMC interface property.
+ */
+ 
+const NvOdmQueryHsmmcInterfaceProperty*
+NvOdmQueryGetHsmmcInterfaceProperty(
+        NvU32 Instance);
+
+/**
+ * Gets the ODM-specific sector size for block devices.
+ *
+ * @param OdmIoModule The ODM I/O module type.
+ * @return An integer indicating the sector size if non-zero, or 
+ *      zero if the sector size equals the actual device-reported sector size.
+ */
+NvU32
+NvOdmQueryGetBlockDeviceSectorSize(NvOdmIoModule OdmIoModule);
+
+/**
+ * Gets the OWR device information.
+ *
+ * @param Instance The instance number of the OWR controller.
+ * @return A pointer to the structure containing the OWR device info.
+ */
+const NvOdmQueryOwrDeviceInfo* NvOdmQueryGetOwrDeviceInfo(NvU32 Instance);
+
+/**
+ * Gets the list of supported wakeup sources.
+ *
+ * @param pCount The number of wakeup sources.
+ * @return A pointer to the array containing the wakeup sources.
+ */
+const NvOdmGpioWakeupSource *NvOdmQueryGetWakeupSources(NvU32 *pCount);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_QUERY_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_query_gpio.h b/arch/arm/mach-tegra/nv/include/nvodm_query_gpio.h
new file mode 100644
index 000000000000..6e0c449355bd
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_query_gpio.h
@@ -0,0 +1,377 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         GPIO Query Interface</b>
+ *
+ * @b Description: Defines the ODM query interface for GPIO pins.
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_GPIO_H
+#define INCLUDED_NVODM_QUERY_GPIO_H
+/**
+ * @defgroup nvodm_gpio GPIO Query Interface
+ * This is the ODM query interface for GPIO configurations.
+ * @ingroup nvodm_query
+ * @{
+ */
+#include "nvcommon.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * Defines GPIO pin groups.
+ */
+typedef enum
+{
+    /// Specifies a NULL display group.
+    NvOdmGpioPinGroup_None = 0,
+
+    /// Specifies a display pin group.
+    NvOdmGpioPinGroup_Display,
+
+    /// Specifies a keypad column pin group--used only if the system uses
+    /// GPIO-based keypad.
+    NvOdmGpioPinGroup_keypadColumns,
+
+    /// Specifies a keypad rows pin group--used only if the system uses
+    /// GPIO-based keypad.
+    NvOdmGpioPinGroup_keypadRows,
+
+    /// Specifies a special key for a keypad--This is used in both KBC based
+    /// keypad and GPIO-based keypad.
+    NvOdmGpioPinGroup_keypadSpecialKeys,
+
+    /// Specifies a pin group representing all the other keypad GPIOs.
+    NvOdmGpioPinGroup_keypadMisc,
+
+    /// Specifies an SDIO pin group. This pin group has 2 instances.
+    /// @note If this value is set, NvOdmQuerySdioInterfaceProperty::IsCardRemovable
+    /// is ignored.
+    NvOdmGpioPinGroup_Sdio,
+
+    /// Specifies an HSMMC pin group.
+    /// @note If this value is set, NvOdmQueryHsmmcInterfaceProperty::IsCardRemovable
+    /// is ignored.
+    NvOdmGpioPinGroup_Hsmmc,
+
+    /// Specifies a USB pin group.
+    NvOdmGpioPinGroup_Usb,
+
+    /// Specifies an IDE function pin group.
+    NvOdmGpioPinGroup_Ide,
+
+    /// Specifies an OEM pin group.
+    NvOdmGpioPinGroup_OEM,
+
+    /// Specifies a test pin group used by the internal tests.
+    NvOdmGpioPinGroup_Test,
+
+    /// Specifies a group used by the external MIO Ethernet adapter.
+    NvOdmGpioPinGroup_MioEthernet,
+
+    /// Deprecated name -- retained for backward compatibility.
+    NvOdmGpioPinGroup_Ethernet = NvOdmGpioPinGroup_MioEthernet,
+
+    /// Specifies a group used for NAND flash write protect.
+    NvOdmGpioPinGroup_NandFlash,
+
+    /// Specifies a group used for scroll wheel pins.
+    NvOdmGpioPinGroup_ScrollWheel,
+
+    /// Specifies a group used for MIO bus control signals.
+    NvOdmGpioPinGroup_Mio,
+
+    /// Specifies a group used for bluetooth control signals.
+    NvOdmGpioPinGroup_Bluetooth,
+
+    /// Specifies a group used for WLAN control signals.
+    NvOdmGpioPinGroup_Wlan,
+
+    /// Specifies a group for HDMI.
+    NvOdmGpioPinGroup_Hdmi,
+
+    /// Specifies a group for CRT.
+    NvOdmGpioPinGroup_Crt,
+
+    /// Specifies a group for SPI.
+    NvOdmGpioPinGroup_SpiEthernet,
+
+    /// Deprecated name -- retained for backward compatibility.
+    NvOdmGpioPinGroup_Spi = NvOdmGpioPinGroup_SpiEthernet,
+
+    /// Specifies a group for Vi.
+    NvOdmGpioPinGroup_Vi,
+
+    /// Specifies a group for DSI.
+    NvOdmGpioPinGroup_Dsi,
+
+    
+    /// Specifies a group for keys used to suspend/resume/shutdown.
+    NvOdmGpioPinGroup_Power,
+
+    /// Specifies a group for keys used to resume from EC keyboard.
+    NvOdmGpioPinGroup_WakeFromECKeyboard,
+
+    /// Specifies the total number of pin groups.
+    NvOdmGpioPinGroup_Num,
+    NvOdmGpioPinGroup_Force32 = 0x7FFFFFFF,
+} NvOdmGpioPinGroup;
+
+/**  @name Display GPIO Pins
+ *  Each panel uses some number of GPIO pins for configuring the panel. The
+ *  usage and the number of pins vary from panel to panel. One main board can
+ *  support multiple panels. In such cases, GPIOs used by all the panels must
+ *  be reserved. GPIO pin table exported by display pin group is a set of all
+ *  the panels it supports--one set for each panel. The client of this API is
+ *  the display ODM adaptation. Display ODM adaptation is written once for a
+ *  panel and all the board-specific changes are abstratced in this API.
+ *
+ *  If the ODM implements its own display adaptation, rather than the using the
+ *  display adaptation provided by NVIDIA, there is no need to implement
+ *  display virtual pin map.
+ *
+ *  Please refer to the documentation for the mapping between physical panel
+ *  and panel index used here.
+ */
+/*@{*/
+#define NvOdmGpioPin_DisplayPanel0Pincount   (6)
+#define NvOdmGpioPin_DisplayPanel0Start      (0)
+#define NvOdmGpioPin_DisplayPanel0End        (NvOdmGpioPin_DisplayPanel0Start + NvOdmGpioPin_DisplayPanel0Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPanel1Pincount   (4)
+#define NvOdmGpioPin_DisplayPanel1Start      (NvOdmGpioPin_DisplayPanel0End + 1)
+#define NvOdmGpioPin_DisplayPanel1End        (NvOdmGpioPin_DisplayPanel1Start + NvOdmGpioPin_DisplayPanel1Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPanel2Pincount   (1)
+#define NvOdmGpioPin_DisplayPanel2Start      (NvOdmGpioPin_DisplayPanel1End + 1)
+#define NvOdmGpioPin_DisplayPanel2End        (NvOdmGpioPin_DisplayPanel2Start + NvOdmGpioPin_DisplayPanel2Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPanel3Pincount   (21)
+#define NvOdmGpioPin_DisplayPanel3Start      (NvOdmGpioPin_DisplayPanel2End + 1)
+#define NvOdmGpioPin_DisplayPanel3End        (NvOdmGpioPin_DisplayPanel3Start + NvOdmGpioPin_DisplayPanel3Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPanel4Pincount   (1)
+#define NvOdmGpioPin_DisplayPanel4Start      (NvOdmGpioPin_DisplayPanel3End + 1)
+
+#define NvOdmGpioPin_DisplayPanel4End        (NvOdmGpioPin_DisplayPanel4Start + NvOdmGpioPin_DisplayPanel4Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPanel5Pincount   (4)
+#define NvOdmGpioPin_DisplayPanel5Start      (NvOdmGpioPin_DisplayPanel4End + 1)
+
+#define NvOdmGpioPin_DisplayPanel5End        (NvOdmGpioPin_DisplayPanel5Start + NvOdmGpioPin_DisplayPanel5Pincount - 1)
+
+#define NvOdmGpioPin_DisplayPinCount         (NvOdmGpioPin_DisplayPanel5End + 1)
+
+/*@}*/
+/**@name Keypad Virtual Pins */
+/*@{*/
+/** Max GPIOs that can be used for as rows in GPIO-based keypad. For chips
+ * later than AP15, silicon supports a dedicated KBC controller.
+ * If using GPIO-based keypad driver, it has the upper limit on the number of
+ * the rows defined by this macro.
+ * When the NvOdmQueryGpioPinMap() is called with virtual pin group of
+ * ::NvOdmGpioPinGroup_keypadColumns, ODM should return an array
+ * of GPIOs mapped for column keys. Array size should not be more than 32. This
+ * upper limit is just for saftey checks and in no sense inidicates the
+ * limitations of the NVIDIA driver. */
+#define NvOdmGpioPin_keypadColumnsPinCountMax       (32)
+
+/** Max GPIOs that can be used for as rows in GPIO  based keypad. For chips
+ * later than AP15, silicon supports a dedicated KBC controller.
+ * If using GPIO-based keypad driver, it has the upper limit on the number of
+ * the rows defined by this macro.
+ * When NvOdmQueryGpioPinMap() is called with virtual pin group of
+ * ::NvOdmGpioPinGroup_keypadRows, ODM should return a array
+ * of GPIOs mapped for row keys. Array size should not be more than
+ * ::NvOdmGpioPin_keypadRowsPinCountMax.
+ * This upper limit is just for saftey checks and does not inidicate the
+ * limitations of the NVIDIA driver. */
+#define NvOdmGpioPin_keypadRowsPinCountMax          (32)
+
+/** Max GPIOs that can be used for the special keys. Driver is limited by this
+ * number of special keys. When NvOdmQueryGpioPinMap() is called with virtual
+ * pin group of ::NvOdmGpioPinGroup_keypadSpecialKeys, ODM should return an array
+ * of GPIOs mapped for special keys. Array size should not be more than 32. This
+ * upper limit is just for saftey checks and in no sense inidicates the
+ * limitations of the NVIDIA driver. */
+#define NvOdmGpioPin_keypadSpecialKeysCountMax      (32)
+
+/*@}*/
+/** @name Misc Keypad GPIOs */
+/*@{*/
+/** GPIO used to control illuminating the keypad. This GPIO line is set to
+ * active state when a key is pressed. */
+#define NvOdmGpioPin_keypadMiscBackLight         (0)
+/** When this key is in pressed state all the inputs are disabled. */
+#define NvOdmGpioPin_keypadMiscHoldKey           (NvOdmGpioPin_keypadMiscBackLight + 1)
+/** Total count pin count for keypad pin group */
+#define NvOdmGpioPin_keypadMiscPinCount          (NvOdmGpioPin_keypadMiscHoldKey + 1)
+
+/*@}*/
+/** @name HSMMC Virtual Pins */
+/*@{*/
+#define NvOdmGpioPin_HsmmcCardDetect        (0)
+#define NvOdmGpioPin_HsmmcWriteProtect      (NvOdmGpioPin_HsmmcCardDetect + 1)
+#define NvOdmGpioPin_HsmmcPinCount          (NvOdmGpioPin_HsmmcWriteProtect + 1)
+
+/*@}*/
+/** @name SDIO Virtual Pins */
+/*@{*/
+#define NvOdmGpioPin_SdioCardDetect         (0)
+#define NvOdmGpioPin_SdioWriteProtect       (NvOdmGpioPin_SdioCardDetect +1)
+#define NvOdmGpioPin_SdioPinCount           (NvOdmGpioPin_SdioWriteProtect + 1)
+
+/*@}*/
+/** @name USB GPIO Pins */
+/*@{*/
+#define NvOdmGpioPin_UsbCableId    (0)
+#define NvOdmGpioPin_UsbPinCount           (NvOdmGpioPin_UsbCableId + 1)
+
+/*@}*/
+/** @name IDE Function GPIO Pins */
+/*@{*/
+#define NvOdmGpioPin_IdePowerEnable (0)
+#define NvOdmGpioPin_IdePinCount (NvOdmGpioPin_IdePowerEnable + 1)
+
+/*@}*/
+/** @name Test Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_Test1                  (0)
+#define NvOdmGpioPin_Test2                  (1)
+#define NvOdmGpioPin_TestPinCount           (NvOdmGpioPin_Test2 + 1)
+
+/*@}*/
+/** @name External Ethernet Adapter Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_Ethernet               (0)
+#define NvOdmGpioPin_EthernetCount          (NvOdmGpioPin_Ethernet + 1)
+
+/*@}*/
+/** @name NAND Flash WP Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_NandFlash              (0)
+#define NvOdmGpioPin_NandFlashCount         (NvOdmGpioPin_NandFlash + 1)
+
+/*@}*/
+/** @name Scroll Wheel Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_ScrollWheelInputPin1   (0)
+#define NvOdmGpioPin_ScrollWheelOnOff       (NvOdmGpioPin_ScrollWheelInputPin1 + 1)
+#define NvOdmGpioPin_ScrollWheelSelectPin   (NvOdmGpioPin_ScrollWheelOnOff + 1)
+#define NvOdmGpioPin_ScrollWheelInputPin2   (NvOdmGpioPin_ScrollWheelSelectPin + 1)
+/*@}*/
+/** @name Bluetooth Control Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_Bluetooth   (0)
+#define NvOdmGpioPin_BluetoothReset        (NvOdmGpioPin_Bluetooth + 1)
+
+/*@}*/
+/** @name WLAN Control Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_Wlan   (0)
+#define NvOdmGpioPin_WlanPower             (NvOdmGpioPin_Wlan + 1)
+#define NvOdmGpioPin_WlanReset             (NvOdmGpioPin_WlanPower + 1)
+
+/*@}*/
+/** @name DSI Pin Groups */
+/*@{*/
+#define NvOdmGpioPin_DsiLcdResetId               (0)
+#define NvOdmGpioPin_DsiLcdTeId          (NvOdmGpioPin_DsiLcdResetId + 1)
+#define NvOdmGpioPin_DsiLcdHsIntId          (NvOdmGpioPin_DsiLcdTeId + 1)
+/*@}*/
+
+/**
+ *  Defines the active state of the pin. For example, a USB cable connect pin
+ *  might be configured to have a active state of low when the cable is
+ *  connetced. On some boards the same pin can be configured as active high.
+ *  This enum abstracts this information.
+ */
+typedef enum
+{
+    NvOdmGpioPinActiveState_Low = 0,
+    NvOdmGpioPinActiveState_High,
+    NvOdmGpioPinActiveState_Force32 = 0x7FFFFFFF,
+} NvOdmGpioPinActiveState;
+
+/**
+ * Holds the GPIO pin information.
+ */
+typedef struct  NvOdmGpioPinInfo_t {
+    /// Holds the physical port mapped to the virtual pin group \c vGroup/virtual pin \c vPin.
+    NvU32 Port;
+    /// Holds the physical pin mapped to the virtual pin group \c vGroup/virtual pin \c vPin.
+    NvU32 Pin;
+    /// Holds the active state of the pin. This is valid only for the input pins. Active
+    /// state is defined by each pin. For example, for a USB cable connect virtual pin,
+    /// the active state is when the cable is connected.
+    NvOdmGpioPinActiveState activeState;
+} NvOdmGpioPinInfo;
+
+#define NVODM_GPIO_INVALID_PORT 0xFF
+#define NVODM_GPIO_INVALID_PIN  0xFF
+
+/// Connected imager devices use the camera reserved GPIOs.
+/// Valid GPIO pins are between 0 and 6, and map to the external
+/// pins referred to as VGP0 thru VGP6, with the exception of 1 and 2.
+/// VGP1 and VGP2 are used for the camera I2C, so the VD10 and VD11 pins
+/// are substituted, via this interface, so as to avoid accidental use.
+#define NVODM_GPIO_CAMERA_PORT  0xFE
+
+/**
+ * Gets the pin mappings for a virtual group. For optimal access the table should be
+ * sorted using the vPin value.
+ *
+ * @see NvOdmGpioPinGroup
+ *
+ * @param Group The pin group for which the query is being made.
+ * @param instance The instance of the pin group. For example, there are 2 instances
+ * of the SDIO pin group.
+ * @param count A pointer to the count of entires in the ::NvOdmGpioPinInfo.
+ *
+ * @return A const pointer to the pin info table if the pin group
+ * has valid GPIO configuration.
+ */
+const NvOdmGpioPinInfo *NvOdmQueryGpioPinMap(NvOdmGpioPinGroup Group, NvU32 instance, NvU32 *count);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif  // INCLUDED_NVODM_QUERY_GPIO_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_query_kbc.h b/arch/arm/mach-tegra/nv/include/nvodm_query_kbc.h
new file mode 100644
index 000000000000..f8078961978e
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_query_kbc.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Keyboard Controller Interface</b>
+ *
+ * @b Description: Defines the ODM query interface for NVIDIA keyboard 
+ *                 controller (KBC) adaptation.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_KBC_H
+#define INCLUDED_NVODM_QUERY_KBC_H
+
+#include "nvcommon.h"
+
+/**
+ * @defgroup nvodm_query_kbc Keyboard Controller Query Interface
+ * This is the keyboard controller (KBC) ODM Query interface.
+ * See also the \link nvodm_kbc KBC ODM Adaptation Interface\endlink.
+ * @ingroup nvodm_query
+ * @{
+ */
+
+/**
+ * Defines the parameters associated with this device.
+ */
+typedef enum
+{
+    NvOdmKbcParameter_NumOfRows=1,
+    NvOdmKbcParameter_NumOfColumns,
+    NvOdmKbcParameter_DebounceTime,
+    NvOdmKbcParameter_RepeatCycleTime,
+    NvOdmKbcParameter_Force32 = 0x7FFFFFFF
+} NvOdmKbcParameter;
+
+/**
+ * Queries the peripheral device for its current settings.
+ * 
+ * @see NvOdmKbcParameter
+ *
+ * @param param  Specifies which parameter value to get.
+ * @param sizeOfValue  The length of the parameter data (in bytes).
+ * @param value  A pointer to the location where the requested parameter shall
+ *     be stored.
+ * 
+ */
+void 
+NvOdmKbcGetParameter(
+        NvOdmKbcParameter param,
+        NvU32 sizeOfValue,
+        void *value);
+
+/**
+ * Gets the key code depending upon the row and column values.
+ * 
+ * @param Row  The value of the row.
+ * @param Column The value of the column.
+ * @param RowCount The number of the rows present in the keypad matrix.
+ * @param ColumnCount The number of the columns present in the keypad matrix.
+ * 
+ * @return The appropriate key code.
+ */
+NvU32 
+NvOdmKbcGetKeyCode(
+    NvU32 Row, 
+    NvU32 Column,
+    NvU32 RowCount,
+    NvU32 ColumnCount);
+
+/**
+ * Queries if wake-up only on selected keys is enabled for WPC-like
+ * configurations. If it is enabled, returns the pointers to the static array
+ * containing the row and columns numbers. If this is enabled and \a NumOfKeys
+ * selected is zero, all the keys are disabled for wake-up when system is
+ * suspended.
+ * 
+ * @note The selected keys must not be a configuration of type 1x1, 1x2, etc. 
+ * In other words, a minimum of two rows must be enabled due to hardware
+ * limitations.
+ *
+ * @param pRowNumber A pointer to the static array containing the row 
+ *                   numbers of the keys.
+ * @param pColNumber A pointer to the static array containing the column 
+ *                   numbers of the keys.
+ * @param NumOfKeys A pointer to the number of keys that must be enabled.
+ *                  This indicates the number of elements in the arrays pointer by
+ *                   \a pRowNumber and \a pColNumber.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmKbcIsSelectKeysWkUpEnabled(
+    NvU32 **pRowNumber,
+    NvU32 **pColNumber,
+    NvU32 *NumOfKeys);
+
+/** @} */
+#endif // INCLUDED_NVODM_QUERY_KBC_H
+
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_query_memc.h b/arch/arm/mach-tegra/nv/include/nvodm_query_memc.h
new file mode 100644
index 000000000000..57dfae9afb2d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_query_memc.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Memory Controller Query Interface</b>
+ *
+ * @b Description: Defines the ODM query interface for Memory Controller.
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_MEMC_H
+#define INCLUDED_NVODM_QUERY_MEMC_H
+
+/**
+ * @defgroup nvodm_memc Memory Controller Query Interface
+ * This is the ODM query interface for memory controller.
+ * @ingroup nvodm_query
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvodm_query.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * Holds the configuration parameters for asynchronous memory like NOR flash
+ * or Memory Mapped I/O (MIO).
+ */
+
+typedef struct
+{
+    /// Holds TRUE for enabling access time extension using ROM busy pin.
+    NvBool isRomBusyEnable;
+
+    /// Holds the dead time in nano seconds between the end of a write access and
+    /// the start of the following access (write or read) for NOR/MIO memory.
+    NvU32 WriteDeadTime;
+
+    /// Holds the access time in nano seconds for which write signal is asserted
+    /// during a write access for MIO/NOR memory.
+    NvU32 WriteAccessTime;
+
+    /// Holds the dead time in nano seconds between the end of a read access and
+    /// the start of the following access (write or read) for MIO/NOR memory.
+    NvU32 ReadDeadTime;
+
+    /// Holds the access time in nano seconds for which read signal is asserted
+    /// during a read access.
+    NvU32 ReadAccessTime;
+
+} NvOdmAsynchMemConfig;
+
+/**
+ * Holds synchronous memory (SDRAM) controller configuration parameters for the
+ * specified SDRAM frequency and controller core voltage. This structure is
+ * assigned fixed revision 1.0.
+ */
+typedef struct NvOdmSdramControllerConfigRec
+{
+    /// Holds the SDRAM frequency in kHz.
+    NvU32 SdramKHz;
+
+    /// Holds minimum core voltage in mV for memory controller operations at
+    /// the specified SDRAM frequency. Actual core voltage can be set higher by
+    /// DVFS depending on the operation requirements for other SoC modules.
+    NvU32 EmcCoreVoltageMv;
+ 
+    /// Holds the memory controller timing parameter 0.
+    NvU32 EmcTiming0;
+ 
+    /// Holds the memory controller timing parameter 1.
+    NvU32 EmcTiming1;
+ 
+    /// Holds the memory controller timing parameter 2.
+    NvU32 EmcTiming2;
+ 
+    /// Holds the memory controller timing parameter 3.
+    NvU32 EmcTiming3;
+ 
+    /// Holds the memory controller timing parameter 4.
+    NvU32 EmcTiming4;
+ 
+    /// Holds the memory controller timing parameter 5.
+    NvU32 EmcTiming5;
+ 
+    /// Holds the memory controller FBIO configuration parameter 6.
+    NvU32 EmcFbioCfg6;
+ 
+    /// Holds the memory controller FBIO QSIB delay parameter.
+    NvU32 EmcFbioDqsibDly;
+ 
+    /// Holds the emory controller FBIO QUSE delay parameter.
+    NvU32 EmcFbioQuseDly;
+} NvOdmSdramControllerConfig;
+
+/// Defines revision for basic memory controller configuration structure,
+/// i.e., 0x10 is Rev 1.0.
+#define NV_EMC_BASIC_REV    (0x10)
+
+/// Defines maximum number of advanced memory controller timing parameters.
+#define NV_EMC_ADV_PARAM_NUM_MAX    (50)
+
+/**
+ * Holds synchronous memory (SDRAM) advanced controller configuration
+ * parameters for the specified SDRAM frequency and controller core voltage.
+ * The revision of this structure is started with 2.0, and it is embedded as
+ * the structure field.
+ */
+typedef struct NvOdmSdramControllerConfigAdvRec
+{
+    /// Holds revision of this structure, e.g., 0x20 is Rev 2.0.
+    NvU32 Revision;
+
+    /// Holds the SDRAM frequency in kHz.
+    NvU32 SdramKHz;
+
+    /// Holds minimum core voltage in mV for memory controller operations at
+    /// the specified SDRAM frequency. Actual core voltage can be set higher by
+    /// DVFS depending on the operation requirements for other SoC modules.
+    NvU32 EmcCoreVoltageMv;
+
+    /// Holds the number of advanced memory controller timing parameters.
+    NvU32 EmcTimingParamNum;
+ 
+    /// Holds the advanced memory controller timing parameters.
+    NvU32 EmcTimingParameters[NV_EMC_ADV_PARAM_NUM_MAX];
+} NvOdmSdramControllerConfigAdv;
+
+/**
+ * Gets the device memory controller configuration.
+ *
+ * @note This function is called early from the boot process where
+ * global variables are not yet valid. Care must be taken not to
+ * use global variables in the implementation of this function.
+ *
+ * @note The implementation of this function must not make reference to
+ * any global or static variables of any kind whatsoever.
+ *
+ * @see NvOdmAsynchMemConfig
+ *
+ * @param ChipSelect The chip select for which configuration
+ * is required:
+ * - 0 means chip select A
+ * - 1 means chip select B
+ * - 2 means chip select C
+ * - and so on.
+ *
+ * @param pMemConfig A pointer to the returned NOR memory configuration.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ *
+ */
+NvBool NvOdmQueryAsynchMemConfig(NvU32 ChipSelect, NvOdmAsynchMemConfig *pMemConfig);
+
+
+/**
+ * Gets the configuration table that provides SDRAM controller parameters for
+ * the selected set of SDRAM frequencies and controller core voltages. This
+ * table is used by the memory controller DVFS.
+ * 
+ * @sa NvOdmSdramControllerConfig structure description for the format of each
+ * table entry, revision 1.0.
+ * @sa NvOdmSdramControllerConfigAdv structure description for the format of
+ * each table entry, revision 2.0.
+ * 
+ * @note The maximum scaled SDRAM frequency Fmax is limited by boot configuration
+ * of memory:
+ * <pre>
+ *    PLL - PLLM: Fmax = (PLLM boot output frequency)/2 
+ * </pre>
+ * The minimum scaled SDRAM frequency is fixed as
+ * <pre>
+ *    Fmin = 12MHz
+ * </pre>
+ *
+ * @par SDRAM Frequency Ladders
+ * 
+ * Revision 1.0 - Only entries for Fmax and evenly
+ * divided from Fmax SDRAM frequencies above Fmin are used by DVFS (e.g. Fmax,
+ * Fmax/2, Fmax/4, Fmax/6, etc). All other entries are ignored. Hence, one
+ * table can contain entries for all different PLLM configurations used for the
+ * particular ODM platform, and DVFS will automatically select the frequency ladder
+ * based on the boot settings. For example, the table can mix entries for Fmax
+ * = 166MHz ladder (166/83/41.5/27.6) and Fmax = 133MHz ladder (133/66.5/33.25/
+ * 21.16). The table is not required to be sorted in any way.
+ * 
+ * Revision 2.0 - Only entries for Fmax and .... 
+ * ladders 
+ * 
+ * The memory controller DVFS is enabled, provided all of the following
+ * conditions are true:
+ * - This function returns a non-NULL pointer to the table.
+ * - The table includes an entry for Fmax SDRAM frequency.
+ * - The table includes an entry for boot SDRAM frequency (if boot configuration
+ * utilizes EMC divider to set initial SDRAM frequency different from Fmax).
+ * This condition is applicable only to Revision 1.0 configuration.
+ * If any of the above conditions are not met, memory controller DVFS will be
+ * disabled and boot SDRAM configuration is preserved during run time.
+ * 
+ * @param pEntries A pointer to a variable which this function sets to the
+ * number of entires in the configuration table.
+ * @param pRevision A pointer to a variable which this function sets to the
+ * revision number of the configuration table entry structure.
+ *
+ * @return A const pointer to the configuration table, or NULL if EMC DVFS
+ *   is disabled.
+ */
+const void*
+NvOdmQuerySdramControllerConfigGet(NvU32 *pEntries, NvU32 *pRevision); 
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_QUERY_MEMC_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_query_nand.h b/arch/arm/mach-tegra/nv/include/nvodm_query_nand.h
new file mode 100644
index 000000000000..0b8964844895
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_query_nand.h
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         NAND Memory Query Interface</b>
+ *
+ * @b Description: Defines the ODM query interface for NVIDIA NAND memory adaptation.
+ *
+ */
+#ifndef INCLUDED_NVODM_QUERY_NAND_H
+#define INCLUDED_NVODM_QUERY_NAND_H
+
+#include "nvcommon.h"
+#include "nvodm_modules.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/**
+ * @defgroup nvodm_query_Nand NAND Memory Query Interface
+ * This is the ODM query interface for NAND configurations.
+ * @ingroup nvodm_query
+ * @{
+ */
+
+#define FLASH_TYPE_SHIFT 16
+#define DEVICE_SHIFT 8
+#define FOURTH_ID_SHIFT 24
+/**
+ *  Defines the list of various capabilities of the NAND devices.
+ */
+typedef enum
+{
+    /// Specifies detected NAND device has only one plane; interleave not
+    /// supported.
+    SINGLE_PLANE,
+    /// Specifies detected NAND device has only one plane; but interleave is
+    /// supported for page programming.
+    SINGLE_PLANE_INTERLEAVE,
+    /// Specifies all types of multiplane capabilities should be declared after
+    /// this.
+    MULTI_PLANE,
+    /// Specifies detected NAND device has multiple planes, and each plane is
+    /// formed with alternate blocks from each bank.
+    MULTIPLANE_ALT_BLOCK,
+    /// Specifies detected NAND device has multiple planes, and each plane is
+    /// formed with sequential blocks from each bank.
+    MULTIPLANE_ALT_PLANE,
+    /// Specifies detected NAND device has multiple planes, and each plane is
+    /// formed with alternate blocks from each bank. Interleaving operation is
+    /// supported across the banks.
+    MULTIPLANE_ALT_BLOCK_INTERLEAVE,
+    /// Specifies detected NAND device has multiple planes, and each plane is
+    /// formed with sequential blocks from each bank. Interleaving operation is
+    /// supported across the banks.
+    MULTIPLANE_ALT_PLANE_INTERLEAVE
+}NvOdmNandInterleaveCapability;
+
+/**
+ * Specifies the NAND Flash type.
+ */
+typedef enum
+{
+    /// Specifies NAND flash type is not known.
+    NvOdmNandFlashType_UnKnown,
+    /// Specifies SLC NAND flash type.
+    NvOdmNandFlashType_Slc,
+    /// Specifies MLC NAND flash type.
+    NvOdmNandFlashType_Mlc,
+    /// Ignore. Forces compilers to make 32-bit enums.
+    NvOdmNandFlashType_Force32 = 0x7FFFFFFF
+}NvOdmNandFlashType;
+
+/// Defines the type of algorithm for error-correcting code (ECC).
+typedef enum
+{
+    /// Specifies Hamming ECC.
+    NvOdmNandECCAlgorithm_Hamming = 0,
+    /// Specifies Reed-Solomon ECC.
+    NvOdmNandECCAlgorithm_ReedSolomon,
+    /// Specifies BCH ECC.
+    NvOdmNandECCAlgorithm_BCH,
+    /// Specifies to disable ECC, if the the NAND flash part being used
+    /// has error correction capability within itself.
+    NvOdmNandECCAlgorithm_NoEcc,
+    /// Ignore. Forces compilers to make 32-bit enums.
+    NvOdmNandECCAlgorithm_Force32 = 0x7FFFFFFF
+}NvOdmNandECCAlgorithm;
+
+/// Defines the number of skip spare bytes.
+typedef enum
+{
+    NvOdmNandSkipSpareBytes_0,
+    NvOdmNandSkipSpareBytes_4,
+    NvOdmNandSkipSpareBytes_8,
+    NvOdmNandSkipSpareBytes_12,
+    NvOdmNandSkipSpareBytes_16,
+    NvOdmNandSkipSpareBytes_Force32 = 0x7FFFFFFF
+}NvOdmNandSkipSpareBytes;
+
+/**
+ * Defines the number of symbol errors correctable per each 512 continous
+ * bytes of the flash area when Reed-Solomon algorithm is chosen for error
+ * correction. Here each symbol is of 9 contiguous bits in the flash.
+ *
+ * @note Based on the chosen number of errors correctable, parity bytes
+ * required to be stored in the spare area of NAND flash will vary. For 4
+ * correctable errors the number of parity bytes required are 36 bytes.
+ * Similarly, for 6 and 8 symbol error correction, 56 and 72 parity bytes
+ * must be stored in the spare area. As we also must use the spare area for
+ * bad block management and wear levelling, we need to have 12 bytes for that
+ * in the spare area. So, the spare area size should be able to accommodate
+ * parity bytes and bytes required for bad block management.
+ * Hence fill this parameter based on the spare area size of the flash being
+ * used.
+ */
+typedef enum
+{
+    /// Specifies 4 symbol error correction per 512 byte area of NAND flash.
+    NvOdmNandNumberOfCorrectableSymbolErrors_Four,
+    /// Specifies 6 symbol error correction per 512 byte area of NAND flash.
+    NvOdmNandNumberOfCorrectableSymbolErrors_Six,
+    /// Specifies 8 symbol error correction per 512 byte area of NAND flash.
+    NvOdmNandNumberOfCorrectableSymbolErrors_Eight,
+    /// Ignore. Forces compilers to make 32-bit enums.
+    NvOdmNandNumberOfCorrectableSymbolErrors_Force32 = 0x7FFFFFFF
+}NvOdmNandNumberOfCorrectableSymbolErrors;
+
+/// Defines the NAND flash command set.
+typedef enum
+{
+    /// Specifies to read command 1st cycle.
+    NvOdmNandCommandList_Read = 0x00,
+    /// Specifies to read command start 2nd cycle.
+    NvOdmNandCommandList_Read_Start = 0x30,
+    /// Specifies to read copy back 1st cycle.
+    NvOdmNandCommandList_Read_Cpy_Bck = 0x00,
+    /// Specifies to read copy back start 2nd cycle.
+    NvOdmNandCommandList_Read_Cpy_Bck_Start = 0x35,
+    /// Specifies to cache the read command.
+    NvOdmNandCommandList_Cache_Read = 0x31,
+    /// Specifies the last command to end cache read operation.
+    NvOdmNandCommandList_Cache_ReadEnd = 0x3F,
+    /// Specifies to read device ID.
+    NvOdmNandCommandList_Read_Id = 0x90,
+    /// Specifies to reset the device.
+    NvOdmNandCommandList_Reset = 0xFF,
+    /// Specifies to program/write page 1st cycle.
+    NvOdmNandCommandList_Page_Program = 0x80,
+    /// Specifies to program/write page 2nd cycle.
+    NvOdmNandCommandList_Page_Program_Start = 0x10,
+    /// Specifies to cache program 1st cycle.
+    NvOdmNandCommandList_Cache_Program = 0x80,
+    /// Specifies to cache program 2nd cycle.
+    NvOdmNandCommandList_Cache_Program_Start = 0x15,
+    /// Specifies to erase block.
+    NvOdmNandCommandList_Block_Erase = 0x60,
+    /// Specifies erase block start.
+    NvOdmNandCommandList_Block_Erase_Start = 0xD0,
+    /// Specifies copy back data.
+    NvOdmNandCommandList_Copy_Back = 0x85,
+    /// Specifies random data write.
+    NvOdmNandCommandList_Random_Data_Input = 0x85,
+    /// Specifies random data read.
+    NvOdmNandCommandList_Random_Data_Out = 0x05,
+    /// Specifies random data read start.
+    NvOdmNandCommandList_Random_Data_Out_Start = 0xE0,
+    /// Specifies multi page command.
+    NvOdmNandCommandList_MultiPage = 0x11,
+    NvOdmNandCommandList_MultiPageProgPlane2 = 0x81,
+    /// Specifies read device status.
+    NvOdmNandCommandList_Status = 0x70,
+    /// Specifies read status of chip 1.
+    NvOdmNandCommandList_Status_1 = 0xF1,
+    /// Specifies read status of chip 2.
+    NvOdmNandCommandList_Status_2 = 0xF2,
+    /// Specifies ONFI read ID command.
+    NvOdmNandCommandList_ONFIReadId = 0xEC,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmNandCommandList_Force32 = 0x7FFFFFFF
+}NvOdmNandCommandList;
+
+/// Defines NAND flash types (42nm NAND or normal NAND).
+typedef enum
+{
+    /// Specifies conventional NAND flash (50nm, 60nm).
+    NvOdmNandDeviceType_Type1,
+    /// Specifies 42nm technology NAND flash.
+    NvOdmNandDeviceType_Type2,
+    NvOdmNandDeviceType_Force32 = 0x7FFFFFFF
+}NvOdmNandDeviceType;
+
+/**
+ * This structure holds various NAND flash parameters.
+ */
+typedef struct NvOdmNandFlashParamsRec
+{
+    /// Holds the vendor ID code.
+    NvU8 VendorId;
+    /// Holds the device ID code.
+    NvU8 DeviceId;
+    /// Holds the device type.
+    NvOdmNandFlashType NandType;
+    /// Holds the information whether the used NAND flash supports internal
+    /// copy back command.
+    NvBool IsCopyBackCommandSupported;
+    /// Holds the information whether the used NAND flash supports cache
+    /// write operations.
+    NvBool IsCacheWriteSupported;
+    /// Holds the size of the flash (in megabytes).
+    NvU32 CapacityInMB;
+    /// Holds the Zones per flash device--minimum value possible is 1.
+    /// Zone is a group of contiguous blocks among which internal copy back can
+    /// be performed, if the chip supports copy-back operation.
+    /// Zone is also referred as plane or district by some flashes.
+    NvU32 ZonesPerDevice;
+    /// Holds the blocks per Zone of the flash.
+    NvU32 BlocksPerZone;
+    /// Holds the expected flash response for READ STATUS command
+    /// when requested previous operation is successful.
+    NvU32 OperationSuccessStatus;
+    /// Holds the interleave mechanism supported by the flash.
+    NvOdmNandInterleaveCapability InterleaveCapability;
+    /// Holds the ECC algorithm to be used for error correction.
+    NvOdmNandECCAlgorithm EccAlgorithm;
+    /// Holds the number of errors that can be corrected per 512 byte area of NAND
+    /// flash using Reed-Solomon algorithm.
+    NvOdmNandNumberOfCorrectableSymbolErrors ErrorsCorrectable;
+    /// Holds the number of bytes to be skipped in spare area, starting from
+    /// spare byte 0.
+    NvOdmNandSkipSpareBytes SkippedSpareBytes;
+    /// Flash timing parameters, which are all to be filled in nSec.
+    /// Holds read pulse width in nSec.
+    NvU32 TRP;
+    /// Holds read hold delay in nSec.
+    NvU32 TRH;
+    /// Holds write pulse width in nSec.
+    NvU32 TWP;
+    /// Holds write hold delay in nSec.
+    NvU32 TWH;
+    /// Holds CE# setup time.
+    NvU32 TCS;
+    /// Holds write hold to read delay in nSec.
+    NvU32 TWHR;
+    /// Holds WE to BSY set wait time in nSec.
+    NvU32 TWB;
+    /// Holds read pulse width for PIO read commands.
+    NvU32 TREA;
+    /// Holds time from final rising edge of WE of addrress input to
+    /// first rising edge of WE for data input.
+    NvU32 TADL;
+    /*
+        tCLH, tALH, tCH, tCLS, tALS params are also
+        required to calculate tCS value.
+    */
+    /// Holds CLE setup time.
+    NvU32 TCLS;
+    /// Holds CLE hold time.
+    NvU32 TCLH;
+    /// Holds CE# hold time.
+    NvU32 TCH;
+    /// Holds ALE setup time.
+    NvU32 TALS;
+    /// Holds ALE hold time.
+    NvU32 TALH;
+    /// Holds Read Cycle hold time.
+    NvU32 TRC;
+    /// Holds Write Cycle hold time.
+    NvU32 TWC;
+    /// Holds CLE High to Read Delay Some data sheets refer it as TCLR.
+    NvU32 TCR;
+    /// Holds ALE High to Read Delay 
+    NvU32 TAR;
+    /// Holds RBSY High to Read Delay 
+    NvU32 TRR;
+    /// Describes whether the NAND is 42 nm NAND or normal.
+    NvOdmNandDeviceType NandDeviceType;
+
+    /// Holds the 4th ID data of the read ID command (as given by the data sheet)
+    /// here to differentiate between 42 nm and other flashes that have the
+    /// same ManufaturerId, DevId, and Flash type (e.g., K9LBG08U0M & K9LBG08U0D).
+    NvU8 ReadIdFourthByte;
+}NvOdmNandFlashParams;
+
+/**
+ * Gets the NAND flash device information.
+ *
+ * @param ReadID The NAND flash ID value that is read from the flash.
+ * @return NULL if unsuccessful, or the appropriate flash params structure.
+ */
+NvOdmNandFlashParams *NvOdmNandGetFlashInfo (NvU32 ReadID);
+
+/** @}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif  // INCLUDED_NVODM_QUERY_NAND_H
+
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_query_pinmux.h b/arch/arm/mach-tegra/nv/include/nvodm_query_pinmux.h
new file mode 100644
index 000000000000..5365201b8457
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_query_pinmux.h
@@ -0,0 +1,534 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Pin-Mux Query Interface</b>
+ *
+ * @b Description: Defines the ODM query interface for Pin-Mux configurations.
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_PINMUX_H
+#define INCLUDED_NVODM_QUERY_PINMUX_H
+
+/**
+ * @defgroup nvodm_pinmux PinMux Query Interface
+ * This is the ODM query interface for pin mux configurations.
+ * 
+ * Pin-mux configurations are logical definitions. Each I/O module defines
+ * their configurations (simply an enum), which may be found in the ODM 
+ * adaptation headers.
+ * 
+ * Every platform defines a unique set of configuration tables. There exists a
+ * configuration table for each I/O module and each entry in the table
+ * represents the configuration for an I/O module instance.
+ * 
+ * This interface is used to query the pin-mux configuration tables defined by
+ * the ODM, because these configurations are platform-specific.
+ * @ingroup nvodm_query
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvodm_modules.h"
+
+#define NVODM_QUERY_PINMAP_MULTIPLEXED 0x40000000UL
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* --- Pin-mux Configurations (for each controller) --- */
+
+/**
+ * Defines the ATA pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmAtaPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmAtaPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmAtaPinMap;
+
+/**
+ * Defines the external clock (CDEV, CSUS) pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmExternalClockPinMap_Config1 = 1,
+    NvOdmExternalClockPinMap_Config2,
+    NvOdmExternalClockPinMap_Config3,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmExternalClockPinMap_Force32 = 0x7FFFFFFF
+} NvOdmExternalClockPinMap;
+
+/**
+ * Defines the CRT pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmCrtPinMap_Config1 = 1,
+    NvOdmCrtPinMap_Config2,
+    NvOdmCrtPinMap_Config3,
+    NvOdmCrtPinMap_Config4,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NVOdmCrtPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmCrtPinMap;
+
+/**
+ * Defines the DAP pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmDapPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmDapPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmDapPinMap;
+
+/**
+ * Defines the display pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmDisplayPinMap_Config1 = 1,
+    NvOdmDisplayPinMap_Config2,
+    NvOdmDisplayPinMap_Config3,
+    NvOdmDisplayPinMap_Config4,
+    NvOdmDisplayPinMap_Config5,
+    NvOdmDisplayPinMap_Config6,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmDisplayPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmDisplayPinMap;
+
+/**
+ * Defines the blacklight PWM pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmBacklightPwmPinMap_Config1 = 1,
+    NvOdmBacklightPwmPinMap_Config2,
+    NvOdmBacklightPwmPinMap_Config3,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmBacklightPwmPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmBacklightPwmPinMap;
+
+/**
+ * Defines the HDCP pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmHdcpPinMap_Config1 = 1,
+    NvOdmHdcpPinMap_Config2,
+    NvOdmHdcpPinMap_Config3,
+    NvOdmHdcpPinMap_Config4,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmHdcpPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmHdcpPinMap;
+
+/**
+ * Defines the HDCMI pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmHdmiPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmHdmiPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmHdmiPinMap;
+
+/**
+ * Defines the HSI pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmHsiPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmHsiPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmHsiPinMap;
+
+/**
+ * Defines the HSMMC pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmHsmmcPinMap_Config1 = 1,
+    NvOdmHsmmcPinMap_Config2,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmHsmmcPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmHsmmcPinMap;
+
+/**
+ * Defines the OWR pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmOwrPinMap_Config1 = 1,
+    NvOdmOwrPinMap_Config2,
+    NvOdmOwrPinMap_Config3,
+
+    /**
+     * This configuration disables (tristates) OWR pins. This option may be
+     * used to change which pins an attached OWR device is using at runtime.
+     * In some cases, one device might set up OWR, communicate across this bus,
+     * and then set the OWR bus configuration to "multiplexed" so that another
+     * device can opt to use OWR with its own configurations at a later time.
+     */
+    NvOdmOwrPinMap_Multiplexed = NVODM_QUERY_PINMAP_MULTIPLEXED,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmOwrPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmOwrPinMap;
+
+/**
+ * Defines I2C pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmI2cPinMap_Config1 = 1,
+    NvOdmI2cPinMap_Config2,
+    NvOdmI2cPinMap_Config3,
+    NvOdmI2cPinMap_Config4,
+
+    /**
+     * This configuration disables (tristates) I2C pins. This option may be
+     * used to change which pins an attached I2C device is using at runtime.
+     * 
+     * In some cases, one device might set up I2C, communicate across this bus,
+     * and then set the I2C bus configuration to "multiplexed" so that another
+     * device can opt to use I2C with its own configurations at a later time.
+     *
+     * This option is only supported on the I2C_2 controller (AP15, AP16, AP20).
+     */
+    NvOdmI2cPinMap_Multiplexed = NVODM_QUERY_PINMAP_MULTIPLEXED,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmI2cPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmI2cPinMap;
+
+/**
+ * Defines the I2C PMU pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmI2cPmuPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmI2cPmuPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmI2cPmuPinMap;
+
+/**
+ * Defines the PWM pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmPwmPinMap_Config1 = 1,
+    NvOdmPwmPinMap_Config2,
+    NvOdmPwmPinMap_Config3,
+    NvOdmPwmPinMap_Config4,
+    NvOdmPwmPinMap_Config5,
+    NvOdmPwmPinMap_Config6,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmPwmPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmPwmPinMap;
+
+/**
+ * Defines KBD pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmKbdPinMap_Config1 = 1,
+    NvOdmKbdPinMap_Config2,
+    NvOdmKbdPinMap_Config3,
+    NvOdmKbdPinMap_Config4,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmKbdPinMap_Forc32 = 0x7FFFFFFF,
+} NvOdmKbdPinMap;
+
+/**
+ * Defines MIO pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmMioPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmMioPinMap_Forc32 = 0x7FFFFFFF,
+} NvOdmMioPinMap;
+
+/**
+ * Defines NAND pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmNandPinMap_Config1 = 1,
+    NvOdmNandPinMap_Config2,
+    NvOdmNandPinMap_Config3,
+    NvOdmNandPinMap_Config4,
+    NvOdmNandPinMap_Config5,
+    NvOdmNandPinMap_Config6,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmNandPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmNandPinMap;
+
+/**
+ * Defines the SDIO pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmSdioPinMap_Config1 = 1,
+    NvOdmSdioPinMap_Config2,
+    NvOdmSdioPinMap_Config3,
+    NvOdmSdioPinMap_Config4,
+    NvOdmSdioPinMap_Config5,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmSdioPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmSdioPinMap;
+
+/**
+ * Defines the SFLASH pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmSflashPinMap_Config1 = 1,
+    NvOdmSflashPinMap_Config2,
+    NvOdmSflashPinMap_Config3,
+    NvOdmSflashPinMap_Config4,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmSflashPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmSflashPinMap;
+
+/**
+ * Defines the SPDIF pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmSpdifPinMap_Config1 = 1,   /**< Default SPDIF configuration. */
+    NvOdmSpdifPinMap_Config2,
+    NvOdmSpdifPinMap_Config3,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmSpdifPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmSpdifPinMap;
+
+/**
+ * Defines the SPI pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmSpiPinMap_Config1 = 1,
+    NvOdmSpiPinMap_Config2,
+    NvOdmSpiPinMap_Config3,
+    NvOdmSpiPinMap_Config4,
+    NvOdmSpiPinMap_Config5,
+    NvOdmSpiPinMap_Config6,
+
+    /**
+     * This configuration disables (tristates) SPI pins. This option may be
+     * used to change which pins an attached SPI device is using at runtime.
+     * 
+     * In some cases, one device might set up SPI, communicate across this bus,
+     * and then set the SPI bus configuration to "multiplexed" so that another
+     * device can opt to use SPI with its own configurations at a later time.
+     *
+     * This option is only supported on SPI_3 (AP15, AP16).
+     */
+    NvOdmSpiPinMap_Multiplexed = NVODM_QUERY_PINMAP_MULTIPLEXED,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmSpiPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmSpiPinMap;
+
+/**
+ * Defines the TV-out pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmTvoPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmTvoPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmTvoPinMap;
+
+/**
+ * Defines the USB-ULPI pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmUsbPinMap_Config1 = 1,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmUsbPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmUsbPinMap;
+
+
+/**
+ * Defines the TWC pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmTwcPinMap_Config1 = 1,
+    NvOdmTwcPinMap_Config2,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmTwcPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmTwcPinMap;
+
+/**
+ * Defines the UART pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmUartPinMap_Config1 = 1,
+    NvOdmUartPinMap_Config2,
+    NvOdmUartPinMap_Config3,
+    NvOdmUartPinMap_Config4,
+    NvOdmUartPinMap_Config5,
+    NvOdmUartPinMap_Config6,
+    NvOdmUartPinMap_Config7,
+
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmUartPinMap_Force32 = 0x7FFFFFFF,
+} NvOdmUartPinMap;
+
+/**
+ * Defines the video input pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmVideoInputPinMap_Config1 = 1,
+    NvOdmVideoInputPinMap_Config2,
+    /** Ignore -- Forces compilers to make 32-bit enums. */
+    NvOdmVideoInputPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmVideoInputPinMap;
+
+/**
+ * Defines the PCI-Express pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmPciExpressPinMap_Config1 = 1,
+    NvOdmPciExpressPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmPciExpressPinMap;
+
+/**
+ * Defines the SyncNor / OneNAND pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmSyncNorPinMap_Config1 = 1,
+    NvOdmSyncNorPinMap_Config2,
+    NvOdmSyncNorPinMap_Config3,
+    NvOdmSyncNorPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmSyncNorPinMap;
+
+/**
+ * Defines the PTM pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmPtmPinMap_Config1 = 1,
+    NvOdmPtmPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmPtmPinMap;
+
+/**
+ * Defines the one-wire pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmOneWirePinMap_Config1 = 1,
+    NvOdmOneWirePinMap_Config2,
+    NvOdmOneWirePinMap_Config3,
+    NvOdmOneWirePinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmOneWirePinMap;
+
+
+/**
+ * Defines the ULPI pin-mux configurations.
+ */
+typedef enum
+{
+    NvOdmUlpiPinMap_Config1 = 1,
+    NvOdmUlpiPinMap_Force32 = 0x7FFFFFFFUL,
+} NvOdmUlpiPinMap;
+
+/* --- Pin-mux API --- */
+
+/**
+ * Gets the pinmux configuration table for a given module.
+ *
+ * @param IoModule The I/O module to query.
+ * @param pPinMuxConfigTable A const pointer to the module's configuration
+ *  table. Each entry in the table represents the configuration for the I/O
+ *  module instance, where the instance indices start from 0.
+ * @param pCount A pointer to a variable that this function sets to the
+ *  number of entires in the configuration table.
+ */
+void
+NvOdmQueryPinMux(
+    NvOdmIoModule IoModule,
+    const NvU32 **pPinMuxConfigTable,
+    NvU32 *pCount);
+
+/**
+ * Gets the maximum clock speed for a given module as imposed by a board.
+ *
+ * @param IoModule The I/O module to query.
+ * @param pClockSpeedLimits A const pointer to the module's clock speed limit.
+ *  Each entry in the array represents the clock speed limit for the I/O
+ *  module instance, where the instance indices start from 0.
+ * @param pCount A pointer to a variable that this function sets to the
+ *  number of entries in the \a pClockSpeedLimits array.
+ */
+
+void
+NvOdmQueryClockLimits(
+    NvOdmIoModule IoModule,
+    const NvU32 **pClockSpeedLimits,
+    NvU32 *pCount);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif  // INCLUDED_NVODM_QUERY_PINMUX_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_query_pins.h b/arch/arm/mach-tegra/nv/include/nvodm_query_pins.h
new file mode 100644
index 000000000000..6c769213689e
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_query_pins.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Pin Attributes Query Interface</b>
+ *
+ * @b Description: Provides a mechanism for ODMs to specify electrical
+ *                 attributes, such as drive strength, for pins.
+ */
+
+#ifndef INCLUDED_NVODM_QUERY_PINS_H
+#define INCLUDED_NVODM_QUERY_PINS_H
+
+/**
+ * @defgroup nvodm_pins Pin Electrical Attributes Query Interface
+ * This is the ODM query interface for pin electrical attributes.
+ *
+ * Pin attribute settings match the hardware register definitions very
+ * closely, and as such are specified in a chip-specific format.  C-language
+ * pre-processor macros are provided to allow for as much code readability
+ * and maintainability as possible. Because the organization and the
+ * electrical fine-tuning capabilities of the pins may change between
+ * products, ODMs should ensure that they are using the macros that match
+ * the SOC in their product.
+ * @ingroup nvodm_query
+ * @{
+ */
+
+#include "nvcommon.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+/**
+ * Defines the pin attributes record.
+ */
+typedef struct NvOdmPinAttribRec
+{
+    ///  Specifies the configuration register to assign, which should be
+    ///  one of the application processor's NvOdmPinRegister enumerants.
+    NvU32 ConfigRegister;
+
+    ///  Specifies the value to assign to the specified configuration register.
+    ///  Each application processor's header file provides pre-processor
+    ///  macros to assist in defining this value.
+    NvU32 Value;
+} NvOdmPinAttrib;
+
+/**
+ * Gets a list of [configuration register, value] pairs that are applied
+ * to the application processor's pin configuration registers. Any
+ * pin configuration register that is not specified in this list is left at
+ * its current state.
+ *
+ * @param pPinAttributes A returned pointer to an array of constant pin
+ *  configuration attributes, or NULL if no pin configuration registers
+ *  should be programmed.
+ *
+ * @return The number of pin configuration attributes in \a pPinAttributes, or
+ *  0 if none.
+ */
+
+NvU32
+NvOdmQueryPinAttributes(const NvOdmPinAttrib **pPinAttributes);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+#endif
+
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_query_pins_ap15.h b/arch/arm/mach-tegra/nv/include/nvodm_query_pins_ap15.h
new file mode 100644
index 000000000000..e1ebe11741bd
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_query_pins_ap15.h
@@ -0,0 +1,422 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *        Pin configurations for NVIDIA APX 2300, APX 2500, Tegra 600 and Tegra 650 processors</b>
+ * 
+ * @b Description: Defines the names and configurable settings for pin electrical
+ *                 attributes, such as drive strength and slew.
+ */
+
+// This is an auto-generated file.  Do not edit.
+// Regenerate with "genpadconfig.py ap15 drivers/hwinc/ap15/arapb_misc.h"
+
+#ifndef INCLUDED_NVODM_QUERY_PINS_AP15_H
+#define INCLUDED_NVODM_QUERY_PINS_AP15_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * This specifies the list of pin configuration registers supported by
+ * AP15-compatible products.  This should be used to generate the pin
+ * pin-attribute query array.
+ * @see NvOdmQueryPinAttributes.
+ * @ingroup nvodm_pins
+ * @{
+ */
+
+typedef enum
+{
+
+    /// Pin configuration registers for NVIDIA APX 2300 products
+    NvOdmPinRegister_Apx2300_PullUpDown_A = 0x100000A0UL,
+    NvOdmPinRegister_Apx2300_PullUpDown_B = 0x100000A4UL,
+    NvOdmPinRegister_Apx2300_PullUpDown_C = 0x100000A8UL,
+    NvOdmPinRegister_Apx2300_PullUpDown_D = 0x100000ACUL,
+    NvOdmPinRegister_Apx2300_PullUpDown_E = 0x100000B0UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_AOCFG1 = 0x10000868UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_AOCFG2 = 0x1000086CUL,
+    NvOdmPinRegister_Apx2300_PadCtrl_ATCFG1 = 0x10000870UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_ATCFG2 = 0x10000874UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_CDEV1CFG = 0x10000878UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_CDEV2CFG = 0x1000087CUL,
+    NvOdmPinRegister_Apx2300_PadCtrl_CSUSCFG = 0x10000880UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_DAP1CFG = 0x10000884UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_DAP2CFG = 0x10000888UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_DAP3CFG = 0x1000088CUL,
+    NvOdmPinRegister_Apx2300_PadCtrl_DAP4CFG = 0x10000890UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_DBGCFG = 0x10000894UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_LCDCFG1 = 0x10000898UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_LCDCFG2 = 0x1000089CUL,
+    NvOdmPinRegister_Apx2300_PadCtrl_SDIO2CFG = 0x100008A0UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_SDIO3CFG = 0x100008A4UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_SPICFG = 0x100008A8UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_UAACFG = 0x100008ACUL,
+    NvOdmPinRegister_Apx2300_PadCtrl_UABCFG = 0x100008B0UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_UART2CFG = 0x100008B4UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_UART3CFG = 0x100008B8UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_VICFG1 = 0x100008BCUL,
+    NvOdmPinRegister_Apx2300_PadCtrl_VICFG2 = 0x100008C0UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_XM2CFGA = 0x100008C4UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_XM2CFGC = 0x100008C8UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_XM2CFGD = 0x100008CCUL,
+    NvOdmPinRegister_Apx2300_PadCtrl_XM2CLKCFG = 0x100008D0UL,
+    NvOdmPinRegister_Apx2300_PadCtrl_MEMCOMP = 0x100008D4UL,
+
+    /// Pin configuration registers for NVIDIA APX 2500 products
+    NvOdmPinRegister_Apx2500_PullUpDown_A = 0x100000A0UL,
+    NvOdmPinRegister_Apx2500_PullUpDown_B = 0x100000A4UL,
+    NvOdmPinRegister_Apx2500_PullUpDown_C = 0x100000A8UL,
+    NvOdmPinRegister_Apx2500_PullUpDown_D = 0x100000ACUL,
+    NvOdmPinRegister_Apx2500_PullUpDown_E = 0x100000B0UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_AOCFG1 = 0x10000868UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_AOCFG2 = 0x1000086CUL,
+    NvOdmPinRegister_Apx2500_PadCtrl_ATCFG1 = 0x10000870UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_ATCFG2 = 0x10000874UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_CDEV1CFG = 0x10000878UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_CDEV2CFG = 0x1000087CUL,
+    NvOdmPinRegister_Apx2500_PadCtrl_CSUSCFG = 0x10000880UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_DAP1CFG = 0x10000884UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_DAP2CFG = 0x10000888UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_DAP3CFG = 0x1000088CUL,
+    NvOdmPinRegister_Apx2500_PadCtrl_DAP4CFG = 0x10000890UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_DBGCFG = 0x10000894UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_LCDCFG1 = 0x10000898UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_LCDCFG2 = 0x1000089CUL,
+    NvOdmPinRegister_Apx2500_PadCtrl_SDIO2CFG = 0x100008A0UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_SDIO3CFG = 0x100008A4UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_SPICFG = 0x100008A8UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_UAACFG = 0x100008ACUL,
+    NvOdmPinRegister_Apx2500_PadCtrl_UABCFG = 0x100008B0UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_UART2CFG = 0x100008B4UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_UART3CFG = 0x100008B8UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_VICFG1 = 0x100008BCUL,
+    NvOdmPinRegister_Apx2500_PadCtrl_VICFG2 = 0x100008C0UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_XM2CFGA = 0x100008C4UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_XM2CFGC = 0x100008C8UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_XM2CFGD = 0x100008CCUL,
+    NvOdmPinRegister_Apx2500_PadCtrl_XM2CLKCFG = 0x100008D0UL,
+    NvOdmPinRegister_Apx2500_PadCtrl_MEMCOMP = 0x100008D4UL,
+
+    /// Pin configuration registers for NVIDIA Tegra 600 products
+    NvOdmPinRegister_Tegra600_PullUpDown_A = 0x100000A0UL,
+    NvOdmPinRegister_Tegra600_PullUpDown_B = 0x100000A4UL,
+    NvOdmPinRegister_Tegra600_PullUpDown_C = 0x100000A8UL,
+    NvOdmPinRegister_Tegra600_PullUpDown_D = 0x100000ACUL,
+    NvOdmPinRegister_Tegra600_PullUpDown_E = 0x100000B0UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_AOCFG1 = 0x10000868UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_AOCFG2 = 0x1000086CUL,
+    NvOdmPinRegister_Tegra600_PadCtrl_ATCFG1 = 0x10000870UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_ATCFG2 = 0x10000874UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_CDEV1CFG = 0x10000878UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_CDEV2CFG = 0x1000087CUL,
+    NvOdmPinRegister_Tegra600_PadCtrl_CSUSCFG = 0x10000880UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_DAP1CFG = 0x10000884UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_DAP2CFG = 0x10000888UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_DAP3CFG = 0x1000088CUL,
+    NvOdmPinRegister_Tegra600_PadCtrl_DAP4CFG = 0x10000890UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_DBGCFG = 0x10000894UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_LCDCFG1 = 0x10000898UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_LCDCFG2 = 0x1000089CUL,
+    NvOdmPinRegister_Tegra600_PadCtrl_SDIO2CFG = 0x100008A0UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_SDIO3CFG = 0x100008A4UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_SPICFG = 0x100008A8UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_UAACFG = 0x100008ACUL,
+    NvOdmPinRegister_Tegra600_PadCtrl_UABCFG = 0x100008B0UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_UART2CFG = 0x100008B4UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_UART3CFG = 0x100008B8UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_VICFG1 = 0x100008BCUL,
+    NvOdmPinRegister_Tegra600_PadCtrl_VICFG2 = 0x100008C0UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_XM2CFGA = 0x100008C4UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_XM2CFGC = 0x100008C8UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_XM2CFGD = 0x100008CCUL,
+    NvOdmPinRegister_Tegra600_PadCtrl_XM2CLKCFG = 0x100008D0UL,
+    NvOdmPinRegister_Tegra600_PadCtrl_MEMCOMP = 0x100008D4UL,
+
+    /// Pin configuration registers for NVIDIA Tegra 650 products
+    NvOdmPinRegister_Tegra650_PullUpDown_A = 0x100000A0UL,
+    NvOdmPinRegister_Tegra650_PullUpDown_B = 0x100000A4UL,
+    NvOdmPinRegister_Tegra650_PullUpDown_C = 0x100000A8UL,
+    NvOdmPinRegister_Tegra650_PullUpDown_D = 0x100000ACUL,
+    NvOdmPinRegister_Tegra650_PullUpDown_E = 0x100000B0UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_AOCFG1 = 0x10000868UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_AOCFG2 = 0x1000086CUL,
+    NvOdmPinRegister_Tegra650_PadCtrl_ATCFG1 = 0x10000870UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_ATCFG2 = 0x10000874UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_CDEV1CFG = 0x10000878UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_CDEV2CFG = 0x1000087CUL,
+    NvOdmPinRegister_Tegra650_PadCtrl_CSUSCFG = 0x10000880UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_DAP1CFG = 0x10000884UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_DAP2CFG = 0x10000888UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_DAP3CFG = 0x1000088CUL,
+    NvOdmPinRegister_Tegra650_PadCtrl_DAP4CFG = 0x10000890UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_DBGCFG = 0x10000894UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_LCDCFG1 = 0x10000898UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_LCDCFG2 = 0x1000089CUL,
+    NvOdmPinRegister_Tegra650_PadCtrl_SDIO2CFG = 0x100008A0UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_SDIO3CFG = 0x100008A4UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_SPICFG = 0x100008A8UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_UAACFG = 0x100008ACUL,
+    NvOdmPinRegister_Tegra650_PadCtrl_UABCFG = 0x100008B0UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_UART2CFG = 0x100008B4UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_UART3CFG = 0x100008B8UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_VICFG1 = 0x100008BCUL,
+    NvOdmPinRegister_Tegra650_PadCtrl_VICFG2 = 0x100008C0UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_XM2CFGA = 0x100008C4UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_XM2CFGC = 0x100008C8UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_XM2CFGD = 0x100008CCUL,
+    NvOdmPinRegister_Tegra650_PadCtrl_XM2CLKCFG = 0x100008D0UL,
+    NvOdmPinRegister_Tegra650_PadCtrl_MEMCOMP = 0x100008D4UL,
+
+    NvOdmPinRegister_Force32 = 0x7fffffffUL,
+} NvOdmPinRegister;
+
+/*
+ * C pre-processor macros are provided below to help ODMs specify
+ * pin electrical attributes in a more readable and maintainable fashion
+ * than hardcoding hexadecimal numbers directly.  Please refer to the
+ * Electrical, Thermal and Mechanical data sheet for your product for more
+ * detailed information regarding the effects these values have
+ */
+
+/**
+ * Use this macro to program the PullUpDown_A register.
+ *
+ * @param ATA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP1 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP2 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP3 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP4 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTF : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GPV : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP15_PULLUPDOWN_A(ATA, ATB, ATC, ATD, ATE, DAP1, DAP2, DAP3, DAP4, DTA, DTB, DTC, DTD, DTE, DTF, GPV) \
+    ((((ATA)&3UL) << 0) | (((ATB)&3UL) << 2) | (((ATC)&3UL) << 4) | \
+     (((ATD)&3UL) << 6) | (((ATE)&3UL) << 8) | (((DAP1)&3UL) << 10) | \
+     (((DAP2)&3UL) << 12) | (((DAP3)&3UL) << 14) | (((DAP4)&3UL) << 16) | \
+     (((DTA)&3UL) << 18) | (((DTB)&3UL) << 20) | (((DTC)&3UL) << 22) | \
+     (((DTD)&3UL) << 24) | (((DTE)&3UL) << 26) | (((DTF)&3UL) << 28) | \
+     (((GPV)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_B register.
+ *
+ * @param RM : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param I2CP : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PTA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GPU7 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPDI : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPDO : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GPU : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXK : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP15_PULLUPDOWN_B(RM, I2CP, PTA, GPU7, KBCA, KBCB, KBCC, KBCD, SPDI, SPDO, GPU, SLXA, SLXB, SLXC, SLXD, SLXK) \
+    ((((RM)&3UL) << 0) | (((I2CP)&3UL) << 2) | (((PTA)&3UL) << 4) | \
+     (((GPU7)&3UL) << 6) | (((KBCA)&3UL) << 8) | (((KBCB)&3UL) << 10) | \
+     (((KBCC)&3UL) << 12) | (((KBCD)&3UL) << 14) | (((SPDI)&3UL) << 16) | \
+     (((SPDO)&3UL) << 18) | (((GPU)&3UL) << 20) | (((SLXA)&3UL) << 22) | \
+     (((SLXB)&3UL) << 24) | (((SLXC)&3UL) << 26) | (((SLXD)&3UL) << 28) | \
+     (((SLXK)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_C register.
+ *
+ * @param CDEV1 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param CDEV2 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPID : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIF : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIG : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIH : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param IRTX : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param IRRX : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param XM2A : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param XM2C : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param XM2D : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param XM2S : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP15_PULLUPDOWN_C(CDEV1, CDEV2, SPIA, SPIB, SPIC, SPID, SPIE, SPIF, SPIG, SPIH, IRTX, IRRX, XM2A, XM2C, XM2D, XM2S) \
+    ((((CDEV1)&3UL) << 0) | (((CDEV2)&3UL) << 2) | (((SPIA)&3UL) << 4) | \
+     (((SPIB)&3UL) << 6) | (((SPIC)&3UL) << 8) | (((SPID)&3UL) << 10) | \
+     (((SPIE)&3UL) << 12) | (((SPIF)&3UL) << 14) | (((SPIG)&3UL) << 16) | \
+     (((SPIH)&3UL) << 18) | (((IRTX)&3UL) << 20) | (((IRRX)&3UL) << 22) | \
+     (((XM2A)&3UL) << 24) | (((XM2C)&3UL) << 26) | (((XM2D)&3UL) << 28) | \
+     (((XM2S)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_D register.
+ *
+ * @param UAA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UAB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UAC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UAD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UCA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UCB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD17_0 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD19_18 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD21_20 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD23_22 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LS : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param CSUS : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SDB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SDC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SDD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP15_PULLUPDOWN_D(UAA, UAB, UAC, UAD, UCA, UCB, LD17_0, LD19_18, LD21_20, LD23_22, LS, LC, CSUS, SDB, SDC, SDD) \
+    ((((UAA)&3UL) << 0) | (((UAB)&3UL) << 2) | (((UAC)&3UL) << 4) | \
+     (((UAD)&3UL) << 6) | (((UCA)&3UL) << 8) | (((UCB)&3UL) << 10) | \
+     (((LD17_0)&3UL) << 12) | (((LD19_18)&3UL) << 14) | (((LD21_20)&3UL) << 16) | \
+     (((LD23_22)&3UL) << 18) | (((LS)&3UL) << 20) | (((LC)&3UL) << 22) | \
+     (((CSUS)&3UL) << 24) | (((SDB)&3UL) << 26) | (((SDC)&3UL) << 28) | \
+     (((SDD)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_E register.
+ *
+ * @param KBCF : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP15_PULLUPDOWN_E(KBCF, KBCE, PMCA, PMCB) \
+    ((((KBCF)&3UL) << 0) | (((KBCE)&3UL) << 2) | (((PMCA)&3UL) << 4) | \
+     (((PMCB)&3UL) << 6))
+
+/**
+ * Use this macro to program the PadCtrl_AOCFG1, PadCtrl_AOCFG2, 
+ * PadCtrl_ATCFG1, PadCtrl_ATCFG2, PadCtrl_CDEV1CFG, PadCtrl_CDEV2CFG, 
+ * PadCtrl_CSUSCFG, PadCtrl_DAP1CFG, PadCtrl_DAP2CFG, PadCtrl_DAP3CFG, 
+ * PadCtrl_DAP4CFG, PadCtrl_DBGCFG, PadCtrl_LCDCFG1, PadCtrl_LCDCFG2, 
+ * PadCtrl_SDIO2CFG, PadCtrl_SDIO3CFG, PadCtrl_SPICFG, PadCtrl_UAACFG, 
+ * PadCtrl_UABCFG, PadCtrl_UART2CFG, PadCtrl_UART3CFG, PadCtrl_VICFG1 and 
+ * PadCtrl_VICFG2 registers.
+ *
+ * @param HSM_EN : Enable high-speed mode (0 = disable).  Valid Range 0 - 1
+ * @param SCHMT_EN : Schmitt trigger enable (0 = disable).  Valid Range 0 - 1
+ * @param LPMD : Low-power current/impedance selection (0 = 400 ohm, 1 = 200 ohm, 2 = 100 ohm, 3 = 50 ohm).  Valid Range 0 - 3
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN_SLWR : Pull-up slew control (0 = max).  Valid Range 0 - 3
+ * @param CAL_DRVUP_SLWF : Pull-down slew control (0 = max).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP15_PADCTRL_AOCFG1(HSM_EN, SCHMT_EN, LPMD, CAL_DRVDN, CAL_DRVUP, CAL_DRVDN_SLWR, CAL_DRVUP_SLWF) \
+    ((((HSM_EN)&1UL) << 2) | (((SCHMT_EN)&1UL) << 3) | (((LPMD)&3UL) << 4) | \
+     (((CAL_DRVDN)&31UL) << 12) | (((CAL_DRVUP)&31UL) << 20) | \
+     (((CAL_DRVDN_SLWR)&3UL) << 28) | (((CAL_DRVUP_SLWF)&3UL) << 30))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CFGA register.
+ *
+ * @param HSM_EN : Enable high-speed mode (0 = disable).  Valid Range 0 - 1
+ * @param LPMD : Low-power current/impedance selection (0 = 400 ohm, 1 = 200 ohm, 2 = 100 ohm, 3 = 50 ohm).  Valid Range 0 - 3
+ * @param VREF_EN : VRef enable.  Valid Range 0 - 1
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN_SLWR : Pull-up slew control (0 = max).  Valid Range 0 - 3
+ * @param CAL_DRVUP_SLWF : Pull-down slew control (0 = max).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP15_PADCTRL_XM2CFGA(HSM_EN, LPMD, VREF_EN, CAL_DRVDN, CAL_DRVUP, CAL_DRVDN_SLWR, CAL_DRVUP_SLWF) \
+    ((((HSM_EN)&1UL) << 2) | (((LPMD)&3UL) << 4) | (((VREF_EN)&1UL) << 6) | \
+     (((CAL_DRVDN)&31UL) << 12) | (((CAL_DRVUP)&31UL) << 20) | \
+     (((CAL_DRVDN_SLWR)&3UL) << 28) | (((CAL_DRVUP_SLWF)&3UL) << 30))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CFGC, PadCtrl_XM2CFGD and 
+ * PadCtrl_XM2CLKCFG registers.
+ *
+ * @param HSM_EN : Enable high-speed mode (0 = disable).  Valid Range 0 - 1
+ * @param SCHMT_EN : Schmitt trigger enable (0 = disable).  Valid Range 0 - 1
+ * @param LPMD : Low-power current/impedance selection (0 = 400 ohm, 1 = 200 ohm, 2 = 100 ohm, 3 = 50 ohm).  Valid Range 0 - 3
+ * @param VREF_EN : VRef enable.  Valid Range 0 - 1
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN_SLWR : Pull-up slew control (0 = max).  Valid Range 0 - 3
+ * @param CAL_DRVUP_SLWF : Pull-down slew control (0 = max).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP15_PADCTRL_XM2CFGC(HSM_EN, SCHMT_EN, LPMD, VREF_EN, CAL_DRVDN, CAL_DRVUP, CAL_DRVDN_SLWR, CAL_DRVUP_SLWF) \
+    ((((HSM_EN)&1UL) << 2) | (((SCHMT_EN)&1UL) << 3) | (((LPMD)&3UL) << 4) | \
+     (((VREF_EN)&1UL) << 6) | (((CAL_DRVDN)&31UL) << 12) | \
+     (((CAL_DRVUP)&31UL) << 20) | (((CAL_DRVDN_SLWR)&3UL) << 28) | \
+     (((CAL_DRVUP_SLWF)&3UL) << 30))
+
+/**
+ * Use this macro to program the PadCtrl_MEMCOMP register.
+ *
+ * @param E_HSM : Enable high-speed mode (0 = disable).  Valid Range 0 - 1
+ * @param COMPPAD_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param COMPPAD_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ */
+
+#define NVODM_QUERY_PIN_AP15_PADCTRL_MEMCOMP(E_HSM, COMPPAD_DRVDN, COMPPAD_DRVUP) \
+    ((((E_HSM)&1UL) << 2) | (((COMPPAD_DRVDN)&31UL) << 12) | \
+     (((COMPPAD_DRVUP)&31UL) << 20))
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+#endif // INCLUDED_NVODM_QUERY_PINS_AP15_H
+
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_query_pins_ap20.h b/arch/arm/mach-tegra/nv/include/nvodm_query_pins_ap20.h
new file mode 100644
index 000000000000..ca8adc014c83
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_query_pins_ap20.h
@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *        Pin configurations for NVIDIA AP20 processors</b>
+ * 
+ * @b Description: Defines the names and configurable settings for pin electrical
+ *                 attributes, such as drive strength and slew.
+ */
+
+// This is an auto-generated file.  Do not edit.
+// Regenerate with "genpadconfig.py ap20 drivers/hwinc/ap20/arapb_misc.h"
+
+#ifndef INCLUDED_NVODM_QUERY_PINS_AP20_H
+#define INCLUDED_NVODM_QUERY_PINS_AP20_H
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/**
+ * This specifies the list of pin configuration registers supported by
+ * AP20-compatible products.  This should be used to generate the pin
+ * pin-attribute query array.
+ * @see NvOdmQueryPinAttributes.
+ * @ingroup nvodm_pins
+ * @{
+ */
+
+typedef enum
+{
+
+    /// Pin configuration registers for NVIDIA AP20 products
+    NvOdmPinRegister_Ap20_PullUpDown_A = 0x200000A0UL,
+    NvOdmPinRegister_Ap20_PullUpDown_B = 0x200000A4UL,
+    NvOdmPinRegister_Ap20_PullUpDown_C = 0x200000A8UL,
+    NvOdmPinRegister_Ap20_PullUpDown_D = 0x200000ACUL,
+    NvOdmPinRegister_Ap20_PullUpDown_E = 0x200000B0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_AOCFG1PADCTRL = 0x20000868UL,
+    NvOdmPinRegister_Ap20_PadCtrl_AOCFG2PADCTRL = 0x2000086CUL,
+    NvOdmPinRegister_Ap20_PadCtrl_ATCFG1PADCTRL = 0x20000870UL,
+    NvOdmPinRegister_Ap20_PadCtrl_ATCFG2PADCTRL = 0x20000874UL,
+    NvOdmPinRegister_Ap20_PadCtrl_CDEV1CFGPADCTRL = 0x20000878UL,
+    NvOdmPinRegister_Ap20_PadCtrl_CDEV2CFGPADCTRL = 0x2000087CUL,
+    NvOdmPinRegister_Ap20_PadCtrl_CSUSCFGPADCTRL = 0x20000880UL,
+    NvOdmPinRegister_Ap20_PadCtrl_DAP1CFGPADCTRL = 0x20000884UL,
+    NvOdmPinRegister_Ap20_PadCtrl_DAP2CFGPADCTRL = 0x20000888UL,
+    NvOdmPinRegister_Ap20_PadCtrl_DAP3CFGPADCTRL = 0x2000088CUL,
+    NvOdmPinRegister_Ap20_PadCtrl_DAP4CFGPADCTRL = 0x20000890UL,
+    NvOdmPinRegister_Ap20_PadCtrl_DBGCFGPADCTRL = 0x20000894UL,
+    NvOdmPinRegister_Ap20_PadCtrl_LCDCFG1PADCTRL = 0x20000898UL,
+    NvOdmPinRegister_Ap20_PadCtrl_LCDCFG2PADCTRL = 0x2000089CUL,
+    NvOdmPinRegister_Ap20_PadCtrl_SDIO2CFGPADCTRL = 0x200008A0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_SDIO3CFGPADCTRL = 0x200008A4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_SPICFGPADCTRL = 0x200008A8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_UAACFGPADCTRL = 0x200008ACUL,
+    NvOdmPinRegister_Ap20_PadCtrl_UABCFGPADCTRL = 0x200008B0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_UART2CFGPADCTRL = 0x200008B4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_UART3CFGPADCTRL = 0x200008B8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_VICFG1PADCTRL = 0x200008BCUL,
+    NvOdmPinRegister_Ap20_PadCtrl_VICFG2PADCTRL = 0x200008C0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CFGAPADCTRL = 0x200008C4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CFGCPADCTRL = 0x200008C8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CFGDPADCTRL = 0x200008CCUL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CLKCFGPADCTRL = 0x200008D0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2COMPPADCTRL = 0x200008D4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2VTTGENPADCTRL = 0x200008D8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_SDIO1CFGPADCTRL = 0x200008E0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CFGCPADCTRL2 = 0x200008E4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_XM2CFGDPADCTRL2 = 0x200008E8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_CRTCFGPADCTRL = 0x200008ECUL,
+    NvOdmPinRegister_Ap20_PadCtrl_DDCCFGPADCTRL = 0x200008F0UL,
+    NvOdmPinRegister_Ap20_PadCtrl_GMACFGPADCTRL = 0x200008F4UL,
+    NvOdmPinRegister_Ap20_PadCtrl_GMBCFGPADCTRL = 0x200008F8UL,
+    NvOdmPinRegister_Ap20_PadCtrl_GMCCFGPADCTRL = 0x200008FCUL,
+    NvOdmPinRegister_Ap20_PadCtrl_GMDCFGPADCTRL = 0x20000900UL,
+    NvOdmPinRegister_Ap20_PadCtrl_GMECFGPADCTRL = 0x20000904UL,
+    NvOdmPinRegister_Ap20_PadCtrl_OWRCFGPADCTRL = 0x20000908UL,
+    NvOdmPinRegister_Ap20_PadCtrl_UADCFGPADCTRL = 0x2000090CUL,
+
+    NvOdmPinRegister_Force32 = 0x7fffffffUL,
+} NvOdmPinRegister;
+
+/*
+ * C pre-processor macros are provided below to help ODMs specify
+ * pin electrical attributes in a more readable and maintainable fashion
+ * than hardcoding hexadecimal numbers directly.  Please refer to the
+ * Electrical, Thermal and Mechanical data sheet for your product for more
+ * detailed information regarding the effects these values have
+ */
+
+/**
+ * Use this macro to program the PullUpDown_A register.
+ *
+ * @param ATA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param ATE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP1 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP2 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP3 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DAP4 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DTF : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GPV : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PULLUPDOWN_A(ATA, ATB, ATC, ATD, ATE, DAP1, DAP2, DAP3, DAP4, DTA, DTB, DTC, DTD, DTE, DTF, GPV) \
+    ((((ATA)&3UL) << 0) | (((ATB)&3UL) << 2) | (((ATC)&3UL) << 4) | \
+     (((ATD)&3UL) << 6) | (((ATE)&3UL) << 8) | (((DAP1)&3UL) << 10) | \
+     (((DAP2)&3UL) << 12) | (((DAP3)&3UL) << 14) | (((DAP4)&3UL) << 16) | \
+     (((DTA)&3UL) << 18) | (((DTB)&3UL) << 20) | (((DTC)&3UL) << 22) | \
+     (((DTD)&3UL) << 24) | (((DTE)&3UL) << 26) | (((DTF)&3UL) << 28) | \
+     (((GPV)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_B register.
+ *
+ * @param RM : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param I2CP : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PTA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GPU7 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPDI : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPDO : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GPU : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param CRTP : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SLXK : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PULLUPDOWN_B(RM, I2CP, PTA, GPU7, KBCA, KBCB, KBCC, KBCD, SPDI, SPDO, GPU, SLXA, CRTP, SLXC, SLXD, SLXK) \
+    ((((RM)&3UL) << 0) | (((I2CP)&3UL) << 2) | (((PTA)&3UL) << 4) | \
+     (((GPU7)&3UL) << 6) | (((KBCA)&3UL) << 8) | (((KBCB)&3UL) << 10) | \
+     (((KBCC)&3UL) << 12) | (((KBCD)&3UL) << 14) | (((SPDI)&3UL) << 16) | \
+     (((SPDO)&3UL) << 18) | (((GPU)&3UL) << 20) | (((SLXA)&3UL) << 22) | \
+     (((CRTP)&3UL) << 24) | (((SLXC)&3UL) << 26) | (((SLXD)&3UL) << 28) | \
+     (((SLXK)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_C register.
+ *
+ * @param CDEV1 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param CDEV2 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPID : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIF : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIG : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SPIH : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param IRTX : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param IRRX : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GME : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param XM2D : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param XM2C : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PULLUPDOWN_C(CDEV1, CDEV2, SPIA, SPIB, SPIC, SPID, SPIE, SPIF, SPIG, SPIH, IRTX, IRRX, GME, XM2D, XM2C) \
+    ((((CDEV1)&3UL) << 0) | (((CDEV2)&3UL) << 2) | (((SPIA)&3UL) << 4) | \
+     (((SPIB)&3UL) << 6) | (((SPIC)&3UL) << 8) | (((SPID)&3UL) << 10) | \
+     (((SPIE)&3UL) << 12) | (((SPIF)&3UL) << 14) | (((SPIG)&3UL) << 16) | \
+     (((SPIH)&3UL) << 18) | (((IRTX)&3UL) << 20) | (((IRRX)&3UL) << 22) | \
+     (((GME)&3UL) << 24) | (((XM2D)&3UL) << 28) | (((XM2C)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_D register.
+ *
+ * @param UAA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UAB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UAC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UAD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UCA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UCB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD17_0 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD19_18 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD21_20 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LD23_22 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LS : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param LC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param CSUS : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DDRC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SDC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SDD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PULLUPDOWN_D(UAA, UAB, UAC, UAD, UCA, UCB, LD17_0, LD19_18, LD21_20, LD23_22, LS, LC, CSUS, DDRC, SDC, SDD) \
+    ((((UAA)&3UL) << 0) | (((UAB)&3UL) << 2) | (((UAC)&3UL) << 4) | \
+     (((UAD)&3UL) << 6) | (((UCA)&3UL) << 8) | (((UCB)&3UL) << 10) | \
+     (((LD17_0)&3UL) << 12) | (((LD19_18)&3UL) << 14) | (((LD21_20)&3UL) << 16) | \
+     (((LD23_22)&3UL) << 18) | (((LS)&3UL) << 20) | (((LC)&3UL) << 22) | \
+     (((CSUS)&3UL) << 24) | (((DDRC)&3UL) << 26) | (((SDC)&3UL) << 28) | \
+     (((SDD)&3UL) << 30))
+
+/**
+ * Use this macro to program the PullUpDown_E register.
+ *
+ * @param KBCF : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param KBCE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param PMCE : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param CK32 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param UDA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param SDIO1 : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GMA : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GMB : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GMC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param GMD : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param DDC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ * @param OWC : Configure internal pull-up/down (0 = normal, 1 = pull-down, 2 = pull-up).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PULLUPDOWN_E(KBCF, KBCE, PMCA, PMCB, PMCC, PMCD, PMCE, CK32, UDA, SDIO1, GMA, GMB, GMC, GMD, DDC, OWC) \
+    ((((KBCF)&3UL) << 0) | (((KBCE)&3UL) << 2) | (((PMCA)&3UL) << 4) | \
+     (((PMCB)&3UL) << 6) | (((PMCC)&3UL) << 8) | (((PMCD)&3UL) << 10) | \
+     (((PMCE)&3UL) << 12) | (((CK32)&3UL) << 14) | (((UDA)&3UL) << 16) | \
+     (((SDIO1)&3UL) << 18) | (((GMA)&3UL) << 20) | (((GMB)&3UL) << 22) | \
+     (((GMC)&3UL) << 24) | (((GMD)&3UL) << 26) | (((DDC)&3UL) << 28) | \
+     (((OWC)&3UL) << 30))
+
+/**
+ * Use this macro to program the PadCtrl_AOCFG1PADCTRL, 
+ * PadCtrl_AOCFG2PADCTRL, PadCtrl_ATCFG1PADCTRL, PadCtrl_ATCFG2PADCTRL, 
+ * PadCtrl_CDEV1CFGPADCTRL, PadCtrl_CDEV2CFGPADCTRL, PadCtrl_CSUSCFGPADCTRL, 
+ * PadCtrl_DAP1CFGPADCTRL, PadCtrl_DAP2CFGPADCTRL, PadCtrl_DAP3CFGPADCTRL, 
+ * PadCtrl_DAP4CFGPADCTRL, PadCtrl_DBGCFGPADCTRL, PadCtrl_LCDCFG1PADCTRL, 
+ * PadCtrl_LCDCFG2PADCTRL, PadCtrl_SDIO2CFGPADCTRL, PadCtrl_SDIO3CFGPADCTRL, 
+ * PadCtrl_SPICFGPADCTRL, PadCtrl_UAACFGPADCTRL, PadCtrl_UABCFGPADCTRL, 
+ * PadCtrl_UART2CFGPADCTRL, PadCtrl_UART3CFGPADCTRL, PadCtrl_VICFG1PADCTRL, 
+ * PadCtrl_VICFG2PADCTRL, PadCtrl_SDIO1CFGPADCTRL, PadCtrl_CRTCFGPADCTRL, 
+ * PadCtrl_DDCCFGPADCTRL, PadCtrl_GMACFGPADCTRL, PadCtrl_GMBCFGPADCTRL, 
+ * PadCtrl_GMCCFGPADCTRL, PadCtrl_GMDCFGPADCTRL, PadCtrl_GMECFGPADCTRL, 
+ * PadCtrl_OWRCFGPADCTRL and PadCtrl_UADCFGPADCTRL registers.
+ *
+ * @param HSM_EN : Enable high-speed mode (0 = disable).  Valid Range 0 - 1
+ * @param SCHMT_EN : Schmitt trigger enable (0 = disable).  Valid Range 0 - 1
+ * @param LPMD : Low-power current/impedance selection (0 = 400 ohm, 1 = 200 ohm, 2 = 100 ohm, 3 = 50 ohm).  Valid Range 0 - 3
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN_SLWR : Pull-up slew control (0 = max).  Valid Range 0 - 3
+ * @param CAL_DRVUP_SLWF : Pull-down slew control (0 = max).  Valid Range 0 - 3
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(HSM_EN, SCHMT_EN, LPMD, CAL_DRVDN, CAL_DRVUP, CAL_DRVDN_SLWR, CAL_DRVUP_SLWF) \
+    ((((HSM_EN)&1UL) << 2) | (((SCHMT_EN)&1UL) << 3) | (((LPMD)&3UL) << 4) | \
+     (((CAL_DRVDN)&31UL) << 12) | (((CAL_DRVUP)&31UL) << 20) | \
+     (((CAL_DRVDN_SLWR)&3UL) << 28) | (((CAL_DRVUP_SLWF)&3UL) << 30))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CFGAPADCTRL register.
+ *
+ * @param BYPASS_EN : .  Valid Range 0 - 1
+ * @param PREEMP_EN : .  Valid Range 0 - 1
+ * @param CLK_SEL : .  Valid Range 0 - 1
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN_SLWR : Pull-up slew control (0 = max).  Valid Range 0 - 15
+ * @param CAL_DRVUP_SLWF : Pull-down slew control (0 = max).  Valid Range 0 - 15
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2CFGAPADCTRL(BYPASS_EN, PREEMP_EN, CLK_SEL, CAL_DRVDN, CAL_DRVUP, CAL_DRVDN_SLWR, CAL_DRVUP_SLWF) \
+    ((((BYPASS_EN)&1UL) << 4) | (((PREEMP_EN)&1UL) << 5) | \
+     (((CLK_SEL)&1UL) << 6) | (((CAL_DRVDN)&31UL) << 14) | \
+     (((CAL_DRVUP)&31UL) << 19) | (((CAL_DRVDN_SLWR)&15UL) << 24) | \
+     (((CAL_DRVUP_SLWF)&15UL) << 28))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CFGCPADCTRL and 
+ * PadCtrl_XM2CFGDPADCTRL registers.
+ *
+ * @param SCHMT_EN : Schmitt trigger enable (0 = disable).  Valid Range 0 - 1
+ * @param CAL_DRVDN_TERM : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP_TERM : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN_SLWR : Pull-up slew control (0 = max).  Valid Range 0 - 15
+ * @param CAL_DRVUP_SLWF : Pull-down slew control (0 = max).  Valid Range 0 - 15
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2CFGCPADCTRL(SCHMT_EN, CAL_DRVDN_TERM, CAL_DRVUP_TERM, CAL_DRVDN, CAL_DRVUP, CAL_DRVDN_SLWR, CAL_DRVUP_SLWF) \
+    ((((SCHMT_EN)&1UL) << 3) | (((CAL_DRVDN_TERM)&31UL) << 4) | \
+     (((CAL_DRVUP_TERM)&31UL) << 9) | (((CAL_DRVDN)&31UL) << 14) | \
+     (((CAL_DRVUP)&31UL) << 19) | (((CAL_DRVDN_SLWR)&15UL) << 24) | \
+     (((CAL_DRVUP_SLWF)&15UL) << 28))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CLKCFGPADCTRL register.
+ *
+ * @param BYPASS_EN : .  Valid Range 0 - 1
+ * @param PREEMP_EN : .  Valid Range 0 - 1
+ * @param CAL_BYPASS_EN : .  Valid Range 0 - 1
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ * @param CAL_DRVDN_SLWR : Pull-up slew control (0 = max).  Valid Range 0 - 15
+ * @param CAL_DRVUP_SLWF : Pull-down slew control (0 = max).  Valid Range 0 - 15
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2CLKCFGPADCTRL(BYPASS_EN, PREEMP_EN, CAL_BYPASS_EN, CAL_DRVDN, CAL_DRVUP, CAL_DRVDN_SLWR, CAL_DRVUP_SLWF) \
+    ((((BYPASS_EN)&1UL) << 1) | (((PREEMP_EN)&1UL) << 2) | \
+     (((CAL_BYPASS_EN)&1UL) << 3) | (((CAL_DRVDN)&31UL) << 14) | \
+     (((CAL_DRVUP)&31UL) << 19) | (((CAL_DRVDN_SLWR)&15UL) << 24) | \
+     (((CAL_DRVUP_SLWF)&15UL) << 28))
+
+/**
+ * Use this macro to program the PadCtrl_XM2COMPPADCTRL register.
+ *
+ * @param VREF_SEL : .  Valid Range 0 - 15
+ * @param TESTOUT_EN : .  Valid Range 0 - 1
+ * @param BIAS_SEL : .  Valid Range 0 - 7
+ * @param DRVDN : Pull-down drive strength.  Valid Range 0 - 31
+ * @param DRVUP : Pull-up drive strength.  Valid Range 0 - 31
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2COMPPADCTRL(VREF_SEL, TESTOUT_EN, BIAS_SEL, DRVDN, DRVUP) \
+    ((((VREF_SEL)&15UL) << 0) | (((TESTOUT_EN)&1UL) << 4) | \
+     (((BIAS_SEL)&7UL) << 5) | (((DRVDN)&31UL) << 12) | (((DRVUP)&31UL) << 20))
+
+/**
+ * Use this macro to program the PadCtrl_XM2VTTGENPADCTRL register.
+ *
+ * @param SHORT : .  Valid Range 0 - 1
+ * @param SHORT_PWRGND : .  Valid Range 0 - 1
+ * @param VCLAMP_LEVEL : .  Valid Range 0 - 7
+ * @param VAUXP_LEVEL : .  Valid Range 0 - 7
+ * @param CAL_DRVDN : Pull-down drive strength.  Valid Range 0 - 7
+ * @param CAL_DRVUP : Pull-up drive strength.  Valid Range 0 - 7
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2VTTGENPADCTRL(SHORT, SHORT_PWRGND, VCLAMP_LEVEL, VAUXP_LEVEL, CAL_DRVDN, CAL_DRVUP) \
+    ((((SHORT)&1UL) << 0) | (((SHORT_PWRGND)&1UL) << 1) | \
+     (((VCLAMP_LEVEL)&7UL) << 8) | (((VAUXP_LEVEL)&7UL) << 12) | \
+     (((CAL_DRVDN)&7UL) << 16) | (((CAL_DRVUP)&7UL) << 24))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CFGCPADCTRL2 register.
+ *
+ * @param RX_FT_REC_EN : .  Valid Range 0 - 1
+ * @param BYPASS_EN : .  Valid Range 0 - 1
+ * @param PREEMP_EN : .  Valid Range 0 - 1
+ * @param CTT_HIZ_EN : .  Valid Range 0 - 1
+ * @param VREF_DQS_EN : .  Valid Range 0 - 1
+ * @param VREF_DQ_EN : .  Valid Range 0 - 1
+ * @param CLKSEL_DQ : .  Valid Range 0 - 1
+ * @param CLKSEL_DQS : .  Valid Range 0 - 1
+ * @param VREF_DQS : .  Valid Range 0 - 15
+ * @param VREF_DQ : .  Valid Range 0 - 15
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2CFGCPADCTRL2(RX_FT_REC_EN, BYPASS_EN, PREEMP_EN, CTT_HIZ_EN, VREF_DQS_EN, VREF_DQ_EN, CLKSEL_DQ, CLKSEL_DQS, VREF_DQS, VREF_DQ) \
+    ((((RX_FT_REC_EN)&1UL) << 0) | (((BYPASS_EN)&1UL) << 1) | \
+     (((PREEMP_EN)&1UL) << 2) | (((CTT_HIZ_EN)&1UL) << 3) | \
+     (((VREF_DQS_EN)&1UL) << 4) | (((VREF_DQ_EN)&1UL) << 5) | \
+     (((CLKSEL_DQ)&1UL) << 6) | (((CLKSEL_DQS)&1UL) << 7) | \
+     (((VREF_DQS)&15UL) << 16) | (((VREF_DQ)&15UL) << 24))
+
+/**
+ * Use this macro to program the PadCtrl_XM2CFGDPADCTRL2 register.
+ *
+ * @param RX_FT_REC : .  Valid Range 0 - 1
+ * @param BYPASS : .  Valid Range 0 - 1
+ * @param PREEMP : .  Valid Range 0 - 1
+ * @param CTT_HIZ : .  Valid Range 0 - 1
+ */
+
+#define NVODM_QUERY_PIN_AP20_PADCTRL_XM2CFGDPADCTRL2(RX_FT_REC, BYPASS, PREEMP, CTT_HIZ) \
+    ((((RX_FT_REC)&1UL) << 0) | (((BYPASS)&1UL) << 1) | (((PREEMP)&1UL) << 2) | \
+     (((CTT_HIZ)&1UL) << 3))
+
+#ifdef __cplusplus
+}
+#endif
+
+/** @} */
+#endif // INCLUDED_NVODM_QUERY_PINS_AP20_H
+
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_scrollwheel.h b/arch/arm/mach-tegra/nv/include/nvodm_scrollwheel.h
new file mode 100644
index 000000000000..e5380f26938d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_scrollwheel.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Scroll Wheel Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for scroll wheel devices.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_SCROLLWHEEL_H
+#define INCLUDED_NVODM_SCROLLWHEEL_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+
+/**
+ * @defgroup nvodm_scrollwheel Scroll Wheel Adaptation Interface
+ * 
+ * This is the scroll wheel ODM adaptation interface. 
+ * 
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+/**
+ * Defines an opaque handle that exists for each scroll wheel device in the
+ * system, each of which is defined by the customer implementation.
+ */
+typedef struct NvOdmScrollWheelRec *NvOdmScrollWheelHandle;
+
+/**
+ * Defines the events generated by the scroll wheel.
+ */
+typedef enum
+{
+    /// Indicates no event.
+    NvOdmScrollWheelEvent_None = 0,
+    
+    /// Indicates the scroll up event.
+    NvOdmScrollWheelEvent_RotateClockWise = 0x1,
+    
+    /// Indicates the scroll down event.
+    NvOdmScrollWheelEvent_RotateAntiClockWise = 0x2,
+    
+    /// Indicates the key press event.
+    NvOdmScrollWheelEvent_Press = 0x4,
+    
+    /// Indicates the release event.
+    NvOdmScrollWheelEvent_Release = 0x8,
+
+    /// Indicates the scroll up event.
+    NvOdmScrollWheelEvent_Up = 0x10,
+
+    /// Indicates the scroll down event.
+    NvOdmScrollWheelEvent_Down = 0x20,
+
+    /// Indicates the scroll right event.
+    NvOdmScrollWheelEvent_Right = 0x40,
+
+    /// Indicates the scroll left event.
+    NvOdmScrollWheelEvent_Left = 0x80,
+    
+    NvOdmScrollWheelEvent_Force32 = 0x7FFFFFFF
+} NvOdmScrollWheelEvent;
+
+
+
+/**
+ * Gets a handle to the scroll wheel device.
+ *
+ * @param hSema A handle to the semaphore to be signalled when 
+ * there is an event.
+ * @param KeyEvents Specifies the ORed version of all the events for which
+ * the client wants to register.
+ *
+ * @return A handle to the scroll wheel device.
+ */
+NvOdmScrollWheelHandle 
+NvOdmScrollWheelOpen( 
+    NvOdmOsSemaphoreHandle hSema,
+    NvOdmScrollWheelEvent KeyEvents);
+
+/**
+ * Closes the scroll wheel handle. 
+ *
+ * @param hOdmScrollWheel The scroll wheel handle to be closed.
+ */
+void NvOdmScrollWheelClose(NvOdmScrollWheelHandle hOdmScrollWheel);
+
+
+/**
+ * Gets the pending event information. 
+ *
+ * This API should be called when the semaphore
+ * that the client is waiting on is signalled.
+ *
+ * @param hOdmScrollWheel A handle to the scroll wheel.
+ * @return The type of event. If there are no pending events,
+ * returns the 'none' event. If there are more than one events, 
+ * returns the ORed version of the events.
+ *
+ */
+NvOdmScrollWheelEvent NvOdmScrollWheelGetEvent(NvOdmScrollWheelHandle hOdmScrollWheel);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_SCROLLWHEEL_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_sdio.h b/arch/arm/mach-tegra/nv/include/nvodm_sdio.h
new file mode 100644
index 000000000000..ba30d74712d3
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_sdio.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         SDIO Adaptation Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for SDIO devices.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_SDIO_H
+#define INCLUDED_NVODM_SDIO_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+#include "nverror.h"
+
+/**
+ * @defgroup nvodm_sdio SDIO Adaptation Interface
+ *
+ * This is the SDIO ODM adaptation interface.
+ *
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+ 
+
+/**
+ * Defines an opaque handle that exists for each SDIO device in the
+ * system, each of which is defined by the customer implementation.
+ */
+typedef struct NvOdmSdioRec *NvOdmSdioHandle;
+
+/**
+ * Gets a handle to the SDIO device.
+ *
+ * @return A handle to the SDIO device.
+ */
+NvOdmSdioHandle NvOdmSdioOpen(NvU32 Instance);
+
+/**
+ * Closes the SDIO handle. 
+ *
+ * @param hOdmSdio The SDIO handle to be closed.
+ */
+void NvOdmSdioClose(NvOdmSdioHandle hOdmSdio);
+
+/**
+ * Suspends the SDIO device.
+ * @param hOdmSdio The handle to SDIO device.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmSdioSuspend(NvOdmSdioHandle hOdmSdio);
+
+/**
+ * Resumes the SDIO device from suspend mode.
+ * @param hOdmSdio The handle to SDIO device.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmSdioResume(NvOdmSdioHandle hOdmSdio);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_Sdio_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_services.h b/arch/arm/mach-tegra/nv/include/nvodm_services.h
new file mode 100644
index 000000000000..904821ca8049
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_services.h
@@ -0,0 +1,1694 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         ODM Services API</b>
+ *
+ * @b Description: Defines the abstraction to SOC resources used by
+ *                 external peripherals.
+ */
+
+#ifndef INCLUDED_NVODM_SERVICES_H
+#define INCLUDED_NVODM_SERVICES_H
+
+// Using addtogroup when defgroup resides in another file
+/**
+ * @addtogroup nvodm_services
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvodm_modules.h"
+#include "nvassert.h"
+#include "nvcolor.h"
+#include "nvodm_query_pinmux.h"
+#include "nvodm_query.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/*
+ * This header is split into two sections: OS abstraction APIs and basic I/O
+ * driver APIs.
+ */
+
+/** @name OS Abstraction APIs
+ * The Operating System APIs are portable to any NVIDIA-supported operating
+ * system and will appear in all of the engineering sample code.
+ */
+/*@{*/
+
+/**
+ * Outputs a message to the console, if present. Do not use this for
+ * interacting with a user from an application.
+ *
+ * @param format A pointer to the format string. The format string and variable
+ * parameters exactly follow the posix printf standard.
+ */
+void
+NvOdmOsPrintf( const char *format, ...);
+
+/**
+ * Outputs a message to the debugging console, if present. Do not use this for
+ * interacting with a user from an application.
+ *
+ * @param format A pointer to the format string. The format string and variable
+ * parameters exactly follow the posix printf standard.
+ */
+void
+NvOdmOsDebugPrintf( const char *format, ... );
+
+/**
+ * Dynamically allocates memory. Alignment, if desired, must be done by the
+ * caller.
+ *
+ * @param size The size, in bytes, of the allocation request.
+ */
+void *
+NvOdmOsAlloc(size_t size);
+
+/**
+ * Frees a dynamic memory allocation.
+ *
+ * Freeing a NULL value is supported.
+ *
+ * @param ptr A pointer to the memory to free, which should be from NvOdmOsAlloc().
+ */
+void
+NvOdmOsFree(void *ptr);
+
+typedef struct NvOdmOsMutexRec *NvOdmOsMutexHandle;
+typedef struct NvOdmOsSemaphoreRec *NvOdmOsSemaphoreHandle;
+typedef struct NvOdmOsThreadRec *NvOdmOsThreadHandle;
+
+/**
+ * Copies a specified number of bytes from a source memory location to
+ * a destination memory location.
+ *
+ *  @param dest A pointer to the destination of the copy.
+ *  @param src A pointer to the source memory.
+ *  @param size The length of the copy in bytes.
+ */
+void
+NvOdmOsMemcpy(void *dest, const void *src, size_t size);
+
+/**
+ * Sets a region of memory to a value.
+ *
+ *  @param s A pointer to the memory region.
+ *  @param c The value to set.
+ *  @param size The length of the region in bytes.
+ */
+void
+NvOdmOsMemset(void *s, NvU8 c, size_t size);
+
+/**
+ * Create a new mutex.
+ *
+ * @note Mutexes can be locked recursively; if a thread owns the lock,
+ * it can lock it again as long as it unlocks it an equal number of times.
+ *
+ * @return NULL on failure.
+ */
+NvOdmOsMutexHandle
+NvOdmOsMutexCreate( void );
+
+/**
+ * Locks the given unlocked mutex.
+ *
+ * @note This is a recursive lock.
+ *
+ * @param mutex The mutex to lock.
+ */
+void
+NvOdmOsMutexLock( NvOdmOsMutexHandle mutex );
+
+/**
+ * Unlock a locked mutex.
+ *
+ * A mutex must be unlocked exactly as many times as it has been locked.
+ *
+ * @param mutex The mutex to unlock.
+ */
+void
+NvOdmOsMutexUnlock( NvOdmOsMutexHandle mutex );
+
+/**
+ * Frees the resources held by a mutex.
+ *
+ * @param mutex The mutex to destroy. Passing a NULL mutex is supported.
+ */
+void
+NvOdmOsMutexDestroy( NvOdmOsMutexHandle mutex );
+
+/**
+ * Creates a counting semaphore.
+ *
+ * @param value The initial semaphore value.
+ *
+ * @return NULL on failure.
+ */
+NvOdmOsSemaphoreHandle
+NvOdmOsSemaphoreCreate( NvU32 value );
+
+/**
+ * Waits until the semaphore value becomes non-zero.
+ *
+ * @param semaphore The semaphore for which to wait.
+ */
+void
+NvOdmOsSemaphoreWait( NvOdmOsSemaphoreHandle semaphore );
+
+/**
+ * Waits for the given semaphore value to become non-zero with timeout.
+ *
+ * @param semaphore The semaphore for which to wait.
+ * @param msec The timeout value in milliseconds. Use ::NV_WAIT_INFINITE
+ * to wait forever.
+ *
+ * @return NV_FALSE if the wait expires.
+ */
+NvBool
+NvOdmOsSemaphoreWaitTimeout( NvOdmOsSemaphoreHandle semaphore, NvU32 msec );
+
+/**
+ * Increments the semaphore value.
+ *
+ * @param semaphore The semaphore to signal.
+ */
+void
+NvOdmOsSemaphoreSignal( NvOdmOsSemaphoreHandle semaphore );
+
+/**
+ * Frees resources held by the semaphore.
+ *
+ * @param semaphore The semaphore to destroy. Passing in a NULL semaphore
+ * is supported (no op).
+ */
+void
+NvOdmOsSemaphoreDestroy( NvOdmOsSemaphoreHandle semaphore );
+
+/**
+ * Entry point for a thread.
+ */
+typedef void (*NvOdmOsThreadFunction)(void *args);
+
+/**
+ * Creates a thread.
+ *
+ *  @param function The thread entry point.
+ *  @param args The thread arguments.
+ *
+ * @return The thread handle, or NULL on failure.
+ */
+NvOdmOsThreadHandle
+NvOdmOsThreadCreate(
+    NvOdmOsThreadFunction function,
+    void *args);
+
+/**
+ * Waits for the given thread to exit.
+ *
+ *  The joined thread will be destroyed automatically. All OS resources
+ *  will be reclaimed. There is no method for terminating a thread
+ *  before it exits naturally.
+ *
+ *  Passing in a NULL thread ID is ok (no op).
+ *
+ *  @param thread The thread to wait for.
+ */
+void
+NvOdmOsThreadJoin(NvOdmOsThreadHandle thread);
+
+/**
+ *  Unschedules the calling thread for at least the given
+ *      number of milliseconds.
+ *
+ *  Other threads may run during the sleep time.
+ *
+ *  @param msec The number of milliseconds to sleep. This API should not be
+ *  called from an ISR, can be called from the IST though!
+ */
+void
+NvOdmOsSleepMS(NvU32 msec);
+
+
+/**
+ * Stalls the calling thread for at least the given number of
+ * microseconds. The actual time waited might be longer, so you cannot
+ * depend on this function for precise timing.
+ *
+ * @note It is safe to use this function at ISR time.
+ *
+ * @param usec The number of microseconds to wait.
+ */
+void
+NvOdmOsWaitUS(NvU32 usec);
+
+/**
+ * Gets the system time in milliseconds.
+ * The returned values are guaranteed to be monotonically increasing,
+ * but may wrap back to zero (after about 50 days of runtime).
+ *
+ * @return The system time in milliseconds.
+ */
+NvU32
+NvOdmOsGetTimeMS(void);
+
+/// Defines possible operating system types.
+typedef enum
+{
+    NvOdmOsOs_Unknown,
+    NvOdmOsOs_Windows,
+    NvOdmOsOs_Linux,
+    NvOdmOsOs_Aos,
+    NvOdmOsOs_Force32 = 0x7fffffffUL,
+} NvOdmOsOs;
+
+/// Defines possible operating system SKUs.
+typedef enum
+{
+    NvOdmOsSku_Unknown,
+    NvOdmOsSku_CeBase,
+    NvOdmOsSku_Mobile_SmartFon,
+    NvOdmOsSku_Mobile_PocketPC,
+    NvOdmOsSku_Android,
+    NvOdmOsSku_Force32 = 0x7fffffffUL,
+} NvOdmOsSku;
+
+/// Defines the OS information record.
+typedef struct NvOdmOsOsInfoRec
+{
+    NvOdmOsOs  OsType;
+    NvOdmOsSku Sku;
+    NvU16   MajorVersion;
+    NvU16   MinorVersion;
+    NvU32   SubVersion;
+    NvU32   Caps;
+} NvOdmOsOsInfo;
+
+/**
+ * Gets the current OS version.
+ *
+ * @param pOsInfo A pointer to the OS version.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmOsGetOsInformation( NvOdmOsOsInfo *pOsInfo );
+
+/*@}*/
+/** @name Basic I/O Driver APIs
+ * The basic I/O driver APIs are a set of common input/outputs
+ * that can be used to extend the functionality of the software stack
+ * for new devices that aren't explicity handled by the stack.
+ * GPIO, I2C, and SPI are currently supported.
+*/
+/*@{*/
+
+/**
+ * Defines an opaque handle to the ODM Services GPIO rec interface.
+ */
+typedef struct NvOdmServicesGpioRec *NvOdmServicesGpioHandle;
+/**
+ * Defines an opaque handle to the ODM Services GPIO intr interface.
+ */
+typedef struct NvOdmServicesGpioIntrRec *NvOdmServicesGpioIntrHandle;
+/**
+ * Defines an opaque handle to the ODM Services SPI interface.
+ */
+typedef struct NvOdmServicesSpiRec *NvOdmServicesSpiHandle;
+/**
+ * Defines an opaque handle to the ODM Services I2C interface.
+ */
+typedef struct NvOdmServicesI2cRec *NvOdmServicesI2cHandle;
+/**
+ * Defines an opaque handle to the ODM Services PMU interface.
+ */
+typedef struct NvOdmServicesPmuRec *NvOdmServicesPmuHandle;
+/**
+ * Defines an opaque handle to the ODM Services PWM interface.
+ */
+typedef struct NvOdmServicesPwmRec *NvOdmServicesPwmHandle;
+/**
+ * Defines an opaque handle to the ODM Services key list interface.
+ */
+typedef struct NvOdmServicesKeyList *NvOdmServicesKeyListHandle;
+
+/**
+ * Defines an interrupt handler.
+ */
+typedef void (*NvOdmInterruptHandler)(void *args);
+
+/**
+ * @brief Defines the possible GPIO pin modes.
+ */
+typedef enum
+{
+    /// Specifies that that the pin is tristated, which will consume less power.
+    NvOdmGpioPinMode_Tristate = 1,
+
+    /// Specifies input mode with active low interrupt.
+    NvOdmGpioPinMode_InputInterruptLow,
+
+    /// Specifies input mode with active high interrupt.
+    NvOdmGpioPinMode_InputInterruptHigh,
+
+    /// Specifies input mode with no events.
+    NvOdmGpioPinMode_InputData,
+
+    /// Specifies output mode.
+    NvOdmGpioPinMode_Output,
+
+    /// Specifies special function.
+    NvOdmGpioPinMode_Function,
+
+    /// Specifies input and interrupt on any edge.
+    NvOdmGpioPinMode_InputInterruptAny,
+
+    /// Specifies input and interrupt on rising edge.
+    NvOdmGpioPinMode_InputInterruptRisingEdge,
+
+    /// Specifies output and interrupt on falling edge.
+    NvOdmGpioPinMode_InputInterruptFallingEdge,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmGpioPinMode_Force32 = 0x7fffffff
+
+} NvOdmGpioPinMode;
+
+/**
+ * Defines the opaque handle to the GPIO pin.
+ */
+typedef struct NvOdmGpioPinRec *NvOdmGpioPinHandle;
+
+/**
+ * Creates and opens a GPIO handle. The handle can then be used to
+ * access GPIO functions.
+ *
+ * @see NvOdmGpioClose
+ *
+ * @return The handle to the GPIO controller, or NULL if an error occurred.
+ */
+NvOdmServicesGpioHandle NvOdmGpioOpen(void);
+
+/**
+ * Closes the GPIO handle. Any pin settings made while this handle is
+ * open will remain. All events enabled by this handle are
+ * disabled.
+ *
+ * @see NvOdmGpioOpen
+ *
+ * @param hOdmGpio The GPIO handle.
+ */
+void NvOdmGpioClose(NvOdmServicesGpioHandle hOdmGpio);
+
+/**
+ * Acquires a pin handle to be used in subsequent calls to
+ * access the pin.
+ *
+ * @see NvOdmGpioClose
+ *
+ * @param hOdmGpio The GPIO handle.
+ * @param port The port.
+ * @param Pin The pin for which to return the handle.
+ *
+ * @return The pin handle, or NULL if an error occurred.
+ */
+NvOdmGpioPinHandle
+NvOdmGpioAcquirePinHandle(NvOdmServicesGpioHandle hOdmGpio,
+        NvU32 port, NvU32 Pin);
+
+/**
+ * Releases the pin handle that was acquired by NvOdmGpioAcquirePinHandle()
+ * and used by the rest of the GPIO ODM APIs.
+ *
+ * @see NvOdmGpioAcquirePinHandle
+ *
+ * @param hOdmGpio The GPIO handle.
+ * @param hPin The pin handle to release.
+ */
+void
+NvOdmGpioReleasePinHandle(NvOdmServicesGpioHandle hOdmGpio,
+        NvOdmGpioPinHandle hPin);
+/**
+ * Sets the output state of a set of GPIO pins.
+ *
+ * @see NvOdmGpioOpen, NvOdmGpioGetState
+ *
+ * @param hOdmGpio The GPIO handle.
+ * @param hGpioPin The pin handle.
+ * @param PinValue The pin state to set. 0 means drive low, 1 means drive high.
+ */
+void
+NvOdmGpioSetState(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmGpioPinHandle hGpioPin,
+    NvU32 PinValue);
+
+/**
+ * Gets the output state of a specified set of GPIO pins in the port.
+ *
+ * @see NvOdmGpioOpen, NvOdmGpioSetState
+ *
+ * @param hOdmGpio The GPIO handle.
+ * @param hGpioPin The pin handle.
+ * @param pPinStateValue A pointer to the returned current state of the pin.
+ */
+void
+NvOdmGpioGetState(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmGpioPinHandle hGpioPin,
+    NvU32 *pPinStateValue);
+
+/**
+ * Configures the GPIO to specific mode. Don't use this API to configure the pin
+ * as interrupt pin, instead use the NvOdmGpioInterruptRegister
+ *  and NvOdmGpioInterruptUnregister APIs which internally call this function.
+ *
+ * @param hOdmGpio  The GPIO handle.
+ * @param hGpioPin  The pin handle.
+ * @param Mode      The mode type to configure.
+ */
+void
+NvOdmGpioConfig(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmGpioPinHandle hGpioPin,
+    NvOdmGpioPinMode Mode);
+
+/**
+ * Registers an interrupt callback function and the mode of interrupt for the
+ * GPIO pin specified.
+ *
+ * Callback uses the interrupt thread and the interrupt stack on Linux
+ * and IST on Windows CE; so, care should be taken on all the APIs used in
+ * the callback function.
+ *
+ * Interrupts are masked when they are triggered. It is up to the caller to
+ * re-enable the interrupts by calling NvOdmGpioInterruptDone().
+ *  
+ * @param hOdmGpio  The GPIO handle.
+ * @param hGpioIntr A pointer to the GPIO interrupt handle. Use this 
+ *  handle while unregistering the interrupt. On failure to hook
+ *  up the interrupt, a NULL handle is returned.
+ * @param hGpioPin  The pin handle.
+ * @param Mode      The mode type to configure. Allowed mode values are:
+ *  - NvOdmGpioPinMode_InputInterruptFallingEdge
+ *  - NvOdmGpioPinMode_InputInterruptRisingEdge
+ *  - NvOdmGpioPinMode_InputInterruptAny
+ *  - NvOdmGpioPinMode_InputInterruptLow
+ *  - NvOdmGpioPinMode_InputInterruptHigh
+ *  
+ * @param Callback The callback function that is called when 
+ *  the interrupt triggers.
+ * @param arg The argument used when the callback is called by the ISR. 
+ * @param DebounceTime The debounce time in milliseconds.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmGpioInterruptRegister(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmServicesGpioIntrHandle *hGpioIntr,
+    NvOdmGpioPinHandle hGpioPin,
+    NvOdmGpioPinMode Mode,
+    NvOdmInterruptHandler Callback,
+    void *arg,
+    NvU32 DebounceTime);
+
+/**
+ *  Client of GPIO interrupt to re-enable the interrupt after
+ *  the handling the interrupt.
+ *
+ *  @param handle GPIO interrupt handle returned by a sucessfull call to
+ *  NvOdmGpioInterruptRegister().
+ */
+void NvOdmGpioInterruptDone( NvOdmServicesGpioIntrHandle handle );
+
+/**
+ * Mask/Unmask a gpio interrupt.
+ *
+ * Drivers can use this API to fend off interrupts. Mask means interrupts are
+ * not forwarded to the CPU. Unmask means, interrupts are forwarded to the CPU.
+ * In case of SMP systems, this API masks the interrutps to all the CPU, not
+ * just the calling CPU.
+ *
+ *
+ * @param handle    Interrupt handle returned by NvOdmGpioInterruptRegister API.
+ * @param mask      NV_FALSE to forrward the interrupt to CPU. NV_TRUE to 
+ * mask the interupts to CPU.
+ */
+void
+NvOdmGpioInterruptMask(NvOdmServicesGpioIntrHandle handle, NvBool mask);
+
+/**
+ * Unregisters the GPIO interrupt handler.
+ *
+ * @param hOdmGpio  The GPIO handle.
+ * @param hGpioPin  The pin handle.
+ * @param handle The interrupt handle returned by a successfull call to
+ * NvOdmGpioInterruptRegister().
+ *
+ */
+void
+NvOdmGpioInterruptUnregister(NvOdmServicesGpioHandle hOdmGpio,
+    NvOdmGpioPinHandle hGpioPin,
+    NvOdmServicesGpioIntrHandle handle);
+
+/**
+ * Obtains a handle that can be used to access one of the serial peripheral
+ * interface (SPI) controllers.
+ *
+ * There may be one or more instances of the SPI, depending upon the SOC,
+ * and these instances start from 0.
+ *
+ * @see NvOdmSpiClose
+ *
+ * @param OdmIoModule  The ODM I/O module for the SFLASH, SPI, or SLINK.
+ * @param ControllerId  The SPI controlled ID for which a handle is required.
+ *     Valid SPI channel IDs start from 0.
+ *
+ *
+ * @return The handle to the SPI controller, or NULL if an error occurred.
+ */
+NvOdmServicesSpiHandle NvOdmSpiOpen(NvOdmIoModule OdmIoModule, NvU32 ControllerId);
+
+/**
+ * Obtains a handle that can be used to access one of the serial peripheral
+ * interface (SPI) controllers, for SPI controllers which are multiplexed
+ * between multiple pin mux configurations. The SPI controller's pin mux
+ * will be reset to the specified value every transaction, so that two handles
+ * to the same controller may safely interleave across pin mux configurations.
+ *
+ * The ODM pin mux query for the specified controller must be
+ * NvOdmSpiPinMap_Multiplexed in order to create a handle using this function.
+ *
+ * There may be one or more instances of the SPI, depending upon the SOC,
+ * and these instances start from 0.
+ *
+ * Currently, this function is only supported for OdmIoModule_Spi, instance 2.
+ *
+ * @see NvOdmSpiClose
+ *
+ * @param OdmIoModule  The ODM I/O module for the SFLASH, SPI, or SLINK.
+ * @param ControllerId  The SPI controlled ID for which a handle is required.
+ *     Valid SPI channel IDs start from 0.
+ * @param PinMap The pin mux configuration to use for every transaction.
+ *
+ * @return The handle to the SPI controller, or NULL if an error occurred.
+ */
+NvOdmServicesSpiHandle 
+NvOdmSpiPinMuxOpen(NvOdmIoModule OdmIoModule,
+                   NvU32 ControllerId,
+                   NvOdmSpiPinMap PinMap);
+
+
+/**
+ * Obtains a handle that can be used to access one of the serial peripheral
+ * interface (SPI) controllers in slave mode.
+ *
+ * There may be one or more instances of the SPI, depending upon the SOC,
+ * and these instances start from 0.
+ *
+ * @see NvOdmSpiClose
+ *
+ * @param OdmIoModule  The ODM I/O module for the SFLASH, SPI, or SLINK.
+ * @param ControllerId  The SPI controlled ID for which a handle is required.
+ *     Valid SPI channel IDs start from 0.
+ *
+ *
+ * @return The handle to the SPI controller, or NULL if an error occurred.
+ */
+NvOdmServicesSpiHandle NvOdmSpiSlaveOpen(NvOdmIoModule OdmIoModule, NvU32 ControllerId);
+
+
+/**
+ * Releases a handle to an SPI controller. This API must be called once per
+ * successful call to NvOdmSpiOpen().
+ *
+ * @param hOdmSpi A SPI handle allocated in a call to \c NvOdmSpiOpen.  If \em hOdmSpi
+ *     is NULL, this API has no effect.
+ */
+void NvOdmSpiClose(NvOdmServicesSpiHandle hOdmSpi);
+
+/**
+ * Performs an SPI controller transaction. Every SPI transaction is by
+ * definition a simultaneous read and write transaction, so there are no
+ * separate APIs for read versus write. However, if you only need to do a read or
+ * write, this API allows you to declare that you are not interested in the read
+ * data, or that the write data is not of interest.
+ *
+ * This is a blocking API. When it returns, all of the data has been sent out
+ * over the pins of the SOC (the transaction). This is true even if the read data
+ * is being discarded, as it cannot merely have been queued up.
+ *
+ * Several SPI transactions may be performed in a single call to this API, but
+ * only if all of the transactions are to the same chip select and have the same
+ * packet size.
+ *
+ * Transaction sizes from 1 bit to 32 bits are supported. However, all
+ * of the buffers in memory are byte-aligned. To perform one transaction,
+ * the \em Size argument should be:
+ *
+ * <tt> <!-- typewriter font formats this nicely in the output document -->
+ *   (PacketSize + 7)/8
+ * </tt>
+ *
+ * To perform n transactions, \em Size should be:
+ *
+ * <tt>
+ *   n*((PacketSize + 7)/8)
+ * </tt>
+ *
+ * Within a given
+ * transaction with the packet size larger than 8 bits, the bytes are stored in 
+ * order of the MSB (most significant byte) first.
+ * The Packet is formed with the first Byte will be in MSB and then next byte 
+ * will be in the  next MSB towards the LSB.
+ *
+ * For the example, if One packet need to be send and its size is the 20 bit 
+ * then it will require the 3 bytes in the pWriteBuffer and arrangement of the 
+ * data  are as follows:
+ * The packet is 0x000ABCDE (Packet with length of 20 bit).
+ * pWriteBuff[0] = 0x0A
+ * pWriteBuff[1] = 0xBC
+ * pWtriteBuff[2] = 0xDE
+ *
+ * The most significant bit will be transmitted first i.e. bit20 is transmitted 
+ * first and bit 0 will be transmitted last.
+ *
+ * If the transmitted packet (command + receive data) is more than 32 like 33 and 
+ * want to transfer in the single call (CS should be active) then it can be transmitted
+ * in following way:
+ * The transfer is command(8 bit)+Dummy(1bit)+Read (24 bit) = 33 bit of transfer.
+ * - Send 33 bit as 33 byte and each byte have the 1 valid bit, So packet bit length = 1 and
+ * bytes requested = 33.
+ * NvU8 pSendData[33], pRecData[33];
+ *  pSendData[0] = (Comamnd >>7) & 0x1;
+ *  pSendData[1] = (Command >> 6)& 0x1; 
+ * ::::::::::::::
+ * pSendData[8] = DummyBit;
+ * pSendData[9] to pSendData[32] = 0;
+ * Call NvOdmSpiTransaction(hRmSpi,ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 33,1);
+ * Now You will get the read data from pRecData[9] to pRecData[32] on bit 0 on each byte.
+ *
+ * - The 33 bit transfer can be also done as 11 byte and each byte have the 3 valid bits.
+ * This need to rearrange the command in the pSendData in such a way that each byte have the
+ * 3 valid bits.
+ * NvU8 pSendData[11], pRecData[11];
+ *  pSendData[0] = (Comamnd >>4) & 0x7;
+ *  pSendData[1] = (Command >> 1)& 0x7; 
+ *  pSendData[2] = (((Command)& 0x3) <<1) | DummyBit; 
+ * pSendData[3] to pSendData[10] = 0;
+ * 
+ * Call NvOdmSpiTransaction(hRmSpi, ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 11,3);
+ * Now You will get the read data from pRecData[4] to pRecData[10] on lower 3 bits on each byte.
+ *
+ * Similarly the 33 bit transfer can also be done as 6 byte and each 2 bytes contain the 11 valid bits.
+ * Call NvOdmSpiTransaction(hRmSpi, ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 6,11);
+ *
+ *
+ * \em ReadBuf and \em WriteBuf may be the same pointer, in which case the write
+ * data is destroyed as we read in the read data. Unless they are identical pointers,
+ * however, \em ReadBuf and \em WriteBuf must not overlap.
+ *
+ * @param hOdmSpi The SPI handle allocated in a call to NvOdmSpiOpen().
+ * @param ChipSelect Select with which of the several external devices (attached
+ *     to a single controller) we are communicating. Chip select indices
+ *     start at 0.
+ * @param ClockSpeedInKHz The speed in kHz on which the device can communicate.
+ * @param ReadBuf A pointer to buffer to be filled in with read data. If this
+ *     pointer is NULL, the read data will be discarded.
+ * @param WriteBuf A pointer to a buffer from which to obtain write data. If this
+ *     pointer is NULL, the write data will be all zeros.
+ * @param Size The size of \em ReadBuf and \em WriteBuf buffers in bytes.
+ * @param PacketSize The packet size in bits of each SPI transaction.
+ */
+void
+NvOdmSpiTransaction(
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU32 ChipSelect,
+    NvU32 ClockSpeedInKHz,
+    NvU8 *ReadBuf,
+    const NvU8 *WriteBuf,
+    NvU32 Size,
+    NvU32 PacketSize);
+
+
+/**
+ * Starts an SPI controller read and write simultaneously in the slave mode.
+ *
+ * This is a nonblocking API, which starts the data transfer and returns
+ * to the caller without waiting for the data transfer completion. 
+ *
+ * @note This API is only supported for the SPI handle, which is opened in
+ * slave mode using NvOdmSpiSlaveOpen(). This API asserts if the opened SPI
+ * handle is the master type.
+ *
+ * @see NvOdmSpiSlaveGetTransactionData
+ *
+ * @par Read or Write Transactions
+ *
+ * Every SPI transaction is by definition a simultaneous read and write 
+ * transaction, so there are no separate APIs for read versus write. 
+ * However, if you only need to start a read or write transaction, this API 
+ * allows you to declare that you are not interested in the read data, 
+ * or that the write data is not of interest. If only read
+ * is required to start, then the client can pass NV_TRUE to the \a IsReadTransfer
+ * parameter and a NULL pointer to \a pWriteBuffer. The state of the data out 
+ * will be set by NvOdmQuerySpiIdleSignalState::IsIdleDataOutHigh  
+ * in nvodm_query.h. Similarly, if the client wants to send data only
+ * then it can pass NV_FALSE to the \a IsReadTransfer parameter.
+ *
+ * @par Transaction Sizes
+ *
+ * Transaction sizes from 1 to 32 bits are supported. However, all of the 
+ * packets are byte-aligned in memory. So, if \a packetBitLength is 12 bits 
+ * then the client needs the 2nd byte for the 1 packet. New packets start from the
+ * new bytes, e.g., byte0 and byte1 contain the first packet and byte2 and byte3
+ * will contain the second packets.
+ *
+ * To perform one transaction, the \a BytesRequested argument should be:
+ * <pre>
+ *   (PacketSizeInBits + 7)/8
+ * </pre>
+ *
+ * To perform \a n transactions, \a BytesRequested should be:
+ * <pre>
+ *   n*((PacketSizeInBits + 7)/8)
+ * </pre>
+ *
+ * Within a given transaction with the packet size larger than 8 bits,
+ * the bytes are stored in the order of the LSB (least significant byte) first.
+ * The packet is formed with the first byte will be in LSB and then next byte 
+ * will be in the next LSB towards the MSB.
+ *  
+ * For example, if one packet needs to be sent and its size is 20 bits, 
+ * then it will require the 3 bytes in the \a pWriteBuffer and arrangement of
+ * the data  are as follows:
+ * - The packet is 0x000ABCDE (Packet with length of 20 bit).
+ * - pWriteBuff[0] = 0xDE
+ * - pWriteBuff[1] = 0xBC
+ * - pWtriteBuff[2] = 0x0A
+ *
+ * The most significant bit will be transmitted first, i.e., bit20 is transmitted 
+ * first and bit0 will be transmitted last.
+ *
+ * @par Transfer Size Limitations
+ *
+ * The limitation on the maximum transfer size of SPI slave communication
+ * depends upon the hardware. The maximum size of byte transfer is 64 K bytes
+ * if the number of packets requested is a multiple of: 
+ * - 4 for 8-bit packet length, or 
+ * - 2 for 16-bit packet length, or 
+ * - any number of packets for 32-bit packet length. 
+ *
+ * For all other cases, the maximum transfer bytes size is limited to 16 K
+ * packets, that is:
+ * <pre>
+ * 16K*((PacketBitLength +7)/8))
+ * </pre>
+ * 
+ * For the example: 
+ * - Non-multiples of 4 for the 8-bit packet length 
+ * - Non multiples of 2 for the 16-bit packet length 
+ * - Any other bit length except for the 32-bit packet length
+ * 
+ * This limitation comes from the:
+ * - Maximum HW DMA transfer of 64 KB
+ * - Maximum packet transfer for HW S-LINK controller of 64 K packets 
+ * - The design of packed/unpacked format of the S-LINK controller
+ *
+ * @par CAIF Use Case
+ * 
+ * The following describes a typical use case for the CAIF interface. The steps
+ * for doing the transfer are:
+ * -# ACPU calls the NvOdmSpiSlaveStartTransaction() to configure the SPI 
+ * controller to set in the receive or transmit mode and make ready for the 
+ * data transfer.
+ * -# ACPU then send the signal to the CCPU to send the SPICLK (by activating 
+ * the SPI_INT) and start the transaction. CCPU get this signal and start sending 
+ * SPICLK.
+ * -# ACPU will call the NvOdmSpiSlaveGetTransactionData() to get the 
+ * data/information about the transaction.
+ * -# After completion of the transfer ACPU inactivate the SPI_INT.
+ *
+ * @param hOdmSpi The SPI handle allocated in a call to NvOdmSpiSlaveOpen().
+ * @param ChipSelectId The chip select ID on which device is connected.
+ * @param ClockSpeedInKHz The clock speed in kHz on which device can communicate.
+ * @param IsReadTransfer Tells that whether or not the read transfer is required.
+ * If it is NV_TRUE then read transfer is required and the read data will be 
+ * available in the local buffer of the driver. The client will get the received
+ * data after calling the \c NvRmSpiGetTransactionData() function.
+ * @param pWriteBuffer A pointer to a buffer from which to obtain write data. 
+ * If this pointer is NULL, the write data will be all zeros.
+ * @param BytesRequested The size of \a pReadBuffer and \a pWriteBuffer buffers
+ * in bytes.
+ * @param PacketSizeInBits The packet size in bits of each SPI transaction.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+ NvBool NvOdmSpiSlaveStartTransaction( 
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvBool IsReadTransfer,
+    NvU8 * pWriteBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketSizeInBits );
+
+/**
+ * Gets the SPI transaction status that is started for the slave mode and waits,
+ * if required, until the transfer completes for a given timeout error.
+ * If a read transaction has been started, then it returns the receive data to 
+ * the client.
+ *
+ * This is a blocking API and waits for the data transfer completion until the
+ * transfer completes or a timeout happens.
+ *
+ * @see NvOdmSpiSlaveStartTransaction
+ *
+ * @param hOdmSpi The SPI handle allocated in a call to NvOdmSpiSlaveOpen().
+ * @param pReadBuffer A pointer to a buffer to be filled in with read data. If this
+ * pointer is NULL, the read data will be discarded.
+ * @param BytesRequested The size of \a pReadBuffer and \a pWriteBuffer buffers
+ * in bytes.
+ * @param pBytesTransfererd A pointer to the number of bytes transferred.
+ * @param WaitTimeout The timeout in millisecond to wait for the transaction to be 
+ * completed.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ *
+ */
+  NvBool NvOdmSpiSlaveGetTransactionData( 
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU8 * pReadBuffer,
+    NvU32 BytesRequested,
+    NvU32 * pBytesTransfererd,
+    NvU32 WaitTimeout );
+
+/**
+ * Sets the signal mode for the SPI communication for a given chip select.
+ * After calling this API, further communication happens with the newly 
+ * configured signal modes.
+ * The default value of the signal mode is taken from ODM Query, and this
+ * API overrides the signal mode that is read from the query.
+ *
+ * @param hOdmSpi The SPI handle allocated in a call to NvOdmSpiOpen().
+ * @param ChipSelectId The chip select ID to which the device is connected.
+ * @param SpiSignalMode The ODM signal mode to be set.
+ *
+ */
+void
+NvOdmSpiSetSignalMode(
+    NvOdmServicesSpiHandle hOdmSpi,
+    NvU32 ChipSelectId,
+    NvOdmQuerySpiSignalMode SpiSignalMode);
+
+/// Contains the error flags for the I2C transaction.
+typedef enum
+{
+    NvOdmI2cStatus_Success = 0,
+    NvOdmI2cStatus_Timeout,
+    NvOdmI2cStatus_SlaveNotFound,
+    NvOdmI2cStatus_InvalidTransferSize,
+    NvOdmI2cStatus_ReadFailed,
+    NvOdmI2cStatus_WriteFailed,
+    NvOdmI2cStatus_InternalError,
+    NvOdmI2cStatus_ArbitrationFailed,
+    NvOdmI2cStatus_Force32 = 0x7FFFFFFF
+} NvOdmI2cStatus;
+
+/// Flag to indicate the I2C write/read operation.
+#define NVODM_I2C_IS_WRITE            0x00000001
+/// Flag to indicate the I2C slave address type as 10-bit or 7-bit.
+#define NVODM_I2C_IS_10_BIT_ADDRESS   0x00000002
+/// Flag to indicate the I2C transaction with repeat start.
+#define NVODM_I2C_USE_REPEATED_START  0x00000004
+/// Flag to indicate that the I2C slave will not generate ACK.
+#define NVODM_I2C_NO_ACK              0x00000008
+/// Flag to indicate software I2C using GPIO.
+#define NVODM_I2C_SOFTWARE_CONTROLLER 0x00000010
+
+
+/// Contians the I2C transaction details.
+typedef struct
+{
+    /// Flags to indicate the transaction details, like write/read operation,
+    /// slave address type 10-bit or 7-bit and the transaction uses repeat
+    /// start or a normal transaction.
+    NvU32 Flags;
+    /// I2C slave device address.
+    NvU32 Address;
+    /// Number of bytes to be transferred.
+    NvU32 NumBytes;
+    /// Send/receive buffer. For I2C send operation this buffer should be
+    /// filled with the data to be sent to the slave device. For I2C receive
+    /// operation this buffer is filled with the data received from the slave device.
+    NvU8 *Buf;
+} NvOdmI2cTransactionInfo;
+
+/**
+ * Initializes and opens the I2C channel. This function allocates the
+ * handle for the I2C channel and provides it to the client.
+ *
+ * @see NvOdmI2cClose
+ *
+ * @param OdmIoModuleId  The ODM I/O module for I2C.
+ * @param instance The instance of the I2C driver to be opened.
+ *
+ * @return The handle to the I2C controller, or NULL if an error occurred.
+ */
+NvOdmServicesI2cHandle
+NvOdmI2cOpen(
+    NvOdmIoModule OdmIoModuleId,
+    NvU32 instance);
+
+/**
+ * Obtains a handle that can be used to access one of the I2C controllers, 
+ * for I2C controllers which are multiplexed between multiple pin mux 
+ * configurations. The I2C controller's pin mux will be reset to the specified 
+ * value every transaction, so that two handles to the same controller may 
+ * safely interleave across pin mux configurations.
+ *
+ * The ODM pin mux query for the specified controller must be
+ * NvOdmI2cPinMap_Multiplexed in order to create a handle using this function.
+ *
+ * There may be one or more instances of the I2C, depending upon the SOC,
+ * and these instances start from 0.
+ *
+ * Currently, this function is only supported for OdmIoModule_I2C, instance 1.
+ *
+ * @see NvOdmI2cClose
+ *
+ * @param OdmIoModule  The ODM I/O module for the I2C.
+ * @param ControllerId  The I2C controlled ID for which a handle is required.
+ *     Valid I2C controller IDs start from 0.
+ * @param PinMap The pin mux configuration to use for every transaction.
+ *
+ * @return The handle to the I2C controller, or NULL if an error occurred.
+ */
+NvOdmServicesI2cHandle 
+NvOdmI2cPinMuxOpen(NvOdmIoModule OdmIoModule,
+                   NvU32 ControllerId,
+                   NvOdmI2cPinMap PinMap);
+
+/**
+ * Closes the I2C channel. This function frees the memory allocated for
+ * the I2C handle and de-initializes the I2C ODM channel.
+ *
+ * @see NvOdmI2cOpen
+ *
+ * @param hOdmI2c The handle to the I2C channel.
+ */
+void NvOdmI2cClose(NvOdmServicesI2cHandle hOdmI2c);
+
+/**
+ * Does the I2C send or receive transactions with the slave deivces. This is a
+ * blocking call (with timeout). This API works for both the normal I2C transactions
+ * or I2C transactions in repeat start mode.
+ *
+ * For the I2C transactions with slave devices, a pointer to the list of required
+ * transactions must be passed and the corresponding number of transactions must
+ * be passed.
+ *
+ * The transaction information structure contains the flags (to indicate the
+ * transaction information, such as read or write transaction, transaction is with
+ * repeat-start or normal transaction and the slave device address type is 7-bit or
+ * 10-bit), slave deivce address, buffer to be transferred and number of bytes
+ * to be transferred.
+ *
+ * @param hOdmI2c The handle to the I2C channel.
+ * @param TransactionInfo A pointer to the array of I2C transaction structures.
+ * @param NumberOfTransactions The number of I2C transactions.
+ * @param ClockSpeedKHz Specifies the clock speed for the I2C transactions.
+ * @param WaitTimeoutInMilliSeconds The timeout in milliseconds.
+ *  ::NV_WAIT_INFINITE specifies to wait forever.
+ *
+ * @retval NvOdmI2cStatus_Success If successful, or the appropriate error code.
+ */
+NvOdmI2cStatus
+NvOdmI2cTransaction(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvOdmI2cTransactionInfo *TransactionInfo,
+    NvU32 NumberOfTransactions,
+    NvU32 ClockSpeedKHz,
+    NvU32 WaitTimeoutInMilliSeconds);
+
+/**
+ *  Defines the PMU VDD rail capabilities.
+ */
+typedef struct NvOdmServicesPmuVddRailCapabilitiesRec
+{
+    /// Specifies ODM protection attribute; if \c NV_TRUE PMU hardware
+    ///  or ODM Kit would protect this voltage from being changed by NvDdk client.
+    NvBool RmProtected;
+
+    /// Specifies the minimum voltage level in mV.
+    NvU32 MinMilliVolts;
+
+    /// Specifies the step voltage level in mV.
+    NvU32 StepMilliVolts;
+
+    /// Specifies the maximum voltage level in mV.
+    NvU32 MaxMilliVolts;
+
+    /// Specifies the request voltage level in mV.
+    NvU32 requestMilliVolts;
+
+} NvOdmServicesPmuVddRailCapabilities;
+
+/// Special level to indicate voltage plane is disabled.
+#define NVODM_VOLTAGE_OFF (0UL)
+
+/**
+ * Initializes and opens the PMU driver. The handle that is returned by this
+ * driver is used for all the other PMU operations.
+ *
+ * @see NvOdmPmuClose
+ *
+ * @return The handle to the PMU driver, or NULL if an error occurred.
+ */
+NvOdmServicesPmuHandle NvOdmServicesPmuOpen(void);
+
+/**
+ * Closes the PMU handle.
+ *
+ * @see NvOdmServicesPmuOpen
+ *
+ * @param handle The handle to the PMU driver.
+ */
+void NvOdmServicesPmuClose(NvOdmServicesPmuHandle handle);
+
+/**
+ * Gets capabilities for the specified PMU rail.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pCapabilities A pointer to the targeted
+ *  capabilities returned by the ODM.
+ *
+ */
+void NvOdmServicesPmuGetCapabilities(
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId,
+        NvOdmServicesPmuVddRailCapabilities * pCapabilities );
+
+/**
+ * Gets current voltage level for the specified PMU rail.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pMilliVolts A pointer to the voltage level returned
+ *  by the ODM.
+ */
+void NvOdmServicesPmuGetVoltage(
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId,
+        NvU32 * pMilliVolts );
+
+/**
+ * Sets new voltage level for the specified PMU rail.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param MilliVolts The new voltage level to be set in millivolts (mV).
+ *  Set to ::NVODM_VOLTAGE_OFF to turn off the target voltage.
+ * @param pSettleMicroSeconds A pointer to the settling time in microseconds (uS),
+ *  which is the time for supply voltage to settle after this function
+ *  returns; this may or may not include PMU control interface transaction time,
+ *  depending on the ODM implementation. If NULL this parameter is ignored.
+ */
+void NvOdmServicesPmuSetVoltage(
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId,
+        NvU32 MilliVolts,
+        NvU32 * pSettleMicroSeconds );
+
+/**
+ * Configures SoC power rail controls for the upcoming PMU voltage transition.
+ *
+ * @note Should be called just before PMU rail On/Off, or Off/On transition.
+ *  Should not be called if rail voltage level is changing within On range.
+ * 
+ * @param handle The handle to the PMU driver.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param Enable Set NV_TRUE if target voltage is about to be turned On, or
+ *  NV_FALSE if target voltage is about to be turned Off.
+ */
+void NvOdmServicesPmuSetSocRailPowerState(
+        NvOdmServicesPmuHandle handle,
+        NvU32 vddId, 
+        NvBool Enable );
+
+/**
+ * Defines battery instances.
+ */
+typedef enum
+{
+    /// Specifies main battery.
+    NvOdmServicesPmuBatteryInst_Main,
+
+    /// Specifies backup battery.
+    NvOdmServicesPmuBatteryInst_Backup,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmServicesPmuBatteryInstance_Force32 = 0x7FFFFFFF
+} NvOdmServicesPmuBatteryInstance;
+
+/**
+ * Gets the battery status.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param batteryInst The battery type.
+ * @param pStatus A pointer to the battery
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool 
+NvOdmServicesPmuGetBatteryStatus(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvU8 * pStatus);
+
+/**
+ * Defines battery data.
+ */
+typedef struct NvOdmServicesPmuBatteryDataRec
+{
+    /// Specifies battery life percent.
+    NvU32 batteryLifePercent;
+
+    /// Specifies battery life time.
+    NvU32 batteryLifeTime;
+
+    /// Specifies voltage.
+    NvU32 batteryVoltage;
+    
+    /// Specifies battery current.
+    NvS32 batteryCurrent;
+
+    /// Specifies battery average current.
+    NvS32 batteryAverageCurrent;
+
+    /// Specifies battery interval.
+    NvU32 batteryAverageInterval;
+
+    /// Specifies the mAH consumed.
+    NvU32 batteryMahConsumed;
+
+    /// Specifies battery temperature.
+    NvU32 batteryTemperature;
+} NvOdmServicesPmuBatteryData;
+
+/**
+ * Gets the battery data.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param batteryInst The battery type.
+ * @param pData A pointer to the battery
+ *  data returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmServicesPmuGetBatteryData(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvOdmServicesPmuBatteryData * pData);
+
+/**
+ * Gets the battery full lifetime.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param batteryInst The battery type.
+ * @param pLifeTime A pointer to the battery
+ *  full lifetime returned by the ODM.
+ */
+void
+NvOdmServicesPmuGetBatteryFullLifeTime(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvU32 * pLifeTime);
+
+/**
+ * Defines battery chemistry.
+ */
+typedef enum
+{
+    /// Specifies an alkaline battery.
+    NvOdmServicesPmuBatteryChemistry_Alkaline,
+
+    /// Specifies a nickel-cadmium (NiCd) battery.
+    NvOdmServicesPmuBatteryChemistry_NICD,
+
+    /// Specifies a nickel-metal hydride (NiMH) battery.
+    NvOdmServicesPmuBatteryChemistry_NIMH,
+
+    /// Specifies a lithium-ion (Li-ion) battery.
+    NvOdmServicesPmuBatteryChemistry_LION,
+
+    /// Specifies a lithium-ion polymer (Li-poly) battery.
+    NvOdmServicesPmuBatteryChemistry_LIPOLY,
+
+    /// Specifies a zinc-air battery.
+    NvOdmServicesPmuBatteryChemistry_XINCAIR,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmServicesPmuBatteryChemistry_Force32 = 0x7FFFFFFF
+} NvOdmServicesPmuBatteryChemistry;
+
+/**
+ * Gets the battery chemistry.
+ *
+ * @param handle The handle to the PMU driver.
+ * @param batteryInst The battery type.
+ * @param pChemistry A pointer to the battery
+ *  chemistry returned by the ODM.
+ */
+void
+NvOdmServicesPmuGetBatteryChemistry(
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuBatteryInstance batteryInst,
+    NvOdmServicesPmuBatteryChemistry * pChemistry);
+
+/**
+ * Defines the charging path.
+ */
+typedef enum
+{
+    /// Specifies external wall plug charger.
+    NvOdmServicesPmuChargingPath_MainPlug, 
+
+    /// Specifies external USB bus charger.
+    NvOdmServicesPmuChargingPath_UsbBus,
+
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmServicesPmuChargingPath_Force32 = 0x7FFFFFFF
+} NvOdmServicesPmuChargingPath;
+
+/** 
+* Sets the charging current limit. 
+* 
+* @param handle The Rm device handle.
+* @param ChargingPath The charging path. 
+* @param ChargingCurrentLimitMa The charging current limit in mA. 
+* @param ChargerType The charger type.
+*/
+void 
+NvOdmServicesPmuSetChargingCurrentLimit( 
+    NvOdmServicesPmuHandle handle,
+    NvOdmServicesPmuChargingPath ChargingPath,
+    NvU32 ChargingCurrentLimitMa,
+    NvOdmUsbChargerType ChargerType);
+
+/**
+ * Obtains a handle to set or get state of keys, for example, the state of the
+ * hold switch.
+ *
+ * @see NvOdmServicesKeyListClose()
+ *
+ * @return A handle to the key-list, or NULL if this open call fails.
+ */
+NvOdmServicesKeyListHandle
+NvOdmServicesKeyListOpen(void);
+
+/**
+ * Releases the handle obtained during the NvOdmServicesKeyListOpen() call and
+ * any other resources allocated.
+ *
+ * @param handle The handle returned from the \c NvOdmServicesKeyListOpen call.
+ */
+void NvOdmServicesKeyListClose(NvOdmServicesKeyListHandle handle);
+
+/**
+ * Searches the list of keys present and returns the value of the appropriate
+ * key.
+ * @param handle The handle obtained from NvOdmServicesKeyListOpen().
+ * @param KeyID The ID of the key whose value is required.
+ *
+ * @return The value of the corresponding key, or 0 if the key is not
+ * present in the list.
+ */
+NvU32
+NvOdmServicesGetKeyValue(
+            NvOdmServicesKeyListHandle handle,
+            NvU32 KeyID);
+
+/**
+ * Searches the list of keys present and sets the value of the key to the value
+ * given. If the key is not present, it adds the key to the list and sets the
+ * value.
+ * @param handle The handle obtained from NvOdmServicesKeyListOpen().
+ * @param Key The ID of the key whose value is to be set.
+ * @param Value The value to be set for the corresponding key.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmServicesSetKeyValuePair(
+            NvOdmServicesKeyListHandle handle,
+            NvU32 Key,
+            NvU32 Value);
+
+/**
+ * @brief Defines the possible PWM modes.
+ */
+
+typedef enum
+{
+    /// Specifies Pwm disabled mode.
+    NvOdmPwmMode_Disable = 1,
+
+    /// Specifies Pwm enabled mode.
+    NvOdmPwmMode_Enable,
+
+    /// Specifies Blink LED enabled mode
+    NvOdmPwmMode_Blink_LED,
+
+    /// Specifies Blink output 32KHz clock enable mode
+    NvOdmPwmMode_Blink_32KHzClockOutput,
+
+    /// Specifies Blink disabled mode
+    NvOdmPwmMode_Blink_Disable,
+
+    NvOdmPwmMode_Force32 = 0x7fffffffUL
+
+} NvOdmPwmMode;
+
+/**
+ * @brief Defines the possible PWM output pin.
+ */
+
+typedef enum
+{
+    /// Specifies PWM Output-0.
+    NvOdmPwmOutputId_PWM0 = 1,
+
+    /// Specifies PWM Output-1.
+    NvOdmPwmOutputId_PWM1,
+
+    /// Specifies PWM Output-2.
+    NvOdmPwmOutputId_PWM2,
+
+    /// Specifies PWM Output-3.
+    NvOdmPwmOutputId_PWM3,
+
+    /// Specifies PMC Blink LED.
+    NvOdmPwmOutputId_Blink, 
+
+    NvOdmPwmOutputId_Force32 = 0x7fffffffUL
+
+} NvOdmPwmOutputId;
+
+/**
+ * Creates and opens a PWM handle. The handle can be used to
+ * access PWM functions.
+ *
+ * @note Only the service client knows when the service can go idle,
+ * like in the case of vibrator, so the client suspend entry code
+ * must call NvOdmPwmClose() to close the PWM service.
+ *
+ * @return The handle to the PWM controller, or NULL if an error occurred.
+ */
+NvOdmServicesPwmHandle NvOdmPwmOpen(void);
+
+/**
+ * Releases a handle to a PWM controller. This API must be called once per
+ * successful call to NvOdmPwmOpen().
+ *
+ * @param hOdmPwm The handle to the PWM controller.
+ */
+void NvOdmPwmClose(NvOdmServicesPwmHandle hOdmPwm);
+
+/**
+ *  @brief Configures PWM module as disable/enable. This API is also
+ *  used to set the PWM duty cycle and frequency. Beside that, it is 
+ *  used to configure PMC' blinking LED if OutputId is 
+ *  NvOdmPwmOutputId_Blink
+ *
+ *  @param hOdmPwm The PWM handle obtained from NvOdmPwmOpen().
+ *  @param OutputId The PWM output pin to configure. Allowed values are
+ *   defined in ::NvOdmPwmOutputId.
+ *  @param Mode The mode type to configure. Allowed values are
+ *   defined in ::NvOdmPwmMode.
+ *  @param DutyCycle The duty cycle is an unsigned 15.16 fixed point
+ *   value that represents the PWM duty cycle in percentage range from
+ *   0.00 to 100.00. For example, 10.5 percentage duty cycle would be
+ *   represented as 0x000A8000. This parameter is ignored if NvOdmPwmMode
+ *   is NvOdmMode_Blink_32KHzClockOutput or NvOdmMode_Blink_Disable
+ *  @param pRequestedFreqHzOrPeriod A pointer to the request frequency in Hz
+ *   or period in second
+ *   A requested frequency value beyond the maximum supported value will be
+ *   clamped to the maximum supported value. If \em pRequestedFreqHzOrPeriod 
+ *   is NULL, it returns the maximum supported frequency. This parameter is 
+ *   ignored if NvOdmPwmMode is NvOdmMode_Blink_32KHzClockOutput or
+ *   NvOdmMode_Blink_Disable
+ *  @param pCurrentFreqHzOrPeriod A pointer to the returned frequency of 
+ *   that mode. If PMC Blink LED is used then it is the pointer to the returns 
+ *   period time. This parameter is ignored if NvOdmPwmMode is
+ *   NvOdmMode_Blink_32KHzClockOutput or NvOdmMode_Blink_Disable
+ */
+void
+NvOdmPwmConfig(NvOdmServicesPwmHandle hOdmPwm,
+    NvOdmPwmOutputId OutputId, 
+    NvOdmPwmMode Mode,            
+    NvU32 DutyCycle,
+    NvU32 *pRequestedFreqHzOrPeriod,
+    NvU32 *pCurrentFreqHzOrPeriod);
+
+/**
+ * Enables and disables external clock interfaces (e.g., CDEV and CSUS pins)
+ * for the specified peripheral. External clock sources should be enabled
+ * prior to programming peripherals reliant on them. If multiple peripherals use
+ * the same external clock source, it is safe to call this API multiple times.
+ *
+ * @param Guid The ODM-defined GUID of the peripheral to be configured. The
+ *             peripheral should have an @see NvOdmIoAddress entry for the
+ *             NvOdmIoModule_ExternalClock device interface. If multiple
+ *             external clock interfaces are specified, all will be
+ *             enabled (disabled).
+ *
+ * @param EnableTristate NV_TRUE will tristate the specified clock sources,
+ *             NV_FALSE will drive them.
+ *  
+ * @param pInstances Returns the list of clocks that were enabled.
+ *  
+ * @param pFrequencies Returns the frequency, in kHz, that is 
+ *                     being output on each clock pin
+ *  
+ * @param pNum Returns the number of clocks that were enabled.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmExternalClockConfig(
+    NvU64 Guid,
+    NvBool EnableTristate,
+    NvU32 *pInstances,
+    NvU32 *pFrequencies,
+    NvU32 *pNum);
+
+/**
+ *  Defines SoC strap groups.
+ */
+typedef enum
+{
+    /// Specifies the ram_code strap group.
+    NvOdmStrapGroup_RamCode = 1,
+
+    NvOdmStrapGroup_Num,
+    NvOdmStrapGroup_Force32 = 0x7FFFFFFF
+} NvOdmStrapGroup;
+
+/**
+ * Gets SoC strap value for the given strap group.
+ * 
+ * @note The strap assignment on each platform must be consistent with SoC
+ *  bootrom specifications and platform-specific BCT contents. The strap
+ *  value usage in ODM queries, however, is not limited to bootrom defined
+ *  functionality. The mapping between strap values and platforms is the ODM's
+ *  responsibility. ODMs should also ensure that they are using strap groups
+ *  that match the SOC in their product.
+ * 
+ * @param StrapGroup The strap group to be read.
+ * @param pStrapValue A pointer to the returned strap group value.
+ *  This value can be used by ODM queries to identify ODM platforms and to
+ *  provide the respective configuration settings.
+ *  
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmGetStraps(NvOdmStrapGroup StrapGroup, NvU32* pStrapValue);
+
+/**
+ * File input/output.
+ */
+typedef void* NvOdmOsFileHandle;
+
+/**
+ *  Defines the OS file types.
+ */
+typedef enum
+{
+    NvOdmOsFileType_Unknown = 0,
+    NvOdmOsFileType_File,
+    NvOdmOsFileType_Directory,
+    NvOdmOsFileType_Fifo,
+
+    NvOdmOsFileType_Force32 = 0x7FFFFFFF
+} NvOdmOsFileType;
+
+/**
+ *  Defines the OS status type.
+ */
+typedef struct NvOdmOsStatTypeRec
+{
+    NvU64 size;
+    NvOdmOsFileType type;
+} NvOdmOsStatType;
+
+/** Open a file with read permissions. */
+#define NVODMOS_OPEN_READ    0x1
+
+/** Open a file with write persmissions. */
+#define NVODMOS_OPEN_WRITE   0x2
+
+/** Create a file if is not present on the file system. */
+#define NVODMOS_OPEN_CREATE  0x4
+
+/**
+ *  Opens a file stream.
+ *
+ *  If the ::NVODMOS_OPEN_CREATE flag is specified, ::NVODMOS_OPEN_WRITE must also
+ *  be specified.
+ *
+ *  If ::NVODMOS_OPEN_WRITE is specified the file will be opened for write and
+ *  will be truncated if it was previously existing.
+ *
+ *  If ::NVODMOS_OPEN_WRITE and ::NVODMOS_OPEN_READ is specified the file will not
+ *  be truncated.
+ *
+ *  @param path A pointer to the path to the file.
+ *  @param flags ORed flags for the open operation (NVODMOS_OPEN_*).
+ *  @param file [out] A pointer to the file that will be opened, if successful.
+ *
+ *  @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmOsFopen(const char *path, NvU32 flags, NvOdmOsFileHandle *file);
+
+/**
+ *  Closes a file stream.
+ *  Passing in a NULL handle is okay.
+ *
+ *  @param stream The file stream to close.
+ */
+void NvOdmOsFclose(NvOdmOsFileHandle stream);
+
+/**
+ *  Writes to a file stream.
+ *
+ *  @param stream The file stream.
+ *  @param ptr A pointer to the data to write.
+ *  @param size The length of the write.
+ *
+ *  @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmOsFwrite(NvOdmOsFileHandle stream, const void *ptr, size_t size);
+
+/**
+ *  Reads a file stream.
+ *
+ *  To detect short reads (less that specified amount), pass in \a bytes
+ *  and check its value to the expected value. The \a bytes parameter may
+ *  be NULL.
+ *
+ *  @param stream The file stream.
+ *  @param ptr A pointer to the buffer for the read data.
+ *  @param size The length of the read.
+ *  @param bytes [out] A pointer to the number of bytes read -- may be NULL.
+ *
+ *  @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmOsFread(NvOdmOsFileHandle stream, void *ptr, size_t size, size_t *bytes);
+
+/**
+ *  Gets file information.
+ *
+ *  @param filename A pointer to the file to get information about.
+ *  @param stat [out] A pointer to the information structure.
+ *
+ *  @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmOsStat(const char *filename, NvOdmOsStatType *stat);
+
+/**
+ * Enables or disables USB OTG circuitry.
+ *
+ * @param Enable NV_TRUE to enable, or NV_FALSE to disable.
+ */
+void NvOdmEnableOtgCircuitry(NvBool Enable);
+
+/**
+ * Checks whether or not USB is connected.
+ *
+ * @pre The USB circuit is enabled by calling NvOdmEnableOtgCircuitry().
+ * To reduce power consumption, disable the USB circuit when not connected
+ * by calling \c NvOdmEnableOtgCircuitry(NV_FALSE).
+ *
+ * @return NV_TRUE if USB is successfully connected, otherwise NV_FALSE.
+ */
+NvBool NvOdmUsbIsConnected(void);
+
+/**
+ * Checks the current charging type.
+ *
+ * @pre The USB circuit is enabled by calling NvOdmEnableOtgCircuitry().
+ * To reduce power consumption, disable the USB circuit when not connected
+ * by calling \c NvOdmEnableOtgCircuitry(NV_FALSE).
+ *
+ * @param Instance Set to 0 by default.
+ * @return The current charging type.
+ */
+NvOdmUsbChargerType NvOdmUsbChargingType(NvU32 Instance);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*@}*/
+/** @} */
+
+#endif // INCLUDED_NVODM_SERVICES_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_tmon.h b/arch/arm/mach-tegra/nv/include/nvodm_tmon.h
new file mode 100644
index 000000000000..ebe90f2b7079
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_tmon.h
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Temperature Monitor Interface</b>
+ *
+ * @b Description: Defines the ODM interface for Temperature Monitor (TMON).
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_TMON_H
+#define INCLUDED_NVODM_TMON_H
+
+#include "nvcommon.h"
+#include "nvodm_services.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * @defgroup nvodm_tmon Temperature Monitor Adaptation Interface 
+ *   
+ * This is the temperature monitor (TMON) ODM adaptation interface, which
+ * handles the abstraction of external devices monitoring temperature zones
+ * on NVIDIA SoC based platforms. For the clients of this API, each zone has
+ * its own monitoring device. Dependencies introduced by multi-channel devices
+ * capable of monitoring several zones are resolved inside the implementation
+ * layer.
+ * 
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+/**
+ * Defines an opaque handle for TMON device.
+ */
+typedef struct NvOdmTmonDeviceRec *NvOdmTmonDeviceHandle;
+
+/**
+ * Defines an opaque handle to the TMON interrupt interface.
+ */
+typedef struct NvOdmTmonIntrRec *NvOdmTmonIntrHandle;
+
+/**
+ * Defines temperature zones.
+ */
+typedef enum
+{
+    /// Specifies ambient temperature zone.
+    NvOdmTmonZoneID_Ambient = 1,
+
+    /// Specifies SoC core temperature zone.
+    NvOdmTmonZoneID_Core,
+
+    NvOdmTmonZoneID_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmTmonZoneID_Force32 = 0x7FFFFFFFUL
+} NvOdmTmonZoneID;
+
+/**
+ * Defines temperature monitoring configuration parameters.
+ */
+typedef enum
+{
+    /// Identifies temperature sampling interval in ms.
+    NvOdmTmonConfigParam_SampleMs = 1,
+
+    /// Identifies High temperature boundary for TMON out of limit
+    ///  interrupt (in degrees C).
+    NvOdmTmonConfigParam_IntrLimitHigh,
+
+    /// Identifies Low temperature boundary for TMON out of limit
+    ///  interrupt (in degrees C).
+    NvOdmTmonConfigParam_IntrLimitLow,
+
+    /// Identifies temperature threshold for TMON comparator that
+    ///  controls h/w critical shutdown mechanism (in degrees C).
+    NvOdmTmonConfigParam_HwLimitCrit,
+
+    NvOdmTmonConfigParam_Num,
+    /// Ignore -- Forces compilers to make 32-bit enums.
+    NvOdmTmonConfigParam_Force32 = 0x7FFFFFFFUL
+} NvOdmTmonConfigParam;
+
+/// Special value for configuration parameters.
+#define ODM_TMON_PARAMETER_UNSPECIFIED (0x7FFFFFFF)
+
+/**
+ * Holds configuration parameter capabilities.
+ */
+typedef struct NvOdmTmonParameterCapsRec
+{ 
+    /// Specifies maximum parameter value (units depend on the parameter).
+    NvS32 MaxValue;
+
+    /// Specifies minimum parameter value (units depend on the parameter).
+    NvS32 MinValue;
+
+    /// Specifies ODM protection attribute; if \c NV_TRUE TMON ODM Kit would
+    ///  not allow to change the parameter.
+    NvBool OdmProtected;
+} NvOdmTmonParameterCaps;
+
+/**
+ * Holds temperature monitoring device capabilities.
+ */
+typedef struct NvOdmTmonCapabilitiesRec
+{ 
+    /// Specifies maximum temperature limit for TMON operations (in degrees C).
+    NvS32 Tmax;
+
+    /// Specifies minimum temperature limit for TMON operations (in degrees C).
+    NvS32 Tmin;
+
+    /// Specifies support for TMON out of limit interrupt.
+    NvBool IntrSupported;
+
+    /// Specifies support for TMON hardware critical shutdown mechanism.
+    NvBool HwCriticalSupported;
+
+    /// Specifies support for TMON hardware auto-cooling mechanism (e.g., fan).
+    NvBool HwCoolingSupported;
+} NvOdmTmonCapabilities;
+
+
+/**
+ * Gets a handle to the TMON in the specified zone.
+ *
+ * @param ZoneId The targeted temperature zone.
+ * 
+ * @return TMON handle, NULL if zone is not monitored.
+ */
+NvOdmTmonDeviceHandle
+NvOdmTmonDeviceOpen(NvOdmTmonZoneID ZoneId);
+
+/**
+ * Closes the TMON handle. 
+ *
+ * @param hTmon The TMON handle to be closed.
+ *  If NULL, this API has no effect.
+ */
+void NvOdmTmonDeviceClose(NvOdmTmonDeviceHandle hTmon);
+
+/**
+ * Gets TMON device capabilities.
+ *
+ * @param hTmon A handle to the TMON device.
+ * @param pCaps A pointer to the TMON device capabilities returned by the ODM.
+ */
+void
+NvOdmTmonCapabilitiesGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonCapabilities* pCaps);
+
+/**
+ * Gets TMON configuration parameter capabilities.
+ *
+ * @param hTmon A handle to the TMON device.
+ * @param ParamId The targeted parameter. 
+ * @param pCaps A pointer to the targeted parameter capabilities
+ *  returned by the ODM.
+ * 
+ *  Special value ::ODM_TMON_PARAMETER_UNSPECIFIED is returned as maximum and
+ *  minimum value in capabilities structure if the targeted parameter is not
+ *  supported.
+ */
+void
+NvOdmTmonParameterCapsGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonConfigParam ParamId,
+    NvOdmTmonParameterCaps* pCaps);
+
+/**
+ * Gets current zone temperature.
+ *
+ * @param hTmon A handle to the TMON device.
+ * @param pDegreesC A pointer to the zone temperature (in degrees C)
+ *  returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmTmonTemperatureGet(
+    NvOdmTmonDeviceHandle hTmon,
+    NvS32* pDegreesC);
+
+/**
+ * Configures specified TMON parameter for the temperature zone.
+ *
+ * @param hTmon A handle to the TMON device.
+ * @param ParamId The targeted parameter to be updated. 
+ * @param pSetting A pointer to a variable with parameter settings.
+ *  On entry, specifies new requested settings, on exit, actually configured
+ *  settings as the best approximation of the request.
+ * 
+ *  The requested setting is clipped to the maximum/minimum values for the
+ *  respective parameter. If special value ::ODM_TMON_PARAMETER_UNSPECIFIED is
+ *  specified on entry, current parameter value is preserved and retrieved on
+ *  exit. If special value \c ODM_TMON_PARAMETER_UNSPECIFIED is returned on exit,
+ *  the targeted parameter is not supported for the given zone.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise
+ */
+NvBool
+NvOdmTmonParameterConfig(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonConfigParam ParamId,
+    NvS32* pSetting);
+
+/**
+ * Suspends temperature zone monitoring.
+ * 
+ * @param hTmon A handle to the TMON device.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmTmonSuspend(NvOdmTmonDeviceHandle hTmon);
+
+/**
+ * Resumes temperature zone monitoring.
+ * 
+ * @param hTmon A handle to the TMON device.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmTmonResume(NvOdmTmonDeviceHandle hTmon);
+
+/**
+ * Registers for TMON out of limit interrupt.
+ * 
+ * @param hTmon A handle to the TMON device.
+ * @param Callback The callback function that is called when TMON
+ *  interrupt triggers.
+ * @param arg The argument passed to the callback when it is
+ *  invoked by TMON IST.
+ * 
+ * @return TMON interrupt handle, NULL if failed to register.
+ */
+NvOdmTmonIntrHandle
+NvOdmTmonIntrRegister(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmInterruptHandler Callback,
+    void* arg);
+
+/**
+ * Unregisters TMON interrupt.
+ * 
+ * @param hTmon A handle to the TMON device.
+ * @param hIntr A TMON interrupt handle.
+ *  If NULL, this API has no effect.
+ */
+void
+NvOdmTmonIntrUnregister(
+    NvOdmTmonDeviceHandle hTmon,
+    NvOdmTmonIntrHandle hIntr);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_TMON_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_touch.h b/arch/arm/mach-tegra/nv/include/nvodm_touch.h
new file mode 100644
index 000000000000..8691302953d3
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_touch.h
@@ -0,0 +1,405 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Touch Pad Sensor Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for touch pad sensor devices.
+ *
+ */
+
+#ifndef INCLUDED_NVODM_TOUCH_H
+#define INCLUDED_NVODM_TOUCH_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+
+/**
+ * @defgroup nvodm_touch Touch Pad Adaptation Interface
+ *
+ * This is the touch pad ODM adaptation interface.
+ *
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+
+/**
+ * Defines an opaque handle that exists for each touch device in the
+ * system, each of which is defined by the customer implementation.
+ */
+typedef struct NvOdmTouchDeviceRec *NvOdmTouchDeviceHandle;
+
+#define NVODM_MAX_INPUT_COORDS 5
+
+/**
+ * @brief Defines the gesture type.
+ */
+typedef enum
+{
+    /// Indicates the gesture is not supported.
+    NvOdmTouchGesture_Not_Supported = 0x0000,
+
+    /// Indicates that there was no gesture recognized.
+    NvOdmTouchGesture_No_Gesture = 0x0001,
+
+    /// Indicates the "tap" gesture: one rapid finger press and release.
+    NvOdmTouchGesture_Tap = 0x0002,
+
+    /// Indicates the "double tap" gesture: two taps in rapid succession.
+    NvOdmTouchGesture_Double_Tap = 0x0004,
+
+    /// Indicates the "tap and hold" gesture: a tap event rapidly followed by press-and-hold.
+    NvOdmTouchGesture_Tap_and_Hold = 0x0008,
+
+    /// Indicates the "press" gesture: a finger that presses down and stays on the panel.
+    NvOdmTouchGesture_Press = 0x0010,
+
+    /**
+     * Indicates the "press and drag" gesture: a finger that presses down, stays
+     * on the panel and then moves
+     */
+    NvOdmTouchGesture_Press_Drag = 0x0020,
+
+    /**
+     * Indicates the "zoom" gesture: a simultaneous two-fingered gesture, where
+     * the two fingers are either moving towards each other, or moving away from
+     * each other.
+     */
+    NvOdmTouchGesture_Zoom = 0x0040,
+
+    /**
+     * Indicates the "Flick" gesture: a "tap and drag" gesture or a fast
+     * "press and drag" where the finger stays on the panel only for a short time.
+     */
+    NvOdmTouchGesture_Flick = 0x0080,
+
+    NvOdmTouchGestureType_Force32 = 0x7fffffffUL
+} NvOdmTouchGestureType;
+
+
+/**
+ *  Defines the touch orientation based on the LCD screen.
+ */
+typedef enum
+{
+    /// Indicates the touch panel X/Y coords are swapped in relation to LCD screen.
+    NvOdmTouchOrientation_XY_SWAP = 0x01,
+    /// Indicates the touch panel X/Y coords are horizontally flipped (or mirrored) in relation to LCD screen.
+    NvOdmTouchOrientation_H_FLIP = 0x02,
+    /// Indicates the touch panel X/Y coords are vertically flipped in relation to LCD screen.
+    NvOdmTouchOrientation_V_FLIP = 0x04,
+
+    NvOdmTouchOrientation_Force32 = 0x7fffffffUL
+} NvOdmTouchOrientationType;
+/**
+ *  Defines the touch capabilities.
+ */
+typedef struct
+{
+    /// Holds a value indicating whether or not multi-touch is supported: 1 single touch : 0 multi-touch.
+    NvBool IsMultiTouchSupported;
+
+    /// Holds the maximum number of finger coordinates that can be reported.
+    NvU32 MaxNumberOfFingerCoordReported;
+
+    /// Holds a value indicating whether or not relative data for X/Y is supported: 1  not support : 0 supported.
+    NvBool IsRelativeDataSupported;
+
+    /// Holds the maximum value for relative coords that can be reported.
+    NvU32 MaxNumberOfRelativeCoordReported;
+
+    /// Holds the maximum width value that can be reported.
+    NvU32 MaxNumberOfWidthReported;
+
+    /// Holds the maximum pressure value that can be reported.
+    NvU32 MaxNumberOfPressureReported;
+
+    /// Holds a bitmask specifying the supported gestures
+    NvU32 Gesture;
+
+    /// Holds a value indicating whether or not finger width is supported.
+    NvBool IsWidthSupported;
+
+    /// Holds a value indicating whether finger signal strength or finger contact only is supported.
+    NvBool IsPressureSupported;
+
+    /// Holds a value indicating whether or not fingers on the panel are supported.
+    NvBool IsFingersSupported;
+
+    /// Holds the minimum X position.
+    NvU32 XMinPosition;
+
+    /// Holds the minimum Y position.
+    NvU32 YMinPosition;
+
+    /// Holds the maximum X position.
+    NvU32 XMaxPosition;
+
+    /// Holds the maximum Y position.
+    NvU32 YMaxPosition;
+
+    /// Holds the orientation based on the LCD screen.
+    NvU32 Orientation;
+
+} NvOdmTouchCapabilities;
+
+
+/**
+ * @brief Defines the possible touch states.
+ */
+typedef enum
+{
+    /// Indicates a valid reading.
+    NvOdmTouchSampleValidFlag = 0x1,
+
+    /// Indicates to ignore the sample.
+    NvOdmTouchSampleIgnore = 0x2,
+
+    /// Indicates the state of the finger.
+    NvOdmTouchSampleDownFlag = 0x4,
+
+    NvOdmTouchSampleFlags_Force32 = 0x7fffffffUL
+} NvOdmTouchSampleFlags;
+
+
+/**
+ * Defines the ODM touch-specific functionality information.
+ */
+typedef struct
+{
+    /// Indicates x,y-coordinates for multiple input coordinates (fingers).
+    NvU32 multi_XYCoords[NVODM_MAX_INPUT_COORDS][2];
+    /// Indicates approximate finger width on the touch panel.
+    NvU8 width[NVODM_MAX_INPUT_COORDS];
+    /// Specifies a bitmask describing the gesture recognized.
+    NvU32 Gesture;
+    /// Indicates whether or not the gesture was valid.
+    NvU8 Confirmed;
+    /// Indicates the number of fingers on the touch panel.
+    NvU8 Fingers;
+    /// Indicates an approximate finger pressure.
+    NvU8 Pressure[NVODM_MAX_INPUT_COORDS];
+    /// Indicates the relative coordinate information.
+    NvS8 XYDelta[NVODM_MAX_INPUT_COORDS][2];
+
+} NvOdmTouchAdditionalInfo;
+
+
+/**
+ * Defines the ODM touch pad coordinate information.
+ */
+typedef struct
+{
+    /// Specifies the X-coordinate.
+    NvU32 xcoord;
+    /// Specifies the Y-coordinate.
+    NvU32 ycoord;
+    /// Specifies the sample state information.
+    NvU32 fingerstate;
+    /// Specifies additional functionality information.
+    NvOdmTouchAdditionalInfo additionalInfo;
+    /// Specifies a pointer to extended data, if needed.
+    void* pextrainfo;
+    /// Specifies the size of extended data.
+    NvU32 extrainfosize;
+
+} NvOdmTouchCoordinateInfo;
+
+
+/**
+ * @brief Defines the structure for the sampling rate.
+ */
+typedef struct
+{
+    /// Specifies a low amount of samples per second.
+    NvU32 NvOdmTouchSampleRateLow;
+
+    /// Specifies a high amount of samples per second.
+    NvU32 NvOdmTouchSampleRateHigh;
+
+    /// Specifies the current sample rate setting, zero is low, 1 is high.
+    NvU32 NvOdmTouchCurrentSampleRate;
+} NvOdmTouchSampleRate;
+
+
+/**
+ * @brief Defines the power mode for the touch panel.
+ */
+typedef enum
+{
+    /// Indicates full power.
+    NvOdmTouch_PowerMode_0 = 0x1,
+    NvOdmTouch_PowerMode_1,
+    NvOdmTouch_PowerMode_2,
+    /// Indicates power off.
+    NvOdmTouch_PowerMode_3,
+    NvOdmTouchPowerMode_Force32 = 0x7fffffffUL
+} NvOdmTouchPowerModeType;
+
+
+
+/**
+ * Gets a handle to the touch pad in the system.
+ *
+ * @param hDevice A pointer to the handle of the touch pad.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmTouchDeviceOpen( NvOdmTouchDeviceHandle *hDevice );
+
+/**
+ * Gets capabilities for the specified touch device.
+ *
+ * @param hDevice The handle of the touch pad.
+ * @param pCapabilities A pointer to the targeted
+ *  capabilities returned by the ODM.
+ */
+void
+NvOdmTouchDeviceGetCapabilities(NvOdmTouchDeviceHandle hDevice, NvOdmTouchCapabilities* pCapabilities);
+
+/**
+ * Gets coordinate info from the touch device.
+ *
+ * @param hDevice The handle to the touch pad.
+ * @param coord  A pointer to the structure holding coordinate info.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmTouchReadCoordinate( NvOdmTouchDeviceHandle hDevice, NvOdmTouchCoordinateInfo *coord);
+
+
+/**
+ * Hooks up the interrupt handle to the GPIO interrupt and enables the interrupt.
+ *
+ * @param hDevice The handle to the touch pad.
+ * @param hInterruptSemaphore A handle to hook up the interrupt.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmTouchEnableInterrupt(NvOdmTouchDeviceHandle hDevice, NvOdmOsSemaphoreHandle hInterruptSemaphore);
+
+/**
+ * Prepares the next interrupt to get notified from the touch device.
+ *
+ * @param hDevice A handle to the touch pad.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool NvOdmTouchHandleInterrupt(NvOdmTouchDeviceHandle hDevice);
+
+/**
+ * Gets the touch ADC sample rate.
+ *
+ * @param hDevice A handle to the touch ADC.
+ * @param pTouchSampleRate A pointer to the NvOdmTouchSampleRate stucture.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+*/
+NvBool
+NvOdmTouchGetSampleRate(NvOdmTouchDeviceHandle hDevice, NvOdmTouchSampleRate* pTouchSampleRate);
+
+
+/**
+ * Sets the touch ADC sample rate.
+ *
+ * @param hDevice A handle to the touch ADC.
+ * @param SampleRate 1 indicates high frequency, 0 indicates low frequency.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+*/
+NvBool
+NvOdmTouchSetSampleRate(NvOdmTouchDeviceHandle hDevice, NvU32 SampleRate);
+
+
+/**
+ * Sets the touch panel power mode.
+ *
+ * @param hDevice A handle to the touch ADC.
+ * @param mode The mode, ranging from full power to power off.
+ *
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+*/
+NvBool
+NvOdmTouchPowerControl(NvOdmTouchDeviceHandle hDevice, NvOdmTouchPowerModeType mode);
+
+/**
+ * Powers the touch device on or off.
+ *
+ * @param hDevice A handle to the touch ADC.
+ * @param OnOff  Specify 1 to power on; 0 to power off.
+*/
+void
+NvOdmTouchPowerOnOff(NvOdmTouchDeviceHandle hDevice, NvBool OnOff);
+
+/**
+ *  Releases the touch pad handle.
+ *
+ * @param hDevice The touch pad handle to be released. If
+ *     NULL, this API has no effect.
+ */
+void NvOdmTouchDeviceClose(NvOdmTouchDeviceHandle hDevice);
+
+/**
+ * Gets the touch ODM debug configuration.
+ *
+ * @param hDevice A handle to the touch pad.
+ *
+ * @return NV_TRUE if debug message is enabled, or NV_FALSE if not.
+ */
+NvBool
+NvOdmTouchOutputDebugMessage(NvOdmTouchDeviceHandle hDevice);
+
+/**
+ * Gets the touch panel calibration data.
+ * This is optional as calibration may perform after the OS is up.
+ * This is not required to bring up the touch panel.
+ *
+ * @param hDevice A handle to the touch panel.
+ * @param NumOfCalibrationData Indicates the number of calibration points.
+ * @param pRawCoordBuffer The collection of X/Y coordinate data.
+ *
+ * @return NV_TRUE if preset calibration data is required, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmTouchGetCalibrationData(NvOdmTouchDeviceHandle hDevice, NvU32 NumOfCalibrationData, NvS32* pRawCoordBuffer);
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_TOUCH_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_uart.h b/arch/arm/mach-tegra/nv/include/nvodm_uart.h
new file mode 100644
index 000000000000..a3e338e0c2f4
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_uart.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         UART Adaptation Interface</b>
+ *
+ * @b Description: Defines the ODM adaptation interface for UART devices.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_UART_H
+#define INCLUDED_NVODM_UART_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvodm_services.h"
+#include "nverror.h"
+
+/**
+ * @defgroup nvodm_uart UART Adaptation Interface
+ * 
+ * This is the UART ODM adaptation interface. 
+ * 
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+/**
+ * Defines an opaque handle that exists for each UART device in the
+ * system, each of which is defined by the customer implementation.
+ */
+typedef struct NvOdmUartRec *NvOdmUartHandle;
+
+/**
+ * Gets a handle to the UART device.
+ *
+ * @param Instance         [IN] UART instance number
+ *
+ * @return A handle to the UART device.
+ */
+NvOdmUartHandle NvOdmUartOpen(NvU32 Instance);
+
+/**
+ * Closes the UART handle. 
+ *
+ * @param hOdmUart The UART handle to be closed.
+ */
+void NvOdmUartClose(NvOdmUartHandle hOdmUart);
+
+/**
+ * Call this API whenever the UART device goes into suspend mode.
+ *
+ * @param hOdmUart The UART handle.
+  */
+NvBool NvOdmUartSuspend(NvOdmUartHandle hOdmUart);
+
+/**
+ * Call this API whenever the UART device resumes from the suspend mode.
+ *
+ * @param hOdmUart The UART handle.
+  */
+NvBool NvOdmUartResume(NvOdmUartHandle hOdmUart);
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_uart_H
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_usbulpi.h b/arch/arm/mach-tegra/nv/include/nvodm_usbulpi.h
new file mode 100644
index 000000000000..024996dad757
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_usbulpi.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         USB ULPI Interface</b>
+ *
+ * @b Description: Defines the ODM interface for USB ULPI device.
+ */
+
+#ifndef INCLUDED_NVODM_USBULPI_H
+#define INCLUDED_NVODM_USBULPI_H
+
+
+/**
+ * @defgroup nvodm_usbulpi USB ULPI Adaptation Interface
+ *
+ * This is the USB ULPI ODM adaptation interface, which
+ * handles the abstraction of opening and closing of the USB ULPI device.
+ * For NVIDIA Driver Development Kit (NvDDK) clients, USB ULPI device
+ * means a USB controller connected to a ULPI interface that has an
+ * external phy. This API allows NvDDK clients to open the USB ULPI device by
+ * setting the ODM specific clocks to ULPI controller or external phy, so that USB ULPI
+ * device can be used.
+ *
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+#if defined(_cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvcommon.h"
+
+
+/**
+ * Defines the USB ULPI context.
+ */
+typedef struct NvOdmUsbUlpiRec * NvOdmUsbUlpiHandle;
+
+/**
+ * Opens the USB ULPI device by setting the ODM-specific clocks 
+ * and/or settings related to USB ULPI controller and external phy.
+ * @param Instance The ULPI instance number.
+ * @return A USB ULPI device handle on success, or NULL on failure.
+*/
+NvOdmUsbUlpiHandle  NvOdmUsbUlpiOpen(NvU32 Instance);
+
+/** 
+ * Closes the USB ULPI device handle by clearing 
+ * the related ODM-specific clocks and settings.
+ * @param hUsbUlpi A handle to USB ULPI device.
+*/
+void NvOdmUsbUlpiClose(NvOdmUsbUlpiHandle hUsbUlpi);
+
+
+#if defined(_cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_USBULPI_H
+
diff --git a/arch/arm/mach-tegra/nv/include/nvodm_vibrate.h b/arch/arm/mach-tegra/nv/include/nvodm_vibrate.h
new file mode 100644
index 000000000000..ea4e3ea5a7f2
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvodm_vibrate.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Vibrate Interface</b>
+ *
+ * @b Description: Defines the ODM interface for vibrate devices.
+ * 
+ */
+
+#ifndef INCLUDED_NVODM_VIBRATE_H
+#define INCLUDED_NVODM_VIBRATE_H
+
+#include "nvcommon.h"
+
+/**
+ * @defgroup nvodm_vibrate Vibrate Adaption Interface
+ *
+ * This is the Vibrate ODM adaptation interface.
+ *
+ * @ingroup nvodm_adaptation
+ * @{
+ */
+
+/**
+ *  @brief Opaque handle to the vibrate device.
+ */
+typedef struct NvOdmVibDeviceRec *NvOdmVibDeviceHandle;
+
+/**
+ * @brief Defines attributes that can be set/queried by clients.
+ */
+typedef enum
+{
+    NvOdmVibCaps_Invalid = 0x0,
+    /** Specifies the maximum supported frequency. */
+    NvOdmVibCaps_MaxFreq,
+    /** Specifies the minimum supported frequency. */
+    NvOdmVibCaps_MinFreq,
+    /** Specifies the maximum supported duty cycle. */
+    NvOdmVibCaps_MaxDutyCycle,
+    NvOdmVibCaps_Num,
+    NvOdmVibCaps_Force32 = 0x7FFFFFFF,
+} NvOdmVibCaps;
+
+#if defined(_cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ *  @brief Allocates a handle to the device. Configures the PWM
+ *   control to the vibro motor with default values. To change
+ *   the duty cycle and frequency, use NvOdmVibSetFrequency() and
+ *   NvOdmVibSetDutyCycle() APIs.
+ *  @param hOdmVibrate  [IN] A pointer to the opaque handle to the device.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmVibOpen(NvOdmVibDeviceHandle *hOdmVibrate);
+
+/**
+ *  @brief Closes the ODM device and destroys all allocated resources.
+ *  @param hOdmVibrate  [IN] The opaque handle to the device.
+ */
+void
+NvOdmVibClose(NvOdmVibDeviceHandle hOdmVibrate);
+
+/**
+ *  @brief Gets capabilities of the vibrate device.
+ *  @param hDevice	    [IN] The opaque handle to the device.
+ *  @param RequestedCaps  [IN] Specifies the capability to get.
+ *  @param pCapsValue    [OUT] A pointer to the returned value.
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmVibGetCaps(
+    NvOdmVibDeviceHandle hDevice,
+    NvOdmVibCaps RequestedCaps,
+    NvU32 *pCapsValue);
+
+/**
+ *  @brief Sets the frequency to the vibro motor.
+ *    A frequency less than zero will be set to zero 
+ *    and a frequency value beyond the maximum supported value
+ *    will be set to the maximum supported value.
+ *  @param hDevice	  [IN] The opaque handle to the device.
+ *  @param Freq         [IN] The frequency to set in Hz.
+ *  @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmVibSetFrequency(NvOdmVibDeviceHandle hDevice, NvS32 Freq);
+
+/**
+ *  @brief Sets the dutycycle of the PWM driving the vibro motor.
+ *    A duty cycle less than zero will be set to zero 
+ *    and value beyond the maximum supported value
+ *    will be set to the maximum supported value.
+ *  @param hDevice  [IN] The opaque handle to the device.
+ *  @param DCycle       [IN] The duty cycle value to set in percentage (0%-100%).
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmVibSetDutyCycle(NvOdmVibDeviceHandle hDevice, NvS32 DCycle);
+
+/**
+ *  @brief Starts the vibro with the frequency and duty cycle set using the
+ *    set API.
+ *  @param hDevice  [IN] The opaque handle to the device.
+ *  @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmVibStart(NvOdmVibDeviceHandle hDevice);
+
+/**
+ *  @brief Stops the vibro motor.
+ *  @param hDevice  [IN] The opaque handle to the device.
+ *  @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+NvBool
+NvOdmVibStop(NvOdmVibDeviceHandle hDevice);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/** @} */
+
+#endif // INCLUDED_NVODM_VIBRATE_H
diff --git a/arch/arm/mach-tegra/nv/include/nvos.h b/arch/arm/mach-tegra/nv/include/nvos.h
new file mode 100644
index 000000000000..9f05fcd905d1
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvos.h
@@ -0,0 +1,2399 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b> NVIDIA Operating System Abstraction</b>
+ *
+ * @b Description: Provides interfaces that enable unification of code
+ * across all supported operating systems.
+ */
+
+
+#ifndef INCLUDED_NVOS_H
+#define INCLUDED_NVOS_H
+
+/**
+ * @defgroup nvos_group NvOS - NVIDIA Operating System Abstraction
+ *
+ * This provides a basic set of interfaces to unify code
+ * across all supported operating systems. This layer does @b not
+ * handle any hardware specific functions, such as interrupts.
+ * "Platform" setup and GPU access are done by other layers.
+ *
+ * @warning Drivers and applications should @b not make any operating system
+ * calls outside of this layer, @b including stdlib functions. Doing so will
+ * result in non-portable code.
+ *
+ * For APIs that take key parameters, keys may be of ::NVOS_KEY_MAX length.
+ * Any characters beyond this maximum is ignored.
+ *
+ * All strings passed to or from NvOS functions are encoded in UTF-8. For
+ * character values below 128, this is the same as simple ASCII. For more
+ * information, see:
+ * <a href="http://en.wikipedia.org/wiki/UTF-8"
+ *    target="_blank">http://en.wikipedia.org/wiki/UTF-8</a>
+ *
+ *
+ * @par Important:
+ *
+ *  At interrupt time there are only a handful of NvOS functions that are safe
+ *  to call:
+ *  - ::NvOsSemaphoreSignal
+ *  - ::NvOsIntrMutexLock
+ *  - ::NvOsIntrMutexUnlock
+ *  - ::NvOsWaitUS
+ *
+ * @note Curerntly, ::NvOsWaitUS for ISR has @b only been implemented for AOS and
+ * WinCE. Use with caution.
+ *
+ * @{
+ */
+
+#include <stdarg.h>
+#include "nvcommon.h"
+#include "nverror.h"
+#include "nvos_trace.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/**
+ * A physical address. Must be 64 bits for OSs that support more than 64 bits
+ * of physical addressing, not necessarily correlated to the size of a virtual
+ * address.
+ *
+ * Currently, 64-bit physical addressing is supported by NvOS on WinNT only.
+ *
+ * XXX 64-bit phys addressing really should be supported on Linux/x86, since
+ * all modern x86 CPUs have 36-bit (or more) physical addressing. We might
+ * need to control a PCI card that the SBIOS has placed at an address above
+ * 4 GB.
+ */
+#if NVOS_IS_WINDOWS && !NVOS_IS_WINDOWS_CE
+typedef NvU64 NvOsPhysAddr;
+#else
+typedef NvU32 NvOsPhysAddr;
+#endif
+
+/** The maximum length of a shared resource identifier string.
+ */
+#define NVOS_KEY_MAX 128
+
+/** The maximum length for a file system path.
+ */
+#define NVOS_PATH_MAX 256
+
+/** @name Print Operations
+ */
+/*@{*/
+
+/** Printf family. */
+typedef struct NvOsFileRec *NvOsFileHandle;
+
+/** Prints a string to a file stream.
+ *
+ *  @param stream The file stream to which to print.
+ *  @param format The format string.
+ */
+NvError
+NvOsFprintf(NvOsFileHandle stream, const char *format, ...);
+
+// Doxygen requires escaping backslash characters (\) with another \ so in
+// @return, ignore the first backslash if you are reading this in the header.
+/** Expands a string into a given string buffer.
+ *
+ *  @param str A pointer to the target string buffer.
+ *  @param size The size of the string buffer.
+ *  @param format A pointer to the format string.
+ *
+ *  @return The number of characters printed (not including the \\0).
+ *  The buffer was printed to successfully if the returned value is
+ *  greater than -1 and less than \a size.
+ */
+NvS32
+NvOsSnprintf(char *str, size_t size, const char *format, ...);
+
+/** Prints a string to a file stream using a va_list.
+ *
+ *  @param stream The file stream.
+ *  @param format A pointer to the format string.
+ *  @param ap The va_list structure.
+ */
+NvError
+NvOsVfprintf(NvOsFileHandle stream, const char *format, va_list ap);
+
+/** Expands a string into a string buffer using a va_list.
+ *
+ *  @param str A pointer to the target string buffer.
+ *  @param size The size of the string buffer.
+ *  @param format A pointer to the format string.
+ *  @param ap The va_list structure.
+ *
+ *  @return The number of characters printed (not including the \\0).
+ *  The buffer was printed to successfully if the returned value is
+ *  greater than -1 and less than \a size.
+ */
+NvS32
+NvOsVsnprintf(char *str, size_t size, const char *format, va_list ap);
+
+/**
+ * Outputs a message to the debugging console, if present. All device driver
+ * debug printfs should use this. Do not use this for interacting with a user
+ * from an application; in that case, use NvTestPrintf() instead.
+ *
+ * @param format A pointer to the format string.
+ */
+void
+NvOsDebugPrintf(const char *format, ...);
+
+/**
+ * Same as ::NvOsDebugPrintf, except takes a va_list.
+ */
+void
+NvOsDebugVprintf( const char *format, va_list ap );
+
+/**
+ * Same as ::NvOsDebugPrintf, except returns the number of chars written.
+ *
+ * @return number of chars written or -1 if that number is unavailable
+ */
+NvS32
+NvOsDebugNprintf( const char *format, ...);
+
+/**
+ * Prints an error and the line it appeared on.
+ * Does nothing if err==NvSuccess
+ *
+ * @param err - the error to return
+ * @param file - file the error occurred in.
+ * @param line - line number the error occurred on.
+ * @returns err
+ */
+NvError
+NvOsShowError(NvError err, const char *file, int line);
+
+// Doxygen requires escaping # with a backslash, so in the examples below
+// ignore the backslash before the # if reading this in the header file.
+/**
+ * Helper macro to go along with ::NvOsDebugPrintf. Usage:
+ * <pre>
+ *     NV_DEBUG_PRINTF(("foo: %s\n", bar));    
+   </pre>
+ *
+ * The debug print will be disabled by default in all builds, debug and
+ * release. @note Usage requires double parentheses.
+ *
+ * To enable debug prints in a particular .c file, add the following
+ * to the top of the .c file and rebuild:
+ * <pre>
+ *     \#define NV_ENABLE_DEBUG_PRINTS 1
+   </pre>
+ *
+ * To enable debug prints in a particular module, add the following 
+ * to the makefile and rebuild:
+ * <pre>
+ *     LCDEFS += -DNV_ENABLE_DEBUG_PRINTS=1
+   </pre>
+ * 
+ */
+#if !defined(NV_ENABLE_DEBUG_PRINTS)
+#define NV_ENABLE_DEBUG_PRINTS 0
+#endif
+#if NV_ENABLE_DEBUG_PRINTS
+// put the print in an if statement so that the compiler will always parse it
+#define NV_DEBUG_PRINTF(x) \
+    do { if (NV_ENABLE_DEBUG_PRINTS) { NvOsDebugPrintf x ; } } while (0)
+#else
+#define NV_DEBUG_PRINTF(x) do {} while (0)
+#endif
+
+/*@}*/
+/** @name OS Version
+ */
+/*@{*/
+
+typedef enum
+{
+    NvOsOs_Unknown,
+    NvOsOs_Windows,
+    NvOsOs_Linux,
+    NvOsOs_Aos,
+    NvOsOs_Force32 = 0x7fffffffUL,
+} NvOsOs;
+
+typedef enum
+{
+    NvOsSku_Unknown,
+    NvOsSku_CeBase,
+    NvOsSku_Mobile_SmartFon,
+    NvOsSku_Mobile_PocketPC,
+    NvOsSku_Android,
+    NvOsSku_Force32 = 0x7fffffffUL,
+} NvOsSku;
+
+typedef struct NvOsOsInfoRec
+{
+    NvOsOs  OsType;
+    NvOsSku Sku;
+    NvU16   MajorVersion;
+    NvU16   MinorVersion;
+    NvU32   SubVersion;
+    NvU32   Caps;
+} NvOsOsInfo;
+
+/**
+ * Gets the current OS version.
+ *
+ * @param pOsInfo A pointer to the operating system information structure.
+ */
+NvError
+NvOsGetOsInformation(NvOsOsInfo *pOsInfo);
+
+/*@}*/
+
+/** @name Resources 
+ */
+/*@{*/
+
+/** An opaque resource handle.
+ */
+typedef struct NvOsResourceRec *NvOsResourceHandle;
+
+typedef enum
+{
+    NvOsResource_Unknown,
+    NvOsResource_Storage,
+    NvOsResource_Force32 = 0x7fffffffUL,
+} NvOsResource;
+
+#define NVOS_DEV_NAME_MAX    16
+
+typedef struct NvOsResourceStorageRec
+{
+    /// The storage device name.
+    NvU8    DeviceName[2*NVOS_DEV_NAME_MAX];
+    /// The mount point for this storage device.
+    NvU8    MountPoint[NVOS_PATH_MAX];
+    /// The free bytes available within the current context.
+    NvU64   FreeBytesAvailable;
+    /// The total bytes available within the current context (used + free).
+    NvU64   TotalBytes;
+    /// The total free bytes available on disk.
+    NvU64   TotalFreeBytes;
+} NvOsResourceStorage;
+
+/**
+ * Obtain a list of resources of the specified type. 
+ *  
+ * This function is used to aquire a NvOsResourceHandle (may be 
+ * more than one) for a designated resource type.  The returned 
+ * handle list is used to retrieve specific details about the 
+ * resource by calling NvOsResouceInfo. 
+ *  
+ * This function may also be used to obtain just the number of 
+ * resources (nResources) if ResourceList is specified as NULL 
+ * by the caller. 
+ *  
+ * If ResourceList is not NULL, this function returns the number 
+ * of resources (nResources) and a pointer to the first resource 
+ * in the array (ResourceList).
+ *  
+ * @see NvOsResouceInfo()
+ *  
+ * @param ResourceType The resource type for which to retrieve a handle.
+ * @param nResources The number of resources in the list.
+ * @param ResourceList Points to the first resource handle in the list.
+ *      If this parameter is NULL, only nResources is returned.
+ */
+NvError
+NvOsListResources(
+    NvOsResource ResourceType,
+    NvU32 *nResources,
+    NvOsResourceHandle *ResourceList);
+
+/**
+ * Gets the resource-specific data for a given
+ * NvOsResourceHandle.  For example, this might include a data
+ * structure which indicates the amount of free space on a
+ * particular storage media.
+ * 
+ * @see NvOsListResources()
+ * @see NvOsResourceStorage
+ *
+ * @param hResource The handle for the resource.
+ * @param InfoSize The size of the resource structure (Info).
+ * @param Info Points to a specific resource information structure. 
+ *  
+ * @retval "NvSuccess" if resource information is valid.
+ * @retval "NvError_FileOperationFailed" if resource info not found.
+ */
+NvError
+NvOsResourceInfo(
+    NvOsResourceHandle hResource,
+    NvU32 InfoSize,
+    void *Info);
+
+/*@}*/
+
+/** @name String Operations
+ */
+/*@{*/
+
+/** Copies a string.
+ *
+ *  @param dest A pointer to the destination of the copy.
+ *  @param src A pointer to the source string.
+ *  @param size The length of the \a dest string buffer plus NULL terminator.
+ */
+void
+NvOsStrncpy(char *dest, const char *src, size_t size);
+
+/** Defines straight-forward mappings to international language encodings.
+ *  Commonly-used encodings on supported operating systems are provided.
+ *  @note NvOS string (and file/directory name) processing functions expect
+ *  UTF-8 encodings. If the system-default encoding is not UTF-8,
+ *  conversion may be required. @see NvUStrConvertCodePage.
+ *
+ **/
+typedef enum
+{
+    NvOsCodePage_Unknown,
+    NvOsCodePage_Utf8,
+    NvOsCodePage_Utf16,
+    NvOsCodePage_Windows1252,
+    NvOsCodePage_Force32 = 0x7fffffffUL,
+} NvOsCodePage;
+
+/** @return The default code page for the system.
+ *
+ */
+NvOsCodePage
+NvOsStrGetSystemCodePage(void);
+
+/** Gets the length of a string.
+ *
+ *  @param s A pointer to the string.
+ */
+size_t
+NvOsStrlen(const char *s);
+
+/** Compares two strings.
+ *
+ *  @param s1 A pointer to the first string.
+ *  @param s2 A pointer to the second string.
+ *
+ *  @return 0 if the strings are identical.
+ */
+int
+NvOsStrcmp(const char *s1, const char *s2);
+
+/** Compares two strings up to the given length.
+ *
+ *  @param s1 A pointer to the first string.
+ *  @param s2 A pointer to the second string.
+ *  @param size The length to compare.
+ *
+ *  @return 0 if the strings are identical.
+ */
+int
+NvOsStrncmp(const char *s1, const char *s2, size_t size);
+
+/*@}*/
+/** @name Memory Operations (Basic)
+ */
+/*@{*/
+
+/** Copies memory.
+ *
+ *  @param dest A pointer to the destination of the copy.
+ *  @param src A pointer to the source memory.
+ *  @param size The length of the copy.
+ */
+void NvOsMemcpy(void *dest, const void *src, size_t size);
+
+/** Compares two memory regions.
+ *
+ *  @param s1 A pointer to the first memory region.
+ *  @param s2 A pointer to the second memory region.
+ *  @param size The length to compare.
+ *
+ *  This returns 0 if the memory regions are identical
+ */
+int
+NvOsMemcmp(const void *s1, const void *s2, size_t size);
+
+/** Sets a region of memory to a value.
+ *
+ *  @param s A pointer to the memory region.
+ *  @param c The value to set.
+ *  @param size The length of the region.
+ */
+void
+NvOsMemset(void *s, NvU8 c, size_t size);
+
+/** Moves memory to a new location (may overlap).
+ *
+ *  @param dest A pointer to the destination memory region.
+ *  @param src A pointer to the source region.
+ *  @param size The size of the region to move.
+ */
+void
+NvOsMemmove(void *dest, const void *src, size_t size);
+
+/**
+ * Like NvOsMemcpy(), but used to safely copy data from an application pointer
+ * (usually embedded inside an \c ioctl() struct) into a driver pointer. Does not
+ * make any assumptions about whether the application pointer is valid--will
+ * return an error instead of crashing if it isn't. Must also validate that
+ * the application pointer points to memory that the application owns; for
+ * example, it should point to the user mode region of the address space and
+ * not the kernel mode region, if such a distinction exists.
+ *
+ * @see NvOsCopyOut
+ *
+ * @param pDst A pointer to the destination (driver).
+ * @param pSrc A pointer to the source (client/application).
+ * @param Bytes The number of bytes to copy.
+ */
+NvError
+NvOsCopyIn(
+    void *pDst,
+    const void *pSrc,
+    size_t Bytes);
+
+/**
+ * Like NvOsMemcpy(), but used to safely copy data to an application pointer
+ * (usually embedded inside an \c ioctl() struct) from a driver pointer. Does not
+ * make any assumptions about whether the application pointer is valid--will
+ * return an error instead of crashing if it isn't. Must also validate that
+ * the application pointer points to memory that the application owns; for
+ * example, it should point to the user mode region of the address space and
+ * not the kernel mode region, if such a distinction exists.
+ *
+ * @see NvOsCopyIn
+ *
+ * @param pDst A pointer to the destination (client/application).
+ * @param pSrc A pointer to the source (driver).
+ * @param Bytes The number of bytes to copy.
+ */
+NvError
+NvOsCopyOut(
+    void *pDst,
+    const void *pSrc,
+    size_t Bytes);
+
+/*@}*/
+/** @name File Input/Output
+ */
+/*@{*/
+
+/**
+ *
+ *  Defines wrappers over stdlib's file stream functions,
+ *  with some changes to the API.
+ */
+typedef enum
+{
+    /** See the fseek manual page for details of Set, Cur, and End. */
+    NvOsSeek_Set = 0,
+    NvOsSeek_Cur = 1,
+    NvOsSeek_End = 2,
+
+    NvOsSeek_Force32 = 0x7FFFFFFF
+} NvOsSeekEnum;
+
+typedef enum
+{
+    NvOsFileType_Unknown = 0,
+    NvOsFileType_File,
+    NvOsFileType_Directory,
+    NvOsFileType_Fifo,
+    NvOsFileType_CharacterDevice,
+    NvOsFileType_BlockDevice,
+
+    NvOsFileType_Force32 = 0x7FFFFFFF
+} NvOsFileType;
+
+typedef struct NvOsStatTypeRec
+{
+    NvU64 size;
+    NvOsFileType type;
+} NvOsStatType;
+
+/** Opens a file with read permissions. */
+#define NVOS_OPEN_READ    0x1
+
+/** Opens a file with write persmissions. */
+#define NVOS_OPEN_WRITE   0x2
+
+/** Creates a file if is not present on the file system. */
+#define NVOS_OPEN_CREATE  0x4
+
+/** Opens a file stream.
+ *
+ *  If the ::NVOS_OPEN_CREATE flag is specified, ::NVOS_OPEN_WRITE must also
+ *  be specified.
+ *
+ *  If \c NVOS_OPEN_WRITE is specified, the file will be opened for write and
+ *  will be truncated if it was previously existing.
+ *
+ *  If \c NVOS_OPEN_WRITE and ::NVOS_OPEN_READ are specified, the file will not
+ *  be truncated.
+ *
+ *  @param path A pointer to the path to the file.
+ *  @param flags Or'd flags for the open operation (\c NVOS_OPEN_*).
+ *  @param [out] file A pointer to the file that will be opened, if successful.
+ */
+NvError
+NvOsFopen(const char *path, NvU32 flags, NvOsFileHandle *file);
+
+/** Closes a file stream.
+ *
+ *  @param stream The file stream to close.
+ *  Passing in a null handle is okay.
+ */
+void NvOsFclose(NvOsFileHandle stream);
+
+/** Writes to a file stream.
+ *
+ *  @param stream The file stream.
+ *  @param ptr A pointer to the data to write.
+ *  @param size The length of the write.
+ *
+ *  @retval NvError_FileWriteFailed Returned on error.
+ */
+NvError
+NvOsFwrite(NvOsFileHandle stream, const void *ptr, size_t size);
+
+/** Reads a file stream.
+ *
+ *  Buffered read implementation if available for a particular OS may
+ *  return corrupted data if multiple threads read from the same
+ *  stream simultaneously.
+ *
+ *  To detect short reads (less that specified amount), pass in \a bytes
+ *  and check its value to the expected value. The \a bytes parameter may
+ *  be null.
+ *
+ *  @param stream The file stream.
+ *  @param ptr A pointer to the buffer for the read data.
+ *  @param size The length of the read.
+ *  @param [out] bytes A pointer to the number of bytes readd; may be null.
+ *
+ *  @retval NvError_FileReadFailed If the file read encountered any
+ *      system errors.
+ */
+NvError
+NvOsFread(NvOsFileHandle stream, void *ptr, size_t size, size_t *bytes);
+
+/** Reads a file stream with timeout.
+ *
+ *  Buffered read implementation if available for a particular OS may
+ *  return corrupted data if multiple threads read from the same
+ *  stream simultaneously.
+ *
+ *  To detect short reads (less that specified amount), pass in \a bytes
+ *  and check its value to the expected value. The \a bytes parameter may
+ *  be null.
+ *
+ *  @param stream The file stream.
+ *  @param ptr A pointer to the buffer for the read data.
+ *  @param size The length of the read.
+ *  @param [out] bytes A pointer to the number of bytes read; may be null.
+ *  @param timeout_msec Timeout for function to return if no bytes available.
+ *
+ *  @retval NvError_FileReadFailed If the file read encountered any
+ *      system errors.
+ *  @retval NvError_Timeout If no bytes are available to read.
+ */
+NvError
+NvOsFreadTimeout(
+    NvOsFileHandle stream,
+    void *ptr,
+    size_t size,
+    size_t *bytes,
+    NvU32 timeout_msec);
+
+/** Gets a character from a file stream.
+ *
+ *  @param stream The file stream.
+ *  @param [out] c A pointer to the character from the file stream.
+ *
+ *  @retval NvError_EndOfFile When the end of file is reached.
+ */
+NvError
+NvOsFgetc(NvOsFileHandle stream, NvU8 *c);
+
+/** Changes the file position pointer.
+ *
+ *  @param file The file.
+ *  @param offset The offset from whence to seek.
+ *  @param whence The starting point for the seek.
+ *
+ *  @retval NvError_FileOperationFailed On error.
+ */
+NvError
+NvOsFseek(NvOsFileHandle file, NvS64 offset, NvOsSeekEnum whence);
+
+/** Gets the current file position pointer.
+ *
+ *  @param file The file.
+ *  @param [out] position A pointer to the file position.
+ *
+ *  @retval NvError_FileOperationFailed On error.
+ */
+NvError
+NvOsFtell(NvOsFileHandle file, NvU64 *position);
+
+/** Gets file information.
+ *
+ *  @param filename A pointer to the file about which to get information.
+ *  @param [out] stat A pointer to the information structure.
+ */
+NvError
+NvOsStat(const char *filename, NvOsStatType *stat);
+
+/** Gets file information from an already open file.
+ *
+ *  @param file The open file.
+ *  @param [out] stat A pointer to the information structure.
+ */
+NvError
+NvOsFstat(NvOsFileHandle file, NvOsStatType *stat);
+
+/** Flushes any pending writes to the file stream.
+ *
+ *  @param stream The file stream.
+ */
+NvError
+NvOsFflush(NvOsFileHandle stream);
+
+/** Commits any pending writes to storage media.
+ *
+ *  After this completes, any pending writes are guaranteed to be on the
+ *  storage media associated with the stream (if any).
+ *
+ *  @param stream The file stream.
+ */
+NvError
+NvOsFsync(NvOsFileHandle stream);
+
+/** Removes a file from the storage media.  If the file is open,
+ *  this function marks the file for deletion upon close.
+ *
+ *  @param filename The file to remove
+ *
+ *  The following error conditions are possible:
+ *  
+ *  NvError_FileOperationFailed - cannot remove file
+ */
+NvError
+NvOsFremove(const char *filename);
+
+/**
+ * Thunk into the device driver implementing this file (usually a device file)
+ * to perform an I/O control (IOCTL) operation.
+ *
+ * @param hFile The file on which to perform the IOCTL operation.
+ * @param IoctlCode The IOCTL code (which operation to perform).
+ * @param pBuffer A pointer to the buffer containing the data for the IOCTL
+ *     operation. This buffer must first consist of \a InBufferSize bytes of
+ *     input-only data, followed by \a InOutBufferSize bytes of input/output
+ *     data, and finally \a OutBufferSize bytes of output-only data. Its total
+ *     size is therefore:
+ * <pre>
+ *     InBufferSize + InOutBufferSize + OutBufferSize
+   </pre>
+ * @param InBufferSize The number of input-only data bytes in the buffer.
+ * @param InOutBufferSize The number of input/output data bytes in the buffer.
+ * @param OutBufferSize The number of output-only data bytes in the buffer.
+ */
+NvError
+NvOsIoctl(
+    NvOsFileHandle hFile,
+    NvU32 IoctlCode,
+    void *pBuffer,
+    NvU32 InBufferSize,
+    NvU32 InOutBufferSize,
+    NvU32 OutBufferSize);
+
+/*@}*/
+/** @name Directories
+ */
+/*@{*/
+
+/** A handle to a directory. */
+typedef struct NvOsDirRec *NvOsDirHandle;
+
+/** Opens a directory.
+ *
+ *  @param path A pointer to the path of the directory to open.
+ *  @param [out] dir A pointer to the directory that will be opened, if successful.
+ *
+ *  @retval NvError_DirOperationFailed Returned upon failure.
+ */
+NvError
+NvOsOpendir(const char *path, NvOsDirHandle *dir);
+
+/** Gets the next entry in the directory.
+ *
+ *  @param dir The directory pointer.
+ *  @param [out] name A pointer to the name of the next file.
+ *  @param size The size of the name buffer.
+ *
+ *  @retval NvError_EndOfDirList When there are no more entries in the
+ *      directory.
+ *  @retval NvError_DirOperationFailed If there is a system error.
+ */
+NvError
+NvOsReaddir(NvOsDirHandle dir, char *name, size_t size);
+
+/** Closes the directory.
+ *
+ *  @param dir The directory to close.
+ *      Passing in a null handle is okay.
+ */
+void NvOsClosedir(NvOsDirHandle dir);
+
+/** Virtual filesystem hook. */
+typedef struct NvOsFileHooksRec {
+
+    NvError (*hookFopen)(
+                    const char *path,
+                    NvU32 flags,
+                    NvOsFileHandle *file );
+    void    (*hookFclose)(
+                    NvOsFileHandle stream);
+    NvError (*hookFwrite)(
+                    NvOsFileHandle stream,
+                    const void *ptr,
+                    size_t size);
+    NvError (*hookFread)(
+                    NvOsFileHandle stream,
+                    void *ptr,
+                    size_t size,
+                    size_t *bytes,
+                    NvU32 timeout_msec);
+    NvError (*hookFseek)(
+                    NvOsFileHandle file,
+                    NvS64 offset,
+                    NvOsSeekEnum whence);
+    NvError (*hookFtell)(
+                    NvOsFileHandle file,
+                    NvU64 *position);
+    NvError (*hookFstat)(
+                    NvOsFileHandle file,
+                    NvOsStatType *stat);
+    NvError (*hookStat)(
+                    const char *filename,
+                    NvOsStatType *stat);
+    NvError (*hookFflush)(
+                    NvOsFileHandle stream);
+    NvError (*hookFsync)(
+                    NvOsFileHandle stream);
+    NvError (*hookFremove)(
+                    const char *filename);
+    NvError (*hookOpendir)(
+                    const char *path,
+                    NvOsDirHandle *dir);
+    NvError (*hookReaddir)(
+                    NvOsDirHandle dir,
+                    char *name,
+                    size_t size);
+    void    (*hookClosedir)(
+                    NvOsDirHandle dir);
+} NvOsFileHooks;
+
+/** Sets up hook functions for extra stream functionality.
+ *
+ *  @note All function pointers must be non-NULL.
+ *
+ *  @param newHooks A pointer to the new set of functions to handle file I/O.
+ *  NULL for defaults.
+ */
+const NvOsFileHooks *NvOsSetFileHooks(NvOsFileHooks *newHooks);
+
+/* configuration variables (in place of getenv) */
+
+/** Retrives an unsigned integer variable from the environment.
+ *
+ *  @param name A pointer to the name of the variable.
+ *  @param [out] value A pointer to the value to write.
+ *
+ *  @retval NvError_ConfigVarNotFound If the name isn't found in the
+ *      environment.
+ *  @retval NvError_InvalidConfigVar If the configuration variable cannot
+ *      be converted into an unsiged integer.
+ */
+NvError
+NvOsGetConfigU32(const char *name, NvU32 *value);
+
+/** Retreives a string variable from the environment.
+ *
+ *  @param name A pointer to the name of the variable.
+ *  @param value A pointer to the value to write into.
+ *  @param size The size of the value buffer.
+ *
+ *  @retval NvError_ConfigVarNotFound If the name isn't found in the
+ *      environment.
+ */
+NvError
+NvOsGetConfigString(const char *name, char *value, NvU32 size);
+
+/*@}*/
+/** @name Memory Allocation
+ */
+/*@{*/
+
+/** Dynamically allocates memory.
+ *  Alignment, if desired, must be done by the caller.
+ *
+ *  @param size The size of the memory to allocate.
+ */
+void *NvOsAlloc(size_t size);
+
+/** Re-sizes a previous dynamic allocation.
+ *
+ *  @param ptr A pointer to the original allocation.
+ *  @param size The new size to allocate.
+ */
+void *NvOsRealloc(void *ptr, size_t size);
+
+/** Frees a dynamic memory allocation.
+ *
+ *  Freeing a null value is okay.
+ *
+ *  @param ptr A pointer to the memory to free, which should be from
+ *      NvOsAlloc().
+ */
+void NvOsFree(void *ptr);
+
+/**
+ * Alocates a block of executable memory.
+ *
+ * @param size The size of the memory to allocate.
+ */
+void *NvOsExecAlloc(size_t size);
+
+/**
+ * Frees a block of executable memory.
+ *
+ * @param ptr A pointer from NvOsExecAlloc() to the memory to free; may be null.
+ * @param size The size of the allocation.
+ */
+void NvOsExecFree(void *ptr, size_t size);
+
+/** An opaque handle returned by shared memory allocations.
+ */
+typedef struct NvOsSharedMemRec *NvOsSharedMemHandle;
+
+/** Dynamically allocates multiprocess shared memory.
+ *
+ *  The memory will be zero initialized when it is first created.
+ *
+ *  @param key A pointer to the global key to identify the shared allocation.
+ *  @param size The size of the allocation.
+ *  @param [out] descriptor A pointer to the result descriptor.
+ *
+ *  @return If the shared memory for \a key already exists, then this returns
+ *  the already allcoated shared memory; otherwise, it creates it.
+ */
+NvError
+NvOsSharedMemAlloc(const char *key, size_t size,
+    NvOsSharedMemHandle *descriptor);
+
+/** Maps a shared memory region into the process virtual memory.
+ *
+ *  @param descriptor The memory descriptor to map.
+ *  @param offset The offset in bytes into the mapped area.
+ *  @param size The size area to map.
+ *  @param [out] ptr A pointer to the result pointer.
+ *
+ *  @retval NvError_SharedMemMapFailed Returned on failure.
+ */
+NvError
+NvOsSharedMemMap(NvOsSharedMemHandle descriptor, size_t offset,
+    size_t size, void **ptr);
+
+/** Unmaps a mapped region of shared memory.
+ *
+ *  @param ptr A pointer to the pointer to virtual memory.
+ *  @param size The size of the mapped region.
+ */
+void NvOsSharedMemUnmap(void *ptr, size_t size);
+
+/** Frees shared memory from NvOsSharedMemAlloc().
+ *
+ *  It is valid to call \c NvOsSharedMemFree while mappings are still
+ *  outstanding.
+ *
+ *  @param descriptor The memory descriptor.
+ */
+void NvOsSharedMemFree(NvOsSharedMemHandle descriptor);
+
+/** Defines memory attributes. */
+typedef enum
+{
+    NvOsMemAttribute_Uncached      = 0,
+    NvOsMemAttribute_WriteBack     = 1,
+    NvOsMemAttribute_WriteCombined = 2,
+
+    NvOsMemAttribute_Force32 = 0x7FFFFFFF
+} NvOsMemAttribute;
+
+/** Specifies no memory flags. */
+#define NVOS_MEM_NONE     0x0
+
+/** Specifies the memory may be read. */
+#define NVOS_MEM_READ     0x1
+
+/** Specifies the memory may be written to. */
+#define NVOS_MEM_WRITE    0x2
+
+/** Specifies the memory may be executed. */
+#define NVOS_MEM_EXECUTE  0x4
+
+/**
+ * The memory must be visible by all processes, this is only valid for
+ * WinCE 5.0.
+ */
+#define NVOS_MEM_GLOBAL_ADDR 0x8
+
+/** The memory may be both read and writen. */
+#define NVOS_MEM_READ_WRITE (NVOS_MEM_READ | NVOS_MEM_WRITE)
+
+/** Maps computer resources into user space.
+ *
+ *  @param phys The physical address start.
+ *  @param size The size of the aperture.
+ *  @param attrib Memory attributes (caching).
+ *  @param flags Bitwise OR of \c NVOS_MEM_*.
+ *  @param [out] ptr A pointer to the result pointer.
+ */
+NvError
+NvOsPhysicalMemMap(NvOsPhysAddr phys, size_t size,
+    NvOsMemAttribute attrib, NvU32 flags, void **ptr);
+
+/** Maps computer resources into user space.
+ *
+ * This function is intended to be called by device drivers only,
+ * and will fail in user space. The virtual address can be allocated
+ * by calling NvRmOsPhysicalMemMap() with flags set to ::NVOS_MEM_NONE, which
+ * should be done by the calling process. That virtual region will be
+ * passed to some device driver, and this function will set up the
+ * PTEs to make the virtual space point to the supplied physical
+ * address.
+ *
+ * This is used by NvRmMemMap() to map memory under WinCE6 where user
+ * mode applications cannot map physical memory directly.
+ *
+ *  @param pCallerPtr A pointer to the virtual address from the calling process.
+ *  @param phys The physical address start.
+ *  @param size The size of the aperture.
+ *  @param attrib Memory attributes (caching).
+ *  @param flags Bitwise OR of NVOS_MEM_*.
+ */
+NvError
+NvOsPhysicalMemMapIntoCaller(void *pCallerPtr, NvOsPhysAddr phys,
+    size_t size, NvOsMemAttribute attrib, NvU32 flags);
+
+/**
+ * Releases resources previously allocated by NvOsPhysicalMemMap().
+ *
+ * @param ptr The virtual pointer returned by \c NvOsPhysicalMemMap. If this
+ *     pointer is null, this function has no effect.
+ * @param size The size of the mapped region.
+ */
+void NvOsPhysicalMemUnmap(void *ptr, size_t size);
+
+/*@}*/
+/** @name Page Allocator
+ */
+/*@{*/
+
+/** 
+ *  Low-level memory allocation of the external system memory.
+ */
+typedef enum
+{
+    NvOsPageFlags_Contiguous    = 0,
+    NvOsPageFlags_NonContiguous = 1,
+
+    NvOsMemFlags_Forceword = 0x7ffffff,
+} NvOsPageFlags;
+
+typedef struct NvOsPageAllocRec *NvOsPageAllocHandle;
+
+/** Allocates memory via the page allocator.
+ *
+ *  @param size The number of bytes to allocate.
+ *  @param attrib Page caching attributes.
+ *  @param flags Various memory allocation flags.
+ *  @param protect Page protection attributes (\c NVOS_MEM_*).
+ *  @param [out] descriptor A pointer to the result descriptor.
+ *
+ *  @return A descriptor (not a pointer to virtual memory),
+ *  which may be passed into other functions.
+ */
+NvError
+NvOsPageAlloc(size_t size, NvOsMemAttribute attrib,
+    NvOsPageFlags flags, NvU32 protect, NvOsPageAllocHandle *descriptor);
+
+/**
+ * Locks down the pages in a region of memory and provides a descriptor that can
+ * be used to query the PTEs. Locked pages are guaranteed to not be swapped
+ * out or moved by the OS. To unlock the pages when done, call NvOsPageFree()
+ * on the resulting descriptor.
+ *
+ * @param ptr Pointer to the buffer to lock down.
+ * @param size Number of bytes in the buffer to lock down.
+ * @param protect Page protection attributes (NVOS_MEM_*)
+ * @param [out] descriptor Output parameter to pass back the descriptor.
+ *
+ * @retval NvSuccess If successful, or the appropriate error code.
+ * @note Some operating systems may not support this operation and will return
+ *     \a NvError_NotImplemented to all requests.
+ */
+NvError
+NvOsPageLock(void *ptr, size_t size, NvU32 protect, NvOsPageAllocHandle *descriptor);
+
+/** Frees pages from NvOsPageAlloc().
+ *
+ *  It is not valid to call NvOsPageFree() while there are outstanding
+ *  mappings.
+ *
+ *  @param descriptor The descriptor from \c NvOsPageAlloc.
+ */
+void
+NvOsPageFree(NvOsPageAllocHandle descriptor);
+
+/** Maps pages into the virtual address space.
+ *
+ *  Upon successful completion, \a *ptr holds a virtual address
+ *  that may be accessed.
+ *
+ *  @param descriptor Allocated pages from NvOsPageAlloc(), etc.
+ *  @param offset Offset in bytes into the page range.
+ *  @param size The size of the mapping.
+ *  @param [out] ptr A pointer to the result pointer.
+ *
+ * @retval NvSuccess If successful, or the appropriate error code.
+ */
+NvError
+NvOsPageMap(NvOsPageAllocHandle descriptor, size_t offset, size_t size,
+    void **ptr);
+
+/** Maps pages into the provided virtual address space.
+ *
+ *  Virtual address space can be obtained by calling
+ *  NvOsPhysicalMemMap() and passing ::NVOS_MEM_NONE for the
+ *  flags parameter.
+ * 
+ * @note You should only use this function if you really, really
+ *       know what you are doing(1).
+ *
+ *  Upon successful completion, \a *ptr holds a virtual address
+ *  that may be accessed.
+ *
+ *  @param descriptor Allocated pages from NvOsPageAlloc(), etc.
+ *  @param pCallerPtr Pointer to user supplied virtual address space.
+ *  @param offset Offset in bytes into the page range
+ *  @param size The size of the mapping
+ *
+ * @retval NvSuccess If successful, or the appropriate error code.
+ */
+NvError
+NvOsPageMapIntoPtr(NvOsPageAllocHandle descriptor, void *pCallerPtr,
+    size_t offset, size_t size);
+
+/** Unmaps the virtual address from NvOsPageMap().
+ *
+ *  @param descriptor Allocated pages from NvOsPageAlloc(), etc.
+ *  @param ptr A pointer to the virtual address to unmap that was returned
+ *      from \c NvOsPageMap.
+ *  @param size The size of the mapping, which should match what
+ *   was passed into \c NvOsPageMap.
+ */
+void
+NvOsPageUnmap(NvOsPageAllocHandle descriptor, void *ptr, size_t size);
+
+/** Returns the physical address given an offset.
+ *
+ *  This is useful for non-contiguous page allocations.
+ *
+ *  @param descriptor The descriptor from NvOsPageAlloc(), etc.
+ *  @param offset The offset in bytes into the page range.
+ */
+NvOsPhysAddr
+NvOsPageAddress(NvOsPageAllocHandle descriptor, size_t offset);
+
+/*@}*/
+/** @name Dynamic Library Handling
+ */
+/*@{*/
+
+/** A handle to a dynamic library. */
+typedef struct NvOsLibraryRec *NvOsLibraryHandle;
+
+/** Load a dynamic library.
+ *
+ *  No operating system specific suffixes or paths should be used for the
+ *  library name. So do not use:
+ *  <pre>
+        /usr/lib/libnvos.so
+        libnvos.dll
+    </pre>
+ * Just use:
+ *  <pre>
+    libnvos 
+   </pre>
+ *
+ *  @param name A pointer to the library name.
+ *  @param [out] library A pointer to the result library.
+ *
+ *  @retval NvError_LibraryNotFound If the library cannot be opened.
+ */
+NvError
+NvOsLibraryLoad(const char *name, NvOsLibraryHandle *library);
+
+/** Gets an address of a symbol in a dynamic library.
+ *
+ *  @param library The dynamic library.
+ *  @param symbol A pointer to the symbol to lookup.
+ *
+ *  @return The address of the symbol, or NULL if the symbol cannot be found.
+ */
+void*
+NvOsLibraryGetSymbol(NvOsLibraryHandle library, const char *symbol);
+
+/** Unloads a dynamic library.
+ *
+ *  @param library The dynamic library to unload.
+ *      It is okay to pass a null \a library value.
+ */
+void
+NvOsLibraryUnload(NvOsLibraryHandle library);
+
+/*@}*/
+/** @name Syncronization Objects and Thread Management
+ */
+/*@{*/
+
+typedef struct NvOsMutexRec *NvOsMutexHandle;
+typedef struct NvOsIntrMutexRec *NvOsIntrMutexHandle;
+typedef struct NvOsSpinMutexRec *NvOsSpinMutexHandle;
+typedef struct NvOsSemaphoreRec *NvOsSemaphoreHandle;
+typedef struct NvOsThreadRec *NvOsThreadHandle;
+
+/** Unschedules the calling thread for at least the given
+ *      number of milliseconds.
+ *
+ *  Other threads may run during the sleep time.
+ *
+ *  @param msec The number of milliseconds to sleep.
+ */
+void
+NvOsSleepMS(NvU32 msec);
+
+/** Stalls the calling thread for at least the given number of
+ *  microseconds. The actual time waited might be longer; you cannot
+ *  depend on this function for precise timing.
+ *
+ *  @note It is safe to use this function at ISR time.
+ *
+ *  @param usec The number of microseconds to wait.
+ */
+void
+NvOsWaitUS(NvU32 usec);
+
+/**
+ * Allocates a new (intra-process) mutex.
+ *
+ * @note Mutexes can be locked recursively; if a thread owns the lock,
+ * it can lock it again as long as it unlocks it an equal number of times.
+ *
+ * @param mutex The mutex to initialize.
+ *
+ * @return \a NvError_MutexCreateFailed, or one of common error codes on
+ * failure.
+ */
+NvError NvOsMutexCreate(NvOsMutexHandle *mutex);
+
+/** Locks the given unlocked mutex.
+ *
+ *  If a process is holding a lock on a multi-process mutex when it terminates,
+ *  this lock will be automatically released.
+ *
+ *  @param mutex The mutex to lock; note that this is a recursive lock.
+ */
+void NvOsMutexLock(NvOsMutexHandle mutex);
+
+/** Unlocks a locked mutex.
+ *
+ *  A mutex must be unlocked exactly as many times as it has been locked.
+ *
+ *  @param mutex The mutex to unlock.
+ */
+void NvOsMutexUnlock(NvOsMutexHandle mutex);
+
+/** Frees the resources held by a mutex.
+ *
+ *  Mutecies are reference counted across the computer (multiproceses),
+ *  and a given mutex will not be destroyed until the last reference has
+ *  gone away.
+ *
+ *  @param mutex The mutex to destroy. Passing in a null mutex is okay.
+ */
+void NvOsMutexDestroy(NvOsMutexHandle mutex);
+
+/**
+ * Creates a mutex that is safe to aquire in an ISR.
+ *
+ * @param mutex A pointer to the mutex is stored here on success.
+ */
+NvError NvOsIntrMutexCreate(NvOsIntrMutexHandle *mutex);
+
+/**
+ * Aquire an ISR-safe mutex.
+ *
+ * @param mutex The mutex to lock. For kernel (OAL) implementations,
+ *     NULL implies the system-wide lock will be used.
+ */
+void NvOsIntrMutexLock(NvOsIntrMutexHandle mutex);
+
+/**
+ * Releases an ISR-safe mutex.
+ *
+ * @param mutex The mutex to unlock. For kernel (OAL) implementations,
+ *     NULL implies the system-wide lock will be used.
+ */
+void NvOsIntrMutexUnlock(NvOsIntrMutexHandle mutex);
+
+/**
+ * Destroys an ISR-safe mutex.
+ *
+ * @param mutex The mutex to destroy. If \a mutex is NULL, this API has no
+ *     effect.
+ */
+void NvOsIntrMutexDestroy(NvOsIntrMutexHandle mutex);
+
+/**
+ * Creates a spin mutex.
+ * This mutex is SMP safe, but it is not ISR-safe.
+ *
+ * @param mutex A pointer to the mutex is stored here on success.
+ */
+NvError NvOsSpinMutexCreate(NvOsSpinMutexHandle *mutex);
+
+/**
+ * Acquire a spin mutex.
+ * Spins until mutex is acquired; when acquired disables kernel preemption.
+ *
+ * @param mutex The mutex handle to lock.
+ */
+void NvOsSpinMutexLock(NvOsSpinMutexHandle mutex);
+
+/**
+ * Releases a spin mutex.
+ *
+ * @param mutex The mutex handle to unlock.
+ */
+void NvOsSpinMutexUnlock(NvOsSpinMutexHandle mutex);
+
+/**
+ * Destroys a spin mutex.
+ *
+ * @param mutex The mutex to destroy. If \a mutex is NULL, this API has no
+ *     effect.
+ */
+void NvOsSpinMutexDestroy(NvOsSpinMutexHandle mutex);
+
+/**
+ * Creates a counting semaphore.
+ *
+ * @param semaphore A pointer to the semaphore to initialize.
+ * @param value The initial semaphore value.
+ *
+ * @retval NvSuccess If successful, or the appropriate error code.
+ */
+NvError
+NvOsSemaphoreCreate(NvOsSemaphoreHandle *semaphore, NvU32 value);
+
+/**
+ * Creates a duplicate semaphore from the given semaphore.
+ * Freeing the original semaphore has no effect on the new semaphore.
+ *
+ * @param orig The semaphore to duplicate.
+ * @param semaphore A pointer to the new semaphore.
+ *
+ * @retval NvSuccess If successful, or the appropriate error code.
+ */
+NvError
+NvOsSemaphoreClone( NvOsSemaphoreHandle orig,  NvOsSemaphoreHandle *semaphore);
+
+/**
+ * Obtains a safe, usable handle to a semaphore passed across an ioctl()
+ * interface by a client to a device driver. Validates that the original
+ * semaphore handle is legal, and creates a new handle (valid in the driver's
+ * process/address space) that the client cannot asynchronously destroy.
+ *
+ * The new handle must be freed, just like any other semaphore handle, by
+ * passing it to NvOsSemaphoreDestroy().
+ *
+ * @param hClientSema The client's semaphore handle.
+ * @param phDriverSema If successful, returns a new handle to the semaphore
+ *     that the driver can safely use.
+ *
+ * @retval NvSuccess If successful, or the appropriate error code.
+ */
+NvError
+NvOsSemaphoreUnmarshal( NvOsSemaphoreHandle hClientSema,
+    NvOsSemaphoreHandle *phDriverSema);
+
+/** Waits until the semaphore value becomes non-zero, then
+ *  decrements the value and returns.
+ *
+ *  @param semaphore The semaphore to wait for.
+ */
+void NvOsSemaphoreWait(NvOsSemaphoreHandle semaphore);
+
+/**
+ * Waits for the given semaphore value to become non-zero with timeout. If
+ * the semaphore value becomes non-zero before the timeout, then the value is
+ * decremented and \a NvSuccess is returned.
+ *
+ * @param semaphore The semaphore to wait for.
+ * @param msec Timeout value in milliseconds.
+ *     ::NV_WAIT_INFINITE can be used to wait forever.
+ *
+ * @retval NvError_Timeout If the wait expires.
+ */
+NvError
+NvOsSemaphoreWaitTimeout(NvOsSemaphoreHandle semaphore, NvU32 msec);
+
+/** Increments the semaphore value.
+ *
+ *  @param semaphore The semaphore to signal.
+ */
+void
+NvOsSemaphoreSignal(NvOsSemaphoreHandle semaphore);
+
+/** Frees resources held by the semaphore.
+ *
+ *  Semaphores are reference counted across the computer (multiproceses),
+ *  and a given semaphore will not be destroyed until the last reference has
+ *  gone away.
+ *
+ *  @param semaphore The semaphore to destroy.
+ *      Passing in a null semaphore is okay (no op).
+ */
+void
+NvOsSemaphoreDestroy(NvOsSemaphoreHandle semaphore);
+
+/** Sets thread mode.
+ *
+ * @pre If this is called, it must be called before any other threading function.
+ * All but the first call to this function do nothing and return
+ * \a NvError_AlreadyAllocated.
+ *
+ * @param coop 0 to disable coop mode, and 1 to enable coop mode.
+ *
+ * @returns NvSuccess On success.
+ * @returns NvError_AlreadyAllocated If called previously.
+ */
+NvError NvOsThreadMode(int coop);
+
+/** Entry point for a thread.
+ */
+typedef void (*NvOsThreadFunction)(void *args);
+
+/** Creates a thread.
+ *
+ *  @param function The thread entry point.
+ *  @param args A pointer to the thread arguments.
+ *  @param [out] thread A pointer to the result thread ID structure.
+ */
+NvError
+NvOsThreadCreate( NvOsThreadFunction function, void *args,
+    NvOsThreadHandle *thread);
+
+/** Creates a near interrupt priority thread.
+ *
+ *  @param function The thread entry point.
+ *  @param args A pointer to the thread arguments.
+ *  @param [out] thread A pointer to the result thread ID structure.
+ */
+NvError
+NvOsInterruptPriorityThreadCreate( NvOsThreadFunction function, void *args,
+    NvOsThreadHandle *thread);
+
+/**
+ * Sets the thread's priority to low priority.
+ *
+ * @retval NvError_NotSupported May be returned.
+ */
+NvError NvOsThreadSetLowPriority(void);
+
+/** Waits for the given thread to exit.
+ *
+ *  The joined thread will be destroyed automatically. All OS resources
+ *  will be reclaimed. There is no method for terminating a thread
+ *  before it exits naturally.
+ *
+ *  @param thread The thread to wait for.
+ *  Passing in a null thread ID is okay (no op).
+ */
+void NvOsThreadJoin(NvOsThreadHandle thread);
+
+/** Yields to another runnable thread.
+ */
+void NvOsThreadYield(void);
+
+/**
+ * Atomically compares the contents of a 32-bit memory location with a value,
+ * and if they match, updates it to a new value. This function is the
+ * equivalent of the following code, except that other threads or processors
+ * are effectively prevented from reading or writing \a *pTarget while we are
+ * inside the function.
+ *
+ * @code
+ * NvS32 OldTarget = *pTarget;
+ * if (OldTarget == OldValue)
+ *     *pTarget = NewValue;
+ * return OldTarget;
+ * @endcode
+ */
+NvS32 NvOsAtomicCompareExchange32(NvS32 *pTarget, NvS32 OldValue, NvS32
+    NewValue);
+
+/**
+ * Atomically swaps the contents of a 32-bit memory location with a value. This
+ * function is the equivalent of the following code, except that other threads
+ * or processors are effectively prevented from reading or writing \a *pTarget
+ * while we are inside the function.
+ *
+ * @code
+ * NvS32 OldTarget = *pTarget;
+ * *pTarget = Value;
+ * return OldTarget;
+ * @endcode
+ */
+NvS32 NvOsAtomicExchange32(NvS32 *pTarget, NvS32 Value);
+
+/**
+ * Atomically increments the contents of a 32-bit memory location by a specified
+ * amount. This function is the equivalent of the following code, except that
+ * other threads or processors are effectively prevented from reading or
+ * writing \a *pTarget while we are inside the function.
+ *
+ * @code
+ * NvS32 OldTarget = *pTarget;
+ * *pTarget = OldTarget + Value;
+ * return OldTarget;
+ * @endcode
+ */
+NvS32 NvOsAtomicExchangeAdd32(NvS32 *pTarget, NvS32 Value);
+
+/** A TLS index that is guaranteed to be invalid. */
+#define NVOS_INVALID_TLS_INDEX 0xFFFFFFFF
+#define NVOS_TLS_CNT            4
+
+/**
+ * Allocates a thread-local storage variable. All TLS variables have initial
+ * value NULL in all threads when first allocated.
+ *
+ * @returns The TLS index of the TLS variable if successful, or
+ *     ::NVOS_INVALID_TLS_INDEX if not.
+ */
+NvU32 NvOsTlsAlloc(void);
+
+/**
+ * Frees a thread-local storage variable.
+ *
+ * @param TlsIndex The TLS index of the TLS variable. This function is a no-op
+ *     if TlsIndex equals ::NVOS_INVALID_TLS_INDEX.
+ */
+void NvOsTlsFree(NvU32 TlsIndex);
+
+/**
+ * Gets the value of a thread-local storage variable.
+ *
+ * @param TlsIndex The TLS index of the TLS variable.
+ *     The current value of the TLS variable is returned.
+ */
+void *NvOsTlsGet(NvU32 TlsIndex);
+
+/**
+ * Sets the value of a thread-local storage variable.
+ *
+ * @param TlsIndex The TLS index of the TLS variable.
+ * @param Value A pointer to the new value of the TLS variable.
+ */
+void NvOsTlsSet(NvU32 TlsIndex, void *Value);
+
+/*@}*/
+/** @name Time Functions
+ */
+/*@{*/
+
+/** @return The system time in milliseconds.
+ *
+ *  The returned values are guaranteed to be monotonically increasing,
+ *  but may wrap back to zero (after about 50 days of runtime).
+ *
+ *  In some systems, this is the number of milliseconds since power-on,
+ *  or may actually be an accurate date.
+ */
+NvU32
+NvOsGetTimeMS(void);
+
+/** @return The system time in microseconds.
+ *
+ *  The returned values are guaranteed to be monotonically increasing,
+ *  but may wrap back to zero.
+ *
+ *  Some systems cannot gauantee a microsecond resolution timer.
+ *  Even though the time returned is in microseconds, it is not gaurnateed
+ *  to have micro-second resolution.
+ *
+ *  Please be advised that this API is mainly used for code profiling and
+ *  meant to be used direclty in driver code.
+ */
+NvU64
+NvOsGetTimeUS(void);
+
+/*@}*/
+/** @name CPU Cache
+ *  Cache operations for both instruction and data cache, implemented
+ *  per processor.
+ */
+/*@{*/
+
+/** Writes back the entire data cache.
+ */
+void
+NvOsDataCacheWriteback(void);
+
+/** Writes back and invalidates the entire data cache.
+ */
+void
+NvOsDataCacheWritebackInvalidate(void);
+
+/** Writes back a range of the data cache.
+ *
+ *  @param start A pointer to the start address.
+ *  @param length The number of bytes to write back.
+ */
+void
+NvOsDataCacheWritebackRange(void *start, NvU32 length);
+
+/** Writes back and invlidates a range of the data cache.
+ *
+ *  @param start A pointer to the start address.
+ *  @param length The number of bytes to write back.
+ */
+void
+NvOsDataCacheWritebackInvalidateRange(void *start, NvU32 length);
+
+/** Invalidates the entire instruction cache.
+ */
+void
+NvOsInstrCacheInvalidate(void);
+
+/** Invalidates a range of the instruction cache.
+ *
+ *  @param start A pointer to the start address.
+ *  @param length The number of bytes.
+ */
+void
+NvOsInstrCacheInvalidateRange(void *start, NvU32 length);
+
+/** Flushes the CPU's write combine buffer.
+ */
+void
+NvOsFlushWriteCombineBuffer(void);
+
+/** Interrupt handler function.
+ */
+typedef void (*NvOsInterruptHandler)(void *args);
+
+/** Interrupt handler type.
+ */
+typedef struct NvOsInterruptRec *NvOsInterruptHandle;
+
+/**
+ * Registers the interrupt handler with the IRQ number.
+ *
+ * @note This function is intended to @b only be called
+ *       from NvRmInterruptRegister().
+ *
+ * @param IrqListSize Size of the \a IrqList passed in for registering the IRQ
+ *      handlers for each IRQ number.
+ * @param pIrqList Array of IRQ numbers for which interupt handlers are to be
+ *     registerd.
+ * @param pIrqHandlerList A pointer to an array of interrupt routines to be
+ *      called when an interrupt occurs.
+ * @param context A pointer to the register's context handle.
+ * @param handle A pointer to the interrupt handle.
+ * @param InterruptEnable If true, immediately enable interrupt.  Otherwise
+ *      enable interrupt only after calling NvOsInterruptEnable().
+ *
+ * @retval NvError_IrqRegistrationFailed If the interrupt is already registered.
+ * @retval NvError_BadParameter If the IRQ number is not valid.
+ */
+NvError
+NvOsInterruptRegister(NvU32 IrqListSize,
+    const NvU32 *pIrqList,
+    const NvOsInterruptHandler *pIrqHandlerList,
+    void *context,
+    NvOsInterruptHandle *handle,
+    NvBool InterruptEnable);
+
+/**
+ * Unregisters the interrupt handler from the associated IRQ number.
+ *
+ * @note This function is intended to @b only be called
+ *       from NvRmInterruptUnregister().
+ *
+ * @param handle interrupt Handle returned when a successfull call is made to
+ *     NvOsInterruptRegister().
+ */
+void
+NvOsInterruptUnregister(NvOsInterruptHandle handle);
+
+/**
+ * Enables the interrupt handler with the IRQ number.
+ *
+ * @note This function is intended to @b only be called
+ *       from NvOsInterruptRegister() and NvRmInterruptRegister().
+ *
+ * @param handle Interrupt handle returned when a successfull call is made to
+ *     \c NvOsInterruptRegister.
+ *
+ * @retval NvError_BadParameter If the handle is not valid.
+ * @retval NvError_InsufficientMemory If interrupt enable failed.
+ * @retval NvSuccess If interrupt enable is successful.
+ */
+NvError
+NvOsInterruptEnable(NvOsInterruptHandle handle);
+
+/**
+ *  Called when the ISR/IST is done handling the interrupt.
+ *
+ *  @note This API should be called only from NvRmInterruptDone().
+ *
+ * @param handle Interrupt handle returned when a successfull call is made to
+ *     NvOsInterruptRegister().
+ */
+void
+NvOsInterruptDone(NvOsInterruptHandle handle);
+
+/**
+ * Mask/unmask an interrupt.
+ *
+ * Drivers can use this API to fend off interrupts. Mask means no interrupts
+ * are forwarded to the CPU. Unmask means, interrupts are forwarded to the
+ * CPU. In case of SMP systems, this API masks the interrutps to all the CPUs,
+ * not just the calling CPU.
+ *
+ * @param handle    Interrupt handle returned by NvOsInterruptRegister().
+ * @param mask      NV_FALSE to forward the interrupt to CPU; NV_TRUE to
+ *     mask the interrupts to CPU.
+ */
+void NvOsInterruptMask(NvOsInterruptHandle handle, NvBool mask);
+
+#define NVOS_MAX_PROFILE_APERTURES  (4UL)
+
+/**
+ * Profile aperture sizes.
+ *
+ * Code may execute and be profiled from mutliple apertures. This will get the
+ * size of each aperture. The caller is expected to allocate the number of
+ * bytes for each aperture into a single void* array (void**), which will be
+ * used in NvOsProfileStart() and NvOsProfileStop().
+ *
+ * This may be called twice, the first time to get the number of apertures
+ * (sizes should be null), and the second time with the sizes parameter
+ * non-null. Alternately, ::NVOS_MAX_PROFILE_APERTURES may be used as the
+ * size of the sizes array.
+ *
+ * @param apertures A pointer to the number of apertures that will be profiled.
+ * @param sizes A pointer to the size of each aperture.
+ */
+void
+NvOsProfileApertureSizes( NvU32 *apertures, NvU32 *sizes );
+
+/**
+ * Enables statistical profiling.
+ *
+ * @param apertures A pointer to an array of storage for profile data.
+ */
+void
+NvOsProfileStart( void **apertures );
+
+/**
+ * Stops profiling and prepares the profile samples for analysis.
+ *
+ * @param apertures A pointer to the storage for the profile samples.
+ */
+void
+NvOsProfileStop( void **apertures );
+
+/**
+ * Writes profile data to the given file.
+ *
+ * @post This is expected to close the file after a successful write.
+ *
+ * @param file The file to write to.
+ * @param index The aperture number.
+ * @param aperture A pointer to the storage for the profile samples.
+ */
+NvError
+NvOsProfileWrite( NvOsFileHandle file, NvU32 index, void *aperture );
+
+/**
+ * Sets the boot arguments from thet system's boot loader. The data may be keyed.
+ *
+ * @param key The key for the argument.
+ * @param arg A pointer to the argument to store.
+ * @param size The size of the argument in bytes.
+ *
+ * @retval NvSuccess If successful, or the appropriate error code.
+ */
+NvError
+NvOsBootArgSet( NvU32 key, void *arg, NvU32 size );
+
+/**
+ * Retrieves the system boot arguments. Requires the same key from
+ * NvOsBootArgSet().
+ *
+ * @param key The key for the argument.
+ * @param arg A pointer to the argument buffer.
+ * @param size The size of the argument in bytes.
+ */
+NvError
+NvOsBootArgGet( NvU32 key, void *arg, NvU32 size );
+
+/*
+ * Tracing support. Enable with NVOS_TRACE in nvos_trace.h.
+ */
+#if NVOS_TRACE || NV_DEBUG
+
+#if NV_DEBUG
+void *NvOsAllocLeak( size_t size, const char *f, int l );
+void *NvOsReallocLeak( void *ptr, size_t size, const char *f, int l );
+void NvOsFreeLeak( void *ptr, const char *f, int l );
+#endif
+
+static NV_INLINE void *NvOsAllocTraced(size_t size, const char *f, int l)
+{
+    void *ptr;
+
+#if NV_DEBUG
+    ptr = (NvOsAllocLeak)(size, f, l);
+#else
+    ptr = (NvOsAlloc)(size);
+#endif
+#if NVOS_TRACE
+    NVOS_TRACE_LOG_PRINTF(("NvOsAlloc, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)ptr));
+#endif
+
+    return ptr;
+}
+
+static NV_INLINE void *NvOsReallocTraced(void *ptr, size_t size, const char *f,
+    int l )
+{
+    void* ret;
+
+#if NV_DEBUG
+    ret = (NvOsReallocLeak)(ptr, size, f, l);
+#else
+    ret = (NvOsRealloc)(ptr, size);
+#endif
+#if NVOS_TRACE
+    NVOS_TRACE_LOG_PRINTF(("NvOsRealloc, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)ret));
+#endif
+
+    return ret;
+}
+
+static NV_INLINE void NvOsFreeTraced(void *ptr, const char *f, int l )
+{
+
+#if NV_DEBUG
+    (NvOsFreeLeak)(ptr, f, l);
+#else
+    (NvOsFree)(ptr);
+#endif
+#if NVOS_TRACE
+    NVOS_TRACE_LOG_PRINTF(("NvOsFree, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)ptr));
+#endif
+}
+
+
+#define NvOsAlloc(size) NvOsAllocTraced(size, __FILE__, __LINE__)
+#define NvOsRealloc(ptr, size) \
+    NvOsReallocTraced(ptr, size, __FILE__, __LINE__)
+#define NvOsFree(ptr) NvOsFreeTraced(ptr, __FILE__, __LINE__)
+
+#endif /* NVOS_TRACE */
+
+
+#if (NVOS_TRACE || NV_DEBUG)
+
+/**
+ * Sets the file and line corresponding to a resource allocation.
+ * Call will fill file and line for the most recently stored 
+ * allocation location, if not already set.
+ *
+ * @param userptr A pointer to used by client to identify resource. 
+ *     Can be NULL, which leads to no-op.
+ * @param file A pointer to the name of the file from which allocation 
+ *     originated. Value cannot be NULL; use "" for an empty string.
+ * @param l The line.
+ */
+void NvOsSetResourceAllocFileLine(void* userptr, const char* file, int line);
+
+static NV_INLINE void *
+NvOsExecAllocTraced(size_t size, const char *f, int l )
+{
+    void* ret;
+    ret = (NvOsExecAlloc)(size);
+    NvOsSetResourceAllocFileLine(ret, f, l);
+    NVOS_TRACE_LOG_PRINTF(("NvOsExecAlloc, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)ret));
+    return ret;
+}
+
+static NV_INLINE void
+NvOsExecFreeTraced(void *ptr, size_t size, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsExecFree, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)ptr));
+    (NvOsExecFree)(ptr, size);
+}
+
+static NV_INLINE NvError
+NvOsSharedMemAllocTraced(const char *key, size_t size,
+    NvOsSharedMemHandle *descriptor, const char *f, int l )
+{
+    NvError status;
+    status = (NvOsSharedMemAlloc)(key, size, descriptor);
+    if (status == NvSuccess)
+        NvOsSetResourceAllocFileLine(*descriptor, f, l);
+    NVOS_TRACE_LOG_PRINTF(("NvOsSharedMemAlloc, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(*descriptor)));
+    return status;
+}
+
+static NV_INLINE NvError
+NvOsSharedMemMapTraced(NvOsSharedMemHandle descriptor, size_t offset,
+    size_t size, void **ptr, const char *f, int l )
+{
+    NvError status;
+    status = (NvOsSharedMemMap)(descriptor, offset, size, ptr);
+    NVOS_TRACE_LOG_PRINTF(("NvOsSharedMemMap, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(*ptr)));
+    return status;
+}
+
+static NV_INLINE void
+NvOsSharedMemUnmapTraced(void *ptr, size_t size, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsSharedMemUnmap, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(ptr)));
+    (NvOsSharedMemUnmap)(ptr, size);
+}
+
+static NV_INLINE void
+NvOsSharedMemFreeTraced(NvOsSharedMemHandle descriptor, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsSharedMemFree, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(descriptor)));
+    (NvOsSharedMemFree)(descriptor);
+}
+
+static NV_INLINE NvError
+NvOsPhysicalMemMapTraced(NvOsPhysAddr phys, size_t size,
+    NvOsMemAttribute attrib, NvU32 flags, void **ptr, const char *f, int l )
+{
+    NvError status;
+    status = (NvOsPhysicalMemMap)(phys, size, attrib, flags, ptr);
+    if (status == NvSuccess)
+        NvOsSetResourceAllocFileLine(*ptr, f, l);
+    NVOS_TRACE_LOG_PRINTF(("NvOsPhysicalMemMap, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(*ptr)));
+    return status;
+}
+
+static NV_INLINE NvError
+NvOsPhysicalMemMapIntoCallerTraced( void *pCallerPtr, NvOsPhysAddr phys,
+    size_t size, NvOsMemAttribute attrib, NvU32 flags, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsPhysicalMemMapIntoCaller, \
+        %s, %d, %ums, 0x%x\n", f, l, NvOsGetTimeMS(), (NvU32)(pCallerPtr)));
+    return (NvOsPhysicalMemMapIntoCaller)(pCallerPtr, phys, size, attrib,
+        flags);
+}
+
+static NV_INLINE void
+NvOsPhysicalMemUnmapTraced(void *ptr, size_t size, const char *f, int l )
+{
+     NVOS_TRACE_LOG_PRINTF(("NvOsPhysicalMemUnmap, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(ptr)));
+     (NvOsPhysicalMemUnmap)(ptr, size);
+}
+
+static NV_INLINE NvError
+NvOsPageAllocTraced(size_t size, NvOsMemAttribute attrib,
+    NvOsPageFlags flags, NvU32 protect, NvOsPageAllocHandle *descriptor,
+    const char *f, int l )
+{
+    NvError status;
+    status = (NvOsPageAlloc)(size, attrib, flags, protect, descriptor);
+    if (status == NvSuccess)
+        NvOsSetResourceAllocFileLine(*descriptor, f, l);
+    NVOS_TRACE_LOG_PRINTF(("NvOsPageAlloc, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(descriptor)));
+    return status;
+}
+
+static NV_INLINE NvError
+NvOsPageLockTraced(void *ptr, size_t size, NvU32 protect, NvOsPageAllocHandle* descriptor,
+    const char *f, int l )
+{
+    NvError status;
+    status = (NvOsPageLock)(ptr, size, protect, descriptor);
+    NVOS_TRACE_LOG_PRINTF(("NvOsPageLock, %s, %d, %ums, 0x%x, %d, 0x%x, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(ptr), size, protect, (NvU32)*descriptor));
+    return status;
+}
+
+static NV_INLINE void
+NvOsPageFreeTraced(NvOsPageAllocHandle descriptor, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsPageFree, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(descriptor)));
+    (NvOsPageFree)(descriptor);
+}
+
+static NV_INLINE NvError
+NvOsPageMapTraced(NvOsPageAllocHandle descriptor, size_t offset, size_t size,
+    void **ptr, const char *f, int l )
+{
+    NvError status;
+    status = (NvOsPageMap)(descriptor, offset, size, ptr);
+    NVOS_TRACE_LOG_PRINTF(("NvOsPageMap, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(*ptr)));
+    return status;
+}
+
+static NV_INLINE NvError
+NvOsPageMapIntoPtrTraced( NvOsPageAllocHandle descriptor, void *pCallerPtr,
+    size_t offset, size_t size, const char *f, int l )
+{
+    NvError status;
+    status = (NvOsPageMapIntoPtr)(descriptor, pCallerPtr, offset, size);
+    NVOS_TRACE_LOG_PRINTF(("NvOsPageMapIntoCaller, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(pCallerPtr)));
+    return status;
+}
+
+static NV_INLINE void
+NvOsPageUnmapTraced(NvOsPageAllocHandle descriptor, void *ptr, size_t size,
+    const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsPageUnmap, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(ptr)));
+    (NvOsPageUnmap)(descriptor, ptr, size);
+}
+
+static NV_INLINE NvOsPhysAddr
+NvOsPageAddressTraced(NvOsPageAllocHandle descriptor, size_t offset,
+    const char *f, int l )
+{
+    NvOsPhysAddr PhysAddr;
+    PhysAddr = (NvOsPageAddress)(descriptor, offset);
+    NVOS_TRACE_LOG_PRINTF(("NvOsPageAddress, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(PhysAddr)));
+    return PhysAddr;
+}
+
+static NV_INLINE NvError
+NvOsMutexCreateTraced(NvOsMutexHandle *mutex, const char *f, int l )
+{
+    NvError status;
+    status = (NvOsMutexCreate)(mutex);
+    if (status == NvSuccess)
+        NvOsSetResourceAllocFileLine(*mutex, f, l);
+    NVOS_TRACE_LOG_PRINTF(("NvOsMutexCreate, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(*mutex)));
+    return status;
+}
+
+static NV_INLINE void
+NvOsMutexLockTraced(NvOsMutexHandle mutex, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsMutexLock, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)mutex));
+    (NvOsMutexLock)(mutex);
+}
+
+static NV_INLINE void
+NvOsMutexUnlockTraced(NvOsMutexHandle mutex, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsMutexUnlock, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)mutex));
+    (NvOsMutexUnlock)(mutex);
+}
+
+static NV_INLINE void NvOsMutexDestroyTraced(
+                            NvOsMutexHandle mutex,
+                            const char *f,
+                            int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsMutexDestroy, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)mutex));
+    (NvOsMutexDestroy)(mutex);
+}
+
+static NV_INLINE NvError
+NvOsIntrMutexCreateTraced(NvOsIntrMutexHandle *mutex, const char *f, int l )
+{
+    NvError status;
+    status = (NvOsIntrMutexCreate)(mutex);
+    if (status == NvSuccess)
+        NvOsSetResourceAllocFileLine(*mutex, f, l);
+    NVOS_TRACE_LOG_PRINTF(("NvOsIntrMutexCreate, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(*mutex)));
+    return status;
+}
+
+static NV_INLINE void
+NvOsIntrMutexLockTraced(NvOsIntrMutexHandle mutex, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsIntrMutexLock, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)mutex));
+    (NvOsIntrMutexLock)(mutex);
+}
+
+static NV_INLINE void
+NvOsIntrMutexUnlockTraced(NvOsIntrMutexHandle mutex, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsIntrMutexUnlock, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)mutex));
+    (NvOsIntrMutexUnlock)(mutex);
+}
+
+static NV_INLINE void
+NvOsIntrMutexDestroyTraced(NvOsIntrMutexHandle mutex, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsIntrMutexDestroy, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)mutex));
+    (NvOsIntrMutexDestroy)(mutex);
+}
+
+static NV_INLINE NvError
+NvOsSemaphoreCreateTraced( NvOsSemaphoreHandle *semaphore,  NvU32 value,
+    const char *f, int l )
+{
+    NvError status;
+    status = (NvOsSemaphoreCreate)(semaphore, value);
+    if (status == NvSuccess)
+        NvOsSetResourceAllocFileLine(*semaphore, f, l);
+    NVOS_TRACE_LOG_PRINTF(("NvOsSemaphoreCreate, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(*semaphore)));
+    return status;
+}
+
+static NV_INLINE NvError
+NvOsSemaphoreCloneTraced( NvOsSemaphoreHandle orig, NvOsSemaphoreHandle *clone,
+    const char *f, int l )
+{
+    NvError status;
+    status = (NvOsSemaphoreClone)(orig, clone);
+    if (status == NvSuccess)
+        NvOsSetResourceAllocFileLine(*clone, f, l);
+    NVOS_TRACE_LOG_PRINTF(("NvOsSemaphoreClone, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(*clone)));
+    return status;
+}
+
+static NV_INLINE NvError
+NvOsSemaphoreUnmarshalTraced( NvOsSemaphoreHandle hClientSema,
+    NvOsSemaphoreHandle *phDriverSema, const char *f, int l )
+{
+    NvError status;
+    status = (NvOsSemaphoreUnmarshal)(hClientSema, phDriverSema);
+    if (status == NvSuccess)
+        NvOsSetResourceAllocFileLine(*phDriverSema, f, l);
+    NVOS_TRACE_LOG_PRINTF(("NvOsSemaphoreUnmarshal, %s, %d, %ums, 0x%x\r\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(hClientSema)));
+    return status;
+}
+
+static NV_INLINE void
+NvOsSemaphoreWaitTraced( NvOsSemaphoreHandle semaphore, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsSemaphoreWait, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)semaphore));
+    (NvOsSemaphoreWait)(semaphore);
+}
+
+static NV_INLINE NvError
+NvOsSemaphoreWaitTimeoutTraced( NvOsSemaphoreHandle semaphore, NvU32 msec,
+    const char *f, int l )
+{
+    NvError status;
+    NVOS_TRACE_LOG_PRINTF(("NvOsSemaphoreWaitTimeout, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)semaphore));
+    status = (NvOsSemaphoreWaitTimeout)(semaphore, msec);
+    return status;
+}
+
+static NV_INLINE void
+NvOsSemaphoreSignalTraced( NvOsSemaphoreHandle semaphore, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsSemaphoreSignal, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)semaphore));
+    (NvOsSemaphoreSignal)(semaphore);
+}
+
+static NV_INLINE void
+NvOsSemaphoreDestroyTraced( NvOsSemaphoreHandle semaphore, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsSemaphoreDestory, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)semaphore));
+    (NvOsSemaphoreDestroy)(semaphore);
+}
+
+static NV_INLINE NvError
+NvOsThreadCreateTraced( NvOsThreadFunction function, void *args,
+    NvOsThreadHandle *thread, const char *f, int l )
+{
+    NvError status;
+    status = (NvOsThreadCreate)(function, args, thread);
+    if (status == NvSuccess)
+        NvOsSetResourceAllocFileLine(*thread, f, l);
+    NVOS_TRACE_LOG_PRINTF(("NvOsThreadCreate, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(*thread)));
+    return status;
+}
+
+static NV_INLINE void
+NvOsThreadJoinTraced( NvOsThreadHandle thread, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsThreadJoin, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)thread));
+    (NvOsThreadJoin)(thread);
+}
+
+static NV_INLINE void
+NvOsThreadYieldTraced(const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsThreadYield, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)0));
+    (NvOsThreadYield)();
+}
+
+static NV_INLINE NvError
+NvOsInterruptRegisterTraced(NvU32 IrqListSize, const NvU32 *pIrqList,
+    const NvOsInterruptHandler *pIrqHandlerList, void *context,
+    NvOsInterruptHandle *handle, NvBool InterruptEnable, const char *f, int l )
+{
+    NvError status;
+    status = (NvOsInterruptRegister)(IrqListSize, pIrqList, pIrqHandlerList,
+        context, handle, InterruptEnable);
+    NVOS_TRACE_LOG_PRINTF(("NvOsInterruptRegister, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(handle)));
+    return status;
+}
+
+static NV_INLINE void
+NvOsInterruptUnregisterTraced(NvOsInterruptHandle handle, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsInterruptUnregister, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(handle)));
+    (NvOsInterruptUnregister)(handle);
+}
+
+static NV_INLINE NvError
+NvOsInterruptEnableTraced(NvOsInterruptHandle handle, const char *f, int l )
+{
+    NvError status;
+
+    status = (NvOsInterruptEnable)(handle);
+    NVOS_TRACE_LOG_PRINTF(("NvOsInterruptRegister, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(handle)));
+    return status;
+}
+
+static NV_INLINE void
+NvOsInterruptDoneTraced(NvOsInterruptHandle handle, const char *f, int l )
+{
+    NVOS_TRACE_LOG_PRINTF(("NvOsInterruptDone, %s, %d, %ums, 0x%x\n",
+        f, l, NvOsGetTimeMS(), (NvU32)(handle)));
+    (NvOsInterruptDone)(handle);
+}
+
+#define NvOsExecAlloc(size) NvOsExecAllocTraced(size, __FILE__, __LINE__)
+#define NvOsExecFree(ptr, size) \
+    NvOsExecFreeTraced(ptr, size, __FILE__, __LINE__)
+#define NvOsSharedMemAlloc(key, size, descriptor) \
+    NvOsSharedMemAllocTraced(key, size, descriptor, __FILE__, __LINE__)
+#define NvOsSharedMemMap(descriptor, offset, size, ptr) \
+    NvOsSharedMemMapTraced(descriptor, offset, size, ptr, __FILE__, __LINE__)
+#define NvOsSharedMemUnmap(ptr, size) \
+    NvOsSharedMemUnmapTraced(ptr, size, __FILE__, __LINE__)
+#define NvOsSharedMemFree(descriptor) \
+    NvOsSharedMemFreeTraced(descriptor, __FILE__, __LINE__)
+#define NvOsPhysicalMemMap(phys, size, attrib, flags, ptr)   \
+    NvOsPhysicalMemMapTraced(phys, size, attrib, flags, ptr, \
+            __FILE__, __LINE__)
+#define NvOsPhysicalMemMapIntoCaller(pCallerPtr, phys, size, attrib, flags) \
+    NvOsPhysicalMemMapIntoCallerTraced(pCallerPtr, phys, size, attrib, flags, \
+            __FILE__, __LINE__)
+#define NvOsPhysicalMemUnmap(ptr, size)   \
+    NvOsPhysicalMemUnmapTraced(ptr, size, __FILE__, __LINE__)
+#define NvOsPageAlloc(size, attrib, flags, protect, descriptor)   \
+    NvOsPageAllocTraced(size, attrib, flags, protect, descriptor, \
+            __FILE__, __LINE__)
+#define NvOsPageFree(descriptor) \
+    NvOsPageFreeTraced(descriptor, __FILE__, __LINE__)
+#define NvOsPageMap(descriptor, offset, size, ptr)   \
+    NvOsPageMapTraced(descriptor, offset, size, ptr, __FILE__, __LINE__)
+#define NvOsPageMapIntoPtr(descriptor, pCallerPtr, offset, size)   \
+    NvOsPageMapIntoPtrTraced(descriptor, pCallerPtr, offset, size, \
+            __FILE__, __LINE__)
+#define NvOsPageUnmap(descriptor, ptr, size) \
+    NvOsPageUnmapTraced(descriptor, ptr, size, __FILE__, __LINE__)
+#define NvOsPageAddress(descriptor, offset)   \
+    NvOsPageAddressTraced(descriptor, offset, __FILE__, __LINE__)
+#define NvOsMutexCreate(mutex) NvOsMutexCreateTraced(mutex, __FILE__, __LINE__)
+#define NvOsMutexLock(mutex) NvOsMutexLockTraced(mutex, __FILE__, __LINE__)
+#define NvOsMutexUnlock(mutex) NvOsMutexUnlockTraced(mutex, __FILE__, __LINE__)
+#define NvOsMutexDestroy(mutex) \
+    NvOsMutexDestroyTraced(mutex, __FILE__, __LINE__)
+#define NvOsIntrMutexCreate(mutex) \
+    NvOsIntrMutexCreateTraced(mutex, __FILE__, __LINE__)
+#define NvOsIntrMutexLock(mutex) \
+    NvOsIntrMutexLockTraced(mutex, __FILE__, __LINE__)
+#define NvOsIntrMutexUnlock(mutex) \
+    NvOsIntrMutexUnlockTraced(mutex, __FILE__, __LINE__)
+#define NvOsIntrMutexDestroy(mutex) \
+    NvOsIntrMutexDestroyTraced(mutex, __FILE__, __LINE__)
+#define NvOsSemaphoreCreate(semaphore, value)   \
+    NvOsSemaphoreCreateTraced(semaphore, value, __FILE__, __LINE__)
+#define NvOsSemaphoreClone(orig, semaphore)   \
+    NvOsSemaphoreCloneTraced(orig, semaphore, __FILE__, __LINE__)
+#define NvOsSemaphoreUnmarshal(hClientSema, phDriverSema)   \
+    NvOsSemaphoreUnmarshalTraced(hClientSema, phDriverSema, __FILE__, __LINE__)
+/*
+#define NvOsSemaphoreWait(semaphore)   \
+    NvOsSemaphoreWaitTraced(semaphore, __FILE__, __LINE__)
+#define NvOsSemaphoreWaitTimeout(semaphore, msec)   \
+    NvOsSemaphoreWaitTimeoutTraced(semaphore, msec, __FILE__, __LINE__)
+*/
+#define NvOsSemaphoreSignal(semaphore)   \
+    NvOsSemaphoreSignalTraced(semaphore, __FILE__, __LINE__)
+#define NvOsSemaphoreDestroy(semaphore)   \
+    NvOsSemaphoreDestroyTraced(semaphore, __FILE__, __LINE__)
+#define NvOsThreadCreate(func, args, thread)    \
+    NvOsThreadCreateTraced(func, args, thread, __FILE__, __LINE__)
+#define NvOsThreadJoin(thread)  \
+    NvOsThreadJoinTraced(thread, __FILE__, __LINE__)
+#define NvOsThreadYield() NvOsThreadYieldTraced(__FILE__, __LINE__)
+#define NvOsInterruptRegister(IrqListSize, pIrqList, pIrqHandlerList, \
+        context, handle, InterruptEnable) \
+    NvOsInterruptRegisterTraced(IrqListSize, pIrqList, pIrqHandlerList, \
+        context, handle, InterruptEnable, __FILE__, __LINE__)
+#define NvOsInterruptUnregister(handle) \
+    NvOsInterruptUnregisterTraced(handle, __FILE__, __LINE__)
+#define NvOsInterruptEnable(handle) \
+    NvOsInterruptEnableTraced(handle, __FILE__, __LINE__)
+#define NvOsInterruptDone(handle) \
+    NvOsInterruptDoneTraced(handle, __FILE__, __LINE__)
+
+#endif // NVOS_TRACE
+
+// Forward declare resource tracking struct.
+typedef struct NvCallstackRec     NvCallstack;
+
+typedef enum
+{
+    NvOsCallstackType_NoStack = 1,
+    NvOsCallstackType_HexStack,
+    NvOsCallstackType_SymbolStack,
+    
+    NvOsCallstackType_Last,
+    NvOsCallstackType_Force32 = 0x7FFFFFFF
+} NvOsCallstackType;
+
+typedef void (*NvOsDumpCallback)(void* context, const char* line);
+
+void NvOsDumpToDebugPrintf(void* context, const char* line);
+void NvOsGetProcessInfo(char* buf, NvU32 len);
+
+/* implemented by the OS-backend, for now CE and Linux only */
+#if (NVOS_IS_WINDOWS_CE || NVOS_IS_LINUX)
+NvCallstack* NvOsCreateCallstack      (NvOsCallstackType stackType);
+void         NvOsGetStackFrame        (char* buf, NvU32 len, NvCallstack* stack, NvU32 level);
+void         NvOsDestroyCallstack     (NvCallstack* callstack);
+NvU32        NvOsHashCallstack        (NvCallstack* stack);
+void         NvOsDumpCallstack        (NvCallstack* stack, NvU32 skip, NvOsDumpCallback callBack, void* context);
+NvBool       NvOsCallstackContainsPid (NvCallstack* stack, NvU32 pid);
+NvU32        NvOsCallstackGetNumLevels(NvCallstack* stack);
+#else // (NVOS_IS_WINDOWS_CE || NVOS_IS_LINUX)
+static NV_INLINE NvCallstack* NvOsCreateCallstack (NvOsCallstackType stackType) { return NULL; }
+static NV_INLINE void NvOsGetStackFrame           (char* buf, NvU32 len, NvCallstack* stack, NvU32 level) { NvOsStrncpy(buf, "<stack>", len); }
+static NV_INLINE void NvOsDestroyCallstack        (NvCallstack* callstack) { }
+static NV_INLINE NvU32 NvOsHashCallstack          (NvCallstack* stack) { return 0; }
+static NV_INLINE void NvOsDumpCallstack           (NvCallstack* stack, NvU32 skip, NvOsDumpCallback callBack, void* context) { }
+static NvBool NV_INLINE NvOsCallstackContainsPid  (NvCallstack* stack, NvU32 pid) { return NV_FALSE; }
+static NV_INLINE NvU32 NvOsCallstackGetNumLevels  (NvCallstack* stack) { return 0; }
+#endif // (NVOS_IS_WINDOWS_CE || NVOS_IS_LINUX)
+
+/*@}*/
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_NVOS_H
diff --git a/arch/arm/mach-tegra/nv/include/nvos_linux_ioctls.h b/arch/arm/mach-tegra/nv/include/nvos_linux_ioctls.h
new file mode 100644
index 000000000000..1875bd82cb04
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvos_linux_ioctls.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/ioctl.h>
+#include "nvos.h"
+#include "nvcommon.h"
+
+#ifndef NVOS_LINUX_IOCTLS_H
+#define NVOS_LINUX_IOCTLS_H
+
+typedef struct
+{
+    NvU32 IoctlCode;
+    NvU32 InBufferSize;
+    NvU32 InOutBufferSize;
+    NvU32 OutBufferSize;
+    void *pBuffer;
+} NV_ALIGN(4) NvOsIoctlParams;
+
+typedef struct
+{
+    NvOsSemaphoreHandle sem;
+    NvU32 value;
+    NvError error;
+} NV_ALIGN(4) NvOsSemaphoreIoctlParams;
+
+typedef struct
+{
+    NvOsSemaphoreHandle hOrig;
+    NvOsSemaphoreHandle hNew;
+    NvError             Error;
+} NV_ALIGN(4) NvOsSemaphoreUnmarshalParams;
+
+typedef struct
+{
+    NvOsSemaphoreHandle hOrig;
+    NvOsSemaphoreHandle hNew;
+    NvError             Error;
+} NV_ALIGN(4) NvOsSemaphoreCloneParams;
+
+typedef struct
+{
+    NvU32 nIrqs;
+    const NvU32 *Irqs;
+    NvOsSemaphoreHandle *SemaphoreList;
+    NvError errCode;
+    NvUPtr  kernelHandle;
+} NV_ALIGN(4) NvOsInterruptRegisterParams;
+
+typedef struct
+{
+    NvUPtr  handle;
+    NvU32   arg;
+    NvError errCode;
+} NV_ALIGN(4) NvOsInterruptOpParams;
+
+typedef struct
+{
+    NvUPtr handle;
+    NvU32 mask;
+} NV_ALIGN(4) NvOsInterruptMaskParams;
+
+typedef struct
+{
+    NvU32 size;
+    char *text;
+} NV_ALIGN(4) NvOsDebugStringParams;
+
+typedef struct
+{
+    NvOsPhysAddr base;
+    NvU32 size;
+} NV_ALIGN(4) NvOsMemRangeParams;
+
+#define NV_IOCTL_SEMAPHORE_CREATE   _IOWR('N', 0x20, NvOsSemaphoreIoctlParams)
+#define NV_IOCTL_SEMAPHORE_DESTROY  _IOW('N', 0x21, NvOsSemaphoreHandle)
+#define NV_IOCTL_SEMAPHORE_CLONE \
+    _IOWR('N', 0x22, NvOsSemaphoreCloneParams)
+#define NV_IOCTL_SEMAPHORE_UNMARSHAL \
+    _IOWR('N', 0x23, NvOsSemaphoreUnmarshalParams)
+#define NV_IOCTL_SEMAPHORE_SIGNAL   _IOW('N', 0x24, NvOsSemaphoreHandle)
+#define NV_IOCTL_SEMAPHORE_WAIT     _IOW('N', 0x25, NvOsSemaphoreHandle)
+#define NV_IOCTL_SEMAPHORE_WAIT_TIMEOUT \
+    _IOW('N', 0x26, NvOsSemaphoreIoctlParams)
+#define NV_IOCTL_INTERRUPT_REGISTER \
+    _IOWR('N', 0x27, NvOsInterruptRegisterParams)
+#define NV_IOCTL_INTERRUPT_UNREGISTER   _IOWR('N', 0x28, NvOsInterruptOpParams)
+#define NV_IOCTL_INTERRUPT_ENABLE       _IOWR('N', 0x29, NvOsInterruptOpParams)
+#define NV_IOCTL_INTERRUPT_DONE         _IOWR('N', 0x2A, NvOsInterruptOpParams)
+#define NV_IOCTL_INTERRUPT_MASK     _IOWR('N', 0x2B, NvOsInterruptOpParams)
+#define NV_IOCTL_GLOBAL_LOCK        _IO('N', 0x2C)
+#define NV_IOCTL_GLOBAL_UNLOCK      _IO('N', 0x2D)
+#define NV_IOCTL_DEBUG_STRING       _IOW('N', 0x2E, NvOsDebugStringParams)
+#define NV_IOCTL_MEMORY_RANGE       _IOW('N', 0x2F, NvOsMemRangeParams)
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvos_trace.h b/arch/arm/mach-tegra/nv/include/nvos_trace.h
new file mode 100644
index 000000000000..8212681f722f
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvos_trace.h
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVOS_TRACE_H
+#define INCLUDED_NVOS_TRACE_H
+
+#define NVOS_TRACE 0
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/**
+ * The nvos_trace.txt is a nvos trace file to collect aggregate statistics
+ * about how system calls and resources are used in higher-level software.
+ * It has format:
+ *    NvOsFunctionName , CallingFile , CallingLine , CallTime , Data 
+ * NvOsFunctionName is the function name 
+ * CallingFile and CallingLine are just the __FILE__ and __LINE__ parameters. 
+ * CallTime is a NvU32 storing time in miliseconds. 
+ * Data is a function-specific data parameter. For MutexLock and MutexUnlock 
+ * this would be the mutex handle. For NvOsAlloc * and NvOsFree this 
+ * would be the allocated address. 
+ *
+ */
+
+/**
+ * opens the trace file nvos_trace.txt
+ *
+ * This function should be called via a macro so that it may be compiled out.
+ *
+ */
+void 
+NvOsTraceLogStart(void);
+
+/**
+ * closes the trace file nvos_trace.txt.
+ *
+ * This function should be called via a macro so that it may be compiled out.
+ */
+void
+NvOsTraceLogEnd(void);
+
+/**
+ * emits a string to the trace file nvos_trace.txt
+ *
+ * @param format Printf style argument format string
+ *
+ * This function should be called via a macro so that it may be compiled out.
+ *
+ */
+void
+NvOsTraceLogPrintf( const char *format, ... );
+
+/**
+ * Helper macro to go along with NvOsTraceLogPrintf.  Usage:
+ *    NVOS_TRACE_LOG_PRINTF(("foo: %s\n", bar));
+ * The NvOs trace log prints will be disabled by default in all builds, debug
+ * and release.
+ * Note the use of double parentheses.
+ *
+ * To enable NvOs trace log prints
+ *     #define NVOS_TRACE 1
+ */
+#if NVOS_TRACE
+#define NVOS_TRACE_LOG_PRINTF(a)    NvOsTraceLogPrintf a
+#define NVOS_TRACE_LOG_START    \
+    do {                        \
+        NvOsTraceLogStart();    \
+    } while (0);
+#define NVOS_TRACE_LOG_END      \
+    do {                        \
+        NvOsTraceLogEnd();      \
+    } while (0);
+#else
+#define NVOS_TRACE_LOG_PRINTF(a)    (void)0
+#define NVOS_TRACE_LOG_START        (void)0
+#define NVOS_TRACE_LOG_END          (void)0
+#endif
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif /* NVOS_TRACE_H */
+
diff --git a/arch/arm/mach-tegra/nv/include/nvreftrack.h b/arch/arm/mach-tegra/nv/include/nvreftrack.h
new file mode 100644
index 000000000000..0b15d633b98c
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvreftrack.h
@@ -0,0 +1,474 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * \file nvreftrack.h
+ * \brief NVIDIA kernel object reference tracking utility
+ *
+ * \mainpage
+ *
+ * NvRefTrack implements a database of client to object
+ * references. The sole purpose of the utility is to provide a
+ * mechanism for freeing up kernel mode driver objects on abnormal
+ * client termination.
+ *
+ * This utility is intended to be used together with the NV IDL
+ * automatic call dispatcher generation. 'refadd' and 'refdel'
+ * modifiers for function parameters instruct the IDL generation to
+ * instrument the dispatcher functions with appropriate calls to
+ * NvRtStoreObjRef() and NvRtFreeObjRef().
+ *
+ * The OS specific kernel driver's responsibility is to create the
+ * NvRt context and to register and unregister clients (user mode
+ * processes accessing the driver). Additionally the context and the
+ * calling client handle need to be passed to the master dispatcher.
+ */
+
+#ifndef INCLUDED_NVREFTRACK_H
+#define INCLUDED_NVREFTRACK_H
+
+#include "nvcommon.h"
+#include "nverror.h"
+
+#ifndef NVRT_ENABLE_LEAK_PRINT
+#define NVRT_ENABLE_LEAK_PRINT NV_DEBUG
+#endif
+
+/*---------------------------------------------------------*/
+/** \defgroup objtype Tracked object types
+ *
+ * NvRefTrack must be able to identify the object types
+ * stored in the database. As the IDL generator can not
+ * produce a list of the types they are statically defined
+ * here. Note that this list of enumerations is not actually
+ * a part of the NvRefTrack public interface - it could be
+ * stored separately. Ideally these enumerations would be
+ * generated by the IDL dispatcher generator.
+ *
+ * The exact syntax of these enumerations is important, as
+ * the IDL generator will refer to these names when creating
+ * reference add/del code in the dispatcher.
+ *
+ * 1) There must a an enumeration for every package that
+ *    contains objects to be tracked. The enumeration should
+ *    be called NvRtObjType_<package>.
+ * 2) For every object type tracked in the package (every
+ *    object type that may have refadd and refdel modifiers
+ *    in the idl description) there needs to be an entry in
+ *    the enumeration called NvRtObjType_<package>_<type>.
+ * 3) The enumerations should start from value 0 and fill
+ *    the number space completely up to
+ *    NvRtObjType_<package>_Num, which will be equal to the
+ *    number of tracked object types in the package.
+ */
+
+/**
+ * Tracked object types for package NvRm
+ * \ingroup objtype
+ */
+typedef enum
+{
+    NvRtObjType_NvRm_NvRmMemHandle = 0,
+    NvRtObjType_NvRm_Num,
+    NvRtObjType_NvRm_ForceWord = 0x7FFFFFFF
+} NvRtObjType_NvRm;
+
+/**
+ * Tracked handles for package NvRmGraphics
+ * \ingroup objtype
+ */
+typedef enum
+{
+    NvRtObjType_NvRmGraphics_NvRmChannelHandle = 0,
+    NvRtObjType_NvRmGraphics_NvRmContextHandle,
+    NvRtObjType_NvRmGraphics_Num,
+    NvRtObjType_NvRmGraphics_ForceWord = 0x7FFFFFFF
+} NvRtObjType_NvRmGraphics;
+
+/**
+ * Tracked handles for package NvMM
+ *
+ * Tentative handles to track:
+ * - NvMMManagerHandle, this does not exist - API failure?
+ * - NvMMIRAMScratchHandle, this does not exist - API failure?
+ *   Can possibly use references to CodecType, a bit dodgy
+ * - pBlock, why is this not a handle?
+ * - pClientId, why is this not a handle?
+ * \ingroup objtype
+ */
+typedef enum
+{
+    NvRtObjType_NvMM_NvmmPowerClientHandle = 0,
+    NvRtObjType_NvMM_NvmmManagerHandle,
+    NvRtObjType_NvMM_NvmmMgrBlockHandle,
+    NvRtObjType_NvMM_Num,
+    NvRtObjType_NvMM_ForceWord = 0x7FFFFFFF
+} NvRtObjType_NvMM;
+
+/**
+ * Tracked handles for package NvECPackage
+ *
+ * Tentative handles to track:
+ * - NvEcHandle
+ * - NvEcEventRegistrationHandle
+ * \ingroup objtype
+ */
+typedef enum
+{
+    NvRtObjType_NvECPackage_NvEcHandle = 0,
+    NvRtObjType_NvECPackage_NvEcEventRegistrationHandle,
+    NvRtObjType_NvECPackage_Num,
+    NvRtObjType_NvECPackage_ForceWord = 0x7FFFFFFF
+} NvRtObjType_NvECPackage;
+
+/**
+ * Tracked handles for package NvStorManager
+ *
+ * Tentative handles to track:
+ * - NvStorMgrFileHandle
+ * \ingroup objtype
+ */
+typedef enum
+{
+    NvRtObjType_NvStorManager_NvStorMgrFileHandle = 0,
+    NvRtObjType_NvStorManager_Num,
+    NvRtObjType_NvStorManager_ForceWord = 0x7FFFFFFF
+} NvRtObjType_NvStorManager;
+
+/**
+ * Tracked handles for package NvDDKAudio
+ * \ingroup objtype
+ */
+typedef enum
+{
+    NvRtObjType_NvDDKAudio_Num = 0,
+    NvRtObjType_NvDDKAudio_ForceWord = 0x7FFFFFFF
+} NvRtObjType_NvDDKAudio;
+
+/**
+ * Tracked handles for package NvDispMgr
+ * \ingroup objtype
+ */
+typedef enum
+{
+    NvRtObjType_NvDispMgr_Client = 0,
+    NvRtObjType_NvDispMgr_Num,
+    NvRtObjType_NvDispMgr_ForceWord = 0x7FFFFFFF
+} NvRtObjType_NvDispMgr;
+
+
+/*---------------------------------------------------------*/
+/** \defgroup os_driver Public interface for os driver */
+
+#if NVRT_ENABLE_LEAK_PRINT
+#define NVRT_LEAK(driver, objtype, ptr) \
+    NvOsDebugPrintf("[%s] Leaked reference on client exit: (%s) 0x%08x\n", \
+                    driver, objtype, ptr);
+#else
+#define NVRT_LEAK(driver, objtype, ptr)
+#endif
+
+
+typedef struct NvRtRec* NvRtHandle;
+typedef NvU32 NvRtClientHandle;
+typedef NvU32 NvRtObjRefHandle;
+
+typedef struct
+{
+    NvRtHandle Rt;
+    NvRtClientHandle Client;
+    NvU32 PackageIdx;
+} NvDispatchCtx;
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+ /** 
+ * Create a reference tracking database.
+ *
+ * The OS driver should create a single database upon driver init for
+ * all the IDL packages that the driver is responsible for. The
+ * created handle should be stored in the global driver context.
+ *
+ * @param NumPackages            Number of IDL packages that the driver is
+ *                               responsible for.
+ * @param NumObjTypesPerPackage  A list of the amount of tracked handles
+ *                               for each of the IDL packages. The order
+ *                               of the list needs to match the package
+ *                               indices passed in to the reference
+ *                               manipulation functions. The XXX_Num value
+ *                               of the object type enumerations can be used
+ *                               in constructing the list.
+ * @param RtOut                  A newly created reference database handle.
+ * @return                       NvSuccess on success.
+ *
+ * \ingroup os_driver
+ */    
+NvError NvRtCreate(
+    NvU32 NumPackages,
+    const NvU32* NumObjTypesPerPackage,
+    NvRtHandle* RtOut);
+
+/**
+ * Destroy a reference tracking database.
+ *
+ * This frees all resources associated to a reference database and should
+ * be called on driver deinitialization. Note that this function makes no
+ * attempt at freeing any outstanding references, the user must make sure
+ * that references to driver objects have been freed prior to destroying
+ * the database.
+ *
+ * @param Rt    The reference database handle.
+ *
+ * \ingroup os_driver
+ */
+void NvRtDestroy(
+    NvRtHandle Rt);
+
+/**
+ * Register a new client to the reference database.
+ *
+ * For all practical purposes, a client refers to a single entity in the
+ * system that uses the driver via the IDL interface and may terminate
+ * unexpectedly, without freeing the driver resource references it holds.
+ * It makes no sense, for example, to register potential kernel-side users
+ * of the driver into the database as it should be impossible to terminate
+ * such a client unexpectedly without resulting in a complete system failure.
+ * Most commonly, but not necessarily, client == usermode process.
+ *
+ * The client ID returned by this function in the location pointed to by the
+ * ClientOut parameter must be stored in a way that it can be passed along
+ * to the master dispatcher function (in the NvDispatchCtx struct) for all
+ * calls originating from the client. This may, for example, be the return
+ * value from a file handle open (XXX_Open) operation passed back as the
+ * "open context" parameter into XXX_Ioctl calls.
+ *
+ * @param Rt            The reference database handle.
+ * @param ClientOut     A unique ID for the newly registered client. This
+ *                      value never equals 0 on success.
+ * @return              NvSuccess on success.
+ *
+ * \ingroup os_driver
+ */
+NvError NvRtRegisterClient(
+    NvRtHandle Rt,
+    NvRtClientHandle* ClientOut);
+
+/**
+ * Add a reference to the already registered client.
+ *
+ * Multiple references to a client may be needed when a single client
+ * can be accessed from multiple entities (processes). 
+ *
+ * @param Rt            The reference database handle.
+ * @param Client        The unique ID of the client.
+ * @return              NvSuccess on success.
+ *
+ * \ingroup os_driver
+ */
+NvError NvRtAddClientRef(
+    NvRtHandle Rt,
+    NvRtClientHandle Client);
+        
+/**
+ * Unregister a client from the reference database.
+ *
+ * As client handles are refcounted the caller and nvreftrack must
+ * conspire to know when to process possibly leaked resources. The library
+ * signals the caller about the correct time to free leaked resources by
+ * returning NV_TRUE (standing for: yes, please do cleanup now).
+ *
+ * Upon a return value of NV_TRUE, it is the responsibility of the OS driver to
+ * iterate over the possibly remaining references and implement the tearing
+ * down of those references appropriately. This is accomplished by calling
+ * NvRtFreeObjRef() until no further object pointers are returned by it for
+ * the given (client, package, objtype). After doing the cleanup, the caller
+ * should call NvRtUnregisterClient() once more to actually free the client
+ * handle.
+ * 
+ * @param Rt            The reference database handle.
+ * @param Client        The unique ID of the Client.
+ * @return              NV_TRUE if the caller should clean up leaked objects
+ *                      and call NvRtUnregisterClient() again, NV_FALSE
+ *                      otherwise.
+ *
+ * \ingroup os_driver
+ */    
+NvBool NvRtUnregisterClient(
+    NvRtHandle Rt,
+    NvRtClientHandle Client);
+
+/**
+ * Set/Get opaque user data associated to a client
+ *
+ * \ingroup os_driver
+ */    
+    
+void NvRtSetClientUserData(
+    NvRtHandle Rt,
+    NvRtClientHandle Client,
+    void* UserData);    
+void* NvRtGetClientUserData(
+    NvRtHandle Rt,
+    NvRtClientHandle Client);
+    
+/*---------------------------------------------------------*/
+/** \defgroup idl_iface Interface used by generated IDL code
+ *
+ * These functions are mainly intended to be called from the
+ * generated IDL dispatcher code. It is of course possible
+ * to use this interface directly from handwritten driver
+ * code as well.
+ *
+ * An exception to this rule is the NvRtFreeObjRef(), which
+ * the os driver uses to iterate over remaining object
+ * references of a client to be unregistered.
+ **/
+
+/**
+ * Allocate an object reference handle.
+ *
+ * Adding an object reference is broken into two parts,
+ * NvRtAllocObjRef() and NvRtStoreObjRef(). This is so that all
+ * resource allocations for the object reference can be done in
+ * advance to eliminate the need to be able to rollback a driver
+ * object reference add in the generated IDL code.
+ *
+ * The caller must call one of NvRtDiscardObjRef() or
+ * NvRtStoreObjRef() for a NvRtObjRefHandle returned by this
+ * function. Failure to do so will unrecoverably leak the object
+ * reference handle.
+ * 
+ * @param Ctx           The dispatcher context, filled by the OS driver
+ * @param ObjRef        A new handle to an object reference
+ *
+ * \ingroup idl_iface
+ */        
+NvError NvRtAllocObjRef(
+    const NvDispatchCtx* Ctx,
+    NvRtObjRefHandle* ObjRef);
+
+    
+/**
+ * Discard an object reference handle.
+ *
+ * Frees a previously allocated object reference handle without storing
+ * anything in the database.
+ * 
+ * @param Ctx           The dispatcher context, filled by the OS driver
+ * @param ObjRef        An object reference handle
+ *
+ * \ingroup idl_iface
+ */        
+void NvRtDiscardObjRef(
+    const NvDispatchCtx* Ctx,
+    NvRtObjRefHandle ObjRef);
+
+/**
+ * Store an object reference to the database.
+ *
+ * This function adds an object reference to the database. An object
+ * is identified via the the attributes (Ctx.PackageIdx, ObjType,
+ * ObjPtr).  The reference is created from Ctx.Client. It is
+ * completely valid to have multiple references to a given object from
+ * the same client, or from multiple clients.
+ *
+ * After calling this function the NvRtObjRefHandle acquired by a call
+ * to NvRtAllocObjRef becomes invalid and may no longer be used for
+ * any other purpose.
+ *
+ * It is the caller's responsibility to make sure that the object type
+ * is within range of the allocated object types for the package. In
+ * practice if the NvRtObjType enumeration is well defined and the
+ * NvRt database correctly initialized with the maximum amount of
+ * objects for the package this should not be an issue.
+ *
+ * @param Ctx           The dispatcher context, filled by the OS driver
+ * @param ObjRef        An object reference handle
+ * @param ObjType       The NvRtObjType of the object to be stored
+ * @param ObjPtr        A opaque pointer uniquely identifying the object
+ *                      that this reference points to. NULL is not allowed.
+ *
+ * \ingroup idl_iface
+ */        
+void NvRtStoreObjRef(
+    const NvDispatchCtx* Ctx,
+    NvRtObjRefHandle ObjRef,
+    NvU32 ObjType,
+    void* ObjPtr);
+
+/**
+ * Find and free an object reference.
+ *
+ * The NvRt API provides no way of enumerating or querying the object
+ * database without simultaneously freeing the object reference as
+ * well.  This is intentional - the utility is built for a very
+ * specific purpose and optimized to do that in a fast and robust way.
+ *
+ * This function is used to free a previously stored object
+ * reference. Upon locating an object reference from Ctx.Client to
+ * (Ctx.PackageIdx, ObjType, ObjPtr) it immediately frees the object
+ * reference from the database.
+ *
+ * Passing in NULL as ObjPtr means 'match any', the function will locate and
+ * free the first object reference from Ctx.Client to (Ctx.PackageIdx,
+ * ObjType). This can be used to free all outstanding references from a client,
+ * iterate over all packages and object types that the client may have used,
+ * call NvRtFreeObjRef() with a NULL ObjPtr parameter and free the returned
+ * ObjPtr reference until no more references are returned.
+ *
+ * In any case, if an object reference was found and freed the ObjPtr
+ * of the reference is returned. A NULL return value means that no reference
+ * matching the criteria was found. Note that if the generated IDL code works
+ * correctly this function should never get called with a ObjPtr parameter that
+ * can't be found from the database.
+ *
+ * @param Ctx           The dispatcher context, filled by the OS driver
+ * @param ObjType       The NvRtObjType of the object to be found
+ * @param ObjPtr        A opaque pointer of the object to be found
+ * @return              The ObjPtr of the reference free'd, NULL if not found
+ *
+ * \ingroup idl_iface
+ */        
+void* NvRtFreeObjRef(
+    const NvDispatchCtx* Ctx,
+    NvU32 ObjType,
+    void* ObjPtr);
+
+#if defined(__cplusplus)
+}
+#endif
+    
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_analog.h b/arch/arm/mach-tegra/nv/include/nvrm_analog.h
new file mode 100644
index 000000000000..fd53d1e62c9d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_analog.h
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_analog_H
+#define INCLUDED_nvrm_analog_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvodm_query.h"
+
+/**
+ * List of controllable analog interfaces.  Multiple instances of any
+ * particlar interface will be handled by the NVRM_ANALOG_INTERFACE macro
+ * below.
+ */
+
+typedef enum
+{
+    NvRmAnalogInterface_Dsi,
+    NvRmAnalogInterface_ExternalMemory,
+    NvRmAnalogInterface_Hdmi,
+    NvRmAnalogInterface_Lcd,
+    NvRmAnalogInterface_Uart,
+    NvRmAnalogInterface_Usb,
+    NvRmAnalogInterface_Sdio,
+    NvRmAnalogInterface_Tv,
+    NvRmAnalogInterface_VideoInput,
+    NvRmAnalogInterface_Num,
+    NvRmAnalogInterface_Force32 = 0x7FFFFFFF
+} NvRmAnalogInterface;
+
+/**
+ * Defines the USB Line state 
+ */
+
+typedef enum
+{
+    NvRmUsbLineStateType_SE0 = 0,
+    NvRmUsbLineStateType_SJ = 1,
+    NvRmUsbLineStateType_SK = 2,
+    NvRmUsbLineStateType_SE1 = 3,
+    NvRmUsbLineStateType_Num,
+    NvRmUsbLineStateType_Force32 = 0x7FFFFFFF
+} NvRmUsbLineStateType;
+
+/**
+ * List of analog TV DAC type
+ */
+
+typedef enum
+{
+    NvRmAnalogTvDacType_CRT,
+    NvRmAnalogTvDacType_SDTV,
+    NvRmAnalogTvDacType_HDTV,
+    NvRmAnalogTvDacType_Num,
+    NvRmAnalogTvDacType_Force32 = 0x7FFFFFFF
+} NvRmAnalogTvDacType;
+
+/**
+ * Create an analog interface id with multiple instances.
+ */
+#define NVRM_ANALOG_INTERFACE( id, instance ) \
+    ((NvRmAnalogInterface)( (instance) << 16 | id ))
+
+/**
+ * Get the interface id.
+ */
+#define NVRM_ANALOG_INTERFACE_ID( id ) ((id) & 0xFFFF)
+
+/**
+ * Get the interface instance.
+ */
+#define NVRM_ANALOG_INTERFACE_INSTANCE( id ) (((id) >> 16) & 0xFFFF)
+
+/**
+ * Control I/O pads, DACs, or PHYs, either enable or disable, with an optional
+ * configuration structure, which may be defined per module.
+ *
+ * @param hDevice Handle to the RM device
+ * @param Interface The physical interface to configure
+ * @param Enable enable/disable bit
+ * @param Config extra configuration options for each module, if necessary
+ * @param ConfigLength the size in bytes of the configuration structure
+ */
+
+ NvError NvRmAnalogInterfaceControl( 
+    NvRmDeviceHandle hDevice,
+    NvRmAnalogInterface Interface,
+    NvBool Enable,
+    void* Config,
+    NvU32 ConfigLength );
+
+/**
+ * Get TV DAC Configuration
+ *
+ * @param hDevice Handle to the RM device
+ * @param Type The analog TV DAC type 
+ * @return The analog TV DAC Configuration value
+ */
+
+ NvU8 NvRmAnalogGetTvDacConfiguration( 
+    NvRmDeviceHandle hDevice,
+    NvRmAnalogTvDacType Type );
+
+/**
+ * Detect if USB is connected or not
+ *
+ * @param hDevice Handle to the RM device
+ * @return TRUE means USB is connected
+ */
+
+ NvBool NvRmUsbIsConnected( 
+    NvRmDeviceHandle hDevice );
+
+/**
+ * Detect charger type
+ *
+ * @param hDevice Handle to the RM device
+ * @param wait Delay time and ready to get the correct charger type
+ * @return USB charger type
+ */
+
+ NvU32 NvRmUsbDetectChargerState( 
+    NvRmDeviceHandle hDevice,
+    NvU32 wait );
+
+/**
+ * Extended configuration structures for NvRmAnalogInterfaceControl.
+ */
+
+typedef struct NvRmAnalogTvDacConfigRec
+{
+
+    /* The DAC input source, may be a Display controller or the TVO engine */
+        NvRmModuleID Source;
+
+    /* The DAC output amplitude */
+        NvU8 DacAmplitude;
+} NvRmAnalogTvDacConfig;
+
+/**
+ * List of USB analog status check parameters
+ */
+
+typedef enum
+{
+    NvRmAnalogUsbInputParam_CheckCableStatus,
+    NvRmAnalogUsbInputParam_CheckChargerStatus,
+    NvRmAnalogUsbInputParam_CheckIdStatus,
+    NvRmAnalogUsbInputParam_WaitForPhyClock,
+    NvRmAnalogUsbInputParam_ConfigureUsbPhy,
+    NvRmAnalogUsbInputParam_ChargerDetection,
+    NvRmAnalogUsbInputParam_SetUlpiNullTrimmers,
+    NvRmAnalogUsbInputParam_ConfigureUlpiNullClock,
+    NvRmAnalogUsbInputParam_SetNullUlpiPinMux,
+    NvRmAnalogUsbInputParam_SetUlpiLinkTrimmers,
+    NvRmAnalogUsbInputParam_VbusInterrupt,
+    NvRmAnalogUsbInputParam_IdInterrupt,
+    NvRmAnalogUsbInputParam_Num,
+    NvRmAnalogUsbInputParam_Force32 = 0x7FFFFFFF
+} NvRmAnalogUsbInputParam;
+
+/**
+ * Extended configuration structures for NvRmAnalogInterfaceControl for USB.
+ */
+
+typedef struct NvRmAnalogUsbConfigRec
+{
+
+    /* The USB Status check parameter */
+        NvRmAnalogUsbInputParam InParam;
+    NvBool UsbCableDetected;
+    NvBool UsbChargerDetected;
+    NvBool UsbIdDetected;
+} NvRmAnalogUsbConfig;
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_arm_cp.h b/arch/arm/mach-tegra/nv/include/nvrm_arm_cp.h
new file mode 100644
index 000000000000..30bdd971f4cf
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_arm_cp.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+
+#ifndef INCLUDED_ARM_CP_H
+#define INCLUDED_ARM_CP_H
+
+#include "nvassert.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+//==========================================================================
+// Compiler-specific status and coprocessor register abstraction macros.
+//==========================================================================
+
+#if defined(_MSC_VER) && NVOS_IS_WINDOWS_CE // Microsoft compiler on WinCE
+
+    // Define the standard ARM coprocessor register names because the ARM compiler requires
+    // that we use the names and the Microsoft compiler requires that we use the numbers for
+    // its intrinsic functions _MoveToCoprocessor() and _MoveFromCoprocessor().
+    #define p14     14
+    #define p15     15
+    #define c0      0
+    #define c1      1
+    #define c2      2
+    #define c3      3
+    #define c4      4
+    #define c5      5
+    #define c6      6
+    #define c7      7
+    #define c8      8
+    #define c9      9
+    #define c10     10
+    #define c11     11
+    #define c12     12
+    #define c13     13
+    #define c14     14
+    #define c15     15
+
+    /*
+     *  @brief Macro to abstract writing of a ARM coprocessor register via the MCR instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will receive the value read from the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7).
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MCR(cp,op1,Rd,CRn,CRm,op2)  _MoveToCoprocessor((NvU32)(Rd), cp, op1, CRn, CRm, op2)
+
+    /*
+     *  @brief Macro to abstract reading of a ARM coprocessor register via the MRC instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will receive the value read from the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7).
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MRC(cp,op1,Rd,CRn,CRm,op2)  *((NvU32*)(&(Rd))) = _MoveFromCoprocessor(cp, op1, CRn, CRm, op2)
+
+#elif defined(__ARMCC_VERSION)  // ARM compiler
+
+    /*
+     *  @brief Macro to abstract writing of a ARM coprocessor register via the MCR instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will be written to the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7)
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MCR(cp,op1,Rd,CRn,CRm,op2)  __asm { MCR cp, op1, Rd, CRn, CRm, op2 }
+
+    /*
+     *  @brief Macro to abstract reading of a ARM coprocessor register via the MRC instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will receive the value read from the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7).
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MRC(cp,op1,Rd,CRn,CRm,op2)  __asm { MRC cp, op1, Rd, CRn, CRm, op2 }
+
+#elif NVOS_IS_LINUX || __GNUC__ // linux compilers
+
+    #if defined(__arm__)    // ARM GNU compiler
+
+    // Define the standard ARM coprocessor register names because the ARM compiler requires
+    // that we use the names and the GNU compiler requires that we use the numbers.
+    #define p14     14
+    #define p15     15
+    #define c0      0
+    #define c1      1
+    #define c2      2
+    #define c3      3
+    #define c4      4
+    #define c5      5
+    #define c6      6
+    #define c7      7
+    #define c8      8
+    #define c9      9
+    #define c10     10
+    #define c11     11
+    #define c12     12
+    #define c13     13
+    #define c14     14
+    #define c15     15
+
+    /*
+     *  @brief Macro to abstract writing of a ARM coprocessor register via the MCR instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will receive the value read from the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7).
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MCR(cp,op1,Rd,CRn,CRm,op2)  asm(" MCR " #cp",%1,%2,"#CRn","#CRm ",%5" \
+        : : "i" (cp), "i" (op1), "r" (Rd), "i" (CRn), "i" (CRm), "i" (op2))
+
+    /*
+     *  @brief Macro to abstract reading of a ARM coprocessor register via the MRC instruction.
+     *  @param cp is the coprocessor name (e.g., p15)
+     *  @param op1 is a coprocessor-specific operation code (must be a manifest constant).
+     *  @param Rd is a variable that will receive the value read from the coprocessor register.
+     *  @param CRn is the destination coprocessor register (e.g., c7).
+     *  @param CRm is an additional destination coprocessor register (e.g., c2).
+     *  @param op2 is a coprocessor-specific operation code (must be a manifest constant).
+    */
+    #define MRC(cp,op1,Rd,CRn,CRm,op2)  asm( " MRC " #cp",%2,%0," #CRn","#CRm",%5" \
+        : "=r" (Rd) : "i" (cp), "i" (op1), "i" (CRn), "i" (CRm), "i" (op2))
+
+    #else
+    
+    /* x86 processor. No such instructions. Callers should not call these macros
+     * when running on x86. If they do, it will compile but will not work. */
+    #define MCR(cp,op1,Rd,CRn,CRm,op2)  do { Rd = Rd; NV_ASSERT(0); } while (0)
+    #define MRC(cp,op1,Rd,CRn,CRm,op2)  do { Rd = 0; /*NV_ASSERT(0);*/ } while (0)
+
+    #endif
+#else
+
+    // !!!FIXME!!! TEST FOR ALL KNOWN COMPILERS -- FOR NOW JUST DIE AT RUN-TIME
+    // #error "Unknown compiler"
+    #define MCR(cp,op1,Rd,CRn,CRm,op2)  do { Rd = Rd; NV_ASSERT(0); } while (0)
+    #define MRC(cp,op1,Rd,CRn,CRm,op2)  do { Rd = 0; /*NV_ASSERT(0);*/ } while (0)
+
+#endif
+
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif // INCLUDED_ARM_CP_H
+
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_avp_shrd_interrupt.h b/arch/arm/mach-tegra/nv/include/nvrm_avp_shrd_interrupt.h
new file mode 100644
index 000000000000..579aab3c240d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_avp_shrd_interrupt.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_avp_shrd_interrupt_H
+#define INCLUDED_nvrm_avp_shrd_interrupt_H
+
+#include "nvos.h"
+#include "nvrm_init.h"
+#include "nvrm_module.h"
+#include "nvrm_interrupt.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+/* Max number of clients with shared interrupt handler */
+enum {MAX_SHRDINT_CLIENTS = 32};
+
+/* Now AP15 support only VDE interrupts 6 */
+enum {MAX_SHRDINT_INTERRUPTS = 6};
+    /* VDE Sync Token Interrupt */
+enum {AP15_SYNC_TOKEN_INTERRUPT_INDEX = 0};
+    /* VDE BSE-V Interrupt */
+enum {AP15_BSE_V_INTERRUPT_INDEX = 1};
+    /* VDE BSE-A Interrupt */
+enum {AP15_BSE_A_INTERRUPT_INDEX = 2};
+    /* VDE SXE Interrupt */
+enum {AP15_SXE_INTERRUPT_INDEX = 3};
+    /* VDE UCQ Error Interrupt */
+enum {AP15_UCQ_INTERRUPT_INDEX = 4};
+    /* VDE Interrupt */
+enum {AP15_VDE_INTERRUPT_INDEX = 5};
+
+/* Now AP20 support only VDE interrupts 5 */
+enum {AP20_MAX_SHRDINT_INTERRUPTS = 5};
+    /* VDE Sync Token Interrupt */
+enum {AP20_SYNC_TOKEN_INTERRUPT_INDEX = 0};
+    /* VDE BSE-V Interrupt */
+enum {AP20_BSE_V_INTERRUPT_INDEX = 1};
+    /* VDE SXE Interrupt */
+enum {AP20_SXE_INTERRUPT_INDEX = 2};
+    /* VDE UCQ Error Interrupt */
+enum {AP20_UCQ_INTERRUPT_INDEX = 3};
+    /* VDE Interrupt */
+enum {AP20_VDE_INTERRUPT_INDEX = 4};
+
+enum
+{
+    NvRmArbSema_Vde = 0,
+    NvRmArbSema_Bsea,
+    //This should be last
+    NvRmArbSema_Num,
+};
+
+/* Shared interrupt private init , init done during RM init on AVP */
+NvError NvRmAvpShrdInterruptPrvInit(NvRmDeviceHandle hRmDevice);
+
+/* Shared interrupt private de-init , de-init done during RM close on AVP */
+void NvRmAvpShrdInterruptPrvDeinit(NvRmDeviceHandle hRmDevice);
+
+/* Get logical interrupt for a module*/
+NvU32 NvRmAvpShrdInterruptGetIrqForLogicalInterrupt(NvRmDeviceHandle hRmDevice,
+                                                    NvRmModuleID ModuleID,
+                                                    NvU32 Index);
+/* Register for shared interrpt */
+NvError NvRmAvpShrdInterruptRegister(NvRmDeviceHandle hRmDevice,
+                                     NvU32 IrqListSize,
+                                     const NvU32 *pIrqList,
+                                     const NvOsInterruptHandler *pIrqHandlerList,
+                                     void *pContext,
+                                     NvOsInterruptHandle *handle,
+                                     NvU32 *ClientIndex);
+/* Un-register a shared interrpt */
+void NvRmAvpShrdInterruptUnregister(NvRmDeviceHandle hRmDevice,
+                                    NvOsInterruptHandle handle,
+                                    NvU32 ClientIndex);
+/* Get exclisive access to a hardware(VDE) block */
+NvError NvRmAvpShrdInterruptAquireHwBlock(NvRmModuleID ModuleID, NvU32 ClientId);
+
+/* Release exclisive access to a hardware(VDE) block */
+NvError NvRmAvpShrdInterruptReleaseHwBlock(NvRmModuleID ModuleID, NvU32 ClientId);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif //INCLUDED_nvrm_avp_shrd_interrupt_H
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_boot.h b/arch/arm/mach-tegra/nv/include/nvrm_boot.h
new file mode 100644
index 000000000000..75258d068ec9
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_boot.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_BOOT_H
+#define INCLUDED_NVRM_BOOT_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+/**
+ * Sets the RM chip shmoo data as a boot argument from the system's
+ * boot loader.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @retval NvSuccess If successful, or the appropriate error code.
+ */
+NvError NvRmBootArgChipShmooSet(NvRmDeviceHandle hRmDevice);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_NVRM_BOOT_H
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_diag.h b/arch/arm/mach-tegra/nv/include/nvrm_diag.h
new file mode 100644
index 000000000000..4ec86ed55f7e
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_diag.h
@@ -0,0 +1,552 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_diag_H
+#define INCLUDED_nvrm_diag_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+#include "nvcommon.h"
+
+/**
+ * All of the hardware modules.  Multiple instances are handled by the
+ * NVRM_DIAG_MODULE macro.
+ */
+
+typedef enum
+{
+    NvRmDiagModuleID_Cache = 1,
+    NvRmDiagModuleID_Vcp,
+    NvRmDiagModuleID_Host1x,
+    NvRmDiagModuleID_Display,
+    NvRmDiagModuleID_Ide,
+    NvRmDiagModuleID_3d,
+    NvRmDiagModuleID_Isp,
+    NvRmDiagModuleID_Usb,
+    NvRmDiagModuleID_2d,
+    NvRmDiagModuleID_Vi,
+    NvRmDiagModuleID_Epp,
+    NvRmDiagModuleID_I2s,
+    NvRmDiagModuleID_Pwm,
+    NvRmDiagModuleID_Twc,
+    NvRmDiagModuleID_Hsmmc,
+    NvRmDiagModuleID_Sdio,
+    NvRmDiagModuleID_NandFlash,
+    NvRmDiagModuleID_I2c,
+    NvRmDiagModuleID_Spdif,
+    NvRmDiagModuleID_Gpio,
+    NvRmDiagModuleID_Uart,
+    NvRmDiagModuleID_Timer,
+    NvRmDiagModuleID_Rtc,
+    NvRmDiagModuleID_Ac97,
+    NvRmDiagModuleID_Coprocessor,
+    NvRmDiagModuleID_Cpu,
+    NvRmDiagModuleID_Bsev,
+    NvRmDiagModuleID_Bsea,
+    NvRmDiagModuleID_Vde,
+    NvRmDiagModuleID_Mpe,
+    NvRmDiagModuleID_Emc,
+    NvRmDiagModuleID_Sprom,
+    NvRmDiagModuleID_Tvdac,
+    NvRmDiagModuleID_Csi,
+    NvRmDiagModuleID_Hdmi,
+    NvRmDiagModuleID_MipiBaseband,
+    NvRmDiagModuleID_Tvo,
+    NvRmDiagModuleID_Dsi,
+    NvRmDiagModuleID_Dvc,
+    NvRmDiagModuleID_Sbc,
+    NvRmDiagModuleID_Xio,
+    NvRmDiagModuleID_Spi,
+    NvRmDiagModuleID_NorFlash,
+    NvRmDiagModuleID_Slc,
+    NvRmDiagModuleID_Fuse,
+    NvRmDiagModuleID_Pmc,
+    NvRmDiagModuleID_StatMon,
+    NvRmDiagModuleID_Kbc,
+    NvRmDiagModuleID_Vg,
+    NvRmDiagModuleID_ApbDma,
+    NvRmDiagModuleID_Mc,
+    NvRmDiagModuleID_SpdifIn,
+    NvRmDiagModuleID_Vfir,
+    NvRmDiagModuleID_Cve,
+    NvRmDiagModuleID_ViSensor,
+    NvRmDiagModuleID_SystemReset,
+    NvRmDiagModuleID_AvpUcq,
+    NvRmDiagModuleID_KFuse,
+    NvRmDiagModuleID_OneWire,
+    NvRmDiagModuleID_SyncNor,
+    NvRmDiagModuleID_Pcie,
+    NvRmDiagModuleID_Num,
+    NvRmDiagModuleID_Force32 = 0x7FFFFFFF
+} NvRmDiagModuleID;
+
+/**
+ * Create a diag module id with multiple instances.
+ */
+#define NVRM_DIAG_MODULE( id, instance ) \
+    ((NvRmDiagModuleID)( (instance) << 16 | id ))
+
+/**
+ * Get the module id.
+ */
+#define NVRM_DIAG_MODULE_ID( id ) ((id) & 0xFFFF)
+
+/**
+ * Get the module instance.
+ */
+#define NVRM_DIAG_MODULE_INSTANCE( id ) (((id) >> 16) & 0xFFFF)
+
+/**
+ * Enable/disable support for individual clock diagnostic lock
+ */
+#define NVRM_DIAG_LOCK_SUPPORTED (0)
+
+/**
+ * Append clock configuration flags with diagnostic lock flag
+ */
+#define NvRmClockConfig_DiagLock ((NvRmClockConfigFlags_Num & (~0x01)) << 1)
+
+/**
+ * Defines clock source types
+ */
+
+typedef enum
+{
+
+    /// Clock source with fixed frequency
+        NvRmDiagClockSourceType_Oscillator = 1,
+
+    /// PLL clock source
+        NvRmDiagClockSourceType_Pll,
+
+    /// Clock scaler derives its clock from oscillators, PLLs or other scalers
+        NvRmDiagClockSourceType_Scaler,
+    NvRmDiagClockSourceType_Num,
+    NvRmDiagClockSourceType_Force32 = 0x7FFFFFFF
+} NvRmDiagClockSourceType;
+
+/**
+ * Defines types of clock scalers. Scale coefficient for all clock scalers
+ * is specified as (m, n) pair of 32-bit values. The interpretation of the
+ * m, n values for each type is clarified below.
+ */
+
+typedef enum
+{
+
+    /// No clock scaler: m = n = 1 always
+        NvRmDiagClockScalerType_NoScaler = 1,
+
+    /// Clock divider with m = 1 always, and n = 31.1 format
+    /// with half-step lowest bit
+        NvRmDiagClockScalerType_Divider_1_N,
+
+    /// Clock divider with rational (m+1)/(n+1) coefficient; m and n are
+    /// integeres, scale 1:1 is applied if m >= n
+        NvRmDiagClockScalerType_Divider_M_N,
+
+    /// Clock divider with rational (m+1)/16 coefficient, i.e., n = 16 always;
+    /// m is integer, scale 1:1 is applied if m >= 15 ("keeps" m + 1 clocks
+    /// out of every 16)
+        NvRmDiagClockScalerType_Divider_M_16,
+
+    /// Clock doubler: scale 2:1 if m != 0, scale 1:1 if m = 0,
+    /// n = 1 always 
+        NvRmDiagClockScalerType_Doubler,
+    NvRmDiagClockScalerType_Num,
+    NvRmDiagClockScalerType_Force32 = 0x7FFFFFFF
+} NvRmDiagClockScalerType;
+
+/**
+ * Defines RM thermal monitoring zones.
+ */
+
+typedef enum
+{
+
+    /// Specifies ambient temperature zone.
+        NvRmTmonZoneId_Ambient = 1,
+
+    /// Specifies SoC core temperature zone.
+        NvRmTmonZoneId_Core,
+    NvRmTmonZoneId_Num,
+    NvRmTmonZoneId_Force32 = 0x7FFFFFFF
+} NvRmTmonZoneId;
+
+/// Clock source opaque handle (TODO: replace forward idl declaration
+/// of <enum> with forward declaration of <handle>, when it is supported 
+typedef struct NvRmClockSourceInfoRec* NvRmDiagClockSourceHandle;
+
+/// Power rail opaque handle
+
+typedef struct NvRmDiagPowerRailRec *NvRmDiagPowerRailHandle;
+
+/**
+ * Enables diagnostic mode (disable is not allowed).  Clock, voltage, etc.,
+ * will no longer be controlled by the Resource Manager. The NvRmDiag
+ * interfaces should be used instead.
+ * 
+ * @param hDevice The RM device handle.
+ * 
+ * @retval NvSuccess if diagnostic mode is successfully enabled.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  diagnostic mode.
+ */
+
+ NvError NvRmDiagEnable( 
+    NvRmDeviceHandle hDevice );
+
+/**
+ * Lists modules present in the chip and available for diagnostic.
+ * 
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of Ids returned. If
+ *  entry size is 0, maximum list size is returned. 
+ * @param pIdList Pointer to the list of combined module Id/Instance values
+ *  to be filled in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the module list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */                               
+
+ NvError NvRmDiagListModules( 
+    NvU32 * pListSize,
+    NvRmDiagModuleID * pIdList );
+
+/**
+ * Lists available SoC clock sources.
+ * 
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of source handles
+ *  returned. If entry size is 0, maximum list size is returned.
+ * @param phSourceList Pointer to the list of source handles to be filled
+ *  in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the source list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */                               
+
+ NvError NvRmDiagListClockSources( 
+    NvU32 * pListSize,
+    NvRmDiagClockSourceHandle * phSourceList );
+
+/**
+ * Lists clock sources for the specified module.
+ * 
+ * @param id Combined Id and instance for the target module.
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of source handles
+ *  returned. If entry size is 0, maximum list size is returned.
+ * @param phSourceList Pointer to the list of source handles to be filled
+ *  in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the source list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagModuleListClockSources( 
+    NvRmDiagModuleID id,
+    NvU32 * pListSize,
+    NvRmDiagClockSourceHandle * phSourceList );
+
+/**
+ * Enables/Disables specified module clock.
+ * 
+ * @param id Combined Id and instance for the target module.
+ * @param enable Requested clock state - enabled if true, disabled if false
+ * 
+ * @retval NvSuccess if clock state changed successfully.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagModuleClockEnable( 
+    NvRmDiagModuleID id,
+    NvBool enable );
+
+/**
+ * Configures the clock for the specified module.
+ *
+ * @param id Combined Id and instance for the target module.
+ * @param hSource The handle of the clock source to drive the given module.
+ * @param divider 31.1 format: lowest bit is half-step. No range checking.
+ *  Half-step bit is ignored if module divider is not fractional. High 
+ *  bits are silently truncated if the value is out of h/w field range.
+ * @param Source1st If true, clock source is updated 1st, and the divider
+ *  is modified after the chip specific delay. If false, the order of update
+ *  is the reversed.
+ * 
+ * @retval NvSuccess if clock state changed successfully.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagModuleClockConfigure( 
+    NvRmDiagModuleID id,
+    NvRmDiagClockSourceHandle hSource,
+    NvU32 divider,
+    NvBool Source1st );
+
+/**
+ * Gets the name of the given clock source..
+ *
+ * @param hSource The target clock source handle.
+ * 
+ * @return The 64-bit packed 8-character name of the given clock source. Zero
+ *  will be returned if diagnostic mode is not enabled or the source is invalid.
+ */
+
+ NvU64 NvRmDiagClockSourceGetName( 
+    NvRmDiagClockSourceHandle hSource );
+
+/**
+ * Gets the type of the given clock source.
+ *
+ * @param hSource The target clock source handle.
+ * 
+ * @return The type of the given clock source. Zero will be returned if
+ *  diagnostic mode is not enabled or the source is invalid.
+ */
+
+ NvRmDiagClockSourceType NvRmDiagClockSourceGetType( 
+    NvRmDiagClockSourceHandle hSource );
+
+/**
+ * Gets the type of the scaler for the given clock source.
+ *
+ * @param hSource The target clock source handle.
+ * 
+ * @return The type of the scaler for the given clock source. Zero will be
+ *  be returned if diagnostic mode is not enabled or the source is invalid.
+ */
+
+ NvRmDiagClockScalerType NvRmDiagClockSourceGetScaler( 
+    NvRmDiagClockSourceHandle hSource );
+
+/**
+ * Lists input clock sources for the specified clock source.
+ * Primary oscillators have no input sources, and always return 0 as
+ * list size. Other sources (secondary sources with fixed frequency,
+ * PLLs and scalers) have 1 + input sources.
+ * 
+ * @param hSource The target clock source handle.
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of source handles
+ *  returned. If entry size is 0, maximum list size is returned.
+ * @param phSourceList Pointer to the list of source handles to be filled
+ *  in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the source list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagClockSourceListSources( 
+    NvRmDiagClockSourceHandle hSource,
+    NvU32 * pListSize,
+    NvRmDiagClockSourceHandle * phSourceList );
+
+/**
+ * Gets the given oscillator frequency in kHz.
+ *
+ * @param hOscillator The targeted oscillator/fixed frequency source handle.
+ * 
+ * @return The oscillator frequency in kHz. Zero will be returned if
+ *  diagnostic mode is not enabled or the target source is invalid.
+ */
+
+ NvU32 NvRmDiagOscillatorGetFreq( 
+    NvRmDiagClockSourceHandle hOscillator );
+
+/**
+ * Configures given PLL. Switches PLL in bypass mode, changes PLL settings,
+ * waits for PLL stabilization, and switches back to PLL output.
+ * 
+ * @param hPll The targeted PLL  handle.
+ * @param M Input divider settings (32-bit integer value)
+ * @param N Feedback divider settings (32-bit integer value)
+ * @param P Post divider settings (32-bit integer value)
+ *  If either M or N is zero PLL is left disabled and bypassed. Bsides that,
+ *  no other M, N, P parameters validation. High bits are silently truncated
+ *  if value is out of h/w field range.
+ * 
+ * @retval NvSuccess if clock state changed successfully.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagPllConfigure( 
+    NvRmDiagClockSourceHandle hPll,
+    NvU32 M,
+    NvU32 N,
+    NvU32 P );
+
+/**
+ * Configures specified clock scaler.
+ *
+ * @param hScaler The targeted Clock Scaler handle.
+ * @param hInput The handle of the input clock source to drive the
+ *  targeted scaler.
+ * @param M The dividend in the scaler coefficient (M/N) - 31.1 format:
+ *  lowest bit is half-step.
+ * @param N The divisor in the scaler coefficient (M/N) - 31.1 format:
+ *  lowest bit is half-step.
+ *  No range checking for M, N parameters. Half-step bit is ignored if
+ *  the scaler is not fractional. High bits are silently truncated if
+ *  the value is out of h/w field range.
+ *
+ * @retval NvSuccess if clock state changed successfully.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagClockScalerConfigure( 
+    NvRmDiagClockSourceHandle hScaler,
+    NvRmDiagClockSourceHandle hInput,
+    NvU32 M,
+    NvU32 N );
+
+/**
+ * Resets module.
+ * 
+ * @param id Combined Id and instance for the target module.
+ * @param KeepAsserted If true, reset will be kept asserted on exit.
+ *  If false, reset is kept asserted for chip specific delay, and
+ *  de-asserted on exit.
+ * 
+ * @retval NvSuccess if module reset completed successfully.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagModuleReset( 
+    NvRmDiagModuleID id,
+    NvBool KeepAsserted );
+
+/**
+ * Lists power rails.
+ * 
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of rail handles
+ *  returned. If entry size is 0, maximum list size is returned.
+ * @param phSourceList Pointer to the list of power rail handles to be filled
+ *  in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the source list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */                               
+
+ NvError NvRmDiagListPowerRails( 
+    NvU32 * pListSize,
+    NvRmDiagPowerRailHandle * phRailList );
+
+/**
+ * Gets the name of the given power rail.
+ *
+ * @param hRail The target power rail handle.
+ * 
+ * @return The 64-bit packed 8-character name of the given rail. Zero will be
+ *  returned if diagnostic mode is not enabled or the rail is invalid.
+ */
+
+ NvU64 NvRmDiagPowerRailGetName( 
+    NvRmDiagPowerRailHandle hRail );
+
+/**
+ * Lists power rails for the specified module.
+ * 
+ * @param id Combined Id and instance for the target module.
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the client, on exit - actual number of power rail handles
+ *  returned. If entry size is 0, maximum list size is returned.
+ * @param phRailList Pointer to the list of source handles to be filled
+ *  in by this function. Ignored if input list size is 0.
+ * 
+ * @retval NvSuccess if the power rail list is successfully returned.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagModuleListPowerRails( 
+    NvRmDiagModuleID id,
+    NvU32 * pListSize,
+    NvRmDiagPowerRailHandle * phRailList );
+
+/**
+ * Configures power rail voltage.
+ * 
+ * @param hRail The target power rail handle.
+ * @param VoltageMV The requested voltage level in millivolts.
+ * 
+ * @retval NvSuccess if the power rail is successfully configured.
+ * @retval NvError_NotInitialized if diagnostic mode is not enabled.
+ */
+
+ NvError NvRmDiagConfigurePowerRail( 
+    NvRmDiagPowerRailHandle hRail,
+    NvU32 VoltageMV );
+
+/**
+ * Verifies support for individual clock diagnostic lock (if supported
+ * clock frequency can be locked when diagnostic mode is disabled).
+ * 
+ * @retval NV_TRUE if individual clock diagnostic lock is supported.
+ * @retval NV_FALSE if individual clock diagnostic lock is not supported.
+ */
+
+ NvBool NvRmDiagIsLockSupported( 
+    void  );
+
+/**
+ * Gets temperature in the specified thermal zone (used for
+ * thermal profiling, does not require diagnostic mode to be enabled)
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ZoneId The targeted thermal zone ID.
+ * @param pTemperatureC Output storage pointer for zone temperature
+ *  (in degrees C).
+ * 
+ * @retval NvSuccess if temperature is returned successfully.
+ * @retval NvError_Busy if attempt to access temperature monitoring
+ *  device failed.
+ * @retval NvError_NotSupported if the specified zone is not monitored.
+ */
+
+ NvError NvRmDiagGetTemperature( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmTmonZoneId ZoneId,
+    NvS32 * pTemperatureC );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_dma.h b/arch/arm/mach-tegra/nv/include/nvrm_dma.h
new file mode 100644
index 000000000000..2ff199ae03f5
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_dma.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_dma_H
+#define INCLUDED_nvrm_dma_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           DMA Resource manager </b>
+ *
+ * @b Description: Defines the interface to the NvRM DMA.
+ * 
+ */
+
+/**
+ * @defgroup nvrm_dma Direct Memory Access (DMA) Controller API
+ * 
+ * This is the Dma interface.  These API provides the data transfer from memory
+ * to the selected destination and vice versa. The one end is the memory and 
+ * other end is the module selected by the dma module Id.
+ * This API allocates the channel based on priority request. Higher priority 
+ * channel can not be shared by other dma requestors. The low priority channel 
+ * is shared between the different requestors.
+ *
+ * @ingroup nvddk_rm
+ * 
+ * @{
+ */
+
+#include "nvos.h"
+
+/** 
+ * NvRmDmaHandle is an opaque context to the NvRmDmaRec interface
+ */
+
+typedef struct NvRmDmaRec *NvRmDmaHandle;
+
+/**
+ * @brief Defines the DMA capability structure for getting the capability of 
+ * the data transfer and any limitation if the dma manager have.
+ */
+
+typedef struct NvRmDmaCapabilitiesRec
+{
+
+    /// Holds the granularity of the data length for dma transfer in bytes
+        NvU32 DmaGranularitySize;
+
+    /// Holds the information if there is any address alignment limitation
+    /// is available in term of bytes.  if this value is 1 then there is no
+    /// limitation, any dma can transfer the data from any address. If this
+    /// value is 2 then the address should be 2 byte aligned always to do
+    /// the dma  transfer. If this value is 4 
+    /// then the address should be 4 byte aligned always to do the dma
+    /// transfer.
+        NvU32 DmaAddressAlignmentSize;
+} NvRmDmaCapabilities;
+
+/**
+ * @brief Defines the DMA client buffer information which is transferred 
+ * recently. The direction of data transfer decides based on this address. The 
+ * source address and destination address should be in line with the source 
+ * module Id and destination module Id.
+ */
+
+typedef struct NvRmDmaClientBufferRec
+{
+
+    /// Specifies the dma source buffer physical address for dma transfer. 
+        NvRmPhysAddr SourceBufferPhyAddress;
+
+    /// Specifies the dma destination buffer physical address for dma transfer.
+        NvRmPhysAddr DestinationBufferPhyAddress;
+
+    /// Source address wrap size in bytes. It tells that after how much bytes, 
+    /// it will be wrapped.
+    /// If it is zero then wrapping for source address is disabled.
+        NvU32 SourceAddressWrapSize;
+
+    /// Destination address wrap size in bytes. It tells that after how much 
+    /// bytes, it will be wrapped. If it is zero then wrapping for destination 
+    /// address is disabled.
+        NvU32 DestinationAddressWrapSize;
+
+    /// Specifies the size of the buffer in bytes which is requested for
+    /// transfer.
+        NvU32 TransferSize;
+} NvRmDmaClientBuffer;
+
+/**
+ * @brief Specify the name of modules which can be supported by nvrm dma
+ * drivers.  These dma modules can be either source or destination based on
+ * direction.
+ */
+
+typedef enum
+{
+
+    /// Specifies the dma module Id as Invalid
+        NvRmDmaModuleID_Invalid = 0x0,
+
+    /// Specifies the dma module Id for memory
+        NvRmDmaModuleID_Memory,
+
+    /// Specifies the dma module Id for I2s controller.
+        NvRmDmaModuleID_I2s,
+
+    /// Specifies the dma module Id for Ac97 controller.
+        NvRmDmaModuleID_Ac97,
+
+    /// Specifies the dma module Id for Spdif controller.
+        NvRmDmaModuleID_Spdif,
+
+    /// Specifies the dma module Id for uart controller.
+        NvRmDmaModuleID_Uart,
+
+    /// Specifies the dma module Id for Vfir controller.
+        NvRmDmaModuleID_Vfir,
+
+    /// Specifies the dma module Id for Mipi controller.
+        NvRmDmaModuleID_Mipi,
+
+    /// Specifies the dma module Id for spi controller.
+        NvRmDmaModuleID_Spi,
+
+    /// Specifies the dma module Id for slink controller.
+        NvRmDmaModuleID_Slink,
+
+    /// Specifies the dma module Id for I2c controller.
+        NvRmDmaModuleID_I2c,
+
+    /// Specifies the dma module Id for Dvc I2c controller.
+        NvRmDmaModuleID_Dvc,
+
+    /// Specifies the maximum number of modules supported.
+        NvRmDmaModuleID_Max,
+    NvRmDmaModuleID_Num,
+    NvRmDmaModuleID_Force32 = 0x7FFFFFFF
+} NvRmDmaModuleID;
+
+/**
+ * @brief Specify the direction of the transfer, either outbound data
+ * (source -> dest) or inboud data (source <- dest)
+ */
+
+typedef enum
+{
+
+    /// Specifies the direction of the transfer to be srcdevice -> dstdevice
+        NvRmDmaDirection_Forward = 0x1,
+
+    /// Specifies the direction of the transfer to be dstdevice -> srcdevice
+        NvRmDmaDirection_Reverse,
+    NvRmDmaDirection_Num,
+    NvRmDmaDirection_Force32 = 0x7FFFFFFF
+} NvRmDmaDirection;
+
+/**
+ * @brief Specify the priority of the dma either low priority or high priority.
+ */
+
+typedef enum
+{
+
+    /// Low priority DMA, no guarantee of latency to start transactions
+        NvRmDmaPriority_Low = 0x1,
+
+    /// High priority DMA guarantees the first buffer you send the 
+    /// NvRmDmaStartDmaTransfer() will begin immediately.
+        NvRmDmaPriority_High,
+    NvRmDmaPriority_Num,
+    NvRmDmaPriority_Force32 = 0x7FFFFFFF
+} NvRmDmaPriority;
+
+/**
+ * @brief Get the capabilities of the dma channels.
+ * 
+ * @param hDevice Handle to RM device.
+ * @param pRmDmaCaps Pointer to the capability structure where the cpas value 
+ * will be stored.
+ *
+ * @retval NvSuccess Indicates the function completed successfully.
+ */
+
+ NvError NvRmDmaGetCapabilities( 
+    NvRmDeviceHandle hDevice,
+    NvRmDmaCapabilities * pRmDmaCaps );
+
+/**
+ * @brief Allocate the DMA channel for the data transfer. The dma is allocated
+ * based on the dma device Id information. Most of the configuration is also
+ * done based on the source/destination device Id during the channel
+ * allocation.  It initializes the channel also with standard configuration
+ * based on source/ destination device.  The data is transferred from memory to
+ * the dma requestor device or vice versa.  The dma requestors device can be
+ * memory or any peripheral device listed in the NvRmDmaDeviceId.
+ * 
+ * Assert encountered in debug mode if passed parameter is invalid.
+ *
+ * @param hRmDevice Handle to RM device.
+ * @param phDma Pointer to the dma handle where the allocated dma handle
+ * will be stored.
+ * @param Enable32bitSwap if set to NV_TRUE will unconditionally reverse the
+ * memory order of bytes on 4-byte chunks.  D3:D2:D1:D0 becomes D0:D1:D2:D3
+ * @param Priority Selects either Hi or Low priority.  A Low priority
+ * allocation will only fail if the system is out of memory, and transfers on a
+ * Low priority channel will be intermixed with other clients of that channel.
+ * Hi priority allocations may fail if there is not a dedicated channel
+ * available for the Hi priority client.  Hi priority channels should only be
+ * used if you have very specific latency requirements.
+ * @param DmaRequestorModuleId Specifies a source module Id.
+ * @param DmaRequestorInstanceId Specifies the instance of the source module.
+ * 
+ * @retval NvSuccess Indicates the function completed successfully.
+ * @retval NvDMAChannelNotAvailable Indicates that there is no channel
+ * available for allocation.
+ * @retval NvError_InsufficientMemory Indicates that it will not able to
+ * allocate the memory for dma handles.
+ * @retval NvDMAInvalidSourceId Indicates that device requested is not the
+ * valid device.
+ * @retval NvError_MemoryMapFailed Indicates that the memory mapping for 
+ * controller register failed.
+ * @retval NvError_MutexCreateFailed Indicates that the creation of mutex
+ * failed.  Mutex is required to provide the thread safety.
+ * @retval NvError_SemaphoreCreateFailed Indicates that the creation of 
+ * semaphore failed. Semaphore is required to provide the synchronization and 
+ * also used in synchronous operation.
+ *
+ */
+
+ NvError NvRmDmaAllocate( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmDmaHandle * phDma,
+    NvBool Enable32bitSwap,
+    NvRmDmaPriority Priority,
+    NvRmDmaModuleID DmaRequestorModuleId,
+    NvU32 DmaRequestorInstanceId );
+
+/**
+ * Frees the channel so that it can be reused by other clients.  This function
+ * will block until all currently enqueued transfers complete.
+ *
+ * @note: We may change the functionality so that Free() returns immediately
+ * but internally the channel remains in an alloc'd state until all transfers
+ * complete.
+ *
+ * @param hDma A DMA handle from NvRmDmaAllocate.  If hDma is NULL, this API has
+ *     no effect.
+ */
+
+ void NvRmDmaFree( 
+    NvRmDmaHandle hDma );
+
+/**
+ * @brief Starts the DMA channel for data transfer.
+ * 
+ * Assert encountered in debug mode if passed parameter is invalid.
+ *
+ * @param hDma Specifies a DMA handle which is allocated by the Rm dma from 
+ * NvRmDmaAllocate.
+ * @param pClientBuffer Specifies a pointer to the client information which 
+ * contains the start buffer, destination buffer, and number of bytes 
+ * transferred.
+ * @param DmaDirection Specifies whether the transfer is Forward src->dst or
+ * Reverse dst->src direction.
+ * @param WaitTimeoutInMilliSecond The time need to wait in milliseconds. If it
+ * is zero then it will be returned immediately as asynchronous operation. If
+ * is non zero then it will wait for a requested timeout. If it is
+ * NV_WAIT_INFINITE then it will wait for infinitely till transaction
+ * completes.
+ * @param AsynchSemaphoreId The semaphore Id which need to be signal if client 
+ * is requested for asynchronous operation.  Pass NULL if not semaphore should 
+ * be signalled when the transfer is complete.
+ * 
+ * @retval NvSuccess Indicates the function completed successfully.
+ * @retval NvError_InvalidAddress Indicates that the address for source or 
+ * destination is invalid.
+ * @retval NvError_InvalidSize Indicates that the bytes requested is invalid.
+ * @retval NvError_Timeout Indicates that transfer is not completed in a
+ * expected time and timeout happen.
+ */
+
+ NvError NvRmDmaStartDmaTransfer( 
+    NvRmDmaHandle hDma,
+    NvRmDmaClientBuffer * pClientBuffer,
+    NvRmDmaDirection DmaDirection,
+    NvU32 WaitTimeoutInMilliSecond,
+    NvOsSemaphoreHandle AsynchSemaphoreId );
+
+/**
+ * @brief Aborts the currently running transfer as well as any other transfers 
+ * that are queued up behind the currently running transfer.
+ * 
+ * @param hDma Specifies a DMA handle which is allocated by the Rm dma from 
+ * NvRmDmaAllocate.
+ */
+
+ void NvRmDmaAbort( 
+    NvRmDmaHandle hDma );
+
+/**
+ * @brief Get the number of bytes transferred by the dma in current tranaction 
+ * from the last.
+ * 
+ * This will tell the number of bytes has been transferred by the dma yet from 
+ * the last transfer completes.
+ *
+ * @param hDma Specifies a DMA handle which is allocated by the Rm dma from 
+ * NvRmDmaAllocate.
+ * @param pTransferCount Pointer to the variable where number of bytes transferred 
+ * by dma will be stored.
+ * @param IsTransferStop Tells whether the current transfer is stopped or not.
+ *
+ * @retval NvSuccess Indicates the function completed successfully.
+ * @retval NvError_InvalidState The transfer is not going on.
+ */
+
+ NvError NvRmDmaGetTransferredCount( 
+    NvRmDmaHandle hDma,
+    NvU32 * pTransferCount,
+    NvBool IsTransferStop );
+
+/**
+ * @brief Tells whether the transfer is completed or not for the given dma transfer.
+ * 
+ * This will tells the first or second half of the buffer transfer for the requestor
+ * who uses the double buffering mechanism like i2s.
+ *
+ * @param hDma Specifies a DMA handle which is allocated by the Rm dma from 
+ * NvRmDmaAllocate.
+ * @param IsFirstHalfBuffer Tells whether the first half or second half of the dma transfer.
+ *
+ * @retval NV_TRUE indicates that the transfre has been completed.
+ * @retval NV_FALSE Indicates that the transfre is going on.
+ */
+
+ NvBool NvRmDmaIsDmaTransferCompletes( 
+    NvRmDmaHandle hDma,
+    NvBool IsFirstHalfBuffer );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_drf.h b/arch/arm/mach-tegra/nv/include/nvrm_drf.h
new file mode 100644
index 000000000000..cc5cbe0cb4a3
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_drf.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_DRF_H
+#define INCLUDED_NVRM_DRF_H
+
+/**
+ *  @defgroup nvrm_drf RM DRF Macros
+ * 
+ *  @ingroup nvddk_rm
+ * 
+ * The following suite of macros are used for generating values to write into
+ * hardware registers, or for extracting fields from read registers.  The
+ * hardware headers have a RANGE define for each field in the register in the
+ * form of x:y, 'x' being the high bit, 'y' the lower.  Through a clever use
+ * of the C ternary operator, x:y may be passed into the macros below to
+ * geneate masks, shift values, etc.
+ *
+ * There are two basic flavors of DRF macros, the first is used to define
+ * a new register value from 0, the other is modifiying a field given a
+ * register value.  An example of the first:
+ *
+ * reg = NV_DRF_DEF( HW, REGISTER0, FIELD0, VALUE0 )
+ *     | NV_DRF_DEF( HW, REGISTER0, FIELD3, VALUE2 );
+ *
+ * To modify 'reg' from the previous example:
+ *
+ * reg = NV_FLD_SET_DRF_DEF( HW, REGISTER0, FIELD2, VALUE1, reg );
+ *
+ * To pass in numeric values instead of defined values from the header:
+ *
+ * reg = NV_DRF_NUM( HW, REGISTER3, FIELD2, 1024 );
+ *
+ * To read a value from a register:
+ *
+ * val = NV_DRF_VAL( HW, REGISTER3, FIELD2, reg );
+ *
+ * Some registers have non-zero reset values which may be extracted from the
+ * hardware headers via NV_RESETVAL.
+ */
+
+/*
+ * The NV_FIELD_* macros are helper macros for the public NV_DRF_* macros.
+ */
+#define NV_FIELD_LOWBIT(x)      (0?x)
+#define NV_FIELD_HIGHBIT(x)     (1?x)
+#define NV_FIELD_SIZE(x)        (NV_FIELD_HIGHBIT(x)-NV_FIELD_LOWBIT(x)+1)
+#define NV_FIELD_SHIFT(x)       ((0?x)%32)
+#define NV_FIELD_MASK(x)        (0xFFFFFFFFUL>>(31-((1?x)%32)+((0?x)%32)))
+#define NV_FIELD_BITS(val, x)   (((val) & NV_FIELD_MASK(x))<<NV_FIELD_SHIFT(x))
+#define NV_FIELD_SHIFTMASK(x)   (NV_FIELD_MASK(x)<< (NV_FIELD_SHIFT(x)))
+
+/** NV_DRF_DEF - define a new register value.
+
+    @ingroup nvrm_drf
+ 
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param c defined value for the field
+ */
+#define NV_DRF_DEF(d,r,f,c) \
+    ((d##_##r##_0_##f##_##c) << NV_FIELD_SHIFT(d##_##r##_0_##f##_RANGE))
+
+/** NV_DRF_NUM - define a new register value.
+
+    @ingroup nvrm_drf
+ 
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param n numeric value for the field
+ */
+#define NV_DRF_NUM(d,r,f,n) \
+    (((n)& NV_FIELD_MASK(d##_##r##_0_##f##_RANGE)) << \
+        NV_FIELD_SHIFT(d##_##r##_0_##f##_RANGE))
+
+/** NV_DRF_VAL - read a field from a register.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param v register value
+ */
+#define NV_DRF_VAL(d,r,f,v) \
+    (((v)>> NV_FIELD_SHIFT(d##_##r##_0_##f##_RANGE)) & \
+        NV_FIELD_MASK(d##_##r##_0_##f##_RANGE))
+
+/** NV_FLD_SET_DRF_NUM - modify a register field.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param n numeric field value
+    @param v register value
+ */
+#define NV_FLD_SET_DRF_NUM(d,r,f,n,v) \
+    ((v & ~NV_FIELD_SHIFTMASK(d##_##r##_0_##f##_RANGE)) | NV_DRF_NUM(d,r,f,n))
+
+/** NV_FLD_SET_DRF_DEF - modify a register field.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param c defined field value
+    @param v register value
+ */
+#define NV_FLD_SET_DRF_DEF(d,r,f,c,v) \
+    (((v) & ~NV_FIELD_SHIFTMASK(d##_##r##_0_##f##_RANGE)) | \
+        NV_DRF_DEF(d,r,f,c))
+
+/** NV_RESETVAL - get the reset value for a register.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+ */
+#define NV_RESETVAL(d,r)    (d##_##r##_0_RESET_VAL)
+
+#endif // INCLUDED_NVRM_DRF_H
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_gpio.h b/arch/arm/mach-tegra/nv/include/nvrm_gpio.h
new file mode 100644
index 000000000000..62a711638621
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_gpio.h
@@ -0,0 +1,389 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_gpio_H
+#define INCLUDED_nvrm_gpio_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit NvRm gpio APIs</b>
+ *
+ * @b Description: Declares Interface for NvRm gpio module.
+ */
+
+ /**
+ * @defgroup nvrm_gpio RM GPIO Services
+ * 
+ * This is the Resource Manager interface to general-purpose input-output
+ * (GPIO) services. Fundamental abstraction of this API is a "pin handle", which
+ * of type NvRmGpioPinHandle. A Pin handle is acquired by making a call to 
+ * NvRmGpioAcquirePinHandle API. This API returns a pin handle which is
+ * subsequently used by the rest of the GPIO APIs.
+ *
+ * @ingroup nvddk_rm
+ * @{
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+
+/**
+ *  NvRmGpioHandle is an opaque handle to the GPIO device on the chip.
+ */
+
+typedef struct NvRmGpioRec *NvRmGpioHandle;
+
+/**
+ * @brief GPIO pin handle which describes the physical pin. This values should
+ * not be cached or hardcoded by the drivers. This can vary from chip to chip
+ * and board to board.
+ */
+ 
+typedef NvU32 NvRmGpioPinHandle;
+
+/**
+ * @brief Defines the possible gpio pin modes.
+ */
+
+typedef enum
+{
+
+    /**
+     * Specifies the gpio pin as not in use. When in this state, the RM or
+     * ODM Kit may park the pin in a board-specific state in order to
+     * minimize leakage current.
+     */
+    NvRmGpioPinMode_Inactive = 1,
+
+    /// Specifies the gpio pin mode as input and enable interrupt for level low.
+    NvRmGpioPinMode_InputInterruptLow,
+
+    /// Specifies the gpio pin mode as input and enable interrupt for level high.
+    NvRmGpioPinMode_InputInterruptHigh,
+
+    /// Specifies the gpio pin mode as input and no interrupt configured.
+    NvRmGpioPinMode_InputData,
+
+    /// Specifies the gpio pin mode as output.
+    NvRmGpioPinMode_Output,
+
+    /// Specifies the gpio pin mode as a special function.
+    NvRmGpioPinMode_Function,
+
+    /// Specifies the gpio pin as input and interrupt configured to any edge.
+    /// i.e seamphore will be signaled for both the rising and failling edges.
+    NvRmGpioPinMode_InputInterruptAny,
+
+    /// Sepciifed the gpio pin a input and interrupt configured to rising edge.
+    NvRmGpioPinMode_InputInterruptRisingEdge,
+
+    /// Sepciifed the gpio pin a input and interrupt configured to falling edge.
+    NvRmGpioPinMode_InputInterruptFallingEdge,
+    NvRmGpioPinMode_Num,
+    NvRmGpioPinMode_Force32 = 0x7FFFFFFF
+} NvRmGpioPinMode;
+
+/** 
+ * @brief Defines the pin state
+ */
+
+typedef enum
+{
+
+   // Pin state high 
+    NvRmGpioPinState_Low = 0,
+
+    // Pin is high
+    NvRmGpioPinState_High,
+  
+    // Pin is in tri state 
+    NvRmGpioPinState_TriState,
+    NvRmGpioPinState_Num,
+    NvRmGpioPinState_Force32 = 0x7FFFFFFF
+} NvRmGpioPinState;
+
+// Gnerates a contruct the pin handle till the NvRmGpioAcquirePinHandle
+// API is implemented.
+#define GPIO_MAKE_PIN_HANDLE(inst, port, pin)  (0x80000000 | (((NvU32)(pin) & 0xFF)) | (((NvU32)(port) & 0xff) << 8) | (((NvU32)(inst) & 0xff )<< 16))
+#define NVRM_GPIO_CAMERA_PORT (0xfe)
+#define NVRM_GPIO_CAMERA_INST (0xfe)
+
+/**
+ * Creates and opens a GPIO handle. The handle can then be used to
+ * access GPIO functions.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param phGpio Specifies a pointer to the gpio handle where the
+ * allocated handle is stored. The memory for handle is allocated
+ * inside this API.
+ * 
+ * @retval NvSuccess gpio initialization is successful.
+ */
+
+ NvError NvRmGpioOpen( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmGpioHandle * phGpio );
+
+/**
+ * Closes the GPIO handle. Any pin settings made while this handle was
+ * open will remain. All events enabled by this handle will be
+ * disabled.
+ * 
+ * @param hGpio A handle from NvRmGpioOpen().  If hGpio is NULL, this API does
+ *     nothing.
+ */
+
+ void NvRmGpioClose( 
+    NvRmGpioHandle hGpio );
+
+/** Get NvRmGpioPinHandle from the physical port and pin number. If a driver
+ * acquires a pin handle another driver will not be able to use this until the
+ * pin is released.
+ *
+ * @param hGpio A handle from NvRmGpioOpen().
+ * @param port Physical gpio ports which are chip specific.
+ * @param pinNumber pin number in that port.
+ * @param phGpioPin Pointer to the GPIO pin handle.
+ */
+
+ NvError NvRmGpioAcquirePinHandle( 
+    NvRmGpioHandle hGpio,
+    NvU32 port,
+    NvU32 pin,
+    NvRmGpioPinHandle * phPin );
+
+/** Releases the pin handles acquired by NvRmGpioAcquirePinHandle API.
+ *
+ * @param hGpio A handle got from NvRmGpioOpen().
+ * @param hPin Array of pin handles got from NvRmGpioAcquirePinHandle().
+ * @param pinCount Size of pin handles array.
+ */
+
+ void NvRmGpioReleasePinHandles( 
+    NvRmGpioHandle hGpio,
+    NvRmGpioPinHandle * hPin,
+    NvU32 pinCount );
+
+/**
+ * Sets the state of array of pins.
+ *
+ * NOTE:  When multiple pins are specified (pinCount is greater than
+ * one), ODMs should not make assumptions about the order in which
+ * pins are updated.  The implementation will attempt to coalesce
+ * updates to occur atomically; however, this can not be guaranteed in
+ * all cases, and may not occur if the list of pins includes pins from
+ * multiple ports.
+ *
+ * @param hGpio Specifies the gpio handle.
+ * @param pin Array of pin handles.
+ * @param pinState Array of elements specifying the pin state (of type
+ * NvRmGpioPinState).
+ * @param pinCount Number of elements in the array.
+ */
+
+ void NvRmGpioWritePins( 
+    NvRmGpioHandle hGpio,
+    NvRmGpioPinHandle * pin,
+    NvRmGpioPinState * pinState,
+    NvU32 pinCount );
+
+/**
+ * Reads the state of array of pins.
+ * 
+ * @param hGpio The gpio handle.
+ * @param pin Array of pin handles.
+ * @param pinState Array of elements specifying the pin state (of type
+ * NvRmGpioPinState).
+ * @param pinCount Number of elements in the array.
+ */
+
+ void NvRmGpioReadPins( 
+    NvRmGpioHandle hGpio,
+    NvRmGpioPinHandle * pin,
+    NvRmGpioPinState * pPinState,
+    NvU32 pinCount );
+
+/**
+ * Configures a set of GPIO pins to a specified mode. Don't use this API for
+ * the interrupt modes. For interrupt modes, use NvRmGpioInterruptRegister and
+ * NvRmGpioInterruptUnregister APIs.
+ *
+ * @param hGpio The gpio handle.
+ * @param pin Pin handle array returned by a calls to NvRmGpioAcquirePinHandle()
+ * @param pinCount Number elements in the pin handle array.
+ *
+ * @param Mode Pin mode of type NvRmGpioPinMode.
+ * 
+ * 
+ * @retval NvSuccess requested operation is successful.
+ */
+
+ NvError NvRmGpioConfigPins( 
+    NvRmGpioHandle hGpio,
+    NvRmGpioPinHandle * pin,
+    NvU32 pinCount,
+    NvRmGpioPinMode Mode );
+
+/*
+ *  Get the IRQs associated with the pin handles. So that the client can
+ *  register the interrupt callback for that using interrupt APIs
+ */
+
+ NvError NvRmGpioGetIrqs( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmGpioPinHandle * pin,
+    NvU32 * Irq,
+    NvU32 pinCount );
+
+/** 
+ *   Opaque handle to the GPIO interrupt.
+ */
+
+typedef struct NvRmGpioInterruptRec *NvRmGpioInterruptHandle;
+
+
+/* NOTE: Use the 2 APIs below to configure the gpios to interrupt mode and to
+ * have callabck functions. For the test case of how to use this APIs refer to
+ * the nvrm_gpio_unit_test applicaiton. 
+ * 
+ *  Since the ISR is written by the clients of the API, care should be taken to
+ *  clear the interrupt before the ISR is returned. If one fails to do that,
+ *  interrupt will be triggered soon after the ISR returns.
+ */
+
+/**
+ * Registers an interrupt callback function and the mode of interrupt for the
+ * gpio pin specified.
+ *  
+ * Callback will be using the interrupt thread an the interrupt stack on linux
+ * and IST on wince. So, care should be taken on what APIs can be used on the
+ * callback function. Not all the nvos functions are available in the interrupt
+ * context. Check the nvos.h header file for the list of the functions available.
+ * When the callback is called, the interrupt on the pin is disabled. As soon as
+ * the callback exists, the interrupt is re-enabled. So, external interrupts
+ * should be cleared and then only the callback should be returned.
+ *
+ * @param hGpio The gpio handle.
+ * @param hRm The RM device handle.
+ * @param hPin The handle to a GPIO pin.
+ * @param Callback Callback function which will be caused when the interrupt
+ * triggers.
+ * @param Mode Interrupt mode. See @NvRmGpioPinMode
+ * @param CallbackArg Argument used when the callback is called by the ISR.
+ * @param hGpioInterrupt Interrupt handle for this registered intterrupt. This
+ * handle should be used while calling NvRmGpioInterruptUnregister for
+ * unregistering the interrupt.
+ * @param DebounceTime The debounce time in milliseconds
+ * @retval NvSuccess requested operation is successful.
+ */
+NvError 
+NvRmGpioInterruptRegister(
+    NvRmGpioHandle hGpio,
+    NvRmDeviceHandle hRm,
+    NvRmGpioPinHandle hPin, 
+    NvOsInterruptHandler Callback,
+    NvRmGpioPinMode Mode,
+    void *CallbackArg,
+    NvRmGpioInterruptHandle *hGpioInterrupt,
+    NvU32 DebounceTime);
+
+/**
+ * Unregister the GPIO interrupt handler.
+ *
+ * @param hGpio The gpio handle.
+ * @param hRm The RM device handle.
+ * @param handle The interrupt handle returned by a successfull call to the
+ * NvRmGpioInterruptRegister API.
+ *
+ */
+void 
+NvRmGpioInterruptUnregister(
+    NvRmGpioHandle hGpio,
+    NvRmDeviceHandle hRm,
+    NvRmGpioInterruptHandle handle);
+
+/**
+ * Enable the GPIO interrupt handler.
+ *
+ * @param handle The interrupt handle returned by a successfull call to the
+ * NvRmGpioInterruptRegister API.
+ *
+ * @retval "NvError_BadParameter" if handle is not valid
+ * @retval "NvError_InsufficientMemory" if interupt enable failed.
+ * @retval "NvSuccess" if registration is successfull.
+*/
+NvError
+NvRmGpioInterruptEnable(NvRmGpioInterruptHandle handle);
+
+/* 
+ * Callback used to re-enable the interrupts.
+ *
+ * @param handle The interrupt handle returned by a successfull call to the
+ * NvRmGpioInterruptRegister API.
+ */
+void
+NvRmGpioInterruptDone( NvRmGpioInterruptHandle handle );
+
+
+
+/**
+ * Mask/Unmask a gpio interrupt.
+ *
+ * Drivers can use this API to fend off interrupts. Mask means interrupts are
+ * not forwarded to the CPU. Unmask means, interrupts are forwarded to the CPU.
+ * In case of SMP systems, this API masks the interrutps to all the CPU, not
+ * just the calling CPU.
+ *
+ *
+ * @param handle    Interrupt handle returned by NvRmGpioInterruptRegister API.
+ * @param mask      NV_FALSE to forrward the interrupt to CPU. NV_TRUE to 
+ * mask the interupts to CPU.
+ */
+void
+NvRmGpioInterruptMask(NvRmGpioInterruptHandle hGpioInterrupt, NvBool mask);
+
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_hardware_access.h b/arch/arm/mach-tegra/nv/include/nvrm_hardware_access.h
new file mode 100644
index 000000000000..497fd94e57a1
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_hardware_access.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_HARDWARE_ACCESS_H
+#define INCLUDED_NVRM_HARDWARE_ACCESS_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+#include "nvos.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+#if !defined(NV_OAL)
+#define NV_OAL 0
+#endif
+
+// By default, sim is supported on WinXP/x86 and Linux/x86 builds only.
+#if !defined(NV_DEF_ENVIRONMENT_SUPPORTS_SIM)
+#if NVCPU_IS_X86 && ((NVOS_IS_WINDOWS && !NVOS_IS_WINDOWS_CE) || NVOS_IS_LINUX) && !NV_OAL
+#define NV_DEF_ENVIRONMENT_SUPPORTS_SIM 1
+#else
+#define NV_DEF_ENVIRONMENT_SUPPORTS_SIM 0
+#endif
+#endif
+
+/**
+ * NV_WRITE* and NV_READ* - low level read/write api to hardware.
+ *
+ * These macros should be used to read and write registers and memory
+ * in NvDDKs so that the DDK will work on simulation and real hardware
+ * with no changes.
+ *
+ * This is for hardware modules that are NOT behind the host.  Modules that
+ * are behind the host should use nvrm_channel.h.
+ *
+ * A DDK can obtain a mapping to its registers by using the
+ * NvRmPhysicalMemMap() function.  This mapping is always uncached.  The
+ * resulting pointer can then be used with NV_READ and NV_WRITE.
+ */
+
+/*
+ * Maps the given physical address to the user's virtual address space.
+ *
+ * @param phys The physical address to map into the virtual address space
+ * @param size The size of the mapping
+ * @param flags Any flags for the mapping -- exactly match's NVOS_MAP_*
+ * @param memType The memory mapping to use (uncached, write-combined, etc.)
+ * @param ptr Output -- the resulting virtual pointer
+ */
+// FIXME: NvOs needs to take this up, however I think this is more
+// complex than just mapping.  E.G. does it map into the kernel vaddr, or
+// the current process vaddr? And how does this work on windows and
+// windows-ce?
+NvError NvRmPhysicalMemMap(NvRmPhysAddr phys, size_t size, NvU32 flags,
+    NvOsMemAttribute memType, void **ptr );
+
+/*
+ * Unmaps the given virtual address from NvRmPhysicalMemMap.
+ */
+void NvRmPhysicalMemUnmap(void *ptr, size_t size);
+
+/**
+ * NV_WRITE[8|16|32|64] - Writes N data bits to hardware.
+ *
+ *   @param a The address to write.
+ *   @param d The data to write.
+ */
+
+/**
+ * NV_READ[8|16|32|64] - Reads N bits from hardware.
+ *
+ * @param a The address to read.
+ */
+
+void NvWrite08(void *addr, NvU8 data);
+void NvWrite16(void *addr, NvU16 data);
+void NvWrite32(void *addr, NvU32 data);
+void NvWrite64(void *addr, NvU64 data);
+NvU8 NvRead08(void *addr);
+NvU16 NvRead16(void *addr);
+NvU32 NvRead32(void *addr);
+NvU64 NvRead64(void *addr);
+void NvWriteBlk(void *dst, const void *src, NvU32 length);
+void NvReadBlk(void *dst, const void *src, NvU32 length);
+
+#if NV_DEF_ENVIRONMENT_SUPPORTS_SIM == 1
+
+#define NV_WRITE08(a,d)     NvWrite08((void *)(a),(d))
+#define NV_WRITE16(a,d)     NvWrite16((void *)(a),(d))
+#define NV_WRITE32(a,d)     NvWrite32((void *)(a),(d))
+#define NV_WRITE64(a,d)     NvWrite64((void *)(a),(d))
+#define NV_READ8(a)         NvRead08((void *)(a))
+#define NV_READ16(a)        NvRead16((void *)(a))
+#define NV_READ32(a)        NvRead32((void *)(a))
+#define NV_READ64(a)        NvRead64((void *)(a))
+#define NV_WRITE(dst, src, len) NvWriteBlk(dst, src, len)
+#define NV_READ(dst, src, len)  NvReadBlk(dst, src, len)
+
+#else
+/* connected to hardware */
+
+#define NV_WRITE08(a,d)     *((volatile NvU8 *)(a)) = (d)
+#define NV_WRITE16(a,d)     *((volatile NvU16 *)(a)) = (d)
+#define NV_WRITE32(a,d)     *((volatile NvU32 *)(a)) = (d)
+#define NV_WRITE64(a,d)     *((volatile NvU64 *)(a)) = (d)
+#define NV_READ8(a)         *((const volatile NvU8 *)(a))
+#define NV_READ16(a)        *((const volatile NvU16 *)(a))
+#define NV_READ32(a)        *((const volatile NvU32 *)(a))
+#define NV_READ64(a)        *((const volatile NvU64 *)(a))
+#define NV_WRITE(dst, src, len)  NvOsMemcpy(dst, src, len)
+#define NV_READ(dst, src, len)   NvOsMemcpy(dst, src, len)
+
+#endif // !hardware
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_HARDWARE_ACCESS_H
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_i2c.h b/arch/arm/mach-tegra/nv/include/nvrm_i2c.h
new file mode 100644
index 000000000000..5cc245def79b
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_i2c.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_i2c_H
+#define INCLUDED_nvrm_i2c_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_pinmux.h"
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvos.h"
+#include "nvcommon.h"
+
+/**
+ * NvRmI2cHandle is an opaque handle to the NvRmI2cStructRec interface
+ */
+ 
+typedef struct NvRmI2cRec *NvRmI2cHandle;
+
+/**
+ * @brief Defines the I2C capability structure. It contains the 
+ * capabilities/limitations (like maximum bytes transferred,  
+ * supported clock speed) of the hardware.
+ */
+ 
+typedef struct NvRmI2cCapabilitiesRec
+{
+
+    /**
+     * Maximum number of packet length in bytes which can be transferred
+     * between start and the stop pulses.
+     */
+    NvU32 MaximumPacketLengthInBytes;
+
+    /// Maximum speed which I2C controller can support.
+    NvU32 MaximumClockSpeed;
+
+    /// Minimum speed which I2C controller can support.
+    NvU32 MinimumClockSpeed;
+} NvRmI2cCapabilities;
+
+/**
+ * @brief Initializes and opens the i2c channel. This function allocates the
+ * handle for the i2c channel and provides it to the client.
+ *
+ * Assert encountered in debug mode if passed parameter is invalid.
+ *
+ * @param hDevice Handle to the Rm device which is required by Rm to acquire
+ * the resources from RM.
+ * @param IoModule The IO module to set, it is either NvOdmIoModule_I2c
+ * or NvOdmIoModule_I2c_Pmu
+ * @param instance Instance of the i2c driver to be opened.
+ * @param phI2c Points to the location where the I2C handle shall be stored.
+ *
+ * @retval NvSuccess Indicates that the I2c channel has successfully opened.
+ * @retval NvError_InsufficientMemory Indicates that function fails to allocate
+ * the memory.
+ * @retval NvError_NotInitialized Indicates the I2c initialization failed.
+ */
+
+ NvError NvRmI2cOpen( 
+    NvRmDeviceHandle hDevice,
+    NvU32 IoModule,
+    NvU32 instance,
+    NvRmI2cHandle * phI2c );
+
+/** 
+ * @brief Closes the i2c channel. This function frees the memory allocated for
+ * the i2c handle for the i2c channel.
+ * This function de-initializes the i2c channel. This API never fails.
+ *
+ * @param hI2c A handle from NvRmI2cOpen().  If hI2c is NULL, this API does
+ *     nothing.
+ */
+
+ void NvRmI2cClose( 
+    NvRmI2cHandle hI2c );
+
+// Maximum number of bytes that can be sent between the i2c start and stop conditions
+#define NVRM_I2C_PACKETSIZE (8)
+
+// Maximum number of bytes that can be sent between the i2c start and repeat start condition.
+#define NVRM_I2C_PACKETSIZE_WITH_NOSTOP (4)
+
+/// Indicates a I2C read transaction.
+#define NVRM_I2C_READ (0x1)
+
+/// Indicates that it is a write transaction
+#define NVRM_I2C_WRITE (0x2)
+
+/// Indicates that there is no STOP following this transaction. This also implies
+/// that there is always one more transaction following a transaction with
+/// NVRM_I2C_NOSTOP attribute.
+#define NVRM_I2C_NOSTOP (0x4)
+
+//  Some devices doesn't support ACK. By, setting this flag, master will not
+//  expect the generation of ACK from the device.
+#define NVRM_I2C_NOACK (0x8)
+
+// Software I2C using GPIO. Doesn't use the hardware controllers. This path
+// should be used only for testing.
+#define NVRM_I2C_SOFTWARE_CONTROLLER (0x10)
+
+typedef struct NvRmI2cTransactionInfoRec
+{
+
+    /// Flags to indicate the transaction details, like write/read or read
+    /// without a stop or write without a stop.
+        NvU32 Flags;
+
+    /// Number of bytes to be transferred.
+        NvU32 NumBytes;
+
+    /// I2C slave device address
+        NvU32 Address;
+
+    /// Indicates that the address is a 10-bit address.
+        NvBool Is10BitAddress;
+} NvRmI2cTransactionInfo;
+
+/** 
+ * @brief Does multiple I2C transactions. Each transaction can be a read or write.
+ *
+ *  AP15 I2C controller has the following limitations:
+ *  - Any read/write transaction is limited to NVRM_I2C_PACKETSIZE
+ *  - All transactions will be terminated by STOP unless NVRM_I2C_NOSTOP flag
+ *  is specified. Specifying NVRM_I2C_NOSTOP means, *next* transaction will start
+ *  with a repeat start, with NO stop between transactions.
+ *  - When NVRM_I2C_NOSTOP is specified for a transaction - 
+ *      1. Next transaction will start with repeat start.
+ *      2. Next transaction is mandatory.
+ *      3. Next Next transaction cannot have NVRM_I2C_NOSTOP flag set. i.e no
+ *         back to back repeat starts.
+ *      4. Current and next transactions are limited to size
+ *         NVRM_I2C_PACKETSIZE_WITH_NOSTOP.
+ *      5. Finally, current transactions and next Transaction should be of same
+ *         size.
+ *
+ *  This imposes some limitations on how the hardware can be used. However, the
+ *  API itself doesn't have any limitations. If the HW cannot be used, it falls
+ *  back to GPIO based I2C. Gpio I2C bypasses Hw controller and bit bangs the
+ *  SDA/SCL lines of I2C.
+ * 
+ * @param hI2c Handle to the I2C channel.
+ * @param I2cPinMap for I2C controllers which are being multiplexed across
+ *        multiple pin mux configurations, this specifies which pin mux configuration
+ *        should be used for the transaction.  Must be 0 when the ODM pin mux query
+ *        specifies a non-multiplexed configuration for the controller.
+ * @param WaitTimeoutInMilliSeconds Timeout for the transcation. 
+ * @param ClockSpeedKHz Clock speed in KHz.
+ * @param Data Continous stream of data
+ * @param DataLength Length of the data stream
+ * @param Transcations Pointer to the NvRmI2cTransactionInfo structure
+ * @param NumOfTransactions Number of transcations
+ *
+ *
+ * @retval NvSuccess Indicates the operation succeeded.
+ * @retval NvError_NotSupported Indicates assumption on parameter values violated.
+ * @retval NvError_InvalidState Indicates that the last read call is not
+ * completed.
+ * @retval NvError_ControllerBusy Indicates controller is presently busy with an
+ * i2c transaction.
+ * @retval NvError_InvalidDeviceAddress Indicates that the slave device address
+ * is invalid
+ */
+
+ NvError NvRmI2cTransaction( 
+    NvRmI2cHandle hI2c,
+    NvU32 I2cPinMap,
+    NvU32 WaitTimeoutInMilliSeconds,
+    NvU32 ClockSpeedKHz,
+    NvU8 * Data,
+    NvU32 DataLen,
+    NvRmI2cTransactionInfo * Transaction,
+    NvU32 NumOfTransactions );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_init.h b/arch/arm/mach-tegra/nv/include/nvrm_init.h
new file mode 100644
index 000000000000..5aaa410d5b17
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_init.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_init_H
+#define INCLUDED_nvrm_init_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+
+#include "nvcommon.h"
+#include "nverror.h"
+
+/**
+ * NvRmDeviceHandle is an opaque handle to an RM device.
+ */
+
+typedef struct NvRmDeviceRec *NvRmDeviceHandle;
+
+/**
+ * A physical address type sized such that it matches the addressing support of
+ * the hardware modules RM typically interfaces with.  May be smaller than an
+ * NvOsPhysAddr.
+ *
+ * XXX We should probably get rid of this and just use NvU32.  It's rather
+ * difficult to explain what exactly NvRmPhysAddr is.  Also, what if some units
+ * are upgraded to do 64-bit addressing and others remain 32?  Would we really
+ * want to increase NvRmPhysAddr to NvU64 across the board?
+ *
+ * Another option would be to put the following types in nvcommon.h:
+ *   typedef NvU32 NvPhysAddr32;
+ *   typedef NvU64 NvPhysAddr64;
+ * Using these types would then be purely a form of documentation and nothing
+ * else.
+ *
+ * This header file is a somewhat odd place to put this type.  Putting it in
+ * memmgr would be even worse, though, because then a lot of header files would
+ * all suddenly need to #include nvrm_memmgr.h just to get the NvRmPhysAddr
+ * type.  (They already all include this header anyway.)
+ */
+
+typedef NvU32 NvRmPhysAddr;
+
+/**
+ * Opens the Resource Manager for a given device.
+ *
+ * Can be called multiple times for a given device.  Subsequent
+ * calls will not necessarily return the same handle.  Each call to
+ * NvRmOpen() must be paired with a corresponding call to NvRmClose().
+ *
+ * Assert encountered in debug mode if DeviceId value is invalid.
+ *
+ * This call is not intended to perform any significant hardware
+ * initialization of the device; rather its primary purpose is to
+ * initialize RM's internal data structures that are involved in
+ * managing the device.
+ * 
+ * @param pHandle the RM handle is stored here.
+ * @param DeviceId implementation-dependent value specifying the device
+ *     to be opened.  Currently must be set to zero.
+ *
+ * @retval NvSuccess Indicates that RM was successfully opened.
+ * @retval NvError_InsufficientMemory Indicates that RM was unable to allocate
+ *     memory for its internal data structures.
+ */
+
+ NvError NvRmOpen( 
+    NvRmDeviceHandle * pHandle,
+    NvU32 DeviceId );
+
+/**
+ * Called by the platform/OS code to initialize the Rm. Usage and
+ * implementation of this API is platform specific.
+ *  
+ * This APIs should not be called by the normal clients of the Rm.
+ *    
+ * This APIs is guaranteed to succeed on the supported platforms.
+ *
+ * @param pHandle the RM handle is stored here.
+ */
+
+ void NvRmInit( 
+    NvRmDeviceHandle * pHandle );
+
+/**
+ * Temporary version of NvRmOpen lacking the DeviceId parameter
+ */
+
+ NvError NvRmOpenNew( 
+    NvRmDeviceHandle * pHandle );
+
+/**
+ * Closes the Resource Manager for a given device.
+ *
+ * Each call to NvRmOpen() must be paired with a corresponding call 
+ * to NvRmClose().
+ *
+ * @param hDevice The RM handle.  If hDevice is NULL, this API has no effect.
+ */
+
+ void NvRmClose( 
+    NvRmDeviceHandle hDevice );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_interrupt.h b/arch/arm/mach-tegra/nv/include/nvrm_interrupt.h
new file mode 100644
index 000000000000..ad06f78b1c8b
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_interrupt.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_interrupt_H
+#define INCLUDED_nvrm_interrupt_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvos.h"
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *     Resource Manager %Interrupt API</b>
+ *
+ * @b Description: Declares the interrupt API for use by NvDDK modules.
+ */
+
+/**
+ * @defgroup nvrm_interrupt RM Interrupt Management Services
+ *
+ * @ingroup nvddk_rm
+ * @{
+ *
+ * IRQ Numbers
+ * -----------
+ * In most cases, we are using the CPU's legacy interrupt support, rather than
+ * the new MPCore interrupt controller.  This means that we only have one ISR
+ * shared between all of the devices in our chip.  To determine which device is
+ * interrupting us, we have to read some registers.  We assign each interrupt
+ * source an "IRQ number".  IRQ numbers are OS-independent and HW-dependent (a
+ * given device may have a different IRQ number from chip to chip).
+ *
+ * It is arbitrary how far we decode interrupts as part of determining the IRQ
+ * number.  Normally we might assign one IRQ number to each interrupt line that
+ * feeds into the main interrupt controller (typically one per device in the
+ * chip), but we can decode further if we want.  For example, there are several
+ * GPIO controllers, each of which controls 32 GPIO lines.  The GPIO controller
+ * interrupt line is constructed by OR'ing together the interrupt lines for each
+ * of the 32 GPIO pins.  If we want, we can assign each GPIO controller 32
+ * separate IRQ numbers, one per GPIO line; this simply means we have to sub-
+ * decode the interrupts a little further inside the ISR.
+ *
+ * The main advantage of doing this sub-decoding is that only a single driver is
+ * allowed to hook each interrupt source -- if multiple drivers both want to
+ * register interrupt handlers for the same interrupt source, the drivers will
+ * fight with one another trying to handle the same interrupt, so this is an
+ * error.  At the same time, it's entirely plausible that out of a group of 32
+ * GPIO pins, multiple different drivers care about different groups of those
+ * pins.  In the absence of sub-decoding, we would have to implement a "GPIO
+ * driver" whose sole purpose was to allow those other drivers to register for
+ * GPIO notifications, and then use driver-to-driver signaling to indicate when
+ * a pin has transitioned state.  This is an extra level of overhead compared
+ * to if drivers are allowed to directly hook the interrupts for the pins they
+ * care about.
+ *
+ * Because IRQ numbers change from chip to chip, you must ask the RM for the IRQ
+ * number of the device when you want to hook its interrupt.  This can be
+ * accomplished using the NvRmGetIrqForLogicalInterrupt() API.  You pass it an
+ * [NvRmModuleID, Index] pair telling it what device you are interested in, and
+ * which sub-interrupt within that device.  Often Index is just zero (many
+ * devices only have one IRQ number).  For GPIO it might by the pin number
+ * within the GPIO controller.  For UART, you might (entirely hypothetically --
+ * there is no requirement that you do this) have Index=0 for the receive
+ * interrupt and Index=1 for the send interrupt.
+ *
+ * Hooking an Interrupt
+ * --------------------
+ * Once you have the IRQ number(s), you can hook the interrupt(s) by calling
+ * NvRmInterruptRegister().  At driver shutdown, you can unhook the interrupt(s)
+ * by calling NvRmInterruptUnregister().
+ *
+ * NvRmInterruptRegister takes a list of IRQs and a list of callback functions to be
+ * called when the corresponding interrupt has fired.  The callback functions
+ * will be passed an extra "void *context" parameter, typically a pointer to
+ * your private driver structure that keeps track of the state of your device.
+ * For example, the NAND driver might pass the NvDdkNandHandle as the context
+ * param.
+ *
+ * Drivers that care about more than one IRQ should call NvRmInterruptRegister only
+ * once.  Calling NvRmInterruptRegister twice (each time with a single IRQ number)
+ * may consume more system resources than calling NvRmInterruptRegister once with
+ * a list of 2 IRQ numbers and 2 callbacks.
+ *
+ * Rules for Interrupt Handlers
+ * ----------------------------
+ * We assume that all interrupt handlers (i.e. the callbacks passed to
+ * NvRmInterruptRegister) are "fast": that is, any complex processing that cannot
+ * complete in a tightly bounded amount of time, such as polling registers to
+ * wait for the HW to complete some processing, is not done in the ISR proper.
+ * Instead, the ISR would signal a semaphore, clear the interrupt, and pass off
+ * the rest of the work to another thread.
+ *
+ * To be more precise about this, we expect all interrupt handlers to follow
+ * these rules:
+ * - They may only call a subset of NvOs functions.  The exact subset is
+ *   documented in nvos.h.
+ * - No floating-point.  (We don't want to have to save and restore the
+ *   floating point registers on an interrupt.)
+ * - They should use as little stack space as possible.  They certainly should
+ *   not use any recursive algorithms, for example.  (For example, if they need
+ *   to look up a node in a red-black tree, they must use an iterative version
+ *   of the tree search rather than recursion.)  Straw man: 256B maximum?
+ * - Any control flow structure that involves looping (like a "for" or "while"
+ *   statement) must be guaranteed to terminate within a clearly understood
+ *   time limit.  We don't have a strict upper bound, but if it takes
+ *   milliseconds, it's out of the question.
+ * - The callback function _must_ clear the cause of the interrupt.  Upon
+ *   returning from the callback the interrupt will be automatically re-enabled.
+ *   If the cause is not cleared the system will be stuck in an infinite loop
+ *   taking interrupts.
+ */
+
+/**
+ * A Logical Interrupt is a tuple that includes the class of interrupts
+ * (i.e., a module), an instance of that module, and the specific interrupt
+ * within that instance (an index).  This is an abstraction for the
+ * actual interrupt bits implemented on the SOC.
+ */
+
+typedef struct NvRmLogicalIntrRec
+{
+
+    /**
+     * Interrupt index within the current instance of specified Module.
+     * This identifies a specific interrupt.  This is an enumerated index
+     * and not a bit-mask.
+     */
+        NvU8 Index;
+
+    /**
+     * The SOC hardware controller class identifier
+     */
+        NvRmModuleID ModuleID;
+} NvRmLogicalIntr;
+
+/**
+ * Translate a given logical interrupt to its corresponding IRQ number.
+ *
+ * @param hRmDevice The RM device handle
+ * @param ModuleID The module of interest
+ * @param Index Zero-based interrupt index within the module
+ *
+ * @return The IRQ number.
+ */
+
+ NvU32 NvRmGetIrqForLogicalInterrupt( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleID,
+    NvU32 Index );
+
+/**
+ * Retrieve the number of IRQs associated with a particular module instance.
+ *
+ * @param hRmDevice The RM device handle
+ * @param ModuleID The module of interest
+ *
+ * @return The number of IRQs.
+ */
+
+ NvU32 NvRmGetIrqCountForLogicalInterrupt( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleID );
+
+/*
+ * Register the interrupt with the given interrupt handler.
+ *
+ * Assert encountered in debug mode if irq number is not valid.
+ *
+ * @see NvRmInterruptEnable()
+ *
+ * @param hRmDevice The RM device handle.
+ * @param IrqListSize size of the IrqList passed in for registering the irq
+ *    handlers for each irq number.
+ * @param pIrqList Array of IRQ numbers for which interupt handlers to be
+ * registerd.
+ * @param pIrqHandlerList array intrupt routine to be called when interrupt
+ * occures.
+ * @param context pointer to the registrer's context handle
+ * @param handle handle to the registered interrupts. This handle is used by for
+ * unregistering the interrupt.
+ * @param InterruptEnable If true, immediately enable interrupt.  Otherwise
+ *  enable interrupt only after calling NvRmInterruptEnable().
+ *
+ * @retval "NvError_IrqRegistrationFailed" if interupt is already registred.
+ * @retval "NvSuccess" if registration is successfull.
+ */
+NvError
+NvRmInterruptRegister(
+    NvRmDeviceHandle hRmDevice,
+    NvU32 IrqListSize,
+    const NvU32 *pIrqList,
+    const NvOsInterruptHandler *pIrqHandlerList,
+    void *context,
+    NvOsInterruptHandle *handle,
+    NvBool InterruptEnable);
+
+/**
+ * Un-registers the interrupt handler from the associated interrupt handle which
+ * is returned by the NvRmInterruptRegister API.
+ *
+ * @param handle Handle returned when the interrupt is registered.
+ */
+void
+NvRmInterruptUnregister(
+    NvRmDeviceHandle hRmDevice,
+    NvOsInterruptHandle handle);
+
+/**
+ * Enable the interrupt handler from the associated interrupt handle which
+ * is returned by the NvRmInterruptRegister API.
+ *
+ * @param handle Handle returned when the interrupt is registered.
+ * 
+ * @retval "NvError_BadParameter" if handle is not valid
+ * @retval "NvError_InsufficientMemory" if interupt enable failed.
+ * @retval "NvSuccess" if registration is successfull.
+ */
+NvError
+NvRmInterruptEnable(
+    NvRmDeviceHandle hRmDevice,
+    NvOsInterruptHandle handle);
+
+/**
+ *  Called by the interrupt callaback to re-enable the interrupt.
+ */
+
+void
+NvRmInterruptDone( NvOsInterruptHandle handle );
+
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_ioctls.h b/arch/arm/mach-tegra/nv/include/nvrm_ioctls.h
new file mode 100644
index 000000000000..4ec15f63677a
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_ioctls.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NVRM_IOCTLS_H
+#define NVRM_IOCTLS_H
+
+
+/* When we trap into the kernel, the majority of the ioctls
+ * are handled by the Generic handler, which is automatically
+ * generated by the IDL compiler.  
+ *
+ * For some special functions, we override the generated code
+ * and supply custom marshalling/unmarshalling code for performance
+ * reasons.  NvRmMemRead/Write are done this way to avoid having
+ * to allocate a buffer and do an extra copy.
+ *
+ * I'm sure as time passes we'll add more to the list here.
+ */
+
+typedef enum
+{
+    NvRmIoctls_Generic = 5000,
+    NvRmIoctls_NvRmMemRead,
+    NvRmIoctls_NvRmMemWrite,
+    NvRmIoctls_NvRmMemReadStrided,
+    NvRmIoctls_NvRmMemWriteStrided,
+    NvRmIoctls_NvRmMemMapIntoCallerPtr,
+    NvRmIoctls_NvRmGetCarveoutInfo,
+    NvRmIoctls_NvRmGraphics,    // Note: not used in Linux (see nvidlcmd.h)
+    NvRmIoctls_NvRmFbControl,
+    NvRmIoctls_NvRmBootDone,    // Called after primary boot-up complete
+
+    // These following ones are used for attaching to an existing NvRm
+    // context from another process - this is used for reference counting
+    // the kernel context when it is used both from a client process and
+    // the nvrm daemon in Linux. This mechanism is roughly equal to duplicating
+    // the nvrm driver filehandle across processes.
+    NvRmIoctls_NvRmGetClientId,
+    NvRmIoctls_NvRmClientAttach,
+    NvRmIoctls_NvRmClientDetach,
+
+    // This ioctl is for the nvrm_gpu module
+    NvRmIoctls_NvRmGpu,
+
+    NvRmIoctls_ForceWord = 0x7FFFFFFF,
+} NvRmKernelIoctls;
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_keylist.h b/arch/arm/mach-tegra/nv/include/nvrm_keylist.h
new file mode 100644
index 000000000000..350282791e8c
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_keylist.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_keylist_H
+#define INCLUDED_nvrm_keylist_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *     Resource Manager Key-List APIs</b>
+ *
+ * @b Description: This API, defines a simple means to set/get the state 
+ * of ODM-Defined Keys.
+ */
+
+#include "nvos.h"
+#include "nvodm_keylist_reserved.h"
+
+/**
+ * Searches the List of Keys present and returns
+ * the Value of the appropriate Key.
+ * 
+ * @param hRm Handle to the RM Device.
+ * @param KeyID ID of the key whose value is required.
+ * 
+ * @retval returns the value of the corresponding key. If the Key is not 
+ * present in the list, it returns 0.
+ */
+
+
+
+ NvU32 NvRmGetKeyValue( 
+    NvRmDeviceHandle hRm,
+    NvU32 KeyID );
+
+/**
+ * Searches the List of Keys Present and sets the value of the Key to the value 
+ * given. If the Key is not present, it adds the key to the list and sets the 
+ * value.
+ * 
+ * @param hRM Handle to the RM Device.
+ * @param KeyID ID of the key whose value is to be set.
+ * @param Value Value to be set for the corresponding key.
+ * 
+ * @retval NvSuccess Value has been successfully set.
+ * @retval NvError_InsufficientMemory Operation has failed while adding the 
+ * key to the existing list.
+ */
+
+ NvError NvRmSetKeyValuePair( 
+    NvRmDeviceHandle hRm,
+    NvU32 KeyID,
+    NvU32 Value );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_memctrl.h b/arch/arm/mach-tegra/nv/include/nvrm_memctrl.h
new file mode 100644
index 000000000000..b760dd538c12
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_memctrl.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_memctrl_H
+#define INCLUDED_nvrm_memctrl_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvos.h"
+
+/*
+ * @ingroup nvrm_memctrl
+ * @{
+ */
+
+/**
+ * NvRmDeviceHandle is an opaque handle to an RM device.
+ */
+
+/**
+ * Start collecting statistics for specified clients. (2 normal clients and 1 llc client)
+ *
+ * @param rm the RM handle is stored here.
+ * @param client_id_0 the ID of the first client
+ * @param client_id_1 the ID of the second client
+ * @param llc_client_id the ID of the llc client
+ *
+ */
+
+ void McStat_Start( 
+    NvRmDeviceHandle rm,
+    NvU32 client_id_0,
+    NvU32 client_id_1,
+    NvU32 llc_client_id );
+
+/**
+ * Stop the counter for collecting statistics for specified clinets
+ * @param rm the RM handle is stored here
+ * @param client_0_cycles pointer to the number of cycles of client_0
+ * @param client_1_cycles pointer to the number of cycles of client_1
+ * @param llc_client_cycles pointer to the number of cycles of llc client
+ * @param llc_client_clocks pointer to the llc client's clock
+ * @param mc_clocks pointer to the memory controller's clock
+ */
+
+ void McStat_Stop( 
+    NvRmDeviceHandle rm,
+    NvU32 * client_0_cycles,
+    NvU32 * client_1_cycles,
+    NvU32 * llc_client_cycles,
+    NvU32 * llc_client_clocks,
+    NvU32 * mc_clocks );
+
+/**
+ * Print out the collected memory control stat data
+ * @param client_id_0 the first client's ID
+ * @param client_0_cycles the number of cycles of client_0 from start to stop
+ * @param client_id_1 the second client's ID
+ * @param client_1_cycles the number of cycles of client_1 from start to stop
+ * @param llc_client_id the ID of llc client
+ * @param llc_client_clocks the clocks of llc client
+ * @param llc_client_cycles the number of cycles of llc client
+ * @param mc_clocks the memory controller's clock
+ */
+
+ void McStat_Report( 
+    NvU32 client_id_0,
+    NvU32 client_0_cycles,
+    NvU32 client_id_1,
+    NvU32 client_1_cycles,
+    NvU32 llc_client_id,
+    NvU32 llc_client_clocks,
+    NvU32 llc_client_cycles,
+    NvU32 mc_clocks );
+
+/**
+ * Read the data of specified module and bit field 
+ * @param modId the specified module ID
+ * @param start_index the start index of the required data
+ * @param length the length of the data
+ * @param value pointer to the variable that will store the data specified
+ *
+ * @retval NvSuccess Indicate the the data is read successfully
+ */
+
+ NvError ReadObsData( 
+    NvRmDeviceHandle rm,
+    NvRmModuleID modId,
+    NvU32 start_index,
+    NvU32 length,
+    NvU32 * value );
+
+/**
+ * Starts CPU performance monitors for the specified list of events
+ * (if monitors were already running they are restarted).
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pEventListSize Pointer to the event list size. On entry specifies
+ *  list size allocated by the client, on exit - actual number of event monitors
+ *  started. If entry size is 0, maximum number of monitored events is returned.
+ * @param pEventList Pointer to the list of events to be monitored. Ignored
+ *  if input list size is 0. Monitors run status is not affected in this case.
+ * 
+ * @note No event validation is performed. It is caller responsibility to pass
+ *  valid event codes. See ARM control coprocessor CP15 specification for the
+ *  list of event numbers and the respective event definitions.
+ * 
+ * @retval NvSuccess if monitoring start function completed successfully.
+ * @retval NvError_NotSupported if core performance monitoring is not supported.
+ */                               
+
+ NvError NvRmCorePerfMonStart( 
+    NvRmDeviceHandle hRmDevice,
+    NvU32 * pEventListSize,
+    NvU32 * pEventList );
+
+/**
+ * Stops CPU performance monitors and returns event counts.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCountListSize Pointer to the count list size. On entry specifies
+ *  list size allocated by the client, on exit - actual number of event counts
+ *  returned.
+ * @param pCountList Pointer to the list filled in by this function with event
+ *  counts since performance monitoring started. The order of returned counts
+ *  is the same as the order of events specified by NvRmCorePerfMonStart()
+ *  call. If input list size exceeds number of started event monitors the extra
+ *  counts are meaningless. If input list size is 0, this parameter is ignored,
+ *  and no event counts are returned.
+ * @param pTotalCycleCount Pointer to the total number of CPU clock cycles
+ *  since performance monitoring started.
+ * 
+ * @retval NvSuccess if monitoring results are retrieved successfully.
+ * @retval NvError_InvalidState if core performance monitoring has not been
+ *  started or monitor overflow has occurred.
+ * @retval NvError_NotSupported if core performance monitoring is not supported.
+ */                               
+
+ NvError NvRmCorePerfMonStop( 
+    NvRmDeviceHandle hRmDevice,
+    NvU32 * pCountListSize,
+    NvU32 * pCountList,
+    NvU32 * pTotalCycleCount );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_memmgr.h b/arch/arm/mach-tegra/nv/include/nvrm_memmgr.h
new file mode 100644
index 000000000000..cc431c8763f7
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_memmgr.h
@@ -0,0 +1,1013 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_memmgr_H
+#define INCLUDED_nvrm_memmgr_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+#include "nvos.h"
+
+/**
+ * FAQ for commonly asked questions:
+ *
+ * Q) Why can NvRmMemMap fail?
+ * A) Some operating systems don't allow user mode applications to map arbitrary
+ *    memory regions, this is a huge security hole.  In other environments, such
+ *    as simulation, its just not even possible to get a direct pointer to 
+ *    the memory, because the simulation is in a different process.
+ *
+ * Q) What do I do if NvRmMemMap fails?
+ * A) Driver writers have two choices.  If the driver must have a mapping, for
+ *    example direct draw requires a pointer to the memory then the driver
+ *    will have to fail whatever operation it is doing and return an error.
+ *    The other choice is to fall back to using NvRmMemRead/Write functions
+ *    or NvRmMemRdxx/NvRmMemWrxx functions, which are guaranteed to succeed.
+ *
+ * Q) Why should I use NvRmMemMap instead of NvOsPhysicalMemMap?
+ * A) NvRmMemMap will do a lot of extra work in an OS like WinCE to create
+ *    a new mapping to the memory in your process space.  NvOsPhysicalMemMap
+ *    will is for mapping registers and other non-memory locations.  Using
+ *    this API on WindowsCE will cause WindowsCE to crash.
+ */
+
+
+
+/**
+ * UNRESOLVED ISSUES:
+ *
+ * 1. Should we have NvRmFill* APIs in addition to NvRmWrite*?  Say, if you just
+ *    want to clear a buffer to zero?
+ *
+ * 2. There is currently an issue with a memhandle that is shared across
+ *    processes.  If a MemHandle is created, and then duplicated into another
+ *    process uesing NvRmMemHandleGetId/NvRmMemHandleFromId it's not clear
+ *    what would happen if both processes tried to do an NvRmAlloc on a handle.
+ *    Perhaps make NvRmMemHandleGetId fail if the memory is not already
+ *    allocated.
+ *
+ * 3. It may be desirable to have more hMem query functions, for debuggability.
+ *    Part of the information associated with a memory buffer will live in
+ *    kernel space, and not be accesible efficiently from a user process.
+ *    Knowing which heap a buffer is in, or whether a buffer is pinned or
+ *    mapped could be useful.  Note that queries like this could involve race
+ *    conditions.  For example, memory could be moved from one heap to another
+ *    the moment after you ask what heap it's in.
+ */
+
+/**
+ * @defgroup nvrm_memmgr RM Memory Management Services
+ * 
+ * @ingroup nvddk_rm
+ * 
+ * The APIs in this header file are intended to be used for allocating and
+ * managing memory that needs to be accessed by HW devices.  It is not intended
+ * as a replacement for malloc() -- that functionality is provided by
+ * NvOsAlloc().  If only the CPU will ever access the memory, this API is
+ * probably extreme overkill for your needs.
+ *
+ * Memory allocated by NvRmMemAlloc() is intended to be asynchronously movable
+ * by the RM at any time.  Although discouraged, it is possible to permanently
+ * lock down ("pin") a memory buffer such that it can never be moved.  Normally,
+ * however, the intent is that you would only pin a buffer for short periods of
+ * time, on an as-needed basis.
+ *
+ * The first step to allocating memory is allocating a handle to refer to the
+ * allocation.  The handle has a separate lifetime from the underlying buffer.
+ * Some properties of the memory, such as its size in bytes, must be declared at
+ * handle allocation time and can never be changed.
+ *
+ * After successfully allocating a handle, you can specify properties of the
+ * memory buffer that are allowed to change over time.  (Currently no such
+ * properties exist, but in the past a "priority" attribute existed and may
+ * return some day in the future.)
+ *
+ * After specifying the properties of the memory buffer, it can be allocated.
+ * Some additional properties, such as the set of heaps that the memory is
+ * permitted to be allocated from, must be specified at allocation time and
+ * cannot be changed over the buffer's lifetime of the buffer.
+ *
+ * The contents of memory can be examined and modified using a variety of read
+ * and write APIs, such as NvRmMemRead and NvRmMemWrite.  However, in some
+ * cases, it is necessary for the driver or application to be able to directly
+ * read or write the buffer using a pointer.  In this case, the NvRmMemMap API
+ * can be used to obtain such a mapping into the current process's virtual
+ * address space.  It is important to note that the map operation is not
+ * guaranteed to succeed.  Drivers that use mappings are strongly encouraged
+ * to support two code paths: one for when the mapping succeeds, and one for
+ * when the mapping fails.  A memory buffer is allowed to be mapped multiple
+ * times, and the mappings are permitted to be of subregions of the buffer if
+ * desired.
+ *
+ * Before the memory buffer is used, it must be pinned.  While pinned, the
+ * buffer will not be moved, and its physical address can be safely queried.  A
+ * memory buffer can be pinned multiple times, and the pinning will be reference
+ * counted.  Assuming a valid handle and a successful allocation, pinning can
+ * never fail.
+ *
+ * After the memory buffer is done being used, it should be unpinned.  Unpinning
+ * never fails.  Any unpinned memory is free to be moved to any location which
+ * satisfies the current properties in the handle.  Drivers are strongly
+ * encouraged to unpin memory when they reach a quiescent state.  It is not
+ * unreasonable to have a goal that all memory buffers (with the possible
+ * exception of memory being continuously scanned out by the display) be
+ * unpinned when the system is idle.
+ *
+ * The NvRmMemPin API is only one of the two ways to pin a buffer.  In the case
+ * of modules that are programmed through command buffers submitted through
+ * host, it is not the preferred way to pin a buffer.  The "RELOC" facility in
+ * the stream API should be used instead if possible.  It is conceivable that in
+ * the distant future, the NvRmMemPin API might be removed.  In such a world,
+ * all graphics modules would be expected to use the RELOC API or a similar API,
+ * and all IO modules would be expected to use zero-copy DMA directly from the
+ * application buffer using NvOsPageLock.
+ *
+ * Some properties of a buffer can be changed at any point in its handle's
+ * lifetime.  Properties that are changed while a memory buffer is pinned will
+ * have no effect until the memory is unpinned.
+ *
+ * After you are done with a memory buffer, you must free its handle.  This
+ * automatically unpins the memory (if necessary) and frees the storage (if any)
+ * associated with it.
+ *
+ * @ingroup nvrm_memmgr
+ * @{
+ */
+
+
+/**
+ * A type-safe handle for a memory buffer.
+ */
+
+typedef struct NvRmMemRec *NvRmMemHandle;
+
+/**
+ * Define for invalid Physical address
+ */
+#define NV_RM_INVALID_PHYS_ADDRESS (0xffffffff)
+
+/**
+ * NvRm heap identifiers.
+ */
+
+typedef enum
+{
+
+    /**
+     * External (non-carveout, i.e., OS-managed) memory heap.
+     */
+    NvRmHeap_External = 1,
+
+    /**
+     * GART memory heap.  The GART heap is really an alias for the External
+     * heap.  All GART allocations will come out of the External heap, but
+     * additionally all such allocations will be mapped in the GART.  Calling
+     * NvRmMemGetAddress() on a buffer allocated in the GART heap will return
+     * the GART address, not the underlying memory address.
+     */
+    NvRmHeap_GART,
+
+    /**
+     * Carve-out memory heap within external memory.
+     */
+    NvRmHeap_ExternalCarveOut,
+
+    /**
+     * IRAM memory heap.
+     */
+    NvRmHeap_IRam,
+    NvRmHeap_Num,
+    NvRmHeap_Force32 = 0x7FFFFFFF
+} NvRmHeap;
+
+/**
+ * NvRm heap statistics. See NvRmMemGetStat() for further details.
+ */
+
+typedef enum
+{
+
+    /**
+     * Total number of bytes reserved for the carveout heap.
+     */
+    NvRmMemStat_TotalCarveout = 1,
+
+    /**
+     * Number of bytes used in the carveout heap.
+     */
+    NvRmMemStat_UsedCarveout,
+
+    /**
+     * Size of the largest free block in the carveout heap. 
+     * Size can be less than the difference of total and 
+     * used memory.
+     */
+    NvRmMemStat_LargestFreeCarveoutBlock,
+
+    /**
+     * Total number of bytes in the GART heap. 
+     */
+    NvRmMemStat_TotalGart,
+
+    /**
+     * Number of bytes reserved from the GART heap.
+     */
+    NvRmMemStat_UsedGart,
+
+    /**
+     * Size of the largest free block in GART heap. Size can be 
+     * less than the difference of total and used memory.
+     */
+    NvRmMemStat_LargestFreeGartBlock,
+    NvRmMemStat_Num,
+    NvRmMemStat_Force32 = 0x7FFFFFFF
+} NvRmMemStat;
+
+/**
+ * Allocates a memory handle that can be used to specify a memory allocation
+ * request and manipulate the resulting storage.
+ *
+ * @see NvRmMemHandleFree()
+ *
+ * @param hDevice An RM device handle.
+ * @param phMem A pointer to an opaque handle that will be filled in with the
+ *     new memory handle.
+ * @param Size Specifies the requested size of the memory buffer in bytes.
+ *
+ * @retval NvSuccess Indicates the memory handle was successfully allocated.
+ * @retval NvError_InsufficientMemory Insufficient system memory exists to
+ *     allocate the memory handle.
+ */
+
+ NvError NvRmMemHandleCreate( 
+    NvRmDeviceHandle hDevice,
+    NvRmMemHandle * phMem,
+    NvU32 Size );
+
+/**
+ * Looks up a pre-existing memory handle whose allocation was preserved through
+ * the boot process.
+ *
+ * Looking up a memory handle is a one-time event.  Once a preserved handle
+ * has been successfully looked up, it may not be looked up again.  Memory
+ * handles created with this mechanism behave identically to memory handles
+ * created through NvRmMemHandleCreate, including freeing the allocation with
+ * NvRmMemHandleFree.
+ *
+ * @param hDevice An RM device handle.
+ * @param Key The key value that was returned by the earlier call to
+ *    @see NvRmMemHandlePreserveHandle.
+ * @param phMem A pointer to an opaque handle that will be filled in with the
+ *    queried memory handle, if a preserved handle matching the key is found.
+ *
+ * @retval NvSuccess Indicates that the key was found and the memory handle
+ *    was successfully created.
+ * @retval NvError_InsufficientMemory Insufficient system memory was available
+ *    to perform the operation, or if no memory handle exists for the specified
+ *    Key.
+ */
+
+ NvError NvRmMemHandleClaimPreservedHandle( 
+    NvRmDeviceHandle hDevice,
+    NvU32 Key,
+    NvRmMemHandle * phMem );
+
+/**
+ * Adds a memory handle to the set of memory handles which will be preserved
+ * between the current OS context and a subsequent OS context.
+ *
+ * @param hMem The handle which will be marked for preservation
+ * @param Key  A key which can be used to claim the memory handle in a
+ *    different OS context.
+ *
+ * @retval NvSuccess Indicates that the memory handle will be preserved
+ * @retval NvError_InsufficientMemory Insufficient system or BootArg memory
+ *    was avaialable to mark the memory handle as preserved.
+ */
+
+ NvError NvRmMemHandlePreserveHandle( 
+    NvRmMemHandle hMem,
+    NvU32 * Key );
+
+/**
+ * Frees a memory handle obtained from NvRmMemHandleCreate(),
+ * or NvRmMemHandleFromId().
+ *
+ * Fully disposing of a handle requires calling this API one time, plus one
+ * time for each NvRmMemHandleFromId().  When the internal reference count of
+ * the handle reaches zero, all resources for the handle will be released, even
+ * if the memory is marked as pinned and/or mapped.  It is the caller's
+ * responsibility to ensure mappings are released before calling this API.
+ *
+ * When the last handle is closed, the associated storage will be implicitly
+ * unpinned and freed.
+ *
+ * This API cannot fail.
+ *
+ * @see NvRmMemHandleCreate()
+ * @see NvRmMemHandleFromId()
+ *
+ * @param hMem A previously allocated memory handle.  If hMem is NULL, this API
+ *     has no effect.
+ */
+
+ void NvRmMemHandleFree( 
+    NvRmMemHandle hMem );
+
+/**
+ * Allocate storage for a memory handle.  The storage must satisfy:
+ *  1) all specified properties in the hMem handle
+ *  2) the alignment parameters
+ *
+ * Memory allocated by this API is intended to be used by modules which
+ * control hardware devices such as media accelerators or I/O controllers.
+ *
+ * The memory will initially be in an unpinned state.
+ *
+ * Assert encountered in debug mode if alignment was not a power of two, 
+ *     or coherency is not one of NvOsMemAttribute_Uncached,
+ *     NvOsMemAttribute_WriteBack or NvOsMemAttribute_WriteCombined.
+ *
+ * @see NvRmMemPin()
+ *
+ * @param hMem The memory handle to allocate storage for.
+ * @param Heaps[] An array of heap enumerants that indicate which heaps the
+ *     memory buffer is allowed to live in.  When a memory buffer is requested
+ *     to be allocated or needs to be moved, Heaps[0] will be the first choice
+ *     to allocate from or move to, Heaps[1] will be the second choice, and so
+ *     on until the end of the array.
+ * @params NumHeaps The size of the Heaps[] array.  If NumHeaps is zero, then
+ *     Heaps must also be NULL, and the RM will select a default list of heaps
+ *     on the client's behalf.
+ * @param Alignment Specifies the requested alignment of the buffer, measured in
+ *     bytes.  Must be a power of two.
+ * @param Coherency Specifies the cache coherency mode desired if the memory
+ *     is ever mapped.
+ *
+ * @retval NvSuccess Indicates the memory buffer was successfully
+ *     allocated.
+ * @retval NvError_InsufficientMemory Insufficient memory exists that
+ *     satisfies the specified memory handle properties and API parameters.
+ * @retval NvError_AlreadyAllocated hMem already has a memory buffer
+ *     allocated.
+ */
+
+ NvError NvRmMemAlloc( 
+    NvRmMemHandle hMem,
+    const NvRmHeap * Heaps,
+    NvU32 NumHeaps,
+    NvU32 Alignment,
+    NvOsMemAttribute Coherency );
+
+/**
+ * Attempts to lock down a piece of previously allocated memory.  By default
+ * memory is "movable" until it is pinned -- the RM is free to relocate it from
+ * one address or heap to another at any time for any reason (say, to defragment
+ * a heap).  This function can be called to prevent the RM from moving the
+ * memory.
+ *
+ * While a memory buffer is pinned, its physical address can safely be queried
+ * with NvRmMemGetAddress().
+ *
+ * This API always succeeds.
+ *
+ * Pins are reference counted, so the memory will remain pinned until all Pin
+ * calls have had a matching Unpin call.
+ *
+ * Pinning and mapping a memory buffer are completely orthogonal.  It is not
+ * necessary to pin a buffer before mapping it.  Mapping a buffer does not imply
+ * that it is pinned.
+ *
+ * @see NvRmMemGetAddress()
+ * @see NvRmMemUnpin()
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate,
+ *              NvRmMemHandleFromId.
+ *
+ * @returns The physical address of the first byte in the specified memory
+ *     handle's storage.  If the memory is mapped through the GART, the
+ *     GART address will be returned, not the address of the underlying memory.
+ */
+
+ NvU32 NvRmMemPin( 
+    NvRmMemHandle hMem );
+
+ /**
+  * A multiple handle version of NvRmMemPin to reduce kernel trap overhead.
+  * 
+  * @see NvRmMemPin
+  *
+  * @param hMems An array of memory handles to pin
+  * @param Addrs An arary of address (the result of the pin)
+  * @param Count The number of handles and addresses
+  */
+
+ void NvRmMemPinMult( 
+    NvRmMemHandle * hMems,
+    NvU32 * Addrs,
+    NvU32 Count );
+
+/**
+ * Retrieves a physical address for an hMem handle and an offset into that
+ * handle's memory buffer.
+ *
+ * If the memory referred to by hMem is not pinned, the return value is
+ * undefined, and an assert will fire in a debug build.
+ *
+ * @see NvRmMemPin()
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset The offset into the memory buffer for which the
+ *     address is desired.
+ *
+ * @returns The physical address of the specified byte within the specified
+ *     memory handle's storage.  If the memory is mapped through the GART, the
+ *     GART address will be returned, not the address of the underlying memory.
+ */
+
+ NvU32 NvRmMemGetAddress( 
+    NvRmMemHandle hMem,
+    NvU32 Offset );
+
+/**
+ * Unpins a memory buffer so that it is once again free to be moved.  Pins are
+ * reference counted, so the memory will not become movable until all Pin calls
+ * have had a matching Unpin call.
+ *
+ * If the pin count is already zero when this API is called, the behavior is
+ * undefined, and an assert will fire in a debug build.
+ *
+ * This API cannot fail.
+ *
+ * @see NvRmMemPin()
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ *     If hMem is NULL, this API will do nothing.
+ */
+
+ void NvRmMemUnpin( 
+    NvRmMemHandle hMem );
+
+ /**
+  * A multiple handle version of NvRmMemUnpin to reduce kernel trap overhead.
+  * 
+  * @see NvRmMemPin
+  *
+  * @param hMems An array of memory handles to unpin
+  * @param Count The number of handles and addresses
+  */
+
+ void NvRmMemUnpinMult( 
+    NvRmMemHandle * hMems,
+    NvU32 Count );
+
+/**
+ * Attempts to map a memory buffer into the process's virtual address space.
+ *
+ * It is recommended that mappings be short-lived as some systems have a limited
+ * number of concurrent mappings that can be supported, or because virtual
+ * address space may be scarce.
+ *
+ * It is legal to have multiple concurrent mappings of a single memory buffer.
+ *
+ * Pinning and mapping a memory buffer are completely orthogonal.  It is not
+ * necessary to pin a buffer before mapping it.  Mapping a buffer does not imply
+ * that it is pinned.
+ *
+ * There is no guarantee that the mapping will succeed.  For example, on some
+ * operating systems, the OS's security mechanisms make it impossible for
+ * untrusted applications to map certain types of memory.  A mapping might also
+ * fail due to exhaustion of memory or virtual address space.  Therefore, you
+ * must implement code paths that can handle mapping failures.  For example, if
+ * the mapping fails, you may want to fall back to using NvRmMemRead() and
+ * NvRmMemWrite().  Alternatively, you may want to consider avoiding the use of
+ * this API altogether, unless there is a compelling reason why you need
+ * mappings.
+ *
+ * @see NvRmMemUnmap()
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset within the memory buffer to start the map at.
+ * @param Size Size in bytes of mapping requested.  Must be greater than 0.
+ * @param Flags Special flags -- use NVOS_MEM_* (see nvos.h for details)
+ * @param pVirtAddr If the mapping is successful, provides a virtual
+ *     address through which the memory buffer can be accessed.
+ *
+ * @retval NvSuccess Indicates that the memory was successfully mapped.
+ * @retval NvError_InsufficientMemory The mapping was unsuccessful.
+ *     This can occur if it is impossible to map the memory, or if offset+size
+ *     is greater than the size of the buffer referred to by hMem.
+ * @retval NvError_NotSupported Mapping not allowed (e.g., for GART heap)
+ */
+
+NvError
+NvRmMemMap(
+    NvRmMemHandle  hMem,
+    NvU32          Offset,
+    NvU32          Size,
+    NvU32          Flags,
+    void          **pVirtAddr);
+
+/**
+ * Unmaps a memory buffer from the process's virtual address space.  This API
+ * cannot fail.
+ *
+ * If hMem is NULL, this API will do nothing.
+ * If pVirtAddr is NULL, this API will do nothing.
+ *
+ * @see NvRmMemMap()
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param pVirtAddr The virtual address returned by a previous call to
+ *     NvRmMemMap with hMem.
+ * @param Size The size in bytes of the mapped region.  Must be the same as the
+ *     Size value originally passed to NvRmMemMap.
+ */
+
+void NvRmMemUnmap(NvRmMemHandle hMem, void *pVirtAddr, NvU32 Size);
+ 
+/**
+ * Reads 8 bits of data from a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ * 
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ *
+ * @returns The value read from the memory location.
+ */
+
+NvU8 NvRmMemRd08(NvRmMemHandle hMem, NvU32 Offset);
+
+/**
+ * Reads 16 bits of data from a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ * 
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     Must be a multiple of 2.
+ *
+ * @returns The value read from the memory location.
+ */
+
+NvU16 NvRmMemRd16(NvRmMemHandle hMem, NvU32 Offset);
+
+/**
+ * Reads 32 bits of data from a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ * 
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     Must be a multiple of 4.
+ *
+ * @returns The value read from the memory location.
+ */
+
+NvU32 NvRmMemRd32(NvRmMemHandle hMem, NvU32 Offset);
+
+/**
+ * Writes 8 bits of data to a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ * 
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param Data The data to write to the memory location.
+ */
+
+void NvRmMemWr08(NvRmMemHandle hMem, NvU32 Offset, NvU8 Data);
+
+/**
+ * Writes 16 bits of data to a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     Must be a multiple of 2.
+ * @param Data The data to write to the memory location.
+ */
+
+void NvRmMemWr16(NvRmMemHandle hMem, NvU32 Offset, NvU16 Data);
+
+/**
+ * Writes 32 bits of data to a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     Must be a multiple of 4.
+ * @param Data The data to write to the memory location.
+ */
+
+void NvRmMemWr32(NvRmMemHandle hMem, NvU32 Offset, NvU32 Data);
+
+/**
+ * Reads a block of data from a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param pDst The buffer where the data should be placed.
+ *     May be arbitrarily aligned -- need not be located at a word boundary.
+ * @param Size The number of bytes of data to be read.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ */
+void NvRmMemRead(NvRmMemHandle hMem, NvU32 Offset, void *pDst, NvU32 Size);
+
+/**
+ * Writes a block of data to a buffer.  This API cannot fail.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param pSrc The buffer to obtain the data from.
+ *     May be arbitrarily aligned -- need not be located at a word boundary.
+ * @param Size The number of bytes of data to be written.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ */
+void NvRmMemWrite(
+    NvRmMemHandle hMem,
+    NvU32 Offset,
+    const void *pSrc,
+    NvU32 Size);
+
+/**
+ * Reads a strided series of blocks of data from a buffer.  This API cannot
+ * fail.
+ *
+ * The total number of bytes copied is Count*ElementSize.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param SrcStride The number of bytes separating each source element.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param pDst The buffer where the data should be placed.
+ *     May be arbitrarily aligned -- need not be located at a word boundary.
+ * @param DstStride The number of bytes separating each destination element.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param ElementSize The number of bytes in each element.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ * @param Count The number of destination elements.
+ */
+void NvRmMemReadStrided(
+    NvRmMemHandle hMem,
+    NvU32 Offset,
+    NvU32 SrcStride,
+    void *pDst,
+    NvU32 DstStride,
+    NvU32 ElementSize,
+    NvU32 Count);
+
+/**
+ * Writes a strided series of blocks of data to a buffer.  This API cannot
+ * fail.
+ *
+ * The total number of bytes copied is Count*ElementSize.
+ *
+ * If hMem refers to an unallocated memory buffer, this function's behavior is
+ * undefined and an assert will trigger in a debug build. 
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate.
+ * @param Offset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param DstStride The number of bytes separating each destination element.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param pSrc The buffer to obtain the data from.
+ *     May be arbitrarily aligned -- need not be located at a word boundary.
+ * @param SrcStride The number of bytes separating each source element.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param ElementSize The number of bytes in each element.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ * @param Count The number of source elements.
+ */
+void NvRmMemWriteStrided(
+    NvRmMemHandle hMem,
+    NvU32 Offset,
+    NvU32 DstStride,
+    const void *pSrc,
+    NvU32 SrcStride,
+    NvU32 ElementSize,
+    NvU32 Count);
+
+/**
+ * Moves (copies) a block of data to a different (or the same) hMem.  This
+ * API cannot fail.  Overlapping copies are supported.
+ * 
+ * NOTE: While easy to use, this is NOT the fastest way to copy memory.  Using
+ * the 2D engine to perform a blit can be much faster than this function.
+ *
+ * If hDstMem or hSrcMem refers to an unallocated memory buffer, this function's
+ * behavior is undefined and an assert will trigger in a debug build. 
+ *
+ * @param hDstMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param DstOffset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param hSrcMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param SrcOffset Byte offset relative to the base of hMem.
+ *     May be arbitrarily aligned -- need not be a multiple of 2 or 4.
+ * @param Size The number of bytes of data to be copied from hSrcMem to hDstMem.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ */
+
+ void NvRmMemMove( 
+    NvRmMemHandle hDstMem,
+    NvU32 DstOffset,
+    NvRmMemHandle hSrcMem,
+    NvU32 SrcOffset,
+    NvU32 Size );
+
+/**
+ * Optionally writes back and/or invalidates a range of the memory from the
+ * data cache, if applicable.  Does nothing for memory that was not allocated
+ * as cached. Memory must be mapped into the calling process.
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param pMapping Starting address (must be within the mapped region of the
+       hMem) to clean
+ * @param Size The number of bytes of data to be written.
+ *     May be arbitrarily sized -- need not be a multiple of 2 or 4.
+ */
+
+void NvRmMemCacheMaint(
+    NvRmMemHandle hMem,
+    void         *pMapping,
+    NvU32         Size,
+    NvBool        WriteBack,
+    NvBool        Invalidate);
+
+/**
+ * Get the size of the buffer associated with a memory handle.
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ *
+ * @returns Size in bytes of memory allocated for this handle.
+ */
+
+ NvU32 NvRmMemGetSize( 
+    NvRmMemHandle hMem );
+
+/**
+ * Get the alignment of the buffer associated with a memory handle.
+ *
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ *
+ * @returns Alignment in bytes of memory allocated for this handle.
+ */
+
+ NvU32 NvRmMemGetAlignment( 
+    NvRmMemHandle hMem );
+
+/**
+ * Queries the maximum cache line size (in bytes) for all of the caches
+ * L1 and L2 in the system
+ *
+ * @returns The largest cache line size of the system
+ */
+
+ NvU32 NvRmMemGetCacheLineSize( 
+    void  );
+
+/**
+ * Queries for the heap type associated with a given memory handle.  Also
+ * returns base physical address for the buffer, if the type is carveout or
+ * GART.  For External type, this parameter does not make sense.
+ * 
+ * @param hMem A memory handle returned from NvRmMemHandleCreate/FromId.
+ * @param BasePhysAddr Output parameter receives the physical address of the
+ *           buffer.
+ *
+ * @returns The heap type allocated for this memory handle.
+ */
+
+ NvRmHeap NvRmMemGetHeapType( 
+    NvRmMemHandle hMem,
+    NvU32 * BasePhysAddr );
+
+/**
+ * Dynamically allocates memory, on CPU this will result in a call to 
+ * NvOsAlloc and on AVP, memAPI's are used to allocate memory.
+ * @param size The memory size to be allocated.
+ * @returns Pointer to the allocated buffer.
+ */
+void* NvRmHostAlloc(size_t Size);
+
+/**
+ * Frees a dynamic memory allocation, previously allocated using NvRmHostAlloc.
+ * 
+ * @param ptr The pointer to buffer which need to be deallocated.
+ */
+void NvRmHostFree(void* ptr);
+
+/** 
+ * This is generally not a publically available function.  It is only available
+ * on WinCE to the nvrm device driver.  Attempting to use this function will
+ * result in a linker error, you should use NvRmMemMap instead, which will do
+ * the "right" thing for all platforms.
+ *
+ * Under WinCE NvRmMemMap has a custom marshaller, the custom marshaller will 
+ * do the following:
+ *  - Allocate virtual space
+ *  - ioctl to the nvrm driver
+ *    - nvrm driver will create a mapping from the allocated buffer to
+ *      the newly allocated virtual space.
+ */
+NvError NvRmMemMapIntoCallerPtr(
+    NvRmMemHandle hMem,
+    void  *pCallerPtr,
+    NvU32 Offset,
+    NvU32 Size);
+
+/**
+ * Create a unique identifier which can be used from any process/processor
+ * to generate a new memory handle.  This can be used to share a memory handle
+ * between processes, or from AVP and CPU.  
+ *
+ *  Typical usage would be
+ *    GetId
+ *    Pass Id to client process/procssor
+ *    Client calls:  NvRmMemHandleFromId
+ *
+ *  See Also NvRmMemHandleFromId
+ *
+ * NOTE: Getting an id _does not_ increment the reference count of the
+ *       memory handle.  You must be sure that whichever process/processor
+ *       that is passed an Id calls @NvRmMemHandleFromId@ before you free
+ *       a handle.
+ *
+ * @param hMem The memory handle to retrieve the id for.
+ * @returns a unique id that identifies the memory handle.
+ */
+
+ NvU32 NvRmMemGetId( 
+    NvRmMemHandle hMem );
+
+/**
+ * Create a new memory handle, which refers to the memory handle identified
+ * by @id@.  This function will increment the reference count on the handle.
+ *
+ *  See Also NvRmMemGetId
+ *
+ * @param id value that refers to a memory handle, returned from NvRmMemGetId
+ * @param hMem The newly created memory handle
+ * @returns NvSuccess if a unique id is created.
+ */
+
+ NvError NvRmMemHandleFromId( 
+    NvU32 id,
+    NvRmMemHandle * hMem );
+
+/**
+ * Get a memory statistics value. 
+ *
+ * Querying values may have an effect on  system performance and may include 
+ * processing, like heap traversal.
+ *
+ * @param Stat NvRmMemStat value that chooses the value to return.
+ * @param Result Result, if the call was successful. Otherwise value 
+ *      is not touched.
+ * @returns NvSuccess on success, NvError_BadParameter if Stat is 
+ *      not a valid value, NvError_NotSupported if the Stat is 
+ *      not available for some reason, or
+ *      NvError_InsufficientMemory.
+ */
+
+ NvError NvRmMemGetStat( 
+    NvRmMemStat Stat,
+    NvS32 * Result );
+
+#define NVRM_MEM_CHECK_ID  0
+#define NVRM_MEM_TRACE     0
+#if     NVRM_MEM_TRACE
+#ifndef NV_IDL_IS_STUB
+#ifndef NV_IDL_IS_DISPATCH
+#define NvRmMemHandleCreate(d,m,s) \
+        NvRmMemHandleCreateTrace(d,m,s,__FILE__,__LINE__)
+#define NvRmMemHandleFree(m) \
+        NvRmMemHandleFreeTrace(m,__FILE__,__LINE__)
+#define NvRmMemGetId(m) \
+        NvRmMemGetIdTrace(m,__FILE__,__LINE__)
+#define NvRmMemHandleFromId(i,m) \
+        NvRmMemHandleFromIdTrace(i,m,__FILE__,__LINE__)
+
+static NV_INLINE NvError NvRmMemHandleCreateTrace( 
+    NvRmDeviceHandle hDevice,
+    NvRmMemHandle * phMem,
+    NvU32 Size,
+    const char *file,
+    NvU32 line)
+{
+    NvError err;
+    err = (NvRmMemHandleCreate)(hDevice, phMem, Size);
+    NvOsDebugPrintf("RMMEMTRACE: Create %08x at %s:%d %s\n",
+        (int)*phMem,
+        file,
+        line,
+        err?"FAILED":"");
+    return err;
+}
+
+static NV_INLINE void NvRmMemHandleFreeTrace( 
+    NvRmMemHandle hMem,
+    const char *file,
+    NvU32 line)
+{
+    NvOsDebugPrintf("RMMEMTRACE: Free   %08x at %s:%d\n",
+        (int)hMem,
+        file,
+        line);
+    (NvRmMemHandleFree)(hMem);
+}
+
+static NV_INLINE NvU32 NvRmMemGetIdTrace( 
+    NvRmMemHandle hMem,
+    const char *file,
+    NvU32 line)
+{
+    NvOsDebugPrintf("RMMEMTRACE: GetId  %08x at %s:%d\n",
+        (int)hMem,
+        file,
+        line);
+    return (NvRmMemGetId)(hMem);
+}
+
+static NV_INLINE NvError NvRmMemHandleFromIdTrace( 
+    NvU32 id,
+    NvRmMemHandle * hMem,
+    const char *file,
+    NvU32 line)
+{
+    NvOsDebugPrintf("RMMEMTRACE: FromId %08x at %s:%d\n",
+        id,
+        file,
+        line);
+    return (NvRmMemHandleFromId)(id,hMem);
+}
+
+#endif // NV_IDL_IS_DISPATCH
+#endif // NV_IDL_IS_STUB
+#endif // NVRM_MEM_TRACE
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_minikernel.h b/arch/arm/mach-tegra/nv/include/nvrm_minikernel.h
new file mode 100644
index 000000000000..79b198b3f7d3
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_minikernel.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_MINIKERNEL_H
+#define INCLUDED_NVRM_MINIKERNEL_H
+
+#include "nvrm_init.h"
+
+/**
+ * Called by the secure OS code to initialize the Rm. Usage and
+ * implementation of this API is platform specific.
+ *
+ * This APIs should not be called by the non secure clients of the Rm.
+ *
+ * This APIs is guaranteed to succeed on the supported platforms.
+ *
+ * @param pHandle the RM handle is stored here.
+ */
+void NvRmBasicInit( NvRmDeviceHandle *pHandle );
+
+/**
+ * Closes the Resource Manager for secure os.
+ *
+ * @param hDevice The RM handle.  If hDevice is NULL, this API has no effect.
+ */
+void NvRmBasicClose( NvRmDeviceHandle hDevice );
+
+#endif // INCLUDED_NVRM_MINIKERNEL_H
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_module.h b/arch/arm/mach-tegra/nv/include/nvrm_module.h
new file mode 100644
index 000000000000..7fed6a90268e
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_module.h
@@ -0,0 +1,745 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_module_H
+#define INCLUDED_nvrm_module_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+#include "nvrm_drf.h"
+
+/**
+ * SOC hardware controller class identifiers.
+ */
+
+typedef enum
+{
+
+    /// Specifies an invalid module ID.
+        NvRmModuleID_Invalid = 0,
+
+    /// Specifies the application processor.
+        NvRmModuleID_Cpu,
+
+    /// Specifies the Audio Video Processor
+        NvRmModuleID_Avp,
+
+    /// Specifies the Vector Co Processor
+        NvRmModuleID_Vcp,
+
+    /// Specifies the display controller.
+        NvRmModuleID_Display,
+
+    /// Specifies the IDE controller.
+        NvRmModuleID_Ide,
+
+    /// Graphics Host
+        NvRmModuleID_GraphicsHost,
+
+    /// Specifies 2D graphics controller
+        NvRmModuleID_2D,
+
+    /// Specifies 3D graphics controller
+        NvRmModuleID_3D,
+
+    /// Specifies VG graphics controller
+        NvRmModuleID_VG,
+
+    /// NV epp (encoder pre-processor)
+        NvRmModuleID_Epp,
+
+    /// NV isp (image signal processor)
+        NvRmModuleID_Isp,
+
+    /// NV vi (video input)
+        NvRmModuleID_Vi,
+
+    /// Specifies USB2 OTG controller
+        NvRmModuleID_Usb2Otg,
+
+    /// Specifies the I2S controller.
+        NvRmModuleID_I2s,
+
+    /// Specifies the Pulse Width Modulator controller.
+        NvRmModuleID_Pwm,
+
+    /// Specifies the Three Wire controller.
+        NvRmModuleID_Twc,
+
+    /// HSMMC controller
+        NvRmModuleID_Hsmmc,
+
+    /// Specifies SDIO controller
+        NvRmModuleID_Sdio,
+
+    /// Specifies the NAND controller.
+        NvRmModuleID_Nand,
+
+    /// Specifies the I2C controller.
+        NvRmModuleID_I2c,
+
+    /// Specifies the Sony Phillips Digital Interface Format controller.
+        NvRmModuleID_Spdif,
+
+    /// Specifies the %UART controller.
+        NvRmModuleID_Uart,
+
+    /// Specifies the timer controller.
+        NvRmModuleID_Timer,
+
+    /// Specifies the timer controller microsecond counter.
+        NvRmModuleID_TimerUs,
+
+    /// Real time clock controller.
+        NvRmModuleID_Rtc,
+
+    /// Specifies the Audio Codec 97 controller.
+        NvRmModuleID_Ac97,
+
+    /// Specifies Audio Bit Stream Engine
+        NvRmModuleID_BseA,
+
+    /// Specifies Video decoder
+        NvRmModuleID_Vde,
+
+    /// Specifies Video encoder (Motion Picture Encoder)
+        NvRmModuleID_Mpe,
+
+    /// Specifies Camera Serial Interface
+        NvRmModuleID_Csi,
+
+    /// Specifies High-Bandwidth Digital Content Protection interface
+        NvRmModuleID_Hdcp,
+
+    /// Specifies High definition Multimedia Interface
+        NvRmModuleID_Hdmi,
+
+    /// Specifies MIPI baseband controller
+        NvRmModuleID_Mipi,
+
+    /// Specifies TV out controller
+        NvRmModuleID_Tvo,
+
+    /// Specifies Serial Display
+        NvRmModuleID_Dsi,
+
+    /// Specifies Dynamic Voltage Controller
+        NvRmModuleID_Dvc,
+
+    /// Specifies the eXtended I/O controller.
+        NvRmModuleID_Xio,
+
+    /// SPI controller
+        NvRmModuleID_Spi,
+
+    /// Specifies SLink controller
+        NvRmModuleID_Slink,
+
+    /// Specifies FUSE controller
+        NvRmModuleID_Fuse,
+
+    /// Specifies KFUSE controller
+        NvRmModuleID_KFuse,
+
+    /// Specifies EthernetMIO controller
+        NvRmModuleID_Mio,
+
+    /// Specifies keyboard controller
+        NvRmModuleID_Kbc,
+
+    /// Specifies Pmif controller
+        NvRmModuleID_Pmif,
+
+    /// Specifies Unified Command Queue
+        NvRmModuleID_Ucq,
+
+    /// Specifies Event controller
+        NvRmModuleID_EventCtrl,
+
+    /// Specifies Flow controller
+        NvRmModuleID_FlowCtrl,
+
+    /// Resource Semaphore
+        NvRmModuleID_ResourceSema,
+
+    /// Arbitration Semaphore
+        NvRmModuleID_ArbitrationSema,
+
+    /// Specifies Arbitration Priority
+        NvRmModuleID_ArbPriority,
+
+    /// Specifies Cache Memory Controller
+        NvRmModuleID_CacheMemCtrl,
+
+    /// Specifies very fast infra red controller
+        NvRmModuleID_Vfir,
+
+    /// Specifies Exception Vector
+        NvRmModuleID_ExceptionVector,
+
+    /// Specifies Boot Strap Controller
+        NvRmModuleID_BootStrap,
+
+    /// Specifies System Statistics Monitor controller
+        NvRmModuleID_SysStatMonitor,
+
+    /// Specifies System 
+        NvRmModuleID_Cdev,
+ 
+    /// Misc module ID which contains registers for PInmux/DAP control etc.
+        NvRmModuleID_Misc,
+
+    // PCIE Device attached to AP20
+        NvRmModuleID_PcieDevice,
+
+    // One-wire interface controller
+        NvRmModuleID_OneWire,
+
+    // Sync NOR controller
+        NvRmModuleID_SyncNor,
+
+    // NOR Memory aperture
+        NvRmModuleID_Nor,
+
+    // AVP UCQ module.
+        NvRmModuleID_AvpUcq,
+
+    /// clock and reset controller
+        NvRmPrivModuleID_ClockAndReset,
+
+    /// interrupt controller
+        NvRmPrivModuleID_Interrupt,
+
+    /// interrupt controller Arbitration Semaphore grant registers
+        NvRmPrivModuleID_InterruptArbGnt,
+
+    /// interrupt controller DMA Tx/Rx DRQ registers
+        NvRmPrivModuleID_InterruptDrq,
+
+    /// interrupt controller special SW interrupt
+        NvRmPrivModuleID_InterruptSw,
+
+    /// interrupt controller special CPU interrupt
+        NvRmPrivModuleID_InterruptCpu,
+
+    /// Apb Dma controller
+        NvRmPrivModuleID_ApbDma,
+
+    /// Apb Dma Channel
+        NvRmPrivModuleID_ApbDmaChannel,
+
+    /// Gpio controller
+        NvRmPrivModuleID_Gpio,
+
+    /// Pin-Mux Controller
+        NvRmPrivModuleID_PinMux,
+
+    /// memory configuation
+        NvRmPrivModuleID_Mselect,
+
+    /// memory controller (internal memory and memory arbitration)
+        NvRmPrivModuleID_MemoryController,
+
+    /// external memory (ddr ram, etc.)
+        NvRmPrivModuleID_ExternalMemoryController,
+
+    /// Processor Id
+        NvRmPrivModuleID_ProcId,
+
+    /// Entire System (used for system reset)
+        NvRmPrivModuleID_System,
+
+    /* CC device id (not sure what it actually does, but it is needed to
+     * set the mem_init_done bit so that memory works).
+     */
+        NvRmPrivModuleID_CC,
+
+    /// AHB Arbitration Control
+        NvRmPrivModuleID_Ahb_Arb_Ctrl,
+
+    /// AHB Gizmo Control
+        NvRmPrivModuleID_Ahb_Gizmo_Ctrl,
+
+    /// External memory
+        NvRmPrivModuleID_ExternalMemory,
+
+    /// Internal memory
+        NvRmPrivModuleID_InternalMemory,
+
+    /// TCRAM 
+        NvRmPrivModuleID_Tcram,
+
+    /// IRAM
+        NvRmPrivModuleID_Iram,
+
+    /// GART 
+        NvRmPrivModuleID_Gart,
+
+    /// MIO/EXIO
+        NvRmPrivModuleID_Mio_Exio,
+
+    /* External PMU */
+        NvRmPrivModuleID_PmuExt,
+
+    /* One module ID for all peripherals which includes cache controller, 
+     * SCU and interrupt controller */
+        NvRmPrivModuleID_ArmPerif,
+    NvRmPrivModuleID_ArmInterruptctrl,
+
+    /* PCIE Root Port internally is made up of 3 major blocks. These 3 blocks
+     * have seperate reset and clock domains. So, the driver treats these 
+     *  
+     *  AFI is the wrapper on the top of the PCI core.
+     *  PCIe refers to the core PCIe state machine module.
+     *  PcieXclk refers to the transmit/receive logic which runs at different
+     *  clock and have different reset.
+     * */
+        NvRmPrivModuleID_Afi,
+    NvRmPrivModuleID_Pcie,
+    NvRmPrivModuleID_PcieXclk,
+
+    /* PL310 */
+        NvRmPrivModuleID_Pl310,
+
+    /* 
+     * AHB re-map aperture seen from AVP. Use this aperture for AVP to have
+     * uncached access to SDRAM.
+     */
+        NvRmPrivModuleID_AhbRemap,
+    NvRmModuleID_Num,
+    NvRmModuleID_Force32 = 0x7FFFFFFF
+} NvRmModuleID;
+
+/* FIXME 
+ * Hack to make the existing drivers work. 
+ * NvRmPriv* should be renamed to NvRm*
+ */
+#define NvRmPrivModuleID_Num  NvRmModuleID_Num
+
+/**
+ * Multiple module instances are handled by packing the instance number into
+ * the high bits of the module id.  This avoids ponderous apis with both
+ * module ids and instance numbers.
+ */
+
+/**
+ * Module bitfields that are compatible with the NV_DRF macros.
+ */
+#define NVRM_MODULE_0                   (0x0)
+#define NVRM_MODULE_0_ID_RANGE          15:0
+#define NVRM_MODULE_0_INSTANCE_RANGE    19:16
+#define NVRM_MODULE_0_BAR_RANGE         23:20
+
+/**
+ * Create a module id with a given instance.
+ */
+#define NVRM_MODULE_ID( id, instance ) \
+    (NvRmModuleID)( \
+          NV_DRF_NUM( NVRM, MODULE, ID, (id) ) \
+        | NV_DRF_NUM( NVRM, MODULE, INSTANCE, (instance) ) )
+
+/**
+ * Get the actual module id.
+ */
+#define NVRM_MODULE_ID_MODULE( id ) \
+    NV_DRF_VAL( NVRM, MODULE, ID, (id) )
+
+/**
+ * Get the instance number of the module id.
+ */
+#define NVRM_MODULE_ID_INSTANCE( id ) \
+    NV_DRF_VAL( NVRM, MODULE, INSTANCE, (id) )
+
+/**
+ * Get the bar number for the module.
+ */
+#define NVRM_MODULE_ID_BAR( id ) \
+    NV_DRF_VAL( NVRM, MODULE, BAR, (id) )
+
+/**
+ * Module Information structure
+ */
+
+typedef struct NvRmModuleInfoRec
+{
+    NvU32 Instance;
+    NvU32 Bar;
+    NvRmPhysAddr BaseAddress;
+    NvU32 Length;
+} NvRmModuleInfo;
+
+/**
+ * Returns list of available module instances and their information.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Module The module for which to get the number of instances.
+ * @param pNum Unsigned integer indicating the number of module information
+ *      structures in the array pModuleInfo.
+ * @param pModuleInfo A pointer to an array of module information structure,
+ *      where the size of array is determined by the value in pNum.
+ *
+ * @retval NvSuccess If successful, or the appropriate error.
+ */
+
+ NvError NvRmModuleGetModuleInfo( 
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID module,
+    NvU32 * pNum,
+    NvRmModuleInfo * pModuleInfo );
+
+/**
+ * Returns a physical address associated with a hardware module.
+ * (To be depcreated and replaced by NvRmModuleGetModuleInfo)
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Module the module for which to get addresses.
+ * @param pBaseAddress a pointer to the beginning of the
+ * hardware register bank is stored here.
+ * @param pSize the length of the aperture in bytes is stored
+ * here.
+ */
+
+ void NvRmModuleGetBaseAddress( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID Module,
+    NvRmPhysAddr * pBaseAddress,
+    NvU32 * pSize );
+
+/**
+ * Returns the number of instances of a particular hardware module.
+ * (To be depcreated and replaced by NvRmModuleGetModuleInfo)
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Module The module for which to get the number of instances.
+ *
+ * @returns Number of instances.
+ */
+
+ NvU32 NvRmModuleGetNumInstances( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID Module );
+
+/**
+ * Resets the module controller hardware.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Module The module to reset
+ */
+
+ void NvRmModuleReset( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID Module );
+
+/** 
+ *  Resets the controller with an option to hold the controller in the reset.
+ *  
+ *  @param hRmDeviceHandle Rm device handle
+ *  @param Module The module to be reset
+ *  @param bHold If NV_TRUE hold the module in reset, If NV_TRUE pulse the
+ *  reset.
+ *
+ *  So, to keep the module in reset and do something 
+ *  NvRmModuleResetWithHold(hRm, ModId, NV_TRUE)
+ *  ... update some registers
+ *  NvRmModuleResetWithHold(hRm, ModId, NV_FALSE)
+ */
+
+ void NvRmModuleResetWithHold( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID Module,
+    NvBool bHold );
+
+/**
+ * DDK capability encapsualtion. See NvRmModuleGetCapabilities().
+ */
+
+typedef struct NvRmModuleCapabilityRec
+{
+    NvU8 MajorVersion;
+    NvU8 MinorVersion;
+    NvU8 EcoLevel;
+    void* Capability;
+} NvRmModuleCapability;
+
+/**
+ * Returns a pointer to a class-specific capabilities structure.
+ *
+ * Each DDK will supply a list of NvRmCapability structures sorted by module
+ * Minor and Eco levels (assuming that no DDK supports two Major versions
+ * simulatenously).  The last cap in the list that matches the hardware's
+ * version and eco level will be returned.  If the current hardware's eco
+ * level is higher than the given module capability list, the last module
+ * capability with the highest eco level (the last in the list) will be
+ * returned.
+ * 
+ * @param hRmDeviceHandle The RM device handle
+ * @param Module the target module
+ * @param pCaps Pointer to the capability list
+ * @param NumCaps The number of capabilities in the list
+ * @param Capability Out parameter: the cap that maches the current hardware
+ *
+ * Example usage:
+ *
+ * typedef struct FakeDdkCapRec
+ * {
+ *     NvU32 FeatureBits;
+ * } FakeDdkCap;
+ *
+ * FakeDdkCap cap1;
+ * FakeDdkCap cap2;
+ * FakeDdkCap *cap;
+ * NvRmModuleCapability caps[] =
+ *       { { 1, 0, 0, &fcap1 },
+ *         { 1, 1, 0, &fcap2 },
+ *       };
+ * cap1.bits = ...;
+ * cap2.bits = ...;
+ * err = NvRmModuleGetCapabilities( hDevice, NvRmModuleID_FakeDDK, caps, 2,
+ *     (void *)&cap );
+ * ...
+ * if( cap->FeatureBits & FAKEDKK_SOME_FEATURE )
+ * {
+ *     ...
+ * }
+ */
+
+ NvError NvRmModuleGetCapabilities( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvRmModuleID Module,
+    NvRmModuleCapability * pCaps,
+    NvU32 NumCaps,
+    void* * Capability );
+
+/**
+ * @brief Queries for the device unique ID.
+ *
+ * @pre Not callable from early boot.
+ *
+ * @param pId A pointer to an area of caller-allocated memory to hold the
+ * unique ID.
+ * @param pIdSize an input, a pointer to a variable containing the size of
+ * the caller-allocated memory to hold the unique ID pointed to by \em pId.
+ * Upon successful return, this value is updated to reflect the actual
+ * size of the unique ID returned in \em pId.
+ *
+ * @retval ::NvError_Success \em pId points to the unique ID and \em pIdSize
+ * points to the actual size of the ID.
+ * @retval ::NvError_BadParameter
+ * @retval ::NvError_NotSupported
+ * @retval ::NvError_InsufficientMemory
+ */
+ 
+ NvError NvRmQueryChipUniqueId( 
+    NvRmDeviceHandle hDevHandle,
+    NvU32 IdSize,
+    void* pId );
+
+/**
+ * @brief Returns random bytes using hardware sources of entropy
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param NumBytes Number of random bytes to return in pBytes.
+ * @param pBytes Array where the random bytes should be stored
+ *
+ * @retval ::NvError_Success
+ * @retval ::NvError_BadParameter
+ * @retval ::NvError_NotSupported If no hardware entropy source is available
+ */
+ 
+ NvError NvRmGetRandomBytes( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 NumBytes,
+    void* pBytes );
+
+/*
+ * Module access functions below. 
+ * NOTE: Rm doesn't gaurantee access to all the modules as it only maps a few
+ * modules.
+ * This is not meant to be a primary mechanism to access the module registers.
+ * Clients should map their register address and access the registers.
+ */
+
+/**
+ * NV_REGR: register read from hardware.
+ *
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param offset The offset inside the aperture
+ *
+ * Note that the aperture comes from the RM's private module id enumeration,
+ * which is a superset of the public enumeration from nvrm_module.h.
+ */
+
+/**
+ * NV_REGW: register write to hardware.
+ * 
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param offset The offset inside the aperture
+ * @param data The data to write
+ *
+ * see the note regarding apertures for NV_REGR.
+ */
+#define NV_REGR(rm, aperture, instance, offset) \
+    NvRegr((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(offset))
+
+#define NV_REGW(rm, aperture, instance, offset, data) \
+    NvRegw((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(offset),(data))
+
+
+ NvU32 NvRegr( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 offset );
+
+ void NvRegw( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 offset,
+    NvU32 data );
+
+/**
+ * NV_REGR_MULT: read multiple registers from hardware
+ *
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param num The number of registers
+ * @param offsets The register offsets
+ * @param values The register values
+ */
+
+/**
+ * NV_REGW_MULT: write multiple registers from hardware
+ *
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param num The number of registers
+ * @param offsets The register offsets
+ * @param values The register values
+ */
+
+/**
+ * NV_REGW_BLOCK: write a block of registers to hardware
+ *
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param num The number of registers
+ * @param offset The beginning register offset
+ * @param values The register values
+ */
+
+/**
+ * NV_REGR_BLOCK: read a block of registers from hardware
+ *
+ * @param rm The resource manager istance
+ * @param aperture The register aperture
+ * @param instance The module instance
+ * @param num The number of registers
+ * @param offset The beginning register offset
+ * @param values The register values
+ */
+
+#define NV_REGR_MULT(rm, aperture, instance, num, offsets, values) \
+    NvRegrm((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(num),(offsets),(values))
+
+#define NV_REGW_MULT(rm, aperture, instance, num, offsets, values) \
+    NvRegwm((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(num),(offsets),(values))
+
+#define NV_REGW_BLOCK(rm, aperture, instance, num, offset, values) \
+    NvRegwb((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(num),(offset),(values))
+
+#define NV_REGR_BLOCK(rm, aperture, instance, num, offset, values) \
+    NvRegrb((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(num),(offset),(values))
+
+ void NvRegrm( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 num,
+    const NvU32 * offsets,
+    NvU32 * values );
+
+ void NvRegwm( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 num,
+    const NvU32 * offsets,
+    const NvU32 * values );
+
+ void NvRegwb( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 num,
+    NvU32 offset,
+    const NvU32 * values );
+
+ void NvRegrb( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 num,
+    NvU32 offset,
+    NvU32 * values );
+
+#define NV_REGR08(rm, aperture, instance, offset) \
+    NvRegr08((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(offset))
+
+#define NV_REGW08(rm, aperture, instance, offset, data) \
+    NvRegw08((rm),(NvRmModuleID)NVRM_MODULE_ID((aperture),(instance)),(offset),(data))
+
+ NvU8 NvRegr08( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvRmModuleID aperture,
+    NvU32 offset );
+
+ void NvRegw08( 
+    NvRmDeviceHandle rm,
+    NvRmModuleID aperture,
+    NvU32 offset,
+    NvU8 data );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_moduleloader.h b/arch/arm/mach-tegra/nv/include/nvrm_moduleloader.h
new file mode 100644
index 000000000000..6214a1ac1413
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_moduleloader.h
@@ -0,0 +1,180 @@
+/*
+ * arch/arm/mach-tegra/include/nvrm_moduleloader.h
+ *
+ *
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef INCLUDED_nvrm_moduleloader_H
+#define INCLUDED_nvrm_moduleloader_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+#include "nvcommon.h"
+#include "nvos.h"
+
+/**
+ * NvRmLibraryHandle is an opaque handle to the Module Loader interface
+ *
+ * @ingroup nvrm_moduleloader
+ */
+
+typedef struct NvRmLibraryRec *NvRmLibraryHandle;
+
+/**
+ * @brief Defines the pin state
+ */
+
+typedef enum
+{
+    NvRmModuleLoaderReason_Attach = 0,
+    NvRmModuleLoaderReason_Detach,
+    NvRmModuleLoaderReason_AttachGreedy,
+    NvRmModuleLoaderReason_Num,
+    NvRmModuleLoaderReason_Force32 = 0x7FFFFFFF
+} NvRmModuleLoaderReason;
+
+/**
+ * Loads the segments of requested library name.
+ * This method will parse the ELF dynamic library, relocate the address,
+ * resolve the symbols and load the segments accordingly.
+ * A successful load should return a valid handle.
+ *
+ * If some of the parameters passed are not valid assert
+ * encountered in debug mode.
+ *
+ * @ingroup nvrm_moduleloader
+ *
+ * @param hDevice The handle to the RM device
+ * @param pLibName The library to be loaded.
+ * @param pArgs The arguments to be passed.
+ * @param sizeOfArgs The size of arguments passed.
+ * @param hLibHandle The handle to the loaded library
+ *
+ * @retval NvSuccess Load library operation completed successfully
+ * @retval NvError_FileReadFailed Indicates that the fileoffset read failed
+ * @retval NvError_LibraryNotFound Indicates the given library could not be found
+ * @retval NvError_InsufficientMemory Indicates memory allocation failed
+ * @retval NvError_InvalidElfFormat Indicates the ELF file is not valid
+ */
+
+ NvError NvRmLoadLibrary(
+    NvRmDeviceHandle hDevice,
+    const char * pLibName,
+    void* pArgs,
+    NvU32 sizeOfArgs,
+    NvRmLibraryHandle * hLibHandle );
+
+/**
+ * Loads the segments of requested library name.This method will parse the ELF dynamic
+ * library, relocate the address, resolve the symbols and load the segments depending
+ * on the conservative or greedy approach. In both the approaches the the IRAM_MAND
+ * sections are loaded in IRAM and DRAM_MAND sections are loaded in DRAM. In conservative
+ * approach  the IRAM_PREF sections are always loaded in SDRAM. In greedy approach
+ * the IRAM_PREF sections are first laoded in IRAM. If IRAM allocation fails for an IRAM_PREF
+ * section, it would fallback to DRAM. A successful load should return a valid handle.
+ *
+ * IRAM_MAND_ADDR = 0x40000000
+ * DRAM_MAND_ADDR = 0x10000000
+ * Then
+ *    If (vaddr < DRAM_MAND_ADDR)
+ *       IRAM_PREF Section
+ *   Else (vaddr >= IRAM_MAND_ADDR)
+ *       IRAM_MAND Section
+ *   Else
+ *       DRAM_MAND Section
+ *
+ * If some of the parameters passed are not valid assert
+ * encountered in debug mode.
+ *
+ * @ingroup nvrm_moduleloader
+ *
+ * @param hDevice The handle to the RM device
+ * @param pLibName The library to be loaded.
+ * @param pArgs The arguments to be passed.
+ * @param sizeOfArgs The size of arguments passed.
+ * @param IsApproachGreedy The approach used to load the segments.
+ * @param hLibHandle The handle to the loaded library
+ *
+ * @retval NvSuccess Load library operation completed successfully
+ * @retval NvError_FileReadFailed Indicates that the fileoffset read failed
+ * @retval NvError_LibraryNotFound Indicates the given library could not be found
+ * @retval NvError_InsufficientMemory Indicates memory allocation failed
+ * @retval NvError_InvalidElfFormat Indicates the ELF file is not valid
+ */
+
+ NvError NvRmLoadLibraryEx(
+    NvRmDeviceHandle hDevice,
+    const char * pLibName,
+    void* pArgs,
+    NvU32 sizeOfArgs,
+    NvBool IsApproachGreedy,
+    NvRmLibraryHandle * hLibHandle );
+
+/**
+ * Get symbol address for a given symbol name and handle.
+ *
+ * Client will request for symbol address for a export function by
+ * sending down the symbol name and handle to the loaded library.
+ *
+ * Assert encountered if some of the parameters passed are not valid
+ *
+ * NOTE: This function is currently only used to obtain the entry
+ * point address (ie, the address of "main"). It should be noted
+ * that the entry point must ALWAYS be in THUMB mode! Using ARM
+ * mode will cause the module to crash.
+ *
+ * @ingroup nvrm_moduleloader
+ *
+ * @param hLibHandle Library handle which is returned by NvRmLoadLibrary().
+ * @param pSymbolName pointer to a symbol name to be looked up
+ * @param pSymAddress pointer to a symbol address
+ *
+ * @retval NvSuccess Symbol address is obtained successfully.
+ * @retval NvError_SymbolNotFound Indicates the symbol requested is not found
+ */
+
+ NvError NvRmGetProcAddress(
+    NvRmLibraryHandle hLibHandle,
+    const char * pSymbolName,
+    void* * pSymAddress );
+
+/**
+ * Free the losded memory of the corresponding library handle.
+ *
+ * This API will use the handle to get the base loaded address and free the memory
+ *
+ * @param hLibHandle The handle which is returned by NvRmLoadLibrary().
+ *
+ * @retval NvSuccess Successfuly unloaded the library memory.
+ */
+
+ NvError NvRmFreeLibrary(
+    NvRmLibraryHandle hLibHandle );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_owr.h b/arch/arm/mach-tegra/nv/include/nvrm_owr.h
new file mode 100755
index 000000000000..8aebb28e4ad0
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_owr.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_owr_H
+#define INCLUDED_nvrm_owr_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_pinmux.h"
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvos.h"
+#include "nvcommon.h"
+
+/**
+ * NvRmOwrHandle is an opaque handle for the RM OWR driver.
+ */
+
+typedef struct NvRmOwrRec *NvRmOwrHandle;
+
+/**
+ * @brief Open the OWR driver. This function allocates the
+ * RM OWR handle.
+ *
+ * Assert encountered in debug mode if passed parameter is invalid.
+ *
+ * @param hDevice Handle to the Rm device which is required by Rm to acquire
+ * the resources from RM.
+ * @param instance Instance of the OWR controller to be opened. Starts from 0.
+ * @param phOwr Points to the location where the OWR handle shall be stored.
+ *
+ * @retval NvSuccess OWR driver opened successfully.
+ * @retval NvError_InsufficientMemory Indicates that function fails to allocate
+ * the memory.
+ */
+
+ NvError NvRmOwrOpen(
+    NvRmDeviceHandle hDevice,
+    NvU32 instance,
+    NvRmOwrHandle * hOwr );
+
+/**
+ * @brief Closes the OWR driver. Disables the clock and invalidates the OWR handle.
+ * This API never fails.
+ *
+ * @param hOwr A handle from NvRmOwrOpen().  If hOwr is NULL, this API does
+ *     nothing.
+ */
+
+ void NvRmOwrClose(
+    NvRmOwrHandle hOwr );
+
+/**
+ * Defines OWR transaction flags.
+ */
+
+typedef enum
+{
+
+      /// OWR read the unique address of the device.
+          NvRmOwr_ReadAddress = 1,
+
+      /// OWR memory read transaction.
+          NvRmOwr_MemRead,
+
+      /// OWR memory write transaction.
+          NvRmOwr_MemWrite,
+
+      /// OWR memory readbyte transaction.
+          NvRmOwr_ReadByte,
+
+      /// OWR memory writebyte transaction.
+          NvRmOwr_WriteByte,
+
+      /// OWR memory Check Presence
+          NvRmOwr_CheckPresence,
+
+      /// OWR readbit transaction.
+      /// The LSB will be received first.
+          NvRmOwr_ReadBit,
+
+      /// OWR writebit transaction.
+      /// The LSB will be transmitted first.
+          NvRmOwr_WriteBit,
+
+    NvRmOwrTransactionFlags_Num,
+    NvRmOwrTransactionFlags_Force32 = 0x7FFFFFFF
+} NvRmOwrTransactionFlags;
+
+/**
+ * Defines OWR transaction info structure. Contains details of the transaction.
+ */
+
+typedef struct NvRmOwrTransactionInfoRec
+{
+
+    /// Transaction type flags. See @NvRmOwrTransactionFlags
+        NvU32 Flags;
+
+    /// Offset in the OWR device where Memory read/write operations need to be performed.
+        NvU32 Offset;
+
+    /// Number of bytes to read/write.
+        NvU32 NumBytes;
+
+    /// OWR device ROM Id. This can be zero, if there is a single OWR device on the bus.
+        NvU32 Address;
+} NvRmOwrTransactionInfo;
+
+/**
+ * @brief Does multiple OWR transactions. Each transaction can be a read or write.
+ *
+ * @param hOwr Handle to the OWR channel.
+ * @param OwrPinMap for OWR controllers which are being multiplexed across
+ *        multiple pin mux configurations, this specifies which pin mux configuration
+ *        should be used for the transaction.  Must be 0 when the ODM pin mux query
+ *        specifies a non-multiplexed configuration for the controller.
+ * @param Data Pointer to the buffer for all the required read, write transactions.
+ * @param DataLength Length of the data buffer.
+ * @param Transcations Pointer to the NvRmOwrTransactionInfo structure.
+ * See @NvRmOwrTransactionInfo
+ * @param NumOfTransactions Number of transcations
+ *
+ *
+ * @retval NvSuccess OWR Transaction succeeded.
+ * @retval NvError_NotSupported Indicates assumption on parameter values violated.
+ * @retval NvError_InvalidState Indicates that the last read or write call is not
+ * completed.
+ * @retval NvError_ControllerBusy Indicates controller is presently busy with an
+ * OWR transaction.
+ */
+
+ NvError NvRmOwrTransaction(
+    NvRmOwrHandle hOwr,
+    NvU32 OwrPinMap,
+    NvU8 * Data,
+    NvU32 DataLen,
+    NvRmOwrTransactionInfo * Transaction,
+    NvU32 NumOfTransactions );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_pcie.h b/arch/arm/mach-tegra/nv/include/nvrm_pcie.h
new file mode 100644
index 000000000000..3a3c7858d98b
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_pcie.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_pcie_H
+#define INCLUDED_nvrm_pcie_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+typedef enum
+{
+
+    // NvRm PCIE access type read
+        NvRmPcieAccessType_Read,
+
+    // NvRm PCIE access type write
+        NvRmPcieAccessType_Write,
+    NvRmPcieAccessType_Num,
+    NvRmPcieAccessType_Force32 = 0x7FFFFFFF
+} NvRmPcieAccessType;
+
+
+/** Reads or writes the config space of the PCI device. 
+ * 
+ * @param hRmDeviceHandle The Rm device handle
+ * @param bus_number Bus number on on which the device is present.
+ * @param type   Specifies the access type
+ * @param offset Start offset to read the configuration data
+ * @param Data   Data in bytes used to read/write from/to device config space,
+ * depending on the access type.
+ * @param DataLen Sepcifies the length of Data Array.
+ *
+ *  Returns NvSuccess or the appropriate error code.
+ */
+
+ NvError NvRmReadWriteConfigSpace( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvU32 bus_number,
+    NvRmPcieAccessType type,
+    NvU32 offset,
+    NvU8 * Data,
+    NvU32 DataLen );
+
+
+/** Registers a MSI handler for the device at an index.
+ *
+ * @param hRmDeviceHandle The Rm device handle
+ * @param function_device_bus function/device/bus tuple.
+ * @param index Msi index. Some devices support more than 1 MSI. For those
+ * devices, index value is from (0 to max-1)
+ * @param sem Semaphore which will be signalled when the MSI interrupt is
+ * triggered.
+ * @param InterruptEnable To enable or disable interrupt.
+ *
+ *  Returns NvSuccess or the appropriate error code.
+ */
+
+
+ NvError NvRmRegisterPcieMSIHandler( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvU32 function_device_bus,
+    NvU32 index,
+    NvOsSemaphoreHandle sem,
+    NvBool InterruptEnable );
+
+ NvError NvRmRegisterPcieLegacyHandler( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvU32 function_device_bus,
+    NvOsSemaphoreHandle sem,
+    NvBool InterruptEnable );
+
+//  PCIE address map supports 64-bit addressing. But, RM driver only supports
+//  32-addressing. In the future, if the device supports 64-bit addressing, one
+//  can change this typedef.
+
+typedef NvU32 NvRmPciPhysAddr;
+
+/**
+ * Attemtps to map the Pcie memory to the 32-bit AXI address region.
+ * Ap20 reserves only 1GB PCIe aperture. Out of that 1GB, some region is reserved for
+ * the register/config/msi access. Only 768MB is left out for the PCIe memory aperture. 
+ * 
+ * @param hRmDeviceHandle   Rm device handle
+ * @param mem               "Base address registers" of a PCI device.
+ * 
+ * Returns the mapped AXI address. If the mapping fails, it returns 0.
+ */
+
+ NvRmPhysAddr NvRmMapPciMemory( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvRmPciPhysAddr mem,
+    NvU32 size );
+
+/** Unmaps the PCI to AXI address mapping
+ *  
+ * @param hRmDeviceHandle Rm device handle
+ * @param mem               AXI addresses mapped by calling NvRmMapPcieMemory
+ * API.
+ */
+
+ void NvRmUnmapPciMemory( 
+    NvRmDeviceHandle hDeviceHandle,
+    NvRmPhysAddr mem,
+    NvU32 size );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_pinmux.h b/arch/arm/mach-tegra/nv/include/nvrm_pinmux.h
new file mode 100644
index 000000000000..bafe6a2655b4
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_pinmux.h
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_pinmux_H
+#define INCLUDED_nvrm_pinmux_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvodm_modules.h"
+
+/**
+ * For each module that has pins (an I/O module), there may be several muxing
+ * configurations. This allows a driver to select or query a particular
+ * configuration per I/O module.  I/O modules may be instantiated on the
+ * chip multiple times.
+ *
+ * Certain combinations of modules configurations may not be physically
+ * possible; say that a hypothetical SPI controller configuration 3 uses pins
+ * that are shared by a hypothectial UART configuration 2.  Presently, these
+ * conflicting configurations are managed via an external tool provided by
+ * SysEng, which identifies the configurations for the ODM pin-mux tables
+ * depending upon choices made by the ODM.
+ */
+
+/**
+ * Sets the module to tristate configuration. 
+ * Use enable to release the pinmux.  The pins will be
+ * tri-stated when not in use to save power.
+ *
+ * @param hDevice The RM instance
+ * @param RmModule The module to set
+ * @param EnableTristate NV_TRUE will tristate the specified pins, NV_FALSE will un-tristate
+ */
+
+ NvError NvRmSetModuleTristate( 
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID RmModule,
+    NvBool EnableTristate );
+
+/**
+ * Sets an ODM module ID to tristate configuration.  Analagous to @see NvRmSetModuleTristate,
+ * but indexed based on the ODM module ID, rather than the controller ID.
+ *
+ * @param hDevice The RM instance
+ * @param OdmModule The module to set (should be of type NvOdmIoModule)
+ * @param OdmInstance The instance of the module to set
+ * @param EnableTristate NV_TRUE will tristate the specified pins, NV_FALSE will un-tristate
+ */
+
+ NvError NvRmSetOdmModuleTristate( 
+    NvRmDeviceHandle hDevice,
+    NvU32 OdmModule,
+    NvU32 OdmInstance,
+    NvBool EnableTristate );
+
+/**
+ * Configures modules which can provide clock sources to peripherals.
+ * If a Tegra application processor is expected to provide a clock source
+ * to an external peripheral, this API should be called to configure the
+ * clock source and to ensure that its pins are driven prior to attempting
+ * to program the peripheral through a command interface (e.g., SPI).
+ *
+ * @param hDevice The RM instance
+ * @param IoModule The module to set, must be NvOdmIoModule_ExternalClock
+ * @param Instance The instance of the I/O module to be set.
+ * @param Config The pin map configuration for the I/O module.
+ * @param EnableTristate NV_TRUE will tristate the specified clock source,
+ *                       NV_FALSE will drive it.
+ * 
+ * @retval Returns the clock frequency, in KHz, that is output on the
+ *  designated pin (or '0' if no clock frequency is specified or found).
+ */
+
+ NvU32 NvRmExternalClockConfig( 
+    NvRmDeviceHandle hDevice,
+    NvU32 IoModule,
+    NvU32 Instance,
+    NvU32 Config,
+    NvBool EnableTristate );
+
+typedef struct NvRmModuleSdmmcInterfaceCapsRec
+{
+
+   ///  Maximum bus width supported by the physical interface
+   ///  Will be 2, 4 or 8 depending on the selected pin mux
+       NvU32 MmcInterfaceWidth;
+} NvRmModuleSdmmcInterfaceCaps;
+
+typedef struct NvRmModulePcieInterfaceCapsRec
+{
+
+   ///  Maximum bus type supported by the physical interface
+   ///  Will be 4X1 or 2X2 depending on the selected pin mux
+       NvU32 PcieNumEndPoints;
+    NvU32 PcieLanesPerEp;
+} NvRmModulePcieInterfaceCaps;
+
+typedef struct NvRmModulePwmInterfaceCapsRec
+{
+
+   ///  The OR bits value of PWM Output IDs supported by the 
+   ///  physical interface depending on the selected pin mux.
+   ///  Hence, PwmOutputId_PWM0 = bit 0, PwmOutputId_PWM1 = bit 1,
+   ///  PwmOutputId_PWM2 = bit 2, PwmOutputId_PWM3 = bit 3
+       NvU32 PwmOutputIdSupported;
+} NvRmModulePwmInterfaceCaps;
+
+typedef struct NvRmModuleNandInterfaceCapsRec
+{
+
+   ///  Maximum bus width supported by the physical interface
+   ///  Will be 8 or 16 depending on the selected pin mux
+       NvU8 NandInterfaceWidth;
+    NvBool IsCombRbsyMode;
+} NvRmModuleNandInterfaceCaps;
+
+typedef struct NvRmModuleUartInterfaceCapsRec
+{
+
+   ///  Maximum number of the interface lines supported by the physical interface.
+   ///  Will be 0, 2, 4 or 8 depending on the selected pin mux.
+   ///  0 means there is no physical interface for the uart.
+   ///  2 means only rx/tx lines are supported.
+   ///  4 means only rx/tx/rtx/cts lines are supported.
+   ///  8 means full modem lines are supported.
+       NvU32 NumberOfInterfaceLines;
+} NvRmModuleUartInterfaceCaps;
+
+/**
+ * @brief Query the board-defined capabilities of an I/O controller
+ *
+ * This API will return capabilities for controller modules based on
+ * interface properties defined by ODM query interfaces, such as the
+ * pin mux query.
+ *
+ * pCap should be a pointer to the matching NvRmxxxInterfaceCaps structure
+ * (defined above) for the ModuleId, and CapStructSize should be
+ * the sizeof(structure type). and also should be word aligned.
+ * 
+ * @retval NvError_NotSupported if the specified ModuleID does not
+ *     exist on the current platform.
+ */
+
+ NvError NvRmGetModuleInterfaceCapabilities( 
+    NvRmDeviceHandle hRm,
+    NvRmModuleID ModuleId,
+    NvU32 CapStructSize,
+    void* pCaps );
+
+/**
+ * Defines SoC strap groups.
+ */
+
+typedef enum
+{
+
+    /// ram_code strap group  
+        NvRmStrapGroup_RamCode = 1,
+    NvRmStrapGroup_Num,
+    NvRmStrapGroup_Force32 = 0x7FFFFFFF
+} NvRmStrapGroup;
+
+/**
+ * Gets SoC strap value for the given strap group.
+ * 
+ * @param hDevice The RM instance
+ * @param StrapGroup Strap group to be read.
+ * @pStrapValue A pointer to the returned strap group value.
+ * 
+ * @retval NvSuccess if strap value is read successfully
+ * @retval NvError_NotSupported if the specified strap group does not
+ *   exist on the current SoC.
+ */
+
+ NvError NvRmGetStraps( 
+    NvRmDeviceHandle hDevice,
+    NvRmStrapGroup StrapGroup,
+    NvU32 * pStrapValue );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_pmu.h b/arch/arm/mach-tegra/nv/include/nvrm_pmu.h
new file mode 100644
index 000000000000..7ab6fa92d309
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_pmu.h
@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_pmu_H
+#define INCLUDED_nvrm_pmu_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_init.h"
+
+/**
+ * @defgroup nvrm_pmu 
+ *   
+ * This is the power management unit (PMU) API for Rm, which
+ * handles the abstraction of external power management devices.
+ * For NVIDIA&reg; Driver Development Kit (DDK) clients, PMU is a 
+ * set of voltages used to provide power to the SoC or to monitor low battery 
+ * conditions. The API allows DDK clients to determine whether the
+ * particular voltage is supported by the ODM platform, retrieve the
+ * capabilities of PMU, and get/set voltage levels at runtime. 
+ *
+ * All voltage rails are referenced using ODM-assigned unsigned integers. ODMs
+ * may select any convention for assigning these values; however, the values
+ * accepted as input parameters by the PMU ODM adaptation interface must
+ * match the values stored in the address field of \c NvRmIoModule_Vdd buses
+ * defined in the Peripheral Discovery ODM adaptation.
+ * 
+ *
+ * @ingroup nvrm_pmu
+ * @{
+ */
+
+/**
+ * Combines information for the particular PMU Vdd rail.
+ */
+
+typedef struct NvRmPmuVddRailCapabilitiesRec
+{
+
+    /// Specifies ODM protection attribute; if \c NV_TRUE PMU hardware
+    ///  or ODM Kit would protect this voltage from being changed by NvDdk client.
+        NvBool RmProtected;
+
+    /// Specifies the minimum voltage level in mV.
+        NvU32 MinMilliVolts;
+
+    /// Specifies the step voltage level in mV.
+        NvU32 StepMilliVolts;
+
+    /// Specifies the maximum voltage level in mV.
+        NvU32 MaxMilliVolts;
+
+    /// Specifies the request voltage level in mV.
+        NvU32 requestMilliVolts;
+} NvRmPmuVddRailCapabilities;
+
+/// Special level to indicate voltage plane is disabled.
+#define ODM_VOLTAGE_OFF (0UL)
+
+/**
+ * Gets capabilities for the specified PMU voltage.
+ *
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pCapabilities A pointer to the targeted
+ *  capabilities returned by the ODM.
+ */
+
+ void NvRmPmuGetCapabilities( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvRmPmuVddRailCapabilities * pCapabilities );
+
+/**
+ * Gets current voltage level for the specified PMU voltage.
+ *
+ * @param hDevice The Rm device handle.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param pMilliVolts A pointer to the voltage level returned
+ *  by the ODM.
+ */
+
+ void NvRmPmuGetVoltage( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32 * pMilliVolts );
+
+/**
+ * Sets new voltage level for the specified PMU voltage.
+ *
+ * @param hDevice The Rm device handle.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param MilliVolts The new voltage level to be set in millivolts (mV).
+ *  Set to \c ODM_VOLTAGE_OFF to turn off the target voltage.
+ * @param pSettleMicroSeconds A pointer to the settling time in microseconds (uS),
+ *  which is the time for supply voltage to settle after this function 
+ *  returns; this may or may not include PMU control interface transaction time, 
+ *  depending on the ODM implementation. If null this parameter is ignored. 
+ */
+
+ void NvRmPmuSetVoltage( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32 MilliVolts,
+    NvU32 * pSettleMicroSeconds );
+
+/**
+ * Configures SoC power rail controls for the upcoming PMU voltage transition.
+ *
+ * @note Should be called just before PMU rail On/Off, or Off/On transition.
+ *  Should not be called if rail voltage level is changing within On range.
+ * 
+ * @param hDevice The Rm device handle.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param Enable Set NV_TRUE if target voltage is about to be turned On, or
+ *  NV_FALSE if target voltage is about to be turned Off.
+ */
+
+ void NvRmPmuSetSocRailPowerState( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvBool Enable );
+
+/**
+ * Defines Charging path.
+ */
+
+typedef enum
+{
+
+    /// Specifies external wall plug charger.
+        NvRmPmuChargingPath_MainPlug,
+
+    /// Specifies external USB bus charger.
+        NvRmPmuChargingPath_UsbBus,
+    NvRmPmuChargingPath_Num,
+    NvRmPmuChargingPath_Force32 = 0x7FFFFFFF
+} NvRmPmuChargingPath;
+
+/// Special level to indicate dumb charger current limit.
+#define NVODM_DUMB_CHARGER_LIMIT (0xFFFFFFFFUL)
+
+/**
+ * Defines AC status.
+ */
+
+typedef enum
+{
+
+    /// Specifies AC is offline.
+        NvRmPmuAcLine_Offline,
+
+    /// Specifies AC is online.
+        NvRmPmuAcLine_Online,
+
+    /// Specifies backup power.
+        NvRmPmuAcLine_BackupPower,
+    NvRmPmuAcLineStatus_Num,
+    NvRmPmuAcLineStatus_Force32 = 0x7FFFFFFF
+} NvRmPmuAcLineStatus;
+
+/** @name Battery Status Defines */
+/*@{*/
+
+#define NVODM_BATTERY_STATUS_HIGH               0x01
+#define NVODM_BATTERY_STATUS_LOW                0x02
+#define NVODM_BATTERY_STATUS_CRITICAL           0x04
+#define NVODM_BATTERY_STATUS_CHARGING           0x08
+#define NVODM_BATTERY_STATUS_NO_BATTERY         0x80
+#define NVODM_BATTERY_STATUS_UNKNOWN            0xFF
+
+/*@}*/
+/** @name Battery Data Defines */
+/*@{*/
+#define NVODM_BATTERY_DATA_UNKNOWN              0x7FFFFFFF
+
+/*@}*/
+
+/**
+ * Defines battery instances.
+ */
+
+typedef enum
+{
+
+    /// Specifies main battery.
+        NvRmPmuBatteryInst_Main,
+    NvRmPmuBatteryInst_Backup,
+    NvRmPmuBatteryInstance_Num,
+    NvRmPmuBatteryInstance_Force32 = 0x7FFFFFFF
+} NvRmPmuBatteryInstance;
+
+/**
+ * Defines battery data.
+ */
+
+typedef struct NvRmPmuBatteryDataRec
+{
+
+    /// Specifies battery life percent.
+        NvU32 batteryLifePercent;
+
+    /// Specifies battery life time.
+        NvU32 batteryLifeTime;
+
+    /// Specifies voltage.
+        NvU32 batteryVoltage;
+
+    /// Specifies battery current.
+        NvS32 batteryCurrent;
+
+    /// Specifies battery average current.
+        NvS32 batteryAverageCurrent;
+
+    /// Specifies battery interval.
+        NvU32 batteryAverageInterval;
+
+    /// Specifies the mAH consumed.
+        NvU32 batteryMahConsumed;
+
+    /// Specifies battery temperature.
+        NvU32 batteryTemperature;
+} NvRmPmuBatteryData;
+
+/**
+ * Defines battery chemistry.
+ */
+
+typedef enum
+{
+
+    /// Specifies an alkaline battery.
+        NvRmPmuBatteryChemistry_Alkaline,
+
+    /// Specifies a nickel-cadmium (NiCd) battery.
+        NvRmPmuBatteryChemistry_NICD,
+
+    /// Specifies a nickel-metal hydride (NiMH) battery.
+        NvRmPmuBatteryChemistry_NIMH,
+
+    /// Specifies a lithium-ion (Li-ion) battery.
+        NvRmPmuBatteryChemistry_LION,
+
+    /// Specifies a lithium-ion polymer (Li-poly) battery.
+        NvRmPmuBatteryChemistry_LIPOLY,
+
+    /// Specifies a zinc-air battery.
+        NvRmPmuBatteryChemistry_XINCAIR,
+    NvRmPmuBatteryChemistry_Num,
+    NvRmPmuBatteryChemistry_Force32 = 0x7FFFFFFF
+} NvRmPmuBatteryChemistry;
+
+/** 
+* Sets the charging current limit. 
+* 
+* @param hRmDevice The Rm device handle.
+* @param ChargingPath The charging path. 
+* @param ChargingCurrentLimitMa The charging current limit in mA. 
+* @param ChargerType Type of the charger detected 
+*        @see NvOdmUsbChargerType
+*/
+
+ void NvRmPmuSetChargingCurrentLimit( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuChargingPath ChargingPath,
+    NvU32 ChargingCurrentLimitMa,
+    NvU32 ChargerType );
+
+/**
+ * Gets the AC line status.
+ *
+ * @param hDevice The Rm device handle.
+ * @param pStatus A pointer to the AC line
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+
+ NvBool NvRmPmuGetAcLineStatus( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuAcLineStatus * pStatus );
+
+/**
+ * Gets the battery status.
+ *
+ * @param hDevice The Rm device handle.
+ * @param batteryInst The battery type.
+ * @param pStatus A pointer to the battery
+ *  status returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+
+ NvBool NvRmPmuGetBatteryStatus( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvU8 * pStatus );
+
+/**
+ * Gets the battery data.
+ *
+ * @param hDevice The Rm device handle.
+ * @param batteryInst The battery type.
+ * @param pData A pointer to the battery
+ *  data returned by the ODM.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+
+ NvBool NvRmPmuGetBatteryData( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvRmPmuBatteryData * pData );
+
+/**
+ * Gets the battery full life time.
+ *
+ * @param hDevice The Rm device handle.
+ * @param batteryInst The battery type.
+ * @param pLifeTime A pointer to the battery
+ *  full life time returned by the ODM.
+ * 
+ */
+
+ void NvRmPmuGetBatteryFullLifeTime( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvU32 * pLifeTime );
+
+/**
+ * Gets the battery chemistry.
+ *
+ * @param hDevice The Rm device handle.
+ * @param batteryInst The battery type.
+ * @param pChemistry A pointer to the battery
+ *  chemistry returned by the ODM.
+ * 
+ */
+
+ void NvRmPmuGetBatteryChemistry( 
+    NvRmDeviceHandle hRmDevice,
+    NvRmPmuBatteryInstance batteryInst,
+    NvRmPmuBatteryChemistry * pChemistry );
+
+/**
+ * Reads current RTC count in seconds.
+ *
+ * @param hRmDevice The Rm device handle.
+ * @param Count A pointer to the RTC count returned by this function.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise. 
+ */
+
+ NvBool NvRmPmuReadRtc( 
+    NvRmDeviceHandle hRmDevice,
+    NvU32 * pCount );
+
+/**
+ * Updates current RTC seconds count.
+ *
+ * @param hRmDevice The Rm device handle.
+ * @param Count Seconds count to update the RTC counter.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise.
+ */
+
+ NvBool NvRmPmuWriteRtc( 
+    NvRmDeviceHandle hRmDevice,
+    NvU32 Count );
+
+/**
+ * Verifies whether the RTC is initialized.
+ *
+ * @param hRmDevice The Rm device handle.
+ * 
+ * @return NV_TRUE if initialized, or NV_FALSE otherwise.
+ */
+
+ NvBool NvRmPmuIsRtcInitialized( 
+    NvRmDeviceHandle hRmDevice );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_power.h b/arch/arm/mach-tegra/nv/include/nvrm_power.h
new file mode 100644
index 000000000000..e8be8c9bf4cf
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_power.h
@@ -0,0 +1,1326 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_power_H
+#define INCLUDED_nvrm_power_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvos.h"
+
+/**
+ * Frequency data type, expressed in KHz.
+ */
+
+typedef NvU32 NvRmFreqKHz;
+
+/**
+ * Special value for an unspecified or default frequency.
+ */
+static const NvRmFreqKHz NvRmFreqUnspecified = 0xFFFFFFFF;
+
+/**
+ * Special value for the maximum possible frequency.
+ */
+static const NvRmFreqKHz NvRmFreqMaximum = 0xFFFFFFFD;
+
+/**
+ * Voltage data type, expressed in millivolts.
+ */
+
+typedef NvU32 NvRmMilliVolts;
+
+/**
+ * Special value for an unspecified or default voltage.
+ */
+static const NvRmMilliVolts NvRmVoltsUnspecified = 0xFFFFFFFF;
+
+/**
+ * Special value for the maximum possible voltage.
+ */
+static const NvRmMilliVolts NvRmVoltsMaximum = 0xFFFFFFFD;
+
+/**
+ * Special value for voltage / power disable.
+ */
+static const NvRmMilliVolts NvRmVoltsCycled = 0xFFFFFFFC;
+
+/**
+ * Special value for voltage / power disable.
+ */
+static const NvRmMilliVolts NvRmVoltsOff = 0;
+
+/**
+ * Defines possible power management events
+ */
+
+typedef enum
+{
+
+    /// Specifies no outstanding events
+        NvRmPowerEvent_NoEvent = 1,
+
+    /// Specifies wake from LP0
+        NvRmPowerEvent_WakeLP0,
+
+    /// Specifies wake from LP1
+        NvRmPowerEvent_WakeLP1,
+    NvRmPowerEvent_Num,
+    NvRmPowerEvent_Force32 = 0x7FFFFFFF
+} NvRmPowerEvent;
+
+/**
+ * Defines combined RM clients power state
+ */
+
+typedef enum
+{
+
+    /// Specifies boot state ("RM is not open, yet")
+        NvRmPowerState_Boot = 1,
+
+    /// Specifies active state ("not ready-to-suspend")
+    /// This state is entered if any client enables power to any module, other
+    /// than NvRmPrivModuleID_System, via NvRmPowerVoltageControl() API
+        NvRmPowerState_Active,
+
+    /// Specifies h/w autonomous state ("ready-to-core-power-on-suspend")
+    /// This state is entered if all RM clients enable power only for
+    /// NvRmPrivModuleID_System, via NvRmPowerVoltageControl() API
+        NvRmPowerState_AutoHw,
+
+    /// Specifies idle state ("ready-to-core-power-off-suspend")
+    /// This state is entered if none of the RM clients enables power
+    /// to any module.
+        NvRmPowerState_Idle,
+
+    /// Specifies LP0 state ("main power-off suspend")
+        NvRmPowerState_LP0,
+
+    /// Specifies LP1 state ("main power-on suspend")
+        NvRmPowerState_LP1,
+
+    /// Specifies Skipped LP0 state (set when LP0 entry error is
+    /// detected, SoC resumes operations without entering LP0 state)
+        NvRmPowerState_SkippedLP0,
+    NvRmPowerState_Num,
+    NvRmPowerState_Force32 = 0x7FFFFFFF
+} NvRmPowerState;
+
+/** Defines the clock configuration flags which are applicable for some modules.
+ * Multiple flags can be OR'ed and passed to the NvRmPowerModuleClockConfig API.
+*/
+
+typedef enum
+{
+
+    /// Use external clock for the pads of the module.
+        NvRmClockConfig_ExternalClockForPads = 0x1,
+
+    /// Use internal clock for the pads of the module
+        NvRmClockConfig_InternalClockForPads = 0x2,
+
+    /// Use external clock for the core of the module, or
+    /// module is in slave mode
+        NvRmClockConfig_ExternalClockForCore = 0x4,
+
+    /// Use Internal clock for the core of the module, or
+    /// module is in master mode.
+        NvRmClockConfig_InternalClockForCore = 0x8,
+ 
+    /// Use inverted clock for the module. i.e the polarity of the clock used is
+    /// inverted with respect to the source clock.
+        NvRmClockConfig_InvertedClock = 0x10,
+ 
+    /// Configure target module sub-clock
+    /// - Target Display: configure Display and TVDAC
+    /// - Target TVO: configure CVE and TVDAC only
+    /// - Target VI: configure VI_SENSOR only
+    /// - Target SPDIF: configure SPDIFIN only
+        NvRmClockConfig_SubConfig = 0x20,
+ 
+    /// Use MIPI PLL as Display clock source
+        NvRmClockConfig_MipiSync = 0x40,
+ 
+    /// Adjust Audio PLL to match requested I2S or SPDIF frequency
+        NvRmClockConfig_AudioAdjust = 0x80,
+ 
+    /// Disable TVDAC along with Display configuration
+        NvRmClockConfig_DisableTvDAC = 0x100,
+ 
+    /// Do not fail clock configuration request with specific target frequency
+    /// above Hw limit - just configure clock at Hw limit. (Note that caller
+    /// can request NvRmFreqMaximum to configure clock at Hw limit, regardless
+    /// of this flag presence).
+        NvRmClockConfig_QuietOverClock = 0x200,
+    NvRmClockConfigFlags_Num,
+    NvRmClockConfigFlags_Force32 = 0x7FFFFFFF
+} NvRmClockConfigFlags;
+
+/**
+ * Defines SOC-wide clocks controlled by Dynamic Frequency Scaling (DFS)
+ * that can be targeted by Starvation and Busy hints
+ */
+
+typedef enum
+{
+
+    /// Specifies CPU clock
+        NvRmDfsClockId_Cpu = 1,
+
+    /// Specifies AVP clock
+        NvRmDfsClockId_Avp,
+
+    /// Specifies System bus clock
+        NvRmDfsClockId_System,
+
+    /// Specifies AHB bus clock
+        NvRmDfsClockId_Ahb,
+
+    /// Specifies APB bus clock
+        NvRmDfsClockId_Apb,
+
+    /// Specifies video pipe clock
+        NvRmDfsClockId_Vpipe,
+
+    /// Specifies external memory controller clock
+        NvRmDfsClockId_Emc,
+    NvRmDfsClockId_Num,
+    NvRmDfsClockId_Force32 = 0x7FFFFFFF
+} NvRmDfsClockId;
+
+/**
+ * Defines DFS manager run states
+ */
+
+typedef enum
+{
+
+    /// DFS is in invalid, not initialized state
+        NvRmDfsRunState_Invalid = 0,
+
+    /// DFS is disabled / not supported (terminal state)
+        NvRmDfsRunState_Disabled = 1,
+
+    /// DFS is stopped - no automatic clock control. Starvation and Busy hints
+    /// are recorded but have no affect.
+        NvRmDfsRunState_Stopped,
+
+    /// DFS is running in closed loop - full automatic control of SoC-wide
+    /// clocks based on clock activity measuremnets. Starvation and Busy hints
+    /// are functional as well.
+        NvRmDfsRunState_ClosedLoop,
+
+    /// DFS is running in closed loop with profiling (can not be set on non
+    /// profiling build).
+        NvRmDfsRunState_ProfiledLoop,
+    NvRmDfsRunState_Num,
+    NvRmDfsRunState_Force32 = 0x7FFFFFFF
+} NvRmDfsRunState;
+
+/**
+ * Defines DFS profile targets
+ */
+
+typedef enum
+{
+
+    /// DFS algorithm within ISR
+        NvRmDfsProfileId_Algorithm = 1,
+
+    /// DFS Interrupt service - includes algorithm plus OS locking and
+    ///  signaling calls; hence, includes blocking time (if any) as well
+        NvRmDfsProfileId_Isr,
+
+    /// DFS clock control time - includes PLL stabilazation time, OS locking
+    /// and signalling calls; hence, includes blocking time (if any) as well 
+        NvRmDfsProfileId_Control,
+    NvRmDfsProfileId_Num,
+    NvRmDfsProfileId_Force32 = 0x7FFFFFFF
+} NvRmDfsProfileId;
+
+/**
+ * Defines voltage rails that are controlled in conjunction with dynamic
+ * frequency scaling.
+ */
+
+typedef enum
+{
+
+    /// SoC core rail
+        NvRmDfsVoltageRailId_Core = 1,
+
+    /// Dedicated CPU rail
+        NvRmDfsVoltageRailId_Cpu,
+    NvRmDfsVoltageRailId_Num,
+    NvRmDfsVoltageRailId_Force32 = 0x7FFFFFFF
+} NvRmDfsVoltageRailId;
+
+/**
+ * Defines busy hint API synchronization modes.
+ */
+
+typedef enum
+{
+
+    /// Asynchronous mode (non-blocking API)
+        NvRmDfsBusyHintSyncMode_Async = 1,
+
+    /// Synchronous mode (blocking API)
+        NvRmDfsBusyHintSyncMode_Sync,
+    NvRmDfsBusyHintSyncMode_Num,
+    NvRmDfsBusyHintSyncMode_Force32 = 0x7FFFFFFF
+} NvRmDfsBusyHintSyncMode;
+
+/**
+ * Holds information on DFS clock domain utilization
+ */
+
+typedef struct NvRmDfsClockUsageRec
+{
+
+    /// Minimum clock domain frequency
+        NvRmFreqKHz MinKHz;
+
+    /// Maximum clock domain frequency
+        NvRmFreqKHz MaxKHz;
+
+    /// Low corner frequency - current low boundary for DFS control algorithm.
+    /// Can be dynamically adjusted via APIs: NvRmDfsSetLowCorner() for all DFS
+    /// domains, NvRmDfsSetCpuEnvelope() for CPU, and NvRmDfsSetEmcEnvelope()
+    /// for EMC. When all DFS domains hit low corner, DFS stops waking up CPU
+    ///  from low power state.
+        NvRmFreqKHz LowCornerKHz;
+
+    /// High corner frequency - current high boundary for DFS control algorithm.
+    /// Can be dynamically adjusted via APIs: NvRmDfsSetCpuEnvelope() for Cpu,
+    /// NvRmDfsSetEmcEnvelope() for Emc, and NvRmDfsSetAvHighCorner() for other
+    //  DFS domains.
+        NvRmFreqKHz HighCornerKHz;
+
+    /// Current clock domain frequency
+        NvRmFreqKHz CurrentKHz;
+
+    /// Average frequency of domain *activity* (not average frequency). For
+    /// domains that do not have activity monitors reported as unspecified.
+        NvRmFreqKHz AverageKHz;
+} NvRmDfsClockUsage;
+
+/**
+ * Holds information on DFS busy hint
+ */
+
+typedef struct NvRmDfsBusyHintRec
+{
+
+    /// Target clock domain ID
+        NvRmDfsClockId ClockId;
+
+    /// Requested boost duration in milliseconds
+        NvU32 BoostDurationMs;
+
+    /// Requested clock frequency level in kHz
+        NvRmFreqKHz BoostKHz;
+
+    /// Busy pulse mode indicator - if true, busy boost is completely removed
+    /// after busy time has expired; if false, DFS will gradually lower domain
+    /// frequency after busy boost.
+        NvBool BusyAttribute;
+} NvRmDfsBusyHint;
+
+/**
+ * Holds information on DFS starvation hint
+ */
+
+typedef struct NvRmDfsStarvationHintRec
+{
+
+    /// Target clock domain ID
+        NvRmDfsClockId ClockId;
+
+    /// The starvation indicator for the target domain
+        NvBool Starving;
+} NvRmDfsStarvationHint;
+
+/**
+ * The NVRM_POWER_CLIENT_TAG macro is used to convert ASCII 4-character codes
+ * into the 32-bit tag that can be used to identify power manager clients for
+ * logging purposes.
+ */
+#define NVRM_POWER_CLIENT_TAG(a,b,c,d) \
+    ((NvU32) ((((a)&0xffUL)<<24UL) |  \
+              (((b)&0xffUL)<<16UL) |  \
+              (((c)&0xffUL)<< 8UL) |  \
+              (((d)&0xffUL))))
+
+/**
+ * Registers RM power client.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param hEventSemaphore The client semaphore for power management event
+ *  signaling. If null, no events will be signaled to the particular client.
+ * @param pClientId A pointer to the storage that on entry contains client
+ *  tag (optional), and on exit returns client ID, assigned by power manager.
+ *
+ * @retval NvSuccess if registration was successful.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for client
+ *  registration.
+ */
+
+ NvError NvRmPowerRegister( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvOsSemaphoreHandle hEventSemaphore,
+    NvU32 * pClientId );
+
+/**
+ * Unregisters RM power client. Power and clock for the modules enabled by this
+ * client are disabled and any starvation or busy requests are cancelled during
+ * the unregistration.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClientId The client ID obtained during registration.
+ */
+
+ void NvRmPowerUnRegister( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId );
+
+/**
+ * Gets last detected and not yet retrieved power management event.
+ * Returns no outstanding event if no events has been detected since the
+ * client registration or the last call to this function.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClientId The client ID obtained during registration.
+ * @param pEvent Output storage pointer for power event identifier.
+ *
+ * @retval NvSuccess if event identifier was retrieved successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ */
+
+ NvError NvRmPowerGetEvent( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId,
+    NvRmPowerEvent * pEvent );
+
+/**
+ * Notifies RM about power management event. Provides an interface for
+ * OS power manager to report system power events to RM.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param Event The event RM power manager is to be aware of.
+ */
+
+ void NvRmPowerEventNotify( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerEvent Event );
+
+/**
+ * Gets combined RM clients power state.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param pState Output storage pointer for combined RM clients power state.
+ *
+ * @retval NvSuccess if power state was retrieved successfully.
+ */
+
+ NvError NvRmPowerGetState( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerState * pState );
+
+/**
+ * Gets SoC primary oscillator/input frequency.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ *
+ * @retval Primary frequency in KHz.
+ */
+
+ NvRmFreqKHz NvRmPowerGetPrimaryFrequency( 
+    NvRmDeviceHandle hRmDeviceHandle );
+
+/**
+ * Gets maximum frequency limit for the module clock.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ModuleId The combined module ID and instance of the target module.
+ * 
+ * @retval Module clock maximum frequency in KHz.
+ */
+
+ NvRmFreqKHz NvRmPowerModuleGetMaxFrequency( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId );
+
+/**
+ *  This API is used to set the clock configuration of the module clock.
+ *  This API can also be used to query the existing configuration.
+ * 
+ *  Usage example:
+ * 
+ *  NvError Error;
+ *  NvRmFreqKHz MyFreqKHz = 0;
+ *  ModuleId = NVRM_MODULE_ID(NvRmModuleID_Uart, 0);
+ * 
+ *  // Get current frequency settings
+ *  Error = NvRmPowerModuleClockConfig(RmHandle, ModuleId, ClientId,
+ *                                      0, 0, NULL, 0, &MyFreqKHz, 0);
+ * 
+ * // Set target frequency within HW defined limits
+ * MyFreqKHz = TARGET_FREQ;
+ * Error = NvRmPowerModuleClockConfig(RmHandle, ModuleId, ClientId,
+ *                                    NvRmFreqUnspecified, NvRmFreqUnspecified,
+ *                                    &MyFreqKHz, 1, &MyFreqKHz);
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ModuleId The combined module ID and instance of the target module.
+ * @param ClientId The client ID obtained during registration.
+ * @param MinFreq Requested minimum frequency for hardware module operation.
+ *      If the value is NvRmFreqUnspecified, RM uses the the min freq that this
+ *      module can operate. 
+ *      If the value specified is more than the Hw minimum, passed value is used.
+ *      If the value specified is less than the Hw minimum, it will be clipped to
+ *      the HW minimum value.
+ * @param MaxFreq Requested maximum frequency for hardware module operation.
+ *      If the value is NvRmFreqUnspecified, RM uses the the max freq that this
+ *      module can run.
+ *      If the value specified is less than the Hw maximum, that value is used.
+ *      If the value specified is more than the Hw limit, it will be clipped to
+ *      the HW maximum.
+ * @param PrefFreqList Pointer to a list of preferred frequencies, sorted in the
+ *      decresing order of priority. Use NvRmFreqMaximum to request Hw maximum.
+ * @param PrefFreqListCount Number of entries in the PrefFreqList array.
+ * @param CurrentFreq Returns the current clock frequency of that module. NULL
+ *      is a valid value for this parameter.
+ * @param flags Module specific flags. Thse flags are valid only for some
+ *      modules. See @NvRmClockConfigFlags
+ * 
+ * @retval NvSuccess if clock control request completed successfully.
+ * @retval NvError_ModuleNotPresent if the module ID or instance is invalid.
+ * @retval NvError_NotSupported if failed to configure requested frequency (e.g.,
+ *  output frequency for possible divider settings is outside specified range).
+ */
+
+ NvError NvRmPowerModuleClockConfig( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvRmFreqKHz MinFreq,
+    NvRmFreqKHz MaxFreq,
+    const NvRmFreqKHz * PrefFreqList,
+    NvU32 PrefFreqListCount,
+    NvRmFreqKHz * CurrentFreq,
+    NvU32 flags );
+
+/**
+ *  This API is used to enable and disable the module clock.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ModuleId The combined module ID and instance of the target module.
+ * @param ClientId The client ID obtained during registration.
+ * @param Enable Enables/diables the module clock.
+ * 
+ * @retval NvSuccess if the module is enabled.
+ * @retval NvError_ModuleNotPresent if the module ID or instance is invalid.
+ */
+
+ NvError NvRmPowerModuleClockControl( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvBool Enable );
+
+/**
+ * Request the voltage range for a hardware module. As power planes are shared
+ * between different modules, in the majority of cases the RM will choose the
+ * appropriate voltage, and module owners only need to enable or disable power
+ * for a module. Enable request is always completed (i.e., voltage is applied
+ * to the module) before this function returns. Disable request just means that
+ * the client is ready for module power down. Actually the power may be removed
+ * within the call or any time later, depending on other client needs and power
+ * plane dependencies with other modules.
+ * 
+ * Assert encountered in debug mode if the module ID or instance is invalid.
+ *
+ * Usage example:
+ * 
+ * NvError Error;
+ * ModuleId = NVRM_MODULE_ID(NvRmModuleID_Uart, 0);
+ * 
+ * // Enable module power
+ * Error = NvRmPowerVoltageControl(RmHandle, ModuleId, ClientId,
+ *          NvRmVoltsUnspecified, NvRmVoltsUnspecified,
+ *          NULL, 0, NULL);
+ * 
+ * // Disable module power
+ * Error = NvRmPowerVoltageControl(RmHandle, ModuleId, ClientId,
+ *          NvRmVoltsOff, NvRmVoltsOff,
+ *          NULL, 0, NULL);
+ * 
+ * @param hRmDeviceHandle The RM device handle
+ * @param ModuleId The combined module ID and instance of the target module
+ * @param ClientId The client ID obtained during registration
+ * @param MinVolts Requested minimum voltage for hardware module operation
+ * @param MaxVolts Requested maximum voltage for hardware module operation
+ *  Set to NvRmVoltsUnspecified when enabling power for a module, or to
+ *  NvRmVoltsOff when disabling.
+ * @param PrefVoltageList Pointer to a list of preferred voltages, ordered from
+ *  lowest to highest, and terminated with a voltage of NvRmVoltsUnspecified.
+ *  This parameter is optional - ignored if null.
+ * @param PrefVoltageListCount Number of entries in the PrefVoltageList array.
+ * @param CurrentVolts Output storage pointer for resulting module voltage.
+ *  NvRmVoltsUnspecified is returned if module power is On and was not cycled,
+ *   since the last voltage request with the same ClientId and ModuleId;
+ *  NvRmVoltsCycled is returned if module power is On but was powered down,
+ *   since the last voltage request with the same ClientId and ModuleId;
+ *  NvRmVoltsOff  is returned if module power is Off.
+ *  This parameter is optional - ignored  if null.
+ * 
+ * @retval NvSuccess if voltage control request completed successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  voltage request.
+ */
+
+ NvError NvRmPowerVoltageControl( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvRmMilliVolts MinVolts,
+    NvRmMilliVolts MaxVolts,
+    const NvRmMilliVolts * PrefVoltageList,
+    NvU32 PrefVoltageListCount,
+    NvRmMilliVolts * CurrentVolts );
+
+/**
+ * Lists modules registered by power clients for voltage control.
+ * 
+ * @param pListSize Pointer to the list size. On entry specifies list size
+ *  allocated by the caller, on exit - actual number of Ids returned. If
+ *  entry size is 0, maximum list size is returned. 
+ * @param pIdList Pointer to the list of combined module Id/Instance values
+ *  to be filled in by this function. Ignored if input list size is 0.
+ * @param pActiveList Pointer to the list of modules Active attributes
+ *  to be filled in by this function. Ignored if input list size is 0.
+ */                               
+
+ void NvRmListPowerAwareModules( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 * pListSize,
+    NvRmModuleID * pIdList,
+    NvBool * pActiveList );
+
+/**
+ * Requests immediate frequency boost for SOC-wide clocks. In general, the RM
+ * DFS manages SOC-wide clocks by measuring the average use of clock cycles,
+ * and adjusting clock rates to minimize wasted clocks. It is preferable and
+ * expected that modules consume clock cycles at a more-or-less constant rate.
+ * Under some circumstances this will not be the case. For example, many cycles
+ * may be consumed to prime a new media processing activity. If power client
+ * anticipates such circumstances, it may sparingly use this API to alert the RM
+ * that a temporary spike in clock usage is about to occur.
+ *
+ * Usage example:
+ * 
+ * // Busy hint for CPU clock
+ * NvError Error;
+ * Error = NvRmPowerBusyHint(RmHandle, NvRmDfsClockId_Cpu, ClientId,
+ *          BoostDurationMs, BoostFreqKHz);
+ *
+ * Clients should not call this API in an attempt to micro-manage a particular
+ * clock frequency as that is the responsibility of the RM.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClockId The DFS ID of the clock targeted by this hint.
+ * @param ClientId The client ID obtained during registration.
+ * @param BoostDurationMs The estimate of the boost duration in milliseconds.
+ *  Use NV_WAIT_INFINITE to specify busy until canceled. Use 0 to request
+ *  instantaneous spike in frequency and let DFS to scale down. 
+ * @param BoostKHz The requirements for the boosted clock frequency in kHz.
+ *  Use NvRmFreqMaximum to request maximum domain frequency. Use 0 to cancel
+ *  all busy hints reported by the specified client for the specified domain.
+ *
+ * @retval NvSuccess if busy request completed successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  busy hint.
+ */
+
+ NvError NvRmPowerBusyHint( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsClockId ClockId,
+    NvU32 ClientId,
+    NvU32 BoostDurationMs,
+    NvRmFreqKHz BoostKHz );
+
+/**
+ * Requests immediate frequency boost for multiple SOC-wide clock domains. 
+ * @sa NvRmPowerBusyHint() for detailed explanation of busy hint effects. 
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClientId The client ID obtained during registration.
+ * @param pMultiHint Pointer to a list of busy hint records for
+ *  targeted clocks.
+ * @param NumHints Number of entries in pMultiHint array.
+ * @param Mode Synchronization mode. In asynchronous mode this API returns to
+ *  the caller after request is signaled to power manager (non-blocking call).
+ *  In synchronous mode the API returns after busy hints are processed by power
+ *  manager (blocking call).
+ * 
+ * @note It is recommended to use synchronous mode only when low frequency
+ *  may result in functional failure. Otherwise, use asynchronous mode or
+ *  NvRmPowerBusyHint API, which is always executed as non-blocking request.
+ *  Synchronous mode must not be used by PMU transport.
+ * 
+ *
+ * @retval NvSuccess if busy hint request completed successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  busy hints.
+ */
+
+ NvError NvRmPowerBusyHintMulti( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId,
+    const NvRmDfsBusyHint * pMultiHint,
+    NvU32 NumHints,
+    NvRmDfsBusyHintSyncMode Mode );
+
+/**
+ * Request frequency increase for SOC-wide clock to avoid real-time starvation
+ * conditions. Allows modules to contribute to the detection and avoidance of
+ * clock starvation for DFS controlled clocks.
+ * 
+ * This API should be called to indicate starvation threat and also to cancel
+ * request when a starvation condition has eased.
+ * 
+ * @note Although the RM DFS does its best to manage clocks without starving
+ * the system for clock cycles, bursty clock usage can occasionally cause
+ * short-term clock starvation. One solution is to leave a large enough clock
+ * rate guard band such that any possible burst in clock usage will be absorbed.
+ * This approach tends to waste clock cycles, and worsen power management.
+ * 
+ * By allowing power clients to participate in the avoidance of system clock
+ * starvation situations, detection responsibility can be moved closer to the
+ * hardware buffers and processors where starvation occurs, while leaving the
+ * overall dynamic clocking policy to the RM. A typical client would be a module
+ * that manages media processing and is able to determine when it is falling
+ * behind by watching buffer levels or some other module-specific indicator. In
+ * response to the starvation request the RM increases gradually the respective
+ * clock frequency until the request vis cancelled by the client.
+ * 
+ * Usage example:
+ * 
+ * NvError Error;
+ * 
+ * // Request CPU clock frequency increase to avoid starvation
+ * Error = NvRmPowerStarvationHint(
+ *          RmHandle, NvRmDfsClockId_Cpu, ClientId, NV_TRUE);
+ * 
+ * // Cancel starvation request for CPU clock frequency
+ * Error = NvRmPowerStarvationHint(
+ *          RmHandle, NvRmDfsClockId_Cpu, ClientId, NV_FALSE);
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClockId The DFS ID of the clock targeted by this hint.
+ * @param ClientId The client ID obtained during registration.
+ * @param Starving The starvation indicator for the target module. If true,
+ *  the client is requesting target frequency increase to avoid starvation
+ *  If false, the indication is that the imminent starvation is no longer a
+ *  concern for this particular client.
+ * 
+ * @retval NvSuccess if starvation request completed successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  starvation hint.
+ */
+
+ NvError NvRmPowerStarvationHint( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsClockId ClockId,
+    NvU32 ClientId,
+    NvBool Starving );
+
+/**
+ * Request frequency increase for multiple SOC-wide clock domains to avoid
+ * real-time starvation conditions.
+ * @sa NvRmPowerStarvationHint() for detailed explanation of starvation hint
+ * effects.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClientId The client ID obtained during registration.
+ * @param pMultiHint Pointer to a list of starvation hint records for
+ *  targeted clocks.
+ * @param NumHints Number of entries in pMultiHint array.
+ *
+ * @retval NvSuccess if starvation hint request completed successfully.
+ * @retval NvError_BadValue if specified client ID is not registered.
+ * @retval NvError_InsufficientMemory if failed to allocate memory for
+ *  starvation hints.
+ */
+
+ NvError NvRmPowerStarvationHintMulti( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 ClientId,
+    const NvRmDfsStarvationHint * pMultiHint,
+    NvU32 NumHints );
+
+/**
+ * Notifies the RM about DDK module activity.
+ * 
+ * @note This function lets DDK modules notify the RM about interesting system
+ * activities. Not all modules will need to make this indication, typically only
+ * modules involved in user input or output activities. However, with current
+ * SOC power management architecture such activities will be detected by the OS
+ * adaptation layer, not RM. This API is not removed, just in case, we will find
+ * out that RM still need to participate in user activity detection. In general,
+ * modules should call this interface sparingly, no more than once every few
+ * seconds.
+ * 
+ * In current power management architecture user activity is handled by OS
+ * (nor RM) power manager, and activity API is not used at all.
+ * 
+ * Assert encountered in debug mode if the module ID or instance is invalid.
+ *
+ * TODO: Remove this API?
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ModuleId The combined module ID and instance of the target module.
+ * @param ClientId The client ID obtained during registration.
+ * @param ActivityDurationMs The duration of the module activity.
+ * 
+ * For cases when activity is a series of discontinuous events (keypresses, for
+ * example), this parameter should simply be set to 1.
+ * 
+ * For lengthy, continuous activities, this parameter is set to the estimated
+ * length of the activity in milliseconds. This can reduce the number of calls
+ * made to this API.
+ * 
+ * A value of 0 in this parameter indicates that the module is not active and
+ * can be used to signal the end of a previously estimated continuous activity.
+ * 
+ * @retval NvSuccess if clock control request completed successfully.
+ */
+
+ NvError NvRmPowerActivityHint( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvU32 ActivityDurationMs );
+
+/**
+ * Gets DFS run sate.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * 
+ * @return Current DFS run state.
+ */
+
+ NvRmDfsRunState NvRmDfsGetState( 
+    NvRmDeviceHandle hRmDeviceHandle );
+
+/**
+ * Gets information on DFS controlled clock utilization. If DFS is stopped
+ * or disabled the average frequency is always equal to current frequency.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param ClockId The DFS ID of the clock targeted by this request.
+ * @param pClockInfo Output storage pointer for clock utilization information.
+ * 
+ * @return NvSuccess if clock usage information is returned successfully.
+ */
+
+ NvError NvRmDfsGetClockUtilization( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsClockId ClockId,
+    NvRmDfsClockUsage * pClockUsage );
+
+/**
+ * Sets DFS run state. Allows to stop or re-start DFS as well as switch
+ * between open and closed loop operations.
+ * 
+ * On transition to the DFS stopped state, the DFS clocks are just kept at
+ * current frequencies. On transition to DFS run states, DFS sampling data
+ * is re-initialized only if originally DFS was stopped. Transition between
+ * running states has no additional effects, besides operation mode changes.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param NewDfsRunState The DFS run state to be set.
+ * 
+ * @retval NvSuccess if DFS state was set successfully.
+ * @retval NvError_NotSupported if DFS was disabled initially, in attempt
+ * to disable initially enabled DFS, or in attempt to run profiled loop
+ * on non profiling build.
+ */
+
+ NvError NvRmDfsSetState( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsRunState NewDfsRunState );
+
+/**
+ * Sets DFS low corner frequencies - low boundaries for DFS clocks when DFS.
+ * is running. If all DFS domains hit low corner, DFS will no longer wake
+ * CPU from low power state.  
+ *
+ * @note When CPU envelope is set via NvRmDfsSetCpuEnvelope() API the CPU
+ *  low corner boundary can not be changed by this function.
+ * @note When EMC envelope is set via NvRmDfsSetEmcEnvelope() API the EMC
+ *  low corner boundary can not be changed by this function.
+ * 
+ * Usage example:
+ * 
+ * NvError Error;
+ * NvRmFreqKHz LowCorner[NvRmDfsClockId_Num];
+ * 
+ * // Fill in low corner array
+ * LowCorner[NvRmDfsClockId_Cpu] = NvRmFreqUnspecified;
+ * LowCorner[NvRmDfsClockId_Avp] = ... ;
+ * LowCorner[NvRmDfsClockId_System] = ...;
+ * LowCorner[NvRmDfsClockId_Ahb] = ...;
+ * LowCorner[NvRmDfsClockId_Apb] = ...;
+ * LowCorner[NvRmDfsClockId_Vpipe] = ...;
+ * LowCorner[NvRmDfsClockId_Emc] = ...;
+ * 
+ * // Set new low corner for domains other than CPU, and preserve CPU boundary
+ * Error = NvRmDfsSetLowCorner(RmHandle, NvRmDfsClockId_Num, LowCorner);
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsFreqListCount Number of entries in the pDfsLowFreqList array.
+ *  Must be always equal to NvRmDfsClockId_Num.
+ * @param pDfsLowFreqList Pointer to a list of low corner frequencies, ordered
+ *  according to NvRmDfsClockId enumeration. If the list entry is set to
+ *  NvRmFreqUnspecified, the respective low corner boundary is not modified.
+ * 
+ * @retval NvSuccess if low corner frequencies were updated successfully.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsSetLowCorner( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 DfsFreqListCount,
+    const NvRmFreqKHz * pDfsLowFreqList );
+
+/**
+ * Sets DFS target frequencies. If DFS is stopped clocks for the DFS domains
+ * will be targeted with the specified frequencies. In any other DFS state
+ * this function has no effect.
+ *
+ * Usage example:
+ * 
+ * NvError Error;
+ * NvRmFreqKHz Target[NvRmDfsClockId_Num];
+ * 
+ * // Fill in target frequencies array
+ * Target[NvRmDfsClockId_Cpu] = ... ;
+ * Target[NvRmDfsClockId_Avp] = ... ;
+ * Target[NvRmDfsClockId_System] = ...;
+ * Target[NvRmDfsClockId_Ahb] = ...;
+ * Target[NvRmDfsClockId_Apb] = ...;
+ * Target[NvRmDfsClockId_Vpipe] = ...;
+ * Target[NvRmDfsClockId_Emc] = ...;
+ * 
+ * // Set new target
+ * Error = NvRmDfsSetTarget(RmHandle, NvRmDfsClockId_Num, Target);
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsFreqListCount Number of entries in the pDfsTargetFreqList array.
+ *  Must be always equal to NvRmDfsClockId_Num.
+ * @param pDfsTargetFreqList Pointer to a list of target frequencies, ordered
+ *  according to NvRmDfsClockId enumeration. If the list entry is set to
+ *  NvRmFreqUnspecified, the current domain frequency is used as a target.
+ * 
+ * @retval NvSuccess if target frequencies were updated successfully.
+ * @retval NvError_NotSupported if DFS is not stopped (disabled, or running).
+ */
+
+ NvError NvRmDfsSetTarget( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 DfsFreqListCount,
+    const NvRmFreqKHz * pDfsTargetFreqList );
+
+/**
+ * Sets DFS high and low boundaries for CPU domain clock frequency.
+ * 
+ * Usage example:
+ *
+ * NvError Error;
+ * 
+ * // Set CPU envelope boundaries to LowKHz : HighKHz
+ * Error = NvRmDfsSetCpuEnvelope(RmHandle, LowKHz, HighKHz);
+ * 
+ * // Change CPU envelope high boundary to HighKHz
+ * Error = NvRmDfsSetCpuEnvelope(RmHandle, NvRmFreqUnspecified, HighKHz);
+ *
+ * // Release CPU envelope back to HW limits
+ * Error = NvRmDfsSetCpuEnvelope(RmHandle, 0, NvRmFreqMaximum);
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsCpuEnvelopeLowKHz Requested low boundary in kHz.
+ * @param DfsCpuEnvelopeHighKHz Requested high limit in kHz.
+ * 
+ * Envelope parameters are clipped to the HW defined CPU domain range.
+ * If envelope parameter is set to NvRmFreqUnspecified, the respective
+ * CPU boundary is not modified, unless it violates the new setting for
+ * the other boundary; in the latter case both boundaries are set to the
+ * new specified value.
+ * 
+ * @retval NvSuccess if DFS envelope for for CPU domain was updated
+ *  successfully.
+ * @retval NvError_BadValue if reversed boundaries are specified.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsSetCpuEnvelope( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsCpuLowCornerKHz,
+    NvRmFreqKHz DfsCpuHighCornerKHz );
+
+/**
+ * Sets DFS high and low boundaries for EMC domain clock frequency.
+ * 
+ * Usage example:
+ *
+ * NvError Error;
+ * 
+ * // Set EMC envelope boundaries to LowKHz : HighKHz
+ * Error = NvRmDfsSetEmcEnvelope(RmHandle, LowKHz, HighKHz);
+ * 
+ * // Change EMC envelope high boundary to HighKHz
+ * Error = NvRmDfsSetEmcEnvelope(RmHandle, NvRmFreqUnspecified, HighKHz);
+ *
+ * // Release EMC envelope back to HW limits
+ * Error = NvRmDfsSetEmcEnvelope(RmHandle, 0, NvRmFreqMaximum);
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsEmcEnvelopeLowKHz Requested low boundary in kHz.
+ * @param DfsEmcEnvelopeHighKHz Requested high limit in kHz.
+ * 
+ * Envelope parameters are clipped to the ODM defined EMC configurations
+ * within HW defined EMC domain range. If envelope parameter is set to
+ * NvRmFreqUnspecified, the respective EMC boundary is not modified, unless
+ * it violates the new setting for the other boundary; in the latter case
+ * both boundaries are set to the new specified value.
+ * 
+ * @retval NvSuccess if DFS envelope for for EMC domain was updated
+ *  successfully.
+ * @retval NvError_BadValue if reversed boundaries are specified.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsSetEmcEnvelope( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsEmcLowCornerKHz,
+    NvRmFreqKHz DfsEmcHighCornerKHz );
+
+/**
+ * Sets DFS high boundaries for CPU and EMC.
+ * 
+ * @note When either CPU or EMC envelope is set via NvRmDfsSetXxxEnvelope()
+ * API, neither CPU nor EMC boundary is changed by this function.
+ * 
+ * Usage example:
+ *
+ * NvError Error;
+ * 
+ * // Set CPU subsystem clock limit to CpuHighKHz and Emc clock limit
+ * // to EmcHighKHz
+ * Error = NvRmDfsSetCpuEmcHighCorner(RmHandle, CpuHighKHz, EmcHighKHz);
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsCpuHighKHz Requested high boundary in kHz for CPU.
+ * @param DfsEmcHighKHz Requested high limit in kHz for EMC.
+ * 
+ * Requested parameters are clipped to the respective HW defined domain
+ * ranges, as well as to ODM defined EMC configurations. If any parameter
+ * is set to NvRmFreqUnspecified, the respective boundary is not modified.
+ * 
+ * @retval NvSuccess if high corner for AV subsystem was updated successfully.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsSetCpuEmcHighCorner( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsCpuHighKHz,
+    NvRmFreqKHz DfsEmcHighKHz );
+
+/**
+ * Sets DFS high boundaries for AV subsystem clocks.
+ * 
+ * Usage example:
+ *
+ * NvError Error;
+ * 
+ * // Set AVP clock limit to AvpHighKHz, Vde clock limit to VpipeHighKHz,
+ * // and preserve System bus clock limit provided it is above requested
+ * // AVP and Vpipe levels.
+ * Error = NvRmDfsSetAvHighCorner(
+ *          RmHandle, NvRmFreqUnspecified, AvpHighKHz, VpipeHighKHz);
+ * 
+ *@note System bus clock limit must be always above AvpHighKHz, and above
+ * VpipeHighKHz. Therefore it may be adjusted up, as a result of this call,
+ * even though, it is marked unspecified.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsSysHighKHz Requested high boundary in kHz for System bus.
+ * @param DfsAvpHighKHz Requested high boundary in kHz for AVP.
+ * @param DfsVdeHighCornerKHz Requested high limit in kHz for Vde pipe.
+ * 
+ * Requested parameter is clipped to the respective HW defined domain
+ * range. If  parameter is set to NvRmFreqUnspecified, the respective
+ * boundary is not modified.
+ * 
+ * @retval NvSuccess if high corner for AV subsystem was updated successfully.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsSetAvHighCorner( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmFreqKHz DfsSystemHighKHz,
+    NvRmFreqKHz DfsAvpHighKHz,
+    NvRmFreqKHz DfsVpipeHighKHz );
+
+/**
+ * Gets DFS profiling information.
+ * 
+ * DFS profiling starts/re-starts every time NvRmDfsRunState_ProfiledLoop
+ * state is set via NvRmDfsSetState(). DFS profiling stops when any other
+ * sate is set.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param DfsProfileCount Number of DFS profiles. Must be always equal to
+ *  NvRmDfsProfileId_Num.
+ * @param pSamplesNoList Output storage pointer to an array of sample counts
+ *  for each profile target ordered according to NvRmDfsProfileId enumeration.
+ * @param pProfileTimeUsList Output storage pointer to an array of cummulative
+ *  execution time in microseconds for each profile target ordered according
+ *  to NvRmDfsProfileId enumeration.
+ * @param pDfsPeriodUs Output storage pointer for average DFS sample
+ *  period in microseconds.
+ * 
+ * @retval NvSuccess if profile information is returned successfully.
+ * @retval NvError_NotSupported if DFS is not ruuning in profiled loop.
+ */
+
+ NvError NvRmDfsGetProfileData( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 DfsProfileCount,
+    NvU32 * pSamplesNoList,
+    NvU32 * pProfileTimeUsList,
+    NvU32 * pDfsPeriodUs );
+
+/**
+ * Starts/Re-starts NV DFS logging.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ */
+
+ void NvRmDfsLogStart( 
+    NvRmDeviceHandle hRmDeviceHandle );
+
+/**
+ * Stops DFS logging and gets cumulative mean values of DFS domains frequencies
+ *  over logging time.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param LogMeanFreqListCount Number of entries in the pLogMeanFreqList array.
+ *  Must be always equal to NvRmDfsClockId_Num.
+ * @param pLogMeanFreqList Pointer to a list filled with mean values of DFS
+ *  frequencies, ordered according to NvRmDfsClockId enumeration.
+ * @param pLogLp2TimeMs Pointer to a variable filled with cumulative time spent
+ *  in LP2 in milliseconds.
+ * @param pLogLp2Entries Pointer to a variable filled with cumulative number of
+ *  LP2 mode entries.
+ * 
+ * @retval NvSuccess if mean values are returned successfully.
+ * @retval NvError_NotSupported if DFS is disabled.
+ */
+
+ NvError NvRmDfsLogGetMeanFrequencies( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 LogMeanFreqListCount,
+    NvRmFreqKHz * pLogMeanFreqList,
+    NvU32 * pLogLp2TimeMs,
+    NvU32 * pLogLp2Entries );
+
+/**
+ * Gets specified entry of the detailed DFS activity log.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param EntryIndex Log entrty index.
+ * @param LogDomainsCount The size of activity arrays.
+ *  Must be always equal to NvRmDfsClockId_Num.
+ * @param pIntervalMs Pointer to a variable filled with sample interval time
+ *  in milliseconds.
+ * @param pLp2TimeMs Pointer to a variable filled with time spent in LP2
+ *  in milliseconds.
+ * @param pActiveCyclesList Pointer to a list filled with domain active cycles
+ *  within sample interval.
+ * @param pAveragesList Pointer to a list filled with average domain activity
+ *  over DFS moving window.
+ * @param pFrequenciesList Pointer to a list filled with instantaneous domains
+ *  frequencies.
+ *  All lists are ordered according to NvRmDfsClockId enumeration.
+ * 
+ * @retval NvSuccess if log entry is retrieved successfully.
+ * @retval NvError_InvalidAddress if requetsed entry is empty.
+ * @retval NvError_NotSupported if DFS is disabled, or detailed logging
+ *  is not supported.
+ */
+
+ NvError NvRmDfsLogActivityGetEntry( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 EntryIndex,
+    NvU32 LogDomainsCount,
+    NvU32 * pIntervalMs,
+    NvU32 * pLp2TimeMs,
+    NvU32 * pActiveCyclesList,
+    NvRmFreqKHz * pAveragesList,
+    NvRmFreqKHz * pFrequenciesList );
+
+/**
+ * Gets specified entry of the detailed DFS starvation hints log.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param EntryIndex Log entrty index.
+ * @param pSampleIndex Pointer to a variable filled with sample interval
+ *  index in the activity log when this hint is associated with.
+ * @param pStarvationHint Pointer to a variable filled with starvation
+ *  hint record.
+ * 
+ * @retval NvSuccess if next entry is retrieved successfully.
+ * @retval NvError_InvalidAddress if requetsed entry is empty.
+ * @retval NvError_NotSupported if DFS is disabled, or detailed logging
+ *  is not supported.
+ */
+
+ NvError NvRmDfsLogStarvationGetEntry( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 EntryIndex,
+    NvU32 * pSampleIndex,
+    NvU32 * pClientId,
+    NvU32 * pClientTag,
+    NvRmDfsStarvationHint * pStarvationHint );
+
+/**
+ * Gets specified entry of the detailed DFS busy hints log.
+ *
+ * @param hRmDeviceHandle The RM device handle.
+ * @param EntryIndex Log entrty index.
+ * @param pSampleIndex Pointer to a variable filled with sample interval
+ *  index in the activity log when this hint is associated with.
+ * @param pBusyHint Pointer to a variable filled with busy
+ *  hint record.
+ * 
+ * @retval NvSuccess if next entry is retrieved successfully.
+ * @retval NvError_InvalidAddress if requetsed entry is empty.
+ * @retval NvError_NotSupported if DFS is disabled, or detailed logging
+ *  is not supported.
+ */
+
+ NvError NvRmDfsLogBusyGetEntry( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 EntryIndex,
+    NvU32 * pSampleIndex,
+    NvU32 * pClientId,
+    NvU32 * pClientTag,
+    NvRmDfsBusyHint * pBusyHint );
+
+/**
+ * Gets low threshold and present voltage on the given rail.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param RailId The targeted voltage rail ID.
+ * @param pLowMv Output storage pointer for low voltage threshold (in 
+ *  millivolt). NvRmVoltsUnspecified is returned if targeted rail does
+ *  not exist on SoC.
+ * @param pPresentMv Output storage pointer for present rail voltage (in 
+ *  millivolt). NvRmVoltsUnspecified is returned if targeted rail does
+ *  not exist on SoC.
+ */
+
+ void NvRmDfsGetLowVoltageThreshold( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsVoltageRailId RailId,
+    NvRmMilliVolts * pLowMv,
+    NvRmMilliVolts * pPresentMv );
+
+/**
+ * Sets low threshold for the given rail. The actual rail voltage is scaled
+ *  to match SoC clock frequencies, but not below the specified threshold.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param RailId The targeted voltage rail ID.
+ * @param LowMv Low voltage threshold (in millivolts) for the targeted rail.
+ *  Ignored if targeted rail does not exist on SoC.
+ */
+
+ void NvRmDfsSetLowVoltageThreshold( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmDfsVoltageRailId RailId,
+    NvRmMilliVolts LowMv );
+
+/**
+ * Notifies RM Kernel about entering Suspend state.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ *
+ * @retval NvSuccess if notifying RM entering Suspend state successfully.
+ */
+
+ NvError NvRmKernelPowerSuspend( 
+    NvRmDeviceHandle hRmDeviceHandle );
+
+/**
+ * Notifies RM kernel about entering Resume state.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ *
+ * @retval NvSuccess if notifying RM entering Resume state successfully.
+ */
+
+ NvError NvRmKernelPowerResume( 
+    NvRmDeviceHandle hRmDeviceHandle );
+
+/** @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_power_private.h b/arch/arm/mach-tegra/nv/include/nvrm_power_private.h
new file mode 100644
index 000000000000..87a6ca6ef69b
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_power_private.h
@@ -0,0 +1,588 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_POWER_PRIVATE_H
+#define INCLUDED_NVRM_POWER_PRIVATE_H
+
+#include "nvrm_power.h"
+#include "nvodm_query.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// Power detect cell stabilization delay
+#define NVRM_PWR_DET_DELAY_US (3)
+
+// Minimum DFS clock domain busy time and busy hints list purge time
+#define NVRM_DFS_BUSY_MIN_MS (10)
+#define NVRM_DFS_BUSY_PURGE_MS (500)
+
+// Temporary definitions for AP20 bring up
+#define NVRM_POWER_AP20_BRINGUP_RETURN(hRm, cond) \
+    if (((hRm)->ChipId.Id == 0x20) && ((cond))) \
+        return
+
+/**
+ * Defines the DFS status flags used by OS kernel to configure SoC for
+ * low power state (multiple flags can be OR'ed).
+ */
+typedef enum
+{
+    // Pause DFS during low power state
+    NvRmDfsStatusFlags_Pause = 0x01,
+
+    // Stop PLL during low power state
+    NvRmDfsStatusFlags_StopPllM0 = 0x02,
+    NvRmDfsStatusFlags_StopPllC0 = 0x04,
+    NvRmDfsStatusFlags_StopPllP0 = 0x08,
+    NvRmDfsStatusFlags_StopPllA0 = 0x10,
+    NvRmDfsStatusFlags_StopPllD0 = 0x20,
+    NvRmDfsStatusFlags_StopPllU0 = 0x40,
+    NvRmDfsStatusFlags_StopPllX0 = 0x80,
+
+    NvRmDfsStatusFlags_Force32 = 0x7FFFFFFF
+} NvRmDfsStatusFlags;
+
+// Defines maximum number of CPUs (must be power of 2)
+#define NVRM_MAX_NUM_CPU_LOG2 (8)
+
+/**
+ * Defines RM power manager requests to OS kernel
+ */
+typedef enum
+{
+    NvRmPmRequest_None = 0,
+
+    // The CPU number is interpreted based on the request flag it is
+    // combined (ORed) with
+    NvRmPmRequest_CpuNumMask = (0x1 << NVRM_MAX_NUM_CPU_LOG2) - 1,
+
+    // Request to abort RM power manager (CPU number is ignored)
+    NvRmPmRequest_ExitFlag,
+
+    // Request to turn On/Off CPU (CPU number specifies target
+    // CPU within current CPU cluster)
+    NvRmPmRequest_CpuOnFlag = NvRmPmRequest_ExitFlag << 1,
+    NvRmPmRequest_CpuOffFlag = NvRmPmRequest_CpuOnFlag << 1,
+
+    // Request to switch between CPU clusters (CPU number specifies target
+    // CPU cluster)
+    NvRmPmRequest_CpuClusterSwitchFlag = NvRmPmRequest_CpuOffFlag << 1,
+
+    NvRmPmRequest_Force32 = 0x7FFFFFFF
+} NvRmPmRequest;
+
+/**
+ * NVRM PM function called within OS shim high priority thread
+ */
+NvRmPmRequest NvRmPrivPmThread(void);
+
+/**
+ * Sets combined RM clients power state in the storage shared with OS
+ * adaptation layer (OAL). While the system is running RM power manger
+ * calls this function to specify idle or active state based on client
+ * requests. On entry to system low power state OAL calls this function
+ * to store the respective LPx id.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param RmState The overall power state to be set
+ */
+void
+NvRmPrivPowerSetState(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPowerState RmState);
+
+/**
+ * Reads combined RM clients power state from the storage shared with OS
+ * adaptation layer (OAL). While the system is running both RM and OAL may
+ * call this function to read the power state. On exit from the system low
+ * power state OAL uses this function to find out which LPx state is exited.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return RM power state
+ */
+NvRmPowerState
+NvRmPrivPowerGetState(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Updates DFS pause flag in the storage shared by RM and NV boot loader
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Pause If NV_TRUE, set DFS pause flag,
+ *  if NV_FALSE, clear DFS pause flag
+ *
+ */
+void
+NvRmPrivUpdateDfsPauseFlag(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvBool Pause);
+
+/**
+ * Reads DFS status flags from the storage shared by RM and NV boot loader.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return DFS status flags as defined @NvRmDfsStatusFlags
+ */
+NvU32
+NvRmPrivGetDfsFlags(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Sets download transport in the storage shared by RM and NV boot loader
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param Transport current download transport (NvOdmDownloadTransport_None
+ *  if no transport or it is not active)
+ */
+void
+NvRmPrivSetDownloadTransport(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvOdmDownloadTransport Transport);
+
+/**
+ * Reads download transport from the storage shared by RM and NV boot loader.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return current download transport (NvOdmDownloadTransport_None
+ *  if no transport or it is not active)
+ */
+NvOdmDownloadTransport
+NvRmPrivGetDownloadTransport(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Save LP2 time in the storage shared by RM and NV boot loader.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param TimeUS Time in microseconds CPU was in LP2 state (power gated)
+ */
+void
+NvRmPrivSetLp2TimeUS(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 TimeUS);
+
+/**
+ * Reads LP2 time from the storage shared by RM and NV boot loader.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return Time in microseconds CPU was in LP2 state (power gated)
+ */
+NvU32
+NvRmPrivGetLp2TimeUS(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Initializes RM access to the storage shared by RM and NV boot loader
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return NvSuccess if initialization completed successfully
+ * or one of common error codes on failure
+ */
+NvError NvRmPrivOalIntfInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Deinitializes RM access to the storage shared by RM and NV boot loader
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivOalIntfDeinit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Initializes RM DFS manager
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return NvSuccess if initialization completed successfully
+ * or one of common error codes on failure
+ */
+NvError NvRmPrivDfsInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Deinitializes RM DFS manager
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivDfsDeinit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Initializes RM DTT manager
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivDttInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Deinitializes RM DTT manager
+ */
+void NvRmPrivDttDeinit(void);
+
+/**
+ * Initializes RM power manager
+ *
+ * @param hRmDeviceHandle The RM device handle
+ *
+ * @return NvSuccess if initialization completed successfully
+ * or one of common error codes on failure
+ */
+NvError
+NvRmPrivPowerInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Deinitializes RM power manager
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void
+NvRmPrivPowerDeinit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Initializes IO power rails control
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivIoPowerControlInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Starts IO power rails level detection
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param PwrDetMask The bit mask of power detection cells to be activated
+ */
+void NvRmPrivIoPowerDetectStart(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PwrDetMask);
+
+/**
+ * Resets enabled power detect cells (chip-specific).
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivAp15IoPowerDetectReset(NvRmDeviceHandle hRmDeviceHandle);
+void NvRmPrivAp20IoPowerDetectReset(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Latches the results of IO power rails level detection
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivIoPowerDetectLatch(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Enables/Disables IO pads on specified power rails
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param NoIoPwrMask Bit mask of affected power rails
+ * @param Enable Set NV_TRUE to enable IO pads, or NV_FALSE to disable.
+ */
+void NvRmPrivIoPowerControl(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 NoIoPwrMask,
+    NvBool Enable);
+
+/**
+ * Configures SoC power rail controls for the upcoming PMU voltage transition.
+ *
+ * @note Should be called just before PMU rail On/Off, or Off/On transition.
+ *  Should not be called if rail voltage level is changing within On range.
+ *
+ * @param hDevice The Rm device handle.
+ * @param PmuRailAddress PMU address (id) for targeted power rail.
+ * @param Enable Set NV_TRUE if target voltage is about to be turned On, or
+ *  NV_FALSE if target voltage is about to be turned Off.
+ * @param pIoPwrDetectMask A pointer to a variable filled with the bit mask
+ *  of activated IO power detection cells to be latched by the caller after
+ *  Off/On transition (set to 0 for On/Off transition).
+ * @param pNoIoPwrMask A pointer to a variable filled with the bit mask of IO
+ *  power pads to be enabled by the caller after Off/On transition (set to 0
+ *  for On/Off transition).
+ */
+void
+NvRmPrivSetSocRailPowerState(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PmuRailAddress,
+    NvBool Enable,
+    NvU32* pIoPwrDetectMask,
+    NvU32* pNoIoPwrMask);
+
+/**
+ * Initializes core SoC power rail.
+ *
+ * @param hDevice The Rm device handle.
+ */
+void NvRmPrivCoreVoltageInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Request nominal core (and rtc) voltage.
+ *
+ * @param hRmDeviceHandle The RM device handle
+ */
+void
+NvRmPrivSetNominalCoreVoltage(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Initializes power group control table (chip-specific)
+ * 
+ * @param pPowerGroupIdsTable 
+ * @param pPowerGroupIdsTable A pointer to a pointer which this function sets
+ *  to the chip specific map between power group number and power gate ID. 
+ * @param pPowerGroupIdsTableSize A pointer to a variable which this function
+ *  sets to the power group IDs table size.
+ * 
+ */
+void
+NvRmPrivAp15PowerGroupTableInit(
+    const NvU32** pPowerGroupIdsTable,
+    NvU32* pPowerGroupIdsTableSize);
+
+void
+NvRmPrivAp20PowerGroupTableInit(
+    const NvU32** pPowerGroupIdsTable,
+    NvU32* pPowerGroupIdsTableSize);
+
+/**
+ * Initializes power group control.
+ * 
+ * @param hRmDeviceHandle The RM device handle
+ */
+void NvRmPrivPowerGroupControlInit(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Enables/disables power for the specified power group
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param PowerGroup targeted power group
+ * @param Enable If NV_TRUE, enable power to the specified power group,
+ *  if NV_FALSE, disable power (power gate) the specified power group
+ */
+void
+NvRmPrivPowerGroupControl(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PowerGroup,
+    NvBool Enable);
+
+/**
+ * Retrieves given power group voltage
+ *
+ * @param hRmDeviceHandle The RM device handle
+ * @param PowerGroup targeted power group
+ *
+ * @return NvRmVoltsUnspecified if power group is On,
+ *  and NvRmVoltsOff if it is power gated
+ */
+NvRmMilliVolts
+NvRmPrivPowerGroupGetVoltage(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvU32 PowerGroup);
+
+/**
+ * Controls power state and clamping for PCIEXCLK/PLLE (chip-specific).
+ *
+ * @param hRmDevice The RM device handle.
+ * @param Enable If NV_TRUE, power up PCIEXCLK and remove clamps,
+ *  if NV_FALSE, power down PCIEXCLK  and set clamps.
+ */
+void
+NvRmPrivAp20PowerPcieXclkControl(
+    NvRmDeviceHandle hRmDevice,
+    NvBool Enable);
+
+/**
+ * Verifies if the specified DFS clock domain is starving.
+ *
+ * @param ClockId The DFS ID of the clock domain to be checked.
+ *
+ * @retval NV_TRUE if domain is starving
+ * @retval NV_FALSE if domain is not starving
+ */
+NvBool NvRmPrivDfsIsStarving(NvRmDfsClockId ClockId);
+
+/**
+ * Gets current busy boost frequency and pulse mode requested for the
+ *  specified DFS clock domain.
+ *
+ * @param ClockId The DFS ID of the targeted clock domain.
+ * @param pBusyKHz A pointer to a variable filled with boost frequency in kHz.
+ * @param pBusyKHz A pointer to a variable filled with pulse mode indicator.
+ * @param pBusyExpireMs A pointer to a variable filled with busy boost
+ *  expiration interval in ms.
+ */
+void NvRmPrivDfsGetBusyHint(
+    NvRmDfsClockId ClockId,
+    NvRmFreqKHz* pBusyKHz,
+    NvBool* pBusyPulseMode,
+    NvU32* pBusyExpireMs);
+
+/**
+ * Gets maximum frequency for the specified DFS clock domain.
+ *
+ * @param ClockId The DFS ID of the targeted clock domain.
+ *
+ * @return Maximum domain frequency in kHz
+ */
+NvRmFreqKHz NvRmPrivDfsGetMaxKHz(NvRmDfsClockId ClockId);
+
+/**
+ * Gets minimum frequency for the specified DFS clock domain.
+ *
+ * @param ClockId The DFS ID of the targeted clock domain.
+ *
+ * @return Minimum domain frequency in kHz
+ */
+NvRmFreqKHz NvRmPrivDfsGetMinKHz(NvRmDfsClockId ClockId);
+
+/**
+ * Gets current frequency for the specified DFS clock domain.
+ *
+ * @param ClockId The DFS ID of the targeted clock domain.
+ *
+ * @return Current domain frequency in kHz
+ */
+NvRmFreqKHz NvRmPrivDfsGetCurrentKHz(NvRmDfsClockId ClockId);
+
+/**
+ * Signals DFS clock control thread
+ * 
+ * @param Mode Synchronization mode. In synchronous mode this function returns
+ *  to the caller after DFS clock control procedure is executed (blocking call).
+ *  In asynchronous mode returns immediately after control thread is signaled.
+ */
+void NvRmPrivDfsSignal(NvRmDfsBusyHintSyncMode Mode);
+
+/**
+ * Synchronize DFS samplers with current clock frequencies
+ */
+void NvRmPrivDfsResync(void);
+
+/**
+ * Gets DFS ready for low power state entry.
+ *
+ * @param state Target low power state.
+ *
+ */
+void NvRmPrivDfsSuspend(NvOdmSocPowerState state);
+
+/**
+ * Restore clock sources after exit from low power state.
+ *
+ * @param hRmDevice The RM device handle.
+ */
+void
+NvRmPrivClocksResume(NvRmDeviceHandle hRmDevice);
+
+
+/**
+ * Initializes DVS settings
+ */
+void NvRmPrivDvsInit(void);
+
+/**
+ * Scales core voltage according to DFS controlled clock frequencies.
+ *
+ * @param BeforeFreqChange Indicates whether this function is called
+ *  before (NV_TRUE) or after (NV_FALSE) frequency change.
+ * @param CpuMv Core voltage in mV required to run CPU at clock source
+ *  frequency selected by DFS.
+ * @param SystemMv Core voltage in mV required to run AVP/System at clock
+ *  source frequency selected by DFS.
+ * @param EmcMv Core voltage in mV required to run EMC/DDR at clock source
+ *  frequency selected by DFS.
+ */
+void NvRmPrivVoltageScale(
+    NvBool BeforeFreqChange,
+    NvRmMilliVolts CpuMv,
+    NvRmMilliVolts SystemMv,
+    NvRmMilliVolts EmcMv);
+
+/**
+ * Requests core voltage update.
+ *
+ * @param TargetMv Requested core voltage level in mV.
+ */
+void NvRmPrivDvsRequest(NvRmMilliVolts TargetMv);
+
+/**
+ * Gets low threshold and present voltage on the given rail.
+ *
+ * @param RailId The targeted voltage rail ID.
+ * @param pLowMv Output storage pointer for low voltage threshold (in
+ *  millivolt).
+ * @param pPresentMv Output storage pointer for present rail voltage (in
+ *  millivolt). This parameter is optional, set to NULL if only low
+ *  threshold is to be retrieved.
+ *
+ *  NvRmVoltsUnspecified is returned if targeted rail does not exist on SoC.
+ */
+void
+NvRmPrivGetLowVoltageThreshold(
+    NvRmDfsVoltageRailId RailId,
+    NvRmMilliVolts* pLowMv,
+    NvRmMilliVolts* pPresentMv);
+
+/**
+ * Outputs debug messages for starvation hints sent by the specified client.
+ *
+ * @param ClientId The client ID assigned by the RM power manager.
+ * @param ClientTag The client tag reported to the RM power manager.
+ * @param pMultiHint Pointer to a list of starvation hints sent by the client.
+ * @param NumHints Number of entries in the pMultiHint list.
+ *
+ */
+void NvRmPrivStarvationHintPrintf(
+    NvU32 ClientId,
+    NvU32 ClientTag,
+    const NvRmDfsStarvationHint* pMultiHint,
+    NvU32 NumHints);
+
+/**
+ * Outputs debug messages for busy hints sent by the specified client.
+ *
+ * @param ClientId The client ID assigned by the RM power manager.
+ * @param ClientTag The client tag reported to the RM power manager.
+ * @param pMultiHint Pointer to a list of busy hints sent by the client.
+ * @param NumHints Number of entries in the pMultiHint list.
+ *
+ */
+void NvRmPrivBusyHintPrintf(
+    NvU32 ClientId,
+    NvU32 ClientTag,
+    const NvRmDfsBusyHint* pMultiHint,
+    NvU32 NumHints);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_POWER_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_pwm.h b/arch/arm/mach-tegra/nv/include/nvrm_pwm.h
new file mode 100644
index 000000000000..d1011dc77439
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_pwm.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_pwm_H
+#define INCLUDED_nvrm_pwm_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_pinmux.h"
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvos.h"
+#include "nvcommon.h"
+
+/**
+ * NvRmPwmHandle is an opaque handle to the NvRmPwmStructRec interface
+ */
+ 
+typedef struct NvRmPwmRec *NvRmPwmHandle;
+
+/**
+ * Defines possible PWM modes.
+ */
+
+typedef enum
+{
+
+    /// Specifies Pwm disable mode
+        NvRmPwmMode_Disable = 1,
+
+    /// Specifies Pwm enable mode
+        NvRmPwmMode_Enable,
+
+    /// Specifies Blink LED enabled mode
+        NvRmPwmMode_Blink_LED,
+
+    /// Specifies Blink output 32KHz clock enable mode
+        NvRmPwmMode_Blink_32KHzClockOutput,
+
+    /// Specifies Blink disabled mode
+        NvRmPwmMode_Blink_Disable,
+    NvRmPwmMode_Num,
+    NvRmPwmMode_Force32 = 0x7FFFFFFF
+} NvRmPwmMode;
+
+/**
+ * Defines the possible PWM output pin
+ */
+
+typedef enum
+{
+
+    /// Specifies PWM Output-0
+        NvRmPwmOutputId_PWM0 = 1,
+
+    /// Specifies PWM Output-1
+        NvRmPwmOutputId_PWM1,
+
+    /// Specifies PWM Output-2
+        NvRmPwmOutputId_PWM2,
+
+    /// Specifies PWM Output-3
+        NvRmPwmOutputId_PWM3,
+
+    /// Specifies PMC Blink LED
+        NvRmPwmOutputId_Blink,
+    NvRmPwmOutputId_Num,
+    NvRmPwmOutputId_Force32 = 0x7FFFFFFF
+} NvRmPwmOutputId;
+
+/**
+ * @brief Initializes and opens the pwm channel. This function allocates the
+ * handle for the pwm channel and provides it to the client.
+ *
+ * Assert encountered in debug mode if passed parameter is invalid.
+ *
+ * @param hDevice Handle to the Rm device which is required by Rm to acquire
+ *  the resources from RM.
+ * @param phPwm Points to the location where the Pwm handle shall be stored.
+ *
+ * @retval NvSuccess Indicates that the Pwm channel has successfully opened.
+ * @retval NvError_InsufficientMemory Indicates that function fails to allocate
+ *  the memory.
+ * @retval NvError_NotInitialized Indicates the Pwm initialization failed.
+ */
+
+ NvError NvRmPwmOpen( 
+    NvRmDeviceHandle hDevice,
+    NvRmPwmHandle * phPwm );
+
+/** 
+ * @brief Closes the Pwm channel. This function frees the memory allocated for
+ *  the pwm handle for the pwm channel.
+ *  This function de-initializes the pwm channel. This API never fails.
+ *
+ * @param hPwm A handle from NvRmPwmOpen().  If hPwm is NULL, this API does
+ *     nothing.
+ */
+
+ void NvRmPwmClose( 
+    NvRmPwmHandle hPwm );
+
+/** 
+ * @brief Configure PWM module as disable/enable. Also, it is used
+ *  to set the PWM duty cycle and frequency. Beside that, it is 
+ *  used to configure PMC' blinking LED if OutputId is NvRmPwmOutputId_Blink
+ *
+ * @param hPwm Handle to the PWM channel.
+ * * @param OutputId The output pin to config. Allowed OutputId values are
+ *   defined in ::NvRmPwmOutputId
+ * @param Mode The mode type to config. Allowed mode values are
+ *   defined in ::NvRmPwmMode
+ * @param DutyCycle The duty cycle is an unsigned 15.16 fixed point
+ *   value that represents PWM duty cycle in percentage range from
+ *   0.00 to 100.00. For example, 10.5 percentage duty cycle would be
+ *   represented as 0x000A8000. This parameter is ignored if NvRmPwmMode
+ *   is NvRmPwmMode_Blink_32KHzClockOutput or NvRmPwmMode_Blink_Disable
+ * @param RequestedFreqHzOrPeriod The requested frequency in Hz or Period
+ *  A requested frequency value beyond the max supported value will be
+ *  clamped to the max supported value.
+ *  If PMC Blink LED is used, this parameter is represented as
+ *  request period time in second unit. This parameter is ignored if 
+ *  NvRmPwmMode is NvRmPwmMode_Blink_32KHzClockOutput or 
+ *  NvRmPwmMode_Blink_Disable
+ *
+ * @param pCurrentFreqHzOrPeriod Pointer to the returns frequency of 
+ *  that mode. If PMC Blink LED is used then it is the pointer to 
+ *  the returns period time. This parameter is ignored if NvRmPwmMode
+ *  is NvRmPwmMode_Blink_32KHzClockOutput or NvRmPwmMode_Blink_Disable
+ *
+ * @retval NvSuccess Indicates the configuration succeeded.
+ */
+
+ NvError NvRmPwmConfig( 
+    NvRmPwmHandle hPwm,
+    NvRmPwmOutputId OutputId,
+    NvRmPwmMode Mode,
+    NvU32 DutyCycle,
+    NvU32 RequestedFreqHzOrPeriod,
+    NvU32 * pCurrentFreqHzOrPeriod );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_rmctrace.h b/arch/arm/mach-tegra/nv/include/nvrm_rmctrace.h
new file mode 100644
index 000000000000..22a9eb45eb71
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_rmctrace.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_RMCTRACE_H
+#define INCLUDED_NVRM_RMCTRACE_H
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_init.h"
+
+/**
+ * RMC is a file format for capturing accesses to hardware, both memory
+ * and register, that may be played back against a simulator.  Drivers
+ * are expected to emit RMC tracing if RMC tracing is enabled.
+ *
+ * The RM will already have an RMC file open before any drivers are expected
+ * to access it, so it is not necessary for NvRmRmcOpen or Close to be called
+ * by anyone except the RM itself (but drivers may want to if capturing a
+ * subset of commands is useful).
+ */
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+#if !defined(NV_OAL)
+#define NV_OAL 0
+#endif
+
+// FIXME: better rmc compile time macros
+#if !defined(NV_DEF_RMC_TRACE)
+#if NV_DEBUG && !NV_OAL
+#define NV_DEF_RMC_TRACE 1
+#else
+#define NV_DEF_RMC_TRACE 0
+#endif
+#endif
+
+/**
+ * exposed structure for RMC files.
+ */
+typedef struct NvRmRMCFile_t
+{
+    NvOsFileHandle file;
+    NvBool enable; /* enable bit for writes */
+} NvRmRmcFile;
+
+/**
+ * opens the an RMC file.
+ *
+ * @param name The name of the rmc file
+ * @param rmc Out param - the opened rmc file (if successful)
+ *
+ * NvOsFile* operatations should not be used directly since RMC commands
+ * or comments may be emited to the file on open/close/etc.
+ */
+NvError
+NvRmRmcOpen( const char *name, NvRmRmcFile *rmc );
+
+/**
+ * closes an RMC file.
+ *
+ * @param rmc The rmc file to close.
+ */
+void
+NvRmRmcClose( NvRmRmcFile *rmc );
+
+/**
+ * emits a string to the RMC file.
+ *
+ * @param file The RMC file
+ * @param format Printf style argument format string
+ *
+ * NvRmRmcOpen must be called before this function.
+ *
+ * This function should be called via a macro so that it may be compiled out.
+ * Note that double parens will be needed:
+ *
+ *     NVRM_RMC_TRACE(( file, "# filling memory with stuff\n" ));
+ */
+void
+NvRmRmcTrace( NvRmRmcFile *rmc, const char *format, ... );
+
+/**
+ * retrieves the RM's global RMC file.
+ *
+ * @param hDevice The RM instance
+ * @param file Output param: the RMC file
+ */
+NvError
+NvRmGetRmcFile( NvRmDeviceHandle hDevice, NvRmRmcFile **file );
+
+#if NV_DEF_RMC_TRACE
+#define NVRM_RMC_TRACE(a) NvRmRmcTrace a
+/**
+ * enable or disable RMC tracing at runtime.
+ *
+ * @param file The RMC file
+ * @param enable Either enable or disable rmc tracing
+ */
+#define NVRM_RMC_ENABLE(f, e) \
+    ((f)->enable = (e))
+
+#define NVRM_RMC_IS_ENABLED(f) \
+    ((f)->enable != 0)
+
+#else
+#define NVRM_RMC_TRACE(a) (void)0
+#define NVRM_RMC_ENABLE(f,e) (void)0
+#define NVRM_RMC_IS_ENABLED(f) (void)0
+#endif
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif /* NVRM_RMCTRACE_H */
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_spi.h b/arch/arm/mach-tegra/nv/include/nvrm_spi.h
new file mode 100644
index 000000000000..e5bee1e1bd1c
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_spi.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_spi_H
+#define INCLUDED_nvrm_spi_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_pinmux.h"
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvcommon.h"
+
+/**
+ * NvRmSpiHandle is an opaque context to the NvRmSpiRec interface.
+ */
+
+typedef struct NvRmSpiRec *NvRmSpiHandle;
+
+/**
+ * Open the handle for the spi/sflash controller. This api initalise the 
+ * sflash/spi controller.
+ * The Instance Id for the sflash and spi controller start from 0.
+ * The handle for the spi/sflash is open in master and slave mode based on the
+ * parameter passed. If the spi handle is opened in master mode the the SPICLK
+ * is generated from the spi controller and it acts like a master for all the 
+ * transaction.
+ *
+ * If the spi handle is opened in master mode then the controller can be shared 
+ * between different chip select client but if the spi handle is created in the 
+ * slave mode then it can not be shared by other client and only one client is
+ * allowed to open the spi handle for the slave mode.
+ *
+ * Assert encountered in debug mode if invalid parameter passed.
+ *
+ * @param hRmDevice Handle to the Rm device.
+ * @param IoModule The Rm IO module to set whether this is the 
+ * NvOdmIoModule_Sflash or NvOdmIoModule_Slink or NvOdmIoModule_Spi.
+ * @param InstanceId  The Instance Id which starts from the 0.
+ * @param IsMasterMode  Tells whether the controller will be open in master mode
+ * or the slave mode?
+ * @param phRmSpi  Pointer to the sflash/spi handle where the allocated handle 
+ * will be stored.
+ *
+ * @retval NvSuccess Indicates the function is successfully completed
+ * @retval NvError_MemoryMappingFail Indicates the address mapping of the
+ * register failed.
+ * @retval NvError_InsufficientMemory Indicates that memory allocation is
+ * failed.
+ * @retval NvError_NotSupported Indicases that the spi is not supported.
+ * @retval NvError_AlreadyAllocated Indicases that the spi handle is already 
+ * allocated to the other slave client.
+ */
+
+ NvError NvRmSpiOpen( 
+    NvRmDeviceHandle hRmDevice,
+    NvU32 IoModule,
+    NvU32 InstanceId,
+    NvBool IsMasterMode,
+    NvRmSpiHandle * phRmSpi );
+
+/**
+ * Deinitialize the spi controller, disable the clock and release the spi
+ * handle.
+ *
+ * @param hRmSpi A handle from NvRmSpiOpen().  If hRmSpi is NULL, this API does
+ *     nothing.
+ */
+
+ void NvRmSpiClose( 
+    NvRmSpiHandle hRmSpi );
+
+/**
+ * Performs an Spi controller read and write simultaneously in master mode. 
+ * This apis is only supported if the handle is open in master mode.
+ *
+ * Every Spi transaction is by definition a simultaneous read and write transaction, so 
+ * there are no separate APIs for read versus write. However, if you only need 
+ * to do a read or write, this API allows you to declare that you are not 
+ * interested in the read data, or that the write data is not of interest.
+ * If only read is required then client can pass the NULL pointer to the 
+ * pWriteBuffer. Zeros will be sent in this case.
+ * Similarly, if client wants to send data only then he can pass the 
+ * pReadBuffer as NULL.
+ * If Read and write is required and he wants to first send the command and 
+ * then want to read the response, then he need to send both the valid pointer
+ * read and write. In this case the bytesRequested will be the sum of the
+ * send command size and response size. The size of the pReadBuffer and 
+ * pWriteBuffer should be equal to the bytes requetsed.
+ * E.g. Client want to send the 4byte command first and the wants to read the
+ * 4 byte response, then he need a 8 byte pWriteBuffer and 8 byte pReadBuffer.
+ * He will fill the first 4 byte of pWriteBuffer with the command which he
+ * wants to send. After calling this api, he needs to ignore the first 4 bytes
+ * and use the next 4 byte as valid response data in the pReadBuffer.
+ *
+ * This is a blocking API. It will returns when all the data has been transferred
+ * over the pins of the SOC (the transaction).
+ *
+ * Several Spi transactions may be performed in a single call to this API, but
+ * only if all of the transactions are to the same chip select and have the same
+ * packet size.
+ *
+ * Transaction sizes from 1 to 32 bits are supported. However, all of the 
+ * packets are byte-aligned in memory. Like, if packetBitLength is 12 bit 
+ * then client needs the 2 byte for the 1 packet. New packets start from the
+ * new bytes e.g. byte0 and byte1 contain the first packet and byte2 and byte3
+ * will contain the second packets.
+ *
+ * To perform one transaction, the BytesRequested argument should be:
+ *
+ *   (PacketSizeInBits + 7)/8
+ *
+ * To perform n transactions, BytesRequested should be:
+ *
+ *   n*((PacketSizeInBits + 7)/8)
+ *
+ * Within a given
+ * transaction with the packet size larger than 8 bits, the bytes are stored in 
+ * order of the MSB (most significant byte) first.
+ * The Packet is formed with the first Byte will be in MSB and then next byte 
+ * will be in the  next MSB towards the LSB.
+ *	
+ * For the example, if One packet need to be send and its size is the 20 bit 
+ * then it will require the 3 bytes in the pWriteBuffer and arrangement of the 
+ * data	 are as follows:
+ * The packet is 0x000ABCDE (Packet with length of 20 bit).
+ * pWriteBuff[0] = 0x0A
+ * pWriteBuff[1] = 0xBC
+ * pWtriteBuff[2] = 0xDE
+ *
+ * The most significant bit will be transmitted first i.e. bit20 is transmitted 
+ * first and bit 0 will be transmitted last.
+ *
+ * If the transmitted packet (command + receive data) is more than 32 like 33 and 
+ * want to transfer in the single call (CS should be active) then it can be transmitted
+ * in following way:
+ * The transfer is command(8 bit)+Dummy(1bit)+Read (24 bit) = 33 bit of transfer.
+ * - Send 33 bit as 33 byte and each byte have the 1 valid bit, So packet bit length = 1 and
+ * bytes requested = 33.
+ * NvU8 pSendData[33], pRecData[33];
+ *  pSendData[0] = (Comamnd >>7) & 0x1;
+ *  pSendData[1] = (Command >> 6)& 0x1; 
+ * ::::::::::::::
+ * pSendData[8] = DummyBit;
+ * pSendData[9] to pSendData[32] = 0;
+ * Call NvRmSpiTransaction(hRmSpi,SpiPinMap,ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 33,1);
+ * Now You will get the read data from pRecData[9] to pRecData[32] on bit 0 on each byte.
+ *
+ * - The 33 bit transfer can be also done as 11 byte and each byte have the 3 valid bits.
+ * This need to rearrange the command in the pSendData in such a way that each byte have the
+ * 3 valid bits.
+ * NvU8 pSendData[11], pRecData[11];
+ *  pSendData[0] = (Comamnd >>4) & 0x7;
+ *  pSendData[1] = (Command >> 1)& 0x7; 
+ *  pSendData[2] = (((Command)& 0x3) <<1) | DummyBit; 
+ * pSendData[3] to pSendData[10] = 0;
+ * 
+ * Call NvRmSpiTransaction(hRmSpi,SpiPinMap,ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 11,3);
+ * Now You will get the read data from pRecData[4] to pRecData[10] on lower 3 bits on each byte.
+ *
+ * Similarly the 33 bit transfer can also be done as 6 byte and each 2 bytes contain the 11 valid bits.
+ * Call NvRmSpiTransaction(hRmSpi,SpiPinMap,ChipSelect,ClockSpeedInKHz,pRecData, pSendData, 6,11);
+ *
+ * pReadBuffer and pWriteBuffer may be the same pointer, in which case the 
+ * write data is destroyed as we read in the read data. Unless they are 
+ * identical pointers, however, pReadBuffer and pWriteBuffer must not overlap.
+ *
+ * @param hOdmSpi The Spi handle allocated in a call to NvOdmSpiOpen().
+ * @param SpiPinMap For SPI master-mode controllers which are being multiplexed across
+ *        multiple pin mux configurations, this specifies which pin mux configuration
+ *        should be used for the transaction.  Must be 0 when the ODM pin mux query
+ *        specifies a non-multiplexed configuration for the controller.
+ * @param ChipSelectId The chip select Id on which device is connected.
+ * @param ClockSpeedInKHz The clock speed in KHz on which device can communicate.
+ * @param pReadBuffer A pointer to buffer to be filled in with read data. If this
+ *     pointer is NULL, the read data will be discarded.
+ * @param pWriteBuffer A pointer to a buffer from which to obtain write data. If this
+ *     pointer is NULL, the write data will be all zeros.
+ * @param BytesRequested The size of pReadBuffer and pWriteBuffer buffers in bytes.
+ * @param PacketSizeInBits The packet size in bits of each Spi transaction.
+ *
+ */
+ 
+ void NvRmSpiTransaction( 
+    NvRmSpiHandle hRmSpi,
+    NvU32 SpiPinMap,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvU8 * pReadBuffer,
+    NvU8 * pWriteBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketSizeInBits );
+
+/**
+ * Start an Spi controller read and write simultaneously in the slave mode. 
+ * This API is only supported for the spi handle which is opened in slave mode. 
+ *
+ * This API will assert if opened spi handle is the master type.
+ *
+ * Every Spi  transaction is by definition a simultaneous read and write 
+ * transaction, so there are no separate APIs for read versus write. 
+ * However, if you only need to start a read or write transaction, this API 
+ * allows you to declare that you are not interested in the read data, 
+ * or that the write data is not of interest.
+ * If only read is required to start then client can pass NV_TRUE to the the
+ * IsReadTransfer and NULL pointer to the pWriteBuffer. The state of the dataout 
+ * will be set by IsIdleDataOutHigh of the structure NvOdmQuerySpiIdleSignalState 
+ * in nvodm_query.h.
+ * Similarly, if client wants to send data only then he can pass NV_FALSE to the
+ * IsReadTransfer.
+ *
+ * This is a nonblocking API. This api start the data transfer and returns to the
+ * caller without waiting for the data transfer completion.
+ *
+ * Transaction sizes from 1 to 32 bits are supported. However, all of the 
+ * packets are byte-aligned in memory. Like, if packetBitLength is 12 bit 
+ * then client needs the 2 byte for the 1 packet. New packets start from the
+ * new bytes e.g. byte0 and byte1 contain the first packet and byte2 and byte3
+ * will contain the second packets.
+ *
+ * To perform one transaction, the BytesRequested argument should be:
+ *
+ *   (PacketSizeInBits + 7)/8
+ *
+ * To perform n transactions, BytesRequested should be:
+ *
+ *   n*((PacketSizeInBits + 7)/8)
+ *
+ * Within a given
+ * transaction with the packet size larger than 8 bits, the bytes are stored in 
+ * order of the LSB (least significant byte) first.
+ * The Packet is formed with the first Byte will be in LSB and then next byte 
+ * will be in the  next LSB towards the MSB.
+ *	
+ * For the example, if One packet need to be send and its size is the 20 bit 
+ * then it will require the 3 bytes in the pWriteBuffer and arrangement of the 
+ * data	 are as follows:
+ * The packet is 0x000ABCDE (Packet with length of 20 bit).
+ * pWriteBuff[0] = 0xDE
+ * pWriteBuff[1] = 0xBC
+ * pWtriteBuff[2] = 0x0A
+ *
+ * The most significant bit will be transmitted first i.e. bit20 is transmitted 
+ * first and bit 0 will be transmitted last.
+ *
+ * @see NvRmSpiGetTransactionData
+ * Typical usecase for the CAIF interface.  The step for doing the transfer is:
+ * 1. ACPU calls the NvRmSpiStartTransaction() to configure the spi controller
+ * to set in the receive or transmit mode and make ready for the data transfer.
+ * 2. ACPU then send the signal to the CCPU to send the SPICLK (by activating 
+ * the SPI_INT) and start the transaction. CCPU get this signal and start sending 
+ * SPICLK.
+ * 3. ACPU will call the NvRmSpiGetTransactionData() to get the data/information 
+ * about the transaction.
+ * 4. After completion of the transfer ACPU inactivate the SPI_INT.
+ *
+ * @param hOdmSpi The Spi handle allocated in a call to NvOdmSpiOpen().
+ * @param ChipSelectId The chip select Id on which device is connected.
+ * @param ClockSpeedInKHz The clock speed in KHz on which device can communicate.
+ * @param IsReadTransfer It tells that whether the read transfer is required or 
+ * not. If it is NV_TRUE then read transfer is required and the read data will be 
+ * available in the local buffer of the driver. The client will get the received
+ * data after calling the NvRmSpiGetTransactionData().
+ * @param pWriteBuffer A pointer to a buffer from which to obtain write data. If this
+ *     pointer is NULL, the write data will be all zeros.
+ * @param BytesRequested The size of pReadBuffer and pWriteBuffer buffers in bytes.
+ * @param PacketSizeInBits The packet size in bits of each Spi transaction.
+ *
+ */
+ 
+ NvError NvRmSpiStartTransaction( 
+    NvRmSpiHandle hRmSpi,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvBool IsReadTransfer,
+    NvU8 * pWriteBuffer,
+    NvU32 BytesRequested,
+    NvU32 PacketSizeInBits );
+
+/**
+ * Get the spi transaction status that is started for the slave mode and wait
+ * if required till the transfer completes for a given timeout error.
+ * If read transaction has been started then it will return the receive data to 
+ * the client.
+ *
+ * This is a blocking API and wait for the data transfer completion till the
+ * data requested transfer completes or the timeout happen.
+ *
+ * @see NvRmSpiStartTransaction
+ *
+ * @param hOdmSpi The Spi handle allocated in a call to NvOdmSpiOpen().
+ * @param pReadBuffer A pointer to buffer to be filled in with read data. If this
+ *     pointer is NULL, the read data will be discarded.
+ * @param BytesRequested The size of pReadBuffer and pWriteBuffer buffers in bytes.
+ * @param BytesTransfererd The number of bytes transferred.
+ * @param WaitTimeout The timeout in millisecond to wait for the trsnaction to be 
+ * completed.
+ *
+ * @retval NvSuccess Indicates that the operation succeeded.
+ * @retval NvError_Timeout Indicates that the timeout happen.
+ * @retval NvError_InvalidState Indicates that the transfer has not been started.
+ *
+ */
+ 
+ NvError NvRmSpiGetTransactionData( 
+    NvRmSpiHandle hRmSpi,
+    NvU8 * pReadBuffer,
+    NvU32 BytesRequested,
+    NvU32 * pBytesTransfererd,
+    NvU32 WaitTimeout );
+
+/**
+ * Set the signal mode for the spi communication for a given chip select.
+ * After calling this API, the further communication happen with the new 
+ * configured signal modes.
+ * The default value of the signal mode is taken from nvodm query and this
+ * api will override the signal mode which is read from query.
+ *
+ * @see NvRmSpiStartTransaction
+ *
+ * @param hOdmSpi The Spi handle allocated in a call to NvOdmSpiOpen().
+ * @param ChipSelectId The chip select Id on which device is connected.
+ * @param SpiSignalMode The nvodm signal modes which need to be set.
+ *
+ */
+ 
+ void NvRmSpiSetSignalMode( 
+    NvRmSpiHandle hRmSpi,
+    NvU32 ChipSelectId,
+    NvU32 SpiSignalMode );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_transport.h b/arch/arm/mach-tegra/nv/include/nvrm_transport.h
new file mode 100644
index 000000000000..179f63223ed5
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_transport.h
@@ -0,0 +1,361 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_transport_H
+#define INCLUDED_nvrm_transport_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *     Resource Manager Transport APIs</b>
+ *
+ * @b Description: This is the Transport API, which defines a simple means to
+ * pass messages across a lower level connection (generally between
+ * processors).
+ *
+ */
+
+/** @defgroup nvrm_transport RM Transport API
+ * 
+ * The Transport API defines a simple protocol through which clients and
+ * services may connect and communicate--normally, though not necessarily,
+ * across separate processors.  Clients to this interface mostly include
+ * audio-visual applications whose code may reside on either the MPCore or AVP
+ * processors.  These applications (and there could be many concurrently) may
+ * utilize this transport API to synchronize their operations.  How the
+ * Transport API shepherds messages through these connections is not visible to
+ * the client.
+ * 
+ * To setup a new connection, both the client and the service must open a port
+ * (whose name is agreed upon before compile-time).  The service waits for a
+ * client to connect; this "handshake" allows a connection to be established.
+ * Once a client has established a connection with the service, they may send
+ * and receive messages.
+ * 
+ * @ingroup nvddk_rm
+ * @{
+ */
+
+#include "nvos.h"
+
+/**
+ * A type-safe handle for the transport connection.
+ */
+
+typedef struct NvRmTransportRec *NvRmTransportHandle;
+
+/**
+ * Creates one end of a transport connection.  Both the service and client
+ * to the service must call this API to create each endpoint of the connection
+ * through a specified port (whose name is agreed upon before compile-time).
+ * A connection is not established between the service and client until a 
+ * handshake is completed (via calls to NvRmTransportWaitForConnect() and
+ * NvRmTransportConnect() respectively).
+ *
+ * Assert in debug mode encountered if PortName is too long or does not exist 
+ *
+ * @see NvRmTransportWaitForConnect()
+ * @see NvRmTransportConnect()
+ * @see NvRmTransportClose()
+ *
+ * @param hRmDevice Handle to RM device
+ * @param pPortName A character string that identifies the name of the port.
+ * This value must be 16 bytes or less, otherwise the caller receives an error.
+ * You can optionally pass NULL for this parameter, in which case a unique
+ * name will  be assigned.  And you can call NvRmTransporGetPortName to retrieve
+ * the name.
+ * @param RecvMessageSemaphore The externally created semaphore that the
+ * transport  connection will signal upon receipt of a message.
+ * @param phTransport Points to the location where the transport handle shall
+ * be stored
+ * 
+ * @retval NvSuccess Transport endpoint successfully allocated
+ * @retval NvError_InsufficientMemory Not enough memory to allocate endpoint
+ * @retval NvError_MutexCreateFailed Creaion of mutex failed.
+ * @retval NvError_SemaphoreCreateFailed Creaion of semaphore failed.
+ * @retval NvError_SharedMemAllocFailed Creaion of shared memory allocation
+ * failed.
+ * @retval NvError_NotInitialized The transport is not able to initialzed the
+ * threads.
+ */
+
+ NvError NvRmTransportOpen( 
+    NvRmDeviceHandle hRmDevice,
+    char * pPortName,
+    NvOsSemaphoreHandle RecvMessageSemaphore,
+    NvRmTransportHandle * phTransport );
+
+/**
+ * Retrieve the name associated with a port.
+ *
+ * Assert in debug mode encountered if PortName is too long or does not exist 
+ *
+ * @see NvRmTransportOpen()
+ *
+ * @param hTransport Handle to the port that you want the name of.
+ * @param PortName A character string that identifies the name of the port.
+ * @param PortNameSize Length of the PortName buffer.
+ * 
+ */
+
+ void NvRmTransportGetPortName( 
+    NvRmTransportHandle hTransport,
+    NvU8 * PortName,
+    NvU32 PortNameSize );
+
+/**
+ * Closes a transport connection.  Proper closure of this connection requires
+ * that both the client and service call this API.  Therefore, it is expected
+ * that the client and service message one another to coordinate the close.
+ *
+ * @see NvRmTransportOpen()
+ * 
+ * @param hTransport Specifies the transport connection to close.  If hTransport
+ *     is NULL, this API does nothing.
+ */
+
+ void NvRmTransportClose( 
+    NvRmTransportHandle hTransport );
+
+/**
+ * Initializes the transport.
+ *
+ * @param hRmDevice Handle to RM device
+ *
+ */
+
+ NvError NvRmTransportInit( 
+    NvRmDeviceHandle hRmDevice );
+
+/**
+ * Deinitializes the transport.
+ *
+ * @param hRmDevice Handle to RM device
+ *
+ */
+
+ void NvRmTransportDeInit( 
+    NvRmDeviceHandle hRmDevice );
+
+/**
+ * This handshake API is called by the service, which waits for a client to
+ * establish a connection via a call to NvRmTransportConnect().  Messages 
+ * cannot be sent and received until this handshake is completed.
+ * 
+ * To ensure a client has sufficient opportunity to establish a connection
+ * from the other end, a large timeout value (such as NV_WAIT_INFINITE) is
+ * recommended here.
+ *
+ * @see NvRmTransportConnect()
+ *
+ * @param hTransport Specifies the transport connection
+ * @param TimeoutMS Specifies the amount of time (in milliseconds) to wait for
+ *   connection to be established.  A value of NV_WAIT_INFINITE means "wait
+ *   indefinitely."  A value of zero (0) will timeout immediately, which is
+ *   not recommended for this function call.
+ * 
+ * @retval NvSuccess Service is waiting to receive a "connect" from client
+ * @retval NvError_NotInitialized hTransport is not open
+ * @retval NvError_Timeout Timed out waiting for service to respond
+ */
+
+ NvError NvRmTransportWaitForConnect( 
+    NvRmTransportHandle hTransport,
+    NvU32 TimeoutMS );
+
+/**
+ * This blocking handshake API is called by the client, which seeks a
+ * service (as specified by a handle) to establish a connection.  Messages
+ * cannot be sent and received until this handshake is completed.
+ *
+ * @see NvRmTransportWaitForConnect()
+ *
+ * @param hTransport Specifies the transport connection
+ * @param TimeoutMS Specifies the amount of time (in milliseconds) to wait for
+ *   connection to be established.  A value of NV_WAIT_INFINITE means "wait
+ *   indefinitely."  A value of zero (0) will timeout immediately, but
+ *   this function will at least take time to check if the port is open and
+ *   waiting for a connection--if so, a connection will be established.
+ * 
+ * @retval NvSuccess Transport connection successfully established
+ * @retval NvError_NotInitialized hTransport is not open
+ * @retval NvError_Timeout Timed out waiting for service to respond.
+ */
+
+ NvError NvRmTransportConnect( 
+    NvRmTransportHandle hTransport,
+    NvU32 TimeoutMS );
+
+/**
+ * Set the max size of the message queue (FIFO) deptha nd length which can be 
+ * send and receive from this port. The programmer must decide the
+ * queue depth that's appropriate for their design.  If this function is not
+ * called, the queue depth is set to one (1) and message size is 256 bytes.  
+ * 
+ *
+ * @see NvRmTransportSendMsg()
+ * @see NvRmTransportRecvMsg()
+ *
+ * @param hTransport Specifies the transport connection
+ * @param MaxQueueDepth The maximum number of message which can be queued for 
+ * this port for receiving and sending. The receive message can queue message 
+ * till this count for this port. If receive queue is full for this port and
+ * if other port send the message to this port then receive queue error status
+ * will turn as overrun and ignore the incoming message.
+ * If send message queue is full and client request to send message then he
+ * will wait for time provided by the parameter.
+ * @param MaxMessageSize Specifies the maximum size of the message in bytes
+ * which client can receive and transmit through this port. 
+ * 
+ * @retval NvSuccess New queue depth is set
+ * @retval NvError_NotInitialized hTransport is not open.
+ * @retval NvError_BadValue The parameter passed is not correct. There is 
+ * limitation for maximum message q and message length from the driver and if 
+ * this parameter is larger than those value then it returns this error.
+ *
+ */
+
+ NvError NvRmTransportSetQueueDepth( 
+    NvRmTransportHandle hTransport,
+    NvU32 MaxQueueDepth,
+    NvU32 MaxMessageSize );
+
+/**
+ * Sends a message to the other port which is connected to this port.
+ * This will use the copy method to copy the client buffer message to
+ * transport message buffer. This function queue the message to the transmit
+ * queue. the data will be send later based on the physical transfer channel
+ * availablity.
+ *
+ * @see NvRmTransportOpen()
+ * @see NvRmTransportSetQueueDepth()
+ * @see NvRmTransportRecvMsg()
+ *
+ * @param hTransport Specifies the transport connection
+ * @param pMessageBuffer The pointer to the message buffer where message which 
+ * need to be send is available.
+ * @param MessageSize Specifies the size of the message.
+ * @param TimeoutMS Specifies the amount of time (in milliseconds) to wait for
+ * sent message to be queued for the transfer. If the transmit queue if full
+ * then this function will block the client till maximum of timeout to queue
+ * this message. If meesage queue is available before timeout then it will
+ * queue the message and comeout. If message queue is full and timeout happen
+ * the it will return the timeout error.
+ * if zero timeout is selecetd and the message queue is full then it will be
+ * return NvError_TransportMessageBoxFull error.
+ * Avalue of NV_WAIT_INFINITE means "wait indefinitely" for queueing the
+ * message.
+ * 
+ * @retval NvSuccess Message is queued successfully.
+ * @retval NvError_NotInitialized hTransport is not open.
+ * @retval NvError_BadValue The parameter passed is not valid.
+ * @retval NvError_InvalidState The port is not connected to the other port and
+ * it is not ready for sending the message.
+ * @retval NvError_Timeout Timed out waiting for message to be queue if send 
+ * message queue.
+ * @retval NvError_TransportMessageBoxFull Message box is full and it is not
+ * able to queue the message.
+ */
+
+ NvError NvRmTransportSendMsg( 
+    NvRmTransportHandle hTransport,
+    void* pMessageBuffer,
+    NvU32 MessageSize,
+    NvU32 TimeoutMS );
+
+/**
+ * Sends a message to the other port which is connected to this port.
+ * This function is to be used ONLY when we're about to enter LP0!
+ * There is no synchronization in this function as only one person
+ * should be talking to the AVP at the time of LP0. The message is sent
+ * on the RPC_AVP_PORT. In the future, there might be instances where
+ * we need to talk on a different port in LP0. 
+ *
+ * @retval NvSuccess Message is queued successfully.
+ * @retval NvError_TransportMessageBoxFull Message box is full and it is not
+ * able to queue the message.
+ */
+
+ NvError NvRmTransportSendMsgInLP0( 
+    NvRmTransportHandle hPort,
+    void* message,
+    NvU32 MessageSize );
+
+/**
+ * Receive the message from the port. This will read the message if it is 
+ * available for this port otherwise it will return the
+ * NvError_TransportMessageBoxEmpty error.
+ *
+ * @see NvRmTransportOpen()
+ * @see NvRmTransportSetQueueDepth()
+ * @see NvRmTransportSendMsg()
+ *
+ * @param hTransport Specifies the transport connection
+ * @param pMessageBuffer The pointer to the receive message buffer where the
+ * received message will be copied.
+ * @param MaxSize The maximum size in bytes that may be copied to the buffer
+ * @param pMessageSize Pointer to the variable where the length of the message 
+ * will be stored.
+ * 
+ * @retval NvSuccess Message received successfully.
+ * @retval NvError_NotInitialized hTransport is not open.
+ * @retval NvError_InvalidState The port is not connection state.
+ * @retval NvError_TransportMessageBoxEmpty The message box empty and not able 
+ * to receive the message.
+ * @retval NvError_TransportIncompleteMessage The received message for this
+ * port is longer than the configured message length for this port. It copied
+ * the maximm size of the configured length of the message for this port and
+ * return the incomplete message buffer.
+ * @retval NvError_TransportMessageOverflow The port receives the message more
+ * than the configured queue depth count for this port and hence message
+ * overflow has been ocuured.
+ */
+
+ NvError NvRmTransportRecvMsg( 
+    NvRmTransportHandle hTransport,
+    void* pMessageBuffer,
+    NvU32 MaxSize,
+    NvU32 * pMessageSize );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvrm_xpc.h b/arch/arm/mach-tegra/nv/include/nvrm_xpc.h
new file mode 100644
index 000000000000..69b61d8d1147
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvrm_xpc.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_nvrm_xpc_H
+#define INCLUDED_nvrm_xpc_H
+
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+#include "nvrm_module.h"
+#include "nvrm_init.h"
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_init.h"
+#include "nvrm_interrupt.h"
+
+/** 
+ * @brief 16 Byte allignment for the shared memory message transfer.
+ */
+
+typedef enum
+{
+    XPC_MESSAGE_ALIGNMENT_SIZE = 0x10,
+    Xpc_Alignment_Num,
+    Xpc_Alignment_Force32 = 0x7FFFFFFF
+} Xpc_Alignment;
+
+/**
+ * NvRmPrivXpcMessageHandle is an opaque handle to NvRmPrivXpcMessage.
+ * 
+ * @ingroup nvrm_xpc
+ */
+
+typedef struct NvRmPrivXpcMessageRec *NvRmPrivXpcMessageHandle;
+
+/**
+ * Create the xpc message handles for sending/receiving the message to/from 
+ * target processor.
+ * This function allocates the memory (from multiprocessor shared memory 
+ * region) and os resources for the message transfer and synchrnoisation.
+ *
+ * @see NvRmPrivXpcSendMessage()
+ * @see NvRmPrivXpcGetMessage()
+ *
+ * @param hDevice Handle to the Rm device which is required by Ddk to acquire 
+ * the resources from RM.
+ * @param phXpcMessage Pointer to the handle to Xpc message where created 
+ * Xpc message handle is stored.
+ *
+ * @retval NvSuccess Indicates the message queue is successfully created.
+ * @retval NvError_BadValue The parameter passed are incorrect.
+ * @retval NvError_InsufficientMemory Indicates that function fails to allocate the 
+ * memory for message queue.
+ * @retval NvError_MemoryMapFailed Indicates that the memory mapping for xpc 
+ * controller register failed.
+ * @retval NvError_NotSupported Indicates that the requested operation is not 
+ * supported for the given target processor/Instance.
+ * 
+ */
+ 
+ NvError NvRmPrivXpcCreate( 
+    NvRmDeviceHandle hDevice,
+    NvRmPrivXpcMessageHandle * phXpcMessage );
+
+/**
+ * Destroy the created Xpc message handle. This frees all the resources
+ * allocated for the xpc message handle.
+ *
+ * @note After calling this function client will not able to  send/receive any 
+ * message.
+ *
+ * @see NvRmPrivXpcMessageCreate()
+ *
+ * @param hXpcMessage Xpc message queue handle which need to be destroy. 
+ * This cas created when function NvRmPrivXpcMessageCreate() was called.
+ *
+ */
+
+ void NvRmPrivXpcDestroy( 
+    NvRmPrivXpcMessageHandle hXpcMessage );
+
+ NvError NvRmPrivXpcSendMessage( 
+    NvRmPrivXpcMessageHandle hXpcMessage,
+    NvU32 data );
+
+ NvU32 NvRmPrivXpcGetMessage( 
+    NvRmPrivXpcMessageHandle hXpcMessage );
+
+/**
+ * Initializes the Arbitration semaphore system for cross processor synchronization.
+ *
+ * @param hDevice The RM handle.
+ *
+ * @retval "NvError_IrqRegistrationFailed" if interupt is already registred.
+ * @retval "NvSuccess" if successfull.
+ */
+
+ NvError NvRmXpcInitArbSemaSystem( 
+    NvRmDeviceHandle hDevice );
+
+/**
+ * Tries to obtain a hw arbitration semaphore. This API is used to
+ * synchronize access to hw blocks across processors.
+ *
+ * @param modId The module that we need to cross-processor safe access to.
+ */
+
+ void NvRmXpcModuleAcquire( 
+    NvRmModuleID modId );
+
+/**
+ * Releases the arbitration semaphore corresponding to the given module id.
+ *
+ * @param modId The module that we are releasing.
+ */
+
+ void NvRmXpcModuleRelease( 
+    NvRmModuleID modId );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvsnor_controller.h b/arch/arm/mach-tegra/nv/include/nvsnor_controller.h
new file mode 100644
index 000000000000..66d7ee87bea4
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvsnor_controller.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef __NVSNOR_CONTROLLER_H
+#define __NVSNOR_CONTROLLER_H
+
+#include "mach/nvrm_linux.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvodm_query.h"
+
+#include "nvodm_services.h"
+#include "nvodm_query_discovery.h"
+
+#include "ap20/arsnor.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_power.h"
+#include "nvrm_drf.h"
+#include "nvrm_module.h"
+#include "nvrm_memmgr.h"
+#include "nvrm_interrupt.h"
+
+#define SNOR_CONTROLLER_CHIPSELECT_MAX 8
+
+#define SNOR_DMA_BUFFER_SIZE_BYTE 0x1000 //4KB
+//#define SNOR_DMA_BUFFER_SIZE_BYTE 0x4000 //16KB
+
+
+#define SNOR_READ32(pSnorHwRegsVirtBaseAdd, reg) \
+        NV_READ32((pSnorHwRegsVirtBaseAdd) + ((SNOR_##reg##_0)/4))
+
+#define SNOR_WRITE32(pSnorHwRegsVirtBaseAdd, reg, val) \
+    do \
+    {  \
+        NV_WRITE32((((pSnorHwRegsVirtBaseAdd) + ((SNOR_##reg##_0)/4))), (val)); \
+    } while (0)
+
+typedef struct
+{
+   NvRmPhysAddr DeviceBaseAddress;   
+   NvU32 DeviceAddressSize;  
+   NvU16 *pDeviceBaseVirtAddress;  
+   NvU32 DevicePureAddress;
+} ConnectedDeviceIntRegister;
+
+typedef struct 
+{
+    NvU32 Config;
+
+    NvU32 Status;
+    NvU32 NorAddressPtr;
+    NvU32 AhbAddrPtr;
+    NvU32 Timing0;
+    NvU32 Timing1;
+    NvU32 MioCfg;
+    NvU32 MioTiming;
+    NvU32 DmaConfig;
+    NvU32 ChipSelectMuxConfig;
+} SnorControllerRegs;
+
+typedef struct 
+{
+    NvU32 Muxed_Width;
+    NvU32 Hold_Width;
+    NvU32 ADV_dWidth;
+    NvU32 WE_Width;
+    NvU32 OE_Width;
+    NvU32 Wait_Width;
+    
+} SnorControllerTimingRegVals;
+
+
+typedef struct NvSnorRec
+{
+    NvRmDeviceHandle hRmDevice;
+
+    NvU32 OpenCount;
+    
+    // Physical Address of the SNOR controller instance
+    NvU32 SnorControllerBaseAdd;
+
+    // Virtual address for the SNOR controller instance
+    NvU32 *pSnorControllerVirtBaseAdd;
+
+    // Size of the SNOR register map
+    NvU32 SnorRegMapSize;
+
+    // Semaphore  for registering the client with the power manager.
+    NvOsSemaphoreHandle hRmPowerEventSema;
+    
+    // Power client Id.
+    NvU32 RmPowerClientId;
+ 
+    // Command complete semaphore
+    NvOsSemaphoreHandle hCommandCompleteSema;
+    
+    // Interrupt handle
+    NvOsInterruptHandle hIntr;
+    //For SNOR controller's DMA allocation
+    NvRmMemHandle hRmMemory;
+    NvRmPhysAddr DmaBuffPhysAdd;
+    NvU32 *pAhbDmaBuffer;
+    NvU32 Snor_DmaBufSize;
+    
+    //Number of devices present
+    NvU32 NumOfDevicesConnected;
+    
+    // Tells whether the device is avialble or not.
+    //NvU32 IsDevAvailable[SNOR_CONTROLLER_CHIPSELECT_MAX];
+
+    // Device interface register to access the devices which is controlled by SNOR controller.
+    ConnectedDeviceIntRegister ConnectedDevReg;
+
+    SnorControllerRegs SnorRegs;
+} NvSnor;
+
+typedef struct NvSnorRec *NvSnorHandle;
+
+typedef struct 
+{
+    NvRmDeviceHandle hRmDevice;
+    NvSnorHandle hSnor;
+} NvSnorInformation;
+
+
+NvError InitSnorInformation(void);
+void DeinitSnorInformation(void);
+void InitSnorController(NvSnorHandle hSnor, NvU32 DevTypeSNOREn, SnorControllerTimingRegVals TimingRegVals);
+void SetChipSelect(NvSnorHandle hSnor, NvU32 ChipSelId);
+NvError CreateSnorHandle(NvRmDeviceHandle hRmDevice, NvSnorHandle *phSnor);
+void DestroySnorHandle(NvSnorHandle hSnor);
+
+void NvReadViaSNORControllerDMA (NvSnorHandle hSnor, void* SnorAddr, NvU32 word32bit_count);
+void NvWriteViaSNORControllerDMA (NvSnorHandle hSnor, void* SnorAddr, NvU32 word32bit_count);
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/include/nvutil.h b/arch/arm/mach-tegra/nv/include/nvutil.h
new file mode 100644
index 000000000000..4c8a9f6d3d31
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/nvutil.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVUTIL_H
+#define INCLUDED_NVUTIL_H
+
+//###########################################################################
+//############################### INCLUDES ##################################
+//###########################################################################
+
+#include "nvcommon.h"
+#include "nvos.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+//###########################################################################
+//############################### PROTOTYPES ################################
+//###########################################################################
+
+/**
+ * parse a string into an unsigned integer.
+ *
+ * @param s - pointer to the string (null-terminated)
+ * @param endptr - if not NULL this returns pointing to the first character
+ *                 in the string that was not used in the conversion.
+ * @param base - must be 0, 10, or 16.
+ *                 10: the number is parsed as a base 10 number
+ *                 16: the number is parsed as a base 16 number (0x ignored)
+ *                 0: base 10 unless there is a leading 0x
+ */
+unsigned long int
+NvUStrtoul(
+        const char *s, 
+        char **endptr, 
+        int base);
+
+/**
+ * Sames NvUStrtoul, execpt can parse a 64 bit unsigned integer.
+ */
+unsigned long long int
+NvUStrtoull(
+        const char *s, 
+        char **endptr, 
+        int base);
+
+/**
+ * parse a string into a signed integer.
+ *
+ * @param s - pointer to the string (null-terminated)
+ * @param endptr - if not NULL this returns pointing to the first character
+ *                 in the string that was not used in the conversion.
+ * @param base - must be 0, 10, or 16.
+ *                 10: the number is parsed as a base 10 number
+ *                 16: the number is parsed as a base 16 number (0x ignored)
+ *                 0: base 10 unless there is a leading 0x
+ */
+long int
+NvUStrtol(
+        const char *s, 
+        char **endptr, 
+        int base);
+
+/**
+ * concatenate 2 strings.
+ *
+ * Note: dest is always left null terminated even if src exceeds n.
+ *
+ * @param dest - string to concatenate to
+ * @param src  - string to add to the end of dest
+ * @param n    - At most n chars from src (plus a NUL) are appended to dest
+ */
+void
+NvUStrncat(
+        char *dest, 
+        const char *src, 
+        size_t n);
+
+/**
+ * returns a pointer to the first occurence of str2 in str1.
+ *
+ * This function returns NULL if no match is found. If the length of str2 is
+ * zero, then str1 is returned.
+ *
+ * @param str1 - string to be scanned
+ * @param str2 - string containing the sequence of characters to match
+ */
+char *
+NvUStrstr(
+        const char *str1, 
+        const char *str2);
+
+/**
+ * converts strings between code pages
+ *
+ * @param pDest - the destination buffer
+ * @param DestCodePage - the target code page
+ * @param DestSize - size of the destination buffer, in bytes
+ * @param pSrc - the source string
+ * @param SrcSize - the size of the source buffer, in bytes, or zero if the
+*       string is NULL-terminated
+ * @param SrcCodePage - the source string's code page
+ *
+ * @returns The length of the destination string and NULL termination, in bytes
+ *
+ * If pDest is NULL, this function will return the number of bytes, including
+ * NULL termination, of the destination buffer required to store the converted
+ * string.
+ *
+ * If pDest is specified, up to DestSize bytes of the code-page converted
+ * string will be written to it.  If the destination buffer is too small to
+ * store the converted string, the string will be truncated and a
+ * NULL-terminator added.
+ *
+ * If either SrcCodePage or DestCodePage is NvOsCodePage_Unknown, the system's
+ * default code page will be used for the conversion.
+ */
+size_t
+NvUStrlConvertCodePage(void *pDest,
+                       size_t DestSize,
+                       NvOsCodePage DestCodePage,
+                       const void *pSrc,
+                       size_t SrcSize,
+                       NvOsCodePage SrcCodePage);
+
+/**
+ * dynamically allocate zeroed memory (uses NvOsAlloc())
+ *
+ * @param size number of bytes to allocate
+ * @returns NULL on failure
+ * @returns pointer to zeroed memory on success (must be freed with NvOsFree)
+ */
+static NV_INLINE void *
+NvUAlloc0(size_t size)
+{
+    void *p = NvOsAlloc(size);
+    if (p)
+        NvOsMemset(p,0,size);
+    return p;
+}
+
+/**
+ * Finds the lowest set bit.
+ *
+ * @param bits The bits to look through
+ * @param nBits The number of bits wide
+ */
+NvU32
+NvULowestBitSet( NvU32 bits, NvU32 nBits );
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif // INCLUDED_NVUTIL_H
diff --git a/arch/arm/mach-tegra/nv/include/rm_spi_slink.h b/arch/arm/mach-tegra/nv/include/rm_spi_slink.h
new file mode 100644
index 000000000000..61714a1333c6
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/rm_spi_slink.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_RM_SPI_SLINK_H
+#define INCLUDED_RM_SPI_SLINK_H
+
+#include "nvrm_spi.h"
+
+typedef struct NvRmSpiTransactionInfoRec
+{
+    NvU8 *rxBuffer;
+    NvU8 *txBuffer;
+    NvU32 len;
+} NvRmSpiTransactionInfo;
+
+
+void NvRmSpiMultipleTransactions(
+    NvRmSpiHandle hRmSpi,
+    NvU32 SpiPinMap,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvU32 PacketSizeInBits,
+    NvRmSpiTransactionInfo *t,
+    NvU32 NumOfTransactions);
+
+#endif // INCLUDED_RM_SPI_SLINK_H
+
diff --git a/arch/arm/mach-tegra/nv/nvos/Makefile b/arch/arm/mach-tegra/nv/nvos/Makefile
new file mode 100644
index 000000000000..b1ed525a701a
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvos/Makefile
@@ -0,0 +1,12 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+ccflags-y += -Iarch/arm/mach-tegra/nv/include
+
+obj-y += nvos.o
+obj-y += nvustring.o
diff --git a/arch/arm/mach-tegra/nv/nvos/nvos.c b/arch/arm/mach-tegra/nv/nvos/nvos.c
new file mode 100644
index 000000000000..16bc55cbb1ec
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvos/nvos.c
@@ -0,0 +1,1657 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvos.h"
+#include "nvos_trace.h"
+#include "nvutil.h"
+#include "nverror.h"
+#include "nvassert.h"
+#include "nvbootargs.h"
+#include "nvio.h"
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/jiffies.h>
+#include <linux/time.h>
+#include <linux/kernel.h>
+#include <linux/kthread.h>
+#include <linux/mm.h>
+#include <linux/mutex.h>
+#include <linux/sched.h>
+#include <linux/semaphore.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/uaccess.h>
+#include <linux/vmalloc.h>
+#include <linux/pagemap.h>
+#include <linux/dma-mapping.h>
+#include <asm/atomic.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/div64.h>
+#include <asm/setup.h>
+#include <asm/cacheflush.h>
+#include <mach/irqs.h>
+#include <linux/freezer.h>
+#include <linux/slab.h>
+
+#if NVOS_TRACE || NV_DEBUG
+#undef NvOsAlloc
+#undef NvOsFree
+#undef NvOsRealloc
+#undef NvOsSharedMemAlloc
+#undef NvOsSharedMemMap
+#undef NvOsSharedMemUnmap
+#undef NvOsSharedMemFree
+#undef NvOsMutexCreate
+#undef NvOsExecAlloc
+#undef NvOsExecFree
+#undef NvOsPageAlloc
+#undef NvOsPageLock
+#undef NvOsPageFree
+#undef NvOsPageMap
+#undef NvOsPageMapIntoPtr
+#undef NvOsPageUnmap
+#undef NvOsPageAddress
+#undef NvOsIntrMutexCreate
+#undef NvOsIntrMutexLock
+#undef NvOsIntrMutexUnlock
+#undef NvOsIntrMutexDestroy
+#undef NvOsInterruptRegister
+#undef NvOsInterruptUnregister
+#undef NvOsInterruptEnable
+#undef NvOsInterruptDone
+#undef NvOsPhysicalMemMapIntoCaller
+#undef NvOsMutexLock
+#undef NvOsMutexUnlock
+#undef NvOsMutexDestroy
+#undef NvOsPhysicalMemMap
+#undef NvOsPhysicalMemUnmap
+#undef NvOsSemaphoreCreate
+#undef NvOsSemaphoreWait
+#undef NvOsSemaphoreWaitTimeout
+#undef NvOsSemaphoreSignal
+#undef NvOsSemaphoreDestroy
+#undef NvOsSemaphoreClone
+#undef NvOsSemaphoreUnmarshal
+#undef NvOsThreadCreate
+#undef NvOsInterruptPriorityThreadCreate
+#undef NvOsThreadJoin
+#undef NvOsThreadYield
+#endif
+
+#define KTHREAD_IRQ_PRIO (MAX_RT_PRIO>>1)
+
+#define NVOS_MAX_SYSTEM_IRQS NR_IRQS
+
+#define NVOS_IRQ_IS_ENABLED 0x1
+
+/* NVOS_IRQ_IS_ flags are mutually exclusive.
+ * IS_TASKLET executes the handler in a tasklet (used for kernel drivers)
+ * IS_KERNEL_THREAD executes in a kernel thread (used for kernel GPIOs)
+ * IS_USER simply signals an NvOs semaphore (used for user-mode interrupts)
+ *
+ * Currently the choice is based on the IRQ number and if the requester is
+ * an IOCTL. Later this can be modified to be exposed in the public APIs.
+ *
+ * If no flag is set, the IRQ is handled in the interrupt handler itself.
+ */
+
+#define NVOS_IRQ_TYPE_SHIFT 1
+#define NVOS_IRQ_TYPE_MASK (0x3 << NVOS_IRQ_TYPE_SHIFT)
+
+#define NVOS_IRQ_IS_IRQ           (0)
+#define NVOS_IRQ_IS_TASKLET       (0x1 << NVOS_IRQ_TYPE_SHIFT)
+#define NVOS_IRQ_IS_KERNEL_THREAD (0x2 << NVOS_IRQ_TYPE_SHIFT)
+#define NVOS_IRQ_IS_USER          (0x3 << NVOS_IRQ_TYPE_SHIFT)
+
+static DEFINE_SPINLOCK(gs_NvOsSpinLock);
+
+typedef struct NvOsIrqHandlerRec
+{
+    union
+    {
+        NvOsInterruptHandler  pHandler;
+        NvOsSemaphoreHandle   pSem;
+    };
+    NvU32                 Irq;
+    char                  IrqName[16];
+    struct semaphore      sem;
+    struct task_struct    *task;
+    struct tasklet_struct Tasklet;
+} NvOsIrqHandler;
+
+typedef struct NvOsInterruptBlockRec
+{
+    void                *pArg;
+    NvU32               Flags;
+    NvU32               NumIrqs;
+    NvU32               Shutdown;
+    NvOsIrqHandler      IrqList[1];
+} NvOsInterruptBlock;
+
+#define INTBLOCK_SIZE(NUMIRQS) \
+    (sizeof(NvOsInterruptBlock) + ((NUMIRQS)-1)*sizeof(NvOsIrqHandler))
+
+static NvOsInterruptBlock *s_pIrqList[NVOS_MAX_SYSTEM_IRQS] = { NULL };
+
+static NvBootArgs s_BootArgs = { {0}, {0}, {0}, {0}, {0}, {0}, {{0}} };
+
+/*  The tasklet "data" parameter is a munging of the s_pIrqList index
+ *  (just the IRQ number), and the InterruptBlock's IrqList index, to
+ *  make interrupt handler lookups O(n)
+ */
+static void NvOsTaskletWrapper(
+       unsigned long data)
+{
+    NvOsInterruptBlock *pBlock = s_pIrqList[(data&0xffff)];
+    if (pBlock)
+        (*pBlock->IrqList[data>>16].pHandler)(pBlock->pArg);    
+}
+
+/*  The thread "pdata" parameter is a munging of the s_pIrqList index
+ *  (just the IRQ number), and the InterruptBlock's IrqList index, to
+ *  make interrupt handler lookups O(n)
+ */
+static int NvOsInterruptThreadWrapper(
+     void *pdata)
+{
+    unsigned long data = (unsigned long)pdata;
+    NvOsInterruptBlock *pBlock = s_pIrqList[(data&0xffff)];
+
+    if (!pBlock)
+    {
+        return 0;
+    } 
+    while (!pBlock->Shutdown)
+    {
+        int t;
+
+        /* Is the timeout large enough? */
+        t = down_interruptible(&pBlock->IrqList[data>>16].sem);
+
+        if (pBlock->Shutdown)
+            break;
+
+        if (t)
+            continue;
+
+        (*pBlock->IrqList[data>>16].pHandler)(pBlock->pArg);
+    }
+
+    return 0;
+}
+
+static irqreturn_t NvOsIrqWrapper(
+    int irq,
+    void *dev_id)
+{
+    unsigned long data = (unsigned long)dev_id;
+    NvOsInterruptBlock *pBlock = s_pIrqList[irq];
+
+    disable_irq_nosync(irq);
+    switch (pBlock->Flags & NVOS_IRQ_TYPE_MASK)
+    {
+    case NVOS_IRQ_IS_TASKLET:
+        tasklet_schedule(&pBlock->IrqList[data].Tasklet);
+        break;
+    case NVOS_IRQ_IS_KERNEL_THREAD:
+        up(&(pBlock->IrqList[data].sem));
+        break;
+    case NVOS_IRQ_IS_USER:
+        NvOsSemaphoreSignal(pBlock->IrqList[data].pSem);
+        break;
+    case NVOS_IRQ_IS_IRQ:
+        (*pBlock->IrqList[data].pHandler)(pBlock->pArg);
+        break;
+    }
+
+    return IRQ_HANDLED;
+}
+
+NvError NvOsFprintf(NvOsFileHandle stream, const char *format, ...)
+{
+    return NvError_NotImplemented;
+}
+
+NvS32 NvOsSnprintf(char *str, size_t size, const char *format, ...)
+{
+    va_list ap;
+    va_start( ap, format );
+    return vsnprintf( str, size, format, ap );
+    va_end( ap );
+}
+
+NvError NvOsVfprintf(NvOsFileHandle stream, const char *format, va_list ap)
+{
+    return NvError_NotImplemented;
+}
+
+NvS32 NvOsVsnprintf(char *str, size_t size, const char *format, va_list ap)
+{
+    return vsnprintf( str, size, format, ap );
+}
+
+void NvOsDebugPrintf(const char *format, ...)
+{
+    va_list ap;
+    va_start( ap, format );
+    vprintk( format, ap );
+    va_end( ap );
+}
+
+void
+NvOsDebugVprintf( const char *format, va_list ap )
+{
+    vprintk( format, ap );
+}
+
+NvS32 NvOsDebugNprintf(const char *format, ...)
+{
+    NvS32 r;
+    va_list ap;
+    va_start( ap, format );
+    r = vprintk( format, ap );
+    va_end( ap );
+    return r;
+}
+
+
+NvError NvOsGetOsInformation(NvOsOsInfo *pOsInfo)
+{
+    if (pOsInfo)
+    {
+        NvOsMemset(pOsInfo, 0, sizeof(NvOsOsInfo));
+        pOsInfo->OsType = NvOsOs_Linux;
+    }
+    else
+    {
+        return NvError_BadParameter;
+    }
+    return NvError_Success;
+}
+
+void NvOsStrncpy(char *dest, const char *src, size_t size)
+{
+    strncpy( dest, src, size );
+}
+
+NvOsCodePage NvOsStrGetSystemCodePage(void)
+{
+    return (NvOsCodePage)0;
+}
+
+size_t NvOsStrlen(const char *s)
+{
+    return strlen(s);
+}
+
+int NvOsStrcmp(const char *s1, const char *s2)
+{
+    return strcmp(s1, s2);
+}
+
+int NvOsStrncmp(const char *s1, const char *s2, size_t size)
+{
+    return strncmp(s1, s2, size);
+}
+
+void NvOsMemcpy(void *dest, const void *src, size_t size)
+{
+    memcpy(dest, src, size);
+}
+
+int NvOsMemcmp(const void *s1, const void *s2, size_t size)
+{
+    return memcmp(s1, s2, size);
+}
+
+void NvOsMemset(void *s, NvU8 c, size_t size)
+{
+    memset(s, c, size);
+}
+
+void NvOsMemmove(void *dest, const void *src, size_t size)
+{
+    memmove(dest, src, size);
+}
+
+NvError NvOsCopyIn(void *pDst, const void *pSrc, size_t Bytes)
+{
+    if (!Bytes)
+        return NvSuccess;
+
+    if( access_ok( VERIFY_READ, pSrc, Bytes ) )
+    {
+        __copy_from_user(pDst, pSrc, Bytes);
+        return NvSuccess;
+    }
+
+    return NvError_InvalidAddress;
+}
+
+NvError NvOsCopyOut(void *pDst, const void *pSrc, size_t Bytes)
+{
+    if (!Bytes)
+        return NvSuccess;
+
+    if( access_ok( VERIFY_WRITE, pDst, Bytes ) )
+    {
+        __copy_to_user(pDst, pSrc, Bytes);
+        return NvSuccess;
+    }
+
+    return NvError_InvalidAddress;
+}
+
+NvError NvOsFopen(const char *path, NvU32 flags, NvOsFileHandle *file)
+{
+    return NvError_NotImplemented;
+}
+
+void NvOsFclose(NvOsFileHandle stream)
+{
+}
+
+NvError NvOsFwrite(NvOsFileHandle stream, const void *ptr, size_t size)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsFread(
+    NvOsFileHandle stream,
+    void *ptr,
+    size_t size,
+    size_t *bytes)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsFreadTimeout(
+    NvOsFileHandle stream,
+    void *ptr,
+    size_t size,
+    size_t *bytes,
+    NvU32 timeout_msec)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsFgetc(NvOsFileHandle stream, NvU8 *c)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsFseek(NvOsFileHandle file, NvS64 offset, NvOsSeekEnum whence)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsFtell(NvOsFileHandle file, NvU64 *position)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsStat(const char *filename, NvOsStatType *stat)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsFstat(NvOsFileHandle file, NvOsStatType *stat)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsFflush(NvOsFileHandle stream)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsFsync(NvOsFileHandle stream)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsIoctl(
+    NvOsFileHandle hFile,
+    NvU32 IoctlCode,
+    void *pBuffer,
+    NvU32 InBufferSize,
+    NvU32 InOutBufferSize,
+    NvU32 OutBufferSize)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsOpendir(const char *path, NvOsDirHandle *dir)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsReaddir(NvOsDirHandle dir, char *name, size_t size)
+{
+    return NvError_NotImplemented;
+}
+
+void NvOsClosedir(NvOsDirHandle dir)
+{
+}
+
+const NvOsFileHooks *NvOsSetFileHooks(NvOsFileHooks *newHooks)
+{
+    return 0;
+}
+
+NvError NvOsGetConfigU32(const char *name, NvU32 *value)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsGetConfigString(const char *name, char *value, NvU32 size)
+{
+    return NvError_NotImplemented;
+}
+
+void *NvOsAlloc(size_t size)
+{
+    size_t AllocSize = size + sizeof(size_t);
+    size_t* ptr = NULL;
+    ptr = vmalloc(AllocSize);
+    if (!ptr)
+        return ptr;
+    *ptr = size;
+    ptr++;
+    return (ptr);
+}
+
+void *NvOsRealloc(void *ptr, size_t size)
+{
+    size_t* NewPtr = NULL;
+    size_t OldSize = 0;
+    size_t SmallerSize = 0;
+
+    if( !ptr )
+    {
+        return NvOsAlloc(size);
+    }
+    if (!size)
+    {
+        NvOsFree(ptr);
+        return NULL;
+    }
+
+    // Get the size of the memory allocated for ptr.
+    NewPtr = (size_t*)ptr;
+    NewPtr--;
+    OldSize = *NewPtr;
+    if (size == OldSize)
+        return ptr;
+    SmallerSize = (OldSize > size) ? size : OldSize;
+
+    NewPtr = NvOsAlloc(size);
+    if(!NewPtr)
+        return NULL;
+    NvOsMemcpy(NewPtr, ptr, SmallerSize);
+    NvOsFree(ptr);
+    return NewPtr;
+}
+
+void NvOsFree(void *ptr)
+{
+    size_t* AllocPtr = NULL;
+    if (ptr)
+    {
+        AllocPtr = (size_t*)ptr;
+        AllocPtr--;
+    }
+    else
+        return;
+    vfree(AllocPtr);
+}
+
+void *NvOsExecAlloc(size_t size)
+{
+    return vmalloc_exec( size );
+}
+
+NvError NvOsSharedMemAlloc(
+    const char *key,
+    size_t size,
+    NvOsSharedMemHandle *descriptor)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsSharedMemMap(
+    NvOsSharedMemHandle descriptor,
+    size_t offset,
+    size_t size,
+    void **ptr)
+{
+    return NvError_NotImplemented;
+}
+
+
+void NvOsSharedMemUnmap(void *ptr, size_t size)
+{
+}
+
+void NvOsSharedMemFree(NvOsSharedMemHandle descriptor)
+{
+}    
+
+NvError NvOsPhysicalMemMap(
+    NvOsPhysAddr phys,
+    size_t size,
+    NvOsMemAttribute attrib,
+    NvU32 flags,
+    void **ptr)
+{
+    /*  For apertures in the static kernel mapping, just return the
+     *  static VA rather than creating a new mapping 
+     *  FIXME:  Eventually, the static phyiscal apertures should be
+     *  registered with NvOs when mapped, since they could be
+     *  chip-dependent
+     */
+#define aperture_comp_map(_name, _pa, _len)                             \
+    if ((phys >= (NvOsPhysAddr)(_pa)) &&                                \
+        ((NvOsPhysAddr)(phys+size)<=(NvOsPhysAddr)((_pa)+(_len)))) {    \
+            *ptr = (void *)tegra_munge_pa(phys);                        \
+            return NvSuccess;                                           \
+    }
+
+    tegra_apertures(aperture_comp_map);
+
+    if (attrib == NvOsMemAttribute_WriteCombined)
+    {
+        *ptr = ioremap_wc(phys, size);
+    }
+    else if (attrib == NvOsMemAttribute_WriteBack)
+    {
+        *ptr = ioremap_cached(phys, size);
+    }
+    else
+    {
+        *ptr = ioremap_nocache(phys, size);
+    }
+
+    if (*ptr == 0)
+        return NvError_InsufficientMemory;
+
+    return NvSuccess;
+}
+
+NvError NvOsPhysicalMemMapIntoCaller(
+    void *pCallerPtr,
+    NvOsPhysAddr phys,
+    size_t size,
+    NvOsMemAttribute attrib,
+    NvU32 flags)
+{
+    return NvError_NotImplemented;
+}
+
+void NvOsPhysicalMemUnmap(void *ptr, size_t size)
+{
+    NvUPtr va = (NvUPtr)ptr;
+
+    /*  No unmapping required for statically mapped I/O space */
+#define aperture_comp_unmap(_name, _pa, _len)                           \
+    if ((tegra_munge_pa((_pa)) <= va) &&                                \
+        (tegra_munge_pa((_pa))+(_len) >= (va+size)))                    \
+        return;
+
+
+    tegra_apertures(aperture_comp_unmap);
+    iounmap(ptr);
+}
+
+NvError NvOsLibraryLoad(const char *name, NvOsLibraryHandle *library)
+{
+    return NvError_NotImplemented;
+}
+
+void* NvOsLibraryGetSymbol(NvOsLibraryHandle library, const char *symbol)
+{
+    return 0;
+}
+
+void NvOsLibraryUnload(NvOsLibraryHandle library)
+{
+}
+
+void NvOsSleepMS(NvU32 msec)
+{
+    msleep( msec );
+}
+
+void NvOsWaitUS(NvU32 usec)
+{
+    udelay( usec );
+}
+
+typedef struct NvOsMutexRec
+{
+    struct mutex mutex;
+    volatile NvU32 count;
+    volatile struct thread_info *owner;
+} NvOsMutex;
+
+/**
+ * nvos mutexes are recursive.
+ */
+NvError NvOsMutexCreate(NvOsMutexHandle *mutex)
+{
+    NvOsMutex *m;
+
+    m = kzalloc( sizeof(NvOsMutex), GFP_KERNEL );
+    if( !m )
+        return NvError_InsufficientMemory;
+
+    mutex_init( &m->mutex );
+    m->count = 0;
+    m->owner = 0;
+
+    *mutex = m;
+    return NvSuccess;
+}
+
+void NvOsMutexLock(NvOsMutexHandle mutex)
+{
+    struct task_struct *task = current;
+    struct thread_info *info = task_thread_info(task);
+    int ret;
+
+    NV_ASSERT( mutex );
+
+    /* if we own the lock, increment the count and bail out */
+    if( mutex->owner == info )
+    {
+        mutex->count++;
+        return;
+    }
+
+    /* lock as normal, then setup the recursive stuff */
+    do
+    {
+        /*  FIXME: interruptible mutexes may not be necessary, since this
+         *  implementation is only used by the kernel tasks. */
+        ret = mutex_lock_interruptible( &mutex->mutex );
+        //  If a signal arrives while the task is sleeping,
+        //  re-schedule it and attempt to reacquire the mutex
+        if (ret && !try_to_freeze())
+            schedule();
+    } while (ret);
+    mutex->owner = info;
+    mutex->count = 1;
+}
+
+void NvOsMutexUnlock(NvOsMutexHandle mutex)
+{
+    NV_ASSERT( mutex );
+
+    mutex->count--;
+    if( mutex->count == 0 )
+    {
+        /* prevent the same thread from unlocking, then doing a recursive
+         * lock (skip mutex_lock).
+         */
+        mutex->owner = 0;
+
+        mutex_unlock( &mutex->mutex );
+    }
+}
+
+void NvOsMutexDestroy(NvOsMutexHandle mutex)
+{
+
+    if( !mutex )
+        return;
+    kfree( mutex );
+}
+
+typedef struct NvOsIntrMutexRec
+{
+    spinlock_t lock;
+    unsigned long flags;
+} NvOsIntrMutex;
+
+NvError NvOsIntrMutexCreate(NvOsIntrMutexHandle *mutex)
+{
+    NvOsIntrMutex *m;
+
+    m = kzalloc( sizeof(NvOsIntrMutex), GFP_KERNEL );
+    if( !m )
+        return NvError_InsufficientMemory;
+
+    spin_lock_init( &m->lock );
+    *mutex = m;
+    return NvSuccess;
+}
+
+void NvOsIntrMutexLock(NvOsIntrMutexHandle mutex)
+{
+    NV_ASSERT( mutex );
+    spin_lock_irqsave( &mutex->lock, mutex->flags );
+}
+
+void NvOsIntrMutexUnlock(NvOsIntrMutexHandle mutex)
+{
+    NV_ASSERT( mutex );
+    spin_unlock_irqrestore( &mutex->lock, mutex->flags );
+}
+
+void NvOsIntrMutexDestroy(NvOsIntrMutexHandle mutex)
+{
+    if (mutex)
+        kfree(mutex);
+}
+
+typedef struct NvOsSpinMutexRec
+{
+    spinlock_t lock;
+} NvOsSpinMutex;
+
+NvError NvOsSpinMutexCreate(NvOsSpinMutexHandle *mutex)
+{
+    NvOsSpinMutex *m;
+
+    m = kzalloc( sizeof(NvOsSpinMutex), GFP_KERNEL );
+    if( !m )
+        return NvError_InsufficientMemory;
+
+    spin_lock_init( &m->lock );
+    *mutex = m;
+    return NvSuccess;
+}
+
+void NvOsSpinMutexLock(NvOsSpinMutexHandle mutex)
+{
+    NV_ASSERT( mutex );
+    spin_lock( &mutex->lock );
+}
+
+void NvOsSpinMutexUnlock(NvOsSpinMutexHandle mutex)
+{
+    NV_ASSERT( mutex );
+    spin_unlock( &mutex->lock );
+}
+
+void NvOsSpinMutexDestroy(NvOsSpinMutexHandle mutex)
+{
+    if (mutex)
+        kfree(mutex);
+}
+
+typedef struct NvOsSemaphoreRec
+{
+    struct semaphore sem;
+    atomic_t refcount;
+} NvOsSemaphore;
+
+NvError NvOsSemaphoreCreate(
+    NvOsSemaphoreHandle *semaphore,
+    NvU32 value)
+{
+    NvOsSemaphore *s;
+
+    s = kzalloc( sizeof(NvOsSemaphore), GFP_KERNEL );
+    if( !s )
+        return NvError_InsufficientMemory;
+
+    sema_init( &s->sem, value );
+    atomic_set( &s->refcount, 1 );
+
+    *semaphore = s;
+
+    return NvSuccess;
+}
+
+NvError NvOsSemaphoreClone(
+    NvOsSemaphoreHandle orig,
+    NvOsSemaphoreHandle *semaphore)
+{
+    NV_ASSERT( orig );
+    NV_ASSERT( semaphore );
+
+    atomic_inc( &orig->refcount );
+    *semaphore = orig;
+
+    return NvSuccess;
+}
+
+NvError NvOsSemaphoreUnmarshal(
+    NvOsSemaphoreHandle hClientSema,
+    NvOsSemaphoreHandle *phDriverSema)
+{
+    NV_ASSERT( hClientSema );
+    NV_ASSERT( phDriverSema );
+
+    atomic_inc( &hClientSema->refcount );
+    *phDriverSema = hClientSema;
+
+    return NvSuccess;
+}
+
+int NvOsSemaphoreWaitInterruptible(NvOsSemaphoreHandle semaphore);
+int NvOsSemaphoreWaitInterruptible(NvOsSemaphoreHandle semaphore)
+{
+    NV_ASSERT(semaphore);
+
+    return down_interruptible(&semaphore->sem);
+}
+
+void NvOsSemaphoreWait(NvOsSemaphoreHandle semaphore)
+{
+    int ret;
+    
+    NV_ASSERT(semaphore);
+
+    do
+    {
+        /* FIXME: We should split the implementation into two parts -
+         * one for semaphore that were created by users ioctl'ing into
+         * the nvos device (which need down_interruptible), and others that
+         * are created and used by the kernel drivers, which do not */
+        ret = down_interruptible(&semaphore->sem);
+        /* The kernel doesn't reschedule tasks
+         * that have pending signals. If a signal
+         * is pending, forcibly reschedule the task.
+         */
+        if (ret && !try_to_freeze())
+            schedule();
+    } while (ret);
+}
+
+NvError NvOsSemaphoreWaitTimeout(
+    NvOsSemaphoreHandle semaphore,
+    NvU32 msec)
+{
+    int t;
+
+    NV_ASSERT( semaphore );
+
+    if (!semaphore)
+        return NvError_Timeout;
+
+    if (msec==NV_WAIT_INFINITE)
+    {
+        NvOsSemaphoreWait(semaphore);
+        return NvSuccess;
+    }
+    else if (msec==0)
+    {
+        t = down_trylock(&semaphore->sem);
+        if (!t)
+            return NvSuccess;
+        else
+            return NvError_Timeout;
+    }
+
+    /* FIXME:  The kernel doesn't provide an interruptible timed
+     * semaphore wait, which would be preferable for our the ioctl'd
+     * NvOs sempahores. */
+    t = down_timeout(&semaphore->sem, (long)msecs_to_jiffies( msec ));
+
+    if (t == -ETIME)
+        return NvError_Timeout;
+    else if (!t)
+        return NvSuccess;
+
+    return NvError_AccessDenied;
+}
+
+void NvOsSemaphoreSignal(NvOsSemaphoreHandle semaphore)
+{
+    NV_ASSERT( semaphore );
+
+    up( &semaphore->sem );
+}
+
+void NvOsSemaphoreDestroy(NvOsSemaphoreHandle semaphore)
+{
+    if (!semaphore)
+        return;
+
+    if( atomic_dec_return( &semaphore->refcount ) == 0 )
+        kfree( semaphore );
+}
+
+NvError NvOsThreadMode(int coop)
+{
+    return NvError_NotImplemented;
+}
+
+typedef struct NvOsThreadRec
+{
+    struct task_struct *task;
+    NvOsThreadFunction func;
+    void *arg;
+} NvOsThread;
+
+static int thread_wrapper( void *arg )
+{
+    NvOsThread *t = (NvOsThread *)arg;
+    t->func(t->arg);
+    return 0;
+}
+
+static NvError NvOsThreadCreateInternal(
+    NvOsThreadFunction function,
+    void *args,
+    NvOsThreadHandle *thread,
+    NvBool elevatedPriority)
+{
+    NvError e;
+    NvOsThread *t = 0;
+    static NvU32 NvOsKernelThreadIndex = 0;
+    struct sched_param sched;
+    int scheduler;
+    NvU32 ThreadId;
+
+    t = kzalloc( sizeof(NvOsThread), GFP_KERNEL );
+    if( !t )
+    {
+        return NvError_InsufficientMemory;
+    }
+
+    t->func = function;
+    t->arg = args;
+
+    ThreadId = (NvU32)NvOsAtomicExchangeAdd32((NvS32*)&NvOsKernelThreadIndex,1);
+    t->task =
+        kthread_create(thread_wrapper, t, "NvOsKernelThread/%d", ThreadId);
+
+    if(IS_ERR(t->task))
+    {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+
+    if (elevatedPriority)
+    {
+        scheduler = SCHED_FIFO;
+        sched.sched_priority = KTHREAD_IRQ_PRIO+1;
+    }
+    else
+    {
+        scheduler = SCHED_NORMAL;
+        sched.sched_priority = 0;
+    }
+
+    if (sched_setscheduler_nocheck( t->task, scheduler, &sched ) < 0)
+        NvOsDebugPrintf("Failed to set task priority to %d\n",
+            sched.sched_priority);
+    
+    *thread = t;
+    wake_up_process( t->task );
+    e = NvSuccess;
+    goto clean;
+
+fail:
+    kfree( t );
+
+clean:
+    return e;
+}
+
+
+NvError NvOsInterruptPriorityThreadCreate(
+    NvOsThreadFunction function,
+    void *args,
+    NvOsThreadHandle *thread)
+{
+    return NvOsThreadCreateInternal(function, args, thread, NV_TRUE);
+}
+
+NvError NvOsThreadCreate(
+    NvOsThreadFunction function,
+    void *args,
+    NvOsThreadHandle *thread)
+{
+    return NvOsThreadCreateInternal(function, args, thread, NV_FALSE);
+}
+
+NvError NvOsThreadSetLowPriority(void)
+{
+    struct sched_param sched;
+    struct task_struct *curr;
+
+    curr = get_current();
+    sched.sched_priority = 0;
+
+    if (unlikely(!curr))
+        return NvError_NotInitialized;
+
+    if (sched_setscheduler_nocheck( curr, SCHED_IDLE, &sched )<0)
+    {
+        NvOsDebugPrintf("Failed to set low priority for thread %p\n", curr);
+        return NvError_NotSupported;
+    }
+
+    return NvSuccess;
+}
+
+void NvOsThreadJoin(NvOsThreadHandle thread)
+{
+    if (!thread)
+        return;
+
+    (void)kthread_stop(thread->task);
+    kfree(thread);
+}
+
+void NvOsThreadYield(void)
+{
+    schedule();
+}
+
+NvS32 NvOsAtomicCompareExchange32(
+    NvS32 *pTarget,
+    NvS32 OldValue,
+    NvS32 NewValue)
+{
+    return atomic_cmpxchg( (atomic_t *)pTarget, OldValue, NewValue );
+}
+
+NvS32 NvOsAtomicExchange32(NvS32 *pTarget, NvS32 Value)
+{
+    return atomic_xchg( (atomic_t *)pTarget, Value );
+}
+
+NvS32 NvOsAtomicExchangeAdd32(NvS32 *pTarget, NvS32 Value)
+{
+    NvS32 new;
+    new = atomic_add_return( Value, (atomic_t *)pTarget );
+    return new + (-Value);
+}
+
+NvU32 NvOsTlsAlloc(void)
+{
+    return 0;
+}
+
+void NvOsTlsFree(NvU32 TlsIndex)
+{
+}
+
+void *NvOsTlsGet(NvU32 TlsIndex)
+{
+    return 0;
+}
+
+void NvOsTlsSet(NvU32 TlsIndex, void *Value)
+{
+}
+
+NvU32 NvOsGetTimeMS(void)
+{
+    struct timespec ts;
+    s64 nsec;
+    getnstimeofday(&ts);
+    nsec = timespec_to_ns(&ts);
+    do_div(nsec, 1000000);
+    return (NvU32)nsec;
+}
+
+NvU64 NvOsGetTimeUS(void)
+{
+    struct timespec ts;
+    s64 nsec;
+    getnstimeofday(&ts);
+    nsec = timespec_to_ns(&ts);
+    do_div(nsec, 1000);
+    return (NvU32)nsec;
+}
+
+void NvOsDataCacheWritebackRange(
+    void *start,
+    NvU32 length)
+{
+	dmac_map_area(start, length, DMA_TO_DEVICE);
+}
+
+void NvOsDataCacheWritebackInvalidateRange(
+    void *start,
+    NvU32 length)
+{
+    dmac_flush_range(start, (NvU8*)start+length);
+}
+
+void NvOsInstrCacheInvalidate(void)
+{
+}
+
+void NvOsInstrCacheInvalidateRange(
+    void *start,
+    NvU32 length)
+{
+    __cpuc_coherent_kern_range((unsigned long)start,
+         (unsigned long)start+length);
+}
+
+void NvOsFlushWriteCombineBuffer( void )
+{
+    dsb();
+    outer_sync();
+}
+
+NvError NvOsInterruptRegisterInternal(
+    NvU32 IrqListSize,
+    const NvU32 *pIrqList,
+    const void *pList,
+    void* context,
+    NvOsInterruptHandle *handle,
+    NvBool InterruptEnable,
+    NvBool IsUser)
+{
+    const NvOsSemaphoreHandle *pSemList = NULL;
+    const NvOsInterruptHandler *pFnList = NULL;
+    NvError e = NvSuccess;
+    NvOsInterruptBlock *pNewBlock;
+    NvU32 i;
+
+    if (!IrqListSize)
+        return NvError_BadValue;
+
+    if (IsUser)
+        pSemList = (const NvOsSemaphoreHandle *)pList;
+    else
+        pFnList = (const NvOsInterruptHandler *)pList;
+
+    *handle = (NvOsInterruptHandle) 0;
+    pNewBlock = (NvOsInterruptBlock *)NvOsAlloc(INTBLOCK_SIZE(IrqListSize));
+    if (!pNewBlock)
+        return NvError_InsufficientMemory;
+
+    NvOsMemset(pNewBlock, 0, INTBLOCK_SIZE(IrqListSize));
+
+    pNewBlock->pArg = context;
+    pNewBlock->NumIrqs = IrqListSize;
+    pNewBlock->Shutdown = 0;
+    for (i=0; i<IrqListSize; i++)
+    {
+        if (pIrqList[i] >= NVOS_MAX_SYSTEM_IRQS)
+        {
+            BUG();
+            e = NvError_InsufficientMemory;
+            goto clean_fail;
+        }
+
+        if (NvOsAtomicCompareExchange32((NvS32*)&s_pIrqList[pIrqList[i]], 0,
+                (NvS32)pNewBlock)!=0)
+        {
+            e = NvError_AlreadyAllocated;
+            goto clean_fail;
+        }
+        snprintf(pNewBlock->IrqList[i].IrqName, 
+            sizeof(pNewBlock->IrqList[i].IrqName),
+            "NvOsIrq%s%04d", (IsUser)?"User":"Kern", pIrqList[i]);
+
+        pNewBlock->IrqList[i].Irq = pIrqList[i];
+
+        /* HACK use threads for GPIO and tasklets for all other interrupts. */
+        if (IsUser)
+        {
+            pNewBlock->IrqList[i].pSem = pSemList[i];
+            pNewBlock->Flags |= NVOS_IRQ_IS_USER;
+        }
+        else
+        {
+            pNewBlock->IrqList[i].pHandler = pFnList[i];
+            if (pIrqList[i] >= INT_GPIO_BASE)
+                pNewBlock->Flags |= NVOS_IRQ_IS_KERNEL_THREAD;
+            else
+                pNewBlock->Flags |= NVOS_IRQ_IS_TASKLET;
+        }
+    
+        if ((pNewBlock->Flags & NVOS_IRQ_TYPE_MASK)==NVOS_IRQ_IS_KERNEL_THREAD)
+        {
+            struct sched_param p;
+            p.sched_priority = KTHREAD_IRQ_PRIO;
+            sema_init(&(pNewBlock->IrqList[i].sem), 0);
+            pNewBlock->IrqList[i].task = 
+                kthread_create(NvOsInterruptThreadWrapper,
+                    (void *)((pIrqList[i]&0xffff) | ((i&0xffff)<<16)), 
+                    pNewBlock->IrqList[i].IrqName);
+            if (sched_setscheduler(pNewBlock->IrqList[i].task,
+                    SCHED_FIFO, &p)<0)
+                NvOsDebugPrintf("Failed to elevate priority for IRQ %u\n",
+                    pIrqList[i]);
+            wake_up_process( pNewBlock->IrqList[i].task );
+        }
+
+        if ((pNewBlock->Flags & NVOS_IRQ_TYPE_MASK)==NVOS_IRQ_IS_TASKLET)
+        {
+            tasklet_init(&pNewBlock->IrqList[i].Tasklet, NvOsTaskletWrapper,
+                (pIrqList[i]&0xffff) | ((i&0xffff)<<16)); 
+        }
+
+        /* NvOs specifies that the interrupt handler is responsible for
+         * re-enabling the interrupt.  This is not the standard behavior
+         * for Linux IRQs, so only interrupts which are installed through
+         * NvOs will have the no-auto-enable flag specified
+         */
+        set_irq_flags(pIrqList[i], IRQF_VALID | IRQF_NOAUTOEN);
+
+        if (request_irq(pIrqList[i], NvOsIrqWrapper, 
+                0, pNewBlock->IrqList[i].IrqName, (void*)i)!=0)
+        {
+            e = NvError_ResourceError;
+            goto clean_fail;
+        }
+    }
+    *handle = (NvOsInterruptHandle)pNewBlock;
+    if (InterruptEnable)
+    {
+        pNewBlock->Flags |= NVOS_IRQ_IS_ENABLED;
+        i = 0;
+    }
+    for ( ; i<IrqListSize; i++)
+        enable_irq(pIrqList[i]);
+
+    return NvSuccess;
+
+ clean_fail:
+    while (i)
+    {
+        --i;
+        if ((pNewBlock->Flags & NVOS_IRQ_TYPE_MASK)==NVOS_IRQ_IS_KERNEL_THREAD)
+        {
+            up(&pNewBlock->IrqList[i].sem);
+            (void)kthread_stop(pNewBlock->IrqList[i].task);
+        }
+        if ((pNewBlock->Flags & NVOS_IRQ_TYPE_MASK) == NVOS_IRQ_IS_TASKLET)
+        {
+            tasklet_kill(&pNewBlock->IrqList[i].Tasklet); 
+        }
+        free_irq(pIrqList[i], (void*)i);
+        set_irq_flags(pIrqList[i], IRQF_VALID);
+        NvOsAtomicCompareExchange32((NvS32*)&s_pIrqList[pIrqList[i]],
+            (NvS32)pNewBlock, 0);
+    }
+    *handle = NULL;
+    NvOsFree(pNewBlock);
+
+    return e;
+}
+
+NvError NvOsInterruptRegister(
+    NvU32 IrqListSize,
+    const NvU32 *pIrqList,
+    const NvOsInterruptHandler *pIrqHandlerList,
+    void *context,
+    NvOsInterruptHandle *handle,
+    NvBool InterruptEnable)
+{
+    return NvOsInterruptRegisterInternal(IrqListSize, pIrqList,
+               (const void*)pIrqHandlerList, context, handle, 
+               InterruptEnable, NV_FALSE);
+}
+
+void NvOsInterruptUnregister(NvOsInterruptHandle handle)
+{
+    NvOsInterruptBlock *pBlock = (NvOsInterruptBlock *)handle;
+    NvU32 i;
+
+    if (!pBlock)
+        return;
+
+    pBlock->Shutdown = 1;
+
+    for (i=0; i<pBlock->NumIrqs; i++)
+    {
+        free_irq(pBlock->IrqList[i].Irq, (void*)i);
+        NvOsAtomicCompareExchange32(
+            (NvS32*)&s_pIrqList[pBlock->IrqList[i].Irq], (NvS32)pBlock, 0);
+
+        if ((pBlock->Flags & NVOS_IRQ_TYPE_MASK) == NVOS_IRQ_IS_KERNEL_THREAD)
+        {
+            up(&pBlock->IrqList[i].sem);
+            (void)kthread_stop(pBlock->IrqList[i].task);
+        }
+        if ((pBlock->Flags & NVOS_IRQ_TYPE_MASK) == NVOS_IRQ_IS_TASKLET)
+        {
+            tasklet_kill(&pBlock->IrqList[i].Tasklet); 
+        }
+        set_irq_flags(pBlock->IrqList[i].Irq, IRQF_VALID);
+    }
+
+    NvOsFree(pBlock);
+}
+
+NvError NvOsInterruptEnable(NvOsInterruptHandle handle)
+{
+    NvOsInterruptBlock *pBlock = (NvOsInterruptBlock *)handle;
+    NvU32 i;
+
+    if (pBlock == NULL)
+        BUG();
+
+    if (!(pBlock->Flags & NVOS_IRQ_IS_ENABLED))
+    {
+        pBlock->Flags |= NVOS_IRQ_IS_ENABLED;
+        for (i=0; i<pBlock->NumIrqs; i++)
+            enable_irq(pBlock->IrqList[i].Irq);
+    }
+
+    return NvSuccess;
+}
+
+void NvOsInterruptDone(NvOsInterruptHandle handle)
+{
+    NvOsInterruptBlock *pBlock = (NvOsInterruptBlock *)handle;
+    NvU32 i;
+
+    if (pBlock == NULL)
+        BUG();
+
+    for (i=0; i<pBlock->NumIrqs; i++)
+        enable_irq(pBlock->IrqList[i].Irq);
+}
+
+void NvOsInterruptMask(NvOsInterruptHandle handle, NvBool mask)
+{
+    NvOsInterruptBlock *pBlock = (NvOsInterruptBlock *)handle;
+    NvU32 i;
+
+    if (pBlock == NULL)
+        BUG();
+
+    if (mask)
+    {
+        for (i=0; i<pBlock->NumIrqs; i++)
+            disable_irq(pBlock->IrqList[i].Irq);
+    }
+    else
+    {
+        for (i=0; i<pBlock->NumIrqs; i++)
+            enable_irq(pBlock->IrqList[i].Irq);
+    }
+}
+
+void NvOsProfileApertureSizes(NvU32 *apertures, NvU32 *sizes)
+{
+}
+
+void NvOsProfileStart(void **apertures)
+{
+}
+
+void NvOsProfileStop(void **apertures)
+{
+}
+
+NvError NvOsProfileWrite(
+    NvOsFileHandle file, NvU32 index,
+    void *aperture)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsBootArgSet(NvU32 key, void *arg, NvU32 size)
+{
+    return NvError_NotImplemented;
+}
+
+NvError NvOsBootArgGet(NvU32 key, void *arg, NvU32 size)
+{
+    const void *src;
+    NvU32 size_src;
+
+    if (key>=NvBootArgKey_PreservedMemHandle_0 &&
+        key<NvBootArgKey_PreservedMemHandle_Num)
+    {
+        int Index = key - NvBootArgKey_PreservedMemHandle_0;
+
+        src = &s_BootArgs.MemHandleArgs[Index];
+        size_src = sizeof(NvBootArgsPreservedMemHandle);
+    }
+    else
+    {
+        switch (key)
+        {
+        case NvBootArgKey_ChipShmoo:
+            src = &s_BootArgs.ChipShmooArgs;
+            size_src = sizeof(NvBootArgsChipShmoo);
+            break;
+        case NvBootArgKey_Framebuffer:
+            src = &s_BootArgs.FramebufferArgs;
+            size_src = sizeof(NvBootArgsFramebuffer);
+            break;
+        case NvBootArgKey_Display:
+            src = &s_BootArgs.DisplayArgs;
+            size_src = sizeof(NvBootArgsDisplay);
+            break;
+        case NvBootArgKey_Rm:            
+            src = &s_BootArgs.RmArgs;
+            size_src = sizeof(NvBootArgsRm);
+            break;
+        case NvBootArgKey_ChipShmooPhys:
+            src = &s_BootArgs.ChipShmooPhysArgs;
+            size_src = sizeof(NvBootArgsChipShmooPhys);
+            break;
+        case NvBootArgKey_WarmBoot:
+            src = &s_BootArgs.WarmbootArgs;
+            size_src = sizeof(NvBootArgsWarmboot);
+            break;
+        default:
+            src = NULL;
+            size_src = 0;
+            break;
+        }
+    }
+
+    if (!arg || !src || (size_src!=size))
+        return NvError_BadParameter;
+
+    NvOsMemcpy(arg, src, size_src);
+    return NvSuccess;
+}
+
+/** nvassert functions */
+
+void NvOsBreakPoint(const char* file, NvU32 line, const char* condition)
+{
+    printk( "assert: %s:%d: %s\n", file, line, (condition) ? condition : " " );
+    dump_stack();
+}
+
+/** trace functions */
+
+void NvOsTraceLogPrintf( const char *format, ... )
+{
+
+}
+
+void NvOsTraceLogStart(void)
+{
+}
+
+void NvOsTraceLogEnd(void)
+{
+}
+
+/* resource tracking */
+
+#if NV_DEBUG
+void *NvOsAllocLeak( size_t size, const char *f, int l )
+{
+    return NvOsAlloc( size );
+}
+
+void *NvOsReallocLeak( void *ptr, size_t size, const char *f, int l )
+{
+    return NvOsRealloc( ptr, size );
+}
+
+void NvOsFreeLeak( void *ptr, const char *f, int l )
+{
+    NvOsFree( ptr );
+}
+#endif
+
+void NvOsGetProcessInfo(char* buf, NvU32 len)
+{
+	NvOsSnprintf(buf,len, "(kernel pid=%d)", current->pid);
+}
+
+#if (NVOS_TRACE || NV_DEBUG)
+void NvOsSetResourceAllocFileLine(void* userptr, const char* file, int line)
+{
+}
+#endif
+
+#ifdef GHACK
+
+static int __init parse_tegra_tag(const struct tag *tag)
+{
+    const struct tag_nvidia_tegra *nvtag = &tag->u.tegra;
+
+    if (nvtag->bootarg_key >= NvBootArgKey_PreservedMemHandle_0 &&
+        nvtag->bootarg_key < NvBootArgKey_PreservedMemHandle_Num)
+    {
+        int Index = nvtag->bootarg_key - NvBootArgKey_PreservedMemHandle_0;
+        NvBootArgsPreservedMemHandle *dst = &s_BootArgs.MemHandleArgs[Index];
+        const NvBootArgsPreservedMemHandle *src =
+            (const NvBootArgsPreservedMemHandle *)nvtag->bootarg;
+
+        if (nvtag->bootarg_len != sizeof(NvBootArgsPreservedMemHandle))
+            printk("Unexpected preserved memory handle tag length!\n");
+        else
+            *dst = *src;
+        return 0;
+    }
+
+    switch (nvtag->bootarg_key)
+    {
+    case NvBootArgKey_ChipShmoo:
+    {
+        NvBootArgsChipShmoo *dst = &s_BootArgs.ChipShmooArgs;
+        const NvBootArgsChipShmoo *src =
+            (const NvBootArgsChipShmoo *)nvtag->bootarg;
+
+        if (nvtag->bootarg_len != sizeof(NvBootArgsChipShmoo))
+            printk("Unexpected shmoo tag length!\n");
+        else
+        {
+            printk("Shmoo tag with %u handle\n",
+                   src->MemHandleKey);
+            *dst = *src;
+        }
+        return 0;
+    }
+    case NvBootArgKey_Display:
+    {
+        NvBootArgsDisplay *dst = &s_BootArgs.DisplayArgs;
+        const NvBootArgsDisplay *src =
+            (const NvBootArgsDisplay *)nvtag->bootarg;
+
+        if (nvtag->bootarg_len != sizeof(NvBootArgsDisplay))
+            printk("Unexpected display tag length!\n");
+        else
+            *dst = *src;
+        return 0;
+    }
+    case NvBootArgKey_Framebuffer:
+    {
+        NvBootArgsFramebuffer *dst = &s_BootArgs.FramebufferArgs;
+        const NvBootArgsFramebuffer *src =
+            (const NvBootArgsFramebuffer *)nvtag->bootarg;
+
+        if (nvtag->bootarg_len != sizeof(NvBootArgsFramebuffer))
+            printk("Unexpected framebuffer tag length!\n");
+        else
+        {
+            printk("Framebuffer tag with %u handle\n",
+                   src->MemHandleKey);
+            *dst = *src;
+        }
+        return 0;
+    }
+    case NvBootArgKey_Rm:
+    {
+        NvBootArgsRm *dst = &s_BootArgs.RmArgs;
+        const NvBootArgsRm *src =
+            (const NvBootArgsRm *)nvtag->bootarg;
+
+        if (nvtag->bootarg_len != sizeof(NvBootArgsRm))
+            printk("Unexpected RM tag length!\n");
+        else
+            *dst = *src;
+        return 0;
+    }
+    case NvBootArgKey_ChipShmooPhys:
+    {
+        NvBootArgsChipShmooPhys *dst = &s_BootArgs.ChipShmooPhysArgs;
+        const NvBootArgsChipShmooPhys *src =
+            (const NvBootArgsChipShmooPhys *)nvtag->bootarg;
+
+        if (nvtag->bootarg_len != sizeof(NvBootArgsChipShmooPhys))
+            printk("Unexpected phys shmoo tag length!\n");
+        else
+        {
+            printk("Phys shmoo tag with pointer 0x%X and length %u\n",
+                   src->PhysShmooPtr, src->Size);
+            *dst = *src;
+        }
+        return 0;
+    }
+    case NvBootArgKey_WarmBoot:
+    {
+        NvBootArgsWarmboot *dst = &s_BootArgs.WarmbootArgs;
+        const NvBootArgsWarmboot *src =
+            (const NvBootArgsWarmboot *)nvtag->bootarg;
+
+        if (nvtag->bootarg_len != sizeof(NvBootArgsWarmboot))
+            printk("Unexpected warmboot tag length!\n");
+        else
+        {
+            printk("Found a warmboot tag!\n");
+            *dst = *src;
+        }
+        return 0;
+    }
+
+    default:
+        return 0;
+    }
+}
+__tagtable(ATAG_NVIDIA_TEGRA, parse_tegra_tag);
+
+void __init tegra_nvos_kernel_init(void);
+
+void __init tegra_nvos_kernel_init(void)
+{
+    spin_lock_init(&gs_NvOsSpinLock);
+}
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvos/nvustring.c b/arch/arm/mach-tegra/nv/nvos/nvustring.c
new file mode 100644
index 000000000000..cc504dbe8789
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvos/nvustring.c
@@ -0,0 +1,532 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvutil.h"
+#include "nvassert.h"
+
+//===========================================================================
+// NvUIsdigit() - like the standard isdigit function
+//===========================================================================
+static int NvUIsdigit(int c)
+{
+    return (c>='0' && c<='9');
+}
+
+//===========================================================================
+// NvUIsxdigit() - like the standard isxdigit function
+//===========================================================================
+static int NvUIsxdigit(int c)
+{
+    return (c>='0' && c<='9') || (c>='A' && c<='F') || (c>='a' && c<='f');
+}
+
+//===========================================================================
+// NvUCharToXDigit() - convert a hex character to its value
+//===========================================================================
+static int NvUCharToXDigit(int c)
+{
+    return (c>='0' && c<='9') ? c - '0' :
+           (c>='a' && c<='f') ? c - 'a' + 10 :
+           (c>='A' && c<='F') ? c - 'A' + 10 : -1;
+}
+
+//===========================================================================
+// NvUStrtoull() - like the standard strtoull function
+//===========================================================================
+unsigned long long int NvUStrtoull(const char *s, char **endptr, int base)
+{
+    int neg = 0;
+    unsigned long long int val = 0;
+
+    NV_ASSERT(s);
+    NV_ASSERT(base==0 || base==10 || base==16);
+
+    if (*s == '-') {
+        s++;
+        neg = 1;
+    }
+    if (s[0]=='0' && (s[1]=='x' || s[1]=='X')) {
+        if (base == 10) {
+            if (endptr) {
+                *endptr = (char*)s+1;
+                return val;
+            }
+        }
+        s += 2;
+        base = 16;
+    }
+
+    if (base == 16) {
+        while (NvUIsxdigit(*s)) {
+            val <<= 4;
+            val +=  NvUCharToXDigit(*s);
+            s++;
+        }
+    } else {
+        while (NvUIsdigit(*s)) {
+            val *= 10;
+            val += NvUCharToXDigit(*s);
+            s++;
+        }
+    }
+
+    if (endptr) {
+        *endptr = (char*)s;
+    }
+    return neg ? ((~val)+1) : val;
+}
+
+//===========================================================================
+// NvUStrtoul() - like the standard strtoul function
+//===========================================================================
+unsigned long int NvUStrtoul(const char *s, char **endptr, int base)
+{
+    return (unsigned long)NvUStrtoull( s, endptr, base );
+}
+
+//===========================================================================
+// NvUStrtol() - like the standard strtol function
+//===========================================================================
+long int NvUStrtol(const char *s, char **endptr, int base)
+{
+    return (long int)NvUStrtoul(s,endptr,base);
+}
+
+//===========================================================================
+// NvUStrncat() - like the standard strcat function
+//===========================================================================
+void NvUStrncat(char *dest, const char *src, size_t n)
+{
+    while(*dest) dest++;
+    while(*src && n--) {
+        *(dest++) = *(src++);
+    }
+    *dest = 0;
+}
+
+//===========================================================================
+// NvUStrstr() - like the standard strstr function
+//===========================================================================
+char *
+NvUStrstr( const char *str1, const char *str2 )
+{
+    char s2;
+    NvU32 len;
+
+    NV_ASSERT( str1 );
+    NV_ASSERT( str2 );
+    
+    s2 = *str2++;
+
+    // empty string case
+    if (!s2) {
+        return (char *)str1;
+    }
+    
+    len = NvOsStrlen(str2);
+    do {
+        char s1;
+
+        do {
+            s1 = *str1++;
+            if (!s1) {
+                return (char *)0;
+            }
+        } while (s1 != s2);
+    } while (NvOsStrncmp(str1, str2, len) != 0);
+
+    return (char *)(str1 - 1);
+}
+
+//===========================================================================
+// NvUStrlConvertCodePage() - see definition in nvutil.h
+//   Lots of static helper functions to get/put characters in various
+//   code pages.  For reference on the encodings, see:
+//   http://en.wikipedia.org/wiki/Windows-1252
+//   http://en.wikipedia.org/wiki/UTF-8
+//   http://en.wikipedia.org/wiki/UTF-16
+//===========================================================================
+typedef const void* (*StrGetFn)(const void*, NvU32*, size_t*);
+typedef size_t (*StrPutFn)(void*, NvU32);
+
+static const void*
+NvUStr_GetUtf8Coding(const void *pSrc, 
+                     NvU32 *Coding,
+                     size_t *SrcSize)
+{
+    const char *pCh = (const char *)pSrc;
+    NvU32 tmp = 0;
+    NvU8 ch;
+
+    if (!*SrcSize)
+    {
+        *Coding = 0;
+        return pSrc;
+    }
+    else
+    {
+        ch = (NvU8)*pCh++;
+        *SrcSize = *SrcSize-1;
+    }
+
+    if (*SrcSize && (ch & 0x80))
+    {
+        tmp = ((ch>>4) & 0x3);
+        if (tmp)
+          tmp--;
+        tmp = (ch & (0x1f>>tmp));
+        do
+        {
+            ch = (NvU8)*pCh++;
+            tmp<<=6;
+            tmp |= (ch & 0x3f);
+            *SrcSize = *SrcSize - 1;
+        } while (*SrcSize && ((NvU8)*pCh & 0xc0)==0x80);
+
+    }
+    else
+    {
+        tmp = (NvU32)(ch&0x7f);
+    }
+
+    *Coding = tmp;
+    return (const void *)pCh;
+}
+
+static const void*
+NvUStr_GetUtf16Coding(const void *pSrc,
+                      NvU32 *Coding,
+                      size_t *SrcSize)
+{
+    const wchar_t *pCh = (const wchar_t *)pSrc;
+    NvU32 tmp = 0;
+
+    if (*SrcSize<2)
+    {
+        *Coding = 0;
+        *SrcSize = 0;
+        return pSrc;
+    }
+
+    tmp = (NvU32) *pCh++;
+    *SrcSize = *SrcSize - 2;
+
+    if ((*SrcSize>1) && ((tmp & 0xd800UL) == 0xd800UL))
+    {
+        tmp = 0x10000UL + (((tmp & 0x3ff)<<10) | (((NvU32)*pCh++) & 0x3ffUL));
+        *SrcSize = *SrcSize - 2;
+    }
+
+    *Coding = tmp;
+    return (const void *)pCh;
+}
+
+static const NvU16 Windows1252EscapeRemapTable[32] = {
+    0x20AC, 0, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
+    0x2C26, 0x2030, 0x0160, 0x2039, 0x0152, 0, 0x017D, 0,
+    0, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
+    0x02Dc, 0x2122, 0x0161, 0x203A, 0x0153, 0, 0x017E, 0x0178 };
+
+static const void*
+NvUStr_GetWindows1252Coding(const void *pSrc,
+                            NvU32 *Coding,
+                            size_t *SrcSize)
+{
+    //  the following table is used to remap windows-1252 codings 0x80-0x9f to
+    //  the closest unicode codings.  reference:
+    // http://en.wikipedia.org/wiki/Windows-1252
+
+    const char *pCh = (const char *)pSrc;
+    NvU32 tmp;
+    
+    if (!*SrcSize)
+    {
+        *Coding = 0;
+        return pSrc;
+    }
+    tmp = (NvU32)*pCh++;
+    *SrcSize = *SrcSize - 1;
+
+    if (tmp>=0x80 && tmp<0xA0) tmp =
+        (NvU32) Windows1252EscapeRemapTable[tmp-0x80];
+
+    return (const void *) pCh;
+}
+
+static size_t
+NvUStr_PutUtf8Coding(void *pDest,
+                     NvU32 Coding)
+{
+    unsigned int bytes;
+    unsigned int i;
+    unsigned int mask;
+    unsigned int shift;
+    NvU8 *pCh = (NvU8 *)pDest;
+
+    if (Coding < 0x80)
+        bytes = 1;
+    else if (Coding < 0x800UL)
+        bytes = 2;
+    else if (Coding < 0x10000UL)
+        bytes = 3;
+    else
+        bytes = 4;
+
+    if (pCh)
+    {
+        mask = 0x7f;
+        if (bytes>1)
+        {
+            mask >>= bytes;
+        }
+        shift = (bytes-1)*6;
+        i = bytes;
+        while (i--)
+        {
+            *pCh++ = (((~((mask<<1)|1))&0xff) | 
+                         ((Coding>>shift) & mask));
+            shift -= 6;
+            mask = 0x3f;
+        }
+    }
+    
+    return (size_t)bytes;
+}
+
+static size_t
+NvUStr_PutUtf16Coding(void *pDest,
+                      NvU32 Coding)
+
+{
+    size_t bytes = (Coding > 0x10000UL) ? 4 : 2;
+    NvU16 *pCh = (NvU16 *)pDest;
+
+    if (pCh)
+    {
+        if (bytes==4)
+        {
+            Coding -= 0x10000UL;
+            *pCh++ = (NvU16) (0xd800UL | ((Coding>>10)&0x3ffUL));
+            *pCh++ = (NvU16) (0xdb00UL | (Coding & 0x3ffUL));
+        }
+        else
+            *pCh++ = (NvU16) (Coding & 0xffffUL);
+    }
+
+    return bytes;
+}
+
+static size_t
+NvUStr_PutWindows1252Coding(void *pDest,
+                            NvU32 Coding)
+{
+    NvU8 *pCh = (NvU8 *)pDest;
+    unsigned int i;
+
+    if (pCh)
+    {
+        if ((Coding<0x80UL) || ((Coding<0x100UL)&&(Coding>0x9FUL)))
+            *pCh++ = (NvU8)(Coding & 0xff);
+        else
+        {
+            for (i=0; i<32 && (NvU32)Windows1252EscapeRemapTable[i]!=Coding; i++) { }
+            *pCh++ = ((i==32) ? 0x90 : ((0x80+i) & 0xff));
+        }
+    }
+    return 1;
+}
+
+size_t
+NvUStrlConvertCodePage(void *pDest,
+                       size_t DestSize,
+                       NvOsCodePage DestCodePage,
+                       const void *pSrc,
+                       size_t SrcSize,
+                       NvOsCodePage SrcCodePage)
+{
+    StrGetFn GetChar = NULL;
+    StrPutFn PutChar = NULL;
+    char *pStr = (char *)pDest;
+    size_t OutputSize = 0;
+    size_t CodeSize = 0;
+    size_t Remain = SrcSize;
+    NvU32 Coding;
+
+    if (!pSrc)
+        return 0;
+    //  to simplify down-stream code paths, if the source is NULL-terminated
+    //  (SrcSize==0), or the destination is NULL, set the corresponding sizes
+    //  to ~0 (effectively infinite, since memory will be filled before the
+    //  size limit is reached)
+    if (!pDest)
+        DestSize = (size_t)~0;
+    if (!Remain)
+        Remain = (size_t)~0;
+
+    if (DestCodePage == NvOsCodePage_Unknown)
+        DestCodePage = NvOsStrGetSystemCodePage();
+    if (SrcCodePage == NvOsCodePage_Unknown)
+        SrcCodePage = NvOsStrGetSystemCodePage();
+
+    switch (DestCodePage)
+    {
+    case NvOsCodePage_Utf8:
+        PutChar = NvUStr_PutUtf8Coding; break;
+    case NvOsCodePage_Utf16:
+        PutChar = NvUStr_PutUtf16Coding; break;
+    case NvOsCodePage_Windows1252:
+        PutChar = NvUStr_PutWindows1252Coding; break;
+    default:
+        NV_ASSERT(!"Unsupported destination code page");
+        return 0;
+    }
+
+    //  the NULL terminator in Unicode is 0; compute the size of the terminator
+    //  in the destination coding by calling the PutChar routine once with
+    //  coding zero.
+    OutputSize = PutChar(NULL, 0);
+    if (OutputSize > DestSize)
+      return 0;
+
+    switch (SrcCodePage)
+    {
+    case NvOsCodePage_Utf8: GetChar =
+        NvUStr_GetUtf8Coding; break;
+    case NvOsCodePage_Utf16: GetChar =
+        NvUStr_GetUtf16Coding; break;
+    case NvOsCodePage_Windows1252: GetChar =
+        NvUStr_GetWindows1252Coding; break;
+    default:
+        NV_ASSERT(!"Unsupported source code page");
+        return 0;
+    }
+
+    //  optimized path for conversions of the lower 128 ASCII characters
+    if (( (DestCodePage == NvOsCodePage_Utf8) || 
+          (DestCodePage == NvOsCodePage_Windows1252)) &&
+        (SrcCodePage == NvOsCodePage_Utf16))
+    {
+        const NvU16 *pCh = (const NvU16 *)pSrc;
+        while (*pCh && (*pCh<0x80) && (OutputSize < DestSize) && Remain)
+        {
+            if (pStr)
+                *pStr++ = (char)*pCh;
+            OutputSize++;
+            Remain -= 2;
+            pCh++;
+        }
+        pSrc = (const void *)pCh;
+    }
+    else if ((DestCodePage == NvOsCodePage_Utf16) &&
+             ( (SrcCodePage == NvOsCodePage_Utf8) ||
+               (SrcCodePage == NvOsCodePage_Windows1252)))
+    {
+        const NvU8 *pCh = (const NvU8 *)pSrc;
+        wchar_t    *pStrW = (wchar_t *)pStr;
+        while (*pCh && (*pCh<0x80) && (OutputSize < DestSize) && Remain)
+        {
+            if (pStrW)
+                *pStrW++ = (wchar_t)*pCh;
+            OutputSize+=2;
+            Remain--;
+            pCh++;
+        }
+        pStr = (char *)pStrW;
+        pSrc = (const void *)pCh;
+    }
+
+    pSrc = GetChar(pSrc, &Coding, &Remain);
+    //  All the GetChar* functions return a NULL coding when insufficient
+    //  source bytes remain, so we don't need to check it in the loop
+    while (Coding)
+    {
+        CodeSize = PutChar(NULL, Coding);
+        if (pStr)
+        {
+            if ((OutputSize + CodeSize)<=DestSize)
+            {
+                pStr += PutChar(pStr, Coding);
+                OutputSize += CodeSize;
+            }
+            else
+                break;
+        }
+        else
+            OutputSize += CodeSize;
+
+        pSrc = GetChar(pSrc, &Coding, &Remain);
+    }
+    if (pStr)
+    {
+        pStr += PutChar(pStr, 0);
+    }
+
+    return OutputSize;
+}
+
+NvU32
+NvULowestBitSet( NvU32 bits, NvU32 nBits )
+{
+    NvU32 ret = 0;
+
+    if( nBits > 16 )
+    {
+        if( !(bits & 0xffff) )
+        {
+            ret += 16;
+            bits >>= 16;
+        }
+    }
+
+    if( nBits > 8 )
+    {
+        if( !(bits & 0xff) )
+        {
+            ret += 8;
+            bits >>= 8;
+        }
+    }
+
+    if( !(bits & 0xf) )
+    {
+        ret += 4;
+        bits >>= 4;
+    }
+
+    if( !(bits & 0x3) )
+    {
+        ret += 2;
+        bits >>= 2;
+    }
+
+    return ret + ((bits & 1) ? 0 : 1 );
+}
diff --git a/arch/arm/mach-tegra/nv/nvos_user.c b/arch/arm/mach-tegra/nv/nvos_user.c
new file mode 100644
index 000000000000..5532d5b99c22
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvos_user.c
@@ -0,0 +1,552 @@
+/*
+ * arch/arm/mach-tegra/nvos_user.c
+ *
+ * User-land access to NvOs APIs
+ *
+ * Copyright (c) 2008-2009, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/mutex.h>
+#include <linux/proc_fs.h>
+#include <linux/spinlock.h>
+#include <linux/uaccess.h>
+#include <linux/rwsem.h>
+#include <mach/irqs.h>
+#include "nvos.h"
+#include "linux/nvos_ioctl.h"
+#include "nvassert.h"
+
+int nvos_open(struct inode *inode, struct file *file);
+int nvos_close(struct inode *inode, struct file *file);
+static long nvos_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
+int nvos_mmap(struct file *file, struct vm_area_struct *vma);
+int NvOsSemaphoreWaitInterruptible(NvOsSemaphoreHandle semaphore);
+
+#define DEVICE_NAME "nvos"
+
+static const struct file_operations nvos_fops =
+{
+    .owner = THIS_MODULE,
+    .open = nvos_open,
+    .release = nvos_close,
+    .unlocked_ioctl = nvos_ioctl,
+    .mmap = nvos_mmap
+};
+
+static struct miscdevice nvosDevice =
+{
+    .name = DEVICE_NAME,
+    .fops = &nvos_fops,
+    .minor = MISC_DYNAMIC_MINOR,
+};
+
+typedef struct NvOsIrqListNodeRec
+{
+    struct list_head list;
+    NvOsInterruptHandle h;
+} NvOsIrqListNode;
+
+typedef struct NvOsInstanceRec
+{
+    struct rw_semaphore    RwLock;
+    struct vm_area_struct *Vma;
+    NvOsMemRangeParams    *MemRange;
+    struct task_struct    *tsk;
+    spinlock_t             Lock;
+    struct list_head       IrqHandles;
+    int                    pid;
+} NvOsInstance;
+
+static int __init nvos_init( void )
+{
+    int retVal = 0;
+
+    retVal = misc_register(&nvosDevice);
+
+    if (retVal < 0)
+    {
+        printk("nvos init failure\n" );
+    }
+
+    return retVal;    
+}
+
+static void __exit nvos_deinit( void )
+{
+    misc_deregister (&nvosDevice);
+}
+
+int nvos_open(struct inode *inode, struct file *filp)
+{
+    NvOsInstance *Instance = NULL;
+
+    filp->private_data = NULL;
+
+    Instance = NvOsAlloc(sizeof(NvOsInstance));
+    if (!Instance)
+    {
+        printk(KERN_INFO __FILE__ ": nvos_open failed\n");
+        return -ENOMEM;
+    }
+    init_rwsem(&Instance->RwLock);
+    Instance->tsk = current;
+    Instance->pid = current->group_leader->pid;
+    Instance->MemRange = NULL;
+    spin_lock_init(&Instance->Lock);
+    INIT_LIST_HEAD(&Instance->IrqHandles);
+    filp->private_data = (void*)Instance;
+
+    return 0;
+}
+
+int nvos_close(struct inode *inode, struct file *filp)
+{
+    NvOsIrqListNode *LeakedIrq;
+
+    if (filp->private_data)
+    {
+        NvOsInstance *Instance = (NvOsInstance *)filp->private_data;
+        filp->private_data = NULL;
+        while (!list_empty(&Instance->IrqHandles))
+        {
+            LeakedIrq = list_first_entry(&Instance->IrqHandles, 
+                            NvOsIrqListNode, list);
+            list_del_init(&LeakedIrq->list);
+            printk(__FILE__": leaked NvOsInterruptHandle %p\n",
+                LeakedIrq->h);
+            NvOsInterruptUnregister(LeakedIrq->h);
+            NvOsFree(LeakedIrq);
+        }
+
+        if (Instance->MemRange)
+            NvOsFree(Instance->MemRange);
+        NvOsFree(Instance);
+    }
+
+    return 0;
+}
+
+extern NvError NvOsInterruptRegisterInternal(
+    NvU32 IrqListSize,
+    const NvU32 *pIrqList,
+    const void *pIrqHandlerList,
+    void* context,
+    NvOsInterruptHandle *handle,
+    NvBool InterruptEnable,
+    NvBool IsUser);
+
+static int interrupt_op(
+    NvOsInstance *Instance,
+    unsigned int cmd,
+    unsigned long arg)
+{
+    NvOsInterruptOpParams p;
+    NvOsInterruptOpParams *user = (NvOsInterruptOpParams*)arg;
+    NvError e;
+
+    e = NvOsCopyIn(&p, user, sizeof(NvOsInterruptOpParams));
+    if (e != NvSuccess)
+        return -EINVAL;
+
+    switch(cmd) {
+    case NV_IOCTL_INTERRUPT_ENABLE:
+        e = NvOsInterruptEnable((NvOsInterruptHandle)p.handle);
+        break;
+    case NV_IOCTL_INTERRUPT_DONE:
+        NvOsInterruptDone((NvOsInterruptHandle)p.handle);
+        e = NvSuccess;
+        break;
+    case NV_IOCTL_INTERRUPT_UNREGISTER:
+    {
+        NvOsIrqListNode *IrqNode;
+        if (Instance)
+        {
+            e = NvError_CountMismatch;
+            spin_lock(&Instance->Lock);
+            list_for_each_entry(IrqNode, &Instance->IrqHandles, list)
+            {
+                if (IrqNode->h == (NvOsInterruptHandle)p.handle)
+                {
+                    list_del(&IrqNode->list);
+                    NvOsInterruptUnregister(IrqNode->h);
+                    NvOsFree(IrqNode);
+                    e = NvSuccess;
+                    break;
+                }
+            }
+            spin_unlock(&Instance->Lock);
+        }
+        else
+        {
+            NvOsInterruptUnregister((NvOsInterruptHandle)p.handle);
+        }
+        e = NvSuccess;
+        break;
+    }
+    case NV_IOCTL_INTERRUPT_MASK:
+        NvOsInterruptMask((NvOsInterruptHandle)p.handle, 
+            p.arg ? NV_TRUE : NV_FALSE);
+        e = NvSuccess;
+        break;
+    default:
+        return -EINVAL;
+    }
+
+    if (NvOsCopyOut(&user->errCode, &e, sizeof(e))!=NvSuccess)
+        return -EINVAL;
+    return 0;
+}
+
+static int interrupt_register(
+    NvOsInstance *Instance,
+    unsigned long arg)
+{
+    NvOsInterruptRegisterParams k;
+    NvOsInterruptHandle h = NULL;
+    NvError e;
+    NvU32 *irqList = NULL;
+    NvOsSemaphoreHandle *semList = NULL;
+    NvOsIrqListNode *node = NULL;
+
+    e = NvOsCopyIn(&k, (void *)arg, sizeof(NvOsInterruptRegisterParams));
+    if (e!=NvSuccess)
+        return -EINVAL;
+        
+    irqList = NvOsAlloc(k.nIrqs * sizeof(NvU32));
+    semList = NvOsAlloc(k.nIrqs * sizeof(NvOsSemaphoreHandle));
+    node = NvOsAlloc(sizeof(NvOsIrqListNode));
+    if (!node)
+    {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+
+    if (!irqList || !semList)
+    {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+    NV_CHECK_ERROR_CLEANUP(NvOsCopyIn(irqList, k.Irqs, k.nIrqs*sizeof(NvU32)));
+
+    NV_CHECK_ERROR_CLEANUP(
+        NvOsCopyIn(semList, k.SemaphoreList, 
+            k.nIrqs*sizeof(NvOsSemaphoreHandle))
+    );
+
+    /* To ensure that the kernel handle is safely stored in the user-space
+     * wrapper before any interrupts are processed, interrupts must be
+     * registered and enabled in two separate ioctls.
+     */
+    e = NvOsInterruptRegisterInternal(k.nIrqs, irqList, 
+            (const void*)semList, NULL, &h, NV_FALSE, NV_TRUE);
+
+    if (e==NvSuccess && Instance)
+    {
+        spin_lock(&Instance->Lock);
+        node->h = h;
+        list_add_tail(&node->list, &Instance->IrqHandles);
+        spin_unlock(&Instance->Lock);
+    }
+
+fail:
+
+    NvOsFree(irqList);
+    NvOsFree(semList);
+    if (e!=NvSuccess)
+    {
+        NvOsFree(node);
+        h = NULL;
+    }
+
+    k.errCode = e;
+    k.kernelHandle = (NvUPtr)h;
+    e = NvOsCopyOut((void*)arg, &k, sizeof(k));
+
+    return (e==NvSuccess) ? 0 : -EINVAL;
+}
+
+static int sem_unmarshal(unsigned long arg)
+{
+    NvOsSemaphoreUnmarshalParams *p = (NvOsSemaphoreUnmarshalParams *)arg;
+    NvOsSemaphoreUnmarshalParams l;
+    NvError e;
+
+    l.hNew = NULL;
+    e = NvOsCopyIn(&l, p, sizeof(l));
+    if (e!=NvSuccess)
+        return -EINVAL;
+
+    e = NvOsSemaphoreUnmarshal(l.hOrig, &l.hNew);
+    l.Error = e;
+
+    e = NvOsCopyOut(p, &l, sizeof(l));
+    if (e!=NvSuccess)
+    {
+        if (l.hNew)
+            NvOsSemaphoreDestroy(l.hNew);
+        return -EINVAL;
+    }
+    return 0;
+}
+
+static int sem_clone(unsigned long arg)
+{
+    NvOsSemaphoreCloneParams *p = (NvOsSemaphoreCloneParams *)arg;
+    NvOsSemaphoreCloneParams l;
+    NvError e;
+
+    l.hNew = NULL;
+    e = NvOsCopyIn(&l, p, sizeof(l));
+    if (e!=NvSuccess)
+        return -EINVAL;
+
+    e = NvOsSemaphoreClone(l.hOrig, &l.hNew);
+    l.Error = e;
+    e = NvOsCopyOut(p, &l, sizeof(l));
+
+    if (e!=NvSuccess)
+    {
+        if (l.hNew)
+            NvOsSemaphoreDestroy(l.hNew);
+        return -EINVAL;
+    }
+
+    return 0;
+}
+
+static int sem_create(unsigned long arg)
+{
+    NvOsSemaphoreIoctlParams *p = (NvOsSemaphoreIoctlParams *)arg;
+    NvOsSemaphoreIoctlParams l;
+
+    if (NvOsCopyIn(&l, p, sizeof(l))!=NvSuccess)
+        return -EINVAL;
+
+    l.sem = NULL;
+    l.error = NvOsSemaphoreCreate(&l.sem, l.value);
+
+    if (NvOsCopyOut(p, &l, sizeof(l))!=NvSuccess)
+    {
+        if (l.sem)
+            NvOsSemaphoreDestroy(l.sem);
+        return -EINVAL;
+    }
+
+    return 0;
+}
+
+static long nvos_ioctl(struct file *filp,
+    unsigned int cmd, unsigned long arg) {
+    int e = 0;
+    NvError err;
+    NvOsSemaphoreHandle kernelSem;
+    NvOsInstance *Instance = (NvOsInstance *)filp->private_data;
+
+    #define DO_CLEANUP( code ) \
+        do { \
+            err = code; \
+            if( err != NvSuccess ) \
+            { \
+                e = -EINVAL; \
+                goto clean; \
+            } \
+        } while( 0 )
+
+    switch( cmd ) {
+    case NV_IOCTL_SEMAPHORE_CREATE:
+        return sem_create(arg);
+
+    case NV_IOCTL_SEMAPHORE_DESTROY:
+        DO_CLEANUP(
+            NvOsCopyIn( &kernelSem, (void *)arg, sizeof(kernelSem) )
+        );
+
+        NvOsSemaphoreDestroy(kernelSem);
+        break;
+    case NV_IOCTL_SEMAPHORE_CLONE:
+        return sem_clone(arg);
+
+    case NV_IOCTL_SEMAPHORE_UNMARSHAL:
+        return sem_unmarshal(arg);
+
+    case NV_IOCTL_SEMAPHORE_SIGNAL:
+        DO_CLEANUP(
+            NvOsCopyIn( &kernelSem, (void *)arg, sizeof(kernelSem) )
+        );
+
+        NvOsSemaphoreSignal(kernelSem);
+        break;           
+    case NV_IOCTL_SEMAPHORE_WAIT:
+        DO_CLEANUP(
+            NvOsCopyIn( &kernelSem, (void *)arg, sizeof(kernelSem) )
+        );
+        e = NvOsSemaphoreWaitInterruptible(kernelSem);
+        break;
+    case NV_IOCTL_SEMAPHORE_WAIT_TIMEOUT:
+    {
+        NvOsSemaphoreIoctlParams *p = (NvOsSemaphoreIoctlParams *)arg;
+        NvOsSemaphoreIoctlParams k;
+
+        DO_CLEANUP(
+            NvOsCopyIn( &k, p, sizeof(k) )
+        );
+
+        if (k.value == NV_WAIT_INFINITE)
+        {
+            k.error = NvSuccess;
+            e = NvOsSemaphoreWaitInterruptible(kernelSem);
+        }
+        else
+        {
+            k.error = NvOsSemaphoreWaitTimeout(k.sem, k.value);
+        }
+
+        DO_CLEANUP(
+            NvOsCopyOut( &p->error, &k.error, sizeof(k.error) )
+        );
+
+        break;
+    }
+    case NV_IOCTL_INTERRUPT_REGISTER:
+        lock_kernel();
+        e = interrupt_register(Instance, arg);
+        unlock_kernel();
+        return e;
+
+    case NV_IOCTL_INTERRUPT_UNREGISTER:
+    case NV_IOCTL_INTERRUPT_DONE:
+    case NV_IOCTL_INTERRUPT_ENABLE:
+    case NV_IOCTL_INTERRUPT_MASK:
+        lock_kernel();
+        e = interrupt_op(Instance, cmd, arg);
+        unlock_kernel();
+        return (e) ? -EINVAL : 0;
+
+    case NV_IOCTL_MEMORY_RANGE:
+    {
+        NvOsMemRangeParams *p;
+
+        p = NvOsAlloc( sizeof(NvOsMemRangeParams) );
+        if( !p )
+        {
+            e = -ENOMEM;
+            goto clean;
+        }
+
+        DO_CLEANUP(
+            NvOsCopyIn( p, (void *)arg, sizeof(NvOsMemRangeParams) );
+        );
+
+        if (!Instance)
+            printk(KERN_INFO __FILE__"(%d): No instance!\n", __LINE__);
+
+        if (Instance)
+        {
+            down_write(&Instance->RwLock);
+            Instance->MemRange = p;
+            up_write(&Instance->RwLock);
+        }
+        return 0;
+    }
+    default:
+        pr_err("Unknown IOCTL: %x\n", _IOC_NR(cmd));
+        e = -1;
+    }
+
+    #undef DO_CLEANUP
+
+clean:
+    return e;
+}
+
+static void nvos_vma_open (struct vm_area_struct *vma)
+{
+}
+
+static void nvos_vma_close (struct vm_area_struct *vma)
+{
+}
+
+static struct vm_operations_struct nvos_vm_ops =
+{
+    .open = nvos_vma_open,
+    .close = nvos_vma_close,
+};
+
+int nvos_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+    unsigned long addr;
+    unsigned long size;
+    unsigned long pfn;
+    NvOsInstance *Instance = (NvOsInstance *)filp->private_data;
+
+    size = vma->vm_end - vma->vm_start;
+    pfn = vma->vm_pgoff;
+    addr = pfn << PAGE_SHIFT;
+
+    if (!Instance)
+        printk(KERN_INFO __FILE__"(%d): No instance!\n", __LINE__);
+
+    if (Instance)
+    {
+        down_read(&Instance->RwLock);
+        if (Instance->MemRange)
+        {
+            /* addr is an offset */
+            if( size > Instance->MemRange->size )
+            {
+                printk( "nvos_mmap: size too big for restricted mapping: %lu "
+                        "max %lu\n", size,
+                        (unsigned long)Instance->MemRange->size );
+                up_read(&Instance->RwLock);
+                return -EAGAIN;
+            }
+            addr += Instance->MemRange->base;
+            pfn = addr >> PAGE_SHIFT;
+        }
+        up_read(&Instance->RwLock);
+    }
+
+    vma->vm_flags |= (VM_IO | VM_DONTCOPY | VM_DONTEXPAND);
+
+    // FIXME: This is a major hack
+#ifdef CONFIG_ARCH_TEGRA_A9
+    if (addr < 0x40000000UL)
+        vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+    else
+#endif
+        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
+
+    if (io_remap_pfn_range(vma, vma->vm_start, pfn, size, vma->vm_page_prot))
+    {
+        printk( "nvos_mmap failed\n" );
+        return -EAGAIN;
+    }
+
+    vma->vm_ops = &nvos_vm_ops;
+    vma->vm_private_data = Instance;
+
+    return 0;
+}
+
+module_init(nvos_init);
+module_exit(nvos_deinit);
diff --git a/arch/arm/mach-tegra/nv/nvreftrack/Makefile b/arch/arm/mach-tegra/nv/nvreftrack/Makefile
new file mode 100644
index 000000000000..11127470828f
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvreftrack/Makefile
@@ -0,0 +1,12 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/nv/include
+
+obj-y += nvreftrack.o
diff --git a/arch/arm/mach-tegra/nv/nvreftrack/nvreftrack.c b/arch/arm/mach-tegra/nv/nvreftrack/nvreftrack.c
new file mode 100644
index 000000000000..3f7829036b14
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvreftrack/nvreftrack.c
@@ -0,0 +1,643 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvreftrack.h"
+#include "nvos.h"
+#include "nvassert.h"
+
+#define NVRT_MAX_PACKAGES              8
+#define NVRT_MAX_OBJ_TYPES_PER_PACKAGE 8
+#define NVRT_CLIENT_SIZE_INCR          16
+#define NVRT_OBJ_SIZE_INCR             128
+
+typedef struct
+{
+    // linked list next ptr (live and free objects)
+    NvU32           NextObj;
+    // the opaque ptr identifier of the object 
+    void*           Ptr;
+} NvRtObj;
+
+typedef struct
+{
+    union
+    {
+        // linked list next ptr for free list, -1 == none
+        NvU32       NextFree;
+        // in use client refcount, -1 == cleaning up
+        NvS32       RefCount;
+    } State;
+    
+    void*           UserData;
+    
+    // lists of objects per obj type. array size can't
+    // be determined compile time so this is not declared
+    //NvU32           Objs[];
+} NvRtClient;
+
+typedef struct NvRtRec
+{
+    NvOsMutexHandle Mutex;
+
+    NvU32           NumPackages;
+    NvU32           MaxTypesPerPkg;
+    NvU32*          ObjTypeIdxLUT;
+    NvU32           NumObjTypes;
+    
+    NvU8*           ClientArr;
+    NvU32           ClientArrSize;
+    NvU32           FreeClientList;
+
+    NvRtObj*        ObjArr;
+    NvU32           ObjArrSize;
+    NvU32           FreeObjList;
+} NvRt;
+
+static NV_INLINE NvU32
+NvRtClientSize(NvRt* Rt)
+{
+    return sizeof(NvRtClient) + Rt->NumObjTypes*sizeof(NvU32);
+}
+
+static NV_INLINE NvRtClient*
+GetClient(NvRt* Rt, NvU32 Idx)
+{
+    void* ptr = (void*)(Rt->ClientArr + Idx*NvRtClientSize(Rt));
+    return (NvRtClient*)ptr;
+}
+
+static NV_INLINE NvU32
+GetObjTypeIdx(NvRt* Rt, NvU32 Package, NvU32 Type)
+{
+    NvU32 LutIdx = Package*Rt->MaxTypesPerPkg + Type;
+    NvU32 Idx;
+
+    Idx = Rt->ObjTypeIdxLUT[LutIdx];
+    NV_ASSERT(Idx != (NvU32)-1);
+
+    return Idx;
+}
+
+static NV_INLINE NvU32*
+GetObjListHead(NvRt* Rt, NvU32 ClientIdx, NvU32 ObjIdx)
+{
+    NvRtClient* Client = GetClient(Rt, ClientIdx);
+    NvU32* Objs = (NvU32*)(Client + 1);
+    return Objs + ObjIdx;
+}
+
+// Temporary wrapper for realloc as the linux kernel nvos doesn't
+// implement NvOsRealloc
+static NV_INLINE void*
+NvRtRealloc(void* old, size_t size, size_t oldsize)
+{
+#if NVOS_IS_LINUX_KERNEL
+    void* ret;
+    
+    if (!size)
+    {
+        if (old) NvOsFree(old);
+        return NULL;
+    }
+
+    ret = NvOsAlloc(size);
+    
+    if (ret && old)
+    {
+        NV_ASSERT(oldsize > 0);
+
+        NvOsMemcpy(ret, old, NV_MIN(size, oldsize));
+        NvOsFree(old);
+    }
+
+    return ret;
+#else
+    return NvOsRealloc(old, size);
+#endif
+}
+
+NvError NvRtCreate(
+    NvU32 NumPackages,
+    const NvU32* NumObjTypesPerPackage,
+    NvRtHandle* RtOut)
+{
+    NvRtHandle Ctx;
+    NvU32 i;
+
+    if (NumPackages == 0)
+    {
+        NV_ASSERT(!"Zero packages is not allowed");
+        return NvError_BadParameter;
+    }
+    
+    if (NumPackages > NVRT_MAX_PACKAGES)
+    {
+        NV_ASSERT(!"NumPackages exceeds NVRT_MAX_PACKAGES");
+        return NvError_BadParameter;
+    }
+    
+    Ctx = NvOsAlloc(sizeof(NvRt));
+    if (!Ctx) return NvError_InsufficientMemory;
+    NvOsMemset(Ctx, 0, sizeof(NvRt));
+
+    Ctx->FreeClientList = -1;    
+    Ctx->FreeObjList    = -1;
+    Ctx->NumPackages    = NumPackages;
+        
+    for (i = 0; i < NumPackages; i++)
+    {
+        if (NumObjTypesPerPackage[i] >
+            NVRT_MAX_OBJ_TYPES_PER_PACKAGE)
+        {
+            NV_ASSERT(!"Too many object types");
+            NvOsFree(Ctx);
+            return NvError_BadParameter;
+        }
+
+        Ctx->NumObjTypes += NumObjTypesPerPackage[i];
+
+        if (NumObjTypesPerPackage[i] > Ctx->MaxTypesPerPkg)
+            Ctx->MaxTypesPerPkg = NumObjTypesPerPackage[i];
+    }
+
+    if (Ctx->MaxTypesPerPkg)
+    {
+        NvU32 idx = 0;
+        
+        Ctx->ObjTypeIdxLUT = NvOsAlloc(sizeof(NvU32)*Ctx->MaxTypesPerPkg*NumPackages);
+        if (!Ctx->ObjTypeIdxLUT)
+        {
+            NvOsFree(Ctx);
+            return NvError_InsufficientMemory;
+        }
+
+        for (i = 0; i < NumPackages; i++)
+        {
+            NvU32 start = i*Ctx->MaxTypesPerPkg;
+            NvU32 j = 0;
+
+            for (; j < NumObjTypesPerPackage[i]; j++)
+            {
+                Ctx->ObjTypeIdxLUT[start+j] = idx++;
+            }
+            for (; j < Ctx->MaxTypesPerPkg; j++)
+            {
+                Ctx->ObjTypeIdxLUT[start+j] = (NvU32)-1;
+            }
+        }
+    }        
+    
+    if (NvOsMutexCreate(&Ctx->Mutex) != NvSuccess)
+    {
+        NvOsFree(Ctx->ObjTypeIdxLUT);
+        NvOsFree(Ctx);
+        return NvError_InsufficientMemory;
+    }
+    
+    *RtOut = Ctx;
+    return NvSuccess;
+}
+
+void NvRtDestroy(NvRtHandle Rt)
+{
+    NvOsMutexDestroy(Rt->Mutex);
+    NvOsFree(Rt->ObjTypeIdxLUT);
+    NvOsFree(Rt);
+}
+
+NvError NvRtRegisterClient(
+    NvRtHandle Rt,
+    NvRtClientHandle* ClientOut)
+{
+    NvOsMutexLock(Rt->Mutex);
+    
+    // Allocate new clients if necessary
+    
+    if (Rt->FreeClientList == -1)
+    {
+        NvU8* NewArr;
+        NvU32 NewSize;
+        NvU32 i;
+        
+        // Grow array by increment
+
+        NewSize = Rt->ClientArrSize + NVRT_CLIENT_SIZE_INCR;
+        NewArr = NvRtRealloc(Rt->ClientArr,
+                             NvRtClientSize(Rt)*NewSize,
+                             NvRtClientSize(Rt)*Rt->ClientArrSize);
+        if (NewArr == NULL)
+        {
+            NvOsMutexUnlock(Rt->Mutex);
+            return NvError_InsufficientMemory;
+        }
+        Rt->ClientArr = NewArr;
+
+        // Initialize new clients and create free list
+
+        for (i = Rt->ClientArrSize; i < NewSize; i++)
+        {
+            NvRtClient* c = GetClient(Rt, i);
+            NvU32* objs = (NvU32*)(c+1);
+            NvU32 j;
+
+            c->State.NextFree = (i == NewSize-1) ? -1 : i+1;
+
+            for (j = 0; j < Rt->NumObjTypes; j++)
+                objs[j] = -1;            
+        }
+                    
+        Rt->FreeClientList = Rt->ClientArrSize;
+        Rt->ClientArrSize = NewSize;
+    }
+
+    NV_ASSERT(Rt->FreeClientList != -1);
+
+    {
+        NvU32       ClientIdx = Rt->FreeClientList;
+        NvRtClient* Client    = GetClient(Rt, ClientIdx);
+    
+        Rt->FreeClientList = Client->State.NextFree;
+
+        NvOsMutexUnlock(Rt->Mutex);
+
+        // Initialize client
+        
+        Client->State.RefCount = 1;
+        Client->UserData = NULL;
+    
+        *ClientOut = ClientIdx + 1;
+    }
+
+    return NvSuccess;
+}
+
+NvError NvRtAddClientRef(
+    NvRtHandle Rt,
+    NvRtClientHandle ClientHandle)
+{
+    NvRtClient* Client;
+    NvU32       ClientIdx = ClientHandle - 1;
+    NvError     Ret = NvSuccess;
+
+    NV_ASSERT(ClientHandle != 0);
+    NV_ASSERT(ClientHandle <= Rt->ClientArrSize);
+
+    NvOsMutexLock(Rt->Mutex);
+
+    Client = GetClient(Rt, ClientIdx);
+
+    if (Client->State.RefCount < 1)
+        Ret = NvError_InvalidState;
+    else
+        Client->State.RefCount++;
+
+    NvOsMutexUnlock(Rt->Mutex);
+
+    return Ret;
+}
+
+NvBool NvRtUnregisterClient(
+    NvRtHandle Rt,
+    NvRtClientHandle ClientHandle)
+{
+    NvRtClient* Client;
+    NvU32       ClientIdx = ClientHandle - 1;
+    NvU32*      Objs;
+    NvU32       i;
+
+    NV_ASSERT(ClientHandle != 0);
+    NV_ASSERT(ClientHandle <= Rt->ClientArrSize);
+
+    NvOsMutexLock(Rt->Mutex);
+
+    Client = GetClient(Rt, ClientIdx);
+    Client->State.RefCount--;
+    
+    if (Client->State.RefCount >= 0)
+    {
+        NvBool DoClean = (Client->State.RefCount == 0);
+        NvOsMutexUnlock(Rt->Mutex);
+        return DoClean;
+    }    
+
+    Objs = (NvU32*)(Client+1);
+
+    // Check that object references are free'd
+    
+    for (i = Rt->NumObjTypes; i != 0; i--)
+    {
+        NvU32 Idx = i - 1;
+        NvU32 Cur = Objs[Idx];
+
+        // The caller should free all object referenced before
+        // unregistering. Assert that this is so.
+        
+        NV_ASSERT(Cur == -1 || !"Leaked object reference");
+
+        // In release builds free at least our state for the leaked
+        // objects. There's nothing we can do about the leaked objects.
+        
+        while (Cur != -1)
+        {
+            NvRtObj* Obj = &Rt->ObjArr[Cur];
+            NvU32 Next = Obj->NextObj;
+
+            Obj->NextObj = Rt->FreeObjList;
+            Rt->FreeObjList = Cur;
+            Cur = Next;
+        }
+
+        Objs[Idx] = -1;
+    }
+
+    // Release client
+
+    Client->State.NextFree = Rt->FreeClientList;
+    Rt->FreeClientList = ClientIdx;
+
+    NvOsMutexUnlock(Rt->Mutex);
+
+    return NV_FALSE;
+}
+
+void NvRtSetClientUserData(
+    NvRtHandle Rt,
+    NvRtClientHandle ClientHandle,
+    void* UserData)
+{
+    NvRtClient* Client;
+    NvU32       ClientIdx = ClientHandle - 1;
+
+    NV_ASSERT(ClientHandle != 0);
+    NV_ASSERT(ClientHandle <= Rt->ClientArrSize);
+
+    NvOsMutexLock(Rt->Mutex);
+
+    Client = GetClient(Rt, ClientIdx);
+    Client->UserData = UserData;
+    
+    NvOsMutexUnlock(Rt->Mutex);
+}
+
+void* NvRtGetClientUserData(
+    NvRtHandle Rt,
+    NvRtClientHandle ClientHandle)
+{
+    NvRtClient* Client;
+    NvU32       ClientIdx = ClientHandle - 1;
+    void*       UserData;
+
+    NV_ASSERT(ClientHandle != 0);
+    NV_ASSERT(ClientHandle <= Rt->ClientArrSize);
+
+    NvOsMutexLock(Rt->Mutex);
+
+    Client = GetClient(Rt, ClientIdx);
+    UserData = Client->UserData;
+    
+    NvOsMutexUnlock(Rt->Mutex);
+
+    return UserData;
+}
+
+NvError NvRtAllocObjRef(
+    const NvDispatchCtx* Ctx,
+    NvRtObjRefHandle* Out)
+{
+    NvRt*    Rt = Ctx->Rt;
+    NvU32    ObjIdx;
+    NvRtObj* Obj;
+    
+    NvOsMutexLock(Rt->Mutex);
+
+    // Allocate new space if necessary
+    
+    if (Rt->FreeObjList == -1)
+    {
+        NvRtObj* NewArr;
+        NvRtObj* Cur;
+        NvU32 NewSize;
+        NvU32 i;
+        
+        // Grow array by increment
+
+        NewSize = Rt->ObjArrSize + NVRT_OBJ_SIZE_INCR;
+        NewArr = NvRtRealloc(Rt->ObjArr,
+                             sizeof(NvRtObj)*NewSize,
+                             sizeof(NvRtObj)*Rt->ObjArrSize);
+        if (NewArr == NULL)
+        {
+            NvOsMutexUnlock(Rt->Mutex);
+            return NvError_InsufficientMemory;
+        }
+
+        // Create free list
+
+        Cur = NewArr + Rt->ObjArrSize;
+        for (i = Rt->ObjArrSize + 1; i < NewSize; i++)
+        {
+            Cur->NextObj = i;
+            Cur++;
+        }
+        Cur->NextObj = -1;
+            
+        // Store new values
+        
+        Rt->ObjArr = NewArr;
+        Rt->FreeObjList = Rt->ObjArrSize;
+        Rt->ObjArrSize = NewSize;
+    }
+
+    NV_ASSERT(Rt->FreeObjList != -1);
+    
+    ObjIdx = Rt->FreeObjList;
+    Obj = &Rt->ObjArr[ObjIdx];
+    Rt->FreeObjList = Obj->NextObj;
+            
+    Obj->NextObj = -1;
+    Obj->Ptr = NULL;
+
+    NvOsMutexUnlock(Rt->Mutex);
+
+    *Out = ObjIdx + 1;
+    return NvSuccess;
+}
+
+void NvRtDiscardObjRef(
+    const NvDispatchCtx* Ctx,
+    NvRtObjRefHandle ObjRef)
+{
+    NvRt* Rt = Ctx->Rt;
+    NvRtObj* Obj;
+
+    if (!ObjRef--) return;
+    
+    NvOsMutexLock(Rt->Mutex);
+
+    Obj = &Rt->ObjArr[ObjRef];
+
+    NV_ASSERT(Obj->NextObj == -1);
+    NV_ASSERT(Obj->Ptr == NULL);
+
+    Obj->NextObj = Rt->FreeObjList;
+    Rt->FreeObjList = ObjRef;
+
+    NvOsMutexUnlock(Rt->Mutex);
+}
+
+void NvRtStoreObjRef(
+    const NvDispatchCtx* Ctx,
+    NvRtObjRefHandle ObjRef,
+    NvU32 ObjType,
+    void* ObjPtr)
+{
+    NvRt*    Rt         = Ctx->Rt;
+    NvU32    ClientIdx  = Ctx->Client - 1;
+    NvU32    ObjTypeIdx = GetObjTypeIdx(Rt, Ctx->PackageIdx, ObjType);
+    NvRtObj* Obj;
+    NvU32*   List;
+
+    NV_ASSERT(ClientIdx < Rt->ClientArrSize);
+
+    if (ObjPtr == NULL)
+    {
+        NV_ASSERT(!"Bad object ptr");
+        return;
+    }
+    
+    if (!ObjRef--)
+    {
+        NV_ASSERT(!"Bad object ref handle");
+        return;
+    }
+        
+    NvOsMutexLock(Rt->Mutex);
+
+    Obj = &Rt->ObjArr[ObjRef];
+
+    NV_ASSERT(Obj->NextObj == -1);
+    NV_ASSERT(Obj->Ptr == NULL);
+
+    List = GetObjListHead(Rt, ClientIdx, ObjTypeIdx);
+
+    Obj->NextObj = *List;
+    Obj->Ptr = ObjPtr;
+
+    *List = ObjRef;    
+
+    NvOsMutexUnlock(Rt->Mutex);    
+}
+
+void* NvRtFreeObjRef(
+    const NvDispatchCtx* Ctx,
+    NvU32 ObjType,
+    void* ObjPtr)
+{
+    NvRt*  Rt         = Ctx->Rt;
+    NvU32  ClientIdx  = Ctx->Client - 1;
+    NvU32  ObjTypeIdx = GetObjTypeIdx(Rt, Ctx->PackageIdx, ObjType);
+    NvU32  PrevIdx;
+    NvU32  CurIdx;
+    NvU32* List;
+    void*  RetVal     = NULL;
+
+    NV_ASSERT(ClientIdx < Rt->ClientArrSize);
+    
+    NvOsMutexLock(Rt->Mutex);
+
+    List = GetObjListHead(Rt, ClientIdx, ObjTypeIdx);
+    CurIdx = *List;
+    PrevIdx = -1;
+
+    // If user requested to find a specific object look it up
+    
+    if (ObjPtr != NULL)
+    {
+        while (CurIdx != -1)
+        {
+            NvRtObj* Obj = &Rt->ObjArr[CurIdx];
+
+            if (Obj->Ptr == ObjPtr) break;
+
+            PrevIdx = CurIdx;
+            CurIdx = Obj->NextObj;
+        }
+
+        // User should not ask to free non-existent objects
+        
+        if (CurIdx == -1)
+        {
+            NV_ASSERT(!"Trying to free non-existent object reference");
+            NvOsMutexUnlock(Rt->Mutex);
+            return NULL;
+        }                
+    }
+
+    // If we have an object, free it
+
+    if (CurIdx != -1)
+    {
+        NvRtObj* Obj = &Rt->ObjArr[CurIdx];
+
+        RetVal = Obj->Ptr;
+        
+        if (PrevIdx == -1)
+        {
+            *List = Obj->NextObj;
+        }
+        else
+        {            
+            NvRtObj* PrevObj = &Rt->ObjArr[PrevIdx];
+            PrevObj->NextObj = Obj->NextObj;
+        }
+
+        Obj->Ptr = NULL;
+        Obj->NextObj = Rt->FreeObjList;
+        Rt->FreeObjList = CurIdx;        
+    }
+    
+    NvOsMutexUnlock(Rt->Mutex);
+
+    return RetVal;
+}
+
+#include <linux/module.h>
+
+EXPORT_SYMBOL(NvRtAllocObjRef);
+EXPORT_SYMBOL(NvRtDiscardObjRef);
+EXPORT_SYMBOL(NvRtFreeObjRef);
+EXPORT_SYMBOL(NvRtStoreObjRef);
+
+EXPORT_SYMBOL(NvRtCreate);
+EXPORT_SYMBOL(NvRtDestroy);
+EXPORT_SYMBOL(NvRtRegisterClient);
+EXPORT_SYMBOL(NvRtUnregisterClient);
diff --git a/arch/arm/mach-tegra/nv/nvrm/Makefile b/arch/arm/mach-tegra/nv/nvrm/Makefile
new file mode 100644
index 000000000000..54d839bae119
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/Makefile
@@ -0,0 +1,20 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+obj-y += core/
+#obj-y += core/ap20/
+#obj-y += core/common/
+
+#obj-y += io/common/
+#obj-y += io/ap15/
+#obj-y += io/ap20/
+
+
+
+obj-y += dispatch/
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/Makefile b/arch/arm/mach-tegra/nv/nvrm/core/Makefile
new file mode 100644
index 000000000000..716418630a1f
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/Makefile
@@ -0,0 +1,12 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+ccflags-y += -Iarch/arm/mach-tegra/nv/include
+
+obj-y += ap15/
+obj-y += common/
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/Makefile b/arch/arm/mach-tegra/nv/nvrm/core/ap15/Makefile
new file mode 100644
index 000000000000..b5e63bd493e1
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/Makefile
@@ -0,0 +1,16 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+ccflags-y += -Iarch/arm/mach-tegra/nv/include
+ccflags-y += -Iarch/arm/mach-tegra/nv/nvrm/core/common
+ccflags-y += -Iarch/arm/mach-tegra/nv/nvrm/core
+
+#obj-y += ap15rm_init.o
+obj-y += ap15rm_avp_service.o
+obj-y += ap15rm_xpc.o
+obj-y += ap15rm_xpc_hw_private.o
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_avp_service.c b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_avp_service.c
new file mode 100644
index 000000000000..64a220fb0a4d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_avp_service.c
@@ -0,0 +1,350 @@
+/*
+ * arch/arm/mach-tegra/nvrm/core/ap15/ap15rm_avp_service.c
+ *
+ * AVP service to handle AVP messages.
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *              Testcases for the xpc </b>
+ *
+ * @b Description: This file implements the AVP service to handle AVP messages.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/string.h>
+#include <linux/miscdevice.h>
+#include <linux/fs.h>
+#include <linux/firmware.h>
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/nvmap.h>
+
+#include "../../../../../../../drivers/video/tegra/nvmap/nvmap.h"
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_init.h"
+#include "nvrm_message.h"
+#include "nvrm_rpc.h"
+#include "nvrm_moduleloader_private.h"
+#include "nvrm_graphics_private.h"
+#include "ap15/arres_sema.h"
+#include "ap15/arflow_ctlr.h"
+#include "ap15/arapbpm.h"
+#include "nvrm_avp_swi_registry.h"
+#include "ap15/arevp.h"
+#include "nvrm_hardware_access.h"
+#include "mach/io.h"
+#include "mach/iomap.h"
+
+extern struct nvmap_client *s_AvpClient;
+
+#define NV_USE_AOS 1
+
+static void HandleCreateMessage(const NvRmMessage_HandleCreat *req,
+                                NvRmMessage_HandleCreatResponse *resp)
+{
+    struct nvmap_handle_ref *ref;
+
+    resp->msg = NvRmMsg_MemHandleCreate_Response;
+    ref = nvmap_create_handle(s_AvpClient, req->size);
+    if (IS_ERR(ref)) {
+        pr_err("[AVP] error creating handle %ld\n", PTR_ERR(ref));
+        resp->error = NvError_InsufficientMemory;
+    } else {
+        resp->error = NvSuccess;
+        resp->hMem = (NvRmMemHandle)nvmap_ref_to_id(ref);
+    }
+}
+
+static void HandleAllocMessage(const NvRmMessage_MemAlloc *req, NvRmMessage_Response *resp)
+{
+    struct nvmap_handle *handle;
+    unsigned int heap_mask = 0;
+    unsigned int i;
+    size_t align;
+    int err;
+
+    resp->msg = NvRmMsg_MemAlloc_Response;
+
+    if (!req->NumHeaps)
+        heap_mask = NVMAP_HEAP_CARVEOUT_GENERIC | NVMAP_HEAP_SYSMEM;
+
+    for (i = 0; i < req->NumHeaps; i++) {
+        if (req->Heaps[i] == NvRmHeap_GART)
+            heap_mask |= NVMAP_HEAP_IOVMM;
+        else if (req->Heaps[i] == NvRmHeap_IRam)
+            heap_mask |= NVMAP_HEAP_CARVEOUT_IRAM;
+        else if (req->Heaps[i] == NvRmHeap_External)
+            heap_mask |= NVMAP_HEAP_SYSMEM;
+        else if (req->Heaps[i] == NvRmHeap_ExternalCarveOut)
+            heap_mask |= NVMAP_HEAP_CARVEOUT_GENERIC;
+    }
+
+    handle = nvmap_get_handle_id(s_AvpClient, (unsigned long)req->hMem);
+    if (IS_ERR(handle)) {
+        resp->error = NvError_AccessDenied;
+        return;
+    }
+
+    align = max_t(size_t, L1_CACHE_BYTES, req->Alignment);
+    err = nvmap_alloc_handle_id(s_AvpClient, (unsigned long)req->hMem,
+                                heap_mask, align, 0);
+    nvmap_handle_put(handle);
+
+    if (err) {
+        pr_err("[AVP] allocate handle error %d\n", err);
+        resp->error = NvError_InsufficientMemory;
+    } else {
+        resp->error = NvSuccess;
+    }
+}
+void NvRmPrivProcessMessage(NvRmRPCHandle hRPCHandle, char *pRecvMessage, int messageLength)
+{
+    switch (*(NvRmMsg *)pRecvMessage) {
+
+    case NvRmMsg_MemHandleCreate:
+    {
+        NvRmMessage_HandleCreat *msgHandleCreate = NULL;
+        NvRmMessage_HandleCreatResponse msgRHandleCreate;
+
+        msgHandleCreate = (NvRmMessage_HandleCreat*)pRecvMessage;
+        HandleCreateMessage(msgHandleCreate, &msgRHandleCreate);
+        NvRmPrivRPCSendMsg(hRPCHandle, &msgRHandleCreate,
+                           sizeof(msgRHandleCreate));
+        barrier();
+    }
+    break;
+    case NvRmMsg_MemHandleOpen:
+        break;
+    case NvRmMsg_MemHandleFree:
+    {
+        NvRmMessage_HandleFree *msgHandleFree = NULL;
+        msgHandleFree = (NvRmMessage_HandleFree*)pRecvMessage;
+        nvmap_free_handle_id(s_AvpClient, (unsigned long)msgHandleFree->hMem);
+        barrier();
+    }
+    break;
+    case NvRmMsg_MemAlloc:
+    {
+        NvRmMessage_MemAlloc *msgMemAlloc = NULL;
+        NvRmMessage_Response msgResponse;
+        msgMemAlloc = (NvRmMessage_MemAlloc*)pRecvMessage;
+
+        HandleAllocMessage(msgMemAlloc, &msgResponse);
+        NvRmPrivRPCSendMsg(hRPCHandle, &msgResponse, sizeof(msgResponse));
+        barrier();
+    }
+    break;
+    case NvRmMsg_MemPin:
+    {
+        struct nvmap_handle_ref *ref;
+        NvRmMessage_Pin *msg;
+        NvRmMessage_PinResponse response;
+        unsigned long id;
+        int err;
+
+        msg = (NvRmMessage_Pin *)pRecvMessage;
+        id = (unsigned long)msg->hMem;
+        response.msg = NvRmMsg_MemPin_Response;
+
+        ref = nvmap_duplicate_handle_id(s_AvpClient, id);
+        if (IS_ERR(ref)) {
+            pr_err("[AVP] unable to duplicate handle for pin\n");
+            err = PTR_ERR(ref);
+        } else {
+            err = nvmap_pin_ids(s_AvpClient, 1, &id);
+        }
+        if (!err) {
+            response.address = nvmap_handle_address(s_AvpClient, id);
+        } else {
+            pr_err("[AVP] pin error %d\n", err);
+            response.address = 0xffffffff;
+        }
+
+        NvRmPrivRPCSendMsg(hRPCHandle, &response, sizeof(response));
+        barrier();
+    }
+    break;
+    case NvRmMsg_MemUnpin:
+    {
+        NvRmMessage_HandleFree *msg = NULL;
+        NvRmMessage_Response msgResponse;
+        unsigned long id;
+
+        msg = (NvRmMessage_HandleFree*)pRecvMessage;
+        id = (unsigned long)msg->hMem;
+        nvmap_unpin_ids(s_AvpClient, 1, &id);
+	nvmap_free_handle_id(s_AvpClient, id);
+
+        msgResponse.msg = NvRmMsg_MemUnpin_Response;
+        msgResponse.error = NvSuccess;
+
+        NvRmPrivRPCSendMsg(hRPCHandle, &msgResponse, sizeof(msgResponse));
+        barrier();
+    }
+    break;
+    case NvRmMsg_MemGetAddress:
+    {
+        NvRmMessage_GetAddress *msg = NULL;
+        NvRmMessage_GetAddressResponse response;
+        unsigned long address;
+
+        msg = (NvRmMessage_GetAddress*)pRecvMessage;
+        address = nvmap_handle_address(s_AvpClient, (unsigned long)msg->hMem);
+        response.address = address + msg->Offset;
+        response.msg = NvRmMsg_MemGetAddress_Response;
+        NvRmPrivRPCSendMsg(hRPCHandle, &response, sizeof(response));
+        barrier();
+    }
+    break;
+    case NvRmMsg_HandleFromId:
+    {
+        NvRmMessage_HandleFromId *msg = NULL;
+        struct nvmap_handle_ref *ref;
+        NvRmMessage_Response response;
+
+        msg = (NvRmMessage_HandleFromId*)pRecvMessage;
+        ref = nvmap_duplicate_handle_id(s_AvpClient, msg->id);
+
+        response.msg = NvRmMsg_HandleFromId_Response;
+        if (IS_ERR(ref)) {
+            response.error = NvError_InsufficientMemory;
+            pr_err("[AVP] duplicate handle error %ld\n", PTR_ERR(ref));
+        } else {
+            response.error = NvSuccess;
+        }
+        NvRmPrivRPCSendMsg(hRPCHandle, &response, sizeof(response));
+    }
+    break;
+    case NvRmMsg_PowerModuleClockControl:
+    {
+        NvRmMessage_Module *msgPMCC;
+        NvRmMessage_Response msgPMCCR;
+        msgPMCC = (NvRmMessage_Module*)pRecvMessage;
+
+        msgPMCCR.msg = NvRmMsg_PowerModuleClockControl_Response;
+        msgPMCCR.error = NvRmPowerModuleClockControl(hRPCHandle->hRmDevice,
+                                                     msgPMCC->ModuleId,
+                                                     msgPMCC->ClientId,
+                                                     msgPMCC->Enable);
+
+        NvRmPrivRPCSendMsg(hRPCHandle, &msgPMCCR, sizeof(msgPMCCR));
+    }
+    break;
+    case NvRmMsg_ModuleReset:
+    {
+        NvRmMessage_Module *msgPMCC;
+        NvRmMessage_Response msgPMCCR;
+        msgPMCC = (NvRmMessage_Module*)pRecvMessage;
+
+        msgPMCCR.msg = NvRmMsg_ModuleReset_Response;
+
+        NvRmModuleReset(hRPCHandle->hRmDevice, msgPMCC->ModuleId);
+        /// Send response since clients to this call needs to wait
+        /// for some time before they can start using the HW module
+        NvRmPrivRPCSendMsg(hRPCHandle, &msgPMCCR, sizeof(msgPMCCR));
+    }
+    break;
+
+    case NvRmMsg_PowerRegister:
+    {
+        NvRmMessage_PowerRegister *msgPower;
+        NvRmMessage_PowerRegister_Response msgResponse;
+
+        msgPower = (NvRmMessage_PowerRegister*)pRecvMessage;
+
+        msgResponse.msg   = NvRmMsg_PowerResponse;
+        msgResponse.error = NvSuccess;
+        msgResponse.clientId = msgPower->clientId;
+
+        NvRmPrivRPCSendMsg(hRPCHandle, &msgResponse, sizeof(msgResponse));
+
+    }
+    break;
+
+    case NvRmMsg_PowerUnRegister:
+        break;
+    case NvRmMsg_PowerStarvationHint:
+    case NvRmMsg_PowerBusyHint:
+    {
+        NvRmMessage_Response msgResponse;
+        msgResponse.msg   = NvRmMsg_PowerResponse;
+        msgResponse.error = NvSuccess;
+        NvRmPrivRPCSendMsg(hRPCHandle, &msgResponse, sizeof(msgResponse));
+    }
+    break;
+    case NvRmMsg_PowerBusyMultiHint:
+        break;
+    case NvRmMsg_PowerDfsGetState:
+    {
+        NvRmMessage_PowerDfsGetState_Response msgResponse;
+        msgResponse.msg = NvRmMsg_PowerDfsGetState_Response;
+        msgResponse.state = NvRmDfsRunState_Stopped;
+        NvRmPrivRPCSendMsg(hRPCHandle, &msgResponse, sizeof(msgResponse));
+    }
+    break;
+    case NvRmMsg_PowerModuleGetMaxFreq:
+    {
+        NvRmMessage_PowerModuleGetMaxFreq_Response msgResponse;
+        msgResponse.msg = NvRmMsg_PowerModuleGetMaxFreq;
+        msgResponse.freqKHz = 0;
+        NvRmPrivRPCSendMsg(hRPCHandle, &msgResponse, sizeof(msgResponse));
+    }
+    break;
+    case NvRmMsg_PowerDfsGetClockUtilization:
+    {
+        NvRmMessage_PowerDfsGetClockUtilization_Response msgResponse;
+        NvRmDfsClockUsage ClockUsage = { 0, 0, 0, 0, 0, 0 };
+
+        msgResponse.msg = NvRmMsg_PowerDfsGetClockUtilization_Response;
+        msgResponse.error = NvSuccess;
+        NvOsMemcpy(&msgResponse.clockUsage, &ClockUsage, sizeof(ClockUsage));
+        NvRmPrivRPCSendMsg(hRPCHandle, &msgResponse, sizeof(msgResponse));
+    }
+    break;
+    case NvRmMsg_InitiateLP0:
+    {
+        //Just for testing purposes.
+    }
+    break;
+    case NvRmMsg_RemotePrintf:
+    {
+        NvRmMessage_RemotePrintf *msg;
+
+        msg = (NvRmMessage_RemotePrintf*)pRecvMessage;
+        printk("AVP: %s", msg->string);
+    }
+    break;
+    case NvRmMsg_AVP_Reset:
+        NvOsDebugPrintf("AVP has been reset by WDT\n");
+        break;
+    default:
+            panic("AVP Service::ProcessMessage: bad message");
+            break;
+    }
+}
+
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_clocks.h b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_clocks.h
new file mode 100644
index 000000000000..9033261ba9ac
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_clocks.h
@@ -0,0 +1,460 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_AP15RM_CLOCKS_H
+#define INCLUDED_AP15RM_CLOCKS_H
+
+#include "nvrm_clocks.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+extern const NvRmModuleClockInfo g_Ap15ModuleClockTable[];
+extern const NvU32 g_Ap15ModuleClockTableSize;
+
+// PLLM ratios for graphic clocks
+#define NVRM_PLLM_HOST_SPEED_RATIO (4)
+#define NVRM_PLLM_2D_LOW_SPEED_RATIO (3)
+#define NVRM_PLLM_2D_HIGH_SPEED_RATIO (2)
+
+/**
+ * Defines frequency steps derived from PLLP0 fixed output to be used as System
+ * clock source frequency. The frequency specified in kHz, and it will be rounded
+ * up to the closest divider output. 
+ */
+#define NVRM_AP15_PLLP_POLICY_SYSTEM_CLOCK \
+    PLLP_POLICY_ENTRY(54000)   /* PLLP divider  6, output frequency  54,000kHz */ \
+    PLLP_POLICY_ENTRY(72000)   /* PLLP divider  4, output frequency  72,000kHz */ \
+    PLLP_POLICY_ENTRY(108000)  /* PLLP divider  2, output frequency 108,000kHz */ \
+    PLLP_POLICY_ENTRY(144000)  /* PLLP divider  1, output frequency 144,000kHz */ \
+    PLLP_POLICY_ENTRY(216000)  /* PLLP divider  0, output frequency 216,000kHz */
+
+/**
+ * Defines frequency steps derived from PLLP0 fixed output to be used as CPU
+ * clock source frequency. The frequency specified in kHz, and it will be rounded
+ * up to the closest divider output. 
+ */
+#define NVRM_AP15_PLLP_POLICY_CPU_CLOCK \
+    PLLP_POLICY_ENTRY(24000)   /* PLLP divider 16, output frequency  24,000kHz */ \
+    PLLP_POLICY_ENTRY(54000)   /* PLLP divider  6, output frequency  54,000kHz */ \
+    PLLP_POLICY_ENTRY(108000)  /* PLLP divider  2, output frequency 108,000kHz */ \
+    PLLP_POLICY_ENTRY(216000)  /* PLLP divider  0, output frequency 216,000kHz */ \
+
+/**
+ * Combines EMC 2x frequency and the respective set of EMC timing parameters for
+ * pre-defined EMC configurations (DDR clock is running at EMC 1x frequency)
+ */
+typedef struct NvRmAp15EmcTimingConfigRec
+{
+    NvRmFreqKHz Emc2xKHz;
+    NvU32 Timing0Reg;
+    NvU32 Timing1Reg;
+    NvU32 Timing2Reg;
+    NvU32 Timing3Reg;
+    NvU32 Timing4Reg;
+    NvU32 Timing5Reg;
+    NvU32 FbioCfg6Reg;
+    NvU32 FbioDqsibDly;
+    NvU32 FbioQuseDly;
+    NvU32 Emc2xDivisor;
+    NvRmFreqKHz McKHz;
+    NvU32 McDivisor;
+    NvU32 McClockSource;
+    NvRmFreqKHz CpuLimitKHz;
+    NvRmMilliVolts CoreVoltageMv;
+} NvRmAp15EmcTimingConfig;
+
+// Defines number of EMC frequency steps for DFS 
+#define NVRM_AP15_DFS_EMC_FREQ_STEPS (5)
+
+// Dfines CPU and EMC ratio policy as 
+// CpuKHz/CpuMax <= PolicyTabel[PLLM0/(2*EMC2xKHz)] / 256
+#define NVRM_AP15_CPU_EMC_RATIO_POLICY \
+    256, 192, 144, 122, 108, 98, 91, 86, 81, 77
+
+/*****************************************************************************/
+
+/**
+ * Enables/disables module clock.
+ * 
+ * @param hDevice The RM device handle.
+ * @param ModuleId Combined module ID and instance of the target module.
+ * @param ClockState Target clock state.
+ */
+void
+Ap15EnableModuleClock(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId, 
+    ModuleClockState ClockState);
+
+// Separate API to control TVDAC clock independently of TVO
+// (when TVDAC is used for CRT)  
+void
+Ap15EnableTvDacClock(
+    NvRmDeviceHandle hDevice,
+    ModuleClockState ClockState);
+
+/**
+ * Resets module (assert/delay/deassert reset signal) if the hold paramter is
+ * NV_FLASE. If the hols paramter is NV_TRUE, just assert the reset and return.
+ * 
+ * @param hDevice The RM device handle.
+ * @param Module Combined module ID and instance of the target module.
+ * @param hold      To hold or relese the reset.
+ */
+void AP15ModuleReset(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId, NvBool hold);
+
+/*****************************************************************************/
+
+/**
+ * Initializes PLL references table.
+ * 
+ * @param pPllReferencesTable A pointer to a pointer which this function sets
+ *  to the PLL reference table base. 
+ * @param pPllReferencesTableSize A pointer to a variable which this function
+ *  sets to the PLL reference table size.
+ */
+void
+NvRmPrivAp15PllReferenceTableInit(
+    NvRmPllReference** pPllReferencesTable,
+    NvU32* pPllReferencesTableSize);
+
+/**
+ * Initializes EMC clocks configuration structures and tables.
+ * 
+ * @param hRmDevice The RM device handle. 
+ */
+void
+NvRmPrivAp15EmcConfigInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Resets 2D module.
+ * 
+ * @param hRmDevice The RM device handle. 
+ */
+void
+NvRmPrivAp15Reset2D(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Initializes clock source table.
+ * 
+ * @return Pointer to the clock sources descriptor table.
+ */
+NvRmClockSourceInfo* NvRmPrivAp15ClockSourceTableInit(void);
+
+/**
+ * Sets "as is" specified PLL configuration: switches PLL in bypass mode,
+ * changes PLL settings, waits for PLL stabilization, and switches to PLL
+ * output.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the PLL description structure.
+ * @param M PLL input divider setting.
+ * @param N PLL feedback divider setting.
+ * @param P PLL output divider setting.
+ *  PLL is left disabled (not bypassed) if either M or N setting is zero:
+ *  M = 0 or N = 0; otherwise, M, N, P validation is caller responsibility.
+ * @param StableDelayUs PLL stabilization delay in microseconds. If specified
+ *  value is above guaranteed stabilization time, the latter one is used.
+ * @param cpcon PLL charge pump control setting; ignored if TypicalControls
+ *  is true.
+ * @param lfcon PLL loop filter control setting; ignored if TypicalControls
+ *  is true.
+ * @param TypicalControls If true, both charge pump and loop filter parameters
+ *  are ignored and typical controls that corresponds to specified M, N, P
+ *  values will be set. If false, the cpcon and lfcon parameters are set; in
+ *  this case parameter validation is caller responsibility.
+ * @param flags PLL specific flags. Thse flags are valid only for some PLLs,
+ *  see @NvRmPllConfigFlags.
+ */
+void
+NvRmPrivAp15PllSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmPllClockInfo* pCinfo,
+    NvU32 M,
+    NvU32 N,
+    NvU32 P,
+    NvU32 StableDelayUs,
+    NvU32 cpcon,
+    NvU32 lfcon,
+    NvBool TypicalControls,
+    NvU32 flags);
+
+/**
+ * Configures output frequency for specified PLL.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param PllId Targeted PLL ID.
+ * @param MaxOutKHz Upper limit for PLL output frequency.
+ * @param pPllOutKHz A pointer to the requested PLL frequency on entry,
+ *  and to the actually configured frequency on exit.
+ */
+void
+NvRmPrivAp15PllConfigureSimple(
+    NvRmDeviceHandle hRmDevice,
+    NvRmClockSource PllId,
+    NvRmFreqKHz MaxOutKHz,
+    NvRmFreqKHz* pPllOutKHz);
+
+/**
+ * Configures specified PLL output to the CM of fixed HDMI frequencies.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param PllId Targeted PLL ID.
+ * @param pPllOutKHz A pointer to the actually configured frequency on exit.
+ */
+void
+NvRmPrivAp15PllConfigureHdmi(
+    NvRmDeviceHandle hRmDevice,
+    NvRmClockSource PllId,
+    NvRmFreqKHz* pPllOutKHz);
+
+/**
+ * Gets PLL output frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the PLL description structure.
+ * 
+ * @return PLL output frequency in kHz (reference frequency if PLL
+ *  is by-passed; zero if PLL is disabled and not by-passed).
+ */
+NvRmFreqKHz
+NvRmPrivAp15PllFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmPllClockInfo* pCinfo);
+
+/**
+ * Gets frequencies of DFS controlled clocks
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pDfsKHz Output storage pointer for DFS clock frequencies structure
+ *  (all frequencies returned in kHz).
+ */
+void
+NvRmPrivAp15DfsClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/**
+ * Configures DFS controlled clocks
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pMaxKHz Pointer to the DFS clock frequencies upper limits
+ * @param pDfsKHz Pointer to the target DFS frequencies structure on entry;
+ *  updated with actual DFS clock frequencies on exit.
+ * 
+ * @return NV_TRUE if clock configuration is completed; NV_FALSE if this
+ *  function has to be called again to complete configuration.
+ */
+NvBool
+NvRmPrivAp15DfsClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDfsFrequencies* pMaxKHz,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/**
+ * Gets maximum DFS domains frequencies that can be used at specified
+ *  core voltage.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param TargetMv Targeted core voltage in mV.
+ * @param pDfsKHz Pointer to a structure filled in by this function with
+ *  output clock frequencies.
+ */
+void
+NvRmPrivAp15DfsVscaleFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMilliVolts TargetMv,
+    NvRmDfsFrequencies* pDfsKHz);
+
+/**
+ * Determines if module clock configuration requires AP15-specific handling,
+ * and configures the clock if yes.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the module clock descriptor. 
+ * @param ClockSourceCount Number of module clock sources.
+ * @param MinFreq Requested minimum module clock frequency.
+ * @param MaxFreq Requested maximum module clock frequency.
+ * @param PrefFreqList Pointer to a list of preferred frequencies sorted
+ *  in the decreasing order of priority.
+ * @param PrefCount Number of entries in the PrefFreqList array.
+ * @param pCstate Pointer to module state structure filled in if special
+ *  handling is completed.
+ * @param flags Module specific flags
+ *
+ * @return True indicates that module clock is configured, and regular
+ *  configuration should be aborted; False indicates that regular clock
+ *  configuration should proceed.
+ */
+NvBool
+NvRmPrivAp15IsModuleClockException(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleClockInfo *pCinfo,
+    NvU32 ClockSourceCount,
+    NvRmFreqKHz MinFreq,
+    NvRmFreqKHz MaxFreq,
+    const NvRmFreqKHz* PrefFreqList,
+    NvU32 PrefCount,
+    NvRmModuleClockState* pCstate,
+    NvU32 flags);
+
+/**
+ * Configures EMC low-latency fifo for CPU clock source switch.
+ * 
+ * @param hRmDevice The RM device handle.
+ */
+void
+NvRmPrivAp15SetEmcForCpuSrcSwitch(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Configures EMC low-latency fifo for CPU clock divider switch.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param CpuFreq Resulting CPU frequency after divider switch
+ * @param Before Specifies if this function is called before (True)
+ *  or after (False) divider changes.
+ */
+void
+NvRmPrivAp15SetEmcForCpuDivSwitch(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz CpuFreq,
+    NvBool Before);
+
+/**
+ * Configures maximum core and memory clocks.
+ * 
+ * @param hRmDevice The RM device handle.
+ */
+void
+NvRmPrivAp15FastClockConfig(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Gets module frequency synchronized with EMC speed.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module The target module ID.
+ * 
+ * @return Module frequency in kHz.
+ */
+NvRmFreqKHz NvRmPrivAp15GetEmcSyncFreq(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module);
+
+/**
+ * Disables PLLs
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the last configured module clock descriptor. 
+ * @param pCstate Pointer to the last configured module state structure.
+ */
+void
+NvRmPrivAp15DisablePLLs(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    const NvRmModuleClockState* pCstate);
+
+/**
+ * Turns PLLD (MIPI PLL) power On/Off
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param ConfigEntry NV_TRUE if this function is called before display
+ *  clock configuration; NV_FALSE otherwise.
+ * @param Pointer to the current state of MIPI PLL power rail, updated
+ *  by this function.
+ */
+void
+NvRmPrivAp15PllDPowerControl(
+    NvRmDeviceHandle hRmDevice,
+    NvBool ConfigEntry,
+    NvBool* pMipiPllVddOn);
+
+/**
+ * Clips EMC frequency high limit to one of the fixed DFS EMC configurations,
+ * and if necessary adjust CPU high limit respectively.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCpuHighKHz A pointer to the variable, which contains CPU frequency
+ *  high limit in KHz (on entry - requested limit, on exit - clipped limit)
+ * @param pEmcHighKHz A pointer to the variable, which contains EMC frequency
+ *  high limit in KHz (on entry - requested limit, on exit - clipped limit)
+ */
+void
+NvRmPrivAp15ClipCpuEmcHighLimits(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz* pCpuHighKHz,
+    NvRmFreqKHz* pEmcHighKHz);
+
+
+/**
+ * Configures some special bits in the clock source register for given module.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module Target module ID.
+ * @param ClkSourceOffset Clock source register offset.
+ * @param flags Module specific clock configuration flags.
+ */
+void
+NvRmPrivAp15ClockConfigEx(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvU32 ClkSourceOffset,
+    NvU32 flags);
+
+/**
+ * Enables PLL in simulation.
+ * 
+ * @param hRmDevice The RM device handle.
+ */
+void NvRmPrivAp15SimPllInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Configures oscillator (main) clock doubler.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param OscKHz Oscillator (main) clock frequency in kHz.
+ * 
+ * @return NvSuccess if the specified oscillator frequency is supported, and
+ * NvError_NotSupported, otherwise.
+ */
+NvError
+NvRmPrivAp15OscDoublerConfigure(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz OscKHz);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  // INCLUDED_AP15RM_CLOCKS_H 
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_init.c b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_init.c
new file mode 100644
index 000000000000..d91a2e1f3293
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_init.c
@@ -0,0 +1,763 @@
+/*
+ * Copyright (c) 2007-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvutil.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_init.h"
+#include "nvrm_rmctrace.h"
+#include "nvrm_configuration.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_pmu_private.h"
+#include "nvrm_processor.h"
+#include "nvrm_xpc.h"
+#include "ap15rm_private.h"
+#include "nvrm_structure.h"
+#include "ap15rm_private.h"
+#include "ap15rm_clocks.h"
+#include "nvodm_query.h"
+#include "nvodm_query_pins.h"
+#include "common/nvrm_hwintf.h"
+#include "ap15/armc.h"
+#include "ap15/aremc.h"
+#include "ap15/project_relocation_table.h"
+#include "ap15/arapb_misc.h"
+#include "ap15/arapbpm.h"
+#include "nvrm_pinmux_utils.h"
+#include "ap15/arfuse.h"
+#include "nvbootargs.h"
+
+static NvRmDevice gs_Rm;
+
+extern NvRmCfgMap g_CfgMap[];
+
+void NvRmPrivMemoryInfo( NvRmDeviceHandle hDevice );
+extern NvError NvRmPrivMapApertures( NvRmDeviceHandle rm );
+extern void NvRmPrivUnmapApertures( NvRmDeviceHandle rm );
+extern NvError NvRmPrivPwmInit(NvRmDeviceHandle hRm);
+extern void NvRmPrivPwmDeInit(NvRmDeviceHandle hRm);
+extern NvU32 NvRmPrivGetBctCustomerOption(NvRmDeviceHandle hRm);
+extern void NvRmPrivReadChipId( NvRmDeviceHandle rm );
+extern NvU32 *NvRmPrivGetRelocationTable( NvRmDeviceHandle hDevice );
+extern NvError NvRmPrivPcieOpen(NvRmDeviceHandle hDeviceHandle);
+extern void NvRmPrivPcieClose(NvRmDeviceHandle hDeviceHandle);
+static void NvRmPrivInitPinAttributes(NvRmDeviceHandle rm);
+static void NvRmPrivBasicReset( NvRmDeviceHandle rm );
+static NvError NvRmPrivMcErrorMonitorStart( NvRmDeviceHandle rm );
+static void NvRmPrivMcErrorMonitorStop( NvRmDeviceHandle rm );
+
+#if !NV_OAL
+/* This function sets some performance timings for Mc & Emc.  Numbers are from
+ * the Arch team.
+ */
+static void
+NvRmPrivSetupMc(NvRmDeviceHandle hRm)
+{
+    switch (hRm->ChipId.Id) {
+    case 0x15:
+    case 0x16:
+        NvRmPrivAp15SetupMc(hRm);
+        break;
+    case 0x20:
+        NvRmPrivAp20SetupMc(hRm);
+        break;
+    default:
+        NV_ASSERT(!"Unsupported chip ID");
+        break;
+    }
+}
+#endif
+
+NvError
+NvRmOpen(NvRmDeviceHandle *pHandle, NvU32 DeviceId ) {
+    return NvRmOpenNew(pHandle);
+}
+
+void NvRmPrivReadChipId( NvRmDeviceHandle rm )
+{
+	NvRmChipId *id;
+	u32 reg, fam;
+
+	id = &rm->ChipID;
+
+	reg = readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE) + 0x804);
+	id->Id = (reg >> 8) & 0xff;
+	id->Major = (reg >> 4) & 0xf;
+	id->Minor = (reg >> 16) & 0xf;
+
+	fam = reg & 0xf;
+
+    switch( fam ) {
+    case APB_MISC_GP_HIDREV_0_HIDFAM_GPU:
+        id->Family = NvRmChipFamily_Gpu;
+        s = "GPU";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD:
+        id->Family = NvRmChipFamily_Handheld;
+        s = "Handheld";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_BR_CHIPS:
+        id->Family = NvRmChipFamily_BrChips;
+        s = "BrChips";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_CRUSH:
+        id->Family = NvRmChipFamily_Crush;
+        s = "Crush";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_MCP:
+        id->Family = NvRmChipFamily_Mcp;
+        s = "MCP";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_CK:
+        id->Family = NvRmChipFamily_Ck;
+        s = "Ck";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_VAIO:
+        id->Family = NvRmChipFamily_Vaio;
+        s = "Vaio";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD_SOC:
+        id->Family = NvRmChipFamily_HandheldSoc;
+        s = "Handheld SOC";
+        break;
+    default:
+        NV_ASSERT( !"bad chip family" );
+        NvRmPhysicalMemUnmap(VirtAddr, 0x1000);
+        return;
+    }
+}
+
+
+
+void NvRmInit(
+    NvRmDeviceHandle * pHandle )
+{
+    NvU32 *table = 0;
+    NvRmDevice *rm = 0;
+    rm = &gs_Rm;
+
+    if( rm->bPreInit )
+    {
+        return;
+    }
+
+    /* Read the chip Id and store in the Rm structure. */
+    NvRmPrivReadChipId( rm );
+
+    /* parse the relocation table */
+//    table = NvRmPrivGetRelocationTable( rm );
+//    NV_ASSERT(table != NULL);
+
+//    NV_ASSERT_SUCCESS(NvRmPrivModuleInit( &rm->ModuleTable, table ));
+//    NvRmPrivMemoryInfo( rm );
+
+//    NvRmPrivInterruptTableInit( rm );
+
+    rm->bPreInit = NV_TRUE;
+    *pHandle = rm;
+
+    return;
+}
+
+NvError
+NvRmOpenNew(NvRmDeviceHandle *pHandle)
+{
+    NvError err;
+    NvRmDevice *rm = 0;
+    NvU32 *table = 0;
+
+    NvU32 BctCustomerOption = 0;
+    NvU64 Uid = 0;
+
+    NvOsMutexHandle rmMutex = NULL;
+
+    /* open the nvos trace file */
+    NVOS_TRACE_LOG_START;
+
+    // OAL does not support these mutexes
+    if (gs_Rm.mutex == NULL)
+    {
+        err = NvOsMutexCreate(&rmMutex);
+        if (err != NvSuccess)
+            return err;
+
+        if (NvOsAtomicCompareExchange32((NvS32*)&gs_Rm.mutex, 0,
+                (NvS32)rmMutex) != 0)
+            NvOsMutexDestroy(rmMutex);
+    }
+
+    NvOsMutexLock(gs_Rm.mutex);
+    rm = &gs_Rm;
+
+    if(rm->refcount )
+    {
+        rm->refcount++;
+        *pHandle = rm;
+        NvOsMutexUnlock(gs_Rm.mutex);
+        return NvSuccess;
+    }
+
+    rmMutex = gs_Rm.mutex;
+    gs_Rm.mutex = rmMutex;
+
+    // create the memmgr mutex
+    err = NvOsMutexCreate(&rm->MemMgrMutex);
+    if (err)
+        goto fail;
+
+    // create mutex for the clock and reset r-m-w top level registers access
+    err = NvOsMutexCreate(&rm->CarMutex);
+    if (err)
+        goto fail;
+
+    /* NvRmOpen needs to be re-entrant to allow I2C, GPIO and KeyList ODM
+     * services to be available to the ODM query.  Therefore, the refcount is
+     * bumped extremely early in initialization, and if any initialization
+     * fails the refcount is reset to 0.
+     */
+    rm->refcount = 1;
+
+#if 0
+    if( !rm->bBasicInit )
+    {
+        /* get the default configuration */
+        err = NvRmPrivGetDefaultCfg( g_CfgMap, &rm->cfg );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        /* get the requested configuration */
+        err = NvRmPrivReadCfgVars( g_CfgMap, &rm->cfg );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+    }
+#endif
+
+#if 0
+    /* start chiplib */
+    if (rm->cfg.Chiplib[0] != '\0')
+    {
+        err = NvRmPrivChiplibStartup( rm->cfg.Chiplib, rm->cfg.ChiplibArgs,
+            NULL );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+    }
+
+    /* open the RMC file */
+    err = NvRmRmcOpen( rm->cfg.RMCTraceFileName, &rm->rmc );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    if( !rm->bPreInit )
+    {
+        /* Read the chip Id and store in the Rm structure. */
+        NvRmPrivReadChipId( rm );
+
+        /* parse the relocation table */
+        table = NvRmPrivGetRelocationTable( rm );
+        if( !table )
+        {
+            goto fail;
+        }
+
+        err = NvRmPrivModuleInit( &rm->ModuleTable, table );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+        NvRmPrivMemoryInfo( rm );
+
+        // Now populate the logical interrupt table.
+        NvRmPrivInterruptTableInit( rm );
+    }
+
+    if( !rm->bBasicInit && !NVOS_IS_WINDOWS_X86 )
+    {
+        err = NvRmPrivMapApertures( rm );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        // Initializing the ODM-defined key list
+        //  This gets initialized first, since the RMs calls into
+        //  the ODM query may result in the ODM query calling
+        //  back into the RM to get this value!
+        BctCustomerOption = NvRmPrivGetBctCustomerOption(rm);
+        err = NvRmPrivInitKeyList(rm, &BctCustomerOption, 1);
+        if (err != NvSuccess)
+        {
+            goto fail;
+        }
+    }
+
+    // prevent re-inits
+    rm->bBasicInit = NV_TRUE;
+    rm->bPreInit = NV_TRUE;
+
+
+    if (!NVOS_IS_WINDOWS_X86)
+    {
+        NvRmPrivCheckBondOut( rm );
+
+        /* bring modules out of reset */
+        NvRmPrivBasicReset( rm );
+
+        /* initialize power manager before any other module that may access
+         * clock or voltage resources
+         */
+        err = NvRmPrivPowerInit(rm);
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        NvRmPrivInterruptStart( rm );
+
+        // Initializing pins attributes
+        NvRmPrivInitPinAttributes(rm);
+
+        // Initialize RM pin-mux (init's the state of internal shadow
+        // register variables)
+        NvRmInitPinMux(rm, NV_TRUE);
+
+        // Initalize the module clocks.
+        err = NvRmPrivClocksInit( rm );
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+    }
+#endif
+
+#ifdef GHACK
+    if (!NVOS_IS_WINDOWS_X86)
+    {
+        // FIXME: this crashes in simulation
+        // Enabling only for the non simulation modes.
+        if ((rm->ChipId.Major == 0) && (rm->ChipId.Netlist == 0))
+        {
+            // this is the csim case, so we don't do this here.
+        }
+        else
+        {
+            // Initializing the dma.
+            err = NvRmPrivDmaInit(rm);
+            if( err != NvSuccess )
+            {
+                goto fail;
+            }
+
+            // Initializing the Spi and Slink.
+            err = NvRmPrivSpiSlinkInit(rm);
+            if( err != NvSuccess )
+            {
+                goto fail;
+            }
+
+            //  Complete pin mux initialization
+            NvRmInitPinMux(rm, NV_FALSE);
+
+            // Initializing the dfs
+            err = NvRmPrivDfsInit(rm);
+            if( err != NvSuccess )
+            {
+                goto fail;
+            }
+        }
+
+        // Initializing the Pwm
+        err = NvRmPrivPwmInit(rm);
+        if (err != NvSuccess)
+        {
+            goto fail;
+        }
+
+        // PMU interface init utilizes ODM services that reenter NvRmOpen().
+        // Therefore, it shall be performed after refcount is set so that
+        // reentry has no side-effects except bumping refcount. The latter
+        // is reset below so that RM can be eventually closed.
+        err = NvRmPrivPmuInit(rm);
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        // set the mc & emc tuning parameters
+        NvRmPrivSetupMc(rm);
+        if (!NvRmIsSimulation())
+        {
+            // Configure PLL rails, boost core power and clocks
+            // Initialize and start temperature monitoring
+            NvRmPrivPllRailsInit(rm);
+            NvRmPrivBoostClocks(rm);
+            NvRmPrivDttInit(rm);
+        }
+
+        if (0)  /* FIXME Don't enable PCI yet */
+        {
+            err = NvRmPrivPcieOpen( rm );
+            if (err != NvSuccess && err != NvError_ModuleNotPresent)
+            {
+                goto fail;
+            }
+        }
+        // Asynchronous interrupts must be disabled until the very end of
+        // RmOpen. They can be enabled just before releasing rm mutex after
+        // completion of all initialization calls.
+        NvRmPrivPmuInterruptEnable(rm);
+
+        // Start Memory Controller Error monitoring.
+        err = NvRmPrivMcErrorMonitorStart(rm);
+        if( err != NvSuccess )
+        {
+            goto fail;
+        }
+
+        // WAR for bug 600821
+        if ((rm->ChipId.Id == 0x20) && 
+            (rm->ChipId.Major == 0x1) && (rm->ChipId.Minor == 0x2))
+        {
+            err = NvRmQueryChipUniqueId(rm, sizeof (NvU64), &Uid);
+            if ((Uid>>32) == 0x08080105)
+            {
+                NV_REGW(rm, NvRmModuleID_Pmif, 0, 0xD0, 0xFFFFFFEF);
+            }
+        }
+    }
+    err = NvRmXpcInitArbSemaSystem(rm);
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+#endif
+
+    /* assign the handle pointer */
+    *pHandle = rm;
+
+    NvOsMutexUnlock(gs_Rm.mutex);
+    return NvSuccess;
+
+fail:
+    // FIXME: free rm if it becomes dynamically allocated
+    // BUG:  there are about ten places that we go to fail, and we make no
+    // effort here to clean anything up.
+    NvOsMutexUnlock(gs_Rm.mutex);
+    NV_DEBUG_PRINTF(("RM init failed\n"));
+    rm->refcount = 0;
+    return err;
+}
+
+void
+NvRmClose(NvRmDeviceHandle handle)
+{
+    if( !handle )
+    {
+        return;
+    }
+
+    NV_ASSERT( handle->mutex );
+
+    /* decrement refcount */
+    NvOsMutexLock( handle->mutex );
+    handle->refcount--;
+
+    /* do deinit if refcount is zero */
+    if( handle->refcount == 0 )
+    {
+#ifdef GHACK
+        if (!NVOS_IS_WINDOWS_X86)
+        {
+            // PMU and DTT deinit through ODM services reenters NvRmClose().
+            // The refcount will wrap around and this will be the only reentry
+            // side-effect, which is compensated after deint exit.
+            NvRmPrivDttDeinit();
+            handle->refcount = 0;
+            NvRmPrivPmuDeinit(handle);
+            handle->refcount = 0;
+
+            if (0)  /* FIXME Don't enable PCIE yet */
+            {
+                NvRmPrivPcieClose( handle );
+            }
+        }
+
+        if (!NVOS_IS_WINDOWS_X86)
+        {
+            /* disable modules */
+            // Enabling only for the non simulation modes.
+            if ((handle->ChipId.Major == 0) && (handle->ChipId.Netlist == 0))
+            {
+                // this is the csim case, so we don't do this here.
+            }
+            else
+            {
+                NvRmPrivDmaDeInit();
+
+                NvRmPrivSpiSlinkDeInit();
+
+                NvRmPrivDfsDeinit(handle);
+            }
+
+            /* deinit clock manager */
+            NvRmPrivClocksDeinit(handle);
+
+            /* deinit power manager */
+            NvRmPrivPowerDeinit(handle);
+
+            NvRmPrivDeInitKeyList(handle);
+            NvRmPrivPwmDeInit(handle);
+            // Stop Memory controller error monitoring.
+            NvRmPrivMcErrorMonitorStop(handle);
+
+            /* if anyone left an interrupt registered, this will clear it. */
+            NvRmPrivInterruptShutdown(handle);
+
+            /* unmap the apertures */
+            NvRmPrivUnmapApertures( handle );
+
+            if (NvRmIsSimulation())
+                NvRmPrivChiplibShutdown();
+
+        }
+#endif
+        NvRmRmcClose( &handle->rmc );
+
+        /* deallocate the instance table */
+//        NvRmPrivModuleDeinit( &handle->ModuleTable );
+
+        /* free up the CAR mutex */
+        NvOsMutexDestroy(handle->CarMutex);
+
+        /* free up the memmgr mutex */
+        NvOsMutexDestroy(handle->MemMgrMutex);
+
+        /* close the nvos trace file */
+        NVOS_TRACE_LOG_END;
+    }
+    NvOsMutexUnlock( handle->mutex );
+
+#if NVOS_IS_WINDOWS && !NVOS_IS_WINDOWS_CE
+    if( handle->refcount == 0 )
+    {
+        NvOsMutexDestroy(handle->mutex);
+        gs_Rm.mutex = 0;
+    }
+#endif
+}
+
+#ifdef GHACK
+void
+NvRmPrivMemoryInfo( NvRmDeviceHandle hDevice )
+{
+    NvRmModuleTable *tbl;
+    NvRmModuleInstance *inst;
+
+    tbl = &hDevice->ModuleTable;
+
+    /* Get External memory module info */
+    inst = tbl->ModInst +
+        (tbl->Modules)[NvRmPrivModuleID_ExternalMemory].Index;
+
+    hDevice->ExtMemoryInfo.base = inst->PhysAddr;
+    hDevice->ExtMemoryInfo.size = inst->Length;
+
+    /* Get Iram Memory Module Info .Special handling since iram has 4 banks
+     * and each has a different instance in the relocation table
+     */
+
+    inst = tbl->ModInst + (tbl->Modules)[NvRmPrivModuleID_Iram].Index;
+    hDevice->IramMemoryInfo.base = inst->PhysAddr;
+    hDevice->IramMemoryInfo.size = inst->Length;
+
+    inst++;
+    // Below loop works assuming that relocation table parsing compacted
+    // scattered multiple instances into sequential list
+    while(NvRmPrivDevToModuleID(inst->DeviceId) == NvRmPrivModuleID_Iram)
+    {
+        // The IRAM banks are contigous address of memory. Cannot handle
+        // non-contigous memory for now
+        NV_ASSERT(hDevice->IramMemoryInfo.base +
+            hDevice->IramMemoryInfo.size == inst->PhysAddr);
+
+        hDevice->IramMemoryInfo.size += inst->Length;
+        inst++;
+    }
+
+}
+
+#endif
+
+NvError
+NvRmGetRmcFile( NvRmDeviceHandle hDevice, NvRmRmcFile **file )
+{
+    NV_ASSERT(hDevice);
+
+    *file = &hDevice->rmc;
+    return NvSuccess;
+}
+
+NvRmDeviceHandle NvRmPrivGetRmDeviceHandle()
+{
+    return &gs_Rm;
+}
+
+#ifdef GHACK
+/**
+ * Initializes pins attributes
+ * @param hRm The RM device handle
+ */
+static void
+NvRmPrivInitPinAttributes(NvRmDeviceHandle rm)
+{
+    NvU32 Count = 0, Offset = 0, Value = 0;
+    NvU32 Major = 0;
+    NvU32 Minor = 0;
+    NvOdmPinAttrib *pPinAttribTable = NULL;
+    NvRmModuleCapability caps[4];
+    NvRmModuleCapability *pCap = NULL;
+
+    NV_ASSERT( rm );
+
+    NvOsMemset(caps, 0, sizeof(caps));
+
+    caps[0].MajorVersion = 1;
+    caps[0].MinorVersion = 0;
+    caps[0].EcoLevel = 0;
+    caps[0].Capability = &caps[0];
+
+    caps[1].MajorVersion = 1;
+    caps[1].MinorVersion = 1;
+    caps[1].EcoLevel = 0;
+
+    caps[2].MajorVersion = 1;
+    caps[2].MinorVersion = 2;
+    caps[2].EcoLevel = 0;
+
+    //  the pin attributes for v 1.0 and v1.1 of the misc module
+    //  are fully compatible, so the version comparison is made against 1.0
+    // Treating 1.2 same as 1.0/1.1.
+    caps[1].Capability = &caps[0];
+    caps[2].Capability = &caps[0];
+
+    /* AP20 misc module pin attributes, set differently than AP15 as the pin
+     * attribute registers in misc module changed */
+    caps[3].MajorVersion = 2;
+    caps[3].MinorVersion = 0;
+    caps[3].EcoLevel = 0;
+    caps[3].Capability = &caps[3];
+
+    NV_ASSERT_SUCCESS(NvRmModuleGetCapabilities(
+            rm,
+            NvRmModuleID_Misc,
+            caps,
+            sizeof(caps)/sizeof(caps[0]),
+            (void**)&pCap));
+
+    Count = NvOdmQueryPinAttributes((const NvOdmPinAttrib **)&pPinAttribTable);
+
+    for ( ; Count ; Count--, pPinAttribTable++)
+    {
+        Major = (pPinAttribTable->ConfigRegister >> 28);
+        Minor = (pPinAttribTable->ConfigRegister >> 24) & 0xF;
+        if ((Major == pCap->MajorVersion) && (Minor == pCap->MinorVersion))
+        {
+            Offset = pPinAttribTable->ConfigRegister & 0xFFFF;
+            Value = pPinAttribTable->Value;
+            NV_REGW(rm, NvRmModuleID_Misc, 0, Offset, Value);
+        }
+    }
+}
+
+
+static void NvRmPrivBasicReset( NvRmDeviceHandle rm )
+{
+    switch (rm->ChipId.Id) {
+    case 0x15:
+    case 0x16:
+        NvRmPrivAp15BasicReset(rm);
+        return;
+    case 0x20:
+        NvRmPrivAp20BasicReset(rm);
+        return;
+    default:
+        NV_ASSERT(!"Unsupported chip ID");
+        return;
+    }
+}
+
+NvError NvRmPrivMcErrorMonitorStart( NvRmDeviceHandle rm )
+{
+    NvError e = NvError_NotSupported;
+
+    switch (rm->ChipId.Id) {
+    case 0x15:
+    case 0x16:
+        e = NvRmPrivAp15McErrorMonitorStart(rm);
+        break;
+    case 0x20:
+        e = NvRmPrivAp20McErrorMonitorStart(rm);
+        break;
+    default:
+        NV_ASSERT(!"Unsupported chip ID");
+        break;
+    }
+    return e;
+}
+
+void NvRmPrivMcErrorMonitorStop( NvRmDeviceHandle rm )
+{
+    switch (rm->ChipId.Id) {
+    case 0x15:
+    case 0x16:
+        NvRmPrivAp15McErrorMonitorStop(rm);
+        break;
+    case 0x20:
+        NvRmPrivAp20McErrorMonitorStop(rm);
+        break;
+    default:
+        NV_ASSERT(!"Unsupported chip ID");
+        break;
+    }
+}
+
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_init_common.c b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_init_common.c
new file mode 100644
index 000000000000..fe3496ed65cd
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_init_common.c
@@ -0,0 +1,521 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvutil.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_init.h"
+#include "nvrm_rmctrace.h"
+#include "nvrm_configuration.h"
+#include "nvrm_chiplib.h"
+#include "nvrm_pmu_private.h"
+#include "nvrm_processor.h"
+#include "nvrm_structure.h"
+#include "ap15rm_private.h"
+#include "ap15rm_private.h"
+#include "ap15rm_clocks.h"
+#include "nvodm_query.h"
+#include "nvodm_query_pins.h"
+#include "common/nvrm_hwintf.h"
+#include "nvrm_pinmux_utils.h"
+#include "nvrm_minikernel.h"
+#include "ap15/arapb_misc.h" // chipid, has to be the same for all chips
+#include "ap15/arapbpm.h"
+#include "ap15/arfuse.h"
+
+extern NvRmCfgMap g_CfgMap[];
+
+void NvRmPrivMemoryInfo( NvRmDeviceHandle hDevice );
+void NvRmPrivReadChipId( NvRmDeviceHandle rm );
+void NvRmPrivGetSku( NvRmDeviceHandle rm );
+/** Returns the pointer to the relocation table */
+NvU32 *NvRmPrivGetRelocationTable( NvRmDeviceHandle hDevice );
+NvError NvRmPrivMapApertures( NvRmDeviceHandle rm );
+void NvRmPrivUnmapApertures( NvRmDeviceHandle rm );
+NvU32 NvRmPrivGetBctCustomerOption(NvRmDeviceHandle hRm);
+
+NvRmCfgMap g_CfgMap[] =
+{
+    { "NV_CFG_RMC_FILE", NvRmCfgType_String, (void *)"",
+        STRUCT_OFFSET(RmConfigurationVariables, RMCTraceFileName) },
+
+    /* don't need chiplib for non-sim builds */
+    { "NV_CFG_CHIPLIB", NvRmCfgType_String, (void *)"",
+        STRUCT_OFFSET(RmConfigurationVariables, Chiplib) },
+
+    { "NV_CFG_CHIPLIB_ARGS", NvRmCfgType_String, (void *)"",
+        STRUCT_OFFSET(RmConfigurationVariables, ChiplibArgs) },
+
+    { 0 }
+};
+
+NvRmModuleTable *
+NvRmPrivGetModuleTable(
+    NvRmDeviceHandle hDevice )
+{
+    return &hDevice->ModuleTable;
+}
+
+NvU32 *
+NvRmPrivGetRelocationTable( NvRmDeviceHandle hDevice )
+{
+    switch( hDevice->ChipId.Id ) {
+    case 0x15:
+        return NvRmPrivAp15GetRelocationTable( hDevice );
+    case 0x16:
+        return NvRmPrivAp16GetRelocationTable( hDevice );
+    case 0x20:
+        return NvRmPrivAp20GetRelocationTable( hDevice );
+    default:
+        NV_ASSERT(!"Invalid Chip" );
+        return 0;
+    }
+}
+
+void
+NvRmPrivReadChipId( NvRmDeviceHandle rm )
+{
+#if (NVCPU_IS_X86 && NVOS_IS_WINDOWS)
+    NvRmChipId *id;
+    NV_ASSERT( rm );
+
+    id = &rm->ChipId;
+
+    id->Family = NvRmChipFamily_HandheldSoc;
+    id->Id = 0x15;
+    id->Major = 0x0;
+    id->Minor = 0x0;
+    id->SKU = 0x0;
+    id->Netlist = 0x0;
+    id->Patch = 0x0;
+#else
+    NvU32 reg;
+    NvRmChipId *id;
+    NvU32 fam;
+    char *s;
+    NvU8 *VirtAddr;
+    NvError e;
+
+    NV_ASSERT( rm );
+    id = &rm->ChipId;
+
+    /* Hard coding the address of the chip ID address space, as we haven't yet
+     * parsed the relocation table.
+     */
+    e = NvRmPhysicalMemMap(0x70000000, 0x1000, NVOS_MEM_READ_WRITE,
+        NvOsMemAttribute_Uncached, (void **)&VirtAddr);
+    if (e != NvSuccess)
+    {
+        NV_DEBUG_PRINTF(("APB misc aperture map failure\n"));
+        return;
+    }
+
+    /* chip id is in the misc aperture */
+    reg = NV_READ32( VirtAddr + APB_MISC_GP_HIDREV_0 );
+    id->Id = (NvU16)NV_DRF_VAL( APB_MISC_GP, HIDREV, CHIPID, reg );
+    id->Major = (NvU8)NV_DRF_VAL( APB_MISC_GP, HIDREV, MAJORREV, reg );
+    id->Minor = (NvU8)NV_DRF_VAL( APB_MISC_GP, HIDREV, MINORREV, reg );
+
+    fam = NV_DRF_VAL( APB_MISC_GP, HIDREV, HIDFAM, reg );
+    switch( fam ) {
+    case APB_MISC_GP_HIDREV_0_HIDFAM_GPU:
+        id->Family = NvRmChipFamily_Gpu;
+        s = "GPU";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD:
+        id->Family = NvRmChipFamily_Handheld;
+        s = "Handheld";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_BR_CHIPS:
+        id->Family = NvRmChipFamily_BrChips;
+        s = "BrChips";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_CRUSH:
+        id->Family = NvRmChipFamily_Crush;
+        s = "Crush";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_MCP:
+        id->Family = NvRmChipFamily_Mcp;
+        s = "MCP";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_CK:
+        id->Family = NvRmChipFamily_Ck;
+        s = "Ck";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_VAIO:
+        id->Family = NvRmChipFamily_Vaio;
+        s = "Vaio";
+        break;
+    case APB_MISC_GP_HIDREV_0_HIDFAM_HANDHELD_SOC:
+        id->Family = NvRmChipFamily_HandheldSoc;
+        s = "Handheld SOC";
+        break;
+    default:
+        NV_ASSERT( !"bad chip family" );
+        NvRmPhysicalMemUnmap(VirtAddr, 0x1000);
+        return;
+    }
+
+    reg = NV_READ32( VirtAddr + APB_MISC_GP_EMU_REVID_0 );
+    id->Netlist = (NvU16)NV_DRF_VAL( APB_MISC_GP, EMU_REVID, NETLIST, reg );
+    id->Patch = (NvU16)NV_DRF_VAL( APB_MISC_GP, EMU_REVID, PATCH, reg );
+
+    if( id->Major == 0 )
+    {
+        char *emu;
+        if( id->Netlist == 0 )
+        {
+            NvOsDebugPrintf( "Simulation Chip: 0x%x\n", id->Id );
+        }
+        else
+        {
+            if( id->Minor == 0 )
+            {
+                emu = "QuickTurn";
+            }
+            else
+            {
+                emu = "FPGA";
+            }
+
+            NvOsDebugPrintf( "Emulation (%s) Chip: 0x%x Netlist: 0x%x "
+                "Patch: 0x%x\n", emu, id->Id, id->Netlist, id->Patch );
+        }
+    }
+    else
+    {
+        // on real silicon
+
+        NvRmPrivGetSku( rm );
+
+        NvOsDebugPrintf( "Chip Id: 0x%x (%s) Major: 0x%x Minor: 0x%x "
+            "SKU: 0x%x\n", id->Id, s, id->Major, id->Minor, id->SKU );
+    }
+
+    // add a sanity check here, so that if we think we are on sim, but don't
+    // detect a sim/quickturn netlist bail out with an error
+    if ( NvRmIsSimulation() && id->Major != 0 )
+    {
+        // this should all get optimized away in release builds because the
+        // above will get evaluated to if ( 0 )
+        NV_ASSERT(!"invalid major version number for simulation");
+    }
+    NvRmPhysicalMemUnmap(VirtAddr, 0x1000);
+#endif
+}
+
+void
+NvRmPrivGetSku( NvRmDeviceHandle rm )
+{
+    NvError e;
+    NvRmChipId *id;
+    NvU8 *FuseVirt;
+    NvU32 reg;
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+    NvU8 *CarVirt = 0;
+#endif
+
+    NV_ASSERT( rm );
+    id = &rm->ChipId;
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+    // Enable fuse clock
+    e = NvRmPhysicalMemMap(0x60006000, 0x1000, NVOS_MEM_READ_WRITE,
+        NvOsMemAttribute_Uncached, (void **)&CarVirt);
+    if (e == NvSuccess)
+    {
+       reg = NV_READ32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
+       reg |= 0x80;
+       NV_WRITE32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, reg);
+    }
+#endif
+
+    /* Read the fuse only on real silicon, as it was not gauranteed to be
+     * preset on the eluation/simulation platforms.
+     */
+    e = NvRmPhysicalMemMap(0x7000f800, 0x400, NVOS_MEM_READ_WRITE,
+        NvOsMemAttribute_Uncached, (void **)&FuseVirt);
+    if (e == NvSuccess)
+    {
+        // Read the SKU from the fuse module.
+        reg = NV_READ32( FuseVirt + FUSE_SKU_INFO_0 );
+        id->SKU = (NvU16)reg;
+        NvRmPhysicalMemUnmap(FuseVirt, 0x400);
+
+#if NV_USE_FUSE_CLOCK_ENABLE
+        // Disable fuse clock
+        if (CarVirt)
+        {
+            reg = NV_READ32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0);
+            reg &= ~0x80;
+            NV_WRITE32(CarVirt + CLK_RST_CONTROLLER_CLK_OUT_ENB_H_0, reg);
+            NvRmPhysicalMemUnmap(CarVirt, 0x1000);
+        }
+#endif
+    } else
+    {
+        NV_ASSERT(!"Cannot map the FUSE aperture to get the SKU");
+        id->SKU = 0;
+    }
+}
+
+NvError
+NvRmPrivMapApertures( NvRmDeviceHandle rm )
+{
+    NvRmModuleTable *tbl;
+    NvRmModuleInstance *inst;
+    NvRmModule *mod;
+    NvU32 devid;
+    NvU32 i;
+    NvError e;
+
+    NV_ASSERT( rm );
+
+    /* loop over the instance list and map everything */
+    tbl = &rm->ModuleTable;
+    mod = tbl->Modules;
+    for( i = 0; i < NvRmPrivModuleID_Num; i++ )
+    {
+        if( mod[i].Index == NVRM_MODULE_INVALID )
+        {
+            continue;
+        }
+
+        if ((i != NvRmPrivModuleID_Ahb_Arb_Ctrl ) &&
+            (i != NvRmPrivModuleID_ApbDma ) &&
+            (i != NvRmPrivModuleID_ApbDmaChannel ) &&
+            (i != NvRmPrivModuleID_ClockAndReset ) &&
+            (i != NvRmPrivModuleID_ExternalMemoryController ) &&
+            (i != NvRmPrivModuleID_Gpio ) &&
+            (i != NvRmPrivModuleID_Interrupt ) &&
+            (i != NvRmPrivModuleID_InterruptArbGnt ) &&
+            (i != NvRmPrivModuleID_InterruptDrq ) &&
+            (i != NvRmPrivModuleID_MemoryController ) &&
+            (i != NvRmModuleID_Misc) &&
+            (i != NvRmPrivModuleID_ArmPerif) &&
+            (i != NvRmModuleID_3D) &&
+            (i != NvRmModuleID_CacheMemCtrl ) &&
+            (i != NvRmModuleID_Display) &&
+            (i != NvRmModuleID_Dvc) &&
+            (i != NvRmModuleID_FlowCtrl ) &&
+            (i != NvRmModuleID_Fuse ) &&
+            (i != NvRmModuleID_GraphicsHost ) &&
+            (i != NvRmModuleID_I2c) &&
+            (i != NvRmModuleID_Isp) &&
+            (i != NvRmModuleID_Mpe) &&
+            (i != NvRmModuleID_Pmif ) &&
+            (i != NvRmModuleID_Mipi ) &&
+            (i != NvRmModuleID_ResourceSema ) &&
+            (i != NvRmModuleID_SysStatMonitor ) &&
+            (i != NvRmModuleID_TimerUs ) &&
+            (i != NvRmModuleID_Vde ) &&
+            (i != NvRmModuleID_ExceptionVector ) &&
+            (i != NvRmModuleID_Usb2Otg ) &&
+            (i != NvRmModuleID_Vi)
+            )
+        {
+            continue;
+        }
+
+        /* FIXME If the multiple instances of the same module is adjacent to
+         * each other then we can do one allocation for all those modules.
+         */
+
+        /* map all of the device instances */
+        inst = tbl->ModInst + mod[i].Index;
+        devid = inst->DeviceId;
+        while( devid == inst->DeviceId )
+        {
+            /* If this is a device that actually has an aperture... */
+            if (inst->PhysAddr)
+            {
+                e = NvRmPhysicalMemMap(
+                        inst->PhysAddr, inst->Length, NVOS_MEM_READ_WRITE,
+                        NvOsMemAttribute_Uncached, &inst->VirtAddr);
+                if (e != NvSuccess)
+                {
+                    NV_DEBUG_PRINTF(("Device %d at physical addr 0x%X has no "
+                        "virtual mapping\n", devid, inst->PhysAddr));
+                    return e;
+                }
+            }
+
+            inst++;
+        }
+    }
+
+    return NvSuccess;
+}
+
+void
+NvRmPrivUnmapApertures( NvRmDeviceHandle rm )
+{
+    NvRmModuleTable *tbl;
+    NvRmModuleInstance *inst;
+    NvRmModule *mod;
+    NvU32 devid;
+    NvU32 i;
+
+    NV_ASSERT( rm );
+
+    /* loop over the instance list and unmap everything */
+    tbl = &rm->ModuleTable;
+    mod = tbl->Modules;
+    for( i = 0; i < NvRmPrivModuleID_Num; i++ )
+    {
+        if( mod[i].Index == NVRM_MODULE_INVALID )
+        {
+            continue;
+        }
+
+        /* map all of the device instances */
+        inst = tbl->ModInst + mod[i].Index;
+        devid = inst->DeviceId;
+        while( devid == inst->DeviceId )
+        {
+            NvRmPhysicalMemUnmap( inst->VirtAddr, inst->Length );
+            inst++;
+        }
+    }
+}
+
+NvU32
+NvRmPrivGetBctCustomerOption(NvRmDeviceHandle hRm)
+{
+    if (!NvRmIsSimulation())
+    {
+        return NV_REGR(hRm, NvRmModuleID_Pmif, 0, APBDEV_PMC_SCRATCH20_0);
+    }
+    else
+    {
+        return 0;
+    }
+}
+
+NvRmChipId *
+NvRmPrivGetChipId(
+    NvRmDeviceHandle hDevice )
+{
+    return &hDevice->ChipId;
+}
+
+#if !NV_OAL
+void NvRmBasicInit(NvRmDeviceHandle * pHandle)
+{
+    NvRmDevice *rm = 0;
+    NvError err;
+    NvU32 *table = 0;
+    NvU32 BctCustomerOption = 0;
+
+    *pHandle = 0;
+    rm = NvRmPrivGetRmDeviceHandle();
+
+    if( rm->bBasicInit )
+    {
+        *pHandle = rm;
+        return; 
+    }
+
+    /* get the default configuration */
+    err = NvRmPrivGetDefaultCfg( g_CfgMap, &rm->cfg );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    /* get the requested configuration */
+    err = NvRmPrivReadCfgVars( g_CfgMap, &rm->cfg );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    /* Read the chip Id and store in the Rm structure. */
+    NvRmPrivReadChipId( rm );
+
+    // init the module control (relocation table, resets, etc.)
+    table = NvRmPrivGetRelocationTable( rm );
+    if( !table )
+    {
+        goto fail;
+    }
+
+    err = NvRmPrivModuleInit( &rm->ModuleTable, table );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    NvRmPrivMemoryInfo( rm );
+
+    // setup the hw apertures
+    err = NvRmPrivMapApertures( rm );
+    if( err != NvSuccess )
+    {
+        goto fail;
+    }
+
+    BctCustomerOption = NvRmPrivGetBctCustomerOption(rm);
+    err = NvRmPrivInitKeyList(rm, &BctCustomerOption, 1);
+    if (err != NvSuccess)
+    {
+        goto fail;
+    }
+
+    // Now populate the logical interrupt table.
+    NvRmPrivInterruptTableInit( rm );
+
+    rm->bBasicInit = NV_TRUE;
+    // basic init is a super-set of preinit
+    rm->bPreInit = NV_TRUE;
+    *pHandle = rm;
+
+fail:
+    return;
+}
+
+void
+NvRmBasicClose(NvRmDeviceHandle handle)
+{
+    if (!NVOS_IS_WINDOWS_X86)
+    {
+        NvRmPrivDeInitKeyList(handle);
+        /* unmap the apertures */
+        NvRmPrivUnmapApertures( handle );
+        /* deallocate the instance table */
+        NvRmPrivModuleDeinit( &handle->ModuleTable );
+    }
+}
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_pinmux_utils.h b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_pinmux_utils.h
new file mode 100755
index 000000000000..f9fd782a3315
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_pinmux_utils.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef AP15RM_PINMUX_UTILS_H
+#define AP15RM_PINMUX_UTILS_H
+
+/*
+ * ap15rm_pinmux_utils.h defines the pinmux macros to implement for the resource
+ * manager.
+ */
+
+#include "nvrm_pinmux_utils.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/* When the state is BranchLink, this is the number of words to increment
+ * the current "PC"
+ */
+#define MUX_ENTRY_0_BRANCH_ADDRESS_RANGE 31:2
+//  The incr1 offset from TRISTATE_REG_A_0 to the pad group's tristate register
+#define MUX_ENTRY_0_TS_OFFSET_RANGE 31:26
+//  The bit position within the tristate register for the pad group
+#define MUX_ENTRY_0_TS_SHIFT_RANGE 25:21
+//  The incr1 offset from PIN_MUX_CTL_A_0 to the pad group's pin mux control register
+#define MUX_ENTRY_0_MUX_CTL_OFFSET_RANGE 20:17
+//  The bit position within the pin mux control register for the pad group
+#define MUX_ENTRY_0_MUX_CTL_SHIFT_RANGE 16:12
+//  The mask for the pad group -- expanded to 3b for forward-compatibility
+#define MUX_ENTRY_0_MUX_CTL_MASK_RANGE 10:8
+//  When a pad group needs to be owned (or disowned), this value is applied
+#define MUX_ENTRY_0_MUX_CTL_SET_RANGE 7:5
+//  This value is compared against, to determine if the pad group should be disowned
+#define MUX_ENTRY_0_MUX_CTL_UNSET_RANGE 4:2
+//  for extended opcodes, this field is set with the extended opcode
+#define MUX_ENTRY_0_OPCODE_EXTENSION_RANGE 3:2
+//  The state for this entry
+#define MUX_ENTRY_0_STATE_RANGE 1:0
+
+/*  This macro is used to generate 32b value to program the  tristate& pad mux control
+ *  registers for config/unconfig for a padgroup
+ */
+#define PIN_MUX_ENTRY(TSOFF,TSSHIFT,MUXOFF,MUXSHIFT,MUXMASK,MUXSET,MUXUNSET,STAT) \
+    (NV_DRF_NUM(MUX, ENTRY, TS_OFFSET, TSOFF) | NV_DRF_NUM(MUX, ENTRY, TS_SHIFT, TSSHIFT) | \
+    NV_DRF_NUM(MUX, ENTRY, MUX_CTL_OFFSET, MUXOFF) | NV_DRF_NUM(MUX, ENTRY, MUX_CTL_SHIFT, MUXSHIFT) | \
+    NV_DRF_NUM(MUX, ENTRY,MUX_CTL_MASK, MUXMASK) | NV_DRF_NUM(MUX, ENTRY,MUX_CTL_SET, MUXSET) | \
+    NV_DRF_NUM(MUX, ENTRY, MUX_CTL_UNSET,MUXUNSET) | NV_DRF_NUM(MUX, ENTRY, STATE,STAT))
+
+//  This is used to program the tristate & pad mux control registers for a pad group
+#define CONFIG_VAL(TRISTATE_REG, MUXCTL_REG, PADGROUP, MUX) \
+    (PIN_MUX_ENTRY(((APB_MISC_PP_TRISTATE_REG_##TRISTATE_REG##_0 - APB_MISC_PP_TRISTATE_REG_A_0)>>2), \
+                APB_MISC_PP_TRISTATE_REG_##TRISTATE_REG##_0_Z_##PADGROUP##_SHIFT, \
+                ((APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0 - APB_MISC_PP_PIN_MUX_CTL_A_0) >> 2), \
+                APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_SHIFT, \
+                APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_DEFAULT_MASK, \
+                APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_##MUX, \
+                0, PinMuxConfig_Set))
+
+/* This macro is used to compare a pad group against a potentially conflicting
+ * enum (where the conflict is caused by setting a new config), and to resolve
+ * the conflict by setting the conflicting pad group to a different,
+ * non-conflicting option. Read this as: if (PADGROUP) is equal to
+ * (CONFLICTMUX), replace it with (RESOLUTIONMUX)
+ */
+#define UNCONFIG_VAL(MUXCTL_REG, PADGROUP, CONFLICTMUX, RESOLUTIONMUX) \
+    (PIN_MUX_ENTRY(0, 0, \
+                  ((APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0 - APB_MISC_PP_PIN_MUX_CTL_A_0) >> 2), \
+                  APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_SHIFT, \
+                  APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_DEFAULT_MASK, \
+                  APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_##RESOLUTIONMUX, \
+                  APB_MISC_PP_PIN_MUX_CTL_##MUXCTL_REG##_0_##PADGROUP##_SEL_##CONFLICTMUX, \
+                  PinMuxConfig_Unset))
+// TODO: Need to implement in PINMUX_DEBUG_MODE
+#define TRISTATE_UNUSED(PADGROUP, TRISTATE_REG) \
+        (PIN_MUX_ENTRY(((APB_MISC_PP_TRISTATE_REG_##TRISTATE_REG##_0 - APB_MISC_PP_TRISTATE_REG_A_0)>>2), \
+                APB_MISC_PP_TRISTATE_REG_##TRISTATE_REG##_0_Z_##PADGROUP##_SHIFT, \
+                0, 0, 0, 0, 0, -1))
+
+
+#if NVRM_PINMUX_DEBUG_FLAG
+#define CONFIG(TRISTATE_REG, MUXCTL_REG, PADGROUP, MUX) \
+    (CONFIG_VAL(TRISTATE_REG, MUXCTL_REG, PADGROUP, MUX)), \
+    (NvU32)(const void*)(#MUXCTL_REG "_0_" #PADGROUP "_SEL to " #MUX), \
+    (NvU32)(const void*)(#TRISTATE_REG "_0_Z_" #PADGROUP)
+
+#define UNCONFIG(MUXCTL_REG, PADGROUP, CONFLICTMUX, RESOLUTIONMUX) \
+    (UNCONFIG_VAL(MUXCTL_REG, PADGROUP, CONFLICTMUX, RESOLUTIONMUX)), \
+    (NvU32)(const void*)(#MUXCTL_REG "_0_" #PADGROUP "_SEL from " #CONFLICTMUX " to " #RESOLUTIONMUX), \
+    (NvU32)(const void*)(NULL)
+#else
+#define CONFIG(TRISTATE_REG, MUXCTL_REG, PADGROUP, MUX) \
+    (CONFIG_VAL(TRISTATE_REG, MUXCTL_REG, PADGROUP, MUX))
+#define UNCONFIG(MUXCTL_REG, PADGROUP, CONFLICTMUX, RESOLUTIONMUX) \
+    (UNCONFIG_VAL(MUXCTL_REG, PADGROUP, CONFLICTMUX, RESOLUTIONMUX))
+#endif
+
+//  The below entries define the table format for GPIO Port/Pin-to-Tristate register mappings
+//  Each table entry is 16b, and one is stored for every GPIO Port/Pin on the chip
+#define MUX_GPIOMAP_0_TS_OFFSET_RANGE 15:10
+//  Defines where in the 32b register the tristate control is located
+#define MUX_GPIOMAP_0_TS_SHIFT_RANGE  4:0
+
+#define TRISTATE_ENTRY(TSOFFS, TSSHIFT) \
+    ((NvU16)(NV_DRF_NUM(MUX,GPIOMAP,TS_OFFSET,(TSOFFS)) | \
+             NV_DRF_NUM(MUX,GPIOMAP,TS_SHIFT,(TSSHIFT))))
+
+#define GPIO_TRISTATE(TRIREG,PADGROUP) \
+    (TRISTATE_ENTRY(((APB_MISC_PP_TRISTATE_REG_##TRIREG##_0 - APB_MISC_PP_TRISTATE_REG_A_0)>>2), \
+        APB_MISC_PP_TRISTATE_REG_##TRIREG##_0_Z_##PADGROUP##_SHIFT))
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // AP15RM_PINMUX_UTILS_H
+
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_pmc_scratch_map.h b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_pmc_scratch_map.h
new file mode 100644
index 000000000000..38cae693e547
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_pmc_scratch_map.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit:
+ *           Power Management Controller (PMC) scratch registers fields
+ *           definitions</b>
+ *
+ * @b Description: Defines SW-allocated fields in the PMC scratch registers
+ *  shared by boot and power management code in RM and OAL.
+ *
+ */
+
+
+#ifndef INCLUDED_AP15RM_PMC_SCRATCH_MAP_H
+#define INCLUDED_AP15RM_PMC_SCRATCH_MAP_H
+
+/*
+ * Scratch registers offsets are part of the HW specification in the below
+ * include file. Scratch registers fields are defined in this header via
+ * bit ranges compatible with nvrm_drf macros.
+ */
+#include "ap15/arapbpm.h"
+
+// Register APBDEV_PMC_SCRATCH0_0 (this is the only scratch register cleared on reset)
+//
+
+// RM clients combined power state (bits 4-7)
+#define APBDEV_PMC_SCRATCH0_0_RM_PWR_STATE_RANGE        11:8
+#define APBDEV_PMC_SCRATCH0_0_RM_LOAD_TRANSPORT_RANGE   15:12
+#define APBDEV_PMC_SCRATCH0_0_RM_DFS_FLAG_RANGE         27:16
+#define APBDEV_PMC_SCRATCH0_0_UPDATE_MODE_FLAG_RANGE     29:28
+#define APBDEV_PMC_SCRATCH0_0_OAL_RTC_INIT_RANGE        30:30
+#define APBDEV_PMC_SCRATCH0_0_RST_PWR_DET_RANGE         31:31
+
+// Register APBDEV_PMC_SCRATCH20_0, used to store the ODM customer data from the BCT
+#define APBDEV_PMC_SCRATCH20_0_BCT_ODM_DATA_RANGE       31:0
+
+// Register APBDEV_PMC_SCRATCH21_0
+//
+#define APBDEV_PMC_SCRATCH21_0_LP2_TIME_US              31:0
+
+#endif // INCLUDED_AP15RM_PMC_SCRATCH_MAP_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_power_dfs.h b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_power_dfs.h
new file mode 100644
index 000000000000..10889666d25c
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_power_dfs.h
@@ -0,0 +1,314 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Power Resource manager </b>
+ *
+ * @b Description: NvRM DFS parameters. 
+ * 
+ */
+
+#ifndef INCLUDED_AP15RM_POWER_DFS_H
+#define INCLUDED_AP15RM_POWER_DFS_H
+
+#include "nvrm_power.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// Min KHz for CPU and AVP with regards to JTAG support - 1MHz * 8  = 8MHz
+// TODO: any other limitations on min KHz?
+// TODO: adjust boost parameters based on testing
+
+/**
+ * Default DFS algorithm parameters for CPU domain
+ */
+#define NVRM_DFS_PARAM_CPU_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    10000,  /* Minimum domain frequency 10 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        32000, /* Fixed frequency boost increase 32 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        4000,  /* Fixed frequency boost increase 4 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    3,      /* Relative adjustement of average freqiency 1/2^3 ~ 12% */ \
+    1,      /* Number of smaple intervals with NRT to trigger boost = 2 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ *  Default DFS algorithm parameters for AVP domain
+ */
+#define NVRM_DFS_PARAM_AVP_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    3,      /* Relative adjustement of average freqiency 1/2^3 ~ 12% */ \
+    2,      /* Number of smaple intervals with NRT to trigger boost = 3 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for System clock domain
+ */
+#define NVRM_DFS_PARAM_SYSTEM_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        32,    /* Proportional frequency boost decrease 32/256 ~ 12% */  \
+    },\
+    5,      /* Relative adjustement of average freqiency 1/2^5 ~ 3% */ \
+    2,      /* Number of smaple intervals with NRT to trigger boost = 3 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for AHB clock domain
+ */
+#define NVRM_DFS_PARAM_AHB_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        32,    /* Proportional frequency boost decrease 32/256 ~ 12% */  \
+    },\
+    0,      /* Relative adjustement of average freqiency 1/2^0 ~ 100% */ \
+    0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for APB clock domain
+ */
+#define NVRM_DFS_PARAM_APB_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    15000,  /* Minimum domain frequency 15 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        8000,  /* Fixed frequency boost increase 8 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        32,    /* Proportional frequency boost decrease 32/256 ~ 12% */  \
+    },\
+    0,      /* Relative adjustement of average freqiency 1/2^0 ~ 100% */ \
+    0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for Video-pipe clock domain
+ */
+#define NVRM_DFS_PARAM_VPIPE_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    24000,  /* Minimum domain frequency 24 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        16000, /* Fixed frequency RT boost increase 16 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    5,      /* Relative adjustement of average freqiency 1/2^5 ~ 3% */ \
+    3,      /* Number of smaple intervals with NRT to trigger boost = 4 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/**
+ * Default DFS algorithm parameters for EMC clock domain
+ */
+#define NVRM_DFS_PARAM_EMC_AP15 \
+    NvRmFreqMaximum, /* Maximum domain frequency set to h/w limit */ \
+    16000,  /* Minimum domain frequency 16 MHz */ \
+    1000,   /* Frequency change upper band 1 MHz */ \
+    1000,   /* Frequency change lower band 1 MHz */ \
+    {          /* RT starvation control parameters */ \
+        16000, /* Fixed frequency RT boost increase 16 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    {          /* NRT starvation control parameters */ \
+        1000,  /* Fixed frequency NRT boost increase 1 MHz */ \
+        255,   /* Proportional frequency boost increase 255/256 ~ 100% */ \
+        128,   /* Proportional frequency boost decrease 128/256 ~ 50% */  \
+    },\
+    0,      /* Relative adjustement of average freqiency 1/2^0 ~ 100% */ \
+    0,      /* Number of smaple intervals with NRT to trigger boost = 1 */ \
+    1       /* NRT idle cycles threshold = 1 */ 
+
+/// Default low corner for core voltage
+#define NVRM_AP15_LOW_CORE_MV (950)
+
+/// Core voltage in suspend
+#define NVRM_AP15_SUSPEND_CORE_MV (1000)
+
+/*****************************************************************************/
+
+/**
+ * Initializes activity monitors within the DFS module. Only activity
+ * monitors are affected. The rest of module's h/w is preserved.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ * 
+ * @return NvSuccess if initialization completed successfully
+ * or one of common error codes on failure.
+ */
+NvError NvRmPrivAp15SystatMonitorsInit(NvRmDfs* pDfs);
+NvError NvRmPrivAp15VdeMonitorsInit(NvRmDfs* pDfs);
+NvError NvRmPrivAp15EmcMonitorsInit(NvRmDfs* pDfs);
+
+/**
+ * Deinitializes activity monitors within the DFS module. Only activity
+ * monitors are affected. The rest of module's h/w is preserved.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ */
+void NvRmPrivAp15SystatMonitorsDeinit(NvRmDfs* pDfs);
+void NvRmPrivAp15VdeMonitorsDeinit(NvRmDfs* pDfs);
+void NvRmPrivAp15EmcMonitorsDeinit(NvRmDfs* pDfs);
+
+/**
+ * Starts activity monitors in the DFS module for the next sample interval.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ * @param pDfsKHz - A pointer to current DFS clock frequencies structure.
+ * @param IntervalMs Next sampling interval in ms.
+ */
+void
+NvRmPrivAp15SystatMonitorsStart(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs);
+void
+NvRmPrivAp15VdeMonitorsStart(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs);
+void
+NvRmPrivAp15EmcMonitorsStart(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntervalMs);
+
+/**
+ * Reads idle count from activity monitors in the DFS module. The monitors are
+ * stopped.
+ * 
+ * @param pDfs - A pointer to DFS structure.
+ * @param pDfsKHz - A pointer to current DFS clock frequencies structure.
+ * @param pIdleData - A pointer to idle cycles structure to be filled in with
+ *  data read from the monitor.
+ * 
+ */
+void
+NvRmPrivAp15SystatMonitorsRead(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData);
+void
+NvRmPrivAp15VdeMonitorsRead(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData);
+void
+NvRmPrivAp15EmcMonitorsRead(
+    const NvRmDfs* pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData);
+
+/**
+ * Changes RAM timing SVOP settings.
+ * 
+ * @param hRm The RM device handle.
+ * @param SvopSetting New SVOP setting.
+ */
+void
+NvRmPrivAp15SetSvopControls(
+    NvRmDeviceHandle hRm,
+    NvU32 SvopSetting);
+
+/**
+ * Gets uS Timer RM virtual address,
+ * 
+ * @param hRm The RM device handle.
+ * 
+ * @return uS Timer RM virtual address mapped by RM
+ */
+void* NvRmPrivAp15GetTimerUsVirtAddr(NvRmDeviceHandle hRm);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_AP15RM_POWER_DFS_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_private.h b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_private.h
new file mode 100644
index 000000000000..6d8a99037952
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_private.h
@@ -0,0 +1,322 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef AP15RM_PRIVATE_H
+#define AP15RM_PRIVATE_H
+
+/*
+ * ap15rm_private.h defines the private implementation functions for the
+ * resource manager.
+ */
+
+#include "nvcommon.h"
+#include "nvrm_structure.h"
+#include "nvrm_power_private.h"
+#include "nvodm_query.h"
+#include "nvos.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// Enable this macro to catch spurious interrupts. By default this is disabled
+// as we allow spurious interrupts from GPIO controller.
+#if 0
+#define NVRM_INTR_DECODE_ASSERT(x) NV_ASSERT(x)
+#else
+#define NVRM_INTR_DECODE_ASSERT(x) 
+#endif
+
+/**
+ * Find a module given its physical register address
+ *
+ * @param hDevice The RM instance
+ * @param Address Physical base address of the module's registers
+ * @param ModuleId Output parameter to hold the Id of the module (includes
+ *  instance).
+ *
+ * @retval NvSuccess The module id was successfully identified.
+ * @retval NvError_NotSupported No module exists at the specified
+ *  physical base address.
+ * @retval NvError_BadValue Invalid input parameters.
+ */
+NvError
+NvRmPrivFindModule(NvRmDeviceHandle hDevice, NvU32 Address,
+    NvRmPrivModuleID* ModuleId);
+
+/** Driver init for interrupts.
+ */
+void
+NvRmPrivInterruptTableInit( NvRmDeviceHandle hDevice );
+
+/**
+ * Enable interrupt source for interrupt decoder.
+ */
+/**
+ * Disable interrupt source for interrupt decoder.
+ */
+
+/**
+ * Main controller interrupt enable/disable for sub-controllers.
+ */
+
+/**
+ * Interrupt source enable/disable for AP15 main interrupt controllers.
+ */
+
+/**
+ * Chip unque id for AP15 and ap16.
+ */
+NvError
+NvRmPrivAp15ChipUniqueId(
+    NvRmDeviceHandle hDevHandle,
+    void* pId);
+
+// Initialize/deinitialize for various RM submodules.
+NvError NvRmPrivDmaInit(NvRmDeviceHandle hDevice);
+void NvRmPrivDmaDeInit(void);
+
+NvError NvRmPrivSpiSlinkInit(NvRmDeviceHandle hDevice);
+void NvRmPrivSpiSlinkDeInit(void);
+
+/**
+ * Retrieves module instance record pointer given module ID
+ *
+ * @param hDevice The RM device handle
+ * @param ModuleId The combined module ID and instance of the target module
+ * @param out Output storage pointer for instance record pointer
+ *
+ * @retval NvSuccess if instance pointer was successfully retrieved
+ * @retval NvError_BadValue if module ID is invalid
+ */
+NvError
+NvRmPrivGetModuleInstance(
+     NvRmDeviceHandle hDevice,
+     NvRmModuleID ModuleId,
+     NvRmModuleInstance **out);
+
+/*
+ *  OS specific interrupt initialization
+ */
+void
+NvRmPrivInterruptStart(NvRmDeviceHandle hDevice);
+
+/**
+ * Clear out anything that registered for an interrupt but didn't clean up
+ * afteritself.
+ */
+
+void
+NvRmPrivInterruptShutdown(NvRmDeviceHandle hDevice);
+
+/**
+ * Initializes the RM's internal state for tracking the pin-mux register
+ * configurations.  This is done by iteratively applying the pre-defined
+ * configurations from ODM Query (see nvodm_query_pinmux.c).  This function
+ * applies an "enable" setting when there's a match against the static
+ * declarations (in ODM Query).
+ *
+ * As this function walks the configuration list defined in ODM Query, it does
+ * *not* disable (apply tristate settings to) unused pin-groups for a given I/O
+ * module's configuration.  That would be an exercise in futility, since the
+ * current I/O module cannot know if another I/O module is using any unclaimed
+ * pin-groups which the current I/O module configuration might otherwise use.
+ * That system-wide view of pin-group resources is the responsibility of the
+ * System Designer who selects pin-group combinations from the pin-mux
+ * documentation (see //sw/mobile/docs/hw/ap15/pin_mux_configurations.xls).
+ * The selected combination of pin-mux settings (which cannot be in conflict)
+ * are then saved to the configuration tables in ODM Query.
+ *
+ * Further, this initialization routine enables the configuration identified by
+ * the ODM Query tables.  Any pre-existing settings are not changed, except as
+ * defined by the static configuration tables in ODM Query.  Therefore, the
+ * System Designer *must* also account for pre-existing power-on-reset (POR)
+ * values when determining the valid pin-mux configurations saved in ODM Query.
+ *
+ * Finally, any use of the pin-mux registers prior to RM initialization *must*
+ * be consistent with the ODM Query tables, otherwise the system configuration
+ * is not deterministic (and may violate the definition applied by the System
+ * Designer).  Once RM initializes its pin-mux state, any direct access to the
+ * pin-mux registers (ie, not using the RM PinMux API) is strictly prohibited.
+ *
+ * @param hDevice The RM device handle.
+ */
+void
+NvRmPrivInitPinMux(NvRmDeviceHandle hDevice);
+
+/**
+ * Initializes the clock manager.
+ *
+ * @param hRmDevice The RM device handle
+ *
+ * @return NvSuccess if initialization completed successfully
+ *  or one of common error codes on failure
+ */
+NvError
+NvRmPrivClocksInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Deinitializes the clock manager.
+ *
+ * @param hRmDevice The RM device handle
+ */
+void
+NvRmPrivClocksDeinit(NvRmDeviceHandle hRmDevice);
+
+
+/*** Private Interrupt API's ***/
+
+
+/**
+ * Performs primary interrupt decode for IRQ interrupts in the main
+ * interrupt controllers.
+ *
+ * @param hRmDevice The RM device handle.
+ * @returns The IRQ number of the interrupting device or NVRM_IRQ_INVALID
+ * if no interrupting device was found.
+ */
+
+
+/**
+ * Performs secondary IRQ interrupt decode for interrupting devices
+ * that are interrupt sub-controllers.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param Irq Primary IRQ number returned from NvRmInterruptPrimaryDecodeIrq().
+ * @returns The IRQ number of the interrupting device.
+ */
+
+
+
+/**
+ * Performs primary interrupt decode for FIQ interrupts in the main
+ * interrupt controllers.
+ *
+ * @param hRmDevice The RM device handle.
+ * @returns The IRQ number of the interrupting device or NVRM_IRQ_INVALID
+ * if no interrupting device was found.
+ */
+
+
+
+/**
+ * Performs secondary FIQ interrupt decode for interrupting devices
+ * that are interrupt sub-controllers.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param Fiq Primary FIQ number returned from NvRmInterruptPrimaryDecodeFiq().
+ * @returns The FIQ number of the interrupting device.
+ */
+
+
+/**
+ * Suspend the dma.
+ */
+NvError NvRmPrivDmaSuspend(void);
+
+/**
+ * Resume the dma.
+ */
+NvError NvRmPrivDmaResume(void);
+
+/**
+ * Check Bond Out to make a module/instance invalid.
+ *
+ * @param hRm The RM device handle
+ */
+void NvRmPrivCheckBondOut( NvRmDeviceHandle hDevice );
+
+/** Returns bond out values and table for AP20 */
+void NvRmPrivAp20GetBondOut( NvRmDeviceHandle hDevice,
+                        const NvU32 **pTable, NvU32 *bondOut );
+
+/**
+ * This API should be sapringly used. There is a bug in the chiplib where the
+ * interrupt handler is not passed an argument. So, the handler will call this
+ * function to get the Rm handle.
+ */
+NvRmDeviceHandle NvRmPrivGetRmDeviceHandle( void );
+
+/** Returns the pointer to the relocation table of AP15 chip */
+NvU32 *NvRmPrivAp15GetRelocationTable( NvRmDeviceHandle hDevice );
+
+/** Returns the pointer to the relocation table of AP16 chip */
+NvU32 *NvRmPrivAp16GetRelocationTable( NvRmDeviceHandle hDevice );
+
+/** Returns the pointer to the relocation table of AP20 chip */
+NvU32 *NvRmPrivAp20GetRelocationTable( NvRmDeviceHandle hDevice );
+
+/** Basic reset of AP15 chip modules */
+void NvRmPrivAp15BasicReset( NvRmDeviceHandle hDevice );
+/** Basic reset of AP20 chip modules */
+void NvRmPrivAp20BasicReset( NvRmDeviceHandle hDevice );
+
+/** This API starts the memory controller error monitoring for AP15/AP16. */
+NvError NvRmPrivAp15McErrorMonitorStart( NvRmDeviceHandle hDevice );
+
+/** This API stops the memory controller error monitoring for AP15/AP16. */
+void NvRmPrivAp15McErrorMonitorStop( NvRmDeviceHandle hDevice );
+
+/** This API starts the memory controller error monitoring for AP20. */
+NvError NvRmPrivAp20McErrorMonitorStart( NvRmDeviceHandle hDevice );
+
+/** This API stops the memory controller error monitoring for AP20. */
+void NvRmPrivAp20McErrorMonitorStop( NvRmDeviceHandle hDevice );
+
+/** This API sets up the memory controller for AP15/AP16. */
+void NvRmPrivAp15SetupMc(NvRmDeviceHandle hRm);
+
+/** This API sets up the memory controller for AP20. */
+void NvRmPrivAp20SetupMc(NvRmDeviceHandle hRm);
+
+/* init and deinit the keylist */
+NvError NvRmPrivInitKeyList(NvRmDeviceHandle hRm, const NvU32*, NvU32);
+void NvRmPrivDeInitKeyList(NvRmDeviceHandle hRm);
+
+/**
+ * @brief Query the max interface freq supported by the board for a given
+ * Module.
+ *
+ * This API returns the max interface freq supported by the board based on the 
+ * ODM query. 
+ */
+NvRmFreqKHz
+NvRmPrivGetInterfaceMaxClock(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleId);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // AP15RM_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_xpc.c b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_xpc.c
new file mode 100644
index 000000000000..b0205c2110c9
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_xpc.c
@@ -0,0 +1,431 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Cross Proc Communication driver </b>
+ *
+ * @b Description: Implements the interface to the NvDdk XPC.
+ * 
+ */
+
+#include <linux/kernel.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+#include <mach/io.h>
+
+#include "nvrm_xpc.h"
+#include "nvrm_memmgr.h"
+#include "ap15rm_xpc_hw_private.h"
+#include "nvrm_hardware_access.h"
+#include "nvassert.h"
+#include "ap15/ararb_sema.h"
+#include "ap15/arictlr_arbgnt.h"
+#include "nvrm_avp_shrd_interrupt.h"
+
+// Minimum sdram offset required so that avp can access the address which is 
+// passed.
+// AVP can not access the 0x0000:0000 to 0x0000:0040
+enum { MIN_SDRAM_OFFSET = 0x100};
+
+
+//There are only 32 arb semaphores
+#define MAX_ARB_NUM 32
+
+#define ARBSEMA_REG_READ(pArbSemaVirtAdd, reg) \
+        NV_READ32(pArbSemaVirtAdd + (ARB_SEMA_##reg##_0))
+
+#define ARBSEMA_REG_WRITE(pArbSemaVirtAdd, reg, data) \
+        NV_WRITE32(pArbSemaVirtAdd + (ARB_SEMA_##reg##_0), (data));
+
+#define ARBGNT_REG_READ(pArbGntVirtAdd, reg) \
+        NV_READ32(pArbGntVirtAdd + (ARBGNT_##reg##_0))
+
+#define ARBGNT_REG_WRITE(pArbGntVirtAdd, reg, data) \
+        NV_WRITE32(pArbGntVirtAdd + (ARBGNT_##reg##_0), (data));
+
+static int s_arbInterruptHandle = -1;
+
+// Combines the Processor Xpc system details. This contains the details of the
+// receive/send message queue and messaging system.
+typedef struct NvRmPrivXpcMessageRec
+{
+    NvRmDeviceHandle hDevice;
+
+    // Hw mail box register.
+    CpuAvpHwMailBoxReg HwMailBoxReg;
+
+} NvRmPrivXpcMessage;
+
+typedef struct NvRmPrivXpcArbSemaRec
+{
+    NvRmDeviceHandle hDevice;
+    NvU8 *pArbSemaVirtAddr;
+    NvU8 *pArbGntVirtAddr;
+    NvOsSemaphoreHandle semaphore[MAX_ARB_NUM];
+    NvOsMutexHandle mutex[MAX_ARB_NUM];
+    NvOsIntrMutexHandle hIntrMutex;
+
+} NvRmPrivXpcArbSema;
+
+static NvRmPrivXpcArbSema s_ArbSema;
+
+//Forward declarations
+static NvError InitArbSemaSystem(NvRmDeviceHandle hDevice);
+static void ArbSemaIsr(void *args);
+NvU32 GetArbIdFromRmModuleId(NvRmModuleID modId);
+/**
+ * Initialize the cpu avp hw mail box address and map the hw register address 
+ * to virtual address.
+ * Thread Safety: Caller responsibility
+ */
+static NvError 
+InitializeCpuAvpHwMailBoxRegister(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    NvRmPhysAddr ResourceSemaPhysAddr;
+
+    // Get base address of the hw mail box register. This register is in the set
+    // of resource semaphore module Id.
+    ResourceSemaPhysAddr = TEGRA_RES_SEMA_BASE;
+    hXpcMessage->HwMailBoxReg.BankSize = TEGRA_RES_SEMA_SIZE;
+
+    // Map the base address to the virtual address.
+    hXpcMessage->HwMailBoxReg.pHwMailBoxRegBaseVirtAddr =
+      IO_ADDRESS(ResourceSemaPhysAddr);
+
+    NvRmPrivXpcHwResetOutbox(&hXpcMessage->HwMailBoxReg);
+
+    return NvSuccess;
+}
+
+/**
+ * DeInitialize the cpu avp hw mail box address and unmap the hw register address 
+ * virtual address.
+ * Thread Safety: Caller responsibility
+ */
+static void DeInitializeCpuAvpHwMailBoxRegister(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    hXpcMessage->HwMailBoxReg.pHwMailBoxRegBaseVirtAddr = NULL;        
+}
+
+/**
+ * Create the cpu-avp messaging system.
+ * This function will call other helper function to create the messaging technique 
+ * used for cpu-avp communication.
+ * Thread Safety: Caller responsibility
+ */
+static NvError 
+CreateCpuAvpMessagingSystem(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    NvError Error = NvSuccess;
+
+    Error = InitializeCpuAvpHwMailBoxRegister(hXpcMessage);
+
+#if NV_IS_AVP
+    hXpcMessage->HwMailBoxReg.IsCpu = NV_FALSE;
+#else            
+    hXpcMessage->HwMailBoxReg.IsCpu = NV_TRUE;
+#endif            
+    
+    // If error found then destroy all the allocation and initialization,
+    if (Error)
+        DeInitializeCpuAvpHwMailBoxRegister(hXpcMessage);
+
+    return Error;
+}
+
+
+/**
+ * Destroy the cpu-avp messaging system.
+ * This function destroy all the allocation/initialization done for creating
+ * the cpu-avp messaging system.
+ * Thread Safety: Caller responsibility
+ */
+static void DestroyCpuAvpMessagingSystem(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    // Destroy the cpu-avp hw mail box registers. 
+    DeInitializeCpuAvpHwMailBoxRegister(hXpcMessage);
+    hXpcMessage->HwMailBoxReg.pHwMailBoxRegBaseVirtAddr = NULL;
+    hXpcMessage->HwMailBoxReg.BankSize = 0;
+}
+
+
+NvError 
+NvRmPrivXpcCreate(
+    NvRmDeviceHandle hDevice,
+    NvRmPrivXpcMessageHandle *phXpcMessage)
+{
+    NvError Error = NvSuccess;
+    NvRmPrivXpcMessageHandle hNewXpcMsgHandle = NULL;
+
+    *phXpcMessage = NULL;
+
+    // Allocates the memory for the xpc message handle.
+    hNewXpcMsgHandle = NvOsAlloc(sizeof(*hNewXpcMsgHandle));
+    if (!hNewXpcMsgHandle)
+    {
+        return NvError_InsufficientMemory;
+    }
+
+    // Initialize all the members of the xpc message handle.
+    hNewXpcMsgHandle->hDevice = hDevice;
+    hNewXpcMsgHandle->HwMailBoxReg.pHwMailBoxRegBaseVirtAddr = NULL;
+    hNewXpcMsgHandle->HwMailBoxReg.BankSize = 0;
+
+    // Create the messaging system between the processors.
+    Error = CreateCpuAvpMessagingSystem(hNewXpcMsgHandle);
+
+    // if error the destroy all allocations done here.    
+    if (Error)
+    {
+        NvOsFree(hNewXpcMsgHandle);
+        hNewXpcMsgHandle = NULL;
+    }
+
+#if NV_IS_AVP
+    Error = InitArbSemaSystem(hDevice);
+    if (Error)
+    {
+        NvOsFree(hNewXpcMsgHandle);
+        hNewXpcMsgHandle = NULL;
+    }
+#endif
+
+    // Copy the new xpc message handle into the passed parameter.
+    *phXpcMessage = hNewXpcMsgHandle;
+    return Error;
+}
+
+
+/**
+ * Destroy the Rm Xpc message handle.
+ * Thread Safety: It is provided inside the function.
+ */
+void NvRmPrivXpcDestroy(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    // If not a null pointer then destroy.
+    if (hXpcMessage)
+    {
+        // Destroy the messaging system between processor.
+        DestroyCpuAvpMessagingSystem(hXpcMessage);
+
+        // Free the allocated memory for the xpc message handle.
+        NvOsFree(hXpcMessage);
+    }
+}
+
+
+// Set the outbound mailbox with the given data.  We might have to spin until
+// it's safe to send the message.
+NvError
+NvRmPrivXpcSendMessage(NvRmPrivXpcMessageHandle hXpcMessage, NvU32 data)
+{
+    NvRmPrivXpcHwSendMessageToTarget(&hXpcMessage->HwMailBoxReg, data);
+    return NvSuccess;
+}
+
+
+// Get the value currently in the inbox register.  This read clears the incoming
+// interrupt.
+NvU32
+NvRmPrivXpcGetMessage(NvRmPrivXpcMessageHandle hXpcMessage)
+{
+    NvU32 data;
+    NvRmPrivXpcHwReceiveMessageFromTarget(&hXpcMessage->HwMailBoxReg, &data);
+    return data;
+}
+
+NvError NvRmXpcInitArbSemaSystem(NvRmDeviceHandle hDevice)
+{
+#if NV_IS_AVP
+    return NvSuccess;
+#else
+    return InitArbSemaSystem(hDevice);
+#endif
+}
+
+static irqreturn_t arbgnt_isr(int irq, void *data)
+{
+    ArbSemaIsr(data);
+    return IRQ_HANDLED;
+}
+
+static NvError InitArbSemaSystem(NvRmDeviceHandle hDevice)
+{
+    NvOsInterruptHandler ArbSemaHandler;
+    NvRmPhysAddr ArbSemaBase, ArbGntBase;
+    NvU32        ArbSemaSize, ArbGntSize;
+    NvU32 irq;
+    NvError e;
+    NvU32 i = 0;
+    int ret;
+
+    /* FIXME:  is this the right interrupt? */
+    irq = INT_GNT_0;
+
+    ArbSemaHandler = ArbSemaIsr;
+    set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
+    ret = request_irq(irq, arbgnt_isr, 0, "nvrm_arbgnt", hDevice);
+    if (ret < 0) {
+      printk("%s request_irq failed %d\n", __func__, ret);
+      return NvError_AccessDenied;
+    }
+    s_arbInterruptHandle = irq;
+
+    ArbSemaBase = TEGRA_ARB_SEMA_BASE;
+    ArbSemaSize = TEGRA_ARB_SEMA_SIZE;
+    ArbGntBase = TEGRA_ARBGNT_ICTLR_BASE;
+    ArbGntSize = TEGRA_ARBGNT_ICTLR_SIZE;
+
+    s_ArbSema.pArbSemaVirtAddr = IO_ADDRESS(ArbSemaBase);
+    s_ArbSema.pArbGntVirtAddr = IO_ADDRESS(ArbGntBase);
+
+    //Initialize all the semaphores and mutexes
+    for (i=0;i<MAX_ARB_NUM;i++)
+    {
+        NV_CHECK_ERROR_CLEANUP(
+            NvOsSemaphoreCreate(&s_ArbSema.semaphore[i], 0)
+        );
+
+        NV_CHECK_ERROR_CLEANUP(
+            NvOsMutexCreate(&s_ArbSema.mutex[i])
+        );
+    }
+
+    NV_CHECK_ERROR_CLEANUP(
+        NvOsIntrMutexCreate(&s_ArbSema.hIntrMutex)
+    );
+
+    enable_irq(irq);
+
+fail:
+
+    return e;
+}
+
+
+static void ArbSemaIsr(void *args)
+{
+    NvU32 int_mask, proc_int_enable, arb_gnt, i = 0;
+
+    NvOsIntrMutexLock(s_ArbSema.hIntrMutex);
+    //Check which arb semaphores have been granted to this processor
+    arb_gnt = ARBSEMA_REG_READ(s_ArbSema.pArbSemaVirtAddr, SMP_GNT_ST);
+
+    //Figure out which arb semaphores were signalled and then disable them.
+#if NV_IS_AVP
+    proc_int_enable = ARBGNT_REG_READ(s_ArbSema.pArbGntVirtAddr, COP_ENABLE);
+    int_mask = arb_gnt & proc_int_enable;
+    ARBGNT_REG_WRITE(s_ArbSema.pArbGntVirtAddr, 
+        COP_ENABLE, (proc_int_enable & ~int_mask));
+#else
+    proc_int_enable = ARBGNT_REG_READ(s_ArbSema.pArbGntVirtAddr, CPU_ENABLE);
+    int_mask = arb_gnt & proc_int_enable;
+    ARBGNT_REG_WRITE(s_ArbSema.pArbGntVirtAddr, 
+        CPU_ENABLE, (proc_int_enable & ~int_mask));
+#endif
+        
+    //Signal all the required semaphores
+    do
+    {
+        if (int_mask & 0x1)
+        {
+            NvOsSemaphoreSignal(s_ArbSema.semaphore[i]);
+        }
+        int_mask >>= 1;
+        i++;
+        
+    } while (int_mask);
+
+    NvOsIntrMutexUnlock(s_ArbSema.hIntrMutex);
+}
+
+NvU32 GetArbIdFromRmModuleId(NvRmModuleID modId)
+{
+    NvU32 arbId;
+
+    switch(modId)
+    {
+        case NvRmModuleID_BseA:
+            arbId = NvRmArbSema_Bsea;
+            break;
+        case NvRmModuleID_Vde:
+        default:
+            arbId = NvRmArbSema_Vde;
+            break;
+    }
+    
+    return arbId;
+}
+
+void NvRmXpcModuleAcquire(NvRmModuleID modId)
+{
+    NvU32 RequestedSemaNum;
+    NvU32 reg;
+
+    RequestedSemaNum = GetArbIdFromRmModuleId(modId);
+
+    NvOsMutexLock(s_ArbSema.mutex[RequestedSemaNum]);
+    NvOsIntrMutexLock(s_ArbSema.hIntrMutex);
+
+    //Try to grab the lock
+    ARBSEMA_REG_WRITE(s_ArbSema.pArbSemaVirtAddr, SMP_GET, 1 << RequestedSemaNum);
+
+    //Enable arb sema interrupt
+#if NV_IS_AVP
+    reg = ARBGNT_REG_READ(s_ArbSema.pArbGntVirtAddr, COP_ENABLE);
+    reg |= (1 << RequestedSemaNum);
+    ARBGNT_REG_WRITE(s_ArbSema.pArbGntVirtAddr, COP_ENABLE, reg);
+#else
+    reg = ARBGNT_REG_READ(s_ArbSema.pArbGntVirtAddr, CPU_ENABLE);
+    reg |= (1 << RequestedSemaNum);
+    ARBGNT_REG_WRITE(s_ArbSema.pArbGntVirtAddr, CPU_ENABLE, reg);
+#endif
+
+    NvOsIntrMutexUnlock(s_ArbSema.hIntrMutex);
+    NvOsSemaphoreWait(s_ArbSema.semaphore[RequestedSemaNum]);
+}
+
+void NvRmXpcModuleRelease(NvRmModuleID modId)
+{
+    NvU32 RequestedSemaNum;
+
+    RequestedSemaNum = GetArbIdFromRmModuleId(modId);
+
+    //Release the lock
+    ARBSEMA_REG_WRITE(s_ArbSema.pArbSemaVirtAddr, SMP_PUT, 1 << RequestedSemaNum);
+
+    NvOsMutexUnlock(s_ArbSema.mutex[RequestedSemaNum]);
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_xpc_hw_private.c b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_xpc_hw_private.c
new file mode 100644
index 000000000000..ffd1dc5d6ebd
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_xpc_hw_private.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Cross Processor Communication driver </b>
+ *
+ * @b Description: Implements the cross processor communication Hw Access APIs
+ * 
+ */
+ 
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvrm_drf.h"
+#include "nvrm_hardware_access.h"
+#include "ap15rm_xpc_hw_private.h"
+#include "ap15/arres_sema.h"
+
+enum {MESSAGE_BOX_MESSAGE_LENGTH_BITS = 28};
+#define RESSEMA_REG_READ32(pResSemaHwRegVirtBaseAdd, reg) \
+    NV_READ32((pResSemaHwRegVirtBaseAdd) + (RES_SEMA_##reg##_0)/4)
+
+#define RESSEMA_REG_WRITE32(pResSemaHwRegVirtBaseAdd, reg, val) \
+   do { \
+         NV_WRITE32(((pResSemaHwRegVirtBaseAdd) + ((RES_SEMA_##reg##_0)/4)), (val)); \
+   } while(0)
+
+void NvRmPrivXpcHwResetOutbox(CpuAvpHwMailBoxReg *pHwMailBoxReg)
+{
+    NvU32 OutboxMessage;
+    NvU32 OutboxVal;
+
+    OutboxMessage = 0;
+
+    // Write Outbox in the message box
+    // Enable the Valid tag
+    // Enable interrupt
+#if NV_IS_AVP
+    OutboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_INBOX);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_STAT, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_DATA, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_CMD, 0, OutboxVal);
+    OutboxVal |= OutboxMessage;
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IE_IBE, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, TAG, 0, OutboxVal);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_INBOX, OutboxVal);
+#else        
+    OutboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_OUTBOX);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_CMD, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_STAT, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_DATA, 0, OutboxVal);
+    OutboxVal |= OutboxMessage;
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, IE_OBE, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, TAG, 0, OutboxVal);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_OUTBOX, OutboxVal);
+#endif        
+}
+
+
+/**
+ * Send message to the target.
+ */
+void
+NvRmPrivXpcHwSendMessageToTarget(
+    CpuAvpHwMailBoxReg *pHwMailBoxReg,
+    NvRmPhysAddr MessageAddress)
+{
+    NvU32 OutboxMessage;
+    NvU32 OutboxVal = 0;
+
+    OutboxMessage = ((NvU32)(MessageAddress)) >> (32 - MESSAGE_BOX_MESSAGE_LENGTH_BITS);
+    
+    // Write Outbox in the message box
+    // Enable the Valid tag
+    // Enable interrupt
+#if NV_IS_AVP
+    // !!! not sure why this would need to be read/modify/write
+//    OutboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_INBOX);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_STAT, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_DATA, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_INBOX, IN_BOX_CMD, 0, OutboxVal);
+    OutboxVal |= OutboxMessage;
+    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_INBOX, IE_IBF, FULL, OutboxVal);
+//    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_INBOX, IE_IBE, EMPTY, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_INBOX, TAG, VALID, OutboxVal);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_INBOX, OutboxVal);
+#else        
+    // !!! not sure why this would need to be read/modify/write
+//    OutboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_OUTBOX);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_CMD, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_STAT, 0, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_NUM(RES_SEMA, SHRD_OUTBOX, OUT_BOX_DATA, 0, OutboxVal);
+    OutboxVal |= OutboxMessage;
+    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_OUTBOX, IE_OBF, FULL, OutboxVal);
+//    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_OUTBOX, IE_OBE, EMPTY, OutboxVal);
+    OutboxVal = NV_FLD_SET_DRF_DEF(RES_SEMA, SHRD_OUTBOX, TAG, VALID, OutboxVal);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_OUTBOX, OutboxVal);
+#endif        
+}
+
+
+
+/**
+ * Receive message from the target.
+ */
+void
+NvRmPrivXpcHwReceiveMessageFromTarget(
+    CpuAvpHwMailBoxReg *pHwMailBoxReg,
+    NvRmPhysAddr *pMessageAddress)
+{
+    NvU32 InboxMessage = 0;
+    NvU32 InboxVal;
+
+    // Read the inbox. Lower 28 bit contains the message.
+#if NV_IS_AVP        
+    InboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_OUTBOX);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_OUTBOX, 0);
+#else        
+    InboxVal = RESSEMA_REG_READ32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr,SHRD_INBOX);
+    RESSEMA_REG_WRITE32(pHwMailBoxReg->pHwMailBoxRegBaseVirtAddr, SHRD_INBOX, 0);
+#endif        
+    if (InboxVal & NV_DRF_DEF(RES_SEMA, SHRD_INBOX, TAG, VALID))
+    {
+         pHwMailBoxReg->MailBoxData = InboxVal;
+    }
+
+    InboxVal = (pHwMailBoxReg->MailBoxData) & (0xFFFFFFFFUL >> (32 - MESSAGE_BOX_MESSAGE_LENGTH_BITS));
+    InboxMessage = (InboxVal << (32 - MESSAGE_BOX_MESSAGE_LENGTH_BITS));
+
+    *pMessageAddress = InboxMessage;
+}
+
+
+
+
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_xpc_hw_private.h b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_xpc_hw_private.h
new file mode 100644
index 000000000000..c5822526b9c8
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/ap15/ap15rm_xpc_hw_private.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Priate Hw access function for XPC driver </b>
+ *
+ * @b Description: Defines the private interface functions for the xpc 
+ * 
+ */
+
+#ifndef INCLUDED_RM_XPC_HW_PRIVATE_H
+#define INCLUDED_RM_XPC_HW_PRIVATE_H
+
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+// Combines the cpu avp hw mail baox system information.
+typedef struct CpuAvpHwMailBoxRegRec
+{
+    // Hw mail box register virtual base address.
+    NvU32 *pHwMailBoxRegBaseVirtAddr;
+    
+    // Bank size of the hw regsiter.
+    NvU32 BankSize;
+
+    // Tells whether this is on cpu or on Avp
+    NvBool IsCpu;
+
+    // Mail box data which was read last time.
+    NvU32 MailBoxData;
+} CpuAvpHwMailBoxReg;
+
+void NvRmPrivXpcHwResetOutbox(CpuAvpHwMailBoxReg *pHwMailBoxReg);
+
+/**
+ * Send message to the target.
+ */
+void
+NvRmPrivXpcHwSendMessageToTarget(
+    CpuAvpHwMailBoxReg *pHwMailBoxReg,
+    NvRmPhysAddr MessageAddress);
+
+/**
+ * Receive message from the target.
+ */
+void
+NvRmPrivXpcHwReceiveMessageFromTarget(
+    CpuAvpHwMailBoxReg *pHwMailBoxReg,
+    NvRmPhysAddr *pMessageAddress);
+
+
+#if defined(__cplusplus)
+ }
+#endif
+
+#endif  // INCLUDED_RM_XPC_HW_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/Makefile b/arch/arm/mach-tegra/nv/nvrm/core/common/Makefile
new file mode 100644
index 000000000000..4cec50329619
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/Makefile
@@ -0,0 +1,21 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+ccflags-y += -Iarch/arm/mach-tegra/nv/include
+ccflags-y += -Iarch/arm/mach-tegra/nv/nvrm/core/common
+ccflags-y += -Iarch/arm/mach-tegra/nv/nvrm/core
+
+obj-y += headavp.o
+obj-y += nvrm_avp_cpu_rpc.o
+obj-y += nvrm_moduleloader.o
+obj-y += nvrm_rmctrace.o
+obj-y += nvrm_transport.o
+obj-y += nvrm_module_stub.o
+obj-y += nvrm_power.o
+obj-y += nvrm_init_stub.o
+
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/chiplib_interface.h b/arch/arm/mach-tegra/nv/nvrm/core/common/chiplib_interface.h
new file mode 100644
index 000000000000..9b27133fd7d2
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/chiplib_interface.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2006-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_CHIPLIB_INTERFACE_H
+#define INCLUDED_CHIPLIB_INTERFACE_H
+
+#include "nvcommon.h"
+
+// IIfaceObject and bootstrapping logic
+typedef enum
+{
+    IID_QUERY_IFACE         = 0,
+    IID_CHIP_IFACE          = 1,
+    IID_INTERRUPT_IFACE     = 8,
+    IID_BUSMEM_IFACE        = 16,
+    IID_LAST_IFACE          = 0xFFFF
+} IID_TYPE;
+
+struct IIfaceObjectRec;
+
+typedef struct IIfaceObjectVtableRec
+{
+    void *Unused1;
+    void *Unused2;
+
+    // IIfaceObject interface
+    void (*AddRef)(struct IIfaceObjectRec *pThis);
+    void (*Release)(struct IIfaceObjectRec *pThis);
+    struct IIfaceObjectRec *(*QueryIface)(struct IIfaceObjectRec *pThis,
+        IID_TYPE id);
+} IIfaceObjectVtable;
+
+typedef struct IIfaceObjectRec
+{
+    IIfaceObjectVtable *pVtable;
+} IIfaceObject;
+
+typedef IIfaceObject *(*QueryIfaceFn)(IID_TYPE id);
+#define QUERY_PROC_NAME "QueryIface"
+
+// IChip
+typedef enum
+{
+    ELEVEL_UNKNOWN    = 0,
+    ELEVEL_HW         = 1,
+    ELEVEL_RTL        = 2,
+    ELEVEL_CMODEL     = 3
+} ELEVEL;
+
+struct IChipRec;
+
+typedef struct IChipVtableRec
+{
+    void *Unused1;
+    void *Unused2;
+
+    // IIfaceObject interface
+    void (*AddRef)(struct IChipRec *pThis);
+    void (*Release)(struct IChipRec *pThis);
+    IIfaceObject *(*QueryIface)(struct IChipRec *pThis, IID_TYPE id);
+
+    void *Unused3;
+
+    // IChip interface
+    int (*Startup)(struct IChipRec *pThis, IIfaceObject* system, char** argv,
+        int argc);
+    void (*Shutdown)(struct IChipRec *pThis);
+    int (*AllocSysMem)(struct IChipRec *pThis, int numBytes, NvU32* physAddr);
+    void (*FreeSysMem)(struct IChipRec *pThis, NvU32 physAddr);
+    void (*ClockSimulator)(struct IChipRec *pThis, NvS32 numClocks);
+    void (*Delay)(struct IChipRec *pThis, NvU32 numMicroSeconds);
+    int (*EscapeWrite)(struct IChipRec *pThis, char* path, NvU32 index,
+        NvU32 size, NvU32 value);
+    int (*EscapeRead)(struct IChipRec *pThis, char* path, NvU32 index,
+        NvU32 size, NvU32* value);
+    int (*FindPCIDevice)(struct IChipRec *pThis, NvU16 vendorId,
+        NvU16 deviceId, int index, NvU32* address);
+    int (*FindPCIClassCode)(struct IChipRec *pThis, NvU32 classCode, int index,
+        NvU32* address);
+    int (*GetSimulatorTime)(struct IChipRec *pThis, NvU64* simTime);
+    double (*GetSimulatorTimeUnitsNS)(struct IChipRec *pThis);
+    int (*GetPCIBaseAddress)(struct IChipRec *pThis, NvU32 cfgAddr, int index,
+        NvU32* pAddress, NvU32* pSize);
+    ELEVEL (*GetChipLevel)(struct IChipRec *pThis);
+} IChipVtable;
+
+typedef struct IChipRec
+{
+    IChipVtable *pVtable;
+} IChip;
+
+// IBusMem
+typedef enum
+{
+    BUSMEM_HANDLED      = 0,
+    BUSMEM_NOTHANDLED   = 1,
+} BusMemRet;
+
+struct IBusMemRec;
+
+typedef struct IBusMemVtableRec
+{
+    void *Unused1;
+    void *Unused2;
+
+    // IIfaceObject interface
+    void (*AddRef)(struct IBusMemRec *pThis);
+    void (*Release)(struct IBusMemRec *pThis);
+    IIfaceObject *(*QueryIface)(struct IBusMemRec *pThis, IID_TYPE id);
+
+    void *Unused3;
+
+    // IBusMem interface
+    BusMemRet (*BusMemWrBlk)(struct IBusMemRec *pThis, NvU64 address,
+        const void *appdata, NvU32 count);
+    BusMemRet (*BusMemRdBlk)(struct IBusMemRec *pThis, NvU64 address,
+        void *appdata, NvU32 count);
+    BusMemRet (*BusMemCpBlk)(struct IBusMemRec *pThis, NvU64 dest,
+        NvU64 source, NvU32 count);
+    BusMemRet (*BusMemSetBlk)(struct IBusMemRec *pThis, NvU64 address,
+        NvU32 size, void* data, NvU32 data_size);
+} IBusMemVtable;
+
+typedef struct IBusMemRec
+{
+    IBusMemVtable *pVtable;
+} IBusMem;
+
+struct IInterruptRec;
+
+typedef struct IInterruptVtableRec
+{
+    void *Unused1;
+    void *Unused2;
+
+    // IIfaceObject interface
+    void (*AddRef)(struct IInterruptRec *pThis);
+    void (*Release)(struct IInterruptRec *pThis);
+    IIfaceObject *(*QueryIface)(struct IInterruptRec *pThis, IID_TYPE id);
+
+    void *Unused3;
+
+    // IInterrupt interface
+    void (*HandleInterrupt)( struct IInterruptRec *pThis );
+
+} IInterruptVtable;
+
+typedef struct IInterruptRec
+{
+    IInterruptVtable *pVtable;
+} IInterrupt;
+
+#endif // INCLUDED_CHIPLIB_INTERFACE_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/headavp.S b/arch/arm/mach-tegra/nv/nvrm/core/common/headavp.S
new file mode 100644
index 000000000000..fee956431af8
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/headavp.S
@@ -0,0 +1,66 @@
+/*
+ * arch/arm/mach-tegra/headavp.S
+ *
+ * AVP kernel launcher stub; programs the AVP MMU and jumps to the
+ * kernel code. Must use ONLY ARMv4 instructions, and must be compiled
+ * in ARM mode.
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+  */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include "headavp.h"
+
+#define PTE0_COMPARE	0
+/* the default translation will translate any VA within
+ * 0x0010:0000..0x001f:ffff to the (megabyte-aligned) value written to
+ * _tegra_avp_launcher_stub_data[AVP_LAUNCHER_MMU_PHYSICAL]
+ */
+ #define PTE0_DEFAULT	(0x00100000 | 0x3ff0)
+
+#define PTE0_TRANSLATE	4
+
+ #define TRANSLATE_DATA	(1 << 11)
+ #define TRANSLATE_CODE	(1 << 10)
+ #define TRANSLATE_WR	(1 << 9)
+ #define TRANSLATE_RD	(1 << 8)
+ #define TRANSLATE_HIT	(1 << 7)
+ #define TRANSLATE_EN	(1 << 2)
+
+#define TRANSLATE_OPT (TRANSLATE_DATA | TRANSLATE_CODE | TRANSLATE_WR | \
+		       TRANSLATE_RD | TRANSLATE_HIT)
+
+ENTRY(_tegra_avp_launcher_stub)
+	adr	r4, _tegra_avp_launcher_stub_data
+	ldmia	r4, {r0-r3}
+	str	r2, [r0, #PTE0_COMPARE]
+	bic	r3, r3, #0xff0
+	bic	r3, r3, #0x00f
+	orr	r3, r3, #TRANSLATE_OPT
+	orr	r3, r3, #TRANSLATE_EN
+	str	r3, [r0, #PTE0_TRANSLATE]
+	bx	r1
+	b	.
+ENDPROC(_tegra_avp_launcher_stub)
+	.type	_tegra_avp_launcher_stub_data, %object
+ENTRY(_tegra_avp_launcher_stub_data)
+	.long	AVP_MMU_TLB_BASE
+	.long	0xdeadbeef
+	.long	PTE0_DEFAULT
+	.long	0xdeadd00d
+	.size	_tegra_avp_launcher_stub_data, . - _tegra_avp_launcher_stub_data
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/headavp.h b/arch/arm/mach-tegra/nv/nvrm/core/common/headavp.h
new file mode 100644
index 000000000000..a4121ee4144c
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/headavp.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-tegra/headavp.h
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _MACH_TEGRA_HEADAVP_H
+#define _MACH_TEGRA_HEADAVP_H
+
+#define AVP_MMU_TLB_BASE		0xF000F000
+
+#define AVP_LAUNCHER_START_VA		1
+#define AVP_LAUNCHER_MMU_VIRTUAL	2
+#define AVP_LAUNCHER_MMU_PHYSICAL	3
+
+#define EVP_COP_RESET			0x200
+#define FLOW_CTRL_HALT_COP		0x4
+
+#ifndef __ASSEMBLY__
+extern void _tegra_avp_launcher_stub(void);
+extern u32 _tegra_avp_launcher_stub_data[];
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_avp_cpu_rpc.c b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_avp_cpu_rpc.c
new file mode 100644
index 000000000000..5a373b14b81e
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_avp_cpu_rpc.c
@@ -0,0 +1,357 @@
+/*
+ * arch/arm/mach-tegra/nvrm/core/common/nvrm_avp_cpu_rpc.c
+ *
+ * Transport API
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *          Transport API</b>
+ *
+ * @b Description: This is the wrapper implementation of Transport API.
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+
+#include "nvrm_transport.h"
+#include "nvrm_xpc.h"
+#include "nvrm_rpc.h"
+#include "nvrm_interrupt.h"
+#include "nvassert.h"
+#include "nvrm_graphics_private.h"
+
+/* global variable passed from nvrpc_user.c */
+extern NvRmTransportHandle g_hTransportAvp;
+extern NvRmTransportHandle g_hTransportCpu;
+extern NvOsSemaphoreHandle g_hTransportAvpSem;
+extern NvOsSemaphoreHandle g_hTransportCpuSem;
+extern int g_hTransportAvpIsConnected;
+extern int g_hTransportCpuIsConnected;
+
+/* local variables for handles */
+static NvOsThreadHandle s_RecvThreadId_Service;
+static NvRmRPCHandle gs_hRPCHandle = NULL;
+volatile static int s_ContinueProcessing = 1;
+
+#if !NV_IS_AVP
+#define  PORT_NAME  "RPC_CPU_PORT"
+#else
+#define  PORT_NAME  "RPC_AVP_PORT"
+#endif
+/* Receive message port thread */
+static void ServiceThread( void *args );
+static void ServiceThread( void *args )
+{
+	NvError Error = NvSuccess;
+	static NvU8 ReceiveMessage[MAX_MESSAGE_LENGTH];
+	NvU32 MessageLength = 0;
+
+	Error = NvRmPrivRPCWaitForConnect(gs_hRPCHandle);
+	if (Error)
+	{
+		goto exit_gracefully;
+	}
+	while (s_ContinueProcessing)
+	{
+		Error = NvRmPrivRPCRecvMsg(gs_hRPCHandle, ReceiveMessage,
+					&MessageLength);
+		if (Error == NvError_InvalidState)
+		{
+			break;
+		}
+		if (!Error)
+		{
+			ReceiveMessage[MessageLength] = '\0';
+		}
+		NvRmPrivProcessMessage(gs_hRPCHandle, (char*)ReceiveMessage,
+				MessageLength);
+	}
+
+exit_gracefully:
+        return;
+}
+
+NvError NvRmPrivRPCInit(NvRmDeviceHandle hDeviceHandle, char* portName,
+			NvRmRPCHandle *hRPCHandle )
+{
+	NvError Error = NvSuccess;
+
+	*hRPCHandle = NvOsAlloc(sizeof(NvRmRPC));
+	if (!*hRPCHandle)
+	{
+		Error = NvError_InsufficientMemory;
+		return Error;
+	}
+
+	Error = NvOsMutexCreate(&(*hRPCHandle)->RecvLock);
+	if( Error != NvSuccess)
+	{
+		goto clean_up;
+	}
+
+	if (! portName) {
+		panic("%s: No port name.\n", __func__);
+	}
+	if (! strcmp(portName, "RPC_AVP_PORT")) {
+		if (g_hTransportAvp) panic("%s: g_hTransportAvp is already set.\n", __func__);
+		Error = NvOsSemaphoreCreate(&g_hTransportAvpSem, 0);
+		if (Error != NvSuccess) panic(__func__);
+
+		Error = NvRmTransportOpen(hDeviceHandle, portName, g_hTransportAvpSem,
+					&g_hTransportAvp);
+		if (Error != NvSuccess) panic(__func__);
+
+		(*hRPCHandle)->svcTransportHandle = g_hTransportAvp;
+		(*hRPCHandle)->TransportRecvSemId = g_hTransportAvpSem;
+		(*hRPCHandle)->isConnected = g_hTransportAvpIsConnected;
+	}
+	if (! strcmp(portName, "RPC_CPU_PORT")) {
+		if (g_hTransportCpu) panic("%s: g_hTransportCpu is already set.\n", __func__);
+		Error = NvOsSemaphoreCreate(&g_hTransportCpuSem, 0);
+		if (Error != NvSuccess) panic(__func__);
+
+		Error = NvRmTransportOpen(hDeviceHandle, portName, g_hTransportCpuSem,
+					&g_hTransportCpu);
+		if (Error != NvSuccess) panic(__func__);
+
+		(*hRPCHandle)->svcTransportHandle = g_hTransportCpu;
+		(*hRPCHandle)->TransportRecvSemId = g_hTransportCpuSem;
+		(*hRPCHandle)->isConnected = g_hTransportCpuIsConnected;
+	}
+	(*hRPCHandle)->hRmDevice = hDeviceHandle;
+
+clean_up:
+	return Error;
+}
+
+void NvRmPrivRPCDeInit( NvRmRPCHandle hRPCHandle )
+{
+	if(hRPCHandle != NULL)
+	{
+		if(hRPCHandle->svcTransportHandle != NULL)
+		{
+			NvOsSemaphoreDestroy(hRPCHandle->TransportRecvSemId);
+			NvOsMutexDestroy(hRPCHandle->RecvLock);
+			NvRmTransportClose(hRPCHandle->svcTransportHandle);
+			hRPCHandle->svcTransportHandle = NULL;
+			hRPCHandle->isConnected = NV_FALSE;
+		}
+		NvOsFree(hRPCHandle);
+	}
+}
+
+void NvRmPrivRPCSendMsg(NvRmRPCHandle hRPCHandle,
+			void* pMessageBuffer,
+			NvU32 MessageSize)
+{
+	NvError Error = NvSuccess;
+	NV_ASSERT(hRPCHandle->svcTransportHandle != NULL);
+
+	NvOsMutexLock(hRPCHandle->RecvLock);
+	Error = NvRmTransportSendMsg(hRPCHandle->svcTransportHandle,
+				pMessageBuffer, MessageSize, NV_WAIT_INFINITE);
+	NvOsMutexUnlock(hRPCHandle->RecvLock);
+	if(Error)
+		NV_ASSERT(Error == NvSuccess);
+}
+
+void NvRmPrivRPCSendMsgWithResponse( NvRmRPCHandle hRPCHandle,
+				void* pRecvMessageBuffer,
+				NvU32 MaxSize,
+				NvU32 * pMessageSize,
+				void* pSendMessageBuffer,
+				NvU32 MessageSize)
+{
+	NvError Error = NvSuccess;
+	NV_ASSERT(hRPCHandle->svcTransportHandle != NULL);
+
+	NvOsMutexLock(hRPCHandle->RecvLock);
+	Error = NvRmTransportSendMsg(hRPCHandle->svcTransportHandle,
+				pSendMessageBuffer, MessageSize, NV_WAIT_INFINITE);
+	if (Error)
+	{
+		// TODO: Determine cause of error and pass appropriate error to caller.
+		NvOsDebugPrintf("%s: error in NvRmTransportSendMsg\n", __func__);
+		goto clean_up;
+	}
+	NvOsSemaphoreWait(hRPCHandle->TransportRecvSemId);
+
+	Error = NvRmTransportRecvMsg(hRPCHandle->svcTransportHandle,
+				pRecvMessageBuffer, MaxSize, pMessageSize);
+	if (Error)
+	{
+		NvOsDebugPrintf("%s: error in NvRmTransportRecvMsg\n", __func__);
+		goto clean_up;
+	}
+
+clean_up:
+	NV_ASSERT(Error == NvSuccess);
+	NvOsMutexUnlock(hRPCHandle->RecvLock);
+}
+
+NvError NvRmPrivRPCWaitForConnect( NvRmRPCHandle hRPCHandle )
+{
+	NvError Error = NvSuccess;
+
+	NV_ASSERT(hRPCHandle != NULL);
+	NV_ASSERT(hRPCHandle->svcTransportHandle != NULL);
+
+	if (hRPCHandle->isConnected) panic("%s: line=%d\n", __func__, __LINE__);
+	if(hRPCHandle->isConnected == NV_FALSE)
+	{
+		Error = NvRmTransportSetQueueDepth(hRPCHandle->svcTransportHandle,
+						MAX_QUEUE_DEPTH, MAX_MESSAGE_LENGTH);
+		if (Error)
+		{
+			goto clean_up;
+		}
+		Error = NvError_InvalidState;
+		// Connect to the other end
+		while (s_ContinueProcessing)
+		{
+			Error = NvRmTransportWaitForConnect(
+				hRPCHandle->svcTransportHandle, 100 );
+			if (Error == NvSuccess)
+			{
+				hRPCHandle->isConnected = NV_TRUE;
+				break;
+			}
+			// if there is some other issue than a timeout, then bail out.
+			if (Error != NvError_Timeout)
+			{
+				goto clean_up;
+			}
+		}
+	}
+
+clean_up:
+	return Error;
+}
+
+NvError NvRmPrivRPCConnect( NvRmRPCHandle hRPCHandle )
+{
+	NvError Error = NvSuccess;
+
+	NV_ASSERT(hRPCHandle != NULL);
+	NV_ASSERT(hRPCHandle->svcTransportHandle != NULL);
+
+	/* if (hRPCHandle->isConnected) panic("%s: line=%d\n", __func__, __LINE__); */
+	NvOsMutexLock(hRPCHandle->RecvLock);
+	if(hRPCHandle->isConnected == NV_TRUE)
+	{
+		goto clean_up;
+	}
+	Error = NvRmTransportSetQueueDepth(hRPCHandle->svcTransportHandle,
+					MAX_QUEUE_DEPTH, MAX_MESSAGE_LENGTH);
+	if (Error)
+	{
+		goto clean_up;
+	}
+	Error = NvError_InvalidState;
+
+#define CONNECTION_TIMEOUT (20 * 1000)
+
+	// Connect to the other end with a large timeout
+	// Timeout value has been increased to suit slow enviornments like
+	// emulation FPGAs
+	Error = NvRmTransportConnect(hRPCHandle->svcTransportHandle,
+				CONNECTION_TIMEOUT );
+	if(Error == NvSuccess)
+	{
+		hRPCHandle->isConnected = NV_TRUE;
+	}
+	else
+	{
+		NvOsDebugPrintf("%s: Not connected.\n", __func__);
+	}
+
+#undef CONNECTION_TIMEOUT
+
+clean_up:
+	NvOsMutexUnlock(hRPCHandle->RecvLock);
+	return Error;
+}
+
+NvError NvRmPrivRPCRecvMsg( NvRmRPCHandle hRPCHandle, void* pMessageBuffer,
+			NvU32 * pMessageSize )
+{
+	NvError Error = NvSuccess;
+	NV_ASSERT(hRPCHandle->svcTransportHandle != NULL);
+
+	if (s_ContinueProcessing == 0)
+	{
+		Error = NvError_InvalidState;
+		goto clean_up;
+	}
+
+	NvOsSemaphoreWait(hRPCHandle->TransportRecvSemId);
+	if(s_ContinueProcessing != 0)
+	{
+
+		Error = NvRmTransportRecvMsg(hRPCHandle->svcTransportHandle,
+					pMessageBuffer, MAX_MESSAGE_LENGTH, pMessageSize);
+	}
+	else
+	{
+		Error = NvError_InvalidState;
+	}
+clean_up:
+	return Error;
+}
+
+void NvRmPrivRPCClose( NvRmRPCHandle hRPCHandle )
+{
+	// signal the thread to exit
+	s_ContinueProcessing = 0;
+	if(hRPCHandle && hRPCHandle->svcTransportHandle != NULL)
+	{
+		if (hRPCHandle->TransportRecvSemId)
+			NvOsSemaphoreSignal(hRPCHandle->TransportRecvSemId);
+	}
+}
+
+NvError NvRmPrivInitService(NvRmDeviceHandle hDeviceHandle)
+{
+	NvError Error = NvSuccess;
+
+	Error = NvRmPrivRPCInit(hDeviceHandle, PORT_NAME, &gs_hRPCHandle);
+	if( Error != NvSuccess)
+	{
+		goto exit_gracefully;
+	}
+	NV_ASSERT(gs_hRPCHandle != NULL);
+
+#if !NV_IS_AVP
+	Error = NvOsInterruptPriorityThreadCreate(ServiceThread, NULL,
+						&s_RecvThreadId_Service);
+#else
+	Error = NvOsThreadCreate(ServiceThread, NULL, &s_RecvThreadId_Service);
+#endif
+
+exit_gracefully:
+	return Error;
+}
+
+void NvRmPrivServiceDeInit()
+{
+	NvRmPrivRPCClose(gs_hRPCHandle);
+	NvOsThreadJoin(s_RecvThreadId_Service);
+	NvRmPrivRPCDeInit(gs_hRPCHandle);
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_avp_swi_registry.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_avp_swi_registry.h
new file mode 100644
index 000000000000..712bca98efde
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_avp_swi_registry.h
@@ -0,0 +1,171 @@
+/*
+ * arch/arm/mach-tegra/nvrm/core/common/nvrm_avp_swi_registry.h
+ *
+ *
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef INCLUDED_NVRM_AVP_SWI_REGISTRY_H
+#define INCLUDED_NVRM_AVP_SWI_REGISTRY_H
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_power.h"
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+enum {MAX_CLIENTS = 5};
+enum {MAX_SWI_PER_CLIENT = 32};
+enum {CLIENT_SWI_NUM_START = 0xD0};
+
+typedef NvError (*AvpClientSwiHandler) (int *pRegs);
+
+typedef enum
+{
+    AvpSwiClientType_None = 0,
+    AvpSwiClientType_NvMM,
+    AvpSwiClientType_Force32 = 0x7fffffff
+} AvpSwiClientType;
+
+typedef enum {
+    AvpSwiClientSwiNum_NvMM = 0xD0,
+    AvpSwiClientSwiNum_Force32 = 0x7fffffff
+} AvpSwiClientSwiNum;
+
+typedef struct AvpSwiClientRec
+{
+    AvpClientSwiHandler ClientSwiHandler[MAX_SWI_PER_CLIENT];
+    AvpSwiClientType ClientId;
+    AvpSwiClientSwiNum SwiNum;
+} AvpSwiClient;
+
+typedef struct AvpSwiClientRegistryRec
+{
+    AvpSwiClient SwiClient[MAX_CLIENTS];
+    NvU32 RefCount;
+    NvOsMutexHandle Mutex;
+}AvpSwiClientRegistry;
+
+NvError
+NvRmAvpClientSwiHandlerRegister(
+    AvpSwiClientType ClientId,
+    AvpClientSwiHandler pClinetSwiFunc,
+    NvU32 *pClientIndex);
+
+NvError
+NvRmAvpClientSwiHandlerUnRegister(
+    AvpSwiClientType ClientId,
+    NvU32 ClientIndex);
+
+NvError
+NvRmAvpHandleClientSwi(
+    NvU32 SwiNum,
+    NvU32 ClientIndex,
+    int *pRegs);
+
+typedef struct{
+    NvRmDfsClockId clockId;
+    NvU32 clientId;
+    NvU32 boostDurationMS;
+    NvRmFreqKHz boostKHz;
+}NvRm_PowerBusyHint;
+
+/** NvRmRegisterLibraryCall - Register a library call with the AVP RM
+ *
+ *  @param id The user id to associate with the function
+ *  @param pEntry The function to be registered
+ *  @param pOwnerKey A special unique key to use when unregistering.
+ *
+ *  @returns InsufficientMemory or AlreadyAllocated on failure.
+ */
+NvError
+NvRmRegisterLibraryCall(NvU32 Id, void *pEntry, NvU32 *pOwnerKey);
+
+/** NvRmUnregisterLibraryCall - Unregister a library call
+ *
+ *  @param id The user id associated with the function
+ *  @param pOwnerKey A special unique key. Used to ensure that the correct owner
+ *  unregisters a function.
+ *
+ */
+void
+NvRmUnregisterLibraryCall(NvU32 Id, NvU32 OwnerKey);
+
+/** NvRmGetLibraryCall - Obtain a registered function from the AVP RM
+ *
+ *  @param id The user id associated with the desired library function
+ *
+ *  @returns NULL on failure. The function pointer on success
+ */
+void *NvRmGetLibraryCall(NvU32 Id);
+
+/** NvRmRemoteDebugPrintf - Routes client prints to the CPU.
+ *
+ *  NOTE: This does *not* route kernel prints. ONLY AVP client prints will
+ *  be routed.
+ *  @param string The debug string to print to console
+ *
+ */
+void *NvRmRemoteDebugPrintf(const char *string);
+
+/** NvOsAVPThreadCreate - Creates threads on the AVP with an optional stackPtr argument.
+ *
+ *  AVP clients can use this function to allocate thread stacks wherever they desire (like in
+ *  IRAM, for instance). It is the clients responsibility to allocate this pointer and free it.
+ *  NOTE: The client must free this pointer only after the thread has been joined.
+ *
+ *  @param function The thread entry point
+ *  @param args The thread args
+ *  @param thread The result thread id structure (out param)
+ *  @param stackPtr The optional pointer to a user allocated stack (Can be NULL)
+ *  @param stackSize The size of the associated stackPtr.
+ *
+ */
+NvError NvOsAVPThreadCreate(NvOsThreadFunction function,
+                            void *args,
+                            NvOsThreadHandle *thread,
+                            void *stackPtr,
+                            NvU32 stackSize);
+
+/** NvOsAVPSetIdle - This function is used to force the AVP kernel to save its state
+ *
+ *  When the PMC_SCRATCH22 register has a non-zero value, the AVP has finished saving all its state.
+ *  @param iramSourceAddress The address at which the IRAM aperture begins
+ *  @param iramBufferAddress The address of the buffer into which the AVP will save all IRAM state.
+ *  @param iramSize The size of the iram aperture.
+ *
+ */
+void NvOsAVPSetIdle(NvU32 iramSourceAddress,
+                    NvU32 iramBufferAddress,
+                    NvU32 iramSize);
+
+/** NvRmPowerBusyMultiHint - Provide hints to multiple modules. Saves on messaging overhead.
+ *
+ *  @param multiHint The array of hints
+ *  @param numHints The number of hints
+ */
+void NvRmPowerBusyMultiHint(NvRm_PowerBusyHint *multiHint, NvU32 numHints);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_chipid.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_chipid.h
new file mode 100644
index 000000000000..52742c0a287e
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_chipid.h
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_CHIPID_H
+#define INCLUDED_NVRM_CHIPID_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/* Chip Id */
+typedef enum
+{
+    NvRmChipFamily_Gpu = 0,
+    NvRmChipFamily_Handheld = 1,
+    NvRmChipFamily_BrChips = 2,
+    NvRmChipFamily_Crush = 3,
+    NvRmChipFamily_Mcp = 4,
+    NvRmChipFamily_Ck = 5,
+    NvRmChipFamily_Vaio = 6,
+    NvRmChipFamily_HandheldSoc = 7,
+
+    NvRmChipFamily_Force32 = 0x7FFFFFFF,
+} NvRmChipFamily;
+
+typedef enum
+{
+    NvRmCaps_HasFalconInterruptController = 0,
+    NvRmCaps_Has128bitInterruptSerializer,
+    NvRmCaps_Num,
+    NvRmCaps_Force32 = 0x7FFFFFFF,
+}  NvRmCaps;
+
+typedef struct NvRmChipIdRec
+{
+    NvU16 Id;
+    NvRmChipFamily Family;
+    NvU8 Major;
+    NvU8 Minor;
+    NvU16 SKU;
+
+    /* the following only apply for emulation -- Major will be 0 and
+     * Minor is either 0 for quickturn or 1 for fpga
+     */
+    NvU16 Netlist;
+    NvU16 Patch;
+
+    /* List of features and bug WARs */
+    NvU32 Flags[(NvRmCaps_Num+31)/32];
+} NvRmChipId;
+
+#define NVRM_IS_CAP_SET(h, bit) (((h)->ChipId.Flags)[(bit) >> 5] & (1 << ((bit) & 31)))
+#define NVRM_CAP_SET(h, bit) (((h)->ChipId.Flags)[(bit) >> 5] |= (1U << ((bit) & 31U)))
+#define NVRM_CAP_CLEAR(h, bit) (((h)->ChipId.Flags)[(bit) >> 5] &= ~(1U << ((bit) & 31U)))
+
+/**
+ * Gets the chip id.
+ *
+ * @param hDevice The RM instance
+ */
+NvRmChipId *
+NvRmPrivGetChipId( NvRmDeviceHandle hDevice );
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_CHIPID_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_chiplib.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_chiplib.h
new file mode 100644
index 000000000000..b617e7b41c25
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_chiplib.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_CHIPLIB_H
+#define INLCUDED_NVRM_CHIPLIB_H
+
+#include "nvcommon.h"
+#include "nvrm_hardware_access.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/**
+ * Chiplib interrupt handler function.
+ */
+typedef void (* ChiplibHandleInterrupt)( void );
+
+#if NV_DEF_ENVIRONMENT_SUPPORTS_SIM == 1
+NvBool NvRmIsSimulation(void);
+#else
+#define NvRmIsSimulation() NV_FALSE
+#endif
+
+/**
+ * starts chiplib.
+ *
+ * @param lib The chiplib name
+ * @param cmdline The chiplib command line
+ * @param handle The interrupt handler - will be called by chiplib
+ */
+NvError
+NvRmPrivChiplibStartup( const char *lib, const char *cmdline,
+    ChiplibHandleInterrupt handler );
+
+/**
+ * stops chiplib.
+ */
+void
+NvRmPrivChiplibShutdown( void );
+
+/**
+ * maps a bogus virtual address to a physical address.
+ *
+ * @param addr The physical address to map
+ * @param size The size of the mapping
+ */
+void *
+NvRmPrivChiplibMap( NvRmPhysAddr addr, size_t size );
+
+/**
+ * unmaps a previously mapped pointer from NvRmPrivChiplibMap.
+ *
+ * @param addr The virtual address to unmap
+ */
+void
+NvRmPrivChiplibUnmap( void *addr );
+
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_clockids.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_clockids.h
new file mode 100644
index 000000000000..79364f3f47eb
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_clockids.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file ap15rm_clockids.h
+    Clock List & string names
+*/
+
+/* This is the list of all clock sources available on AP15 and AP20.
+ */
+
+// 32 KHz clock - A.K.A relaxation oscillator.
+NVRM_CLOCK_SOURCE('C', 'l', 'k', 'S', ' ', ' ', ' ', ' ', ClkS)
+// Main clock (crystal or input)
+NVRM_CLOCK_SOURCE('C', 'l', 'k', 'M', ' ', ' ', ' ', ' ', ClkM)
+// Always double the Clock M
+NVRM_CLOCK_SOURCE('C', 'l', 'k', 'D', ' ', ' ', ' ', ' ', ClkD)
+
+// PLL clocks
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'A', '0', ' ', ' ', ' ', PllA0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'A', '1', ' ', ' ', ' ', PllA1)
+
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'C', '0', ' ', ' ', ' ', PllC0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'C', '1', ' ', ' ', ' ', PllC1)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'D', '0', ' ', ' ', ' ', PllD0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'E', '0', ' ', ' ', ' ', PllE0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'M', '0', ' ', ' ', ' ', PllM0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'M', '1', ' ', ' ', ' ', PllM1)
+
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'P', '0', ' ', ' ', ' ', PllP0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'P', '1', ' ', ' ', ' ', PllP1)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'P', '2', ' ', ' ', ' ', PllP2)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'P', '3', ' ', ' ', ' ', PllP3)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'P', '4', ' ', ' ', ' ', PllP4)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'S', '0', ' ', ' ', ' ', PllS0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'U', '0', ' ', ' ', ' ', PllU0)
+NVRM_CLOCK_SOURCE('P', 'l', 'l', 'X', '0', ' ', ' ', ' ', PllX0)
+
+// External and recovered bit clock sources
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'S', 'p', 'd', 'f', ' ', ExtSpdf)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'I', '2', 's', '1', ' ', ExtI2s1)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'I', '2', 's', '2', ' ', ExtI2s2)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'A', 'c', '9', '7', ' ', ExtAc97)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'A', 'u', 'd', 'i', '1', ExtAudio1)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'A', 'u', 'd', 'i', '2', ExtAudio2)
+NVRM_CLOCK_SOURCE('E', 'x', 't', 'V', 'i', ' ', ' ', ' ', ExtVi)
+
+// Audio Clocks
+NVRM_CLOCK_SOURCE('A', 'u', 'd', 'i', 'S', 'y', 'n', 'c', AudioSync)
+NVRM_CLOCK_SOURCE('M', 'p', 'e', 'A', 'u', 'd', 'o', ' ', MpeAudio)
+
+// Internal bus sources
+NVRM_CLOCK_SOURCE('C', 'p', 'u', 'B', 'u', 's', ' ', ' ', CpuBus)
+NVRM_CLOCK_SOURCE('C', 'p', 'u', 'B', 'r', 'd', 'g', ' ', CpuBridge)
+NVRM_CLOCK_SOURCE('S', 'y', 's', 't', 'B', 'u', 's', ' ', SystemBus)
+NVRM_CLOCK_SOURCE('A', 'h', 'B', 'u', 's', ' ', ' ', ' ', Ahb)
+NVRM_CLOCK_SOURCE('A', 'p', 'B', 'u', 's', ' ', ' ', ' ', Apb)
+NVRM_CLOCK_SOURCE('V', 'd', 'e', 'B', 'u', 's', ' ', ' ', Vbus)
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_clocks.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_clocks.h
new file mode 100644
index 000000000000..bef73d86bd9d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_clocks.h
@@ -0,0 +1,1387 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_CLOCKS_H
+#define INCLUDED_NVRM_CLOCKS_H
+
+#include "nvrm_clocks_limits_private.h"
+#include "nvrm_module.h"
+#include "nvrm_diag.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+#define NVRM_RESET_DELAY            (10)
+#define NVRM_CLOCK_CHANGE_DELAY     (2)
+#define NVRM_VARIABLE_DIVIDER       ((NvU32)-1)
+
+// Fixed HDMI frequencies
+#define NVRM_HDMI_480p_FIXED_FREQ_KHZ (27000)
+#define NVRM_HDMI_720p_FIXED_FREQ_KHZ (74250)
+#define NVRM_HDMI_1080p_FIXED_FREQ_KHZ (148500)
+
+#define NvRmIsFixedHdmiKHz(KHz) \
+    (((KHz) == NVRM_HDMI_480p_FIXED_FREQ_KHZ) || \
+     ((KHz) == NVRM_HDMI_720p_FIXED_FREQ_KHZ) || \
+     ((KHz) == NVRM_HDMI_1080p_FIXED_FREQ_KHZ))
+
+// BR-fixed PLLP output frequency in kHz (override disabled) 
+#define NV_BOOT_PLLP_FIXED_FREQ_KHZ (432000)
+
+// RM-fixed PLLP output frequency in kHz (override enabled)
+#define NVRM_PLLP_FIXED_FREQ_KHZ (216000)
+
+// PLLP1-PLLP4 configurations set by RM during initialization and resume
+// from LP0 state. PLLP1 and PLLP3 settings are never changed. PLLP2 and
+// PLLP4 settings are overwritten according to SoC-specific DVFS policy.
+// PLLPx output frequency = NVRM_PLLP_FIXED_FREQ_KHZ / (1 + setting/2)
+#define NVRM_FIXED_PLLP1_SETTING (13)
+#define NVRM_FIXED_PLLP2_SETTING (7)
+#define NVRM_FIXED_PLLP3_SETTING (4)
+#define NVRM_FIXED_PLLP4_SETTING (2)
+
+/// Guaranteed MIPI PLL Stabilization Delay
+#define NVRM_PLL_MIPI_STABLE_DELAY_US (1000)
+
+/**
+ * MIPI PLL feedback divider N threshold for loop filter control setting:
+ * LFCON = 1 if N is above threshold, and LFCON = 0, otherwise
+ */
+#define NVRM_PLL_MIPI_LFCON_SELECT_N_DIVIDER (600)
+
+/**
+ * MIPI PLL feedback divider N thresholds for charge pump control setting
+ * selection.
+ */
+#define NVRM_PLL_MIPI_CPCON_SELECT_STEPS_N_DIVIDER \
+    0,      /* CPCON = 1 if feedback divider  N = 0 (invalid setting)*/ \
+    50,     /* CPCON = 2 if feedback divider  N <= 50 */ \
+    175,    /* CPCON = 3 if feedback divider  N = ( 50 - 175] */ \
+    300,    /* CPCON = 4 if feedback divider  N = (175 - 300] */ \
+    375,    /* CPCON = 5 if feedback divider  N = (300 - 375] */ \
+    450,    /* CPCON = 6 if feedback divider  N = (375 - 450] */ \
+    525,    /* CPCON = 7 if feedback divider  N = (450 - 525] */ \
+    600,    /* CPCON = 8 if feedback divider  N = (525 - 600] */ \
+    700,    /* CPCON = 9 if feedback divider  N = (600 - 700] */ \
+    800,    /* CPCON = 10 if feedback divider N = (700 - 800] */ \
+    900,    /* CPCON = 11 if feedback divider N = (800 - 900] */ \
+    1000    /* CPCON = 12 if feedback divider N = (900 - 1000] */
+            /* CPCON = 13 if feedback divider N > 1000 (invalid setting) */
+
+/// Guaranteed Low power PLL Stabilization Delay
+#define NVRM_PLL_LP_STABLE_DELAY_US (300)
+
+/**
+ * Low power PLL feedback divider N threshold for charge pump control. For N
+ * values below threshold charge pump control is always set to 1. For N values
+ * above threshold charge pump control setting depends on comparison frequency
+ * as specified in the table below.
+ */
+#define NVRM_PLL_LP_MIN_N_FOR_CPCON_SELECTION (200)
+
+/**
+ * Low power PLL comparison frequency Fcomp = Din/M thresholds for charge pump
+ * control setting selection.
+ */
+#define NVRM_PLL_LP_CPCON_SELECT_STEPS_KHZ \
+    6000,   /* CPCON = 1 if Fin/M >= 6000 kHz (outside valid range)*/ \
+    4000,   /* CPCON = 2 if Fin/M = [4000 - 6000) kHz */ \
+    3000,   /* CPCON = 3 if Fin/M = [3000 - 4000) kHz */ \
+    2000,   /* CPCON = 4 if Fin/M = [2000 - 3000) kHz */ \
+    1750,   /* CPCON = 5 if Fin/M = [1750 - 2000) kHz */ \
+    1500,   /* CPCON = 6 if Fin/M = [1500 - 1750) kHz */ \
+    1250,   /* CPCON = 7 if Fin/M = [1250 - 1500) kHz */ \
+    1000    /* CPCON = 8 if Fin/M = [1000 - 1250) kHz */
+            /* CPCON = 9 if Fin/M < 1000 kHz (outside valid range) */
+
+/// Combines PLL and PLL output divider settings for fixed pre-defined frequency
+typedef struct NvRmPllFixedConfigRec
+{
+    // Output pre-defined frequency
+    NvRmFreqKHz OutputKHz;
+
+    // Interanl PLL dividers settings
+    NvU32 M;
+    NvU32 N;
+    NvU32 P;
+
+    // Exteranl output divider settings
+    // (ignored if there is no output divider)
+    NvU32 D;
+} NvRmPllFixedConfig;
+
+/**
+ * Defines list of supported PLLA configurations (2 entries for 12.2896
+ * frequency that can be either truncated or rounded to KHz). The reference
+ * frequency for PLLA is fixed at 28.8MHz, therefore there is no dependency on
+ * oscillator frequency. Output frequency is divided by PLLA_OUT0 fractional
+ * divider.
+ */
+#define NVRM_PLLA_CONFIGURATIONS \
+    { 11289, 25, 49, 0, 8}, \
+    { 11290, 25, 49, 0, 8}, \
+    { 12000, 24, 50, 0, 8}, \
+    { 12288, 25, 64, 0, 10}, \
+    { 56448, 25, 49, 0, 0}, \
+    { 73728, 25, 64, 0, 0}
+
+// Default audio sync frequency
+#define NVRM_AUDIO_SYNC_KHZ (11289)
+
+/**
+ * Defines PLLU configurations for different oscillator frequencies. Output
+ * frequency is 12MHz for USB with no ULPI support, or 60MHz if null ULPI is
+ * supported, or 480MHz for HS PLL. PLLU_OUT0 does not have output divider.
+ * 
+ */
+#define NVRM_PLLU_AT_12MHZ { 12000, 12, 384, 5, 0}
+#define NVRM_PLLU_AT_13MHZ { 12000, 13, 384, 5, 0}
+#define NVRM_PLLU_AT_19MHZ { 12000,  4,  80, 5, 0}
+#define NVRM_PLLU_AT_26MHZ { 12000, 26, 384, 5, 0}
+
+#define NVRM_PLLU_ULPI_AT_12MHZ { 60000, 12, 240, 2, 0}
+#define NVRM_PLLU_ULPI_AT_13MHZ { 60000, 13, 240, 2, 0}
+#define NVRM_PLLU_ULPI_AT_19MHZ { 60000,  4,  50, 2, 0}
+#define NVRM_PLLU_ULPI_AT_26MHZ { 60000, 26, 240, 2, 0}
+
+#define NVRM_PLLU_HS_AT_12MHZ { 480000, 12, 960, 1, 0}
+#define NVRM_PLLU_HS_AT_13MHZ { 480000, 13, 960, 1, 0}
+#define NVRM_PLLU_HS_AT_19MHZ { 480000,  4, 200, 1, 0}
+#define NVRM_PLLU_HS_AT_26MHZ { 480000, 26, 960, 1, 0}
+
+/**
+ * Defines PLLP configurations for different oscillator frequencies. Output
+ * frequency is always the same. PLLP_OUT0 does not have output divider
+ * 
+ */
+#define NVRM_PLLP_AT_12MHZ { NVRM_PLLP_FIXED_FREQ_KHZ, 12, 432, 1, 0}
+#define NVRM_PLLP_AT_13MHZ { NVRM_PLLP_FIXED_FREQ_KHZ, 13, 432, 1, 0}
+#define NVRM_PLLP_AT_19MHZ { NVRM_PLLP_FIXED_FREQ_KHZ,  4,  90, 1, 0}
+#define NVRM_PLLP_AT_26MHZ { NVRM_PLLP_FIXED_FREQ_KHZ, 26, 432, 1, 0}
+
+/**
+ * Defines PLLD/PLLC 720p/1080i HDMI configurations for different oscillator
+ * frequencies. For both PLLC and PLLD output frequency is fixed as 4 * 74250
+ * = 594000. However, PLLC_OUT0 will be running at this frequency exactly, while
+ * PLLD_OUT0 will be runnig at half frequency 297000 (h/w divide by 2 always). 
+ * This difference in source frequency is will be taken care by Display and
+ * HDMI clock dividers.
+ */
+#define NVRM_PLLHD_AT_12MHZ { 594000, 12, 594, 0, 0}
+#define NVRM_PLLHD_AT_13MHZ { 594000, 13, 594, 0, 0}
+#define NVRM_PLLHD_AT_19MHZ { 594000, 16, 495, 0, 0}
+#define NVRM_PLLHD_AT_26MHZ { 594000, 26, 594, 0, 0}
+
+// Display divider is part of the display module and it is not described
+// in central module clock information table. Hence, need this define.
+#define NVRM_DISPLAY_DIVIDER_MAX (128)
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+/*
+ * Defines module clock state
+ */ 
+typedef enum 
+{
+    // Module clock disable
+    ModuleClockState_Disable = 0, 
+
+    // Module clock enable
+    ModuleClockState_Enable = 1, 
+
+    ModuleClockState_Force32 = 0x7FFFFFFF
+} ModuleClockState;
+
+
+typedef enum
+{
+    NvRmClockSource_Invalid = 0,
+#define NVRM_CLOCK_SOURCE(A, B, C, D, E, F, G, H, x) NvRmClockSource_##x,
+#include "nvrm_clockids.h"
+#undef NVRM_CLOCK_SOURCE
+    NvRmClockSource_Num,
+    NvRmClockSource_Force32 = 0x7FFFFFFF
+} NvRmClockSource;
+
+
+typedef enum
+{
+    // Clock source with fixed frequency (e.g., oscillator, not configurable
+    // PLL, external clock, etc.)
+    NvRmClockSourceType_Fixed = 1,
+
+    // Clock source from configurable PLL
+    NvRmClockSourceType_Pll,
+
+    // Secondary clock source derived from oscillator, PLL or other secondary
+    // source via clock divider
+    NvRmClockSourceType_Divider,
+
+    // Core clock source derived from several input sources via 2-stage selector
+    // and rational super-clock divider
+    NvRmClockSourceType_Core,
+
+    // Selector clock source derived from several input sources via 1-stage selector
+    // and optional clock frequency doubler
+    NvRmClockSourceType_Selector,
+
+    NvRmClockSourceType_Num,
+    NvRmClockSourceType_Force32 = 0x7FFFFFFF
+} NvRmClockSourceType;
+
+typedef enum
+{
+    // No divider
+    NvRmClockDivider_None = 1,
+
+    // Integer divider by N
+    NvRmClockDivider_Integer,
+
+    // Integer divider by (N + 1)
+    NvRmClockDivider_Integer_1,
+
+    // Fractional divider by (N/2 + 1)
+    NvRmClockDivider_Fractional_2,
+
+    // Skipping N clocks out of every 16, i.e fout = fin * (16-N)/16
+    // (= to Keeper16 with 1-complemented settings N = 15 - M)
+    NvRmClockDivider_Skipper16,
+
+    // Keep M+1 clocks out of every 16, fout = fin * (M+1)/16
+    // (= to Skipper16 with 1-complemented setting M = 15 - N)
+    NvRmClockDivider_Keeper16,
+
+    // Integer divider by (N + 2) = cascade Fractional : Fixed 1/2
+    NvRmClockDivider_Integer_2,
+
+    NvRmClockDivider_Num,
+    NvRmClockDivider_Force32 = 0x7FFFFFFF
+} NvRmClockDivider;
+
+typedef enum
+{
+    // AP10 PLLs (PLLC and PLLA)
+    NvRmPllType_AP10 = 1,
+
+    // MIPI PLLs (PLLD and PLLU on AP15)
+    NvRmPllType_MIPI,
+
+    // Low Power PLLs (PLLA, PLLC, PLLM, PLLP, PLLX, PLLS) 
+    NvRmPllType_LP,
+
+    // AP20 USB HS PLL (PLLU on AP20) 
+    NvRmPllType_UHS,
+
+    NvRmPllType_Num,
+    NvRmPllType_Force32 = 0x7FFFFFFF
+} NvRmPllType;
+
+/**
+ * Defines PLL configuration flags which are applicable for some PLLs.
+ * Multiple flags can be OR'ed and passed to the NvRmPrivAp15PllSet() API.
+ */
+typedef enum
+{
+    /// Use Slow Mode output for MIPI PLL
+    NvRmPllConfigFlags_SlowMode = 0x1,
+
+    /// Use Fast Mode output for MIPI PLL
+    NvRmPllConfigFlags_FastMode = 0x2,
+
+    /// Enable differential outputs for MIPI PLL
+    NvRmPllConfigFlags_DiffClkEnable = 0x4,
+
+    /// Disable differential outputs for MIPI PLL
+    NvRmPllConfigFlags_DiffClkDisable = 0x8,
+
+    /// Override fixed configuration for PLLP
+    NvRmPllConfigFlags_Override = 0x10,
+
+    /// Enable duty cycle correction for LP PLL
+    NvRmPllConfigFlags_DccEnable = 0x20,
+
+    /// Disable duty cycle correction for LP PLL
+    NvRmPllConfigFlags_DccDisable = 0x40,
+
+    NvRmPllConfigFlags_Num,
+    NvRmPllConfigFlags_Force32 = 0x7FFFFFFF
+} NvRmPllConfigFlags;
+
+/*****************************************************************************/
+
+// Holds source selection and divider configuration for module clock as well
+// as module reset information.
+typedef struct NvRmModuleClockInfoRec
+{
+    NvRmModuleID Module;
+    NvU32 Instance;
+    NvU32 SubClockId;
+
+    NvRmClockSource Sources[NvRmClockSource_Num];
+    NvRmClockDivider Divider;
+
+    NvU32 ClkSourceOffset;
+
+    NvU32 SourceFieldMask;
+    NvU32 SourceFieldShift;
+
+    NvU32 DivisorFieldMask;
+    NvU32 DivisorFieldShift;
+
+    NvU32 ClkEnableOffset;
+    NvU32 ClkEnableField;
+    NvU32 ClkResetOffset;
+    NvU32 ClkResetField;
+
+    NvRmDiagModuleID DiagModuleID;
+}NvRmModuleClockInfo;
+
+typedef struct NvRmModuleClockStateRec
+{
+    NvU32 Divider;
+    NvU32 SourceClock;
+    NvRmFreqKHz actual_freq;
+    NvU32 refCount;
+    NvU32 Vstep;
+    NvBool Vscale;
+    NvBool FirstReference;
+#if NVRM_DIAG_LOCK_SUPPORTED
+    NvBool DiagLock;    // once locked, can not be changed
+#endif
+} NvRmModuleClockState;
+
+/*****************************************************************************/
+
+// Holds configuration information about the fixed clock source that can be
+// only enabled/disabled (e.g, oscillator, external clock, fixed frequency PLL).
+typedef struct NvRmFixedClockInfoRec
+{
+    // Source ID
+    NvRmClockSource SourceId;
+
+    // Fixed source input (must be fixed source as well). For primary sources
+    // this field is set to NvRmClockSource_Invalid
+    NvRmClockSource InputId;
+
+    // Enable register offset and field
+    NvU32 ClkEnableOffset;
+    NvU32 ClkEnableField;
+} NvRmFixedClockInfo;
+
+
+// Holds configuration information about configurable PLL 
+typedef struct NvRmPllClockInfoRec
+{
+    // PLL output ID
+    NvRmClockSource SourceId;
+
+    // PLL reference clock ID
+    NvRmClockSource InputId;
+
+    // PLL type
+    NvRmPllType PllType;
+
+    // Ofsets of PLL registers
+    NvU32 PllBaseOffset;
+    NvU32 PllMiscOffset;
+
+    // PLL VCO range
+    NvRmFreqKHz PllVcoMin;
+    NvRmFreqKHz PllVcoMax;
+} NvRmPllClockInfo;
+
+
+// Holds configuration information about secondary clock source derived
+// from one input source via clock divider
+typedef struct NvRmDividerClockInfoRec
+{
+    // Divider output clock ID
+    NvRmClockSource SourceId;
+
+    // Divider input clock ID
+    NvRmClockSource InputId;
+
+    // Type of the divider
+    NvRmClockDivider Divider;
+
+    // Divider control register offset
+    NvU32 ClkControlOffset;
+
+    // Clock rate parameter field;
+    // ignored for divider with fixed setting
+    NvU32 ClkRateFieldMask;
+    NvU32 ClkRateFieldShift;
+
+    // Divider control field
+    NvU32 ClkControlField;
+    NvU32 ClkEnableSettings;
+    NvU32 ClkDisableSettings;
+
+    // Fixed divider rate parameter setting;
+    // NVRM_VARIABLE_DIVIDER if divider is variable
+    NvU32 FixedRateSetting;
+} NvRmDividerClockInfo;
+
+
+typedef enum
+{
+    // The enumeartion values must not be changed for Mode(ModeField) formula
+    // below to work properly 
+    NvRmCoreClockMode_Suspend = 0,
+    NvRmCoreClockMode_Idle = 1,
+    NvRmCoreClockMode_Run = 2,
+    NvRmCoreClockMode_Irq = 3,
+    NvRmCoreClockMode_Fiq = 4,
+
+    NvRmCoreClockMode_Num,
+    NvRmCoreClockMode_Force32 = 0x7FFFFFFF
+} NvRmCoreClockMode;
+
+// Holds configuration information about core clock source derived from several
+// input sources via 2-stage selector and rational super-clock divider  
+typedef struct NvRmCoreClockInfoRec
+{
+    // Core clock ID
+    NvRmClockSource SourceId;
+
+    // Super clock input sources, same in each mode
+    NvRmClockSource Sources[NvRmClockSource_Num];
+
+    // Offset of the core clock input source selector register
+    NvU32 SelectorOffset;
+
+    // Clock mode field: 
+    // 0 => NvRmCoreClockMode_Suspend (0)
+    // 1 => NvRmCoreClockMode_Idle (1)
+    // 2-3 => NvRmCoreClockMode_Run (2)
+    // 4-7 => NvRmCoreClockMode_Irq (3)
+    // 8-15 => NvRmCoreClockMode_Fiq (4)
+    // Mode = (ModeField == 0) ? NvRmCoreClockMode_Suspend : (1 + LOG2(ModeField))
+    NvU32 ModeFieldMask;
+    NvU32 ModeFieldShift;
+
+    // Sorce selection fileds for each mode
+    NvU32 SourceFieldMasks[NvRmCoreClockMode_Num];
+    NvU32 SourceFieldShifts[NvRmCoreClockMode_Num];
+
+    // Offset of the divider register
+    NvU32 DividerOffset;
+
+    // Divider enable field (divider is by-passed if disabled)
+    // Fout = Fin * (Dividend + 1) / (Divisor + 1)
+    NvU32 DividerEnableFiledMask;
+    NvU32 DividerEnableFiledShift;
+
+    // Dividend field
+    NvU32 DividendFieldMask;
+    NvU32 DividendFieldShift;
+    NvU32 DividendFieldSize;
+
+    // Divisor field
+    NvU32 DivisorFieldMask;
+    NvU32 DivisorFieldShift;
+    NvU32 DivisorFieldSize;
+} NvRmCoreClockInfo;
+
+// Holds configuration information about secondary clock source derived from
+// several input sources via 1-stage selector and clock frequency doubler 
+typedef struct NvRmSelectorClockInfoRec
+{
+    // Selector output clock ID
+    NvRmClockSource SourceId;
+
+    // Selector input sources
+    NvRmClockSource Sources[NvRmClockSource_Num];
+
+    // Offset of the input source selector register
+    NvU32 SelectorOffset;
+
+    // Source selection field
+    NvU32 SourceFieldMask;
+    NvU32 SourceFieldShift;
+
+    // Doubler control (optional - set field to 0, if no doubler)
+    NvU32 DoublerEnableOffset;
+    NvU32 DoublerEnableField;
+} NvRmSelectorClockInfo;
+
+// Holds information on system bus clock dividers
+typedef struct NvRmSystemBusComplexInfoRec
+{
+    // Offset of the Bus Rates control register
+    NvU32 BusRateOffset;
+
+    // Combined bus clocks disable fields (1 = disable)
+    NvU32 BusClockDisableFields;
+
+    // V-pipe vclk divider field: vclk rate = system core rate * (n+1) /16
+    // All fields are 0, if VDE (V-pipe) clock is decoupled from the System bus
+    NvU32 VclkDividendFieldMask;
+    NvU32 VclkDividendFieldShift;
+    NvU32 VclkDividendFieldSize;
+
+    // AHB hclk divider field: hclk rate = system core rate / (n+1)
+    NvU32 HclkDivisorFieldMask;
+    NvU32 HclkDivisorFieldShift;
+    NvU32 HclkDivisorFieldSize;
+
+    // APB pclk divider field: pclk rate = hclk rate / (n+1)
+    NvU32 PclkDivisorFieldMask;
+    NvU32 PclkDivisorFieldShift;
+    NvU32 PclkDivisorFieldSize;
+} NvRmSystemBusComplexInfo;
+
+/*****************************************************************************/
+
+typedef union
+{
+    NvRmFixedClockInfo* pFixed;
+    NvRmPllClockInfo* pPll;
+    NvRmDividerClockInfo* pDivider;
+    NvRmCoreClockInfo* pCore;
+    NvRmSelectorClockInfo* pSelector;
+} NvRmClockSourceInfoPtr;
+
+// Abstarcts clock source information for different source types.
+typedef struct NvRmClockSourceInfoRec
+{
+    // Clock source ID
+    NvRmClockSource SourceId;
+
+    // Clock source type
+    NvRmClockSourceType SourceType;
+
+    // Pointer to clock source information
+    NvRmClockSourceInfoPtr pInfo;
+} NvRmClockSourceInfo;
+
+/*****************************************************************************/
+
+// Holds PLL references
+typedef struct NvRmPllReferenceRec
+{
+    // PLL ID
+    NvRmClockSource SourceId;
+
+    // Stop PLL during low power state flag (reported by DFS to kernel)
+    NvRmDfsStatusFlags StopFlag;
+
+    // Reference counter
+    NvU32 ReferenceCnt;
+
+    // Module clocks reference array
+    NvBool* AttachedModules; 
+
+    // External clock attachment reference count (debugging only)
+    NvU32 ExternalClockRefCnt;
+} NvRmPllReference;
+
+/**
+ * Holds DFS clock source configuration record
+ */
+typedef struct NvRmDfsSourceRec
+{
+    // DFS Clock Source Id
+    NvRmClockSource SourceId;
+
+    // DFS Clock Source frequency
+    // CPU and System/AVP clock domains: this field holds input frequency
+    // of core super-divider (from base PLL output or secondary PLL divider) 
+    // V-pipe domain (if it is decoupled from System bus): this field holds
+    // output frequency of VDE module divider = VDE domain frequency
+    // EMC domain: this field holds EMC2x frequency specified in selected
+    // entry in EMC configuration table
+    NvRmFreqKHz SourceKHz;
+
+    // DFS Clock Source divider setting
+    // CPU and System/AVP clock domains: this field holds settings for
+    // secondary PLL divider between base PLL output and super-divider
+    // V-pipe domain (if it is decoupled from System bus): this field holds
+    // settings for VDE module clock divider
+    // EMC domain: this field holds index into EMC configuration table
+    NvU32 DividerSetting;
+
+    // Minimum Voltage required to run DFS domain from this source 
+    NvRmMilliVolts MinMv;
+} NvRmDfsSource;
+
+/**
+ * Combines frequencies for DFS controlled clock domains
+ */
+typedef struct NvRmDfsFrequenciesRec
+{
+    NvRmFreqKHz Domains[NvRmDfsClockId_Num];
+} NvRmDfsFrequencies;
+
+/*****************************************************************************/
+
+/*
+ * Defines execution platforms
+ */
+typedef enum
+{
+    // SoC Chip
+    ExecPlatform_Soc = 0x1,
+
+    // FPGA
+    ExecPlatform_Fpga,
+
+    // QuickTurn
+    ExecPlatform_Qt,
+
+    // Simulation
+    ExecPlatform_Sim,
+
+    ExecPlatform_Force32 = 0x7FFFFFFF
+} ExecPlatform;
+
+/*****************************************************************************/
+/*****************************************************************************/
+
+/**
+ * Determines execution platform.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * 
+ * @return Execution platform ID.
+ */
+ExecPlatform NvRmPrivGetExecPlatform(NvRmDeviceHandle hRmDeviceHandle);
+
+/**
+ * Initializes clock sources frequencies.
+ * 
+ * @param hRmDevice The RM device handle. 
+ * @param pClockSourceFreq A pointer to the source frequencies table to be
+ *  filled in by this function.
+ */
+void
+NvRmPrivClockSourceFreqInit(
+    NvRmDeviceHandle hRmDevice,
+    NvU32* pClockSourceFreq);
+
+/**
+ * Initializes bus clocks.
+ * 
+ * @param hRmDevice The RM device handle. 
+ * @param SystemFreq The system bus frequency
+ */
+void
+NvRmPrivBusClockInit(NvRmDeviceHandle hRmDevice, NvRmFreqKHz SystemFreq);
+
+/**
+ * Initializes PLL power rails and synchronizes PMU ref count
+ * 
+ * @param hRmDevice The RM device handle.
+ */
+void
+NvRmPrivPllRailsInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Set nominal core and DDR I/O voltages and boosts core and memory
+ * clocks to maximum.
+ * 
+ * @param hRmDevice The RM device handle.
+ */
+void
+NvRmPrivBoostClocks(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Enables/disables module clock (private utility directly accessing h/w,
+ * no ref counting).
+ * 
+ * @param hDevice The RM device handle.
+ * @param ModuleId Combined module ID and instance of the target module.
+ * @param ClockState Target clock state.
+ */
+void
+NvRmPrivEnableModuleClock(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID ModuleId,
+    ModuleClockState ClockState);
+
+/**
+ * Gets currently selected clock source for the specified core clock.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the core clock description structure.
+ * 
+ * @return Core clock source ID.
+ */
+NvRmClockSource
+NvRmPrivCoreClockSourceGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo);
+
+/**
+ * Gets core clock frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the core clock description structure.
+ * 
+ * @return Core clock frequency in kHz.
+ */
+NvRmFreqKHz
+NvRmPrivCoreClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo);
+
+/**
+ * Finds the slection index of the specified core clock source.
+ * 
+ * @param pCinfo Pointer to the core clock description structure.
+ * @param SourceId Id of the clock source to find index of 
+ * @param pSourceIndex Output storage pointer for the clock source index;
+ *  returns NvRmClockSource_Num if specified source Id can not be found
+ *  in the core clock descriptor.
+ */
+void
+NvRmPrivCoreClockSourceIndexFind(
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmClockSource SourceId,
+    NvU32* pSourceIndex);
+
+/**
+ * Finds the best source for the target core clock frequency.
+ * The best source is a valid source with frequency above and closest
+ * to the target; if such source does not exist, the best source is a
+ * valid source below and closest to the target. If no valid source
+ * exists (i.e., all available find source are above maximum domain
+ * frequency)
+ * 
+ * @param pCinfo Pointer to the core clock description structure.
+ * @param MaxFreq Upper limit for source frequency in kHz
+ * @param Target frequency in kHz
+ * @param pSourceFreq Output storage pointer for the best source frequency;
+ *  returns 0 if no valid source below upper limit was found
+ * @param pSourceIndex Output storage pointer for the best source index in
+ *  core clock descriptor; returns NvRmClockSource_Num if no valid source
+ *  was found
+ */
+void
+NvRmPrivCoreClockBestSourceFind(
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmFreqKHz MaxFreq,
+    NvRmFreqKHz TargetFreq,
+    NvRmFreqKHz* pSourceFreq,
+    NvU32* pSourceIndex);
+
+/**
+ * Sets "as is" specified core clock configuration.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the core clock description structure.
+ * @param SourceId The ID of the clock source to drive core clock.
+ * @param m Superdivider dividend value.
+ * @param n Superdivider divisor value.
+ * 
+ * There is no error return status for this API call.
+ * If specified source can not be selected(not present 
+ * in core clock descriptor), asserts are encountered.
+ */
+void
+NvRmPrivCoreClockSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmClockSource SourceId,
+    NvU32 m,
+    NvU32 n);
+
+/**
+ * Configures core clock frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the core clock description structure.
+ * @param MaxFreq Upper limit for clock source frequency in kHz.
+ * @param pFreq Pointer to the target frequency in kHz on entry; updated
+ *  with actual clock frequencies on exit.
+ * @param pSourceId Pointer to the target clock source ID on entry; if set
+ *  to NvRmClockSource_Num, no source target is specified, and the best source
+ *  for the target frequency is selected automatically. On exit, points to the
+ *  actually selected source ID.
+ * 
+ * @retval NvSuccess if core clock was configured successfully.
+ * @retval NvError_NotSupported if the specified target source is invalid or
+ *  no target source specified and no valid source was found. 
+ */
+NvError
+NvRmPrivCoreClockConfigure(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmCoreClockInfo* pCinfo,
+    NvRmFreqKHz MaxFreq,
+    NvRmFreqKHz* pFreq,
+    NvRmClockSource* pSourceId);
+
+/**
+ * Gets bus clocks frequencies.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param SystemFreq System core clock frequency in kHz.
+ * @param pVclkFreq Output storage pointer for V-bus clock frequency in kHz.
+ *  If VDE clock is decoupled from the System bus, 0kHz will be returned.
+ * @param pHclkFreq Output storage pointer for AHB clock frequency in kHz.
+ * @param pPclkFreq Output storage pointer for APB clock frequency in kHz.
+ */
+void
+NvRmPrivBusClockFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz SystemFreq,
+    NvRmFreqKHz* pVclkFreq,
+    NvRmFreqKHz* pHclkFreq,
+    NvRmFreqKHz* pPclkFreq);
+
+/**
+ * Configures bus clocks frequencies.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param SystemFreq System core clock frequency in kHz.
+ * @param pVclkFreq Pointer to the target V-bus clock frequency in kHz
+ *  on entry, updated with actually set frequency on exit. If VDE clock
+ *  is decoupled from the System bus, 0kHz will be returned.
+ * @param pHclkFreq Pointer to the target AHB clock frequency in kHz
+ *  on entry, updated with actually set frequency on exit.
+ * @param pPclkFreq Pointer to the target APB clock frequency in kHz
+ *  on entry, updated with actually set frequency on exit.
+ * @param PclkMaxFreq APB clock maximum frequency; APB is the only clock
+ *  in the system complex that may have different (lower) maximum limit. 
+ */
+void
+NvRmPrivBusClockFreqSet(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz SystemFreq,
+    NvRmFreqKHz* pVclkFreq,
+    NvRmFreqKHz* pHclkFreq,
+    NvRmFreqKHz* pPclkFreq,
+    NvRmFreqKHz PclkMaxFreq);
+
+/**
+ * Reconfigures PLLX0 to specified frequency (and switches CPU to back-up
+ * PLLP0 if PLLX0 is currently used as CPU source).
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param TargetFreq New PLLX0 output frequency.
+ */
+void
+NvRmPrivReConfigurePllX(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz TargetFreq);
+
+/**
+ * Reconfigures PLLC0 to specified frequency (switches to PLLP0 all modules
+ * that use PLLC0 as a source, and then restores source configuration back).
+ * Should be called only when core voltage is set at nominal.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param TargetFreq New PLLC0 output frequency.
+ */
+void
+NvRmPrivReConfigurePllC(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz TargetFreq);
+
+/**
+ * Gets maximum PLLC0 frequency set as a default target, when there are no
+ * fixed frequency requirements.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return Maximum target for PLLC0 frequency.
+ */
+NvRmFreqKHz NvRmPrivGetMaxFreqPllC(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Configures PLLC0 at maximum frequency, when there are no fixed frequency
+ * requirements. Should be called only when core voltage is set at nominal.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return Maximum target for PLLC0 frequency.
+ */
+void NvRmPrivBoostPllC(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Updates PLL frequency entry in the clock source table.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the PLL description structure.
+ */
+void
+NvRmPrivPllFreqUpdate(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmPllClockInfo* pCinfo);
+
+/**
+ * Updates divider frequency entry in the clock source table.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the divider clock description structure.
+ */
+void
+NvRmPrivDividerFreqUpdate(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDividerClockInfo* pCinfo);
+
+/**
+ * Sets "as is" specified divider parmeter.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the divider clock description structure.
+ * @param setting Divider setting
+ */
+void
+NvRmPrivDividerSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDividerClockInfo* pCinfo,
+    NvU32 setting);
+
+/**
+ * Gets divider output frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the divider clock description structure.
+ * 
+ * @return Divider output frequency in kHz; zero if divider itself or
+ *  divider's input clock is disabled.
+ */
+NvRmFreqKHz
+NvRmPrivDividerFreqGet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmDividerClockInfo* pCinfo);
+
+/**
+ * Finds minimum divider output frequency, which is above the specified
+ *  target frequency.
+ * 
+ * @param DividerType Divider type (only fractional dividers for now).
+ * @param pCinfo SourceKHz Divider source (input) frequency in kHz.
+ * @param MaxKHz Output divider frequency upper limit. Target frequency must
+ *  be below this limit. If no frequency above the target but within the limit
+ *  can be found, then maximum frequency within the limit is returned.
+ * @param pTargetKHz A pointer to the divider output frequency. On entry
+ *  specifies target; on exit - found frequency.  
+ * 
+ * @return Divider setting to get found frequency from the given source.
+ */
+NvU32
+NvRmPrivFindFreqMinAbove(
+    NvRmClockDivider DividerType,
+    NvRmFreqKHz SourceKHz,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pTargetKHz);
+
+/**
+ * Finds maximum divider output frequency, which is below the specified
+ *  target frequency.
+ * 
+ * @param DividerType Divider type (only fractional dividers for now).
+ * @param pCinfo SourceKHz Divider source (input) frequency in kHz.
+ * @param MaxKHz Output divider frequency upper limit. Target frequency must
+ *  be below this limit.
+ * @param pTargetKHz A pointer to the divider output frequency. On entry
+ *  specifies target; on exit - found frequency.  
+ * 
+ * @return Divider setting to get found frequency from the given source.
+ */
+NvU32
+NvRmPrivFindFreqMaxBelow(
+    NvRmClockDivider DividerType,
+    NvRmFreqKHz SourceKHz,
+    NvRmFreqKHz MaxKHz,
+    NvRmFreqKHz* pTargetKHz);
+
+/**
+ * Sets "as is" specified slector clock configuration.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the selector clock description structure.
+ * @param SourceId The ID of the input clock source to select.
+ * @param Double If true, enable output doubler. If false, disable
+ *  output doubler.
+ * 
+ * There is no error return status for this API call.
+ * If specified source can not be selected(not present 
+ * in core clock descriptor), asserts are encountered.
+ */
+void
+NvRmPrivSelectorClockSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmSelectorClockInfo* pCinfo,
+    NvRmClockSource SourceId,
+    NvBool Double);
+
+/**
+ * Parses clock sources configuration table of the given type.
+ * 
+ * @param pDst The pointer to the list of the clock source records the results
+ *  of parsing are to be stored in. The records in this list are arranged in
+ *  the order of source IDs.
+ * @param DestinationTableSize Maximum number of sources that can be recorded.
+ * @param The clock source configuration table to be parsed.
+ * @param SourceTableSize Number of records to be parsed.
+ * @param SourceType The type of source records to be parsed.
+ */
+void
+NvRmPrivParseClockSources(
+    NvRmClockSourceInfo* pDst,
+    NvU32 DestinationTableSize,
+    NvRmClockSourceInfoPtr Src,
+    NvU32 SourceTableSize,
+    NvRmClockSourceType SourceType);
+
+/**
+ * Gets pointer to the given clock source descriptor.
+ * 
+ * @param id The targeted clock source ID.
+ * 
+ * @return A pointer to the specified clock source descriptor.
+ *  NULL is returned, if the target clock source is not valid.
+ */
+NvRmClockSourceInfo* NvRmPrivGetClockSourceHandle(NvRmClockSource id);
+
+/**
+ * Gets given clock source frequency,
+ * 
+ * @param id The targeted clock source ID.
+ * 
+ * @return Clock source frequency in KHz.
+ */
+NvRmFreqKHz NvRmPrivGetClockSourceFreq(NvRmClockSource id);
+
+/**
+ * Verifies if the specified clock source is currently selected
+ * by the specified module.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param SourceId The clock source ID to be verified. 
+ * @param ModuleId The combined module id and instance of the module in question.
+ * 
+ * @return True if specified clock source is selected by the module;
+ *  False returned, otherwise.
+ */
+NvBool
+NvRmPrivIsSourceSelectedByModule(
+    NvRmDeviceHandle hRmDevice,
+    NvRmClockSource SourceId,
+    NvRmModuleID ModuleId);
+
+/**
+ * Verifies if specified frequency range is reachable from the given
+ *  clock source. 
+ * 
+ * @param SourceFreq Clock source frequency in KHz.
+ * @param MinFreq Frequency range low boundary in KHz. 
+ * @param MaxFreq Frequency range high boundary in KHz.
+ * @param MaxDivisor Maximum possible source clock divisor.
+ * 
+ * @return True, if whole divisor can be found so that divided source
+ *  frequency is within the range boundaries; False, otherwise.
+ */
+NvBool
+NvRmIsFreqRangeReachable(
+    NvRmFreqKHz SourceFreq,
+    NvRmFreqKHz MinFreq,
+    NvRmFreqKHz MaxFreq,
+    NvU32 MaxDivisor);
+
+/**
+ * Reports if clock/voltage diagnostic is in progress for the specified module.
+ * 
+ * @param ModuleId The combined module id and instance of the module in question.
+ *  If set to NvRmModuleID_Invalid reports if diagnostic is in progress for any
+ *  module.
+ * 
+ * @return True, if clock/voltage diagnostic is in progress; False, otherwise.
+ */
+NvBool NvRmPrivIsDiagMode(NvRmModuleID ModuleId);
+
+/**
+ * Gets clock frequency limits for the specified SoC module.
+ * 
+ * @param ModuleId The targeted module ID.
+ * 
+ * @return The pointer to the clock limts structure for the given module ID.
+ */
+const NvRmModuleClockLimits* NvRmPrivGetSocClockLimits(NvRmModuleID Module);
+
+/** 
+ * Locks/Unclocks acces to shared PLL
+ */
+void NvRmPrivLockSharedPll(void);
+void NvRmPrivUnlockSharedPll(void);
+
+/**
+ * Locks/Unclocks acces to module clock state
+ */
+void NvRmPrivLockModuleClockState(void);
+void NvRmPrivUnlockModuleClockState(void);
+
+/** 
+ * Enable/Disable the clock source for the module. 
+ *
+ * @param hRmDevice The RM device handle.
+ * @param ModuleId Module ID and instace information.
+ * @param enbale Should the clock source be enabled or disabled.
+ */
+void
+NvRmPrivConfigureClockSource(
+        NvRmDeviceHandle hRmDevice, 
+        NvRmModuleID ModuleId, 
+        NvBool enable);
+
+/** 
+ * Gets pointers to clock descriptor and clock state for the given module.
+ *
+ * @param hDevice The RM device handle.
+ * @param ModuleId Module ID and instance information.
+ * @param CinfoOut A pointer to a variable that this function sets to the
+ *  clock descriptor pointer.
+ * @param StateOut A pointer to a variable that this function sets to the
+ *  clock state pointer.
+ * 
+ * @retval NvSuccess if busy request completed successfully.
+ * @retval NvError_NotSupported if no clock descriptor for the given module.
+ * @retval NvError_ModuleNotPresent if the given module is not listed in
+ *  relocation table.
+ */
+NvError
+NvRmPrivGetClockState(
+    NvRmDeviceHandle hDevice,
+    NvRmModuleID ModuleId,
+    NvRmModuleClockInfo** CinfoOut,
+    NvRmModuleClockState** StateOut);
+
+/**
+ * Updates memory controller clock source reference counts.
+ * 
+ * @param hDevice The RM device handle.
+ * @param pCinfo Pointer to the memory controller clock descriptor.
+ * @param pCstate Pointer to the memory controller clock state.
+ */
+void
+NvRmPrivMemoryClockReAttach(
+    NvRmDeviceHandle hDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    const NvRmModuleClockState* pCstate);
+
+/**
+ * Updates generic module clock source reference counts.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * @param pCstate Pointer to the targeted module clock state.
+ */
+void
+NvRmPrivModuleClockReAttach(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* cinfo,
+    const NvRmModuleClockState* state);
+
+/**
+ * Updates external clock source references.
+ * 
+ * @param hDevice The RM device handle.
+ * @param SourceId The external clock source ID.
+ * @param Enable NV_TRUE if external clock is enabled;
+ *  NV_FALSE if external clock is disabled.
+ */
+void
+NvRmPrivExternalClockAttach( 
+    NvRmDeviceHandle hDevice,
+    NvRmClockSource SourceId,
+    NvBool Enable);
+
+/**
+ * Updates PLL attachment reference count and PLL stop flag in the storage
+ *  shared by RM and NV boot loader.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param pPllRef Pointer to the PLL references record.
+ * @param Increment If NV_TRUE, increment PLL reference count,
+ *  if NV_FALSE, decrement PLL reference count.
+ */
+void
+NvRmPrivPllRefUpdate(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmPllReference* pPllRef,
+    NvBool Increment);
+
+/**
+ * Verifies if the targeted module is prohibited to use the specified clock
+ *  source per clock manager policy.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module Target module ID.
+ * @param SourceId Clock source ID.
+ * 
+ * @return NV_TRUE if the targeted module is prohibited to use the specified
+ *  clock source; NV_FALSE if the targeted module can use the specified clock
+ *  source.
+ */
+NvBool
+NvRmPrivIsSourceProtected(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvRmClockSource SourceId);
+
+/**
+ * Gets maximum avilable clock source frequency for the specified module
+ *  per clock manager policy.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * 
+ * @return Source frequency in kHz.
+ */
+NvRmFreqKHz
+NvRmPrivModuleGetMaxSrcKHz(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo);
+
+/**
+ * Similar to the Rm pulbic Module reset API, but have the option of either
+ * pulsing or keeping the reset line active.
+ *
+ * @param hold  if NV_TRUE keep the asserting the reset. If the value is
+ * NV_FALSE pulse a reset to the hardware module.
+ *
+ */
+void 
+NvRmPrivModuleReset(NvRmDeviceHandle hDevice, NvRmModuleID ModuleId, NvBool hold);
+
+/**
+ * Updates voltage scaling references, when the specified module clock
+ * is enabled, or disabled.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * @param pCstate Pointer to the targeted module clock state.
+ * @param Enable NV_TRUE if module clock is about to be enabled;
+ *  NV_FALSE if module clock has just been disabled.
+ * @param Preview NV_TRUE if scaling references should be preserved when
+ *  voltage increase is required, NV_FALSE if scaling references should
+ *  be updated in any case.
+ * 
+ * @return Core voltage level in mV required for the new module configuration.
+ *  NvRmVoltsUnspecified is returned if module clock can be enabled without
+ *  changing voltage requirements. NvRmVoltsOff is returned when module clock
+ *  is disabled.
+ */
+NvRmMilliVolts
+NvRmPrivModuleVscaleAttach(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    NvRmModuleClockState* pCstate,
+    NvBool Enable,
+    NvBool Preview);
+
+/**
+ * Updates voltage scaling references, when the clock frequency for the
+ * specified module is re-configured.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * @param pCstate Pointer to the targeted module clock state.
+ * @param TargetModuleKHz Traget module frequency in kHz.
+ * @param TargetSrcKHz Clock source frequency for the traget module in kHz.
+ * @param Preview NV_TRUE if scaling references should be preserved when
+ *  voltage increase is required, NV_FALSE if scaling references should
+ *  be updated in any case.
+ *
+ * @return Core voltage level in mV required for new module configuration.
+ *  NvRmVoltsUnspecified is returned if all specified frequencies can be
+ *  configured without changing voltage requirements. NvRmVoltsOff is returned
+ *  if new configuration may lower voltage requirements.
+ */
+NvRmMilliVolts
+NvRmPrivModuleVscaleReAttach(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    NvRmModuleClockState* pCstate,
+    NvRmFreqKHz TargetModuleKHz,
+    NvRmFreqKHz TargetSrcKHz,
+    NvBool Preview);
+
+/**
+ * Updates target level, and reference count for pending voltage scaling
+ * transactions.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param Set PendingMv pending transaction target; NvRmVoltsOff is used
+ *  to indicate completed transaction.
+ *
+ */
+void NvRmPrivModuleVscaleSetPending(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMilliVolts PendingMv);
+
+/**
+ * Sets voltage scaling attribute for the specified module clock.
+ * 
+ * @param hRmDeviceHandle The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * @param pCstate Pointer to the targeted module clock state, which is updated
+ *  by this function. 
+ * 
+ * @note The scaling attribute in the clock state structure is set NV_FALSE for
+ *  all core clocks (CPU, AVP, system buses, memory). For modules designated
+ *  clocks it is set NV_FALSE if any frequency within module clock limits can
+ *  be selected at any core voltage level within SoC operational range.
+ *  Otherwise, the attribute is set NV_TRUE.
+ */
+void
+NvRmPrivModuleSetScalingAttribute(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    NvRmModuleClockState* pCstate);
+
+/**
+ * Sets "as is" module clock configuration as specified by the given
+ * clock state structure.
+ *
+ * @param hRmDevice The RM device handle.
+ * @param pCinfo Pointer to the targeted module clock descriptor.
+ * @param pCstate Pointer to the targeted module clock state to be set
+ *  by this function. 
+ */
+void
+NvRmPrivModuleClockSet(
+    NvRmDeviceHandle hRmDevice,
+    const NvRmModuleClockInfo* pCinfo,
+    const NvRmModuleClockState* pCstate);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  // INCLUDED_NVRM_CLOCKS_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_clocks_limits_private.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_clocks_limits_private.h
new file mode 100644
index 000000000000..fb8bb3b0e781
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_clocks_limits_private.h
@@ -0,0 +1,308 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_CLOCKS_LIMITS_PRIVATE_H
+#define INCLUDED_NVRM_CLOCKS_LIMITS_PRIVATE_H
+
+#include "nvrm_power_private.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// Maximum supported SoC process corners
+#define NVRM_PROCESS_CORNERS (4)
+
+// Maximum supported core and/or CPU voltage characterization steps
+#define NVRM_VOLTAGE_STEPS (7)
+
+// Minimum required core voltage resolution
+#define NVRM_CORE_RESOLUTION_MV (25)
+
+/// Maximum safe core voltage step
+#define NVRM_SAFE_VOLTAGE_STEP_MV (100)
+
+// Minimum system bus frequency
+#define NVRM_BUS_MIN_KHZ (32)
+
+// Minimum SDRAM bus frequency
+#define NVRM_SDRAM_MIN_KHZ (12000)
+
+// ID used by RM to record clock sources V/F dependencies
+#define NVRM_DEVID_CLK_SRC (1000)
+
+/**
+ * Oscillator (main) clock doubler configuration record
+ */
+typedef struct NvRmOscDoublerConfigRec
+{
+    NvRmFreqKHz OscKHz;
+    NvU32 Taps[NVRM_PROCESS_CORNERS];
+} NvRmOscDoublerConfig;
+
+/**
+ * Module clocks limits arranged according to the HW module IDs.
+ */
+typedef struct NvRmScaledClkLimitsRec
+{
+    NvU32 HwDeviceId;
+    NvU32 SubClockId;
+    NvRmFreqKHz MinKHz;
+    NvRmFreqKHz MaxKHzList[NVRM_VOLTAGE_STEPS];
+} NvRmScaledClkLimits;
+
+/**
+ * Combines maximum limits for modules depended on SoC SKU
+ */
+typedef struct NvRmSKUedLimitsRec
+{
+    NvRmFreqKHz CpuMaxKHz;
+    NvRmFreqKHz AvpMaxKHz;
+    NvRmFreqKHz VdeMaxKHz;
+    NvRmFreqKHz McMaxKHz;
+    NvRmFreqKHz Emc2xMaxKHz;
+    NvRmFreqKHz TDMaxKHz;
+    NvRmFreqKHz DisplayAPixelMaxKHz;
+    NvRmFreqKHz DisplayBPixelMaxKHz;
+    NvRmMilliVolts NominalCoreMv;   // for common core rail
+    NvRmMilliVolts NominalCpuMv;    // for dedicated CPU rail
+} NvRmSKUedLimits;
+
+/**
+ * Combines SoC frequency/voltage shmoo data
+ * (includes data for CPU on the common core rail)
+ */
+typedef struct NvRmSocShmooRec
+{
+    const NvU32* ShmooVoltages;
+    NvU32 ShmooVmaxIndex;
+
+    const NvRmScaledClkLimits* ScaledLimitsList;
+    NvU32 ScaledLimitsListSize;
+
+    const NvRmSKUedLimits* pSKUedLimits;
+
+    const NvRmOscDoublerConfig* OscDoublerCfgList;
+    NvU32 OscDoublerCfgListSize;
+
+    NvU32 DqsibOffset;
+    NvRmMilliVolts SvopLowVoltage;
+    NvU32 SvopLowSetting;
+    NvU32 SvopHighSetting;
+} NvRmSocShmoo;
+
+/**
+ * Combines frequency/voltage shmoo data for CPU on the dedicated voltage rail
+ * (separated from common SoC core rail)
+ */
+typedef struct NvRmCpuShmooRec
+{
+    const NvU32* ShmooVoltages;
+    NvU32 ShmooVmaxIndex;
+
+    const NvRmScaledClkLimits* pScaledCpuLimits;
+} NvRmCpuShmoo;
+
+/**
+ * Combines chip SKU and process corner records with shmoo data
+ */
+typedef struct NvRmChipFlavorRec
+{
+    NvU16 sku;
+
+    NvU16 corner;
+    const NvRmSocShmoo* pSocShmoo; // shmoo core rail (may include CPU)
+
+    NvU16 CpuCorner;
+    const NvRmCpuShmoo* pCpuShmoo; // shmoo dedicated CPU rail (NULL if none)
+} NvRmChipFlavor;
+
+/**
+ * Combines module clock frequency limits
+ */
+typedef struct NvRmModuleClockLimitsRec
+{
+    NvRmFreqKHz MinKHz;
+    NvRmFreqKHz MaxKHz;
+} NvRmModuleClockLimits;
+
+/**
+ * Initializes module clock limits table.
+ * 
+ * @param hRmDevice The RM device handle. 
+ * 
+ * @return A pointer to the module clock limits table
+ */
+const NvRmModuleClockLimits*
+NvRmPrivClockLimitsInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Gets list of maximum frequencies for the specified module clock in
+ * ascending order of scaling voltage levels.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module  The targeted module ID.
+ * @param pListSize A pointer to a variable filled with list size (i.e.,
+ *  number of scaling voltage levels)
+ * 
+ * @return Pointer to the frequencies list (NULL if the module is not present,
+ *  or the list does not exist)
+ */
+const NvRmFreqKHz*
+NvRmPrivModuleVscaleGetMaxKHzList(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvU32* pListSize);
+
+/**
+ * Gets core voltage level required for operation of the specified module
+ * at the specified frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param Module  The targeted module ID.
+ * @param FreqKHz The trageted module frequency in kHz.
+ * 
+ * @return Core voltage level in mV.
+ */
+NvRmMilliVolts
+NvRmPrivModuleVscaleGetMV(
+    NvRmDeviceHandle hRmDevice,
+    NvRmModuleID Module,
+    NvRmFreqKHz FreqKHz);
+
+/**
+ * Gets minimum core voltage level required for operation of all non-DFS
+ * modules at current frequencies.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return Core voltage level in mV.
+ */
+NvRmMilliVolts
+NvRmPrivModulesGetOperationalMV(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Gets minimum core voltage level required to use module clock source with
+ * specified frequency.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return Core voltage level in mV.
+ */
+NvRmMilliVolts
+NvRmPrivSourceVscaleGetMV(NvRmDeviceHandle hRmDevice, NvRmFreqKHz FreqKHz);
+
+/**
+ * Gets SoC nominal core voltage.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return Nominal core voltage in mV.
+ */
+NvRmMilliVolts
+NvRmPrivGetNominalMV(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Gets number of delay taps for Oscillator Doubler.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param OscKHz Oscillator (main) frequency in KHz.
+ * @param pTaps A pointer to the variable, filled with number of delay taps.
+ * 
+ * @return NvSuccess if the specified oscillator frequency is supported, and
+ * NvError_NotSupported, otherwise.
+ */
+NvError
+NvRmPrivGetOscDoublerTaps(
+    NvRmDeviceHandle hRmDevice,
+    NvRmFreqKHz OscKHz,
+    NvU32* pTaps);
+
+/**
+ * Gets RAM SVOP low voltage parameters.
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pSvopLowMv A pointer to a variable filled with SVOP low voltage
+ *  threshold in mv.
+ * @param pSvopLvSetting A pointer to a variable filled with SVOP low voltage
+ *  settings.
+ * @param pSvopHvSetting A pointer to a variable filled with SVOP high voltage
+ *  settings.
+ */
+void
+NvRmPrivGetSvopParameters(
+    NvRmDeviceHandle hRmDevice,
+    NvRmMilliVolts* pSvopLowMv,
+    NvU32* pSvopLvSetting,
+    NvU32* pSvopHvSetting);
+
+/**
+ * Gets 32-bit offset to ODM EMC DQSIB settings.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return DQSIB offset.
+ */
+NvU32
+NvRmPrivGetEmcDqsibOffset(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Verifies if SoC has dedicated CPU voltage rail.
+ * 
+ * @param hRmDevice The RM device handle.
+ * 
+ * @return NV_TRUE if SoC has dedicated CPU voltage rail,
+ *  and NV_FALSE if CPU is on common SoC core rail.
+ */
+NvBool NvRmPrivIsCpuRailDedicated(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Initializes SoC characterization data base
+ * 
+ * @param hRmDevice The RM device handle.
+ * @param pChipFlavor a pointer to the chip "flavor" structure
+ *  that this function fills in
+ * 
+ * @return NvSuccess if completed successfully, or NvError_NotSupported,
+ *  otherwise.
+ */
+NvError
+NvRmPrivChipShmooDataInit(
+    NvRmDeviceHandle hRmDevice,
+    NvRmChipFlavor* pChipFlavor);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif  // INCLUDED_NVRM_CLOCKS_LIMITS_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_configuration.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_configuration.h
new file mode 100644
index 000000000000..f5b3ff0e1ae8
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_configuration.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_CONFIGURATION_H
+#define INCLUDED_NVRM_CONFIGURATION_H
+
+#include "nvcommon.h"
+#include "nverror.h"
+
+/**
+ * The RM configuration variables are represented by two structures:
+ * a configuration map, which lists all of the variables, their default
+ * values and types, and a struct of strings, which holds the runtime value of
+ * the variables.  The map holds the index into the runtime structure.
+ *
+ */
+
+/**
+ * The configuration varible type.
+ */
+typedef enum
+{
+    /* String should be parsed as a decimal */
+    NvRmCfgType_Decimal = 0,
+
+    /* String should be parsed as a hexadecimal */
+    NvRmCfgType_Hex = 1,
+
+    /* String should be parsed as a character */
+    NvRmCfgType_Char = 2,
+
+    /* String used as-is. */
+    NvRmCfgType_String = 3,
+} NvRmCfgType;
+
+/**
+ * The configuration map (all possible variables).  The map must be
+ * null terminated.  Each Rm instance (for each chip) can/will have
+ * different configuration maps.
+ */
+typedef struct NvRmCfgMap_t
+{  
+    const char *name;
+    NvRmCfgType type; 
+    void *initial; /* default value of the variable */
+    void *offset; /* the index into the string structure */
+} NvRmCfgMap;
+
+/* helper macro for generating the offset for the map */
+#define STRUCT_OFFSET( s, e )       (void *)(&(((s*)0)->e))
+
+/* maximum size of a configuration variable */
+#define NVRM_CFG_MAXLEN NVOS_PATH_MAX
+
+/**
+ * get the default configuration variables.
+ *
+ * @param map The configuration map
+ * @param cfg The configuration runtime values
+ */
+NvError
+NvRmPrivGetDefaultCfg( NvRmCfgMap *map, void *cfg );
+
+/**
+ * get requested configuration.
+ *
+ * @param map The configuration map
+ * @param cfg The configuration runtime values
+ *
+ * Note: 'cfg' should have already been initialized with
+ * NvRmPrivGetDefaultCfg()  before calling this.
+ */
+NvError
+NvRmPrivReadCfgVars( NvRmCfgMap *map, void *cfg );
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_graphics_private.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_graphics_private.h
new file mode 100644
index 000000000000..3953b3665d3d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_graphics_private.h
@@ -0,0 +1,77 @@
+/*
+ * arch/arm/mach-tegra/nvrm/core/common/nvrm_graphics_private.h
+ *
+ *
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef NVRM_GRAPHICS_PRIVATE_H
+#define NVRM_GRAPHICS_PRIVATE_H
+
+#define NVRM_TRANSPORT_IN_KERNEL 1
+
+/**
+ * Initialize all graphics stuff
+ *
+ * @param hDevice The RM instance
+ */
+NvError
+NvRmGraphicsOpen( NvRmDeviceHandle rm );
+
+/**
+ * Deinitialize all graphics stuff
+ *
+ * @param hDevice The RM instance
+ */
+void
+NvRmGraphicsClose( NvRmDeviceHandle rm );
+
+/**
+ * Initialize the channels.
+ *
+ * @param hDevice The RM instance
+ */
+NvError
+NvRmPrivChannelInit( NvRmDeviceHandle hDevice );
+
+/**
+ * Deinitialize the channels.
+ *
+ * @param hDevice The RM instance
+ */
+void
+NvRmPrivChannelDeinit( NvRmDeviceHandle hDevice );
+
+/**
+ * Initialize the graphics host, including interrupts.
+ */
+void
+NvRmPrivHostInit( NvRmDeviceHandle rm );
+
+void
+NvRmPrivHostShutdown( NvRmDeviceHandle rm );
+
+#if (NVRM_TRANSPORT_IN_KERNEL == 0)
+NvError
+NvRmPrivTransportInit(NvRmDeviceHandle hRmDevice);
+
+void
+NvRmPrivTransportDeInit(NvRmDeviceHandle hRmDevice);
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_hw_devids.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_hw_devids.h
new file mode 100644
index 000000000000..9ce89e16b3b3
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_hw_devids.h
@@ -0,0 +1,447 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_HW_DEVIDS_H
+#define INCLUDED_NVRM_HW_DEVIDS_H
+
+// Memory Aperture: Internal Memory
+#define NVRM_DEVID_IMEM                            1
+
+// Memory Aperture: External Memory
+#define NVRM_DEVID_EMEM                            2
+
+// Memory Aperture: TCRAM
+#define NVRM_DEVID_TCRAM                           3
+
+// Memory Aperture: IRAM
+#define NVRM_DEVID_IRAM                            4
+
+// Memory Aperture: NOR FLASH
+#define NVRM_DEVID_NOR                             5
+
+// Memory Aperture: EXIO
+#define NVRM_DEVID_EXIO                            6
+
+// Memory Aperture: GART
+#define NVRM_DEVID_GART                            7
+
+// Device Aperture: Graphics Host (HOST1X)
+#define NVRM_DEVID_HOST1X                          8
+
+// Device Aperture: ARM PERIPH registers
+#define NVRM_DEVID_ARM_PERIPH                      9
+
+// Device Aperture: MSELECT
+#define NVRM_DEVID_MSELECT                         10
+
+// Device Aperture: memory controller
+#define NVRM_DEVID_MC                              11
+
+// Device Aperture: external memory controller
+#define NVRM_DEVID_EMC                             12
+
+// Device Aperture: video input
+#define NVRM_DEVID_VI                              13
+
+// Device Aperture: encoder pre-processor
+#define NVRM_DEVID_EPP                             14
+
+// Device Aperture: video encoder
+#define NVRM_DEVID_MPE                             15
+
+// Device Aperture: 3D engine
+#define NVRM_DEVID_GR3D                            16
+
+// Device Aperture: 2D + SBLT engine
+#define NVRM_DEVID_GR2D                            17
+
+// Device Aperture: Image Signal Processor
+#define NVRM_DEVID_ISP                             18
+
+// Device Aperture: DISPLAY
+#define NVRM_DEVID_DISPLAY                         19
+
+// Device Aperture: UPTAG
+#define NVRM_DEVID_UPTAG                           20
+
+// Device Aperture - SHR_SEM
+#define NVRM_DEVID_SHR_SEM                         21
+
+// Device Aperture - ARB_SEM
+#define NVRM_DEVID_ARB_SEM                         22
+
+// Device Aperture - ARB_PRI
+#define NVRM_DEVID_ARB_PRI                         23
+
+// Obsoleted for AP15
+#define NVRM_DEVID_PRI_INTR                        24
+
+// Obsoleted for AP15
+#define NVRM_DEVID_SEC_INTR                        25
+
+// Device Aperture: Timer Programmable
+#define NVRM_DEVID_TMR                             26
+
+// Device Aperture: Clock and Reset
+#define NVRM_DEVID_CAR                             27
+
+// Device Aperture: Flow control
+#define NVRM_DEVID_FLOW                            28
+
+// Device Aperture: Event
+#define NVRM_DEVID_EVENT                           29
+
+// Device Aperture: AHB DMA
+#define NVRM_DEVID_AHB_DMA                         30
+
+// Device Aperture: APB DMA
+#define NVRM_DEVID_APB_DMA                         31
+
+// Obsolete - use AVP_CACHE
+#define NVRM_DEVID_CC                              32
+
+// Device Aperture: COP Cache Controller
+#define NVRM_DEVID_AVP_CACHE                       32
+
+// Device Aperture: SYS_REG
+#define NVRM_DEVID_SYS_REG                         32
+
+// Device Aperture: System Statistic monitor
+#define NVRM_DEVID_STAT                            33
+
+// Device Aperture: GPIO
+#define NVRM_DEVID_GPIO                            34
+
+// Device Aperture: Vector Co-Processor 2
+#define NVRM_DEVID_VCP                             35
+
+// Device Aperture: Arm Vectors
+#define NVRM_DEVID_VECTOR                          36
+
+// Device: MEM
+#define NVRM_DEVID_MEM                             37
+
+// Obsolete - use VDE
+#define NVRM_DEVID_SXE                             38
+
+// Device Aperture: video decoder
+#define NVRM_DEVID_VDE                             38
+
+// Obsolete - use VDE
+#define NVRM_DEVID_BSEV                            39
+
+// Obsolete - use VDE
+#define NVRM_DEVID_MBE                             40
+
+// Obsolete - use VDE
+#define NVRM_DEVID_PPE                             41
+
+// Obsolete - use VDE
+#define NVRM_DEVID_MCE                             42
+
+// Obsolete - use VDE
+#define NVRM_DEVID_TFE                             43
+
+// Obsolete - use VDE
+#define NVRM_DEVID_PPB                             44
+
+// Obsolete - use VDE
+#define NVRM_DEVID_VDMA                            45
+
+// Obsolete - use VDE
+#define NVRM_DEVID_UCQ                             46
+
+// Device Aperture: BSEA (now in AVP cluster)
+#define NVRM_DEVID_BSEA                            47
+
+// Obsolete - use VDE
+#define NVRM_DEVID_FRAMEID                         48
+
+// Device Aperture: Misc regs
+#define NVRM_DEVID_MISC                            49
+
+// Obsolete
+#define NVRM_DEVID_AC97                            50
+
+// Device Aperture: S/P-DIF
+#define NVRM_DEVID_SPDIF                           51
+
+// Device Aperture: I2S
+#define NVRM_DEVID_I2S                             52
+
+// Device Aperture: UART
+#define NVRM_DEVID_UART                            53
+
+// Device Aperture: VFIR
+#define NVRM_DEVID_VFIR                            54
+
+// Device Aperture: NAND Flash Controller
+#define NVRM_DEVID_NANDCTRL                        55
+
+// Obsolete - use NANDCTRL
+#define NVRM_DEVID_NANDFLASH                       55
+
+// Device Aperture: HSMMC
+#define NVRM_DEVID_HSMMC                           56
+
+// Device Aperture: XIO
+#define NVRM_DEVID_XIO                             57
+
+// Device Aperture: PWFM
+#define NVRM_DEVID_PWFM                            58
+
+// Device Aperture: MIPI
+#define NVRM_DEVID_MIPI_HS                         59
+
+// Device Aperture: I2C
+#define NVRM_DEVID_I2C                             60
+
+// Device Aperture: TWC
+#define NVRM_DEVID_TWC                             61
+
+// Device Aperture: SLINK
+#define NVRM_DEVID_SLINK                           62
+
+// Device Aperture: SLINK4B
+#define NVRM_DEVID_SLINK4B                         63
+
+// Device Aperture: SPI
+#define NVRM_DEVID_SPI                             64
+
+// Device Aperture: DTV
+#define NVRM_DEVID_DTV                             64
+
+// Device Aperture: DVC
+#define NVRM_DEVID_DVC                             65
+
+// Device Aperture: RTC
+#define NVRM_DEVID_RTC                             66
+
+// Device Aperture: KeyBoard Controller
+#define NVRM_DEVID_KBC                             67
+
+// Device Aperture: PMIF
+#define NVRM_DEVID_PMIF                            68
+
+// Device Aperture: FUSE
+#define NVRM_DEVID_FUSE                            69
+
+// Device Aperture: L2 Cache Controller
+#define NVRM_DEVID_CMC                             70
+
+// Device Apertuer: NOR FLASH Controller
+#define NVRM_DEVID_NOR_REG                         71
+
+// Device Aperture: EIDE
+#define NVRM_DEVID_EIDE                            72
+
+// Device Aperture: USB
+#define NVRM_DEVID_USB                             73
+
+// Device Aperture: SDIO
+#define NVRM_DEVID_SDIO                            74
+
+// Device Aperture: TVO
+#define NVRM_DEVID_TVO                             75
+
+// Device Aperture: DSI
+#define NVRM_DEVID_DSI                             76
+
+// Device Aperture: HDMI
+#define NVRM_DEVID_HDMI                            77
+
+// Device Aperture: Third Interrupt Controller extra registers
+#define NVRM_DEVID_TRI_INTR                        78
+
+// Device Aperture: Common Interrupt Controller
+#define NVRM_DEVID_ICTLR                           79
+
+// Non-Aperture Interrupt: DMA TX interrupts
+#define NVRM_DEVID_DMA_TX_INTR                     80
+
+// Non-Aperture Interrupt: DMA RX interrupts
+#define NVRM_DEVID_DMA_RX_INTR                     81
+
+// Non-Aperture Interrupt: SW reserved interrupt
+#define NVRM_DEVID_SW_INTR                         82
+
+// Non-Aperture Interrupt: CPU PMU Interrupt
+#define NVRM_DEVID_CPU_INTR                        83
+
+// Device Aperture: Timer Free Running MicroSecond
+#define NVRM_DEVID_TMRUS                           84
+
+// Device Aperture: Interrupt Controller ARB_GNT Registers
+#define NVRM_DEVID_ICTLR_ARBGNT                    85
+
+// Device Aperture: Interrupt Controller DMA Registers
+#define NVRM_DEVID_ICTLR_DRQ                       86
+
+// Device Aperture: AHB DMA Channel
+#define NVRM_DEVID_AHB_DMA_CH                      87
+
+// Device Aperture: APB DMA Channel
+#define NVRM_DEVID_APB_DMA_CH                      88
+
+// Device Aperture: AHB Arbitration Controller
+#define NVRM_DEVID_AHB_ARBC                        89
+
+// Obsolete - use AHB_ARBC
+#define NVRM_DEVID_AHB_ARB_CTRL                    89
+
+// Device Aperture: AHB/APB Debug Bus Registers
+#define NVRM_DEVID_AHPBDEBUG                       91
+
+// Device Aperture: Secure Boot Register
+#define NVRM_DEVID_SECURE_BOOT                     92
+
+// Device Aperture: SPROM
+#define NVRM_DEVID_SPROM                           93
+
+// Memory Aperture: AHB external memory remapping
+#define NVRM_DEVID_AHB_EMEM                        94
+
+// Non-Aperture Interrupt: External PMU interrupt
+#define NVRM_DEVID_PMU_EXT                         95
+
+// Device Aperture: AHB EMEM to MC Flush Register
+#define NVRM_DEVID_PPCS                            96
+
+// Device Aperture: MMU TLB registers for COP/AVP
+#define NVRM_DEVID_MMU_TLB                         97
+
+// Device Aperture: OVG engine
+#define NVRM_DEVID_VG                              98
+
+// Device Aperture: CSI
+#define NVRM_DEVID_CSI                             99
+
+// Device ID for COP
+#define NVRM_DEVID_AVP                             100
+
+// Device ID for MPCORE
+#define NVRM_DEVID_CPU                             101
+
+// Device Aperture: ULPI controller
+#define NVRM_DEVID_ULPI                            102
+
+// Device Aperture: ARM CONFIG registers
+#define NVRM_DEVID_ARM_CONFIG                      103
+
+// Device Aperture: ARM PL310 (L2 controller)
+#define NVRM_DEVID_ARM_PL310                       104
+
+// Device Aperture: PCIe
+#define NVRM_DEVID_PCIE                            105
+
+// Device Aperture: OWR (one wire)
+#define NVRM_DEVID_OWR                             106
+
+// Device Aperture: AVPUCQ
+#define NVRM_DEVID_AVPUCQ                          107
+
+// Device Aperture: AVPBSEA (obsolete)
+#define NVRM_DEVID_AVPBSEA                         108
+
+// Device Aperture: Sync NOR
+#define NVRM_DEVID_SNOR                            109
+
+// Device Aperture: SDMMC
+#define NVRM_DEVID_SDMMC                           110
+
+// Device Aperture: KFUSE
+#define NVRM_DEVID_KFUSE                           111
+
+// Device Aperture: CSITE
+#define NVRM_DEVID_CSITE                           112
+
+// Non-Aperture Interrupt: ARM Interprocessor Interrupt
+#define NVRM_DEVID_ARM_IPI                         113
+
+// Device Aperture: ARM Interrupts 0-31
+#define NVRM_DEVID_ARM_ICTLR                       114
+
+// Device Aperture: IOBIST
+#define NVRM_DEVID_IOBIST                          115
+
+// Device Aperture: SPEEDO
+#define NVRM_DEVID_SPEEDO                          116
+
+// Device Aperture: LA
+#define NVRM_DEVID_LA                              117
+
+// Device Aperture: VS
+#define NVRM_DEVID_VS                              118
+
+// Device Aperture: VCI
+#define NVRM_DEVID_VCI                             119
+
+// Device Aperture: APBIF
+#define NVRM_DEVID_APBIF                           120
+
+// Device Aperture: AUDIO
+#define NVRM_DEVID_AUDIO                           121
+
+// Device Aperture: DAM
+#define NVRM_DEVID_DAM                             122
+
+// Device Aperture: TSENSOR
+#define NVRM_DEVID_TSENSOR                         123
+
+// Device Aperture: SE
+#define NVRM_DEVID_SE                              124
+
+// Device Aperture: TZRAM
+#define NVRM_DEVID_TZRAM                           125
+
+// Device Aperture: AUDIO_CLUSTER
+#define NVRM_DEVID_AUDIO_CLUSTER                   126
+
+// Device Aperture: HDA
+#define NVRM_DEVID_HDA                             127
+
+// Device Aperture: SATA
+#define NVRM_DEVID_SATA                            128
+
+// Device Aperture: ATOMICS
+#define NVRM_DEVID_ATOMICS                         129
+
+// Device Aperture: IPATCH
+#define NVRM_DEVID_IPATCH                          130
+
+// Device Aperture: Activity Monitor
+#define NVRM_DEVID_ACTMON                          131
+
+// Device Aperture: Watch Dog Timer
+#define NVRM_DEVID_WDT                             132
+
+#endif // INCLUDED_NVRM_HW_DEVIDS_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_hwintf.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_hwintf.h
new file mode 100644
index 000000000000..07017fb9b337
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_hwintf.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NVRM_HWINTF_H
+#define NVRM_HWINTF_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+#include "nvrm_module.h"
+#include "nvrm_module_private.h"
+#include "nvrm_hardware_access.h"
+
+#endif  /* NVRM_HWINTF_H */
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_init_stub.c b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_init_stub.c
new file mode 100644
index 000000000000..481ebd43260f
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_init_stub.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.  All rights reserved.
+ *
+ * NVIDIA Corporation and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA Corporation is strictly prohibited.
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvidlcmd.h"
+#include "nvrm_init.h"
+
+void NvRmClose(NvRmDeviceHandle hDevice)
+{
+}
+
+NvError NvRmOpenNew(NvRmDeviceHandle *pHandle)
+{
+    *pHandle = (void *)1;
+    return NvSuccess;
+}
+
+void NvRmInit(NvRmDeviceHandle *pHandle)
+{
+}
+
+NvError NvRmOpen(NvRmDeviceHandle *pHandle, NvU32 DeviceId)
+{
+    return NvRmOpenNew(pHandle);
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_message.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_message.h
new file mode 100644
index 000000000000..28ead1029339
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_message.h
@@ -0,0 +1,276 @@
+/*
+ * arch/arm/mach-tegra/nvrm/core/common/nvrm_message.h
+ *
+ *
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef INCLUDED_NVRM_MESSAGE_H
+#define INCLUDED_NVRM_MESSAGE_H
+
+#include "nvrm_memmgr.h"
+#include "nvrm_module.h"
+#include "nvrm_transport.h"
+#include "nvrm_power.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/* Maximum message queue depth */
+enum {MAX_QUEUE_DEPTH = 5};
+/* Maximum message length */
+enum {MAX_MESSAGE_LENGTH = 256};
+/* Maximum argument size */
+enum {MAX_ARGS_SIZE = 220};
+/* Max String length */
+enum {MAX_STRING_LENGTH = 200};
+
+typedef struct NvRmRPCRec
+{
+    NvRmTransportHandle svcTransportHandle;
+    NvOsSemaphoreHandle TransportRecvSemId;
+    NvOsMutexHandle RecvLock;
+    NvRmDeviceHandle hRmDevice;
+    NvBool isConnected;
+} NvRmRPC;
+
+typedef struct NvRmRPCRec *NvRmRPCHandle;
+
+void NvRmPrivProcessMessage(NvRmRPCHandle hRPCHandle, char *pRecvMessage, int messageLength);
+
+typedef enum
+{
+    NvRmMsg_MemHandleCreate = 0x0,
+    NvRmMsg_MemHandleCreate_Response,
+    NvRmMsg_MemHandleOpen,
+    NvRmMsg_MemHandleFree,
+    NvRmMsg_MemAlloc,
+    NvRmMsg_MemAlloc_Response,
+    NvRmMsg_MemPin,
+    NvRmMsg_MemPin_Response,
+    NvRmMsg_MemUnpin,
+    NvRmMsg_MemUnpin_Response,
+    NvRmMsg_MemGetAddress,
+    NvRmMsg_MemGetAddress_Response,
+    NvRmMsg_HandleFromId,
+    NvRmMsg_HandleFromId_Response,
+    NvRmMsg_PowerModuleClockControl,
+    NvRmMsg_PowerModuleClockControl_Response,
+    NvRmMsg_ModuleReset,
+    NvRmMsg_ModuleReset_Response,
+    NvRmMsg_PowerRegister,
+    NvRmMsg_PowerUnRegister,
+    NvRmMsg_PowerStarvationHint,
+    NvRmMsg_PowerBusyHint,
+    NvRmMsg_PowerBusyMultiHint,
+    NvRmMsg_PowerDfsGetState,
+    NvRmMsg_PowerDfsGetState_Response,
+    NvRmMsg_PowerResponse,
+    NvRmMsg_PowerModuleGetMaxFreq,
+    NvRmMsg_InitiateLP0,
+    NvRmMsg_InitiateLP0_Response,
+    NvRmMsg_RemotePrintf,
+    NvRmMsg_AttachModule,
+    NvRmMsg_AttachModule_Response,
+    NvRmMsg_DetachModule,
+    NvRmMsg_DetachModule_Response,
+    NvRmMsg_AVP_Reset,
+    NvRmMsg_PowerDfsGetClockUtilization,
+    NvRmMsg_PowerDfsGetClockUtilization_Response,
+    NvRmMsg_Force32 = 0x7FFFFFFF
+}NvRmMsg;
+
+typedef struct{
+    NvRmMsg         msg;
+    NvU32           size;
+}NvRmMessage_HandleCreat;
+
+typedef struct{
+    NvRmMsg         msg;
+    NvRmMemHandle   hMem;
+    NvError         error;
+}NvRmMessage_HandleCreatResponse;
+
+typedef struct{
+    NvRmMsg        msg;
+    NvRmMemHandle  hMem;
+}NvRmMessage_HandleFree;
+
+typedef struct{
+    NvRmMsg     msg;
+    NvError     error;
+}NvRmMessage_Response;
+
+typedef struct{
+    NvRmMsg             msg;
+    NvRmMemHandle       hMem;
+    NvRmHeap            Heaps[4];
+    NvU32               NumHeaps;
+    NvU32               Alignment;
+    NvOsMemAttribute    Coherency;
+}NvRmMessage_MemAlloc;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvRmMemHandle hMem;
+    NvU32         Offset;
+}NvRmMessage_GetAddress;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvU32         address;
+}NvRmMessage_GetAddressResponse;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvU32         id;
+}NvRmMessage_HandleFromId;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvRmMemHandle hMem;
+}NvRmMessage_Pin;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvU32         address;
+}NvRmMessage_PinResponse;
+
+typedef struct{
+    NvRmMsg         msg;
+    NvRmModuleID    ModuleId;
+    NvU32           ClientId;
+    NvBool          Enable;
+}NvRmMessage_Module;
+
+typedef struct{
+    NvRmMsg msg;
+    NvU32 clientId;
+    NvOsSemaphoreHandle eventSema;
+}NvRmMessage_PowerRegister;
+
+typedef struct{
+    NvRmMsg msg;
+    NvU32 clientId;
+}NvRmMessage_PowerUnRegister;
+
+typedef struct{
+    NvRmMsg msg;
+    NvRmDfsClockId clockId;
+    NvU32 clientId;
+    NvBool starving;
+}NvRmMessage_PowerStarvationHint;
+
+typedef struct{
+    NvRmMsg msg;
+    NvRmDfsClockId clockId;
+    NvU32 clientId;
+    NvU32 boostDurationMS;
+    NvRmFreqKHz boostKHz;
+}NvRmMessage_PowerBusyHint;
+
+typedef struct{
+    NvRmMsg msg;
+    NvU32 numHints;
+    NvU8 busyHints[MAX_STRING_LENGTH];
+}NvRmMessage_PowerBusyMultiHint;
+
+typedef struct{
+    NvRmMsg msg;
+}NvRmMessage_PowerDfsGetState;
+
+typedef struct{
+    NvRmMsg msg;
+    NvError error;
+    NvU32 clientId;
+}NvRmMessage_PowerRegister_Response;
+
+typedef struct{
+    NvRmMsg msg;
+    NvRmDfsRunState state;
+}NvRmMessage_PowerDfsGetState_Response;
+
+typedef struct{
+    NvRmMsg msg;
+    NvRmModuleID moduleID;
+}NvRmMessage_PowerModuleGetMaxFreq;
+
+typedef struct{
+    NvRmMsg msg;
+    NvRmFreqKHz freqKHz;
+}NvRmMessage_PowerModuleGetMaxFreq_Response;
+
+typedef struct{
+    NvRmMsg msg;
+    NvError error;
+    NvRmDfsClockId clockId;
+}NvRmMessage_PowerDfsGetClockUtilization;
+
+typedef struct{
+    NvRmMsg msg;
+    NvError error;
+    NvRmDfsClockUsage clockUsage;
+}NvRmMessage_PowerDfsGetClockUtilization_Response;
+
+typedef struct{
+    NvRmMsg msg;
+    NvU32 sourceAddr;
+    NvU32 bufferAddr;
+    NvU32 bufferSize;
+} NvRmMessage_InitiateLP0;
+
+typedef struct{
+    NvRmMsg msg;
+    const char string[MAX_STRING_LENGTH];
+} NvRmMessage_RemotePrintf;
+
+
+typedef struct{
+    NvRmMsg       msg;
+    NvU32         address;
+    NvU32         size;
+    NvU32         filesize;
+    char          args[MAX_ARGS_SIZE];
+    NvU32         reason;
+}NvRmMessage_AttachModule;
+
+typedef struct {
+    NvRmMsg       msg;
+    NvError       error;
+    NvU32         libraryId;
+}NvRmMessage_AttachModuleResponse;
+
+typedef struct {
+    NvRmMsg       msg;
+    NvU32         reason;
+    NvU32         libraryId;
+}NvRmMessage_DetachModule;
+
+typedef struct{
+    NvRmMsg       msg;
+    NvError       error;
+}NvRmMessage_DetachModuleResponse;
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_module_private.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_module_private.h
new file mode 100644
index 000000000000..0648911e0b1c
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_module_private.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NVRM_MODULE_PRIVATE_H
+#define NVRM_MODULE_PRIVATE_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+#include "nvrm_relocation_table.h"
+#include "nvrm_moduleids.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+typedef struct NvRmModuleTableRec
+{
+    NvRmModule Modules[NvRmPrivModuleID_Num];
+    NvRmModuleInstance *ModInst;
+    NvRmModuleInstance *LastModInst;
+    NvU32 NumModuleInstances;
+    NvRmIrqMap IrqMap;
+} NvRmModuleTable;
+
+/**
+ * Initialize the module info via the relocation table.
+ *
+ * @param mod_table The module table
+ * @param reloc_table The relocation table
+ * @param modid The module id conversion function
+ */
+NvError
+NvRmPrivModuleInit(
+    NvRmModuleTable *mod_table,
+    NvU32 *reloc_table);
+
+void
+NvRmPrivModuleDeinit(
+    NvRmModuleTable *mod_table );
+
+NvRmModuleTable *
+NvRmPrivGetModuleTable(
+    NvRmDeviceHandle hDevice );
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // NVRM_MODULE_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_module_stub.c b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_module_stub.c
new file mode 100644
index 000000000000..8e891e49c7bd
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_module_stub.c
@@ -0,0 +1,219 @@
+
+#define NV_IDL_IS_STUB
+
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.  All rights reserved.
+ *
+ * NVIDIA Corporation and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA Corporation is strictly prohibited.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <mach/iomap.h>
+
+#include "nvcommon.h"
+#include "nvrm_module.h"
+#include "../../../../clock.h"
+
+NvError NvRmModuleGetCapabilities( NvRmDeviceHandle hDeviceHandle,
+    NvRmModuleID Module, NvRmModuleCapability * pCaps, NvU32 NumCaps,
+    void * * Capability )
+{
+	NvU32 major = 0, minor = 0;
+	unsigned i;
+
+        switch (NVRM_MODULE_ID_MODULE(Module)) {
+        case NvRmModuleID_Mpe:
+		major = 1;
+		minor = 2;
+                break;
+
+	case NvRmModuleID_BseA:
+		major = 1;
+		minor = 1;
+		break;
+
+        case NvRmModuleID_Display:
+		major = 1;
+		minor = 3;
+                break;
+
+	case NvRmModuleID_Spdif:
+		major = 1;
+		minor = 0;
+		break;
+
+	case NvRmModuleID_I2s:
+		major = 1;
+		minor = 1;
+		break;
+
+	case NvRmModuleID_Misc:
+		major = 2;
+		minor = 0;
+		break;
+
+	case NvRmModuleID_Vde:
+		major = 1;
+		minor = 2;
+		break;
+
+	case NvRmModuleID_Isp:
+		major = 1;
+		minor = 0;
+		break;
+
+	case NvRmModuleID_Vi:
+		major = 1;
+		minor = 1;
+		break;
+
+	case NvRmModuleID_3D:
+		major = 1;
+		minor = 2;
+		break;
+
+	case NvRmModuleID_2D:
+		major = 1;
+		minor = 1;
+                break;
+
+        default:
+                printk("%s module %d not implemented\n", __func__, Module);
+        }
+
+	for (i=0; i<NumCaps; i++) {
+		if (pCaps[i].MajorVersion==major &&
+		    pCaps[i].MinorVersion==minor) {
+			*Capability = pCaps[i].Capability;
+			return NvSuccess;
+		}
+	}
+
+        return NvError_NotSupported;
+}
+
+NvU32 NvRmModuleGetNumInstances( NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID Module )
+{
+        switch (Module) {
+	case NvRmModuleID_I2s:
+		return 4;
+
+        case NvRmModuleID_Display:
+                return 2;
+
+	case NvRmModuleID_3D:
+	case NvRmModuleID_Avp:
+	case NvRmModuleID_GraphicsHost:
+	case NvRmModuleID_Vcp:
+	case NvRmModuleID_Isp:
+	case NvRmModuleID_Vi:
+	case NvRmModuleID_Epp:
+        case NvRmModuleID_2D:
+	case NvRmModuleID_Spdif:
+	case NvRmModuleID_Vde:
+	case NvRmModuleID_Mpe:
+	case NvRmModuleID_Hdcp:
+	case NvRmModuleID_Hdmi:
+	case NvRmModuleID_Tvo:
+	case NvRmModuleID_Dsi:
+	case NvRmModuleID_BseA:
+                return 1;
+
+        default:
+                printk("%s module %d not implemented\n", __func__, Module);
+                return 1;
+        }
+}
+
+void NvRmModuleGetBaseAddress( NvRmDeviceHandle hRmDeviceHandle, NvRmModuleID Module, NvRmPhysAddr * pBaseAddress, NvU32 * pSize )
+{
+	switch (NVRM_MODULE_ID_MODULE(Module)) {
+	case NvRmModuleID_GraphicsHost:
+		*pBaseAddress = 0x50000000;
+		*pSize = 144 * 1024;
+		break;
+	case NvRmModuleID_Display:
+		*pBaseAddress = 0x54200000 + (NVRM_MODULE_ID_INSTANCE(Module))*0x40000;
+		*pSize = 256 * 1024;
+		break;
+
+	case NvRmModuleID_Mpe:
+		*pBaseAddress = 0x54040000;
+		*pSize = 256 * 1024;
+		break;
+
+	case NvRmModuleID_Vcp:
+		*pBaseAddress = 0x6000e000;
+		*pSize = 4096;
+		break;
+
+    case NvRmModuleID_BseA:
+        *pBaseAddress = 0x60011000;
+        *pSize = 4096;
+        break;
+
+    case NvRmModuleID_Vde:
+        *pBaseAddress = 0x6001a000;
+        *pSize = 0x3c00;
+        break;
+
+	case NvRmModuleID_Vi:
+		*pBaseAddress = 0x54080000;
+		*pSize = 256 * 1024;
+		break;
+
+	case NvRmModuleID_Dsi:
+		*pBaseAddress = 0x54300000;
+		*pSize = 256 * 1024;
+		break;
+
+	default:
+		*pBaseAddress = 0x0000000;
+		*pSize = 00;
+		printk("%s module %d not implemented\n", __func__, Module);
+	}
+	printk("%s module %d 0x%08x x %dK\n", __func__, Module, *pBaseAddress, *pSize / 1024);
+}
+
+#define is_avp(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Avp)
+#define is_vcp(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Vcp)
+#define is_bsea(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_BseA)
+#define is_vde(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Vde)
+
+void NvRmModuleReset(NvRmDeviceHandle hRmDevice, NvRmModuleID Module)
+{
+    struct clk *clk = NULL;
+    void __iomem *clk_rst = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+
+    if (is_avp(Module)) {
+        writel(1<<1, clk_rst + 0x300);
+        udelay(10);
+        writel(1<<1, clk_rst + 0x304);
+    } else if (is_vcp(Module))
+        clk = clk_get_sys("vcp", NULL);
+    else if (is_bsea(Module))
+        clk = clk_get_sys("bsea", NULL);
+    else if (is_vde(Module))
+        clk = clk_get_sys("vde", NULL);
+    else {
+        printk("%s MOD[%lu] INST[%lu] not implemented\n", __func__,
+               NVRM_MODULE_ID_MODULE(Module),
+               NVRM_MODULE_ID_INSTANCE(Module));
+        return;
+    }
+
+    if (clk) {
+        tegra2_periph_reset_assert(clk);
+        udelay(10);
+        tegra2_periph_reset_deassert(clk);
+        clk_put(clk);
+    }
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_moduleids.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_moduleids.h
new file mode 100644
index 000000000000..3d63f093b932
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_moduleids.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NVRM_MODULEIDS_H
+#define NVRM_MODULEIDS_H
+
+#include "nvcommon.h"
+#include "nvrm_module.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/* FIXME - This is depricated. Use NvRmModuleID instead*/ 
+typedef NvRmModuleID NvRmPrivModuleID;
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // NVRM_MODULEIDS_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_moduleloader.c b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_moduleloader.c
new file mode 100644
index 000000000000..a4d47cd1748b
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_moduleloader.c
@@ -0,0 +1,811 @@
+/*
+ * arch/arm/mach-tegra/nvrm/core/common/nvrm_moduleloader.c
+ *
+ * AVP firmware module loader
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#define NV_ENABLE_DEBUG_PRINTS 0
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/device.h>
+#include <linux/string.h>
+#include <linux/miscdevice.h>
+#include <linux/fs.h>
+#include <linux/firmware.h>
+#include <linux/uaccess.h>
+#include <linux/platform_device.h>
+#include <asm/cacheflush.h>
+#include <asm/io.h>
+#include <mach/nvmap.h>
+
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvos.h"
+#include "nvutil.h"
+#include "nvrm_hardware_access.h"
+#include "nvrm_message.h"
+#include "nvrm_rpc.h"
+#include "nvrm_moduleloader.h"
+#include "nvrm_moduleloader_private.h"
+#include "nvrm_graphics_private.h"
+#include "nvrm_structure.h"
+#include "nvfw.h"
+#include "ap15/arflow_ctlr.h"
+#include "ap15/arevp.h"
+#include "mach/io.h"
+#include "mach/iomap.h"
+#include "headavp.h"
+
+#define DEVICE_NAME "nvfw"
+
+#define _TEGRA_AVP_RESET_VECTOR_ADDR	\
+	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + EVP_COP_RESET_VECTOR_0)
+
+static const struct firmware *s_FwEntry;
+static NvRmRPCHandle s_RPCHandle = NULL;
+
+static struct nvmap_handle_ref *s_KernelImage = NULL;
+struct nvmap_client *s_AvpClient = NULL;
+
+static NvError SendMsgDetachModule(NvRmLibraryHandle  hLibHandle);
+static NvError SendMsgAttachModule(
+    NvRmLibraryHandle hLibHandle,
+    void* pArgs,
+    NvU32 loadAddress,
+    NvU32 fileSize,
+    NvBool greedy,
+    NvU32 sizeOfArgs);
+NvU32 NvRmModuleGetChipId(NvRmDeviceHandle hDevice);
+NvError NvRmPrivInitModuleLoaderRPC(NvRmDeviceHandle hDevice);
+void NvRmPrivDeInitModuleLoaderRPC(void);
+static NvError NvRmPrivInitAvp(NvRmDeviceHandle hDevice);
+
+#define AVP_KERNEL_SIZE_MAX	SZ_1M
+
+#define ADD_MASK                   0x00000001
+#define SUB_MASK                   0xFFFFFFFD
+
+static int nvfw_open(struct inode *inode, struct file *file);
+static int nvfw_close(struct inode *inode, struct file *file);
+static long nvfw_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
+static ssize_t nvfw_write(struct file *, const char __user *, size_t, loff_t *);
+
+static NvError NvRmPrivInitAvp(NvRmDeviceHandle hRm);
+
+static const struct file_operations nvfw_fops =
+{
+	.owner		= THIS_MODULE,
+	.open		= nvfw_open,
+	.release	= nvfw_close,
+	.write		= nvfw_write,
+	.unlocked_ioctl = nvfw_ioctl,
+};
+
+static struct miscdevice nvfw_dev =
+{
+	.name	= DEVICE_NAME,
+	.fops	= &nvfw_fops,
+	.minor	= MISC_DYNAMIC_MINOR,
+};
+
+// FIXME: This function is just for debugging.
+ssize_t nvfw_write(struct file *file, const char __user *buff, size_t count, loff_t *offp)
+{
+	NvRmDeviceHandle hRmDevice;
+	NvRmLibraryHandle hRmLibHandle;
+	char filename[100];
+	int error;
+
+	error = copy_from_user(filename, buff, count);
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+	filename[count] = 0;
+	error = NvRmOpen( &hRmDevice, 0 );
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	error = NvRmLoadLibrary(hRmDevice, filename, NULL, 0, &hRmLibHandle);
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	return count;
+}
+
+int nvfw_open(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+int nvfw_close(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static int nvfw_ioctl_load_library(struct file *filp, void __user *arg)
+{
+	struct nvfw_load_handle op;
+	NvRmDeviceHandle hRmDevice;
+	NvRmLibraryHandle hRmLibHandle;
+	char *filename = NULL;
+	void *args = NULL;
+	int error;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	filename = NvOsAlloc(op.length + 1);
+	error = copy_from_user(filename, op.filename, op.length + 1);
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	args = NvOsAlloc(op.argssize);
+	error = copy_from_user(args, op.args, op.argssize);
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	error = NvRmOpen( &hRmDevice, 0 );
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	error = NvRmLoadLibrary(hRmDevice, filename, args, op.argssize, &hRmLibHandle);
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	op.handle = hRmLibHandle;
+	error = copy_to_user(arg, &op, sizeof(op));
+
+	NvOsFree(filename);
+	NvOsFree(args);
+	return error;
+}
+
+static int nvfw_ioctl_load_library_ex(struct file *filp, void __user *arg)
+{
+	struct nvfw_load_handle op;
+	NvRmDeviceHandle hRmDevice;
+	NvRmLibraryHandle hRmLibHandle;
+	char *filename = NULL;
+	void *args = NULL;
+	int error;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	filename = NvOsAlloc(op.length + 1);
+	error = copy_from_user(filename, op.filename, op.length + 1);
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	args = NvOsAlloc(op.argssize);
+	error = copy_from_user(args, op.args, op.argssize);
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	error = NvRmOpen( &hRmDevice, 0 );
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	error = NvRmLoadLibraryEx(hRmDevice, filename, args, op.argssize, op.greedy, &hRmLibHandle);
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	op.handle = hRmLibHandle;
+	error = copy_to_user(arg, &op, sizeof(op));
+
+	NvOsFree(filename);
+	NvOsFree(args);
+	return error;
+}
+
+static int nvfw_ioctl_free_library(struct file *filp, void __user *arg)
+{
+	struct nvfw_load_handle op;
+	NvRmDeviceHandle hRmDevice;
+	int error;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	error = NvRmOpen( &hRmDevice, 0 );
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	error = NvRmFreeLibrary(op.handle);
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	return error;
+}
+
+static int nvfw_ioctl_get_proc_address(struct file *filp, void __user *arg)
+{
+	struct nvfw_get_proc_address_handle op;
+	NvRmDeviceHandle hRmDevice;
+	char *symbolname;
+	int error;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	symbolname = NvOsAlloc(op.length + 1);
+	error = copy_from_user(symbolname, op.symbolname, op.length + 1);
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	error = NvRmOpen( &hRmDevice, 0 );
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	error = NvRmGetProcAddress(op.handle, symbolname, &op.address);
+	if (error) panic("%s: line=%d\n", __func__, __LINE__);
+
+	error = copy_to_user(arg, &op, sizeof(op));
+
+	NvOsFree(symbolname);
+	return error;
+}
+
+static long nvfw_ioctl(struct file *filp,
+	unsigned int cmd, unsigned long arg)
+{
+	int err = 0;
+	void __user *uarg = (void __user *)arg;
+
+	switch (cmd) {
+	case NVFW_IOC_LOAD_LIBRARY:
+		err = nvfw_ioctl_load_library(filp, uarg);
+		break;
+	case NVFW_IOC_LOAD_LIBRARY_EX:
+		err = nvfw_ioctl_load_library_ex(filp, uarg);
+		break;
+	case NVFW_IOC_FREE_LIBRARY:
+		err = nvfw_ioctl_free_library(filp, uarg);
+		break;
+	case NVFW_IOC_GET_PROC_ADDRESS:
+		err = nvfw_ioctl_get_proc_address(filp, uarg);
+		break;
+	default:
+		return -ENOTTY;
+	}
+	return err;
+}
+
+static NvError PrivateOsFopen(
+    const char *filename,
+    NvU32 flags,
+    PrivateOsFileHandle *file)
+{
+    PrivateOsFileHandle hFile;
+
+    hFile = NvOsAlloc(sizeof(PrivateOsFile));
+    if (hFile == NULL)
+        return NvError_InsufficientMemory;
+
+    pr_debug("%s <kernel impl>: file=%s\n", __func__, filename);
+    if (request_firmware(&s_FwEntry, filename, nvfw_dev.this_device) != 0)
+    {
+        pr_err("%s: Cannot read firmware '%s'\n", __func__, filename);
+        return NvError_FileReadFailed;
+    }
+    hFile->pstart = s_FwEntry->data;
+    hFile->pread = s_FwEntry->data;
+    hFile->pend = s_FwEntry->data + s_FwEntry->size;
+
+    *file = hFile;
+
+    return NvError_Success;
+}
+
+static void PrivateOsFclose(PrivateOsFileHandle hFile)
+{
+    release_firmware(s_FwEntry);
+    NV_ASSERT(hFile);
+    NvOsFree(hFile);
+}
+
+NvError NvRmLoadLibrary(
+    NvRmDeviceHandle hDevice,
+    const char *pLibName,
+    void* pArgs,
+    NvU32 sizeOfArgs,
+    NvRmLibraryHandle *hLibHandle)
+{
+    NvError Error = NvSuccess;
+    NV_ASSERT(sizeOfArgs <= MAX_ARGS_SIZE);
+
+    Error = NvRmLoadLibraryEx(hDevice, pLibName, pArgs, sizeOfArgs, NV_FALSE,
+                              hLibHandle);
+    return Error;
+}
+
+NvError NvRmLoadLibraryEx(
+    NvRmDeviceHandle hDevice,
+    const char *pLibName,
+    void* pArgs,
+    NvU32 sizeOfArgs,
+    NvBool IsApproachGreedy,
+    NvRmLibraryHandle *hLibHandle)
+{
+    NvRmLibraryHandle library = NULL;
+    NvError e = NvSuccess;
+    PrivateOsFileHandle hFile = NULL;
+    struct nvmap_handle_ref *staging = NULL;
+    void *loadAddr = NULL;
+    NvU32 len = 0;
+    NvU32 physAddr;
+
+    NV_ASSERT(sizeOfArgs <= MAX_ARGS_SIZE);
+
+    NV_CHECK_ERROR_CLEANUP(NvRmPrivInitAvp(hDevice));
+
+    e = NvRmPrivRPCConnect(s_RPCHandle);
+    if (e != NvSuccess)
+    {
+        NvOsDebugPrintf("RPCConnect timed out during NvRmLoadLibrary\n");
+        goto fail;
+    }
+
+    library = NvOsAlloc(sizeof(*library));
+    if (!library)
+    {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+
+    NV_CHECK_ERROR_CLEANUP(PrivateOsFopen(pLibName, NVOS_OPEN_READ, &hFile));
+    len = (NvU32)hFile->pend - (NvU32)hFile->pstart;
+
+    staging = nvmap_alloc(s_AvpClient, len, L1_CACHE_BYTES,
+                          NVMAP_HANDLE_WRITE_COMBINE);
+    if (IS_ERR(staging)) {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+    loadAddr = nvmap_mmap(staging);
+    if (!loadAddr) {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+    physAddr = nvmap_pin(s_AvpClient, staging);
+    if (IS_ERR((void*)physAddr)) {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+
+    NvOsMemcpy(loadAddr, hFile->pstart, len);
+
+    memcpy(loadAddr, hFile->pstart, len);
+    wmb();
+
+    NV_CHECK_ERROR_CLEANUP(SendMsgAttachModule(library, pArgs, physAddr, len,
+                                               IsApproachGreedy, sizeOfArgs));
+
+fail:
+    if (loadAddr)
+    {
+        if (!IS_ERR((void*)physAddr))
+            nvmap_unpin(s_AvpClient, staging);
+
+        nvmap_munmap(staging, loadAddr);
+    }
+
+    if (!IS_ERR_OR_NULL(staging))
+        nvmap_free(s_AvpClient, staging);
+
+    if (hFile)
+        PrivateOsFclose(hFile);
+
+    if (e != NvSuccess)
+    {
+        NvOsFree(library);
+        library = NULL;
+    }
+
+    *hLibHandle = library;
+    return e;
+}
+
+NvError NvRmGetProcAddress(
+    NvRmLibraryHandle Handle,
+    const char *pSymbol,
+    void **pSymAddress)
+{
+    NvError Error = NvSuccess;
+    NV_ASSERT(Handle);
+    Error = NvRmPrivGetProcAddress(Handle, pSymbol, pSymAddress);
+    return Error;
+}
+
+NvError NvRmFreeLibrary(NvRmLibraryHandle hLibHandle)
+{
+    NvError e = NvSuccess;
+    NV_ASSERT(hLibHandle);
+
+    e = NvRmPrivRPCConnect(s_RPCHandle);
+    if (e != NvSuccess)
+        return e;
+
+    e = SendMsgDetachModule(hLibHandle);
+    if (e != NvSuccess)
+        return e;
+
+    NvOsFree(hLibHandle);
+    return NvSuccess;
+}
+
+//before unloading loading send message to avp with args and entry point via transport
+static NvError SendMsgDetachModule(NvRmLibraryHandle hLibHandle)
+{
+    NvU32 RecvMsgSize;
+    NvRmMessage_DetachModule Msg;
+    NvRmMessage_DetachModuleResponse MsgR;
+
+    Msg.msg = NvRmMsg_DetachModule;
+
+    Msg.msg = NvRmMsg_DetachModule;
+    Msg.reason = NvRmModuleLoaderReason_Detach;
+    Msg.libraryId = hLibHandle->libraryId;
+    RecvMsgSize = sizeof(NvRmMessage_DetachModuleResponse);
+    NvRmPrivRPCSendMsgWithResponse(s_RPCHandle, &MsgR, RecvMsgSize,
+                                   &RecvMsgSize, &Msg, sizeof(Msg));
+
+    return MsgR.error;
+}
+
+//after successful loading send message to avp with args and entry point via transport
+static NvError SendMsgAttachModule(
+    NvRmLibraryHandle hLibHandle,
+    void* pArgs,
+    NvU32 loadAddress,
+    NvU32 fileSize,
+    NvBool greedy,
+    NvU32 sizeOfArgs)
+{
+    NvU32 RecvMsgSize;
+    NvRmMessage_AttachModule Msg;
+    NvRmMessage_AttachModuleResponse MsgR;
+
+    NvOsMemset(&Msg, 0, sizeof(Msg));
+    Msg.msg = NvRmMsg_AttachModule;
+
+    if(pArgs)
+        NvOsMemcpy(Msg.args, pArgs, sizeOfArgs);
+
+    Msg.size = sizeOfArgs;
+    Msg.address = loadAddress;
+    Msg.filesize = fileSize;
+    if (greedy)
+        Msg.reason = NvRmModuleLoaderReason_AttachGreedy;
+    else
+        Msg.reason = NvRmModuleLoaderReason_Attach;
+
+    RecvMsgSize = sizeof(NvRmMessage_AttachModuleResponse);
+
+    NvRmPrivRPCSendMsgWithResponse(s_RPCHandle, &MsgR, RecvMsgSize,
+                                   &RecvMsgSize, &Msg, sizeof(Msg));
+
+    hLibHandle->libraryId = MsgR.libraryId;
+    return MsgR.error;
+}
+
+
+NvError NvRmPrivInitModuleLoaderRPC(NvRmDeviceHandle hDevice)
+{
+    NvError err = NvSuccess;
+
+    if (s_RPCHandle)
+        return NvError_Success;
+
+    NvOsDebugPrintf("%s <kernel impl>: NvRmPrivRPCInit(RPC_AVP_PORT)\n", __func__);
+    err = NvRmPrivRPCInit(hDevice, "RPC_AVP_PORT", &s_RPCHandle);
+    if (err) panic("%s: NvRmPrivRPCInit FAILED\n", __func__);
+
+    return err;
+}
+
+void NvRmPrivDeInitModuleLoaderRPC()
+{
+    NvRmPrivRPCDeInit(s_RPCHandle);
+}
+
+NvError NvRmPrivGetProcAddress(
+    NvRmLibraryHandle Handle,
+    const char *pSymbol,
+    void **pSymAddress)
+{
+    NvRmLibHandle *hHandle = Handle;
+
+    if (hHandle->libraryId == 0)
+        return NvError_SymbolNotFound;
+
+    *pSymAddress = (void *)hHandle->libraryId;
+    return NvSuccess;
+}
+
+static void NvRmPrivResetAvp(NvRmDeviceHandle hRm, unsigned long reset_va)
+{
+    u32 *stub_va = &_tegra_avp_launcher_stub_data[AVP_LAUNCHER_START_VA];
+    unsigned long stub_addr = virt_to_phys(_tegra_avp_launcher_stub);
+    unsigned int tmp;
+    unsigned long timeout;
+
+    *stub_va = reset_va;
+    __cpuc_flush_dcache_area(stub_va, sizeof(*stub_va));
+    outer_clean_range(__pa(stub_va), __pa(stub_va+1));
+
+    tmp = readl(_TEGRA_AVP_RESET_VECTOR_ADDR);
+    writel(stub_addr, _TEGRA_AVP_RESET_VECTOR_ADDR);
+    barrier();
+    NvRmModuleReset(hRm, NvRmModuleID_Avp);
+    writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + FLOW_CTRL_HALT_COP);
+
+    barrier();
+    timeout = jiffies + HZ;
+    /* the AVP firmware will reprogram its reset vector as the kernel
+     * starts, so a dead kernel can be detected by polling this value */
+    while (time_before(jiffies, timeout)) {
+        if (readl(_TEGRA_AVP_RESET_VECTOR_ADDR) != stub_addr)
+            break;
+        cpu_relax();
+    }
+
+    WARN_ON(readl(_TEGRA_AVP_RESET_VECTOR_ADDR) == stub_addr);
+}
+
+void NvRmPrivXpcSendMsgAddress(void);
+
+static NvError NvRmPrivInitAvp(NvRmDeviceHandle hRm)
+{
+    u32 *stub_phys = &_tegra_avp_launcher_stub_data[AVP_LAUNCHER_MMU_PHYSICAL];
+    PrivateOsFileHandle kernel;
+    void *map = NULL;
+    NvError e;
+    NvU32 len;
+    NvU32 phys;
+
+    if (s_KernelImage)
+        return NvSuccess;
+
+    s_AvpClient = nvmap_create_client(nvmap_dev, "nvrm");
+    if (IS_ERR(s_AvpClient)) {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+
+    s_KernelImage = nvmap_alloc(s_AvpClient, SZ_1M, SZ_1M,
+                                NVMAP_HANDLE_WRITE_COMBINE);
+    if (IS_ERR(s_KernelImage)) {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+
+    map = nvmap_mmap(s_KernelImage);
+    if (map == NULL) {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+
+    phys = nvmap_pin(s_AvpClient, s_KernelImage);
+    if (IS_ERR((void *)phys)) {
+        e = NvError_InsufficientMemory;
+        goto fail;
+    }
+
+    NV_CHECK_ERROR_CLEANUP(PrivateOsFopen("nvrm_avp.bin",
+                                          NVOS_OPEN_READ, &kernel));
+
+    memset(map, 0, SZ_1M);
+    len = (NvU32)kernel->pend - (NvU32)kernel->pstart;
+    memcpy(map, kernel->pstart, len);
+    wmb();
+
+    PrivateOsFclose(kernel);
+
+    *stub_phys = phys;
+    __cpuc_flush_dcache_area(stub_phys, sizeof(*stub_phys));
+    outer_clean_range(__pa(stub_phys), __pa(stub_phys+1));
+
+    NvRmPrivResetAvp(hRm, 0x00100000ul);
+
+    NV_CHECK_ERROR_CLEANUP(NvRmPrivInitService(hRm));
+
+    NvRmPrivXpcSendMsgAddress();
+
+    e = NvRmPrivInitModuleLoaderRPC(hRm);
+    if (e != NvSuccess)
+    {
+        NvRmPrivServiceDeInit();
+        goto fail;
+    }
+
+    nvmap_munmap(s_KernelImage, map);
+
+    return NvSuccess;
+
+fail:
+    writel(2 << 29, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + FLOW_CTRL_HALT_COP);
+    if (map)
+    {
+        if (!IS_ERR_OR_NULL((void *)phys))
+            nvmap_unpin(s_AvpClient, s_KernelImage);
+    }
+    if (!IS_ERR_OR_NULL(s_KernelImage))
+        nvmap_free(s_AvpClient, s_KernelImage);
+    if (!IS_ERR_OR_NULL(s_AvpClient))
+        nvmap_client_put(s_AvpClient);
+    s_KernelImage = NULL;
+    s_AvpClient = NULL;
+    return e;
+}
+
+static void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_BASE);
+static void __iomem *iram_backup;
+static dma_addr_t iram_backup_addr;
+static u32 iram_size = TEGRA_IRAM_SIZE;
+static u32 iram_backup_size = TEGRA_IRAM_SIZE + 4;
+static u32 avp_resume_addr;
+
+static NvError NvRmPrivSuspendAvp(NvRmRPCHandle hRPCHandle)
+{
+    NvError err = NvSuccess;
+    NvRmMessage_InitiateLP0 lp0_msg;
+    void *avp_suspend_done = iram_backup + iram_size;
+    unsigned long timeout;
+
+    pr_info("%s()+\n", __func__);
+
+    if (!s_KernelImage)
+        goto done;
+    else if (!iram_backup_addr) {
+        /* XXX: should we return error? */
+        pr_warning("%s: iram backup ram missing, not suspending avp\n",
+                   __func__);
+        goto done;
+    }
+
+    NV_ASSERT(hRPCHandle->svcTransportHandle != NULL);
+
+    lp0_msg.msg = NvRmMsg_InitiateLP0;
+    lp0_msg.sourceAddr = (u32)TEGRA_IRAM_BASE;
+    lp0_msg.bufferAddr = (u32)iram_backup_addr;
+    lp0_msg.bufferSize = (u32)iram_size;
+
+    writel(0, avp_suspend_done);
+
+    NvOsMutexLock(hRPCHandle->RecvLock);
+    err = NvRmTransportSendMsg(hRPCHandle->svcTransportHandle, &lp0_msg,
+                               sizeof(lp0_msg), 1000);
+    NvOsMutexUnlock(hRPCHandle->RecvLock);
+
+    if (err != NvSuccess) {
+        pr_err("%s: cannot send AVP LP0 message\n", __func__);
+        goto done;
+    }
+
+    timeout = jiffies + msecs_to_jiffies(1000);
+    while (!readl(avp_suspend_done) && time_before(jiffies, timeout)) {
+        udelay(10);
+        cpu_relax();
+    }
+
+    if (!readl(avp_suspend_done)) {
+        pr_err("%s: AVP failed to suspend\n", __func__);
+        err = NvError_Timeout;
+        goto done;
+    }
+
+    avp_resume_addr = readl(iram_base);
+    if (!avp_resume_addr) {
+        pr_err("%s: AVP failed to set it's resume address\n", __func__);
+        err = NvError_InvalidState;
+        goto done;
+    }
+
+    pr_info("avp_suspend: resume_addr=%x\n", avp_resume_addr);
+    avp_resume_addr &= 0xFFFFFFFE;
+
+    pr_info("%s()-\n", __func__);
+
+done:
+    return err;
+}
+
+static NvError NvRmPrivResumeAvp(NvRmRPCHandle hRPCHandle)
+{
+    NvError ret = NvSuccess;
+
+    pr_info("%s()+\n", __func__);
+    if (!s_KernelImage || !avp_resume_addr)
+        goto done;
+
+    NvRmPrivResetAvp(hRPCHandle->hRmDevice, avp_resume_addr);
+    avp_resume_addr = 0;
+
+    pr_info("%s()-\n", __func__);
+
+done:
+    return ret;
+}
+
+int __init _avp_suspend_resume_init(void)
+{
+    /* allocate an iram sized chunk of ram to give to the AVP */
+    iram_backup = dma_alloc_coherent(NULL, iram_backup_size,
+                                     &iram_backup_addr, GFP_KERNEL);
+    if (!iram_backup)
+    {
+        pr_err("%s: Unable to allocate iram backup mem\n", __func__);
+        return -ENOMEM;
+    }
+
+    return 0;
+}
+
+static int avp_suspend(struct platform_device *pdev, pm_message_t state)
+{
+        NvError err;
+
+        err = NvRmPrivSuspendAvp(s_RPCHandle);
+        if (err != NvSuccess)
+                return -EIO;
+        return 0;
+}
+
+static int avp_resume(struct platform_device *pdev)
+{
+        NvError err;
+
+        err = NvRmPrivResumeAvp(s_RPCHandle);
+        if (err != NvSuccess)
+                return -EIO;
+        return 0;
+}
+
+static struct platform_driver avp_nvfw_driver = {
+        .suspend = avp_suspend,
+        .resume  = avp_resume,
+        .driver  = {
+                .name  = "nvfw-avp-device",
+                .owner = THIS_MODULE,
+        },
+};
+
+int __init _avp_suspend_resume_init(void);
+
+static int __init nvfw_init(void)
+{
+    int ret = 0;
+    struct platform_device *pdev;
+
+    ret = misc_register(&nvfw_dev);
+    s_KernelImage = NULL;
+    if (ret) panic("%s: misc_register FAILED\n", __func__);
+
+    ret = _avp_suspend_resume_init();
+    if (ret)
+        goto err;
+    pdev = platform_create_bundle(&avp_nvfw_driver, NULL, NULL, 0, NULL, 0);
+    if (!pdev) {
+        pr_err("%s: Can't reg platform driver\n", __func__);
+        ret = -EINVAL;
+        goto err;
+    }
+
+    return 0;
+
+err:
+    return ret;
+}
+
+static void __exit nvfw_deinit(void)
+{
+    misc_deregister(&nvfw_dev);
+}
+
+module_init(nvfw_init);
+module_exit(nvfw_deinit);
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_moduleloader_private.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_moduleloader_private.h
new file mode 100644
index 000000000000..5f607b07e3ac
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_moduleloader_private.h
@@ -0,0 +1,181 @@
+/*
+ * arch/arm/mach-tegra/nvrm/core/common/nvrm_moduleloader_private.h
+ *
+ * AVP firmware module loader
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef INCLUDED_NVRM_MODULELOADER_PRIVATE_H
+#define INCLUDED_NVRM_MODULELOADER_PRIVATE_H
+
+#include "nvrm_moduleloader.h"
+#include "nvrm_memmgr.h"
+
+typedef struct PrivateOsFileRec
+{
+    const NvU8 *pstart;
+    const NvU8 *pread;
+    const NvU8 *pend;
+} PrivateOsFile;
+
+typedef struct PrivateOsFileRec *PrivateOsFileHandle;
+
+#define LOAD_ADDRESS        0x11001000
+#define IRAM_PREF_EXT_ADDRESS   0x50000000
+#define IRAM_MAND_ADDRESS   0x40000000
+#define DRAM_MAND_ADDRESS   0x10000000
+#define DT_ARM_SYMTABSZ     0x70000001
+#define DT_ARM_RESERVED1    0x70000000
+
+/// ELF magic number
+enum
+{
+    ELF_MAG0 = 0x7F
+};
+
+/// ELF section header entry types.
+enum
+{
+    SHT_INIT_ARRAY = 12,             ///< Code initialization array
+    SHT_FINI_ARRAY,             ///< Code finalization array
+    SHT_PREINIT_ARRAY,          ///< Code pre-inialization array
+    SHT_GROUP,                  ///< Group
+    SHT_SYMTAB_SHNDX,           ///< Symbol table index
+};
+#define SHT_LOPROC 0x70000000    ///< Start of processor-specific
+#define SHT_HIPROC 0x7fffffff    ///< End of processor-specific
+#define SHT_LOUSER 0x80000000    ///< Start of application-specific
+#define SHT_HIUSER 0xffffffff     ///< End of application-specific
+
+/// ELF dynamic section type flags
+enum
+{
+    DT_NUM              = 34,           ///< Number used
+};
+
+/// ARM specific relocation codes
+enum
+{
+    R_ARM_RABS32 = 253,
+};
+
+/// A linked list of load segment records
+typedef struct SegmentRec SegmentNode;
+
+struct SegmentRec
+{
+    NvRmMemHandle pLoadRegion;
+    NvU32 LoadAddress;
+    NvU32 Index;
+    NvU32 VirtualAddr;
+    NvU32 MemorySize;
+    NvU32 FileOffset;
+    NvU32 FileSize;
+    void* MapAddr;
+    SegmentNode *Next;
+};
+
+/// ModuleLoader handle structure
+typedef struct NvRmLibraryRec
+{
+    NvU32 libraryId;
+} NvRmLibHandle;
+
+NvError
+NvRmPrivLoadKernelLibrary(NvRmDeviceHandle hDevice,
+                      const char *pLibName,
+                      NvRmLibraryHandle *hLibHandle);
+
+/// Add a load region to the segment list
+SegmentNode* AddToSegmentList(SegmentNode *pList,
+                      NvRmMemHandle pRegion,
+                      Elf32_Phdr Phdr,
+                      NvU32 Idx,
+                      NvU32 PhysAddr,
+                      void* MapAddr);
+
+/// Apply the relocation code based on relocation info from relocation table
+NvError
+ApplyRelocation(SegmentNode *pList,
+                NvU32 FileOffset,
+                NvU32 SegmentOffset,
+                NvRmMemHandle pRegion,
+                const Elf32_Rel *pRel);
+
+/// Get the special section name for a given section type and flag
+NvError
+GetSpecialSectionName(Elf32_Word SectionType,
+                      Elf32_Word SectionFlags,
+                      const char** SpecialSectionName);
+
+/// Parse the dynamic segment of ELF to extract the relocation table
+ NvError
+ParseDynamicSegment(SegmentNode *pList,
+                    const char* pSegmentData,
+                    size_t SegmentSize,
+                    NvU32 DynamicSegmentOffset);
+
+/// Parse ELF library and load the relocated library segments for a given library name
+NvError NvRmPrivLoadLibrary(NvRmDeviceHandle hDevice,
+                                                            const char *Filename,
+                                                            NvU32 Address,
+                                                            NvBool IsApproachGreedy,
+                                                            NvRmLibraryHandle *hLibHandle);
+
+/// Get the symbol address. In phase1, this api will return the entry point address of the module
+NvError
+NvRmPrivGetProcAddress(NvRmLibraryHandle Handle,
+               const char *pSymbol,
+               void **pSymAddress);
+/// Free the ELF library by unloading the library from memory
+NvError NvRmPrivFreeLibrary(NvRmLibHandle *hLibHandle);
+
+NvError NvRmPrivInitModuleLoaderRPC(NvRmDeviceHandle hDevice);
+
+/// Unmap memory segments
+void UnMapRegion(SegmentNode *pList);
+/// Unload segments
+void RemoveRegion(SegmentNode *pList);
+
+void parseElfHeader(Elf32_Ehdr *elf);
+
+NvError
+LoadLoadableProgramSegment(PrivateOsFileHandle elfSourceHandle,
+            NvRmDeviceHandle hDevice,
+            NvRmLibraryHandle hLibHandle,
+            Elf32_Phdr Phdr,
+            Elf32_Ehdr Ehdr,
+            const NvRmHeap * Heaps,
+            NvU32 NumHeaps,
+            NvU32 loop,
+            const char *Filename,
+            SegmentNode **segmentList);
+
+NvError
+parseProgramSegmentHeaders(PrivateOsFileHandle elfSourceHandle,
+            NvU32 segmentHeaderOffset,
+            NvU32 segmentCount);
+
+ NvError
+parseSectionHeaders(PrivateOsFileHandle elfSourceHandle,
+            Elf32_Ehdr *elf);
+
+NvError
+loadSegmentsInFixedMemory(PrivateOsFileHandle elfSourceHandle,
+                        Elf32_Ehdr *elf, NvU32 segmentIndex, void **loadaddress);
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_pinmux_utils.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_pinmux_utils.h
new file mode 100755
index 000000000000..8614aecb5cb3
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_pinmux_utils.h
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef NVRM_PINMUX_UTILS_H
+#define NVRM_PINMUX_UTILS_H
+
+/*
+ * nvrm_pinmux_utils.h defines the pinmux macros to implement for the resource
+ * manager.
+ */
+
+#include "nvcommon.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_drf.h"
+#include "nvassert.h"
+#include "nvrm_hwintf.h"
+#include "nvodm_modules.h"
+
+// This is to disable trisate refcounting.
+#define SKIP_TRISTATE_REFCNT 0
+
+/*  The pin mux code supports run-time trace debugging of all updates to the
+ *  pin mux & tristate registers by embedding strings (cast to NvU32s) into the
+ *  control tables.
+ */
+#define NVRM_PINMUX_DEBUG_FLAG 0
+#define NVRM_PINMUX_SET_OPCODE_SIZE_RANGE 3:1
+
+
+#if NVRM_PINMUX_DEBUG_FLAG
+NV_CT_ASSERT(sizeof(NvU32)==sizeof(const char*));
+#endif
+
+//  The extra strings bloat the size of Set/Unset opcodes
+#define NVRM_PINMUX_SET_OPCODE_SIZE ((NVRM_PINMUX_DEBUG_FLAG)?NVRM_PINMUX_SET_OPCODE_SIZE_RANGE)
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+typedef enum {
+    PinMuxConfig_OpcodeExtend = 0,
+    PinMuxConfig_Set = 1,
+    PinMuxConfig_Unset = 2,
+    PinMuxConfig_BranchLink = 3,
+} PinMuxConfigStates;
+
+typedef enum {
+    PinMuxOpcode_ConfigEnd = 0,
+    PinMuxOpcode_ModuleDone = 1,
+    PinMuxOpcode_SubroutinesDone = 2,
+} PinMuxConfigExtendOpcodes;
+
+//  for extended opcodes, this field is set with the extended opcode
+#define MUX_ENTRY_0_OPCODE_EXTENSION_RANGE 3:2
+//  The state for this entry
+#define MUX_ENTRY_0_STATE_RANGE 1:0
+
+#define MAX_NESTING_DEPTH 4
+
+/*  This macro is used for opcode entries in the tables */
+#define PIN_MUX_OPCODE(_OP_) \
+    (NV_DRF_NUM(MUX,ENTRY,STATE,PinMuxConfig_OpcodeExtend) | \
+     NV_DRF_NUM(MUX,ENTRY,OPCODE_EXTENSION,(_OP_)))
+
+/*  This is a dummy entry in the array which indicates that all setting/unsetting for
+ *  a configuration is complete. */
+#define CONFIGEND() PIN_MUX_OPCODE(PinMuxOpcode_ConfigEnd)
+
+/*  This is a dummy entry in the array which indicates that the last configuration
+ *  for the module instance has been passed. */
+#define MODULEDONE()  PIN_MUX_OPCODE(PinMuxOpcode_ModuleDone)
+
+/*  This is a dummy entry in the array which indicates that all "extra" configurations
+ *  used by sub-routines have been passed. */
+#define SUBROUTINESDONE() PIN_MUX_OPCODE(PinMuxOpcode_SubroutinesDone)
+
+/*  This macro is used to insert a branch-and-link from one configuration to another */
+#define BRANCH(_ADDR_) \
+     (NV_DRF_NUM(MUX,ENTRY,STATE,PinMuxConfig_BranchLink) | \
+      NV_DRF_NUM(MUX,ENTRY,BRANCH_ADDRESS,(_ADDR_)))
+
+/**  RmInitPinMux will program the pin mux settings for all IO controllers to
+  *  the ODM-selected value (or a safe reset value, if no value is defined in
+  *  the ODM query.
+  *  It will also read the current value of the tristate registers, to
+  *  initialize the reference count
+  *
+  * @param hDevice The RM instance
+  * @param First Indicates whether to perform just safe-reset and DVC
+  *     initialization, for early boot, or full initialization
+  */
+void NvRmInitPinMux(
+    NvRmDeviceHandle hDevice,
+    NvBool First);
+
+/**  RmPinMuxConfigSelect sets a specific module to a specific configuration.  It is used
+  *  for multiplexed controllers, and should only be called by modules which support
+  *  multiplexing.  Note that this interface uses the IoModule enumerant, not the RmModule.
+  *
+  *@param hDevice The RM instance
+  *@param IoModule The module to set
+  *@param Instance The instance number of the Module
+  *@param Configuaration The module's configuration to set
+  */
+
+void NvRmPinMuxConfigSelect(
+    NvRmDeviceHandle hDevice,
+    NvOdmIoModule IoModule,
+    NvU32 Instance,
+    NvU32 Configuration);
+
+/** RmPinMuxConfigSetTristate will either enable or disable the tristate for a specific
+  * IO module configuration.  It is used for multiplexed controllers, and should only be
+  * called by modules which support multiplexing.   Note that this interface uses the
+  * IoModule enumerant, not the RmModule.
+  *
+  *@param hDevice The RM instance
+  *@param RMModule The module to set
+  *@param Instance  The instance number of the module.
+  *@param Configuaration The module's configuration to set
+  *@param EnableTristate NV_TRUE will tristate the specified pins, NV_FALSE will un-tristate
+  */
+
+void NvRmPinMuxConfigSetTristate(
+    NvRmDeviceHandle hDevice,
+    NvOdmIoModule IoModule,
+    NvU32 Instance,
+    NvU32 Configuration,
+    NvBool EnableTristate);
+
+/** NvRmSetGpioTristate will either enable or disable the tristate for GPIO ports.
+  * RM client gpio should only call NvRmSetGpioTristate,
+  * which will program the tristate correctly based pins of the particular port.
+  *
+  *@param hDevice The RM instance
+  *@param Port The GPIO port to set
+  *@param Pin The Pinnumber  of the port to set.
+  *@param EnableTristate NV_TRUE will tristate the specified pins, NV_FALSE will un-tristate
+  */
+void NvRmSetGpioTristate(
+    NvRmDeviceHandle hDevice,
+    NvU32 Port,
+    NvU32 Pin,
+    NvBool EnableTristate);
+
+/** NvRmPrivRmModuleToOdmModule will perform the mapping of RM modules to
+ *  ODM modules and instances, using the chip-specific mapping wherever
+ *  necessary */
+NvU32 NvRmPrivRmModuleToOdmModule(
+    NvU32 ChipId,
+    NvU32 RmModule,
+    NvOdmIoModule *pOdmModules,
+    NvU32 *pOdmInstances);
+
+
+//  Forward declarations for all chip-specific helper functions
+NvError NvRmPrivAp15GetModuleInterfaceCaps(
+    NvOdmIoModule Module,
+    NvU32 Instance,
+    NvU32 Config,
+    void* pCaps);
+
+NvError NvRmPrivAp16GetModuleInterfaceCaps(
+    NvOdmIoModule Module,
+    NvU32 Instance,
+    NvU32 Config,
+    void* pCaps);
+
+NvError NvRmPrivAp20GetModuleInterfaceCaps(
+    NvOdmIoModule Module,
+    NvU32 Instance,
+    NvU32 Config,
+    void* pCaps);
+
+const NvU32*** NvRmAp15GetPinMuxConfigs(NvRmDeviceHandle hDevice);
+
+const NvU32*** NvRmAp16GetPinMuxConfigs(NvRmDeviceHandle hDevice);
+
+const NvU32*** NvRmAp20GetPinMuxConfigs(NvRmDeviceHandle hDevice);
+
+NvBool NvRmAp15GetPinGroupForGpio(
+    NvRmDeviceHandle hDevice,
+    NvU32 Port,
+    NvU32 Pin,
+    NvU32 *pMapping);
+
+NvBool NvRmAp20GetPinGroupForGpio(
+    NvRmDeviceHandle hDevice,
+    NvU32 Port,
+    NvU32 Pin,
+    NvU32* pMapping);
+
+void NvRmPrivAp15EnableExternalClockSource(
+   NvRmDeviceHandle hDevice,
+   const NvU32* pModuleProgram,
+   NvU32 Config,
+   NvBool EnableClock);
+
+void NvRmPrivAp20EnableExternalClockSource(
+    NvRmDeviceHandle hDevice,
+    const NvU32* pModuleProgram,
+    NvU32 Config,
+    NvBool EnableClock);
+
+NvU32 NvRmPrivAp15GetExternalClockSourceFreq(
+    NvRmDeviceHandle hDevice,
+    const NvU32* pModuleProgram,
+    NvU32 Config);
+
+NvU32 NvRmPrivAp20GetExternalClockSourceFreq(
+    NvRmDeviceHandle hDevice,
+    const NvU32* pModuleProgram,
+    NvU32 Config);
+
+NvBool NvRmPrivAp15RmModuleToOdmModule(
+    NvRmModuleID ModuleID,
+    NvOdmIoModule* pOdmModules,
+    NvU32* pOdmInstances,
+    NvU32 *pCnt);
+
+NvBool NvRmPrivAp16RmModuleToOdmModule(
+    NvRmModuleID ModuleID,
+    NvOdmIoModule* pOdmModules,
+    NvU32* pOdmInstances,
+    NvU32 *pCnt);
+
+NvBool NvRmPrivAp20RmModuleToOdmModule(
+    NvRmModuleID ModuldID,
+    NvOdmIoModule* pOdmModules,
+    NvU32* pOdmInstances,
+    NvU32 *pCnt);
+
+/**
+ * Chip-specific functions to get SoC strap value for the given strap group.
+ *
+ * @param hDevice The RM instance
+ * @param StrapGroup Strap group to be read.
+ * @pStrapValue A pointer to the returned strap group value.
+ *
+ * @retval NvSuccess if strap value is read successfully
+ * @retval NvError_NotSupported if the specified strap group does not
+ *   exist on the current SoC.
+ */
+NvError
+NvRmAp15GetStraps(
+    NvRmDeviceHandle hDevice,
+    NvRmStrapGroup StrapGroup,
+    NvU32* pStrapValue);
+
+NvError
+NvRmAp20GetStraps(
+    NvRmDeviceHandle hDevice,
+    NvRmStrapGroup StrapGroup,
+    NvU32* pStrapValue);
+
+void NvRmPrivAp15SetPadTristates(
+    NvRmDeviceHandle hDevice,
+    const NvU32* Module,
+    NvU32 Config,
+    NvBool EnableTristate);
+
+void NvRmPrivAp15SetPinMuxCtl(
+    NvRmDeviceHandle hDevice,
+    const NvU32* Module,
+    NvU32 Config);
+
+void NvRmPrivAp15InitTrisateRefCount(NvRmDeviceHandle hDevice);
+
+const NvU32*
+NvRmPrivAp15FindConfigStart(
+    const NvU32* Instance,
+    NvU32 Config,
+    NvU32 EndMarker);
+
+void
+NvRmPrivAp15SetGpioTristate(
+    NvRmDeviceHandle hDevice,
+    NvU32 Port,
+    NvU32 Pin,
+    NvBool EnableTristate);
+
+void NvRmAp15SetDefaultTristate (NvRmDeviceHandle hDevice);
+
+void NvRmAp20SetDefaultTristate (NvRmDeviceHandle hDevice);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // NVRM_PINMUX_UTILS_H
+
+
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_pmu_private.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_pmu_private.h
new file mode 100644
index 000000000000..79c818d21838
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_pmu_private.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_PMU_PRIVATE_H
+#define INCLUDED_NVRM_PMU_PRIVATE_H
+
+#include "nvodm_query.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+// CPU rail lowering voltage delay (applicable only to the platforms
+// with dedicated CPU rail)
+#define NVRM_CPU_TO_CORE_DOWN_US (2000)
+
+// Default voltage returned in environment with no PMU support
+#define NVRM_NO_PMU_DEFAULT_VOLTAGE (1)
+
+/**
+ * Initializes RM PMU interface handle
+ *
+ * @param hRmDevice The RM device handle
+ * 
+ * @return NvSuccess if initialization completed successfully
+ *  or one of common error codes on failure
+ */
+NvError
+NvRmPrivPmuInit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Enables PMU interrupt.
+ *
+ * @param hRmDevice The RM device handle
+ */
+void NvRmPrivPmuInterruptEnable(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Masks/Unmasks OMU interrupt
+ * 
+ * @param hRmDevice The RM device handle
+ * @param mask Set NV_TRUE to maks, and NV_FALSE to unmask PMU interrupt
+ */
+void NvRmPrivPmuInterruptMask(NvRmDeviceHandle hRmDevice, NvBool mask);
+
+/**
+ * Deinitializes RM PMU interface
+ *
+ * @param hRmDevice The RM device handle
+ */
+void
+NvRmPrivPmuDeinit(NvRmDeviceHandle hRmDevice);
+
+/**
+ * Sets new voltage level for the specified PMU voltage rail.
+ * Private interface for diagnostic mode only.
+ *
+ * @param hDevice The Rm device handle.
+ * @param vddId The ODM-defined PMU rail ID.
+ * @param MilliVolts The new voltage level to be set in millivolts (mV).
+ *  Set to ODM_VOLTAGE_OFF to turn off the target voltage.
+ * @param pSettleMicroSeconds A pointer to the settling time in microseconds (uS),
+ *  which is the time for supply voltage to settle after this function 
+ *  returns; this may or may not include PMU control interface transaction time, 
+ *  depending on the ODM implementation. If null this parameter is ignored.
+ * 
+ * @return NV_TRUE if successful, or NV_FALSE otherwise. 
+ */
+NvBool
+NvRmPrivDiagPmuSetVoltage( 
+    NvRmDeviceHandle hDevice,
+    NvU32 vddId,
+    NvU32 MilliVolts,
+    NvU32 * pSettleMicroSeconds);
+
+/**
+ * Turns PMU rail On/Off
+ *
+ * @param hRmDevice The RM device handle
+ * @param NvRailId The reserved NV rail GUID
+ * @param TurnOn Turn rail ON if True, or turn  rail Off if False
+ */
+void
+NvRmPrivPmuRailControl(
+    NvRmDeviceHandle hRmDevice,
+    NvU64 NvRailId,
+    NvBool TurnOn);
+
+/**
+ * Gets PMU rail voltage
+ *
+ * @param hRmDevice The RM device handle
+ * @param NvRailId The reserved NV rail GUID
+ * 
+ * @return PMU rail voltage in mv
+ */
+NvU32
+NvRmPrivPmuRailGetVoltage(
+    NvRmDeviceHandle hRmDevice,
+    NvU64 NvRailId);
+
+//  Forward declarations for all chip-specific helper functions
+
+/**
+ * Sets polarity of dedicated SoC PMU interrupt input
+ *
+ * @param hRmDevice The RM device handle
+ * @param Polarity PMU interrupt polarity to be set
+ */
+void
+NvRmPrivAp20SetPmuIrqPolarity(
+    NvRmDeviceHandle hRmDevice,
+    NvOdmInterruptPolarity Polarity);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_PMU_PRIVATE_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_power.c b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_power.c
new file mode 100644
index 000000000000..fd93eb66ea37
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_power.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/delay.h>
+
+#include <mach/iomap.h>
+
+#include "nvcommon.h"
+#include "nvrm_power.h"
+#include "../../../../clock.h"
+
+#define is_vcp(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Vcp)
+
+#define is_bsea(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_BseA)
+
+#define is_vde(_mod) (NVRM_MODULE_ID_MODULE(_mod)==NvRmModuleID_Vde)
+
+#define CLK_VI_CORE_EXTERNAL (1<<24)
+#define CLK_VI_PAD_INTERNAL (1<<25)
+
+NvError NvRmPowerModuleClockConfig(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvRmFreqKHz MinFreq,
+    NvRmFreqKHz MaxFreq,
+    const NvRmFreqKHz *PrefFreqList,
+    NvU32 PrefFreqListCount,
+    NvRmFreqKHz *CurrentFreq,
+    NvU32 flags)
+{
+    if (CurrentFreq)
+        *CurrentFreq = 0;
+
+    return NvSuccess;
+}
+
+NvError NvRmPowerModuleClockControl(
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvBool Enable)
+{
+    const char *vcp_names[] = { "vcp", NULL };
+    const char *bsea_names[] = { "bsea", NULL };
+    const char *vde_names[] = { "vde", NULL };
+    const char **names = NULL;
+
+    if (is_vcp(ModuleId))
+        names = vcp_names;
+    else if (is_bsea(ModuleId))
+        names = bsea_names;
+    else if (is_vde(ModuleId))
+        names = vde_names;
+
+    if (!names) {
+        pr_err("%s: MOD[%lu] INST[%lu] not supported\n", __func__,
+               NVRM_MODULE_ID_MODULE(ModuleId),
+               NVRM_MODULE_ID_INSTANCE(ModuleId));
+        return NvError_BadParameter;
+    }
+
+    for ( ; *names ; names++) {
+        struct clk *clk = clk_get_sys(*names, NULL);
+
+        if (IS_ERR_OR_NULL(clk)) {
+            pr_err("%s: unable to get struct clk for %s\n", __func__, *names);
+            continue;
+        }
+
+        if (Enable)
+            clk_enable(clk);
+        else
+            clk_disable(clk);
+    }
+
+    return NvSuccess;
+}
+
+NvError NvRmPowerVoltageControl( 
+    NvRmDeviceHandle hRmDeviceHandle,
+    NvRmModuleID ModuleId,
+    NvU32 ClientId,
+    NvRmMilliVolts MinVolts,
+    NvRmMilliVolts MaxVolts,
+    const NvRmMilliVolts * PrefVoltageList,
+    NvU32 PrefVoltageListCount,
+    NvRmMilliVolts * CurrentVolts)
+{
+    return NvSuccess;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_power_dfs.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_power_dfs.h
new file mode 100644
index 000000000000..65137c83a8ce
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_power_dfs.h
@@ -0,0 +1,576 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** 
+ * @file
+ * @brief <b>nVIDIA Driver Development Kit: 
+ *           Power Resource manager </b>
+ *
+ * @b Description: NvRM DFS manager definitions. 
+ * 
+ */
+
+#ifndef INCLUDED_NVRM_POWER_DFS_H
+#define INCLUDED_NVRM_POWER_DFS_H
+
+#include "nvrm_power_private.h"
+#include "nvrm_clocks.h"
+#include "nvrm_interrupt.h"
+#include "nvodm_tmon.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+/**
+ * Sampling window definitions:
+ * - minimum and maximum sampling interval in ms
+ * - maximum number of intervals in the sampling window
+ * (always defined as power of 2 to simplify calculations)
+ */
+#define NVRM_DFS_MIN_SAMPLE_MS (10)
+#define NVRM_DFS_MAX_SAMPLE_MS (20)
+
+#define NVRM_DFS_MAX_SAMPLES_LOG2 (7)
+#define NVRM_DFS_MAX_SAMPLES (0x1 << NVRM_DFS_MAX_SAMPLES_LOG2)
+
+/// Specifies that CPU idle monitor readings should be explicitly offset
+///  by time spent in LP2
+#define NVRM_CPU_IDLE_LP2_OFFSET (1)
+
+/// Number of bits in the fractional part of boost koefficients
+#define BOOST_FRACTION_BITS (8)
+
+/*****************************************************************************/
+
+/// Enumerates synchronous busy hints states
+typedef enum
+{
+    NvRmDfsBusySyncState_Idle = 0,
+    NvRmDfsBusySyncState_Signal,
+    NvRmDfsBusySyncState_Execute,
+
+    NvRmDfsBusySyncState_Num,
+    NvRmDfsBusySyncState_Force32 = 0x7FFFFFFF
+} NvRmDfsBusySyncState;
+
+/// Enumerates DFS modules = modules, which include activity monitors for clock
+/// domains controlled by DFS
+typedef enum
+{
+    // Specifies system statistic module - includes activity monitors
+    // for CPU, AVP, AHB, and APB clock domains
+    NvRmDfsModuleId_Systat = 1,
+
+    // Specifies VDE module - includes activity monitor
+    // for video-pipe clock domain
+    NvRmDfsModuleId_Vde,
+
+    // Specifies EMC module - includes activity monitor
+    // for EMC 1x clock domain
+    NvRmDfsModuleId_Emc,
+
+    NvRmDfsModuleId_Num,
+    NvRmDfsModuleId_Force32 = 0x7FFFFFFF
+} NvRmDfsModuleId;
+
+/**
+ * Combines idle count readings from DFS activity monitors during current
+ * sample interval
+ */
+typedef struct NvRmDfsIdleDataRec
+{
+    // Current Sample interval in ms
+    NvU32 CurrentIntervalMs;
+
+    // Data readings from DFS activity monitors
+    NvU32 Readings[NvRmDfsClockId_Num];
+
+    // Time spent in LP2 in ms
+    NvU32 Lp2TimeMs;
+} NvRmDfsIdleData;
+
+/**
+ *  DFS module access function pointers
+ */
+typedef struct NvRmDfsRec* NvRmDfsPtr;
+typedef const struct NvRmDfsRec* NvRmConstDfsPtr;
+typedef NvError (*FuncPtrModuleMonitorsInit)(NvRmDfsPtr pDfs);
+typedef void (*FuncPtrModuleMonitorsDeinit)(NvRmDfsPtr pDfs);
+
+typedef void
+(*FuncPtrModuleMonitorsStart)(
+    NvRmConstDfsPtr pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    const NvU32 IntevalMs);
+
+typedef void
+(*FuncPtrModuleMonitorsRead)(
+    NvRmConstDfsPtr pDfs,
+    const NvRmDfsFrequencies* pDfsKHz,
+    NvRmDfsIdleData* pIdleData);
+
+/**
+ * Combines capabilities, access function pointers, and base virtual
+ * addresses of the DFS module
+ */
+typedef struct NvRmDfsModuleRec
+{
+    // Clock domains monitored by this module 
+    NvBool DomainMap[NvRmDfsClockId_Num];
+
+    // Pointer to the function that initializes module activity monitors
+    // (null if module is not present)
+    FuncPtrModuleMonitorsInit Init;
+
+    // Pointer to the function that de-initializes module activity monitors
+    // (null if module is not present)
+    FuncPtrModuleMonitorsDeinit Deinit;
+
+    // Pointer to the function that starts module activity monitors
+    // (null if module is not present)
+    FuncPtrModuleMonitorsStart Start;
+
+    // Pointer to the function that reads module activity monitors
+    // (null if module is not present)
+    FuncPtrModuleMonitorsRead Read;
+
+    // Monitor readouts scale and offset (usage and interpretation may differ
+    // for different monitors)
+    NvU32 Scale;
+    NvU32 Offset;
+
+    // Base virtual address for module registers
+    void* pBaseReg;
+} NvRmDfsModule;
+
+/*****************************************************************************/
+
+/**
+ * Combines DFS starvation control parameters
+ */
+typedef struct NvRmDfsStarveParamRec
+{
+    // Fixed increase in frequency boost for a sample interval the clock
+    // consumer is starving: new boost = old boost +  BoostStepKHz
+    NvRmFreqKHz BoostStepKHz;
+
+    // Proportional increase in frequency boost for a sample interval the
+    // clock consumer is starving (scaled in 0-255 range):
+    // new boost = old boost + old boost * BoostIncKoef / 256
+    NvU8 BoostIncKoef;
+
+    // Proportional decrease in frequency boost for a sample interval the
+    // clock consumer is not starving (scaled in 0-255 range):
+    // new boost = old boost - old boost * BoostDecKoef / 256
+    NvU8 BoostDecKoef;
+} NvRmDfsStarveParam;
+
+
+/**
+ * Combines scaling algorithm parameters for DFS controlled clock domain
+ */
+typedef struct NvRmDfsParamRec
+{
+    // Maximum domain clock frequency
+    NvRmFreqKHz MaxKHz;
+    // Minimum domain clock frequency
+    NvRmFreqKHz MinKHz;
+
+    // Minimum average activity change in upward direction recognized by DFS
+    NvRmFreqKHz UpperBandKHz;
+    // Minimum average activity change in downward direction recognized by DFS
+    NvRmFreqKHz LowerBandKHz;
+
+    // Control parameters for real time starvation reported by the DFS client
+    NvRmDfsStarveParam RtStarveParam;
+
+    // Control parameters for non real time starvation detected by DFS itself
+    NvRmDfsStarveParam NrtStarveParam;
+
+    // Relative adjustment up of average activity applied by DFS:
+    // adjusted frequency = measured average activity * (1 + 2^(-RelAdjustBits))
+    NvU8 RelAdjustBits;
+
+    // Minimum number of sample intervals in a row with non-realtime starvation
+    // that triggers frequency boost (0 = boost trigger on the 1st NRT interval)
+    NvU8 MinNrtSamples;
+
+    // Minimum number of idle cycles in the sample interval required to avoid
+    // non-realtime starvation
+    NvU32 MinNrtIdleCycles;
+} NvRmDfsParam;
+
+/**
+ * Combines sampling statistic and starvation controls for DFS clock domain
+ */
+typedef struct NvRmDfsSamplerRec
+{
+    // Domain clock id
+    NvRmDfsClockId ClockId;
+
+    // Activity monitor present indicator (domain is still controlled by DFS
+    // even if no activity monitor present)
+    NvBool MonitorPresent;
+
+    // Circular buffer of active cycles per sample interval within the
+    // sampling window
+    NvU32 Cycles[NVRM_DFS_MAX_SAMPLES];
+
+    // Pointer to the last ("recent") sample in the sampling window
+    NvU32* pLastSample;
+
+    // Total number of active cycles in the sampling window
+    NvU64 TotalActiveCycles;
+
+    // Measured average clock activity frequency over the sampling window
+    NvRmFreqKHz AverageKHz;
+
+    // Average clock frequency adjusted up by DFS
+    NvRmFreqKHz BumpedAverageKHz;
+
+    // Non-real time starving sample counter
+    NvU32 NrtSampleCounter;
+
+    // Non-real time starvation boost 
+    NvRmFreqKHz NrtStarveBoostKHz;
+
+    // Real time starvation boost 
+    NvRmFreqKHz RtStarveBoostKHz;
+
+    // Busy pulse mode indicator - if true, busy boost is completely removed
+    // after busy time has expired; if false, DFS averaging mechanism is used
+    // to gradually lower frequency after busy boost
+    NvBool BusyPulseMode;
+
+    // Cumulative number of cycles since log start
+    NvU64 CumulativeLogCycles;
+} NvRmDfsSampler;
+
+/**
+ * Holds information for DFS moving sampling window
+ */
+typedef struct NvRmDfsSampleWindowRec
+{
+    // Minimum sampling interval
+    NvU32 MinIntervalMs;
+
+    // Maximum sampling interval
+    NvU32 MaxIntervalMs;
+
+    // Next sample interval
+    NvU32 NextIntervalMs;
+
+    // Circular buffer of sample intervals in the sampling window
+    NvU32 IntervalsMs[NVRM_DFS_MAX_SAMPLES];
+
+    // Pointer to the last ("recent") sample unterval in the sampling window
+    NvU32* pLastInterval;
+
+    // Cumulative width of the sampling window
+    NvU32 SampleWindowMs;
+
+    // Last busy hints check time stamp
+    NvU32 BusyCheckLastUs;
+
+    // Delay before busy hints next check
+    NvU32 BusyCheckDelayUs;
+
+    // Free running sample counter
+    NvU32 SampleCnt;
+
+    // Cumulative DFS time since log start
+    NvU32 CumulativeLogMs;
+
+    // Cumulative LP2 statistic since log start
+    NvU32 CumulativeLp2TimeMs;
+    NvU32 CumulativeLp2Entries;
+} NvRmDfsSampleWindow;
+
+/*****************************************************************************/
+
+/**
+ * Holds voltage corner for DFS domains and non-DFS modules. Each voltage
+ * corner field specifies minimum core voltage required to run the respective
+ * device(s) at current clock frequency.
+ */
+typedef struct NvRmDvsCornerRec
+{
+    // CPU voltage requirements
+    NvRmMilliVolts CpuMv;
+
+    // AVP/System voltage requirements
+    NvRmMilliVolts SystemMv;
+
+    // EMC / DDR voltage requirements
+    NvRmMilliVolts EmcMv;
+
+    // Cumulative voltage requirements for non-DFS modules
+    NvRmMilliVolts ModulesMv;
+} NvRmDvsCorner;
+
+/**
+ * Combines voltage threshold and core rail status and control information
+ */
+typedef struct NvRmDvsRec
+{
+    // Current DVS voltage thresholds
+    NvRmDvsCorner DvsCorner;
+
+    // RTC (AO) rail address (PMU voltage id)
+    NvU32 RtcRailAddress;
+
+    // Core rail address (PMU voltage id)
+    NvU32 CoreRailAddress;
+
+    // Current core rail voltage
+    NvRmMilliVolts CurrentCoreMv;
+
+    // Nominal core rail voltage
+    NvRmMilliVolts NominalCoreMv;
+
+    // Minimum core rail voltage
+    NvRmMilliVolts MinCoreMv;
+
+    // Low corner voltage for core rail loaded by DVS control API
+    NvRmMilliVolts LowCornerCoreMv;
+
+    // Dedicated Cpu rail address (PMU voltage id)
+    NvU32 CpuRailAddress;
+
+    // Current dedicated CPU rail voltage
+    NvRmMilliVolts CurrentCpuMv;
+
+    // Nominal dedicated CPU rail voltage
+    NvRmMilliVolts NominalCpuMv;
+
+    // Minimum dedicated CPU rail voltage
+    NvRmMilliVolts MinCpuMv;
+
+    // Low corner voltage for CPU rail loaded by DVS control API
+    NvRmMilliVolts LowCornerCpuMv;
+
+    // OTP (default) dedicated CPU rail voltage
+    NvRmMilliVolts CpuOTPMv;
+
+    // Specifies whether or not CPU voltage will switch back to OTP
+    // (default) value after CPU request On-Off-On transition
+    NvBool  VCpuOTPOnWakeup;
+
+    // RAM timing SVOP controls low voltage threshold
+    NvRmMilliVolts LowSvopThresholdMv;
+
+    // RAM timing SVOP controls low voltage setting
+    NvU32 LowSvopSettings;
+
+    // RAM timing SVOP controls high voltage setting
+    NvU32 HighSvopSettings;
+
+    // Request core voltage update
+    volatile NvBool UpdateFlag;
+
+    // Stop voltage scaling flag
+    volatile NvBool StopFlag;
+
+    // CPU LP2 state indicator (used on platforms with dedicated CPU rail that
+    // returns to default setting by PMU underneath DVFS on every LP2 exit)
+    volatile NvBool Lp2SyncOTPFlag;
+} NvRmDvs;
+
+/**
+ * RM thermal zone policy
+ */
+typedef struct NvRmTzonePolicyRec
+{
+    // Request policy update
+    volatile NvBool UpdateFlag;
+
+    // Last policy update request time stamp
+    NvU32 TimeUs;
+
+    // Update period (NV_WAIT_INFINITE is allowed in interrupt mode) 
+    NvU32 UpdateIntervalUs;
+
+    // Out of limit interrupt boundaries
+    NvS32 LowLimit;
+    NvS32 HighLimit;
+
+    // Policy range
+    NvU32 PolicyRange;
+} NvRmTzonePolicy;
+
+/**
+ * Combines status and control information for dynamic thermal throttling
+ */
+typedef struct NvRmDttRec
+{
+    // SoC core temperature monitor (TMON) handle
+    NvOdmTmonDeviceHandle hOdmTcore;
+
+    // Core TMON out-of-limit-interrupt handle
+    NvOdmTmonIntrHandle hOdmTcoreIntr;
+
+    // Core TMON capabilities
+    NvOdmTmonCapabilities TcoreCaps;
+
+    // Out of limit interrupt cpabilities for low limit
+    NvOdmTmonParameterCaps TcoreLowLimitCaps;
+
+    // Out-of-limit interrupt cpabilities for high limit
+    NvOdmTmonParameterCaps TcoreHighLimitCaps;
+
+    // Core zone policy
+    NvRmTzonePolicy TcorePolicy;
+
+    // Core temperature
+    NvS32 CoreTemperatureC;
+
+    // Specifies if out-of-limit interrupt is used for temperature update
+    volatile NvBool UseIntr;
+} NvRmDtt;
+
+/*****************************************************************************/
+
+/**
+ * Combines DFS status and control information
+ */
+typedef struct NvRmDfsRec
+{
+    // RM Device handle
+    NvRmDeviceHandle hRm;
+
+    // DFS state variable
+    NvRmDfsRunState DfsRunState;
+
+    // DFS state saved on system suspend entry
+    NvRmDfsRunState DfsLPxSavedState;
+
+    // ID assigned to DFS by RM Power Manager
+    NvU32 PowerClientId;
+
+    // DFS low power corner hit status - true, when all domains (with
+    // possible exception of CPU) are running at minimum frequency
+    NvBool LowCornerHit;
+
+    // Request to report low corner hit status to OS adaptation layer; DFS
+    // interrupt will not wake CPU if it is power gated and low corner is hit
+    NvBool LowCornerReport;
+
+    // PM thread request for CPU state control
+    NvRmPmRequest PmRequest;
+
+    // DFS IRQ number
+    NvU16 IrqNumber;
+
+    // DFS mutex for safe data access by DFS ISR,
+    // clock control thread, and API threads
+    NvOsIntrMutexHandle hIntrMutex;
+
+    // DFS mutex for synchronous busy hints
+    NvOsMutexHandle hSyncBusyMutex;
+
+    // DFS semaphore for synchronous busy hints
+    NvOsSemaphoreHandle hSyncBusySemaphore;
+
+    // Synchronous busy hints state
+    volatile NvRmDfsBusySyncState BusySyncState;
+
+    // Clock control execution thread init indicator
+    volatile NvBool InitializedThread;
+
+    // Clock control execution thread abort indicator
+    volatile NvBool AbortThread;
+
+    // DFS semaphore for sampling interrupt and wake event signaling
+    NvOsSemaphoreHandle hSemaphore;
+
+    // DFS Modules
+    NvRmDfsModule Modules[NvRmDfsModuleId_Num];
+
+    // DFS algorithm parameters 
+    NvRmDfsParam DfsParameters[NvRmDfsClockId_Num];
+
+    // DFS Samplers
+    NvRmDfsSampler Samplers[NvRmDfsClockId_Num];
+
+    // DFS sampling window
+    NvRmDfsSampleWindow SamplingWindow;
+
+    // Maximum DFS domains frequencies (shortcut to the respective parameters)
+    NvRmDfsFrequencies MaxKHz;
+
+    // Target DFS doamins frequencies: output of the DFS algorithm,
+    // input to clock control
+    NvRmDfsFrequencies TargetKHz;
+
+    // Current DFS domains frequencies: output from clock control, input
+    // to DFS algorithm
+    NvRmDfsFrequencies CurrentKHz;
+
+    // DFS domains frequencies set on entry to suspend state
+    NvRmDfsFrequencies SuspendKHz;
+
+    // Busy boost frequencies requested by Busy load API
+    NvRmDfsFrequencies BusyKHz;
+
+    // Low corner frequencies loaded by DFS control API
+    NvRmDfsFrequencies LowCornerKHz;
+
+    // High corner frequencies loaded by DFS control API
+    NvRmDfsFrequencies HighCornerKHz;
+
+    // A shadow of CPU corners (updated by APIs that directly set CPU corners,
+    // preserved when CPU corners are indirectly throttled by EMC envelope)
+    NvRmModuleClockLimits CpuCornersShadow;
+
+    // CPU envelope API indicator (if set supercedes low/high corner APIs)
+    NvBool CpuEnvelopeSet;
+
+    // EMC envelope API indicator (if set supercedes low/high corner APIs)
+    NvBool EmcEnvelopeSet;
+
+    // Voltage Scaler
+    NvRmDvs VoltageScaler;
+
+    // Thermal throttler
+    NvRmDtt ThermalThrottler;
+
+    // nvos interrupt handle for DVS 
+    NvOsInterruptHandle DfsInterruptHandle;
+} NvRmDfs;
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_POWER_DFS_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_priv_ap_general.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_priv_ap_general.h
new file mode 100644
index 000000000000..ded480bdb41d
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_priv_ap_general.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+ /** @file
+  *
+  * @b Description: Contains the maximum instance of the controller on soc.
+  * Must be >= the max of all chips.
+  */
+
+#ifndef INCLUDED_NVRM_PRIV_AP_GENERAL_H
+#define INCLUDED_NVRM_PRIV_AP_GENERAL_H
+
+
+// Dma specific definitions for latest SOC
+
+// Maximum number of DMA channels available on SOC.
+#define MAX_APB_DMA_CHANNELS        32
+
+
+// SPI specific definitions for latest SOC
+#define MAX_SPI_CONTROLLERS         8
+
+#define MAX_SLINK_CONTROLLERS       8
+
+
+// I2C specific definitions for latest soc
+#define MAX_I2C_CONTROLLERS         3
+
+#define MAX_DVC_CONTROLLERS         1
+
+#endif // INCLUDED_NVRM_PRIV_AP_GENERAL_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_processor.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_processor.h
new file mode 100644
index 000000000000..48c8f57e9f64
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_processor.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_PROCESSOR_H
+#define INCLUDED_NVRM_PROCESSOR_H
+
+#include "nvcommon.h"
+
+#ifdef  __cplusplus
+extern "C" {
+#endif
+
+
+//==========================================================================
+//  ARM CPSR/SPSR definitions
+//==========================================================================
+
+#define PSR_MODE_MASK   0x1F
+#define PSR_MODE_USR    0x10
+#define PSR_MODE_FIQ    0x11
+#define PSR_MODE_IRQ    0x12
+#define PSR_MODE_SVC    0x13
+#define PSR_MODE_ABT    0x17
+#define PSR_MODE_UND    0x1B
+#define PSR_MODE_SYS    0x1F    // only available on ARM Arch. v4 and higher
+#define PSR_MODE_MON    0x16    // only available on ARM Arch. v6 and higher with TrustZone extension
+
+
+//==========================================================================
+// Compiler-independent abstraction macros.
+//==========================================================================
+
+#define IS_USER_MODE(cpsr)  ((cpsr & PSR_MODE_MASK) == PSR_MODE_USR)
+
+//==========================================================================
+// Compiler-specific instruction abstraction macros.
+//==========================================================================
+
+#if defined(__arm__) && !defined(__thumb__)  // ARM compiler compiling ARM code
+
+    #if (__GNUC__) // GCC inline assembly syntax
+
+    static NV_INLINE NvU32
+    CountLeadingZeros(NvU32 x)
+    {
+        NvU32 count;
+        __asm__ __volatile__ (      \
+                "clz %0, %1 \r\t"   \
+                :"=r"(count)        \
+                :"r"(x));
+        return count;
+    }
+
+    #define GET_CPSR(x) __asm__ __volatile__ (          \
+                                "mrs %0, cpsr\r\t"     \
+                                : "=r"(x))
+
+    #else   // assume RVDS compiler
+    /*
+     *  @brief Macro to abstract retrieval of the current processor 
+     *  status register (CPSR) value.
+     *  @param x is a variable of type NvU32 that will receive 
+     *  the CPSR value.
+     */
+    #define GET_CPSR(x) __asm { MRS x, CPSR }           // x = CPSR
+    
+    static NV_INLINE NvU32
+    CountLeadingZeros(NvU32 x)
+    {
+        NvU32 count;
+        __asm { CLZ count, x }
+        return count;
+    }
+
+    #endif
+#else
+    /*
+     *  @brief Macro to abstract retrieval of the current processor status register (CPSR) value.
+     *  @param x is a variable of type NvU32 that will receive the CPSR value.
+    */
+    #define GET_CPSR(x) (x = PSR_MODE_USR)  // Always assume USER mode for now
+
+    // If no built-in method for counting leading zeros do it the less efficient way.
+    static NV_INLINE NvU32 
+    CountLeadingZeros(NvU32 x)
+    {
+        NvU32   i;
+
+        if (x)
+        {
+            i = 0;
+
+            do
+            {
+                if (x & 0x80000000)
+                {
+                    break;
+                }
+                x <<= 1;
+            } while (++i < 32);
+        }
+        else
+        {
+            i = 32;
+        }
+
+        return i;
+    }
+
+#endif
+
+#ifdef  __cplusplus
+}
+#endif
+
+#endif // INCLUDED_NVRM_PROCESSOR_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_relocation_table.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_relocation_table.h
new file mode 100644
index 000000000000..04b4eacc550b
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_relocation_table.h
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_RELOCATION_TABLE_H
+#define INCLUDED_NVRM_RELOCATION_TABLE_H
+
+#include "nvcommon.h"
+#include "nvrm_init.h"
+
+/**
+ * The AP family supports a Relocation Table which lists the devices in the
+ * system, their version numbers, and their physical base addressess and
+ * aperture size.  Interrupt information is also stored in the table.
+ *
+ * The relcation table format:
+ *
+ * +-------------------( 32 bits )-------------------------------------+
+ * |                    table version                                  |
+ * +-------------------------------------------------------------------+
+ * |               [ device table entries ]                            |
+ * +-------------------------------------------------------------------+
+ * |                    null (0)                                       |
+ * +-------------------------------------------------------------------+
+ * |                [ irq table entries ]                              |
+ * +-------------------------------------------------------------------+
+ * |                    null (0)                                       |
+ * +-------------------------------------------------------------------+
+ *
+ * The device table entry format:
+ *
+ * +-------------------( 32 bits )-------------------------------------+
+ * | id [31:16] | major [15:12] | minor [11:8] | res [7:4] | bar [3:0] |
+ * |-------------------------------------------------------------------|
+ * |                    start address                                  |
+ * |-------------------------------------------------------------------|
+ * |                    length                                         |
+ * +-------------------------------------------------------------------+
+ *
+ * The irq entry format:
+ *
+ * +-------------------( 32 bits )-----------------------------------------+
+ * |V[31]|rsvd[30:29]|IntDevIdx[28:20]|rsvd[19:17]|DevIdx[16:8]|IntNum[7:0]|
+ * +-----------------------------------------------------------------------+
+ *
+ * Every entry (whether valid or not) will always contain an Interrupt
+ * Controller Device Index (IntDevIdx), a Device Index (DevIdx), and an
+ * Interrupt Number (IntNum) value. Whether or not that entry actually
+ * corresponds to an interrupt source is determined by the valid (V) bit.
+ * If the valid bit is 1, the interrupt number corresponds to an actual
+ * interrupt source. If the valid bit is zero, this entry represents an
+ * interrupt source that was present in a prior SOC but that is no longer
+ * used. The slot for that interrupt in the interrupt map table must be
+ * preseved because "indexed" interrupts are determined positionally.
+ * Removal of an interrupt would change the positional assignment of all
+ * following interrupt numbers and would break forward compatibility.
+ */
+
+#define NVRM_DEVICE_UNKNOWN     ((NvU32)-2)
+#define NVRM_DEVICE_ERROR       ((NvU32)-3)
+
+// The module index in the NvRmModule table is invalid; this is not an error.
+#define NVRM_MODULE_INVALID     (0xFFFF)
+
+// Number of interrupt controllers
+#define NVRM_MAX_MAIN_INTR_CTLRS    5
+
+// Number of DMA transmit interrupt controllers
+#define NVRM_MAX_DRQ_INTR_CTLRS     2
+
+// Number of Arbitration Grant interrupt controllers
+#define NVRM_ARB_GNT_INTR_CTLRS     1
+
+// Number of interrupt controllers of all types
+#define NVRM_MAX_INTERRUPT_CTLRS    (NVRM_MAX_MAIN_INTR_CTLRS + \
+    NVRM_MAX_DRQ_INTR_CTLRS + NVRM_ARB_GNT_INTR_CTLRS)
+
+// Relative position of first DMA transmit interrupt controller
+#define NVRM_FIRST_DRQ_INTR_CTLR    (NVRM_MAX_MAIN_INTR_CTLRS)
+
+// Relative position of first Arbitration Grant interrupt controller
+#define NVRM_FIRST_ARB_INTR_CTLR    (NVRM_MAX_MAIN_INTR_CTLRS + \
+    NVRM_MAX_DRQ_INTR_CTLRS)
+
+// Number of IRQs per interrupt controller (main, DRQ, & ARB)
+#define NVRM_IRQS_PER_INTR_CTLR     32
+
+// Number of IRQs per GPIO controller
+#define NVRM_IRQS_PER_GPIO_CTLR     32
+
+// Number of IRQs per AHB DMA channel
+#define NVRM_IRQS_PER_AHB_DMA_CHAN  1
+
+// Number of IRQs per APB DMA channel
+#define NVRM_IRQS_PER_APB_DMA_CHAN  1
+
+// Invalid IRQ valid
+#define NVRM_IRQ_INVALID            0xFFFF
+
+// Maximum number of interrupts per device
+#define NVRM_MAX_DEVICE_IRQS        8
+
+// Maximum number of IRQs
+#define NVRM_MAX_IRQS               500
+
+// Maximum number of devices that can generate IRQs
+// !!!CHECKME!!! CHECK THE SIZING OF THIS VALUE
+#define NVRM_MAX_IRQ_DEVICES        96
+
+// Maximum number of DMA channels 
+#define NVRM_MAX_DMA_CHANNELS       32
+
+// This is the Maximum number of instance of all modules on any chip
+// supported by Rm.
+// Need to increase this value when more modules are added in the up comming
+// chips.
+#define NVRM_MAX_MODULE_INSTANCES   256
+
+/**
+ * Device IRQ assignments structure.
+ */
+typedef struct NvRmModuleIrqMapRec
+{
+    /* Number of IRQs owned by this device */
+    NvU16 IrqCount;
+
+    /* Maximum instance IRQ index */
+    NvU16 IndexMax;
+
+    /* Base IRQ for subcontroller "index" IRQ fanout */
+    NvU16 IndexBase;
+
+    /* IRQs owned by this device */
+    NvU16 Irq[NVRM_MAX_DEVICE_IRQS];
+} NvRmModuleIrqMap;
+
+/**
+ * System IRQ assignments structure.
+ */
+typedef struct NvRmIrqMapRec
+{
+    /* Number of devices owning IRQs */
+    NvU32 DeviceCount;
+
+    /* Device IRQ mapping */
+    NvRmModuleIrqMap DeviceIrq[NVRM_MAX_IRQ_DEVICES];
+} NvRmIrqMap;
+
+/**
+ * Some hardware modules may be instantiated multiple times - all hw modules
+ * are mapped into this structure.
+ */
+typedef struct NvRmModuleInstanceRec
+{
+    /* the base address of the module instance */
+    NvRmPhysAddr PhysAddr;
+
+    /* length of the aperture */
+    NvU32 Length;
+
+    /* bar number */
+    // FIXME: not supported properly - each bar is reported as a different
+    // hardware module instance.
+    NvU8 Bar;
+
+    /* hardware version */
+    NvU8 MajorVersion;
+    NvU8 MinorVersion;
+
+    /* power group */
+    NvU8 DevPowerGroup;
+
+    /* the original index into the relocation table */
+    NvU8 DevIdx;
+
+    /* hardware device id */
+    NvU32 DeviceId;
+
+    /* Irq mapping for this module instance */
+    NvRmModuleIrqMap *IrqMap;
+
+    /* virtual address: will be mapped by a later mechanism.  this is here
+     * as a space optimization.
+     */
+    void *VirtAddr;
+
+    /* Module specific data like clocks, resets etc.. */
+    void *ModuleData;
+} NvRmModuleInstance;
+
+/**
+ * Module index table.  Each index points to the first module instance in the
+ * NvRmModuleInstance table. The NvRmModule table itself is indexed by module
+ * id.
+ */
+typedef struct NvRmModuleRec
+{
+    /* offset into the NvRmModuleInstance table */
+    NvU16 Index;
+} NvRmModule;
+
+/**
+ * Maps relocation table device ids to software module ids.
+ * NVRM_DEVICE_UNKNOWN for unknown ids (will keep parsing table),
+ * or NVRM_DEVICE_ERROR if something bad happened
+ * (will stop parsing the table).
+ *
+ * NVRM_DEVICE_UNKOWN can be used to cull the device list to save space by
+ * not allocating memory for devices that won't be used.
+ */
+NvU32 NvRmPrivDevToModuleID(NvU32 devid);
+
+/**
+ * Parse the relocation table.
+ *
+ * The module instance table (NvRmModuleInstance) will be allocated to exactly
+ * match the number of hardware modules in the system rather than using a
+ * worst-case number of instances for all hardware modules.
+ *
+ * The module table should be allocated prior to this function and should be
+ * sized to the maximum number of module ids.
+ *
+ * The irq map will not be allocated (statically sized).
+ *
+ * The instance array will be null terminated -- the last instance will contain
+ * zero in all of its fields.
+ *
+ * @param hDevice The resource manager instance
+ * @param table The relocation table
+ * @param instances Out param - will contain the allocated instance table
+ * @param instanceLast Out param - will contain the last allocated instance + 1
+ * @param modules Out param - will contain the allocated module table
+ * @param irqs The irq table - will be filled in by the parser
+ */
+NvError
+NvRmPrivRelocationTableParse(
+    const NvU32 *table,
+    NvRmModuleInstance **instances,
+    NvRmModuleInstance **instanceLast,
+    NvRmModule *modules,
+    NvRmIrqMap *irqs );
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_rmctrace.c b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_rmctrace.c
new file mode 100644
index 000000000000..8e8353739f36
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_rmctrace.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvrm_rmctrace.h"
+#include "nvos.h"
+#include "nvassert.h"
+
+NvError NvRmRmcOpen( const char *name, NvRmRmcFile *rmc )
+{
+    return NvSuccess;
+}
+
+void NvRmRmcClose( NvRmRmcFile *rmc )
+{
+}
+
+void NvRmRmcTrace( NvRmRmcFile *rmc, const char *format, ... )
+{
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_rpc.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_rpc.h
new file mode 100644
index 000000000000..b38e8a1b1f3a
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_rpc.h
@@ -0,0 +1,198 @@
+/*
+ * arch/arm/mach-tegra/nvrm/core/common/nvrm_rpc.h
+ *
+ * communication between processors (cpu and avp)
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef NVRM_RPC_H
+#define NVRM_RPC_H
+
+/*
+ * nvrm_cpu_avp_rpc_private.h defines the private implementation functions to facilitate
+ * communication between processors (cpu and avp).
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_init.h"
+#include "nvrm_message.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+
+/**
+ * Initialize RPC
+ *
+ * Init the RPC.  Both the service and client
+ * to the service must call this API before calling to create each endpoint of the connection
+ * via NvRmPrivRPCConnect
+ *
+ * If PortName is too long or does not exist debug mode
+ * assert is encountered.
+ *
+ * @param hDeviceHandle rm device handle
+ * @param rpcPortName the port name
+ * @param hRPCHandle the RPC transport handle
+ *
+ * @retval NvError_SemaphoreCreateFailed Creaion of semaphore failed.
+ */
+ NvError NvRmPrivRPCInit( NvRmDeviceHandle hDeviceHandle, char* rpcPortName, NvRmRPCHandle *hRPCHandle );
+/**
+ * De-intialize the RPC and other resources.
+ * @param hRPCHandle the RPC transport handle
+ *
+ */
+void NvRmPrivRPCDeInit( NvRmRPCHandle hRPCHandle );
+
+/**
+ * Connect to RPC port
+ *
+ * Creates one end of a RPC connection.  Both the service and client
+ * to the service must call this API to create each endpoint of the connection
+ * through a specified port
+ *
+ * If PortName is too long or does not exist debug mode
+ * assert is encountered.
+ *
+ * @param hRPCHandle the RPC transport handle
+ *
+ * @retval NvSuccess Transport endpoint successfully allocated
+ * @retval NvError_InsufficientMemory Not enough memory to allocate endpoint
+ * @retval NvError_MutexCreateFailed Creaion of mutex failed.
+ * @retval NvError_SemaphoreCreateFailed Creaion of semaphore failed.
+ * @retval NvError_SharedMemAllocFailed Creaion of shared memory allocation
+ * failed.
+ * @retval NvError_NotInitialized The transport is not able to initialzed the
+ * threads.
+ */
+ NvError NvRmPrivRPCConnect( NvRmRPCHandle hRPCHandle );
+
+ /**
+ * Connect to RPC port
+ *
+ * Creates one end of a RPC connection.  Both the service and client
+ * to the service must call this API to create each endpoint of the connection
+ * through a specified port
+ *
+ * If PortName is too long or does not exist debug mode
+ * assert is encountered.
+ *
+ * @param hRPCHandle the RPC transport handle
+ *
+ * @retval NvSuccess Transport endpoint successfully allocated
+ * @retval NvError_InsufficientMemory Not enough memory to allocate endpoint
+ * @retval NvError_MutexCreateFailed Creaion of mutex failed.
+ * @retval NvError_SemaphoreCreateFailed Creaion of semaphore failed.
+ * @retval NvError_SharedMemAllocFailed Creaion of shared memory allocation
+ * failed.
+ * @retval NvError_NotInitialized The transport is not able to initialzed the
+ * threads.
+ */
+ NvError NvRmPrivRPCWaitForConnect( NvRmRPCHandle hRPCHandle );
+ /**
+ * Receive the message from the port. This will read the message if it is
+ * available for this port otherwise it will return the
+ * NvError_TransportMessageBoxEmpty error.
+ *
+ * @param hRPCHandle the RPC transport handle
+ * @param pMessageBuffer The pointer to the receive message buffer where the
+ * received message will be copied.
+ * @param pMessageSize Pointer to the variable where the length of the message
+ * will be stored.
+ *
+ * @retval NvSuccess Message received successfully.
+ * @retval NvError_NotInitialized hTransport is not open.
+ * @retval NvError_InvalidState The port is not connection state.
+ * @retval NvError_TransportMessageBoxEmpty The message box empty and not able
+ * to receive the message.
+ * @retval NvError_TransportIncompleteMessage The received message for this
+ * port is longer than the configured message length for this port. It copied
+ * the maximm size of the configured length of the message for this port and
+ * return the incomplete message buffer.
+ * @retval NvError_TransportMessageOverflow The port receives the message more
+ * than the configured queue depth count for this port and hence message
+ * overflow has been ocuured.
+ */
+
+ NvError NvRmPrivRPCRecvMsg( NvRmRPCHandle hRPCHandle, void* pMessageBuffer, NvU32 * pMessageSize );
+
+ /**
+ * Send Message.
+ *
+ * Sends a message to the other port which is connected to this port.
+ * Its a wrapper to rm transport send message
+ *
+ * @param hRPCHandle the RPC transport handle
+ * @param pMessageBuffer The pointer to the message buffer where message which
+ * need to be send is available.
+ * @param MessageSize Specifies the size of the message.
+ *
+ */
+void
+NvRmPrivRPCSendMsg(NvRmRPCHandle hRPCHandle,
+                   void* pMessageBuffer,
+                   NvU32 MessageSize);
+
+/**
+ * Send and Recieve message.
+ *
+ * Send and Recieve a message between port.
+ * Its a wrapper to rm transport send message with response
+ *
+ * @param hRPCHandle the RPC transport handle
+ * @param pRecvMessageBuffer The pointer to the receive message buffer where the
+ * received message will be copied.
+ * @param MaxSize The maximum size in bytes that may be copied to the buffer
+ * @param pMessageSize Pointer to the variable where the length of the message
+ * will be stored.
+ * @param pSendMessageBuffer The pointer to the message buffer where message which
+ * need to be send is available.
+ * @param MessageSize Specifies the size of the message.
+ *
+ */
+void
+NvRmPrivRPCSendMsgWithResponse(NvRmRPCHandle hRPCHandle,
+                               void* pRecvMessageBuffer,
+                               NvU32 MaxSize,
+                               NvU32 *pMessageSize,
+                               void* pSendMessageBuffer,
+                               NvU32 MessageSize);
+
+
+/**
+ * Closes a transport connection.  Proper closure of this connection requires
+ * that both the client and service call this API.  Therefore, it is expected
+ * that the client and service message one another to coordinate the close.
+ *
+ */
+void NvRmPrivRPCClose(NvRmRPCHandle hRPCHandle);
+
+NvError  NvRmPrivInitService(NvRmDeviceHandle hDeviceHandle);
+
+void NvRmPrivServiceDeInit(void);
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+
+#endif
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_structure.h b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_structure.h
new file mode 100644
index 000000000000..da3f68423c02
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_structure.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2008-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_NVRM_STRUCTURE_H
+#define INCLUDED_NVRM_STRUCTURE_H
+
+/*
+ * nvrm_structure.h defines all of the internal data structures for the
+ * resource manager which are chip independent.
+ *
+ * Don't add chip specific stuff to this file.
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvrm_module.h"
+#include "nvrm_module_private.h"
+#include "nvrm_chipid.h"
+#include "nvrm_interrupt.h"
+#include "nvrm_memmgr.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_rmctrace.h"
+#include "nvrm_configuration.h"
+#include "nvrm_relocation_table.h"
+#include "nvrm_moduleids.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif  /* __cplusplus */
+
+typedef struct RmConfigurationVariables_t
+{
+    /* RMC Trace file name */
+    char RMCTraceFileName[ NVRM_CFG_MAXLEN ];
+
+    /* chiplib name */
+    char Chiplib[ NVRM_CFG_MAXLEN ];
+
+    /* chiplib args */
+    char ChiplibArgs[ NVRM_CFG_MAXLEN ];
+
+} RmConfigurationVariables;
+
+/* memory pool information */
+typedef struct RmMemoryPool_t
+{
+    NvU32 base;
+    NvU32 size;
+} RmMemoryPool;
+
+/* The state for the resource manager */
+typedef struct NvRmDeviceRec
+{
+    RmConfigurationVariables cfg;
+    NvRmRmcFile rmc;
+    NvBool rmc_enable;
+    NvOsMutexHandle mutex;
+    //  FIXME:  this is hardcoded to the number of tristate registers in AP15.
+    NvS16 TristateRefCount[4 * sizeof(NvU32)*8];
+    NvU32 refcount;
+
+    NvOsMutexHandle MemMgrMutex;
+    NvOsMutexHandle PinMuxMutex;
+    NvOsMutexHandle CarMutex;   /* r-m-w top level CAR registers mutex */
+
+    /* chip id */
+    NvRmChipId ChipId;
+
+    /* module instances and module index table */
+    NvRmModuleTable ModuleTable;
+
+    RmMemoryPool ExtMemoryInfo;
+    RmMemoryPool IramMemoryInfo;
+    RmMemoryPool GartMemoryInfo;
+
+    NvU16 MaxIrqs;
+
+    const NvU32  ***PinMuxTable;
+    // FIXME: get rid of all the various Init and Open functions in favor
+    // of a sane state machine for system boot/initialization
+    NvBool bPreInit;
+    NvBool bBasicInit;
+} NvRmDevice;
+
+// FIXME: This macro should be comming from the relocation table.
+#define NVRM_MAX_INSTANCES 32
+
+/**
+ * Sub-contoller interrupt decoder description forward reference.
+ */
+typedef struct NvRmIntrDecoderRec *NvRmIntrDecoderHandle;
+
+/**
+ * Attributes of the Interrupt sub-decoders.
+ */
+typedef struct NvRmIntrDecoderRec
+{
+    NvRmModuleID ModuleID;
+
+    //  Number of IRQs owned by this sub-controller.
+    //  This value is same for all the instances of the controller.
+    NvU32 SubIrqCount;
+
+    // Number of instance for this sub-decoder
+    NvU32 NumberOfInstances;
+    
+    // Main controller IRQ.
+    NvU16 MainIrq[NVRM_MAX_INSTANCES];
+
+    // First IRQ owned by this sub-controller.
+    NvU16 SubIrqFirst[NVRM_MAX_INSTANCES];
+
+    // Last IRQ owned by this sub-controller.
+    NvU16 SubIrqLast[NVRM_MAX_INSTANCES];
+
+} NvRmIntrDecoder;
+
+#ifdef __cplusplus
+}
+#endif  /* __cplusplus */
+
+#endif // INCLUDED_NVRM_STRUCTURE_H
diff --git a/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_transport.c b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_transport.c
new file mode 100644
index 000000000000..0ccd0784192e
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/core/common/nvrm_transport.c
@@ -0,0 +1,1497 @@
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/** @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *          Transport API</b>
+ *
+ * @b Description: This is the implementation of Transport API, which
+ * implements a simple means to pass messages across a port name regardless of
+ * port exist in what processor (on same processor or other processor).
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <mach/irqs.h>
+#include "nvrm_transport.h"
+#include "nvrm_xpc.h"
+#include "nvrm_interrupt.h"
+#include "nvrm_message.h"
+#include "nvutil.h"
+#include "nvassert.h"
+#include "nvcommon.h"
+#include "avp.h"
+#include <linux/jiffies.h>
+
+#define LOOPBACK_PROFILE 0
+
+// indices where to save data for the loopback test
+#define LOOP_CPU_SEND_INDEX 0
+#define LOOP_AVP_ISR_INDEX  1
+#define LOOP_AVP_RECV_INDEX 2
+#define LOOP_AVP_SEND_INDEX 3
+#define LOOP_CPU_ISR_INDEX  4
+#define LOOP_CPU_RECV_INDEX 5
+
+#define SEMAPHORE_BASED_MUTUAL_EXCLUSION 0
+
+enum {MAX_INT_FOR_TRANSPORT = 2};
+
+// Interrupt bit index in the interrupt controller relocation table.
+enum {CPU_TRANSPORT_INT_OBE = 1};
+enum {CPU_TRANSPORT_INT_IBF = 0};
+enum {AVP_TRANSPORT_INT_OBE = 0};
+enum {AVP_TRANSPORT_INT_IBF = 1};
+
+// Some constraints parameter to develop the transport APIs.
+
+// Maximum port name length
+enum {MAX_PORT_NAME_LENGTH = 16};
+
+// Maximum possible message length between the ports
+#define  MAX_COMMAND_SIZE   16
+
+// Message header size MessageCommand + port Name + message Length (24 Bytes)
+enum {MESSAGE_HEADER_SIZE = 0x20};
+
+// Maximum receive message queue depth
+enum {MAX_MESSAGE_DEPTH = 30};
+
+// Maximum time to wait for the response when open the port.
+enum {MAX_OPEN_TIMEOUT_MS = 200};
+
+// Try to resend the message after this time.
+enum {MESSAGE_RETRY_AFTER_MS = 500 };
+
+// Connection message transfer and response wait timeout.
+enum {MAX_CONNECTION_TIMEOUT_MS = 500 };
+
+
+
+// Transport Commands which uses to do the handshaking and message transfer
+// between the processor. This commands are send to the remote processor
+// when any type if transaction happens.
+typedef enum
+{
+  TransportCmd_None = 0x0,
+
+  // The first transport command from the cpu->avp will inform the
+  // avp of size of the buffer.
+  TransportCmd_SetBufferInfo,
+
+  // Transport command for staring the connection process.
+  TransportCmd_Connect,
+
+  // Transport command for disconnecting the port and deleting the port entry.
+  TransportCmd_Disconnect,
+
+  // Transport command which used for normal message transfer to the port.
+  TransportCmd_Message,
+
+  // When a command requires a response, the value in the command field will
+  // be changed by the called processor here to indicate that the response is ready.
+  TransportCmd_Response,
+
+  TransportCmd_Force32 = 0x7FFFFFFF
+
+} TransportCmd;
+
+
+
+// Ports (endpoint) state.
+typedef enum
+{
+    // Port is opened only.
+    PortState_Open = 0x1,
+
+    // Port is waiting for connection.
+    PortState_Waiting,
+
+    // Port is connected.
+    PortState_Connected,
+
+    // Port has been disconnected from other side.  You can pop out messages
+    // but you can't send anymore
+    PortState_Disconnected,
+
+    // Set to destroy when there is someone waiting for a connection, but
+    // and a different thread calls to kill close the port.
+    PortState_Destroy,
+
+    PortState_Force32 = 0x7FFFFFFF
+} PortState;
+
+
+
+// Message list which will be queued in the port receive message queue.
+typedef struct RmReceiveMessageRec
+{
+    // Length of message.
+    NvU32 MessageLength;
+
+    // Fixed size message buffer where the receiving message will be store.
+    NvU8 MessageBuffer[MAX_MESSAGE_LENGTH];
+} RmReceiveMessage;
+
+
+// Combines the information for keeping the received messages to the
+// corresponding ports.
+typedef struct MessageQueueRec
+{
+    // Receive message Q details to receive the message.  We make the queue 1 extra bigger than the
+    // requested size, and then we can do lockless updates because only the Recv function modifies
+    // ReadIndex, and only the ISR modifies the WriteIndex
+    RmReceiveMessage *pReceiveMsg;
+
+    volatile NvU16 ReadIndex;
+    volatile NvU16 WriteIndex;
+
+    NvU16 QueueSize;
+
+} MessageQueue;
+
+
+
+// Combines all required information for the transport port.
+// The port information  contains the state, recv message q, message depth and
+// message length.
+typedef struct NvRmTransportRec
+{
+    // Name of the port, 1 exra byte for NULL termination
+    char PortName[MAX_PORT_NAME_LENGTH+1];
+
+    // The state of port whether this is open or connected or waiting for
+    // connection.
+    PortState State;
+
+    // Receive message Box which contains the receive messages for this port.
+    MessageQueue RecvMessageQueue;
+
+    // Semaphore which is signal after getting the message for that port.
+    // This is the client passed semaphore.
+    NvOsSemaphoreHandle hOnPushMsgSem;
+
+    // Pointer to the partner port.  If the connect is to a remote partner,
+    // then this pointer is NULL
+    NvRmTransportHandle hConnectedPort;
+
+    // If this is a remote connection, this holds the remote ports "name"
+    NvU32               RemotePort;
+
+    // save a copy of the rm handle.
+    NvRmDeviceHandle hRmDevice;
+
+    struct NvRmTransportRec *pNext;
+
+    // unlikely to be used members at the end
+
+    // to be signalled when someone waits for a connector.
+    NvOsSemaphoreHandle hOnConnectSem;
+
+#if LOOPBACK_PROFILE
+    NvBool              bLoopTest;
+#endif
+
+} NvRmTransport;
+
+
+
+// Combines the common information for keeping the transport information and
+// sending and receiving the messages.
+typedef struct NvRmPrivPortsRec
+{
+    // Device handle.
+    NvRmDeviceHandle hDevice;
+
+    // List of port names of the open ports in the system.
+    NvRmTransport   *pPortHead;
+
+    // Mutex for transport
+    NvOsMutexHandle mutex;
+    dma_addr_t     messageDma;
+    void __iomem  *pTransmitMem;
+    void __iomem  *pReceiveMem;
+
+    NvRmPrivXpcMessageHandle hXpc;
+
+    // if a message comes in, but the receiver's queue is full,    // then we don't clear the inbound message to allow another message
+    // and set this flag.  We use 2 variables here, so we don't need a lock.
+    volatile NvU8  ReceiveBackPressureOn;
+    NvU8           ReceiveBackPressureOff;
+
+#if LOOPBACK_PROFILE
+    volatile NvU32 *pTimer;
+#endif
+} NvRmPrivPorts;
+
+
+// !!! Fixme, this should be part of the rm handle.
+static NvRmPrivPorts s_TransportInfo;
+
+extern NvU32 NvRmAvpPrivGetUncachedAddress(NvU32 addr);
+
+#define MESSAGE_QUEUE_SIZE_IN_BYTES ( sizeof(RmReceiveMessage) * (MAX_MESSAGE_DEPTH+1) )
+static NvU32 s_RpcAvpQueue[ (MESSAGE_QUEUE_SIZE_IN_BYTES + 3) / 4 ];
+static NvU32 s_RpcCpuQueue[ (MESSAGE_QUEUE_SIZE_IN_BYTES + 3) / 4 ];
+static struct NvRmTransportRec s_RpcAvpPortStruct;
+static struct NvRmTransportRec s_RpcCpuPortStruct;
+
+static int s_TransportInterruptHandle = -1;
+
+static NvRmTransportHandle
+FindPort(NvRmDeviceHandle hDevice, char *pPortName);
+
+static NvError NvRmPrivTransportSendMessage(NvRmDeviceHandle hDevice,
+    NvU32 *messagehdr, NvU32 MessageHdrLength,
+    NvU32 *Message, NvU32 MessageLength);
+
+static void HandleAVPResetMessage(NvRmDeviceHandle hDevice);
+
+// expect caller to handle mutex
+static char *NvRmPrivTransportUniqueName(void)
+{
+    static char UniqueName[] = "aaaaaaaa+";
+    NvU32 len = 8;
+    NvU32 i;
+
+    // this will roll a new name until we hit zzzz:zzzz
+    // it's not unbounded, but it is a lot of names...
+    // Unique names end in a '+' which won't be allowed in supplied names, to avoid
+    // collision.
+    for (i=0; i < len; ++i)
+    {
+        ++UniqueName[i];
+        if (UniqueName[i] != 'z')
+        {
+            break;
+        }
+        UniqueName[i] = 'a';
+
+    }
+
+    return UniqueName;
+}
+
+
+/* Returns NV_TRUE if the message was inserted ok
+ *  Returns NV_FALSE if message was not inserted because the queue is already full
+
+ */static NvBool
+InsertMessage(NvRmTransportHandle hPort, const NvU8 *message, const NvU32 MessageSize)
+{
+    NvU32 index;
+    NvU32 NextIndex;
+
+    index = (NvU32)hPort->RecvMessageQueue.WriteIndex;
+    NextIndex = index + 1;
+    if (NextIndex == hPort->RecvMessageQueue.QueueSize)
+        NextIndex = 0;
+
+    // check for full condition
+    if (NextIndex == hPort->RecvMessageQueue.ReadIndex)
+        return NV_FALSE;
+
+    // copy in the message
+    NvOsMemcpy(hPort->RecvMessageQueue.pReceiveMsg[index].MessageBuffer,
+               message,
+               MessageSize);
+    hPort->RecvMessageQueue.pReceiveMsg[index].MessageLength = MessageSize;
+
+    hPort->RecvMessageQueue.WriteIndex = (NvU16)NextIndex;
+    return NV_TRUE;
+}
+
+
+static void
+ExtractMessage(NvRmTransportHandle hPort, NvU8 *message, NvU32 *pMessageSize, NvU32 MaxSize)
+{
+    NvU32 NextIndex;
+    NvU32 index = (NvU32)hPort->RecvMessageQueue.ReadIndex;
+    NvU32 size  = hPort->RecvMessageQueue.pReceiveMsg[index].MessageLength;
+
+    NextIndex = index + 1;
+    if (NextIndex == hPort->RecvMessageQueue.QueueSize)
+        NextIndex = 0;
+
+    NV_ASSERT(index != hPort->RecvMessageQueue.WriteIndex); // assert on empty condition
+    NV_ASSERT(size <= MaxSize);
+
+    *pMessageSize = size;
+
+    // only do the copy and update if there is sufficient room, otherwise
+    // the caller will propogate an error up.
+    if (size > MaxSize)
+    {
+        return;
+    }
+    NvOsMemcpy(message,
+               hPort->RecvMessageQueue.pReceiveMsg[index].MessageBuffer,
+               size);
+
+    hPort->RecvMessageQueue.ReadIndex = (NvU16)NextIndex;
+}
+
+/**
+ * Connect message
+ *  [ Transport Command ]
+ *  [ Remote Handle ]
+ *  [ Port Name ]
+ *
+ * Response:
+ *   [ Remote Handle ] <- [ Local Handle ]
+ */
+
+static void
+HandleConnectMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
+{
+    char PortName[MAX_PORT_NAME_LENGTH+1];
+    NvU32 RemotePort;
+    NvRmTransportHandle hPort;
+
+    RemotePort = pMessage[1];
+    NvOsMemcpy(PortName, (void*)&pMessage[2], MAX_PORT_NAME_LENGTH);
+    PortName[MAX_PORT_NAME_LENGTH] = 0;
+
+    // See if there is a local port with that name
+    hPort = FindPort(hDevice, PortName);
+    if (hPort && hPort->State == PortState_Waiting)
+    {
+        NvOsAtomicCompareExchange32((NvS32 *)&hPort->State, PortState_Waiting, PortState_Connected);
+        if (hPort->State == PortState_Connected)
+        {
+            hPort->RemotePort = RemotePort;
+            NvOsSemaphoreSignal(hPort->hOnConnectSem);
+            pMessage[1] = (NvU32)hPort;
+        }
+        else
+        {
+            pMessage[1] = 0;
+        }
+    }
+    else
+    {
+        pMessage[1] = 0;
+    }
+    pMessage[0] = TransportCmd_Response;
+}
+
+
+
+/**
+ * Disconnect message
+ *  [ Transport Command ]
+ *  [ Local Handle ]
+ *
+ * Response:
+ *   [ Local Handle ] <- 0
+ */
+static void
+HandleDisconnectMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
+{
+    NvRmTransportHandle hPort;
+    hPort = (NvRmTransportHandle)pMessage[1];
+
+    // !!! For sanity we should walk the list of open ports to make sure this is a valid port!
+    if (hPort && hPort->State == PortState_Connected)
+    {
+        hPort->State = PortState_Disconnected;
+        hPort->RemotePort = 0;
+    }
+    pMessage[1] = 0;
+    pMessage[0] = TransportCmd_None;
+}
+
+
+/**
+ * Disconnect message
+ *  [ Transport Command ]
+ *  [ Local Handle ]
+ *  [ Message Length ]
+ *  [ Message ]
+ *
+ * Response:
+ *   [ Message Length ] <- NvSuccess
+ *   [ Transport Command ] <- When we can accept a new message
+ */
+
+static void
+HandlePortMessage(NvRmDeviceHandle hDevice, volatile NvU32 *pMessage)
+{
+    NvRmTransportHandle hPort;
+    NvU32               MessageLength;
+    NvBool              bSuccess;
+
+    hPort         = (NvRmTransportHandle)pMessage[1];
+    MessageLength = pMessage[2];
+
+#if LOOPBACK_PROFILE
+    if (hPort && hPort->bLoopTest)
+    {
+# if NV_IS_AVP
+        pMessage[LOOP_AVP_ISR_INDEX + 3] = *s_TransportInfo.pTimer;
+# else
+        pMessage[LOOP_CPU_ISR_INDEX + 3] = *s_TransportInfo.pTimer;
+# endif
+    }
+#endif
+
+
+    // !!! For sanity we should walk the list of open ports to make sure this is a valid port!
+    // Queue the message even if in the open state as presumably this should only have happened if
+    // due to a race condition with the transport connected messages.
+    if (hPort && (hPort->State == PortState_Connected || hPort->State == PortState_Open))
+    {
+        bSuccess = InsertMessage(hPort, (NvU8*)&pMessage[3], MessageLength);
+        if (bSuccess)
+        {
+            if (hPort->hOnPushMsgSem)
+                NvOsSemaphoreSignal(hPort->hOnPushMsgSem);
+            pMessage[0] = TransportCmd_None;
+        }
+        else
+        {
+            ++s_TransportInfo.ReceiveBackPressureOn;
+        }
+    }
+}
+
+static void
+HandleAVPResetMessage(NvRmDeviceHandle hDevice)
+{
+    NvRmTransportHandle hPort;
+
+    hPort = FindPort(hDevice,(char*)"RPC_CPU_PORT");
+    if (hPort && (hPort->State == PortState_Connected || hPort->State == PortState_Open))
+    {
+        NvU32 message;
+        message = NvRmMsg_AVP_Reset;
+        InsertMessage(hPort, (NvU8*)&message, sizeof(NvU32));
+        if (hPort->hOnPushMsgSem)
+            NvOsSemaphoreSignal(hPort->hOnPushMsgSem);
+        else
+            NV_ASSERT(0);
+    }
+    else
+        NV_ASSERT(0);
+
+}
+
+
+/**
+ * Handle the Inbox full interrupt.
+ */
+static void InboxFullIsr(void *args)
+{
+    NvRmDeviceHandle hDevice = (NvRmDeviceHandle)args;
+    NvU32 MessageData;
+    NvU32 MessageCommand;
+    volatile NvU32 *pMessage;
+
+    MessageData = NvRmPrivXpcGetMessage(s_TransportInfo.hXpc);
+    if(MessageData == AVP_WDT_RESET)
+    {
+         HandleAVPResetMessage(hDevice);
+         return;
+    }
+
+    // otherwise decode and dispatch the message.
+
+
+    BUG_ON(s_TransportInfo.pReceiveMem == NULL);
+    pMessage = (NvU32*)s_TransportInfo.pReceiveMem;
+
+    MessageCommand = pMessage[0];
+
+    switch (MessageCommand)
+    {
+    case  TransportCmd_Connect:
+        HandleConnectMessage(hDevice, pMessage);
+        break;
+
+    case  TransportCmd_Disconnect:
+        HandleDisconnectMessage(hDevice, pMessage);
+        break;
+
+    case TransportCmd_Message:
+        HandlePortMessage(hDevice, pMessage);
+        break;
+
+    default:
+        NV_ASSERT(0);
+    }
+}
+
+static irqreturn_t transport_isr(int irq, void *data)
+{
+    InboxFullIsr(data);
+    return IRQ_HANDLED;
+}
+
+/**
+ * Register for the transport interrupts.
+ */
+static NvError
+RegisterTransportInterrupt(NvRmDeviceHandle hDevice)
+{
+    NvU32 IrqList;
+    int ret;
+
+    if (s_TransportInterruptHandle >= 0)
+    {
+        return NvSuccess;
+    }
+    
+    IrqList = INT_SHR_SEM_INBOX_IBF;
+
+    set_irq_flags(IrqList, IRQF_VALID);
+    ret = request_irq(IrqList, transport_isr, 0,
+                      "nvrm_transport", hDevice);
+    if (ret) {
+      printk("%s failed %d\n", __func__, ret);
+      return NvError_BadParameter;
+    }
+    s_TransportInterruptHandle = IrqList;
+    return NvSuccess;
+}
+
+void NvRmPrivXpcSendMsgAddress(void)
+{
+    BUG_ON(!s_TransportInfo.messageDma);
+    pr_info("msgBuff at %08x\n", s_TransportInfo.messageDma);
+    NvRmPrivXpcSendMessage(s_TransportInfo.hXpc,
+                           s_TransportInfo.messageDma);
+}
+
+#define MESSAGE_DMA_SIZE (2 * (MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE))
+
+// allocate buffers to be used for sending/receiving messages.
+static void NvRmPrivTransportAllocBuffers(NvRmDeviceHandle hRmDevice)
+{
+
+    s_TransportInfo.pTransmitMem = dma_alloc_coherent(NULL, MESSAGE_DMA_SIZE,
+                                      &s_TransportInfo.messageDma, GFP_KERNEL);
+
+    BUG_ON(!s_TransportInfo.pTransmitMem);
+
+    s_TransportInfo.pReceiveMem = s_TransportInfo.pTransmitMem +
+        MAX_MESSAGE_LENGTH + MAX_COMMAND_SIZE;
+
+    // set this non-zero to throttle messages to the avp till avp is ready.
+    writel(0xdeadf00dul, s_TransportInfo.pTransmitMem);
+    writel(0, s_TransportInfo.pReceiveMem);
+}
+
+
+static void NvRmPrivTransportFreeBuffers(NvRmDeviceHandle hRmDevice)
+{
+    dma_free_coherent(NULL, MESSAGE_DMA_SIZE, s_TransportInfo.pTransmitMem,
+                      s_TransportInfo.messageDma);
+}
+
+static volatile NvBool s_Transport_Inited = NV_FALSE;
+
+/**
+ * Initialize the transport structures, this is callled once
+ * at NvRmOpen time.
+ */
+NvError NvRmTransportInit(NvRmDeviceHandle hRmDevice)
+{
+    NvError err;
+
+    NvOsMemset(&s_TransportInfo, 0, sizeof(s_TransportInfo));
+    s_TransportInfo.hDevice = hRmDevice;
+
+    err = NvOsMutexCreate(&s_TransportInfo.mutex);
+    if (err)
+        goto fail;
+
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE
+    err = NvRmPrivXpcCreate(hRmDevice, &s_TransportInfo.hXpc);
+    if (err)
+        goto fail;
+
+    NvRmPrivTransportAllocBuffers(hRmDevice);
+#endif
+
+#if LOOPBACK_PROFILE
+    {
+        NvU32             TimerAddr;
+        NvU32             TimerSize;
+
+        NvRmModuleGetBaseAddress(hRmDevice, NvRmModuleID_TimerUs, &TimerAddr, &TimerSize);
+        // map the us counter
+        err = NvRmPhysicalMemMap(TimerAddr, TimerSize, NVOS_MEM_READ_WRITE,
+            NvOsMemAttribute_Uncached, (void*)&s_TransportInfo.pTimer);
+        if (err)
+            goto fail;
+    }
+
+#endif
+
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE
+    err = RegisterTransportInterrupt(hRmDevice);
+    if (err)
+        goto fail;
+#endif
+    s_Transport_Inited = NV_TRUE;
+    return NvSuccess;
+
+
+fail:
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE
+    NvRmPrivXpcDestroy(s_TransportInfo.hXpc);
+    NvRmPrivTransportFreeBuffers(hRmDevice);
+#endif
+    NvOsMutexDestroy(s_TransportInfo.mutex);
+    return err;
+}
+
+/**
+ * DeInitialize the transport structures.
+ */
+void NvRmTransportDeInit(NvRmDeviceHandle hRmDevice)
+{
+    // Unregister the interrupts.
+#if !NVOS_IS_WINDOWS || NVOS_IS_WINDOWS_CE
+    NvRmPrivXpcDestroy(s_TransportInfo.hXpc);
+    NvRmPrivTransportFreeBuffers(hRmDevice);
+    free_irq(s_TransportInterruptHandle, hRmDevice);
+    set_irq_flags(s_TransportInterruptHandle, IRQF_VALID);
+    s_TransportInterruptHandle = -1;
+#endif
+    NvOsMutexDestroy(s_TransportInfo.mutex);
+}
+
+
+static void
+InsertPort(NvRmDeviceHandle hDevice, NvRmTransportHandle hPort)
+{
+    hPort->pNext = s_TransportInfo.pPortHead;
+    s_TransportInfo.pPortHead = hPort;
+}
+
+
+static NvRmTransportHandle
+FindPort(NvRmDeviceHandle hDevice, char *pPortName)
+{
+    NvRmTransportHandle hPort = NULL;
+    NvRmTransportHandle hIter = NULL;
+
+    hIter = s_TransportInfo.pPortHead;
+    while (hIter)
+    {
+        if ( NvOsStrcmp(pPortName, hIter->PortName) == 0)
+        {
+            hPort = hIter;
+            break;
+        }
+        hIter = hIter->pNext;
+    }
+
+    return hPort;
+}
+
+
+// Remove the given hPort from the list of ports
+static void
+DeletePort(NvRmDeviceHandle hRmDevice, const NvRmTransportHandle hPort)
+{
+    // Pointer to the pointer alleviates all special cases in linked list walking.
+    // I wish I was clever enough to have figured this out myself.
+
+    NvRmTransportHandle *hIter;
+
+    hIter = &s_TransportInfo.pPortHead;
+    while (*hIter)
+    {
+        if ( *hIter == hPort )
+        {
+            *hIter = (*hIter)->pNext;
+            break;
+        }
+        hIter = &(*hIter)->pNext;
+    }
+}
+
+
+
+
+/**
+ * Open the port handle with a given port name. With the same name, only two
+ * port can be open.
+ * Thread Safety: It is done inside the function.
+ */
+
+NvError
+NvRmTransportOpen(
+    NvRmDeviceHandle hRmDevice,
+    char *pPortName,
+    NvOsSemaphoreHandle RecvMessageSemaphore,
+    NvRmTransportHandle *phTransport)
+{
+    NvU32               PortNameLen;
+    NvRmTransportHandle hPartner = NULL;
+    NvRmTransportHandle hPort    = NULL;
+    NvError             err      = NvError_InsufficientMemory;
+    char                TmpName[MAX_PORT_NAME_LENGTH+1];
+
+    while (!s_Transport_Inited) {
+        // This can happen, if this API is called before avp init.
+        NvOsSleepMS(500);
+    }
+    // Look and see if this port exists anywhere.
+    if (pPortName == NULL)
+    {
+        NvOsMutexLock(s_TransportInfo.mutex);
+
+        pPortName = NvRmPrivTransportUniqueName();
+        PortNameLen = NvOsStrlen(pPortName);
+        NvOsStrncpy(TmpName, pPortName, sizeof(TmpName) );
+        pPortName = TmpName;
+
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+    }
+    else
+    {
+        PortNameLen = NvOsStrlen(pPortName);
+        NV_ASSERT(PortNameLen <= MAX_PORT_NAME_LENGTH);
+    }
+
+    NvOsMutexLock(s_TransportInfo.mutex);
+    hPartner = FindPort(hRmDevice, pPortName);
+
+    if (hPartner && hPartner->hConnectedPort != NULL)
+    {
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        return NvError_TransportPortAlreadyExist;
+    }
+
+    // check if this is one of the special RPC ports used by the rm
+    if ( NvOsStrcmp(pPortName, "RPC_AVP_PORT") == 0)
+    {
+        //If someone else wants to open this port
+        //just return the one already created.
+        if (hPartner)
+        {
+            hPort = hPartner;
+            goto success;
+        }
+        else
+        {
+            hPort = &s_RpcAvpPortStruct;
+            hPort->RecvMessageQueue.pReceiveMsg = (void *)&s_RpcAvpQueue[0];
+        }
+    }
+    else if (NvOsStrcmp(pPortName, "RPC_CPU_PORT") == 0)
+    {
+        hPort = &s_RpcCpuPortStruct;
+        hPort->RecvMessageQueue.pReceiveMsg = (void *)&s_RpcCpuQueue[0];
+    }
+    else
+    {
+        // Create a new TransportPort
+        hPort = NvOsAlloc( sizeof(*hPort) );
+        if (!hPort)
+            goto fail;
+
+        NvOsMemset(hPort, 0, sizeof(*hPort) );
+
+        // Allocate the receive queue
+        hPort->RecvMessageQueue.pReceiveMsg = NvOsAlloc( sizeof(RmReceiveMessage) * (MAX_MESSAGE_DEPTH+1));
+        if (!hPort->RecvMessageQueue.pReceiveMsg)
+            goto fail;
+    }
+
+    NvOsStrncpy(hPort->PortName, pPortName, PortNameLen);
+    hPort->State =  PortState_Open;
+    hPort->hConnectedPort = hPartner;
+
+    if (RecvMessageSemaphore)
+    {
+        err = NvOsSemaphoreClone(RecvMessageSemaphore, &hPort->hOnPushMsgSem);
+        if (err)
+            goto fail;
+    }
+
+    hPort->RecvMessageQueue.QueueSize = MAX_MESSAGE_DEPTH+1;
+    hPort->hRmDevice = hRmDevice;
+
+    if (hPort->hConnectedPort != NULL)
+    {
+        hPort->hConnectedPort->hConnectedPort = hPort;
+    }
+    InsertPort(hRmDevice, hPort);
+
+
+    // !!! loopback info
+#if LOOPBACK_PROFILE
+    if (NvOsStrcmp(hPort->PortName, "LOOPTEST") == 0)
+        hPort->bLoopTest = 1;
+#endif
+
+success:
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+    *phTransport = hPort;
+    return NvSuccess;
+
+fail:
+    if (hPort)
+    {
+        NvOsFree(hPort->RecvMessageQueue.pReceiveMsg);
+        NvOsSemaphoreDestroy(hPort->hOnPushMsgSem);
+        NvOsFree(hPort);
+        hPort = NULL;
+    }
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+
+    return err;
+}
+
+
+/**
+ * Close the transport handle
+ * Thread Safety: It is done inside the function.
+ */
+void NvRmTransportClose(NvRmTransportHandle hPort)
+{
+    NvU32 RemoteMessage[4];
+
+    if (!hPort)
+        return;
+
+    // Look and see if this port exists anywhere.
+    NV_ASSERT(hPort);
+
+
+    NvOsMutexLock(s_TransportInfo.mutex);
+    DeletePort(hPort->hRmDevice, hPort);  // unlink this port
+
+    // Check if there is already a port waiting to connect, and if there is
+    // switch the port state to _Destroy, and signal the waiters semaphore.
+    // The "State" member is not protected by the mutex because it can be
+    // updated by the ISR.
+    while (hPort->State == PortState_Waiting)
+    {
+        NvOsAtomicCompareExchange32((NvS32*)&hPort->State, PortState_Waiting, PortState_Destroy);
+        if (hPort->State == PortState_Destroy)
+        {
+            NvOsSemaphoreSignal(hPort->hOnConnectSem);
+
+            // in this case, we can't complete the destroy, the signalled thread will
+            // have to complete.  We just return now
+            NvOsMutexUnlock(s_TransportInfo.mutex);
+            return;
+        }
+    }
+
+    if (hPort->hConnectedPort)
+    {
+        // unlink this port from the other side of the connection.
+        hPort->hConnectedPort->hConnectedPort = NULL;
+    }
+
+    if (hPort->RemotePort)
+    {
+        RemoteMessage[0] = TransportCmd_Disconnect;
+        RemoteMessage[1] = hPort->RemotePort;
+        NvRmPrivTransportSendMessage(hPort->hRmDevice, RemoteMessage,
+            2*sizeof(NvU32), NULL, 0);
+    }
+
+    NvOsSemaphoreDestroy(hPort->hOnPushMsgSem);
+
+
+    if (hPort == &s_RpcAvpPortStruct ||
+        hPort == &s_RpcCpuPortStruct)
+    {
+        // don't free these..
+        NvOsMemset(hPort, 0, sizeof(*hPort));
+    }
+    else
+    {
+        NvOsFree(hPort->RecvMessageQueue.pReceiveMsg);
+        NvOsFree(hPort);
+    }
+
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+}
+
+
+/**
+ * Wait for the connection to the other end.
+ * Thread Safety: It is done inside the function.
+ */
+NvError
+NvRmTransportWaitForConnect(
+    NvRmTransportHandle hPort,
+    NvU32 TimeoutMS)
+{
+    NvOsSemaphoreHandle hSem = NULL;
+    NvError             err  = NvSuccess;
+
+    NvOsMutexLock(s_TransportInfo.mutex);
+    if (hPort->State != PortState_Open)
+    {
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        err = NvError_TransportPortAlreadyExist;
+        goto exit_gracefully;
+    }
+
+    err = NvOsSemaphoreCreate(&hSem, 0);
+    if (err)
+    {
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        goto exit_gracefully;
+    }
+
+    hPort->hOnConnectSem = hSem;
+    hPort->State = PortState_Waiting;
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+
+    err = NvOsSemaphoreWaitTimeout(hSem, TimeoutMS);
+    if (err)
+    {
+        // we have to be careful here, the ISR _might_ happen just after the semaphore
+        // times out.
+        NvOsAtomicCompareExchange32((NvS32 *)&hPort->State, PortState_Waiting, PortState_Open);
+        NV_ASSERT(hPort->State == PortState_Open || hPort->State == PortState_Connected);
+        if (hPort->State == PortState_Connected)
+        {
+            err = NvSuccess;
+        }
+    }
+
+    NvOsMutexLock(s_TransportInfo.mutex);
+    hPort->hOnConnectSem = NULL;
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+
+    if (hPort->State == PortState_Destroy)
+    {
+        // finish the destroy process
+        NvRmTransportClose(hPort);
+        err = NvError_TransportConnectionFailed;
+    }
+
+exit_gracefully:
+    NvOsSemaphoreDestroy(hSem);
+    return err;
+}
+
+
+
+static NvError NvRmPrivTransportWaitResponse(NvRmDeviceHandle hDevice,
+                                             NvU32 *response,
+                                             NvU32 ResponseLength,
+                                             NvU32 TimeoutMS)
+{
+    NvU32   Elapsed;
+    NvU32   StartTime;
+    NvU32   Response;
+
+    StartTime = NvOsGetTimeMS();
+
+    do {
+        Response = readl(s_TransportInfo.pTransmitMem);
+        if (Response == TransportCmd_Response)
+            break;
+        cpu_relax();
+        Elapsed = NvOsGetTimeMS() - StartTime;
+    } while (Elapsed < TimeoutMS);
+
+    if (Response != TransportCmd_Response)
+        return NvError_Timeout;
+
+    memcpy(response, s_TransportInfo.pTransmitMem, ResponseLength);
+    return NvSuccess;
+}
+
+
+static NvError NvRmPrivTransportSendMessage(NvRmDeviceHandle hDevice,
+                                            NvU32 *MessageHdr,
+                                            NvU32 MessageHdrLength,
+                                            NvU32 *Message, NvU32 MessageLength)
+{
+    NvU32 ReadData;
+
+    BUG_ON(s_TransportInfo.pTransmitMem == NULL);
+    ReadData = readl(s_TransportInfo.pTransmitMem);
+
+    // Check for clear to send
+    if (ReadData != 0)
+        return NvError_TransportMessageBoxFull;  // someone else is sending a message
+
+    memcpy(s_TransportInfo.pTransmitMem, MessageHdr, MessageHdrLength);
+    if (Message && MessageLength)
+    {
+        memcpy(s_TransportInfo.pTransmitMem + MessageHdrLength,
+               Message, MessageLength);
+    }
+    wmb();
+    NvRmPrivXpcSendMessage(s_TransportInfo.hXpc, s_TransportInfo.messageDma);
+    return NvSuccess;
+}
+
+NvError NvRmTransportSendMsgInLP0(NvRmTransportHandle hPort,
+    void *pMessageBuffer, NvU32 MessageSize)
+{
+    NvU32 ReadData;
+    NvU32 MessageHdr[3];
+
+    NV_ASSERT(pMessageBuffer);
+
+    MessageHdr[0] = TransportCmd_Message;
+    MessageHdr[1] = hPort->RemotePort;
+    MessageHdr[2] = MessageSize;
+
+    ReadData = ((volatile NvU32*)s_TransportInfo.pTransmitMem)[0];
+
+    // Check for clear to send
+    if ( ReadData != 0)
+        return NvError_TransportMessageBoxFull;  // someone else is sending a message
+
+    NvOsMemcpy(s_TransportInfo.pTransmitMem, MessageHdr, sizeof(MessageHdr));
+    if (MessageSize) {
+        NvOsMemcpy(s_TransportInfo.pTransmitMem + sizeof(MessageHdr),
+            pMessageBuffer, MessageSize);
+    }
+    NvOsFlushWriteCombineBuffer();
+
+    NvRmPrivXpcSendMessage(s_TransportInfo.hXpc, s_TransportInfo.messageDma);
+    return NvSuccess;
+}
+
+static void NvRmPrivTransportClearSend(NvRmDeviceHandle hDevice)
+{
+    writel(TransportCmd_None, s_TransportInfo.pTransmitMem);
+}
+
+/**
+ * Make the connection to the other end.
+ * Thread Safety: It is done inside the function.
+ */
+NvError NvRmTransportConnect(NvRmTransportHandle hPort, NvU32 TimeoutMS)
+{
+    NvRmTransportHandle hPartnerPort;
+    NvU32               StartTime;
+    NvU32               CurrentTime;
+    NvU32               ConnectMessage[ MAX_PORT_NAME_LENGTH/4 + 3];
+    NvError             err;
+
+
+    // Look and see if there is a local port with the same name that is currently waiting, if there is
+    // mark both ports as connected.
+
+    NV_ASSERT(hPort);
+    NV_ASSERT(hPort->hRmDevice);
+    NV_ASSERT(hPort->State == PortState_Open);
+
+
+    StartTime = NvOsGetTimeMS();
+    for (;;)
+    {
+        // Someone is waiting for a connection here locally.
+        NvOsMutexLock(s_TransportInfo.mutex);
+
+        hPartnerPort = hPort->hConnectedPort;
+        if (hPartnerPort)
+        {
+            // Found a local connection
+            if (hPartnerPort->State == PortState_Waiting)
+            {
+
+                hPartnerPort->State = PortState_Connected;
+                hPartnerPort->hConnectedPort = hPort;
+
+                hPort->State = PortState_Connected;
+                NvOsSemaphoreSignal(hPartnerPort->hOnConnectSem);
+                break;
+            }
+        }
+        else if (s_TransportInfo.pReceiveMem)
+        {
+            ConnectMessage[0] = TransportCmd_Connect;
+            ConnectMessage[1] = (NvU32)hPort;
+            NvOsMemcpy(&ConnectMessage[2], hPort->PortName, MAX_PORT_NAME_LENGTH);
+
+            err = NvRmPrivTransportSendMessage(hPort->hRmDevice,
+                      ConnectMessage, sizeof(ConnectMessage), NULL, 0);
+            if (!err)
+            {
+                // should send back 2 words of data.  Give remote side 1000ms to respond, which should be about 100x more
+                // than it needs.
+                NvU32 WaitTime = NV_MAX(1000, TimeoutMS);
+                if (TimeoutMS == NV_WAIT_INFINITE)
+                    TimeoutMS = NV_WAIT_INFINITE;
+
+                // !!! Note, we can do this without holding the mutex...
+                err = NvRmPrivTransportWaitResponse(hPort->hRmDevice, ConnectMessage, 2*sizeof(NvU32), WaitTime);
+                NvRmPrivTransportClearSend(hPort->hRmDevice);
+                if (err)
+                {
+                    // the other side is not responding to messages, doh!
+                    NvOsMutexUnlock(s_TransportInfo.mutex);
+                    return NvError_TransportConnectionFailed;
+                }
+
+                // check the response
+                hPort->RemotePort = ConnectMessage[1];
+                if (hPort->RemotePort != 0)
+                {
+                    hPort->State = PortState_Connected;
+                    break;
+                }
+            }
+        }
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        NV_ASSERT(hPort->State == PortState_Open);  // it better still be open
+
+        // Didn't find a connection, wait a few ms and then try again
+        CurrentTime = NvOsGetTimeMS();
+        if ( (CurrentTime - StartTime) > TimeoutMS )
+            return NvError_Timeout;
+
+        NvOsSleepMS(10);
+    }
+
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+    return NvSuccess;
+}
+
+
+/**
+ * Set the queue depth and message size of the transport handle.
+ * Thread Safety: It is done inside the function.
+ */
+NvError NvRmTransportSetQueueDepth(
+    NvRmTransportHandle hPort,
+    NvU32 MaxQueueDepth,
+    NvU32 MaxMessageSize)
+{
+    RmReceiveMessage *pNewReceiveMsg = NULL;
+
+    NV_ASSERT(hPort != NULL);
+    NV_ASSERT(MaxQueueDepth != 0);
+    NV_ASSERT(MaxMessageSize != 0);
+
+    // You cannot change the queue after a connection has been opened
+    NV_ASSERT(hPort->State == PortState_Open);
+
+    // !!! FIXME
+    // Xpc does not allow changing the base message size, so we can't change the message size here (yet!)
+    // Once we have per port message buffers we can set this.
+    NV_ASSERT(MaxMessageSize <= MAX_MESSAGE_LENGTH);
+
+    // These are statically allocated ports, they cannot be modified!
+    // !!! FIXME: this is just a sanity check.  Remove this and make it so that
+    //            cpu/avp rpc doesn't call this function and just knows that the
+    //            transport will give it a port with a large enough queue to support
+    //            rpc, since rpc ports and queue are statically allocated this has to be true.
+    if (hPort == &s_RpcAvpPortStruct ||
+        hPort == &s_RpcCpuPortStruct)
+    {
+        if (MaxMessageSize <= MAX_MESSAGE_LENGTH &&
+            MaxQueueDepth <= MAX_MESSAGE_DEPTH)
+        {
+            return NvSuccess;
+        }
+
+        NV_ASSERT(!" Illegal meesage length or queue depth. ");
+    }
+
+    // Freeing default allocated message queue.
+    NvOsFree(hPort->RecvMessageQueue.pReceiveMsg);
+    hPort->RecvMessageQueue.pReceiveMsg = NULL;
+    // create a new message queue struct, one longer than requested on purpose.
+    pNewReceiveMsg = NvOsAlloc( sizeof(RmReceiveMessage) * (MaxQueueDepth+1));
+    if (pNewReceiveMsg == NULL)
+        return NvError_InsufficientMemory;
+
+    hPort->RecvMessageQueue.pReceiveMsg = pNewReceiveMsg;
+    hPort->RecvMessageQueue.QueueSize = (NvU16)(MaxQueueDepth+1);
+
+    return NvSuccess;
+}
+
+
+static NvError
+NvRmPrivTransportSendRemoteMsg(
+    NvRmTransportHandle hPort,
+    void* pMessageBuffer,
+    NvU32 MessageSize,
+    NvU32 TimeoutMS)
+{
+    NvError err;
+    NvU32 StartTime;
+    NvU32 CurrentTime;
+    NvU32 MessageHdr[3];
+    NvU32 JiffyTime = jiffies_to_msecs(1);
+
+    NV_ASSERT((MAX_MESSAGE_LENGTH) >= MessageSize);
+
+    StartTime = NvOsGetTimeMS();
+
+    MessageHdr[0] = TransportCmd_Message;
+    MessageHdr[1] = hPort->RemotePort;
+    MessageHdr[2] = MessageSize;
+
+    for (;;)
+    {
+        NvOsMutexLock(s_TransportInfo.mutex);
+        err = NvRmPrivTransportSendMessage(hPort->hRmDevice,
+                  MessageHdr, sizeof(MessageHdr),
+                  pMessageBuffer, MessageSize);
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        if (err == NvSuccess)
+        {
+            return NvSuccess;
+        }
+
+        // Sleep and then try again in a few ms to send again
+        CurrentTime = NvOsGetTimeMS();
+        if ( TimeoutMS != NV_WAIT_INFINITE && (CurrentTime - StartTime) > TimeoutMS )
+            return NvError_Timeout;
+        /* Sleeping for 1msec may not sleep exactly for 1msec. It depends
+         * on OS jiffy(tick) time. If jiffy time is much bigger,then this 1msec
+         * sleep would cause performance issues. At the same time, if complete
+         * polling is used, it can potentially block other threads from running.
+         * To reduce the impact of sleep in either ways, poll for one jiffy time
+         * and if operation is not complete then start sleeping.
+         */
+        if ( (CurrentTime - StartTime) > JiffyTime )
+            NvOsSleepMS(1); // try again later...
+    }
+}
+
+
+
+static NvError
+NvRmPrivTransportSendLocalMsg(
+    NvRmTransportHandle hPort,
+    void* pMessageBuffer,
+    NvU32 MessageSize,
+    NvU32 TimeoutMS)
+{
+    NvU32  CurrentTime;
+    NvU32  StartTime;
+    NvError err            = NvSuccess;
+    NvU32 JiffyTime = jiffies_to_msecs(1);
+
+    NvRmTransportHandle hRemotePort;
+
+    NvOsMutexLock(s_TransportInfo.mutex);
+    hRemotePort = hPort->hConnectedPort;
+
+
+    StartTime = NvOsGetTimeMS();
+    CurrentTime = StartTime;
+
+    for (;;)
+    {
+        // try to insert into the message into the receivers queue.
+        NvBool bSuccess = InsertMessage(hRemotePort, (NvU8*)pMessageBuffer, MessageSize);
+        if (bSuccess)
+        {
+            if (hRemotePort->hOnPushMsgSem)
+                NvOsSemaphoreSignal(hRemotePort->hOnPushMsgSem);
+            break;
+        }
+
+        // The destination port is full.
+        if (TimeoutMS == 0)
+        {
+            err = NvError_TransportMessageBoxFull;
+            break;
+        }
+
+        // The user wants a timeout, so we just sleep a short time so the
+        // other thread can pop a message.  It would be better to use another semaphore
+        // to indicate that the box is not full, but that just seems overkill since this
+        // should rarely happen anyhow.
+        // unlock the mutex, and wait a small amount of time.
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+
+        /* Sleeping for 1msec may not sleep exactly for 1msec. It depends
+         * on OS jiffy(tick) time. If jiffy time is much bigger,then this 1msec
+         * sleep would cause performance issues. At the same time, if complete
+         * polling is used, it can potentially block other threads from running.
+         * To reduce the impact of sleep in either ways, poll for one jiffy time
+         * and if operation is not complete then start sleeping.
+         */
+        if ( (CurrentTime - StartTime) > JiffyTime )
+            NvOsSleepMS(1);
+        NvOsMutexLock(s_TransportInfo.mutex);
+        if (TimeoutMS != NV_WAIT_INFINITE)
+        {
+            // check for a timeout condition.
+            CurrentTime = NvOsGetTimeMS();
+            if ( (CurrentTime - StartTime) >= TimeoutMS)
+            {
+                err = NvError_Timeout;
+                break;
+            }
+        }
+    }
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+
+    return err;
+}
+
+
+/**
+ * Send the message to the other end port.
+ * Thread Safety: It is done inside the function.
+ */
+NvError
+NvRmTransportSendMsg(
+    NvRmTransportHandle hPort,
+    void* pMessageBuffer,
+    NvU32 MessageSize,
+    NvU32 TimeoutMS)
+{
+    NvError err;
+
+    NV_ASSERT(hPort);
+    NV_ASSERT(hPort->State == PortState_Connected);
+    NV_ASSERT(pMessageBuffer);
+
+#if LOOPBACK_PROFILE
+    if (hPort->bLoopTest)
+    {
+# if NV_IS_AVP
+        ((NvU32*)pMessageBuffer)[LOOP_AVP_SEND_INDEX] = *s_TransportInfo.pTimer;
+# else
+        ((NvU32*)pMessageBuffer)[LOOP_CPU_SEND_INDEX] = *s_TransportInfo.pTimer;
+# endif
+    }
+#endif
+
+    if (hPort->hConnectedPort)
+    {
+        err = NvRmPrivTransportSendLocalMsg(hPort, pMessageBuffer, MessageSize, TimeoutMS);
+    }
+    else if (hPort->State == PortState_Connected)
+    {
+        err = NvRmPrivTransportSendRemoteMsg(hPort, pMessageBuffer, MessageSize, TimeoutMS);
+    }
+    else
+    {
+        NV_ASSERT(0);  // someone did something naughty
+        err = NvError_TransportNotConnected;
+    }
+
+    return err;
+}
+
+
+
+/**
+ * Receive the message from the other end port.
+ * Thread Safety: It is done inside the function.
+ */
+NvError
+NvRmTransportRecvMsg(
+    NvRmTransportHandle hPort,
+    void* pMessageBuffer,
+    NvU32 MaxSize,
+    NvU32 *pMessageSize)
+{
+    NV_ASSERT(hPort);
+    NV_ASSERT( (hPort->State == PortState_Connected) || (hPort->State == PortState_Disconnected) );
+    NV_ASSERT(pMessageBuffer);
+    NV_ASSERT(pMessageSize);
+
+
+    *pMessageSize = 0;
+    NvOsMutexLock(s_TransportInfo.mutex);
+    if (hPort->RecvMessageQueue.ReadIndex == hPort->RecvMessageQueue.WriteIndex)
+    {
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        return NvError_TransportMessageBoxEmpty;
+    }
+
+    ExtractMessage(hPort, (NvU8*)pMessageBuffer, pMessageSize, MaxSize);
+    if (*pMessageSize > MaxSize)
+    {
+        // not enough room to copy the message
+        NvOsMutexUnlock(s_TransportInfo.mutex);
+        NV_ASSERT(!" RM Transport: Illegal message size. ");
+        return NvError_InvalidSize;
+    }
+
+
+    // if there was backpressure asserted, try to handle the currently posted message, and re-enable messages
+    if (s_TransportInfo.ReceiveBackPressureOn != s_TransportInfo.ReceiveBackPressureOff)
+    {
+        NV_ASSERT( ((NvU8)s_TransportInfo.ReceiveBackPressureOn) == ((NvU8)(s_TransportInfo.ReceiveBackPressureOff+1)) );
+        ++s_TransportInfo.ReceiveBackPressureOff;
+
+        BUG_ON(s_TransportInfo.pReceiveMem == NULL);
+        HandlePortMessage(hPort->hRmDevice, (NvU32*)s_TransportInfo.pReceiveMem);
+    }
+
+#if LOOPBACK_PROFILE
+    if (hPort->bLoopTest)
+    {
+# if NV_IS_AVP
+        ((NvU32*)pMessageBuffer)[LOOP_AVP_RECV_INDEX] = *s_TransportInfo.pTimer;
+# else
+        ((NvU32*)pMessageBuffer)[LOOP_CPU_RECV_INDEX] = *s_TransportInfo.pTimer;
+# endif
+    }
+#endif
+
+    NvOsMutexUnlock(s_TransportInfo.mutex);
+
+    return NvSuccess;
+}
+
+void
+NvRmTransportGetPortName(
+    NvRmTransportHandle hPort,
+    NvU8 *PortName,
+    NvU32 PortNameSize )
+{
+    NvU32 len;
+
+    NV_ASSERT(hPort);
+    NV_ASSERT(PortName);
+
+    len = NvOsStrlen(hPort->PortName);
+    if (len >= PortNameSize)
+    {
+        NV_ASSERT(!" RM Transport: Port Name too long. ");
+    }
+
+    NvOsStrncpy((char *)PortName, hPort->PortName, PortNameSize);
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/Makefile b/arch/arm/mach-tegra/nv/nvrm/dispatch/Makefile
new file mode 100644
index 000000000000..8dbf0732ae53
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/Makefile
@@ -0,0 +1,31 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+ccflags-y += -Iarch/arm/mach-tegra/nv/include
+
+obj-y += NvRm_Dispatch.o
+#obj-y += nvrm_analog_dispatch.o
+#obj-y += nvrm_diag_dispatch.o
+#obj-y += nvrm_dma_dispatch.o
+#obj-y += nvrm_gpio_dispatch.o
+#obj-y += nvrm_i2c_dispatch.o
+#obj-y += nvrm_owr_dispatch.o
+#obj-y += nvrm_pwm_dispatch.o
+#obj-y += nvrm_init_dispatch.o
+#obj-y += nvrm_interrupt_dispatch.o
+#obj-y += nvrm_memmgr_dispatch.o
+obj-y += nvrm_module_dispatch.o
+#obj-y += nvrm_pinmux_dispatch.o
+obj-y += nvrm_power_dispatch.o
+#obj-y += nvrm_spi_dispatch.o
+#obj-y += nvrm_pmu_dispatch.o
+#obj-y += nvrm_keylist_dispatch.o
+#obj-y += nvrm_pcie_dispatch.o
+#obj-y += nvrm_memctrl_dispatch.o
+obj-y += nvrm_transport_dispatch.o
+#obj-y += nvrm_xpc_dispatch.o
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/NvRm_Dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/NvRm_Dispatch.c
new file mode 100644
index 000000000000..70181e8275e0
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/NvRm_Dispatch.c
@@ -0,0 +1,264 @@
+/*
+ * Copyright (c) 2009-2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <linux/kernel.h>
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvidlcmd.h"
+#include "nvreftrack.h"
+#include "nvrm_xpc.h"
+#include "nvrm_transport.h"
+#include "nvrm_memctrl.h"
+#include "nvrm_pcie.h"
+#include "nvrm_pwm.h"
+#include "nvrm_keylist.h"
+#include "nvrm_pmu.h"
+#include "nvrm_diag.h"
+#include "nvrm_pinmux.h"
+#include "nvrm_analog.h"
+#include "nvrm_owr.h"
+#include "nvrm_i2c.h"
+#include "nvrm_spi.h"
+#include "nvrm_interrupt.h"
+#include "nvrm_dma.h"
+#include "nvrm_power.h"
+#include "nvrm_gpio.h"
+#include "nvrm_module.h"
+#include "nvrm_memmgr.h"
+#include "nvrm_init.h"
+NvError nvrm_xpc_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_transport_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_memctrl_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pcie_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pwm_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_keylist_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pmu_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_diag_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pinmux_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_analog_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_owr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_i2c_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_spi_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_interrupt_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_dma_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_power_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_gpio_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_module_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_memmgr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_init_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+
+NvError nvrm_xpc_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_memctrl_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_pcie_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_pwm_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_keylist_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_pmu_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_diag_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_pinmux_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_analog_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_owr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_i2c_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_spi_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_interrupt_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_dma_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_gpio_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_memmgr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+NvError nvrm_init_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+	printk("NVRM: %s %d\n", __func__, function);
+	return NvSuccess;
+}
+
+// NvRm Package
+typedef enum
+{
+    NvRm_Invalid = 0,
+    NvRm_nvrm_xpc,
+    NvRm_nvrm_transport,
+    NvRm_nvrm_memctrl,
+    NvRm_nvrm_pcie,
+    NvRm_nvrm_pwm,
+    NvRm_nvrm_keylist,
+    NvRm_nvrm_pmu,
+    NvRm_nvrm_diag,
+    NvRm_nvrm_pinmux,
+    NvRm_nvrm_analog,
+    NvRm_nvrm_owr,
+    NvRm_nvrm_i2c,
+    NvRm_nvrm_spi,
+    NvRm_nvrm_interrupt,
+    NvRm_nvrm_dma,
+    NvRm_nvrm_power,
+    NvRm_nvrm_gpio,
+    NvRm_nvrm_module,
+    NvRm_nvrm_memmgr,
+    NvRm_nvrm_init,
+    NvRm_Num,
+    NvRm_Force32 = 0x7FFFFFFF,
+} NvRm;
+
+typedef NvError (* NvIdlDispatchFunc)( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+
+typedef struct NvIdlDispatchTableRec
+{
+    NvU32 PackageId;
+    NvIdlDispatchFunc DispFunc;
+} NvIdlDispatchTable;
+
+static NvIdlDispatchTable gs_DispatchTable[] =
+{
+    { NvRm_nvrm_xpc, nvrm_xpc_Dispatch },
+    { NvRm_nvrm_transport, nvrm_transport_Dispatch },
+    { NvRm_nvrm_memctrl, nvrm_memctrl_Dispatch },
+    { NvRm_nvrm_pcie, nvrm_pcie_Dispatch },
+    { NvRm_nvrm_pwm, nvrm_pwm_Dispatch },
+    { NvRm_nvrm_keylist, nvrm_keylist_Dispatch },
+    { NvRm_nvrm_pmu, nvrm_pmu_Dispatch },
+    { NvRm_nvrm_diag, nvrm_diag_Dispatch },
+    { NvRm_nvrm_pinmux, nvrm_pinmux_Dispatch },
+    { NvRm_nvrm_analog, nvrm_analog_Dispatch },
+    { NvRm_nvrm_owr, nvrm_owr_Dispatch },
+    { NvRm_nvrm_i2c, nvrm_i2c_Dispatch },
+    { NvRm_nvrm_spi, nvrm_spi_Dispatch },
+    { NvRm_nvrm_interrupt, nvrm_interrupt_Dispatch },
+    { NvRm_nvrm_dma, nvrm_dma_Dispatch },
+    { NvRm_nvrm_power, nvrm_power_Dispatch },
+    { NvRm_nvrm_gpio, nvrm_gpio_Dispatch },
+    { NvRm_nvrm_module, nvrm_module_Dispatch },
+    { NvRm_nvrm_memmgr, nvrm_memmgr_Dispatch },
+    { NvRm_nvrm_init, nvrm_init_Dispatch },
+    { 0 },
+};
+
+NvError NvRm_Dispatch( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvU32 packid_;
+    NvU32 funcid_;
+    NvIdlDispatchTable *table_;
+
+    NV_ASSERT( InBuffer );
+    NV_ASSERT( OutBuffer );
+
+    packid_ = ((NvU32 *)InBuffer)[0];
+    funcid_ = ((NvU32 *)InBuffer)[1];
+    table_ = gs_DispatchTable;
+
+    if ( packid_-1 >= NV_ARRAY_SIZE(gs_DispatchTable) ||
+         !table_[packid_ - 1].DispFunc )
+        return NvError_IoctlFailed;
+
+    return table_[packid_ - 1].DispFunc( funcid_, InBuffer, InSize,
+        OutBuffer, OutSize, Ctx );
+}
+
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_analog_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_analog_dispatch.c
new file mode 100644
index 000000000000..a94b79914907
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_analog_dispatch.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_analog.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmUsbDetectChargerState_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 wait;
+} NV_ALIGN(4) NvRmUsbDetectChargerState_in;
+
+typedef struct NvRmUsbDetectChargerState_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmUsbDetectChargerState_inout;
+
+typedef struct NvRmUsbDetectChargerState_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmUsbDetectChargerState_out;
+
+typedef struct NvRmUsbDetectChargerState_params_t
+{
+    NvRmUsbDetectChargerState_in in;
+    NvRmUsbDetectChargerState_inout inout;
+    NvRmUsbDetectChargerState_out out;
+} NvRmUsbDetectChargerState_params;
+
+typedef struct NvRmUsbIsConnected_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmUsbIsConnected_in;
+
+typedef struct NvRmUsbIsConnected_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmUsbIsConnected_inout;
+
+typedef struct NvRmUsbIsConnected_out_t
+{
+    NvBool ret_;
+} NV_ALIGN(4) NvRmUsbIsConnected_out;
+
+typedef struct NvRmUsbIsConnected_params_t
+{
+    NvRmUsbIsConnected_in in;
+    NvRmUsbIsConnected_inout inout;
+    NvRmUsbIsConnected_out out;
+} NvRmUsbIsConnected_params;
+
+typedef struct NvRmAnalogGetTvDacConfiguration_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmAnalogTvDacType Type;
+} NV_ALIGN(4) NvRmAnalogGetTvDacConfiguration_in;
+
+typedef struct NvRmAnalogGetTvDacConfiguration_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmAnalogGetTvDacConfiguration_inout;
+
+typedef struct NvRmAnalogGetTvDacConfiguration_out_t
+{
+    NvU8 ret_;
+} NV_ALIGN(4) NvRmAnalogGetTvDacConfiguration_out;
+
+typedef struct NvRmAnalogGetTvDacConfiguration_params_t
+{
+    NvRmAnalogGetTvDacConfiguration_in in;
+    NvRmAnalogGetTvDacConfiguration_inout inout;
+    NvRmAnalogGetTvDacConfiguration_out out;
+} NvRmAnalogGetTvDacConfiguration_params;
+
+typedef struct NvRmAnalogInterfaceControl_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmAnalogInterface Interface;
+    NvBool Enable;
+    void* Config;
+    NvU32 ConfigLength;
+} NV_ALIGN(4) NvRmAnalogInterfaceControl_in;
+
+typedef struct NvRmAnalogInterfaceControl_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmAnalogInterfaceControl_inout;
+
+typedef struct NvRmAnalogInterfaceControl_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmAnalogInterfaceControl_out;
+
+typedef struct NvRmAnalogInterfaceControl_params_t
+{
+    NvRmAnalogInterfaceControl_in in;
+    NvRmAnalogInterfaceControl_inout inout;
+    NvRmAnalogInterfaceControl_out out;
+} NvRmAnalogInterfaceControl_params;
+
+static NvError NvRmUsbDetectChargerState_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmUsbDetectChargerState_in *p_in;
+    NvRmUsbDetectChargerState_out *p_out;
+
+    p_in = (NvRmUsbDetectChargerState_in *)InBuffer;
+    p_out = (NvRmUsbDetectChargerState_out *)((NvU8 *)OutBuffer + OFFSET(NvRmUsbDetectChargerState_params, out) - OFFSET(NvRmUsbDetectChargerState_params, inout));
+
+
+    p_out->ret_ = NvRmUsbDetectChargerState( p_in->hDevice, p_in->wait );
+
+    return err_;
+}
+
+static NvError NvRmUsbIsConnected_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmUsbIsConnected_in *p_in;
+    NvRmUsbIsConnected_out *p_out;
+
+    p_in = (NvRmUsbIsConnected_in *)InBuffer;
+    p_out = (NvRmUsbIsConnected_out *)((NvU8 *)OutBuffer + OFFSET(NvRmUsbIsConnected_params, out) - OFFSET(NvRmUsbIsConnected_params, inout));
+
+
+    p_out->ret_ = NvRmUsbIsConnected( p_in->hDevice );
+
+    return err_;
+}
+
+static NvError NvRmAnalogGetTvDacConfiguration_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmAnalogGetTvDacConfiguration_in *p_in;
+    NvRmAnalogGetTvDacConfiguration_out *p_out;
+
+    p_in = (NvRmAnalogGetTvDacConfiguration_in *)InBuffer;
+    p_out = (NvRmAnalogGetTvDacConfiguration_out *)((NvU8 *)OutBuffer + OFFSET(NvRmAnalogGetTvDacConfiguration_params, out) - OFFSET(NvRmAnalogGetTvDacConfiguration_params, inout));
+
+
+    p_out->ret_ = NvRmAnalogGetTvDacConfiguration( p_in->hDevice, p_in->Type );
+
+    return err_;
+}
+
+static NvError NvRmAnalogInterfaceControl_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmAnalogInterfaceControl_in *p_in;
+    NvRmAnalogInterfaceControl_out *p_out;
+    void*  Config = NULL;
+
+    p_in = (NvRmAnalogInterfaceControl_in *)InBuffer;
+    p_out = (NvRmAnalogInterfaceControl_out *)((NvU8 *)OutBuffer + OFFSET(NvRmAnalogInterfaceControl_params, out) - OFFSET(NvRmAnalogInterfaceControl_params, inout));
+
+    if( p_in->ConfigLength && p_in->Config )
+    {
+        Config = (void*  )NvOsAlloc( p_in->ConfigLength );
+        if( !Config )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Config )
+        {
+            err_ = NvOsCopyIn( Config, p_in->Config, p_in->ConfigLength );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmAnalogInterfaceControl( p_in->hDevice, p_in->Interface, p_in->Enable, Config, p_in->ConfigLength );
+
+    if(p_in->Config && Config)
+    {
+        err_ = NvOsCopyOut( p_in->Config, Config, p_in->ConfigLength );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( Config );
+    return err_;
+}
+
+NvError nvrm_analog_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_analog_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 3:
+        err_ = NvRmUsbDetectChargerState_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmUsbIsConnected_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmAnalogGetTvDacConfiguration_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmAnalogInterfaceControl_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_diag_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_diag_dispatch.c
new file mode 100644
index 000000000000..b521ca38d815
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_diag_dispatch.c
@@ -0,0 +1,1078 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_diag.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmDiagGetTemperature_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmTmonZoneId ZoneId;
+} NV_ALIGN(4) NvRmDiagGetTemperature_in;
+
+typedef struct NvRmDiagGetTemperature_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagGetTemperature_inout;
+
+typedef struct NvRmDiagGetTemperature_out_t
+{
+    NvError ret_;
+    NvS32 pTemperatureC;
+} NV_ALIGN(4) NvRmDiagGetTemperature_out;
+
+typedef struct NvRmDiagGetTemperature_params_t
+{
+    NvRmDiagGetTemperature_in in;
+    NvRmDiagGetTemperature_inout inout;
+    NvRmDiagGetTemperature_out out;
+} NvRmDiagGetTemperature_params;
+
+typedef struct NvRmDiagIsLockSupported_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+} NV_ALIGN(4) NvRmDiagIsLockSupported_in;
+
+typedef struct NvRmDiagIsLockSupported_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagIsLockSupported_inout;
+
+typedef struct NvRmDiagIsLockSupported_out_t
+{
+    NvBool ret_;
+} NV_ALIGN(4) NvRmDiagIsLockSupported_out;
+
+typedef struct NvRmDiagIsLockSupported_params_t
+{
+    NvRmDiagIsLockSupported_in in;
+    NvRmDiagIsLockSupported_inout inout;
+    NvRmDiagIsLockSupported_out out;
+} NvRmDiagIsLockSupported_params;
+
+typedef struct NvRmDiagConfigurePowerRail_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagPowerRailHandle hRail;
+    NvU32 VoltageMV;
+} NV_ALIGN(4) NvRmDiagConfigurePowerRail_in;
+
+typedef struct NvRmDiagConfigurePowerRail_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagConfigurePowerRail_inout;
+
+typedef struct NvRmDiagConfigurePowerRail_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagConfigurePowerRail_out;
+
+typedef struct NvRmDiagConfigurePowerRail_params_t
+{
+    NvRmDiagConfigurePowerRail_in in;
+    NvRmDiagConfigurePowerRail_inout inout;
+    NvRmDiagConfigurePowerRail_out out;
+} NvRmDiagConfigurePowerRail_params;
+
+typedef struct NvRmDiagModuleListPowerRails_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID id;
+    NvRmDiagPowerRailHandle  * phRailList;
+} NV_ALIGN(4) NvRmDiagModuleListPowerRails_in;
+
+typedef struct NvRmDiagModuleListPowerRails_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagModuleListPowerRails_inout;
+
+typedef struct NvRmDiagModuleListPowerRails_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagModuleListPowerRails_out;
+
+typedef struct NvRmDiagModuleListPowerRails_params_t
+{
+    NvRmDiagModuleListPowerRails_in in;
+    NvRmDiagModuleListPowerRails_inout inout;
+    NvRmDiagModuleListPowerRails_out out;
+} NvRmDiagModuleListPowerRails_params;
+
+typedef struct NvRmDiagPowerRailGetName_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagPowerRailHandle hRail;
+} NV_ALIGN(4) NvRmDiagPowerRailGetName_in;
+
+typedef struct NvRmDiagPowerRailGetName_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagPowerRailGetName_inout;
+
+typedef struct NvRmDiagPowerRailGetName_out_t
+{
+    NvU64 ret_;
+} NV_ALIGN(4) NvRmDiagPowerRailGetName_out;
+
+typedef struct NvRmDiagPowerRailGetName_params_t
+{
+    NvRmDiagPowerRailGetName_in in;
+    NvRmDiagPowerRailGetName_inout inout;
+    NvRmDiagPowerRailGetName_out out;
+} NvRmDiagPowerRailGetName_params;
+
+typedef struct NvRmDiagListPowerRails_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagPowerRailHandle  * phRailList;
+} NV_ALIGN(4) NvRmDiagListPowerRails_in;
+
+typedef struct NvRmDiagListPowerRails_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagListPowerRails_inout;
+
+typedef struct NvRmDiagListPowerRails_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagListPowerRails_out;
+
+typedef struct NvRmDiagListPowerRails_params_t
+{
+    NvRmDiagListPowerRails_in in;
+    NvRmDiagListPowerRails_inout inout;
+    NvRmDiagListPowerRails_out out;
+} NvRmDiagListPowerRails_params;
+
+typedef struct NvRmDiagModuleReset_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID id;
+    NvBool KeepAsserted;
+} NV_ALIGN(4) NvRmDiagModuleReset_in;
+
+typedef struct NvRmDiagModuleReset_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagModuleReset_inout;
+
+typedef struct NvRmDiagModuleReset_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagModuleReset_out;
+
+typedef struct NvRmDiagModuleReset_params_t
+{
+    NvRmDiagModuleReset_in in;
+    NvRmDiagModuleReset_inout inout;
+    NvRmDiagModuleReset_out out;
+} NvRmDiagModuleReset_params;
+
+typedef struct NvRmDiagClockScalerConfigure_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hScaler;
+    NvRmDiagClockSourceHandle hInput;
+    NvU32 M;
+    NvU32 N;
+} NV_ALIGN(4) NvRmDiagClockScalerConfigure_in;
+
+typedef struct NvRmDiagClockScalerConfigure_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagClockScalerConfigure_inout;
+
+typedef struct NvRmDiagClockScalerConfigure_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagClockScalerConfigure_out;
+
+typedef struct NvRmDiagClockScalerConfigure_params_t
+{
+    NvRmDiagClockScalerConfigure_in in;
+    NvRmDiagClockScalerConfigure_inout inout;
+    NvRmDiagClockScalerConfigure_out out;
+} NvRmDiagClockScalerConfigure_params;
+
+typedef struct NvRmDiagPllConfigure_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hPll;
+    NvU32 M;
+    NvU32 N;
+    NvU32 P;
+} NV_ALIGN(4) NvRmDiagPllConfigure_in;
+
+typedef struct NvRmDiagPllConfigure_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagPllConfigure_inout;
+
+typedef struct NvRmDiagPllConfigure_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagPllConfigure_out;
+
+typedef struct NvRmDiagPllConfigure_params_t
+{
+    NvRmDiagPllConfigure_in in;
+    NvRmDiagPllConfigure_inout inout;
+    NvRmDiagPllConfigure_out out;
+} NvRmDiagPllConfigure_params;
+
+typedef struct NvRmDiagOscillatorGetFreq_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hOscillator;
+} NV_ALIGN(4) NvRmDiagOscillatorGetFreq_in;
+
+typedef struct NvRmDiagOscillatorGetFreq_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagOscillatorGetFreq_inout;
+
+typedef struct NvRmDiagOscillatorGetFreq_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmDiagOscillatorGetFreq_out;
+
+typedef struct NvRmDiagOscillatorGetFreq_params_t
+{
+    NvRmDiagOscillatorGetFreq_in in;
+    NvRmDiagOscillatorGetFreq_inout inout;
+    NvRmDiagOscillatorGetFreq_out out;
+} NvRmDiagOscillatorGetFreq_params;
+
+typedef struct NvRmDiagClockSourceListSources_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hSource;
+    NvRmDiagClockSourceHandle  * phSourceList;
+} NV_ALIGN(4) NvRmDiagClockSourceListSources_in;
+
+typedef struct NvRmDiagClockSourceListSources_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagClockSourceListSources_inout;
+
+typedef struct NvRmDiagClockSourceListSources_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagClockSourceListSources_out;
+
+typedef struct NvRmDiagClockSourceListSources_params_t
+{
+    NvRmDiagClockSourceListSources_in in;
+    NvRmDiagClockSourceListSources_inout inout;
+    NvRmDiagClockSourceListSources_out out;
+} NvRmDiagClockSourceListSources_params;
+
+typedef struct NvRmDiagClockSourceGetScaler_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hSource;
+} NV_ALIGN(4) NvRmDiagClockSourceGetScaler_in;
+
+typedef struct NvRmDiagClockSourceGetScaler_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetScaler_inout;
+
+typedef struct NvRmDiagClockSourceGetScaler_out_t
+{
+    NvRmDiagClockScalerType ret_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetScaler_out;
+
+typedef struct NvRmDiagClockSourceGetScaler_params_t
+{
+    NvRmDiagClockSourceGetScaler_in in;
+    NvRmDiagClockSourceGetScaler_inout inout;
+    NvRmDiagClockSourceGetScaler_out out;
+} NvRmDiagClockSourceGetScaler_params;
+
+typedef struct NvRmDiagClockSourceGetType_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hSource;
+} NV_ALIGN(4) NvRmDiagClockSourceGetType_in;
+
+typedef struct NvRmDiagClockSourceGetType_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetType_inout;
+
+typedef struct NvRmDiagClockSourceGetType_out_t
+{
+    NvRmDiagClockSourceType ret_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetType_out;
+
+typedef struct NvRmDiagClockSourceGetType_params_t
+{
+    NvRmDiagClockSourceGetType_in in;
+    NvRmDiagClockSourceGetType_inout inout;
+    NvRmDiagClockSourceGetType_out out;
+} NvRmDiagClockSourceGetType_params;
+
+typedef struct NvRmDiagClockSourceGetName_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle hSource;
+} NV_ALIGN(4) NvRmDiagClockSourceGetName_in;
+
+typedef struct NvRmDiagClockSourceGetName_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetName_inout;
+
+typedef struct NvRmDiagClockSourceGetName_out_t
+{
+    NvU64 ret_;
+} NV_ALIGN(4) NvRmDiagClockSourceGetName_out;
+
+typedef struct NvRmDiagClockSourceGetName_params_t
+{
+    NvRmDiagClockSourceGetName_in in;
+    NvRmDiagClockSourceGetName_inout inout;
+    NvRmDiagClockSourceGetName_out out;
+} NvRmDiagClockSourceGetName_params;
+
+typedef struct NvRmDiagModuleClockConfigure_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID id;
+    NvRmDiagClockSourceHandle hSource;
+    NvU32 divider;
+    NvBool Source1st;
+} NV_ALIGN(4) NvRmDiagModuleClockConfigure_in;
+
+typedef struct NvRmDiagModuleClockConfigure_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagModuleClockConfigure_inout;
+
+typedef struct NvRmDiagModuleClockConfigure_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagModuleClockConfigure_out;
+
+typedef struct NvRmDiagModuleClockConfigure_params_t
+{
+    NvRmDiagModuleClockConfigure_in in;
+    NvRmDiagModuleClockConfigure_inout inout;
+    NvRmDiagModuleClockConfigure_out out;
+} NvRmDiagModuleClockConfigure_params;
+
+typedef struct NvRmDiagModuleClockEnable_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID id;
+    NvBool enable;
+} NV_ALIGN(4) NvRmDiagModuleClockEnable_in;
+
+typedef struct NvRmDiagModuleClockEnable_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagModuleClockEnable_inout;
+
+typedef struct NvRmDiagModuleClockEnable_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagModuleClockEnable_out;
+
+typedef struct NvRmDiagModuleClockEnable_params_t
+{
+    NvRmDiagModuleClockEnable_in in;
+    NvRmDiagModuleClockEnable_inout inout;
+    NvRmDiagModuleClockEnable_out out;
+} NvRmDiagModuleClockEnable_params;
+
+typedef struct NvRmDiagModuleListClockSources_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID id;
+    NvRmDiagClockSourceHandle  * phSourceList;
+} NV_ALIGN(4) NvRmDiagModuleListClockSources_in;
+
+typedef struct NvRmDiagModuleListClockSources_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagModuleListClockSources_inout;
+
+typedef struct NvRmDiagModuleListClockSources_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagModuleListClockSources_out;
+
+typedef struct NvRmDiagModuleListClockSources_params_t
+{
+    NvRmDiagModuleListClockSources_in in;
+    NvRmDiagModuleListClockSources_inout inout;
+    NvRmDiagModuleListClockSources_out out;
+} NvRmDiagModuleListClockSources_params;
+
+typedef struct NvRmDiagListClockSources_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagClockSourceHandle  * phSourceList;
+} NV_ALIGN(4) NvRmDiagListClockSources_in;
+
+typedef struct NvRmDiagListClockSources_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagListClockSources_inout;
+
+typedef struct NvRmDiagListClockSources_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagListClockSources_out;
+
+typedef struct NvRmDiagListClockSources_params_t
+{
+    NvRmDiagListClockSources_in in;
+    NvRmDiagListClockSources_inout inout;
+    NvRmDiagListClockSources_out out;
+} NvRmDiagListClockSources_params;
+
+typedef struct NvRmDiagListModules_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDiagModuleID  * pIdList;
+} NV_ALIGN(4) NvRmDiagListModules_in;
+
+typedef struct NvRmDiagListModules_inout_t
+{
+    NvU32 pListSize;
+} NV_ALIGN(4) NvRmDiagListModules_inout;
+
+typedef struct NvRmDiagListModules_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagListModules_out;
+
+typedef struct NvRmDiagListModules_params_t
+{
+    NvRmDiagListModules_in in;
+    NvRmDiagListModules_inout inout;
+    NvRmDiagListModules_out out;
+} NvRmDiagListModules_params;
+
+typedef struct NvRmDiagEnable_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmDiagEnable_in;
+
+typedef struct NvRmDiagEnable_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDiagEnable_inout;
+
+typedef struct NvRmDiagEnable_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDiagEnable_out;
+
+typedef struct NvRmDiagEnable_params_t
+{
+    NvRmDiagEnable_in in;
+    NvRmDiagEnable_inout inout;
+    NvRmDiagEnable_out out;
+} NvRmDiagEnable_params;
+
+static NvError NvRmDiagGetTemperature_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagGetTemperature_in *p_in;
+    NvRmDiagGetTemperature_out *p_out;
+
+    p_in = (NvRmDiagGetTemperature_in *)InBuffer;
+    p_out = (NvRmDiagGetTemperature_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagGetTemperature_params, out) - OFFSET(NvRmDiagGetTemperature_params, inout));
+
+
+    p_out->ret_ = NvRmDiagGetTemperature( p_in->hRmDeviceHandle, p_in->ZoneId, &p_out->pTemperatureC );
+
+    return err_;
+}
+
+static NvError NvRmDiagIsLockSupported_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagIsLockSupported_out *p_out;
+    p_out = (NvRmDiagIsLockSupported_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagIsLockSupported_params, out) - OFFSET(NvRmDiagIsLockSupported_params, inout));
+
+
+    p_out->ret_ = NvRmDiagIsLockSupported(  );
+
+    return err_;
+}
+
+static NvError NvRmDiagConfigurePowerRail_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagConfigurePowerRail_in *p_in;
+    NvRmDiagConfigurePowerRail_out *p_out;
+
+    p_in = (NvRmDiagConfigurePowerRail_in *)InBuffer;
+    p_out = (NvRmDiagConfigurePowerRail_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagConfigurePowerRail_params, out) - OFFSET(NvRmDiagConfigurePowerRail_params, inout));
+
+
+    p_out->ret_ = NvRmDiagConfigurePowerRail( p_in->hRail, p_in->VoltageMV );
+
+    return err_;
+}
+
+static NvError NvRmDiagModuleListPowerRails_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagModuleListPowerRails_in *p_in;
+    NvRmDiagModuleListPowerRails_inout *p_inout;
+    NvRmDiagModuleListPowerRails_out *p_out;
+    NvRmDiagModuleListPowerRails_inout inout;
+    NvRmDiagPowerRailHandle *phRailList = NULL;
+
+    p_in = (NvRmDiagModuleListPowerRails_in *)InBuffer;
+    p_inout = (NvRmDiagModuleListPowerRails_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagModuleListPowerRails_params, inout));
+    p_out = (NvRmDiagModuleListPowerRails_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagModuleListPowerRails_params, out) - OFFSET(NvRmDiagModuleListPowerRails_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->phRailList )
+    {
+        phRailList = (NvRmDiagPowerRailHandle  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagPowerRailHandle  ) );
+        if( !phRailList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagModuleListPowerRails( p_in->id, &inout.pListSize, phRailList );
+
+
+    p_inout = (NvRmDiagModuleListPowerRails_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->phRailList && phRailList)
+    {
+        err_ = NvOsCopyOut( p_in->phRailList, phRailList, p_inout->pListSize * sizeof( NvRmDiagPowerRailHandle  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( phRailList );
+    return err_;
+}
+
+static NvError NvRmDiagPowerRailGetName_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagPowerRailGetName_in *p_in;
+    NvRmDiagPowerRailGetName_out *p_out;
+
+    p_in = (NvRmDiagPowerRailGetName_in *)InBuffer;
+    p_out = (NvRmDiagPowerRailGetName_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagPowerRailGetName_params, out) - OFFSET(NvRmDiagPowerRailGetName_params, inout));
+
+
+    p_out->ret_ = NvRmDiagPowerRailGetName( p_in->hRail );
+
+    return err_;
+}
+
+static NvError NvRmDiagListPowerRails_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagListPowerRails_in *p_in;
+    NvRmDiagListPowerRails_inout *p_inout;
+    NvRmDiagListPowerRails_out *p_out;
+    NvRmDiagListPowerRails_inout inout;
+    NvRmDiagPowerRailHandle *phRailList = NULL;
+
+    p_in = (NvRmDiagListPowerRails_in *)InBuffer;
+    p_inout = (NvRmDiagListPowerRails_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagListPowerRails_params, inout));
+    p_out = (NvRmDiagListPowerRails_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagListPowerRails_params, out) - OFFSET(NvRmDiagListPowerRails_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->phRailList )
+    {
+        phRailList = (NvRmDiagPowerRailHandle  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagPowerRailHandle  ) );
+        if( !phRailList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagListPowerRails( &inout.pListSize, phRailList );
+
+
+    p_inout = (NvRmDiagListPowerRails_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->phRailList && phRailList)
+    {
+        err_ = NvOsCopyOut( p_in->phRailList, phRailList, p_inout->pListSize * sizeof( NvRmDiagPowerRailHandle  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( phRailList );
+    return err_;
+}
+
+static NvError NvRmDiagModuleReset_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagModuleReset_in *p_in;
+    NvRmDiagModuleReset_out *p_out;
+
+    p_in = (NvRmDiagModuleReset_in *)InBuffer;
+    p_out = (NvRmDiagModuleReset_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagModuleReset_params, out) - OFFSET(NvRmDiagModuleReset_params, inout));
+
+
+    p_out->ret_ = NvRmDiagModuleReset( p_in->id, p_in->KeepAsserted );
+
+    return err_;
+}
+
+static NvError NvRmDiagClockScalerConfigure_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagClockScalerConfigure_in *p_in;
+    NvRmDiagClockScalerConfigure_out *p_out;
+
+    p_in = (NvRmDiagClockScalerConfigure_in *)InBuffer;
+    p_out = (NvRmDiagClockScalerConfigure_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagClockScalerConfigure_params, out) - OFFSET(NvRmDiagClockScalerConfigure_params, inout));
+
+
+    p_out->ret_ = NvRmDiagClockScalerConfigure( p_in->hScaler, p_in->hInput, p_in->M, p_in->N );
+
+    return err_;
+}
+
+static NvError NvRmDiagPllConfigure_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagPllConfigure_in *p_in;
+    NvRmDiagPllConfigure_out *p_out;
+
+    p_in = (NvRmDiagPllConfigure_in *)InBuffer;
+    p_out = (NvRmDiagPllConfigure_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagPllConfigure_params, out) - OFFSET(NvRmDiagPllConfigure_params, inout));
+
+
+    p_out->ret_ = NvRmDiagPllConfigure( p_in->hPll, p_in->M, p_in->N, p_in->P );
+
+    return err_;
+}
+
+static NvError NvRmDiagOscillatorGetFreq_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagOscillatorGetFreq_in *p_in;
+    NvRmDiagOscillatorGetFreq_out *p_out;
+
+    p_in = (NvRmDiagOscillatorGetFreq_in *)InBuffer;
+    p_out = (NvRmDiagOscillatorGetFreq_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagOscillatorGetFreq_params, out) - OFFSET(NvRmDiagOscillatorGetFreq_params, inout));
+
+
+    p_out->ret_ = NvRmDiagOscillatorGetFreq( p_in->hOscillator );
+
+    return err_;
+}
+
+static NvError NvRmDiagClockSourceListSources_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagClockSourceListSources_in *p_in;
+    NvRmDiagClockSourceListSources_inout *p_inout;
+    NvRmDiagClockSourceListSources_out *p_out;
+    NvRmDiagClockSourceListSources_inout inout;
+    NvRmDiagClockSourceHandle *phSourceList = NULL;
+
+    p_in = (NvRmDiagClockSourceListSources_in *)InBuffer;
+    p_inout = (NvRmDiagClockSourceListSources_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagClockSourceListSources_params, inout));
+    p_out = (NvRmDiagClockSourceListSources_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagClockSourceListSources_params, out) - OFFSET(NvRmDiagClockSourceListSources_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->phSourceList )
+    {
+        phSourceList = (NvRmDiagClockSourceHandle  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( !phSourceList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagClockSourceListSources( p_in->hSource, &inout.pListSize, phSourceList );
+
+
+    p_inout = (NvRmDiagClockSourceListSources_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->phSourceList && phSourceList)
+    {
+        err_ = NvOsCopyOut( p_in->phSourceList, phSourceList, p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( phSourceList );
+    return err_;
+}
+
+static NvError NvRmDiagClockSourceGetScaler_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagClockSourceGetScaler_in *p_in;
+    NvRmDiagClockSourceGetScaler_out *p_out;
+
+    p_in = (NvRmDiagClockSourceGetScaler_in *)InBuffer;
+    p_out = (NvRmDiagClockSourceGetScaler_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagClockSourceGetScaler_params, out) - OFFSET(NvRmDiagClockSourceGetScaler_params, inout));
+
+
+    p_out->ret_ = NvRmDiagClockSourceGetScaler( p_in->hSource );
+
+    return err_;
+}
+
+static NvError NvRmDiagClockSourceGetType_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagClockSourceGetType_in *p_in;
+    NvRmDiagClockSourceGetType_out *p_out;
+
+    p_in = (NvRmDiagClockSourceGetType_in *)InBuffer;
+    p_out = (NvRmDiagClockSourceGetType_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagClockSourceGetType_params, out) - OFFSET(NvRmDiagClockSourceGetType_params, inout));
+
+
+    p_out->ret_ = NvRmDiagClockSourceGetType( p_in->hSource );
+
+    return err_;
+}
+
+static NvError NvRmDiagClockSourceGetName_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagClockSourceGetName_in *p_in;
+    NvRmDiagClockSourceGetName_out *p_out;
+
+    p_in = (NvRmDiagClockSourceGetName_in *)InBuffer;
+    p_out = (NvRmDiagClockSourceGetName_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagClockSourceGetName_params, out) - OFFSET(NvRmDiagClockSourceGetName_params, inout));
+
+
+    p_out->ret_ = NvRmDiagClockSourceGetName( p_in->hSource );
+
+    return err_;
+}
+
+static NvError NvRmDiagModuleClockConfigure_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagModuleClockConfigure_in *p_in;
+    NvRmDiagModuleClockConfigure_out *p_out;
+
+    p_in = (NvRmDiagModuleClockConfigure_in *)InBuffer;
+    p_out = (NvRmDiagModuleClockConfigure_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagModuleClockConfigure_params, out) - OFFSET(NvRmDiagModuleClockConfigure_params, inout));
+
+
+    p_out->ret_ = NvRmDiagModuleClockConfigure( p_in->id, p_in->hSource, p_in->divider, p_in->Source1st );
+
+    return err_;
+}
+
+static NvError NvRmDiagModuleClockEnable_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagModuleClockEnable_in *p_in;
+    NvRmDiagModuleClockEnable_out *p_out;
+
+    p_in = (NvRmDiagModuleClockEnable_in *)InBuffer;
+    p_out = (NvRmDiagModuleClockEnable_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagModuleClockEnable_params, out) - OFFSET(NvRmDiagModuleClockEnable_params, inout));
+
+
+    p_out->ret_ = NvRmDiagModuleClockEnable( p_in->id, p_in->enable );
+
+    return err_;
+}
+
+static NvError NvRmDiagModuleListClockSources_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagModuleListClockSources_in *p_in;
+    NvRmDiagModuleListClockSources_inout *p_inout;
+    NvRmDiagModuleListClockSources_out *p_out;
+    NvRmDiagModuleListClockSources_inout inout;
+    NvRmDiagClockSourceHandle *phSourceList = NULL;
+
+    p_in = (NvRmDiagModuleListClockSources_in *)InBuffer;
+    p_inout = (NvRmDiagModuleListClockSources_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagModuleListClockSources_params, inout));
+    p_out = (NvRmDiagModuleListClockSources_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagModuleListClockSources_params, out) - OFFSET(NvRmDiagModuleListClockSources_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->phSourceList )
+    {
+        phSourceList = (NvRmDiagClockSourceHandle  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( !phSourceList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagModuleListClockSources( p_in->id, &inout.pListSize, phSourceList );
+
+
+    p_inout = (NvRmDiagModuleListClockSources_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->phSourceList && phSourceList)
+    {
+        err_ = NvOsCopyOut( p_in->phSourceList, phSourceList, p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( phSourceList );
+    return err_;
+}
+
+static NvError NvRmDiagListClockSources_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagListClockSources_in *p_in;
+    NvRmDiagListClockSources_inout *p_inout;
+    NvRmDiagListClockSources_out *p_out;
+    NvRmDiagListClockSources_inout inout;
+    NvRmDiagClockSourceHandle *phSourceList = NULL;
+
+    p_in = (NvRmDiagListClockSources_in *)InBuffer;
+    p_inout = (NvRmDiagListClockSources_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagListClockSources_params, inout));
+    p_out = (NvRmDiagListClockSources_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagListClockSources_params, out) - OFFSET(NvRmDiagListClockSources_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->phSourceList )
+    {
+        phSourceList = (NvRmDiagClockSourceHandle  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( !phSourceList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagListClockSources( &inout.pListSize, phSourceList );
+
+
+    p_inout = (NvRmDiagListClockSources_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->phSourceList && phSourceList)
+    {
+        err_ = NvOsCopyOut( p_in->phSourceList, phSourceList, p_inout->pListSize * sizeof( NvRmDiagClockSourceHandle  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( phSourceList );
+    return err_;
+}
+
+static NvError NvRmDiagListModules_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagListModules_in *p_in;
+    NvRmDiagListModules_inout *p_inout;
+    NvRmDiagListModules_out *p_out;
+    NvRmDiagListModules_inout inout;
+    NvRmDiagModuleID *pIdList = NULL;
+
+    p_in = (NvRmDiagListModules_in *)InBuffer;
+    p_inout = (NvRmDiagListModules_inout *)((NvU8 *)InBuffer + OFFSET(NvRmDiagListModules_params, inout));
+    p_out = (NvRmDiagListModules_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagListModules_params, out) - OFFSET(NvRmDiagListModules_params, inout));
+
+    (void)inout;
+    inout.pListSize = p_inout->pListSize;
+    if( p_inout->pListSize && p_in->pIdList )
+    {
+        pIdList = (NvRmDiagModuleID  *)NvOsAlloc( p_inout->pListSize * sizeof( NvRmDiagModuleID  ) );
+        if( !pIdList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDiagListModules( &inout.pListSize, pIdList );
+
+
+    p_inout = (NvRmDiagListModules_inout *)OutBuffer;
+    p_inout->pListSize = inout.pListSize;
+    if(p_in->pIdList && pIdList)
+    {
+        err_ = NvOsCopyOut( p_in->pIdList, pIdList, p_inout->pListSize * sizeof( NvRmDiagModuleID  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pIdList );
+    return err_;
+}
+
+static NvError NvRmDiagEnable_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDiagEnable_in *p_in;
+    NvRmDiagEnable_out *p_out;
+
+    p_in = (NvRmDiagEnable_in *)InBuffer;
+    p_out = (NvRmDiagEnable_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDiagEnable_params, out) - OFFSET(NvRmDiagEnable_params, inout));
+
+
+    p_out->ret_ = NvRmDiagEnable( p_in->hDevice );
+
+    return err_;
+}
+
+NvError nvrm_diag_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_diag_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 19:
+        err_ = NvRmDiagGetTemperature_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 18:
+        err_ = NvRmDiagIsLockSupported_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 17:
+        err_ = NvRmDiagConfigurePowerRail_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 16:
+        err_ = NvRmDiagModuleListPowerRails_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 15:
+        err_ = NvRmDiagPowerRailGetName_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 14:
+        err_ = NvRmDiagListPowerRails_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 13:
+        err_ = NvRmDiagModuleReset_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 12:
+        err_ = NvRmDiagClockScalerConfigure_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 11:
+        err_ = NvRmDiagPllConfigure_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 10:
+        err_ = NvRmDiagOscillatorGetFreq_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 9:
+        err_ = NvRmDiagClockSourceListSources_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 8:
+        err_ = NvRmDiagClockSourceGetScaler_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 7:
+        err_ = NvRmDiagClockSourceGetType_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmDiagClockSourceGetName_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmDiagModuleClockConfigure_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmDiagModuleClockEnable_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmDiagModuleListClockSources_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmDiagListClockSources_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmDiagListModules_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmDiagEnable_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_dma_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_dma_dispatch.c
new file mode 100644
index 000000000000..ff246393b5ef
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_dma_dispatch.c
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_dma.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmDmaIsDmaTransferCompletes_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDmaHandle hDma;
+    NvBool IsFirstHalfBuffer;
+} NV_ALIGN(4) NvRmDmaIsDmaTransferCompletes_in;
+
+typedef struct NvRmDmaIsDmaTransferCompletes_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaIsDmaTransferCompletes_inout;
+
+typedef struct NvRmDmaIsDmaTransferCompletes_out_t
+{
+    NvBool ret_;
+} NV_ALIGN(4) NvRmDmaIsDmaTransferCompletes_out;
+
+typedef struct NvRmDmaIsDmaTransferCompletes_params_t
+{
+    NvRmDmaIsDmaTransferCompletes_in in;
+    NvRmDmaIsDmaTransferCompletes_inout inout;
+    NvRmDmaIsDmaTransferCompletes_out out;
+} NvRmDmaIsDmaTransferCompletes_params;
+
+typedef struct NvRmDmaGetTransferredCount_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDmaHandle hDma;
+    NvBool IsTransferStop;
+} NV_ALIGN(4) NvRmDmaGetTransferredCount_in;
+
+typedef struct NvRmDmaGetTransferredCount_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaGetTransferredCount_inout;
+
+typedef struct NvRmDmaGetTransferredCount_out_t
+{
+    NvError ret_;
+    NvU32 pTransferCount;
+} NV_ALIGN(4) NvRmDmaGetTransferredCount_out;
+
+typedef struct NvRmDmaGetTransferredCount_params_t
+{
+    NvRmDmaGetTransferredCount_in in;
+    NvRmDmaGetTransferredCount_inout inout;
+    NvRmDmaGetTransferredCount_out out;
+} NvRmDmaGetTransferredCount_params;
+
+typedef struct NvRmDmaAbort_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDmaHandle hDma;
+} NV_ALIGN(4) NvRmDmaAbort_in;
+
+typedef struct NvRmDmaAbort_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaAbort_inout;
+
+typedef struct NvRmDmaAbort_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaAbort_out;
+
+typedef struct NvRmDmaAbort_params_t
+{
+    NvRmDmaAbort_in in;
+    NvRmDmaAbort_inout inout;
+    NvRmDmaAbort_out out;
+} NvRmDmaAbort_params;
+
+typedef struct NvRmDmaStartDmaTransfer_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDmaHandle hDma;
+    NvRmDmaClientBuffer pClientBuffer;
+    NvRmDmaDirection DmaDirection;
+    NvU32 WaitTimeoutInMilliSecond;
+    NvOsSemaphoreHandle AsynchSemaphoreId;
+} NV_ALIGN(4) NvRmDmaStartDmaTransfer_in;
+
+typedef struct NvRmDmaStartDmaTransfer_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaStartDmaTransfer_inout;
+
+typedef struct NvRmDmaStartDmaTransfer_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDmaStartDmaTransfer_out;
+
+typedef struct NvRmDmaStartDmaTransfer_params_t
+{
+    NvRmDmaStartDmaTransfer_in in;
+    NvRmDmaStartDmaTransfer_inout inout;
+    NvRmDmaStartDmaTransfer_out out;
+} NvRmDmaStartDmaTransfer_params;
+
+typedef struct NvRmDmaFree_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDmaHandle hDma;
+} NV_ALIGN(4) NvRmDmaFree_in;
+
+typedef struct NvRmDmaFree_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaFree_inout;
+
+typedef struct NvRmDmaFree_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaFree_out;
+
+typedef struct NvRmDmaFree_params_t
+{
+    NvRmDmaFree_in in;
+    NvRmDmaFree_inout inout;
+    NvRmDmaFree_out out;
+} NvRmDmaFree_params;
+
+typedef struct NvRmDmaAllocate_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvBool Enable32bitSwap;
+    NvRmDmaPriority Priority;
+    NvRmDmaModuleID DmaRequestorModuleId;
+    NvU32 DmaRequestorInstanceId;
+} NV_ALIGN(4) NvRmDmaAllocate_in;
+
+typedef struct NvRmDmaAllocate_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaAllocate_inout;
+
+typedef struct NvRmDmaAllocate_out_t
+{
+    NvError ret_;
+    NvRmDmaHandle phDma;
+} NV_ALIGN(4) NvRmDmaAllocate_out;
+
+typedef struct NvRmDmaAllocate_params_t
+{
+    NvRmDmaAllocate_in in;
+    NvRmDmaAllocate_inout inout;
+    NvRmDmaAllocate_out out;
+} NvRmDmaAllocate_params;
+
+typedef struct NvRmDmaGetCapabilities_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmDmaCapabilities pRmDmaCaps;
+} NV_ALIGN(4) NvRmDmaGetCapabilities_in;
+
+typedef struct NvRmDmaGetCapabilities_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmDmaGetCapabilities_inout;
+
+typedef struct NvRmDmaGetCapabilities_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmDmaGetCapabilities_out;
+
+typedef struct NvRmDmaGetCapabilities_params_t
+{
+    NvRmDmaGetCapabilities_in in;
+    NvRmDmaGetCapabilities_inout inout;
+    NvRmDmaGetCapabilities_out out;
+} NvRmDmaGetCapabilities_params;
+
+static NvError NvRmDmaIsDmaTransferCompletes_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaIsDmaTransferCompletes_in *p_in;
+    NvRmDmaIsDmaTransferCompletes_out *p_out;
+
+    p_in = (NvRmDmaIsDmaTransferCompletes_in *)InBuffer;
+    p_out = (NvRmDmaIsDmaTransferCompletes_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDmaIsDmaTransferCompletes_params, out) - OFFSET(NvRmDmaIsDmaTransferCompletes_params, inout));
+
+
+    p_out->ret_ = NvRmDmaIsDmaTransferCompletes( p_in->hDma, p_in->IsFirstHalfBuffer );
+
+    return err_;
+}
+
+static NvError NvRmDmaGetTransferredCount_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaGetTransferredCount_in *p_in;
+    NvRmDmaGetTransferredCount_out *p_out;
+
+    p_in = (NvRmDmaGetTransferredCount_in *)InBuffer;
+    p_out = (NvRmDmaGetTransferredCount_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDmaGetTransferredCount_params, out) - OFFSET(NvRmDmaGetTransferredCount_params, inout));
+
+
+    p_out->ret_ = NvRmDmaGetTransferredCount( p_in->hDma, &p_out->pTransferCount, p_in->IsTransferStop );
+
+    return err_;
+}
+
+static NvError NvRmDmaAbort_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaAbort_in *p_in;
+
+    p_in = (NvRmDmaAbort_in *)InBuffer;
+
+
+    NvRmDmaAbort( p_in->hDma );
+
+    return err_;
+}
+
+static NvError NvRmDmaStartDmaTransfer_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaStartDmaTransfer_in *p_in;
+    NvRmDmaStartDmaTransfer_out *p_out;
+    NvOsSemaphoreHandle AsynchSemaphoreId = NULL;
+
+    p_in = (NvRmDmaStartDmaTransfer_in *)InBuffer;
+    p_out = (NvRmDmaStartDmaTransfer_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDmaStartDmaTransfer_params, out) - OFFSET(NvRmDmaStartDmaTransfer_params, inout));
+
+    if( p_in->AsynchSemaphoreId )
+    {
+        err_ = NvOsSemaphoreUnmarshal( p_in->AsynchSemaphoreId, &AsynchSemaphoreId );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmDmaStartDmaTransfer( p_in->hDma, &p_in->pClientBuffer, p_in->DmaDirection, p_in->WaitTimeoutInMilliSecond, AsynchSemaphoreId );
+
+clean:
+    NvOsSemaphoreDestroy( AsynchSemaphoreId );
+    return err_;
+}
+
+static NvError NvRmDmaFree_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaFree_in *p_in;
+
+    p_in = (NvRmDmaFree_in *)InBuffer;
+
+
+    NvRmDmaFree( p_in->hDma );
+
+    return err_;
+}
+
+static NvError NvRmDmaAllocate_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaAllocate_in *p_in;
+    NvRmDmaAllocate_out *p_out;
+
+    p_in = (NvRmDmaAllocate_in *)InBuffer;
+    p_out = (NvRmDmaAllocate_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDmaAllocate_params, out) - OFFSET(NvRmDmaAllocate_params, inout));
+
+
+    p_out->ret_ = NvRmDmaAllocate( p_in->hRmDevice, &p_out->phDma, p_in->Enable32bitSwap, p_in->Priority, p_in->DmaRequestorModuleId, p_in->DmaRequestorInstanceId );
+
+    return err_;
+}
+
+static NvError NvRmDmaGetCapabilities_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmDmaGetCapabilities_in *p_in;
+    NvRmDmaGetCapabilities_out *p_out;
+
+    p_in = (NvRmDmaGetCapabilities_in *)InBuffer;
+    p_out = (NvRmDmaGetCapabilities_out *)((NvU8 *)OutBuffer + OFFSET(NvRmDmaGetCapabilities_params, out) - OFFSET(NvRmDmaGetCapabilities_params, inout));
+
+
+    p_out->ret_ = NvRmDmaGetCapabilities( p_in->hDevice, &p_in->pRmDmaCaps );
+
+    return err_;
+}
+
+NvError nvrm_dma_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_dma_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 6:
+        err_ = NvRmDmaIsDmaTransferCompletes_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmDmaGetTransferredCount_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmDmaAbort_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmDmaStartDmaTransfer_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmDmaFree_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmDmaAllocate_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmDmaGetCapabilities_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_gpio_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_gpio_dispatch.c
new file mode 100644
index 000000000000..d932c98db502
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_gpio_dispatch.c
@@ -0,0 +1,566 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_gpio.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmGpioGetIrqs_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmGpioPinHandle  * pin;
+    NvU32  * Irq;
+    NvU32 pinCount;
+} NV_ALIGN(4) NvRmGpioGetIrqs_in;
+
+typedef struct NvRmGpioGetIrqs_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioGetIrqs_inout;
+
+typedef struct NvRmGpioGetIrqs_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmGpioGetIrqs_out;
+
+typedef struct NvRmGpioGetIrqs_params_t
+{
+    NvRmGpioGetIrqs_in in;
+    NvRmGpioGetIrqs_inout inout;
+    NvRmGpioGetIrqs_out out;
+} NvRmGpioGetIrqs_params;
+
+typedef struct NvRmGpioConfigPins_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+    NvRmGpioPinHandle  * pin;
+    NvU32 pinCount;
+    NvRmGpioPinMode Mode;
+} NV_ALIGN(4) NvRmGpioConfigPins_in;
+
+typedef struct NvRmGpioConfigPins_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioConfigPins_inout;
+
+typedef struct NvRmGpioConfigPins_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmGpioConfigPins_out;
+
+typedef struct NvRmGpioConfigPins_params_t
+{
+    NvRmGpioConfigPins_in in;
+    NvRmGpioConfigPins_inout inout;
+    NvRmGpioConfigPins_out out;
+} NvRmGpioConfigPins_params;
+
+typedef struct NvRmGpioReadPins_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+    NvRmGpioPinHandle  * pin;
+    NvRmGpioPinState  * pPinState;
+    NvU32 pinCount;
+} NV_ALIGN(4) NvRmGpioReadPins_in;
+
+typedef struct NvRmGpioReadPins_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioReadPins_inout;
+
+typedef struct NvRmGpioReadPins_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioReadPins_out;
+
+typedef struct NvRmGpioReadPins_params_t
+{
+    NvRmGpioReadPins_in in;
+    NvRmGpioReadPins_inout inout;
+    NvRmGpioReadPins_out out;
+} NvRmGpioReadPins_params;
+
+typedef struct NvRmGpioWritePins_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+    NvRmGpioPinHandle  * pin;
+    NvRmGpioPinState  * pinState;
+    NvU32 pinCount;
+} NV_ALIGN(4) NvRmGpioWritePins_in;
+
+typedef struct NvRmGpioWritePins_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioWritePins_inout;
+
+typedef struct NvRmGpioWritePins_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioWritePins_out;
+
+typedef struct NvRmGpioWritePins_params_t
+{
+    NvRmGpioWritePins_in in;
+    NvRmGpioWritePins_inout inout;
+    NvRmGpioWritePins_out out;
+} NvRmGpioWritePins_params;
+
+typedef struct NvRmGpioReleasePinHandles_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+    NvRmGpioPinHandle  * hPin;
+    NvU32 pinCount;
+} NV_ALIGN(4) NvRmGpioReleasePinHandles_in;
+
+typedef struct NvRmGpioReleasePinHandles_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioReleasePinHandles_inout;
+
+typedef struct NvRmGpioReleasePinHandles_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioReleasePinHandles_out;
+
+typedef struct NvRmGpioReleasePinHandles_params_t
+{
+    NvRmGpioReleasePinHandles_in in;
+    NvRmGpioReleasePinHandles_inout inout;
+    NvRmGpioReleasePinHandles_out out;
+} NvRmGpioReleasePinHandles_params;
+
+typedef struct NvRmGpioAcquirePinHandle_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+    NvU32 port;
+    NvU32 pin;
+} NV_ALIGN(4) NvRmGpioAcquirePinHandle_in;
+
+typedef struct NvRmGpioAcquirePinHandle_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioAcquirePinHandle_inout;
+
+typedef struct NvRmGpioAcquirePinHandle_out_t
+{
+    NvError ret_;
+    NvRmGpioPinHandle phPin;
+} NV_ALIGN(4) NvRmGpioAcquirePinHandle_out;
+
+typedef struct NvRmGpioAcquirePinHandle_params_t
+{
+    NvRmGpioAcquirePinHandle_in in;
+    NvRmGpioAcquirePinHandle_inout inout;
+    NvRmGpioAcquirePinHandle_out out;
+} NvRmGpioAcquirePinHandle_params;
+
+typedef struct NvRmGpioClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmGpioHandle hGpio;
+} NV_ALIGN(4) NvRmGpioClose_in;
+
+typedef struct NvRmGpioClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioClose_inout;
+
+typedef struct NvRmGpioClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioClose_out;
+
+typedef struct NvRmGpioClose_params_t
+{
+    NvRmGpioClose_in in;
+    NvRmGpioClose_inout inout;
+    NvRmGpioClose_out out;
+} NvRmGpioClose_params;
+
+typedef struct NvRmGpioOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmGpioOpen_in;
+
+typedef struct NvRmGpioOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGpioOpen_inout;
+
+typedef struct NvRmGpioOpen_out_t
+{
+    NvError ret_;
+    NvRmGpioHandle phGpio;
+} NV_ALIGN(4) NvRmGpioOpen_out;
+
+typedef struct NvRmGpioOpen_params_t
+{
+    NvRmGpioOpen_in in;
+    NvRmGpioOpen_inout inout;
+    NvRmGpioOpen_out out;
+} NvRmGpioOpen_params;
+
+static NvError NvRmGpioGetIrqs_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioGetIrqs_in *p_in;
+    NvRmGpioGetIrqs_out *p_out;
+    NvRmGpioPinHandle *pin = NULL;
+    NvU32  *Irq = NULL;
+
+    p_in = (NvRmGpioGetIrqs_in *)InBuffer;
+    p_out = (NvRmGpioGetIrqs_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGpioGetIrqs_params, out) - OFFSET(NvRmGpioGetIrqs_params, inout));
+
+    if( p_in->pinCount && p_in->pin )
+    {
+        pin = (NvRmGpioPinHandle  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+        if( !pin )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pin )
+        {
+            err_ = NvOsCopyIn( pin, p_in->pin, p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->pinCount && p_in->Irq )
+    {
+        Irq = (NvU32  *)NvOsAlloc( p_in->pinCount * sizeof( NvU32  ) );
+        if( !Irq )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmGpioGetIrqs( p_in->hRmDevice, pin, Irq, p_in->pinCount );
+
+    if(p_in->Irq && Irq)
+    {
+        err_ = NvOsCopyOut( p_in->Irq, Irq, p_in->pinCount * sizeof( NvU32  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pin );
+    NvOsFree( Irq );
+    return err_;
+}
+
+static NvError NvRmGpioConfigPins_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioConfigPins_in *p_in;
+    NvRmGpioConfigPins_out *p_out;
+    NvRmGpioPinHandle *pin = NULL;
+
+    p_in = (NvRmGpioConfigPins_in *)InBuffer;
+    p_out = (NvRmGpioConfigPins_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGpioConfigPins_params, out) - OFFSET(NvRmGpioConfigPins_params, inout));
+
+    if( p_in->pinCount && p_in->pin )
+    {
+        pin = (NvRmGpioPinHandle  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+        if( !pin )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pin )
+        {
+            err_ = NvOsCopyIn( pin, p_in->pin, p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmGpioConfigPins( p_in->hGpio, pin, p_in->pinCount, p_in->Mode );
+
+clean:
+    NvOsFree( pin );
+    return err_;
+}
+
+static NvError NvRmGpioReadPins_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioReadPins_in *p_in;
+    NvRmGpioPinHandle *pin = NULL;
+    NvRmGpioPinState *pPinState = NULL;
+
+    p_in = (NvRmGpioReadPins_in *)InBuffer;
+
+    if( p_in->pinCount && p_in->pin )
+    {
+        pin = (NvRmGpioPinHandle  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+        if( !pin )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pin )
+        {
+            err_ = NvOsCopyIn( pin, p_in->pin, p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->pinCount && p_in->pPinState )
+    {
+        pPinState = (NvRmGpioPinState  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinState  ) );
+        if( !pPinState )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    NvRmGpioReadPins( p_in->hGpio, pin, pPinState, p_in->pinCount );
+
+    if(p_in->pPinState && pPinState)
+    {
+        err_ = NvOsCopyOut( p_in->pPinState, pPinState, p_in->pinCount * sizeof( NvRmGpioPinState  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pin );
+    NvOsFree( pPinState );
+    return err_;
+}
+
+static NvError NvRmGpioWritePins_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioWritePins_in *p_in;
+    NvRmGpioPinHandle *pin = NULL;
+    NvRmGpioPinState *pinState = NULL;
+
+    p_in = (NvRmGpioWritePins_in *)InBuffer;
+
+    if( p_in->pinCount && p_in->pin )
+    {
+        pin = (NvRmGpioPinHandle  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+        if( !pin )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pin )
+        {
+            err_ = NvOsCopyIn( pin, p_in->pin, p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->pinCount && p_in->pinState )
+    {
+        pinState = (NvRmGpioPinState  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinState  ) );
+        if( !pinState )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pinState )
+        {
+            err_ = NvOsCopyIn( pinState, p_in->pinState, p_in->pinCount * sizeof( NvRmGpioPinState  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRmGpioWritePins( p_in->hGpio, pin, pinState, p_in->pinCount );
+
+clean:
+    NvOsFree( pin );
+    NvOsFree( pinState );
+    return err_;
+}
+
+static NvError NvRmGpioReleasePinHandles_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioReleasePinHandles_in *p_in;
+    NvRmGpioPinHandle *hPin = NULL;
+
+    p_in = (NvRmGpioReleasePinHandles_in *)InBuffer;
+
+    if( p_in->pinCount && p_in->hPin )
+    {
+        hPin = (NvRmGpioPinHandle  *)NvOsAlloc( p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+        if( !hPin )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->hPin )
+        {
+            err_ = NvOsCopyIn( hPin, p_in->hPin, p_in->pinCount * sizeof( NvRmGpioPinHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRmGpioReleasePinHandles( p_in->hGpio, hPin, p_in->pinCount );
+
+clean:
+    NvOsFree( hPin );
+    return err_;
+}
+
+static NvError NvRmGpioAcquirePinHandle_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioAcquirePinHandle_in *p_in;
+    NvRmGpioAcquirePinHandle_out *p_out;
+
+    p_in = (NvRmGpioAcquirePinHandle_in *)InBuffer;
+    p_out = (NvRmGpioAcquirePinHandle_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGpioAcquirePinHandle_params, out) - OFFSET(NvRmGpioAcquirePinHandle_params, inout));
+
+
+    p_out->ret_ = NvRmGpioAcquirePinHandle( p_in->hGpio, p_in->port, p_in->pin, &p_out->phPin );
+
+    return err_;
+}
+
+static NvError NvRmGpioClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioClose_in *p_in;
+
+    p_in = (NvRmGpioClose_in *)InBuffer;
+
+
+    NvRmGpioClose( p_in->hGpio );
+
+    return err_;
+}
+
+static NvError NvRmGpioOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGpioOpen_in *p_in;
+    NvRmGpioOpen_out *p_out;
+
+    p_in = (NvRmGpioOpen_in *)InBuffer;
+    p_out = (NvRmGpioOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGpioOpen_params, out) - OFFSET(NvRmGpioOpen_params, inout));
+
+
+    p_out->ret_ = NvRmGpioOpen( p_in->hRmDevice, &p_out->phGpio );
+
+    return err_;
+}
+
+NvError nvrm_gpio_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_gpio_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 7:
+        err_ = NvRmGpioGetIrqs_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmGpioConfigPins_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmGpioReadPins_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmGpioWritePins_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmGpioReleasePinHandles_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmGpioAcquirePinHandle_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmGpioClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmGpioOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_i2c_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_i2c_dispatch.c
new file mode 100644
index 000000000000..6e2672dff896
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_i2c_dispatch.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_i2c.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmI2cTransaction_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmI2cHandle hI2c;
+    NvU32 I2cPinMap;
+    NvU32 WaitTimeoutInMilliSeconds;
+    NvU32 ClockSpeedKHz;
+    NvU8  * Data;
+    NvU32 DataLen;
+    NvRmI2cTransactionInfo  * Transaction;
+    NvU32 NumOfTransactions;
+} NV_ALIGN(4) NvRmI2cTransaction_in;
+
+typedef struct NvRmI2cTransaction_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmI2cTransaction_inout;
+
+typedef struct NvRmI2cTransaction_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmI2cTransaction_out;
+
+typedef struct NvRmI2cTransaction_params_t
+{
+    NvRmI2cTransaction_in in;
+    NvRmI2cTransaction_inout inout;
+    NvRmI2cTransaction_out out;
+} NvRmI2cTransaction_params;
+
+typedef struct NvRmI2cClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmI2cHandle hI2c;
+} NV_ALIGN(4) NvRmI2cClose_in;
+
+typedef struct NvRmI2cClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmI2cClose_inout;
+
+typedef struct NvRmI2cClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmI2cClose_out;
+
+typedef struct NvRmI2cClose_params_t
+{
+    NvRmI2cClose_in in;
+    NvRmI2cClose_inout inout;
+    NvRmI2cClose_out out;
+} NvRmI2cClose_params;
+
+typedef struct NvRmI2cOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 IoModule;
+    NvU32 instance;
+} NV_ALIGN(4) NvRmI2cOpen_in;
+
+typedef struct NvRmI2cOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmI2cOpen_inout;
+
+typedef struct NvRmI2cOpen_out_t
+{
+    NvError ret_;
+    NvRmI2cHandle phI2c;
+} NV_ALIGN(4) NvRmI2cOpen_out;
+
+typedef struct NvRmI2cOpen_params_t
+{
+    NvRmI2cOpen_in in;
+    NvRmI2cOpen_inout inout;
+    NvRmI2cOpen_out out;
+} NvRmI2cOpen_params;
+
+static NvError NvRmI2cTransaction_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmI2cTransaction_in *p_in;
+    NvRmI2cTransaction_out *p_out;
+    NvU8  *Data = NULL;
+    NvRmI2cTransactionInfo *Transaction = NULL;
+
+    p_in = (NvRmI2cTransaction_in *)InBuffer;
+    p_out = (NvRmI2cTransaction_out *)((NvU8 *)OutBuffer + OFFSET(NvRmI2cTransaction_params, out) - OFFSET(NvRmI2cTransaction_params, inout));
+
+    if( p_in->DataLen && p_in->Data )
+    {
+        Data = (NvU8  *)NvOsAlloc( p_in->DataLen * sizeof( NvU8  ) );
+        if( !Data )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Data )
+        {
+            err_ = NvOsCopyIn( Data, p_in->Data, p_in->DataLen * sizeof( NvU8  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->NumOfTransactions && p_in->Transaction )
+    {
+        Transaction = (NvRmI2cTransactionInfo  *)NvOsAlloc( p_in->NumOfTransactions * sizeof( NvRmI2cTransactionInfo  ) );
+        if( !Transaction )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Transaction )
+        {
+            err_ = NvOsCopyIn( Transaction, p_in->Transaction, p_in->NumOfTransactions * sizeof( NvRmI2cTransactionInfo  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmI2cTransaction( p_in->hI2c, p_in->I2cPinMap, p_in->WaitTimeoutInMilliSeconds, p_in->ClockSpeedKHz, Data, p_in->DataLen, Transaction, p_in->NumOfTransactions );
+
+    if(p_in->Data && Data)
+    {
+        err_ = NvOsCopyOut( p_in->Data, Data, p_in->DataLen * sizeof( NvU8  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( Data );
+    NvOsFree( Transaction );
+    return err_;
+}
+
+static NvError NvRmI2cClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmI2cClose_in *p_in;
+
+    p_in = (NvRmI2cClose_in *)InBuffer;
+
+
+    NvRmI2cClose( p_in->hI2c );
+
+    return err_;
+}
+
+static NvError NvRmI2cOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmI2cOpen_in *p_in;
+    NvRmI2cOpen_out *p_out;
+
+    p_in = (NvRmI2cOpen_in *)InBuffer;
+    p_out = (NvRmI2cOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmI2cOpen_params, out) - OFFSET(NvRmI2cOpen_params, inout));
+
+
+    p_out->ret_ = NvRmI2cOpen( p_in->hDevice, p_in->IoModule, p_in->instance, &p_out->phI2c );
+
+    return err_;
+}
+
+NvError nvrm_i2c_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_i2c_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 2:
+        err_ = NvRmI2cTransaction_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmI2cClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmI2cOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_init_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_init_dispatch.c
new file mode 100644
index 000000000000..1c438a100957
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_init_dispatch.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_init.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmClose_in;
+
+typedef struct NvRmClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmClose_inout;
+
+typedef struct NvRmClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmClose_out;
+
+typedef struct NvRmClose_params_t
+{
+    NvRmClose_in in;
+    NvRmClose_inout inout;
+    NvRmClose_out out;
+} NvRmClose_params;
+
+typedef struct NvRmOpenNew_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+} NV_ALIGN(4) NvRmOpenNew_in;
+
+typedef struct NvRmOpenNew_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOpenNew_inout;
+
+typedef struct NvRmOpenNew_out_t
+{
+    NvError ret_;
+    NvRmDeviceHandle pHandle;
+} NV_ALIGN(4) NvRmOpenNew_out;
+
+typedef struct NvRmOpenNew_params_t
+{
+    NvRmOpenNew_in in;
+    NvRmOpenNew_inout inout;
+    NvRmOpenNew_out out;
+} NvRmOpenNew_params;
+
+typedef struct NvRmInit_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+} NV_ALIGN(4) NvRmInit_in;
+
+typedef struct NvRmInit_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmInit_inout;
+
+typedef struct NvRmInit_out_t
+{
+    NvRmDeviceHandle pHandle;
+} NV_ALIGN(4) NvRmInit_out;
+
+typedef struct NvRmInit_params_t
+{
+    NvRmInit_in in;
+    NvRmInit_inout inout;
+    NvRmInit_out out;
+} NvRmInit_params;
+
+typedef struct NvRmOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvU32 DeviceId;
+} NV_ALIGN(4) NvRmOpen_in;
+
+typedef struct NvRmOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOpen_inout;
+
+typedef struct NvRmOpen_out_t
+{
+    NvError ret_;
+    NvRmDeviceHandle pHandle;
+} NV_ALIGN(4) NvRmOpen_out;
+
+typedef struct NvRmOpen_params_t
+{
+    NvRmOpen_in in;
+    NvRmOpen_inout inout;
+    NvRmOpen_out out;
+} NvRmOpen_params;
+
+static NvError NvRmClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmClose_in *p_in;
+
+    p_in = (NvRmClose_in *)InBuffer;
+
+
+    NvRmClose( p_in->hDevice );
+
+    return err_;
+}
+
+static NvError NvRmOpenNew_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmOpenNew_in *p_in;
+    NvRmOpenNew_out *p_out;
+
+    p_in = (NvRmOpenNew_in *)InBuffer;
+    p_out = (NvRmOpenNew_out *)((NvU8 *)OutBuffer + OFFSET(NvRmOpenNew_params, out) - OFFSET(NvRmOpenNew_params, inout));
+
+
+    p_out->ret_ = NvRmOpenNew( &p_out->pHandle );
+
+    return err_;
+}
+
+static NvError NvRmInit_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmInit_in *p_in;
+    NvRmInit_out *p_out;
+
+    p_in = (NvRmInit_in *)InBuffer;
+    p_out = (NvRmInit_out *)((NvU8 *)OutBuffer + OFFSET(NvRmInit_params, out) - OFFSET(NvRmInit_params, inout));
+
+
+    NvRmInit( &p_out->pHandle );
+
+    return err_;
+}
+
+static NvError NvRmOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmOpen_in *p_in;
+    NvRmOpen_out *p_out;
+
+    p_in = (NvRmOpen_in *)InBuffer;
+    p_out = (NvRmOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmOpen_params, out) - OFFSET(NvRmOpen_params, inout));
+
+
+    p_out->ret_ = NvRmOpen( &p_out->pHandle, p_in->DeviceId );
+
+    return err_;
+}
+
+NvError nvrm_init_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_init_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 3:
+        err_ = NvRmClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmOpenNew_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmInit_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_interrupt_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_interrupt_dispatch.c
new file mode 100644
index 000000000000..007117333979
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_interrupt_dispatch.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_interrupt.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmGetIrqCountForLogicalInterrupt_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmModuleID ModuleID;
+} NV_ALIGN(4) NvRmGetIrqCountForLogicalInterrupt_in;
+
+typedef struct NvRmGetIrqCountForLogicalInterrupt_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetIrqCountForLogicalInterrupt_inout;
+
+typedef struct NvRmGetIrqCountForLogicalInterrupt_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmGetIrqCountForLogicalInterrupt_out;
+
+typedef struct NvRmGetIrqCountForLogicalInterrupt_params_t
+{
+    NvRmGetIrqCountForLogicalInterrupt_in in;
+    NvRmGetIrqCountForLogicalInterrupt_inout inout;
+    NvRmGetIrqCountForLogicalInterrupt_out out;
+} NvRmGetIrqCountForLogicalInterrupt_params;
+
+typedef struct NvRmGetIrqForLogicalInterrupt_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmModuleID ModuleID;
+    NvU32 Index;
+} NV_ALIGN(4) NvRmGetIrqForLogicalInterrupt_in;
+
+typedef struct NvRmGetIrqForLogicalInterrupt_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetIrqForLogicalInterrupt_inout;
+
+typedef struct NvRmGetIrqForLogicalInterrupt_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmGetIrqForLogicalInterrupt_out;
+
+typedef struct NvRmGetIrqForLogicalInterrupt_params_t
+{
+    NvRmGetIrqForLogicalInterrupt_in in;
+    NvRmGetIrqForLogicalInterrupt_inout inout;
+    NvRmGetIrqForLogicalInterrupt_out out;
+} NvRmGetIrqForLogicalInterrupt_params;
+
+static NvError NvRmGetIrqCountForLogicalInterrupt_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGetIrqCountForLogicalInterrupt_in *p_in;
+    NvRmGetIrqCountForLogicalInterrupt_out *p_out;
+
+    p_in = (NvRmGetIrqCountForLogicalInterrupt_in *)InBuffer;
+    p_out = (NvRmGetIrqCountForLogicalInterrupt_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGetIrqCountForLogicalInterrupt_params, out) - OFFSET(NvRmGetIrqCountForLogicalInterrupt_params, inout));
+
+
+    p_out->ret_ = NvRmGetIrqCountForLogicalInterrupt( p_in->hRmDevice, p_in->ModuleID );
+
+    return err_;
+}
+
+static NvError NvRmGetIrqForLogicalInterrupt_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGetIrqForLogicalInterrupt_in *p_in;
+    NvRmGetIrqForLogicalInterrupt_out *p_out;
+
+    p_in = (NvRmGetIrqForLogicalInterrupt_in *)InBuffer;
+    p_out = (NvRmGetIrqForLogicalInterrupt_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGetIrqForLogicalInterrupt_params, out) - OFFSET(NvRmGetIrqForLogicalInterrupt_params, inout));
+
+
+    p_out->ret_ = NvRmGetIrqForLogicalInterrupt( p_in->hRmDevice, p_in->ModuleID, p_in->Index );
+
+    return err_;
+}
+
+NvError nvrm_interrupt_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_interrupt_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 1:
+        err_ = NvRmGetIrqCountForLogicalInterrupt_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmGetIrqForLogicalInterrupt_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_keylist_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_keylist_dispatch.c
new file mode 100644
index 000000000000..4e242392cd4a
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_keylist_dispatch.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_keylist.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmSetKeyValuePair_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRm;
+    NvU32 KeyID;
+    NvU32 Value;
+} NV_ALIGN(4) NvRmSetKeyValuePair_in;
+
+typedef struct NvRmSetKeyValuePair_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSetKeyValuePair_inout;
+
+typedef struct NvRmSetKeyValuePair_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmSetKeyValuePair_out;
+
+typedef struct NvRmSetKeyValuePair_params_t
+{
+    NvRmSetKeyValuePair_in in;
+    NvRmSetKeyValuePair_inout inout;
+    NvRmSetKeyValuePair_out out;
+} NvRmSetKeyValuePair_params;
+
+typedef struct NvRmGetKeyValue_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRm;
+    NvU32 KeyID;
+} NV_ALIGN(4) NvRmGetKeyValue_in;
+
+typedef struct NvRmGetKeyValue_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetKeyValue_inout;
+
+typedef struct NvRmGetKeyValue_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmGetKeyValue_out;
+
+typedef struct NvRmGetKeyValue_params_t
+{
+    NvRmGetKeyValue_in in;
+    NvRmGetKeyValue_inout inout;
+    NvRmGetKeyValue_out out;
+} NvRmGetKeyValue_params;
+
+static NvError NvRmSetKeyValuePair_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSetKeyValuePair_in *p_in;
+    NvRmSetKeyValuePair_out *p_out;
+
+    p_in = (NvRmSetKeyValuePair_in *)InBuffer;
+    p_out = (NvRmSetKeyValuePair_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSetKeyValuePair_params, out) - OFFSET(NvRmSetKeyValuePair_params, inout));
+
+
+    p_out->ret_ = NvRmSetKeyValuePair( p_in->hRm, p_in->KeyID, p_in->Value );
+
+    return err_;
+}
+
+static NvError NvRmGetKeyValue_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGetKeyValue_in *p_in;
+    NvRmGetKeyValue_out *p_out;
+
+    p_in = (NvRmGetKeyValue_in *)InBuffer;
+    p_out = (NvRmGetKeyValue_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGetKeyValue_params, out) - OFFSET(NvRmGetKeyValue_params, inout));
+
+
+    p_out->ret_ = NvRmGetKeyValue( p_in->hRm, p_in->KeyID );
+
+    return err_;
+}
+
+NvError nvrm_keylist_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_keylist_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 1:
+        err_ = NvRmSetKeyValuePair_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmGetKeyValue_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_memctrl_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_memctrl_dispatch.c
new file mode 100644
index 000000000000..b2a4f77a8f67
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_memctrl_dispatch.c
@@ -0,0 +1,383 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_memctrl.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmCorePerfMonStop_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvU32  * pCountList;
+} NV_ALIGN(4) NvRmCorePerfMonStop_in;
+
+typedef struct NvRmCorePerfMonStop_inout_t
+{
+    NvU32 pCountListSize;
+} NV_ALIGN(4) NvRmCorePerfMonStop_inout;
+
+typedef struct NvRmCorePerfMonStop_out_t
+{
+    NvError ret_;
+    NvU32 pTotalCycleCount;
+} NV_ALIGN(4) NvRmCorePerfMonStop_out;
+
+typedef struct NvRmCorePerfMonStop_params_t
+{
+    NvRmCorePerfMonStop_in in;
+    NvRmCorePerfMonStop_inout inout;
+    NvRmCorePerfMonStop_out out;
+} NvRmCorePerfMonStop_params;
+
+typedef struct NvRmCorePerfMonStart_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvU32  * pEventList;
+} NV_ALIGN(4) NvRmCorePerfMonStart_in;
+
+typedef struct NvRmCorePerfMonStart_inout_t
+{
+    NvU32 pEventListSize;
+} NV_ALIGN(4) NvRmCorePerfMonStart_inout;
+
+typedef struct NvRmCorePerfMonStart_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmCorePerfMonStart_out;
+
+typedef struct NvRmCorePerfMonStart_params_t
+{
+    NvRmCorePerfMonStart_in in;
+    NvRmCorePerfMonStart_inout inout;
+    NvRmCorePerfMonStart_out out;
+} NvRmCorePerfMonStart_params;
+
+typedef struct ReadObsData_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle rm;
+    NvRmModuleID modId;
+    NvU32 start_index;
+    NvU32 length;
+} NV_ALIGN(4) ReadObsData_in;
+
+typedef struct ReadObsData_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) ReadObsData_inout;
+
+typedef struct ReadObsData_out_t
+{
+    NvError ret_;
+    NvU32 value;
+} NV_ALIGN(4) ReadObsData_out;
+
+typedef struct ReadObsData_params_t
+{
+    ReadObsData_in in;
+    ReadObsData_inout inout;
+    ReadObsData_out out;
+} ReadObsData_params;
+
+typedef struct McStat_Report_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvU32 client_id_0;
+    NvU32 client_0_cycles;
+    NvU32 client_id_1;
+    NvU32 client_1_cycles;
+    NvU32 llc_client_id;
+    NvU32 llc_client_clocks;
+    NvU32 llc_client_cycles;
+    NvU32 mc_clocks;
+} NV_ALIGN(4) McStat_Report_in;
+
+typedef struct McStat_Report_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) McStat_Report_inout;
+
+typedef struct McStat_Report_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) McStat_Report_out;
+
+typedef struct McStat_Report_params_t
+{
+    McStat_Report_in in;
+    McStat_Report_inout inout;
+    McStat_Report_out out;
+} McStat_Report_params;
+
+typedef struct McStat_Stop_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle rm;
+} NV_ALIGN(4) McStat_Stop_in;
+
+typedef struct McStat_Stop_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) McStat_Stop_inout;
+
+typedef struct McStat_Stop_out_t
+{
+    NvU32 client_0_cycles;
+    NvU32 client_1_cycles;
+    NvU32 llc_client_cycles;
+    NvU32 llc_client_clocks;
+    NvU32 mc_clocks;
+} NV_ALIGN(4) McStat_Stop_out;
+
+typedef struct McStat_Stop_params_t
+{
+    McStat_Stop_in in;
+    McStat_Stop_inout inout;
+    McStat_Stop_out out;
+} McStat_Stop_params;
+
+typedef struct McStat_Start_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle rm;
+    NvU32 client_id_0;
+    NvU32 client_id_1;
+    NvU32 llc_client_id;
+} NV_ALIGN(4) McStat_Start_in;
+
+typedef struct McStat_Start_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) McStat_Start_inout;
+
+typedef struct McStat_Start_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) McStat_Start_out;
+
+typedef struct McStat_Start_params_t
+{
+    McStat_Start_in in;
+    McStat_Start_inout inout;
+    McStat_Start_out out;
+} McStat_Start_params;
+
+static NvError NvRmCorePerfMonStop_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmCorePerfMonStop_in *p_in;
+    NvRmCorePerfMonStop_inout *p_inout;
+    NvRmCorePerfMonStop_out *p_out;
+    NvRmCorePerfMonStop_inout inout;
+    NvU32  *pCountList = NULL;
+
+    p_in = (NvRmCorePerfMonStop_in *)InBuffer;
+    p_inout = (NvRmCorePerfMonStop_inout *)((NvU8 *)InBuffer + OFFSET(NvRmCorePerfMonStop_params, inout));
+    p_out = (NvRmCorePerfMonStop_out *)((NvU8 *)OutBuffer + OFFSET(NvRmCorePerfMonStop_params, out) - OFFSET(NvRmCorePerfMonStop_params, inout));
+
+    (void)inout;
+    inout.pCountListSize = p_inout->pCountListSize;
+    if( p_inout->pCountListSize && p_in->pCountList )
+    {
+        pCountList = (NvU32  *)NvOsAlloc( p_inout->pCountListSize * sizeof( NvU32  ) );
+        if( !pCountList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmCorePerfMonStop( p_in->hRmDevice, &inout.pCountListSize, pCountList, &p_out->pTotalCycleCount );
+
+
+    p_inout = (NvRmCorePerfMonStop_inout *)OutBuffer;
+    p_inout->pCountListSize = inout.pCountListSize;
+    if(p_in->pCountList && pCountList)
+    {
+        err_ = NvOsCopyOut( p_in->pCountList, pCountList, p_inout->pCountListSize * sizeof( NvU32  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pCountList );
+    return err_;
+}
+
+static NvError NvRmCorePerfMonStart_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmCorePerfMonStart_in *p_in;
+    NvRmCorePerfMonStart_inout *p_inout;
+    NvRmCorePerfMonStart_out *p_out;
+    NvRmCorePerfMonStart_inout inout;
+    NvU32  *pEventList = NULL;
+
+    p_in = (NvRmCorePerfMonStart_in *)InBuffer;
+    p_inout = (NvRmCorePerfMonStart_inout *)((NvU8 *)InBuffer + OFFSET(NvRmCorePerfMonStart_params, inout));
+    p_out = (NvRmCorePerfMonStart_out *)((NvU8 *)OutBuffer + OFFSET(NvRmCorePerfMonStart_params, out) - OFFSET(NvRmCorePerfMonStart_params, inout));
+
+    (void)inout;
+    inout.pEventListSize = p_inout->pEventListSize;
+    if( p_inout->pEventListSize && p_in->pEventList )
+    {
+        pEventList = (NvU32  *)NvOsAlloc( p_inout->pEventListSize * sizeof( NvU32  ) );
+        if( !pEventList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pEventList )
+        {
+            err_ = NvOsCopyIn( pEventList, p_in->pEventList, p_inout->pEventListSize * sizeof( NvU32  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmCorePerfMonStart( p_in->hRmDevice, &inout.pEventListSize, pEventList );
+
+
+    p_inout = (NvRmCorePerfMonStart_inout *)OutBuffer;
+    p_inout->pEventListSize = inout.pEventListSize;
+clean:
+    NvOsFree( pEventList );
+    return err_;
+}
+
+static NvError ReadObsData_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    ReadObsData_in *p_in;
+    ReadObsData_out *p_out;
+
+    p_in = (ReadObsData_in *)InBuffer;
+    p_out = (ReadObsData_out *)((NvU8 *)OutBuffer + OFFSET(ReadObsData_params, out) - OFFSET(ReadObsData_params, inout));
+
+
+    p_out->ret_ = ReadObsData( p_in->rm, p_in->modId, p_in->start_index, p_in->length, &p_out->value );
+
+    return err_;
+}
+
+static NvError McStat_Report_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    McStat_Report_in *p_in;
+
+    p_in = (McStat_Report_in *)InBuffer;
+
+
+    McStat_Report( p_in->client_id_0, p_in->client_0_cycles, p_in->client_id_1, p_in->client_1_cycles, p_in->llc_client_id, p_in->llc_client_clocks, p_in->llc_client_cycles, p_in->mc_clocks );
+
+    return err_;
+}
+
+static NvError McStat_Stop_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    McStat_Stop_in *p_in;
+    McStat_Stop_out *p_out;
+
+    p_in = (McStat_Stop_in *)InBuffer;
+    p_out = (McStat_Stop_out *)((NvU8 *)OutBuffer + OFFSET(McStat_Stop_params, out) - OFFSET(McStat_Stop_params, inout));
+
+
+    McStat_Stop( p_in->rm, &p_out->client_0_cycles, &p_out->client_1_cycles, &p_out->llc_client_cycles, &p_out->llc_client_clocks, &p_out->mc_clocks );
+
+    return err_;
+}
+
+static NvError McStat_Start_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    McStat_Start_in *p_in;
+
+    p_in = (McStat_Start_in *)InBuffer;
+
+
+    McStat_Start( p_in->rm, p_in->client_id_0, p_in->client_id_1, p_in->llc_client_id );
+
+    return err_;
+}
+
+NvError nvrm_memctrl_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_memctrl_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 5:
+        err_ = NvRmCorePerfMonStop_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmCorePerfMonStart_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = ReadObsData_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = McStat_Report_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = McStat_Stop_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = McStat_Start_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_memmgr_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_memmgr_dispatch.c
new file mode 100644
index 000000000000..57b08df02223
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_memmgr_dispatch.c
@@ -0,0 +1,941 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_memmgr.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmMemGetStat_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemStat Stat;
+} NV_ALIGN(4) NvRmMemGetStat_in;
+
+typedef struct NvRmMemGetStat_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetStat_inout;
+
+typedef struct NvRmMemGetStat_out_t
+{
+    NvError ret_;
+    NvS32 Result;
+} NV_ALIGN(4) NvRmMemGetStat_out;
+
+typedef struct NvRmMemGetStat_params_t
+{
+    NvRmMemGetStat_in in;
+    NvRmMemGetStat_inout inout;
+    NvRmMemGetStat_out out;
+} NvRmMemGetStat_params;
+
+typedef struct NvRmMemHandleFromId_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvU32 id;
+} NV_ALIGN(4) NvRmMemHandleFromId_in;
+
+typedef struct NvRmMemHandleFromId_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandleFromId_inout;
+
+typedef struct NvRmMemHandleFromId_out_t
+{
+    NvError ret_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemHandleFromId_out;
+
+typedef struct NvRmMemHandleFromId_params_t
+{
+    NvRmMemHandleFromId_in in;
+    NvRmMemHandleFromId_inout inout;
+    NvRmMemHandleFromId_out out;
+} NvRmMemHandleFromId_params;
+
+typedef struct NvRmMemGetId_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemGetId_in;
+
+typedef struct NvRmMemGetId_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetId_inout;
+
+typedef struct NvRmMemGetId_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemGetId_out;
+
+typedef struct NvRmMemGetId_params_t
+{
+    NvRmMemGetId_in in;
+    NvRmMemGetId_inout inout;
+    NvRmMemGetId_out out;
+} NvRmMemGetId_params;
+
+typedef struct NvRmMemGetHeapType_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemGetHeapType_in;
+
+typedef struct NvRmMemGetHeapType_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetHeapType_inout;
+
+typedef struct NvRmMemGetHeapType_out_t
+{
+    NvRmHeap ret_;
+    NvU32 BasePhysAddr;
+} NV_ALIGN(4) NvRmMemGetHeapType_out;
+
+typedef struct NvRmMemGetHeapType_params_t
+{
+    NvRmMemGetHeapType_in in;
+    NvRmMemGetHeapType_inout inout;
+    NvRmMemGetHeapType_out out;
+} NvRmMemGetHeapType_params;
+
+typedef struct NvRmMemGetCacheLineSize_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+} NV_ALIGN(4) NvRmMemGetCacheLineSize_in;
+
+typedef struct NvRmMemGetCacheLineSize_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetCacheLineSize_inout;
+
+typedef struct NvRmMemGetCacheLineSize_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemGetCacheLineSize_out;
+
+typedef struct NvRmMemGetCacheLineSize_params_t
+{
+    NvRmMemGetCacheLineSize_in in;
+    NvRmMemGetCacheLineSize_inout inout;
+    NvRmMemGetCacheLineSize_out out;
+} NvRmMemGetCacheLineSize_params;
+
+typedef struct NvRmMemGetAlignment_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemGetAlignment_in;
+
+typedef struct NvRmMemGetAlignment_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetAlignment_inout;
+
+typedef struct NvRmMemGetAlignment_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemGetAlignment_out;
+
+typedef struct NvRmMemGetAlignment_params_t
+{
+    NvRmMemGetAlignment_in in;
+    NvRmMemGetAlignment_inout inout;
+    NvRmMemGetAlignment_out out;
+} NvRmMemGetAlignment_params;
+
+typedef struct NvRmMemGetSize_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemGetSize_in;
+
+typedef struct NvRmMemGetSize_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetSize_inout;
+
+typedef struct NvRmMemGetSize_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemGetSize_out;
+
+typedef struct NvRmMemGetSize_params_t
+{
+    NvRmMemGetSize_in in;
+    NvRmMemGetSize_inout inout;
+    NvRmMemGetSize_out out;
+} NvRmMemGetSize_params;
+
+typedef struct NvRmMemMove_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hDstMem;
+    NvU32 DstOffset;
+    NvRmMemHandle hSrcMem;
+    NvU32 SrcOffset;
+    NvU32 Size;
+} NV_ALIGN(4) NvRmMemMove_in;
+
+typedef struct NvRmMemMove_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemMove_inout;
+
+typedef struct NvRmMemMove_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemMove_out;
+
+typedef struct NvRmMemMove_params_t
+{
+    NvRmMemMove_in in;
+    NvRmMemMove_inout inout;
+    NvRmMemMove_out out;
+} NvRmMemMove_params;
+
+typedef struct NvRmMemUnpinMult_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle  * hMems;
+    NvU32 Count;
+} NV_ALIGN(4) NvRmMemUnpinMult_in;
+
+typedef struct NvRmMemUnpinMult_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemUnpinMult_inout;
+
+typedef struct NvRmMemUnpinMult_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemUnpinMult_out;
+
+typedef struct NvRmMemUnpinMult_params_t
+{
+    NvRmMemUnpinMult_in in;
+    NvRmMemUnpinMult_inout inout;
+    NvRmMemUnpinMult_out out;
+} NvRmMemUnpinMult_params;
+
+typedef struct NvRmMemUnpin_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemUnpin_in;
+
+typedef struct NvRmMemUnpin_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemUnpin_inout;
+
+typedef struct NvRmMemUnpin_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemUnpin_out;
+
+typedef struct NvRmMemUnpin_params_t
+{
+    NvRmMemUnpin_in in;
+    NvRmMemUnpin_inout inout;
+    NvRmMemUnpin_out out;
+} NvRmMemUnpin_params;
+
+typedef struct NvRmMemGetAddress_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+    NvU32 Offset;
+} NV_ALIGN(4) NvRmMemGetAddress_in;
+
+typedef struct NvRmMemGetAddress_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemGetAddress_inout;
+
+typedef struct NvRmMemGetAddress_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemGetAddress_out;
+
+typedef struct NvRmMemGetAddress_params_t
+{
+    NvRmMemGetAddress_in in;
+    NvRmMemGetAddress_inout inout;
+    NvRmMemGetAddress_out out;
+} NvRmMemGetAddress_params;
+
+typedef struct NvRmMemPinMult_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle  * hMems;
+    NvU32  * Addrs;
+    NvU32 Count;
+} NV_ALIGN(4) NvRmMemPinMult_in;
+
+typedef struct NvRmMemPinMult_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemPinMult_inout;
+
+typedef struct NvRmMemPinMult_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemPinMult_out;
+
+typedef struct NvRmMemPinMult_params_t
+{
+    NvRmMemPinMult_in in;
+    NvRmMemPinMult_inout inout;
+    NvRmMemPinMult_out out;
+} NvRmMemPinMult_params;
+
+typedef struct NvRmMemPin_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemPin_in;
+
+typedef struct NvRmMemPin_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemPin_inout;
+
+typedef struct NvRmMemPin_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmMemPin_out;
+
+typedef struct NvRmMemPin_params_t
+{
+    NvRmMemPin_in in;
+    NvRmMemPin_inout inout;
+    NvRmMemPin_out out;
+} NvRmMemPin_params;
+
+typedef struct NvRmMemAlloc_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+    NvRmHeap  * Heaps;
+    NvU32 NumHeaps;
+    NvU32 Alignment;
+    NvOsMemAttribute Coherency;
+} NV_ALIGN(4) NvRmMemAlloc_in;
+
+typedef struct NvRmMemAlloc_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemAlloc_inout;
+
+typedef struct NvRmMemAlloc_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmMemAlloc_out;
+
+typedef struct NvRmMemAlloc_params_t
+{
+    NvRmMemAlloc_in in;
+    NvRmMemAlloc_inout inout;
+    NvRmMemAlloc_out out;
+} NvRmMemAlloc_params;
+
+typedef struct NvRmMemHandleFree_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemHandleFree_in;
+
+typedef struct NvRmMemHandleFree_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandleFree_inout;
+
+typedef struct NvRmMemHandleFree_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandleFree_out;
+
+typedef struct NvRmMemHandleFree_params_t
+{
+    NvRmMemHandleFree_in in;
+    NvRmMemHandleFree_inout inout;
+    NvRmMemHandleFree_out out;
+} NvRmMemHandleFree_params;
+
+typedef struct NvRmMemHandlePreserveHandle_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmMemHandle hMem;
+} NV_ALIGN(4) NvRmMemHandlePreserveHandle_in;
+
+typedef struct NvRmMemHandlePreserveHandle_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandlePreserveHandle_inout;
+
+typedef struct NvRmMemHandlePreserveHandle_out_t
+{
+    NvError ret_;
+    NvU32 Key;
+} NV_ALIGN(4) NvRmMemHandlePreserveHandle_out;
+
+typedef struct NvRmMemHandlePreserveHandle_params_t
+{
+    NvRmMemHandlePreserveHandle_in in;
+    NvRmMemHandlePreserveHandle_inout inout;
+    NvRmMemHandlePreserveHandle_out out;
+} NvRmMemHandlePreserveHandle_params;
+
+typedef struct NvRmMemHandleClaimPreservedHandle_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 Key;
+} NV_ALIGN(4) NvRmMemHandleClaimPreservedHandle_in;
+
+typedef struct NvRmMemHandleClaimPreservedHandle_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandleClaimPreservedHandle_inout;
+
+typedef struct NvRmMemHandleClaimPreservedHandle_out_t
+{
+    NvError ret_;
+    NvRmMemHandle phMem;
+} NV_ALIGN(4) NvRmMemHandleClaimPreservedHandle_out;
+
+typedef struct NvRmMemHandleClaimPreservedHandle_params_t
+{
+    NvRmMemHandleClaimPreservedHandle_in in;
+    NvRmMemHandleClaimPreservedHandle_inout inout;
+    NvRmMemHandleClaimPreservedHandle_out out;
+} NvRmMemHandleClaimPreservedHandle_params;
+
+typedef struct NvRmMemHandleCreate_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 Size;
+} NV_ALIGN(4) NvRmMemHandleCreate_in;
+
+typedef struct NvRmMemHandleCreate_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMemHandleCreate_inout;
+
+typedef struct NvRmMemHandleCreate_out_t
+{
+    NvError ret_;
+    NvRmMemHandle phMem;
+} NV_ALIGN(4) NvRmMemHandleCreate_out;
+
+typedef struct NvRmMemHandleCreate_params_t
+{
+    NvRmMemHandleCreate_in in;
+    NvRmMemHandleCreate_inout inout;
+    NvRmMemHandleCreate_out out;
+} NvRmMemHandleCreate_params;
+
+static NvError NvRmMemGetStat_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetStat_in *p_in;
+    NvRmMemGetStat_out *p_out;
+
+    p_in = (NvRmMemGetStat_in *)InBuffer;
+    p_out = (NvRmMemGetStat_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetStat_params, out) - OFFSET(NvRmMemGetStat_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetStat( p_in->Stat, &p_out->Result );
+
+    return err_;
+}
+
+static NvError NvRmMemHandleFromId_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemHandleFromId_in *p_in;
+    NvRmMemHandleFromId_out *p_out;
+    NvRtObjRefHandle ref_hMem = 0;
+
+    p_in = (NvRmMemHandleFromId_in *)InBuffer;
+    p_out = (NvRmMemHandleFromId_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemHandleFromId_params, out) - OFFSET(NvRmMemHandleFromId_params, inout));
+
+    err_ = NvRtAllocObjRef(Ctx, &ref_hMem);
+    if (err_ != NvSuccess)
+    {
+        goto clean;
+    }
+
+    p_out->ret_ = NvRmMemHandleFromId( p_in->id, &p_out->hMem );
+
+    if ( p_out->ret_ == NvSuccess )
+    {
+        NvRtStoreObjRef(Ctx, ref_hMem, NvRtObjType_NvRm_NvRmMemHandle, p_out->hMem);
+        ref_hMem = 0;
+    }
+clean:
+    if (ref_hMem) NvRtDiscardObjRef(Ctx, ref_hMem);
+    return err_;
+}
+
+static NvError NvRmMemGetId_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetId_in *p_in;
+    NvRmMemGetId_out *p_out;
+
+    p_in = (NvRmMemGetId_in *)InBuffer;
+    p_out = (NvRmMemGetId_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetId_params, out) - OFFSET(NvRmMemGetId_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetId( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemGetHeapType_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetHeapType_in *p_in;
+    NvRmMemGetHeapType_out *p_out;
+
+    p_in = (NvRmMemGetHeapType_in *)InBuffer;
+    p_out = (NvRmMemGetHeapType_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetHeapType_params, out) - OFFSET(NvRmMemGetHeapType_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetHeapType( p_in->hMem, &p_out->BasePhysAddr );
+
+    return err_;
+}
+
+static NvError NvRmMemGetCacheLineSize_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetCacheLineSize_out *p_out;
+    p_out = (NvRmMemGetCacheLineSize_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetCacheLineSize_params, out) - OFFSET(NvRmMemGetCacheLineSize_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetCacheLineSize(  );
+
+    return err_;
+}
+
+static NvError NvRmMemGetAlignment_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetAlignment_in *p_in;
+    NvRmMemGetAlignment_out *p_out;
+
+    p_in = (NvRmMemGetAlignment_in *)InBuffer;
+    p_out = (NvRmMemGetAlignment_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetAlignment_params, out) - OFFSET(NvRmMemGetAlignment_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetAlignment( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemGetSize_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetSize_in *p_in;
+    NvRmMemGetSize_out *p_out;
+
+    p_in = (NvRmMemGetSize_in *)InBuffer;
+    p_out = (NvRmMemGetSize_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetSize_params, out) - OFFSET(NvRmMemGetSize_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetSize( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemMove_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemMove_in *p_in;
+
+    p_in = (NvRmMemMove_in *)InBuffer;
+
+
+    NvRmMemMove( p_in->hDstMem, p_in->DstOffset, p_in->hSrcMem, p_in->SrcOffset, p_in->Size );
+
+    return err_;
+}
+
+static NvError NvRmMemUnpinMult_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemUnpinMult_in *p_in;
+    NvRmMemHandle *hMems = NULL;
+
+    p_in = (NvRmMemUnpinMult_in *)InBuffer;
+
+    if( p_in->Count && p_in->hMems )
+    {
+        hMems = (NvRmMemHandle  *)NvOsAlloc( p_in->Count * sizeof( NvRmMemHandle  ) );
+        if( !hMems )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->hMems )
+        {
+            err_ = NvOsCopyIn( hMems, p_in->hMems, p_in->Count * sizeof( NvRmMemHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRmMemUnpinMult( hMems, p_in->Count );
+
+clean:
+    NvOsFree( hMems );
+    return err_;
+}
+
+static NvError NvRmMemUnpin_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemUnpin_in *p_in;
+
+    p_in = (NvRmMemUnpin_in *)InBuffer;
+
+
+    NvRmMemUnpin( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemGetAddress_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemGetAddress_in *p_in;
+    NvRmMemGetAddress_out *p_out;
+
+    p_in = (NvRmMemGetAddress_in *)InBuffer;
+    p_out = (NvRmMemGetAddress_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemGetAddress_params, out) - OFFSET(NvRmMemGetAddress_params, inout));
+
+
+    p_out->ret_ = NvRmMemGetAddress( p_in->hMem, p_in->Offset );
+
+    return err_;
+}
+
+static NvError NvRmMemPinMult_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemPinMult_in *p_in;
+    NvRmMemHandle *hMems = NULL;
+    NvU32  *Addrs = NULL;
+
+    p_in = (NvRmMemPinMult_in *)InBuffer;
+
+    if( p_in->Count && p_in->hMems )
+    {
+        hMems = (NvRmMemHandle  *)NvOsAlloc( p_in->Count * sizeof( NvRmMemHandle  ) );
+        if( !hMems )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->hMems )
+        {
+            err_ = NvOsCopyIn( hMems, p_in->hMems, p_in->Count * sizeof( NvRmMemHandle  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->Count && p_in->Addrs )
+    {
+        Addrs = (NvU32  *)NvOsAlloc( p_in->Count * sizeof( NvU32  ) );
+        if( !Addrs )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    NvRmMemPinMult( hMems, Addrs, p_in->Count );
+
+    if(p_in->Addrs && Addrs)
+    {
+        err_ = NvOsCopyOut( p_in->Addrs, Addrs, p_in->Count * sizeof( NvU32  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( hMems );
+    NvOsFree( Addrs );
+    return err_;
+}
+
+static NvError NvRmMemPin_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemPin_in *p_in;
+    NvRmMemPin_out *p_out;
+
+    p_in = (NvRmMemPin_in *)InBuffer;
+    p_out = (NvRmMemPin_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemPin_params, out) - OFFSET(NvRmMemPin_params, inout));
+
+
+    p_out->ret_ = NvRmMemPin( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemAlloc_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemAlloc_in *p_in;
+    NvRmMemAlloc_out *p_out;
+    NvRmHeap *Heaps = NULL;
+
+    p_in = (NvRmMemAlloc_in *)InBuffer;
+    p_out = (NvRmMemAlloc_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemAlloc_params, out) - OFFSET(NvRmMemAlloc_params, inout));
+
+    if( p_in->NumHeaps && p_in->Heaps )
+    {
+        Heaps = (NvRmHeap  *)NvOsAlloc( p_in->NumHeaps * sizeof( NvRmHeap  ) );
+        if( !Heaps )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Heaps )
+        {
+            err_ = NvOsCopyIn( Heaps, p_in->Heaps, p_in->NumHeaps * sizeof( NvRmHeap  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmMemAlloc( p_in->hMem, Heaps, p_in->NumHeaps, p_in->Alignment, p_in->Coherency );
+
+clean:
+    NvOsFree( Heaps );
+    return err_;
+}
+
+static NvError NvRmMemHandleFree_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemHandleFree_in *p_in;
+
+    p_in = (NvRmMemHandleFree_in *)InBuffer;
+
+    if (p_in->hMem != NULL) NvRtFreeObjRef(Ctx, NvRtObjType_NvRm_NvRmMemHandle, p_in->hMem);
+
+    NvRmMemHandleFree( p_in->hMem );
+
+    return err_;
+}
+
+static NvError NvRmMemHandlePreserveHandle_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemHandlePreserveHandle_in *p_in;
+    NvRmMemHandlePreserveHandle_out *p_out;
+
+    p_in = (NvRmMemHandlePreserveHandle_in *)InBuffer;
+    p_out = (NvRmMemHandlePreserveHandle_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemHandlePreserveHandle_params, out) - OFFSET(NvRmMemHandlePreserveHandle_params, inout));
+
+
+    p_out->ret_ = NvRmMemHandlePreserveHandle( p_in->hMem, &p_out->Key );
+
+    return err_;
+}
+
+static NvError NvRmMemHandleClaimPreservedHandle_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemHandleClaimPreservedHandle_in *p_in;
+    NvRmMemHandleClaimPreservedHandle_out *p_out;
+    NvRtObjRefHandle ref_phMem = 0;
+
+    p_in = (NvRmMemHandleClaimPreservedHandle_in *)InBuffer;
+    p_out = (NvRmMemHandleClaimPreservedHandle_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemHandleClaimPreservedHandle_params, out) - OFFSET(NvRmMemHandleClaimPreservedHandle_params, inout));
+
+    err_ = NvRtAllocObjRef(Ctx, &ref_phMem);
+    if (err_ != NvSuccess)
+    {
+        goto clean;
+    }
+
+    p_out->ret_ = NvRmMemHandleClaimPreservedHandle( p_in->hDevice, p_in->Key, &p_out->phMem );
+
+    if ( p_out->ret_ == NvSuccess )
+    {
+        NvRtStoreObjRef(Ctx, ref_phMem, NvRtObjType_NvRm_NvRmMemHandle, p_out->phMem);
+        ref_phMem = 0;
+    }
+clean:
+    if (ref_phMem) NvRtDiscardObjRef(Ctx, ref_phMem);
+    return err_;
+}
+
+static NvError NvRmMemHandleCreate_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMemHandleCreate_in *p_in;
+    NvRmMemHandleCreate_out *p_out;
+    NvRtObjRefHandle ref_phMem = 0;
+
+    p_in = (NvRmMemHandleCreate_in *)InBuffer;
+    p_out = (NvRmMemHandleCreate_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMemHandleCreate_params, out) - OFFSET(NvRmMemHandleCreate_params, inout));
+
+    err_ = NvRtAllocObjRef(Ctx, &ref_phMem);
+    if (err_ != NvSuccess)
+    {
+        goto clean;
+    }
+
+    p_out->ret_ = NvRmMemHandleCreate( p_in->hDevice, &p_out->phMem, p_in->Size );
+
+    if ( p_out->ret_ == NvSuccess )
+    {
+        NvRtStoreObjRef(Ctx, ref_phMem, NvRtObjType_NvRm_NvRmMemHandle, p_out->phMem);
+        ref_phMem = 0;
+    }
+clean:
+    if (ref_phMem) NvRtDiscardObjRef(Ctx, ref_phMem);
+    return err_;
+}
+
+NvError nvrm_memmgr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_memmgr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 17:
+        err_ = NvRmMemGetStat_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 16:
+        err_ = NvRmMemHandleFromId_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 15:
+        err_ = NvRmMemGetId_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 14:
+        err_ = NvRmMemGetHeapType_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 13:
+        err_ = NvRmMemGetCacheLineSize_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 12:
+        err_ = NvRmMemGetAlignment_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 11:
+        err_ = NvRmMemGetSize_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 10:
+        err_ = NvRmMemMove_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 9:
+        err_ = NvRmMemUnpinMult_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 8:
+        err_ = NvRmMemUnpin_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 7:
+        err_ = NvRmMemGetAddress_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmMemPinMult_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmMemPin_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmMemAlloc_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmMemHandleFree_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmMemHandlePreserveHandle_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmMemHandleClaimPreservedHandle_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmMemHandleCreate_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_module_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_module_dispatch.c
new file mode 100644
index 000000000000..70a8eec1e2b8
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_module_dispatch.c
@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_module.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRegw08_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle rm;
+    NvRmModuleID aperture;
+    NvU32 offset;
+    NvU8 data;
+} NV_ALIGN(4) NvRegw08_in;
+
+typedef struct NvRegw08_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegw08_inout;
+
+typedef struct NvRegw08_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegw08_out;
+
+typedef struct NvRegw08_params_t
+{
+    NvRegw08_in in;
+    NvRegw08_inout inout;
+    NvRegw08_out out;
+} NvRegw08_params;
+
+typedef struct NvRegr08_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 offset;
+} NV_ALIGN(4) NvRegr08_in;
+
+typedef struct NvRegr08_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegr08_inout;
+
+typedef struct NvRegr08_out_t
+{
+    NvU8 ret_;
+} NV_ALIGN(4) NvRegr08_out;
+
+typedef struct NvRegr08_params_t
+{
+    NvRegr08_in in;
+    NvRegr08_inout inout;
+    NvRegr08_out out;
+} NvRegr08_params;
+
+typedef struct NvRegrb_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 num;
+    NvU32 offset;
+    NvU32  * values;
+} NV_ALIGN(4) NvRegrb_in;
+
+typedef struct NvRegrb_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegrb_inout;
+
+typedef struct NvRegrb_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegrb_out;
+
+typedef struct NvRegrb_params_t
+{
+    NvRegrb_in in;
+    NvRegrb_inout inout;
+    NvRegrb_out out;
+} NvRegrb_params;
+
+typedef struct NvRegwb_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 num;
+    NvU32 offset;
+    NvU32  * values;
+} NV_ALIGN(4) NvRegwb_in;
+
+typedef struct NvRegwb_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegwb_inout;
+
+typedef struct NvRegwb_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegwb_out;
+
+typedef struct NvRegwb_params_t
+{
+    NvRegwb_in in;
+    NvRegwb_inout inout;
+    NvRegwb_out out;
+} NvRegwb_params;
+
+typedef struct NvRegwm_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 num;
+    NvU32  * offsets;
+    NvU32  * values;
+} NV_ALIGN(4) NvRegwm_in;
+
+typedef struct NvRegwm_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegwm_inout;
+
+typedef struct NvRegwm_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegwm_out;
+
+typedef struct NvRegwm_params_t
+{
+    NvRegwm_in in;
+    NvRegwm_inout inout;
+    NvRegwm_out out;
+} NvRegwm_params;
+
+typedef struct NvRegrm_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 num;
+    NvU32  * offsets;
+    NvU32  * values;
+} NV_ALIGN(4) NvRegrm_in;
+
+typedef struct NvRegrm_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegrm_inout;
+
+typedef struct NvRegrm_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegrm_out;
+
+typedef struct NvRegrm_params_t
+{
+    NvRegrm_in in;
+    NvRegrm_inout inout;
+    NvRegrm_out out;
+} NvRegrm_params;
+
+typedef struct NvRegw_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 offset;
+    NvU32 data;
+} NV_ALIGN(4) NvRegw_in;
+
+typedef struct NvRegw_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegw_inout;
+
+typedef struct NvRegw_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegw_out;
+
+typedef struct NvRegw_params_t
+{
+    NvRegw_in in;
+    NvRegw_inout inout;
+    NvRegw_out out;
+} NvRegw_params;
+
+typedef struct NvRegr_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvRmModuleID aperture;
+    NvU32 offset;
+} NV_ALIGN(4) NvRegr_in;
+
+typedef struct NvRegr_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRegr_inout;
+
+typedef struct NvRegr_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRegr_out;
+
+typedef struct NvRegr_params_t
+{
+    NvRegr_in in;
+    NvRegr_inout inout;
+    NvRegr_out out;
+} NvRegr_params;
+
+typedef struct NvRmGetRandomBytes_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvU32 NumBytes;
+    void* pBytes;
+} NV_ALIGN(4) NvRmGetRandomBytes_in;
+
+typedef struct NvRmGetRandomBytes_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetRandomBytes_inout;
+
+typedef struct NvRmGetRandomBytes_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmGetRandomBytes_out;
+
+typedef struct NvRmGetRandomBytes_params_t
+{
+    NvRmGetRandomBytes_in in;
+    NvRmGetRandomBytes_inout inout;
+    NvRmGetRandomBytes_out out;
+} NvRmGetRandomBytes_params;
+
+typedef struct NvRmQueryChipUniqueId_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevHandle;
+    NvU32 IdSize;
+    void* pId;
+} NV_ALIGN(4) NvRmQueryChipUniqueId_in;
+
+typedef struct NvRmQueryChipUniqueId_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmQueryChipUniqueId_inout;
+
+typedef struct NvRmQueryChipUniqueId_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmQueryChipUniqueId_out;
+
+typedef struct NvRmQueryChipUniqueId_params_t
+{
+    NvRmQueryChipUniqueId_in in;
+    NvRmQueryChipUniqueId_inout inout;
+    NvRmQueryChipUniqueId_out out;
+} NvRmQueryChipUniqueId_params;
+
+typedef struct NvRmModuleGetCapabilities_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvRmModuleID Module;
+    NvRmModuleCapability  * pCaps;
+    NvU32 NumCaps;
+} NV_ALIGN(4) NvRmModuleGetCapabilities_in;
+
+typedef struct NvRmModuleGetCapabilities_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleGetCapabilities_inout;
+
+typedef struct NvRmModuleGetCapabilities_out_t
+{
+    NvError ret_;
+    void* Capability;
+} NV_ALIGN(4) NvRmModuleGetCapabilities_out;
+
+typedef struct NvRmModuleGetCapabilities_params_t
+{
+    NvRmModuleGetCapabilities_in in;
+    NvRmModuleGetCapabilities_inout inout;
+    NvRmModuleGetCapabilities_out out;
+} NvRmModuleGetCapabilities_params;
+
+typedef struct NvRmModuleResetWithHold_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID Module;
+    NvBool bHold;
+} NV_ALIGN(4) NvRmModuleResetWithHold_in;
+
+typedef struct NvRmModuleResetWithHold_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleResetWithHold_inout;
+
+typedef struct NvRmModuleResetWithHold_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleResetWithHold_out;
+
+typedef struct NvRmModuleResetWithHold_params_t
+{
+    NvRmModuleResetWithHold_in in;
+    NvRmModuleResetWithHold_inout inout;
+    NvRmModuleResetWithHold_out out;
+} NvRmModuleResetWithHold_params;
+
+typedef struct NvRmModuleReset_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID Module;
+} NV_ALIGN(4) NvRmModuleReset_in;
+
+typedef struct NvRmModuleReset_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleReset_inout;
+
+typedef struct NvRmModuleReset_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleReset_out;
+
+typedef struct NvRmModuleReset_params_t
+{
+    NvRmModuleReset_in in;
+    NvRmModuleReset_inout inout;
+    NvRmModuleReset_out out;
+} NvRmModuleReset_params;
+
+typedef struct NvRmModuleGetNumInstances_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID Module;
+} NV_ALIGN(4) NvRmModuleGetNumInstances_in;
+
+typedef struct NvRmModuleGetNumInstances_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleGetNumInstances_inout;
+
+typedef struct NvRmModuleGetNumInstances_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmModuleGetNumInstances_out;
+
+typedef struct NvRmModuleGetNumInstances_params_t
+{
+    NvRmModuleGetNumInstances_in in;
+    NvRmModuleGetNumInstances_inout inout;
+    NvRmModuleGetNumInstances_out out;
+} NvRmModuleGetNumInstances_params;
+
+typedef struct NvRmModuleGetBaseAddress_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID Module;
+} NV_ALIGN(4) NvRmModuleGetBaseAddress_in;
+
+typedef struct NvRmModuleGetBaseAddress_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmModuleGetBaseAddress_inout;
+
+typedef struct NvRmModuleGetBaseAddress_out_t
+{
+    NvRmPhysAddr pBaseAddress;
+    NvU32 pSize;
+} NV_ALIGN(4) NvRmModuleGetBaseAddress_out;
+
+typedef struct NvRmModuleGetBaseAddress_params_t
+{
+    NvRmModuleGetBaseAddress_in in;
+    NvRmModuleGetBaseAddress_inout inout;
+    NvRmModuleGetBaseAddress_out out;
+} NvRmModuleGetBaseAddress_params;
+
+typedef struct NvRmModuleGetModuleInfo_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmModuleID module;
+    NvRmModuleInfo  * pModuleInfo;
+} NV_ALIGN(4) NvRmModuleGetModuleInfo_in;
+
+typedef struct NvRmModuleGetModuleInfo_inout_t
+{
+    NvU32 pNum;
+} NV_ALIGN(4) NvRmModuleGetModuleInfo_inout;
+
+typedef struct NvRmModuleGetModuleInfo_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmModuleGetModuleInfo_out;
+
+typedef struct NvRmModuleGetModuleInfo_params_t
+{
+    NvRmModuleGetModuleInfo_in in;
+    NvRmModuleGetModuleInfo_inout inout;
+    NvRmModuleGetModuleInfo_out out;
+} NvRmModuleGetModuleInfo_params;
+
+static NvError NvRmModuleReset_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmModuleReset_in *p_in;
+
+    p_in = (NvRmModuleReset_in *)InBuffer;
+
+
+    NvRmModuleReset( p_in->hRmDeviceHandle, p_in->Module );
+
+    return err_;
+}
+
+NvError nvrm_module_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_module_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 3:
+        err_ = NvRmModuleReset_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvSuccess;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_owr_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_owr_dispatch.c
new file mode 100644
index 000000000000..57f9b7b703e8
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_owr_dispatch.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_owr.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmOwrTransaction_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmOwrHandle hOwr;
+    NvU32 OwrPinMap;
+    NvU8  * Data;
+    NvU32 DataLen;
+    NvRmOwrTransactionInfo  * Transaction;
+    NvU32 NumOfTransactions;
+} NV_ALIGN(4) NvRmOwrTransaction_in;
+
+typedef struct NvRmOwrTransaction_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOwrTransaction_inout;
+
+typedef struct NvRmOwrTransaction_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmOwrTransaction_out;
+
+typedef struct NvRmOwrTransaction_params_t
+{
+    NvRmOwrTransaction_in in;
+    NvRmOwrTransaction_inout inout;
+    NvRmOwrTransaction_out out;
+} NvRmOwrTransaction_params;
+
+typedef struct NvRmOwrClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmOwrHandle hOwr;
+} NV_ALIGN(4) NvRmOwrClose_in;
+
+typedef struct NvRmOwrClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOwrClose_inout;
+
+typedef struct NvRmOwrClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOwrClose_out;
+
+typedef struct NvRmOwrClose_params_t
+{
+    NvRmOwrClose_in in;
+    NvRmOwrClose_inout inout;
+    NvRmOwrClose_out out;
+} NvRmOwrClose_params;
+
+typedef struct NvRmOwrOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 instance;
+} NV_ALIGN(4) NvRmOwrOpen_in;
+
+typedef struct NvRmOwrOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmOwrOpen_inout;
+
+typedef struct NvRmOwrOpen_out_t
+{
+    NvError ret_;
+    NvRmOwrHandle hOwr;
+} NV_ALIGN(4) NvRmOwrOpen_out;
+
+typedef struct NvRmOwrOpen_params_t
+{
+    NvRmOwrOpen_in in;
+    NvRmOwrOpen_inout inout;
+    NvRmOwrOpen_out out;
+} NvRmOwrOpen_params;
+
+static NvError NvRmOwrTransaction_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmOwrTransaction_in *p_in;
+    NvRmOwrTransaction_out *p_out;
+    NvU8  *Data = NULL;
+    NvRmOwrTransactionInfo *Transaction = NULL;
+
+    p_in = (NvRmOwrTransaction_in *)InBuffer;
+    p_out = (NvRmOwrTransaction_out *)((NvU8 *)OutBuffer + OFFSET(NvRmOwrTransaction_params, out) - OFFSET(NvRmOwrTransaction_params, inout));
+
+    if( p_in->DataLen && p_in->Data )
+    {
+        Data = (NvU8  *)NvOsAlloc( p_in->DataLen * sizeof( NvU8  ) );
+        if( !Data )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Data )
+        {
+            err_ = NvOsCopyIn( Data, p_in->Data, p_in->DataLen * sizeof( NvU8  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+    if( p_in->NumOfTransactions && p_in->Transaction )
+    {
+        Transaction = (NvRmOwrTransactionInfo  *)NvOsAlloc( p_in->NumOfTransactions * sizeof( NvRmOwrTransactionInfo  ) );
+        if( !Transaction )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Transaction )
+        {
+            err_ = NvOsCopyIn( Transaction, p_in->Transaction, p_in->NumOfTransactions * sizeof( NvRmOwrTransactionInfo  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmOwrTransaction( p_in->hOwr, p_in->OwrPinMap, Data, p_in->DataLen, Transaction, p_in->NumOfTransactions );
+
+    if(p_in->Data && Data)
+    {
+        err_ = NvOsCopyOut( p_in->Data, Data, p_in->DataLen * sizeof( NvU8  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( Data );
+    NvOsFree( Transaction );
+    return err_;
+}
+
+static NvError NvRmOwrClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmOwrClose_in *p_in;
+
+    p_in = (NvRmOwrClose_in *)InBuffer;
+
+
+    NvRmOwrClose( p_in->hOwr );
+
+    return err_;
+}
+
+static NvError NvRmOwrOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmOwrOpen_in *p_in;
+    NvRmOwrOpen_out *p_out;
+
+    p_in = (NvRmOwrOpen_in *)InBuffer;
+    p_out = (NvRmOwrOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmOwrOpen_params, out) - OFFSET(NvRmOwrOpen_params, inout));
+
+
+    p_out->ret_ = NvRmOwrOpen( p_in->hDevice, p_in->instance, &p_out->hOwr );
+
+    return err_;
+}
+
+NvError nvrm_owr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_owr_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 2:
+        err_ = NvRmOwrTransaction_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmOwrClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmOwrOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pcie_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pcie_dispatch.c
new file mode 100644
index 000000000000..1a6b9344b493
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pcie_dispatch.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_pcie.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmUnmapPciMemory_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvRmPhysAddr mem;
+    NvU32 size;
+} NV_ALIGN(4) NvRmUnmapPciMemory_in;
+
+typedef struct NvRmUnmapPciMemory_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmUnmapPciMemory_inout;
+
+typedef struct NvRmUnmapPciMemory_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmUnmapPciMemory_out;
+
+typedef struct NvRmUnmapPciMemory_params_t
+{
+    NvRmUnmapPciMemory_in in;
+    NvRmUnmapPciMemory_inout inout;
+    NvRmUnmapPciMemory_out out;
+} NvRmUnmapPciMemory_params;
+
+typedef struct NvRmMapPciMemory_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvRmPciPhysAddr mem;
+    NvU32 size;
+} NV_ALIGN(4) NvRmMapPciMemory_in;
+
+typedef struct NvRmMapPciMemory_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmMapPciMemory_inout;
+
+typedef struct NvRmMapPciMemory_out_t
+{
+    NvRmPhysAddr ret_;
+} NV_ALIGN(4) NvRmMapPciMemory_out;
+
+typedef struct NvRmMapPciMemory_params_t
+{
+    NvRmMapPciMemory_in in;
+    NvRmMapPciMemory_inout inout;
+    NvRmMapPciMemory_out out;
+} NvRmMapPciMemory_params;
+
+typedef struct NvRmRegisterPcieLegacyHandler_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvU32 function_device_bus;
+    NvOsSemaphoreHandle sem;
+    NvBool InterruptEnable;
+} NV_ALIGN(4) NvRmRegisterPcieLegacyHandler_in;
+
+typedef struct NvRmRegisterPcieLegacyHandler_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmRegisterPcieLegacyHandler_inout;
+
+typedef struct NvRmRegisterPcieLegacyHandler_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmRegisterPcieLegacyHandler_out;
+
+typedef struct NvRmRegisterPcieLegacyHandler_params_t
+{
+    NvRmRegisterPcieLegacyHandler_in in;
+    NvRmRegisterPcieLegacyHandler_inout inout;
+    NvRmRegisterPcieLegacyHandler_out out;
+} NvRmRegisterPcieLegacyHandler_params;
+
+typedef struct NvRmRegisterPcieMSIHandler_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvU32 function_device_bus;
+    NvU32 index;
+    NvOsSemaphoreHandle sem;
+    NvBool InterruptEnable;
+} NV_ALIGN(4) NvRmRegisterPcieMSIHandler_in;
+
+typedef struct NvRmRegisterPcieMSIHandler_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmRegisterPcieMSIHandler_inout;
+
+typedef struct NvRmRegisterPcieMSIHandler_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmRegisterPcieMSIHandler_out;
+
+typedef struct NvRmRegisterPcieMSIHandler_params_t
+{
+    NvRmRegisterPcieMSIHandler_in in;
+    NvRmRegisterPcieMSIHandler_inout inout;
+    NvRmRegisterPcieMSIHandler_out out;
+} NvRmRegisterPcieMSIHandler_params;
+
+typedef struct NvRmReadWriteConfigSpace_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDeviceHandle;
+    NvU32 bus_number;
+    NvRmPcieAccessType type;
+    NvU32 offset;
+    NvU8  * Data;
+    NvU32 DataLen;
+} NV_ALIGN(4) NvRmReadWriteConfigSpace_in;
+
+typedef struct NvRmReadWriteConfigSpace_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmReadWriteConfigSpace_inout;
+
+typedef struct NvRmReadWriteConfigSpace_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmReadWriteConfigSpace_out;
+
+typedef struct NvRmReadWriteConfigSpace_params_t
+{
+    NvRmReadWriteConfigSpace_in in;
+    NvRmReadWriteConfigSpace_inout inout;
+    NvRmReadWriteConfigSpace_out out;
+} NvRmReadWriteConfigSpace_params;
+
+static NvError NvRmUnmapPciMemory_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmUnmapPciMemory_in *p_in;
+
+    p_in = (NvRmUnmapPciMemory_in *)InBuffer;
+
+
+    NvRmUnmapPciMemory( p_in->hDeviceHandle, p_in->mem, p_in->size );
+
+    return err_;
+}
+
+static NvError NvRmMapPciMemory_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmMapPciMemory_in *p_in;
+    NvRmMapPciMemory_out *p_out;
+
+    p_in = (NvRmMapPciMemory_in *)InBuffer;
+    p_out = (NvRmMapPciMemory_out *)((NvU8 *)OutBuffer + OFFSET(NvRmMapPciMemory_params, out) - OFFSET(NvRmMapPciMemory_params, inout));
+
+
+    p_out->ret_ = NvRmMapPciMemory( p_in->hDeviceHandle, p_in->mem, p_in->size );
+
+    return err_;
+}
+
+static NvError NvRmRegisterPcieLegacyHandler_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmRegisterPcieLegacyHandler_in *p_in;
+    NvRmRegisterPcieLegacyHandler_out *p_out;
+    NvOsSemaphoreHandle sem = NULL;
+
+    p_in = (NvRmRegisterPcieLegacyHandler_in *)InBuffer;
+    p_out = (NvRmRegisterPcieLegacyHandler_out *)((NvU8 *)OutBuffer + OFFSET(NvRmRegisterPcieLegacyHandler_params, out) - OFFSET(NvRmRegisterPcieLegacyHandler_params, inout));
+
+    if( p_in->sem )
+    {
+        err_ = NvOsSemaphoreUnmarshal( p_in->sem, &sem );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmRegisterPcieLegacyHandler( p_in->hDeviceHandle, p_in->function_device_bus, sem, p_in->InterruptEnable );
+
+clean:
+    NvOsSemaphoreDestroy( sem );
+    return err_;
+}
+
+static NvError NvRmRegisterPcieMSIHandler_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmRegisterPcieMSIHandler_in *p_in;
+    NvRmRegisterPcieMSIHandler_out *p_out;
+    NvOsSemaphoreHandle sem = NULL;
+
+    p_in = (NvRmRegisterPcieMSIHandler_in *)InBuffer;
+    p_out = (NvRmRegisterPcieMSIHandler_out *)((NvU8 *)OutBuffer + OFFSET(NvRmRegisterPcieMSIHandler_params, out) - OFFSET(NvRmRegisterPcieMSIHandler_params, inout));
+
+    if( p_in->sem )
+    {
+        err_ = NvOsSemaphoreUnmarshal( p_in->sem, &sem );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmRegisterPcieMSIHandler( p_in->hDeviceHandle, p_in->function_device_bus, p_in->index, sem, p_in->InterruptEnable );
+
+clean:
+    NvOsSemaphoreDestroy( sem );
+    return err_;
+}
+
+static NvError NvRmReadWriteConfigSpace_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmReadWriteConfigSpace_in *p_in;
+    NvRmReadWriteConfigSpace_out *p_out;
+    NvU8  *Data = NULL;
+
+    p_in = (NvRmReadWriteConfigSpace_in *)InBuffer;
+    p_out = (NvRmReadWriteConfigSpace_out *)((NvU8 *)OutBuffer + OFFSET(NvRmReadWriteConfigSpace_params, out) - OFFSET(NvRmReadWriteConfigSpace_params, inout));
+
+    if( p_in->DataLen && p_in->Data )
+    {
+        Data = (NvU8  *)NvOsAlloc( p_in->DataLen * sizeof( NvU8  ) );
+        if( !Data )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->Data )
+        {
+            err_ = NvOsCopyIn( Data, p_in->Data, p_in->DataLen * sizeof( NvU8  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmReadWriteConfigSpace( p_in->hDeviceHandle, p_in->bus_number, p_in->type, p_in->offset, Data, p_in->DataLen );
+
+    if(p_in->Data && Data)
+    {
+        err_ = NvOsCopyOut( p_in->Data, Data, p_in->DataLen * sizeof( NvU8  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( Data );
+    return err_;
+}
+
+NvError nvrm_pcie_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pcie_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 4:
+        err_ = NvRmUnmapPciMemory_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmMapPciMemory_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmRegisterPcieLegacyHandler_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmRegisterPcieMSIHandler_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmReadWriteConfigSpace_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pinmux_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pinmux_dispatch.c
new file mode 100644
index 000000000000..4064ca6e0029
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pinmux_dispatch.c
@@ -0,0 +1,301 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_pinmux.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmGetStraps_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmStrapGroup StrapGroup;
+} NV_ALIGN(4) NvRmGetStraps_in;
+
+typedef struct NvRmGetStraps_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetStraps_inout;
+
+typedef struct NvRmGetStraps_out_t
+{
+    NvError ret_;
+    NvU32 pStrapValue;
+} NV_ALIGN(4) NvRmGetStraps_out;
+
+typedef struct NvRmGetStraps_params_t
+{
+    NvRmGetStraps_in in;
+    NvRmGetStraps_inout inout;
+    NvRmGetStraps_out out;
+} NvRmGetStraps_params;
+
+typedef struct NvRmGetModuleInterfaceCapabilities_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRm;
+    NvRmModuleID ModuleId;
+    NvU32 CapStructSize;
+    void* pCaps;
+} NV_ALIGN(4) NvRmGetModuleInterfaceCapabilities_in;
+
+typedef struct NvRmGetModuleInterfaceCapabilities_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmGetModuleInterfaceCapabilities_inout;
+
+typedef struct NvRmGetModuleInterfaceCapabilities_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmGetModuleInterfaceCapabilities_out;
+
+typedef struct NvRmGetModuleInterfaceCapabilities_params_t
+{
+    NvRmGetModuleInterfaceCapabilities_in in;
+    NvRmGetModuleInterfaceCapabilities_inout inout;
+    NvRmGetModuleInterfaceCapabilities_out out;
+} NvRmGetModuleInterfaceCapabilities_params;
+
+typedef struct NvRmExternalClockConfig_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 IoModule;
+    NvU32 Instance;
+    NvU32 Config;
+    NvBool EnableTristate;
+} NV_ALIGN(4) NvRmExternalClockConfig_in;
+
+typedef struct NvRmExternalClockConfig_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmExternalClockConfig_inout;
+
+typedef struct NvRmExternalClockConfig_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmExternalClockConfig_out;
+
+typedef struct NvRmExternalClockConfig_params_t
+{
+    NvRmExternalClockConfig_in in;
+    NvRmExternalClockConfig_inout inout;
+    NvRmExternalClockConfig_out out;
+} NvRmExternalClockConfig_params;
+
+typedef struct NvRmSetOdmModuleTristate_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 OdmModule;
+    NvU32 OdmInstance;
+    NvBool EnableTristate;
+} NV_ALIGN(4) NvRmSetOdmModuleTristate_in;
+
+typedef struct NvRmSetOdmModuleTristate_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSetOdmModuleTristate_inout;
+
+typedef struct NvRmSetOdmModuleTristate_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmSetOdmModuleTristate_out;
+
+typedef struct NvRmSetOdmModuleTristate_params_t
+{
+    NvRmSetOdmModuleTristate_in in;
+    NvRmSetOdmModuleTristate_inout inout;
+    NvRmSetOdmModuleTristate_out out;
+} NvRmSetOdmModuleTristate_params;
+
+typedef struct NvRmSetModuleTristate_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvRmModuleID RmModule;
+    NvBool EnableTristate;
+} NV_ALIGN(4) NvRmSetModuleTristate_in;
+
+typedef struct NvRmSetModuleTristate_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSetModuleTristate_inout;
+
+typedef struct NvRmSetModuleTristate_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmSetModuleTristate_out;
+
+typedef struct NvRmSetModuleTristate_params_t
+{
+    NvRmSetModuleTristate_in in;
+    NvRmSetModuleTristate_inout inout;
+    NvRmSetModuleTristate_out out;
+} NvRmSetModuleTristate_params;
+
+static NvError NvRmGetStraps_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGetStraps_in *p_in;
+    NvRmGetStraps_out *p_out;
+
+    p_in = (NvRmGetStraps_in *)InBuffer;
+    p_out = (NvRmGetStraps_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGetStraps_params, out) - OFFSET(NvRmGetStraps_params, inout));
+
+
+    p_out->ret_ = NvRmGetStraps( p_in->hDevice, p_in->StrapGroup, &p_out->pStrapValue );
+
+    return err_;
+}
+
+static NvError NvRmGetModuleInterfaceCapabilities_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmGetModuleInterfaceCapabilities_in *p_in;
+    NvRmGetModuleInterfaceCapabilities_out *p_out;
+    void*  pCaps = NULL;
+
+    p_in = (NvRmGetModuleInterfaceCapabilities_in *)InBuffer;
+    p_out = (NvRmGetModuleInterfaceCapabilities_out *)((NvU8 *)OutBuffer + OFFSET(NvRmGetModuleInterfaceCapabilities_params, out) - OFFSET(NvRmGetModuleInterfaceCapabilities_params, inout));
+
+    if( p_in->CapStructSize && p_in->pCaps )
+    {
+        pCaps = (void*  )NvOsAlloc( p_in->CapStructSize );
+        if( !pCaps )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmGetModuleInterfaceCapabilities( p_in->hRm, p_in->ModuleId, p_in->CapStructSize, pCaps );
+
+    if(p_in->pCaps && pCaps)
+    {
+        err_ = NvOsCopyOut( p_in->pCaps, pCaps, p_in->CapStructSize );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pCaps );
+    return err_;
+}
+
+static NvError NvRmExternalClockConfig_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmExternalClockConfig_in *p_in;
+    NvRmExternalClockConfig_out *p_out;
+
+    p_in = (NvRmExternalClockConfig_in *)InBuffer;
+    p_out = (NvRmExternalClockConfig_out *)((NvU8 *)OutBuffer + OFFSET(NvRmExternalClockConfig_params, out) - OFFSET(NvRmExternalClockConfig_params, inout));
+
+
+    p_out->ret_ = NvRmExternalClockConfig( p_in->hDevice, p_in->IoModule, p_in->Instance, p_in->Config, p_in->EnableTristate );
+
+    return err_;
+}
+
+static NvError NvRmSetOdmModuleTristate_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSetOdmModuleTristate_in *p_in;
+    NvRmSetOdmModuleTristate_out *p_out;
+
+    p_in = (NvRmSetOdmModuleTristate_in *)InBuffer;
+    p_out = (NvRmSetOdmModuleTristate_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSetOdmModuleTristate_params, out) - OFFSET(NvRmSetOdmModuleTristate_params, inout));
+
+
+    p_out->ret_ = NvRmSetOdmModuleTristate( p_in->hDevice, p_in->OdmModule, p_in->OdmInstance, p_in->EnableTristate );
+
+    return err_;
+}
+
+static NvError NvRmSetModuleTristate_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSetModuleTristate_in *p_in;
+    NvRmSetModuleTristate_out *p_out;
+
+    p_in = (NvRmSetModuleTristate_in *)InBuffer;
+    p_out = (NvRmSetModuleTristate_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSetModuleTristate_params, out) - OFFSET(NvRmSetModuleTristate_params, inout));
+
+
+    p_out->ret_ = NvRmSetModuleTristate( p_in->hDevice, p_in->RmModule, p_in->EnableTristate );
+
+    return err_;
+}
+
+NvError nvrm_pinmux_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pinmux_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 4:
+        err_ = NvRmGetStraps_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmGetModuleInterfaceCapabilities_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmExternalClockConfig_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmSetOdmModuleTristate_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmSetModuleTristate_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pmu_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pmu_dispatch.c
new file mode 100644
index 000000000000..593d6e256bd7
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pmu_dispatch.c
@@ -0,0 +1,617 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_pmu.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmPmuIsRtcInitialized_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmPmuIsRtcInitialized_in;
+
+typedef struct NvRmPmuIsRtcInitialized_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuIsRtcInitialized_inout;
+
+typedef struct NvRmPmuIsRtcInitialized_out_t
+{
+    NvBool ret_;
+} NV_ALIGN(4) NvRmPmuIsRtcInitialized_out;
+
+typedef struct NvRmPmuIsRtcInitialized_params_t
+{
+    NvRmPmuIsRtcInitialized_in in;
+    NvRmPmuIsRtcInitialized_inout inout;
+    NvRmPmuIsRtcInitialized_out out;
+} NvRmPmuIsRtcInitialized_params;
+
+typedef struct NvRmPmuWriteRtc_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvU32 Count;
+} NV_ALIGN(4) NvRmPmuWriteRtc_in;
+
+typedef struct NvRmPmuWriteRtc_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuWriteRtc_inout;
+
+typedef struct NvRmPmuWriteRtc_out_t
+{
+    NvBool ret_;
+} NV_ALIGN(4) NvRmPmuWriteRtc_out;
+
+typedef struct NvRmPmuWriteRtc_params_t
+{
+    NvRmPmuWriteRtc_in in;
+    NvRmPmuWriteRtc_inout inout;
+    NvRmPmuWriteRtc_out out;
+} NvRmPmuWriteRtc_params;
+
+typedef struct NvRmPmuReadRtc_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmPmuReadRtc_in;
+
+typedef struct NvRmPmuReadRtc_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuReadRtc_inout;
+
+typedef struct NvRmPmuReadRtc_out_t
+{
+    NvBool ret_;
+    NvU32 pCount;
+} NV_ALIGN(4) NvRmPmuReadRtc_out;
+
+typedef struct NvRmPmuReadRtc_params_t
+{
+    NvRmPmuReadRtc_in in;
+    NvRmPmuReadRtc_inout inout;
+    NvRmPmuReadRtc_out out;
+} NvRmPmuReadRtc_params;
+
+typedef struct NvRmPmuGetBatteryChemistry_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmPmuBatteryInstance batteryInst;
+} NV_ALIGN(4) NvRmPmuGetBatteryChemistry_in;
+
+typedef struct NvRmPmuGetBatteryChemistry_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetBatteryChemistry_inout;
+
+typedef struct NvRmPmuGetBatteryChemistry_out_t
+{
+    NvRmPmuBatteryChemistry pChemistry;
+} NV_ALIGN(4) NvRmPmuGetBatteryChemistry_out;
+
+typedef struct NvRmPmuGetBatteryChemistry_params_t
+{
+    NvRmPmuGetBatteryChemistry_in in;
+    NvRmPmuGetBatteryChemistry_inout inout;
+    NvRmPmuGetBatteryChemistry_out out;
+} NvRmPmuGetBatteryChemistry_params;
+
+typedef struct NvRmPmuGetBatteryFullLifeTime_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmPmuBatteryInstance batteryInst;
+} NV_ALIGN(4) NvRmPmuGetBatteryFullLifeTime_in;
+
+typedef struct NvRmPmuGetBatteryFullLifeTime_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetBatteryFullLifeTime_inout;
+
+typedef struct NvRmPmuGetBatteryFullLifeTime_out_t
+{
+    NvU32 pLifeTime;
+} NV_ALIGN(4) NvRmPmuGetBatteryFullLifeTime_out;
+
+typedef struct NvRmPmuGetBatteryFullLifeTime_params_t
+{
+    NvRmPmuGetBatteryFullLifeTime_in in;
+    NvRmPmuGetBatteryFullLifeTime_inout inout;
+    NvRmPmuGetBatteryFullLifeTime_out out;
+} NvRmPmuGetBatteryFullLifeTime_params;
+
+typedef struct NvRmPmuGetBatteryData_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmPmuBatteryInstance batteryInst;
+} NV_ALIGN(4) NvRmPmuGetBatteryData_in;
+
+typedef struct NvRmPmuGetBatteryData_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetBatteryData_inout;
+
+typedef struct NvRmPmuGetBatteryData_out_t
+{
+    NvBool ret_;
+    NvRmPmuBatteryData pData;
+} NV_ALIGN(4) NvRmPmuGetBatteryData_out;
+
+typedef struct NvRmPmuGetBatteryData_params_t
+{
+    NvRmPmuGetBatteryData_in in;
+    NvRmPmuGetBatteryData_inout inout;
+    NvRmPmuGetBatteryData_out out;
+} NvRmPmuGetBatteryData_params;
+
+typedef struct NvRmPmuGetBatteryStatus_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmPmuBatteryInstance batteryInst;
+} NV_ALIGN(4) NvRmPmuGetBatteryStatus_in;
+
+typedef struct NvRmPmuGetBatteryStatus_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetBatteryStatus_inout;
+
+typedef struct NvRmPmuGetBatteryStatus_out_t
+{
+    NvBool ret_;
+    NvU8 pStatus;
+} NV_ALIGN(4) NvRmPmuGetBatteryStatus_out;
+
+typedef struct NvRmPmuGetBatteryStatus_params_t
+{
+    NvRmPmuGetBatteryStatus_in in;
+    NvRmPmuGetBatteryStatus_inout inout;
+    NvRmPmuGetBatteryStatus_out out;
+} NvRmPmuGetBatteryStatus_params;
+
+typedef struct NvRmPmuGetAcLineStatus_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmPmuGetAcLineStatus_in;
+
+typedef struct NvRmPmuGetAcLineStatus_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetAcLineStatus_inout;
+
+typedef struct NvRmPmuGetAcLineStatus_out_t
+{
+    NvBool ret_;
+    NvRmPmuAcLineStatus pStatus;
+} NV_ALIGN(4) NvRmPmuGetAcLineStatus_out;
+
+typedef struct NvRmPmuGetAcLineStatus_params_t
+{
+    NvRmPmuGetAcLineStatus_in in;
+    NvRmPmuGetAcLineStatus_inout inout;
+    NvRmPmuGetAcLineStatus_out out;
+} NvRmPmuGetAcLineStatus_params;
+
+typedef struct NvRmPmuSetChargingCurrentLimit_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvRmPmuChargingPath ChargingPath;
+    NvU32 ChargingCurrentLimitMa;
+    NvU32 ChargerType;
+} NV_ALIGN(4) NvRmPmuSetChargingCurrentLimit_in;
+
+typedef struct NvRmPmuSetChargingCurrentLimit_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuSetChargingCurrentLimit_inout;
+
+typedef struct NvRmPmuSetChargingCurrentLimit_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuSetChargingCurrentLimit_out;
+
+typedef struct NvRmPmuSetChargingCurrentLimit_params_t
+{
+    NvRmPmuSetChargingCurrentLimit_in in;
+    NvRmPmuSetChargingCurrentLimit_inout inout;
+    NvRmPmuSetChargingCurrentLimit_out out;
+} NvRmPmuSetChargingCurrentLimit_params;
+
+typedef struct NvRmPmuSetSocRailPowerState_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 vddId;
+    NvBool Enable;
+} NV_ALIGN(4) NvRmPmuSetSocRailPowerState_in;
+
+typedef struct NvRmPmuSetSocRailPowerState_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuSetSocRailPowerState_inout;
+
+typedef struct NvRmPmuSetSocRailPowerState_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuSetSocRailPowerState_out;
+
+typedef struct NvRmPmuSetSocRailPowerState_params_t
+{
+    NvRmPmuSetSocRailPowerState_in in;
+    NvRmPmuSetSocRailPowerState_inout inout;
+    NvRmPmuSetSocRailPowerState_out out;
+} NvRmPmuSetSocRailPowerState_params;
+
+typedef struct NvRmPmuSetVoltage_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 vddId;
+    NvU32 MilliVolts;
+} NV_ALIGN(4) NvRmPmuSetVoltage_in;
+
+typedef struct NvRmPmuSetVoltage_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuSetVoltage_inout;
+
+typedef struct NvRmPmuSetVoltage_out_t
+{
+    NvU32 pSettleMicroSeconds;
+} NV_ALIGN(4) NvRmPmuSetVoltage_out;
+
+typedef struct NvRmPmuSetVoltage_params_t
+{
+    NvRmPmuSetVoltage_in in;
+    NvRmPmuSetVoltage_inout inout;
+    NvRmPmuSetVoltage_out out;
+} NvRmPmuSetVoltage_params;
+
+typedef struct NvRmPmuGetVoltage_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 vddId;
+} NV_ALIGN(4) NvRmPmuGetVoltage_in;
+
+typedef struct NvRmPmuGetVoltage_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetVoltage_inout;
+
+typedef struct NvRmPmuGetVoltage_out_t
+{
+    NvU32 pMilliVolts;
+} NV_ALIGN(4) NvRmPmuGetVoltage_out;
+
+typedef struct NvRmPmuGetVoltage_params_t
+{
+    NvRmPmuGetVoltage_in in;
+    NvRmPmuGetVoltage_inout inout;
+    NvRmPmuGetVoltage_out out;
+} NvRmPmuGetVoltage_params;
+
+typedef struct NvRmPmuGetCapabilities_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+    NvU32 vddId;
+} NV_ALIGN(4) NvRmPmuGetCapabilities_in;
+
+typedef struct NvRmPmuGetCapabilities_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPmuGetCapabilities_inout;
+
+typedef struct NvRmPmuGetCapabilities_out_t
+{
+    NvRmPmuVddRailCapabilities pCapabilities;
+} NV_ALIGN(4) NvRmPmuGetCapabilities_out;
+
+typedef struct NvRmPmuGetCapabilities_params_t
+{
+    NvRmPmuGetCapabilities_in in;
+    NvRmPmuGetCapabilities_inout inout;
+    NvRmPmuGetCapabilities_out out;
+} NvRmPmuGetCapabilities_params;
+
+static NvError NvRmPmuIsRtcInitialized_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuIsRtcInitialized_in *p_in;
+    NvRmPmuIsRtcInitialized_out *p_out;
+
+    p_in = (NvRmPmuIsRtcInitialized_in *)InBuffer;
+    p_out = (NvRmPmuIsRtcInitialized_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuIsRtcInitialized_params, out) - OFFSET(NvRmPmuIsRtcInitialized_params, inout));
+
+
+    p_out->ret_ = NvRmPmuIsRtcInitialized( p_in->hRmDevice );
+
+    return err_;
+}
+
+static NvError NvRmPmuWriteRtc_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuWriteRtc_in *p_in;
+    NvRmPmuWriteRtc_out *p_out;
+
+    p_in = (NvRmPmuWriteRtc_in *)InBuffer;
+    p_out = (NvRmPmuWriteRtc_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuWriteRtc_params, out) - OFFSET(NvRmPmuWriteRtc_params, inout));
+
+
+    p_out->ret_ = NvRmPmuWriteRtc( p_in->hRmDevice, p_in->Count );
+
+    return err_;
+}
+
+static NvError NvRmPmuReadRtc_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuReadRtc_in *p_in;
+    NvRmPmuReadRtc_out *p_out;
+
+    p_in = (NvRmPmuReadRtc_in *)InBuffer;
+    p_out = (NvRmPmuReadRtc_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuReadRtc_params, out) - OFFSET(NvRmPmuReadRtc_params, inout));
+
+
+    p_out->ret_ = NvRmPmuReadRtc( p_in->hRmDevice, &p_out->pCount );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetBatteryChemistry_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetBatteryChemistry_in *p_in;
+    NvRmPmuGetBatteryChemistry_out *p_out;
+
+    p_in = (NvRmPmuGetBatteryChemistry_in *)InBuffer;
+    p_out = (NvRmPmuGetBatteryChemistry_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetBatteryChemistry_params, out) - OFFSET(NvRmPmuGetBatteryChemistry_params, inout));
+
+
+    NvRmPmuGetBatteryChemistry( p_in->hRmDevice, p_in->batteryInst, &p_out->pChemistry );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetBatteryFullLifeTime_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetBatteryFullLifeTime_in *p_in;
+    NvRmPmuGetBatteryFullLifeTime_out *p_out;
+
+    p_in = (NvRmPmuGetBatteryFullLifeTime_in *)InBuffer;
+    p_out = (NvRmPmuGetBatteryFullLifeTime_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetBatteryFullLifeTime_params, out) - OFFSET(NvRmPmuGetBatteryFullLifeTime_params, inout));
+
+
+    NvRmPmuGetBatteryFullLifeTime( p_in->hRmDevice, p_in->batteryInst, &p_out->pLifeTime );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetBatteryData_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetBatteryData_in *p_in;
+    NvRmPmuGetBatteryData_out *p_out;
+
+    p_in = (NvRmPmuGetBatteryData_in *)InBuffer;
+    p_out = (NvRmPmuGetBatteryData_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetBatteryData_params, out) - OFFSET(NvRmPmuGetBatteryData_params, inout));
+
+
+    p_out->ret_ = NvRmPmuGetBatteryData( p_in->hRmDevice, p_in->batteryInst, &p_out->pData );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetBatteryStatus_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetBatteryStatus_in *p_in;
+    NvRmPmuGetBatteryStatus_out *p_out;
+
+    p_in = (NvRmPmuGetBatteryStatus_in *)InBuffer;
+    p_out = (NvRmPmuGetBatteryStatus_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetBatteryStatus_params, out) - OFFSET(NvRmPmuGetBatteryStatus_params, inout));
+
+
+    p_out->ret_ = NvRmPmuGetBatteryStatus( p_in->hRmDevice, p_in->batteryInst, &p_out->pStatus );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetAcLineStatus_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetAcLineStatus_in *p_in;
+    NvRmPmuGetAcLineStatus_out *p_out;
+
+    p_in = (NvRmPmuGetAcLineStatus_in *)InBuffer;
+    p_out = (NvRmPmuGetAcLineStatus_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetAcLineStatus_params, out) - OFFSET(NvRmPmuGetAcLineStatus_params, inout));
+
+
+    p_out->ret_ = NvRmPmuGetAcLineStatus( p_in->hRmDevice, &p_out->pStatus );
+
+    return err_;
+}
+
+static NvError NvRmPmuSetChargingCurrentLimit_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuSetChargingCurrentLimit_in *p_in;
+
+    p_in = (NvRmPmuSetChargingCurrentLimit_in *)InBuffer;
+
+
+    NvRmPmuSetChargingCurrentLimit( p_in->hRmDevice, p_in->ChargingPath, p_in->ChargingCurrentLimitMa, p_in->ChargerType );
+
+    return err_;
+}
+
+static NvError NvRmPmuSetSocRailPowerState_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuSetSocRailPowerState_in *p_in;
+
+    p_in = (NvRmPmuSetSocRailPowerState_in *)InBuffer;
+
+
+    NvRmPmuSetSocRailPowerState( p_in->hDevice, p_in->vddId, p_in->Enable );
+
+    return err_;
+}
+
+static NvError NvRmPmuSetVoltage_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuSetVoltage_in *p_in;
+    NvRmPmuSetVoltage_out *p_out;
+
+    p_in = (NvRmPmuSetVoltage_in *)InBuffer;
+    p_out = (NvRmPmuSetVoltage_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuSetVoltage_params, out) - OFFSET(NvRmPmuSetVoltage_params, inout));
+
+
+    NvRmPmuSetVoltage( p_in->hDevice, p_in->vddId, p_in->MilliVolts, &p_out->pSettleMicroSeconds );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetVoltage_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetVoltage_in *p_in;
+    NvRmPmuGetVoltage_out *p_out;
+
+    p_in = (NvRmPmuGetVoltage_in *)InBuffer;
+    p_out = (NvRmPmuGetVoltage_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetVoltage_params, out) - OFFSET(NvRmPmuGetVoltage_params, inout));
+
+
+    NvRmPmuGetVoltage( p_in->hDevice, p_in->vddId, &p_out->pMilliVolts );
+
+    return err_;
+}
+
+static NvError NvRmPmuGetCapabilities_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPmuGetCapabilities_in *p_in;
+    NvRmPmuGetCapabilities_out *p_out;
+
+    p_in = (NvRmPmuGetCapabilities_in *)InBuffer;
+    p_out = (NvRmPmuGetCapabilities_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPmuGetCapabilities_params, out) - OFFSET(NvRmPmuGetCapabilities_params, inout));
+
+
+    NvRmPmuGetCapabilities( p_in->hDevice, p_in->vddId, &p_out->pCapabilities );
+
+    return err_;
+}
+
+NvError nvrm_pmu_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pmu_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 12:
+        err_ = NvRmPmuIsRtcInitialized_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 11:
+        err_ = NvRmPmuWriteRtc_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 10:
+        err_ = NvRmPmuReadRtc_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 9:
+        err_ = NvRmPmuGetBatteryChemistry_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 8:
+        err_ = NvRmPmuGetBatteryFullLifeTime_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 7:
+        err_ = NvRmPmuGetBatteryData_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmPmuGetBatteryStatus_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmPmuGetAcLineStatus_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmPmuSetChargingCurrentLimit_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmPmuSetSocRailPowerState_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmPmuSetVoltage_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmPmuGetVoltage_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmPmuGetCapabilities_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_power_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_power_dispatch.c
new file mode 100644
index 000000000000..fd80efcb642f
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_power_dispatch.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_power.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+typedef struct NvRmPowerVoltageControl_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID ModuleId;
+    NvU32 ClientId;
+    NvRmMilliVolts MinVolts;
+    NvRmMilliVolts MaxVolts;
+    NvRmMilliVolts  * PrefVoltageList;
+    NvU32 PrefVoltageListCount;
+} NV_ALIGN(4) NvRmPowerVoltageControl_in;
+
+typedef struct NvRmPowerVoltageControl_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerVoltageControl_inout;
+
+typedef struct NvRmPowerVoltageControl_out_t
+{
+    NvError ret_;
+    NvRmMilliVolts CurrentVolts;
+} NV_ALIGN(4) NvRmPowerVoltageControl_out;
+
+typedef struct NvRmPowerVoltageControl_params_t
+{
+    NvRmPowerVoltageControl_in in;
+    NvRmPowerVoltageControl_inout inout;
+    NvRmPowerVoltageControl_out out;
+} NvRmPowerVoltageControl_params;
+
+typedef struct NvRmPowerModuleClockControl_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID ModuleId;
+    NvU32 ClientId;
+    NvBool Enable;
+} NV_ALIGN(4) NvRmPowerModuleClockControl_in;
+
+typedef struct NvRmPowerModuleClockControl_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerModuleClockControl_inout;
+
+typedef struct NvRmPowerModuleClockControl_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmPowerModuleClockControl_out;
+
+typedef struct NvRmPowerModuleClockControl_params_t
+{
+    NvRmPowerModuleClockControl_in in;
+    NvRmPowerModuleClockControl_inout inout;
+    NvRmPowerModuleClockControl_out out;
+} NvRmPowerModuleClockControl_params;
+
+typedef struct NvRmPowerModuleClockConfig_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDeviceHandle;
+    NvRmModuleID ModuleId;
+    NvU32 ClientId;
+    NvRmFreqKHz MinFreq;
+    NvRmFreqKHz MaxFreq;
+    NvRmFreqKHz  * PrefFreqList;
+    NvU32 PrefFreqListCount;
+    NvU32 flags;
+} NV_ALIGN(4) NvRmPowerModuleClockConfig_in;
+
+typedef struct NvRmPowerModuleClockConfig_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPowerModuleClockConfig_inout;
+
+typedef struct NvRmPowerModuleClockConfig_out_t
+{
+    NvError ret_;
+    NvRmFreqKHz CurrentFreq;
+} NV_ALIGN(4) NvRmPowerModuleClockConfig_out;
+
+typedef struct NvRmPowerModuleClockConfig_params_t
+{
+    NvRmPowerModuleClockConfig_in in;
+    NvRmPowerModuleClockConfig_inout inout;
+    NvRmPowerModuleClockConfig_out out;
+} NvRmPowerModuleClockConfig_params;
+
+static NvError NvRmPowerVoltageControl_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerVoltageControl_in *p_in;
+    NvRmPowerVoltageControl_out *p_out;
+    NvRmMilliVolts *PrefVoltageList = NULL;
+
+    p_in = (NvRmPowerVoltageControl_in *)InBuffer;
+    p_out = (NvRmPowerVoltageControl_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerVoltageControl_params, out) - OFFSET(NvRmPowerVoltageControl_params, inout));
+
+    if( p_in->PrefVoltageListCount && p_in->PrefVoltageList )
+    {
+        PrefVoltageList = (NvRmMilliVolts  *)NvOsAlloc( p_in->PrefVoltageListCount * sizeof( NvRmMilliVolts  ) );
+        if( !PrefVoltageList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->PrefVoltageList )
+        {
+            err_ = NvOsCopyIn( PrefVoltageList, p_in->PrefVoltageList, p_in->PrefVoltageListCount * sizeof( NvRmMilliVolts  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmPowerVoltageControl( p_in->hRmDeviceHandle, p_in->ModuleId, p_in->ClientId, p_in->MinVolts, p_in->MaxVolts, PrefVoltageList, p_in->PrefVoltageListCount, &p_out->CurrentVolts );
+
+clean:
+    NvOsFree( PrefVoltageList );
+    return err_;
+}
+
+static NvError NvRmPowerModuleClockControl_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerModuleClockControl_in *p_in;
+    NvRmPowerModuleClockControl_out *p_out;
+
+    p_in = (NvRmPowerModuleClockControl_in *)InBuffer;
+    p_out = (NvRmPowerModuleClockControl_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerModuleClockControl_params, out) - OFFSET(NvRmPowerModuleClockControl_params, inout));
+
+
+    p_out->ret_ = NvRmPowerModuleClockControl( p_in->hRmDeviceHandle, p_in->ModuleId, p_in->ClientId, p_in->Enable );
+
+    return err_;
+}
+
+static NvError NvRmPowerModuleClockConfig_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPowerModuleClockConfig_in *p_in;
+    NvRmPowerModuleClockConfig_out *p_out;
+    NvRmFreqKHz *PrefFreqList = NULL;
+
+    p_in = (NvRmPowerModuleClockConfig_in *)InBuffer;
+    p_out = (NvRmPowerModuleClockConfig_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPowerModuleClockConfig_params, out) - OFFSET(NvRmPowerModuleClockConfig_params, inout));
+
+    if( p_in->PrefFreqListCount && p_in->PrefFreqList )
+    {
+        PrefFreqList = (NvRmFreqKHz  *)NvOsAlloc( p_in->PrefFreqListCount * sizeof( NvRmFreqKHz  ) );
+        if( !PrefFreqList )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->PrefFreqList )
+        {
+            err_ = NvOsCopyIn( PrefFreqList, p_in->PrefFreqList, p_in->PrefFreqListCount * sizeof( NvRmFreqKHz  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmPowerModuleClockConfig( p_in->hRmDeviceHandle, p_in->ModuleId, p_in->ClientId, p_in->MinFreq, p_in->MaxFreq, PrefFreqList, p_in->PrefFreqListCount, &p_out->CurrentFreq, p_in->flags );
+
+clean:
+    NvOsFree( PrefFreqList );
+    return err_;
+}
+
+NvError nvrm_power_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 9:
+        err_ = NvRmPowerVoltageControl_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 8:
+        err_ = NvRmPowerModuleClockControl_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 7:
+        err_ = NvRmPowerModuleClockConfig_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvSuccess;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pwm_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pwm_dispatch.c
new file mode 100644
index 000000000000..44d1b5e4a3b3
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_pwm_dispatch.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_pwm.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmPwmConfig_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmPwmHandle hPwm;
+    NvRmPwmOutputId OutputId;
+    NvRmPwmMode Mode;
+    NvU32 DutyCycle;
+    NvU32 RequestedFreqHzOrPeriod;
+} NV_ALIGN(4) NvRmPwmConfig_in;
+
+typedef struct NvRmPwmConfig_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPwmConfig_inout;
+
+typedef struct NvRmPwmConfig_out_t
+{
+    NvError ret_;
+    NvU32 pCurrentFreqHzOrPeriod;
+} NV_ALIGN(4) NvRmPwmConfig_out;
+
+typedef struct NvRmPwmConfig_params_t
+{
+    NvRmPwmConfig_in in;
+    NvRmPwmConfig_inout inout;
+    NvRmPwmConfig_out out;
+} NvRmPwmConfig_params;
+
+typedef struct NvRmPwmClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmPwmHandle hPwm;
+} NV_ALIGN(4) NvRmPwmClose_in;
+
+typedef struct NvRmPwmClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPwmClose_inout;
+
+typedef struct NvRmPwmClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPwmClose_out;
+
+typedef struct NvRmPwmClose_params_t
+{
+    NvRmPwmClose_in in;
+    NvRmPwmClose_inout inout;
+    NvRmPwmClose_out out;
+} NvRmPwmClose_params;
+
+typedef struct NvRmPwmOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmPwmOpen_in;
+
+typedef struct NvRmPwmOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPwmOpen_inout;
+
+typedef struct NvRmPwmOpen_out_t
+{
+    NvError ret_;
+    NvRmPwmHandle phPwm;
+} NV_ALIGN(4) NvRmPwmOpen_out;
+
+typedef struct NvRmPwmOpen_params_t
+{
+    NvRmPwmOpen_in in;
+    NvRmPwmOpen_inout inout;
+    NvRmPwmOpen_out out;
+} NvRmPwmOpen_params;
+
+static NvError NvRmPwmConfig_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPwmConfig_in *p_in;
+    NvRmPwmConfig_out *p_out;
+
+    p_in = (NvRmPwmConfig_in *)InBuffer;
+    p_out = (NvRmPwmConfig_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPwmConfig_params, out) - OFFSET(NvRmPwmConfig_params, inout));
+
+
+    p_out->ret_ = NvRmPwmConfig( p_in->hPwm, p_in->OutputId, p_in->Mode, p_in->DutyCycle, p_in->RequestedFreqHzOrPeriod, &p_out->pCurrentFreqHzOrPeriod );
+
+    return err_;
+}
+
+static NvError NvRmPwmClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPwmClose_in *p_in;
+
+    p_in = (NvRmPwmClose_in *)InBuffer;
+
+
+    NvRmPwmClose( p_in->hPwm );
+
+    return err_;
+}
+
+static NvError NvRmPwmOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPwmOpen_in *p_in;
+    NvRmPwmOpen_out *p_out;
+
+    p_in = (NvRmPwmOpen_in *)InBuffer;
+    p_out = (NvRmPwmOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPwmOpen_params, out) - OFFSET(NvRmPwmOpen_params, inout));
+
+
+    p_out->ret_ = NvRmPwmOpen( p_in->hDevice, &p_out->phPwm );
+
+    return err_;
+}
+
+NvError nvrm_pwm_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_pwm_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 2:
+        err_ = NvRmPwmConfig_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmPwmClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmPwmOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_spi_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_spi_dispatch.c
new file mode 100644
index 000000000000..8581343518f5
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_spi_dispatch.c
@@ -0,0 +1,407 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#define NV_IDL_IS_DISPATCH
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_spi.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmSpiSetSignalMode_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmSpiHandle hRmSpi;
+    NvU32 ChipSelectId;
+    NvU32 SpiSignalMode;
+} NV_ALIGN(4) NvRmSpiSetSignalMode_in;
+
+typedef struct NvRmSpiSetSignalMode_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiSetSignalMode_inout;
+
+typedef struct NvRmSpiSetSignalMode_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiSetSignalMode_out;
+
+typedef struct NvRmSpiSetSignalMode_params_t
+{
+    NvRmSpiSetSignalMode_in in;
+    NvRmSpiSetSignalMode_inout inout;
+    NvRmSpiSetSignalMode_out out;
+} NvRmSpiSetSignalMode_params;
+
+typedef struct NvRmSpiGetTransactionData_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmSpiHandle hRmSpi;
+    NvU8  * pReadBuffer;
+    NvU32 BytesRequested;
+    NvU32 WaitTimeout;
+} NV_ALIGN(4) NvRmSpiGetTransactionData_in;
+
+typedef struct NvRmSpiGetTransactionData_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiGetTransactionData_inout;
+
+typedef struct NvRmSpiGetTransactionData_out_t
+{
+    NvError ret_;
+    NvU32 pBytesTransfererd;
+} NV_ALIGN(4) NvRmSpiGetTransactionData_out;
+
+typedef struct NvRmSpiGetTransactionData_params_t
+{
+    NvRmSpiGetTransactionData_in in;
+    NvRmSpiGetTransactionData_inout inout;
+    NvRmSpiGetTransactionData_out out;
+} NvRmSpiGetTransactionData_params;
+
+typedef struct NvRmSpiStartTransaction_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmSpiHandle hRmSpi;
+    NvU32 ChipSelectId;
+    NvU32 ClockSpeedInKHz;
+    NvBool IsReadTransfer;
+    NvU8  * pWriteBuffer;
+    NvU32 BytesRequested;
+    NvU32 PacketSizeInBits;
+} NV_ALIGN(4) NvRmSpiStartTransaction_in;
+
+typedef struct NvRmSpiStartTransaction_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiStartTransaction_inout;
+
+typedef struct NvRmSpiStartTransaction_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmSpiStartTransaction_out;
+
+typedef struct NvRmSpiStartTransaction_params_t
+{
+    NvRmSpiStartTransaction_in in;
+    NvRmSpiStartTransaction_inout inout;
+    NvRmSpiStartTransaction_out out;
+} NvRmSpiStartTransaction_params;
+
+typedef struct NvRmSpiTransaction_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmSpiHandle hRmSpi;
+    NvU32 SpiPinMap;
+    NvU32 ChipSelectId;
+    NvU32 ClockSpeedInKHz;
+    NvU8  * pReadBuffer;
+    NvU8  * pWriteBuffer;
+    NvU32 BytesRequested;
+    NvU32 PacketSizeInBits;
+} NV_ALIGN(4) NvRmSpiTransaction_in;
+
+typedef struct NvRmSpiTransaction_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiTransaction_inout;
+
+typedef struct NvRmSpiTransaction_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiTransaction_out;
+
+typedef struct NvRmSpiTransaction_params_t
+{
+    NvRmSpiTransaction_in in;
+    NvRmSpiTransaction_inout inout;
+    NvRmSpiTransaction_out out;
+} NvRmSpiTransaction_params;
+
+typedef struct NvRmSpiClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmSpiHandle hRmSpi;
+} NV_ALIGN(4) NvRmSpiClose_in;
+
+typedef struct NvRmSpiClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiClose_inout;
+
+typedef struct NvRmSpiClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiClose_out;
+
+typedef struct NvRmSpiClose_params_t
+{
+    NvRmSpiClose_in in;
+    NvRmSpiClose_inout inout;
+    NvRmSpiClose_out out;
+} NvRmSpiClose_params;
+
+typedef struct NvRmSpiOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    NvU32 IoModule;
+    NvU32 InstanceId;
+    NvBool IsMasterMode;
+} NV_ALIGN(4) NvRmSpiOpen_in;
+
+typedef struct NvRmSpiOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmSpiOpen_inout;
+
+typedef struct NvRmSpiOpen_out_t
+{
+    NvError ret_;
+    NvRmSpiHandle phRmSpi;
+} NV_ALIGN(4) NvRmSpiOpen_out;
+
+typedef struct NvRmSpiOpen_params_t
+{
+    NvRmSpiOpen_in in;
+    NvRmSpiOpen_inout inout;
+    NvRmSpiOpen_out out;
+} NvRmSpiOpen_params;
+
+static NvError NvRmSpiSetSignalMode_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiSetSignalMode_in *p_in;
+
+    p_in = (NvRmSpiSetSignalMode_in *)InBuffer;
+
+
+    NvRmSpiSetSignalMode( p_in->hRmSpi, p_in->ChipSelectId, p_in->SpiSignalMode );
+
+    return err_;
+}
+
+static NvError NvRmSpiGetTransactionData_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiGetTransactionData_in *p_in;
+    NvRmSpiGetTransactionData_out *p_out;
+    NvU8  *pReadBuffer = NULL;
+
+    p_in = (NvRmSpiGetTransactionData_in *)InBuffer;
+    p_out = (NvRmSpiGetTransactionData_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSpiGetTransactionData_params, out) - OFFSET(NvRmSpiGetTransactionData_params, inout));
+
+    if( p_in->BytesRequested && p_in->pReadBuffer )
+    {
+        pReadBuffer = (NvU8  *)NvOsAlloc( p_in->BytesRequested * sizeof( NvU8  ) );
+        if( !pReadBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmSpiGetTransactionData( p_in->hRmSpi, pReadBuffer, p_in->BytesRequested, &p_out->pBytesTransfererd, p_in->WaitTimeout );
+
+    if(p_in->pReadBuffer && pReadBuffer)
+    {
+        err_ = NvOsCopyOut( p_in->pReadBuffer, pReadBuffer, p_in->BytesRequested * sizeof( NvU8  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pReadBuffer );
+    return err_;
+}
+
+static NvError NvRmSpiStartTransaction_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiStartTransaction_in *p_in;
+    NvRmSpiStartTransaction_out *p_out;
+    NvU8  *pWriteBuffer = NULL;
+
+    p_in = (NvRmSpiStartTransaction_in *)InBuffer;
+    p_out = (NvRmSpiStartTransaction_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSpiStartTransaction_params, out) - OFFSET(NvRmSpiStartTransaction_params, inout));
+
+    if( p_in->BytesRequested && p_in->pWriteBuffer )
+    {
+        pWriteBuffer = (NvU8  *)NvOsAlloc( p_in->BytesRequested * sizeof( NvU8  ) );
+        if( !pWriteBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pWriteBuffer )
+        {
+            err_ = NvOsCopyIn( pWriteBuffer, p_in->pWriteBuffer, p_in->BytesRequested * sizeof( NvU8  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmSpiStartTransaction( p_in->hRmSpi, p_in->ChipSelectId, p_in->ClockSpeedInKHz, p_in->IsReadTransfer, pWriteBuffer, p_in->BytesRequested, p_in->PacketSizeInBits );
+
+clean:
+    NvOsFree( pWriteBuffer );
+    return err_;
+}
+
+static NvError NvRmSpiTransaction_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiTransaction_in *p_in;
+    NvU8  *pReadBuffer = NULL;
+    NvU8  *pWriteBuffer = NULL;
+
+    p_in = (NvRmSpiTransaction_in *)InBuffer;
+
+    if( p_in->BytesRequested && p_in->pReadBuffer )
+    {
+        pReadBuffer = (NvU8  *)NvOsAlloc( p_in->BytesRequested * sizeof( NvU8  ) );
+        if( !pReadBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+    if( p_in->BytesRequested && p_in->pWriteBuffer )
+    {
+        pWriteBuffer = (NvU8  *)NvOsAlloc( p_in->BytesRequested * sizeof( NvU8  ) );
+        if( !pWriteBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pWriteBuffer )
+        {
+            err_ = NvOsCopyIn( pWriteBuffer, p_in->pWriteBuffer, p_in->BytesRequested * sizeof( NvU8  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRmSpiTransaction( p_in->hRmSpi, p_in->SpiPinMap, p_in->ChipSelectId, p_in->ClockSpeedInKHz, pReadBuffer, pWriteBuffer, p_in->BytesRequested, p_in->PacketSizeInBits );
+
+    if(p_in->pReadBuffer && pReadBuffer)
+    {
+        err_ = NvOsCopyOut( p_in->pReadBuffer, pReadBuffer, p_in->BytesRequested * sizeof( NvU8  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    NvOsFree( pReadBuffer );
+    NvOsFree( pWriteBuffer );
+    return err_;
+}
+
+static NvError NvRmSpiClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiClose_in *p_in;
+
+    p_in = (NvRmSpiClose_in *)InBuffer;
+
+
+    NvRmSpiClose( p_in->hRmSpi );
+
+    return err_;
+}
+
+static NvError NvRmSpiOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmSpiOpen_in *p_in;
+    NvRmSpiOpen_out *p_out;
+
+    p_in = (NvRmSpiOpen_in *)InBuffer;
+    p_out = (NvRmSpiOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmSpiOpen_params, out) - OFFSET(NvRmSpiOpen_params, inout));
+
+
+    p_out->ret_ = NvRmSpiOpen( p_in->hRmDevice, p_in->IoModule, p_in->InstanceId, p_in->IsMasterMode, &p_out->phRmSpi );
+
+    return err_;
+}
+
+NvError nvrm_spi_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_spi_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 5:
+        err_ = NvRmSpiSetSignalMode_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmSpiGetTransactionData_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmSpiStartTransaction_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmSpiTransaction_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmSpiClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmSpiOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_transport_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_transport_dispatch.c
new file mode 100644
index 000000000000..0ab58edd8f17
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_transport_dispatch.c
@@ -0,0 +1,678 @@
+
+#define NV_IDL_IS_DISPATCH
+
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_transport.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+#define MAX_MESSAGE_LENGTH 256
+#define MAX_PORT_NAME_LENGTH 20
+
+typedef struct NvRmTransportRecvMsg_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    void* pMessageBuffer;
+    NvU32 MaxSize;
+} NV_ALIGN(4) NvRmTransportRecvMsg_in;
+
+typedef struct NvRmTransportRecvMsg_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportRecvMsg_inout;
+
+typedef struct NvRmTransportRecvMsg_out_t
+{
+    NvError ret_;
+    NvU32 pMessageSize;
+} NV_ALIGN(4) NvRmTransportRecvMsg_out;
+
+typedef struct NvRmTransportRecvMsg_params_t
+{
+    NvRmTransportRecvMsg_in in;
+    NvRmTransportRecvMsg_inout inout;
+    NvRmTransportRecvMsg_out out;
+} NvRmTransportRecvMsg_params;
+
+typedef struct NvRmTransportSendMsgInLP0_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hPort;
+    void* message;
+    NvU32 MessageSize;
+} NV_ALIGN(4) NvRmTransportSendMsgInLP0_in;
+
+typedef struct NvRmTransportSendMsgInLP0_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportSendMsgInLP0_inout;
+
+typedef struct NvRmTransportSendMsgInLP0_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportSendMsgInLP0_out;
+
+typedef struct NvRmTransportSendMsgInLP0_params_t
+{
+    NvRmTransportSendMsgInLP0_in in;
+    NvRmTransportSendMsgInLP0_inout inout;
+    NvRmTransportSendMsgInLP0_out out;
+} NvRmTransportSendMsgInLP0_params;
+
+typedef struct NvRmTransportSendMsg_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    void* pMessageBuffer;
+    NvU32 MessageSize;
+    NvU32 TimeoutMS;
+} NV_ALIGN(4) NvRmTransportSendMsg_in;
+
+typedef struct NvRmTransportSendMsg_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportSendMsg_inout;
+
+typedef struct NvRmTransportSendMsg_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportSendMsg_out;
+
+typedef struct NvRmTransportSendMsg_params_t
+{
+    NvRmTransportSendMsg_in in;
+    NvRmTransportSendMsg_inout inout;
+    NvRmTransportSendMsg_out out;
+} NvRmTransportSendMsg_params;
+
+typedef struct NvRmTransportSetQueueDepth_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    NvU32 MaxQueueDepth;
+    NvU32 MaxMessageSize;
+} NV_ALIGN(4) NvRmTransportSetQueueDepth_in;
+
+typedef struct NvRmTransportSetQueueDepth_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportSetQueueDepth_inout;
+
+typedef struct NvRmTransportSetQueueDepth_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportSetQueueDepth_out;
+
+typedef struct NvRmTransportSetQueueDepth_params_t
+{
+    NvRmTransportSetQueueDepth_in in;
+    NvRmTransportSetQueueDepth_inout inout;
+    NvRmTransportSetQueueDepth_out out;
+} NvRmTransportSetQueueDepth_params;
+
+typedef struct NvRmTransportConnect_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    NvU32 TimeoutMS;
+} NV_ALIGN(4) NvRmTransportConnect_in;
+
+typedef struct NvRmTransportConnect_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportConnect_inout;
+
+typedef struct NvRmTransportConnect_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportConnect_out;
+
+typedef struct NvRmTransportConnect_params_t
+{
+    NvRmTransportConnect_in in;
+    NvRmTransportConnect_inout inout;
+    NvRmTransportConnect_out out;
+} NvRmTransportConnect_params;
+
+typedef struct NvRmTransportWaitForConnect_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    NvU32 TimeoutMS;
+} NV_ALIGN(4) NvRmTransportWaitForConnect_in;
+
+typedef struct NvRmTransportWaitForConnect_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportWaitForConnect_inout;
+
+typedef struct NvRmTransportWaitForConnect_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportWaitForConnect_out;
+
+typedef struct NvRmTransportWaitForConnect_params_t
+{
+    NvRmTransportWaitForConnect_in in;
+    NvRmTransportWaitForConnect_inout inout;
+    NvRmTransportWaitForConnect_out out;
+} NvRmTransportWaitForConnect_params;
+
+typedef struct NvRmTransportDeInit_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmTransportDeInit_in;
+
+typedef struct NvRmTransportDeInit_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportDeInit_inout;
+
+typedef struct NvRmTransportDeInit_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportDeInit_out;
+
+typedef struct NvRmTransportDeInit_params_t
+{
+    NvRmTransportDeInit_in in;
+    NvRmTransportDeInit_inout inout;
+    NvRmTransportDeInit_out out;
+} NvRmTransportDeInit_params;
+
+typedef struct NvRmTransportInit_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+} NV_ALIGN(4) NvRmTransportInit_in;
+
+typedef struct NvRmTransportInit_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportInit_inout;
+
+typedef struct NvRmTransportInit_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmTransportInit_out;
+
+typedef struct NvRmTransportInit_params_t
+{
+    NvRmTransportInit_in in;
+    NvRmTransportInit_inout inout;
+    NvRmTransportInit_out out;
+} NvRmTransportInit_params;
+
+typedef struct NvRmTransportClose_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+} NV_ALIGN(4) NvRmTransportClose_in;
+
+typedef struct NvRmTransportClose_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportClose_inout;
+
+typedef struct NvRmTransportClose_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportClose_out;
+
+typedef struct NvRmTransportClose_params_t
+{
+    NvRmTransportClose_in in;
+    NvRmTransportClose_inout inout;
+    NvRmTransportClose_out out;
+} NvRmTransportClose_params;
+
+typedef struct NvRmTransportGetPortName_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmTransportHandle hTransport;
+    NvU8  * PortName;
+    NvU32 PortNameSize;
+} NV_ALIGN(4) NvRmTransportGetPortName_in;
+
+typedef struct NvRmTransportGetPortName_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportGetPortName_inout;
+
+typedef struct NvRmTransportGetPortName_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportGetPortName_out;
+
+typedef struct NvRmTransportGetPortName_params_t
+{
+    NvRmTransportGetPortName_in in;
+    NvRmTransportGetPortName_inout inout;
+    NvRmTransportGetPortName_out out;
+} NvRmTransportGetPortName_params;
+
+typedef struct NvRmTransportOpen_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hRmDevice;
+    char * pPortName_data;
+    NvU32 pPortName_len;
+    NvOsSemaphoreHandle RecvMessageSemaphore;
+} NV_ALIGN(4) NvRmTransportOpen_in;
+
+typedef struct NvRmTransportOpen_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmTransportOpen_inout;
+
+typedef struct NvRmTransportOpen_out_t
+{
+    NvError ret_;
+    NvRmTransportHandle phTransport;
+} NV_ALIGN(4) NvRmTransportOpen_out;
+
+typedef struct NvRmTransportOpen_params_t
+{
+    NvRmTransportOpen_in in;
+    NvRmTransportOpen_inout inout;
+    NvRmTransportOpen_out out;
+} NvRmTransportOpen_params;
+
+static NvError NvRmTransportRecvMsg_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportRecvMsg_in *p_in;
+    NvRmTransportRecvMsg_out *p_out;
+    void*  pMessageBuffer = NULL;
+    NvU32 MsgBuff[MAX_MESSAGE_LENGTH/sizeof(NvU32)];
+
+    p_in = (NvRmTransportRecvMsg_in *)InBuffer;
+    p_out = (NvRmTransportRecvMsg_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportRecvMsg_params, out) - OFFSET(NvRmTransportRecvMsg_params, inout));
+
+    if( p_in->MaxSize && p_in->pMessageBuffer )
+    {
+        pMessageBuffer = (void*  )MsgBuff;
+        if( p_in->MaxSize > MAX_MESSAGE_LENGTH )
+            pMessageBuffer = (void* )NvOsAlloc( p_in->MaxSize );
+        if( !pMessageBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmTransportRecvMsg( p_in->hTransport, pMessageBuffer, p_in->MaxSize, &p_out->pMessageSize );
+
+    if(p_in->pMessageBuffer && pMessageBuffer)
+    {
+        err_ = NvOsCopyOut( p_in->pMessageBuffer, pMessageBuffer, p_in->MaxSize );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    if (pMessageBuffer != MsgBuff)
+        NvOsFree( pMessageBuffer );
+    return err_;
+}
+
+static NvError NvRmTransportSendMsgInLP0_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportSendMsgInLP0_in *p_in;
+    NvRmTransportSendMsgInLP0_out *p_out;
+    void*  message = NULL;
+    NvU32 MsgBuff[MAX_MESSAGE_LENGTH/sizeof(NvU32)];
+
+    p_in = (NvRmTransportSendMsgInLP0_in *)InBuffer;
+    p_out = (NvRmTransportSendMsgInLP0_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportSendMsgInLP0_params, out) - OFFSET(NvRmTransportSendMsgInLP0_params, inout));
+
+    if( p_in->MessageSize && p_in->message )
+    {
+        message = (void*  )MsgBuff;
+        if( p_in->MessageSize > MAX_MESSAGE_LENGTH )
+            message = (void*  )NvOsAlloc( p_in->MessageSize );
+        if( !message )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->message )
+        {
+            err_ = NvOsCopyIn( message, p_in->message, p_in->MessageSize );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmTransportSendMsgInLP0( p_in->hPort, message, p_in->MessageSize );
+
+clean:
+    if( message != MsgBuff )
+        NvOsFree( message );
+    return err_;
+}
+
+static NvError NvRmTransportSendMsg_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportSendMsg_in *p_in;
+    NvRmTransportSendMsg_out *p_out;
+    void*  pMessageBuffer = NULL;
+    NvU32 MsgBuff[MAX_MESSAGE_LENGTH/sizeof(NvU32)];
+
+    p_in = (NvRmTransportSendMsg_in *)InBuffer;
+    p_out = (NvRmTransportSendMsg_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportSendMsg_params, out) - OFFSET(NvRmTransportSendMsg_params, inout));
+
+    if( p_in->MessageSize && p_in->pMessageBuffer )
+    {
+        pMessageBuffer = (void*  )&MsgBuff[0];
+        if( p_in->MessageSize > MAX_MESSAGE_LENGTH )
+            pMessageBuffer = (void*  )NvOsAlloc( p_in->MessageSize );
+        if( !pMessageBuffer )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->pMessageBuffer )
+        {
+            err_ = NvOsCopyIn( pMessageBuffer, p_in->pMessageBuffer, p_in->MessageSize );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    p_out->ret_ = NvRmTransportSendMsg( p_in->hTransport, pMessageBuffer, p_in->MessageSize, p_in->TimeoutMS );
+
+clean:
+    if( pMessageBuffer != MsgBuff )
+        NvOsFree( pMessageBuffer );
+    return err_;
+}
+
+static NvError NvRmTransportSetQueueDepth_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportSetQueueDepth_in *p_in;
+    NvRmTransportSetQueueDepth_out *p_out;
+
+    p_in = (NvRmTransportSetQueueDepth_in *)InBuffer;
+    p_out = (NvRmTransportSetQueueDepth_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportSetQueueDepth_params, out) - OFFSET(NvRmTransportSetQueueDepth_params, inout));
+
+
+    p_out->ret_ = NvRmTransportSetQueueDepth( p_in->hTransport, p_in->MaxQueueDepth, p_in->MaxMessageSize );
+
+    return err_;
+}
+
+static NvError NvRmTransportConnect_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportConnect_in *p_in;
+    NvRmTransportConnect_out *p_out;
+
+    p_in = (NvRmTransportConnect_in *)InBuffer;
+    p_out = (NvRmTransportConnect_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportConnect_params, out) - OFFSET(NvRmTransportConnect_params, inout));
+
+
+    p_out->ret_ = NvRmTransportConnect( p_in->hTransport, p_in->TimeoutMS );
+
+    return err_;
+}
+
+static NvError NvRmTransportWaitForConnect_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportWaitForConnect_in *p_in;
+    NvRmTransportWaitForConnect_out *p_out;
+
+    p_in = (NvRmTransportWaitForConnect_in *)InBuffer;
+    p_out = (NvRmTransportWaitForConnect_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportWaitForConnect_params, out) - OFFSET(NvRmTransportWaitForConnect_params, inout));
+
+
+    p_out->ret_ = NvRmTransportWaitForConnect( p_in->hTransport, p_in->TimeoutMS );
+
+    return err_;
+}
+
+static NvError NvRmTransportDeInit_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportDeInit_in *p_in;
+
+    p_in = (NvRmTransportDeInit_in *)InBuffer;
+
+
+    NvRmTransportDeInit( p_in->hRmDevice );
+
+    return err_;
+}
+
+static NvError NvRmTransportInit_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportInit_in *p_in;
+    NvRmTransportInit_out *p_out;
+
+    p_in = (NvRmTransportInit_in *)InBuffer;
+    p_out = (NvRmTransportInit_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportInit_params, out) - OFFSET(NvRmTransportInit_params, inout));
+
+
+    p_out->ret_ = NvRmTransportInit( p_in->hRmDevice );
+
+    return err_;
+}
+
+static NvError NvRmTransportClose_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportClose_in *p_in;
+
+    p_in = (NvRmTransportClose_in *)InBuffer;
+
+
+    NvRmTransportClose( p_in->hTransport );
+
+    return err_;
+}
+
+static NvError NvRmTransportGetPortName_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportGetPortName_in *p_in;
+    NvU8  *PortName = NULL;
+    NvU32 PortNameBuff[MAX_PORT_NAME_LENGTH/sizeof(NvU32)];
+
+    p_in = (NvRmTransportGetPortName_in *)InBuffer;
+
+    if( p_in->PortNameSize && p_in->PortName )
+    {
+        PortName = (NvU8  *)PortNameBuff;
+        if( (p_in->PortNameSize * sizeof(NvU8)) > MAX_PORT_NAME_LENGTH )
+            PortName = (NvU8  *)NvOsAlloc( p_in->PortNameSize * sizeof( NvU8  ) );
+        if( !PortName )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        if( p_in->PortName )
+        {
+            err_ = NvOsCopyIn( PortName, p_in->PortName, p_in->PortNameSize * sizeof( NvU8  ) );
+            if( err_ != NvSuccess )
+            {
+                err_ = NvError_BadParameter;
+                goto clean;
+            }
+        }
+    }
+
+    NvRmTransportGetPortName( p_in->hTransport, PortName, p_in->PortNameSize );
+
+    if(p_in->PortName && PortName)
+    {
+        err_ = NvOsCopyOut( p_in->PortName, PortName, p_in->PortNameSize * sizeof( NvU8  ) );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+        }
+    }
+clean:
+    if ( PortName != PortNameBuff )
+        NvOsFree( PortName );
+    return err_;
+}
+
+static NvError NvRmTransportOpen_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmTransportOpen_in *p_in;
+    NvRmTransportOpen_out *p_out;
+    char *pPortName = NULL;
+    NvOsSemaphoreHandle RecvMessageSemaphore = NULL;
+    NvU32 PortNameBuff[MAX_PORT_NAME_LENGTH/sizeof(NvU32)];
+
+    p_in = (NvRmTransportOpen_in *)InBuffer;
+    p_out = (NvRmTransportOpen_out *)((NvU8 *)OutBuffer + OFFSET(NvRmTransportOpen_params, out) - OFFSET(NvRmTransportOpen_params, inout));
+
+    if( p_in->pPortName_len )
+    {
+        pPortName = (char *)PortNameBuff;
+        if( p_in->pPortName_len > MAX_PORT_NAME_LENGTH )
+            pPortName = NvOsAlloc( p_in->pPortName_len );
+        if( !pPortName )
+        {
+            err_ = NvError_InsufficientMemory;
+            goto clean;
+        }
+        err_ = NvOsCopyIn( pPortName, p_in->pPortName_data, p_in->pPortName_len );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+            goto clean;
+        }
+        if( pPortName[p_in->pPortName_len - 1] != 0 )
+        {
+            err_ = NvError_BadParameter;
+            goto clean;
+        }
+    }
+    if( p_in->RecvMessageSemaphore )
+    {
+        err_ = NvOsSemaphoreUnmarshal( p_in->RecvMessageSemaphore, &RecvMessageSemaphore );
+        if( err_ != NvSuccess )
+        {
+            err_ = NvError_BadParameter;
+            goto clean;
+        }
+    }
+
+    p_out->ret_ = NvRmTransportOpen( p_in->hRmDevice, pPortName, RecvMessageSemaphore, &p_out->phTransport );
+
+clean:
+    if( pPortName != PortNameBuff )
+        NvOsFree( pPortName );
+    NvOsSemaphoreDestroy( RecvMessageSemaphore );
+    return err_;
+}
+
+NvError nvrm_transport_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_transport_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 10:
+        err_ = NvRmTransportRecvMsg_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 9:
+        err_ = NvRmTransportSendMsgInLP0_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 8:
+        err_ = NvRmTransportSendMsg_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 7:
+        err_ = NvRmTransportSetQueueDepth_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 6:
+        err_ = NvRmTransportConnect_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmTransportWaitForConnect_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmTransportDeInit_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmTransportInit_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmTransportClose_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmTransportGetPortName_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmTransportOpen_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_xpc_dispatch.c b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_xpc_dispatch.c
new file mode 100644
index 000000000000..16b98ede32e0
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm/dispatch/nvrm_xpc_dispatch.c
@@ -0,0 +1,348 @@
+
+#define NV_IDL_IS_DISPATCH
+
+/*
+ * Copyright (c) 2010 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvcommon.h"
+#include "nvos.h"
+#include "nvassert.h"
+#include "nvreftrack.h"
+#include "nvidlcmd.h"
+#include "nvrm_xpc.h"
+
+#define OFFSET( s, e ) (NvU32)(void *)(&(((s*)0)->e))
+
+
+typedef struct NvRmXpcModuleRelease_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmModuleID modId;
+} NV_ALIGN(4) NvRmXpcModuleRelease_in;
+
+typedef struct NvRmXpcModuleRelease_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmXpcModuleRelease_inout;
+
+typedef struct NvRmXpcModuleRelease_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmXpcModuleRelease_out;
+
+typedef struct NvRmXpcModuleRelease_params_t
+{
+    NvRmXpcModuleRelease_in in;
+    NvRmXpcModuleRelease_inout inout;
+    NvRmXpcModuleRelease_out out;
+} NvRmXpcModuleRelease_params;
+
+typedef struct NvRmXpcModuleAcquire_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmModuleID modId;
+} NV_ALIGN(4) NvRmXpcModuleAcquire_in;
+
+typedef struct NvRmXpcModuleAcquire_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmXpcModuleAcquire_inout;
+
+typedef struct NvRmXpcModuleAcquire_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmXpcModuleAcquire_out;
+
+typedef struct NvRmXpcModuleAcquire_params_t
+{
+    NvRmXpcModuleAcquire_in in;
+    NvRmXpcModuleAcquire_inout inout;
+    NvRmXpcModuleAcquire_out out;
+} NvRmXpcModuleAcquire_params;
+
+typedef struct NvRmXpcInitArbSemaSystem_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmXpcInitArbSemaSystem_in;
+
+typedef struct NvRmXpcInitArbSemaSystem_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmXpcInitArbSemaSystem_inout;
+
+typedef struct NvRmXpcInitArbSemaSystem_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmXpcInitArbSemaSystem_out;
+
+typedef struct NvRmXpcInitArbSemaSystem_params_t
+{
+    NvRmXpcInitArbSemaSystem_in in;
+    NvRmXpcInitArbSemaSystem_inout inout;
+    NvRmXpcInitArbSemaSystem_out out;
+} NvRmXpcInitArbSemaSystem_params;
+
+typedef struct NvRmPrivXpcGetMessage_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmPrivXpcMessageHandle hXpcMessage;
+} NV_ALIGN(4) NvRmPrivXpcGetMessage_in;
+
+typedef struct NvRmPrivXpcGetMessage_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPrivXpcGetMessage_inout;
+
+typedef struct NvRmPrivXpcGetMessage_out_t
+{
+    NvU32 ret_;
+} NV_ALIGN(4) NvRmPrivXpcGetMessage_out;
+
+typedef struct NvRmPrivXpcGetMessage_params_t
+{
+    NvRmPrivXpcGetMessage_in in;
+    NvRmPrivXpcGetMessage_inout inout;
+    NvRmPrivXpcGetMessage_out out;
+} NvRmPrivXpcGetMessage_params;
+
+typedef struct NvRmPrivXpcSendMessage_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmPrivXpcMessageHandle hXpcMessage;
+    NvU32 data;
+} NV_ALIGN(4) NvRmPrivXpcSendMessage_in;
+
+typedef struct NvRmPrivXpcSendMessage_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPrivXpcSendMessage_inout;
+
+typedef struct NvRmPrivXpcSendMessage_out_t
+{
+    NvError ret_;
+} NV_ALIGN(4) NvRmPrivXpcSendMessage_out;
+
+typedef struct NvRmPrivXpcSendMessage_params_t
+{
+    NvRmPrivXpcSendMessage_in in;
+    NvRmPrivXpcSendMessage_inout inout;
+    NvRmPrivXpcSendMessage_out out;
+} NvRmPrivXpcSendMessage_params;
+
+typedef struct NvRmPrivXpcDestroy_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmPrivXpcMessageHandle hXpcMessage;
+} NV_ALIGN(4) NvRmPrivXpcDestroy_in;
+
+typedef struct NvRmPrivXpcDestroy_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPrivXpcDestroy_inout;
+
+typedef struct NvRmPrivXpcDestroy_out_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPrivXpcDestroy_out;
+
+typedef struct NvRmPrivXpcDestroy_params_t
+{
+    NvRmPrivXpcDestroy_in in;
+    NvRmPrivXpcDestroy_inout inout;
+    NvRmPrivXpcDestroy_out out;
+} NvRmPrivXpcDestroy_params;
+
+typedef struct NvRmPrivXpcCreate_in_t
+{
+    NvU32 package_;
+    NvU32 function_;
+    NvRmDeviceHandle hDevice;
+} NV_ALIGN(4) NvRmPrivXpcCreate_in;
+
+typedef struct NvRmPrivXpcCreate_inout_t
+{
+    NvU32 dummy_;
+} NV_ALIGN(4) NvRmPrivXpcCreate_inout;
+
+typedef struct NvRmPrivXpcCreate_out_t
+{
+    NvError ret_;
+    NvRmPrivXpcMessageHandle phXpcMessage;
+} NV_ALIGN(4) NvRmPrivXpcCreate_out;
+
+typedef struct NvRmPrivXpcCreate_params_t
+{
+    NvRmPrivXpcCreate_in in;
+    NvRmPrivXpcCreate_inout inout;
+    NvRmPrivXpcCreate_out out;
+} NvRmPrivXpcCreate_params;
+
+static NvError NvRmXpcModuleRelease_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmXpcModuleRelease_in *p_in;
+
+    p_in = (NvRmXpcModuleRelease_in *)InBuffer;
+
+
+    NvRmXpcModuleRelease( p_in->modId );
+
+    return err_;
+}
+
+static NvError NvRmXpcModuleAcquire_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmXpcModuleAcquire_in *p_in;
+
+    p_in = (NvRmXpcModuleAcquire_in *)InBuffer;
+
+
+    NvRmXpcModuleAcquire( p_in->modId );
+
+    return err_;
+}
+
+static NvError NvRmXpcInitArbSemaSystem_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmXpcInitArbSemaSystem_in *p_in;
+    NvRmXpcInitArbSemaSystem_out *p_out;
+
+    p_in = (NvRmXpcInitArbSemaSystem_in *)InBuffer;
+    p_out = (NvRmXpcInitArbSemaSystem_out *)((NvU8 *)OutBuffer + OFFSET(NvRmXpcInitArbSemaSystem_params, out) - OFFSET(NvRmXpcInitArbSemaSystem_params, inout));
+
+
+    p_out->ret_ = NvRmXpcInitArbSemaSystem( p_in->hDevice );
+
+    return err_;
+}
+
+static NvError NvRmPrivXpcGetMessage_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPrivXpcGetMessage_in *p_in;
+    NvRmPrivXpcGetMessage_out *p_out;
+
+    p_in = (NvRmPrivXpcGetMessage_in *)InBuffer;
+    p_out = (NvRmPrivXpcGetMessage_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPrivXpcGetMessage_params, out) - OFFSET(NvRmPrivXpcGetMessage_params, inout));
+
+
+    p_out->ret_ = NvRmPrivXpcGetMessage( p_in->hXpcMessage );
+
+    return err_;
+}
+
+static NvError NvRmPrivXpcSendMessage_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPrivXpcSendMessage_in *p_in;
+    NvRmPrivXpcSendMessage_out *p_out;
+
+    p_in = (NvRmPrivXpcSendMessage_in *)InBuffer;
+    p_out = (NvRmPrivXpcSendMessage_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPrivXpcSendMessage_params, out) - OFFSET(NvRmPrivXpcSendMessage_params, inout));
+
+
+    p_out->ret_ = NvRmPrivXpcSendMessage( p_in->hXpcMessage, p_in->data );
+
+    return err_;
+}
+
+static NvError NvRmPrivXpcDestroy_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPrivXpcDestroy_in *p_in;
+
+    p_in = (NvRmPrivXpcDestroy_in *)InBuffer;
+
+
+    NvRmPrivXpcDestroy( p_in->hXpcMessage );
+
+    return err_;
+}
+
+static NvError NvRmPrivXpcCreate_dispatch_( void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+    NvRmPrivXpcCreate_in *p_in;
+    NvRmPrivXpcCreate_out *p_out;
+
+    p_in = (NvRmPrivXpcCreate_in *)InBuffer;
+    p_out = (NvRmPrivXpcCreate_out *)((NvU8 *)OutBuffer + OFFSET(NvRmPrivXpcCreate_params, out) - OFFSET(NvRmPrivXpcCreate_params, inout));
+
+
+    p_out->ret_ = NvRmPrivXpcCreate( p_in->hDevice, &p_out->phXpcMessage );
+
+    return err_;
+}
+
+NvError nvrm_xpc_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx );
+NvError nvrm_xpc_Dispatch( NvU32 function, void *InBuffer, NvU32 InSize, void *OutBuffer, NvU32 OutSize, NvDispatchCtx* Ctx )
+{
+    NvError err_ = NvSuccess;
+
+    switch( function ) {
+    case 6:
+        err_ = NvRmXpcModuleRelease_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 5:
+        err_ = NvRmXpcModuleAcquire_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 4:
+        err_ = NvRmXpcInitArbSemaSystem_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 3:
+        err_ = NvRmPrivXpcGetMessage_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 2:
+        err_ = NvRmPrivXpcSendMessage_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 1:
+        err_ = NvRmPrivXpcDestroy_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    case 0:
+        err_ = NvRmPrivXpcCreate_dispatch_( InBuffer, InSize, OutBuffer, OutSize, Ctx );
+        break;
+    default:
+        err_ = NvError_BadParameter;
+        break;
+    }
+
+    return err_;
+}
diff --git a/arch/arm/mach-tegra/nv/nvrm_user.c b/arch/arm/mach-tegra/nv/nvrm_user.c
new file mode 100644
index 000000000000..7bdfd01e7149
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrm_user.c
@@ -0,0 +1,696 @@
+/*
+ * arch/arm/mach-tegra/nvrm_user.c
+ *
+ * User-land access to NvRm APIs
+ *
+ * Copyright (c) 2008-2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/proc_fs.h>
+#include <linux/miscdevice.h>
+#include <linux/uaccess.h>
+#include <linux/cpumask.h>
+#include <linux/sched.h>
+#include <linux/cpu.h>
+#include <linux/platform_device.h>
+#include <linux/freezer.h>
+#include <linux/suspend.h>
+#include <linux/percpu.h>
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+#endif
+#include <linux/smp.h>
+#include <asm/smp_twd.h>
+#include <asm/cpu.h>
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvos.h"
+#include "nvrm_memmgr.h"
+#include "nvrm_ioctls.h"
+#include "mach/nvrm_linux.h"
+#include "linux/nvos_ioctl.h"
+#include "nvrm_power_private.h"
+#include "nvreftrack.h"
+#include "mach/timex.h"
+
+pid_t s_nvrm_daemon_pid = 0;
+
+NvError NvRm_Dispatch(void *InBuffer,
+                      NvU32 InSize,
+                      void *OutBuffer,
+                      NvU32 OutSize,
+                      NvDispatchCtx* Ctx);
+
+static int nvrm_open(struct inode *inode, struct file *file);
+static int nvrm_close(struct inode *inode, struct file *file);
+static long nvrm_unlocked_ioctl(struct file *file,
+    unsigned int cmd, unsigned long arg);
+static int nvrm_mmap(struct file *file, struct vm_area_struct *vma);
+extern void reset_cpu(unsigned int cpu, unsigned int reset);
+
+static NvOsThreadHandle s_DfsThread = NULL;
+static NvRtHandle s_RtHandle = NULL;
+
+#define DEVICE_NAME "nvrm"
+
+static const struct file_operations nvrm_fops =
+{
+    .owner = THIS_MODULE,
+    .open = nvrm_open,
+    .release = nvrm_close,
+    .unlocked_ioctl = nvrm_unlocked_ioctl,
+    .mmap = nvrm_mmap
+};
+
+static struct miscdevice nvrm_dev =
+{
+    .name = DEVICE_NAME,
+    .fops = &nvrm_fops,
+    .minor = MISC_DYNAMIC_MINOR,
+};
+
+#ifdef GHACK_DFS
+static void NvRmDfsThread(void *args)
+{
+    NvRmDeviceHandle hRm = (NvRmDeviceHandle)args;
+    struct cpumask cpu_mask;
+
+    //Ensure that only cpu0 is in the affinity mask
+    cpumask_clear(&cpu_mask);
+    cpumask_set_cpu(0, &cpu_mask);
+    if (sched_setaffinity(0, &cpu_mask))
+    {
+        panic("Unable to setaffinity of DFS thread!\n");
+    }
+
+    //Confirm that only CPU0 can run this thread
+    if (!cpumask_test_cpu(0, &cpu_mask) || cpumask_weight(&cpu_mask) != 1)
+    {
+        panic("Unable to setaffinity of DFS thread!\n");
+    }
+
+    set_freezable_with_signal();
+
+    if (NvRmDfsGetState(hRm) > NvRmDfsRunState_Disabled)
+    {
+        NvRmFreqKHz CpuKHz, f;
+        CpuKHz = NvRmPrivDfsGetCurrentKHz(NvRmDfsClockId_Cpu);
+        local_timer_rescale(CpuKHz);
+
+        NvRmDfsSetState(hRm, NvRmDfsRunState_ClosedLoop);
+
+        for (;;)
+        {
+            NvRmPmRequest Request = NvRmPrivPmThread();
+            f = NvRmPrivDfsGetCurrentKHz(NvRmDfsClockId_Cpu);
+            if (CpuKHz != f)
+            {
+                CpuKHz = f;
+                local_timer_rescale(CpuKHz);
+                twd_set_prescaler(NULL);
+                smp_call_function(twd_set_prescaler, NULL, NV_TRUE);
+            }
+            if (Request & NvRmPmRequest_ExitFlag)
+            {
+                break;
+            }
+            if (Request & NvRmPmRequest_CpuOnFlag)
+            {
+#ifdef CONFIG_HOTPLUG_CPU
+                printk("DFS requested CPU1 ON\n");
+                preset_lpj = per_cpu(cpu_data, 0).loops_per_jiffy;
+                cpu_up(1);
+                smp_call_function(twd_set_prescaler, NULL, NV_TRUE);
+#endif
+            }
+
+            if (Request & NvRmPmRequest_CpuOffFlag)
+            {
+#ifdef CONFIG_HOTPLUG_CPU
+                printk("DFS requested CPU1 OFF\n");
+                cpu_down(1);
+#endif
+            }
+        }
+    }
+}
+#endif
+
+static void client_detach(NvRtClientHandle client)
+{
+    if (NvRtUnregisterClient(s_RtHandle, client))
+    {
+        NvDispatchCtx dctx;
+
+        dctx.Rt = s_RtHandle;
+        dctx.Client = client;
+        dctx.PackageIdx = 0;
+
+        for (;;)
+        {
+            void* ptr = NvRtFreeObjRef(&dctx,
+                                       NvRtObjType_NvRm_NvRmMemHandle,
+                                       NULL);
+            WARN_ON_ONCE(ptr);
+	    if (!ptr)
+		    break;
+            NVRT_LEAK("NvRm", "NvRmMemHandle", ptr);
+        }
+
+        NvRtUnregisterClient(s_RtHandle, client);
+    }
+}
+
+int nvrm_open(struct inode *inode, struct file *file)
+{
+    NvRtClientHandle Client;
+
+    if (NvRtRegisterClient(s_RtHandle, &Client) != NvSuccess)
+    {
+        return -ENOMEM;
+    }
+
+    file->private_data = (void*)Client;
+
+    return 0;
+}
+
+int nvrm_close(struct inode *inode, struct file *file)
+{
+    client_detach((NvRtClientHandle)file->private_data);
+    return 0;
+}
+
+long nvrm_unlocked_ioctl(struct file *file,
+    unsigned int cmd, unsigned long arg)
+{
+    NvError err;
+    NvOsIoctlParams p;
+    NvU32 size;
+    NvU32 small_buf[8];
+    void *ptr = 0;
+    long e;
+    NvBool bAlloc = NV_FALSE;
+
+    switch( cmd ) {
+    case NvRmIoctls_Generic:
+    {
+        NvDispatchCtx dctx;
+
+        dctx.Rt         = s_RtHandle;
+        dctx.Client     = (NvRtClientHandle)file->private_data;
+        dctx.PackageIdx = 0;
+
+        err = NvOsCopyIn( &p, (void *)arg, sizeof(p) );
+        if( err != NvSuccess )
+        {
+            printk( "NvRmIoctls_Generic: copy in failed\n" );
+            goto fail;
+        }
+
+        //printk( "NvRmIoctls_Generic: %d %d %d\n", p.InBufferSize,
+        //    p.InOutBufferSize, p.OutBufferSize );
+
+        size = p.InBufferSize + p.InOutBufferSize + p.OutBufferSize;
+        if( size <= sizeof(small_buf) )
+        {
+            ptr = small_buf;
+        }
+        else
+        {
+            ptr = NvOsAlloc( size );
+            if( !ptr )
+            {
+                printk( "NvRmIoctls_Generic: alloc failure (%d bytes)\n",
+                    size );
+                goto fail;
+            }
+
+            bAlloc = NV_TRUE;
+        }
+
+        err = NvOsCopyIn( ptr, p.pBuffer, p.InBufferSize +
+            p.InOutBufferSize );
+        if( err != NvSuccess )
+        {
+            printk( "NvRmIoctls_Generic: copy in failure\n" );
+            goto fail;
+        }
+
+        err = NvRm_Dispatch( ptr, p.InBufferSize + p.InOutBufferSize,
+            ((NvU8 *)ptr) + p.InBufferSize, p.InOutBufferSize +
+            p.OutBufferSize, &dctx );
+        if( err != NvSuccess )
+        {
+            printk( "NvRmIoctls_Generic: dispatch failure\n" );
+            goto fail;
+        }
+
+        if( p.InOutBufferSize || p.OutBufferSize )
+        {
+            err = NvOsCopyOut( ((NvU8 *)((NvOsIoctlParams *)arg)->pBuffer)
+                + p.InBufferSize,
+                ((NvU8 *)ptr) + p.InBufferSize,
+                p.InOutBufferSize + p.OutBufferSize );
+            if( err != NvSuccess )
+            {
+                printk( "NvRmIoctls_Generic: copy out failure\n" );
+                goto fail;
+            }
+        }
+
+        break;
+    }
+    case NvRmIoctls_NvRmGraphics:
+        printk( "NvRmIoctls_NvRmGraphics: not supported\n" );
+        goto fail;
+    case NvRmIoctls_NvRmFbControl:
+        printk( "NvRmIoctls_NvRmFbControl: deprecated \n" );
+	break;
+
+    case NvRmIoctls_NvRmMemRead:
+    case NvRmIoctls_NvRmMemWrite:
+    case NvRmIoctls_NvRmMemReadStrided:
+    case NvRmIoctls_NvRmGetCarveoutInfo:
+    case NvRmIoctls_NvRmMemWriteStrided:
+        goto fail;
+
+    case NvRmIoctls_NvRmMemMapIntoCallerPtr:
+        // FIXME: implement?
+        printk( "NvRmIoctls_NvRmMemMapIntoCallerPtr: not supported\n" );
+        goto fail;
+    case NvRmIoctls_NvRmBootDone:
+#ifdef GHACK_DFS
+        if (!s_DfsThread)
+        {
+            if (NvOsInterruptPriorityThreadCreate(NvRmDfsThread,
+                    (void*)s_hRmGlobal, &s_DfsThread)!=NvSuccess)
+            {
+                NvOsDebugPrintf("Failed to create DFS processing thread\n");
+                goto fail;
+            }
+        }
+#endif
+        break;
+    case NvRmIoctls_NvRmGetClientId:
+		err = NvOsCopyIn(&p, (void*)arg, sizeof(p));
+		if (err != NvSuccess)
+		{
+			NvOsDebugPrintf("NvRmIoctls_NvRmGetClientId: copy in failed\n");
+			goto fail;
+		}
+
+		NV_ASSERT(p.InBufferSize == 0);
+		NV_ASSERT(p.OutBufferSize == sizeof(NvRtClientHandle));
+		NV_ASSERT(p.InOutBufferSize == 0);
+
+		if (NvOsCopyOut(p.pBuffer,
+						&file->private_data,
+						sizeof(NvRtClientHandle)) != NvSuccess)
+		{
+			NvOsDebugPrintf("Failed to copy client id\n");
+			goto fail;
+		}
+		break;
+	case NvRmIoctls_NvRmClientAttach:
+	{
+		NvRtClientHandle Client;
+
+		err = NvOsCopyIn(&p, (void*)arg, sizeof(p));
+		if (err != NvSuccess)
+		{
+			NvOsDebugPrintf("NvRmIoctls_NvRmClientAttach: copy in failed\n");
+			goto fail;
+		}
+
+		NV_ASSERT(p.InBufferSize == sizeof(NvRtClientHandle));
+		NV_ASSERT(p.OutBufferSize == 0);
+		NV_ASSERT(p.InOutBufferSize == 0);
+
+		if (NvOsCopyIn((void*)&Client,
+					   p.pBuffer,
+					   sizeof(NvRtClientHandle)) != NvSuccess)
+		{
+			NvOsDebugPrintf("Failed to copy client id\n");
+			goto fail;
+		}
+
+		NV_ASSERT(Client || !"Bad client");
+
+		if (Client == (NvRtClientHandle)file->private_data)
+		{
+			// The daemon is attaching to itself, no need to add refcount
+			break;
+		}
+		if (NvRtAddClientRef(s_RtHandle, Client) != NvSuccess)
+		{
+			NvOsDebugPrintf("Client ref add unsuccessful\n");
+			goto fail;
+		}
+		break;
+	}
+	case NvRmIoctls_NvRmClientDetach:
+	{
+		NvRtClientHandle Client;
+
+		err = NvOsCopyIn(&p, (void*)arg, sizeof(p));
+		if (err != NvSuccess)
+		{
+			NvOsDebugPrintf("NvRmIoctls_NvRmClientAttach: copy in failed\n");
+			goto fail;
+		}
+
+		NV_ASSERT(p.InBufferSize == sizeof(NvRtClientHandle));
+		NV_ASSERT(p.OutBufferSize == 0);
+		NV_ASSERT(p.InOutBufferSize == 0);
+
+		if (NvOsCopyIn((void*)&Client,
+					   p.pBuffer,
+					   sizeof(NvRtClientHandle)) != NvSuccess)
+		{
+			NvOsDebugPrintf("Failed to copy client id\n");
+			goto fail;
+		}
+
+		NV_ASSERT(Client || !"Bad client");
+
+		if (Client == (NvRtClientHandle)file->private_data)
+		{
+			// The daemon is detaching from itself, no need to dec refcount
+			break;
+		}
+
+		client_detach(Client);
+		break;
+	}
+	// FIXME: power ioctls?
+	default:
+		printk( "unknown ioctl code\n" );
+		goto fail;
+	}
+
+	e = 0;
+	goto clean;
+
+fail:
+	e = -EINVAL;
+
+clean:
+	if( bAlloc )
+	{
+		NvOsFree( ptr );
+	}
+
+	return e;
+}
+
+int nvrm_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	return 0;
+}
+
+static int nvrm_probe(struct platform_device *pdev)
+{
+	int e = 0;
+	NvU32 NumTypes = NvRtObjType_NvRm_Num;
+
+	printk("nvrm probe\n");
+
+	NV_ASSERT(s_RtHandle == NULL);
+
+	if (NvRtCreate(1, &NumTypes, &s_RtHandle) != NvSuccess)
+	{
+		e = -ENOMEM;
+	}
+
+	if (e == 0)
+	{
+		e = misc_register( &nvrm_dev );
+	}
+
+	if( e < 0 )
+	{
+		if (s_RtHandle)
+		{
+			NvRtDestroy(s_RtHandle);
+			s_RtHandle = NULL;
+		}
+
+		printk("nvrm probe failed to open\n");
+	}
+	return e;
+}
+
+static int nvrm_remove(struct platform_device *pdev)
+{
+	misc_deregister( &nvrm_dev );
+	NvRtDestroy(s_RtHandle);
+	s_RtHandle = NULL;
+	return 0;
+}
+
+static int nvrm_suspend(struct platform_device *pdev, pm_message_t state)
+{
+#ifdef GHACK
+	if(NvRmKernelPowerSuspend(s_hRmGlobal)) {
+		printk(KERN_INFO "%s : FAILED\n", __func__);
+		return -1;
+	}
+#endif
+	return 0;
+}
+
+static int nvrm_resume(struct platform_device *pdev)
+{
+#ifdef GHACK
+	if(NvRmKernelPowerResume(s_hRmGlobal)) {
+		printk(KERN_INFO "%s : FAILED\n", __func__);
+		return -1;
+	}
+#endif
+	return 0;
+
+}
+
+static struct platform_driver nvrm_driver =
+{
+	.probe	 = nvrm_probe,
+	.remove	 = nvrm_remove,
+	.suspend = nvrm_suspend,
+	.resume	 = nvrm_resume,
+	.driver	 = { .name = "nvrm" }
+};
+
+#if defined(CONFIG_PM)
+//
+// /sys/power/nvrm/notifier
+//
+
+wait_queue_head_t tegra_pm_notifier_wait;
+wait_queue_head_t sys_nvrm_notifier_wait;
+
+int tegra_pm_notifier_continue_ok;
+
+struct kobject *nvrm_kobj;
+
+const char* sys_nvrm_notifier;
+
+static const char *STRING_PM_SUSPEND_PREPARE = "PM_SUSPEND_PREPARE";
+static const char *STRING_PM_POST_SUSPEND    = "PM_POST_SUSPEND";
+static const char *STRING_PM_DISPLAY_OFF     = "PM_DISPLAY_OFF";
+static const char *STRING_PM_DISPLAY_ON      = "PM_DISPLAY_ON";
+static const char *STRING_PM_CONTINUE        = "PM_CONTINUE";
+static const char *STRING_PM_SIGNAL          = "PM_SIGNAL";
+
+// Reading blocks if the value is not available.
+static ssize_t
+nvrm_notifier_show(struct kobject *kobj, struct kobj_attribute *attr,
+		   char *buf)
+{
+	int nchar;
+
+	// Block if the value is not available yet.
+	if (! sys_nvrm_notifier)
+	{
+	    printk(KERN_INFO "%s: blocking\n", __func__);
+	    wait_event_interruptible(sys_nvrm_notifier_wait, sys_nvrm_notifier);
+	}
+
+	// In case of false wakeup, return "".
+	if (! sys_nvrm_notifier)
+	{
+	    printk(KERN_INFO "%s: false wakeup, returning with '\\n'\n", __func__);
+	    nchar = sprintf(buf, "\n");
+	    return nchar;
+	}
+
+	// Return the value, and clear.
+	printk(KERN_INFO "%s: returning with '%s'\n", __func__, sys_nvrm_notifier);
+	nchar = sprintf(buf, "%s\n", sys_nvrm_notifier);
+	sys_nvrm_notifier = NULL;
+	return nchar;
+}
+
+// Writing is no blocking.
+static ssize_t
+nvrm_notifier_store(struct kobject *kobj, struct kobj_attribute *attr,
+			const char *buf, size_t count)
+{
+	if (!strncmp(buf, STRING_PM_CONTINUE, strlen(STRING_PM_CONTINUE))) {
+		// Wake up pm_notifier.
+		tegra_pm_notifier_continue_ok = 1;
+		wake_up(&tegra_pm_notifier_wait);
+	}
+	else if (!strncmp(buf, STRING_PM_SIGNAL, strlen(STRING_PM_SIGNAL))) {
+		s_nvrm_daemon_pid = 0;
+		sscanf(buf, "%*s %d", &s_nvrm_daemon_pid);
+		printk(KERN_INFO "%s: nvrm_daemon=%d\n", __func__, s_nvrm_daemon_pid);
+	}
+	else {
+		printk(KERN_ERR "%s: wrong value '%s'\n", __func__, buf);
+	}
+
+	return count;
+}
+
+static struct kobj_attribute nvrm_notifier_attribute =
+	__ATTR(notifier, 0666, nvrm_notifier_show, nvrm_notifier_store);
+
+//
+// PM notifier
+//
+
+static void notify_daemon(const char* notice)
+{
+	long timeout = HZ * 30;
+
+	// In case daemon's pid is not reported, do not signal or wait.
+	if (!s_nvrm_daemon_pid) {
+		printk(KERN_ERR "%s: don't know nvrm_daemon's PID\n", __func__);
+		return;
+	}
+
+	// Clear before kicking nvrm_daemon.
+	tegra_pm_notifier_continue_ok = 0;
+
+	// Notify nvrm_daemon.
+	sys_nvrm_notifier = notice;
+	wake_up(&sys_nvrm_notifier_wait);
+
+	// Wait for the reply from nvrm_daemon.
+	printk(KERN_INFO "%s: wait for nvrm_daemon\n", __func__);
+	if (wait_event_timeout(tegra_pm_notifier_wait,
+			       tegra_pm_notifier_continue_ok, timeout) == 0) {
+	    printk(KERN_ERR "%s: timed out. nvrm_daemon did not reply\n", __func__);
+	}
+
+	// Go back to the initial state.
+	sys_nvrm_notifier = NULL;
+}
+
+int tegra_pm_notifier(struct notifier_block *nb,
+			  unsigned long event, void *nouse)
+{
+	printk(KERN_INFO "%s: start processing event=%lx\n", __func__, event);
+
+	// Notify the event to nvrm_daemon.
+	if (event == PM_SUSPEND_PREPARE) {
+#ifndef CONFIG_HAS_EARLYSUSPEND
+		notify_daemon(STRING_PM_DISPLAY_OFF);
+#endif
+		notify_daemon(STRING_PM_SUSPEND_PREPARE);
+	}
+	else if (event == PM_POST_SUSPEND) {
+		notify_daemon(STRING_PM_POST_SUSPEND);
+#ifndef CONFIG_HAS_EARLYSUSPEND
+		notify_daemon(STRING_PM_DISPLAY_ON);
+#endif
+	}
+	else {
+		printk(KERN_ERR "%s: unknown event %ld\n", __func__, event);
+		return NOTIFY_DONE;
+	}
+
+	printk(KERN_INFO "%s: finished processing event=%ld\n", __func__, event);
+	return NOTIFY_OK;
+}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+void tegra_display_off(struct early_suspend *h)
+{
+	notify_daemon(STRING_PM_DISPLAY_OFF);
+}
+
+void tegra_display_on(struct early_suspend *h)
+{
+	notify_daemon(STRING_PM_DISPLAY_ON);
+}
+
+static struct early_suspend tegra_display_power =
+{
+	.suspend = tegra_display_off,
+	.resume = tegra_display_on,
+	.level = EARLY_SUSPEND_LEVEL_DISABLE_FB
+};
+#endif
+#endif
+
+static struct platform_device nvrm_device =
+{
+    .name = "nvrm"
+};
+
+
+static int __init nvrm_init(void)
+{
+	int ret = 0;
+	printk(KERN_INFO "%s called\n", __func__);
+
+	#if defined(CONFIG_PM)
+	// Register PM notifier.
+	pm_notifier(tegra_pm_notifier, 0);
+	tegra_pm_notifier_continue_ok = 0;
+	init_waitqueue_head(&tegra_pm_notifier_wait);
+
+	#if defined(CONFIG_HAS_EARLYSUSPEND)
+	register_early_suspend(&tegra_display_power);
+	#endif
+
+	// Create /sys/power/nvrm/notifier.
+	nvrm_kobj = kobject_create_and_add("nvrm", power_kobj);
+	sysfs_create_file(nvrm_kobj, &nvrm_notifier_attribute.attr);
+	sys_nvrm_notifier = NULL;
+	init_waitqueue_head(&sys_nvrm_notifier_wait);
+	#endif
+
+	// Register NvRm platform driver.
+	ret = platform_driver_register(&nvrm_driver);
+
+	platform_device_register(&nvrm_device);
+
+	return ret;
+}
+
+static void __exit nvrm_deinit(void)
+{
+    printk(KERN_INFO "%s called\n", __func__);
+    platform_driver_unregister(&nvrm_driver);
+}
+
+module_init(nvrm_init);
+module_exit(nvrm_deinit);
diff --git a/arch/arm/mach-tegra/nv/nvrpc_user.c b/arch/arm/mach-tegra/nv/nvrpc_user.c
new file mode 100644
index 000000000000..526c9fffb2a2
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/nvrpc_user.c
@@ -0,0 +1,676 @@
+/*
+ * arch/arm/mach-tegra/nvrpc_user.c
+ *
+ * User-land access to NvRm transport APIs
+ *
+ * Copyright (c) 2008-2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#define NV_DEBUG 0
+
+#include <linux/module.h>
+#include <linux/proc_fs.h>
+#include <linux/miscdevice.h>
+#include <linux/uaccess.h>
+#include <mach/nvrm_linux.h>
+#include <mach/nvrpc.h>
+#include "nvcommon.h"
+#include "nvassert.h"
+#include "nvos.h"
+#include "nvrm_transport.h"
+#include "nvrm_xpc.h"
+
+#define DEVICE_NAME "nvrpc"
+#define NVRPC_MAX_LOCAL_STACK   256
+#define nvrpc_stack_kzalloc(stackbuf, size, gfp) \
+            ((size) > sizeof((stackbuf)) ? kzalloc((size),(gfp)) : (stackbuf))
+#define nvrpc_stack_kfree(stackbuf, buf) \
+            do { \
+                if ((buf) && (buf)!=(void *)(stackbuf)) \
+                kfree(buf); \
+            } while (0);
+
+static int nvrpc_open(struct inode *inode, struct file *file);
+static int nvrpc_close(struct inode *inode, struct file *file);
+static long nvrpc_unlocked_ioctl(struct file *file,
+    unsigned int cmd, unsigned long arg);
+
+//Ioctl functions
+static int nvrpc_ioctl_open(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_get_port_name(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_close(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_wait_for_connect(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_connect(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_set_queue_depth(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_send_msg(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_send_msg_lp0(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_recv_msg(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_xpc_init(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_xpc_acquire(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_xpc_release(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_xpc_get_msg(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_xpc_send_msg(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_xpc_destroy(struct file *filp,
+	unsigned int cmd, void __user *arg);
+static int nvrpc_ioctl_xpc_create(struct file *filp,
+	unsigned int cmd, void __user *arg);
+// local function
+static int nvrpc_make_error_code(NvError e);
+
+static const struct file_operations nvrpc_fops =
+{
+	.owner		= THIS_MODULE,
+	.open		= nvrpc_open,
+	.release	= nvrpc_close,
+	.unlocked_ioctl	= nvrpc_unlocked_ioctl,
+};
+
+static struct miscdevice nvrpc_dev =
+{
+	.name	= DEVICE_NAME,
+	.fops	= &nvrpc_fops,
+	.minor	= MISC_DYNAMIC_MINOR,
+};
+
+static DEFINE_MUTEX(nvrpc_device_lock);
+
+static NvBool s_init_done = NV_FALSE;
+NvRmDeviceHandle s_hRmGlobal = NULL;
+
+int nvrpc_open(struct inode *inode, struct file *file)
+{
+	NvError e = NvSuccess;
+
+	mutex_lock(&nvrpc_device_lock);
+	if (s_init_done == NV_FALSE) {
+		e = NvRmTransportInit(s_hRmGlobal);
+		s_init_done = NV_TRUE;
+	}
+	mutex_unlock(&nvrpc_device_lock);
+
+	if (e == NvSuccess)
+		return 0;
+	else
+		return -ENODEV;
+}
+
+int nvrpc_close(struct inode *inode, struct file *file)
+{
+	return 0;
+}
+
+static int nvrpc_make_error_code(NvError e)
+{
+	int error = 0;
+	if (error != NvSuccess) {
+		if (e == NvError_InvalidAddress)
+			error = -EFAULT;
+		else if (e == NvError_BadParameter)
+			error = -EINVAL;
+		else
+			error = -EIO;
+	}
+	return error;
+}
+
+NvRmTransportHandle g_hTransportAvp = NULL;
+NvRmTransportHandle g_hTransportCpu = NULL;
+NvOsSemaphoreHandle g_hTransportAvpSem = NULL;
+NvOsSemaphoreHandle g_hTransportCpuSem = NULL;
+int g_hTransportAvpIsConnected = 0;
+int g_hTransportCpuIsConnected = 0;
+
+static int nvrpc_ioctl_open(struct file *filp,
+			    unsigned int cmd, void __user *arg)
+{
+	NvError e = NvSuccess;
+	int error;
+	struct nvrpc_open_params op;
+	char *p_name = NULL;
+	NvOsSemaphoreHandle recv_sem = NULL;
+	NvU32 port_name[NVRPC_MAX_LOCAL_STACK/sizeof(NvU32)];
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+
+	if (op.port_name_size) {
+		p_name = nvrpc_stack_kzalloc(port_name,
+					     op.port_name_size, GFP_KERNEL);
+		if (!p_name) {
+			error = -ENOMEM;
+			goto fail;
+		}
+		error = copy_from_user(p_name, (const void*)op.port_name,
+				       op.port_name_size);
+		if (error)
+			goto fail;
+		if (p_name[op.port_name_size - 1] != 0) {
+			error = -EINVAL;
+			goto fail;
+		}
+	}
+	if (op.sem) {
+		NvOsSemaphoreHandle sem = (NvOsSemaphoreHandle) op.sem;
+		e = NvOsSemaphoreUnmarshal(sem, &recv_sem);
+		if (e != NvSuccess)
+			goto fail;
+	}
+	op.ret_val = NvRmTransportOpen(s_hRmGlobal, p_name, recv_sem,
+				       (void *)&op.transport_handle);
+	error = copy_to_user(arg, &op, sizeof(op));
+	if (p_name && ! strcmp(p_name, "RPC_CPU_PORT")) {
+	    if (g_hTransportCpu) {
+		    panic("%s: g_hTransportCpu=%p is already assigned.\n", __func__, g_hTransportCpu);
+	    }
+	    g_hTransportCpu = (NvRmTransportHandle)op.transport_handle;
+	    g_hTransportCpuSem = (NvOsSemaphoreHandle) op.sem;
+	}
+	if (p_name && ! strcmp(p_name, "RPC_AVP_PORT")) {
+	    if (g_hTransportAvp) {
+		    panic("%s: g_hTransportAvp=%p is already assigned.\n", __func__, g_hTransportAvp);
+	    }
+	    g_hTransportAvp = (NvRmTransportHandle)op.transport_handle;
+	    g_hTransportAvpSem = (NvOsSemaphoreHandle) op.sem;
+	}
+
+fail:
+	nvrpc_stack_kfree((char*)port_name, p_name);
+	if (recv_sem)
+		NvOsSemaphoreDestroy(recv_sem);
+	if (e != NvSuccess)
+		error = nvrpc_make_error_code(e);
+	return error;
+}
+
+static int nvrpc_ioctl_get_port_name(struct file *filp,
+				     unsigned int cmd, void __user *arg)
+{
+	int error;
+
+	struct nvrpc_open_params op;
+	NvS8 *p_name = NULL;
+	NvU32 port_name[NVRPC_MAX_LOCAL_STACK/sizeof(NvU32)];
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	if (op.port_name_size && op.port_name) {
+		p_name = nvrpc_stack_kzalloc(port_name,
+					     op.port_name_size, GFP_KERNEL);
+		if (!p_name) {
+			error = -ENOMEM;
+			goto fail;
+		}
+	}
+	NvRmTransportGetPortName((NvRmTransportHandle)op.transport_handle,
+				 p_name, op.port_name_size);
+
+	if (op.port_name_size && p_name) {
+		error = copy_to_user((void*)op.port_name,
+				     p_name, op.port_name_size * sizeof(NvU8));
+	}
+
+fail:
+	nvrpc_stack_kfree((NvS8*)port_name, p_name);
+	return error;
+}
+
+static int nvrpc_ioctl_close(struct file *filp,
+			     unsigned int cmd, void __user *arg)
+{
+	int error;
+	struct nvrpc_handle_param op;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	NvRmTransportClose((void*)op.handle);
+
+fail:
+	return error;
+}
+
+static int nvrpc_ioctl_wait_for_connect(struct file *filp,
+					unsigned int cmd, void __user *arg)
+{
+	NvError e = NvSuccess;
+	int error;
+	struct nvrpc_handle_param op;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	op.ret_val = NvRmTransportWaitForConnect(
+		(void *)op.handle, op.param);
+	error = copy_to_user(arg, &op, sizeof(op));
+
+fail:
+	if (e != NvSuccess)
+		error = nvrpc_make_error_code(e);
+	return error;
+}
+
+static int nvrpc_ioctl_connect(struct file *filp,
+			       unsigned int cmd, void __user *arg)
+{
+	NvError e = NvSuccess;
+	int error;
+	struct nvrpc_handle_param op;
+	NvU8 port_name[NVRPC_MAX_LOCAL_STACK];
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+
+	NvRmTransportGetPortName((void *)op.handle,
+				 port_name, sizeof(port_name));
+
+
+	op.ret_val = NvRmTransportConnect(
+		(void *)op.handle, op.param);
+	error = copy_to_user(arg, &op, sizeof(op));
+
+	if (! strcmp(port_name, "RPC_AVP_PORT")) {
+	    g_hTransportAvpIsConnected = 1;
+	}
+	if (! strcmp(port_name, "RPC_CPU_PORT")) {
+	    g_hTransportCpuIsConnected = 1;
+	}
+
+fail:
+	if (e != NvSuccess)
+		error = nvrpc_make_error_code(e);
+	return error;
+}
+
+static int nvrpc_ioctl_set_queue_depth(struct file *filp,
+				       unsigned int cmd, void __user *arg)
+{
+	NvError e = NvSuccess;
+	int error;
+	struct nvrpc_set_queue_depth_params op;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	op.ret_val = NvRmTransportSetQueueDepth(
+		(NvRmTransportHandle)op.transport_handle,
+		op.max_queue_depth,
+		op.max_message_size);
+	error = copy_to_user(arg, &op, sizeof(op));
+
+fail:
+	if (e != NvSuccess)
+		error = nvrpc_make_error_code(e);
+	return error;
+}
+
+static int nvrpc_ioctl_send_msg(struct file *filp,
+				unsigned int cmd, void __user *arg)
+{
+	int error;
+	struct nvrpc_msg_params op;
+	void* msg_buffer = NULL;
+	NvU32 buffer[NVRPC_MAX_LOCAL_STACK/sizeof(NvU32)];
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	if (op.msg_buffer && op.max_message_size) {
+		msg_buffer = nvrpc_stack_kzalloc(buffer,
+						 op.max_message_size,
+						 GFP_KERNEL);
+		if (!msg_buffer) {
+			error = -ENOMEM;
+			goto fail;
+		}
+		error = copy_from_user(msg_buffer,
+				       (void*)op.msg_buffer,
+				       op.max_message_size);
+        if (error)
+		goto fail;
+	}
+
+	op.ret_val = NvRmTransportSendMsg(
+		(NvRmTransportHandle)op.transport_handle,
+		msg_buffer, op.max_message_size, op.params);
+	error = copy_to_user(arg, &op, sizeof(op));
+
+fail:
+	nvrpc_stack_kfree(buffer, msg_buffer);
+	return error;
+}
+
+static int nvrpc_ioctl_send_msg_lp0(struct file *filp,
+				    unsigned int cmd, void __user *arg)
+{
+	int error;
+	struct nvrpc_msg_params op;
+	void* msg_buffer = NULL;
+	NvU32 buffer[NVRPC_MAX_LOCAL_STACK/sizeof(NvU32)];
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	if (op.msg_buffer && op.max_message_size)  {
+        msg_buffer = nvrpc_stack_kzalloc(buffer,
+					 op.max_message_size, GFP_KERNEL);
+        if (!msg_buffer) {
+		error = -ENOMEM;
+		goto fail;
+        }
+        error = copy_from_user(msg_buffer, (void*)op.msg_buffer,
+			       op.max_message_size);
+        if (error)
+		goto fail;
+	}
+	op.ret_val = NvRmTransportSendMsgInLP0(
+		(NvRmTransportHandle)op.transport_handle,
+		msg_buffer, op.max_message_size);
+	error = copy_to_user(arg, &op, sizeof(op));
+
+fail:
+	nvrpc_stack_kfree(buffer, msg_buffer);
+	return error;
+}
+
+static int nvrpc_ioctl_recv_msg(struct file *filp,
+				unsigned int cmd, void __user *arg)
+{
+	int error;
+	struct nvrpc_msg_params op;
+	void* msg_buffer = NULL;
+	NvU32 buffer[NVRPC_MAX_LOCAL_STACK/sizeof(NvU32)];
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	if (op.msg_buffer && op.max_message_size) {
+		msg_buffer = nvrpc_stack_kzalloc(buffer,
+			op.max_message_size, GFP_KERNEL);
+		if (!msg_buffer) {
+			error = -ENOMEM;
+			goto fail;
+		}
+	} else {
+		error = -EINVAL;
+		goto fail;
+	}
+	op.ret_val = NvRmTransportRecvMsg(
+		(NvRmTransportHandle)op.transport_handle,
+		msg_buffer, op.max_message_size, &op.params);
+	error = copy_to_user(arg, &op, sizeof(op));
+	if (op.msg_buffer && msg_buffer) {
+		error = copy_to_user((void*)op.msg_buffer,
+                    msg_buffer, op.max_message_size);
+		if (error)
+			goto fail;
+	}
+
+fail:
+	nvrpc_stack_kfree(buffer, msg_buffer);
+	return error;
+}
+
+static int nvrpc_ioctl_xpc_init(struct file *filp,
+				unsigned int cmd, void __user *arg)
+{
+	int error;
+	struct nvrpc_handle_param op;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	op.ret_val = NvRmXpcInitArbSemaSystem((void *)op.handle);
+	error = copy_to_user(arg, &op, sizeof(op));
+
+fail:
+	return error;
+}
+
+static int nvrpc_ioctl_xpc_acquire(struct file *filp,
+				   unsigned int cmd, void __user *arg)
+{
+	int error;
+	struct nvrpc_handle_param op;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	NvRmXpcModuleAcquire(op.param);
+
+fail:
+	return error;
+}
+
+static int nvrpc_ioctl_xpc_release(struct file *filp,
+				   unsigned int cmd, void __user *arg)
+{
+	int error;
+	struct nvrpc_handle_param op;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	NvRmXpcModuleRelease(op.param);
+
+fail:
+	return error;
+}
+
+static int nvrpc_ioctl_xpc_get_msg(struct file *filp,
+				   unsigned int cmd, void __user *arg)
+{
+	int error;
+	struct nvrpc_handle_param op;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	op.ret_val = NvRmPrivXpcGetMessage(
+		(NvRmPrivXpcMessageHandle)op.handle);
+	error = copy_to_user(arg, &op, sizeof(op));
+
+fail:
+	return error;
+}
+
+static int nvrpc_ioctl_xpc_send_msg(struct file *filp,
+				    unsigned int cmd, void __user *arg)
+{
+	int error;
+	struct nvrpc_handle_param op;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	op.ret_val = NvRmPrivXpcSendMessage(
+		(NvRmPrivXpcMessageHandle)op.handle, op.param);
+	error = copy_to_user(arg, &op, sizeof(op));
+
+fail:
+	return error;
+}
+
+static int nvrpc_ioctl_xpc_destroy(struct file *filp,
+				   unsigned int cmd, void __user *arg)
+{
+	int error;
+	struct nvrpc_handle_param op;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	NvRmPrivXpcDestroy((NvRmPrivXpcMessageHandle)op.handle);
+
+fail:
+	return error;
+}
+
+static int nvrpc_ioctl_xpc_create(struct file *filp,
+				  unsigned int cmd, void __user *arg)
+{
+	int error;
+	struct nvrpc_handle_param op;
+
+	error = copy_from_user(&op, arg, sizeof(op));
+	if (error)
+		goto fail;
+	op.ret_val = NvRmPrivXpcCreate((NvRmDeviceHandle)op.handle,
+				       (void*)&op.param);
+	error = copy_to_user(&op, arg, sizeof(op));
+
+fail:
+	return error;
+}
+
+
+static long nvrpc_unlocked_ioctl(struct file *file,
+				 unsigned int cmd, unsigned long arg)
+{
+	int err = 0;
+	void __user *uarg = (void __user *)arg;
+
+	if (_IOC_TYPE(cmd) != NVRPC_IOC_MAGIC)
+		return -ENOTTY;
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		err = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	if (_IOC_DIR(cmd) & _IOC_WRITE)
+		err = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+
+	if (err)
+		return -EFAULT;
+
+	switch (cmd) {
+	case NVRPC_IOCTL_OPEN:
+		err = nvrpc_ioctl_open(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_GET_PORTNAME:
+		err = nvrpc_ioctl_get_port_name(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_CLOSE:
+		err = nvrpc_ioctl_close(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_INIT:
+	case NVRPC_IOCTL_DEINIT:
+		break;
+
+	case NVRPC_IOCTL_WAIT_FOR_CONNECT:
+		err = nvrpc_ioctl_wait_for_connect(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_CONNECT:
+		err = nvrpc_ioctl_connect(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_SET_QUEUE_DEPTH:
+		err = nvrpc_ioctl_set_queue_depth(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_SEND_MSG:
+		err = nvrpc_ioctl_send_msg(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_SEND_MSG_LP0:
+		err = nvrpc_ioctl_send_msg_lp0(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_RECV_MSG:
+		err = nvrpc_ioctl_recv_msg(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_XPC_INIT:
+		err = nvrpc_ioctl_xpc_init(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_XPC_ACQUIRE:
+		err = nvrpc_ioctl_xpc_acquire(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_XPC_RELEASE:
+		err = nvrpc_ioctl_xpc_release(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_XPC_GET_MSG:
+		err = nvrpc_ioctl_xpc_get_msg(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_XPC_SEND_MSG:
+		err = nvrpc_ioctl_xpc_send_msg(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_XPC_DESTROY:
+		err = nvrpc_ioctl_xpc_destroy(file, cmd, uarg);
+		break;
+
+	case NVRPC_IOCTL_XPC_CREATE:
+		err = nvrpc_ioctl_xpc_create(file, cmd, uarg);
+		break;
+
+	default:
+		return -ENOTTY;
+	}
+	return err;
+}
+
+static int __init nvrpc_init(void)
+{
+	int ret = 0;
+
+	NvRmDeviceHandle handle;
+	NvRmInit(&handle);
+
+	if (s_init_done == NV_FALSE) {
+		NvError e;
+
+		e = NvRmOpen(&s_hRmGlobal, 0);
+		e = NvRmTransportInit(s_hRmGlobal);
+		s_init_done = NV_TRUE;
+	}
+
+	ret = misc_register(&nvrpc_dev);
+	if (ret) {
+		pr_err("%s misc register FAILED\n", __func__);
+	}
+	return ret;
+}
+
+static void __exit nvrpc_deinit(void)
+{
+	misc_deregister(&nvrpc_dev);
+}
+
+module_init(nvrpc_init);
+module_exit(nvrpc_deinit);
diff --git a/arch/arm/mach-tegra/pwm.c b/arch/arm/mach-tegra/pwm.c
index 1328310a404c..a268c391cb27 100644
--- a/arch/arm/mach-tegra/pwm.c
+++ b/arch/arm/mach-tegra/pwm.c
@@ -87,6 +87,9 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
 
 	if (rate >> PWM_SCALE_WIDTH)
 		return -EINVAL;
+        /* Due to the PWM divider is zero-based, we need to minus 1 to get desired frequency*/
+	if (rate>0)
+	    rate--;
 
 	val |= (rate << PWM_SCALE_SHIFT);
 
diff --git a/arch/arm/mach-tegra/spi_tegra_slave.c b/arch/arm/mach-tegra/spi_tegra_slave.c
new file mode 100644
index 000000000000..48492ab9253a
--- /dev/null
+++ b/arch/arm/mach-tegra/spi_tegra_slave.c
@@ -0,0 +1,860 @@
+/*
+ * arch/arm/mach-tegra/tegra_spi_slave.c
+ *
+ * Tegra slave spi driver for NVIDIA Tegra SoCs
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/clk.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+
+#include <linux/spi/spi.h>
+
+#include <mach/dma.h>
+#include <mach/spi.h>
+
+#define SLINK_COMMAND		0x000
+#define   SLINK_BIT_LENGTH(x)		(((x) & 0x1f) << 0)
+#define   SLINK_WORD_SIZE(x)		(((x) & 0x1f) << 5)
+#define   SLINK_BOTH_EN			(1 << 10)
+#define   SLINK_CS_SW			(1 << 11)
+#define   SLINK_CS_VALUE		(1 << 12)
+#define   SLINK_CS_POLARITY		(1 << 13)
+#define   SLINK_IDLE_SDA_DRIVE_LOW	(0 << 16)
+#define   SLINK_IDLE_SDA_DRIVE_HIGH	(1 << 16)
+#define   SLINK_IDLE_SDA_PULL_LOW	(2 << 16)
+#define   SLINK_IDLE_SDA_PULL_HIGH	(3 << 16)
+#define   SLINK_IDLE_SDA_MASK		(3 << 16)
+#define   SLINK_CS_POLARITY1		(1 << 20)
+#define   SLINK_CK_SDA			(1 << 21)
+#define   SLINK_CS_POLARITY2		(1 << 22)
+#define   SLINK_CS_POLARITY3		(1 << 23)
+#define   SLINK_IDLE_SCLK_DRIVE_LOW	(0 << 24)
+#define   SLINK_IDLE_SCLK_DRIVE_HIGH	(1 << 24)
+#define   SLINK_IDLE_SCLK_PULL_LOW	(2 << 24)
+#define   SLINK_IDLE_SCLK_PULL_HIGH	(3 << 24)
+#define   SLINK_IDLE_SCLK_MASK		(3 << 24)
+#define   SLINK_M_S			(1 << 28)
+#define   SLINK_WAIT			(1 << 29)
+#define   SLINK_GO			(1 << 30)
+#define   SLINK_ENB			(1 << 31)
+
+#define SLINK_COMMAND2		0x004
+#define   SLINK_LSBFE			(1 << 0)
+#define   SLINK_SSOE			(1 << 1)
+#define   SLINK_SPIE			(1 << 4)
+#define   SLINK_BIDIROE			(1 << 6)
+#define   SLINK_MODFEN			(1 << 7)
+#define   SLINK_INT_SIZE(x)		(((x) & 0x1f) << 8)
+#define   SLINK_CS_ACTIVE_BETWEEN	(1 << 17)
+#define   SLINK_SS_EN_CS(x)		(((x) & 0x3) << 18)
+#define   SLINK_SS_SETUP(x)		(((x) & 0x3) << 20)
+#define   SLINK_FIFO_REFILLS_0		(0 << 22)
+#define   SLINK_FIFO_REFILLS_1		(1 << 22)
+#define   SLINK_FIFO_REFILLS_2		(2 << 22)
+#define   SLINK_FIFO_REFILLS_3		(3 << 22)
+#define   SLINK_FIFO_REFILLS_MASK	(3 << 22)
+#define   SLINK_WAIT_PACK_INT(x)	(((x) & 0x7) << 26)
+#define   SLINK_SPC0			(1 << 29)
+#define   SLINK_TXEN			(1 << 30)
+#define   SLINK_RXEN			(1 << 31)
+
+#define SLINK_STATUS		0x008
+#define   SLINK_COUNT(val)		(((val) >> 0) & 0x1f)
+#define   SLINK_WORD(val)		(((val) >> 5) & 0x1f)
+#define   SLINK_BLK_CNT(val)		(((val) >> 0) & 0xffff)
+#define   SLINK_MODF			(1 << 16)
+#define   SLINK_RX_UNF			(1 << 18)
+#define   SLINK_TX_OVF			(1 << 19)
+#define   SLINK_TX_FULL			(1 << 20)
+#define   SLINK_TX_EMPTY		(1 << 21)
+#define   SLINK_RX_FULL			(1 << 22)
+#define   SLINK_RX_EMPTY		(1 << 23)
+#define   SLINK_TX_UNF			(1 << 24)
+#define   SLINK_RX_OVF			(1 << 25)
+#define   SLINK_TX_FLUSH		(1 << 26)
+#define   SLINK_RX_FLUSH		(1 << 27)
+#define   SLINK_SCLK			(1 << 28)
+#define   SLINK_ERR			(1 << 29)
+#define   SLINK_RDY			(1 << 30)
+#define   SLINK_BSY			(1 << 31)
+
+#define SLINK_MAS_DATA		0x010
+#define SLINK_SLAVE_DATA	0x014
+
+#define SLINK_DMA_CTL		0x018
+#define   SLINK_DMA_BLOCK_SIZE(x)	(((x) & 0xffff) << 0)
+#define   SLINK_TX_TRIG_1		(0 << 16)
+#define   SLINK_TX_TRIG_4		(1 << 16)
+#define   SLINK_TX_TRIG_8		(2 << 16)
+#define   SLINK_TX_TRIG_16		(3 << 16)
+#define   SLINK_TX_TRIG_MASK		(3 << 16)
+#define   SLINK_RX_TRIG_1		(0 << 18)
+#define   SLINK_RX_TRIG_4		(1 << 18)
+#define   SLINK_RX_TRIG_8		(2 << 18)
+#define   SLINK_RX_TRIG_16		(3 << 18)
+#define   SLINK_RX_TRIG_MASK		(3 << 18)
+#define   SLINK_PACKED			(1 << 20)
+#define   SLINK_PACK_SIZE_4		(0 << 21)
+#define   SLINK_PACK_SIZE_8		(1 << 21)
+#define   SLINK_PACK_SIZE_16		(2 << 21)
+#define   SLINK_PACK_SIZE_32		(3 << 21)
+#define   SLINK_PACK_SIZE_MASK		(3 << 21)
+#define   SLINK_IE_TXC			(1 << 26)
+#define   SLINK_IE_RXC			(1 << 27)
+#define   SLINK_DMA_EN			(1 << 31)
+
+#define SLINK_STATUS2		0x01c
+#define   SLINK_TX_FIFO_EMPTY_COUNT(val)	(((val) & 0x3f) >> 0)
+#define   SLINK_RX_FIFO_FULL_COUNT(val)		(((val) & 0x3f) >> 16)
+
+#define SLINK_TX_FIFO		0x100
+#define SLINK_RX_FIFO		0x180
+
+static const unsigned long spi_tegra_req_sels[] = {
+	TEGRA_DMA_REQ_SEL_SL2B1,
+	TEGRA_DMA_REQ_SEL_SL2B2,
+	TEGRA_DMA_REQ_SEL_SL2B3,
+	TEGRA_DMA_REQ_SEL_SL2B4,
+};
+
+#define BB_LEN			2048
+#define TX_FIFO_EMPTY_COUNT_MAX		SLINK_TX_FIFO_EMPTY_COUNT(0x20)
+#define RX_FIFO_FULL_COUNT_ZERO		SLINK_RX_FIFO_FULL_COUNT(0)
+
+#define SLINK_STATUS2_RESET \
+	(TX_FIFO_EMPTY_COUNT_MAX | \
+	RX_FIFO_FULL_COUNT_ZERO << 16)
+
+struct spi_tegra_data {
+	struct spi_master	*master;
+	struct platform_device	*pdev;
+	spinlock_t		lock;
+
+	struct clk		*clk;
+	void __iomem		*base;
+	unsigned long		phys;
+
+	u32			cur_speed;
+
+	struct list_head	queue;
+	struct spi_transfer	*cur;
+	unsigned		cur_pos;
+	unsigned		cur_len;
+	unsigned		cur_bytes_per_word;
+
+	/* The tegra spi controller has a bug which causes the first word
+	 * in PIO transactions to be garbage.  Since packed DMA transactions
+	 * require transfers to be 4 byte aligned we need a bounce buffer
+	 * for the generic case.
+	 */
+	struct tegra_dma_req	rx_dma_req;
+	struct tegra_dma_channel *rx_dma;
+	u32			*rx_bb;
+	dma_addr_t		rx_bb_phys;
+
+	struct tegra_dma_req	tx_dma_req;
+	struct tegra_dma_channel *tx_dma;
+	u32			*tx_bb;
+	dma_addr_t		tx_bb_phys;
+
+	bool			is_suspended;
+	unsigned long		save_slink_cmd;
+	callback client_funct;
+	void *client_data;
+
+	u32 rx_complete;
+	u32 tx_complete;
+	bool abort_happen;
+
+	u8 g_bits_per_word;
+};
+
+static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
+					unsigned long reg)
+{
+	return readl(tspi->base + reg);
+}
+
+static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
+					unsigned long val,
+					unsigned long reg)
+{
+	writel(val, tspi->base + reg);
+}
+
+static void spi_tegra_clear_status(struct spi_tegra_data *tspi)
+{
+	unsigned long val;
+	unsigned long val_write = 0;
+
+	val = spi_tegra_readl(tspi, SLINK_STATUS);
+	if (val & SLINK_BSY)
+		val_write |= SLINK_BSY;
+
+	if (val & SLINK_ERR) {
+		val_write |= SLINK_ERR;
+		printk("%s ERROR bit set 0x%lx \n", __func__, val);
+		if (val & SLINK_TX_OVF)
+			val_write |= SLINK_TX_OVF;
+		if (val & SLINK_RX_OVF)
+			val_write |= SLINK_RX_OVF;
+		if (val & SLINK_RX_UNF)
+			val_write |= SLINK_RX_UNF;
+		if (val & SLINK_TX_UNF)
+			val_write |= SLINK_TX_UNF;
+		if (!(val & SLINK_TX_EMPTY))
+			val_write |= SLINK_TX_FLUSH;
+		if (!(val & SLINK_RX_EMPTY))
+			val_write |= SLINK_RX_FLUSH;
+	}
+	spi_tegra_writel(tspi, val_write, SLINK_STATUS);
+}
+
+static void spi_tegra_go(struct spi_tegra_data *tspi)
+{
+	unsigned long val;
+	unsigned long test_val;
+
+	wmb();
+
+	val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
+	val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
+	val |= SLINK_DMA_BLOCK_SIZE(tspi->rx_dma_req.size / 4 - 1);
+	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
+	tegra_dma_enqueue_req(tspi->tx_dma, &tspi->tx_dma_req);
+	tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
+
+	val |= SLINK_DMA_EN;
+	val &= ~SLINK_TX_TRIG_MASK & ~SLINK_RX_TRIG_MASK;
+
+	if (tspi->rx_dma_req.size & 0xF)
+		val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
+	else if (((tspi->rx_dma_req.size) >> 4) & 0x1)
+		val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
+	else
+		val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
+
+	/*
+	 * TRM 24.1.1.7 wait for the FIFO to be full
+	 */
+	test_val = spi_tegra_readl(tspi, SLINK_STATUS);
+	while (!(test_val & SLINK_TX_FULL))
+		test_val = spi_tegra_readl(tspi, SLINK_STATUS);
+
+	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
+}
+
+static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,
+				struct spi_transfer *t)
+{
+	unsigned len = min(t->len - tspi->cur_pos, BB_LEN *
+				tspi->cur_bytes_per_word);
+	u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_pos;
+	int i, j;
+	unsigned long val;
+
+	val = spi_tegra_readl(tspi, SLINK_COMMAND);
+	val &= ~SLINK_WORD_SIZE(~0);
+	val |= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1);
+	spi_tegra_writel(tspi, val, SLINK_COMMAND);
+
+	if (tspi->g_bits_per_word == 32) {
+		memcpy(tspi->tx_bb, (void *)tx_buf, len);
+	} else {
+		for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
+			val = 0;
+			for (j = 0; j < tspi->cur_bytes_per_word; j++)
+				val |= tx_buf[i + j] << j * 8;
+
+			tspi->tx_bb[i / tspi->cur_bytes_per_word] = val;
+		}
+	}
+
+	tspi->tx_dma_req.size = len / tspi->cur_bytes_per_word * 4;
+
+	return len;
+}
+
+static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data *tspi,
+				struct spi_transfer *t)
+{
+	unsigned len = tspi->cur_len;
+	int i, j;
+	u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_pos;
+	unsigned long val;
+
+	if (tspi->g_bits_per_word == 32) {
+		memcpy(rx_buf, (void *)tspi->rx_bb, len);
+	} else {
+		for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
+			val = tspi->rx_bb[i / tspi->cur_bytes_per_word];
+			for (j = 0; j < tspi->cur_bytes_per_word; j++)
+				rx_buf[i + j] = (val >> (j * 8)) & 0xff;
+		}
+	}
+
+	return len;
+}
+
+int spi_tegra_register_callback(struct spi_device *spi, callback func,
+					void *client_data)
+{
+	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
+
+	if (!tspi || !func)
+		return -EINVAL;
+	tspi->client_funct = func;
+	tspi->client_data = client_data;
+	return 0;
+}
+EXPORT_SYMBOL(spi_tegra_register_callback);
+
+static void spi_tegra_start_transfer(struct spi_device *spi,
+					struct spi_transfer *t)
+{
+	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
+	unsigned long cs_bit;
+	u32 speed;
+	u8 bits_per_word;
+	unsigned long val;
+
+	speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
+	bits_per_word = t->bits_per_word ? t->bits_per_word  :
+		spi->bits_per_word;
+	tspi->g_bits_per_word = bits_per_word;
+
+	tspi->cur_bytes_per_word = (bits_per_word - 1) / 8 + 1;
+
+	if (speed != tspi->cur_speed)
+		clk_set_rate(tspi->clk, speed);
+
+	if (tspi->cur_speed == 0)
+		clk_enable(tspi->clk);
+
+	tspi->cur_speed = speed;
+
+	spi_tegra_clear_status(tspi);
+	val = spi_tegra_readl(tspi, SLINK_COMMAND2);
+	val &= ~SLINK_SS_EN_CS(~0) | SLINK_RXEN | SLINK_TXEN;
+	if (t->rx_buf)
+		val |= SLINK_RXEN;
+	if (t->tx_buf)
+		val |= SLINK_TXEN;
+	val |= SLINK_SS_EN_CS(spi->chip_select);
+	val |= SLINK_SPIE;
+	spi_tegra_writel(tspi, val, SLINK_COMMAND2);
+
+	val = spi_tegra_readl(tspi, SLINK_COMMAND);
+	switch (spi->chip_select) {
+	case 0:
+		cs_bit = SLINK_CS_POLARITY;
+		break;
+
+	case 1:
+		cs_bit = SLINK_CS_POLARITY1;
+		break;
+
+	case 2:
+		cs_bit = SLINK_CS_POLARITY2;
+		break;
+
+	case 4:
+		cs_bit = SLINK_CS_POLARITY3;
+		break;
+
+	default:
+		return;
+	}
+	if (spi->mode & SPI_CS_HIGH)
+		val |= cs_bit;
+	else
+		val &= ~cs_bit;
+
+	val &= ~SLINK_BIT_LENGTH(~0);
+	val |= SLINK_BIT_LENGTH(bits_per_word - 1);
+
+	/* FIXME: should probably control CS manually so that we can be sure
+	 * it does not go low between transfer and to support delay_usecs
+	 * correctly.
+	 */
+	val &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA & ~SLINK_CS_SW;
+
+	if (spi->mode & SPI_CPHA)
+		val |= SLINK_CK_SDA;
+	if (spi->mode & SPI_CPOL)
+		val |= SLINK_IDLE_SCLK_DRIVE_HIGH;
+	else
+		val |= SLINK_IDLE_SCLK_DRIVE_LOW;
+
+	val &= ~(SLINK_M_S); /* set slave mode */
+
+	spi_tegra_writel(tspi, val, SLINK_COMMAND);
+	spi_tegra_writel(tspi, SLINK_RX_FLUSH | SLINK_TX_FLUSH, SLINK_STATUS);
+	tspi->cur = t;
+	tspi->cur_pos = 0;
+	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, t);
+	tspi->rx_dma_req.size = tspi->tx_dma_req.size;
+	tspi->rx_complete = 0;
+	tspi->tx_complete = 0;
+	tspi->abort_happen = false;
+
+	spi_tegra_go(tspi);
+	/* notify client that we're ready for transfer */
+	if (tspi->client_funct)
+		tspi->client_funct(tspi->client_data);
+}
+
+static void spi_tegra_start_message(struct spi_device *spi,
+					struct spi_message *m)
+{
+	struct spi_transfer *t;
+
+	m->actual_length = 0;
+	m->status = 0;
+
+	t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
+	spi_tegra_start_transfer(spi, t);
+}
+
+static void complete_operation(struct tegra_dma_req *req)
+{
+	struct spi_tegra_data *tspi = req->dev;
+	unsigned long val;
+	struct spi_message *m;
+	struct spi_device *spi;
+	u32 timeout = 0;
+	u32 temp = 0;
+
+	if (tspi->abort_happen == true) {
+		unsigned long val_write = 0;
+		val_write = spi_tegra_readl(tspi, SLINK_STATUS);
+		val_write = val_write | SLINK_TX_FLUSH | SLINK_RX_FLUSH ;
+
+		spi_tegra_writel(tspi, val_write, SLINK_STATUS);
+
+		/*In order to make sure Tx fifo fluch is completed.*/
+		while (spi_tegra_readl(tspi, SLINK_STATUS)&SLINK_TX_FLUSH)
+			;
+		/*In order to make sure Rx fifo fluch is completed.*/
+		while (spi_tegra_readl(tspi, SLINK_STATUS)&SLINK_RX_FLUSH)
+			;
+	}
+
+	/* the SPI controller may come back with both the BSY and RDY bits
+	* set.  In this case we need to wait for the BSY bit to clear so
+	* that we are sure the DMA is finished.  1000 reads was empirically
+	* determined to be long enough.
+	*/
+
+	while ((spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY)) {
+		if (timeout++ > 1000)
+			break;
+	}
+
+	while ((spi_tegra_readl(tspi, SLINK_STATUS2)) != SLINK_STATUS2_RESET) {
+		if (temp++ > 50000)
+			break;
+	}
+
+	spi_tegra_clear_status(tspi);
+
+	val = spi_tegra_readl(tspi, SLINK_STATUS);
+	val |= SLINK_RDY;
+	spi_tegra_writel(tspi, val, SLINK_STATUS);
+
+	m = list_first_entry(&tspi->queue, struct spi_message, queue);
+
+	if ((timeout >= 1000) || (temp >= 50000))
+		m->status = -EIO;
+
+	spi = m->state;
+
+	tspi->cur_pos += spi_tegra_drain_rx_fifo(tspi, tspi->cur);
+	m->actual_length += tspi->cur_pos;
+
+	if (!list_is_last(&tspi->cur->transfer_list, &m->transfers)) {
+		tspi->cur = list_first_entry(&tspi->cur->transfer_list,
+			struct spi_transfer, transfer_list);
+		spi_tegra_start_transfer(spi, tspi->cur);
+	} else {
+		list_del(&m->queue);
+
+		m->complete(m->context);
+
+		if (!list_empty(&tspi->queue)) {
+			m = list_first_entry(&tspi->queue, struct spi_message,
+				queue);
+			spi = m->state;
+			spi_tegra_start_message(spi, m);
+		} else {
+			clk_disable(tspi->clk);
+			tspi->cur_speed = 0;
+		}
+	}
+}
+
+static void tegra_spi_tx_dma_complete(struct tegra_dma_req *req)
+{
+	struct spi_tegra_data *tspi = req->dev;
+	unsigned long flags;
+
+	spin_lock_irqsave(&tspi->lock, flags);
+
+	(tspi->tx_complete)++;
+
+	if (((tspi->rx_complete) == 1) && ((tspi->tx_complete) == 1))
+		complete_operation(req);
+
+	spin_unlock_irqrestore(&tspi->lock, flags);
+
+}
+
+static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
+{
+	struct spi_tegra_data *tspi = req->dev;
+	unsigned long flags;
+
+	spin_lock_irqsave(&tspi->lock, flags);
+
+	(tspi->rx_complete)++;
+
+	if (((tspi->rx_complete) == 1) && ((tspi->tx_complete) == 1))
+		complete_operation(req);
+
+	spin_unlock_irqrestore(&tspi->lock, flags);
+}
+
+static int spi_tegra_setup(struct spi_device *spi)
+{
+	dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
+		spi->bits_per_word,
+		spi->mode & SPI_CPOL ? "" : "~",
+		spi->mode & SPI_CPHA ? "" : "~",
+		spi->max_speed_hz);
+
+	return 0;
+}
+
+static int spi_tegra_transfer(struct spi_device *spi, struct spi_message *m)
+{
+	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
+	struct spi_transfer *t;
+	unsigned long flags;
+	int was_empty;
+
+	if (list_empty(&m->transfers) || !m->complete)
+		return -EINVAL;
+
+	list_for_each_entry(t, &m->transfers, transfer_list) {
+		if (t->bits_per_word < 0 || t->bits_per_word > 32)
+			return -EINVAL;
+
+		if (t->len == 0)
+			return -EINVAL;
+
+		if (!t->rx_buf && !t->tx_buf)
+			return -EINVAL;
+	}
+
+	spin_lock_irqsave(&tspi->lock, flags);
+
+	if (WARN_ON(tspi->is_suspended)) {
+		spin_unlock_irqrestore(&tspi->lock, flags);
+		return -EBUSY;
+	}
+
+	m->state = spi;
+
+	was_empty = list_empty(&tspi->queue);
+	list_add_tail(&m->queue, &tspi->queue);
+
+	if (was_empty)
+		spi_tegra_start_message(spi, m);
+
+	spin_unlock_irqrestore(&tspi->lock, flags);
+
+	return 0;
+}
+
+static int __init spi_tegra_probe(struct platform_device *pdev)
+{
+	struct spi_master	*master;
+	struct spi_tegra_data	*tspi;
+	struct resource		*r;
+	int ret;
+
+	master = spi_alloc_master(&pdev->dev, sizeof *tspi);
+	if (master == NULL) {
+		dev_err(&pdev->dev, "master allocation failed\n");
+		return -ENOMEM;
+	}
+
+	/* the spi->mode bits understood by this driver: */
+	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
+
+	if (pdev->id != -1)
+		master->bus_num = pdev->id;
+
+	master->setup = spi_tegra_setup;
+	master->transfer = spi_tegra_transfer;
+	master->num_chipselect = 4;
+
+	dev_set_drvdata(&pdev->dev, master);
+	tspi = spi_master_get_devdata(master);
+	tspi->master = master;
+	tspi->pdev = pdev;
+	spin_lock_init(&tspi->lock);
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (r == NULL) {
+		ret = -ENODEV;
+		goto err0;
+	}
+
+	if (!request_mem_region(r->start, (r->end - r->start) + 1,
+				dev_name(&pdev->dev))) {
+		ret = -EBUSY;
+		goto err0;
+	}
+
+	tspi->phys = r->start;
+	tspi->base = ioremap(r->start, r->end - r->start + 1);
+	if (!tspi->base) {
+		dev_err(&pdev->dev, "can't ioremap iomem\n");
+		ret = -ENOMEM;
+		goto err1;
+	}
+
+	tspi->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR_OR_NULL(tspi->clk)) {
+		dev_err(&pdev->dev, "can not get clock\n");
+		ret = PTR_ERR(tspi->clk);
+		goto err2;
+	}
+
+	INIT_LIST_HEAD(&tspi->queue);
+
+	tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
+	if (!tspi->rx_dma) {
+		dev_err(&pdev->dev, "can not allocate rx dma channel\n");
+		ret = -ENODEV;
+		goto err3;
+	}
+
+	tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
+					 &tspi->rx_bb_phys, GFP_KERNEL);
+	if (!tspi->rx_bb) {
+		dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");
+		ret = -ENOMEM;
+		goto err4;
+	}
+
+	memset(&tspi->rx_dma_req, 0, sizeof(struct tegra_dma_req)) ;
+	tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
+	tspi->rx_dma_req.to_memory = 1;
+	tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
+	tspi->rx_dma_req.virt_addr = tspi->rx_bb ;
+	tspi->rx_dma_req.dest_bus_width = 32;
+	tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
+	tspi->rx_dma_req.source_bus_width = 32;
+	tspi->rx_dma_req.source_wrap = 4;
+	tspi->rx_dma_req.dest_wrap = 0 ;
+	tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
+	tspi->rx_dma_req.dev = tspi;
+
+	tspi->tx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
+	if (IS_ERR(tspi->tx_dma)) {
+		dev_err(&pdev->dev, "can not allocate tx dma channel\n");
+		ret = PTR_ERR(tspi->tx_dma);
+		goto err5;
+	}
+
+	tspi->tx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
+					 &tspi->tx_bb_phys, GFP_KERNEL);
+	if (!tspi->tx_bb) {
+		dev_err(&pdev->dev, "can not allocate tx bounce buffer\n");
+		ret = -ENOMEM;
+		goto err6;
+	}
+
+	memset(&tspi->tx_dma_req, 0, sizeof(struct tegra_dma_req)) ;
+	tspi->tx_dma_req.complete = tegra_spi_tx_dma_complete;
+	tspi->tx_dma_req.to_memory = 0;
+	tspi->tx_dma_req.dest_addr = tspi->phys + SLINK_TX_FIFO;
+	tspi->tx_dma_req.virt_addr = tspi->tx_bb ;
+	tspi->tx_dma_req.dest_bus_width = 32;
+	tspi->tx_dma_req.dest_wrap = 4;
+	tspi->tx_dma_req.source_wrap = 0 ;
+	tspi->tx_dma_req.source_addr = tspi->tx_bb_phys;
+	tspi->tx_dma_req.source_bus_width = 32;
+	tspi->tx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
+	tspi->tx_dma_req.dev = tspi;
+
+	ret = spi_register_master(master);
+	if (ret < 0)
+		goto err7;
+
+	return ret;
+
+err7:
+	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
+				tspi->tx_bb, tspi->tx_bb_phys);
+err6:
+	tegra_dma_free_channel(tspi->tx_dma);
+err5:
+	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
+				tspi->rx_bb, tspi->rx_bb_phys);
+err4:
+	tegra_dma_free_channel(tspi->rx_dma);
+err3:
+	clk_put(tspi->clk);
+err2:
+	iounmap(tspi->base);
+err1:
+	release_mem_region(r->start, (r->end - r->start) + 1);
+err0:
+	spi_master_put(master);
+	return ret;
+}
+
+static int __devexit spi_tegra_remove(struct platform_device *pdev)
+{
+	struct spi_master	*master;
+	struct spi_tegra_data	*tspi;
+	struct resource		*r;
+
+	master = dev_get_drvdata(&pdev->dev);
+	tspi = spi_master_get_devdata(master);
+
+	tegra_dma_free_channel(tspi->rx_dma);
+
+	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
+			  tspi->rx_bb, tspi->rx_bb_phys);
+
+	clk_put(tspi->clk);
+	iounmap(tspi->base);
+
+	spi_master_put(master);
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(r->start, (r->end - r->start) + 1);
+
+	return 0;
+}
+
+void spi_tegra_abort_transfer(struct spi_device *spi)
+{
+	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
+	struct spi_message *m;
+	unsigned long flags;
+
+	spin_lock_irqsave(&tspi->lock, flags);
+	if (((tspi->rx_complete) != 0) || ((tspi->tx_complete) != 0))
+		spin_unlock_irqrestore(&tspi->lock, flags);
+
+	tspi->abort_happen = true;
+	spin_unlock_irqrestore(&tspi->lock, flags);
+
+	m = list_first_entry(&tspi->queue, struct spi_message, queue);
+	m->status = -EIO;
+
+	tegra_dma_dequeue(tspi->tx_dma);
+	tegra_dma_dequeue(tspi->rx_dma);
+}
+EXPORT_SYMBOL(spi_tegra_abort_transfer);
+
+#ifdef CONFIG_PM
+static int spi_tegra_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct spi_master	*master;
+	struct spi_tegra_data	*tspi;
+	unsigned long		flags;
+	unsigned		limit = 50;
+
+	master = dev_get_drvdata(&pdev->dev);
+	tspi = spi_master_get_devdata(master);
+	spin_lock_irqsave(&tspi->lock, flags);
+	tspi->is_suspended = true;
+	WARN_ON(!list_empty(&tspi->queue));
+
+	while (!list_empty(&tspi->queue) && limit--) {
+		spin_unlock_irqrestore(&tspi->lock, flags);
+		msleep(10);
+		spin_lock_irqsave(&tspi->lock, flags);
+	}
+
+	tspi->save_slink_cmd = spi_tegra_readl(tspi, SLINK_COMMAND);
+	spin_unlock_irqrestore(&tspi->lock, flags);
+	return 0;
+}
+
+static int spi_tegra_resume(struct platform_device *pdev)
+{
+	struct spi_master	*master;
+	struct spi_tegra_data	*tspi;
+	unsigned long		flags;
+
+	master = dev_get_drvdata(&pdev->dev);
+	tspi = spi_master_get_devdata(master);
+	spin_lock_irqsave(&tspi->lock, flags);
+	clk_enable(tspi->clk);
+	spi_tegra_writel(tspi, tspi->save_slink_cmd, SLINK_COMMAND);
+	clk_disable(tspi->clk);
+	tspi->cur_speed = 0;
+	tspi->is_suspended = false;
+	spin_unlock_irqrestore(&tspi->lock, flags);
+	return 0;
+}
+#endif
+
+MODULE_ALIAS("platform:tegra_spi_slave");
+
+static struct platform_driver spi_tegra_driver = {
+	.driver = {
+		.name =		"tegra_spi_slave",
+		.owner =	THIS_MODULE,
+	},
+	.remove =	__devexit_p(spi_tegra_remove),
+#ifdef CONFIG_PM
+	.suspend =	spi_tegra_suspend,
+	.resume  =	spi_tegra_resume,
+#endif
+};
+
+static int __init spi_tegra_init(void)
+{
+	return platform_driver_probe(&spi_tegra_driver, spi_tegra_probe);
+}
+module_init(spi_tegra_init);
+
+static void __exit spi_tegra_exit(void)
+{
+	platform_driver_unregister(&spi_tegra_driver);
+}
+module_exit(spi_tegra_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-tegra/syncpt.c b/arch/arm/mach-tegra/syncpt.c
new file mode 100644
index 000000000000..bb649a9fe51a
--- /dev/null
+++ b/arch/arm/mach-tegra/syncpt.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Erik Gilling <konkers@google.com>
+ *
+ * Copyright (C) 2010, NVIDIA Corporation
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+
+#define HOST1X_SYNC_OFFSET 0x3000
+#define HOST1X_SYNC_SIZE 0x800
+enum {
+	HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS = 0x40,
+	HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE = 0x60
+};
+
+static void syncpt_thresh_mask(unsigned int irq)
+{
+	(void)irq;
+}
+
+static void syncpt_thresh_unmask(unsigned int irq)
+{
+	(void)irq;
+}
+
+static void syncpt_thresh_cascade(unsigned int irq, struct irq_desc *desc)
+{
+	void __iomem *sync_regs = get_irq_desc_data(desc);
+	u32 reg;
+	int id;
+
+	desc->chip->ack(irq);
+
+	reg = readl(sync_regs + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS);
+
+	while ((id = __fls(reg)) >= 0) {
+		reg ^= BIT(id);
+		generic_handle_irq(id + INT_SYNCPT_THRESH_BASE);
+	}
+
+	desc->chip->unmask(irq);
+}
+
+static struct irq_chip syncpt_thresh_irq = {
+	.name		= "syncpt",
+	.mask		= syncpt_thresh_mask,
+	.unmask		= syncpt_thresh_unmask
+};
+
+static int __init syncpt_init_irq(void)
+{
+	void __iomem *sync_regs;
+	unsigned int i;
+	int irq;
+
+	sync_regs = ioremap(TEGRA_HOST1X_BASE + HOST1X_SYNC_OFFSET,
+			HOST1X_SYNC_SIZE);
+	BUG_ON(!sync_regs);
+
+	writel(0xffffffffUL,
+		sync_regs + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE);
+	writel(0xffffffffUL,
+		sync_regs + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS);
+
+	for (i = 0; i < INT_SYNCPT_THRESH_NR; i++) {
+		irq = INT_SYNCPT_THRESH_BASE + i;
+		set_irq_chip(irq, &syncpt_thresh_irq);
+		set_irq_chip_data(irq, sync_regs);
+		set_irq_handler(irq, handle_simple_irq);
+		set_irq_flags(irq, IRQF_VALID);
+	}
+	if (set_irq_data(INT_HOST1X_MPCORE_SYNCPT, sync_regs))
+		BUG();
+	set_irq_chained_handler(INT_HOST1X_MPCORE_SYNCPT,
+				syncpt_thresh_cascade);
+
+	return 0;
+}
+
+core_initcall(syncpt_init_irq);
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 2f809e0219b7..d657ef0792c5 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -24,6 +24,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/cpufreq.h>
 
 #include <asm/clkdev.h>
 
@@ -695,21 +696,6 @@ static struct clk_ops tegra_pll_ops = {
 	.set_rate		= tegra2_pll_clk_set_rate,
 };
 
-static void tegra2_pllx_clk_init(struct clk *c)
-{
-	tegra2_pll_clk_init(c);
-
-	if (tegra_sku_id() == 7)
-		c->max_rate = 750000000;
-}
-
-static struct clk_ops tegra_pllx_ops = {
-	.init     = tegra2_pllx_clk_init,
-	.enable   = tegra2_pll_clk_enable,
-	.disable  = tegra2_pll_clk_disable,
-	.set_rate = tegra2_pll_clk_set_rate,
-};
-
 /* Clock divider ops */
 static void tegra2_pll_div_clk_init(struct clk *c)
 {
@@ -939,8 +925,8 @@ static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
 	for (sel = c->inputs; sel->input != NULL; sel++) {
 		if (sel->input == p) {
 			val = clk_readl(c->reg);
-			val &= ~PERIPH_CLK_SOURCE_MASK;
-			val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
+			val &= ~((c->reg_shift >> 8) << (c->reg_shift & 0xFF));
+			val |= (sel->value) << (c->reg_shift & 0xFF);
 
 			if (c->refcnt)
 				clk_enable(p);
@@ -1578,6 +1564,12 @@ static struct clk tegra_pll_u = {
 };
 
 static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+	/* 1.2 GHz */
+	{ 12000000, 1200000000, 600,  6,  1, 12},
+	{ 13000000, 1200000000, 923,  10, 1, 12},
+	{ 19200000, 1200000000, 750,  12, 1, 8},
+	{ 26000000, 1200000000, 600,  13, 1, 12},
+
 	/* 1 GHz */
 	{ 12000000, 1000000000, 1000, 12, 1, 12},
 	{ 13000000, 1000000000, 1000, 13, 1, 12},
@@ -1602,6 +1594,12 @@ static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
 	{ 19200000, 760000000,  950,  24, 1, 8},
 	{ 26000000, 760000000,  760,  26, 1, 12},
 
+	/* 750 MHz */
+	{ 12000000, 750000000,  750,  12, 1, 12},
+	{ 13000000, 750000000,  750,  13, 1, 12},
+	{ 19200000, 750000000,  625,  16, 1, 8},
+	{ 26000000, 750000000,  750,  26, 1, 12},
+
 	/* 608 MHz */
 	{ 12000000, 608000000,  608,  12, 1, 12},
 	{ 13000000, 608000000,  608,  13, 1, 12},
@@ -1626,7 +1624,7 @@ static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
 static struct clk tegra_pll_x = {
 	.name      = "pll_x",
 	.flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
-	.ops       = &tegra_pllx_ops,
+	.ops       = &tegra_pll_ops,
 	.reg       = 0xe0,
 	.parent    = &tegra_clk_m,
 	.max_rate  = 1000000000,
@@ -1924,7 +1922,7 @@ static struct clk tegra_clk_emc = {
 	},
 };
 
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _reg_shift, _max, _inputs, _flags) \
 	{						\
 		.name      = _name,			\
 		.lookup    = {				\
@@ -1933,6 +1931,7 @@ static struct clk tegra_clk_emc = {
 		},					\
 		.ops       = &tegra_periph_clk_ops,	\
 		.reg       = _reg,			\
+		.reg_shift = _reg_shift,		\
 		.inputs    = _inputs,			\
 		.flags     = _flags,			\
 		.max_rate  = _max,			\
@@ -1953,70 +1952,72 @@ static struct clk tegra_clk_emc = {
 	}
 
 struct clk tegra_list_clks[] = {
-	PERIPH_CLK("rtc",	"rtc-tegra",		NULL,	4,	0,	32768,     mux_clk_32k,			PERIPH_NO_RESET),
-	PERIPH_CLK("timer",	"timer",		NULL,	5,	0,	26000000,  mux_clk_m,			0),
-	PERIPH_CLK("i2s1",	"i2s.0",		NULL,	11,	0x100,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("i2s2",	"i2s.1",		NULL,	18,	0x104,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("spdif_out",	"spdif_out",		NULL,	10,	0x108,	100000000, mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("spdif_in",	"spdif_in",		NULL,	10,	0x10c,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71),
-	PERIPH_CLK("pwm",	"pwm",			NULL,	17,	0x110,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71),
-	PERIPH_CLK("spi",	"spi",			NULL,	43,	0x114,	40000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("xio",	"xio",			NULL,	45,	0x120,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("twc",	"twc",			NULL,	16,	0x12c,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc1",	"spi_tegra.0",		NULL,	41,	0x134,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc2",	"spi_tegra.1",		NULL,	44,	0x118,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc3",	"spi_tegra.2",		NULL,	46,	0x11c,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sbc4",	"spi_tegra.3",		NULL,	68,	0x1b4,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("ide",	"ide",			NULL,	25,	0x144,	100000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("ndflash",	"tegra_nand",		NULL,	13,	0x160,	164000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("vfir",	"vfir",			NULL,	7,	0x168,	72000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("sdmmc1",	"sdhci-tegra.0",	NULL,	14,	0x150,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc2",	"sdhci-tegra.1",	NULL,	9,	0x154,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc3",	"sdhci-tegra.2",	NULL,	69,	0x1bc,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("sdmmc4",	"sdhci-tegra.3",	NULL,	15,	0x164,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("vcp",	"tegra-avp",		"vcp",	29,	0,	250000000, mux_clk_m, 			0),
-	PERIPH_CLK("bsea",	"tegra-avp",		"bsea",	62,	0,	250000000, mux_clk_m, 			0),
-	PERIPH_CLK("bsev",	"tegra-aes",		"bsev",	63,	0,	250000000, mux_clk_m, 			0),
-	PERIPH_CLK("vde",	"tegra-avp",		"vde",	61,	0x1c8,	250000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("csite",	"csite",		NULL,	73,	0x1d4,	144000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* max rate ??? */
+	PERIPH_CLK("rtc",	"rtc-tegra",		NULL,	4,	0,	0x31E,	32768,     mux_clk_32k,			PERIPH_NO_RESET),
+	PERIPH_CLK("kbc",	"tegra-kbc",		NULL,	36, 	0,	0x31E,	32768,	   mux_clk_32k, PERIPH_NO_RESET),
+	PERIPH_CLK("timer",	"timer",		NULL,	5,	0,	0x31E,	26000000,  mux_clk_m,			0),
+	PERIPH_CLK("kfuse",	"kfuse-tegra",		NULL,	40,	0,	0x31E,  26000000,  mux_clk_m,			0),
+	PERIPH_CLK("i2s1",	"i2s.0",		NULL,	11,	0x100,	0x31E,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("i2s2",	"i2s.1",		NULL,	18,	0x104,	0x31E,	26000000,  mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("spdif_out",	"spdif_out",		NULL,	10,	0x108,	0x31E,	100000000, mux_pllaout0_audio2x_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("spdif_in",	"spdif_in",		NULL,	10,	0x10c,	0x31E,	100000000, mux_pllp_pllc_pllm,		MUX | DIV_U71),
+	PERIPH_CLK("pwm",	"pwm",			NULL,	17,	0x110,	0x71C,	432000000, mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71),
+	PERIPH_CLK("spi",	"spi",			NULL,	43,	0x114,	0x31E,	40000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("xio",	"xio",			NULL,	45,	0x120,	0x31E,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("twc",	"twc",			NULL,	16,	0x12c,	0x31E,	150000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc1",	"spi_tegra.0",		NULL,	41,	0x134,	0x31E,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc2",	"spi_tegra.1",		NULL,	44,	0x118,	0x31E,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc3",	"spi_tegra.2",		NULL,	46,	0x11c,	0x31E,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc4",	"spi_tegra.3",		NULL,	68,	0x1b4,	0x31E,	160000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("ide",	"ide",			NULL,	25,	0x144,	0x31E,	100000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("ndflash",	"tegra_nand",		NULL,	13,	0x160,	0x31E,	164000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("vfir",	"vfir",			NULL,	7,	0x168,	0x31E,	72000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sdmmc1",	"sdhci-tegra.0",	NULL,	14,	0x150,	0x31E,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("sdmmc2",	"sdhci-tegra.1",	NULL,	9,	0x154,	0x31E,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("sdmmc3",	"sdhci-tegra.2",	NULL,	69,	0x1bc,	0x31E,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("sdmmc4",	"sdhci-tegra.3",	NULL,	15,	0x164,	0x31E,	52000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("vcp",	"tegra-avp",		"vcp",	29,	0,	0x31E,	250000000, mux_clk_m, 			0),
+	PERIPH_CLK("bsea",	"tegra-avp",		"bsea",	62,	0,	0x31E,	250000000, mux_clk_m, 			0),
+	PERIPH_CLK("bsev",	"tegra-aes",		"bsev",	63,	0,	0x31E,  250000000, mux_clk_m, 			0),
+	PERIPH_CLK("vde",	"tegra-avp",		"vde",	61,	0x1c8,	0x31E,	250000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("csite",	"csite",		NULL,	73,	0x1d4,	0x31E,	144000000, mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* max rate ??? */
 	/* FIXME: what is la? */
-	PERIPH_CLK("la",	"la",			NULL,	76,	0x1f8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("owr",	"tegra_w1",		NULL,	71,	0x1cc,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
-	PERIPH_CLK("nor",	"nor",			NULL,	42,	0x1d0,	92000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("mipi",	"mipi",			NULL,	50,	0x174,	60000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
-	PERIPH_CLK("i2c1",	"tegra-i2c.0",		NULL,	12,	0x124,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("i2c2",	"tegra-i2c.1",		NULL,	54,	0x198,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("i2c3",	"tegra-i2c.2",		NULL,	67,	0x1b8,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("dvc",	"tegra-i2c.3",		NULL,	47,	0x128,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
-	PERIPH_CLK("i2c1_i2c",	"tegra-i2c.0",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("i2c2_i2c",	"tegra-i2c.1",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("i2c3_i2c",	"tegra-i2c.2",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("dvc_i2c",	"tegra-i2c.3",		"i2c",	0,	0,	72000000,  mux_pllp_out3,			0),
-	PERIPH_CLK("uarta",	"uart.0",		NULL,	6,	0x178,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uartb",	"uart.1",		NULL,	7,	0x17c,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uartc",	"uart.2",		NULL,	55,	0x1a0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uartd",	"uart.3",		NULL,	65,	0x1c0,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("uarte",	"uart.4",		NULL,	66,	0x1c4,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
-	PERIPH_CLK("3d",	"3d",			NULL,	24,	0x158,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
-	PERIPH_CLK("2d",	"2d",			NULL,	21,	0x15c,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("vi",	"tegra_camera",		"vi",	20,	0x148,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("vi_sensor",	"tegra_camera",		"vi_sensor",	20,	0x1a8,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
-	PERIPH_CLK("epp",	"epp",			NULL,	19,	0x16c,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("mpe",	"mpe",			NULL,	60,	0x170,	250000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("host1x",	"host1x",		NULL,	28,	0x180,	166000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("cve",	"cve",			NULL,	49,	0x140,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("tvo",	"tvo",			NULL,	49,	0x188,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("hdmi",	"hdmi",			NULL,	51,	0x18c,	600000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("tvdac",	"tvdac",		NULL,	53,	0x194,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
-	PERIPH_CLK("disp1",	"tegradc.0",		NULL,	27,	0x138,	600000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("disp2",	"tegradc.1",		NULL,	26,	0x13c,	600000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* scales with voltage and process_id */
-	PERIPH_CLK("usbd",	"fsl-tegra-udc",	NULL,	22,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("usb2",	"tegra-ehci.1",		NULL,	58,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("usb3",	"tegra-ehci.2",		NULL,	59,	0,	480000000, mux_clk_m,			0), /* requires min voltage */
-	PERIPH_CLK("dsi",	"dsi",			NULL,	48,	0,	500000000, mux_plld,			0), /* scales with voltage */
-	PERIPH_CLK("csi",	"tegra_camera",		"csi",	52,	0,	72000000,  mux_pllp_out3,		0),
-	PERIPH_CLK("isp",	"tegra_camera",		"isp",	23,	0,	150000000, mux_clk_m,			0), /* same frequency as VI */
-	PERIPH_CLK("csus",	"tegra_camera",		"csus",	92,	0,	150000000, mux_clk_m,			PERIPH_NO_RESET),
+	PERIPH_CLK("la",	"la",			NULL,	76,	0x1f8,	0x31E,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("owr",	"tegra_w1",		NULL,	71,	0x1cc,	0x31E,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("nor",	"nor",			NULL,	42,	0x1d0,	0x31E,	92000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("mipi",	"mipi",			NULL,	50,	0x174,	0x31E,	60000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71), /* scales with voltage */
+	PERIPH_CLK("i2c1",	"tegra-i2c.0",		NULL,	12,	0x124,	0x31E,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
+	PERIPH_CLK("i2c2",	"tegra-i2c.1",		NULL,	54,	0x198,	0x31E,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
+	PERIPH_CLK("i2c3",	"tegra-i2c.2",		NULL,	67,	0x1b8,	0x31E,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
+	PERIPH_CLK("dvc",	"tegra-i2c.3",		NULL,	47,	0x128,	0x31E,	26000000,  mux_pllp_pllc_pllm_clkm,	MUX | DIV_U16),
+	PERIPH_CLK("i2c1_i2c",	"tegra-i2c.0",		"i2c",	0,	0,	0x31E,	72000000,  mux_pllp_out3,			0),
+	PERIPH_CLK("i2c2_i2c",	"tegra-i2c.1",		"i2c",	0,	0,	0x31E,	72000000,  mux_pllp_out3,			0),
+	PERIPH_CLK("i2c3_i2c",	"tegra-i2c.2",		"i2c",	0,	0,	0x31E,	72000000,  mux_pllp_out3,			0),
+	PERIPH_CLK("dvc_i2c",	"tegra-i2c.3",		"i2c",	0,	0,	0x31E,	72000000,  mux_pllp_out3,			0),
+	PERIPH_CLK("uarta",	"uart.0",		NULL,	6,	0x178,	0x31E,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
+	PERIPH_CLK("uartb",	"uart.1",		NULL,	7,	0x17c,	0x31E,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
+	PERIPH_CLK("uartc",	"uart.2",		NULL,	55,	0x1a0,	0x31E,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
+	PERIPH_CLK("uartd",	"uart.3",		NULL,	65,	0x1c0,	0x31E,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
+	PERIPH_CLK("uarte",	"uart.4",		NULL,	66,	0x1c4,	0x31E,	600000000, mux_pllp_pllc_pllm_clkm,	MUX),
+	PERIPH_CLK("3d",	"3d",			NULL,	24,	0x158,	0x31E,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
+	PERIPH_CLK("2d",	"2d",			NULL,	21,	0x15c,	0x31E,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("vi",	"tegra_camera",		"vi",	20,	0x148,	0x31E,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("vi_sensor",	"tegra_camera",		"vi_sensor",	20,	0x1a8,	0x31E,	150000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
+	PERIPH_CLK("epp",	"epp",			NULL,	19,	0x16c,	0x31E,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("mpe",	"mpe",			NULL,	60,	0x170,	0x31E,	300000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("host1x",	"host1x",		NULL,	28,	0x180,	0x31E,	166000000, mux_pllm_pllc_pllp_plla,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("cve",	"cve",			NULL,	49,	0x140,	0x31E,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("tvo",	"tvo",			NULL,	49,	0x188,	0x31E,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("hdmi",	"hdmi",			NULL,	51,	0x18c,	0x31E,	600000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("tvdac",	"tvdac",		NULL,	53,	0x194,	0x31E,	250000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* requires min voltage */
+	PERIPH_CLK("disp1",	"tegradc.0",		NULL,	27,	0x138,	0x31E,	600000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("disp2",	"tegradc.1",		NULL,	26,	0x13c,	0x31E,	600000000, mux_pllp_plld_pllc_clkm,	MUX | DIV_U71), /* scales with voltage and process_id */
+	PERIPH_CLK("usbd",	"fsl-tegra-udc",	NULL,	22,	0,	0x31E,	480000000, mux_clk_m,			0), /* requires min voltage */
+	PERIPH_CLK("usb2",	"tegra-ehci.1",		NULL,	58,	0,	0x31E,	480000000, mux_clk_m,			0), /* requires min voltage */
+	PERIPH_CLK("usb3",	"tegra-ehci.2",		NULL,	59,	0,	0x31E,	480000000, mux_clk_m,			0), /* requires min voltage */
+	PERIPH_CLK("dsi",	"dsi",			NULL,	48,	0,	0x31E,	500000000, mux_plld,			0), /* scales with voltage */
+	PERIPH_CLK("csi",	"tegra_camera",		"csi",	52,	0,	0x31E,	72000000,  mux_pllp_out3,		0),
+	PERIPH_CLK("isp",	"tegra_camera",		"isp",	23,	0,	0x31E,	150000000, mux_clk_m,			0), /* same frequency as VI */
+	PERIPH_CLK("csus",	"tegra_camera",		"csus",	92,	0,	0x31E,	150000000, mux_clk_m,			PERIPH_NO_RESET),
 
 	SHARED_CLK("avp.sclk",	"tegra-avp",		"sclk",	&tegra_clk_sclk),
 	SHARED_CLK("avp.emc",	"tegra-avp",		"emc",	&tegra_clk_emc),
@@ -2107,6 +2108,65 @@ struct clk *tegra_ptr_clks[] = {
 	&tegra_clk_emc,
 };
 
+/* For some clocks maximum rate limits depend on tegra2 SKU */
+#define RATE_LIMIT(_name, _max_rate, _skus...)	\
+	{					\
+		.clk_name 	= _name,	\
+		.max_rate 	= _max_rate,	\
+		.sku_ids	= {_skus}	\
+	}
+
+static struct tegra_sku_rate_limit sku_limits[] =
+{
+	RATE_LIMIT("cpu",	750000000, 0x07, 0x10),
+	RATE_LIMIT("cclk",	750000000, 0x07, 0x10),
+	RATE_LIMIT("pll_x",	750000000, 0x07, 0x10),
+
+	RATE_LIMIT("cpu",	1000000000, 0x04, 0x08, 0x0F),
+	RATE_LIMIT("cclk",	1000000000, 0x04, 0x08, 0x0F),
+	RATE_LIMIT("pll_x",	1000000000, 0x04, 0x08, 0x0F),
+
+	RATE_LIMIT("cpu",	1200000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
+	RATE_LIMIT("cclk",	1200000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
+	RATE_LIMIT("pll_x",	1200000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
+
+	RATE_LIMIT("sclk",	240000000, 0x04, 0x7, 0x08, 0x0F, 0x10),
+	RATE_LIMIT("hclk",	240000000, 0x04, 0x7, 0x08, 0x0F, 0x10),
+	RATE_LIMIT("avp.sclk",	240000000, 0x04, 0x7, 0x08, 0x0F, 0x10),
+	RATE_LIMIT("vde",	240000000, 0x04, 0x7, 0x08, 0x0F, 0x10),
+	RATE_LIMIT("3d",	300000000, 0x04, 0x7, 0x08, 0x0F, 0x10),
+
+	RATE_LIMIT("sclk",	300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
+	RATE_LIMIT("hclk",	300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
+	RATE_LIMIT("avp.sclk",	300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
+	RATE_LIMIT("vde",	300000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
+	RATE_LIMIT("3d",	400000000, 0x14, 0x17, 0x18, 0x1B, 0x1C),
+};
+
+static void tegra2_init_sku_limits(void)
+{
+	int i, j;
+	struct clk *c;
+	int sku_id = tegra_sku_id();
+
+	for (i = 0; i < ARRAY_SIZE(sku_limits); i++) {
+		struct tegra_sku_rate_limit *limit = &sku_limits[i];
+
+		for (j = 0; (j < MAX_SAME_LIMIT_SKU_IDS) &&
+		      (limit->sku_ids[j] != 0); j++) {
+			if (limit->sku_ids[j] == sku_id) {
+				c = tegra_get_clock_by_name(limit->clk_name);
+				if (!c) {
+					pr_err("%s: Unknown sku clock %s\n",
+					       __func__, limit->clk_name);
+					continue;
+				}
+				c->max_rate = limit->max_rate;
+			}
+		}
+	}
+}
+
 static void tegra2_init_one_clock(struct clk *c)
 {
 	clk_init(c);
@@ -2141,8 +2201,75 @@ void __init tegra2_init_clocks(void)
 	}
 
 	init_audio_sync_clock_mux();
+	tegra2_init_sku_limits();
 }
 
+#ifdef CONFIG_CPU_FREQ
+
+/*
+ * Frequency table index must be sequential starting at 0 and frequencies
+ * must be ascending.
+ */
+
+static struct cpufreq_frequency_table freq_table_750MHz[] = {
+	{ 0, 216000 },
+	{ 1, 312000 },
+	{ 2, 456000 },
+	{ 3, 608000 },
+	{ 4, 750000 },
+	{ 5, CPUFREQ_TABLE_END },
+};
+
+static struct cpufreq_frequency_table freq_table_1p0GHz[] = {
+	{ 0, 216000 },
+	{ 1, 312000 },
+	{ 2, 456000 },
+	{ 3, 608000 },
+	{ 4, 760000 },
+	{ 5, 816000 },
+	{ 6, 912000 },
+	{ 7, 1000000 },
+	{ 8, CPUFREQ_TABLE_END },
+};
+
+static struct cpufreq_frequency_table freq_table_1p2GHz[] = {
+	{ 0, 216000 },
+	{ 1, 312000 },
+	{ 2, 456000 },
+	{ 3, 608000 },
+	{ 4, 760000 },
+	{ 5, 816000 },
+	{ 6, 912000 },
+	{ 7, 1000000 },
+	{ 8, 1200000 },
+	{ 9, CPUFREQ_TABLE_END },
+};
+
+static struct tegra_cpufreq_table_data cpufreq_tables[] = {
+	{ freq_table_750MHz, 1, 4 },
+	{ freq_table_1p0GHz, 2, 6 },
+	{ freq_table_1p2GHz, 2, 7 },
+};
+
+struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void)
+{
+	int i, ret;
+	struct clk *cpu_clk = tegra_get_clock_by_name("cpu");
+
+	for (i = 0; i < ARRAY_SIZE(cpufreq_tables); i++) {
+		struct cpufreq_policy policy;
+		ret = cpufreq_frequency_table_cpuinfo(
+			&policy, cpufreq_tables[i].freq_table);
+		BUG_ON(ret);
+		if ((policy.max * 1000) == cpu_clk->max_rate)
+			return &cpufreq_tables[i];
+	}
+	pr_err("%s: No cpufreq table matching cpu range", __func__);
+	BUG();
+	return &cpufreq_tables[0];
+}
+#endif
+
 #ifdef CONFIG_PM
 static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
 			   PERIPH_CLK_SOURCE_NUM + 22];
diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c
index 9b5397414e03..61218af5b97f 100644
--- a/arch/arm/mach-tegra/tegra2_dvfs.c
+++ b/arch/arm/mach-tegra/tegra2_dvfs.c
@@ -38,33 +38,41 @@ static bool tegra_dvfs_cpu_disabled = true;
 #endif
 
 static const int core_millivolts[MAX_DVFS_FREQS] =
-	{950, 1000, 1100, 1200, 1275};
+	{950, 1000, 1100, 1200, 1225, 1275, 1300};
 static const int cpu_millivolts[MAX_DVFS_FREQS] =
-	{750, 775, 800, 825, 875,  900,  925,  975,  1000, 1050, 1100};
+	{750, 775, 800, 825, 850, 875, 900, 925, 950, 975, 1000, 1025, 1050, 1100, 1125};
+
+static const int cpu_speedo_nominal_millivolts[] =
+/* spedo_id  0,    1,    2 */
+	{ 1100, 1025, 1125 };
+
+static const int core_speedo_nominal_millivolts[] =
+/* spedo_id  0,    1,    2 */
+	{ 1225, 1225, 1300 };
 
 #define KHZ 1000
 #define MHZ 1000000
 
 static struct dvfs_rail tegra2_dvfs_rail_vdd_cpu = {
 	.reg_id = "vdd_cpu",
-	.max_millivolts = 1100,
+	.max_millivolts = 1125,
 	.min_millivolts = 750,
-	.nominal_millivolts = 1100,
+	.nominal_millivolts = 1125,
 };
 
 static struct dvfs_rail tegra2_dvfs_rail_vdd_core = {
 	.reg_id = "vdd_core",
-	.max_millivolts = 1275,
+	.max_millivolts = 1300,
 	.min_millivolts = 950,
-	.nominal_millivolts = 1200,
+	.nominal_millivolts = 1225,
 	.step = 150, /* step vdd_core by 150 mV to allow vdd_aon to follow */
 };
 
 static struct dvfs_rail tegra2_dvfs_rail_vdd_aon = {
 	.reg_id = "vdd_aon",
-	.max_millivolts = 1275,
+	.max_millivolts = 1300,
 	.min_millivolts = 950,
-	.nominal_millivolts = 1200,
+	.nominal_millivolts = 1225,
 #ifndef CONFIG_TEGRA_CORE_DVFS
 	.disabled = true,
 #endif
@@ -120,10 +128,11 @@ static struct dvfs_rail *tegra2_dvfs_rails[] = {
 	&tegra2_dvfs_rail_vdd_aon,
 };
 
-#define CPU_DVFS(_clk_name, _process_id, _mult, _freqs...)	\
+#define CPU_DVFS(_clk_name, _speedo_id, _process_id, _mult, _freqs...)	\
 	{							\
 		.clk_name	= _clk_name,			\
-		.cpu_process_id	= _process_id,			\
+		.speedo_id	= _speedo_id,			\
+		.process_id	= _process_id,			\
 		.freqs		= {_freqs},			\
 		.freqs_mult	= _mult,			\
 		.millivolts	= cpu_millivolts,		\
@@ -131,10 +140,11 @@ static struct dvfs_rail *tegra2_dvfs_rails[] = {
 		.dvfs_rail	= &tegra2_dvfs_rail_vdd_cpu,	\
 	}
 
-#define CORE_DVFS(_clk_name, _auto, _mult, _freqs...)		\
+#define CORE_DVFS(_clk_name, _process_id, _auto, _mult, _freqs...)	\
 	{							\
 		.clk_name	= _clk_name,			\
-		.cpu_process_id = -1,				\
+		.speedo_id	= -1,				\
+		.process_id	= _process_id,				\
 		.freqs		= {_freqs},			\
 		.freqs_mult	= _mult,			\
 		.millivolts	= core_millivolts,		\
@@ -143,14 +153,24 @@ static struct dvfs_rail *tegra2_dvfs_rails[] = {
 	}
 
 static struct dvfs dvfs_init[] = {
-	/* Cpu voltages (mV):   750, 775, 800, 825, 875, 900, 925, 975, 1000, 1050, 1100 */
-	CPU_DVFS("cpu", 0, MHZ, 314, 314, 314, 456, 456, 608, 608, 760, 817,  912,  1000),
-	CPU_DVFS("cpu", 1, MHZ, 314, 314, 314, 456, 456, 618, 618, 770, 827,  922,  1000),
-	CPU_DVFS("cpu", 2, MHZ, 494, 675, 675, 675, 817, 817, 922, 1000),
-	CPU_DVFS("cpu", 3, MHZ, 730, 760, 845, 845, 1000),
+	/* Cpu voltages (mV):	   750, 775, 800, 825, 850, 875,  900,  925,  950,  975,  1000, 1025, 1050, 1100, 1125 */
+	CPU_DVFS("cpu", 0, 0, MHZ, 314, 314, 314, 456, 456, 456,  608,  608,  608,  760,  817,  817,  912,  1000),
+	CPU_DVFS("cpu", 0, 1, MHZ, 314, 314, 314, 456, 456, 456,  618,  618,  618,  770,  827,  827,  922,  1000),
+	CPU_DVFS("cpu", 0, 2, MHZ, 494, 494, 494, 675, 675, 817,  817,  922,  922,  1000),
+	CPU_DVFS("cpu", 0, 3, MHZ, 730, 760, 845, 845, 940, 1000),
+
+	CPU_DVFS("cpu", 1, 0, MHZ, 380, 380, 503, 503, 655, 655,  798,  798,  902,  902,  960,  1000),
+	CPU_DVFS("cpu", 1, 1, MHZ, 389, 389, 503, 503, 655, 760,  798,  798,  950,  950,  1000),
+	CPU_DVFS("cpu", 1, 2, MHZ, 598, 598, 750, 750, 893, 893,  1000),
+	CPU_DVFS("cpu", 1, 3, MHZ, 730, 760, 845, 845, 940, 1000),
 
-	/* Core voltages (mV):       950,    1000,   1100,   1200,   1275 */
-	CORE_DVFS("emc",     1, KHZ, 57000,  333000, 333000, 666000, 666000),
+	CPU_DVFS("cpu", 2, 0, MHZ,   0,   0,   0,   0, 655, 655,  798,  798,  902,  902,  960,  1000, 1100, 1100, 1200),
+	CPU_DVFS("cpu", 2, 1, MHZ,   0,   0,   0,   0, 655, 760,  798,  798,  950,  950,  1015, 1015, 1100, 1200),
+	CPU_DVFS("cpu", 2, 2, MHZ,   0,   0,   0,   0, 769, 769,  902,  902,  1026, 1026, 1140, 1140, 1200),
+	CPU_DVFS("cpu", 2, 3, MHZ,   0,   0,   0,   0, 940, 1000, 1000, 1000, 1130, 1130, 1200),
+
+	/* Core voltages (mV):           950,    1000,   1100,   1200,   1225,   1275,   1300 */
+	CORE_DVFS("emc",     -1, 1, KHZ, 57000,  333000, 380000, 666000, 666000, 666000, 760000),
 
 #if 0
 	/*
@@ -159,22 +179,22 @@ static struct dvfs dvfs_init[] = {
 	 * For now, boards must ensure that the core voltage does not drop
 	 * below 1V, or that the sdmmc busses are set to 44 MHz or less.
 	 */
-	CORE_DVFS("sdmmc1",  1, KHZ, 44000,  52000,  52000,  52000,  52000),
-	CORE_DVFS("sdmmc2",  1, KHZ, 44000,  52000,  52000,  52000,  52000),
-	CORE_DVFS("sdmmc3",  1, KHZ, 44000,  52000,  52000,  52000,  52000),
-	CORE_DVFS("sdmmc4",  1, KHZ, 44000,  52000,  52000,  52000,  52000),
+	CORE_DVFS("sdmmc1",  -1, 1, KHZ, 44000,  52000,  52000,  52000,  52000,  52000,  52000),
+	CORE_DVFS("sdmmc2",  -1, 1, KHZ, 44000,  52000,  52000,  52000,  52000,  52000,  52000),
+	CORE_DVFS("sdmmc3",  -1, 1, KHZ, 44000,  52000,  52000,  52000,  52000,  52000,  52000),
+	CORE_DVFS("sdmmc4",  -1, 1, KHZ, 44000,  52000,  52000,  52000,  52000,  52000,  52000),
 #endif
 
-	CORE_DVFS("ndflash", 1, KHZ, 130000, 150000, 158000, 164000, 164000),
-	CORE_DVFS("nor",     1, KHZ, 0,      92000,  92000,  92000,  92000),
-	CORE_DVFS("ide",     1, KHZ, 0,      0,      100000, 100000, 100000),
-	CORE_DVFS("mipi",    1, KHZ, 0,      40000,  40000,  40000, 60000),
-	CORE_DVFS("usbd",    1, KHZ, 0,      0,      0,      480000, 480000),
-	CORE_DVFS("usb2",    1, KHZ, 0,      0,      0,      480000, 480000),
-	CORE_DVFS("usb3",    1, KHZ, 0,      0,      0,      480000, 480000),
-	CORE_DVFS("pcie",    1, KHZ, 0,      0,      0,      250000, 250000),
-	CORE_DVFS("dsi",     1, KHZ, 100000, 100000, 100000, 500000, 500000),
-	CORE_DVFS("tvo",     1, KHZ, 0,      0,      0,      250000, 250000),
+	CORE_DVFS("ndflash", -1, 1, KHZ, 130000, 150000, 158000, 164000, 164000, 164000, 164000),
+	CORE_DVFS("nor",     -1, 1, KHZ, 0,      92000,  92000,  92000,  92000,  92000,  92000),
+	CORE_DVFS("ide",     -1, 1, KHZ, 0,      0,      100000, 100000, 100000, 100000, 100000),
+	CORE_DVFS("mipi",    -1, 1, KHZ, 0,      40000,  40000,  40000,  40000,  60000,  60000),
+	CORE_DVFS("usbd",    -1, 1, KHZ, 0,      0,      480000, 480000, 480000, 480000, 480000),
+	CORE_DVFS("usb2",    -1, 1, KHZ, 0,      0,      480000, 480000, 480000, 480000, 480000),
+	CORE_DVFS("usb3",    -1, 1, KHZ, 0,      0,      480000, 480000, 480000, 480000, 480000),
+	CORE_DVFS("pcie",    -1, 1, KHZ, 0,      0,      0,      250000, 250000, 250000, 250000),
+	CORE_DVFS("dsi",     -1, 1, KHZ, 100000, 100000, 100000, 500000, 500000, 500000, 500000),
+	CORE_DVFS("tvo",     -1, 1, KHZ, 0,      0,      0,      250000, 250000, 250000, 250000),
 
 	/*
 	 * The clock rate for the display controllers that determines the
@@ -182,24 +202,43 @@ static struct dvfs dvfs_init[] = {
 	 * to the display block.  Disable auto-dvfs on the display clocks,
 	 * and let the display driver call tegra_dvfs_set_rate manually
 	 */
-	CORE_DVFS("disp1",   0, KHZ, 158000, 158000, 190000, 190000, 190000),
-	CORE_DVFS("disp2",   0, KHZ, 158000, 158000, 190000, 190000, 190000),
-	CORE_DVFS("hdmi",    0, KHZ, 0,      0,      0,      148500, 148500),
+	CORE_DVFS("disp1",   -1, 0, KHZ, 158000, 158000, 190000, 190000, 190000, 190000, 190000),
+	CORE_DVFS("disp2",   -1, 0, KHZ, 158000, 158000, 190000, 190000, 190000, 190000, 190000),
+	CORE_DVFS("hdmi",    -1, 0, KHZ, 0,      0,      0,      148500, 148500, 148500, 148500),
 
 	/*
-	 * These clocks technically depend on the core process id,
-	 * but just use the worst case value for now
+	 * Clocks below depend on the core process id. Define per process_id
+	 * tables for SCLK/VDE/3D clocks (maximum rate for these clocks is
+	 * increased depending on tegra2 sku). Use the worst case value for
+	 * other clocks for now.
 	 */
-	CORE_DVFS("host1x",  1, KHZ, 104500, 133000, 166000, 166000, 166000),
-	CORE_DVFS("epp",     1, KHZ, 133000, 171000, 247000, 300000, 300000),
-	CORE_DVFS("2d",      1, KHZ, 133000, 171000, 247000, 300000, 300000),
-	CORE_DVFS("3d",      1, KHZ, 114000, 161500, 247000, 300000, 300000),
-	CORE_DVFS("mpe",     1, KHZ, 104500, 152000, 228000, 250000, 250000),
-	CORE_DVFS("vi",      1, KHZ, 85000,  100000, 150000, 150000, 150000),
-	CORE_DVFS("sclk",    1, KHZ, 95000,  133000, 190000, 250000, 250000),
-	CORE_DVFS("vde",     1, KHZ, 95000,  123500, 209000, 250000, 250000),
+	CORE_DVFS("host1x",  -1, 1, KHZ, 104500, 133000, 166000, 166000, 166000, 166000, 166000),
+	CORE_DVFS("epp",     -1, 1, KHZ, 133000, 171000, 247000, 300000, 300000, 300000, 300000),
+	CORE_DVFS("2d",      -1, 1, KHZ, 133000, 171000, 247000, 300000, 300000, 300000, 300000),
+
+	CORE_DVFS("3d",       0, 1, KHZ, 114000, 161500, 247000, 304000, 304000, 333500, 333500),
+	CORE_DVFS("3d",       1, 1, KHZ, 161500, 209000, 285000, 333500, 333500, 361000, 361000),
+	CORE_DVFS("3d",       2, 1, KHZ, 218500, 256500, 323000, 380000, 380000, 400000, 400000),
+	CORE_DVFS("3d",       3, 1, KHZ, 247000, 285000, 351500, 400000, 400000, 400000, 400000),
+
+	CORE_DVFS("mpe",      0, 1, KHZ, 104500, 152000, 228000, 300000, 300000, 300000, 300000),
+	CORE_DVFS("mpe",      1, 1, KHZ, 142500, 190000, 275500, 300000, 300000, 300000, 300000),
+	CORE_DVFS("mpe",      2, 1, KHZ, 190000, 237500, 300000, 300000, 300000, 300000, 300000),
+	CORE_DVFS("mpe",      3, 1, KHZ, 228000, 266000, 300000, 300000, 300000, 300000, 300000),
+
+	CORE_DVFS("vi",      -1, 1, KHZ, 85000,  100000, 150000, 150000, 150000, 150000, 150000),
+
+	CORE_DVFS("sclk",     0, 1, KHZ, 95000,  133000, 190000, 222500, 240000, 247000, 262000),
+	CORE_DVFS("sclk",     1, 1, KHZ, 123500, 159500, 207000, 240000, 240000, 264000, 277500),
+	CORE_DVFS("sclk",     2, 1, KHZ, 152000, 180500, 229500, 260000, 260000, 285000, 300000),
+	CORE_DVFS("sclk",     3, 1, KHZ, 171000, 218500, 256500, 292500, 292500, 300000, 300000),
+
+	CORE_DVFS("vde",      0, 1, KHZ, 95000,  123500, 209000, 275500, 275500, 300000, 300000),
+	CORE_DVFS("vde",      1, 1, KHZ, 123500, 152000, 237500, 300000, 300000, 300000, 300000),
+	CORE_DVFS("vde",      2, 1, KHZ, 152000, 209000, 285000, 300000, 300000, 300000, 300000),
+	CORE_DVFS("vde",      3, 1, KHZ, 171000, 218500, 300000, 300000, 300000, 300000, 300000),
 	/* What is this? */
-	CORE_DVFS("NVRM_DEVID_CLK_SRC", 1, MHZ, 480, 600, 800, 1067, 1067),
+	CORE_DVFS("NVRM_DEVID_CLK_SRC", -1, 1, MHZ, 480, 600, 800, 1067, 1067, 1067, 1067),
 };
 
 int tegra_dvfs_disable_core_set(const char *arg, const struct kernel_param *kp)
@@ -259,8 +298,20 @@ void __init tegra2_init_dvfs(void)
 	int i;
 	struct clk *c;
 	struct dvfs *d;
+	int process_id;
 	int ret;
 	int cpu_process_id = tegra_cpu_process_id();
+	int core_process_id = tegra_core_process_id();
+	int speedo_id = tegra_soc_speedo_id();
+
+	BUG_ON(speedo_id >= ARRAY_SIZE(cpu_speedo_nominal_millivolts));
+	tegra2_dvfs_rail_vdd_cpu.nominal_millivolts =
+		cpu_speedo_nominal_millivolts[speedo_id];
+	BUG_ON(speedo_id >= ARRAY_SIZE(core_speedo_nominal_millivolts));
+	tegra2_dvfs_rail_vdd_core.nominal_millivolts =
+		core_speedo_nominal_millivolts[speedo_id];
+	tegra2_dvfs_rail_vdd_aon.nominal_millivolts =
+		core_speedo_nominal_millivolts[speedo_id];
 
 	tegra_dvfs_init_rails(tegra2_dvfs_rails, ARRAY_SIZE(tegra2_dvfs_rails));
 	tegra_dvfs_add_relationships(tegra2_dvfs_relationships,
@@ -272,9 +323,15 @@ void __init tegra2_init_dvfs(void)
 	for (i = 0; i < ARRAY_SIZE(dvfs_init); i++) {
 		d = &dvfs_init[i];
 
-		if (d->cpu_process_id != -1 &&
-				d->cpu_process_id != cpu_process_id)
+		process_id = strcmp(d->clk_name, "cpu") ?
+			core_process_id : cpu_process_id;
+		if ((d->process_id != -1 && d->process_id != process_id) ||
+		    (d->speedo_id != -1 && d->speedo_id != speedo_id)) {
+			pr_debug("tegra_dvfs: rejected %s speedo %d,"
+				" process %d\n", d->clk_name, d->speedo_id,
+				d->process_id);
 			continue;
+		}
 
 		c = tegra_get_clock_by_name(d->clk_name);
 
diff --git a/arch/arm/mach-tegra/tegra2_i2s.c b/arch/arm/mach-tegra/tegra2_i2s.c
new file mode 100644
index 000000000000..de50df917048
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra2_i2s.c
@@ -0,0 +1,492 @@
+/*
+ * arch/arm/mach-tegra/tegra2_i2s.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *      Iliyan Malchev <malchev@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+
+#include "clock.h"
+#include <asm/io.h>
+#include <mach/iomap.h>
+#include <mach/tegra2_i2s.h>
+
+
+#define NR_I2S_IFC	2
+
+#define check_ifc(n, ...) if ((n) > NR_I2S_IFC) {			\
+	pr_err("%s: invalid i2s interface %d\n", __func__, (n));	\
+	return __VA_ARGS__;						\
+}
+
+static phys_addr_t i2s_phy_base[NR_I2S_IFC] = {
+	TEGRA_I2S1_BASE,
+	TEGRA_I2S2_BASE,
+};
+
+static void *i2s_base[NR_I2S_IFC] = {
+	IO_ADDRESS(TEGRA_I2S1_BASE),
+	IO_ADDRESS(TEGRA_I2S2_BASE),
+};
+
+static inline void i2s_writel(int ifc, u32 val, u32 reg)
+{
+	__raw_writel(val, i2s_base[ifc] + reg);
+}
+
+static inline u32 i2s_readl(int ifc, u32 reg)
+{
+	return __raw_readl(i2s_base[ifc] + reg);
+}
+
+void i2s_dump_registers(int ifc)
+{
+	check_ifc(ifc);
+
+	pr_info("%s: CTRL   %08x\n", __func__,
+			i2s_readl(ifc, I2S_I2S_CTRL_0));
+	pr_info("%s: STATUS %08x\n", __func__,
+			i2s_readl(ifc, I2S_I2S_STATUS_0));
+	pr_info("%s: TIMING %08x\n", __func__,
+			i2s_readl(ifc, I2S_I2S_TIMING_0));
+	pr_info("%s: SCR    %08x\n", __func__,
+			i2s_readl(ifc, I2S_I2S_FIFO_SCR_0));
+	pr_info("%s: FIFO1  %08x\n", __func__,
+			i2s_readl(ifc, I2S_I2S_FIFO1_0));
+	pr_info("%s: FIFO2  %08x\n", __func__,
+			i2s_readl(ifc, I2S_I2S_FIFO1_0));
+}
+
+void i2s_get_all_regs(int ifc, struct i2s_runtime_data* ird)
+{
+	check_ifc(ifc);
+	ird->i2s_ctrl_0 = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	ird->i2s_status_0 = i2s_readl(ifc, I2S_I2S_STATUS_0);
+	ird->i2s_timing_0 = i2s_readl(ifc, I2S_I2S_TIMING_0);
+	ird->i2s__fifo_scr_0 = i2s_readl(ifc, I2S_I2S_FIFO_SCR_0);
+	ird->i2s_fifo1_0 = i2s_readl(ifc, I2S_I2S_FIFO1_0);
+	ird->i2s_fifo2_0 = i2s_readl(ifc, I2S_I2S_FIFO2_0);
+}
+
+void i2s_set_all_regs(int ifc, struct i2s_runtime_data* ird)
+{
+	check_ifc(ifc);
+	i2s_writel(ifc, ird->i2s_ctrl_0, I2S_I2S_CTRL_0);
+	i2s_writel(ifc, ird->i2s_status_0, I2S_I2S_STATUS_0);
+	i2s_writel(ifc, ird->i2s_timing_0, I2S_I2S_TIMING_0);
+	i2s_writel(ifc, ird->i2s__fifo_scr_0, I2S_I2S_FIFO_SCR_0);
+	i2s_writel(ifc, ird->i2s_fifo1_0, I2S_I2S_FIFO1_0);
+	i2s_writel(ifc, ird->i2s_fifo2_0, I2S_I2S_FIFO2_0);
+}
+
+int i2s_set_channel_bit_count(int ifc, int sampling, int bitclk)
+{
+	u32 val;
+	int bitcnt;
+
+	check_ifc(ifc, -EINVAL);
+
+	bitcnt = bitclk / (2 * sampling) - 1;
+
+	if (bitcnt < 0 || bitcnt >= 1<<11) {
+		pr_err("%s: bit count %d is out of bounds\n", __func__,
+			bitcnt);
+		return -EINVAL;
+	}
+
+	val = bitcnt;
+	if (bitclk % (2 * sampling)) {
+		pr_info("%s: enabling non-symmetric mode\n", __func__);
+		val |= I2S_I2S_TIMING_NON_SYM_ENABLE;
+	}
+
+	i2s_writel(ifc, val, I2S_I2S_TIMING_0);
+	return 0;
+}
+
+void i2s_set_fifo_mode(int ifc, int fifo, int tx)
+{
+	u32 val;
+
+	check_ifc(ifc);
+
+	val = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	if (fifo == 0) {
+		val &= ~I2S_I2S_CTRL_FIFO1_RX_ENABLE;
+		val |= (!tx) ? I2S_I2S_CTRL_FIFO1_RX_ENABLE : 0;
+	}
+	else {
+		val &= ~I2S_I2S_CTRL_FIFO2_TX_ENABLE;
+		val |= tx ? I2S_I2S_CTRL_FIFO2_TX_ENABLE : 0;
+	}
+	i2s_writel(ifc, val, I2S_I2S_CTRL_0);
+}
+
+void i2s_set_loopback(int ifc, int on)
+{
+	u32 val;
+
+	check_ifc(ifc);
+
+	val = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	val &= ~I2S_I2S_CTRL_FIFO_LPBK_ENABLE;
+	val |= on ? I2S_I2S_CTRL_FIFO_LPBK_ENABLE : 0;
+
+	i2s_writel(ifc, val, I2S_I2S_CTRL_0);
+}
+
+int i2s_fifo_set_attention_level(int ifc, int fifo, unsigned level)
+{
+	u32 val;
+
+	check_ifc(ifc, -EINVAL);
+
+	if (level > I2S_FIFO_ATN_LVL_TWELVE_SLOTS) {
+		pr_err("%s: invalid fifo level selector %d\n", __func__,
+			level);
+		return -EINVAL;
+	}
+
+	val = i2s_readl(ifc, I2S_I2S_FIFO_SCR_0);
+
+	if (!fifo) {
+		val &= ~I2S_I2S_FIFO_SCR_FIFO1_ATN_LVL_MASK;
+		val |= level << I2S_FIFO1_ATN_LVL_SHIFT;
+	}
+	else {
+		val &= ~I2S_I2S_FIFO_SCR_FIFO2_ATN_LVL_MASK;
+		val |= level << I2S_FIFO2_ATN_LVL_SHIFT;
+	}
+
+	i2s_writel(ifc, val, I2S_I2S_FIFO_SCR_0);
+	return 0;
+}
+
+void i2s_fifo_enable(int ifc, int fifo, int on)
+{
+	u32 val;
+
+	check_ifc(ifc);
+
+	val = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	if (!fifo) {
+		val &= ~I2S_I2S_CTRL_FIFO1_ENABLE;
+		val |= on ? I2S_I2S_CTRL_FIFO1_ENABLE : 0;
+	}
+	else {
+		val &= ~I2S_I2S_CTRL_FIFO2_ENABLE;
+		val |= on ? I2S_I2S_CTRL_FIFO2_ENABLE : 0;
+	}
+
+	i2s_writel(ifc, val, I2S_I2S_CTRL_0);
+}
+
+void i2s_fifo_clear(int ifc, int fifo)
+{
+	u32 val;
+
+	check_ifc(ifc);
+
+	val = i2s_readl(ifc, I2S_I2S_FIFO_SCR_0);
+	if (!fifo) {
+		val &= ~I2S_I2S_FIFO_SCR_FIFO1_CLR;
+		val |= I2S_I2S_FIFO_SCR_FIFO1_CLR;
+	}
+	else {
+		val &= ~I2S_I2S_FIFO_SCR_FIFO2_CLR;
+		val |= I2S_I2S_FIFO_SCR_FIFO2_CLR;
+	}
+
+	i2s_writel(ifc, val, I2S_I2S_FIFO_SCR_0);
+}
+
+void i2s_set_master(int ifc, int master)
+{
+	u32 val;
+	check_ifc(ifc);
+	val = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	val &= ~I2S_I2S_CTRL_MASTER_ENABLE;
+	val |= master ? I2S_I2S_CTRL_MASTER_ENABLE : 0;
+	i2s_writel(ifc, val, I2S_I2S_CTRL_0);
+}
+
+int i2s_set_bit_format(int ifc, unsigned fmt)
+{
+	u32 val;
+
+	check_ifc(ifc, -EINVAL);
+
+	if (fmt > I2S_BIT_FORMAT_DSP) {
+		pr_err("%s: invalid bit-format selector %d\n", __func__, fmt);
+		return -EINVAL;
+	}
+
+	val = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	val &= ~I2S_I2S_CTRL_BIT_FORMAT_MASK;
+	val |= fmt << I2S_BIT_FORMAT_SHIFT;
+
+	i2s_writel(ifc, val, I2S_I2S_CTRL_0);
+
+	if (fmt == I2S_BIT_FORMAT_DSP) {
+		i2s_enable_pcm_mode(ifc, 1);
+	}
+	else {
+		i2s_enable_pcm_mode(ifc, 0);
+	}
+	return 0;
+}
+
+int i2s_set_bit_size(int ifc, unsigned bit_size)
+{
+	u32 val;
+
+	check_ifc(ifc, -EINVAL);
+
+	val = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	val &= ~I2S_I2S_CTRL_BIT_SIZE_MASK;
+
+	if (bit_size > I2S_BIT_SIZE_32) {
+		pr_err("%s: invalid bit_size selector %d\n", __func__,
+			bit_size);
+		return -EINVAL;
+	}
+
+	val |= bit_size << I2S_BIT_SIZE_SHIFT;
+
+	i2s_writel(ifc, val, I2S_I2S_CTRL_0);
+	return 0;
+}
+
+int i2s_set_fifo_format(int ifc, unsigned fmt)
+{
+	u32 val;
+
+	check_ifc(ifc, -EINVAL);
+
+	val = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	val &= ~I2S_I2S_CTRL_FIFO_FORMAT_MASK;
+
+	if (fmt > I2S_FIFO_32 && fmt != I2S_FIFO_PACKED) {
+		pr_err("%s: invalid fmt selector %d\n", __func__, fmt);
+		return -EINVAL;
+	}
+
+	val |= fmt << I2S_FIFO_SHIFT;
+
+	i2s_writel(ifc, val, I2S_I2S_CTRL_0);
+	return 0;
+}
+
+void i2s_set_left_right_control_polarity(int ifc, int high_low)
+{
+	u32 val;
+
+	check_ifc(ifc);
+
+	val = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	val &= ~I2S_I2S_CTRL_L_R_CTRL;
+	val |= high_low ? I2S_I2S_CTRL_L_R_CTRL : 0;
+	i2s_writel(ifc, val, I2S_I2S_CTRL_0);
+}
+
+void i2s_enable_pcm_mode(int ifc, int on)
+{
+	u32 val;
+
+	check_ifc(ifc);
+
+	val = i2s_readl(ifc, I2S_I2S_PCM_CTRL_0);
+	val &= ~(I2S_I2S_PCM_CTRL_TRM_MODE | I2S_I2S_PCM_CTRL_RCV_MODE);
+	val |= on ? (I2S_I2S_PCM_CTRL_TRM_MODE | I2S_I2S_PCM_CTRL_RCV_MODE) : 0;
+	i2s_writel(ifc, val, I2S_I2S_PCM_CTRL_0);
+}
+
+int i2s_set_pcm_edge_mode(int ifc, unsigned edge_mode)
+{
+	u32 val;
+
+	check_ifc(ifc, -EINVAL);
+
+	if (edge_mode > I2S_I2S_PCM_TRM_EDGE_NEG_EDGE_HIGHZ) {
+		pr_err("%s: invalid dsp edge mode \n", __func__);
+		return -EINVAL;
+	}
+
+	val = i2s_readl(ifc, I2S_I2S_PCM_CTRL_0);
+	val &= ~I2S_I2S_PCM_TRM_EDGE_CTRL_MASK;
+	val |= edge_mode << I2S_PCM_TRM_EDGE_CTRL_SHIFT;
+
+	i2s_writel(ifc, val, I2S_I2S_PCM_CTRL_0);
+	return 0;
+}
+
+int i2s_set_pcm_mask_bits(int ifc, unsigned mask_bits, int tx)
+{
+	u32 val;
+
+	check_ifc(ifc, -EINVAL);
+
+	val = i2s_readl(ifc, I2S_I2S_PCM_CTRL_0);
+	if (tx) {
+		if (mask_bits > I2S_I2S_PCM_TRM_MASK_BITS_SEVEN) {
+			pr_err("%s: invalid dsp mask bits \n", __func__);
+			return -EINVAL;
+		}
+		val &= ~I2S_I2S_PCM_TRM_MASK_BITS_MASK;
+		val |= mask_bits << I2S_PCM_TRM_MASK_BITS_SHIFT;
+	}
+	else {
+		if (mask_bits > I2S_I2S_PCM_RCV_MASK_BITS_SEVEN) {
+			pr_err("%s: invalid dsp mask bits \n", __func__);
+			return -EINVAL;
+		}
+		val &= ~I2S_I2S_PCM_RCV_MASK_BITS_MASK;
+		val |= mask_bits << I2S_PCM_RCV_MASK_BITS_SHIFT;
+	}
+	i2s_writel(ifc, val, I2S_I2S_PCM_CTRL_0);
+	return 0;
+}
+
+void i2s_set_pcm_fsync_width(int ifc, int fsync_long)
+{
+	u32 val;
+
+	check_ifc(ifc);
+
+	val = i2s_readl(ifc, I2S_I2S_PCM_CTRL_0);
+	val &= ~I2S_I2S_PCM_CTRL_FSYNC_PCM_CTRL;
+	val |= fsync_long ? I2S_I2S_PCM_CTRL_FSYNC_PCM_CTRL : 0;
+
+	i2s_writel(ifc, val, I2S_I2S_PCM_CTRL_0);
+}
+
+void i2s_set_fifo_irq_on_err(int ifc, int fifo, int on)
+{
+	u32 val;
+
+	check_ifc(ifc);
+
+	val = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	if (!fifo) {
+		val &= ~I2S_I2S_IE_FIFO1_ERR;
+		val |= on ? I2S_I2S_IE_FIFO1_ERR : 0;
+	}
+	else {
+		val &= ~I2S_I2S_IE_FIFO2_ERR;
+		val |= on ? I2S_I2S_IE_FIFO2_ERR : 0;
+	}
+	i2s_writel(ifc, val, I2S_I2S_CTRL_0);
+}
+
+void i2s_set_fifo_irq_on_qe(int ifc, int fifo, int on)
+{
+	u32 val;
+
+	check_ifc(ifc);
+
+	val = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	if (!fifo) {
+		val &= ~I2S_I2S_QE_FIFO1;
+		val |= on ? I2S_I2S_QE_FIFO1 : 0;
+	}
+	else {
+		val &= ~I2S_I2S_QE_FIFO2;
+		val |= on ? I2S_I2S_QE_FIFO2 : 0;
+	}
+	i2s_writel(ifc, val, I2S_I2S_CTRL_0);
+}
+
+void i2s_enable_fifos(int ifc, int on)
+{
+	u32 val;
+
+	check_ifc(ifc);
+
+	val = i2s_readl(ifc, I2S_I2S_CTRL_0);
+	if (on)
+		val |= I2S_I2S_QE_FIFO1 | I2S_I2S_QE_FIFO2 |
+		       I2S_I2S_IE_FIFO1_ERR | I2S_I2S_IE_FIFO2_ERR;
+	else
+		val &= ~(I2S_I2S_QE_FIFO1 | I2S_I2S_QE_FIFO2 |
+			 I2S_I2S_IE_FIFO1_ERR | I2S_I2S_IE_FIFO2_ERR);
+
+	i2s_writel(ifc, val, I2S_I2S_CTRL_0);
+}
+
+void i2s_fifo_write(int ifc, int fifo, u32 data)
+{
+	check_ifc(ifc);
+	i2s_writel(ifc, data, fifo ? I2S_I2S_FIFO2_0 : I2S_I2S_FIFO1_0);
+}
+
+u32 i2s_fifo_read(int ifc, int fifo)
+{
+	check_ifc(ifc, 0);
+	return i2s_readl(ifc, fifo ? I2S_I2S_FIFO2_0 : I2S_I2S_FIFO1_0);
+}
+
+u32 i2s_get_status(int ifc)
+{
+	check_ifc(ifc, 0);
+	return i2s_readl(ifc, I2S_I2S_STATUS_0);
+}
+
+u32 i2s_get_control(int ifc)
+{
+	check_ifc(ifc, 0);
+	return i2s_readl(ifc, I2S_I2S_CTRL_0);
+}
+
+void i2s_ack_status(int ifc)
+{
+	check_ifc(ifc);
+	return i2s_writel(ifc, i2s_readl(ifc, I2S_I2S_STATUS_0), I2S_I2S_STATUS_0);
+}
+
+u32 i2s_get_fifo_scr(int ifc)
+{
+	check_ifc(ifc, 0);
+	return i2s_readl(ifc, I2S_I2S_FIFO_SCR_0);
+}
+
+phys_addr_t i2s_get_fifo_phy_base(int ifc, int fifo)
+{
+	check_ifc(ifc, 0);
+	return i2s_phy_base[ifc] + (fifo ? I2S_I2S_FIFO2_0 : I2S_I2S_FIFO1_0);
+}
+
+u32 i2s_get_fifo_full_empty_count(int ifc, int fifo)
+{
+	u32 val;
+
+	check_ifc(ifc, 0);
+
+	val = i2s_readl(ifc, I2S_I2S_FIFO_SCR_0);
+
+	if (!fifo)
+		val = val >> I2S_I2S_FIFO_SCR_FIFO1_FULL_EMPTY_COUNT_SHIFT;
+	else
+		val = val >> I2S_I2S_FIFO_SCR_FIFO2_FULL_EMPTY_COUNT_SHIFT;
+
+	return val & I2S_I2S_FIFO_SCR_FIFO_FULL_EMPTY_COUNT_MASK;
+}
+
+
+struct clk *i2s_get_clock_by_name(const char *name)
+{
+    return tegra_get_clock_by_name(name);
+}
diff --git a/arch/arm/mach-tegra/tegra2_speedo.c b/arch/arm/mach-tegra/tegra2_speedo.c
new file mode 100644
index 000000000000..1e5fa26a5c41
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra2_speedo.c
@@ -0,0 +1,140 @@
+/*
+ * arch/arm/mach-tegra/tegra2_speedo.c
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/err.h>
+
+#include <mach/iomap.h>
+
+#include "fuse.h"
+
+#define CPU_SPEEDO_LSBIT		20
+#define CPU_SPEEDO_MSBIT		29
+#define CPU_SPEEDO_REDUND_LSBIT		30
+#define CPU_SPEEDO_REDUND_MSBIT		39
+#define CPU_SPEEDO_REDUND_OFFS	(CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
+
+#define CORE_SPEEDO_LSBIT		40
+#define CORE_SPEEDO_MSBIT		47
+#define CORE_SPEEDO_REDUND_LSBIT	48
+#define CORE_SPEEDO_REDUND_MSBIT	55
+#define CORE_SPEEDO_REDUND_OFFS	(CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT)
+
+#define SPEEDO_MULT			4
+
+#define CHIP_ID				0x804
+#define CHIP_MINOR_SHIFT		16
+#define CHIP_MINOR_MASK			(0xF <<	CHIP_MINOR_SHIFT)
+
+#define PROCESS_CORNERS_NUM		4
+
+#define SPEEDO_ID_SELECT_0(rev)		((rev) <= 2)
+#define SPEEDO_ID_SELECT_1(sku)		\
+	(((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
+	 ((sku) != 27) && ((sku) != 28))
+
+/* Maximum speedo levels for each CPU process corner */
+static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
+/* proc_id 0	1    2	       3		  */
+	{315, 366, 420, UINT_MAX}, /* speedo_id 0 */
+	{303, 368, 419, UINT_MAX}, /* speedo_id 1 */
+	{316, 331, 383, UINT_MAX}, /* speedo_id 2 */
+};
+
+/* Maximum speedo levels for each core process corner */
+static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = {
+/* proc_id 0	1    2	       3		  */
+	{165, 195, 224, UINT_MAX}, /* speedo_id 0 */
+	{165, 195, 224, UINT_MAX}, /* speedo_id 1 */
+	{165, 195, 224, UINT_MAX}, /* speedo_id 2 */
+};
+
+static int cpu_process_id;
+static int core_process_id;
+static int soc_speedo_id;
+
+void tegra_init_speedo_data(void)
+{
+	u32 reg, val;
+	int i, bit, rev;
+	int sku = tegra_sku_id();
+	void __iomem *apb_misc = IO_ADDRESS(TEGRA_APB_MISC_BASE);
+
+	reg = readl(apb_misc + CHIP_ID);
+	rev = (reg & CHIP_MINOR_MASK) >> CHIP_MINOR_SHIFT;
+	if (SPEEDO_ID_SELECT_0(rev))
+		soc_speedo_id = 0;
+	else if (SPEEDO_ID_SELECT_1(sku))
+		soc_speedo_id = 1;
+	else
+		soc_speedo_id = 2;
+	BUG_ON(soc_speedo_id >= ARRAY_SIZE(cpu_process_speedos));
+	BUG_ON(soc_speedo_id >= ARRAY_SIZE(core_process_speedos));
+
+	val = 0;
+	for (bit = CPU_SPEEDO_MSBIT; bit >= CPU_SPEEDO_LSBIT; bit--) {
+		reg = tegra_spare_fuse(bit) |
+			tegra_spare_fuse(bit + CPU_SPEEDO_REDUND_OFFS);
+		val = (val << 1) | (reg & 0x1);
+	}
+	val = val * SPEEDO_MULT;
+	pr_debug("%s CPU speedo level %u\n", __func__, val);
+
+	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
+		if (val <= cpu_process_speedos[soc_speedo_id][i])
+			break;
+	}
+	cpu_process_id = i;
+
+	val = 0;
+	for (bit = CORE_SPEEDO_MSBIT; bit >= CORE_SPEEDO_LSBIT; bit--) {
+		reg = tegra_spare_fuse(bit) |
+			tegra_spare_fuse(bit + CORE_SPEEDO_REDUND_OFFS);
+		val = (val << 1) | (reg & 0x1);
+	}
+	val = val * SPEEDO_MULT;
+	pr_debug("%s Core speedo level %u\n", __func__, val);
+
+	for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
+		if (val <= core_process_speedos[soc_speedo_id][i])
+			break;
+	}
+	core_process_id = i;
+
+	pr_info("Tegra SKU: %d Rev: A%.2d CPU Process: %d Core Process: %d"
+		" Speedo ID: %d\n", sku, rev, cpu_process_id, core_process_id,
+		soc_speedo_id);
+}
+
+int tegra_cpu_process_id(void)
+{
+	return cpu_process_id;
+}
+
+int tegra_core_process_id(void)
+{
+	return core_process_id;
+}
+
+int tegra_soc_speedo_id(void)
+{
+	return soc_speedo_id;
+}
diff --git a/arch/arm/mach-tegra/tegra_das.c b/arch/arm/mach-tegra/tegra_das.c
new file mode 100644
index 000000000000..601759c10b29
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_das.c
@@ -0,0 +1,507 @@
+/*
+ * linux/arch/arm/mach-tegra/tegra_das.c
+ *
+ * Digital audio switch driver for tegra soc
+ *
+ * Copyright (C) 2010 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/mutex.h>
+
+#include <mach/iomap.h>
+#include <mach/pinmux.h>
+#include <mach/tegra_das.h>
+
+#define TOTAL_DAP_PORTS		5
+
+struct das_driver_context {
+	struct platform_device *pdev;
+	struct tegra_das_platform_data *pdata;
+	phys_addr_t das_phys;
+	unsigned long das_base;
+	struct mutex mlock;
+	unsigned long tristate_count;
+	struct tegra_das_mux_select *mux_table;
+	enum tegra_das_port_con_id cur_con_id;
+	u32 total_dap_ports;
+	tegra_das_port hifi_port_idx;
+	tegra_das_port voice_codec_idx;
+	tegra_das_port bb_port_idx;
+	tegra_das_port bt_port_idx;
+	tegra_das_port fm_radio_port_idx;
+};
+
+struct das_driver_context *das_drv_data;
+
+#define SET_DAP_REG_FIELDS(dap_port, reg_off, mux_val) 		\
+	{							\
+		.port_type = dap_port,				\
+		.reg_offset = reg_off,				\
+		.mux_mask = DAP_CTRL_SEL_DEFAULT_MASK,		\
+		.mux_shift = DAP_CTRL_SEL_SHIFT,		\
+		.sdata1_mask = DAP_SDATA1_TX_RX_DEFAULT_MASK,	\
+		.sdata1_shift = DAP_SDATA1_TX_RX_SHIFT,		\
+		.sdata2_mask = DAP_SDATA2_RX_TX_DEFAULT_MASK,	\
+		.sdata2_shift = DAP_SDATA2_RX_TX_SHIFT,		\
+		.ms_mode_mask = DAP_MS_SEL_DEFAULT_MASK,	\
+		.ms_mode_shift = DAP_MS_SEL_SHIFT,		\
+		.mux_value = mux_val,				\
+	}
+
+#define SET_DAC_REG_FIELDS(dac_port, reg_off, mux_val) 		\
+	{							\
+		.port_type = dac_port,				\
+		.reg_offset = reg_off,				\
+		.mux_mask = DAC_CLK_SEL_DEFAULT_MASK,		\
+		.mux_shift = DAC_CLK_SEL_SHIFT,			\
+		.sdata1_mask = DAC_SDATA1_SEL_DEFAULT_MASK,	\
+		.sdata1_shift = DAC_SDATA1_SEL_SHIFT,		\
+		.sdata2_mask = DAC_SDATA2_SEL_DEFAULT_MASK,	\
+		.sdata2_shift = DAC_SDATA2_SEL_SHIFT,		\
+		.ms_mode_mask = 0,				\
+		.ms_mode_shift = 0,				\
+		.mux_value = mux_val,				\
+	}
+
+struct tegra_das_mux_select das_mux_table[] = {
+	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+	/* set DAP control registers fields */
+	SET_DAP_REG_FIELDS(tegra_das_port_dap1, APB_MISC_DAS_DAP_CTRL_SEL_0, DAP_CTRL_SEL_DAP1),
+	SET_DAP_REG_FIELDS(tegra_das_port_dap2, APB_MISC_DAS_DAP_CTRL_SEL_1, DAP_CTRL_SEL_DAP2),
+	SET_DAP_REG_FIELDS(tegra_das_port_dap3, APB_MISC_DAS_DAP_CTRL_SEL_2, DAP_CTRL_SEL_DAP3),
+	SET_DAP_REG_FIELDS(tegra_das_port_dap4, APB_MISC_DAS_DAP_CTRL_SEL_3, DAP_CTRL_SEL_DAP4),
+	SET_DAP_REG_FIELDS(tegra_das_port_dap5, APB_MISC_DAS_DAP_CTRL_SEL_4, DAP_CTRL_SEL_DAP5),
+
+	/* set DAC control registers fields */
+	SET_DAC_REG_FIELDS(tegra_das_port_i2s1, APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_0, DAP_CTRL_SEL_DAC1),
+	SET_DAC_REG_FIELDS(tegra_das_port_i2s2, APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_1, DAP_CTRL_SEL_DAC2),
+	SET_DAC_REG_FIELDS(tegra_das_port_ac97, APB_MISC_DAS_DAC_INPUT_DATA_CLK_SEL_2, DAP_CTRL_SEL_DAC3),
+};
+
+static int das_set_pin_state(bool normal);
+
+#ifdef CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static int dbg_das_show(struct seq_file *s, void *unused)
+{
+	struct das_driver_context *ctx = s->private;
+	int i;
+	u32 base_add = ctx->das_base;
+	u32 reg_off;
+
+	seq_printf(s, "Digital Audio Switch Registers \n");
+	seq_printf(s, "------------------------------\n");
+
+	for (i = 0; i < ARRAY_SIZE(das_mux_table); i++) {
+		reg_off = das_mux_table[i].reg_offset;
+		seq_printf(s, "%4X: 0x%08X \n",
+			(reg_off), readl(base_add + reg_off));
+	}
+
+	return 0;
+}
+
+static int dbg_das_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, dbg_das_show, inode->i_private);
+}
+
+static const struct file_operations debug_fops = {
+	.open		= dbg_das_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static void tegra_das_debuginit(struct das_driver_context *ctx)
+{
+	(void) debugfs_create_file("tegra_das", S_IRUGO,
+					NULL, ctx, &debug_fops);
+}
+
+#else
+static void __init tegra_das_debuginit(void)
+{
+	return;
+}
+#endif
+
+
+static inline void das_writel(unsigned long base, u32 val, u32 reg)
+{
+	writel(val, base + reg);
+}
+
+static inline u32 das_readl(unsigned long base, u32 reg)
+{
+	return readl(base + reg);
+}
+
+static int das_set_mux_ctrl_reg(u32 src_idx, u32 dest_idx)
+{
+	u32 reg_val = 0, reg_off = 0;
+	u32 dest_mux_sel_field = 0, dest_mux_sel_val = 0;
+	u32 mask = 0, shift = 0;
+
+	if (dest_idx == tegra_das_port_none) {
+		dest_idx = src_idx;
+	}
+
+	mask = das_drv_data->mux_table[dest_idx].mux_mask;
+	shift = das_drv_data->mux_table[dest_idx].mux_shift;
+
+	dest_mux_sel_field = mask << shift;
+	dest_mux_sel_val = das_drv_data->mux_table[src_idx].mux_value;
+
+	reg_off = das_drv_data->mux_table[dest_idx].reg_offset;
+
+	if (dest_idx > tegra_das_port_dap5)
+		dest_mux_sel_val = src_idx - tegra_das_port_dap1;
+
+	/* read the default DAS/DAP register */
+	reg_val = das_readl(das_drv_data->das_base, reg_off);
+
+	/* clear the exiting selection bits */
+	reg_val &= ~(dest_mux_sel_field);
+
+	/* set the destination value */
+	reg_val |= (dest_mux_sel_val & mask) << shift;
+
+	if (dest_idx > tegra_das_port_dap5) {
+		mask = das_drv_data->mux_table[dest_idx].sdata2_mask;
+		shift = das_drv_data->mux_table[dest_idx].sdata2_shift;
+		dest_mux_sel_field = mask << shift;
+		reg_val &= ~(dest_mux_sel_field);
+		reg_val |= (dest_mux_sel_val & mask) << shift;
+
+		mask = das_drv_data->mux_table[dest_idx].sdata1_mask;
+		shift = das_drv_data->mux_table[dest_idx].sdata1_shift;
+		dest_mux_sel_field = mask << shift;
+		reg_val &= ~(dest_mux_sel_field);
+		reg_val |= (dest_mux_sel_val & mask) << shift;
+	}
+
+	das_writel(das_drv_data->das_base, reg_val, reg_off);
+
+	return 0;
+}
+
+/*
+ * function to set dap as master/slave, when two or more DAPs
+ * are in by-pass mode
+ */
+static int das_set_dap_ms_mode(u32 dap_port_idx, bool is_master_mode)
+{
+	u32 reg_val = 0;
+	u32 mask = 0, shift = 0;
+	u32 src_mode = 0;
+	u32 reg_off = das_drv_data->mux_table[dap_port_idx].reg_offset;
+
+	mask = das_drv_data->mux_table[dap_port_idx].ms_mode_mask;
+	shift = das_drv_data->mux_table[dap_port_idx].ms_mode_shift;
+
+	src_mode = mask << shift;
+	/* nothing to do for the None Port */
+	if (dap_port_idx == tegra_das_port_none)
+		return 0;
+
+	/* Read the default DAS/DAP Register */
+	reg_val = das_readl(das_drv_data->das_base, reg_off);
+	/* Clear the Mode bits */
+	reg_val &= ~(src_mode);
+
+	if (is_master_mode) {
+		reg_val |= (1 & mask) << shift;
+	}
+
+	das_writel(das_drv_data->das_base, reg_val, reg_off);
+
+	return 0;
+}
+
+static int das_set_pin_state(bool normal)
+{
+	mutex_lock(&das_drv_data->mlock);
+	if (normal) {
+		if (das_drv_data->tristate_count == 0) {
+			/* Enable the DAP outputs */
+			tegra_pinmux_set_tristate(TEGRA_PINGROUP_DAP1,
+						TEGRA_TRI_NORMAL);
+			tegra_pinmux_set_tristate(TEGRA_PINGROUP_CDEV1,
+					TEGRA_TRI_NORMAL);
+			tegra_pinmux_set_tristate(TEGRA_PINGROUP_CDEV2,
+					TEGRA_TRI_NORMAL);
+		}
+		das_drv_data->tristate_count++;
+	} else {
+		das_drv_data->tristate_count--;
+		/* Tristate the DAP pinmux */
+		if (das_drv_data->tristate_count == 0) {
+			tegra_pinmux_set_tristate(TEGRA_PINGROUP_DAP1,
+					TEGRA_TRI_TRISTATE);
+			tegra_pinmux_set_tristate(TEGRA_PINGROUP_CDEV1,
+					TEGRA_TRI_TRISTATE);
+			tegra_pinmux_set_tristate(TEGRA_PINGROUP_CDEV2,
+					TEGRA_TRI_TRISTATE);
+		}
+	}
+	mutex_unlock(&das_drv_data->mlock);
+
+	return 0;
+}
+
+static int tegra_dap_default_settings(tegra_das_port dest_port)
+{
+	tegra_das_port src_port = tegra_das_port_i2s1;
+	const struct tegra_dap_property *dap_port_info_tbl;
+
+	if ((dest_port <= tegra_das_port_none) || (dest_port >
+		tegra_das_port_dap5)) {
+		return 0;
+	}
+
+	dap_port_info_tbl = das_drv_data->pdata->tegra_dap_port_info_table;
+
+	src_port = dap_port_info_tbl[dest_port].dac_port;
+
+	das_set_mux_ctrl_reg(src_port, dest_port);
+
+	/* Set the Port to Slave Mode */
+	das_set_dap_ms_mode(dest_port, false);
+
+	return 0;
+}
+
+const struct tegra_das_con* get_con_table_entry(
+				enum tegra_das_port_con_id con_id)
+{
+	const struct tegra_das_con *ptable =
+				das_drv_data->pdata->tegra_das_con_table;
+	int i;
+
+	for (i = 0; i < tegra_das_port_con_id_max; i++) {
+		if (con_id == ptable[i].con_id) {
+			return &ptable[i];
+		}
+	}
+
+	return NULL;
+}
+
+static int das_set_con_end_points(u32 src_idx, u32 dest_idx, bool is_src_master)
+{
+	if (src_idx == tegra_das_port_none && dest_idx == tegra_das_port_none)
+		return 0;
+
+	/* src to dest index */
+	das_set_mux_ctrl_reg(src_idx, dest_idx);
+
+	/* If src_idx is None swap the src and dest */
+	if (src_idx == tegra_das_port_none)
+		src_idx = dest_idx;
+
+	/* set the master/slave mode for source port */
+	das_set_dap_ms_mode(src_idx, is_src_master);
+	/* set the master/slave mode for destination port */
+	das_set_dap_ms_mode(dest_idx, !(is_src_master));
+
+	return 0;
+}
+
+
+int tegra_das_set_connection(enum tegra_das_port_con_id new_con_id)
+{
+	int i;
+	const struct tegra_das_con *pcon = NULL;
+
+	/* do nothng if same connection is requested */
+	if (das_drv_data->cur_con_id == new_con_id)
+		return 0;
+
+	pcon = get_con_table_entry(new_con_id);
+
+	mutex_lock(&das_drv_data->mlock);
+
+	if (pcon) {
+		for (i = 0; i < pcon->num_entries; i++) {
+			das_set_con_end_points(pcon->con_line[i].src,
+					pcon->con_line[i].dest,
+					pcon->con_line[i].src_master);
+		}
+	}
+
+	das_drv_data->cur_con_id = new_con_id;
+
+	mutex_unlock(&das_drv_data->mlock);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(tegra_das_set_connection);
+
+int tegra_das_get_connection(void)
+{
+	enum tegra_das_port_con_id con_id;
+
+	mutex_lock(&das_drv_data->mlock);
+	con_id = das_drv_data->cur_con_id;
+	mutex_unlock(&das_drv_data->mlock);
+
+	return con_id;
+}
+EXPORT_SYMBOL_GPL(tegra_das_get_connection);
+
+/* if is_normal is true then power mode is normal else tristated */
+int tegra_das_power_mode(bool is_normal)
+{
+	das_set_pin_state(is_normal);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(tegra_das_power_mode);
+
+int tegra_das_open(void)
+{
+	return 0;
+}
+EXPORT_SYMBOL_GPL(tegra_das_open);
+
+int tegra_das_close(void)
+{
+	return 0;
+}
+EXPORT_SYMBOL_GPL(tegra_das_close);
+
+static int tegra_das_probe(struct platform_device *pdev)
+{
+	int rc = 0;
+	struct resource *res;
+	struct das_driver_context *das_ctx;
+	const struct tegra_dap_property *dap_prop;
+	bool found;
+	int i;
+
+	das_ctx = kzalloc(sizeof(*das_ctx), GFP_KERNEL);
+	if (!das_ctx)
+		return -ENOMEM;
+
+	das_drv_data = das_ctx;
+	das_ctx->pdev = pdev;
+	das_ctx->pdata = pdev->dev.platform_data;
+	das_ctx->pdata->driver_data = das_ctx;
+	BUG_ON(!das_ctx->pdata);
+
+	das_ctx->mux_table = das_mux_table;
+	das_ctx->total_dap_ports = TOTAL_DAP_PORTS;
+	das_ctx->cur_con_id = tegra_das_port_con_id_none;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "no mem resource!\n");
+		rc = -ENODEV;
+		goto err;
+	}
+
+	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
+		dev_err(&pdev->dev, "memory region already claimed!\n");
+		rc = -ENOMEM;
+		goto err;
+	}
+
+	das_ctx->das_phys = res->start;
+	das_ctx->das_base = (unsigned long)ioremap(res->start,
+					res->end - res->start + 1);
+	if (!das_ctx->das_base) {
+		dev_err(&pdev->dev, "cannot remap iomem!\n");
+		rc = -EIO;
+		goto err;
+	}
+
+	mutex_init(&das_ctx->mlock);
+
+	platform_set_drvdata(pdev, das_ctx);
+
+	tegra_das_debuginit(das_ctx);
+
+	for (i = 0; i <= tegra_das_port_dap5; i++) {
+		dap_prop = &(das_ctx->pdata->tegra_dap_port_info_table[i]);
+		found = true;
+		/*
+		For low power consumption - default the values as follows
+		0x7000009c = 0x00000248, This sets DAP2, 3, 4 connected to DAC2
+		0x70000014 = 0x00000700, SDOUT2,3,4 are input
+		*/
+
+		/* Obtain the port index for each codec type */
+		switch(dap_prop->codec_type) {
+		case tegra_audio_codec_type_hifi:
+			das_ctx->hifi_port_idx = i;
+			break;
+		case tegra_audio_codec_type_voice:
+			das_ctx->voice_codec_idx = i;
+			break;
+		case tegra_audio_codec_type_bluetooth:
+			das_ctx->bt_port_idx = i;
+			break;
+		case tegra_audio_codec_type_baseband:
+			das_ctx->bb_port_idx = i;
+			break;
+		case tegra_audio_codec_type_fm_radio:
+			das_ctx->fm_radio_port_idx = i;
+			break;
+		default:
+			found = false;
+			break;
+		}
+		if (found) {
+			tegra_dap_default_settings(i);
+		}
+	}
+
+	/* by default connect to hifi codec */
+	tegra_das_set_connection(tegra_das_port_con_id_hifi);
+
+	return 0;
+
+err:
+	kfree(das_ctx);
+	return rc;
+}
+
+
+static struct platform_driver tegra_das_driver = {
+	.driver = {
+		.name = "tegra_das",
+		.owner = THIS_MODULE,
+	},
+	.probe = tegra_das_probe,
+};
+
+static int __init tegra_das_init(void)
+{
+	return platform_driver_register(&tegra_das_driver);
+}
+
+module_init(tegra_das_init);
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c
index 7242dda542c2..9e809253170f 100644
--- a/arch/arm/mach-tegra/usb_phy.c
+++ b/arch/arm/mach-tegra/usb_phy.c
@@ -28,6 +28,8 @@
 #include <asm/mach-types.h>
 #include <mach/usb_phy.h>
 #include <mach/iomap.h>
+#include <mach/pinmux.h>
+#include "gpio-names.h"
 
 #define USB_USBSTS		0x144
 #define   USB_USBSTS_PCI	(1 << 2)
@@ -76,9 +78,28 @@
 #define   USB1_VBUS_SENSE_CTL_AB_SESS_VLD	(2 << 1)
 #define   USB1_VBUS_SENSE_CTL_A_SESS_VLD	(3 << 1)
 
+#define ULPIS2S_CTRL		0x418
+#define   ULPIS2S_ENA			(1 << 0)
+#define   ULPIS2S_SUPPORT_DISCONNECT	(1 << 2)
+#define   ULPIS2S_PLLU_MASTER_BLASTER60	(1 << 3)
+#define   ULPIS2S_SPARE(x)		(((x) & 0xF) << 8)
+#define   ULPIS2S_FORCE_ULPI_CLK_OUT	(1 << 12)
+#define   ULPIS2S_DISCON_DONT_CHECK_SE0	(1 << 13)
+#define   ULPIS2S_SUPPORT_HS_KEEP_ALIVE (1 << 14)
+#define   ULPIS2S_DISABLE_STP_PU	(1 << 15)
+
 #define ULPI_TIMING_CTRL_0	0x424
+#define   ULPI_CLOCK_OUT_DELAY(x)	((x) & 0x1F)
 #define   ULPI_OUTPUT_PINMUX_BYP	(1 << 10)
 #define   ULPI_CLKOUT_PINMUX_BYP	(1 << 11)
+#define   ULPI_SHADOW_CLK_LOOPBACK_EN	(1 << 12)
+#define   ULPI_SHADOW_CLK_SEL		(1 << 13)
+#define   ULPI_CORE_CLK_SEL		(1 << 14)
+#define   ULPI_SHADOW_CLK_DELAY(x)	(((x) & 0x1F) << 16)
+#define   ULPI_LBK_PAD_EN		(1 << 26)
+#define   ULPI_LBK_PAD_E_INPUT_OR	(1 << 27)
+#define   ULPI_CLK_OUT_ENA		(1 << 28)
+#define   ULPI_CLK_PADOUT_ENA		(1 << 29)
 
 #define ULPI_TIMING_CTRL_1	0x428
 #define   ULPI_DATA_TRIMMER_LOAD	(1 << 0)
@@ -339,6 +360,7 @@ static void utmi_phy_power_on(struct tegra_usb_phy *phy)
 {
 	unsigned long val;
 	void __iomem *base = phy->regs;
+	int gpio_status;
 	struct tegra_utmip_config *config = phy->config;
 
 	val = readl(base + USB_SUSP_CTRL);
@@ -448,6 +470,21 @@ static void utmi_phy_power_on(struct tegra_usb_phy *phy)
 		val = readl(base + USB_SUSP_CTRL);
 		val &= ~USB_SUSP_SET;
 		writel(val, base + USB_SUSP_CTRL);
+		if (phy->mode == TEGRA_USB_PHY_MODE_HOST) {
+			gpio_status = gpio_request(TEGRA_GPIO_PD0,"VBUS_BUS");
+			if (gpio_status < 0) {
+				printk("VBUS_USB1 request GPIO FAILED\n");
+				WARN_ON(1);
+			}
+			tegra_gpio_enable(TEGRA_GPIO_PD0);
+			gpio_status = gpio_direction_output(TEGRA_GPIO_PD0, 1);
+			if (gpio_status < 0) {
+				printk("VBUS_USB1 request GPIO DIRECTION FAILED \n");
+				WARN_ON(1);
+			}
+			gpio_set_value(TEGRA_GPIO_PD0, 1);
+			tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_NORMAL);
+		}
 	}
 
 	utmi_phy_clk_enable(phy);
@@ -466,6 +503,11 @@ static void utmi_phy_power_off(struct tegra_usb_phy *phy)
 
 	utmi_phy_clk_disable(phy);
 
+	if (phy->instance == 0 && phy->mode == TEGRA_USB_PHY_MODE_HOST) {
+		gpio_free(TEGRA_GPIO_PD0);
+		tegra_pinmux_set_tristate(TEGRA_PINGROUP_SLXK, TEGRA_TRI_TRISTATE);
+	}
+
 	if (phy->mode == TEGRA_USB_PHY_MODE_DEVICE) {
 		val = readl(base + USB_SUSP_CTRL);
 		val &= ~USB_WAKEUP_DEBOUNCE_COUNT(~0);
@@ -641,6 +683,108 @@ static void ulpi_phy_power_off(struct tegra_usb_phy *phy)
 	clk_disable(phy->clk);
 }
 
+static void null_phy_power_on(struct tegra_usb_phy *phy)
+{
+	const struct tegra_ulpi_trimmer default_trimmer = {0, 0, 4, 4};
+	unsigned long val;
+	void __iomem *base = phy->regs;
+	struct tegra_ulpi_config *config = phy->config;
+
+	if (config->preinit)
+		config->preinit();
+
+	if (!config->trimmer)
+		config->trimmer = &default_trimmer;
+
+	val = readl(base + USB_SUSP_CTRL);
+	val |= UHSIC_RESET;
+	writel(val, base + USB_SUSP_CTRL);
+
+	val = readl(base + ULPI_TIMING_CTRL_0);
+	val |= ULPI_OUTPUT_PINMUX_BYP | ULPI_CLKOUT_PINMUX_BYP;
+	writel(val, base + ULPI_TIMING_CTRL_0);
+
+	val = readl(base + USB_SUSP_CTRL);
+	val |= ULPI_PHY_ENABLE;
+	writel(val, base + USB_SUSP_CTRL);
+
+	/* set timming parameters */
+	val = readl(base + ULPI_TIMING_CTRL_0);
+	val |= ULPI_SHADOW_CLK_LOOPBACK_EN;
+	val |= ULPI_SHADOW_CLK_SEL;
+	val |= ULPI_OUTPUT_PINMUX_BYP;
+	val |= ULPI_CLKOUT_PINMUX_BYP;
+	val |= ULPI_LBK_PAD_EN;
+	val |= ULPI_SHADOW_CLK_DELAY(config->trimmer->shadow_clk_delay);
+	val |= ULPI_CLOCK_OUT_DELAY(config->trimmer->clock_out_delay);
+	val |= ULPI_LBK_PAD_E_INPUT_OR;
+	writel(val, base + ULPI_TIMING_CTRL_0);
+
+	val = 0;
+	writel(val, base + ULPI_TIMING_CTRL_1);
+	udelay(10);
+
+	/* enable null phy mode */
+	val = ULPIS2S_ENA;
+	val |= ULPIS2S_PLLU_MASTER_BLASTER60;
+	val |= ULPIS2S_SPARE((phy->mode == TEGRA_USB_PHY_MODE_HOST)? 3:1);
+	writel(val, base + ULPIS2S_CTRL);
+
+	/* select ULPI_CORE_CLK_SEL to SHADOW_CLK */
+	val = readl(base + ULPI_TIMING_CTRL_0);
+	val |= ULPI_CORE_CLK_SEL;
+	writel(val, base + ULPI_TIMING_CTRL_0);
+	udelay(10);
+
+	/* enable ULPI null clocks - can't set the trimmers before this */
+	val = readl(base + ULPI_TIMING_CTRL_0);
+	val |= ULPI_CLK_OUT_ENA;
+	writel(val, base + ULPI_TIMING_CTRL_0);
+	udelay(10);
+
+	val = ULPI_DATA_TRIMMER_SEL(config->trimmer->data_trimmer);
+	val |= ULPI_STPDIRNXT_TRIMMER_SEL(config->trimmer->stpdirnxt_trimmer);
+	val |= ULPI_DIR_TRIMMER_SEL(4);
+	writel(val, base + ULPI_TIMING_CTRL_1);
+	udelay(10);
+
+	val |= ULPI_DATA_TRIMMER_LOAD;
+	val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
+	val |= ULPI_DIR_TRIMMER_LOAD;
+	writel(val, base + ULPI_TIMING_CTRL_1);
+
+	val = readl(base + ULPI_TIMING_CTRL_0);
+	val |= ULPI_CLK_PADOUT_ENA;
+	writel(val, base + ULPI_TIMING_CTRL_0);
+	udelay(10);
+
+	val = readl(base + USB_SUSP_CTRL);
+	val |= USB_SUSP_CLR;
+	writel(val, base + USB_SUSP_CTRL);
+	udelay(100);
+
+	val = readl(base + USB_SUSP_CTRL);
+	val &= ~USB_SUSP_CLR;
+	writel(val, base + USB_SUSP_CTRL);
+
+	if (utmi_wait_register(base + USB_SUSP_CTRL, USB_PHY_CLK_VALID,
+						     USB_PHY_CLK_VALID))
+		pr_err("%s: timeout waiting for phy to stabilize\n", __func__);
+
+	if (config->postinit)
+		config->postinit();
+}
+
+static void null_phy_power_off(struct tegra_usb_phy *phy)
+{
+	unsigned long val;
+	void __iomem *base = phy->regs;
+
+	val = readl(base + ULPI_TIMING_CTRL_0);
+	val &= ~ULPI_CLK_PADOUT_ENA;
+	writel(val, base + ULPI_TIMING_CTRL_0);
+}
+
 struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
 			void *config, enum tegra_usb_phy_mode phy_mode)
 {
@@ -691,15 +835,18 @@ struct tegra_usb_phy *tegra_usb_phy_open(int instance, void __iomem *regs,
 
 	if (phy->instance == 1) {
 		ulpi_config = config;
-		phy->clk = clk_get_sys(NULL, ulpi_config->clk);
-		if (IS_ERR(phy->clk)) {
-			pr_err("%s: can't get ulpi clock\n", __func__);
-			err = -ENXIO;
-			goto err1;
+
+		if (ulpi_config->inf_type == TEGRA_USB_LINK_ULPI) {
+			phy->clk = clk_get_sys(NULL, ulpi_config->clk);
+			if (IS_ERR(phy->clk)) {
+				pr_err("%s: can't get ulpi clock\n", __func__);
+				err = -ENXIO;
+				goto err1;
+			}
+			tegra_gpio_enable(ulpi_config->reset_gpio);
+			gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
+			gpio_direction_output(ulpi_config->reset_gpio, 0);
 		}
-		tegra_gpio_enable(ulpi_config->reset_gpio);
-		gpio_request(ulpi_config->reset_gpio, "ulpi_phy_reset_b");
-		gpio_direction_output(ulpi_config->reset_gpio, 0);
 	} else {
 		err = utmip_pad_open(phy);
 		if (err < 0)
@@ -718,9 +865,14 @@ err0:
 
 int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 {
-	if (phy->instance == 1)
-		ulpi_phy_power_on(phy);
-	else
+	if (phy->instance == 1) {
+		struct tegra_ulpi_config *ulpi_config = phy->config;
+
+		if (ulpi_config->inf_type == TEGRA_USB_LINK_ULPI)
+			ulpi_phy_power_on(phy);
+		else
+			null_phy_power_on(phy);
+	} else
 		utmi_phy_power_on(phy);
 
 	return 0;
@@ -728,9 +880,14 @@ int tegra_usb_phy_power_on(struct tegra_usb_phy *phy)
 
 int tegra_usb_phy_power_off(struct tegra_usb_phy *phy)
 {
-	if (phy->instance == 1)
-		ulpi_phy_power_off(phy);
-	else
+	if (phy->instance == 1) {
+		struct tegra_ulpi_config *ulpi_config = phy->config;
+
+		if (ulpi_config->inf_type == TEGRA_USB_LINK_ULPI)
+			ulpi_phy_power_off(phy);
+		else
+			null_phy_power_off(phy);
+	} else
 		utmi_phy_power_off(phy);
 
 	return 0;
@@ -783,9 +940,12 @@ int tegra_usb_phy_clk_enable(struct tegra_usb_phy *phy)
 
 int tegra_usb_phy_close(struct tegra_usb_phy *phy)
 {
-	if (phy->instance == 1)
-		clk_put(phy->clk);
-	else
+	if (phy->instance == 1) {
+		struct tegra_ulpi_config *ulpi_config = phy->config;
+
+		if (ulpi_config->inf_type == TEGRA_USB_LINK_ULPI)
+			clk_put(phy->clk);
+	} else
 		utmip_pad_close(phy);
 	clk_disable(phy->pll_u);
 	clk_put(phy->pll_u);
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 598c51ad5071..b8061519ce77 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index f55fa1044f72..bdba6c65c901 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
 	unsigned int offset = CACHE_COLOUR(vaddr);
 	unsigned long kfrom, kto;
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	/* FIXME: not highmem safe */
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 9920c0ae2096..649bbcd325bf 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 4bc43e535d3b..16df5767ff78 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -523,6 +523,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
 		outer_inv_range(paddr, paddr + size);
 
 	dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+
+	/*
+	 * Mark the D-cache clean for this page to avoid extra flushing.
+	 */
+	if (dir != DMA_TO_DEVICE)
+		set_bit(PG_dcache_clean, &page->flags);
 }
 EXPORT_SYMBOL(___dma_page_dev_to_cpu);
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 74e71052da12..33486f952d63 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -28,6 +28,7 @@
 
 static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
 
+#ifndef CONFIG_SMP
 /*
  * We take the easy way out of this problem - we make the
  * PTE uncacheable.  However, we leave the write buffer on.
@@ -165,7 +166,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
  * a page table, or changing an existing PTE.  Basically, there are two
  * things that we need to take care of:
  *
- *  1. If PG_dcache_dirty is set for the page, we need to ensure
+ *  1. If PG_dcache_clean is not set for the page, we need to ensure
  *     that any cache entries for the kernels virtual memory
  *     range are written back to the page.
  *  2. If we have multiple shared mappings of the same space in
@@ -192,7 +193,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 		return;
 
 	mapping = page_mapping(page);
-	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
 		__flush_dcache_page(mapping, page);
 	if (mapping) {
 		if (cache_is_vivt())
@@ -201,6 +202,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 			__flush_icache_all();
 	}
 }
+#endif	/* !CONFIG_SMP */
 
 /*
  * Check whether the write buffer has physical address aliasing
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index e0758968e9f8..7fe64b25dc5a 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -94,12 +94,10 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
 #define flush_pfn_alias(pfn,vaddr)	do { } while (0)
 #endif
 
-#ifdef CONFIG_SMP
 static void flush_ptrace_access_other(void *args)
 {
 	__flush_icache_all();
 }
-#endif
 
 static
 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
@@ -123,11 +121,9 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 	if (vma->vm_flags & VM_EXEC) {
 		unsigned long addr = (unsigned long)kaddr;
 		__cpuc_coherent_kern_range(addr, addr + len);
-#ifdef CONFIG_SMP
 		if (cache_ops_need_broadcast())
 			smp_call_function(flush_ptrace_access_other,
 					  NULL, 1);
-#endif
 	}
 }
 
@@ -216,6 +212,21 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
 	flush_dcache_mmap_unlock(mapping);
 }
 
+#ifdef CONFIG_SMP
+void __sync_icache_dcache(pte_t pteval)
+{
+	unsigned long pfn = pte_pfn(pteval);
+
+	if (pfn_valid(pfn) && pte_present_exec_user(pteval)) {
+		struct page *page = pfn_to_page(pfn);
+
+		if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+			__flush_dcache_page(NULL, page);
+		__flush_icache_all();
+	}
+}
+#endif
+
 /*
  * Ensure cache coherency between kernel mapping and userspace mapping
  * of this page.
@@ -248,14 +259,15 @@ void flush_dcache_page(struct page *page)
 	mapping = page_mapping(page);
 
 	if (!cache_ops_need_broadcast() &&
-	    !PageHighMem(page) && mapping && !mapping_mapped(mapping))
-		set_bit(PG_dcache_dirty, &page->flags);
+	    mapping && !mapping_mapped(mapping))
+		clear_bit(PG_dcache_clean, &page->flags);
 	else {
 		__flush_dcache_page(mapping, page);
 		if (mapping && cache_is_vivt())
 			__flush_dcache_aliases(mapping, page);
 		else if (mapping)
 			__flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
 	}
 }
 EXPORT_SYMBOL(flush_dcache_page);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 55590a4d87c9..e640a4478e76 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -3044,3 +3044,4 @@ harvest_desoto		MACH_HARVEST_DESOTO	HARVEST_DESOTO		3059
 msm8x60_qrdc		MACH_MSM8X60_QRDC	MSM8X60_QRDC		3060
 spear900		MACH_SPEAR900		SPEAR900		3061
 pcontrol_g20		MACH_PCONTROL_G20	PCONTROL_G20		3062
+whistler                MACH_WHISTLER           WHISTLER                3241
\ No newline at end of file
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index 91aa11ce0de2..8a7c909f5fc3 100755..100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -31,14 +31,16 @@
 #include <mach/clk.h>
 #include <mach/pinmux.h>
 
-#define TEGRA_I2C_TIMEOUT (msecs_to_jiffies(1000))
-#define BYTES_PER_FIFO_WORD 4
+#define TEGRA_I2C_TIMEOUT			(msecs_to_jiffies(1000))
+#define TEGRA_I2C_RETRIES			3
+#define BYTES_PER_FIFO_WORD			4
 
 #define I2C_CNFG				0x000
 #define I2C_CNFG_DEBOUNCE_CNT_SHIFT		12
 #define I2C_CNFG_PACKET_MODE_EN			(1<<10)
 #define I2C_CNFG_NEW_MASTER_FSM			(1<<11)
 #define I2C_STATUS				0x01C
+#define I2C_STATUS_BUSY				(1<<8)
 #define I2C_SL_CNFG				0x020
 #define I2C_SL_CNFG_NEWSL			(1<<2)
 #define I2C_SL_ADDR1				0x02c
@@ -80,6 +82,7 @@
 #define I2C_ERR_NO_ACK				0x01
 #define I2C_ERR_ARBITRATION_LOST		0x02
 #define I2C_ERR_UNKNOWN_INTERRUPT		0x04
+#define I2C_ERR_UNEXPECTED_STATUS		0x08
 
 #define PACKET_HEADER0_HEADER_SIZE_SHIFT	28
 #define PACKET_HEADER0_PACKET_ID_SHIFT		16
@@ -120,9 +123,14 @@ struct tegra_i2c_dev {
 	struct completion msg_complete;
 	int msg_err;
 	u8 *msg_buf;
+	u32 packet_header;
+	u32 payload_size;
+	u32 io_header;
 	size_t msg_buf_remaining;
 	int msg_read;
 	int msg_transfer_complete;
+	struct i2c_msg *msgs;
+	int msgs_num;
 	bool is_suspended;
 	int bus_count;
 	const struct tegra_pingroup_config *last_mux;
@@ -344,13 +352,10 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 	status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 
 	if (status == 0) {
-		dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
-			 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
-			 i2c_readl(i2c_dev, I2C_STATUS),
-			 i2c_readl(i2c_dev, I2C_CNFG));
+		dev_warn(i2c_dev->dev, "unknown interrupt\n");
 		i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 
-		if (! i2c_dev->irq_disabled) {
+		if (!i2c_dev->irq_disabled) {
 			disable_irq_nosync(i2c_dev->irq);
 			i2c_dev->irq_disabled = 1;
 		}
@@ -360,10 +365,32 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 	}
 
 	if (unlikely(status & status_err)) {
-		if (status & I2C_INT_NO_ACK)
+		if (status & I2C_INT_NO_ACK) {
 			i2c_dev->msg_err |= I2C_ERR_NO_ACK;
-		if (status & I2C_INT_ARBITRATION_LOST)
+			dev_warn(i2c_dev->dev, "no acknowledge\n");
+		}
+
+		if (status & I2C_INT_ARBITRATION_LOST) {
 			i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
+			dev_warn(i2c_dev->dev, "arbitration lost\n");
+		}
+
+		complete(&i2c_dev->msg_complete);
+		goto err;
+	}
+
+	if (unlikely((i2c_readl(i2c_dev, I2C_STATUS) & I2C_STATUS_BUSY)
+				&& (status == I2C_INT_TX_FIFO_DATA_REQ)
+				&& i2c_dev->msg_read
+				&& i2c_dev->msg_buf_remaining)) {
+		dev_warn(i2c_dev->dev, "unexpected status\n");
+		i2c_dev->msg_err |= I2C_ERR_UNEXPECTED_STATUS;
+
+		if (!i2c_dev->irq_disabled) {
+			disable_irq_nosync(i2c_dev->irq);
+			i2c_dev->irq_disabled = 1;
+		}
+
 		complete(&i2c_dev->msg_complete);
 		goto err;
 	}
@@ -387,18 +414,45 @@ static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 
 	if (i2c_dev->msg_transfer_complete && !i2c_dev->msg_buf_remaining)
 		complete(&i2c_dev->msg_complete);
+
 	i2c_writel(i2c_dev, status, I2C_INT_STATUS);
+
 	if (i2c_dev->is_dvc)
 		dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
+
 	return IRQ_HANDLED;
+
 err:
+	dev_dbg(i2c_dev->dev, "reg: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+		 i2c_readl(i2c_dev, I2C_CNFG), i2c_readl(i2c_dev, I2C_STATUS),
+		 i2c_readl(i2c_dev, I2C_INT_STATUS),
+		 i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS));
+
+	dev_dbg(i2c_dev->dev, "packet: 0x%08x %u 0x%08x\n",
+		 i2c_dev->packet_header, i2c_dev->payload_size,
+		 i2c_dev->io_header);
+
+	if (i2c_dev->msgs) {
+		struct i2c_msg *msgs = i2c_dev->msgs;
+		int i;
+
+		for (i = 0; i < i2c_dev->msgs_num; i++)
+			dev_dbg(i2c_dev->dev,
+				 "msgs[%d] %c, addr=0x%04x, len=%d\n",
+				 i, (msgs[i].flags & I2C_M_RD) ? 'R' : 'W',
+				 msgs[i].addr, msgs[i].len);
+	}
+
 	/* An error occured, mask all interrupts */
 	tegra_i2c_mask_irq(i2c_dev, I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST |
 		I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
 		I2C_INT_RX_FIFO_DATA_REQ);
+
 	i2c_writel(i2c_dev, status, I2C_INT_STATUS);
+
 	if (i2c_dev->is_dvc)
 		dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
+
 	return IRQ_HANDLED;
 }
 
@@ -406,7 +460,6 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_bus *i2c_bus,
 	struct i2c_msg *msg, int stop)
 {
 	struct tegra_i2c_dev *i2c_dev = i2c_bus->dev;
-	u32 packet_header;
 	u32 int_mask;
 	int ret;
 
@@ -423,26 +476,26 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_bus *i2c_bus,
 	i2c_dev->msg_read = (msg->flags & I2C_M_RD);
 	INIT_COMPLETION(i2c_dev->msg_complete);
 
-	packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
+	i2c_dev->packet_header = (0 << PACKET_HEADER0_HEADER_SIZE_SHIFT) |
 			PACKET_HEADER0_PROTOCOL_I2C |
 			(i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) |
 			(1 << PACKET_HEADER0_PACKET_ID_SHIFT);
-	i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
+	i2c_writel(i2c_dev, i2c_dev->packet_header, I2C_TX_FIFO);
 
-	packet_header = msg->len - 1;
-	i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
+	i2c_dev->payload_size = msg->len - 1;
+	i2c_writel(i2c_dev, i2c_dev->payload_size, I2C_TX_FIFO);
 
-	packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
-	packet_header |= I2C_HEADER_IE_ENABLE;
+	i2c_dev->io_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
+	i2c_dev->io_header |= I2C_HEADER_IE_ENABLE;
 	if (!stop)
-		packet_header |= I2C_HEADER_REPEAT_START;
+		i2c_dev->io_header |= I2C_HEADER_REPEAT_START;
 	if (msg->flags & I2C_M_TEN)
-		packet_header |= I2C_HEADER_10BIT_ADDR;
+		i2c_dev->io_header |= I2C_HEADER_10BIT_ADDR;
 	if (msg->flags & I2C_M_IGNORE_NAK)
-		packet_header |= I2C_HEADER_CONT_ON_NAK;
+		i2c_dev->io_header |= I2C_HEADER_CONT_ON_NAK;
 	if (msg->flags & I2C_M_RD)
-		packet_header |= I2C_HEADER_READ;
-	i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
+		i2c_dev->io_header |= I2C_HEADER_READ;
+	i2c_writel(i2c_dev, i2c_dev->io_header, I2C_TX_FIFO);
 
 	if (!(msg->flags & I2C_M_RD))
 		tegra_i2c_fill_tx_fifo(i2c_dev);
@@ -455,17 +508,21 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_bus *i2c_bus,
 	tegra_i2c_unmask_irq(i2c_dev, int_mask);
 	pr_debug("unmasked irq: %02x\n", i2c_readl(i2c_dev, I2C_INT_MASK));
 
-	ret = wait_for_completion_timeout(&i2c_dev->msg_complete, TEGRA_I2C_TIMEOUT);
+	ret = wait_for_completion_timeout(&i2c_dev->msg_complete,
+					TEGRA_I2C_TIMEOUT);
 	tegra_i2c_mask_irq(i2c_dev, int_mask);
 
 	if (WARN_ON(ret == 0)) {
-		dev_err(i2c_dev->dev, "i2c transfer timed out\n");
+		dev_err(i2c_dev->dev,
+			"i2c transfer timed out, addr 0x%04x, data 0x%02x\n",
+			msg->addr, msg->buf[0]);
 
 		tegra_i2c_init(i2c_dev);
 		return -ETIMEDOUT;
 	}
 
-	pr_debug("transfer complete: %d %d %d\n", ret, completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
+	pr_debug("transfer complete: %d %d %d\n", ret,
+		completion_done(&i2c_dev->msg_complete), i2c_dev->msg_err);
 
 	if (likely(i2c_dev->msg_err == I2C_ERR_NONE))
 		return 0;
@@ -477,6 +534,9 @@ static int tegra_i2c_xfer_msg(struct tegra_i2c_bus *i2c_bus,
 		return -EREMOTEIO;
 	}
 
+	if (i2c_dev->msg_err & I2C_ERR_UNEXPECTED_STATUS)
+		return -EAGAIN;
+
 	return -EIO;
 }
 
@@ -507,6 +567,9 @@ static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
 		i2c_dev->last_bus_clk = i2c_bus->bus_clk_rate;
 	}
 
+	i2c_dev->msgs = msgs;
+	i2c_dev->msgs_num = num;
+
 	clk_enable(i2c_dev->clk);
 	for (i = 0; i < num; i++) {
 		int stop = (i == (num - 1)) ? 1  : 0;
@@ -521,6 +584,9 @@ out:
 
 	rt_mutex_unlock(&i2c_dev->dev_lock);
 
+	i2c_dev->msgs = NULL;
+	i2c_dev->msgs_num = 0;
+
 	return ret;
 }
 
@@ -528,7 +594,7 @@ static u32 tegra_i2c_func(struct i2c_adapter *adap)
 {
 	/* FIXME: For now keep it simple and don't support protocol mangling
 	   features */
-	return I2C_FUNC_I2C;
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA;
 }
 
 static const struct i2c_algorithm tegra_i2c_algo = {
@@ -615,6 +681,8 @@ static int tegra_i2c_probe(struct platform_device *pdev)
 	i2c_dev->cont_id = pdev->id;
 	i2c_dev->dev = &pdev->dev;
 	i2c_dev->last_bus_clk = plat->bus_clk_rate[0] ?: 100000;
+	i2c_dev->msgs = NULL;
+	i2c_dev->msgs_num = 0;
 	rt_mutex_init(&i2c_dev->dev_lock);
 
 	i2c_dev->is_dvc = plat->is_dvc;
@@ -651,6 +719,15 @@ static int tegra_i2c_probe(struct platform_device *pdev)
 			sizeof(i2c_bus->adapter.name));
 		i2c_bus->adapter.dev.parent = &pdev->dev;
 		i2c_bus->adapter.nr = plat->adapter_nr + i;
+
+		if (plat->retries)
+			i2c_bus->adapter.retries = plat->retries;
+		else
+			i2c_bus->adapter.retries = TEGRA_I2C_RETRIES;
+
+		if (plat->timeout)
+			i2c_bus->adapter.timeout = plat->timeout;
+
 		ret = i2c_add_numbered_adapter(&i2c_bus->adapter);
 		if (ret) {
 			dev_err(&pdev->dev, "Failed to add I2C adapter\n");
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index 9cc488d21490..149a32fa8372 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -327,6 +327,13 @@ config KEYBOARD_NEWTON
 	  To compile this driver as a module, choose M here: the
 	  module will be called newtonkbd.
 
+config KEYBOARD_TEGRA
+	boolean "NVIDIA Tegra internal matrix keyboard controller support"
+	depends on ARCH_TEGRA
+	help
+	  Say Y here if you want to use a matrix keyboard connected directly
+	  to the internal keyboard controller on Tegra SoCs
+
 config KEYBOARD_OPENCORES
 	tristate "OpenCores Keyboard Controller"
 	help
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 504b591be0cd..2c7686eb90b4 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_KEYBOARD_MATRIX)		+= matrix_keypad.o
 obj-$(CONFIG_KEYBOARD_MAX7359)		+= max7359_keypad.o
 obj-$(CONFIG_KEYBOARD_MCS)		+= mcs_touchkey.o
 obj-$(CONFIG_KEYBOARD_NEWTON)		+= newtonkbd.o
+obj-$(CONFIG_KEYBOARD_TEGRA)		+= tegra-kbc.o
 obj-$(CONFIG_KEYBOARD_OMAP)		+= omap-keypad.o
 obj-$(CONFIG_KEYBOARD_OPENCORES)	+= opencores-kbd.o
 obj-$(CONFIG_KEYBOARD_PXA27x)		+= pxa27x_keypad.o
diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c
index 6069abe31e42..4b75848b6351 100644
--- a/drivers/input/keyboard/gpio_keys.c
+++ b/drivers/input/keyboard/gpio_keys.c
@@ -594,14 +594,26 @@ static int gpio_keys_resume(struct device *dev)
 	struct platform_device *pdev = to_platform_device(dev);
 	struct gpio_keys_drvdata *ddata = platform_get_drvdata(pdev);
 	struct gpio_keys_platform_data *pdata = pdev->dev.platform_data;
+	int wakeup_key = KEY_RESERVED;
 	int i;
 
+	if (pdata->wakeup_key)
+		wakeup_key = pdata->wakeup_key();
+
 	for (i = 0; i < pdata->nbuttons; i++) {
 
 		struct gpio_keys_button *button = &pdata->buttons[i];
 		if (button->wakeup && device_may_wakeup(&pdev->dev)) {
 			int irq = gpio_to_irq(button->gpio);
 			disable_irq_wake(irq);
+
+			if (wakeup_key == button->code) {
+				unsigned int type = button->type ?: EV_KEY;
+
+				input_event(ddata->input, type, button->code, 1);
+				input_event(ddata->input, type, button->code, 0);
+				input_sync(ddata->input);
+			}
 		}
 
 		gpio_keys_report_event(&ddata->data[i]);
diff --git a/drivers/input/keyboard/tegra-kbc.c b/drivers/input/keyboard/tegra-kbc.c
new file mode 100644
index 000000000000..cddd9cce2b29
--- /dev/null
+++ b/drivers/input/keyboard/tegra-kbc.c
@@ -0,0 +1,700 @@
+/*
+ * drivers/input/keyboard/tegra-kbc.c
+ *
+ * Keyboard class input driver for the NVIDIA Tegra SoC internal matrix
+ * keyboard controller
+ *
+ * Copyright (c) 2009-2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+/*#define DEBUG           1*/
+/*#define VERBOSE_DEBUG   1*/
+#include <linux/module.h>
+#include <linux/input.h>
+#include <linux/platform_device.h>
+#include <linux/kthread.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <mach/clk.h>
+#include <mach/kbc.h>
+
+#define KBC_CONTROL_0	0
+#define KBC_INT_0	4
+#define KBC_ROW_CFG0_0	8
+#define KBC_COL_CFG0_0	0x18
+#define KBC_TO_CNT_0	0x24
+#define KBC_RPT_DLY_0	0x2c
+#define KBC_KP_ENT0_0	0x30
+#define KBC_KP_ENT1_0	0x34
+#define KBC_ROW0_MASK_0	0x38
+
+#define res_size(res)	((res)->end - (res)->start + 1)
+
+struct tegra_kbc {
+	void __iomem *mmio;
+	struct input_dev *idev;
+	struct device *dev;
+	int irq;
+	unsigned int wake_enable_keys[KBC_MAX_ROW];
+	spinlock_t lock;
+	unsigned int repoll_time;
+	struct tegra_kbc_platform_data *pdata;
+	int *plain_keycode;
+	int *fn_keycode;
+	struct work_struct key_repeat;
+	struct workqueue_struct *kbc_work_queue;
+	struct clk *clk;
+	int row_seq[KBC_MAX_ROW];
+	int col_seq[KBC_MAX_COL];
+	int ncols;
+};
+
+static int tegra_kbc_filter_keys(struct tegra_kbc *kbc, int *prows, int *pcols,
+		int nkey_pressed)
+{
+	int i = 0;
+	int j = 0;
+	int k = 0;
+	int filter_keys[2] = {0};
+	int is_filtered = false;
+	int new_key_press_count = nkey_pressed;
+
+	dev_dbg(kbc->dev, "%s\n", __func__);
+
+	if (nkey_pressed <= 3) {
+		for (i = 0; i < nkey_pressed; i++) {
+			for (j = (i + 1); j < nkey_pressed; j++) {
+				if ((prows[i] + 1 == prows[j]) ||
+						(prows[j] + 1 == prows[i])) {
+					for (k = j; i < (nkey_pressed - 1);
+									i++) {
+						prows[k] = prows[k+1];
+						pcols[k] = pcols[k+1];
+					}
+					nkey_pressed--;
+				}
+				if ((pcols[i] + 1 == pcols[j]) ||
+						(pcols[j] + 1 == pcols[i])) {
+					for (k = j; i < (nkey_pressed - 1);
+									i++) {
+						prows[k] = prows[k+1];
+						pcols[k] = pcols[k+1];
+					}
+					nkey_pressed--;
+				}
+			}
+		}
+		return nkey_pressed;
+	}
+
+	for (i = 0; i < nkey_pressed; i++) {
+		for (j = (i + 1); j < nkey_pressed; j++) {
+			if (prows[i] == prows[j]) {
+				for (k = 0; k < nkey_pressed; k++) {
+					if (k == i)
+						continue;
+
+					if (pcols[i] == pcols[k]) {
+						filter_keys[0] = k;
+						is_filtered = true;
+					}
+				}
+				for (k = 0; k < nkey_pressed; k++) {
+					if (k == j)
+						continue;
+					if (pcols[j] == pcols[k]) {
+						filter_keys[1] = k;
+						is_filtered = true;
+					}
+				}
+				goto end;
+			}
+		}
+	}
+
+end:
+	if (is_filtered) {
+		for (i = filter_keys[0]; i < (nkey_pressed - 1); i++) {
+			prows[i] = prows[i+1];
+			pcols[i] = pcols[i+1];
+		}
+		new_key_press_count--;
+		for (i = filter_keys[1]; i < (nkey_pressed - 1); i++) {
+			prows[i] = prows[i+1];
+			pcols[i] = pcols[i+1];
+		}
+		new_key_press_count--;
+	}
+	nkey_pressed = new_key_press_count;
+	return new_key_press_count;
+}
+
+static int tegra_kbc_keycode(struct tegra_kbc *kbc, int r, int c, bool fn_key)
+{
+	int code_index = kbc->row_seq[r] * kbc->ncols + kbc->col_seq[c];
+	if (!fn_key)
+		return kbc->plain_keycode[code_index];
+	else
+		return kbc->fn_keycode[code_index];
+}
+
+static void tegra_kbc_report_keys(struct tegra_kbc *kbc, int *fifo)
+{
+	int curr_fifo[KBC_MAX_KPRESS_EVENT];
+	int rows_val[KBC_MAX_KPRESS_EVENT], cols_val[KBC_MAX_KPRESS_EVENT];
+	u32 kp_ent_val[(KBC_MAX_KPRESS_EVENT + 3) / 4];
+	u32 *kp_ents = kp_ent_val;
+	u32 kp_ent = 0;
+	unsigned long flags;
+	int i, j, valid = 0;
+	bool fn = false;
+
+	dev_dbg(kbc->dev, "KBC: tegra_kbc_report_keys\n");
+
+	local_irq_save(flags);
+	for (i = 0; i < ARRAY_SIZE(kp_ent_val); i++)
+		kp_ent_val[i] = readl(kbc->mmio + KBC_KP_ENT0_0 + (i*4));
+	local_irq_restore(flags);
+
+	valid = 0;
+	for (i = 0; i < KBC_MAX_KPRESS_EVENT; i++) {
+		if (!(i&3))
+			kp_ent = *kp_ents++;
+
+		if (kp_ent & 0x80) {
+			cols_val[valid] = kp_ent & 0x7;
+			rows_val[valid++] = (kp_ent >> 3) & 0xf;
+		}
+		kp_ent >>= 8;
+	}
+
+	if (kbc->pdata->is_filter_keys)
+		valid = tegra_kbc_filter_keys(kbc, rows_val, cols_val, valid);
+
+	for (i = 0; i < valid; i++) {
+		int k = tegra_kbc_keycode(kbc, rows_val[i], cols_val[i], false);
+		if (k == KEY_FN) {
+			fn = true;
+			break;
+		}
+	}
+
+	j = 0;
+	for (i = 0; i < valid; i++) {
+		int k = tegra_kbc_keycode(kbc, rows_val[i], cols_val[i], fn);
+		if (likely(k != -1))
+			curr_fifo[j++] = k;
+	}
+	valid = j;
+
+	for (i = 0; i < KBC_MAX_KPRESS_EVENT; i++) {
+		if (fifo[i] == -1)
+			continue;
+		for (j = 0; j < valid; j++) {
+			if (curr_fifo[j] == fifo[i]) {
+				curr_fifo[j] = -1;
+				break;
+			}
+		}
+		if (j == valid) {
+			input_report_key(kbc->idev, fifo[i], 0);
+			fifo[i] = -1;
+		}
+	}
+	for (j = 0; j < valid; j++) {
+		if (curr_fifo[j] == -1)
+			continue;
+		for (i = 0; i < KBC_MAX_KPRESS_EVENT; i++) {
+			if (fifo[i] == -1)
+				break;
+		}
+		if (i != KBC_MAX_KPRESS_EVENT) {
+			fifo[i] = curr_fifo[j];
+			input_report_key(kbc->idev, fifo[i], 1);
+		} else
+			WARN_ON(1);
+	}
+}
+
+static void tegra_kbc_key_repeat(struct work_struct *work)
+{
+	struct tegra_kbc *kbc;
+	unsigned long flags;
+	u32 val;
+	int fifo[KBC_MAX_KPRESS_EVENT];
+	int i;
+
+	kbc = container_of(work, struct tegra_kbc, key_repeat);
+	dev_dbg(kbc->dev, "KBC: tegra_kbc_key_repeat\n");
+
+	for (i = 0; i < ARRAY_SIZE(fifo); i++)
+		fifo[i] = -1;
+
+	while (1) {
+		val = (readl(kbc->mmio + KBC_INT_0) >> 4) & 0xf;
+		if (!val) {
+			/* release any pressed keys and exit the loop */
+			for (i = 0; i < ARRAY_SIZE(fifo); i++) {
+				if (fifo[i] == -1)
+					continue;
+				input_report_key(kbc->idev, fifo[i], 0);
+			}
+			break;
+		}
+		tegra_kbc_report_keys(kbc, fifo);
+		msleep((val == 1) ? kbc->repoll_time : 1);
+	}
+
+	spin_lock_irqsave(&kbc->lock, flags);
+	val = readl(kbc->mmio + KBC_CONTROL_0);
+	val |= (1<<3);
+	writel(val, kbc->mmio + KBC_CONTROL_0);
+	spin_unlock_irqrestore(&kbc->lock, flags);
+}
+
+static void tegra_kbc_close(struct input_dev *dev)
+{
+	struct tegra_kbc *kbc = input_get_drvdata(dev);
+	unsigned long flags;
+	u32 val;
+
+	dev_dbg(kbc->dev, "KBC: tegra_kbc_close\n");
+
+	spin_lock_irqsave(&kbc->lock, flags);
+	val = readl(kbc->mmio + KBC_CONTROL_0);
+	val &= ~1;
+	writel(val, kbc->mmio + KBC_CONTROL_0);
+	spin_unlock_irqrestore(&kbc->lock, flags);
+
+	clk_disable(kbc->clk);
+}
+
+static void tegra_kbc_setup_wakekeys(struct tegra_kbc *kbc, bool filter)
+{
+	int i;
+	unsigned int rst_val;
+
+	dev_dbg(kbc->dev, "KBC: tegra_kbc_setup_wakekeys\n");
+
+	BUG_ON(kbc->pdata->wake_key_cnt > KBC_MAX_KEY);
+	rst_val = (filter && (kbc->pdata->wake_key_cnt ||
+				kbc->pdata->is_wake_on_any_key)) ? ~0 : 0;
+
+	for (i = 0; i < KBC_MAX_ROW; i++)
+		writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
+
+	if (filter) {
+		for (i = 0; i < KBC_MAX_ROW; i++) {
+			if (kbc->wake_enable_keys[i] != rst_val)
+				writel(kbc->wake_enable_keys[i],
+					kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
+		}
+	}
+}
+
+static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
+{
+	const struct tegra_kbc_platform_data *pdata = kbc->pdata;
+	int i;
+	unsigned int row_config[4];
+	unsigned int col_config[3];
+
+	dev_dbg(kbc->dev, "KBC: tegra_kbc_config_pins\n");
+	for (i = 0; i < 4; i++)
+		row_config[i] = 0;
+	for (i = 0; i < 3; i++)
+		col_config[i] = 0;
+
+	for (i = 0; i < KBC_MAX_GPIO; i++) {
+		u32 r_shift = 5 * (pdata->pin_cfg[i].num % 6);
+		u32 c_shift = 4 * (pdata->pin_cfg[i].num % 8);
+		u32 r_mask = 0x1f << r_shift;
+		u32 c_mask = 0xf << c_shift;
+		u32 index;
+
+		if (pdata->pin_cfg[i].pin_type == kbc_pin_unused)
+			continue;
+
+		if (pdata->pin_cfg[i].pin_type == kbc_pin_row) {
+			index = pdata->pin_cfg[i].num / 6;
+			row_config[index] &= ~r_mask;
+			row_config[index] |=
+				((pdata->pin_cfg[i].num << 1) | 1) << r_shift;
+		} else {
+			index = (pdata->pin_cfg[i].num + KBC_MAX_ROW) / 8;
+			col_config[index] &= ~c_mask;
+			col_config[index] |=
+				((pdata->pin_cfg[i].num << 1) | 1) << c_shift;
+		}
+	}
+	for (i = 0; i < 4; i++) {
+		u32 r_offs = i * 4 + KBC_ROW_CFG0_0;
+		writel(row_config[i], kbc->mmio + r_offs);
+	}
+	for (i = 0; i < 3; i++) {
+		u32 c_offs = i * 4 + KBC_COL_CFG0_0;
+		writel(col_config[i], kbc->mmio + c_offs);
+	}
+}
+
+static int tegra_kbc_open(struct input_dev *dev)
+{
+	struct tegra_kbc *kbc = input_get_drvdata(dev);
+	unsigned long flags;
+	u32 val = 0;
+
+	dev_dbg(kbc->dev, "KBC: tegra_kbc_open\n");
+
+	clk_enable(kbc->clk);
+
+	/* Reset the KBC controller to clear all previous status.*/
+	tegra_periph_reset_assert(kbc->clk);
+	udelay(100);
+	tegra_periph_reset_deassert(kbc->clk);
+	udelay(100);
+
+	tegra_kbc_config_pins(kbc);
+	tegra_kbc_setup_wakekeys(kbc, false);
+
+	writel(kbc->pdata->repeat_cnt, kbc->mmio + KBC_RPT_DLY_0);
+
+	val = kbc->pdata->debounce_cnt << 4;
+	val |= 1<<14; /* fifo interrupt threshold = 1 entry */
+	val |= 1<<3;  /* interrupt on FIFO threshold reached */
+	val |= 1;     /* enable */
+	writel(val, kbc->mmio + KBC_CONTROL_0);
+
+	/* Bit 19:0 is for scan timeout count */
+	kbc->pdata->scan_timeout_cnt &= 0xFFFFF;
+	writel(kbc->pdata->scan_timeout_cnt, kbc->mmio + KBC_TO_CNT_0);
+
+	/* atomically clear out any remaining entries in the key FIFO
+	 * and enable keyboard interrupts */
+	spin_lock_irqsave(&kbc->lock, flags);
+
+	while (1) {
+		val = readl(kbc->mmio + KBC_INT_0);
+		val >>= 4;
+		if (val) {
+			val = readl(kbc->mmio + KBC_KP_ENT0_0);
+			val = readl(kbc->mmio + KBC_KP_ENT1_0);
+		} else {
+			break;
+		}
+	}
+	writel(0x7, kbc->mmio + KBC_INT_0);
+	spin_unlock_irqrestore(&kbc->lock, flags);
+	return 0;
+}
+
+static irqreturn_t tegra_kbc_isr(int irq, void *args)
+{
+	struct tegra_kbc *kbc = args;
+	u32 val, ctl;
+
+	dev_dbg(kbc->dev, "KBC: tegra_kbc_isr\n");
+
+	/* until all keys are released, defer further processing to
+	 * the polling loop in tegra_kbc_key_repeat */
+	ctl = readl(kbc->mmio + KBC_CONTROL_0);
+	ctl &= ~(1<<3);
+	writel(ctl, kbc->mmio + KBC_CONTROL_0);
+
+	/* quickly bail out & reenable interrupts if the interrupt source
+	 * wasn't fifo count threshold */
+	val = readl(kbc->mmio + KBC_INT_0);
+	writel(val, kbc->mmio + KBC_INT_0);
+
+	if (!(val & (1<<2))) {
+		ctl |= 1<<3;
+		writel(ctl, kbc->mmio + KBC_CONTROL_0);
+		return IRQ_HANDLED;
+	}
+
+	queue_work(kbc->kbc_work_queue, &kbc->key_repeat);
+	return IRQ_HANDLED;
+}
+
+static int __devinit tegra_kbc_probe(struct platform_device *pdev)
+{
+	struct tegra_kbc *kbc;
+	struct tegra_kbc_platform_data *pdata = pdev->dev.platform_data;
+	struct resource *res;
+	int irq;
+	int err;
+	int rows[KBC_MAX_ROW];
+	int cols[KBC_MAX_COL];
+	int i, j;
+	int nr = 0;
+	int nc = 0;
+	char name[64];
+
+	dev_dbg(&pdev->dev, "KBC: tegra_kbc_probe\n");
+
+	if (!pdata)
+		return -EINVAL;
+
+	/* Validate the data entry */
+	if (!pdata->plain_keycode) {
+		dev_err(&pdev->dev, "No key codes\n");
+		return -EINVAL;
+	}
+
+	for (i = 0; i < KBC_MAX_GPIO; i++) {
+		if ((pdata->pin_cfg[i].pin_type == kbc_pin_row) &&
+			(pdata->pin_cfg[i].num >= KBC_MAX_ROW)) {
+				dev_err(&pdev->dev, "Invalid row number\n");
+				return -EINVAL;
+		} else if ((pdata->pin_cfg[i].pin_type == kbc_pin_col) &&
+			(pdata->pin_cfg[i].num >= KBC_MAX_COL)) {
+				dev_err(&pdev->dev, "Invalid column number\n");
+				return -EINVAL;
+		}
+	}
+
+	kbc = kzalloc(sizeof(*kbc), GFP_KERNEL);
+	if (!kbc)
+		return -ENOMEM;
+
+	kbc->pdata = pdata;
+	kbc->irq = -EINVAL;
+
+	memset(rows, 0, sizeof(rows));
+	memset(cols, 0, sizeof(cols));
+
+	kbc->idev = input_allocate_device();
+	if (!kbc->idev) {
+		err = -ENOMEM;
+		goto fail;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to get I/O memory\n");
+		err = -ENXIO;
+		goto fail;
+	}
+	res = request_mem_region(res->start, res_size(res), pdev->name);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to request I/O memory\n");
+		err = -EBUSY;
+		goto fail;
+	}
+	kbc->mmio = ioremap(res->start, res_size(res));
+	if (!kbc->mmio) {
+		dev_err(&pdev->dev, "failed to remap I/O memory\n");
+		err = -ENXIO;
+		goto fail;
+	}
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "failed to get keypad IRQ\n");
+		err = -ENXIO;
+		goto fail;
+	}
+	kbc->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR_OR_NULL(kbc->clk)) {
+		dev_err(&pdev->dev, "failed to get keypad clock\n");
+		err = (kbc->clk) ? PTR_ERR(kbc->clk) : -ENODEV;
+		kbc->clk = NULL;
+		goto fail;
+	}
+
+	platform_set_drvdata(pdev, kbc);
+
+	kbc->dev = &pdev->dev;
+	kbc->idev->name = pdev->name;
+	input_set_drvdata(kbc->idev, kbc);
+	kbc->idev->id.bustype = BUS_HOST;
+	kbc->idev->open = tegra_kbc_open;
+	kbc->idev->close = tegra_kbc_close;
+	kbc->idev->dev.parent = &pdev->dev;
+	spin_lock_init(&kbc->lock);
+
+	for (i = 0; i < KBC_MAX_GPIO; i++) {
+		if (pdata->pin_cfg[i].pin_type == kbc_pin_row) {
+			rows[pdata->pin_cfg[i].num] = 1;
+			kbc->row_seq[pdata->pin_cfg[i].num] = nr++;
+		} else if (pdata->pin_cfg[i].pin_type == kbc_pin_col) {
+			cols[pdata->pin_cfg[i].num] = 1;
+			kbc->col_seq[pdata->pin_cfg[i].num] = nc++;
+		}
+	}
+	kbc->ncols = nc;
+
+	for (i = 0; i < pdata->wake_key_cnt; i++)
+		kbc->wake_enable_keys[i] = ~0u;
+
+	for (i = 0; i < pdata->wake_key_cnt; i++)
+		kbc->wake_enable_keys[kbc->pdata->wake_cfg[i].row] &=
+					~(1 << kbc->pdata->wake_cfg[i].col);
+
+	pdata->debounce_cnt = min_t(unsigned int, pdata->debounce_cnt, 0x3fful);
+	kbc->repoll_time = 5 + (16+pdata->debounce_cnt)*nr + pdata->repeat_cnt;
+	kbc->repoll_time = (kbc->repoll_time + 31) / 32;
+
+	kbc->plain_keycode = pdata->plain_keycode;
+	kbc->fn_keycode = pdata->fn_keycode;
+
+	kbc->idev->evbit[0] = BIT_MASK(EV_KEY);
+	for (i = 0; i < KBC_MAX_ROW; i++) {
+		if (!rows[i])
+			continue;
+		for (j = 0; j < KBC_MAX_COL; j++) {
+			int keycode;
+			if (!cols[j])
+				continue;
+			keycode = tegra_kbc_keycode(kbc, i, j, false);
+			if (keycode == KEY_RESERVED)
+				continue;
+			set_bit(keycode, kbc->idev->keybit);
+		}
+	}
+
+	/* create the workqueue for the kbc path */
+	snprintf(name, sizeof(name), "tegra-kbc");
+	kbc->kbc_work_queue = create_singlethread_workqueue(name);
+	if (kbc->kbc_work_queue == NULL) {
+		dev_err(&pdev->dev, "Failed to create work queue\n");
+		err = -ENODEV;
+		goto fail;
+	}
+
+	/* keycode FIFO needs to be read atomically; leave local
+	 * interrupts disabled when handling KBC interrupt */
+	INIT_WORK(&kbc->key_repeat, tegra_kbc_key_repeat);
+
+	err = request_irq(irq, tegra_kbc_isr, IRQF_DISABLED, pdev->name, kbc);
+	if (err) {
+		dev_err(&pdev->dev, "failed to request keypad IRQ\n");
+		goto fail;
+	}
+	kbc->irq = irq;
+
+	err = input_register_device(kbc->idev);
+	if (err) {
+		dev_err(&pdev->dev, "failed to register input device\n");
+		goto fail;
+	}
+
+	device_init_wakeup(&pdev->dev, 1);
+	return 0;
+
+fail:
+	if (kbc->irq >= 0)
+		free_irq(kbc->irq, pdev);
+	if (kbc->idev)
+		input_free_device(kbc->idev);
+	if (kbc->clk)
+		clk_put(kbc->clk);
+	if (kbc->mmio)
+		iounmap(kbc->mmio);
+	if (kbc->kbc_work_queue)
+		destroy_workqueue(kbc->kbc_work_queue);
+	kfree(kbc);
+
+	return err;
+}
+
+static int __devexit tegra_kbc_remove(struct platform_device *pdev)
+{
+	struct tegra_kbc *kbc = platform_get_drvdata(pdev);
+	struct resource *res;
+
+	dev_dbg(kbc->dev, "KBC: tegra_kbc_remove\n");
+
+	free_irq(kbc->irq, pdev);
+	clk_disable(kbc->clk);
+	clk_put(kbc->clk);
+
+	input_unregister_device(kbc->idev);
+	input_free_device(kbc->idev);
+	iounmap(kbc->mmio);
+	destroy_workqueue(kbc->kbc_work_queue);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(res->start, res_size(res));
+
+	kfree(kbc);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int tegra_kbc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct tegra_kbc *kbc = platform_get_drvdata(pdev);
+
+	dev_dbg(&pdev->dev, "KBC: tegra_kbc_suspend\n");
+	if (device_may_wakeup(&pdev->dev) &&
+		(kbc->pdata->is_wake_on_any_key || kbc->pdata->wake_key_cnt)) {
+		tegra_kbc_setup_wakekeys(kbc, true);
+		enable_irq_wake(kbc->irq);
+		/* Forcefully clear the interrupt status */
+		writel(0x7, kbc->mmio + KBC_INT_0);
+		msleep(30);
+	} else {
+		tegra_kbc_close(kbc->idev);
+	}
+	return 0;
+}
+
+static int tegra_kbc_resume(struct platform_device *pdev)
+{
+	struct tegra_kbc *kbc = platform_get_drvdata(pdev);
+
+	dev_dbg(&pdev->dev, "KBC: tegra_kbc_resume\n");
+
+	if (device_may_wakeup(&pdev->dev)) {
+		disable_irq_wake(kbc->irq);
+		tegra_kbc_setup_wakekeys(kbc, false);
+	} else if (kbc->idev->users)
+		return tegra_kbc_open(kbc->idev);
+
+	return 0;
+}
+#endif
+
+static struct platform_driver tegra_kbc_driver = {
+	.probe   = tegra_kbc_probe,
+	.remove  = tegra_kbc_remove,
+#ifdef CONFIG_PM
+	.suspend = tegra_kbc_suspend,
+	.resume  = tegra_kbc_resume,
+#endif
+	.driver = {
+		.name = "tegra-kbc"
+	}
+};
+
+static int __devinit tegra_kbc_init(void)
+{
+	pr_debug("KBC: tegra_kbc_init\n");
+	return platform_driver_register(&tegra_kbc_driver);
+}
+
+static void __exit tegra_kbc_exit(void)
+{
+	pr_debug("KBC: tegra_kbc_exit\n");
+	platform_driver_unregister(&tegra_kbc_driver);
+}
+
+module_init(tegra_kbc_init);
+module_exit(tegra_kbc_exit);
+
+MODULE_DESCRIPTION("Tegra matrix keyboard controller driver");
diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
index 263471a905f7..37f843e95af0 100644
--- a/drivers/input/misc/Kconfig
+++ b/drivers/input/misc/Kconfig
@@ -454,4 +454,20 @@ config INPUT_ADXL34X_SPI
 	  To compile this driver as a module, choose M here: the
 	  module will be called adxl34x-spi.
 
+config INPUT_ALPS_GPIO_SCROLLWHEEL
+	tristate "Alps GPIO Scrollwheel"
+	depends on GENERIC_GPIO
+	help
+	  This driver implements support for Alps SRBE
+          ScrollWheel connected to GPIO pins of various
+          CPUs (and some other chips).
+
+	  Say Y here if your device has ScrollWheel connected
+	  directly to such GPIO pins.  Your board-specific
+	  setup logic must also provide a platform device,
+	  with configuration data saying which GPIOs are used.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called alps_gpio_scrollwheel.
+
 endif
diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
index 7ac4ca759999..bc875ba892da 100644
--- a/drivers/input/misc/Makefile
+++ b/drivers/input/misc/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_INPUT_AD714X_SPI)		+= ad714x-spi.o
 obj-$(CONFIG_INPUT_ADXL34X)		+= adxl34x.o
 obj-$(CONFIG_INPUT_ADXL34X_I2C)		+= adxl34x-i2c.o
 obj-$(CONFIG_INPUT_ADXL34X_SPI)		+= adxl34x-spi.o
+obj-$(CONFIG_INPUT_ALPS_GPIO_SCROLLWHEEL) += alps_gpio_scrollwheel.o
 obj-$(CONFIG_INPUT_APANEL)		+= apanel.o
 obj-$(CONFIG_INPUT_ATI_REMOTE)		+= ati_remote.o
 obj-$(CONFIG_INPUT_ATI_REMOTE2)		+= ati_remote2.o
diff --git a/drivers/input/misc/alps_gpio_scrollwheel.c b/drivers/input/misc/alps_gpio_scrollwheel.c
new file mode 100644
index 000000000000..4a789267c475
--- /dev/null
+++ b/drivers/input/misc/alps_gpio_scrollwheel.c
@@ -0,0 +1,428 @@
+/*
+ * kernel/drivers/input/misc/alps_gpio_scrollwheel.c
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * Driver for ScrollWheel on GPIO lines capable of generating interrupts.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/sched.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/sysctl.h>
+#include <linux/proc_fs.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/gpio_scrollwheel.h>
+#include <linux/workqueue.h>
+#include <linux/gpio.h>
+
+struct scrollwheel_button_data {
+	struct gpio_scrollwheel_button *button;
+	struct input_dev *input;
+	struct timer_list timer;
+	struct work_struct work;
+	int timer_debounce;	/* in msecs */
+	int rotgpio;
+	bool disabled;
+};
+
+struct gpio_scrollwheel_drvdata {
+	struct input_dev *input;
+	struct mutex disable_lock;
+	unsigned int n_buttons;
+	int (*enable)(struct device *dev);
+	void (*disable)(struct device *dev);
+	struct scrollwheel_button_data data[0];
+};
+
+static void scrollwheel_report_key(struct scrollwheel_button_data *bdata)
+{
+	struct gpio_scrollwheel_button *button = bdata->button;
+	struct input_dev *input = bdata->input;
+	int state = (gpio_get_value(button->gpio) ? 1 : 0) ^ \
+				button->active_low;
+	int state2 = 0;
+
+	switch (button->pinaction) {
+	case GPIO_SCROLLWHEEL_PIN_PRESS:
+		input_report_key(input, KEY_ENTER, 1);
+		input_report_key(input, KEY_ENTER, 0);
+		input_sync(input);
+		break;
+
+	case GPIO_SCROLLWHEEL_PIN_ROT1:
+	case GPIO_SCROLLWHEEL_PIN_ROT2:
+		state2 = (gpio_get_value(bdata->rotgpio) ? 1 : 0) \
+					^ button->active_low;
+		if (state != state2) {
+			input_report_key(input, KEY_DOWN, 1);
+			input_report_key(input, KEY_DOWN, 0);
+		} else {
+			input_report_key(input, KEY_UP, 1);
+			input_report_key(input, KEY_UP, 0);
+		}
+		input_sync(input);
+		break;
+
+	default:
+		pr_err("%s:Line=%d, Invalid Pinaction\n", __func__, __LINE__);
+	}
+}
+
+static void scrollwheel_work_func(struct work_struct *work)
+{
+	struct scrollwheel_button_data *bdata =
+		container_of(work, struct scrollwheel_button_data, work);
+
+	scrollwheel_report_key(bdata);
+}
+
+static void scrollwheel_timer(unsigned long _data)
+{
+	struct scrollwheel_button_data *data = \
+		(struct scrollwheel_button_data *)_data;
+
+	schedule_work(&data->work);
+}
+
+static irqreturn_t scrollwheel_isr(int irq, void *dev_id)
+{
+	struct scrollwheel_button_data *bdata = dev_id;
+	struct gpio_scrollwheel_button *button = bdata->button;
+
+	BUG_ON(irq != gpio_to_irq(button->gpio));
+
+	if (bdata->timer_debounce)
+		mod_timer(&bdata->timer,
+			jiffies + msecs_to_jiffies(bdata->timer_debounce));
+	else
+		schedule_work(&bdata->work);
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit gpio_scrollwheel_setup_key(struct platform_device *pdev,
+			struct scrollwheel_button_data *bdata,
+			struct gpio_scrollwheel_button *button)
+{
+	char *desc = button->desc ? button->desc : "gpio_scrollwheel";
+	struct device *dev = &pdev->dev;
+	unsigned long irqflags;
+	int irq, error;
+
+	setup_timer(&bdata->timer, scrollwheel_timer, (unsigned long)bdata);
+	INIT_WORK(&bdata->work, scrollwheel_work_func);
+
+	error = gpio_request(button->gpio, desc);
+	if (error < 0) {
+		dev_err(dev, "failed to request GPIO %d, error %d\n",
+			button->gpio, error);
+		return error;
+	}
+
+	error = gpio_direction_input(button->gpio);
+	if (error < 0) {
+		dev_err(dev, "failed to configure"
+			" direction for GPIO %d, error %d\n",
+			button->gpio, error);
+		goto fail;
+	}
+
+	if (button->debounce_interval) {
+		error = gpio_set_debounce(button->gpio,
+					  button->debounce_interval * 1000);
+		/* use timer if gpiolib doesn't provide debounce */
+		if (error < 0)
+			bdata->timer_debounce = button->debounce_interval;
+	}
+
+	irq = gpio_to_irq(button->gpio);
+	if (irq < 0) {
+		error = irq;
+		dev_err(dev, "Unable to get irq no for GPIO %d, error %d\n",
+			button->gpio, error);
+		goto fail;
+	}
+
+	irqflags = IRQF_TRIGGER_FALLING;
+
+	error = request_irq(irq, scrollwheel_isr, irqflags, desc, bdata);
+	if (error) {
+		dev_err(dev, "Unable to claim irq %d; error %d\n",
+			irq, error);
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	return error;
+}
+
+static int gpio_scrollwheel_open(struct input_dev *input)
+{
+	struct gpio_scrollwheel_drvdata *ddata = input_get_drvdata(input);
+
+	return ddata->enable ? ddata->enable(input->dev.parent) : 0;
+}
+
+static void gpio_scrollwheel_close(struct input_dev *input)
+{
+	struct gpio_scrollwheel_drvdata *ddata = input_get_drvdata(input);
+
+	if (ddata->disable)
+		ddata->disable(input->dev.parent);
+}
+
+static int __devinit gpio_scrollwheel_probe(struct platform_device *pdev)
+{
+	struct gpio_scrollwheel_platform_data *pdata = pdev->dev.platform_data;
+	struct gpio_scrollwheel_drvdata *ddata;
+	struct device *dev = &pdev->dev;
+	struct input_dev *input;
+	int i, error;
+
+	ddata = kzalloc(sizeof(struct gpio_scrollwheel_drvdata) +
+		pdata->nbuttons * sizeof(struct scrollwheel_button_data),
+		GFP_KERNEL);
+	if (ddata == NULL) {
+		dev_err(dev, "failed to allocate memory\n");
+		error = -ENOMEM;
+		return error;
+	}
+
+	input = input_allocate_device();
+	if (input == NULL) {
+		dev_err(dev, "failed to allocate input device\n");
+		error = -ENOMEM;
+		kfree(ddata);
+		return error;
+	}
+
+	ddata->input = input;
+	ddata->n_buttons = pdata->nbuttons;
+	ddata->enable = pdata->enable;
+	ddata->disable = pdata->disable;
+	mutex_init(&ddata->disable_lock);
+
+	platform_set_drvdata(pdev, ddata);
+	input_set_drvdata(input, ddata);
+
+	input->name = pdev->name;
+	input->phys = "gpio-scrollwheel/input0";
+	input->dev.parent = &pdev->dev;
+	input->open = gpio_scrollwheel_open;
+	input->close = gpio_scrollwheel_close;
+
+	input->id.bustype = BUS_HOST;
+	input->id.vendor = 0x0001;
+	input->id.product = 0x0001;
+	input->id.version = 0x0100;
+
+	/* Enable auto repeat feature of Linux input subsystem */
+	if (pdata->rep)
+		__set_bit(EV_REP, input->evbit);
+
+	for (i = 0; i < pdata->nbuttons; i++) {
+		struct gpio_scrollwheel_button *button = &pdata->buttons[i];
+		struct scrollwheel_button_data *bdata = &ddata->data[i];
+
+		bdata->input = input;
+		bdata->button = button;
+
+		if (button->pinaction == GPIO_SCROLLWHEEL_PIN_PRESS ||
+			button->pinaction == GPIO_SCROLLWHEEL_PIN_ROT1) {
+			error = gpio_scrollwheel_setup_key(pdev, bdata, button);
+			if (error)
+				goto fail;
+		} else {
+			if (button->pinaction == GPIO_SCROLLWHEEL_PIN_ONOFF) {
+				gpio_request(button->gpio, button->desc);
+				gpio_direction_output(button->gpio, 0);
+			}
+
+			if (button->pinaction == GPIO_SCROLLWHEEL_PIN_ROT2) {
+				gpio_request(button->gpio, button->desc);
+				gpio_direction_input(button->gpio);
+				/* Save rot2 gpio number in rot1 context */
+				ddata->data[2].rotgpio = button->gpio;
+			}
+		}
+	}
+
+	/* set input capability */
+	__set_bit(EV_KEY, input->evbit);
+	__set_bit(KEY_ENTER, input->keybit);
+	__set_bit(KEY_UP, input->keybit);
+	__set_bit(KEY_DOWN, input->keybit);
+
+	error = input_register_device(input);
+	if (error) {
+		dev_err(dev, "Unable to register input device, error: %d\n",
+			error);
+		goto fail;
+	}
+
+	input_sync(input);
+
+	return 0;
+
+fail:
+	while (--i >= 0) {
+		if (pdata->buttons[i].pinaction == GPIO_SCROLLWHEEL_PIN_PRESS ||
+			pdata->buttons[i].pinaction == GPIO_SCROLLWHEEL_PIN_ROT1) {
+			free_irq(gpio_to_irq(pdata->buttons[i].gpio), &ddata->data[i]);
+			if (ddata->data[i].timer_debounce)
+				del_timer_sync(&ddata->data[i].timer);
+			cancel_work_sync(&ddata->data[i].work);
+		}
+		gpio_free(pdata->buttons[i].gpio);
+	}
+
+	platform_set_drvdata(pdev, NULL);
+	input_free_device(input);
+	kfree(ddata);
+	return error;
+}
+
+static int __devexit gpio_scrollwheel_remove(struct platform_device *pdev)
+{
+	struct gpio_scrollwheel_platform_data *pdata = pdev->dev.platform_data;
+	struct gpio_scrollwheel_drvdata *ddata = platform_get_drvdata(pdev);
+	struct input_dev *input = ddata->input;
+	int i;
+
+	for (i = 0; i < pdata->nbuttons; i++) {
+		if (pdata->buttons[i].pinaction == GPIO_SCROLLWHEEL_PIN_PRESS ||
+			pdata->buttons[i].pinaction == GPIO_SCROLLWHEEL_PIN_ROT1) {
+			int irq = gpio_to_irq(pdata->buttons[i].gpio);
+			free_irq(irq, &ddata->data[i]);
+			if (ddata->data[i].timer_debounce)
+				del_timer_sync(&ddata->data[i].timer);
+			cancel_work_sync(&ddata->data[i].work);
+		}
+		gpio_free(pdata->buttons[i].gpio);
+	}
+
+	input_unregister_device(input);
+
+	return 0;
+}
+
+
+#ifdef CONFIG_PM
+static int gpio_scrollwheel_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct gpio_scrollwheel_platform_data *pdata = pdev->dev.platform_data;
+	struct gpio_scrollwheel_drvdata *ddata = platform_get_drvdata(pdev);
+	int i, irq;
+
+	for (i = 0; i < pdata->nbuttons; i++) {
+		if (pdata->buttons[i].pinaction == GPIO_SCROLLWHEEL_PIN_PRESS ||
+			pdata->buttons[i].pinaction == GPIO_SCROLLWHEEL_PIN_ROT1) {
+			irq = gpio_to_irq(pdata->buttons[i].gpio);
+			disable_irq(irq);
+			if (ddata->data[i].timer_debounce)
+				del_timer_sync(&ddata->data[i].timer);
+			cancel_work_sync(&ddata->data[i].work);
+		} else {
+			if (pdata->buttons[i].pinaction == GPIO_SCROLLWHEEL_PIN_ONOFF)
+				gpio_direction_output(pdata->buttons[i].gpio, 1);
+			else {
+				irq = gpio_to_irq(pdata->buttons[i].gpio);
+				disable_irq(irq);
+			}
+		}
+	}
+	return 0;
+}
+
+static int gpio_scrollwheel_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct gpio_scrollwheel_platform_data *pdata = pdev->dev.platform_data;
+	struct gpio_scrollwheel_drvdata *ddata = platform_get_drvdata(pdev);
+	int i, irq;
+
+	for (i = 0; i < pdata->nbuttons; i++) {
+		if (pdata->buttons[i].pinaction == GPIO_SCROLLWHEEL_PIN_PRESS ||
+			pdata->buttons[i].pinaction == GPIO_SCROLLWHEEL_PIN_ROT1) {
+			irq = gpio_to_irq(pdata->buttons[i].gpio);
+			enable_irq(irq);
+			if (ddata->data[i].timer_debounce)
+				setup_timer(&ddata->data[i].timer,\
+				scrollwheel_timer, (unsigned long)&ddata->data[i]);
+
+			INIT_WORK(&ddata->data[i].work, scrollwheel_work_func);
+		} else {
+			if (pdata->buttons[i].pinaction == GPIO_SCROLLWHEEL_PIN_ONOFF)
+				gpio_direction_output(pdata->buttons[i].gpio, 0);
+			else {
+				irq = gpio_to_irq(pdata->buttons[i].gpio);
+				enable_irq(irq);
+			}
+		}
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops gpio_scrollwheel_pm_ops = {
+	.suspend	= gpio_scrollwheel_suspend,
+	.resume		= gpio_scrollwheel_resume,
+};
+#endif
+
+static struct platform_driver gpio_scrollwheel_device_driver = {
+	.probe		= gpio_scrollwheel_probe,
+	.remove		= __devexit_p(gpio_scrollwheel_remove),
+	.driver		= {
+		.name	= "alps-gpio-scrollwheel",
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &gpio_scrollwheel_pm_ops,
+#endif
+	}
+};
+
+static int __init gpio_scrollwheel_init(void)
+{
+	return platform_driver_register(&gpio_scrollwheel_device_driver);
+}
+
+static void __exit gpio_scrollwheel_exit(void)
+{
+	platform_driver_unregister(&gpio_scrollwheel_device_driver);
+}
+
+module_init(gpio_scrollwheel_init);
+module_exit(gpio_scrollwheel_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("NVIDIA Corporation");
+MODULE_DESCRIPTION("Alps SRBE ScrollWheel driver");
+
+MODULE_ALIAS("platform:alps-gpio-scrollwheel");
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index d50fd5603604..f7c25b2b7ed6 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -383,6 +383,13 @@ config TOUCHSCREEN_ATMEL_TSADCC
 	  To compile this driver as a module, choose M here: the
 	  module will be called atmel_tsadcc.
 
+config TOUCHSCREEN_ATMEL_MT_T9
+	tristate "Atmel Touchscreen Interface"
+	depends on I2C
+	help
+	  To compile this driver as a module, choose M here: the
+	  module will be called atmel_tsadcc.
+
 config TOUCHSCREEN_UCB1400
 	tristate "Philips UCB1400 touchscreen"
 	depends on AC97_BUS
diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
index 93e641bc320e..b588efc90bf8 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_TOUCHSCREEN_AD7879_I2C)	+= ad7879-i2c.o
 obj-$(CONFIG_TOUCHSCREEN_AD7879_SPI)	+= ad7879-spi.o
 obj-$(CONFIG_TOUCHSCREEN_ADS7846)	+= ads7846.o
 obj-$(CONFIG_TOUCHSCREEN_ATMEL_TSADCC)	+= atmel_tsadcc.o
+obj-$(CONFIG_TOUCHSCREEN_ATMEL_MT_T9)   += atmel_maxtouch.o
 obj-$(CONFIG_TOUCHSCREEN_BITSY)		+= h3600_ts_input.o
 obj-$(CONFIG_TOUCHSCREEN_CY8CTMG110)	+= cy8ctmg110_ts.o
 obj-$(CONFIG_TOUCHSCREEN_DA9034)	+= da9034-ts.o
diff --git a/drivers/input/touchscreen/atmel_maxtouch.c b/drivers/input/touchscreen/atmel_maxtouch.c
new file mode 100755
index 000000000000..44ef974575d1
--- /dev/null
+++ b/drivers/input/touchscreen/atmel_maxtouch.c
@@ -0,0 +1,2056 @@
+/*
+ *  Atmel maXTouch Touchscreen Controller
+ *
+ *
+ *  Copyright (C) 2010 Atmel Corporation
+ *  Copyright (C) 2009 Raphael Derosso Pereira <raphaelpereira@gmail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/debugfs.h>
+#include <linux/cdev.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+
+#include <linux/uaccess.h>
+
+#include <linux/i2c/atmel_maxtouch.h>
+
+/*
+ * This is a driver for the Atmel maXTouch Object Protocol
+ *
+ * When the driver is loaded, mxt_init is called.
+ * mxt_driver registers the "mxt_driver" structure in the i2c subsystem
+ * The mxt_idtable.name string allows the board support to associate
+ * the driver with its own data.
+ *
+ * The i2c subsystem will call the mxt_driver.probe == mxt_probe
+ * to detect the device.
+ * mxt_probe will reset the maXTouch device, and then
+ * determine the capabilities of the I2C peripheral in the
+ * host processor (needs to support BYTE transfers)
+ *
+ * If OK; mxt_probe will try to identify which maXTouch device it is
+ * by calling mxt_identify.
+ *
+ * If a known device is found, a linux input device is initialized
+ * the "mxt" device data structure is allocated,
+ * as well as an input device structure "mxt->input"
+ * "mxt->client" is provided as a parameter to mxt_probe.
+ *
+ * mxt_read_object_table is called to determine which objects
+ * are present in the device, and to determine their adresses.
+ *
+ *
+ * Addressing an object:
+ *
+ * The object is located at a 16-bit address in the object address space.
+ *
+ * The address is provided through an object descriptor table in the beginning
+ * of the object address space. This address can change between firmware
+ * revisions, so it's important that the driver will make no assumptions
+ * about addresses but instead reads the object table and gets the correct
+ * addresses there.
+ *
+ * Each object type can have several instances, and the number of
+ * instances is available in the object table as well.
+ *
+ * The base address of the first instance of an object is stored in
+ * "mxt->object_table[object_type].chip_addr",
+ * This is indexed by the object type and allows direct access to the
+ * first instance of an object.
+ *
+ * Each instance of an object is assigned a "Report Id" uniquely identifying
+ * this instance. Information about this instance is available in the
+ * "mxt->report_id" variable, which is a table indexed by the "Report Id".
+ *
+ * The maXTouch object protocol supports adding a checksum to messages.
+ * By setting the most significant bit of the maXTouch address,
+ * an 8 bit checksum is added to all writes.
+ *
+ *
+ * How to use driver.
+ * -----------------
+ * Example:
+ * In arch/avr32/boards/atstk1000/atstk1002.c
+ * an "i2c_board_info" descriptor is declared.
+ * This contains info about which driver ("mXT224"),
+ * which i2c address and which pin for CHG interrupts are used.
+ *
+ * In the "atstk1002_init" routine, "i2c_register_board_info" is invoked
+ * with this information. Also, the I/O pins are configured, and the I2C
+ * controller registered is on the application processor.
+ *
+ *
+ */
+
+static int debug = NO_DEBUG;
+static int comms;
+module_param(debug, int, 0644);
+module_param(comms, int, 0644);
+
+MODULE_PARM_DESC(debug, "Activate debugging output");
+MODULE_PARM_DESC(comms, "Select communications mode");
+
+/* Device Info descriptor */
+/* Parsed from maXTouch "Id information" inside device */
+struct mxt_device_info {
+	u8 family_id;
+	u8 variant_id;
+	u8 major;
+	u8 minor;
+	u8 build;
+	u8 num_objs;
+	u8 x_size;
+	u8 y_size;
+	char family_name[16];	/* Family name */
+	char variant_name[16];	/* Variant name */
+	u16 num_nodes;		/* Number of sensor nodes */
+};
+
+/* object descriptor table, parsed from maXTouch "object table" */
+struct mxt_object {
+	u16 chip_addr;
+	u8 type;
+	u8 size;
+	u8 instances;
+	u8 num_report_ids;
+};
+
+/* Mapping from report id to object type and instance */
+struct report_id_map {
+	u8 object;
+	u8 instance;
+/*
+ * This is the first report ID belonging to object. It enables us to
+ * find out easily the touch number: each touch has different report
+ * ID (which are assigned to touches in increasing order). By
+ * subtracting the first report ID from current, we get the touch
+ * number.
+ */
+	u8 first_rid;
+};
+
+/* Driver datastructure */
+struct mxt_data {
+	struct i2c_client *client;
+	struct input_dev *input;
+	char phys_name[32];
+	int irq;
+
+	u16 last_read_addr;
+	bool new_msgs;
+	u8 *last_message;
+
+	int valid_irq_counter;
+	int invalid_irq_counter;
+	int irq_counter;
+	int message_counter;
+	int read_fail_counter;
+
+	int bytes_to_read;
+
+	struct delayed_work dwork;
+	u8 xpos_format;
+	u8 ypos_format;
+
+	u8 numtouch;
+
+	struct mxt_device_info device_info;
+
+	u32 info_block_crc;
+	u32 configuration_crc;
+	u16 report_id_count;
+	struct report_id_map *rid_map;
+	struct mxt_object *object_table;
+
+	u16 msg_proc_addr;
+	u8 message_size;
+
+	u16 max_x_val;
+	u16 max_y_val;
+
+	void (*init_hw) (void);
+	void (*exit_hw) (void);
+	 u8(*valid_interrupt) (void);
+	 u8(*read_chg) (void);
+
+	/* debugfs variables */
+	struct dentry *debug_dir;
+	int current_debug_datap;
+
+	struct mutex debug_mutex;
+	u16 *debug_data;
+
+	/* Character device variables */
+	struct cdev cdev;
+	struct cdev cdev_messages;	/* 2nd Char dev for messages */
+	dev_t dev_num;
+	struct class *mxt_class;
+
+	u16 address_pointer;
+	bool valid_ap;
+
+	/* Message buffer & pointers */
+	char *messages;
+	int msg_buffer_startp, msg_buffer_endp;
+	/* Put only non-touch messages to buffer if this is set */
+	char nontouch_msg_only;
+	struct mutex msg_mutex;
+};
+
+#define I2C_RETRY_COUNT 5
+#define I2C_PAYLOAD_SIZE 254
+
+/* Returns the start address of object in mXT memory. */
+#define	MXT_BASE_ADDR(object_type, mxt)					\
+	get_object_address(object_type, 0, mxt->object_table,           \
+			   mxt->device_info.num_objs)
+
+/* Maps a report ID to an object type (object type number). */
+#define	REPORT_ID_TO_OBJECT(rid, mxt)			\
+	(((rid) == 0xff) ? 0 : mxt->rid_map[rid].object)
+
+/* Maps a report ID to an object type (string). */
+#define	REPORT_ID_TO_OBJECT_NAME(rid, mxt)			\
+	object_type_name[REPORT_ID_TO_OBJECT(rid, mxt)]
+
+/* Returns non-zero if given object is a touch object */
+#define IS_TOUCH_OBJECT(object) \
+	((object == MXT_TOUCH_MULTITOUCHSCREEN_T9) || \
+	 (object == MXT_TOUCH_KEYARRAY_T15) ||	\
+	 (object == MXT_TOUCH_PROXIMITY_T23) || \
+	 (object == MXT_TOUCH_SINGLETOUCHSCREEN_T10) || \
+	 (object == MXT_TOUCH_XSLIDER_T11) || \
+	 (object == MXT_TOUCH_YSLIDER_T12) || \
+	 (object == MXT_TOUCH_XWHEEL_T13) || \
+	 (object == MXT_TOUCH_YWHEEL_T14) || \
+	 (object == MXT_TOUCH_KEYSET_T31) || \
+	 (object == MXT_TOUCH_XSLIDERSET_T32) ? 1 : 0)
+
+#define mxt_debug(level, ...) \
+	do { \
+		if (debug >= (level)) \
+			pr_debug(__VA_ARGS__); \
+	} while (0)
+
+static const u8 *object_type_name[] = {
+	[0] = "Reserved",
+	[5] = "GEN_MESSAGEPROCESSOR_T5",
+	[6] = "GEN_COMMANDPROCESSOR_T6",
+	[7] = "GEN_POWERCONFIG_T7",
+	[8] = "GEN_ACQUIRECONFIG_T8",
+	[9] = "TOUCH_MULTITOUCHSCREEN_T9",
+	[15] = "TOUCH_KEYARRAY_T15",
+	[17] = "SPT_COMMSCONFIG_T18",
+	[19] = "SPT_GPIOPWM_T19",
+	[20] = "PROCI_GRIPFACESUPPRESSION_T20",
+	[22] = "PROCG_NOISESUPPRESSION_T22",
+	[23] = "TOUCH_PROXIMITY_T23",
+	[24] = "PROCI_ONETOUCHGESTUREPROCESSOR_T24",
+	[25] = "SPT_SELFTEST_T25",
+	[27] = "PROCI_TWOTOUCHGESTUREPROCESSOR_T27",
+	[28] = "SPT_CTECONFIG_T28",
+	[37] = "DEBUG_DIAGNOSTICS_T37",
+	[38] = "SPT_USER_DATA_T38",
+	[40] = "PROCI_GRIPSUPPRESSION_T40",
+	[41] = "PROCI_PALMSUPPRESSION_T41",
+	[42] = "PROCI_FACESUPPRESSION_T42",
+	[43] = "SPT_DIGITIZER_T43",
+	[44] = "SPT_MESSAGECOUNT_T44",
+};
+
+static u16 get_object_address(uint8_t object_type,
+			      uint8_t instance,
+			      struct mxt_object *object_table, int max_objs);
+
+static int mxt_write_ap(struct mxt_data *mxt, u16 ap);
+
+static int mxt_read_block_wo_addr(struct i2c_client *client,
+				  u16 length, u8 *value);
+
+ssize_t debug_data_read(struct mxt_data *mxt, char *buf, size_t count,
+			loff_t *ppos, u8 debug_command)
+{
+	int i;
+	u16 *data;
+	u16 diagnostics_reg;
+	int offset = 0;
+	int size;
+	int read_size;
+	int error;
+	char *buf_start;
+	u16 debug_data_addr;
+	u16 page_address;
+	u8 page;
+	u8 debug_command_reg;
+
+	data = mxt->debug_data;
+	if (data == NULL)
+		return -EIO;
+
+	/* If first read after open, read all data to buffer. */
+	if (mxt->current_debug_datap == 0) {
+
+		diagnostics_reg = MXT_BASE_ADDR(MXT_GEN_COMMANDPROCESSOR_T6,
+						mxt) + MXT_ADR_T6_DIAGNOSTIC;
+		if (count > (mxt->device_info.num_nodes * 2))
+			count = mxt->device_info.num_nodes;
+
+		debug_data_addr = MXT_BASE_ADDR(MXT_DEBUG_DIAGNOSTIC_T37, mxt) +
+		    MXT_ADR_T37_DATA;
+		page_address = MXT_BASE_ADDR(MXT_DEBUG_DIAGNOSTIC_T37, mxt) +
+		    MXT_ADR_T37_PAGE;
+		error = mxt_read_block(mxt->client, page_address, 1, &page);
+		if (error < 0)
+			return error;
+		mxt_debug(DEBUG_TRACE, "debug data page = %d\n", page);
+		while (page != 0) {
+			error = mxt_write_byte(mxt->client,
+					       diagnostics_reg,
+					       MXT_CMD_T6_PAGE_DOWN);
+			if (error < 0)
+				return error;
+			/* Wait for command to be handled; when it has, the
+			   register will be cleared. */
+			debug_command_reg = 1;
+			while (debug_command_reg != 0) {
+				error = mxt_read_block(mxt->client,
+						       diagnostics_reg, 1,
+						       &debug_command_reg);
+				if (error < 0)
+					return error;
+				mxt_debug(DEBUG_TRACE,
+					  "Waiting for debug diag command "
+					  "to propagate...\n");
+
+			}
+			error = mxt_read_block(mxt->client, page_address, 1,
+					       &page);
+			if (error < 0)
+				return error;
+			mxt_debug(DEBUG_TRACE, "debug data page = %d\n", page);
+		}
+
+		/*
+		 * Lock mutex to prevent writing some unwanted data to debug
+		 * command register. User can still write through the char
+		 * device interface though. TODO: fix?
+		 */
+
+		mutex_lock(&mxt->debug_mutex);
+		/* Configure Debug Diagnostics object to show deltas/refs */
+		error = mxt_write_byte(mxt->client, diagnostics_reg,
+				       debug_command);
+
+		/* Wait for command to be handled; when it has, the
+		 * register will be cleared. */
+		debug_command_reg = 1;
+		while (debug_command_reg != 0) {
+			error = mxt_read_block(mxt->client,
+					       diagnostics_reg, 1,
+					       &debug_command_reg);
+			if (error < 0)
+				return error;
+			mxt_debug(DEBUG_TRACE, "Waiting for debug diag command "
+				  "to propagate...\n");
+
+		}
+
+		if (error < 0) {
+			printk(KERN_WARNING
+			       "Error writing to maXTouch device!\n");
+			return error;
+		}
+
+		size = mxt->device_info.num_nodes * sizeof(u16);
+
+		while (size > 0) {
+			read_size = size > 128 ? 128 : size;
+			mxt_debug(DEBUG_TRACE,
+				  "Debug data read loop, reading %d bytes...\n",
+				  read_size);
+			error = mxt_read_block(mxt->client,
+					       debug_data_addr,
+					       read_size,
+					       (u8 *) &data[offset]);
+			if (error < 0) {
+				printk(KERN_WARNING
+				       "Error reading debug data\n");
+				goto error;
+			}
+			offset += read_size / 2;
+			size -= read_size;
+
+			/* Select next page */
+			error = mxt_write_byte(mxt->client, diagnostics_reg,
+					       MXT_CMD_T6_PAGE_UP);
+			if (error < 0) {
+				printk(KERN_WARNING
+				       "Error writing to maXTouch device!\n");
+				goto error;
+			}
+		}
+		mutex_unlock(&mxt->debug_mutex);
+	}
+
+	buf_start = buf;
+	i = mxt->current_debug_datap;
+
+	while (((buf - buf_start) < (count - 6)) &&
+	       (i < mxt->device_info.num_nodes)) {
+
+		mxt->current_debug_datap++;
+		if (debug_command == MXT_CMD_T6_REFERENCES_MODE)
+			buf += sprintf(buf, "%d: %5d\n", i,
+				       (u16) le16_to_cpu(data[i]));
+		else if (debug_command == MXT_CMD_T6_DELTAS_MODE)
+			buf += sprintf(buf, "%d: %5d\n", i,
+				       (s16) le16_to_cpu(data[i]));
+		i++;
+	}
+
+	return buf - buf_start;
+ error:
+	mutex_unlock(&mxt->debug_mutex);
+	return error;
+}
+
+ssize_t deltas_read(struct file *file, char *buf, size_t count, loff_t *ppos)
+{
+	return debug_data_read(file->private_data, buf, count, ppos,
+			       MXT_CMD_T6_DELTAS_MODE);
+}
+
+ssize_t refs_read(struct file *file, char *buf, size_t count, loff_t *ppos)
+{
+	return debug_data_read(file->private_data, buf, count, ppos,
+			       MXT_CMD_T6_REFERENCES_MODE);
+}
+
+int debug_data_open(struct inode *inode, struct file *file)
+{
+	struct mxt_data *mxt;
+	int i;
+	mxt = inode->i_private;
+	if (mxt == NULL)
+		return -EIO;
+	mxt->current_debug_datap = 0;
+	mxt->debug_data = kmalloc(mxt->device_info.num_nodes * sizeof(u16),
+				  GFP_KERNEL);
+	if (mxt->debug_data == NULL)
+		return -ENOMEM;
+
+	for (i = 0; i < mxt->device_info.num_nodes; i++)
+		mxt->debug_data[i] = 7777;
+
+	file->private_data = mxt;
+	return 0;
+}
+
+int debug_data_release(struct inode *inode, struct file *file)
+{
+	struct mxt_data *mxt;
+	mxt = file->private_data;
+	kfree(mxt->debug_data);
+	return 0;
+}
+
+const struct file_operations delta_fops = {
+	.owner = THIS_MODULE,
+	.open = debug_data_open,
+	.release = debug_data_release,
+	.read = deltas_read,
+};
+
+const struct file_operations refs_fops = {
+	.owner = THIS_MODULE,
+	.open = debug_data_open,
+	.release = debug_data_release,
+	.read = refs_read,
+};
+
+int mxt_memory_open(struct inode *inode, struct file *file)
+{
+	struct mxt_data *mxt;
+	mxt = container_of(inode->i_cdev, struct mxt_data, cdev);
+	if (mxt == NULL)
+		return -EIO;
+	file->private_data = mxt;
+	return 0;
+}
+
+int mxt_message_open(struct inode *inode, struct file *file)
+{
+	struct mxt_data *mxt;
+	mxt = container_of(inode->i_cdev, struct mxt_data, cdev_messages);
+	if (mxt == NULL)
+		return -EIO;
+	file->private_data = mxt;
+	return 0;
+}
+
+ssize_t mxt_memory_read(struct file *file, char *buf, size_t count,
+			loff_t *ppos)
+{
+	int i;
+	struct mxt_data *mxt;
+
+	mxt = file->private_data;
+	if (mxt->valid_ap) {
+		mxt_debug(DEBUG_TRACE, "Reading %d bytes from current ap\n",
+			  (int)count);
+		i = mxt_read_block_wo_addr(mxt->client, count, (u8 *) buf);
+	} else {
+		mxt_debug(DEBUG_TRACE, "Address pointer changed since set;"
+			  "writing AP (%d) before reading %d bytes",
+			  mxt->address_pointer, (int)count);
+		i = mxt_read_block(mxt->client, mxt->address_pointer, count,
+				   buf);
+	}
+
+	return i;
+}
+
+ssize_t mxt_memory_write(struct file *file, const char *buf, size_t count,
+			 loff_t *ppos)
+{
+	int i;
+	int whole_blocks;
+	int last_block_size;
+	struct mxt_data *mxt;
+	u16 address;
+
+	mxt = file->private_data;
+	address = mxt->address_pointer;
+
+	mxt_debug(DEBUG_TRACE, "mxt_memory_write entered\n");
+	whole_blocks = count / I2C_PAYLOAD_SIZE;
+	last_block_size = count % I2C_PAYLOAD_SIZE;
+
+	for (i = 0; i < whole_blocks; i++) {
+		mxt_debug(DEBUG_TRACE, "About to write to %d...", address);
+		mxt_write_block(mxt->client, address, I2C_PAYLOAD_SIZE,
+				(u8 *) buf);
+		address += I2C_PAYLOAD_SIZE;
+		buf += I2C_PAYLOAD_SIZE;
+	}
+
+	mxt_write_block(mxt->client, address, last_block_size, (u8 *) buf);
+
+	return count;
+}
+
+static int mxt_ioctl(struct file *file,
+		     unsigned int cmd, unsigned long arg)
+{
+	int retval;
+	struct mxt_data *mxt;
+
+	retval = 0;
+	mxt = file->private_data;
+
+	switch (cmd) {
+	case MXT_SET_ADDRESS:
+		retval = mxt_write_ap(mxt, (u16) arg);
+		if (retval >= 0) {
+			mxt->address_pointer = (u16) arg;
+			mxt->valid_ap = 1;
+		}
+		break;
+	case MXT_RESET:
+		retval = mxt_write_byte(mxt->client,
+					MXT_BASE_ADDR
+					(MXT_GEN_COMMANDPROCESSOR_T6,
+					 mxt) + MXT_ADR_T6_RESET, 1);
+		break;
+	case MXT_CALIBRATE:
+		retval = mxt_write_byte(mxt->client,
+					MXT_BASE_ADDR
+					(MXT_GEN_COMMANDPROCESSOR_T6,
+					 mxt) + MXT_ADR_T6_CALIBRATE, 1);
+
+		break;
+	case MXT_BACKUP:
+		retval = mxt_write_byte(mxt->client,
+					MXT_BASE_ADDR
+					(MXT_GEN_COMMANDPROCESSOR_T6,
+					 mxt) + MXT_ADR_T6_BACKUPNV,
+					MXT_CMD_T6_BACKUP);
+		break;
+	case MXT_NONTOUCH_MSG:
+		mxt->nontouch_msg_only = 1;
+		break;
+	case MXT_ALL_MSG:
+		mxt->nontouch_msg_only = 0;
+		break;
+	default:
+		return -EIO;
+	}
+
+	return retval;
+}
+
+/*
+ * Copies messages from buffer to user space.
+ *
+ * NOTE: if less than (mxt->message_size * 5 + 1) bytes requested,
+ * this will return 0!
+ *
+ */
+ssize_t mxt_message_read(struct file *file, char *buf, size_t count,
+			 loff_t *ppos)
+{
+	int i;
+	struct mxt_data *mxt;
+	char *buf_start;
+
+	mxt = file->private_data;
+	if (mxt == NULL)
+		return -EIO;
+	buf_start = buf;
+
+	mutex_lock(&mxt->msg_mutex);
+	/* Copy messages until buffer empty, or 'count' bytes written */
+	while ((mxt->msg_buffer_startp != mxt->msg_buffer_endp) &&
+	       ((buf - buf_start) < (count - 5 * mxt->message_size - 1))) {
+
+		for (i = 0; i < mxt->message_size; i++) {
+			buf += sprintf(buf, "[%2X] ",
+				       *(mxt->messages + mxt->msg_buffer_endp *
+					 mxt->message_size + i));
+		}
+		buf += sprintf(buf, "\n");
+		if (mxt->msg_buffer_endp < MXT_MESSAGE_BUFFER_SIZE)
+			mxt->msg_buffer_endp++;
+		else
+			mxt->msg_buffer_endp = 0;
+	}
+	mutex_unlock(&mxt->msg_mutex);
+	return buf - buf_start;
+}
+
+const struct file_operations mxt_message_fops = {
+	.owner = THIS_MODULE,
+	.open = mxt_message_open,
+	.read = mxt_message_read,
+};
+
+const struct file_operations mxt_memory_fops = {
+	.owner = THIS_MODULE,
+	.open = mxt_memory_open,
+	.read = mxt_memory_read,
+	.write = mxt_memory_write,
+	.unlocked_ioctl = mxt_ioctl,
+};
+
+/* Writes the address pointer (to set up following reads). */
+
+int mxt_write_ap(struct mxt_data *mxt, u16 ap)
+{
+	struct i2c_client *client;
+	__le16 le_ap = cpu_to_le16(ap);
+	client = mxt->client;
+	if (mxt != NULL)
+		mxt->last_read_addr = -1;
+	if (i2c_master_send(client, (u8 *) &le_ap, 2) == 2) {
+		mxt_debug(DEBUG_TRACE, "Address pointer set to %d\n", ap);
+		return 0;
+	} else {
+		mxt_debug(DEBUG_INFO, "Error writing address pointer!\n");
+		return -EIO;
+	}
+}
+
+/* Calculates the 24-bit CRC sum. */
+static u32 CRC_24(u32 crc, u8 byte1, u8 byte2)
+{
+	static const u32 crcpoly = 0x80001B;
+	u32 result;
+	u32 data_word;
+
+	data_word = ((((u16) byte2) << 8u) | byte1);
+	result = ((crc << 1u) ^ data_word);
+	if (result & 0x1000000)
+		result ^= crcpoly;
+	return result;
+}
+
+/* Returns object address in mXT chip, or zero if object is not found */
+static u16 get_object_address(uint8_t object_type,
+			      uint8_t instance,
+			      struct mxt_object *object_table, int max_objs)
+{
+	uint8_t object_table_index = 0;
+	uint8_t address_found = 0;
+	uint16_t address = 0;
+	struct mxt_object *obj;
+
+	while ((object_table_index < max_objs) && !address_found) {
+		obj = &object_table[object_table_index];
+		if (obj->type == object_type) {
+			address_found = 1;
+			/* Are there enough instances defined in the FW? */
+			if (obj->instances >= instance) {
+				address = obj->chip_addr +
+				    (obj->size + 1) * instance;
+			} else {
+				return 0;
+			}
+		}
+		object_table_index++;
+	}
+	return address;
+}
+
+/*
+ * Reads a block of bytes from given address from mXT chip. If we are
+ * reading from message window, and previous read was from message window,
+ * there's no need to write the address pointer: the mXT chip will
+ * automatically set the address pointer back to message window start.
+ */
+
+static int mxt_read_block(struct i2c_client *client,
+			  u16 addr, u16 length, u8 *value)
+{
+	struct i2c_adapter *adapter = client->adapter;
+	struct i2c_msg msg[2];
+	__le16 le_addr;
+	struct mxt_data *mxt;
+
+	mxt = i2c_get_clientdata(client);
+
+	if (mxt != NULL) {
+		if ((mxt->last_read_addr == addr) &&
+		    (addr == mxt->msg_proc_addr)) {
+			if (i2c_master_recv(client, value, length) == length)
+				return length;
+			else
+				return -EIO;
+		} else {
+			mxt->last_read_addr = addr;
+		}
+	}
+
+	mxt_debug(DEBUG_TRACE, "Writing address pointer & reading %d bytes "
+		  "in on i2c transaction...\n", length);
+
+	le_addr = cpu_to_le16(addr);
+	msg[0].addr = client->addr;
+	msg[0].flags = 0x00;
+	msg[0].len = 2;
+	msg[0].buf = (u8 *) &le_addr;
+
+	msg[1].addr = client->addr;
+	msg[1].flags = I2C_M_RD;
+	msg[1].len = length;
+	msg[1].buf = (u8 *) value;
+	if (i2c_transfer(adapter, msg, 2) == 2)
+		return length;
+	else
+		return -EIO;
+
+}
+
+/* Reads a block of bytes from current address from mXT chip. */
+
+static int mxt_read_block_wo_addr(struct i2c_client *client,
+				  u16 length, u8 *value)
+{
+
+	if (i2c_master_recv(client, value, length) == length) {
+		mxt_debug(DEBUG_TRACE, "I2C block read ok\n");
+		return length;
+	} else {
+		mxt_debug(DEBUG_INFO, "I2C block read failed\n");
+		return -EIO;
+	}
+
+}
+
+/* Writes one byte to given address in mXT chip. */
+
+static int mxt_write_byte(struct i2c_client *client, u16 addr, u8 value)
+{
+	struct {
+		__le16 le_addr;
+		u8 data;
+
+	} i2c_byte_transfer;
+
+	struct mxt_data *mxt;
+
+	mxt = i2c_get_clientdata(client);
+	if (mxt != NULL)
+		mxt->last_read_addr = -1;
+	i2c_byte_transfer.le_addr = cpu_to_le16(addr);
+	i2c_byte_transfer.data = value;
+	if (i2c_master_send(client, (u8 *) &i2c_byte_transfer, 3) == 3)
+		return 0;
+	else
+		return -EIO;
+}
+
+/* Writes a block of bytes (max 256) to given address in mXT chip. */
+static int mxt_write_block(struct i2c_client *client,
+			   u16 addr, u16 length, u8 *value)
+{
+	int i;
+	struct {
+		__le16 le_addr;
+		u8 data[256];
+
+	} i2c_block_transfer;
+
+	struct mxt_data *mxt;
+
+	mxt_debug(DEBUG_TRACE, "Writing %d bytes to %d...", length, addr);
+	if (length > 256)
+		return -EINVAL;
+	mxt = i2c_get_clientdata(client);
+	if (mxt != NULL)
+		mxt->last_read_addr = -1;
+	for (i = 0; i < length; i++)
+		i2c_block_transfer.data[i] = *value++;
+	i2c_block_transfer.le_addr = cpu_to_le16(addr);
+	i = i2c_master_send(client, (u8 *) &i2c_block_transfer, length + 2);
+	if (i == (length + 2))
+		return length;
+	else
+		return -EIO;
+}
+
+/* Calculates the CRC value for mXT infoblock. */
+int calculate_infoblock_crc(u32 *crc_result, u8 *data, int crc_area_size)
+{
+	u32 crc = 0;
+	int i;
+
+	for (i = 0; i < (crc_area_size - 1); i = i + 2)
+		crc = CRC_24(crc, *(data + i), *(data + i + 1));
+	/* If uneven size, pad with zero */
+	if (crc_area_size & 0x0001)
+		crc = CRC_24(crc, *(data + i), 0);
+	/* Return only 24 bits of CRC. */
+	*crc_result = (crc & 0x00FFFFFF);
+
+	return 0;
+}
+
+void process_T9_message(u8 *message, struct mxt_data *mxt, int last_touch)
+{
+
+	struct input_dev *input;
+	u8 status;
+	u16 xpos = 0xFFFF;
+	u16 ypos = 0xFFFF;
+	u8 touch_size = 255;
+	u8 touch_number;
+	u8 amplitude;
+	u8 report_id;
+
+	static int stored_size[10];
+	static int stored_x[10];
+	static int stored_y[10];
+	int i;
+	int active_touches = 0;
+	/*
+	 * If the 'last_touch' flag is set, we have received
+		all the touch messages
+	 * there are available in this cycle, so send the
+		events for touches that are
+	 * active.
+	 */
+	if (last_touch) {
+		for (i = 0; i < 10; i++) {
+			if (stored_size[i]) {
+				active_touches++;
+				input_report_abs(mxt->input, ABS_MT_TRACKING_ID,
+						 i);
+				input_report_abs(mxt->input, ABS_MT_TOUCH_MAJOR,
+						 stored_size[i]);
+				input_report_abs(mxt->input, ABS_MT_POSITION_X,
+						 stored_x[i]);
+				input_report_abs(mxt->input, ABS_MT_POSITION_Y,
+						 stored_y[i]);
+				input_mt_sync(mxt->input);
+			}
+		}
+		if (active_touches)
+			input_sync(mxt->input);
+		else {
+			input_mt_sync(mxt->input);
+			input_sync(mxt->input);
+		}
+
+	} else {
+
+		input = mxt->input;
+		status = message[MXT_MSG_T9_STATUS];
+		report_id = message[0];
+
+		if (status & MXT_MSGB_T9_SUPPRESS) {
+			/* Touch has been suppressed by grip/face */
+			/* detection                              */
+			mxt_debug(DEBUG_TRACE, "SUPRESS");
+		} else {
+			xpos = message[MXT_MSG_T9_XPOSMSB] * 16 +
+			    ((message[MXT_MSG_T9_XYPOSLSB] >> 4) & 0xF);
+			ypos = message[MXT_MSG_T9_YPOSMSB] * 16 +
+			    ((message[MXT_MSG_T9_XYPOSLSB] >> 0) & 0xF);
+			if (mxt->max_x_val < 1024)
+				xpos >>= 2;
+			if (mxt->max_y_val < 1024)
+				ypos >>= 2;
+
+			touch_number = message[MXT_MSG_REPORTID] -
+			    mxt->rid_map[report_id].first_rid;
+
+			stored_x[touch_number] = xpos;
+			stored_y[touch_number] = ypos;
+
+			if (status & MXT_MSGB_T9_DETECT) {
+				/*
+				 * TODO: more precise touch size calculation?
+				 * mXT224 reports the number of touched nodes,
+				 * so the exact value for touch ellipse major
+				 * axis length would be 2*sqrt(touch_size/pi)
+				 * (assuming round touch shape).
+				 */
+				touch_size = message[MXT_MSG_T9_TCHAREA];
+				touch_size = touch_size >> 2;
+				if (!touch_size)
+					touch_size = 1;
+
+				stored_size[touch_number] = touch_size;
+
+				if (status & MXT_MSGB_T9_AMP)
+					/* Amplitude of touch has changed */
+					amplitude =
+					    message[MXT_MSG_T9_TCHAMPLITUDE];
+			}
+
+			if (status & MXT_MSGB_T9_RELEASE) {
+				/* The previously reported touch has
+					been removed. */
+				stored_size[touch_number] = 0;
+			}
+		}
+
+		if (status & MXT_MSGB_T9_SUPPRESS) {
+			mxt_debug(DEBUG_TRACE, "SUPRESS");
+		} else {
+			if (status & MXT_MSGB_T9_DETECT) {
+				mxt_debug(DEBUG_TRACE, "DETECT:%s%s%s%s",
+					  ((status & MXT_MSGB_T9_PRESS) ?
+					   " PRESS" : ""),
+					  ((status & MXT_MSGB_T9_MOVE) ? " MOVE"
+					   : ""),
+					  ((status & MXT_MSGB_T9_AMP) ? " AMP" :
+					   ""),
+					  ((status & MXT_MSGB_T9_VECTOR) ?
+					   " VECT" : ""));
+
+			} else if (status & MXT_MSGB_T9_RELEASE) {
+				mxt_debug(DEBUG_TRACE, "RELEASE");
+			}
+		}
+		mxt_debug(DEBUG_TRACE, "X=%d, Y=%d, TOUCHSIZE=%d",
+			  xpos, ypos, touch_size);
+	}
+	return;
+}
+
+int process_message(u8 *message, u8 object, struct mxt_data *mxt)
+{
+	struct i2c_client *client;
+	u8 status;
+	u16 xpos = 0xFFFF;
+	u16 ypos = 0xFFFF;
+	u8 event;
+	u8 length;
+	u8 report_id;
+
+	client = mxt->client;
+	length = mxt->message_size;
+	report_id = message[0];
+
+	if ((mxt->nontouch_msg_only == 0) || (!IS_TOUCH_OBJECT(object))) {
+		mutex_lock(&mxt->msg_mutex);
+		/* Copy the message to buffer */
+		if (mxt->msg_buffer_startp < MXT_MESSAGE_BUFFER_SIZE)
+			mxt->msg_buffer_startp++;
+		else
+			mxt->msg_buffer_startp = 0;
+
+		if (mxt->msg_buffer_startp == mxt->msg_buffer_endp) {
+			mxt_debug(DEBUG_TRACE,
+				  "Message buf full, discarding last entry.\n");
+			if (mxt->msg_buffer_endp < MXT_MESSAGE_BUFFER_SIZE)
+				mxt->msg_buffer_endp++;
+			else
+				mxt->msg_buffer_endp = 0;
+		}
+		memcpy((mxt->messages + mxt->msg_buffer_startp * length),
+		       message, length);
+		mutex_unlock(&mxt->msg_mutex);
+	}
+
+	switch (object) {
+	case MXT_GEN_COMMANDPROCESSOR_T6:
+		status = message[1];
+		if (status & MXT_MSGB_T6_COMSERR)
+			dev_err(&client->dev, "maXTouch checksum error\n");
+		if (status & MXT_MSGB_T6_CFGERR) {
+			/*
+			 * Configuration error. A proper configuration
+			 * needs to be written to chip and backed up. Refer
+			 * to protocol document for further info.
+			 */
+			dev_err(&client->dev, "maXTouch configuration error\n");
+		}
+		if (status & MXT_MSGB_T6_CAL) {
+			/* Calibration in action, no need to react */
+			dev_info(&client->dev,
+				 "maXTouch calibration in progress\n");
+		}
+		if (status & MXT_MSGB_T6_SIGERR) {
+			/*
+			 * Signal acquisition error, something is seriously
+			 * wrong, not much we can in the driver to correct
+			 * this
+			 */
+			dev_err(&client->dev, "maXTouch acquisition error\n");
+		}
+		if (status & MXT_MSGB_T6_OFL) {
+			/*
+			 * Cycle overflow, the acquisition is too short.
+			 * Can happen temporarily when there's a complex
+			 * touch shape on the screen requiring lots of
+			 * processing.
+			 */
+			dev_err(&client->dev, "maXTouch cycle overflow\n");
+		}
+		if (status & MXT_MSGB_T6_RESET) {
+			/* Chip has reseted, no need to react. */
+			dev_info(&client->dev, "maXTouch chip reset\n");
+		}
+		if (status == 0) {
+			/* Chip status back to normal. */
+			dev_info(&client->dev, "maXTouch status normal\n");
+		}
+		break;
+
+	case MXT_TOUCH_MULTITOUCHSCREEN_T9:
+		process_T9_message(message, mxt, 0);
+		break;
+
+	case MXT_SPT_GPIOPWM_T19:
+		if (debug >= DEBUG_TRACE)
+			dev_info(&client->dev, "Receiving GPIO message\n");
+		break;
+
+	case MXT_PROCI_GRIPFACESUPPRESSION_T20:
+		if (debug >= DEBUG_TRACE)
+			dev_info(&client->dev,
+				 "Receiving face suppression msg\n");
+		break;
+
+	case MXT_PROCG_NOISESUPPRESSION_T22:
+		if (debug >= DEBUG_TRACE)
+			dev_info(&client->dev,
+				 "Receiving noise suppression msg\n");
+		status = message[MXT_MSG_T22_STATUS];
+		if (status & MXT_MSGB_T22_FHCHG) {
+			if (debug >= DEBUG_TRACE)
+				dev_info(&client->dev,
+					 "maXTouch: Freq changed\n");
+		}
+		if (status & MXT_MSGB_T22_GCAFERR) {
+			if (debug >= DEBUG_TRACE)
+				dev_info(&client->dev,
+					 "maXTouch: High noise " "level\n");
+		}
+		if (status & MXT_MSGB_T22_FHERR) {
+			if (debug >= DEBUG_TRACE)
+				dev_info(&client->dev,
+					 "maXTouch: Freq changed - "
+					 "Noise level too high\n");
+		}
+		break;
+
+	case MXT_PROCI_ONETOUCHGESTUREPROCESSOR_T24:
+		if (debug >= DEBUG_TRACE)
+			dev_info(&client->dev,
+				 "Receiving one-touch gesture msg\n");
+
+		event = message[MXT_MSG_T24_STATUS] & 0x0F;
+		xpos = message[MXT_MSG_T24_XPOSMSB] * 16 +
+		    ((message[MXT_MSG_T24_XYPOSLSB] >> 4) & 0x0F);
+		ypos = message[MXT_MSG_T24_YPOSMSB] * 16 +
+		    ((message[MXT_MSG_T24_XYPOSLSB] >> 0) & 0x0F);
+		xpos >>= 2;
+		ypos >>= 2;
+
+		switch (event) {
+		case MT_GESTURE_RESERVED:
+			break;
+		case MT_GESTURE_PRESS:
+			break;
+		case MT_GESTURE_RELEASE:
+			break;
+		case MT_GESTURE_TAP:
+			break;
+		case MT_GESTURE_DOUBLE_TAP:
+			break;
+		case MT_GESTURE_FLICK:
+			break;
+		case MT_GESTURE_DRAG:
+			break;
+		case MT_GESTURE_SHORT_PRESS:
+			break;
+		case MT_GESTURE_LONG_PRESS:
+			break;
+		case MT_GESTURE_REPEAT_PRESS:
+			break;
+		case MT_GESTURE_TAP_AND_PRESS:
+			break;
+		case MT_GESTURE_THROW:
+			break;
+		default:
+			break;
+		}
+		break;
+
+	case MXT_SPT_SELFTEST_T25:
+		if (debug >= DEBUG_TRACE)
+			dev_info(&client->dev, "Receiving Self-Test msg\n");
+
+		if (message[MXT_MSG_T25_STATUS] == MXT_MSGR_T25_OK) {
+			if (debug >= DEBUG_TRACE)
+				dev_info(&client->dev,
+					 "maXTouch: Self-Test OK\n");
+
+		} else {
+			dev_err(&client->dev,
+				"maXTouch: Self-Test Failed [%02x]:"
+				"{%02x,%02x,%02x,%02x,%02x}\n",
+				message[MXT_MSG_T25_STATUS],
+				message[MXT_MSG_T25_STATUS + 0],
+				message[MXT_MSG_T25_STATUS + 1],
+				message[MXT_MSG_T25_STATUS + 2],
+				message[MXT_MSG_T25_STATUS + 3],
+				message[MXT_MSG_T25_STATUS + 4]
+			    );
+		}
+		break;
+
+	case MXT_PROCI_TWOTOUCHGESTUREPROCESSOR_T27:
+		if (debug >= DEBUG_TRACE)
+			dev_info(&client->dev,
+				 "Receiving 2-touch gesture message\n");
+		break;
+
+	case MXT_SPT_CTECONFIG_T28:
+		if (debug >= DEBUG_TRACE)
+			dev_info(&client->dev, "Receiving CTE message...\n");
+		status = message[MXT_MSG_T28_STATUS];
+		if (status & MXT_MSGB_T28_CHKERR)
+			dev_err(&client->dev,
+				"maXTouch: Power-Up CRC failure\n");
+
+		break;
+	default:
+		if (debug >= DEBUG_TRACE)
+			dev_info(&client->dev, "maXTouch: Unknown message!\n");
+
+		break;
+	}
+
+	return 0;
+}
+
+/*
+ * Processes messages when the interrupt line (CHG) is asserted. Keeps
+ * reading messages until a message with report ID 0xFF is received,
+ * which indicates that there is no more new messages.
+ *
+ */
+
+static void mxt_worker(struct work_struct *work)
+{
+	struct mxt_data *mxt;
+	struct i2c_client *client;
+
+	u8 *message;
+	u16 message_length;
+	u16 message_addr;
+	u8 report_id;
+	u8 object;
+	int error;
+	int i;
+	char *message_string;
+	char *message_start;
+
+	int n = 0;
+
+	message = NULL;
+	mxt = container_of(work, struct mxt_data, dwork.work);
+	disable_irq(mxt->irq);
+	client = mxt->client;
+	message_addr = mxt->msg_proc_addr;
+	message_length = mxt->message_size;
+
+	if (message_length < 256) {
+		message = kmalloc(message_length, GFP_KERNEL);
+		if (message == NULL) {
+			dev_err(&client->dev, "Error allocating memory\n");
+			return;
+		}
+	} else {
+		dev_err(&client->dev,
+			"Message length larger than 256 bytes not supported\n");
+		return;
+	}
+
+	mxt_debug("maXTouch worker active: \n");
+	do {
+		/* Read next message, reread on failure. */
+		/* -1 TO WORK AROUND A BUG ON 0.9 FW MESSAGING, needs */
+		/* to be changed back if checksum is read */
+		mxt->message_counter++;
+		for (i = 1; i < I2C_RETRY_COUNT; i++) {
+			error = mxt_read_block(client,
+					       message_addr,
+					       message_length - 1, message);
+			if (error >= 0)
+				break;
+			mxt->read_fail_counter++;
+			dev_err(&client->dev,
+				"Failure reading maxTouch device\n");
+		}
+		if (error < 0) {
+			kfree(message);
+			return;
+		}
+
+		if (mxt->address_pointer != message_addr)
+			mxt->valid_ap = 0;
+		report_id = message[0];
+
+		if (debug >= DEBUG_RAW) {
+			mxt_debug(DEBUG_RAW, "%s message [msg count: %08x]:",
+				  REPORT_ID_TO_OBJECT_NAME(report_id, mxt),
+				  mxt->message_counter);
+			/* 5 characters per one byte */
+			message_string = kmalloc(message_length * 5,
+						 GFP_KERNEL);
+			if (message_string == NULL) {
+				dev_err(&client->dev,
+					"Error allocating memory\n");
+				kfree(message);
+				return;
+			}
+			message_start = message_string;
+			for (i = 0; i < message_length; i++) {
+				message_string +=
+				    sprintf(message_string,
+					    "0x%02X ", message[i]);
+			}
+			mxt_debug(DEBUG_RAW, "%s", message_start);
+			kfree(message_start);
+		}
+
+		if ((report_id != MXT_END_OF_MESSAGES) && (report_id != 0)) {
+			memcpy(mxt->last_message, message, message_length);
+			mxt->new_msgs = 1;
+			smp_wmb();
+			/* Get type of object and process the message */
+			object = mxt->rid_map[report_id].object;
+			process_message(message, object, mxt);
+		}
+		mxt_debug(DEBUG_TRACE, "chgline: %d\n", mxt->read_chg());
+	} while (comms ? (mxt->read_chg() == 0) :
+		 ((report_id != MXT_END_OF_MESSAGES) && (report_id != 0)));
+
+	/* All messages processed, send the events) */
+	process_T9_message(NULL, mxt, 1);
+
+	kfree(message);
+	enable_irq(mxt->irq);
+	/* Make sure we don't miss any interrupts and read changeline. */
+	if (mxt->read_chg() == 0)
+		schedule_delayed_work(&mxt->dwork, 0);
+}
+
+/*
+ * The maXTouch device will signal the host about a new message by asserting
+ * the CHG line. This ISR schedules a worker routine to read the message when
+ * that happens.
+ */
+
+static irqreturn_t mxt_irq_handler(int irq, void *_mxt)
+{
+	struct mxt_data *mxt = _mxt;
+
+	mxt->irq_counter++;
+	if (mxt->valid_interrupt()) {
+		/* Send the signal only if falling edge generated the irq. */
+		cancel_delayed_work(&mxt->dwork);
+		schedule_delayed_work(&mxt->dwork, 0);
+		mxt->valid_irq_counter++;
+	} else {
+		mxt->invalid_irq_counter++;
+		return IRQ_NONE;
+	}
+
+	return IRQ_HANDLED;
+}
+
+/******************************************************************************/
+/* Initialization of driver                                                   */
+/******************************************************************************/
+
+static int __devinit mxt_identify(struct i2c_client *client,
+				  struct mxt_data *mxt, u8 * id_block_data)
+{
+	u8 buf[7];
+	int error;
+	int identified;
+
+	identified = 0;
+
+	/* Read Device info to check if chip is valid */
+	error = mxt_read_block(client, MXT_ADDR_INFO_BLOCK, MXT_ID_BLOCK_SIZE,
+			       (u8 *) buf);
+
+	if (error < 0) {
+		mxt->read_fail_counter++;
+		dev_err(&client->dev, "Failure accessing maXTouch device\n");
+		return -EIO;
+	}
+
+	memcpy(id_block_data, buf, MXT_ID_BLOCK_SIZE);
+
+	mxt->device_info.family_id = buf[0];
+	mxt->device_info.variant_id = buf[1];
+	mxt->device_info.major = ((buf[2] >> 4) & 0x0F);
+	mxt->device_info.minor = (buf[2] & 0x0F);
+	mxt->device_info.build = buf[3];
+	mxt->device_info.x_size = buf[4];
+	mxt->device_info.y_size = buf[5];
+	mxt->device_info.num_objs = buf[6];
+	mxt->device_info.num_nodes = mxt->device_info.x_size *
+	    mxt->device_info.y_size;
+
+	/*
+	 * Check Family & Variant Info; warn if not recognized but
+	 * still continue.
+	 */
+
+	/* MXT224 */
+	if (mxt->device_info.family_id == MXT224_FAMILYID) {
+		strcpy(mxt->device_info.family_name, "mXT224");
+
+		if (mxt->device_info.variant_id == MXT224_CAL_VARIANTID) {
+			strcpy(mxt->device_info.variant_name, "Calibrated");
+		} else if (mxt->device_info.variant_id ==
+			   MXT224_UNCAL_VARIANTID) {
+			strcpy(mxt->device_info.variant_name, "Uncalibrated");
+		} else {
+			dev_err(&client->dev,
+				"Warning: maXTouch Variant ID [%d] not "
+				"supported\n", mxt->device_info.variant_id);
+			strcpy(mxt->device_info.variant_name, "UNKNOWN");
+			/* identified = -ENXIO; */
+		}
+
+		/* MXT1386 */
+	} else if (mxt->device_info.family_id == MXT1386_FAMILYID) {
+		strcpy(mxt->device_info.family_name, "mXT1386");
+
+		if (mxt->device_info.variant_id == MXT1386_CAL_VARIANTID) {
+			strcpy(mxt->device_info.variant_name, "Calibrated");
+		} else {
+			dev_err(&client->dev,
+				"Warning: maXTouch Variant ID [%d] not "
+				"supported\n", mxt->device_info.variant_id);
+			strcpy(mxt->device_info.variant_name, "UNKNOWN");
+			/* identified = -ENXIO; */
+		}
+		/* Unknown family ID! */
+	} else {
+		dev_err(&client->dev,
+			"Warning: maXTouch Family ID [%d] not supported\n",
+			mxt->device_info.family_id);
+		strcpy(mxt->device_info.family_name, "UNKNOWN");
+		strcpy(mxt->device_info.variant_name, "UNKNOWN");
+		/* identified = -ENXIO; */
+	}
+
+	dev_info(&client->dev,
+		 "Atmel maXTouch (Family %s (%X), Variant %s (%X)) Firmware "
+		 "version [%d.%d] Build %d\n",
+		 mxt->device_info.family_name,
+		 mxt->device_info.family_id,
+		 mxt->device_info.variant_name,
+		 mxt->device_info.variant_id,
+		 mxt->device_info.major,
+		 mxt->device_info.minor, mxt->device_info.build);
+	dev_info(&client->dev,
+		 "Atmel maXTouch Configuration "
+		 "[X: %d] x [Y: %d]\n",
+		 mxt->device_info.x_size, mxt->device_info.y_size);
+	return identified;
+}
+
+/*
+ * Reads the object table from maXTouch chip to get object data like
+ * address, size, report id. For Info Block CRC calculation, already read
+ * id data is passed to this function too (Info Block consists of the ID
+ * block and object table).
+ *
+ */
+static int __devinit mxt_read_object_table(struct i2c_client *client,
+					   struct mxt_data *mxt,
+					   u8 *raw_id_data)
+{
+	u16 report_id_count;
+	u8 buf[MXT_OBJECT_TABLE_ELEMENT_SIZE];
+	u8 *raw_ib_data;
+	u8 object_type;
+	u16 object_address;
+	u16 object_size;
+	u8 object_instances;
+	u8 object_report_ids;
+	u16 object_info_address;
+	u32 crc;
+	u32 calculated_crc;
+	int i;
+	int error;
+
+	u8 object_instance;
+	u8 object_report_id;
+	u8 report_id;
+	int first_report_id;
+	int ib_pointer;
+	struct mxt_object *object_table;
+
+	mxt_debug(DEBUG_TRACE, "maXTouch driver reading configuration\n");
+
+	object_table = kzalloc(sizeof(struct mxt_object) *
+			       mxt->device_info.num_objs, GFP_KERNEL);
+	if (object_table == NULL) {
+		printk(KERN_WARNING "maXTouch: Memory allocation failed!\n");
+		error = -ENOMEM;
+		goto err_object_table_alloc;
+	}
+
+	raw_ib_data = kmalloc(MXT_OBJECT_TABLE_ELEMENT_SIZE *
+			      mxt->device_info.num_objs + MXT_ID_BLOCK_SIZE,
+			      GFP_KERNEL);
+	if (raw_ib_data == NULL) {
+		printk(KERN_WARNING "maXTouch: Memory allocation failed!\n");
+		error = -ENOMEM;
+		goto err_ib_alloc;
+	}
+
+	/* Copy the ID data for CRC calculation. */
+	memcpy(raw_ib_data, raw_id_data, MXT_ID_BLOCK_SIZE);
+	ib_pointer = MXT_ID_BLOCK_SIZE;
+
+	mxt->object_table = object_table;
+
+	mxt_debug(DEBUG_TRACE, "maXTouch driver Memory allocated\n");
+
+	object_info_address = MXT_ADDR_OBJECT_TABLE;
+
+	report_id_count = 0;
+	for (i = 0; i < mxt->device_info.num_objs; i++) {
+		mxt_debug(DEBUG_TRACE, "Reading maXTouch at [0x%04x]: ",
+			  object_info_address);
+
+		error = mxt_read_block(client, object_info_address,
+				       MXT_OBJECT_TABLE_ELEMENT_SIZE, buf);
+
+		if (error < 0) {
+			mxt->read_fail_counter++;
+			dev_err(&client->dev,
+				"maXTouch Object %d could not be read\n", i);
+			error = -EIO;
+			goto err_object_read;
+		}
+
+		memcpy(raw_ib_data + ib_pointer, buf,
+		       MXT_OBJECT_TABLE_ELEMENT_SIZE);
+		ib_pointer += MXT_OBJECT_TABLE_ELEMENT_SIZE;
+
+		object_type = buf[0];
+		object_address = (buf[2] << 8) + buf[1];
+		object_size = buf[3] + 1;
+		object_instances = buf[4] + 1;
+		object_report_ids = buf[5];
+		mxt_debug(DEBUG_TRACE, "Type=%03d, Address=0x%04x, "
+			  "Size=0x%02x, %d instances, %d report id's\n",
+			  object_type,
+			  object_address,
+			  object_size, object_instances, object_report_ids);
+
+		/* TODO: check whether object is known and supported? */
+
+		/* Save frequently needed info. */
+		if (object_type == MXT_GEN_MESSAGEPROCESSOR_T5) {
+			mxt->msg_proc_addr = object_address;
+			mxt->message_size = object_size;
+			printk(KERN_ALERT "message length: %d", object_size);
+		}
+
+		object_table[i].type = object_type;
+		object_table[i].chip_addr = object_address;
+		object_table[i].size = object_size;
+		object_table[i].instances = object_instances;
+		object_table[i].num_report_ids = object_report_ids;
+		report_id_count += object_instances * object_report_ids;
+
+		object_info_address += MXT_OBJECT_TABLE_ELEMENT_SIZE;
+	}
+
+	mxt->rid_map =
+	    kzalloc(sizeof(struct report_id_map) * (report_id_count + 1),
+		    /* allocate for report_id 0, even if not used */
+		    GFP_KERNEL);
+	if (mxt->rid_map == NULL) {
+		printk(KERN_WARNING "maXTouch: Can't allocate memory!\n");
+		error = -ENOMEM;
+		goto err_rid_map_alloc;
+	}
+
+	mxt->messages = kzalloc(mxt->message_size * MXT_MESSAGE_BUFFER_SIZE,
+				GFP_KERNEL);
+	if (mxt->messages == NULL) {
+		printk(KERN_WARNING "maXTouch: Can't allocate memory!\n");
+		error = -ENOMEM;
+		goto err_msg_alloc;
+	}
+
+	mxt->last_message = kzalloc(mxt->message_size, GFP_KERNEL);
+	if (mxt->last_message == NULL) {
+		printk(KERN_WARNING "maXTouch: Can't allocate memory!\n");
+		error = -ENOMEM;
+		goto err_msg_alloc;
+	}
+
+	mxt->report_id_count = report_id_count;
+	if (report_id_count > 254) {	/* 0 & 255 are reserved */
+		dev_err(&client->dev,
+			"Too many maXTouch report id's [%d]\n",
+			report_id_count);
+		error = -ENXIO;
+		goto err_max_rid;
+	}
+
+	/* Create a mapping from report id to object type */
+	report_id = 1;		/* Start from 1, 0 is reserved. */
+
+	/* Create table associating report id's with objects & instances */
+	for (i = 0; i < mxt->device_info.num_objs; i++) {
+		for (object_instance = 0;
+		     object_instance < object_table[i].instances;
+		     object_instance++) {
+			first_report_id = report_id;
+			for (object_report_id = 0;
+			     object_report_id < object_table[i].num_report_ids;
+			     object_report_id++) {
+				mxt->rid_map[report_id].object =
+				    object_table[i].type;
+				mxt->rid_map[report_id].instance =
+				    object_instance;
+				mxt->rid_map[report_id].first_rid =
+				    first_report_id;
+				report_id++;
+			}
+		}
+	}
+
+	/* Read 3 byte CRC */
+	error = mxt_read_block(client, object_info_address, 3, buf);
+	if (error < 0) {
+		mxt->read_fail_counter++;
+		dev_err(&client->dev, "Error reading CRC\n");
+	}
+
+	crc = (buf[2] << 16) | (buf[1] << 8) | buf[0];
+
+	if (calculate_infoblock_crc(&calculated_crc, raw_ib_data, ib_pointer)) {
+		printk(KERN_WARNING "Error while calculating CRC!\n");
+		calculated_crc = 0;
+	}
+	kfree(raw_ib_data);
+
+	mxt_debug(DEBUG_TRACE, "\nReported info block CRC = 0x%6X\n", crc);
+	mxt_debug(DEBUG_TRACE, "Calculated info block CRC = 0x%6X\n\n",
+		  calculated_crc);
+
+	if (crc == calculated_crc) {
+		mxt->info_block_crc = crc;
+	} else {
+		mxt->info_block_crc = 0;
+		printk(KERN_ALERT "maXTouch: Info block CRC invalid!\n");
+	}
+
+	if (debug >= DEBUG_VERBOSE) {
+
+		dev_info(&client->dev, "maXTouch: %d Objects\n",
+			 mxt->device_info.num_objs);
+
+		for (i = 0; i < mxt->device_info.num_objs; i++) {
+			dev_info(&client->dev, "Type:\t\t\t[%d]: %s\n",
+				 object_table[i].type,
+				 object_type_name[object_table[i].type]);
+			dev_info(&client->dev, "\tAddress:\t0x%04X\n",
+				 object_table[i].chip_addr);
+			dev_info(&client->dev, "\tSize:\t\t%d Bytes\n",
+				 object_table[i].size);
+			dev_info(&client->dev, "\tInstances:\t%d\n",
+				 object_table[i].instances);
+			dev_info(&client->dev, "\tReport Id's:\t%d\n",
+				 object_table[i].num_report_ids);
+		}
+	}
+
+	return 0;
+
+ err_max_rid:
+	kfree(mxt->last_message);
+ err_msg_alloc:
+	kfree(mxt->rid_map);
+ err_rid_map_alloc:
+ err_object_read:
+	kfree(raw_ib_data);
+ err_ib_alloc:
+	kfree(object_table);
+ err_object_table_alloc:
+	return error;
+}
+
+static int __devinit mxt_probe(struct i2c_client *client,
+			       const struct i2c_device_id *id)
+{
+	struct mxt_data *mxt;
+	struct mxt_platform_data *pdata;
+	struct input_dev *input;
+	u8 *id_data;
+	int error;
+
+	mxt_debug(DEBUG_INFO, "mXT224: mxt_probe\n");
+
+	if (client == NULL) {
+		pr_debug("maXTouch: client == NULL\n");
+		return -EINVAL;
+	} else if (client->adapter == NULL) {
+		pr_debug("maXTouch: client->adapter == NULL\n");
+		return -EINVAL;
+	} else if (&client->dev == NULL) {
+		pr_debug("maXTouch: client->dev == NULL\n");
+		return -EINVAL;
+	} else if (&client->adapter->dev == NULL) {
+		pr_debug("maXTouch: client->adapter->dev == NULL\n");
+		return -EINVAL;
+	} else if (id == NULL) {
+		pr_debug("maXTouch: id == NULL\n");
+		return -EINVAL;
+	}
+
+	mxt_debug(DEBUG_INFO, "maXTouch driver\n");
+	mxt_debug(DEBUG_INFO, "\t \"%s\"\n", client->name);
+	mxt_debug(DEBUG_INFO, "\taddr:\t0x%04x\n", client->addr);
+	mxt_debug(DEBUG_INFO, "\tirq:\t%d\n", client->irq);
+	mxt_debug(DEBUG_INFO, "\tflags:\t0x%04x\n", client->flags);
+	mxt_debug(DEBUG_INFO, "\tadapter:\"%s\"\n", client->adapter->name);
+	mxt_debug(DEBUG_INFO, "\tdevice:\t\"%s\"\n", client->dev.init_name);
+
+	/* Check if the I2C bus supports BYTE transfer */
+	error = i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE);
+	dev_info(&client->dev, "RRC:  i2c_check_functionality = %i\n", error);
+	error = 0xff;
+/*
+	if (!error) {
+		dev_err(&client->dev, "maXTouch driver\n");
+		dev_err(&client->dev, "\t \"%s\"\n", client->name);
+		dev_err(&client->dev, "\taddr:\t0x%04x\n", client->addr);
+		dev_err(&client->dev, "\tirq:\t%d\n", client->irq);
+		dev_err(&client->dev, "\tflags:\t0x%04x\n", client->flags);
+		dev_err(&client->dev, "\tadapter:\"%s\"\n",
+			client->adapter->name);
+		dev_err(&client->dev, "\tdevice:\t\"%s\"\n",
+			client->dev.init_name);
+		dev_err(&client->dev, "%s adapter not supported\n",
+				dev_driver_string(&client->adapter->dev));
+		return -ENODEV;
+	}
+*/
+	mxt_debug(DEBUG_TRACE, "maXTouch driver functionality OK\n");
+
+	/* Allocate structure - we need it to identify device */
+	mxt = kzalloc(sizeof(struct mxt_data), GFP_KERNEL);
+	if (mxt == NULL) {
+		dev_err(&client->dev, "insufficient memory\n");
+		error = -ENOMEM;
+		goto err_mxt_alloc;
+	}
+
+	id_data = kmalloc(MXT_ID_BLOCK_SIZE, GFP_KERNEL);
+	if (id_data == NULL) {
+		dev_err(&client->dev, "insufficient memory\n");
+		error = -ENOMEM;
+		goto err_id_alloc;
+	}
+
+	input = input_allocate_device();
+	if (!input) {
+		dev_err(&client->dev, "error allocating input device\n");
+		error = -ENOMEM;
+		goto err_input_dev_alloc;
+	}
+
+	/* Initialize Platform data */
+
+	pdata = client->dev.platform_data;
+	if (pdata == NULL) {
+		dev_err(&client->dev, "platform data is required!\n");
+		error = -EINVAL;
+		goto err_pdata;
+	}
+	if (debug >= DEBUG_TRACE)
+		printk(KERN_INFO "Platform OK: pdata = 0x%08x\n",
+		       (unsigned int)pdata);
+
+	mxt->read_fail_counter = 0;
+	mxt->message_counter = 0;
+	mxt->max_x_val = pdata->max_x;
+	mxt->max_y_val = pdata->max_y;
+
+	/* Get data that is defined in board specific code. */
+	mxt->init_hw = pdata->init_platform_hw;
+	mxt->exit_hw = pdata->exit_platform_hw;
+	mxt->read_chg = pdata->read_chg;
+
+	if (pdata->valid_interrupt != NULL)
+		mxt->valid_interrupt = pdata->valid_interrupt;
+	else
+		mxt->valid_interrupt = mxt_valid_interrupt_dummy;
+
+	if (mxt->init_hw != NULL)
+		mxt->init_hw();
+
+	if (debug >= DEBUG_TRACE)
+		printk(KERN_INFO "maXTouch driver identifying chip\n");
+
+	if (mxt_identify(client, mxt, id_data) < 0) {
+		dev_err(&client->dev, "Chip could not be identified\n");
+		error = -ENODEV;
+		goto err_identify;
+	}
+	/* Chip is valid and active. */
+	if (debug >= DEBUG_TRACE)
+		printk(KERN_INFO "maXTouch driver allocating input device\n");
+
+	mxt->client = client;
+	mxt->input = input;
+
+	INIT_DELAYED_WORK(&mxt->dwork, mxt_worker);
+	mutex_init(&mxt->debug_mutex);
+	mutex_init(&mxt->msg_mutex);
+	mxt_debug(DEBUG_TRACE, "maXTouch driver creating device name\n");
+
+	snprintf(mxt->phys_name,
+		 sizeof(mxt->phys_name), "%s/input0", dev_name(&client->dev)
+	    );
+	input->name = "atmel-maxtouch";
+	input->phys = mxt->phys_name;
+	input->id.bustype = BUS_I2C;
+	input->dev.parent = &client->dev;
+
+	mxt_debug(DEBUG_INFO, "maXTouch name: \"%s\"\n", input->name);
+	mxt_debug(DEBUG_INFO, "maXTouch phys: \"%s\"\n", input->phys);
+	mxt_debug(DEBUG_INFO, "maXTouch driver setting abs parameters\n");
+
+	set_bit(BTN_TOUCH, input->keybit);
+
+	/* Single touch */
+	input_set_abs_params(input, ABS_X, 0, mxt->max_x_val, 0, 0);
+	input_set_abs_params(input, ABS_Y, 0, mxt->max_y_val, 0, 0);
+	input_set_abs_params(input, ABS_PRESSURE, 0, MXT_MAX_REPORTED_PRESSURE,
+			     0, 0);
+	input_set_abs_params(input, ABS_TOOL_WIDTH, 0, MXT_MAX_REPORTED_WIDTH,
+			     0, 0);
+
+	/* Multitouch */
+	input_set_abs_params(input, ABS_MT_POSITION_X, 0, mxt->max_x_val, 0, 0);
+	input_set_abs_params(input, ABS_MT_POSITION_Y, 0, mxt->max_y_val, 0, 0);
+	input_set_abs_params(input, ABS_MT_TOUCH_MAJOR, 0, MXT_MAX_TOUCH_SIZE,
+			     0, 0);
+	input_set_abs_params(input, ABS_MT_TRACKING_ID, 0, MXT_MAX_NUM_TOUCHES,
+			     0, 0);
+
+	__set_bit(EV_ABS, input->evbit);
+	__set_bit(EV_SYN, input->evbit);
+	__set_bit(EV_KEY, input->evbit);
+
+	mxt_debug(DEBUG_TRACE, "maXTouch driver setting client data\n");
+	i2c_set_clientdata(client, mxt);
+	mxt_debug(DEBUG_TRACE, "maXTouch driver setting drv data\n");
+	input_set_drvdata(input, mxt);
+	mxt_debug(DEBUG_TRACE, "maXTouch driver input register device\n");
+	error = input_register_device(mxt->input);
+	if (error < 0) {
+		dev_err(&client->dev, "Failed to register input device\n");
+		goto err_register_device;
+	}
+
+	error = mxt_read_object_table(client, mxt, id_data);
+	if (error < 0)
+		goto err_read_ot;
+
+	/* Create debugfs entries. */
+	mxt->debug_dir = debugfs_create_dir("maXTouch", NULL);
+	if (mxt->debug_dir == -ENODEV) {
+		/* debugfs is not enabled. */
+		printk(KERN_WARNING "debugfs not enabled in kernel\n");
+	} else if (mxt->debug_dir == NULL) {
+		printk(KERN_WARNING "error creating debugfs dir\n");
+	} else {
+		mxt_debug(DEBUG_TRACE, "created \"maXTouch\" debugfs dir\n");
+
+		debugfs_create_file("deltas", S_IRUSR, mxt->debug_dir, mxt,
+				    &delta_fops);
+		debugfs_create_file("refs", S_IRUSR, mxt->debug_dir, mxt,
+				    &refs_fops);
+	}
+
+	/* Create character device nodes for reading & writing registers */
+	mxt->mxt_class = class_create(THIS_MODULE, "maXTouch_memory");
+	/* 2 numbers; one for memory and one for messages */
+	error = alloc_chrdev_region(&mxt->dev_num, 0, 2, "maXTouch_memory");
+	mxt_debug(DEBUG_VERBOSE,
+		  "device number %d allocated!\n", MAJOR(mxt->dev_num));
+	if (error)
+		printk(KERN_WARNING "Error registering device\n");
+	cdev_init(&mxt->cdev, &mxt_memory_fops);
+	cdev_init(&mxt->cdev_messages, &mxt_message_fops);
+
+	mxt_debug(DEBUG_VERBOSE, "cdev initialized\n");
+	mxt->cdev.owner = THIS_MODULE;
+	mxt->cdev_messages.owner = THIS_MODULE;
+
+	error = cdev_add(&mxt->cdev, mxt->dev_num, 1);
+	if (error)
+		printk(KERN_WARNING "Bad cdev\n");
+
+	error = cdev_add(&mxt->cdev_messages, mxt->dev_num + 1, 1);
+	if (error)
+		printk(KERN_WARNING "Bad cdev\n");
+
+	mxt_debug(DEBUG_VERBOSE, "cdev added\n");
+
+	device_create(mxt->mxt_class, NULL, MKDEV(MAJOR(mxt->dev_num), 0), NULL,
+		      "maXTouch");
+
+	device_create(mxt->mxt_class, NULL, MKDEV(MAJOR(mxt->dev_num), 1), NULL,
+		      "maXTouch_messages");
+
+	mxt->msg_buffer_startp = 0;
+	mxt->msg_buffer_endp = 0;
+
+	/* Allocate the interrupt */
+	mxt_debug(DEBUG_TRACE, "maXTouch driver allocating interrupt...\n");
+	mxt->irq = client->irq;
+	mxt->valid_irq_counter = 0;
+	mxt->invalid_irq_counter = 0;
+	mxt->irq_counter = 0;
+	if (mxt->irq) {
+		/* Try to request IRQ with falling edge first. This is
+		 * not always supported. If it fails, try with any edge. */
+		error = request_irq(mxt->irq,
+				    mxt_irq_handler,
+				    IRQF_TRIGGER_FALLING,
+				    client->dev.driver->name, mxt);
+		if (error < 0) {
+			/* TODO: why only 0 works on STK1000? */
+			error = request_irq(mxt->irq,
+					    mxt_irq_handler,
+					    0, client->dev.driver->name, mxt);
+		}
+
+		if (error < 0) {
+			dev_err(&client->dev,
+				"failed to allocate irq %d\n", mxt->irq);
+			goto err_irq;
+		}
+	}
+
+	if (debug > DEBUG_INFO)
+		dev_info(&client->dev, "touchscreen, irq %d\n", mxt->irq);
+
+	/* Schedule a worker routine to read any messages that might have
+	 * been sent before interrupts were enabled. */
+	cancel_delayed_work(&mxt->dwork);
+	schedule_delayed_work(&mxt->dwork, 0);
+	kfree(id_data);
+
+	/*
+	   TODO: REMOVE!!!!!!!!!!!!!!!!!!!!!!!
+
+	   REMOVE!!!!!!!!!!!!!!!!!!!!!!!
+	 */
+	mxt_write_byte(mxt->client,
+		       MXT_BASE_ADDR(MXT_TOUCH_MULTITOUCHSCREEN_T9, mxt), 15);
+
+	return 0;
+
+ err_irq:
+	kfree(mxt->rid_map);
+	kfree(mxt->object_table);
+	kfree(mxt->last_message);
+ err_read_ot:
+ err_register_device:
+ err_identify:
+ err_pdata:
+	input_free_device(input);
+ err_input_dev_alloc:
+	kfree(id_data);
+ err_id_alloc:
+	if (mxt->exit_hw != NULL)
+		mxt->exit_hw();
+	kfree(mxt);
+ err_mxt_alloc:
+	return error;
+}
+
+static int __devexit mxt_remove(struct i2c_client *client)
+{
+	struct mxt_data *mxt;
+
+	mxt = i2c_get_clientdata(client);
+
+	/* Remove debug dir entries */
+	debugfs_remove_recursive(mxt->debug_dir);
+
+	if (mxt != NULL) {
+
+		if (mxt->exit_hw != NULL)
+			mxt->exit_hw();
+
+		if (mxt->irq)
+			free_irq(mxt->irq, mxt);
+
+		unregister_chrdev_region(mxt->dev_num, 2);
+		device_destroy(mxt->mxt_class, MKDEV(MAJOR(mxt->dev_num), 0));
+		device_destroy(mxt->mxt_class, MKDEV(MAJOR(mxt->dev_num), 1));
+		cdev_del(&mxt->cdev);
+		cdev_del(&mxt->cdev_messages);
+		cancel_delayed_work_sync(&mxt->dwork);
+		input_unregister_device(mxt->input);
+		class_destroy(mxt->mxt_class);
+		debugfs_remove(mxt->debug_dir);
+
+		kfree(mxt->rid_map);
+		kfree(mxt->object_table);
+		kfree(mxt->last_message);
+	}
+	kfree(mxt);
+
+	i2c_set_clientdata(client, NULL);
+	if (debug >= DEBUG_TRACE)
+		dev_info(&client->dev, "Touchscreen unregistered\n");
+
+	return 0;
+}
+
+#if defined(CONFIG_PM)
+static int mxt_suspend(struct i2c_client *client, pm_message_t mesg)
+{
+	struct mxt_data *mxt = i2c_get_clientdata(client);
+
+	if (device_may_wakeup(&client->dev))
+		enable_irq_wake(mxt->irq);
+
+	return 0;
+}
+
+static int mxt_resume(struct i2c_client *client)
+{
+	struct mxt_data *mxt = i2c_get_clientdata(client);
+
+	if (device_may_wakeup(&client->dev))
+		disable_irq_wake(mxt->irq);
+
+	return 0;
+}
+#else
+#define mxt_suspend NULL
+#define mxt_resume NULL
+#endif
+
+static const struct i2c_device_id mxt_idtable[] = {
+	{"maXTouch", 0,},
+	{}
+};
+
+MODULE_DEVICE_TABLE(i2c, mxt_idtable);
+
+static struct i2c_driver mxt_driver = {
+	.driver = {
+		   .name = "maXTouch",
+		   .owner = THIS_MODULE,
+		   },
+
+	.id_table = mxt_idtable,
+	.probe = mxt_probe,
+	.remove = __devexit_p(mxt_remove),
+	.suspend = mxt_suspend,
+	.resume = mxt_resume,
+
+};
+
+static int __init mxt_init(void)
+{
+	int err;
+	err = i2c_add_driver(&mxt_driver);
+	if (err) {
+		printk(KERN_WARNING "Adding maXTouch driver failed "
+		       "(errno = %d)\n", err);
+	} else {
+		mxt_debug(DEBUG_TRACE, "Successfully added driver %s\n",
+			  mxt_driver.driver.name);
+	}
+	return err;
+}
+
+static void __exit mxt_cleanup(void)
+{
+	i2c_del_driver(&mxt_driver);
+}
+
+module_init(mxt_init);
+module_exit(mxt_cleanup);
+
+MODULE_AUTHOR("Iiro Valkonen");
+MODULE_DESCRIPTION("Driver for Atmel maXTouch Touchscreen Controller");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/tegra/Kconfig b/drivers/media/video/tegra/Kconfig
index ae77e8994dc8..1a122258ad82 100644
--- a/drivers/media/video/tegra/Kconfig
+++ b/drivers/media/video/tegra/Kconfig
@@ -8,3 +8,10 @@ config TEGRA_CAMERA
           Enables support for the Tegra camera interface
 
           If unsure, say Y
+
+config VIDEO_OV5650
+        tristate "OV5650 camera sensor support"
+        depends on I2C && ARCH_TEGRA
+        ---help---
+          This is a driver for the Omnivision OV5650 5MP camera sensor
+          for use with the tegra isp.
diff --git a/drivers/media/video/tegra/Makefile b/drivers/media/video/tegra/Makefile
index 68b5c42b0e7a..1ff76a82df40 100644
--- a/drivers/media/video/tegra/Makefile
+++ b/drivers/media/video/tegra/Makefile
@@ -1,2 +1,6 @@
+#
+# Makefile for the video capture/playback device drivers.
+#
 obj-y				+= avp/
-obj-$(CONFIG_TEGRA_CAMERA)		+= tegra_camera.o
+obj-$(CONFIG_TEGRA_CAMERA)	+= tegra_camera.o
+obj-$(CONFIG_VIDEO_OV5650)	+= ov5650.o
diff --git a/drivers/media/video/tegra/avp/avp.c b/drivers/media/video/tegra/avp/avp.c
index ced838ac6e2b..29cbfc01e44f 100644
--- a/drivers/media/video/tegra/avp/avp.c
+++ b/drivers/media/video/tegra/avp/avp.c
@@ -111,7 +111,7 @@ struct avp_info {
 
 	struct trpc_node		*rpc_node;
 	struct miscdevice		misc_dev;
-	bool				opened;
+	int 				refcount;
 	struct mutex			open_lock;
 
 	spinlock_t			state_lock;
@@ -1328,16 +1328,13 @@ static int tegra_avp_open(struct inode *inode, struct file *file)
 	nonseekable_open(inode, file);
 
 	mutex_lock(&avp->open_lock);
-	/* only one userspace client at a time */
-	if (avp->opened) {
-		pr_err("%s: already have client, aborting\n", __func__);
-		ret = -EBUSY;
-		goto out;
-	}
 
-	ret = avp_init(avp, TEGRA_AVP_KERNEL_FW);
-	avp->opened = !ret;
-out:
+	if (!avp->refcount)
+		ret = avp_init(avp, TEGRA_AVP_KERNEL_FW);
+
+	if (!ret)
+		avp->refcount++;
+
 	mutex_unlock(&avp->open_lock);
 	return ret;
 }
@@ -1349,15 +1346,16 @@ static int tegra_avp_release(struct inode *inode, struct file *file)
 
 	pr_info("%s: release\n", __func__);
 	mutex_lock(&avp->open_lock);
-	if (!avp->opened) {
+	if (!avp->refcount) {
 		pr_err("%s: releasing while in invalid state\n", __func__);
 		ret = -EINVAL;
 		goto out;
 	}
+	if (avp->refcount > 0)
+		avp->refcount--;
+	if (!avp->refcount)
+		avp_uninit(avp);
 
-	avp_uninit(avp);
-
-	avp->opened = false;
 out:
 	mutex_unlock(&avp->open_lock);
 	return ret;
@@ -1681,12 +1679,11 @@ static int tegra_avp_remove(struct platform_device *pdev)
 		return 0;
 
 	mutex_lock(&avp->open_lock);
-	if (avp->opened) {
+	if (avp->refcount) {
 		mutex_unlock(&avp->open_lock);
 		return -EBUSY;
 	}
 	/* ensure that noone can open while we tear down */
-	avp->opened = true;
 	mutex_unlock(&avp->open_lock);
 
 	misc_deregister(&avp->misc_dev);
diff --git a/drivers/media/video/tegra/ov5650.c b/drivers/media/video/tegra/ov5650.c
new file mode 100644
index 000000000000..579249da8f43
--- /dev/null
+++ b/drivers/media/video/tegra/ov5650.c
@@ -0,0 +1,765 @@
+/*
+ * ov5650.c - ov5650 sensor driver
+ *
+ * Copyright (C) 2010 Google Inc.
+ *
+ * Contributors:
+ *      Rebecca Schultz Zavin <rebecca@android.com>
+ *
+ * Leverage OV9640.c
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/i2c.h>
+#include <linux/miscdevice.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+#include <media/ov5650.h>
+
+struct ov5650_reg {
+	u16 addr;
+	u16 val;
+};
+
+struct ov5650_info {
+	int mode;
+	struct i2c_client *i2c_client;
+	struct ov5650_platform_data *pdata;
+};
+
+#define OV5650_TABLE_WAIT_MS 0
+#define OV5650_TABLE_END 1
+#define OV5650_MAX_RETRIES 3
+
+static struct ov5650_reg mode_start[] = {
+	{0x3008, 0x82}, /* reset registers pg 72 */
+	{OV5650_TABLE_WAIT_MS, 5},
+	{0x3008, 0x42}, /* register power down pg 72 */
+	{OV5650_TABLE_WAIT_MS, 5},
+	{0x3103, 0x93}, /* power up system clock from PLL page 77 */
+	{0x3017, 0xff}, /* PAD output enable page 100 */
+	{0x3018, 0xfc}, /* PAD output enable page 100 */
+
+	{0x3600, 0x50}, /* analog pg 108 */
+	{0x3601, 0x0d}, /* analog pg 108 */
+	{0x3604, 0x50}, /* analog pg 108 */
+	{0x3605, 0x04}, /* analog pg 108 */
+	{0x3606, 0x3f}, /* analog pg 108 */
+	{0x3612, 0x1a}, /* analog pg 108 */
+	{0x3630, 0x22}, /* analog pg 108 */
+	{0x3631, 0x22}, /* analog pg 108 */
+	{0x3702, 0x3a}, /* analog pg 108 */
+	{0x3704, 0x18}, /* analog pg 108 */
+	{0x3705, 0xda}, /* analog pg 108 */
+	{0x3706, 0x41}, /* analog pg 108 */
+	{0x370a, 0x80}, /* analog pg 108 */
+	{0x370b, 0x40}, /* analog pg 108 */
+	{0x370e, 0x00}, /* analog pg 108 */
+	{0x3710, 0x28}, /* analog pg 108 */
+	{0x3712, 0x13}, /* analog pg 108 */
+	{0x3830, 0x50}, /* manual exposure gain bit [0] */
+	{0x3a18, 0x00}, /* AEC gain ceiling bit 8 pg 114 */
+	{0x3a19, 0xf8}, /* AEC gain ceiling pg 114 */
+	{0x3a00, 0x38}, /* AEC control 0 debug mode band low
+			   limit mode band func pg 112 */
+
+	{0x3603, 0xa7}, /* analog pg 108 */
+	{0x3615, 0x50}, /* analog pg 108 */
+	{0x3620, 0x56}, /* analog pg 108 */
+	{0x3810, 0x00}, /* TIMING HVOFFS both are zero pg 80 */
+	{0x3836, 0x00}, /* TIMING HVPAD both are zero pg 82 */
+	{0x3a1a, 0x06}, /* DIFF MAX an AEC register??? pg 114 */
+	{0x4000, 0x01}, /* BLC enabled pg 120 */
+	{0x401c, 0x48}, /* reserved pg 120 */
+	{0x401d, 0x28}, /* BLC control pg 120 */
+	{0x5000, 0x00}, /* ISP control00 features are disabled. pg 132 */
+	{0x5001, 0x00}, /* ISP control01 awb disabled. pg 132 */
+	{0x5002, 0x00}, /* ISP control02 debug mode disabled pg 132 */
+	{0x503d, 0x00}, /* ISP control3D features disabled pg 133 */
+	{0x5046, 0x00}, /* ISP control isp disable awbg disable pg 133 */
+
+	{0x300f, 0x8f}, /* PLL control00 R_SELD5 [7:6] div by 4 R_DIVL [2]
+			   two lane div 1 SELD2P5 [1:0] div 2.5 pg 99 */
+	{0x3010, 0x10}, /* PLL control01 DIVM [3:0] DIVS [7:4] div 1 pg 99 */
+	{0x3011, 0x14}, /* PLL control02 R_DIVP [5:0] div 20 pg 99 */
+	{0x3012, 0x02}, /* PLL CTR 03, default */
+	{0x3815, 0x82}, /* PCLK to SCLK ratio bit[4:0] is set to 2 pg 81 */
+	{0x3503, 0x33}, /* AEC auto AGC auto gain has no latch delay. pg 38 */
+	/*	{FAST_SETMODE_START, 0}, */
+	{0x3613, 0x44}, /* analog pg 108 */
+	{OV5650_TABLE_END, 0x0},
+};
+
+static struct ov5650_reg mode_2592x1944[] = {
+	{0x3621, 0x2f}, /* analog horizontal binning/sampling not enabled.
+			   pg 108 */
+	{0x3632, 0x55}, /* analog pg 108 */
+	{0x3703, 0xe6}, /* analog pg 108 */
+	{0x370c, 0xa0}, /* analog pg 108 */
+	{0x370d, 0x04}, /* analog pg 108 */
+	{0x3713, 0x2f}, /* analog pg 108 */
+	{0x3800, 0x02}, /* HREF start point higher 4 bits [3:0] pg 108 */
+	{0x3801, 0x58}, /* HREF start point lower  8 bits [7:0] pg 108 */
+	{0x3802, 0x00}, /* VREF start point higher 4 bits [3:0] pg 108 */
+	{0x3803, 0x0c}, /* VREF start point [7:0] pg 108 */
+	{0x3804, 0x0a}, /* HREF width  higher 4 bits [3:0] pg 108 */
+	{0x3805, 0x20}, /* HREF width  lower  8 bits [7:0] pg 108 */
+	{0x3806, 0x07}, /* VREF height higher 4 bits [3:0] pg 109 */
+	{0x3807, 0xa0}, /* VREF height lower  8 bits [7:0] pg 109 */
+	{0x3808, 0x0a}, /* DVP horizontal output size higher 4 bits [3:0]
+			   pg 109 */
+	{0x3809, 0x20}, /* DVP horizontal output size lower  8 bits [7:0]
+			   pg 109 */
+	{0x380a, 0x07}, /* DVP vertical   output size higher 4 bits [3:0]
+			   pg 109 */
+	{0x380b, 0xa0}, /* DVP vertical   output size lower  8 bits [7:0]
+			   pg 109 */
+	{0x380c, 0x0c}, /* total horizontal size higher 5 bits [4:0] pg 109,
+			   line length */
+	{0x380d, 0xb4}, /* total horizontal size lower  8 bits [7:0] pg 109,
+			   line length */
+	{0x380e, 0x07}, /* total vertical   size higher 5 bits [4:0] pg 109,
+			   frame length */
+	{0x380f, 0xb0}, /* total vertical   size lower  8 bits [7:0] pg 109,
+			   frame length */
+	{0x3818, 0xc0}, /* timing control reg18 mirror & dkhf pg 110 */
+	{0x381a, 0x3c}, /* HS mirror adjustment pg 110 */
+	{0x3a0d, 0x06}, /* b60 max pg 113 */
+	{0x3c01, 0x00}, /* 5060HZ_CTRL01 pg 116 */
+	{0x3007, 0x3f}, /* clock enable03 pg 98 */
+	{0x5059, 0x80}, /* => NOT found */
+	{0x3003, 0x03}, /* reset MIPI and DVP pg 97 */
+	{0x3500, 0x00}, /* long exp 1/3 in unit of 1/16 line, pg 38 */
+	{0x3501, 0x7a}, /* long exp 2/3 in unit of 1/16 line, pg 38,
+			   note frame length start with 0x7b0,
+			   and SENSOR_BAYER_DEFAULT_MAX_COARSE_DIFF=3 */
+	{0x3502, 0xd0}, /* long exp 3/3 in unit of 1/16 line, pg 38.
+			   Two lines of integration time. */
+	{0x350a, 0x00}, /* gain output to sensor, pg 38 */
+	{0x350b, 0x00}, /* gain output to sensor, pg 38 */
+	{0x4801, 0x0f}, /* MIPI control01 pg 125 */
+	{0x300e, 0x0c}, /* SC_MIPI_SC_CTRL0 pg 73 */
+	{0x4803, 0x50}, /* MIPI CTRL3 pg 91 */
+	{0x4800, 0x34}, /* MIPI CTRl0 idle and short line pg 89 */
+	{OV5650_TABLE_END, 0x0000}
+};
+
+static struct ov5650_reg mode_1296x972[] = {
+	{0x3621, 0xaf}, /* analog horizontal binning/sampling not enabled.
+			   pg 108 */
+	{0x3632, 0x5a}, /* analog pg 108 */
+	{0x3703, 0xb0}, /* analog pg 108 */
+	{0x370c, 0xc5}, /* analog pg 108 */
+	{0x370d, 0x42}, /* analog pg 108 */
+	{0x3713, 0x2f}, /* analog pg 108 */
+	{0x3800, 0x03}, /* HREF start point higher 4 bits [3:0] pg 108 */
+	{0x3801, 0x3c}, /* HREF start point lower  8 bits [7:0] pg 108 */
+	{0x3802, 0x00}, /* VREF start point higher 4 bits [3:0] pg 108 */
+	{0x3803, 0x06}, /* VREF start point [7:0] pg 108 */
+	{0x3804, 0x05}, /* HREF width  higher 4 bits [3:0] pg 108 */
+	{0x3805, 0x10}, /* HREF width  lower  8 bits [7:0] pg 108 */
+	{0x3806, 0x03}, /* VREF height higher 4 bits [3:0] pg 109 */
+	{0x3807, 0xd0}, /* VREF height lower  8 bits [7:0] pg 109 */
+	{0x3808, 0x05}, /* DVP horizontal output size higher 4 bits [3:0]
+			   pg 109 */
+	{0x3809, 0x10}, /* DVP horizontal output size lower  8 bits [7:0]
+			   pg 109 */
+	{0x380a, 0x03}, /* DVP vertical   output size higher 4 bits [3:0]
+			   pg 109 */
+	{0x380b, 0xd0}, /* DVP vertical   output size lower  8 bits [7:0]
+			   pg 109 */
+	{0x380c, 0x08}, /* total horizontal size higher 5 bits [4:0]
+			   pg 109, line length */
+	{0x380d, 0xa8}, /* total horizontal size lower  8 bits [7:0] pg 109,
+			   line length */
+	{0x380e, 0x05}, /* total vertical   size higher 5 bits [4:0] pg 109,
+			   frame length */
+	{0x380f, 0xa4}, /* total horizontal size lower  8 bits [7:0] pg 109,
+			   frame length */
+	{0x3818, 0xc1}, /* timing control reg18 mirror & dkhf pg 110 */
+	{0x381a, 0x00}, /* HS mirror adjustment pg 110 */
+	{0x3a0d, 0x08}, /* b60 max pg 113 */
+	{0x3c01, 0x00}, /* 5060HZ_CTRL01 pg 116 */
+	{0x3007, 0x3b}, /* clock enable03 pg 98 */
+	{0x5059, 0x80}, /* => NOT found. added */
+	{0x3003, 0x03}, /* reset MIPI and DVP pg 97 */
+	{0x3500, 0x00}, /* long exp 1/3 in unit of 1/16 line, pg 38,
+			   note frame length is from 0x5a4,
+			   and SENSOR_BAYER_DEFAULT_MAX_COARSE_DIFF=3 */
+	{0x3501, 0x5a}, /* long exp 2/3 in unit of 1/16 line, pg 38 */
+	{0x3502, 0x10}, /* long exp 3/3 in unit of 1/16 line, pg 38 */
+	{0x350a, 0x00}, /* gain output to sensor, pg 38 */
+	{0x350b, 0x10}, /* gain output to sensor, pg 38 */
+	{0x4801, 0x0f}, /* MIPI control01 pg 125 */
+	{0x300e, 0x0c}, /* SC_MIPI_SC_CTRL0 pg 73 */
+	{0x4803, 0x50}, /* MIPI CTRL3 pg 91 */
+	{0x4800, 0x34}, /* MIPI CTRl0 idle and short line pg 89 */
+	{OV5650_TABLE_END, 0x0000}
+};
+
+static struct ov5650_reg mode_1920x1088[] = {
+	{0x3621, 0x2f}, /* analog horizontal binning/sampling not enabled.
+			   pg 108 */
+	{0x3632, 0x55}, /* analog pg 108 */
+	{0x3703, 0xe6}, /* analog pg 108 */
+	{0x370c, 0xa0}, /* analog pg 108 */
+	{0x370d, 0x04}, /* analog pg 108 */
+	{0x3713, 0x2f}, /* analog pg 108 */
+	{0x3800, 0x02}, /* HREF start point higher 4 bits [3:0] pg 108 */
+	{0x3801, 0x58}, /* HREF start point lower  8 bits [7:0] pg 108 */
+	{0x3802, 0x00}, /* VREF start point higher 4 bits [3:0] pg 108 */
+	{0x3803, 0x0c}, /* VREF start point [7:0] pg 108 */
+	{0x3804, 0x0a}, /* HREF width  higher 4 bits [3:0] pg 108 */
+	{0x3805, 0x20}, /* HREF width  lower  8 bits [7:0] pg 108 */
+	{0x3806, 0x07}, /* VREF height higher 4 bits [3:0] pg 109 */
+	{0x3807, 0xa0}, /* VREF height lower  8 bits [7:0] pg 109 */
+	{0x3808, 0x0a}, /* DVP horizontal output size higher 4 bits [3:0]
+			   pg 109 */
+	{0x3809, 0x20}, /* DVP horizontal output size lower  8 bits [7:0]
+			   pg 109 */
+	{0x380a, 0x07}, /* DVP vertical   output size higher 4 bits [3:0]
+			   pg 109 */
+	{0x380b, 0xa0}, /* DVP vertical   output size lower  8 bits [7:0]
+			   pg 109 */
+	{0x380c, 0x0c}, /* total horizontal size higher 5 bits [4:0] pg 109,
+			   line length */
+	{0x380d, 0xb4}, /* total horizontal size lower  8 bits [7:0] pg 109,
+			   line length */
+	{0x380e, 0x07}, /* total vertical size higher 5 bits [4:0] pg 109,
+			   frame length */
+	{0x380f, 0xb0}, /* total vertical size lower  8 bits [7:0] pg 109,
+			   frame length */
+	{0x3818, 0xc0}, /* timing control reg18 mirror & dkhf pg 110 */
+	{0x381a, 0x3c}, /* HS mirror adjustment pg 110 */
+	{0x3a0d, 0x06}, /* b60 max pg 113 */
+	{0x3c01, 0x00}, /* 5060HZ_CTRL01 pg 116 */
+	{0x3007, 0x3f}, /* clock enable03 pg 98 */
+	{0x5059, 0x80}, /* => NOT found */
+	{0x3003, 0x03}, /* reset MIPI and DVP pg 97 */
+	{0x3500, 0x00}, /* long exp 1/3 in unit of 1/16 line, pg 38 */
+	{0x3501, 0x7a}, /* long exp 2/3 in unit of 1/16 line, pg 38,
+			   note frame length start with 0x7b0,
+			   and SENSOR_BAYER_DEFAULT_MAX_COARSE_DIFF=3 */
+	{0x3502, 0xd0}, /* long exp 3/3 in unit of 1/16 line, pg 38.
+			   Two lines of integration time. */
+	{0x350a, 0x00}, /* gain output to sensor, pg 38 */
+	{0x350b, 0x00}, /* gain output to sensor, pg 38 */
+	{0x4801, 0x0f}, /* MIPI control01 pg 125 */
+	{0x300e, 0x0c}, /* SC_MIPI_SC_CTRL0 pg 73 */
+	{0x4803, 0x50}, /* MIPI CTRL3 pg 91 */
+	{0x4800, 0x34}, /* MIPI CTRl0 idle and short line pg 89 */
+	{OV5650_TABLE_END, 0x0000}
+};
+
+static struct ov5650_reg mode_1264x704[] = {
+	{0x3600, 0x54}, /* analog pg 108 */
+	{0x3601, 0x05}, /* analog pg 108 */
+	{0x3604, 0x40}, /* analog pg 108 */
+	{0x3705, 0xdb}, /* analog pg 108 */
+	{0x370a, 0x81}, /* analog pg 108 */
+	{0x3615, 0x52}, /* analog pg 108 */
+	{0x3810, 0x40}, /* TIMING HVOFFS both are zero pg 80 */
+	{0x3836, 0x41}, /* TIMING HVPAD both are zero pg 82 */
+	{0x4000, 0x05}, /* BLC enabled pg 120 */
+	{0x401c, 0x42}, /* reserved pg 120 */
+	{0x5046, 0x09}, /* ISP control isp disable awbg disable pg 133 */
+	{0x3010, 0x00}, /* PLL control01 DIVM [3:0] DIVS [7:4] div 1 pg 99 */
+	{0x3503, 0x00}, /* AEC auto AGC auto gain has no latch delay. pg 38 */
+	{0x3613, 0xc4}, /* analog pg 108 */
+
+	{0x3621, 0xaf}, /* analog horizontal binning/sampling not enabled.
+			   pg 108 */
+	{0x3632, 0x55}, /* analog pg 108 */
+	{0x3703, 0x9a}, /* analog pg 108 */
+	{0x370c, 0x00}, /* analog pg 108 */
+	{0x370d, 0x42}, /* analog pg 108 */
+	{0x3713, 0x22}, /* analog pg 108 */
+	{0x3800, 0x02}, /* HREF start point higher 4 bits [3:0] pg 108 */
+	{0x3801, 0x54}, /* HREF start point lower  8 bits [7:0] pg 108 */
+	{0x3802, 0x00}, /* VREF start point higher 4 bits [3:0] pg 108 */
+	{0x3803, 0x0c}, /* VREF start point [7:0] pg 108 */
+	{0x3804, 0x05}, /* HREF width  higher 4 bits [3:0] pg 108 */
+	{0x3805, 0x00}, /* HREF width  lower  8 bits [7:0] pg 108 */
+	{0x3806, 0x02}, /* VREF height higher 4 bits [3:0] pg 109 */
+	{0x3807, 0xd0}, /* VREF height lower  8 bits [7:0] pg 109 */
+	{0x3808, 0x05}, /* DVP horizontal output size higher 4 bits [3:0]
+			   pg 109 */
+	{0x3809, 0x00}, /* DVP horizontal output size lower  8 bits [7:0]
+			   pg 109 */
+	{0x380a, 0x02}, /* DVP vertical   output size higher 4 bits [3:0]
+			   pg 109 */
+	{0x380b, 0xd0}, /* DVP vertical   output size lower  8 bits [7:0]
+			   pg 109 */
+	{0x380c, 0x08}, /* total horizontal size higher 5 bits [4:0] pg 109,
+			   line length */
+	{0x380d, 0x72}, /* total horizontal size lower  8 bits [7:0] pg 109,
+			   line length */
+	{0x380e, 0x02}, /* total vertical size higher 5 bits [4:0] pg 109,
+			   frame length */
+	{0x380f, 0xe4}, /* total vertical size lower  8 bits [7:0] pg 109,
+			   frame length */
+	{0x3818, 0xc1}, /* timing control reg18 mirror & dkhf pg 110 */
+	{0x381a, 0x3c}, /* HS mirror adjustment pg 110 */
+	{0x3a0d, 0x06}, /* b60 max pg 113 */
+	{0x3c01, 0x34}, /* 5060HZ_CTRL01 pg 116 */
+	{0x3007, 0x3b}, /* clock enable03 pg 98 */
+	{0x5059, 0x80}, /* => NOT found */
+	{0x3003, 0x03}, /* reset MIPI and DVP pg 97 */
+	{0x3500, 0x04}, /* long exp 1/3 in unit of 1/16 line, pg 38 */
+	{0x3501, 0xa5}, /* long exp 2/3 in unit of 1/16 line, pg 38,
+			   note frame length start with 0x7b0,
+			   and SENSOR_BAYER_DEFAULT_MAX_COARSE_DIFF=3 */
+	{0x3502, 0x10}, /* long exp 3/3 in unit of 1/16 line, pg 38.
+			   Two lines of integration time. */
+	{0x350a, 0x00}, /* gain output to sensor, pg 38 */
+	{0x350b, 0x00}, /* gain output to sensor, pg 38 */
+	{0x4801, 0x0f}, /* MIPI control01 pg 125 */
+	{0x300e, 0x0c}, /* SC_MIPI_SC_CTRL0 pg 73 */
+	{0x4803, 0x50}, /* MIPI CTRL3 pg 91 */
+	{0x4800, 0x24}, /* MIPI CTRl0 idle and short line pg 89 */
+
+	{0x300f, 0x8b}, /* PLL control00 R_SELD5 [7:6] div by 4 R_DIVL [2]
+			   two lane div 1 SELD2P5 [1:0] div 2.5 pg 99 */
+
+	{0x3711, 0x24},
+	{0x3713, 0x92},
+	{0x3714, 0x17},
+	{0x381c, 0x10},
+	{0x381d, 0x82},
+	{0x381e, 0x05},
+	{0x381f, 0xc0},
+	{0x3821, 0x20},
+	{0x3824, 0x23},
+	{0x3825, 0x2c},
+	{0x3826, 0x00},
+	{0x3827, 0x0c},
+	{0x3623, 0x01},
+	{0x3633, 0x24},
+	{0x3632, 0x5f},
+	{0x401f, 0x03},
+
+	{OV5650_TABLE_END, 0x0000}
+};
+
+static struct ov5650_reg mode_end[] = {
+	{0x3212, 0x00}, /* SRM_GROUP_ACCESS (group hold begin) */
+	{0x3003, 0x01}, /* reset DVP pg 97 */
+	{0x3212, 0x10}, /* SRM_GROUP_ACCESS (group hold end) */
+	{0x3212, 0xa0}, /* SRM_GROUP_ACCESS (group hold launch) */
+	{0x3008, 0x02}, /* SYSTEM_CTRL0 mipi suspend mask pg 98 */
+
+	/*	{FAST_SETMODE_END, 0}, */
+	{OV5650_TABLE_END, 0x0000}
+};
+
+enum {
+	OV5650_MODE_2592x1944,
+	OV5650_MODE_1296x972,
+	OV5650_MODE_1920x1088,
+	OV5650_MODE_1264x704,
+};
+
+static struct ov5650_reg *mode_table[] = {
+	[OV5650_MODE_2592x1944] = mode_2592x1944,
+	[OV5650_MODE_1296x972] = mode_1296x972,
+	[OV5650_MODE_1920x1088] = mode_1920x1088,
+	[OV5650_MODE_1264x704] = mode_1264x704,
+};
+
+/* 2 regs to program frame length */
+static inline void ov5650_get_frame_length_regs(struct ov5650_reg *regs,
+						u32 frame_length)
+{
+	regs->addr = 0x380e;
+	regs->val = (frame_length >> 8) & 0xff;
+	(regs + 1)->addr = 0x380f;
+	(regs + 1)->val = (frame_length) & 0xff;
+}
+
+/* 3 regs to program coarse time */
+static inline void ov5650_get_coarse_time_regs(struct ov5650_reg *regs,
+                                               u32 coarse_time)
+{
+	regs->addr = 0x3500;
+	regs->val = (coarse_time >> 12) & 0xff;
+	(regs + 1)->addr = 0x3501;
+	(regs + 1)->val = (coarse_time >> 4) & 0xff;
+	(regs + 2)->addr = 0x3502;
+	(regs + 2)->val = (coarse_time & 0xf) << 4;
+}
+
+/* 1 reg to program gain */
+static inline void ov5650_get_gain_reg(struct ov5650_reg *regs, u16 gain)
+{
+	regs->addr = 0x350b;
+	regs->val = gain;
+}
+
+static int ov5650_read_reg(struct i2c_client *client, u16 addr, u8 *val)
+{
+	int err;
+	struct i2c_msg msg[2];
+	unsigned char data[3];
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	msg[0].addr = client->addr;
+	msg[0].flags = 0;
+	msg[0].len = 2;
+	msg[0].buf = data;
+
+	/* high byte goes out first */
+	data[0] = (u8) (addr >> 8);;
+	data[1] = (u8) (addr & 0xff);
+
+	msg[1].addr = client->addr;
+	msg[1].flags = I2C_M_RD;
+	msg[1].len = 1;
+	msg[1].buf = data + 2;
+
+	err = i2c_transfer(client->adapter, msg, 2);
+
+	if (err != 2)
+		return -EINVAL;
+
+	*val = data[2];
+
+	return 0;
+}
+
+static int ov5650_write_reg(struct i2c_client *client, u16 addr, u8 val)
+{
+	int err;
+	struct i2c_msg msg;
+	unsigned char data[3];
+	int retry = 0;
+
+	if (!client->adapter)
+		return -ENODEV;
+
+	data[0] = (u8) (addr >> 8);;
+	data[1] = (u8) (addr & 0xff);
+	data[2] = (u8) (val & 0xff);
+
+	msg.addr = client->addr;
+	msg.flags = 0;
+	msg.len = 3;
+	msg.buf = data;
+
+	do {
+		err = i2c_transfer(client->adapter, &msg, 1);
+		if (err == 1)
+			return 0;
+		retry++;
+		pr_err("ov5650: i2c transfer failed, retrying %x %x\n",
+		       addr, val);
+		msleep(3);
+	} while (retry <= OV5650_MAX_RETRIES);
+
+	return err;
+}
+
+static int ov5650_write_table(struct i2c_client *client,
+			      const struct ov5650_reg table[],
+			      const struct ov5650_reg override_list[],
+			      int num_override_regs)
+{
+	int err;
+	const struct ov5650_reg *next;
+	int i;
+	u16 val;
+
+	for (next = table; next->addr != OV5650_TABLE_END; next++) {
+		if (next->addr == OV5650_TABLE_WAIT_MS) {
+			msleep(next->val);
+			continue;
+		}
+
+		val = next->val;
+
+		/* When an override list is passed in, replace the reg */
+		/* value to write if the reg is in the list            */
+		if (override_list) {
+			for (i = 0; i < num_override_regs; i++) {
+				if (next->addr == override_list[i].addr) {
+					val = override_list[i].val;
+					break;
+				}
+			}
+		}
+
+		err = ov5650_write_reg(client, next->addr, val);
+		if (err)
+			return err;
+	}
+	return 0;
+}
+
+static int ov5650_set_mode(struct ov5650_info *info, struct ov5650_mode *mode)
+{
+	int sensor_mode;
+	int err;
+	struct ov5650_reg reg_list[6];
+
+	pr_info("%s: xres %u yres %u framelength %u coarsetime %u gain %u\n",
+		__func__, mode->xres, mode->yres, mode->frame_length,
+		mode->coarse_time, mode->gain);
+	if (mode->xres == 2592 && mode->yres == 1944)
+		sensor_mode = OV5650_MODE_2592x1944;
+	else if (mode->xres == 1296 && mode->yres == 972)
+		sensor_mode = OV5650_MODE_1296x972;
+	else if (mode->xres == 1920 && mode->yres == 1088)
+		sensor_mode = OV5650_MODE_1920x1088;
+	else if (mode->xres == 1264 && mode->yres == 704)
+		sensor_mode = OV5650_MODE_1264x704;
+	else {
+		pr_err("%s: invalid resolution supplied to set mode %d %d\n",
+		       __func__, mode->xres, mode->yres);
+		return -EINVAL;
+	}
+
+	/* get a list of override regs for the asking frame length, */
+	/* coarse integration time, and gain.                       */
+	ov5650_get_frame_length_regs(reg_list, mode->frame_length);
+	ov5650_get_coarse_time_regs(reg_list + 2, mode->coarse_time);
+	ov5650_get_gain_reg(reg_list + 5, mode->gain);
+
+	err = ov5650_write_table(info->i2c_client, mode_start, NULL, 0);
+	if (err)
+		return err;
+
+	err = ov5650_write_table(info->i2c_client, mode_table[sensor_mode],
+		reg_list, 6);
+	if (err)
+		return err;
+
+	err = ov5650_write_table(info->i2c_client, mode_end, NULL, 0);
+	if (err)
+		return err;
+
+	info->mode = sensor_mode;
+	return 0;
+}
+
+static int ov5650_set_frame_length(struct ov5650_info *info, u32 frame_length)
+{
+	struct ov5650_reg reg_list[2];
+	int i = 0;
+	int ret;
+
+	ov5650_get_frame_length_regs(reg_list, frame_length);
+
+	for (i = 0; i < 2; i++)	{
+		ret = ov5650_write_reg(info->i2c_client, reg_list[i].addr,
+			reg_list[i].val);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int ov5650_set_coarse_time(struct ov5650_info *info, u32 coarse_time)
+{
+	int ret;
+
+	struct ov5650_reg reg_list[3];
+	int i = 0;
+
+	ov5650_get_coarse_time_regs(reg_list, coarse_time);
+
+	ret = ov5650_write_reg(info->i2c_client, 0x3212, 0x01);
+	if (ret)
+		return ret;
+
+	for (i = 0; i < 3; i++)	{
+		ret = ov5650_write_reg(info->i2c_client, reg_list[i].addr,
+			reg_list[i].val);
+		if (ret)
+			return ret;
+	}
+
+	ret = ov5650_write_reg(info->i2c_client, 0x3212, 0x11);
+	if (ret)
+		return ret;
+
+	ret = ov5650_write_reg(info->i2c_client, 0x3212, 0xa1);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int ov5650_set_gain(struct ov5650_info *info, u16 gain)
+{
+	int ret;
+	struct ov5650_reg reg_list;
+
+	ov5650_get_gain_reg(&reg_list, gain);
+
+	ret = ov5650_write_reg(info->i2c_client, reg_list.addr, reg_list.val);
+
+	return ret;
+}
+
+static int ov5650_get_status(struct ov5650_info *info, u8 *status)
+{
+	int err;
+
+	*status = 0;
+	err = ov5650_read_reg(info->i2c_client, 0x002, status);
+	return err;
+}
+
+
+static long ov5650_ioctl(struct file *file,
+			 unsigned int cmd, unsigned long arg)
+{
+	int err;
+	struct ov5650_info *info = file->private_data;
+
+	switch (cmd) {
+	case OV5650_IOCTL_SET_MODE:
+	{
+		struct ov5650_mode mode;
+		if (copy_from_user(&mode,
+				   (const void __user *)arg,
+				   sizeof(struct ov5650_mode))) {
+			return -EFAULT;
+		}
+
+		return ov5650_set_mode(info, &mode);
+	}
+	case OV5650_IOCTL_SET_FRAME_LENGTH:
+		return ov5650_set_frame_length(info, (u32)arg);
+	case OV5650_IOCTL_SET_COARSE_TIME:
+		return ov5650_set_coarse_time(info, (u32)arg);
+	case OV5650_IOCTL_SET_GAIN:
+		return ov5650_set_gain(info, (u16)arg);
+	case OV5650_IOCTL_GET_STATUS:
+	{
+		u8 status;
+
+		err = ov5650_get_status(info, &status);
+		if (err)
+			return err;
+		if (copy_to_user((void __user *)arg, &status,
+				 2)) {
+			return -EFAULT;
+		}
+		return 0;
+	}
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static struct ov5650_info *info;
+
+static int ov5650_open(struct inode *inode, struct file *file)
+{
+	u8 status;
+
+	file->private_data = info;
+	if (info->pdata && info->pdata->power_on)
+		info->pdata->power_on();
+	ov5650_get_status(info, &status);
+	return 0;
+}
+
+int ov5650_release(struct inode *inode, struct file *file)
+{
+	if (info->pdata && info->pdata->power_off)
+		info->pdata->power_off();
+	file->private_data = NULL;
+	return 0;
+}
+
+
+static const struct file_operations ov5650_fileops = {
+	.owner = THIS_MODULE,
+	.open = ov5650_open,
+	.unlocked_ioctl = ov5650_ioctl,
+	.release = ov5650_release,
+};
+
+static struct miscdevice ov5650_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "ov5650",
+	.fops = &ov5650_fileops,
+};
+
+static int ov5650_probe(struct i2c_client *client,
+			const struct i2c_device_id *id)
+{
+	int err;
+
+	pr_info("ov5650: probing sensor.\n");
+
+	info = kzalloc(sizeof(struct ov5650_info), GFP_KERNEL);
+	if (!info) {
+		pr_err("ov5650: Unable to allocate memory!\n");
+		return -ENOMEM;
+	}
+
+	err = misc_register(&ov5650_device);
+	if (err) {
+		pr_err("ov5650: Unable to register misc device!\n");
+		kfree(info);
+		return err;
+	}
+
+	info->pdata = client->dev.platform_data;
+	info->i2c_client = client;
+
+	i2c_set_clientdata(client, info);
+	return 0;
+}
+
+static int ov5650_remove(struct i2c_client *client)
+{
+	struct ov5650_info *info;
+	info = i2c_get_clientdata(client);
+	misc_deregister(&ov5650_device);
+	kfree(info);
+	return 0;
+}
+
+static const struct i2c_device_id ov5650_id[] = {
+	{ "ov5650", 0 },
+	{ },
+};
+
+MODULE_DEVICE_TABLE(i2c, ov5650_id);
+
+static struct i2c_driver ov5650_i2c_driver = {
+	.driver = {
+		.name = "ov5650",
+		.owner = THIS_MODULE,
+	},
+	.probe = ov5650_probe,
+	.remove = ov5650_remove,
+	.id_table = ov5650_id,
+};
+
+static int __init ov5650_init(void)
+{
+	pr_info("ov5650 sensor driver loading\n");
+	return i2c_add_driver(&ov5650_i2c_driver);
+}
+
+static void __exit ov5650_exit(void)
+{
+	i2c_del_driver(&ov5650_i2c_driver);
+}
+
+module_init(ov5650_init);
+module_exit(ov5650_exit);
+
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 0d762688effe..008179158b78 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -303,6 +303,16 @@ config MFD_MAX8998
 	  accessing the device, additional drivers must be enabled in order
 	  to use the functionality of the device.
 
+config MFD_MAX8907C
+	tristate "Maxim Semiconductor MAX8907C PMIC Support"
+	select MFD_CORE
+	depends on I2C
+	help
+	  Say yes here to support for Maxim Semiconductor MAX8907C. This is
+	  a Power Management IC. This driver provies common support for
+	  accessing the device, additional drivers must be enabled in order
+	  to use the functionality of the device.
+
 config MFD_WM8400
 	tristate "Support Wolfson Microelectronics WM8400"
 	select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index feaeeaeeddb7..fdfc6f01aa82 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -76,3 +76,5 @@ obj-$(CONFIG_MFD_RDC321X)	+= rdc321x-southbridge.o
 obj-$(CONFIG_MFD_JANZ_CMODIO)	+= janz-cmodio.o
 obj-$(CONFIG_MFD_JZ4740_ADC)	+= jz4740-adc.o
 obj-$(CONFIG_MFD_TPS6586X)	+= tps6586x.o
+obj-$(CONFIG_MFD_MAX8907C)	+= max8907c.o
+obj-$(CONFIG_MFD_MAX8907C)	+= max8907c-irq.o
diff --git a/drivers/mfd/max8907c-irq.c b/drivers/mfd/max8907c-irq.c
new file mode 100644
index 000000000000..e9773c0fe00e
--- /dev/null
+++ b/drivers/mfd/max8907c-irq.c
@@ -0,0 +1,359 @@
+/*
+ * Battery driver for Maxim MAX8907C
+ *
+ * Copyright (c) 2011, NVIDIA Corporation.
+ * Based on driver/mfd/max8925-core.c, Copyright (C) 2009-2010 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/max8907c.h>
+
+struct max8907c_irq_data {
+	int	reg;
+	int	mask_reg;
+	int	enable;		/* enable or not */
+	int	offs;		/* bit offset in mask register */
+	bool	is_rtc;
+};
+
+static struct max8907c_irq_data max8907c_irqs[] = {
+	[MAX8907C_IRQ_VCHG_DC_OVP] = {
+		.reg		= MAX8907C_REG_CHG_IRQ1,
+		.mask_reg	= MAX8907C_REG_CHG_IRQ1_MASK,
+		.offs		= 1 << 0,
+	},
+	[MAX8907C_IRQ_VCHG_DC_F] = {
+		.reg		= MAX8907C_REG_CHG_IRQ1,
+		.mask_reg	= MAX8907C_REG_CHG_IRQ1_MASK,
+		.offs		= 1 << 1,
+	},
+	[MAX8907C_IRQ_VCHG_DC_R] = {
+		.reg		= MAX8907C_REG_CHG_IRQ1,
+		.mask_reg	= MAX8907C_REG_CHG_IRQ1_MASK,
+		.offs		= 1 << 2,
+	},
+	[MAX8907C_IRQ_VCHG_THM_OK_R] = {
+		.reg		= MAX8907C_REG_CHG_IRQ2,
+		.mask_reg	= MAX8907C_REG_CHG_IRQ2_MASK,
+		.offs		= 1 << 0,
+	},
+	[MAX8907C_IRQ_VCHG_THM_OK_F] = {
+		.reg		= MAX8907C_REG_CHG_IRQ2,
+		.mask_reg	= MAX8907C_REG_CHG_IRQ2_MASK,
+		.offs		= 1 << 1,
+	},
+	[MAX8907C_IRQ_VCHG_MBATTLOW_F] = {
+		.reg		= MAX8907C_REG_CHG_IRQ2,
+		.mask_reg	= MAX8907C_REG_CHG_IRQ2_MASK,
+		.offs		= 1 << 2,
+	},
+	[MAX8907C_IRQ_VCHG_MBATTLOW_R] = {
+		.reg		= MAX8907C_REG_CHG_IRQ2,
+		.mask_reg	= MAX8907C_REG_CHG_IRQ2_MASK,
+		.offs		= 1 << 3,
+	},
+	[MAX8907C_IRQ_VCHG_RST] = {
+		.reg		= MAX8907C_REG_CHG_IRQ2,
+		.mask_reg	= MAX8907C_REG_CHG_IRQ2_MASK,
+		.offs		= 1 << 4,
+	},
+	[MAX8907C_IRQ_VCHG_DONE] = {
+		.reg		= MAX8907C_REG_CHG_IRQ2,
+		.mask_reg	= MAX8907C_REG_CHG_IRQ2_MASK,
+		.offs		= 1 << 5,
+	},
+	[MAX8907C_IRQ_VCHG_TOPOFF] = {
+		.reg		= MAX8907C_REG_CHG_IRQ2,
+		.mask_reg	= MAX8907C_REG_CHG_IRQ2_MASK,
+		.offs		= 1 << 6,
+	},
+	[MAX8907C_IRQ_VCHG_TMR_FAULT] = {
+		.reg		= MAX8907C_REG_CHG_IRQ2,
+		.mask_reg	= MAX8907C_REG_CHG_IRQ2_MASK,
+		.offs		= 1 << 7,
+	},
+	[MAX8907C_IRQ_GPM_RSTIN] = {
+		.reg		= MAX8907C_REG_ON_OFF_IRQ1,
+		.mask_reg	= MAX8907C_REG_ON_OFF_IRQ1_MASK,
+		.offs		= 1 << 0,
+	},
+	[MAX8907C_IRQ_GPM_MPL] = {
+		.reg		= MAX8907C_REG_ON_OFF_IRQ1,
+		.mask_reg	= MAX8907C_REG_ON_OFF_IRQ1_MASK,
+		.offs		= 1 << 1,
+	},
+	[MAX8907C_IRQ_GPM_SW_3SEC] = {
+		.reg		= MAX8907C_REG_ON_OFF_IRQ1,
+		.mask_reg	= MAX8907C_REG_ON_OFF_IRQ1_MASK,
+		.offs		= 1 << 2,
+	},
+	[MAX8907C_IRQ_GPM_EXTON_F] = {
+		.reg		= MAX8907C_REG_ON_OFF_IRQ1,
+		.mask_reg	= MAX8907C_REG_ON_OFF_IRQ1_MASK,
+		.offs		= 1 << 3,
+	},
+	[MAX8907C_IRQ_GPM_EXTON_R] = {
+		.reg		= MAX8907C_REG_ON_OFF_IRQ1,
+		.mask_reg	= MAX8907C_REG_ON_OFF_IRQ1_MASK,
+		.offs		= 1 << 4,
+	},
+	[MAX8907C_IRQ_GPM_SW_1SEC] = {
+		.reg		= MAX8907C_REG_ON_OFF_IRQ1,
+		.mask_reg	= MAX8907C_REG_ON_OFF_IRQ1_MASK,
+		.offs		= 1 << 5,
+	},
+	[MAX8907C_IRQ_GPM_SW_F] = {
+		.reg		= MAX8907C_REG_ON_OFF_IRQ1,
+		.mask_reg	= MAX8907C_REG_ON_OFF_IRQ1_MASK,
+		.offs		= 1 << 6,
+	},
+	[MAX8907C_IRQ_GPM_SW_R] = {
+		.reg		= MAX8907C_REG_ON_OFF_IRQ1,
+		.mask_reg	= MAX8907C_REG_ON_OFF_IRQ1_MASK,
+		.offs		= 1 << 7,
+	},
+	[MAX8907C_IRQ_GPM_SYSCKEN_F] = {
+		.reg		= MAX8907C_REG_ON_OFF_IRQ2,
+		.mask_reg	= MAX8907C_REG_ON_OFF_IRQ2_MASK,
+		.offs		= 1 << 0,
+	},
+	[MAX8907C_IRQ_GPM_SYSCKEN_R] = {
+		.reg		= MAX8907C_REG_ON_OFF_IRQ2,
+		.mask_reg	= MAX8907C_REG_ON_OFF_IRQ2_MASK,
+		.offs		= 1 << 1,
+	},
+	[MAX8907C_IRQ_RTC_ALARM1] = {
+		.reg		= MAX8907C_REG_RTC_IRQ,
+		.mask_reg	= MAX8907C_REG_RTC_IRQ_MASK,
+		.offs		= 1 << 2,
+		.is_rtc		= true,
+	},
+	[MAX8907C_IRQ_RTC_ALARM0] = {
+		.reg		= MAX8907C_REG_RTC_IRQ,
+		.mask_reg	= MAX8907C_REG_RTC_IRQ_MASK,
+		.offs		= 1 << 3,
+		.is_rtc		= true,
+	},
+};
+
+static inline struct max8907c_irq_data *irq_to_max8907c(struct max8907c *chip,
+						      int irq)
+{
+	return &max8907c_irqs[irq - chip->irq_base];
+}
+
+static irqreturn_t max8907c_irq(int irq, void *data)
+{
+	struct max8907c *chip = data;
+	struct max8907c_irq_data *irq_data;
+	struct i2c_client *i2c;
+	int read_reg = -1, value = 0;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(max8907c_irqs); i++) {
+		irq_data = &max8907c_irqs[i];
+
+		if (irq_data->is_rtc)
+			i2c = chip->i2c_rtc;
+		else
+			i2c = chip->i2c_power;
+
+		if (read_reg != irq_data->reg) {
+			read_reg = irq_data->reg;
+			value = max8907c_reg_read(i2c, irq_data->reg);
+		}
+
+		if (value & irq_data->enable)
+			handle_nested_irq(chip->irq_base + i);
+	}
+	return IRQ_HANDLED;
+}
+
+static void max8907c_irq_lock(unsigned int irq)
+{
+	struct max8907c *chip = get_irq_chip_data(irq);
+
+	mutex_lock(&chip->irq_lock);
+}
+
+static void max8907c_irq_sync_unlock(unsigned int irq)
+{
+	struct max8907c *chip = get_irq_chip_data(irq);
+	struct max8907c_irq_data *irq_data;
+	static unsigned char cache_chg[2] = {0xff, 0xff};
+	static unsigned char cache_on[2] = {0xff, 0xff};
+	static unsigned char cache_rtc = 0xff;
+	unsigned char irq_chg[2], irq_on[2];
+	unsigned char irq_rtc;
+	int i;
+
+	/* Load cached value. In initial, all IRQs are masked */
+	irq_chg[0] = cache_chg[0];
+	irq_chg[1] = cache_chg[1];
+	irq_on[0] = cache_on[0];
+	irq_on[1] = cache_on[1];
+	irq_rtc = cache_rtc;
+	for (i = 0; i < ARRAY_SIZE(max8907c_irqs); i++) {
+		irq_data = &max8907c_irqs[i];
+		/* 1 -- disable, 0 -- enable */
+		switch (irq_data->mask_reg) {
+		case MAX8907C_REG_CHG_IRQ1_MASK:
+			irq_chg[0] &= ~irq_data->enable;
+			break;
+		case MAX8907C_REG_CHG_IRQ2_MASK:
+			irq_chg[1] &= ~irq_data->enable;
+			break;
+		case MAX8907C_REG_ON_OFF_IRQ1_MASK:
+			irq_on[0] &= ~irq_data->enable;
+			break;
+		case MAX8907C_REG_ON_OFF_IRQ2_MASK:
+			irq_on[1] &= ~irq_data->enable;
+			break;
+		case MAX8907C_REG_RTC_IRQ_MASK:
+			irq_rtc &= ~irq_data->enable;
+			break;
+		default:
+			dev_err(chip->dev, "wrong IRQ\n");
+			break;
+		}
+	}
+	/* update mask into registers */
+	if (cache_chg[0] != irq_chg[0]) {
+		cache_chg[0] = irq_chg[0];
+		max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ1_MASK,
+			irq_chg[0]);
+	}
+	if (cache_chg[1] != irq_chg[1]) {
+		cache_chg[1] = irq_chg[1];
+		max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ2_MASK,
+			irq_chg[1]);
+	}
+	if (cache_on[0] != irq_on[0]) {
+		cache_on[0] = irq_on[0];
+		max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ1_MASK,
+				irq_on[0]);
+	}
+	if (cache_on[1] != irq_on[1]) {
+		cache_on[1] = irq_on[1];
+		max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ2_MASK,
+				irq_on[1]);
+	}
+	if (cache_rtc != irq_rtc) {
+		cache_rtc = irq_rtc;
+		max8907c_reg_write(chip->i2c_rtc, MAX8907C_REG_RTC_IRQ_MASK,
+				   irq_rtc);
+	}
+
+	mutex_unlock(&chip->irq_lock);
+}
+
+static void max8907c_irq_enable(unsigned int irq)
+{
+	struct max8907c *chip = get_irq_chip_data(irq);
+	max8907c_irqs[irq - chip->irq_base].enable
+		= max8907c_irqs[irq - chip->irq_base].offs;
+}
+
+static void max8907c_irq_disable(unsigned int irq)
+{
+	struct max8907c *chip = get_irq_chip_data(irq);
+	max8907c_irqs[irq - chip->irq_base].enable = 0;
+}
+
+static struct irq_chip max8907c_irq_chip = {
+	.name		= "max8907c",
+	.bus_lock	= max8907c_irq_lock,
+	.bus_sync_unlock = max8907c_irq_sync_unlock,
+	.enable		= max8907c_irq_enable,
+	.disable	= max8907c_irq_disable,
+};
+
+int max8907c_irq_init(struct max8907c *chip, int irq, int irq_base)
+{
+	unsigned long flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
+	struct irq_desc *desc;
+	int i, ret;
+	int __irq;
+
+	if (!irq_base || !irq) {
+		dev_warn(chip->dev, "No interrupt support\n");
+		return -EINVAL;
+	}
+	/* clear all interrupts */
+	max8907c_reg_read(chip->i2c_power, MAX8907C_REG_CHG_IRQ1);
+	max8907c_reg_read(chip->i2c_power, MAX8907C_REG_CHG_IRQ2);
+	max8907c_reg_read(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ1);
+	max8907c_reg_read(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ2);
+	max8907c_reg_read(chip->i2c_rtc, MAX8907C_REG_RTC_IRQ);
+	/* mask all interrupts */
+	max8907c_reg_write(chip->i2c_rtc, MAX8907C_REG_ALARM0_CNTL, 0);
+	max8907c_reg_write(chip->i2c_rtc, MAX8907C_REG_ALARM1_CNTL, 0);
+	max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ1_MASK, 0xff);
+	max8907c_reg_write(chip->i2c_power, MAX8907C_REG_CHG_IRQ2_MASK, 0xff);
+	max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ1_MASK, 0xff);
+	max8907c_reg_write(chip->i2c_power, MAX8907C_REG_ON_OFF_IRQ2_MASK, 0xff);
+	max8907c_reg_write(chip->i2c_rtc, MAX8907C_REG_RTC_IRQ_MASK, 0xff);
+
+	mutex_init(&chip->irq_lock);
+	chip->core_irq = irq;
+	chip->irq_base = irq_base;
+	desc = irq_to_desc(chip->core_irq);
+
+	/* register with genirq */
+	for (i = 0; i < ARRAY_SIZE(max8907c_irqs); i++) {
+		__irq = i + chip->irq_base;
+		set_irq_chip_data(__irq, chip);
+		set_irq_chip_and_handler(__irq, &max8907c_irq_chip,
+					 handle_edge_irq);
+		set_irq_nested_thread(__irq, 1);
+#ifdef CONFIG_ARM
+		set_irq_flags(__irq, IRQF_VALID);
+#else
+		set_irq_noprobe(__irq);
+#endif
+	}
+
+	ret = request_threaded_irq(irq, NULL, max8907c_irq, flags,
+				   "max8907c", chip);
+	if (ret) {
+		dev_err(chip->dev, "Failed to request core IRQ: %d\n", ret);
+		chip->core_irq = 0;
+	}
+
+	return ret;
+}
+
+int max8907c_suspend(struct i2c_client *i2c, pm_message_t state)
+{
+	struct max8907c *max8907c = i2c_get_clientdata(i2c);
+
+	disable_irq(max8907c->core_irq);
+
+	return 0;
+}
+
+int max8907c_resume(struct i2c_client *i2c)
+{
+	struct max8907c *max8907c = i2c_get_clientdata(i2c);
+
+	enable_irq(max8907c->core_irq);
+
+	return 0;
+}
+
+void max8907c_irq_free(struct max8907c *chip)
+{
+	if (chip->core_irq)
+		free_irq(chip->core_irq, chip);
+}
+
diff --git a/drivers/mfd/max8907c.c b/drivers/mfd/max8907c.c
new file mode 100644
index 000000000000..8475c4be50e9
--- /dev/null
+++ b/drivers/mfd/max8907c.c
@@ -0,0 +1,286 @@
+/*
+ * max8907c.c - mfd driver for MAX8907c
+ *
+ * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/max8907c.h>
+
+static struct mfd_cell cells[] = {
+	{.name = "max8907-regulator",},
+	{.name = "max8907c-rtc",},
+};
+
+static int max8907c_i2c_read(struct i2c_client *i2c, u8 reg, u8 count, u8 *dest)
+{
+	struct i2c_msg xfer[2];
+	int ret = 0;
+
+	xfer[0].addr = i2c->addr;
+	xfer[0].flags = I2C_M_NOSTART;
+	xfer[0].len = 1;
+	xfer[0].buf = &reg;
+
+	xfer[1].addr = i2c->addr;
+	xfer[1].flags = I2C_M_RD;
+	xfer[1].len = count;
+	xfer[1].buf = dest;
+
+	ret = i2c_transfer(i2c->adapter, xfer, 2);
+	if (ret < 0)
+		return ret;
+	if (ret != 2)
+		return -EIO;
+
+	return 0;
+}
+
+static int max8907c_i2c_write(struct i2c_client *i2c, u8 reg, u8 count, const u8 *src)
+{
+	u8 msg[0x100 + 1];
+	int ret = 0;
+
+	msg[0] = reg;
+	memcpy(&msg[1], src, count);
+
+	ret = i2c_master_send(i2c, msg, count + 1);
+	if (ret < 0)
+		return ret;
+	if (ret != count + 1)
+		return -EIO;
+
+	return 0;
+}
+
+int max8907c_reg_read(struct i2c_client *i2c, u8 reg)
+{
+	int ret;
+	u8 val;
+
+	ret = max8907c_i2c_read(i2c, reg, 1, &val);
+
+	pr_debug("max8907c: reg read  reg=%x, val=%x\n",
+		 (unsigned int)reg, (unsigned int)val);
+
+	if (ret != 0)
+		pr_err("Failed to read max8907c I2C driver: %d\n", ret);
+	return val;
+}
+EXPORT_SYMBOL_GPL(max8907c_reg_read);
+
+int max8907c_reg_bulk_read(struct i2c_client *i2c, u8 reg, u8 count, u8 *val)
+{
+	int ret;
+
+	ret = max8907c_i2c_read(i2c, reg, count, val);
+
+	pr_debug("max8907c: reg read  reg=%x, val=%x\n",
+		 (unsigned int)reg, (unsigned int)*val);
+
+	if (ret != 0)
+		pr_err("Failed to read max8907c I2C driver: %d\n", ret);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(max8907c_reg_bulk_read);
+
+int max8907c_reg_write(struct i2c_client *i2c, u8 reg, u8 val)
+{
+	struct max8907c *max8907c = i2c_get_clientdata(i2c);
+	int ret;
+
+	pr_debug("max8907c: reg write  reg=%x, val=%x\n",
+		 (unsigned int)reg, (unsigned int)val);
+
+	mutex_lock(&max8907c->io_lock);
+	ret = max8907c_i2c_write(i2c, reg, 1, &val);
+	mutex_unlock(&max8907c->io_lock);
+
+	if (ret != 0)
+		pr_err("Failed to write max8907c I2C driver: %d\n", ret);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(max8907c_reg_write);
+
+int max8907c_reg_bulk_write(struct i2c_client *i2c, u8 reg, u8 count, u8 *val)
+{
+	struct max8907c *max8907c = i2c_get_clientdata(i2c);
+	int ret;
+
+	pr_debug("max8907c: reg write  reg=%x, val=%x\n",
+		 (unsigned int)reg, (unsigned int)*val);
+
+	mutex_lock(&max8907c->io_lock);
+	ret = max8907c_i2c_write(i2c, reg, count, val);
+	mutex_unlock(&max8907c->io_lock);
+
+	if (ret != 0)
+		pr_err("Failed to write max8907c I2C driver: %d\n", ret);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(max8907c_reg_bulk_write);
+
+int max8907c_set_bits(struct i2c_client *i2c, u8 reg, u8 mask, u8 val)
+{
+	struct max8907c *max8907c = i2c_get_clientdata(i2c);
+	u8 tmp;
+	int ret;
+
+	pr_debug("max8907c: reg write  reg=%02X, val=%02X, mask=%02X\n",
+		 (unsigned int)reg, (unsigned int)val, (unsigned int)mask);
+
+	mutex_lock(&max8907c->io_lock);
+	ret = max8907c_i2c_read(i2c, reg, 1, &tmp);
+	if (ret == 0) {
+		val = (tmp & ~mask) | (val & mask);
+		ret = max8907c_i2c_write(i2c, reg, 1, &val);
+	}
+	mutex_unlock(&max8907c->io_lock);
+
+	if (ret != 0)
+		pr_err("Failed to write max8907c I2C driver: %d\n", ret);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(max8907c_set_bits);
+
+static int max8907c_remove_subdev(struct device *dev, void *unused)
+{
+	platform_device_unregister(to_platform_device(dev));
+	return 0;
+}
+
+static int max8907c_remove_subdevs(struct max8907c *max8907c)
+{
+	return device_for_each_child(max8907c->dev, NULL,
+				     max8907c_remove_subdev);
+}
+
+static int max8097c_add_subdevs(struct max8907c *max8907c,
+				struct max8907c_platform_data *pdata)
+{
+	struct platform_device *pdev;
+	int ret;
+	int i;
+
+	for (i = 0; i < pdata->num_subdevs; i++) {
+		pdev = platform_device_alloc(pdata->subdevs[i]->name,
+					     pdata->subdevs[i]->id);
+
+		pdev->dev.parent = max8907c->dev;
+		pdev->dev.platform_data = pdata->subdevs[i]->dev.platform_data;
+
+		ret = platform_device_add(pdev);
+		if (ret)
+			goto error;
+	}
+	return 0;
+
+error:
+	max8907c_remove_subdevs(max8907c);
+	return ret;
+}
+
+static int max8907c_i2c_probe(struct i2c_client *i2c,
+			      const struct i2c_device_id *id)
+{
+	struct max8907c *max8907c;
+	struct max8907c_platform_data *pdata = i2c->dev.platform_data;
+	int ret;
+	int i;
+
+	max8907c = kzalloc(sizeof(struct max8907c), GFP_KERNEL);
+	if (max8907c == NULL)
+		return -ENOMEM;
+
+	max8907c->dev = &i2c->dev;
+	dev_set_drvdata(max8907c->dev, max8907c);
+
+	max8907c->i2c_power = i2c;
+	i2c_set_clientdata(i2c, max8907c);
+
+	max8907c->i2c_rtc = i2c_new_dummy(i2c->adapter, RTC_I2C_ADDR);
+	i2c_set_clientdata(max8907c->i2c_rtc, max8907c);
+
+	mutex_init(&max8907c->io_lock);
+
+	for (i = 0; i < ARRAY_SIZE(cells); i++)
+		cells[i].driver_data = max8907c;
+	ret = mfd_add_devices(max8907c->dev, -1, cells, ARRAY_SIZE(cells),
+			      NULL, 0);
+	if (ret != 0) {
+	  	i2c_unregister_device(max8907c->i2c_rtc);
+		kfree(max8907c);
+		pr_debug("max8907c: failed to add MFD devices   %X\n", ret);
+		return ret;
+	}
+
+	max8907c_irq_init(max8907c, i2c->irq, pdata->irq_base);
+
+	ret = max8097c_add_subdevs(max8907c, pdata);
+
+	return ret;
+}
+
+static int max8907c_i2c_remove(struct i2c_client *i2c)
+{
+	struct max8907c *max8907c = i2c_get_clientdata(i2c);
+
+	max8907c_remove_subdevs(max8907c);
+	i2c_unregister_device(max8907c->i2c_rtc);
+	mfd_remove_devices(max8907c->dev);
+	max8907c_irq_free(max8907c);
+	kfree(max8907c);
+
+	return 0;
+}
+
+static const struct i2c_device_id max8907c_i2c_id[] = {
+	{"max8907c", 0},
+	{}
+};
+
+MODULE_DEVICE_TABLE(i2c, max8907c_i2c_id);
+
+static struct i2c_driver max8907c_i2c_driver = {
+	.driver = {
+		   .name = "max8907c",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = max8907c_i2c_probe,
+	.remove = max8907c_i2c_remove,
+	.suspend = max8907c_suspend,
+	.resume = max8907c_resume,
+	.id_table = max8907c_i2c_id,
+};
+
+static int __init max8907c_i2c_init(void)
+{
+	int ret = -ENODEV;
+
+	ret = i2c_add_driver(&max8907c_i2c_driver);
+	if (ret != 0)
+		pr_err("Failed to register I2C driver: %d\n", ret);
+
+	return ret;
+}
+
+subsys_initcall(max8907c_i2c_init);
+
+static void __exit max8907c_i2c_exit(void)
+{
+	i2c_del_driver(&max8907c_i2c_driver);
+}
+
+module_exit(max8907c_i2c_exit);
+
+MODULE_DESCRIPTION("MAX8907C multi-function core driver");
+MODULE_AUTHOR("Gyungoh Yoo <jack.yoo@maxim-ic.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index ab667f296897..e2d8c80bc02e 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -27,6 +27,10 @@
 #include <linux/mfd/core.h>
 #include <linux/mfd/tps6586x.h>
 
+#define TPS6586X_SUPPLYENE  0x14
+#define EXITSLREQ_BIT       BIT(1) /* Exit sleep mode request */
+#define SLEEP_MODE_BIT      BIT(3) /* Sleep mode */
+
 /* GPIO control registers */
 #define TPS6586X_GPIOSET1	0x5d
 #define TPS6586X_GPIOSET2	0x5e
@@ -251,6 +255,28 @@ out:
 }
 EXPORT_SYMBOL_GPL(tps6586x_update);
 
+static struct i2c_client *tps6586x_i2c_client = NULL;
+int tps6586x_power_off(void)
+{
+	struct device *dev = NULL;
+	int ret = -EINVAL;
+
+	if (!tps6586x_i2c_client)
+		return ret;
+
+	dev = &tps6586x_i2c_client->dev;
+
+	ret = tps6586x_clr_bits(dev, TPS6586X_SUPPLYENE, EXITSLREQ_BIT);
+	if (ret)
+		return ret;
+
+	ret = tps6586x_set_bits(dev, TPS6586X_SUPPLYENE, SLEEP_MODE_BIT);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
 static int tps6586x_gpio_get(struct gpio_chip *gc, unsigned offset)
 {
 	struct tps6586x *tps6586x = container_of(gc, struct tps6586x, gpio);
@@ -274,13 +300,24 @@ static void tps6586x_gpio_set(struct gpio_chip *chip, unsigned offset,
 			 value << offset);
 }
 
+static int tps6586x_gpio_input(struct gpio_chip *gc, unsigned offset)
+{
+	/* FIXME: add handling of GPIOs as dedicated inputs */
+	return -ENOSYS;
+}
+
 static int tps6586x_gpio_output(struct gpio_chip *gc, unsigned offset,
 				int value)
 {
 	struct tps6586x *tps6586x = container_of(gc, struct tps6586x, gpio);
 	uint8_t val, mask;
+	int ret;
 
-	tps6586x_gpio_set(gc, offset, value);
+	val = value << offset;
+	mask = 0x1 << offset;
+	ret = tps6586x_update(tps6586x->dev, TPS6586X_GPIOSET2, val, mask);
+	if (ret)
+		return ret;
 
 	val = 0x1 << (offset * 2);
 	mask = 0x3 << (offset * 2);
@@ -302,7 +339,7 @@ static void tps6586x_gpio_init(struct tps6586x *tps6586x, int gpio_base)
 	tps6586x->gpio.ngpio		= 4;
 	tps6586x->gpio.can_sleep	= 1;
 
-	/* FIXME: add handling of GPIOs as dedicated inputs */
+	tps6586x->gpio.direction_input	= tps6586x_gpio_input;
 	tps6586x->gpio.direction_output	= tps6586x_gpio_output;
 	tps6586x->gpio.set		= tps6586x_gpio_set;
 	tps6586x->gpio.get		= tps6586x_gpio_get;
@@ -519,6 +556,8 @@ static int __devinit tps6586x_i2c_probe(struct i2c_client *client,
 
 	tps6586x_gpio_init(tps6586x, pdata->gpio_base);
 
+	tps6586x_i2c_client = client;
+
 	return 0;
 
 err_add_devs:
@@ -570,4 +609,3 @@ module_exit(tps6586x_exit);
 MODULE_DESCRIPTION("TPS6586X core driver");
 MODULE_AUTHOR("Mike Rapoport <mike@compulab.co.il>");
 MODULE_LICENSE("GPL");
-
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index c0377ca064ae..68794d916f78 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -444,9 +444,22 @@ config APANIC_PLABEL
 	 If your platform uses a different flash partition label for storing
  	 crashdumps, enter it here.
 
+config BCM4329_RFKILL
+	bool "Enable BCM4329 RFKILL driver"
+	default n
+	---help---
+	Adds BCM4329 RFKILL driver for Broadcom BCM4329 chipset
+
+config TEGRA_CRYPTO_DEV
+	bool "Device node to access tegra aes hardware"
+	---help---
+	Dev node /dev/tegra-crypto in order to get access to tegra aes
+	hardware from user space
+
 source "drivers/misc/c2port/Kconfig"
 source "drivers/misc/eeprom/Kconfig"
 source "drivers/misc/cb710/Kconfig"
 source "drivers/misc/iwmc3200top/Kconfig"
+source "drivers/misc/mpu3050/Kconfig"
 
 endif # MISC_DEVICES
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 8edb90117929..c06b6e507cff 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -12,8 +12,8 @@ obj-$(CONFIG_ATMEL_TCLIB)	+= atmel_tclib.o
 obj-$(CONFIG_BMP085)		+= bmp085.o
 obj-$(CONFIG_ICS932S401)	+= ics932s401.o
 obj-$(CONFIG_LKDTM)		+= lkdtm.o
-obj-$(CONFIG_TIFM_CORE)       	+= tifm_core.o
-obj-$(CONFIG_TIFM_7XX1)       	+= tifm_7xx1.o
+obj-$(CONFIG_TIFM_CORE)		+= tifm_core.o
+obj-$(CONFIG_TIFM_7XX1)		+= tifm_7xx1.o
 obj-$(CONFIG_PHANTOM)		+= phantom.o
 obj-$(CONFIG_SENSORS_BH1780)	+= bh1780gli.o
 obj-$(CONFIG_ANDROID_PMEM)	+= pmem.o
@@ -41,4 +41,7 @@ obj-$(CONFIG_ARM_CHARLCD)	+= arm-charlcd.o
 obj-$(CONFIG_WL127X_RFKILL)	+= wl127x-rfkill.o
 obj-$(CONFIG_APANIC)		+= apanic.o
 obj-$(CONFIG_SENSORS_AK8975)	+= akm8975.o
+obj-$(CONFIG_BCM4329_RFKILL)	+= bcm4329_rfkill.o
+obj-$(CONFIG_SENSORS_MPU3050)	+= mpu3050/
 obj-$(CONFIG_SENSORS_NCT1008)	+= nct1008.o
+obj-$(CONFIG_TEGRA_CRYPTO_DEV)	+= tegra-cryptodev.o
diff --git a/drivers/misc/akm8975.c b/drivers/misc/akm8975.c
index 830d2897afd6..0264bd6c8192 100644
--- a/drivers/misc/akm8975.c
+++ b/drivers/misc/akm8975.c
@@ -222,8 +222,8 @@ static int akm_aot_release(struct inode *inode, struct file *file)
 	return 0;
 }
 
-static int akm_aot_ioctl(struct inode *inode, struct file *file,
-	      unsigned int cmd, unsigned long arg)
+static long akm_aot_ioctl(struct file *file,
+			  unsigned int cmd, unsigned long arg)
 {
 	void __user *argp = (void __user *) arg;
 	short flag;
@@ -316,8 +316,8 @@ static int akmd_release(struct inode *inode, struct file *file)
 	return 0;
 }
 
-static int akmd_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
-		      unsigned long arg)
+static long akmd_ioctl(struct file *file, unsigned int cmd,
+		       unsigned long arg)
 {
 	void __user *argp = (void __user *) arg;
 
@@ -537,14 +537,14 @@ static const struct file_operations akmd_fops = {
 	.owner = THIS_MODULE,
 	.open = akmd_open,
 	.release = akmd_release,
-	.ioctl = akmd_ioctl,
+	.unlocked_ioctl = akmd_ioctl,
 };
 
 static const struct file_operations akm_aot_fops = {
 	.owner = THIS_MODULE,
 	.open = akm_aot_open,
 	.release = akm_aot_release,
-	.ioctl = akm_aot_ioctl,
+	.unlocked_ioctl = akm_aot_ioctl,
 };
 
 static struct miscdevice akm_aot_device = {
diff --git a/drivers/misc/bcm4329_rfkill.c b/drivers/misc/bcm4329_rfkill.c
new file mode 100644
index 000000000000..c266195a6db9
--- /dev/null
+++ b/drivers/misc/bcm4329_rfkill.c
@@ -0,0 +1,196 @@
+/*
+ * drivers/misc/bcm4329_rfkill.c
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+#include <linux/fs.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/rfkill.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/slab.h>
+
+struct bcm4329_rfkill_data {
+	int gpio_reset;
+	int gpio_shutdown;
+	int delay;
+	struct clk *bt_32k_clk;
+};
+
+static struct bcm4329_rfkill_data *bcm4329_rfkill;
+
+static int bcm4329_bt_rfkill_set_power(void *data, bool blocked)
+{
+	if (blocked) {
+		if (bcm4329_rfkill->gpio_shutdown)
+			gpio_direction_output(bcm4329_rfkill->gpio_shutdown, 0);
+		if (bcm4329_rfkill->gpio_reset)
+			gpio_direction_output(bcm4329_rfkill->gpio_reset, 0);
+		if (bcm4329_rfkill->bt_32k_clk)
+			clk_disable(bcm4329_rfkill->bt_32k_clk);
+	} else {
+		if (bcm4329_rfkill->bt_32k_clk)
+			clk_enable(bcm4329_rfkill->bt_32k_clk);
+		if (bcm4329_rfkill->gpio_shutdown)
+			gpio_direction_output(bcm4329_rfkill->gpio_shutdown, 1);
+		if (bcm4329_rfkill->gpio_reset)
+			gpio_direction_output(bcm4329_rfkill->gpio_reset, 1);
+	}
+
+	return 0;
+}
+
+static const struct rfkill_ops bcm4329_bt_rfkill_ops = {
+	.set_block = bcm4329_bt_rfkill_set_power,
+};
+
+static int bcm4329_rfkill_probe(struct platform_device *pdev)
+{
+	struct rfkill *bt_rfkill;
+	struct resource *res;
+	int ret;
+	bool enable = false;  /* off */
+	bool default_sw_block_state;
+
+	bcm4329_rfkill = kzalloc(sizeof(*bcm4329_rfkill), GFP_KERNEL);
+	if (!bcm4329_rfkill)
+		return -ENOMEM;
+
+	bcm4329_rfkill->bt_32k_clk = clk_get(&pdev->dev, "bcm4329_32k_clk");
+	if (IS_ERR(bcm4329_rfkill->bt_32k_clk)) {
+		pr_warn("%s: can't find bcm4329_32k_clk.\
+				assuming 32k clock to chip\n", __func__);
+		bcm4329_rfkill->bt_32k_clk = NULL;
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_IO,
+						"bcm4329_nreset_gpio");
+	if (res) {
+		bcm4329_rfkill->gpio_reset = res->start;
+		tegra_gpio_enable(bcm4329_rfkill->gpio_reset);
+		ret = gpio_request(bcm4329_rfkill->gpio_reset,
+						"bcm4329_nreset_gpio");
+	} else {
+		pr_warn("%s : can't find reset gpio.\n", __func__);
+		bcm4329_rfkill->gpio_reset = 0;
+	}
+
+	res = platform_get_resource_byname(pdev, IORESOURCE_IO,
+						"bcm4329_nshutdown_gpio");
+	if (res) {
+		bcm4329_rfkill->gpio_shutdown = res->start;
+		tegra_gpio_enable(bcm4329_rfkill->gpio_shutdown);
+		ret = gpio_request(bcm4329_rfkill->gpio_shutdown,
+						"bcm4329_nshutdown_gpio");
+	} else {
+		pr_warn("%s : can't find shutdown gpio.\n", __func__);
+		bcm4329_rfkill->gpio_shutdown = 0;
+	}
+
+	/* make sure at-least one of the GPIO is defined */
+	if (!bcm4329_rfkill->gpio_reset && !bcm4329_rfkill->gpio_shutdown)
+		goto free_bcm_res;
+
+	if (bcm4329_rfkill->bt_32k_clk && enable)
+		clk_enable(bcm4329_rfkill->bt_32k_clk);
+	if (bcm4329_rfkill->gpio_shutdown)
+		gpio_direction_output(bcm4329_rfkill->gpio_shutdown, enable);
+	if (bcm4329_rfkill->gpio_reset)
+		gpio_direction_output(bcm4329_rfkill->gpio_reset, enable);
+
+	bt_rfkill = rfkill_alloc("bcm4329 Bluetooth", &pdev->dev,
+				RFKILL_TYPE_BLUETOOTH, &bcm4329_bt_rfkill_ops,
+				NULL);
+
+	if (unlikely(!bt_rfkill))
+		goto free_bcm_res;
+
+	default_sw_block_state = !enable;
+	rfkill_set_states(bt_rfkill, default_sw_block_state, false);
+
+	ret = rfkill_register(bt_rfkill);
+
+	if (unlikely(ret)) {
+		rfkill_destroy(bt_rfkill);
+		goto free_bcm_res;
+	}
+
+	return 0;
+
+free_bcm_res:
+	if (bcm4329_rfkill->gpio_shutdown)
+		gpio_free(bcm4329_rfkill->gpio_shutdown);
+	if (bcm4329_rfkill->gpio_reset)
+		gpio_free(bcm4329_rfkill->gpio_reset);
+	if (bcm4329_rfkill->bt_32k_clk && enable)
+		clk_disable(bcm4329_rfkill->bt_32k_clk);
+	if (bcm4329_rfkill->bt_32k_clk)
+		clk_put(bcm4329_rfkill->bt_32k_clk);
+	kfree(bcm4329_rfkill);
+	return -ENODEV;
+}
+
+static int bcm4329_rfkill_remove(struct platform_device *pdev)
+{
+	struct rfkill *bt_rfkill = platform_get_drvdata(pdev);
+
+	if (bcm4329_rfkill->bt_32k_clk)
+		clk_put(bcm4329_rfkill->bt_32k_clk);
+	rfkill_unregister(bt_rfkill);
+	rfkill_destroy(bt_rfkill);
+	if (bcm4329_rfkill->gpio_shutdown)
+		gpio_free(bcm4329_rfkill->gpio_shutdown);
+	if (bcm4329_rfkill->gpio_reset)
+		gpio_free(bcm4329_rfkill->gpio_reset);
+	kfree(bcm4329_rfkill);
+
+	return 0;
+}
+
+static struct platform_driver bcm4329_rfkill_driver = {
+	.probe = bcm4329_rfkill_probe,
+	.remove = bcm4329_rfkill_remove,
+	.driver = {
+		   .name = "bcm4329_rfkill",
+		   .owner = THIS_MODULE,
+	},
+};
+
+static int __init bcm4329_rfkill_init(void)
+{
+	return platform_driver_register(&bcm4329_rfkill_driver);
+}
+
+static void __exit bcm4329_rfkill_exit(void)
+{
+	platform_driver_unregister(&bcm4329_rfkill_driver);
+}
+
+module_init(bcm4329_rfkill_init);
+module_exit(bcm4329_rfkill_exit);
+
+MODULE_DESCRIPTION("BCM4329 rfkill");
+MODULE_AUTHOR("NVIDIA");
+MODULE_LICENSE("GPL");
diff --git a/drivers/misc/mpu3050/Kconfig b/drivers/misc/mpu3050/Kconfig
new file mode 100644
index 000000000000..579ffd2665fb
--- /dev/null
+++ b/drivers/misc/mpu3050/Kconfig
@@ -0,0 +1,92 @@
+

+menu "Motion Sensors Support"

+

+choice

+    tristate "Motion Processing Unit"

+    depends on I2C

+    default MPU_NONE

+

+config MPU_NONE

+    bool "None"

+    help

+      This disables support for motion processing using the MPU family of 

+      motion processing units.

+

+config SENSORS_MPU3050

+    tristate "MPU3050"

+    depends on I2C

+    help

+      If you say yes here you get support for the MPU3050 Gyroscope driver

+      This driver can also be built as a module.  If so, the module

+      will be called mpu3050.

+

+config SENSORS_MPU6000

+    tristate "MPU6000"

+    depends on I2C

+    help

+      If you say yes here you get support for the MPU6000 Gyroscope driver

+      This driver can also be built as a module.  If so, the module

+      will be called mpu6000.

+

+endchoice

+

+choice

+    prompt "Accelerometer Type"

+    depends on SENSORS_MPU3050

+    default SENSORS_KXTF9_MPU

+

+config SENSORS_ACCELEROMETER_NONE

+    bool "NONE"

+    depends on SENSORS_MPU3050 || SENSORS_MPU6000

+    help

+      This disables accelerometer support for the MPU3050

+

+config SENSORS_KXTF9_MPU

+    bool "Kionix KXTF9"

+    depends on SENSORS_MPU3050

+    help

+      This enables support for the Kionix KXFT9 accelerometer

+

+endchoice

+

+choice

+    prompt "Compass Type"

+    depends on SENSORS_MPU6000 || SENSORS_MPU3050

+    default SENSORS_AK8975_MPU

+

+config SENSORS_COMPASS_NONE

+    bool "NONE"

+    depends on SENSORS_MPU6000 || SENSORS_MPU3050

+    help

+      This disables compass support for the MPU6000

+

+config SENSORS_AK8975_MPU

+    bool "AKM ak8975"

+    depends on SENSORS_MPU6000 || SENSORS_MPU3050

+    help

+      This enables support for the AKM ak8975 compass

+

+endchoice

+

+choice

+    prompt "Pressure Type"

+    depends on SENSORS_MPU6000 || SENSORS_MPU3050

+    default SENSORS_NONE

+

+config SENSORS_PRESSURE_NONE

+    bool "NONE"

+    depends on SENSORS_MPU6000 || SENSORS_MPU3050

+    help

+      This disables pressure sensor support for the MPU6000

+

+endchoice

+

+config SENSORS_MPU_DEBUG

+    bool "MPU debug"

+    depends on SENSORS_MPU3050 || SENSORS_MPU6000

+    help

+      If you say yes here you get extra debug messages from the MPU3050

+      and other slave sensors.

+

+endmenu

+

diff --git a/drivers/misc/mpu3050/Makefile b/drivers/misc/mpu3050/Makefile
new file mode 100644
index 000000000000..c03e473e375b
--- /dev/null
+++ b/drivers/misc/mpu3050/Makefile
@@ -0,0 +1,117 @@
+

+# Kernel makefile for motions sensors

+#

+# 

+

+# MPU

+obj-$(CONFIG_SENSORS_MPU3050)	+= mpu3050.o

+mpu3050-objs += mpuirq.o \

+	slaveirq.o \

+	mpu-dev.o \

+	mpu-i2c.o \

+	mlsl-kernel.o \

+	mlos-kernel.o \

+	$(MLLITE_DIR)mldl_cfg.o

+

+#

+# Accel options

+#

+ifdef CONFIG_SENSORS_ADXL346

+mpu3050-objs += $(MLLITE_DIR)accel/adxl346.o

+endif

+

+ifdef CONFIG_SENSORS_BMA150

+mpu3050-objs += $(MLLITE_DIR)accel/bma150.o

+endif

+

+ifdef CONFIG_SENSORS_BMA222

+mpu3050-objs += $(MLLITE_DIR)accel/bma222.o

+endif

+

+ifdef CONFIG_SENSORS_KXSD9

+mpu3050-objs += $(MLLITE_DIR)accel/kxsd9.o

+endif

+

+ifdef CONFIG_SENSORS_KXTF9_MPU

+mpu3050-objs += $(MLLITE_DIR)accel/kxtf9.o

+endif

+

+ifdef CONFIG_SENSORS_LIS331DLH

+mpu3050-objs += $(MLLITE_DIR)accel/lis331.o

+endif

+

+ifdef CONFIG_SENSORS_LSM303DLHA

+mpu3050-objs += $(MLLITE_DIR)accel/lsm303a.o

+endif

+

+ifdef CONFIG_SENSORS_MMA8450

+mpu3050-objs += $(MLLITE_DIR)accel/mma8450.o

+endif

+

+ifdef CONFIG_SENSORS_MMA8451

+mpu3050-objs += $(MLLITE_DIR)accel/mma8451.o

+endif

+

+#

+# Compass options

+#

+ifdef CONFIG_SENSORS_AK8975_MPU

+mpu3050-objs += $(MLLITE_DIR)compass/ak8975.o

+endif

+

+ifdef CONFIG_SENSORS_AMI30X

+mpu3050-objs += $(MLLITE_DIR)compass/ami30x.o

+endif

+

+ifdef CONFIG_SENSORS_HMC5883

+mpu3050-objs += $(MLLITE_DIR)compass/hmc5883.o

+endif

+

+ifdef CONFIG_SENSORS_LSM303DLHM

+mpu3050-objs += $(MLLITE_DIR)compass/lsm303m.o

+endif

+

+ifdef CONFIG_SENSORS_MMC314X

+mpu3050-objs += $(MLLITE_DIR)compass/mmc314x.o

+endif

+

+ifdef CONFIG_SENSORS_YAS529

+mpu3050-objs += $(MLLITE_DIR)compass/yas529-kernel.o

+endif

+

+ifdef CONFIG_SENSORS_HSCDTD002B

+mpu3050-objs += $(MLLITE_DIR)compass/hscdtd002b.o

+endif

+

+#

+# Pressure options

+#

+ifdef CONFIG_SENSORS_BMA085

+mpu3050-objs += $(MLLITE_DIR)pressure/bma085.o

+endif

+

+EXTRA_CFLAGS += -I$(M)/$(MLLITE_DIR) \

+                -I$(M)/../../include \

+		-Idrivers/misc/mpu3050 \

+                -Iinclude/linux

+

+ifdef CONFIG_SENSORS_MPU_DEBUG

+EXTRA_CFLAGS += -DDEBUG

+endif

+

+obj-$(CONFIG_SENSORS_MPU6000)= mpu6000.o

+mpu6000-objs += mpuirq.o \

+	mpu-dev.o \

+	mpu-i2c.o \

+	mlsl-kernel.o \

+	mlos-kernel.o \

+	$(MLLITE_DIR)mldl_cfg.o \

+	$(MLLITE_DIR)accel/mantis.o

+

+ifdef CONFIG_SENSORS_AK8975_MPU

+mpu6000-objs += $(MLLITE_DIR)compass/ak8975.o

+endif

+

+ifdef CONFIG_SENSORS_MPU6000

+EXTRA_CFLAGS += -DM_HW

+endif

diff --git a/drivers/misc/mpu3050/accel/kxtf9.c b/drivers/misc/mpu3050/accel/kxtf9.c
new file mode 100644
index 000000000000..11a9491dd7f1
--- /dev/null
+++ b/drivers/misc/mpu3050/accel/kxtf9.c
@@ -0,0 +1,157 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+/**
+ *  @defgroup   ACCELDL (Motion Library - Accelerometer Driver Layer)
+ *  @brief      Provides the interface to setup and handle an accelerometers
+ *              connected to the secondary I2C interface of the gyroscope.
+ *
+ *  @{
+ *      @file   kxtf9.c
+ *      @brief  Accelerometer setup and handling methods.
+*/
+
+/* ------------------ */
+/* - Include Files. - */
+/* ------------------ */
+
+#ifdef __KERNEL__
+#include <linux/module.h>
+#endif
+
+#include "mpu.h"
+#include "mlsl.h"
+#include "mlos.h"
+
+#include <log.h>
+#undef MPL_LOG_TAG
+#define MPL_LOG_TAG "MPL-acc"
+
+/* --------------------- */
+/* -    Variables.     - */
+/* --------------------- */
+
+/*****************************************
+    Accelerometer Initialization Functions
+*****************************************/
+
+static int kxtf9_suspend(void *mlsl_handle,
+			 struct ext_slave_descr *slave,
+			 struct ext_slave_platform_data *pdata)
+{
+	int result;
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->address, 0x1b, 0);
+	ERROR_CHECK(result);
+	return result;
+}
+
+/* full scale setting - register and mask */
+#define ACCEL_KIONIX_CTRL_REG      (0x1b)
+#define ACCEL_KIONIX_CTRL_MASK     (0x18)
+
+static int kxtf9_resume(void *mlsl_handle,
+			struct ext_slave_descr *slave,
+			struct ext_slave_platform_data *pdata)
+{
+	int result = ML_SUCCESS;
+	unsigned char reg;
+
+	/* RAM reset */
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->address, 0x1d, 0xcd);
+	ERROR_CHECK(result);
+	MLOSSleep(10);
+	/* Wake up */
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->address, 0x1b, 0x42);
+	ERROR_CHECK(result);
+	/* INT_CTRL_REG1: */
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->address, 0x1e, 0x14);
+	ERROR_CHECK(result);
+	/* WUF_THRESH: */
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->address, 0x5a, 0x00);
+	ERROR_CHECK(result);
+	/* DATA_CTRL_REG */
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->address, 0x21, 0x04);
+	ERROR_CHECK(result);
+	/* WUF_TIMER */
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->address, 0x29, 0x02);
+	ERROR_CHECK(result);
+
+	/* Full Scale */
+	reg = 0xc2;
+	reg &= ~ACCEL_KIONIX_CTRL_MASK;
+	reg |= 0x00;
+	if (slave->range.mantissa == 4)
+		reg |= 0x08;
+	else if (slave->range.mantissa == 8)
+		reg |= 0x10;
+	else {
+		slave->range.mantissa = 2;
+		reg |= 0x00;
+	}
+	slave->range.fraction = 0;
+
+	/* Normal operation  */
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->address, 0x1b, reg);
+	ERROR_CHECK(result);
+	MLOSSleep(50);
+
+	return ML_SUCCESS;
+}
+
+static int kxtf9_read(void *mlsl_handle,
+		      struct ext_slave_descr *slave,
+		      struct ext_slave_platform_data *pdata,
+		      unsigned char *data)
+{
+	return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+}
+
+static struct ext_slave_descr kxtf9_descr = {
+	/*.init             = */ NULL,
+	/*.exit             = */ NULL,
+	/*.suspend          = */ kxtf9_suspend,
+	/*.resume           = */ kxtf9_resume,
+	/*.read             = */ kxtf9_read,
+	/*.config           = */ NULL,
+	/*.name             = */ "kxtf9",
+	/*.type             = */ EXT_SLAVE_TYPE_ACCELEROMETER,
+	/*.id               = */ ACCEL_ID_KXTF9,
+	/*.reg              = */ 0x06,
+	/*.len              = */ 6,
+	/*.endian           = */ EXT_SLAVE_LITTLE_ENDIAN,
+	/*.range            = */ {2, 0},
+};
+
+struct ext_slave_descr *kxtf9_get_slave_descr(void)
+{
+	return &kxtf9_descr;
+}
+EXPORT_SYMBOL(kxtf9_get_slave_descr);
+
+/**
+ *  @}
+**/
diff --git a/drivers/misc/mpu3050/compass/ak8975.c b/drivers/misc/mpu3050/compass/ak8975.c
new file mode 100644
index 000000000000..18606e240f1c
--- /dev/null
+++ b/drivers/misc/mpu3050/compass/ak8975.c
@@ -0,0 +1,151 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+/**
+ *  @defgroup   COMPASSDL (Motion Library - Accelerometer Driver Layer)
+ *  @brief      Provides the interface to setup and handle an accelerometers
+ *              connected to the secondary I2C interface of the gyroscope.
+ *
+ *  @{
+ *      @file   AK8975.c
+ *      @brief  Magnetometer setup and handling methods for AKM 8975 compass.
+**/
+
+/* ------------------ */
+/* - Include Files. - */
+/* ------------------ */
+
+#ifdef __KERNEL__
+#include <linux/module.h>
+#endif
+
+#include "mpu.h"
+#include "mlsl.h"
+#include "mlos.h"
+
+#include <log.h>
+#undef MPL_LOG_TAG
+#define MPL_LOG_TAG "MPL-compass"
+
+
+#define AK8975_REG_ST1  (0x02)
+#define AK8975_REG_HXL  (0x03)
+#define AK8975_REG_ST2  (0x09)
+
+#define AK8975_REG_CNTL (0x0A)
+
+#define AK8975_CNTL_MODE_POWER_DOWN         (0x00)
+#define AK8975_CNTL_MODE_SINGLE_MEASUREMENT (0x01)
+
+int ak8975_suspend(void *mlsl_handle,
+		   struct ext_slave_descr *slave,
+		   struct ext_slave_platform_data *pdata)
+{
+	int result = ML_SUCCESS;
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->address,
+				  AK8975_REG_CNTL,
+				  AK8975_CNTL_MODE_POWER_DOWN);
+	MLOSSleep(1);		/* wait at least 100us */
+	ERROR_CHECK(result);
+	return result;
+}
+
+int ak8975_resume(void *mlsl_handle,
+		  struct ext_slave_descr *slave,
+		  struct ext_slave_platform_data *pdata)
+{
+	int result = ML_SUCCESS;
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->address,
+				  AK8975_REG_CNTL,
+				  AK8975_CNTL_MODE_SINGLE_MEASUREMENT);
+	ERROR_CHECK(result);
+	return result;
+}
+
+int ak8975_read(void *mlsl_handle,
+		struct ext_slave_descr *slave,
+		struct ext_slave_platform_data *pdata, unsigned char *data)
+{
+	unsigned char stat;
+	unsigned char stat2;
+	int result = ML_SUCCESS;
+
+	result =
+	    MLSLSerialRead(mlsl_handle, pdata->address, AK8975_REG_ST1, 1,
+			   &stat);
+	ERROR_CHECK(result);
+	if (stat & 0x01) {
+		result =
+		    MLSLSerialRead(mlsl_handle, pdata->address,
+				   AK8975_REG_HXL, 6,
+				   (unsigned char *) data);
+		ERROR_CHECK(result);
+		result =
+		    MLSLSerialRead(mlsl_handle, pdata->address,
+				   AK8975_REG_ST2, 1, &stat2);
+		ERROR_CHECK(result);
+		if (stat2 & 0x04)	/* data error */
+			return ML_ERROR_COMPASS_DATA_NOT_READY;
+		if (stat2 & 0x08)
+			return ML_ERROR_COMPASS_DATA_OVERFLOW;
+
+		result =
+		    MLSLSerialWriteSingle(mlsl_handle, pdata->address,
+					  AK8975_REG_CNTL,
+					  AK8975_CNTL_MODE_SINGLE_MEASUREMENT);
+		ERROR_CHECK(result);
+		return ML_SUCCESS;
+	} else if (stat & 0x02) {
+		result =
+		    MLSLSerialRead(mlsl_handle, pdata->address,
+				   AK8975_REG_ST2, 1, &stat2);
+		ERROR_CHECK(result);
+		return ML_ERROR_COMPASS_DATA_OVERFLOW;
+	} else {
+		return ML_ERROR_COMPASS_DATA_NOT_READY;
+	}
+}
+
+struct ext_slave_descr ak8975_descr = {
+	/*.init             = */ NULL,
+	/*.exit             = */ NULL,
+	/*.suspend          = */ ak8975_suspend,
+	/*.resume           = */ ak8975_resume,
+	/*.read             = */ ak8975_read,
+	/*.config           = */ NULL,
+	/*.name             = */ "ak8975",
+	/*.type             = */ EXT_SLAVE_TYPE_COMPASS,
+	/*.id               = */ COMPASS_ID_AKM,
+	/*.reg              = */ 0x01,
+	/*.len              = */ 9,
+	/*.endian           = */ EXT_SLAVE_LITTLE_ENDIAN,
+	/*.range            = */ {9830, 4000}
+};
+
+struct ext_slave_descr *ak8975_get_slave_descr(void)
+{
+	return &ak8975_descr;
+}
+EXPORT_SYMBOL(ak8975_get_slave_descr);
+
+/**
+ *  @}
+**/
diff --git a/drivers/misc/mpu3050/log.h b/drivers/misc/mpu3050/log.h
new file mode 100644
index 000000000000..ceee28526265
--- /dev/null
+++ b/drivers/misc/mpu3050/log.h
@@ -0,0 +1,286 @@
+/*
+ * Copyright (C) 2010 InvenSense Inc
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/*
+ * C/C++ logging functions.  See the logging documentation for API details.
+ *
+ * We'd like these to be available from C code (in case we import some from
+ * somewhere), so this has a C interface.
+ *
+ * The output will be correct when the log file is shared between multiple
+ * threads and/or multiple processes so long as the operating system
+ * supports O_APPEND.  These calls have mutex-protected data structures
+ * and so are NOT reentrant.  Do not use MPL_LOG in a signal handler.
+ */
+#ifndef _LIBS_CUTILS_MPL_LOG_H
+#define _LIBS_CUTILS_MPL_LOG_H
+
+#include <stdarg.h>
+
+#ifdef ANDROID
+#include <utils/Log.h>		/* For the LOG macro */
+#endif
+
+#ifdef __KERNEL__
+#include <linux/kernel.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* --------------------------------------------------------------------- */
+
+/*
+ * Normally we strip MPL_LOGV (VERBOSE messages) from release builds.
+ * You can modify this (for example with "#define MPL_LOG_NDEBUG 0"
+ * at the top of your source file) to change that behavior.
+ */
+#ifndef MPL_LOG_NDEBUG
+#ifdef NDEBUG
+#define MPL_LOG_NDEBUG 1
+#else
+#define MPL_LOG_NDEBUG 0
+#endif
+#endif
+
+#ifdef __KERNEL__
+#define MPL_LOG_UNKNOWN MPL_LOG_VERBOSE
+#define MPL_LOG_DEFAULT KERN_DEFAULT
+#define MPL_LOG_VERBOSE KERN_CONT
+#define MPL_LOG_DEBUG   KERN_NOTICE
+#define MPL_LOG_INFO    KERN_INFO
+#define MPL_LOG_WARN    KERN_WARNING
+#define MPL_LOG_ERROR   KERN_ERR
+#define MPL_LOG_SILENT  MPL_LOG_VERBOSE
+
+#else
+	/* Based off the log priorities in android
+	   /system/core/include/android/log.h */
+#define MPL_LOG_UNKNOWN (0)
+#define MPL_LOG_DEFAULT (1)
+#define MPL_LOG_VERBOSE (2)
+#define MPL_LOG_DEBUG (3)
+#define MPL_LOG_INFO (4)
+#define MPL_LOG_WARN (5)
+#define MPL_LOG_ERROR (6)
+#define MPL_LOG_SILENT (8)
+#endif
+
+
+/*
+ * This is the local tag used for the following simplified
+ * logging macros.  You can change this preprocessor definition
+ * before using the other macros to change the tag.
+ */
+#ifndef MPL_LOG_TAG
+#ifdef __KERNEL__
+#define MPL_LOG_TAG
+#else
+#define MPL_LOG_TAG NULL
+#endif
+#endif
+
+/* --------------------------------------------------------------------- */
+
+/*
+ * Simplified macro to send a verbose log message using the current MPL_LOG_TAG.
+ */
+#ifndef MPL_LOGV
+#if MPL_LOG_NDEBUG
+#define MPL_LOGV(...) ((void)0)
+#else
+#define MPL_LOGV(...) ((void)MPL_LOG(LOG_VERBOSE, MPL_LOG_TAG, __VA_ARGS__))
+#endif
+#endif
+
+#ifndef CONDITION
+#define CONDITION(cond)     ((cond) != 0)
+#endif
+
+#ifndef MPL_LOGV_IF
+#if MPL_LOG_NDEBUG
+#define MPL_LOGV_IF(cond, ...)   ((void)0)
+#else
+#define MPL_LOGV_IF(cond, ...) \
+	((CONDITION(cond))						\
+		? ((void)MPL_LOG(LOG_VERBOSE, MPL_LOG_TAG, __VA_ARGS__)) \
+		: (void)0)
+#endif
+#endif
+
+/*
+ * Simplified macro to send a debug log message using the current MPL_LOG_TAG.
+ */
+#ifndef MPL_LOGD
+#define MPL_LOGD(...) ((void)MPL_LOG(LOG_DEBUG, MPL_LOG_TAG, __VA_ARGS__))
+#endif
+
+#ifndef MPL_LOGD_IF
+#define MPL_LOGD_IF(cond, ...) \
+	((CONDITION(cond))					       \
+		? ((void)MPL_LOG(LOG_DEBUG, MPL_LOG_TAG, __VA_ARGS__)) \
+		: (void)0)
+#endif
+
+/*
+ * Simplified macro to send an info log message using the current MPL_LOG_TAG.
+ */
+#ifndef MPL_LOGI
+#define MPL_LOGI(...) ((void)MPL_LOG(LOG_INFO, MPL_LOG_TAG, __VA_ARGS__))
+#endif
+
+#ifndef MPL_LOGI_IF
+#define MPL_LOGI_IF(cond, ...) \
+	((CONDITION(cond))                                              \
+		? ((void)MPL_LOG(LOG_INFO, MPL_LOG_TAG, __VA_ARGS__))   \
+		: (void)0)
+#endif
+
+/*
+ * Simplified macro to send a warning log message using the current MPL_LOG_TAG.
+ */
+#ifndef MPL_LOGW
+#define MPL_LOGW(...) ((void)MPL_LOG(LOG_WARN, MPL_LOG_TAG, __VA_ARGS__))
+#endif
+
+#ifndef MPL_LOGW_IF
+#define MPL_LOGW_IF(cond, ...) \
+	((CONDITION(cond))					       \
+		? ((void)MPL_LOG(LOG_WARN, MPL_LOG_TAG, __VA_ARGS__))  \
+		: (void)0)
+#endif
+
+/*
+ * Simplified macro to send an error log message using the current MPL_LOG_TAG.
+ */
+#ifndef MPL_LOGE
+#define MPL_LOGE(...) ((void)MPL_LOG(LOG_ERROR, MPL_LOG_TAG, __VA_ARGS__))
+#endif
+
+#ifndef MPL_LOGE_IF
+#define MPL_LOGE_IF(cond, ...) \
+	((CONDITION(cond))					       \
+		? ((void)MPL_LOG(LOG_ERROR, MPL_LOG_TAG, __VA_ARGS__)) \
+		: (void)0)
+#endif
+
+/* --------------------------------------------------------------------- */
+
+/*
+ * Log a fatal error.  If the given condition fails, this stops program
+ * execution like a normal assertion, but also generating the given message.
+ * It is NOT stripped from release builds.  Note that the condition test
+ * is -inverted- from the normal assert() semantics.
+ */
+#define MPL_LOG_ALWAYS_FATAL_IF(cond, ...) \
+	((CONDITION(cond))					   \
+		? ((void)android_printAssert(#cond, MPL_LOG_TAG, __VA_ARGS__)) \
+		: (void)0)
+
+#define MPL_LOG_ALWAYS_FATAL(...) \
+	(((void)android_printAssert(NULL, MPL_LOG_TAG, __VA_ARGS__)))
+
+/*
+ * Versions of MPL_LOG_ALWAYS_FATAL_IF and MPL_LOG_ALWAYS_FATAL that
+ * are stripped out of release builds.
+ */
+#if MPL_LOG_NDEBUG
+
+#define MPL_LOG_FATAL_IF(cond, ...) ((void)0)
+#define MPL_LOG_FATAL(...)          ((void)0)
+
+#else
+
+#define MPL_LOG_FATAL_IF(cond, ...) MPL_LOG_ALWAYS_FATAL_IF(cond, __VA_ARGS__)
+#define MPL_LOG_FATAL(...)          MPL_LOG_ALWAYS_FATAL(__VA_ARGS__)
+
+#endif
+
+/*
+ * Assertion that generates a log message when the assertion fails.
+ * Stripped out of release builds.  Uses the current MPL_LOG_TAG.
+ */
+#define MPL_LOG_ASSERT(cond, ...) MPL_LOG_FATAL_IF(!(cond), __VA_ARGS__)
+
+/* --------------------------------------------------------------------- */
+
+/*
+ * Basic log message macro.
+ *
+ * Example:
+ *  MPL_LOG(MPL_LOG_WARN, NULL, "Failed with error %d", errno);
+ *
+ * The second argument may be NULL or "" to indicate the "global" tag.
+ */
+#ifndef MPL_LOG
+#define MPL_LOG(priority, tag, ...) \
+    MPL_LOG_PRI(priority, tag, __VA_ARGS__)
+#endif
+
+/*
+ * Log macro that allows you to specify a number for the priority.
+ */
+#ifndef MPL_LOG_PRI
+#ifdef ANDROID
+#define MPL_LOG_PRI(priority, tag, ...) \
+	LOG(priority, tag, __VA_ARGS__)
+#elif defined __KERNEL__
+#define MPL_LOG_PRI(priority, tag, ...) \
+	printk(MPL_##priority tag __VA_ARGS__)
+#else
+#define MPL_LOG_PRI(priority, tag, ...) \
+	_MLPrintLog(MPL_##priority, tag, __VA_ARGS__)
+#endif
+#endif
+
+/*
+ * Log macro that allows you to pass in a varargs ("args" is a va_list).
+ */
+#ifndef MPL_LOG_PRI_VA
+#ifdef ANDROID
+#define MPL_LOG_PRI_VA(priority, tag, fmt, args) \
+    android_vprintLog(priority, NULL, tag, fmt, args)
+#elif defined __KERNEL__
+#define MPL_LOG_PRI_VA(priority, tag, fmt, args) \
+    vprintk(MPL_##priority tag fmt, args)
+#else
+#define MPL_LOG_PRI_VA(priority, tag, fmt, args) \
+    _MLPrintVaLog(priority, NULL, tag, fmt, args)
+#endif
+#endif
+
+/* --------------------------------------------------------------------- */
+
+/*
+ * ===========================================================================
+ *
+ * The stuff in the rest of this file should not be used directly.
+ */
+
+#ifndef ANDROID
+	int _MLPrintLog(int priority, const char *tag, const char *fmt,
+			...);
+	int _MLPrintVaLog(int priority, const char *tag, const char *fmt,
+			  va_list args);
+/* Final implementation of actual writing to a character device */
+	int _MLWriteLog(const char *buf, int buflen);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* _LIBS_CUTILS_MPL_LOG_H */
diff --git a/drivers/misc/mpu3050/mldl_cfg.c b/drivers/misc/mpu3050/mldl_cfg.c
new file mode 100644
index 000000000000..668a4cf03ccc
--- /dev/null
+++ b/drivers/misc/mpu3050/mldl_cfg.c
@@ -0,0 +1,1535 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+/**
+ *  @addtogroup MLDL
+ *
+ *  @{
+ *      @file   mldl_cfg.c
+ *      @brief  The Motion Library Driver Layer.
+ */
+
+/* ------------------ */
+/* - Include Files. - */
+/* ------------------ */
+
+#include <stddef.h>
+
+#include "mldl_cfg.h"
+#include "mpu.h"
+
+#include "mlsl.h"
+#include "mlos.h"
+
+#include "log.h"
+#undef MPL_LOG_TAG
+#define MPL_LOG_TAG "mldl_cfg:"
+
+/* --------------------- */
+/* -    Variables.     - */
+/* --------------------- */
+#ifdef M_HW
+#define SLEEP   0
+#define WAKE_UP 7
+#define RESET   1
+#define STANDBY 1
+#else
+/* licteral significance of all parameters used in MLDLPowerMgmtMPU */
+#define SLEEP   1
+#define WAKE_UP 0
+#define RESET   1
+#define STANDBY 1
+#endif
+
+/* --------------------- */
+/* -    Prototypes.    - */
+/* --------------------- */
+#ifdef M_HW
+static tMLError MLDLPowerMgmtMantis(struct mldl_cfg *pdata,
+				    void *mlsl_handle,
+				    unsigned char reset,
+				    unsigned char powerselection);
+static tMLError MLDLStandByGyros(struct mldl_cfg *pdata,
+				 void *mlsl_handle,
+				 unsigned char disable_gx,
+				 unsigned char disable_gy,
+				 unsigned char disable_gz);
+#else
+static int MLDLPowerMgmtMPU(struct mldl_cfg *pdata,
+			    void *mlsl_handle,
+			    unsigned char reset,
+			    unsigned char sleep,
+			    unsigned char disable_gx,
+			    unsigned char disable_gy,
+			    unsigned char disable_gz);
+#endif
+
+/* ---------------------- */
+/* -  Static Functions. - */
+/* ---------------------- */
+
+/**
+ *  @internal
+ * @brief   MLDLCfgDMP configures the Digital Motion Processor internal to
+ *          the MPU. The DMP can be enabled or disabled and the start address
+ *          can be set.
+ *
+ * @param   enableRun   Enables the DMP processing if set to TRUE.
+ * @param   enableFIFO  Enables DMP output to the FIFO if set to TRUE.
+ *
+ * @return  Zero if the command is successful, an error code otherwise.
+ */
+static int MLDLCtrlDmp(struct mldl_cfg *pdata, void *mlsl_handle,
+		       bool enableRun, bool enableFIFO)
+{
+	unsigned char b;
+
+	MLSLSerialRead(mlsl_handle, pdata->addr, MPUREG_USER_CTRL, 1, &b);
+	if (enableRun)
+		b |= BIT_DMP_EN;
+	else
+		b &= ~BIT_DMP_EN;
+
+	if (enableFIFO)
+		b |= BIT_FIFO_EN;
+
+	b |= BIT_DMP_RST;
+
+	MLSLSerialWriteSingle(mlsl_handle, pdata->addr, MPUREG_USER_CTRL,
+			      b);
+
+	return ML_SUCCESS;
+}
+
+/**
+ * @brief Starts the DMP running
+ *
+ * @return ML_SUCCESS or non-zero error code
+ */
+static int MLDLDmpStart(struct mldl_cfg *pdata, void *mlsl_handle)
+{
+	unsigned char fifoBuf[2];
+	unsigned char tries = 0;
+	unsigned char userCtrlReg;
+	int result;
+	unsigned short len = !0;
+
+	result = MLSLSerialRead(mlsl_handle, pdata->addr,
+				MPUREG_USER_CTRL, 1, &userCtrlReg);
+
+	while (len != 0 && tries < 6) {
+		result = MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+					       MPUREG_USER_CTRL,
+					       ((userCtrlReg & (~BIT_FIFO_EN))
+							     |   BIT_FIFO_RST));
+		MLSLSerialRead(mlsl_handle, pdata->addr,
+			       MPUREG_FIFO_COUNTH, 2, fifoBuf);
+		len = (((unsigned short) fifoBuf[0] << 8)
+		       | (unsigned short) fifoBuf[1]);
+		tries++;
+	}
+
+	MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+			      MPUREG_USER_CTRL, userCtrlReg);
+
+	return MLDLCtrlDmp(pdata, mlsl_handle,
+			   pdata->dmp_enable, pdata->fifo_enable);
+}
+
+/**
+ *  @brief  enables/disables the I2C bypass to an external device
+ *          connected to MPU's secondary I2C bus.
+ *  @param  enable
+ *              Non-zero to enable pass through.
+ *  @return ML_SUCCESS if successful, a non-zero error code otherwise.
+ */
+static int MLDLSetI2CBypass(struct mldl_cfg *mldl_cfg,
+			    void *mlsl_handle,
+			    unsigned char enable)
+{
+	unsigned char b;
+	int result;
+
+#ifdef ML_USE_DMP_SIM
+	/*  done this way so that pc demo  */
+	/*  w/arm board works with universal api  */
+	if (!MLGetGyroPresent())
+		return ML_SUCCESS;
+#endif
+
+	/*---- get current 'USER_CTRL' into b ----*/
+	result = MLSLSerialRead(mlsl_handle, mldl_cfg->addr,
+				MPUREG_USER_CTRL, 1, &b);
+	ERROR_CHECK(result);
+
+	/* No change */
+	if ((b & BIT_AUX_IF_EN) != (enable * BIT_AUX_IF_EN))
+		return ML_SUCCESS;
+
+	b &= ~BIT_AUX_IF_EN;
+
+	if (!enable) {
+		result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+					       MPUREG_USER_CTRL,
+					       (b | BIT_AUX_IF_EN));
+		ERROR_CHECK(result);
+	} else {
+		/* Coming out of I2C is tricky due to several erratta.  Do not
+		 * modify this algorithm
+		 */
+		/*
+		 * 1) wait for the right time and send the command to change
+		 * the aux i2c slave address to an invalid address that will
+		 * get nack'ed
+		 *
+		 * 0x00 is broadcast.  0x7F is unlikely to be used by any aux.
+		 */
+		result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+					       MPUREG_AUX_SLV_ADDR, 0x7F);
+		ERROR_CHECK(result);
+		/*
+		 * 2) wait enough time for a nack to occur, then go into
+		 *    bypass mode:
+		 */
+		MLOSSleep(2);
+		result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+					       MPUREG_USER_CTRL, (b));
+		ERROR_CHECK(result);
+		/*
+		 * 3) wait for up to one MPU cycle then restore the slave
+		 *    address
+		 */
+		MLOSSleep(5);
+		result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+					       MPUREG_AUX_SLV_ADDR,
+					       mldl_cfg->pdata->
+					       accel.address);
+		ERROR_CHECK(result);
+
+		/*
+		 * 4) reset the ime interface
+		 */
+#ifdef M_HW
+		result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+					       MPUREG_USER_CTRL,
+					       (b | BIT_I2C_MST_RST));
+
+#else
+		result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+					       MPUREG_USER_CTRL,
+					       (b | BIT_AUX_IF_RST));
+#endif
+		ERROR_CHECK(result);
+		MLOSSleep(2);
+	}
+
+	return result;
+}
+
+struct tsProdRevMap {
+	unsigned char siliconRev;
+	unsigned short sensTrim;
+};
+
+#define NUM_OF_PROD_REVS (DIM(prodRevsMap))
+
+/* NOTE : 'npp' is a non production part */
+#ifdef M_HW
+#define OLDEST_PROD_REV_SUPPORTED 1
+static struct tsProdRevMap prodRevsMap[] = {
+	{0, 0},
+	{MPU_SILICON_REV_A1, 131},	/* 1 A1 */
+	{MPU_SILICON_REV_A1, 131},	/* 2 A1 */
+	{MPU_SILICON_REV_A1, 131},	/* 3 A1 */
+	{MPU_SILICON_REV_A1, 131},	/* 4 A1 */
+	{MPU_SILICON_REV_A1, 131},	/* 5 A1 */
+};
+
+#else				/* !M_HW */
+#define OLDEST_PROD_REV_SUPPORTED 11
+
+static struct tsProdRevMap prodRevsMap[] = {
+	{0, 0},
+	{MPU_SILICON_REV_A4, 131},	/* 1 A? OBSOLETED */
+	{MPU_SILICON_REV_A4, 131},	/* 2 | */
+	{MPU_SILICON_REV_A4, 131},	/* 3 V */
+	{MPU_SILICON_REV_A4, 131},	/* 4 */
+	{MPU_SILICON_REV_A4, 131},	/* 5 */
+	{MPU_SILICON_REV_A4, 131},	/* 6 */
+	{MPU_SILICON_REV_A4, 131},	/* 7 */
+	{MPU_SILICON_REV_A4, 131},	/* 8 */
+	{MPU_SILICON_REV_A4, 131},	/* 9 */
+	{MPU_SILICON_REV_A4, 131},	/* 10 */
+	{MPU_SILICON_REV_B1, 131},	/* 11 B1 */
+	{MPU_SILICON_REV_B1, 131},	/* 12 | */
+	{MPU_SILICON_REV_B1, 131},	/* 13 V */
+	{MPU_SILICON_REV_B1, 131},	/* 14 B4 */
+	{MPU_SILICON_REV_B4, 131},	/* 15 | */
+	{MPU_SILICON_REV_B4, 131},	/* 16 V */
+	{MPU_SILICON_REV_B4, 131},	/* 17 */
+	{MPU_SILICON_REV_B4, 131},	/* 18 */
+	{MPU_SILICON_REV_B4, 115},	/* 19  */
+	{MPU_SILICON_REV_B4, 115},	/* 20 */
+	{MPU_SILICON_REV_B6, 131},	/* 21 B6 (B6/A9)  */
+	{MPU_SILICON_REV_B4, 115},	/* 22 B4 (B7/A10) */
+	{MPU_SILICON_REV_B6, 0},	/* 23 B6 (npp)    */
+	{MPU_SILICON_REV_B6, 0},	/* 24 |  (npp)    */
+	{MPU_SILICON_REV_B6, 0},	/* 25 V  (npp)    */
+	{MPU_SILICON_REV_B6, 131},	/* 26    (B6/A11) */
+};
+#endif				/* !M_HW */
+
+/**
+ *  @internal
+ *  @brief  Get the silicon revision ID from OTP.
+ *          The silicon revision number is in read from OTP bank 0,
+ *          ADDR6[7:2].  The corresponding ID is retrieved by lookup
+ *          in a map.
+ *  @return The silicon revision ID (0 on error).
+ */
+static int MLDLGetSiliconRev(struct mldl_cfg *pdata,
+			     void *mlsl_handle)
+{
+	int result;
+	unsigned char index = 0x00;
+	unsigned char bank =
+	    (BIT_PRFTCH_EN | BIT_CFG_USER_BANK | MPU_MEM_OTP_BANK_0);
+	unsigned short memAddr = ((bank << 8) | 0x06);
+
+	result = MLSLSerialReadMem(mlsl_handle, pdata->addr,
+				   memAddr, 1, &index);
+	ERROR_CHECK(result)
+	if (result)
+		return result;
+	index >>= 2;
+
+	/* clean the prefetch and cfg user bank bits */
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+				  MPUREG_BANK_SEL, 0);
+	ERROR_CHECK(result)
+	if (result)
+		return result;
+
+	if (index < OLDEST_PROD_REV_SUPPORTED || NUM_OF_PROD_REVS <= index) {
+		pdata->silicon_revision = 0;
+		pdata->trim = 0;
+		MPL_LOGE("Unsupported Product Revision Detected : %d\n", index);
+		return ML_ERROR_INVALID_MODULE;
+	}
+
+	pdata->silicon_revision = prodRevsMap[index].siliconRev;
+	pdata->trim = prodRevsMap[index].sensTrim;
+
+	if (pdata->trim == 0) {
+		MPL_LOGE("sensitivity trim is 0"
+			 " - unsupported non production part.\n");
+		return ML_ERROR_INVALID_MODULE;
+	}
+
+	return result;
+}
+
+/**
+ *  @brief      Enable/Disable the use MPU's VDDIO level shifters.
+ *              When enabled the voltage interface with AUX or other external
+ *              accelerometer is using Vlogic instead of VDD (supply).
+ *
+ *  @note       Must be called after MLSerialOpen().
+ *  @note       Typically be called before MLDmpOpen().
+ *              If called after MLDmpOpen(), must be followed by a call to
+ *              MLDLApplyLevelShifterBit() to write the setting on the hw.
+ *
+ *  @param[in]  enable
+ *                  1 to enable, 0 to disable
+ *
+ *  @return     ML_SUCCESS if successfull, a non-zero error code otherwise.
+**/
+static int MLDLSetLevelShifterBit(struct mldl_cfg *pdata,
+				  void *mlsl_handle,
+				  unsigned char enable)
+{
+#ifndef M_HW
+	int result;
+	unsigned char reg;
+	unsigned char mask;
+	unsigned char regval;
+
+	if (0 == pdata->silicon_revision)
+		return ML_ERROR_INVALID_PARAMETER;
+
+	/*-- on parts before B6 the VDDIO bit is bit 7 of ACCEL_BURST_ADDR --
+	  NOTE: this is incompatible with ST accelerometers where the VDDIO
+		bit MUST be set to enable ST's internal logic to autoincrement
+		the register address on burst reads --*/
+	if ((pdata->silicon_revision & 0xf) < MPU_SILICON_REV_B6) {
+		reg = MPUREG_ACCEL_BURST_ADDR;
+		mask = 0x80;
+	} else {
+		/*-- on B6 parts the VDDIO bit was moved to FIFO_EN2 =>
+		  the mask is always 0x04 --*/
+		reg = MPUREG_FIFO_EN2;
+		mask = 0x04;
+	}
+
+	result = MLSLSerialRead(mlsl_handle, pdata->addr, reg, 1, &regval);
+	if (result)
+		return result;
+
+	if (enable)
+		regval |= mask;
+	else
+		regval &= ~mask;
+
+	result =
+	    MLSLSerialWriteSingle(mlsl_handle, pdata->addr, reg, regval);
+
+	return result;
+#else
+	return ML_SUCCESS;
+#endif
+}
+
+
+#ifdef M_HW
+/**
+ *  @internal
+ * @param reset 1 to reset hardware
+**/
+static tMLError MLDLPowerMgmtMantis(struct mldl_cfg *pdata,
+				    void *mlsl_handle,
+				    unsigned char reset,
+				    unsigned char powerselection)
+{
+	unsigned char b;
+	tMLError result;
+
+	if (powerselection < 0 || powerselection > 7)
+		return ML_ERROR_INVALID_PARAMETER;
+
+	result =
+	    MLSLSerialRead(mlsl_handle, pdata->addr, MPUREG_PWR_MGMT_1, 1,
+			   &b);
+	ERROR_CHECK(result);
+
+	b &= ~(BITS_PWRSEL);
+
+	if (reset) {
+		/* Current sillicon has an errata where the reset will get
+		 * nacked.  Ignore the error code for now. */
+		result = MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+					       MPUREG_PWR_MGM, b | 0x80);
+#define M_HW_RESET_ERRATTA
+#ifndef M_HW_RESET_ERRATTA
+		ERROR_CHECK(result);
+#else
+		MLOSSleep(50);
+#endif
+	}
+
+	b |= (powerselection << 4);
+
+	if (b & BITS_PWRSEL)
+		pdata->is_suspended = FALSE;
+	else
+		pdata->is_suspended = TRUE;
+
+	result = MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+				       MPUREG_PWR_MGM, b);
+	ERROR_CHECK(result);
+
+	return ML_SUCCESS;
+}
+
+/**
+ *  @internal
+ */
+static tMLError MLDLStandByGyros(struct mldl_cfg *pdata,
+				 void *mlsl_handle,
+				 unsigned char disable_gx,
+				 unsigned char disable_gy,
+				 unsigned char disable_gz)
+{
+	unsigned char b;
+	tMLError result;
+
+	result =
+	    MLSLSerialRead(mlsl_handle, pdata->addr, MPUREG_PWR_MGMT_2, 1,
+			   &b);
+	ERROR_CHECK(result);
+
+	b &= ~(BIT_STBY_XG | BIT_STBY_YG | BIT_STBY_ZG);
+	b |= (disable_gx << 2 | disable_gy << 1 | disable_gz);
+
+	result = MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+				       MPUREG_PWR_MGMT_2, b);
+	ERROR_CHECK(result);
+
+	return ML_SUCCESS;
+}
+
+/**
+ *  @internal
+ */
+static tMLError MLDLStandByAccels(struct mldl_cfg *pdata,
+				  void *mlsl_handle,
+				  unsigned char disable_ax,
+				  unsigned char disable_ay,
+				  unsigned char disable_az)
+{
+	unsigned char b;
+	tMLError result;
+
+	result =
+	    MLSLSerialRead(mlsl_handle, pdata->addr, MPUREG_PWR_MGMT_2, 1,
+			   &b);
+	ERROR_CHECK(result);
+
+	b &= ~(BIT_STBY_XA | BIT_STBY_YA | BIT_STBY_ZA);
+	b |= (disable_ax << 2 | disable_ay << 1 | disable_az);
+
+	result = MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+				       MPUREG_PWR_MGMT_2, b);
+	ERROR_CHECK(result);
+
+	return ML_SUCCESS;
+}
+
+#else				/* ! M_HW */
+
+/**
+ * @internal
+ * @brief   This function controls the power management on the MPU device.
+ *          The entire chip can be put to low power sleep mode, or individual
+ *          gyros can be turned on/off.
+ *
+ *          Putting the device into sleep mode depending upon the changing needs
+ *          of the associated applications is a recommended method for reducing
+ *          power consuption.  It is a safe opearation in that sleep/wake up of
+ *          gyros while running will not result in any interruption of data.
+ *
+ *          Although it is entirely allowed to put the device into full sleep
+ *          while running the DMP, it is not recomended because it will disrupt
+ *          the ongoing calculations carried on inside the DMP and consequently
+ *          the sensor fusion algorithm. Furthermore, while in sleep mode
+ *          read & write operation from the app processor on both registers and
+ *          memory are disabled and can only regained by restoring the MPU in
+ *          normal power mode.
+ *          Disabling any of the gyro axis will reduce the associated power
+ *          consuption from the PLL but will not stop the DMP from running
+ *          state.
+ *
+ * @param   reset
+ *              Non-zero to reset the device. Note that this setting
+ *              is volatile and the corresponding register bit will
+ *              clear itself right after being applied.
+ * @param   sleep
+ *              Non-zero to put device into full sleep.
+ * @param   disable_gx
+ *              Non-zero to disable gyro X.
+ * @param   disable_gy
+ *              Non-zero to disable gyro Y.
+ * @param   disable_gz
+ *              Non-zero to disable gyro Z.
+ *
+ * @return  ML_SUCCESS if successfull; a non-zero error code otherwise.
+ */
+static int MLDLPowerMgmtMPU(struct mldl_cfg *pdata,
+			    void *mlsl_handle,
+			    unsigned char reset,
+			    unsigned char sleep,
+			    unsigned char disable_gx,
+			    unsigned char disable_gy,
+			    unsigned char disable_gz)
+{
+	unsigned char b;
+	int result;
+
+	result =
+	    MLSLSerialRead(mlsl_handle, pdata->addr, MPUREG_PWR_MGM, 1,
+			   &b);
+	ERROR_CHECK(result);
+
+	/* If we are awake, we need to put it in bypass before resetting */
+	if ((!(b & BIT_SLEEP)) && reset)
+		result = MLDLSetI2CBypass(pdata, mlsl_handle, 1);
+
+	/* Reset if requested */
+	if (reset) {
+		result =
+		    MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+					  MPUREG_PWR_MGM, b | BIT_H_RESET);
+		MLOSSleep(5);
+	}
+
+	/* Some chips are awake after reset and some are asleep, check the
+	 * status */
+	result =
+	    MLSLSerialRead(mlsl_handle, pdata->addr, MPUREG_PWR_MGM, 1,
+			   &b);
+	ERROR_CHECK(result);
+
+	/* Update the suspended state just in case we return early */
+	if (b & BIT_SLEEP)
+		pdata->is_suspended = TRUE;
+	else
+		pdata->is_suspended = FALSE;
+
+	if ((b & (BIT_SLEEP | BIT_STBY_XG | BIT_STBY_YG | BIT_STBY_ZG))
+	    == (((sleep != 0) * BIT_SLEEP) |
+		((disable_gx != 0) * BIT_STBY_XG) |
+		((disable_gy != 0) * BIT_STBY_YG) |
+		((disable_gz != 0) * BIT_STBY_ZG))) {
+		return ML_SUCCESS;
+	}
+
+	/*
+	 * This specific transition between states needs to be reinterpreted:
+	 *    (1,1,1,1) -> (0,1,1,1) has to become
+	 *    (1,1,1,1) -> (1,0,0,0) -> (0,1,1,1)
+	 * where
+	 *    (1,1,1,1) is (sleep=1,disable_gx=1,disable_gy=1,disable_gz=1)
+	 */
+	if ((b & (BIT_SLEEP | BIT_STBY_XG | BIT_STBY_YG | BIT_STBY_ZG)) ==
+		 (BIT_SLEEP | BIT_STBY_XG | BIT_STBY_YG | BIT_STBY_ZG)
+	    && ((!sleep) && disable_gx && disable_gy && disable_gz)) {
+		result = MLDLPowerMgmtMPU(pdata, mlsl_handle, 0, 1, 0, 0, 0);
+		if (result)
+			return result;
+		b |= BIT_SLEEP;
+		b &= ~(BIT_STBY_XG | BIT_STBY_YG | BIT_STBY_ZG);
+	}
+
+
+	if ((b & BIT_SLEEP) != ((sleep != 0) * BIT_SLEEP)) {
+		if (sleep) {
+			result = MLDLSetI2CBypass(pdata, mlsl_handle, 1);
+			ERROR_CHECK(result);
+			b |= BIT_SLEEP;
+			result =
+			    MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+						  MPUREG_PWR_MGM, b);
+			ERROR_CHECK(result);
+			pdata->is_suspended = TRUE;
+		} else {
+			b &= ~BIT_SLEEP;
+
+			result =
+			    MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+						  MPUREG_PWR_MGM, b);
+			ERROR_CHECK(result);
+			pdata->is_suspended = FALSE;
+			MLOSSleep(5);
+		}
+	}
+    /*---
+      WORKAROUND FOR PUTTING GYRO AXIS in STAND-BY MODE
+      1) put one axis at a time in stand-by
+      ---*/
+	if ((b & BIT_STBY_XG) != ((disable_gx != 0) * BIT_STBY_XG)) {
+		b ^= BIT_STBY_XG;
+		result = MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+					       MPUREG_PWR_MGM, b);
+		ERROR_CHECK(result);
+	}
+	if ((b & BIT_STBY_YG) != ((disable_gy != 0) * BIT_STBY_YG)) {
+		b ^= BIT_STBY_YG;
+		result = MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+					       MPUREG_PWR_MGM, b);
+		ERROR_CHECK(result);
+	}
+	if ((b & BIT_STBY_ZG) != ((disable_gz != 0) * BIT_STBY_ZG)) {
+		b ^= BIT_STBY_ZG;
+		result = MLSLSerialWriteSingle(mlsl_handle, pdata->addr,
+					       MPUREG_PWR_MGM, b);
+		ERROR_CHECK(result);
+	}
+
+	return ML_SUCCESS;
+}
+#endif				/* M_HW */
+
+
+void mpu_print_cfg(struct mldl_cfg *mldl_cfg)
+{
+	struct mpu3050_platform_data *pdata = mldl_cfg->pdata;
+	struct ext_slave_platform_data *accel = &mldl_cfg->pdata->accel;
+	struct ext_slave_platform_data *compass =
+	    &mldl_cfg->pdata->compass;
+	struct ext_slave_platform_data *pressure =
+	    &mldl_cfg->pdata->pressure;
+
+	MPL_LOGD("mldl_cfg.addr             = %02x\n", mldl_cfg->addr);
+	MPL_LOGD("mldl_cfg.int_config       = %02x\n",
+		 mldl_cfg->int_config);
+	MPL_LOGD("mldl_cfg.ext_sync         = %02x\n", mldl_cfg->ext_sync);
+	MPL_LOGD("mldl_cfg.full_scale       = %02x\n",
+		 mldl_cfg->full_scale);
+	MPL_LOGD("mldl_cfg.lpf              = %02x\n", mldl_cfg->lpf);
+	MPL_LOGD("mldl_cfg.clk_src          = %02x\n", mldl_cfg->clk_src);
+	MPL_LOGD("mldl_cfg.divider          = %02x\n", mldl_cfg->divider);
+	MPL_LOGD("mldl_cfg.dmp_enable       = %02x\n",
+		 mldl_cfg->dmp_enable);
+	MPL_LOGD("mldl_cfg.fifo_enable      = %02x\n",
+		 mldl_cfg->fifo_enable);
+	MPL_LOGD("mldl_cfg.dmp_cfg1         = %02x\n", mldl_cfg->dmp_cfg1);
+	MPL_LOGD("mldl_cfg.dmp_cfg2         = %02x\n", mldl_cfg->dmp_cfg2);
+	MPL_LOGD("mldl_cfg.offset_tc[0]     = %02x\n",
+		 mldl_cfg->offset_tc[0]);
+	MPL_LOGD("mldl_cfg.offset_tc[1]     = %02x\n",
+		 mldl_cfg->offset_tc[1]);
+	MPL_LOGD("mldl_cfg.offset_tc[2]     = %02x\n",
+		 mldl_cfg->offset_tc[2]);
+	MPL_LOGD("mldl_cfg.silicon_revision = %02x\n",
+		 mldl_cfg->silicon_revision);
+	MPL_LOGD("mldl_cfg.product_id       = %02x\n",
+		 mldl_cfg->product_id);
+	MPL_LOGD("mldl_cfg.trim             = %02x\n", mldl_cfg->trim);
+
+	if (mldl_cfg->accel) {
+		MPL_LOGD("slave_accel->suspend      = %02x\n",
+			 (int) mldl_cfg->accel->suspend);
+		MPL_LOGD("slave_accel->resume       = %02x\n",
+			 (int) mldl_cfg->accel->resume);
+		MPL_LOGD("slave_accel->read         = %02x\n",
+			 (int) mldl_cfg->accel->read);
+		MPL_LOGD("slave_accel->type         = %02x\n",
+			 mldl_cfg->accel->type);
+		MPL_LOGD("slave_accel->reg          = %02x\n",
+			 mldl_cfg->accel->reg);
+		MPL_LOGD("slave_accel->len          = %02x\n",
+			 mldl_cfg->accel->len);
+		MPL_LOGD("slave_accel->endian       = %02x\n",
+			 mldl_cfg->accel->endian);
+		MPL_LOGD("slave_accel->range.mantissa= %02lx\n",
+			 mldl_cfg->accel->range.mantissa);
+		MPL_LOGD("slave_accel->range.fraction= %02lx\n",
+			 mldl_cfg->accel->range.fraction);
+	} else {
+		MPL_LOGD("slave_accel               = NULL\n");
+	}
+
+	if (mldl_cfg->compass) {
+		MPL_LOGD("slave_compass->suspend    = %02x\n",
+			 (int) mldl_cfg->compass->suspend);
+		MPL_LOGD("slave_compass->resume     = %02x\n",
+			 (int) mldl_cfg->compass->resume);
+		MPL_LOGD("slave_compass->read       = %02x\n",
+			 (int) mldl_cfg->compass->read);
+		MPL_LOGD("slave_compass->type       = %02x\n",
+			 mldl_cfg->compass->type);
+		MPL_LOGD("slave_compass->reg        = %02x\n",
+			 mldl_cfg->compass->reg);
+		MPL_LOGD("slave_compass->len        = %02x\n",
+			 mldl_cfg->compass->len);
+		MPL_LOGD("slave_compass->endian     = %02x\n",
+			 mldl_cfg->compass->endian);
+		MPL_LOGD("slave_compass->range.mantissa= %02lx\n",
+			 mldl_cfg->compass->range.mantissa);
+		MPL_LOGD("slave_compass->range.fraction= %02lx\n",
+			 mldl_cfg->compass->range.fraction);
+
+	} else {
+		MPL_LOGD("slave_compass             = NULL\n");
+	}
+
+	if (mldl_cfg->pressure) {
+		MPL_LOGD("slave_pressure->suspend    = %02x\n",
+			 (int) mldl_cfg->pressure->suspend);
+		MPL_LOGD("slave_pressure->resume     = %02x\n",
+			 (int) mldl_cfg->pressure->resume);
+		MPL_LOGD("slave_pressure->read       = %02x\n",
+			 (int) mldl_cfg->pressure->read);
+		MPL_LOGD("slave_pressure->type       = %02x\n",
+			 mldl_cfg->pressure->type);
+		MPL_LOGD("slave_pressure->reg        = %02x\n",
+			 mldl_cfg->pressure->reg);
+		MPL_LOGD("slave_pressure->len        = %02x\n",
+			 mldl_cfg->pressure->len);
+		MPL_LOGD("slave_pressure->endian     = %02x\n",
+			 mldl_cfg->pressure->endian);
+		MPL_LOGD("slave_pressure->range.mantissa= %02lx\n",
+			 mldl_cfg->pressure->range.mantissa);
+		MPL_LOGD("slave_pressure->range.fraction= %02lx\n",
+			 mldl_cfg->pressure->range.fraction);
+
+	} else {
+		MPL_LOGD("slave_pressure             = NULL\n");
+	}
+	MPL_LOGD("accel->get_slave_descr    = %x\n",
+		 (unsigned int) accel->get_slave_descr);
+	MPL_LOGD("accel->irq                = %02x\n", accel->irq);
+	MPL_LOGD("accel->adapt_num          = %02x\n", accel->adapt_num);
+	MPL_LOGD("accel->bus                = %02x\n", accel->bus);
+	MPL_LOGD("accel->address            = %02x\n", accel->address);
+	MPL_LOGD("accel->orientation        =\n"
+		 "                            %2d %2d %2d\n"
+		 "                            %2d %2d %2d\n"
+		 "                            %2d %2d %2d\n",
+		 accel->orientation[0], accel->orientation[1],
+		 accel->orientation[2], accel->orientation[3],
+		 accel->orientation[4], accel->orientation[5],
+		 accel->orientation[6], accel->orientation[7],
+		 accel->orientation[8]);
+	MPL_LOGD("compass->get_slave_descr  = %x\n",
+		 (unsigned int) compass->get_slave_descr);
+	MPL_LOGD("compass->irq              = %02x\n", compass->irq);
+	MPL_LOGD("compass->adapt_num        = %02x\n", compass->adapt_num);
+	MPL_LOGD("compass->bus              = %02x\n", compass->bus);
+	MPL_LOGD("compass->address          = %02x\n", compass->address);
+	MPL_LOGD("compass->orientation      =\n"
+		 "                            %2d %2d %2d\n"
+		 "                            %2d %2d %2d\n"
+		 "                            %2d %2d %2d\n",
+		 compass->orientation[0], compass->orientation[1],
+		 compass->orientation[2], compass->orientation[3],
+		 compass->orientation[4], compass->orientation[5],
+		 compass->orientation[6], compass->orientation[7],
+		 compass->orientation[8]);
+	MPL_LOGD("pressure->get_slave_descr  = %x\n",
+		 (unsigned int) pressure->get_slave_descr);
+	MPL_LOGD("pressure->irq             = %02x\n", pressure->irq);
+	MPL_LOGD("pressure->adapt_num       = %02x\n", pressure->adapt_num);
+	MPL_LOGD("pressure->bus             = %02x\n", pressure->bus);
+	MPL_LOGD("pressure->address         = %02x\n", pressure->address);
+	MPL_LOGD("pressure->orientation     =\n"
+		 "                            %2d %2d %2d\n"
+		 "                            %2d %2d %2d\n"
+		 "                            %2d %2d %2d\n",
+		 pressure->orientation[0], pressure->orientation[1],
+		 pressure->orientation[2], pressure->orientation[3],
+		 pressure->orientation[4], pressure->orientation[5],
+		 pressure->orientation[6], pressure->orientation[7],
+		 pressure->orientation[8]);
+
+	MPL_LOGD("pdata->int_config         = %02x\n", pdata->int_config);
+	MPL_LOGD("pdata->level_shifter      = %02x\n",
+		 pdata->level_shifter);
+	MPL_LOGD("pdata->orientation        =\n"
+		 "                            %2d %2d %2d\n"
+		 "                            %2d %2d %2d\n"
+		 "                            %2d %2d %2d\n",
+		 pdata->orientation[0], pdata->orientation[1],
+		 pdata->orientation[2], pdata->orientation[3],
+		 pdata->orientation[4], pdata->orientation[5],
+		 pdata->orientation[6], pdata->orientation[7],
+		 pdata->orientation[8]);
+
+	MPL_LOGD("Struct sizes: mldl_cfg: %d, "
+		 "ext_slave_descr:%d, "
+		 "mpu3050_platform_data:%d: RamOffset: %d\n",
+		 sizeof(struct mldl_cfg), sizeof(struct ext_slave_descr),
+		 sizeof(struct mpu3050_platform_data),
+		 offsetof(struct mldl_cfg, ram));
+}
+
+/*******************************************************************************
+ *******************************************************************************
+ * Exported functions
+ *******************************************************************************
+ ******************************************************************************/
+
+/**
+ * Initializes the pdata structure to defaults.
+ *
+ * Opens the device to read silicon revision, product id and whoami.
+ *
+ * @param mldl_cfg
+ *          The internal device configuration data structure.
+ * @param mlsl_handle
+ *          The serial communication handle.
+ *
+ * @return ML_SUCCESS if silicon revision, product id and woami are supported
+ *         by this software.
+ */
+int mpu3050_open(struct mldl_cfg *mldl_cfg,
+		 void *mlsl_handle,
+		 void *accel_handle,
+		 void *compass_handle,
+		 void *pressure_handle)
+{
+	int result;
+	/* Default is Logic HIGH, pushpull, latch disabled, anyread to clear */
+	mldl_cfg->int_config = BIT_INT_ANYRD_2CLEAR | BIT_DMP_INT_EN;
+	mldl_cfg->clk_src = MPU_CLK_SEL_PLLGYROZ;
+	mldl_cfg->lpf = MPU_FILTER_42HZ;
+	mldl_cfg->full_scale = MPU_FS_2000DPS;
+	mldl_cfg->divider = 4;
+	mldl_cfg->dmp_enable = 1;
+	mldl_cfg->fifo_enable = 1;
+	mldl_cfg->ext_sync = 0;
+	mldl_cfg->dmp_cfg1 = 0;
+	mldl_cfg->dmp_cfg2 = 0;
+	mldl_cfg->gyro_power = 0;
+	if (mldl_cfg->addr == 0) {
+#ifdef __KERNEL__
+		return ML_ERROR_INVALID_PARAMETER;
+#else
+		mldl_cfg->addr = 0x68;
+#endif
+	}
+
+	/*
+	 * Reset,
+	 * Take the DMP out of sleep, and
+	 * read the product_id, sillicon rev and whoami
+	 */
+#ifdef M_HW
+	result =
+	    MLDLPowerMgmtMantis(mldl_cfg, mlsl_handle, RESET, WAKE_UP);
+#else
+	result =
+	    MLDLPowerMgmtMPU(mldl_cfg, mlsl_handle, RESET, 0, 0, 0, 0);
+#endif
+	ERROR_CHECK(result);
+
+	result = MLDLGetSiliconRev(mldl_cfg, mlsl_handle);
+	ERROR_CHECK(result);
+	result = MLSLSerialRead(mlsl_handle, mldl_cfg->addr,
+				MPUREG_PRODUCT_ID, 1,
+				&mldl_cfg->product_id);
+	ERROR_CHECK(result);
+
+	/* Get the factory temperature compensation offsets */
+	result = MLSLSerialRead(mlsl_handle, mldl_cfg->addr,
+				MPUREG_XG_OFFS_TC, 1,
+				&mldl_cfg->offset_tc[0]);
+	ERROR_CHECK(result);
+	result = MLSLSerialRead(mlsl_handle, mldl_cfg->addr,
+				MPUREG_YG_OFFS_TC, 1,
+				&mldl_cfg->offset_tc[1]);
+	ERROR_CHECK(result);
+	result = MLSLSerialRead(mlsl_handle, mldl_cfg->addr,
+				MPUREG_ZG_OFFS_TC, 1,
+				&mldl_cfg->offset_tc[2]);
+	ERROR_CHECK(result);
+
+	/* Configure the MPU */
+#ifdef M_HW
+	result = MLDLPowerMgmtMantis(mldl_cfg, mlsl_handle, 0, SLEEP);
+#else
+	result =
+	    MLDLPowerMgmtMPU(mldl_cfg, mlsl_handle, 0, SLEEP, 0, 0, 0);
+#endif
+	ERROR_CHECK(result);
+
+	if (mldl_cfg->accel && mldl_cfg->accel->init) {
+		result = mldl_cfg->accel->init(accel_handle,
+					mldl_cfg->accel,
+					&mldl_cfg->pdata->accel);
+		ERROR_CHECK(result);
+	}
+
+	if (mldl_cfg->compass && mldl_cfg->compass->init) {
+		result = mldl_cfg->compass->init(compass_handle,
+						mldl_cfg->compass,
+						&mldl_cfg->pdata->compass);
+		if (ML_SUCCESS != result) {
+			MPL_LOGE("mldl_cfg->compass->init returned %d\n",
+				result);
+			goto out_accel;
+		}
+	}
+
+	if (mldl_cfg->pressure && mldl_cfg->pressure->init) {
+		result = mldl_cfg->pressure->init(pressure_handle,
+						mldl_cfg->pressure,
+						&mldl_cfg->pdata->pressure);
+		if (ML_SUCCESS != result) {
+			MPL_LOGE("mldl_cfg->pressure->init returned %d\n",
+				result);
+			goto out_compass;
+		}
+	}
+
+	return result;
+
+out_compass:
+	if (mldl_cfg->compass->init)
+		mldl_cfg->compass->exit(compass_handle,
+				mldl_cfg->compass,
+				&mldl_cfg->pdata->compass);
+out_accel:
+	if (mldl_cfg->accel->init)
+		mldl_cfg->accel->exit(accel_handle,
+				mldl_cfg->accel,
+				&mldl_cfg->pdata->accel);
+	return result;
+
+}
+
+/**
+ * Close the mpu3050 interface
+ *
+ * @param mldl_cfg pointer to the configuration structure
+ * @param mlsl_handle pointer to the serial layer handle
+ *
+ * @return ML_SUCCESS or non-zero error code
+ */
+int mpu3050_close(struct mldl_cfg *mldl_cfg,
+		  void *mlsl_handle,
+		  void *accel_handle,
+		  void *compass_handle,
+		  void *pressure_handle)
+{
+	int result = ML_SUCCESS;
+	int ret_result = ML_SUCCESS;
+
+	if (mldl_cfg->accel && mldl_cfg->accel->exit) {
+		result = mldl_cfg->accel->exit(accel_handle,
+					mldl_cfg->accel,
+					&mldl_cfg->pdata->accel);
+		if (ML_SUCCESS != result)
+			MPL_LOGE("Accel exit failed %d\n", result);
+		ret_result = result;
+	}
+	if (ML_SUCCESS == ret_result)
+		ret_result = result;
+
+	if (mldl_cfg->compass && mldl_cfg->compass->exit) {
+		result = mldl_cfg->compass->exit(compass_handle,
+						mldl_cfg->compass,
+						&mldl_cfg->pdata->compass);
+		if (ML_SUCCESS != result)
+			MPL_LOGE("Compass exit failed %d\n", result);
+	}
+	if (ML_SUCCESS == ret_result)
+		ret_result = result;
+
+	if (mldl_cfg->pressure && mldl_cfg->pressure->exit) {
+		result = mldl_cfg->pressure->exit(pressure_handle,
+						mldl_cfg->pressure,
+						&mldl_cfg->pdata->pressure);
+		if (ML_SUCCESS != result)
+			MPL_LOGE("Pressure exit failed %d\n", result);
+	}
+	if (ML_SUCCESS == ret_result)
+		ret_result = result;
+
+	return ret_result;
+}
+
+/**
+ *  @brief  resume the MPU3050 device and all the other sensor
+ *          devices from their low power state.
+ *  @param  mlsl_handle
+ *              the main file handle to the MPU3050 device.
+ *  @param  accel_handle
+ *              an handle to the accelerometer device, if sitting
+ *              onto a separate bus. Can match mlsl_handle if
+ *              the accelerometer device operates on the same
+ *              primary bus of MPU.
+ *  @param  compass_handle
+ *              an handle to the compass device, if sitting
+ *              onto a separate bus. Can match mlsl_handle if
+ *              the compass device operates on the same
+ *              primary bus of MPU.
+ *  @param  pressure_handle
+ *              an handle to the pressure sensor device, if sitting
+ *              onto a separate bus. Can match mlsl_handle if
+ *              the pressure sensor device operates on the same
+ *              primary bus of MPU.
+ *  @param  resume_accel
+ *              whether resuming the accelerometer device is
+ *              actually needed (if the device supports low power
+ *              mode of some sort).
+ *  @param  resume_compass
+ *              whether resuming the compass device is
+ *              actually needed (if the device supports low power
+ *              mode of some sort).
+ *  @param  resume_pressure
+ *              whether resuming the pressure sensor device is
+ *              actually needed (if the device supports low power
+ *              mode of some sort).
+ *  @return  ML_SUCCESS or a non-zero error code.
+ */
+int mpu3050_resume(struct mldl_cfg *mldl_cfg,
+		   void *mlsl_handle,
+		   void *accel_handle,
+		   void *compass_handle,
+		   void *pressure_handle,
+		   bool resume_accel, bool resume_compass, bool resume_pressure)
+{
+	int result;
+	int ii;
+	int jj;
+	unsigned char reg;
+	unsigned char regs[7];
+
+
+#ifdef CONFIG_SENSORS_MPU_DEBUG
+	mpu_print_cfg(mldl_cfg);
+#endif
+
+	/* Wake up the part */
+#ifdef M_HW
+	result = MLDLPowerMgmtMantis(mldl_cfg, mlsl_handle, 0, WAKE_UP);
+#else
+	result = MLDLPowerMgmtMPU(mldl_cfg, mlsl_handle, 1, 0,
+				  mldl_cfg->gyro_power & BIT_STBY_XG,
+				  mldl_cfg->gyro_power & BIT_STBY_YG,
+				  mldl_cfg->gyro_power & BIT_STBY_ZG);
+#endif
+	ERROR_CHECK(result);
+
+	/* Configure the MPU */
+#ifdef M_HW
+	result = MLDLSetI2CBypass(mldl_cfg, mlsl_handle, 1);
+	ERROR_CHECK(result);
+	result = MLDLPowerMgmtMantis(mldl_cfg, mlsl_handle, RESET, SLEEP);
+	ERROR_CHECK(result);
+	result = MLDLPowerMgmtMantis(mldl_cfg, mlsl_handle, 0, WAKE_UP);
+	ERROR_CHECK(result);
+	/* setting int_config with the propert flag BIT_BYPASS_EN should be
+	   done by the setup functions */
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_INT_PIN_CFG,
+				       (mldl_cfg->pdata->int_config |
+					       BIT_BYPASS_EN));
+	ERROR_CHECK(result);
+	/* temporary: masking out higher bits to avoid switching intelligence */
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_INT_ENABLE,
+				       (mldl_cfg->int_config & 0x0f));
+	ERROR_CHECK(result);
+#else
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_INT_CFG,
+				       (mldl_cfg->
+					int_config | mldl_cfg->pdata->
+					int_config));
+	ERROR_CHECK(result);
+#endif
+
+	result = MLSLSerialRead(mlsl_handle, mldl_cfg->addr,
+				MPUREG_PWR_MGM, 1, &reg);
+	ERROR_CHECK(result);
+	reg &= ~BITS_CLKSEL;
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_PWR_MGM,
+				       mldl_cfg->clk_src | reg);
+	ERROR_CHECK(result);
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_SMPLRT_DIV,
+				       mldl_cfg->divider);
+	ERROR_CHECK(result);
+
+#ifdef M_HW
+	reg = DLPF_FS_SYNC_VALUE(0, mldl_cfg->full_scale, 0);
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_GYRO_CONFIG, reg);
+	reg = DLPF_FS_SYNC_VALUE(0, 0, mldl_cfg->lpf);
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_CONFIG, reg);
+#else
+	reg = DLPF_FS_SYNC_VALUE(mldl_cfg->ext_sync,
+				 mldl_cfg->full_scale, mldl_cfg->lpf);
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_DLPF_FS_SYNC, reg);
+#endif
+	ERROR_CHECK(result);
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_DMP_CFG_1,
+				       mldl_cfg->dmp_cfg1);
+	ERROR_CHECK(result);
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_DMP_CFG_2,
+				       mldl_cfg->dmp_cfg2);
+	ERROR_CHECK(result);
+
+	/* Write and verify memory */
+	for (ii = 0; ii < MPU_MEM_NUM_RAM_BANKS; ii++) {
+		unsigned char read[MPU_MEM_BANK_SIZE];
+
+		result = MLSLSerialWriteMem(mlsl_handle, mldl_cfg->addr,
+					    ((ii << 8) | 0x00),
+					    MPU_MEM_BANK_SIZE,
+					    mldl_cfg->ram[ii]);
+		ERROR_CHECK(result);
+		result = MLSLSerialReadMem(mlsl_handle, mldl_cfg->addr,
+					   ((ii << 8) | 0x00),
+					   MPU_MEM_BANK_SIZE, read);
+		ERROR_CHECK(result);
+
+#ifdef M_HW
+#define ML_SKIP_CHECK 38
+#else
+#define ML_SKIP_CHECK 20
+#endif
+		for (jj = 0; jj < MPU_MEM_BANK_SIZE; jj++) {
+			/* skip the register memory locations */
+			if (ii == 0 && jj < ML_SKIP_CHECK)
+				continue;
+			if (mldl_cfg->ram[ii][jj] != read[jj]) {
+				result = ML_ERROR_SERIAL_WRITE;
+				break;
+			}
+		}
+		ERROR_CHECK(result);
+	}
+
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_XG_OFFS_TC,
+				       mldl_cfg->offset_tc[0]);
+	ERROR_CHECK(result);
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_YG_OFFS_TC,
+				       mldl_cfg->offset_tc[1]);
+	ERROR_CHECK(result);
+	result = MLSLSerialWriteSingle(mlsl_handle, mldl_cfg->addr,
+				       MPUREG_ZG_OFFS_TC,
+				       mldl_cfg->offset_tc[2]);
+	ERROR_CHECK(result);
+
+	regs[0] = MPUREG_X_OFFS_USRH;
+	for (ii = 0; ii < DIM(mldl_cfg->offset); ii++) {
+		regs[1 + ii * 2] =
+		    (unsigned char)(mldl_cfg->offset[ii] >> 8) & 0xff;
+		regs[1 + ii * 2 + 1] =
+		    (unsigned char)(mldl_cfg->offset[ii] & 0xff);
+	}
+	result = MLSLSerialWrite(mlsl_handle, mldl_cfg->addr, 7, regs);
+	ERROR_CHECK(result);
+
+	/* Configure slaves */
+	result = MLDLSetLevelShifterBit(mldl_cfg, mlsl_handle,
+					mldl_cfg->pdata->level_shifter);
+	ERROR_CHECK(result);
+
+	if (resume_accel) {
+		if ((!mldl_cfg->accel) || (!mldl_cfg->accel->resume))
+			return ML_ERROR_INVALID_PARAMETER;
+
+		result = mldl_cfg->accel->resume(accel_handle,
+						 mldl_cfg->accel,
+						 &mldl_cfg->pdata->accel);
+		ERROR_CHECK(result);
+		if (EXT_SLAVE_BUS_SECONDARY == mldl_cfg->pdata->accel.bus) {
+			/* Address */
+			result =
+			    MLSLSerialWriteSingle(accel_handle,
+						  mldl_cfg->addr,
+						  MPUREG_AUX_SLV_ADDR,
+						  mldl_cfg->pdata->
+						  accel.address);
+			ERROR_CHECK(result);
+			/* Register */
+			result =
+			    MLSLSerialRead(accel_handle, mldl_cfg->addr,
+					   MPUREG_ACCEL_BURST_ADDR, 1,
+					   &reg);
+			ERROR_CHECK(result);
+			reg = ((reg & 0x80) | mldl_cfg->accel->reg);
+			/* Set VDDIO bit for ST accel */
+			if ((ACCEL_ID_LIS331 == mldl_cfg->accel->id)
+			    || (ACCEL_ID_LSM303 == mldl_cfg->accel->id)) {
+				reg |= 0x80;
+			}
+			result =
+			    MLSLSerialWriteSingle(accel_handle,
+						  mldl_cfg->addr,
+						  MPUREG_ACCEL_BURST_ADDR,
+						  reg);
+			ERROR_CHECK(result);
+			/* Length */
+			result =
+			    MLSLSerialRead(accel_handle, mldl_cfg->addr,
+					   MPUREG_USER_CTRL, 1, &reg);
+			ERROR_CHECK(result);
+			reg = (reg & ~BIT_AUX_RD_LENG);
+			result =
+			    MLSLSerialWriteSingle(accel_handle,
+						  mldl_cfg->addr,
+						  MPUREG_USER_CTRL, reg);
+			ERROR_CHECK(result);
+			result =
+			    MLDLSetI2CBypass(mldl_cfg, accel_handle, 0);
+			ERROR_CHECK(result);
+		}
+	}
+
+	if (resume_compass) {
+		if ((mldl_cfg->compass) && (mldl_cfg->compass->resume)) {
+			result = mldl_cfg->compass->resume(compass_handle,
+							   mldl_cfg->compass,
+							   &mldl_cfg->pdata->
+							   compass);
+			ERROR_CHECK(result);
+		}
+		ERROR_CHECK(result);
+		if (EXT_SLAVE_BUS_SECONDARY ==
+		    mldl_cfg->pdata->compass.bus) {
+			/* Address */
+			result =
+			    MLSLSerialWriteSingle(mlsl_handle,
+						  mldl_cfg->addr,
+						  MPUREG_AUX_SLV_ADDR,
+						  mldl_cfg->pdata->
+						  compass.address);
+			ERROR_CHECK(result);
+			/* Register */
+			result =
+			    MLSLSerialRead(mlsl_handle, mldl_cfg->addr,
+					   MPUREG_ACCEL_BURST_ADDR, 1,
+					   &reg);
+			ERROR_CHECK(result);
+			reg = ((reg & 0x80) | mldl_cfg->compass->reg);
+			result =
+			    MLSLSerialWriteSingle(mlsl_handle,
+						  mldl_cfg->addr,
+						  MPUREG_ACCEL_BURST_ADDR,
+						  reg);
+			ERROR_CHECK(result);
+
+#ifdef M_HW
+			/* Length, byte swapping, grouping & enable */
+			if (mldl_cfg->compass->len > BITS_SLV_LENG) {
+				MPL_LOGW("Limiting slave burst read length to "
+					 "the allowed maximum (15B, req. %d)\n",
+					 mldl_cfg->compass->len);
+				mldl_cfg->compass->len = BITS_SLV_LENG;
+			}
+			reg = mldl_cfg->compass->len;
+			if (mldl_cfg->compass->endian ==
+			    EXT_SLAVE_LITTLE_ENDIAN)
+				reg |= BIT_SLV_BYTE_SW;
+			reg |= BIT_SLV_GRP;
+			reg |= BIT_SLV_ENABLE;
+
+			result =
+			    MLSLSerialWriteSingle(mlsl_handle,
+						  mldl_cfg->addr,
+						  MPUREG_I2C_SLV0_CTRL,
+						  reg);
+#else
+			/* Length */
+			result =
+			    MLSLSerialRead(mlsl_handle, mldl_cfg->addr,
+					   MPUREG_USER_CTRL, 1, &reg);
+			ERROR_CHECK(result);
+			reg = (reg & ~BIT_AUX_RD_LENG);
+			result =
+			    MLSLSerialWriteSingle(mlsl_handle,
+						  mldl_cfg->addr,
+						  MPUREG_USER_CTRL, reg);
+			ERROR_CHECK(result);
+#endif
+			result =
+			    MLDLSetI2CBypass(mldl_cfg, mlsl_handle, 0);
+			ERROR_CHECK(result);
+		}
+	}
+
+	if (resume_pressure) {
+		if ((mldl_cfg->pressure) && (mldl_cfg->pressure->resume)) {
+			result = mldl_cfg->pressure->resume(pressure_handle,
+							   mldl_cfg->pressure,
+							   &mldl_cfg->pdata->
+							   pressure);
+			ERROR_CHECK(result);
+		}
+		ERROR_CHECK(result);
+	}
+
+	/* Now start */
+	result = MLDLDmpStart(mldl_cfg, mlsl_handle);
+	ERROR_CHECK(result);
+	return result;
+}
+
+
+/**
+ *  @brief  suspend the MPU3050 device and all the other sensor
+ *          devices into their low power state.
+ *  @param  mlsl_handle
+ *              the main file handle to the MPU3050 device.
+ *  @param  accel_handle
+ *              an handle to the accelerometer device, if sitting
+ *              onto a separate bus. Can match mlsl_handle if
+ *              the accelerometer device operates on the same
+ *              primary bus of MPU.
+ *  @param  compass_handle
+ *              an handle to the compass device, if sitting
+ *              onto a separate bus. Can match mlsl_handle if
+ *              the compass device operates on the same
+ *              primary bus of MPU.
+ *  @param  pressure_handle
+ *              an handle to the pressure sensor device, if sitting
+ *              onto a separate bus. Can match mlsl_handle if
+ *              the pressure sensor device operates on the same
+ *              primary bus of MPU.
+ *  @param  accel
+ *              whether suspending the accelerometer device is
+ *              actually needed (if the device supports low power
+ *              mode of some sort).
+ *  @param  compass
+ *              whether suspending the compass device is
+ *              actually needed (if the device supports low power
+ *              mode of some sort).
+ *  @param  pressure
+ *              whether suspending the pressure sensor device is
+ *              actually needed (if the device supports low power
+ *              mode of some sort).
+ *  @return  ML_SUCCESS or a non-zero error code.
+ */
+int mpu3050_suspend(struct mldl_cfg *mldl_cfg, void *mlsl_handle,
+		    void *accel_handle,
+		    void *compass_handle,
+		    void *pressure_handle,
+		    bool accel, bool compass, bool pressure)
+{
+	int result;
+	/* This puts the bus into bypass mode */
+
+#ifdef M_HW
+	result = MLDLSetI2CBypass(mldl_cfg, mlsl_handle, 1);
+	ERROR_CHECK(result);
+	result = MLDLPowerMgmtMantis(mldl_cfg, mlsl_handle, 0, SLEEP);
+#else
+	result =
+	    MLDLPowerMgmtMPU(mldl_cfg, mlsl_handle, 0, SLEEP, 0, 0, 0);
+#endif
+	if (ML_SUCCESS == result &&
+	    accel && mldl_cfg->accel && mldl_cfg->accel->suspend) {
+		result = mldl_cfg->accel->suspend(accel_handle,
+						  mldl_cfg->accel,
+						  &mldl_cfg->pdata->accel);
+	}
+
+	if (ML_SUCCESS == result && compass &&
+	    mldl_cfg->compass && mldl_cfg->compass->suspend) {
+		result = mldl_cfg->compass->suspend(compass_handle,
+						    mldl_cfg->compass,
+						    &mldl_cfg->
+						    pdata->compass);
+	}
+
+	if (ML_SUCCESS == result && pressure &&
+	    mldl_cfg->pressure && mldl_cfg->pressure->suspend) {
+		result = mldl_cfg->pressure->suspend(pressure_handle,
+						    mldl_cfg->pressure,
+						    &mldl_cfg->
+						    pdata->pressure);
+	}
+	return result;
+}
+
+
+/**
+ *  @brief  read raw sensor data from the accelerometer device
+ *          in use.
+ *  @param  data
+ *              a buffer to store the raw sensor data.
+ *  @return ML_SUCCESS if successful, a non-zero error code otherwise.
+ */
+int mpu3050_read_accel(struct mldl_cfg *mldl_cfg,
+		       void *mlsl_handle, unsigned char *data)
+{
+	if (NULL != mldl_cfg->accel && NULL != mldl_cfg->accel->read)
+		return mldl_cfg->accel->read(mlsl_handle,
+					     mldl_cfg->accel,
+					     &mldl_cfg->pdata->accel,
+					     data);
+	else
+		return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+}
+
+/**
+ *  @brief  read raw sensor data from the compass device
+ *          in use.
+ *  @param  data
+ *              a buffer to store the raw sensor data.
+ *  @return ML_SUCCESS if successful, a non-zero error code otherwise.
+ */
+int mpu3050_read_compass(struct mldl_cfg *mldl_cfg,
+			 void *mlsl_handle, unsigned char *data)
+{
+	if (NULL != mldl_cfg->compass && NULL != mldl_cfg->compass->read)
+		return mldl_cfg->compass->read(mlsl_handle,
+					       mldl_cfg->compass,
+					       &mldl_cfg->pdata->compass,
+					       data);
+	else
+		return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+}
+
+/**
+ *  @brief  read raw sensor data from the pressure device
+ *          in use.
+ *  @param  data
+ *              a buffer to store the raw sensor data.
+ *  @return ML_SUCCESS if successful, a non-zero error code otherwise.
+ */
+int mpu3050_read_pressure(struct mldl_cfg *mldl_cfg,
+			 void *mlsl_handle, unsigned char *data)
+{
+	if (NULL != mldl_cfg->pressure && NULL != mldl_cfg->pressure->read)
+		return mldl_cfg->pressure->read(mlsl_handle,
+					       mldl_cfg->pressure,
+					       &mldl_cfg->pdata->pressure,
+					       data);
+	else
+		return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+}
+
+int mpu3050_config_accel(struct mldl_cfg *mldl_cfg,
+			void *accel_handle,
+			struct ext_slave_config *data)
+{
+	if (NULL != mldl_cfg->accel && NULL != mldl_cfg->accel->config)
+		return mldl_cfg->accel->config(accel_handle,
+					mldl_cfg->accel,
+					&mldl_cfg->pdata->accel,
+					data);
+	else
+		return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+
+}
+
+int mpu3050_config_compass(struct mldl_cfg *mldl_cfg,
+			void *compass_handle,
+			struct ext_slave_config *data)
+{
+	if (NULL != mldl_cfg->compass && NULL != mldl_cfg->compass->config)
+		return mldl_cfg->compass->config(compass_handle,
+						mldl_cfg->compass,
+						&mldl_cfg->pdata->compass,
+						data);
+	else
+		return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+
+}
+
+int mpu3050_config_pressure(struct mldl_cfg *mldl_cfg,
+			void *pressure_handle,
+			struct ext_slave_config *data)
+{
+	if (NULL != mldl_cfg->pressure && NULL != mldl_cfg->pressure->config)
+		return mldl_cfg->pressure->config(pressure_handle,
+						mldl_cfg->pressure,
+						&mldl_cfg->pdata->pressure,
+						data);
+	else
+		return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+}
+
+
+/**
+ *@}
+ */
diff --git a/drivers/misc/mpu3050/mldl_cfg.h b/drivers/misc/mpu3050/mldl_cfg.h
new file mode 100644
index 000000000000..d714a0ee3ed8
--- /dev/null
+++ b/drivers/misc/mpu3050/mldl_cfg.h
@@ -0,0 +1,137 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+/**
+ *  @addtogroup MLDL
+ *
+ *  @{
+ *      @file   mldl_cfg.h
+ *      @brief  The Motion Library Driver Layer Configuration header file.
+ */
+
+#ifndef __MLDL_CFG_H__
+#define __MLDL_CFG_H__
+
+/* ------------------ */
+/* - Include Files. - */
+/* ------------------ */
+
+#include "mlsl.h"
+#include "mpu.h"
+
+/* --------------------- */
+/* -    Defines.       - */
+/* --------------------- */
+
+#define SAMPLING_PERIOD(mldl_cfg) \
+	(((((mldl_cfg->lpf) == 0) || ((mldl_cfg->lpf) == 7))		\
+		? (8000)						\
+		: (1000))						\
+		/ (mldl_cfg->divider + 1))
+
+/* --------------------- */
+/* -    Variables.     - */
+/* --------------------- */
+
+/* Platform data for the MPU */
+struct mldl_cfg {
+	/* MPU related configuration */
+	unsigned char addr;
+	unsigned char int_config;
+	unsigned char ext_sync;
+	unsigned char full_scale;
+	unsigned char lpf;
+	unsigned char clk_src;
+	unsigned char divider;
+	unsigned char dmp_enable;
+	unsigned char fifo_enable;
+	unsigned char dmp_cfg1;
+	unsigned char dmp_cfg2;
+	unsigned char gyro_power;
+	unsigned char offset_tc[MPU_NUM_AXES];
+	unsigned short offset[MPU_NUM_AXES];
+	unsigned char ram[MPU_MEM_NUM_RAM_BANKS][MPU_MEM_BANK_SIZE];
+
+	/* MPU Related stored status and info */
+	unsigned char silicon_revision;
+	unsigned char product_id;
+	unsigned short trim;
+
+	/* Driver/Kernel related state information */
+	int is_suspended;
+
+	/* Slave related information */
+	struct ext_slave_descr *accel;
+	struct ext_slave_descr *compass;
+	struct ext_slave_descr *pressure;
+
+	struct mpu3050_platform_data *pdata;
+};
+
+
+int mpu3050_open(struct mldl_cfg *mldl_cfg,
+		 void *mlsl_handle,
+		 void *accel_handle,
+		 void *compass_handle,
+		 void *pressure_handle);
+int mpu3050_close(struct mldl_cfg *mldl_cfg,
+		  void *mlsl_handle,
+		  void *accel_handle,
+		  void *compass_handle,
+		  void *pressure_handle);
+int mpu3050_resume(struct mldl_cfg *mldl_cfg,
+		   void *mlsl_handle,
+		   void *accel_handle,
+		   void *compass_handle,
+		   void *pressure_handle,
+		   bool resume_accel,
+		   bool resume_compass,
+		   bool resume_pressure);
+int mpu3050_suspend(struct mldl_cfg *mldl_cfg, void *mlsl_handle,
+		    void *accel_handle,
+		    void *compass_handle,
+		    void *pressure_handle,
+		    bool resume_accel,
+		    bool resume_compass,
+		    bool resume_pressure);
+int mpu3050_read_accel(struct mldl_cfg *mldl_cfg,
+		       void *accel_handle,
+		       unsigned char *data);
+int mpu3050_read_compass(struct mldl_cfg *mldl_cfg,
+			 void *compass_handle,
+			 unsigned char *data);
+int mpu3050_read_pressure(struct mldl_cfg *mldl_cfg, void *mlsl_handle,
+			  unsigned char *data);
+
+int mpu3050_config_accel(struct mldl_cfg *mldl_cfg,
+			 void *accel_handle,
+			 struct ext_slave_config *data);
+int mpu3050_config_compass(struct mldl_cfg *mldl_cfg,
+			   void *compass_handle,
+			   struct ext_slave_config *data);
+int mpu3050_config_pressure(struct mldl_cfg *mldl_cfg,
+			    void *pressure_handle,
+			    struct ext_slave_config *data);
+
+
+#endif				/* __MLDL_CFG_H__ */
+
+/**
+ *@}
+ */
diff --git a/drivers/misc/mpu3050/mlos-kernel.c b/drivers/misc/mpu3050/mlos-kernel.c
new file mode 100644
index 000000000000..ced9ba4f6f3c
--- /dev/null
+++ b/drivers/misc/mpu3050/mlos-kernel.c
@@ -0,0 +1,89 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+/**
+ * @defgroup
+ * @brief
+ *
+ * @{
+ * @file     mlos-kernel.c
+ * @brief
+ *
+ *
+ */
+
+#include "mlos.h"
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+void *MLOSMalloc(unsigned int numBytes)
+{
+	return kmalloc(numBytes, GFP_KERNEL);
+}
+
+tMLError MLOSFree(void *ptr)
+{
+	kfree(ptr);
+	return ML_SUCCESS;
+}
+
+tMLError MLOSCreateMutex(HANDLE *mutex)
+{
+	/* @todo implement if needed */
+	return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+}
+
+tMLError MLOSLockMutex(HANDLE mutex)
+{
+	/* @todo implement if needed */
+	return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+}
+
+tMLError MLOSUnlockMutex(HANDLE mutex)
+{
+	/* @todo implement if needed */
+	return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+}
+
+tMLError MLOSDestroyMutex(HANDLE handle)
+{
+	/* @todo implement if needed */
+	return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+}
+
+FILE *MLOSFOpen(char *filename)
+{
+	/* @todo implement if needed */
+	return NULL;
+}
+
+void MLOSFClose(FILE *fp)
+{
+	/* @todo implement if needed */
+}
+
+void MLOSSleep(int mSecs)
+{
+	msleep(mSecs);
+}
+
+unsigned long MLOSGetTickCount(void)
+{
+	/* @todo implement if needed */
+	return ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+}
diff --git a/drivers/misc/mpu3050/mlos.h b/drivers/misc/mpu3050/mlos.h
new file mode 100644
index 000000000000..4ebb86c9fa5c
--- /dev/null
+++ b/drivers/misc/mpu3050/mlos.h
@@ -0,0 +1,73 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+#ifndef _MLOS_H
+#define _MLOS_H
+
+#ifndef __KERNEL__
+#include <stdio.h>
+#endif
+
+#include "mltypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+	/* ------------ */
+	/* - Defines. - */
+	/* ------------ */
+
+	/* - MLOSCreateFile defines. - */
+
+#define MLOS_GENERIC_READ         ((unsigned int)0x80000000)
+#define MLOS_GENERIC_WRITE        ((unsigned int)0x40000000)
+#define MLOS_FILE_SHARE_READ      ((unsigned int)0x00000001)
+#define MLOS_FILE_SHARE_WRITE     ((unsigned int)0x00000002)
+#define MLOS_OPEN_EXISTING        ((unsigned int)0x00000003)
+
+	/* ---------- */
+	/* - Enums. - */
+	/* ---------- */
+
+	/* --------------- */
+	/* - Structures. - */
+	/* --------------- */
+
+	/* --------------------- */
+	/* - Function p-types. - */
+	/* --------------------- */
+
+	void *MLOSMalloc(unsigned int numBytes);
+	tMLError MLOSFree(void *ptr);
+	tMLError MLOSCreateMutex(HANDLE *mutex);
+	tMLError MLOSLockMutex(HANDLE mutex);
+	tMLError MLOSUnlockMutex(HANDLE mutex);
+	FILE *MLOSFOpen(char *filename);
+	void MLOSFClose(FILE *fp);
+
+	tMLError MLOSDestroyMutex(HANDLE handle);
+
+	void MLOSSleep(int mSecs);
+	unsigned long MLOSGetTickCount(void);
+
+#ifdef __cplusplus
+}
+#endif
+#endif				/* _MLOS_H */
diff --git a/drivers/misc/mpu3050/mlsl-kernel.c b/drivers/misc/mpu3050/mlsl-kernel.c
new file mode 100644
index 000000000000..908b16f16b24
--- /dev/null
+++ b/drivers/misc/mpu3050/mlsl-kernel.c
@@ -0,0 +1,331 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+#include "mlsl.h"
+#include "mpu-i2c.h"
+
+/* ------------ */
+/* - Defines. - */
+/* ------------ */
+
+/* ---------------------- */
+/* - Types definitions. - */
+/* ---------------------- */
+
+/* --------------------- */
+/* - Function p-types. - */
+/* --------------------- */
+
+/**
+ *  @brief  used to open the I2C or SPI serial port.
+ *          This port is used to send and receive data to the MPU device.
+ *  @param  portNum
+ *              The COM port number associated with the device in use.
+ *  @return ML_SUCCESS if successful, a non-zero error code otherwise.
+ */
+tMLError MLSLSerialOpen(char const *port, void **sl_handle)
+{
+	return ML_SUCCESS;
+}
+
+/**
+ *  @brief  used to reset any buffering the driver may be doing
+ *  @return ML_SUCCESS if successful, a non-zero error code otherwise.
+ */
+tMLError MLSLSerialReset(void *sl_handle)
+{
+	return ML_SUCCESS;
+}
+
+/**
+ *  @brief  used to close the I2C or SPI serial port.
+ *          This port is used to send and receive data to the MPU device.
+ *  @return ML_SUCCESS if successful, a non-zero error code otherwise.
+ */
+tMLError MLSLSerialClose(void *sl_handle)
+{
+	return ML_SUCCESS;
+}
+
+/**
+ *  @brief  used to read a single byte of data.
+ *          This should be sent by I2C or SPI.
+ *
+ *  @param  slaveAddr       I2C slave address of device.
+ *  @param  registerAddr    Register address to read.
+ *  @param  data            Single byte of data to read.
+ *
+ *  @return ML_SUCCESS if the command is successful, an error code otherwise.
+ */
+tMLError MLSLSerialWriteSingle(void *sl_handle,
+			       unsigned char slaveAddr,
+			       unsigned char registerAddr,
+			       unsigned char data)
+{
+	return sensor_i2c_write_register((struct i2c_adapter *) sl_handle,
+					 slaveAddr, registerAddr, data);
+}
+
+
+/**
+ *  @brief  used to write multiple bytes of data from registers.
+ *          This should be sent by I2C.
+ *
+ *  @param  slaveAddr       I2C slave address of device.
+ *  @param  registerAddr    Register address to write.
+ *  @param  length          Length of burst of data.
+ *  @param  data            Pointer to block of data.
+ *
+ *  @return ML_SUCCESS if successful, a non-zero error code otherwise.
+ */
+tMLError MLSLSerialWrite(void *sl_handle,
+			 unsigned char slaveAddr,
+			 unsigned short length, unsigned char const *data)
+{
+	tMLError result;
+	const unsigned short dataLength = length - 1;
+	const unsigned char startRegAddr = data[0];
+	unsigned char i2cWrite[SERIAL_MAX_TRANSFER_SIZE + 1];
+	unsigned short bytesWritten = 0;
+
+	while (bytesWritten < dataLength) {
+		unsigned short thisLen = min(SERIAL_MAX_TRANSFER_SIZE,
+					     dataLength - bytesWritten);
+		if (bytesWritten == 0) {
+			result = sensor_i2c_write((struct i2c_adapter *)
+						  sl_handle, slaveAddr,
+						  1 + thisLen, data);
+		} else {
+			/* manually increment register addr between chunks */
+			i2cWrite[0] = startRegAddr + bytesWritten;
+			memcpy(&i2cWrite[1], &data[1 + bytesWritten],
+			       thisLen);
+			result = sensor_i2c_write((struct i2c_adapter *)
+						  sl_handle, slaveAddr,
+						  1 + thisLen, i2cWrite);
+		}
+		if (ML_SUCCESS != result)
+			return result;
+		bytesWritten += thisLen;
+	}
+	return ML_SUCCESS;
+}
+
+
+/**
+ *  @brief  used to read multiple bytes of data from registers.
+ *          This should be sent by I2C.
+ *
+ *  @param  slaveAddr       I2C slave address of device.
+ *  @param  registerAddr    Register address to read.
+ *  @param  length          Length of burst of data.
+ *  @param  data            Pointer to block of data.
+ *
+ *  @return Zero if successful; an error code otherwise
+ */
+tMLError MLSLSerialRead(void *sl_handle,
+			unsigned char slaveAddr,
+			unsigned char registerAddr,
+			unsigned short length, unsigned char *data)
+{
+	tMLError result;
+	unsigned short bytesRead = 0;
+
+	if (registerAddr == MPUREG_FIFO_R_W
+	    || registerAddr == MPUREG_MEM_R_W) {
+		return ML_ERROR_INVALID_PARAMETER;
+	}
+	while (bytesRead < length) {
+		unsigned short thisLen =
+		    min(SERIAL_MAX_TRANSFER_SIZE, length - bytesRead);
+		result =
+		    sensor_i2c_read((struct i2c_adapter *) sl_handle,
+				    slaveAddr, registerAddr + bytesRead,
+				    thisLen, &data[bytesRead]);
+		if (ML_SUCCESS != result)
+			return result;
+		bytesRead += thisLen;
+	}
+	return ML_SUCCESS;
+}
+
+
+/**
+ *  @brief  used to write multiple bytes of data to the memory.
+ *          This should be sent by I2C.
+ *
+ *  @param  slaveAddr       I2C slave address of device.
+ *  @param  memAddr         The location in the memory to write to.
+ *  @param  length          Length of burst data.
+ *  @param  data            Pointer to block of data.
+ *
+ *  @return Zero if successful; an error code otherwise
+ */
+tMLError MLSLSerialWriteMem(void *sl_handle,
+			    unsigned char slaveAddr,
+			    unsigned short memAddr,
+			    unsigned short length,
+			    unsigned char const *data)
+{
+	tMLError result;
+	unsigned short bytesWritten = 0;
+
+	if ((memAddr & 0xFF) + length > MPU_MEM_BANK_SIZE) {
+		printk
+		    ("memory read length (%d B) extends beyond its limits (%d) "
+		     "if started at location %d\n", length,
+		     MPU_MEM_BANK_SIZE, memAddr & 0xFF);
+		return ML_ERROR_INVALID_PARAMETER;
+	}
+	while (bytesWritten < length) {
+		unsigned short thisLen =
+		    min(SERIAL_MAX_TRANSFER_SIZE, length - bytesWritten);
+		result =
+		    mpu_memory_write((struct i2c_adapter *) sl_handle,
+				     slaveAddr, memAddr + bytesWritten,
+				     thisLen, &data[bytesWritten]);
+		if (ML_SUCCESS != result)
+			return result;
+		bytesWritten += thisLen;
+	}
+	return ML_SUCCESS;
+}
+
+
+/**
+ *  @brief  used to read multiple bytes of data from the memory.
+ *          This should be sent by I2C.
+ *
+ *  @param  slaveAddr       I2C slave address of device.
+ *  @param  memAddr         The location in the memory to read from.
+ *  @param  length          Length of burst data.
+ *  @param  data            Pointer to block of data.
+ *
+ *  @return Zero if successful; an error code otherwise
+ */
+tMLError MLSLSerialReadMem(void *sl_handle,
+			   unsigned char slaveAddr,
+			   unsigned short memAddr,
+			   unsigned short length, unsigned char *data)
+{
+	tMLError result;
+	unsigned short bytesRead = 0;
+
+	if ((memAddr & 0xFF) + length > MPU_MEM_BANK_SIZE) {
+		printk
+		    ("memory read length (%d B) extends beyond its limits (%d) "
+		     "if started at location %d\n", length,
+		     MPU_MEM_BANK_SIZE, memAddr & 0xFF);
+		return ML_ERROR_INVALID_PARAMETER;
+	}
+	while (bytesRead < length) {
+		unsigned short thisLen =
+		    min(SERIAL_MAX_TRANSFER_SIZE, length - bytesRead);
+		result =
+		    mpu_memory_read((struct i2c_adapter *) sl_handle,
+				    slaveAddr, memAddr + bytesRead,
+				    thisLen, &data[bytesRead]);
+		if (ML_SUCCESS != result)
+			return result;
+		bytesRead += thisLen;
+	}
+	return ML_SUCCESS;
+}
+
+
+/**
+ *  @brief  used to write multiple bytes of data to the fifo.
+ *          This should be sent by I2C.
+ *
+ *  @param  slaveAddr       I2C slave address of device.
+ *  @param  length          Length of burst of data.
+ *  @param  data            Pointer to block of data.
+ *
+ *  @return Zero if successful; an error code otherwise
+ */
+tMLError MLSLSerialWriteFifo(void *sl_handle,
+			     unsigned char slaveAddr,
+			     unsigned short length,
+			     unsigned char const *data)
+{
+	tMLError result;
+	unsigned char i2cWrite[SERIAL_MAX_TRANSFER_SIZE + 1];
+	unsigned short bytesWritten = 0;
+
+	if (length > FIFO_HW_SIZE) {
+		printk(KERN_ERR
+		       "maximum fifo write length is %d\n", FIFO_HW_SIZE);
+		return ML_ERROR_INVALID_PARAMETER;
+	}
+	while (bytesWritten < length) {
+		unsigned short thisLen =
+		    min(SERIAL_MAX_TRANSFER_SIZE, length - bytesWritten);
+		i2cWrite[0] = MPUREG_FIFO_R_W;
+		memcpy(&i2cWrite[1], &data[bytesWritten], thisLen);
+		result = sensor_i2c_write((struct i2c_adapter *) sl_handle,
+					  slaveAddr, thisLen + 1,
+					  i2cWrite);
+		if (ML_SUCCESS != result)
+			return result;
+		bytesWritten += thisLen;
+	}
+	return ML_SUCCESS;
+}
+
+
+/**
+ *  @brief  used to read multiple bytes of data from the fifo.
+ *          This should be sent by I2C.
+ *
+ *  @param  slaveAddr       I2C slave address of device.
+ *  @param  length          Length of burst of data.
+ *  @param  data            Pointer to block of data.
+ *
+ *  @return Zero if successful; an error code otherwise
+ */
+tMLError MLSLSerialReadFifo(void *sl_handle,
+			    unsigned char slaveAddr,
+			    unsigned short length, unsigned char *data)
+{
+	tMLError result;
+	unsigned short bytesRead = 0;
+
+	if (length > FIFO_HW_SIZE) {
+		printk(KERN_ERR
+		       "maximum fifo read length is %d\n", FIFO_HW_SIZE);
+		return ML_ERROR_INVALID_PARAMETER;
+	}
+	while (bytesRead < length) {
+		unsigned short thisLen =
+		    min(SERIAL_MAX_TRANSFER_SIZE, length - bytesRead);
+		result =
+		    sensor_i2c_read((struct i2c_adapter *) sl_handle,
+				    slaveAddr, MPUREG_FIFO_R_W, thisLen,
+				    &data[bytesRead]);
+		if (ML_SUCCESS != result)
+			return result;
+		bytesRead += thisLen;
+	}
+
+	return ML_SUCCESS;
+}
+
+/**
+ *  @}
+ */
diff --git a/drivers/misc/mpu3050/mlsl.h b/drivers/misc/mpu3050/mlsl.h
new file mode 100644
index 000000000000..76f69c77ba98
--- /dev/null
+++ b/drivers/misc/mpu3050/mlsl.h
@@ -0,0 +1,103 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+#ifndef __MSSL_H__
+#define __MSSL_H__
+
+#include "mltypes.h"
+#include "mpu.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ------------ */
+/* - Defines. - */
+/* ------------ */
+
+/*
+ * NOTE : to properly support Yamaha compass reads,
+ * the max transfer size should be at least 9 B.
+ * Length in bytes, typically a power of 2 >= 2
+ */
+#define SERIAL_MAX_TRANSFER_SIZE 128
+
+/* ---------------------- */
+/* - Types definitions. - */
+/* ---------------------- */
+
+/* --------------------- */
+/* - Function p-types. - */
+/* --------------------- */
+
+	tMLError MLSLSerialOpen(char const *port,
+				void **sl_handle);
+	tMLError MLSLSerialReset(void *sl_handle);
+	tMLError MLSLSerialClose(void *sl_handle);
+
+	tMLError MLSLSerialWriteSingle(void *sl_handle,
+				       unsigned char slaveAddr,
+				       unsigned char registerAddr,
+				       unsigned char data);
+
+	tMLError MLSLSerialRead(void *sl_handle,
+				unsigned char slaveAddr,
+				unsigned char registerAddr,
+				unsigned short length,
+				unsigned char *data);
+
+	tMLError MLSLSerialWrite(void *sl_handle,
+				 unsigned char slaveAddr,
+				 unsigned short length,
+				 unsigned char const *data);
+
+	tMLError MLSLSerialReadMem(void *sl_handle,
+				   unsigned char slaveAddr,
+				   unsigned short memAddr,
+				   unsigned short length,
+				   unsigned char *data);
+
+	tMLError MLSLSerialWriteMem(void *sl_handle,
+				    unsigned char slaveAddr,
+				    unsigned short memAddr,
+				    unsigned short length,
+				    unsigned char const *data);
+
+	tMLError MLSLSerialReadFifo(void *sl_handle,
+				    unsigned char slaveAddr,
+				    unsigned short length,
+				    unsigned char *data);
+
+	tMLError MLSLSerialWriteFifo(void *sl_handle,
+				     unsigned char slaveAddr,
+				     unsigned short length,
+				     unsigned char const *data);
+
+	tMLError MLSLWriteCal(unsigned char *cal, unsigned int len);
+	tMLError MLSLReadCal(unsigned char *cal, unsigned int len);
+	tMLError MLSLGetCalLength(unsigned int *len);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+#endif				/* MLSL_H */
diff --git a/drivers/misc/mpu3050/mltypes.h b/drivers/misc/mpu3050/mltypes.h
new file mode 100644
index 000000000000..447e208ee0a5
--- /dev/null
+++ b/drivers/misc/mpu3050/mltypes.h
@@ -0,0 +1,223 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+/******************************************************************************
+ *
+ * $Id: mltypes.h 4436 2011-01-13 05:07:53Z mcaramello $
+ * 
+ *****************************************************************************/
+
+/**
+ *  @defgroup MLERROR
+ *  @brief  Motion Library - Error definitions.
+ *          Definition of the error codes used within the MPL and returned
+ *          to the user.
+ *          Every function tries to return a meaningful error code basing
+ *          on the occuring error condition. The error code is numeric.
+ *
+ *          The available error codes and their associated values are:
+ *          - (0)       ML_SUCCESS
+ *          - (1)       ML_ERROR
+ *          - (2)       ML_ERROR_INVALID_PARAMETER
+ *          - (3)       ML_ERROR_FEATURE_NOT_ENABLED
+ *          - (4)       ML_ERROR_FEATURE_NOT_IMPLEMENTED
+ *          - (6)       ML_ERROR_DMP_NOT_STARTED
+ *          - (7)       ML_ERROR_DMP_STARTED
+ *          - (8)       ML_ERROR_NOT_OPENED
+ *          - (9)       ML_ERROR_OPENED
+ *          - (10)      ML_ERROR_INVALID_MODULE
+ *          - (11)      ML_ERROR_MEMORY_EXAUSTED
+ *          - (12)      ML_ERROR_DIVIDE_BY_ZERO
+ *          - (13)      ML_ERROR_ASSERTION_FAILURE
+ *          - (14)      ML_ERROR_FILE_OPEN
+ *          - (15)      ML_ERROR_FILE_READ
+ *          - (16)      ML_ERROR_FILE_WRITE
+ *          - (20)      ML_ERROR_SERIAL_CLOSED
+ *          - (21)      ML_ERROR_SERIAL_OPEN_ERROR
+ *          - (22)      ML_ERROR_SERIAL_READ
+ *          - (23)      ML_ERROR_SERIAL_WRITE
+ *          - (24)      ML_ERROR_SERIAL_DEVICE_NOT_RECOGNIZED
+ *          - (25)      ML_ERROR_SM_TRANSITION
+ *          - (26)      ML_ERROR_SM_IMPROPER_STATE
+ *          - (30)      ML_ERROR_FIFO_OVERFLOW
+ *          - (31)      ML_ERROR_FIFO_FOOTER
+ *          - (32)      ML_ERROR_FIFO_READ_COUNT
+ *          - (33)      ML_ERROR_FIFO_READ_DATA
+ *          - (40)      ML_ERROR_MEMORY_SET
+ *          - (50)      ML_ERROR_LOG_MEMORY_ERROR
+ *          - (51)      ML_ERROR_LOG_OUTPUT_ERROR
+ *          - (60)      ML_ERROR_OS_BAD_PTR
+ *          - (61)      ML_ERROR_OS_BAD_HANDLE
+ *          - (62)      ML_ERROR_OS_CREATE_FAILED
+ *          - (63)      ML_ERROR_OS_LOCK_FAILED
+ *          - (70)      ML_ERROR_COMPASS_DATA_OVERFLOW
+ *          - (71)      ML_ERROR_COMPASS_DATA_UNDERFLOW
+ *          - (72)      ML_ERROR_COMPASS_DATA_NOT_READY
+ *          - (75)      ML_ERROR_CALIBRATION_LOAD
+ *          - (76)      ML_ERROR_CALIBRATION_STORE
+ *          - (77)      ML_ERROR_CALIBRATION_LEN
+ *          - (78)      ML_ERROR_CALIBRATION_CHECKSUM
+ *
+ *  @{
+ *      @file mltypes.h
+ *  @}
+ */
+
+#ifndef MLTYPES_H
+#define MLTYPES_H
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include "stdint_invensense.h"
+#endif
+#include "log.h"
+
+/*---------------------------
+    ML Types
+---------------------------*/
+
+/**
+ * @struct tMLError The MPL Error Code return type.
+ *
+ * @code
+ *      typedef unsigned char tMLError;
+ * @endcode
+ */
+typedef unsigned char tMLError;
+
+#if defined(LINUX) || defined(__KERNEL__)
+typedef unsigned int HANDLE;
+#endif
+
+#ifdef __KERNEL__
+typedef HANDLE FILE;
+#endif
+
+#ifndef __cplusplus
+#ifndef __KERNEL__
+typedef int_fast8_t bool;
+#endif
+#endif
+
+/*---------------------------
+    ML Defines
+---------------------------*/
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+/* Dimension of an array */
+#ifndef DIM
+#define DIM(array) (sizeof(array)/sizeof((array)[0]))
+#endif
+
+/* - ML Errors. - */
+#define ERROR_NAME(x)   (#x)
+#define ERROR_CHECK(x)                                                  \
+	{								\
+		if (ML_SUCCESS != x) {					\
+			MPL_LOGE("%s|%s|%d returning %d\n",		\
+				__FILE__, __func__, __LINE__, x);	\
+			return x;					\
+		}							\
+	}
+
+#define ERROR_CHECK_FIRST(first, x)                                     \
+	{ if (ML_SUCCESS == first) first = x; }
+
+#define ML_SUCCESS                       (0)
+/* Generic Error code.  Proprietary Error Codes only */
+#define ML_ERROR                         (1)
+
+/* Compatibility and other generic error codes */
+#define ML_ERROR_INVALID_PARAMETER       (2)
+#define ML_ERROR_FEATURE_NOT_ENABLED     (3)
+#define ML_ERROR_FEATURE_NOT_IMPLEMENTED (4)
+#define ML_ERROR_DMP_NOT_STARTED         (6)
+#define ML_ERROR_DMP_STARTED             (7)
+#define ML_ERROR_NOT_OPENED              (8)
+#define ML_ERROR_OPENED                  (9)
+#define ML_ERROR_INVALID_MODULE         (10)
+#define ML_ERROR_MEMORY_EXAUSTED        (11)
+#define ML_ERROR_DIVIDE_BY_ZERO         (12)
+#define ML_ERROR_ASSERTION_FAILURE      (13)
+#define ML_ERROR_FILE_OPEN              (14)
+#define ML_ERROR_FILE_READ              (15)
+#define ML_ERROR_FILE_WRITE             (16)
+#define ML_ERROR_INVALID_CONFIGURATION  (17)
+
+/* Serial Communication */
+#define ML_ERROR_SERIAL_CLOSED          (20)
+#define ML_ERROR_SERIAL_OPEN_ERROR      (21)
+#define ML_ERROR_SERIAL_READ            (22)
+#define ML_ERROR_SERIAL_WRITE           (23)
+#define ML_ERROR_SERIAL_DEVICE_NOT_RECOGNIZED  (24)
+
+/* SM = State Machine */
+#define ML_ERROR_SM_TRANSITION          (25)
+#define ML_ERROR_SM_IMPROPER_STATE      (26)
+
+/* Fifo */
+#define ML_ERROR_FIFO_OVERFLOW          (30)
+#define ML_ERROR_FIFO_FOOTER            (31)
+#define ML_ERROR_FIFO_READ_COUNT        (32)
+#define ML_ERROR_FIFO_READ_DATA         (33)
+
+/* Memory & Registers, Set & Get */
+#define ML_ERROR_MEMORY_SET             (40)
+
+#define ML_ERROR_LOG_MEMORY_ERROR       (50)
+#define ML_ERROR_LOG_OUTPUT_ERROR       (51)
+
+/* OS interface errors */
+#define ML_ERROR_OS_BAD_PTR             (60)
+#define ML_ERROR_OS_BAD_HANDLE          (61)
+#define ML_ERROR_OS_CREATE_FAILED       (62)
+#define ML_ERROR_OS_LOCK_FAILED         (63)
+
+/* Compass errors */
+#define ML_ERROR_COMPASS_DATA_OVERFLOW  (70)
+#define ML_ERROR_COMPASS_DATA_UNDERFLOW (71)
+#define ML_ERROR_COMPASS_DATA_NOT_READY (72)
+
+/* Load/Store calibration */
+#define ML_ERROR_CALIBRATION_LOAD       (75)
+#define ML_ERROR_CALIBRATION_STORE      (76)
+#define ML_ERROR_CALIBRATION_LEN        (77)
+#define ML_ERROR_CALIBRATION_CHECKSUM   (78)
+
+/* For Linux coding compliance */
+#ifndef __KERNEL__
+#define EXPORT_SYMBOL(x) 
+#endif
+
+/*---------------------------
+    p-Types
+---------------------------*/
+
+#endif				/* MLTYPES_H */
diff --git a/drivers/misc/mpu3050/mpu-dev.c b/drivers/misc/mpu3050/mpu-dev.c
new file mode 100644
index 000000000000..6cde9eeccced
--- /dev/null
+++ b/drivers/misc/mpu3050/mpu-dev.c
@@ -0,0 +1,1172 @@
+/*
+    mpu-dev.c - mpu3050 char device interface
+
+    Copyright (C) 1995-97 Simon G. Vogl
+    Copyright (C) 1998-99 Frodo Looijaard <frodol@dds.nl>
+    Copyright (C) 2003 Greg Kroah-Hartman <greg@kroah.com>
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+/* Code inside mpudev_ioctl_rdrw is copied from i2c-dev.c
+ */
+#include <linux/i2c.h>
+#include <linux/i2c-dev.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/stat.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/signal.h>
+#include <linux/miscdevice.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+#include <linux/pm.h>
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+#include <linux/earlysuspend.h>
+#endif
+
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+#include "mpuirq.h"
+#include "slaveirq.h"
+#include "mlsl.h"
+#include "mpu-i2c.h"
+#include "mldl_cfg.h"
+#include "mpu.h"
+
+#define MPU3050_EARLY_SUSPEND_IN_DRIVER 0
+
+/* Platform data for the MPU */
+struct mpu_private_data {
+	struct mldl_cfg mldl_cfg;
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	struct early_suspend early_suspend;
+#endif
+};
+
+static int pid;
+
+static struct i2c_client *this_client;
+
+static int mpu_open(struct inode *inode, struct file *file)
+{
+	dev_dbg(&this_client->adapter->dev, "mpu_open\n");
+	dev_dbg(&this_client->adapter->dev, "current->pid %d\n",
+		current->pid);
+	pid = current->pid;
+	file->private_data = this_client;
+	/* we could do some checking on the flags supplied by "open" */
+	/* i.e. O_NONBLOCK */
+	/* -> set some flag to disable interruptible_sleep_on in mpu_read */
+	return 0;
+}
+
+/* close function - called when the "file" /dev/mpu is closed in userspace   */
+static int mpu_release(struct inode *inode, struct file *file)
+{
+	struct i2c_client *client =
+	    (struct i2c_client *) file->private_data;
+	struct mpu_private_data *mpu =
+	    (struct mpu_private_data *) i2c_get_clientdata(client);
+	struct mldl_cfg *mldl_cfg = &mpu->mldl_cfg;
+	int result = 0;
+
+	pid = 0;
+
+	if (!mldl_cfg->is_suspended) {
+		struct i2c_adapter *accel_adapter;
+		struct i2c_adapter *compass_adapter;
+		struct i2c_adapter *pressure_adapter;
+		accel_adapter =
+		    i2c_get_adapter(mldl_cfg->pdata->accel.adapt_num);
+		compass_adapter =
+		    i2c_get_adapter(mldl_cfg->pdata->compass.adapt_num);
+		pressure_adapter =
+		    i2c_get_adapter(mldl_cfg->pdata->pressure.adapt_num);
+		result =
+		    mpu3050_suspend(mldl_cfg, client->adapter,
+				    accel_adapter, compass_adapter,
+				    pressure_adapter,
+				    TRUE, TRUE, TRUE);
+	}
+
+	dev_dbg(&this_client->adapter->dev, "mpu_release\n");
+	return result;
+}
+
+static noinline int mpudev_ioctl_rdrw(struct i2c_client *client,
+				      unsigned long arg)
+{
+	struct i2c_rdwr_ioctl_data rdwr_arg;
+	struct i2c_msg *rdwr_pa;
+	u8 __user **data_ptrs;
+	int i, res;
+
+	if (copy_from_user(&rdwr_arg,
+			   (struct i2c_rdwr_ioctl_data __user *) arg,
+			   sizeof(rdwr_arg)))
+		return -EFAULT;
+
+	/* Put an arbitrary limit on the number of messages that can
+	 * be sent at once */
+	if (rdwr_arg.nmsgs > I2C_RDRW_IOCTL_MAX_MSGS)
+		return -EINVAL;
+
+	rdwr_pa = (struct i2c_msg *)
+	    kmalloc(rdwr_arg.nmsgs * sizeof(struct i2c_msg), GFP_KERNEL);
+	if (!rdwr_pa)
+		return -ENOMEM;
+
+	if (copy_from_user(rdwr_pa, rdwr_arg.msgs,
+			   rdwr_arg.nmsgs * sizeof(struct i2c_msg))) {
+		kfree(rdwr_pa);
+		return -EFAULT;
+	}
+
+	data_ptrs =
+	    kmalloc(rdwr_arg.nmsgs * sizeof(u8 __user *), GFP_KERNEL);
+	if (data_ptrs == NULL) {
+		kfree(rdwr_pa);
+		return -ENOMEM;
+	}
+
+	res = 0;
+	for (i = 0; i < rdwr_arg.nmsgs; i++) {
+		/* Limit the size of the message to a sane amount;
+		 * and don't let length change either. */
+		if ((rdwr_pa[i].len > 8192) ||
+		    (rdwr_pa[i].flags & I2C_M_RECV_LEN)) {
+			res = -EINVAL;
+			break;
+		}
+		data_ptrs[i] = (u8 __user *) rdwr_pa[i].buf;
+		rdwr_pa[i].buf = kmalloc(rdwr_pa[i].len, GFP_KERNEL);
+		if (rdwr_pa[i].buf == NULL) {
+			res = -ENOMEM;
+			break;
+		}
+		if (copy_from_user(rdwr_pa[i].buf, data_ptrs[i],
+				   rdwr_pa[i].len)) {
+			++i;	/* Needs to be kfreed too */
+			res = -EFAULT;
+			break;
+		}
+	}
+	if (res < 0) {
+		int j;
+		for (j = 0; j < i; ++j)
+			kfree(rdwr_pa[j].buf);
+		kfree(data_ptrs);
+		kfree(rdwr_pa);
+		return res;
+	}
+
+	res = i2c_transfer(client->adapter, rdwr_pa, rdwr_arg.nmsgs);
+	while (i-- > 0) {
+		if (res >= 0 && (rdwr_pa[i].flags & I2C_M_RD)) {
+			if (copy_to_user(data_ptrs[i], rdwr_pa[i].buf,
+					 rdwr_pa[i].len))
+				res = -EFAULT;
+		}
+		kfree(rdwr_pa[i].buf);
+	}
+	kfree(data_ptrs);
+	kfree(rdwr_pa);
+	return res;
+}
+
+/* read function called when from /dev/mpu is read.  Read from the FIFO */
+static ssize_t mpu_read(struct file *file,
+			char __user *buf, size_t count, loff_t *offset)
+{
+	char *tmp;
+	int ret;
+
+	struct i2c_client *client =
+	    (struct i2c_client *) file->private_data;
+
+	if (count > 8192)
+		count = 8192;
+
+	tmp = kmalloc(count, GFP_KERNEL);
+	if (tmp == NULL)
+		return -ENOMEM;
+
+	pr_debug("i2c-dev: i2c-%d reading %zu bytes.\n",
+		 iminor(file->f_path.dentry->d_inode), count);
+
+/* @todo fix this to do a i2c trasnfer from the FIFO */
+	ret = i2c_master_recv(client, tmp, count);
+	if (ret >= 0)
+		ret = copy_to_user(buf, tmp, count) ? -EFAULT : ret;
+	kfree(tmp);
+	return ret;
+}
+
+static int
+mpu_ioctl_set_mpu_pdata(struct i2c_client *client, unsigned long arg)
+{
+	int ii;
+	int result;
+	struct mpu_private_data *mpu =
+	    (struct mpu_private_data *) i2c_get_clientdata(client);
+	struct mpu3050_platform_data *pdata = mpu->mldl_cfg.pdata;
+	struct mpu3050_platform_data local_pdata;
+
+	result = copy_from_user(&local_pdata,
+				(unsigned char *) arg,
+				sizeof(local_pdata));
+
+	pdata->int_config = local_pdata.int_config;
+	for (ii = 0; ii < DIM(pdata->orientation); ii++)
+		pdata->orientation[ii] = local_pdata.orientation[ii];
+	pdata->level_shifter = local_pdata.level_shifter;
+
+	pdata->accel.address = local_pdata.accel.address;
+	for (ii = 0; ii < DIM(pdata->accel.orientation); ii++)
+		pdata->accel.orientation[ii] =
+			local_pdata.accel.orientation[ii];
+
+	pdata->compass.address = local_pdata.compass.address;
+	for (ii = 0; ii < DIM(pdata->compass.orientation); ii++)
+		pdata->compass.orientation[ii] =
+			local_pdata.compass.orientation[ii];
+
+	pdata->pressure.address = local_pdata.pressure.address;
+	for (ii = 0; ii < DIM(pdata->pressure.orientation); ii++)
+		pdata->pressure.orientation[ii] =
+			local_pdata.pressure.orientation[ii];
+
+	dev_dbg(&client->adapter->dev, "%s\n", __func__);
+
+	return result;
+}
+
+static int
+mpu_ioctl_set_mpu_config(struct i2c_client *client, unsigned long arg)
+{
+	struct mpu_private_data *mpu =
+	    (struct mpu_private_data *) i2c_get_clientdata(client);
+	struct mldl_cfg *mldl_cfg = &mpu->mldl_cfg;
+
+	dev_dbg(&this_client->adapter->dev, "%s\n", __func__);
+
+	/*
+	 * User space is not allowed to modify accel compass pressure or
+	 * pdata structs, as well as silicon_revision product_id or trim
+	 */
+	if (copy_from_user(mldl_cfg, (struct mldl_cfg *) arg,
+			   offsetof(struct mldl_cfg, silicon_revision)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int
+mpu_ioctl_get_mpu_config(struct i2c_client *client, unsigned long arg)
+{
+	/* Have to be careful as there are 3 pointers in the mldl_cfg
+	 * structure */
+	struct mpu_private_data *mpu =
+	    (struct mpu_private_data *) i2c_get_clientdata(client);
+	struct mldl_cfg *mldl_cfg = &mpu->mldl_cfg;
+	struct mldl_cfg *local_mldl_cfg;
+	int retval = 0;
+
+	local_mldl_cfg = kzalloc(sizeof(struct mldl_cfg), GFP_KERNEL);
+	if (NULL == local_mldl_cfg)
+		return -ENOMEM;
+
+	retval =
+	    copy_from_user(local_mldl_cfg, (void *) arg,
+			   sizeof(struct mldl_cfg));
+	if (retval)
+		goto out;
+
+	/* Fill in the accel, compass, pressure and pdata pointers */
+	if (mldl_cfg->accel) {
+		retval = copy_to_user(local_mldl_cfg->accel,
+				      mldl_cfg->accel,
+				      sizeof(*mldl_cfg->accel));
+		if (retval)
+			goto out;
+	}
+
+	if (mldl_cfg->compass) {
+		retval = copy_to_user(local_mldl_cfg->compass,
+				      mldl_cfg->compass,
+				      sizeof(*mldl_cfg->compass));
+		if (retval)
+			goto out;
+	}
+
+	if (mldl_cfg->pressure) {
+		retval = copy_to_user(local_mldl_cfg->pressure,
+				      mldl_cfg->pressure,
+				      sizeof(*mldl_cfg->pressure));
+		if (retval)
+			goto out;
+	}
+
+	if (mldl_cfg->pdata) {
+		retval = copy_to_user(local_mldl_cfg->pdata,
+				      mldl_cfg->pdata,
+				      sizeof(*mldl_cfg->pdata));
+		if (retval)
+			goto out;
+	}
+
+	/* Do not modify the accel, compass, pressure and pdata pointers */
+	retval = copy_to_user((struct mldl_cfg *) arg,
+			      mldl_cfg, offsetof(struct mldl_cfg, accel));
+
+out:
+	kfree(local_mldl_cfg);
+	return retval;
+}
+
+/* ioctl - I/O control */
+static long mpu_ioctl(struct file *file,
+		      unsigned int cmd, unsigned long arg)
+{
+	struct i2c_client *client =
+	    (struct i2c_client *) file->private_data;
+	struct mpu_private_data *mpu =
+	    (struct mpu_private_data *) i2c_get_clientdata(client);
+	struct mldl_cfg *mldl_cfg = &mpu->mldl_cfg;
+	int retval = 0;
+	struct i2c_adapter *accel_adapter;
+	struct i2c_adapter *compass_adapter;
+	struct i2c_adapter *pressure_adapter;
+
+	accel_adapter = i2c_get_adapter(mldl_cfg->pdata->accel.adapt_num);
+	compass_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->compass.adapt_num);
+	pressure_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->pressure.adapt_num);
+
+	switch (cmd) {
+	case I2C_RDWR:
+		mpudev_ioctl_rdrw(client, arg);
+		break;
+	case I2C_SLAVE:
+		if ((arg & 0x7E) != (client->addr & 0x7E)) {
+			dev_err(&this_client->adapter->dev,
+				"%s: Invalid I2C_SLAVE arg %lu\n",
+				__func__, arg);
+		}
+		break;
+	case MPU_SET_MPU_CONFIG:
+		retval = mpu_ioctl_set_mpu_config(client, arg);
+		break;
+	case MPU_SET_INT_CONFIG:
+		mldl_cfg->int_config = (unsigned char) arg;
+		break;
+	case MPU_SET_EXT_SYNC:
+		mldl_cfg->ext_sync = (enum mpu_ext_sync) arg;
+		break;
+	case MPU_SET_FULL_SCALE:
+		mldl_cfg->full_scale = (enum mpu_fullscale) arg;
+		break;
+	case MPU_SET_LPF:
+		mldl_cfg->lpf = (enum mpu_filter) arg;
+		break;
+	case MPU_SET_CLK_SRC:
+		mldl_cfg->clk_src = (enum mpu_clock_sel) arg;
+		break;
+	case MPU_SET_DIVIDER:
+		mldl_cfg->divider = (unsigned char) arg;
+		break;
+	case MPU_SET_LEVEL_SHIFTER:
+		mldl_cfg->pdata->level_shifter = (unsigned char) arg;
+		break;
+	case MPU_SET_DMP_ENABLE:
+		mldl_cfg->dmp_enable = (unsigned char) arg;
+		break;
+	case MPU_SET_FIFO_ENABLE:
+		mldl_cfg->fifo_enable = (unsigned char) arg;
+		break;
+	case MPU_SET_DMP_CFG1:
+		mldl_cfg->dmp_cfg1 = (unsigned char) arg;
+		break;
+	case MPU_SET_DMP_CFG2:
+		mldl_cfg->dmp_cfg2 = (unsigned char) arg;
+		break;
+	case MPU_SET_OFFSET_TC:
+		retval = copy_from_user(mldl_cfg->offset_tc,
+					(unsigned char *) arg,
+					sizeof(mldl_cfg->offset_tc));
+		break;
+	case MPU_SET_RAM:
+		retval = copy_from_user(mldl_cfg->ram,
+					(unsigned char *) arg,
+					sizeof(mldl_cfg->ram));
+		break;
+	case MPU_SET_PLATFORM_DATA:
+		retval = mpu_ioctl_set_mpu_pdata(client, arg);
+		break;
+	case MPU_GET_MPU_CONFIG:
+		retval = mpu_ioctl_get_mpu_config(client, arg);
+		break;
+	case MPU_GET_INT_CONFIG:
+		mldl_cfg->int_config = (unsigned char) arg;
+		break;
+	case MPU_GET_EXT_SYNC:
+		mldl_cfg->ext_sync = (enum mpu_ext_sync) arg;
+		break;
+	case MPU_GET_FULL_SCALE:
+		mldl_cfg->full_scale = (enum mpu_fullscale) arg;
+		break;
+	case MPU_GET_LPF:
+		mldl_cfg->lpf = (enum mpu_filter) arg;
+		break;
+	case MPU_GET_CLK_SRC:
+		mldl_cfg->clk_src = (enum mpu_clock_sel) arg;
+		break;
+	case MPU_GET_DIVIDER:
+		mldl_cfg->divider = (unsigned char) arg;
+		break;
+	case MPU_GET_LEVEL_SHIFTER:
+		mldl_cfg->pdata->level_shifter = (unsigned char) arg;
+		break;
+	case MPU_GET_DMP_ENABLE:
+		mldl_cfg->dmp_enable = (unsigned char) arg;
+		break;
+	case MPU_GET_FIFO_ENABLE:
+		mldl_cfg->fifo_enable = (unsigned char) arg;
+		break;
+	case MPU_GET_DMP_CFG1:
+		mldl_cfg->dmp_cfg1 = (unsigned char) arg;
+		break;
+	case MPU_GET_DMP_CFG2:
+		mldl_cfg->dmp_cfg2 = (unsigned char) arg;
+		break;
+	case MPU_GET_OFFSET_TC:
+		retval = copy_to_user((unsigned char *) arg,
+				      mldl_cfg->offset_tc,
+				      sizeof(mldl_cfg->offset_tc));
+		break;
+	case MPU_GET_RAM:
+		retval = copy_to_user((unsigned char *) arg,
+				      mldl_cfg->ram,
+				      sizeof(mldl_cfg->ram));
+		break;
+	case MPU_CONFIG_ACCEL:
+	{
+		if ((mldl_cfg->accel) && (mldl_cfg->accel->config)) {
+			struct ext_slave_config config;
+			retval = copy_from_user(
+				&config,
+				(struct ext_slave_config *)arg,
+				sizeof(config));
+			if (retval)
+				break;
+
+			if (config.len && config.data) {
+				int *data;
+				data = kzalloc(config.len, GFP_KERNEL);
+				if (!data) {
+					retval = ML_ERROR_MEMORY_EXAUSTED;
+					break;
+				}
+				retval = copy_from_user(data,
+							(void *)config.data,
+							config.len);
+				if (retval) {
+					kfree(data);
+					break;
+				}
+				config.data = data;
+			}
+			retval = mldl_cfg->accel->config(
+				accel_adapter,
+				mldl_cfg->accel,
+				&mldl_cfg->pdata->accel,
+				&config);
+			kfree(config.data);
+		}
+		break;
+	}
+	case MPU_CONFIG_COMPASS:
+	{
+		if ((mldl_cfg->compass) && (mldl_cfg->compass->config)) {
+			struct ext_slave_config config;
+			retval = copy_from_user(
+				&config,
+				(struct ext_slave_config *)arg,
+				sizeof(config));
+			if (retval)
+				break;
+
+			if (config.len && config.data) {
+				int *data;
+				data = kzalloc(config.len, GFP_KERNEL);
+				if (!data) {
+					retval = ML_ERROR_MEMORY_EXAUSTED;
+					break;
+				}
+				retval = copy_from_user(data,
+							(void *)config.data,
+							config.len);
+				if (retval) {
+					kfree(data);
+					break;
+				}
+				config.data = data;
+			}
+			retval = mldl_cfg->compass->config(
+				compass_adapter,
+				mldl_cfg->compass,
+				&mldl_cfg->pdata->compass,
+				&config);
+			kfree(config.data);
+		}
+		break;
+	}
+	case MPU_CONFIG_PRESSURE:
+	{
+		if ((mldl_cfg->pressure) && (mldl_cfg->pressure->config)) {
+			struct ext_slave_config config;
+			retval = copy_from_user(
+				&config,
+				(struct ext_slave_config *)arg,
+				sizeof(config));
+			if (retval)
+				break;
+
+			if (config.len && config.data) {
+				int *data;
+				data = kzalloc(config.len, GFP_KERNEL);
+				if (!data) {
+					retval = ML_ERROR_MEMORY_EXAUSTED;
+					break;
+				}
+				retval = copy_from_user(data,
+							(void *)config.data,
+							config.len);
+				if (retval) {
+					kfree(data);
+					break;
+				}
+				config.data = data;
+			}
+			retval = mldl_cfg->pressure->config(
+				pressure_adapter,
+				mldl_cfg->pressure,
+				&mldl_cfg->pdata->pressure,
+				&config);
+			kfree(config.data);
+		}
+		break;
+	}
+	case MPU_READ_MEMORY:
+	case MPU_WRITE_MEMORY:
+	case MPU_SUSPEND:
+		{
+			struct mpu_suspend_resume suspend;
+			retval =
+			    copy_from_user(&suspend,
+					   (struct mpu_suspend_resume *)
+					   arg, sizeof(suspend));
+			if (retval)
+				break;
+			if (suspend.gyro) {
+				retval =
+				    mpu3050_suspend(mldl_cfg,
+						    client->adapter,
+						    accel_adapter,
+						    compass_adapter,
+						    pressure_adapter,
+						    suspend.accel,
+						    suspend.compass,
+						    suspend.pressure);
+			} else {
+				/* Cannot suspend the pressure compass or
+				 * accel while the MPU is running */
+				retval = ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+			}
+		}
+		break;
+	case MPU_RESUME:
+		{
+			struct mpu_suspend_resume resume;
+			retval =
+			    copy_from_user(&resume,
+					   (struct mpu_suspend_resume *)
+					   arg, sizeof(resume));
+			if (retval)
+				break;
+			if (resume.gyro) {
+				retval =
+				    mpu3050_resume(mldl_cfg,
+						   client->adapter,
+						   accel_adapter,
+						   compass_adapter,
+						   pressure_adapter,
+						   resume.accel,
+						   resume.compass,
+						   resume.pressure);
+			} else if (mldl_cfg->is_suspended) {
+				if (resume.accel) {
+					retval =
+					    mldl_cfg->
+					    accel->resume(accel_adapter,
+							  mldl_cfg->accel,
+							  &mldl_cfg->
+							  pdata->accel);
+					if (retval)
+						break;
+				}
+
+				if (resume.compass) {
+					retval =
+					    mldl_cfg->
+					    compass->resume
+					    (compass_adapter,
+					     mldl_cfg->compass,
+					     &mldl_cfg->pdata->compass);
+					if (retval)
+						break;
+				}
+
+				if (resume.pressure)
+					retval =
+					    mldl_cfg->
+					    pressure->resume
+					    (pressure_adapter,
+					     mldl_cfg->pressure,
+					     &mldl_cfg->pdata->pressure);
+			} else {
+				/* Cannot resume the pressure compass or
+				 * accel while the MPU is running */
+				retval = ML_ERROR_FEATURE_NOT_IMPLEMENTED;
+			}
+		}
+		break;
+	case MPU_READ_ACCEL:
+		{
+			unsigned char data[6];
+			retval =
+			    mpu3050_read_accel(mldl_cfg, client->adapter,
+					       data);
+			if (ML_SUCCESS == retval)
+				retval =
+				    copy_to_user((unsigned char *) arg,
+						 data, sizeof(data));
+		}
+		break;
+	case MPU_READ_COMPASS:
+		{
+			unsigned char data[6];
+			struct i2c_adapter *compass_adapt =
+			    i2c_get_adapter(mldl_cfg->pdata->compass.
+					    adapt_num);
+			retval =
+			    mpu3050_read_compass(mldl_cfg, compass_adapt,
+						 data);
+			if (ML_SUCCESS == retval)
+				retval =
+				    copy_to_user((unsigned char *) arg,
+						 data, sizeof(data));
+		}
+		break;
+	case MPU_READ_PRESSURE:
+		{
+			unsigned char data[3];
+			struct i2c_adapter *pressure_adapt =
+			    i2c_get_adapter(mldl_cfg->pdata->pressure.
+					    adapt_num);
+			retval =
+			    mpu3050_read_pressure(mldl_cfg, pressure_adapt,
+						 data);
+			if (ML_SUCCESS == retval)
+				retval =
+				    copy_to_user((unsigned char *) arg,
+						 data, sizeof(data));
+		}
+		break;
+	default:
+		dev_err(&this_client->adapter->dev,
+			"%s: Unknown cmd %d, arg %lu\n", __func__, cmd,
+			arg);
+		retval = -EINVAL;
+	}
+
+	return retval;
+}
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+void mpu3050_early_suspend(struct early_suspend *h)
+{
+	struct mpu_private_data *mpu = container_of(h,
+						    struct
+						    mpu_private_data,
+						    early_suspend);
+	struct mldl_cfg *mldl_cfg = &mpu->mldl_cfg;
+	struct i2c_adapter *accel_adapter;
+	struct i2c_adapter *compass_adapter;
+	struct i2c_adapter *pressure_adapter;
+
+	accel_adapter = i2c_get_adapter(mldl_cfg->pdata->accel.adapt_num);
+	compass_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->compass.adapt_num);
+	pressure_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->pressure.adapt_num);
+
+	dev_dbg(&this_client->adapter->dev, "%s: %d, %d\n", __func__,
+		h->level, mpu->mldl_cfg.is_suspended);
+	if (MPU3050_EARLY_SUSPEND_IN_DRIVER)
+		(void) mpu3050_suspend(mldl_cfg, this_client->adapter,
+				       accel_adapter, compass_adapter,
+				       pressure_adapter, TRUE, TRUE, TRUE);
+}
+
+void mpu3050_early_resume(struct early_suspend *h)
+{
+	struct mpu_private_data *mpu = container_of(h,
+						    struct
+						    mpu_private_data,
+						    early_suspend);
+	struct mldl_cfg *mldl_cfg = &mpu->mldl_cfg;
+	struct i2c_adapter *accel_adapter;
+	struct i2c_adapter *compass_adapter;
+	struct i2c_adapter *pressure_adapter;
+
+	accel_adapter = i2c_get_adapter(mldl_cfg->pdata->accel.adapt_num);
+	compass_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->compass.adapt_num);
+	pressure_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->pressure.adapt_num);
+
+	if (MPU3050_EARLY_SUSPEND_IN_DRIVER) {
+		if (pid) {
+			(void) mpu3050_resume(mldl_cfg,
+					      this_client->adapter,
+					      accel_adapter,
+					      compass_adapter,
+					      pressure_adapter,
+					      TRUE, TRUE, TRUE);
+			dev_dbg(&this_client->adapter->dev,
+				"%s for pid %d\n", __func__, pid);
+		}
+	}
+	dev_dbg(&this_client->adapter->dev, "%s: %d\n", __func__, h->level);
+}
+#endif
+
+void mpu_shutdown(struct i2c_client *client)
+{
+	struct mpu_private_data *mpu =
+	    (struct mpu_private_data *) i2c_get_clientdata(client);
+	struct mldl_cfg *mldl_cfg = &mpu->mldl_cfg;
+	struct i2c_adapter *accel_adapter;
+	struct i2c_adapter *compass_adapter;
+	struct i2c_adapter *pressure_adapter;
+
+	accel_adapter = i2c_get_adapter(mldl_cfg->pdata->accel.adapt_num);
+	compass_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->compass.adapt_num);
+	pressure_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->pressure.adapt_num);
+
+	(void) mpu3050_suspend(mldl_cfg, this_client->adapter,
+			       accel_adapter, compass_adapter, pressure_adapter,
+			       TRUE, TRUE, TRUE);
+	dev_dbg(&this_client->adapter->dev, "%s\n", __func__);
+}
+
+int mpu_suspend(struct i2c_client *client, pm_message_t mesg)
+{
+	struct mpu_private_data *mpu =
+	    (struct mpu_private_data *) i2c_get_clientdata(client);
+	struct mldl_cfg *mldl_cfg = &mpu->mldl_cfg;
+	struct i2c_adapter *accel_adapter;
+	struct i2c_adapter *compass_adapter;
+	struct i2c_adapter *pressure_adapter;
+
+	accel_adapter = i2c_get_adapter(mldl_cfg->pdata->accel.adapt_num);
+	compass_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->compass.adapt_num);
+	pressure_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->pressure.adapt_num);
+
+	if (!mpu->mldl_cfg.is_suspended) {
+		dev_dbg(&this_client->adapter->dev,
+			"%s: suspending on event %d\n", __func__,
+			mesg.event);
+		(void) mpu3050_suspend(mldl_cfg, this_client->adapter,
+				       accel_adapter, compass_adapter,
+				       pressure_adapter,
+				       TRUE, TRUE, TRUE);
+	} else {
+		dev_dbg(&this_client->adapter->dev,
+			"%s: Already suspended %d\n", __func__,
+			mesg.event);
+	}
+	return 0;
+}
+
+int mpu_resume(struct i2c_client *client)
+{
+	struct mpu_private_data *mpu =
+	    (struct mpu_private_data *) i2c_get_clientdata(client);
+	struct mldl_cfg *mldl_cfg = &mpu->mldl_cfg;
+	struct i2c_adapter *accel_adapter;
+	struct i2c_adapter *compass_adapter;
+	struct i2c_adapter *pressure_adapter;
+
+	accel_adapter = i2c_get_adapter(mldl_cfg->pdata->accel.adapt_num);
+	compass_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->compass.adapt_num);
+	pressure_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->pressure.adapt_num);
+
+	if (pid) {
+		(void) mpu3050_resume(mldl_cfg, this_client->adapter,
+				      accel_adapter,
+				      compass_adapter,
+				      pressure_adapter,
+				      TRUE, TRUE, TRUE);
+		dev_dbg(&this_client->adapter->dev,
+			"%s for pid %d\n", __func__, pid);
+	}
+	return 0;
+}
+
+/* define which file operations are supported */
+static const struct file_operations mpu_fops = {
+	.owner = THIS_MODULE,
+	.read = mpu_read,
+#if HAVE_COMPAT_IOCTL
+	.compat_ioctl = mpu_ioctl,
+#endif
+#if HAVE_UNLOCKED_IOCTL
+	.unlocked_ioctl = mpu_ioctl,
+#endif
+	.open = mpu_open,
+	.release = mpu_release,
+};
+
+static unsigned short normal_i2c[] = { I2C_CLIENT_END };
+
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 32)
+I2C_CLIENT_INSMOD;
+#endif
+
+static struct miscdevice i2c_mpu_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "mpu", /* Same for both 3050 and 6000 */
+	.fops = &mpu_fops,
+};
+
+
+int mpu3050_probe(struct i2c_client *client,
+		  const struct i2c_device_id *devid)
+{
+	struct mpu3050_platform_data *pdata;
+	struct mpu_private_data *mpu;
+	int res = 0;
+	struct i2c_adapter *accel_adapter = NULL;
+	struct i2c_adapter *compass_adapter = NULL;
+	struct i2c_adapter *pressure_adapter = NULL;
+
+	dev_dbg(&client->adapter->dev, "%s\n", __func__);
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+		res = -ENODEV;
+		goto out_check_functionality_failed;
+	}
+
+	mpu = kzalloc(sizeof(struct mpu_private_data), GFP_KERNEL);
+	if (!mpu) {
+		res = -ENOMEM;
+		goto out_alloc_data_failed;
+	}
+
+	i2c_set_clientdata(client, mpu);
+	this_client = client;
+
+	pdata = (struct mpu3050_platform_data *) client->dev.platform_data;
+	if (!pdata) {
+		dev_warn(&this_client->adapter->dev,
+			 "Warning no platform data for mpu3050\n");
+	} else {
+		mpu->mldl_cfg.pdata = pdata;
+
+#if defined(CONFIG_SENSORS_MPU3050_MODULE) || \
+    defined(CONFIG_SENSORS_MPU6000_MODULE)
+		pdata->accel.get_slave_descr = get_accel_slave_descr;
+		pdata->compass.get_slave_descr = get_compass_slave_descr;
+		pdata->pressure.get_slave_descr = get_pressure_slave_descr;
+#endif
+
+		if (pdata->accel.get_slave_descr) {
+			mpu->mldl_cfg.accel =
+			    pdata->accel.get_slave_descr();
+			dev_info(&this_client->adapter->dev,
+				 "%s: +%s\n", MPU_NAME,
+				 mpu->mldl_cfg.accel->name);
+			accel_adapter =
+				i2c_get_adapter(pdata->accel.adapt_num);
+			if (pdata->accel.irq > 0) {
+				dev_info(&this_client->adapter->dev,
+					"Installing Accel irq using %d\n",
+					pdata->accel.irq);
+				res = slaveirq_init(accel_adapter,
+						&pdata->accel,
+						"accelirq");
+				if (res)
+					goto out_accelirq_failed;
+			} else {
+				dev_warn(&this_client->adapter->dev,
+					"WARNING: Accel irq not assigned\n");
+			}
+		} else {
+			dev_warn(&this_client->adapter->dev,
+				 "%s: No Accel Present\n", MPU_NAME);
+		}
+
+		if (pdata->compass.get_slave_descr) {
+			mpu->mldl_cfg.compass =
+			    pdata->compass.get_slave_descr();
+			dev_info(&this_client->adapter->dev,
+				 "%s: +%s\n", MPU_NAME,
+				 mpu->mldl_cfg.compass->name);
+			compass_adapter =
+				i2c_get_adapter(pdata->compass.adapt_num);
+			if (pdata->compass.irq > 0) {
+				dev_info(&this_client->adapter->dev,
+					"Installing Compass irq using %d\n",
+					pdata->compass.irq);
+				res = slaveirq_init(compass_adapter,
+						&pdata->compass,
+						"compassirq");
+				if (res)
+					goto out_compassirq_failed;
+			} else {
+				dev_warn(&this_client->adapter->dev,
+					"WARNING: Compass irq not assigned\n");
+			}
+		} else {
+			dev_warn(&this_client->adapter->dev,
+				 "%s: No Compass Present\n", MPU_NAME);
+		}
+
+		if (pdata->pressure.get_slave_descr) {
+			mpu->mldl_cfg.pressure =
+			    pdata->pressure.get_slave_descr();
+			dev_info(&this_client->adapter->dev,
+				 "%s: +%s\n", MPU_NAME,
+				 mpu->mldl_cfg.pressure->name);
+			pressure_adapter =
+				i2c_get_adapter(pdata->pressure.adapt_num);
+
+			if (pdata->pressure.irq > 0) {
+				dev_info(&this_client->adapter->dev,
+					"Installing Pressure irq using %d\n",
+					pdata->pressure.irq);
+				res = slaveirq_init(pressure_adapter,
+						&pdata->pressure,
+						"pressureirq");
+				if (res)
+					goto out_pressureirq_failed;
+			} else {
+				dev_warn(&this_client->adapter->dev,
+					"WARNING: Pressure irq not assigned\n");
+			}
+		} else {
+			dev_warn(&this_client->adapter->dev,
+				 "%s: No Pressure Present\n", MPU_NAME);
+		}
+	}
+
+	mpu->mldl_cfg.addr = client->addr;
+	res = mpu3050_open(&mpu->mldl_cfg, client->adapter,
+			accel_adapter, compass_adapter, pressure_adapter);
+
+	if (res) {
+		dev_err(&this_client->adapter->dev,
+			"Unable to open %s %d\n", MPU_NAME, res);
+		res = -ENODEV;
+		goto out_whoami_failed;
+	}
+
+	res = misc_register(&i2c_mpu_device);
+	if (res < 0) {
+		dev_err(&this_client->adapter->dev,
+			"ERROR: misc_register returned %d\n", res);
+		goto out_misc_register_failed;
+	}
+
+	if (this_client->irq > 0) {
+		dev_info(&this_client->adapter->dev,
+			 "Installing irq using %d\n", this_client->irq);
+		res = mpuirq_init(this_client);
+		if (res)
+			goto out_mpuirq_failed;
+	} else {
+		dev_warn(&this_client->adapter->dev,
+			 "WARNING: %s irq not assigned\n", MPU_NAME);
+	}
+
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	mpu->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1;
+	mpu->early_suspend.suspend = mpu3050_early_suspend;
+	mpu->early_suspend.resume = mpu3050_early_resume;
+	register_early_suspend(&mpu->early_suspend);
+#endif
+	return res;
+
+out_mpuirq_failed:
+	misc_deregister(&i2c_mpu_device);
+out_misc_register_failed:
+	mpu3050_close(&mpu->mldl_cfg, client->adapter,
+		accel_adapter, compass_adapter, pressure_adapter);
+out_whoami_failed:
+	if (pdata &&
+	    pdata->pressure.get_slave_descr &&
+	    pdata->pressure.irq)
+		slaveirq_exit(&pdata->pressure);
+out_pressureirq_failed:
+	if (pdata &&
+	    pdata->compass.get_slave_descr &&
+	    pdata->compass.irq)
+		slaveirq_exit(&pdata->compass);
+out_compassirq_failed:
+	if (pdata &&
+	    pdata->accel.get_slave_descr &&
+	    pdata->accel.irq)
+		slaveirq_exit(&pdata->accel);
+out_accelirq_failed:
+	kfree(mpu);
+out_alloc_data_failed:
+out_check_functionality_failed:
+	dev_err(&this_client->adapter->dev, "%s failed %d\n", __func__,
+		res);
+	return res;
+
+}
+
+static int mpu3050_remove(struct i2c_client *client)
+{
+	struct mpu_private_data *mpu = i2c_get_clientdata(client);
+	struct i2c_adapter *accel_adapter;
+	struct i2c_adapter *compass_adapter;
+	struct i2c_adapter *pressure_adapter;
+	struct mldl_cfg *mldl_cfg = &mpu->mldl_cfg;
+	struct mpu3050_platform_data *pdata = mldl_cfg->pdata;
+
+	accel_adapter = i2c_get_adapter(mldl_cfg->pdata->accel.adapt_num);
+	compass_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->compass.adapt_num);
+	pressure_adapter =
+	    i2c_get_adapter(mldl_cfg->pdata->pressure.adapt_num);
+
+	dev_dbg(&client->adapter->dev, "%s\n", __func__);
+
+#ifdef CONFIG_HAS_EARLYSUSPEND
+	unregister_early_suspend(&mpu->early_suspend);
+#endif
+	mpu3050_close(mldl_cfg, client->adapter,
+		accel_adapter, compass_adapter, pressure_adapter);
+
+	if (client->irq)
+		mpuirq_exit();
+
+	if (pdata &&
+	    pdata->pressure.get_slave_descr &&
+	    pdata->pressure.irq)
+		slaveirq_exit(&pdata->pressure);
+
+	if (pdata &&
+	    pdata->compass.get_slave_descr &&
+	    pdata->compass.irq)
+		slaveirq_exit(&pdata->compass);
+
+	if (pdata &&
+	    pdata->accel.get_slave_descr &&
+	    pdata->accel.irq)
+		slaveirq_exit(&pdata->accel);
+
+	misc_deregister(&i2c_mpu_device);
+	kfree(mpu);
+
+	return 0;
+}
+
+static const struct i2c_device_id mpu3050_id[] = {
+	{MPU_NAME, 0},
+	{}
+};
+
+MODULE_DEVICE_TABLE(i2c, mpu3050_id);
+
+static struct i2c_driver mpu3050_driver = {
+	.class = I2C_CLASS_HWMON,
+	.probe = mpu3050_probe,
+	.remove = mpu3050_remove,
+	.id_table = mpu3050_id,
+	.driver = {
+		   .owner = THIS_MODULE,
+		   .name = MPU_NAME,
+		   },
+#if LINUX_VERSION_CODE <= KERNEL_VERSION(2, 6, 32)
+	.address_data = &addr_data,
+#else
+	.address_list = normal_i2c,
+#endif
+
+	.shutdown = mpu_shutdown,	/* optional */
+	.suspend = mpu_suspend,	/* optional */
+	.resume = mpu_resume,	/* optional */
+
+};
+
+static int __init mpu_init(void)
+{
+	int res = i2c_add_driver(&mpu3050_driver);
+	pid = 0;
+	printk(KERN_DEBUG "%s\n", __func__);
+	if (res)
+		dev_err(&this_client->adapter->dev, "%s failed\n",
+			__func__);
+	return res;
+}
+
+static void __exit mpu_exit(void)
+{
+	printk(KERN_DEBUG "%s\n", __func__);
+	i2c_del_driver(&mpu3050_driver);
+}
+
+module_init(mpu_init);
+module_exit(mpu_exit);
+
+MODULE_AUTHOR("Invensense Corporation");
+MODULE_DESCRIPTION("User space character device interface for MPU3050");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS(MPU_NAME);
diff --git a/drivers/misc/mpu3050/mpu-i2c.c b/drivers/misc/mpu3050/mpu-i2c.c
new file mode 100644
index 000000000000..b1298d313abf
--- /dev/null
+++ b/drivers/misc/mpu3050/mpu-i2c.c
@@ -0,0 +1,196 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+/**
+ *  @defgroup
+ *  @brief
+ *
+ *  @{
+ *      @file   mpu-i2c.c
+ *      @brief
+ *
+ */
+
+#include <linux/i2c.h>
+#include "mpu.h"
+
+int sensor_i2c_write(struct i2c_adapter *i2c_adap,
+		     unsigned char address,
+		     unsigned int len, unsigned char const *data)
+{
+	struct i2c_msg msgs[1];
+	int res;
+
+	if (NULL == data || NULL == i2c_adap)
+		return -EINVAL;
+
+	msgs[0].addr = address;
+	msgs[0].flags = 0;	/* write */
+	msgs[0].buf = (unsigned char *) data;
+	msgs[0].len = len;
+
+	res = i2c_transfer(i2c_adap, msgs, 1);
+	if (res < 1)
+		return res;
+	else
+		return 0;
+}
+
+int sensor_i2c_write_register(struct i2c_adapter *i2c_adap,
+			      unsigned char address,
+			      unsigned char reg, unsigned char value)
+{
+	unsigned char data[2];
+
+	data[0] = reg;
+	data[1] = value;
+	return sensor_i2c_write(i2c_adap, address, 2, data);
+}
+
+int sensor_i2c_read(struct i2c_adapter *i2c_adap,
+		    unsigned char address,
+		    unsigned char reg,
+		    unsigned int len, unsigned char *data)
+{
+	struct i2c_msg msgs[2];
+	int res;
+
+	if (NULL == data || NULL == i2c_adap)
+		return -EINVAL;
+
+	msgs[0].addr = address;
+	msgs[0].flags = 0;	/* write */
+	msgs[0].buf = &reg;
+	msgs[0].len = 1;
+
+	msgs[1].addr = address;
+	msgs[1].flags = I2C_M_RD;
+	msgs[1].buf = data;
+	msgs[1].len = len;
+
+	res = i2c_transfer(i2c_adap, msgs, 2);
+	if (res < 2)
+		return res;
+	else
+		return 0;
+}
+
+int mpu_memory_read(struct i2c_adapter *i2c_adap,
+		    unsigned char mpu_addr,
+		    unsigned short mem_addr,
+		    unsigned int len, unsigned char *data)
+{
+	unsigned char bank[2];
+	unsigned char addr[2];
+	unsigned char buf;
+
+	struct i2c_msg msgs[4];
+	int ret;
+
+	if (NULL == data || NULL == i2c_adap)
+		return -EINVAL;
+
+	bank[0] = MPUREG_BANK_SEL;
+	bank[1] = mem_addr >> 8;
+
+	addr[0] = MPUREG_MEM_START_ADDR;
+	addr[1] = mem_addr & 0xFF;
+
+	buf = MPUREG_MEM_R_W;
+
+	/* Write Message */
+	msgs[0].addr = mpu_addr;
+	msgs[0].flags = 0;
+	msgs[0].buf = bank;
+	msgs[0].len = sizeof(bank);
+
+	msgs[1].addr = mpu_addr;
+	msgs[1].flags = 0;
+	msgs[1].buf = addr;
+	msgs[1].len = sizeof(addr);
+
+	msgs[2].addr = mpu_addr;
+	msgs[2].flags = 0;
+	msgs[2].buf = &buf;
+	msgs[2].len = 1;
+
+	msgs[3].addr = mpu_addr;
+	msgs[3].flags = I2C_M_RD;
+	msgs[3].buf = data;
+	msgs[3].len = len;
+
+	ret = i2c_transfer(i2c_adap, msgs, 4);
+	if (ret != 4)
+		return ret;
+	else
+		return 0;
+}
+
+int mpu_memory_write(struct i2c_adapter *i2c_adap,
+		     unsigned char mpu_addr,
+		     unsigned short mem_addr,
+		     unsigned int len, unsigned char const *data)
+{
+	unsigned char bank[2];
+	unsigned char addr[2];
+	unsigned char buf[513];
+
+	struct i2c_msg msgs[3];
+	int ret;
+
+	if (NULL == data || NULL == i2c_adap)
+		return -EINVAL;
+	if (len >= (sizeof(buf) - 1))
+		return -ENOMEM;
+
+	bank[0] = MPUREG_BANK_SEL;
+	bank[1] = mem_addr >> 8;
+
+	addr[0] = MPUREG_MEM_START_ADDR;
+	addr[1] = mem_addr & 0xFF;
+
+	buf[0] = MPUREG_MEM_R_W;
+	memcpy(buf + 1, data, len);
+
+	/* Write Message */
+	msgs[0].addr = mpu_addr;
+	msgs[0].flags = 0;
+	msgs[0].buf = bank;
+	msgs[0].len = sizeof(bank);
+
+	msgs[1].addr = mpu_addr;
+	msgs[1].flags = 0;
+	msgs[1].buf = addr;
+	msgs[1].len = sizeof(addr);
+
+	msgs[2].addr = mpu_addr;
+	msgs[2].flags = 0;
+	msgs[2].buf = (unsigned char *) buf;
+	msgs[2].len = len + 1;
+
+	ret = i2c_transfer(i2c_adap, msgs, 3);
+	if (ret != 3)
+		return ret;
+	else
+		return 0;
+}
+
+/**
+ *  @}
+ */
diff --git a/drivers/misc/mpu3050/mpu-i2c.h b/drivers/misc/mpu3050/mpu-i2c.h
new file mode 100644
index 000000000000..0bbc8c64594e
--- /dev/null
+++ b/drivers/misc/mpu3050/mpu-i2c.h
@@ -0,0 +1,58 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+/**
+ * @defgroup
+ * @brief
+ *
+ * @{
+ * @file     mpu-i2c.c
+ * @brief
+ *
+ *
+ */
+
+#ifndef __MPU_I2C_H__
+#define __MPU_I2C_H__
+
+#include <linux/i2c.h>
+
+int sensor_i2c_write(struct i2c_adapter *i2c_adap,
+		     unsigned char address,
+		     unsigned int len, unsigned char const *data);
+
+int sensor_i2c_write_register(struct i2c_adapter *i2c_adap,
+			      unsigned char address,
+			      unsigned char reg, unsigned char value);
+
+int sensor_i2c_read(struct i2c_adapter *i2c_adap,
+		    unsigned char address,
+		    unsigned char reg,
+		    unsigned int len, unsigned char *data);
+
+int mpu_memory_read(struct i2c_adapter *i2c_adap,
+		    unsigned char mpu_addr,
+		    unsigned short mem_addr,
+		    unsigned int len, unsigned char *data);
+
+int mpu_memory_write(struct i2c_adapter *i2c_adap,
+		     unsigned char mpu_addr,
+		     unsigned short mem_addr,
+		     unsigned int len, unsigned char const *data);
+
+#endif	/* __MPU_I2C_H__ */
diff --git a/drivers/misc/mpu3050/mpuirq.c b/drivers/misc/mpu3050/mpuirq.c
new file mode 100644
index 000000000000..b6f21856cf32
--- /dev/null
+++ b/drivers/misc/mpu3050/mpuirq.c
@@ -0,0 +1,323 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/stat.h>
+#include <linux/irq.h>
+#include <linux/signal.h>
+#include <linux/miscdevice.h>
+#include <linux/i2c.h>
+#include <linux/i2c-dev.h>
+#include <linux/workqueue.h>
+#include <linux/poll.h>
+
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/uaccess.h>
+#include <linux/io.h>
+
+#include "mpu.h"
+#include "mpuirq.h"
+#include "mldl_cfg.h"
+#include "mpu-i2c.h"
+
+#define MPUIRQ_NAME "mpuirq"
+
+/* function which gets accel data and sends it to MPU */
+
+DECLARE_WAIT_QUEUE_HEAD(mpuirq_wait);
+
+struct mpuirq_dev_data {
+	struct work_struct work;
+	struct i2c_client *mpu_client;
+	struct miscdevice *dev;
+	int irq;
+	int pid;
+	int accel_divider;
+	int data_ready;
+	int timeout;
+};
+
+static struct mpuirq_dev_data mpuirq_dev_data;
+static struct irq_data mpuirq_data;
+static char *interface = MPUIRQ_NAME;
+
+static void mpu_accel_data_work_fcn(struct work_struct *work);
+
+static int mpuirq_open(struct inode *inode, struct file *file)
+{
+	dev_dbg(mpuirq_dev_data.dev->this_device,
+		"%s current->pid %d\n", __func__, current->pid);
+	mpuirq_dev_data.pid = current->pid;
+	file->private_data = &mpuirq_dev_data;
+	/* we could do some checking on the flags supplied by "open" */
+	/* i.e. O_NONBLOCK */
+	/* -> set some flag to disable interruptible_sleep_on in mpuirq_read */
+	return 0;
+}
+
+/* close function - called when the "file" /dev/mpuirq is closed in userspace */
+static int mpuirq_release(struct inode *inode, struct file *file)
+{
+	dev_dbg(mpuirq_dev_data.dev->this_device, "mpuirq_release\n");
+	return 0;
+}
+
+/* read function called when from /dev/mpuirq is read */
+static ssize_t mpuirq_read(struct file *file,
+			   char *buf, size_t count, loff_t *ppos)
+{
+	int len, err;
+	struct mpuirq_dev_data *p_mpuirq_dev_data = file->private_data;
+
+	if (!mpuirq_dev_data.data_ready) {
+		wait_event_interruptible_timeout(mpuirq_wait,
+						 mpuirq_dev_data.
+						 data_ready,
+						 mpuirq_dev_data.timeout);
+	}
+
+	if (mpuirq_dev_data.data_ready && NULL != buf
+	    && count >= sizeof(mpuirq_data)) {
+		err = copy_to_user(buf, &mpuirq_data, sizeof(mpuirq_data));
+		mpuirq_data.data_type = 0;
+	} else {
+		return 0;
+	}
+	if (err != 0) {
+		dev_err(p_mpuirq_dev_data->dev->this_device,
+			"Copy to user returned %d\n", err);
+		return -EFAULT;
+	}
+	mpuirq_dev_data.data_ready = 0;
+	len = sizeof(mpuirq_data);
+	return len;
+}
+
+unsigned int mpuirq_poll(struct file *file, struct poll_table_struct *poll)
+{
+	int mask = 0;
+
+	poll_wait(file, &mpuirq_wait, poll);
+	if (mpuirq_dev_data.data_ready)
+		mask |= POLLIN | POLLRDNORM;
+	return mask;
+}
+
+/* ioctl - I/O control */
+static long mpuirq_ioctl(struct file *file,
+			 unsigned int cmd, unsigned long arg)
+{
+	int retval = 0;
+	int data;
+
+	switch (cmd) {
+	case MPUIRQ_SET_TIMEOUT:
+		mpuirq_dev_data.timeout = arg;
+		break;
+
+	case MPUIRQ_GET_INTERRUPT_CNT:
+		data = mpuirq_data.interruptcount - 1;
+		if (mpuirq_data.interruptcount > 1)
+			mpuirq_data.interruptcount = 1;
+
+		if (copy_to_user((int *) arg, &data, sizeof(int)))
+			return -EFAULT;
+		break;
+	case MPUIRQ_GET_IRQ_TIME:
+		if (copy_to_user((int *) arg, &mpuirq_data.irqtime,
+				 sizeof(mpuirq_data.irqtime)))
+			return -EFAULT;
+		mpuirq_data.irqtime = 0;
+		break;
+	case MPUIRQ_SET_FREQUENCY_DIVIDER:
+		mpuirq_dev_data.accel_divider = arg;
+		break;
+	default:
+		retval = -EINVAL;
+	}
+	return retval;
+}
+
+static void mpu_accel_data_work_fcn(struct work_struct *work)
+{
+	struct mpuirq_dev_data *mpuirq_dev_data =
+	    (struct mpuirq_dev_data *) work;
+	struct mldl_cfg *mldl_cfg =
+	    (struct mldl_cfg *)
+	    i2c_get_clientdata(mpuirq_dev_data->mpu_client);
+	struct i2c_adapter *accel_adapter;
+	unsigned char wbuff[16];
+	unsigned char rbuff[16];
+	int ii;
+
+	accel_adapter = i2c_get_adapter(mldl_cfg->pdata->accel.adapt_num);
+	mldl_cfg->accel->read(accel_adapter,
+			      mldl_cfg->accel,
+			      &mldl_cfg->pdata->accel, rbuff);
+
+
+	/* @todo add other data formats here as well */
+	if (EXT_SLAVE_BIG_ENDIAN == mldl_cfg->accel->endian) {
+		for (ii = 0; ii < 3; ii++) {
+			wbuff[2 * ii + 1] = rbuff[2 * ii + 1];
+			wbuff[2 * ii + 2] = rbuff[2 * ii + 0];
+		}
+	} else {
+		memcpy(wbuff + 1, rbuff, mldl_cfg->accel->len);
+	}
+
+	wbuff[7] = 0;
+	wbuff[8] = 1;		/*set semaphore */
+
+	mpu_memory_write(mpuirq_dev_data->mpu_client->adapter,
+			 mldl_cfg->addr, 0x0108, 8, wbuff);
+}
+
+static irqreturn_t mpuirq_handler(int irq, void *dev_id)
+{
+	static int mycount;
+	struct timeval irqtime;
+	mycount++;
+
+	mpuirq_data.interruptcount++;
+
+	/* wake up (unblock) for reading data from userspace */
+	/* and ignore first interrupt generated in module init */
+	if (mpuirq_data.interruptcount > 1) {
+		mpuirq_dev_data.data_ready = 1;
+
+		do_gettimeofday(&irqtime);
+		mpuirq_data.irqtime = (((long long) irqtime.tv_sec) << 32);
+		mpuirq_data.irqtime += irqtime.tv_usec;
+
+		if ((mpuirq_dev_data.accel_divider >= 0) &&
+		    (0 ==
+		     (mycount % (mpuirq_dev_data.accel_divider + 1)))) {
+			schedule_work((struct work_struct
+				       *) (&mpuirq_dev_data));
+		}
+
+		wake_up_interruptible(&mpuirq_wait);
+	}
+
+	return IRQ_HANDLED;
+
+}
+
+/* define which file operations are supported */
+const struct file_operations mpuirq_fops = {
+	.owner = THIS_MODULE,
+	.read = mpuirq_read,
+	.poll = mpuirq_poll,
+
+#if HAVE_COMPAT_IOCTL
+	.compat_ioctl = mpuirq_ioctl,
+#endif
+#if HAVE_UNLOCKED_IOCTL
+	.unlocked_ioctl = mpuirq_ioctl,
+#endif
+	.open = mpuirq_open,
+	.release = mpuirq_release,
+};
+
+static struct miscdevice mpuirq_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = MPUIRQ_NAME,
+	.fops = &mpuirq_fops,
+};
+
+int mpuirq_init(struct i2c_client *mpu_client)
+{
+
+	int res;
+	struct mldl_cfg *mldl_cfg =
+	    (struct mldl_cfg *) i2c_get_clientdata(mpu_client);
+
+	/* work_struct initialization */
+	INIT_WORK((struct work_struct *) &mpuirq_dev_data,
+		  mpu_accel_data_work_fcn);
+	mpuirq_dev_data.mpu_client = mpu_client;
+
+	dev_info(&mpu_client->adapter->dev,
+		 "Module Param interface = %s\n", interface);
+
+	mpuirq_dev_data.irq = mpu_client->irq;
+	mpuirq_dev_data.pid = 0;
+	mpuirq_dev_data.accel_divider = -1;
+	mpuirq_dev_data.data_ready = 0;
+	mpuirq_dev_data.timeout = 0;
+	mpuirq_dev_data.dev = &mpuirq_device;
+
+	if (mpuirq_dev_data.irq) {
+		unsigned long flags;
+		if (BIT_ACTL_LOW ==
+		    ((mldl_cfg->pdata->int_config) & BIT_ACTL))
+			flags = IRQF_TRIGGER_FALLING;
+		else
+			flags = IRQF_TRIGGER_RISING;
+
+		res =
+		    request_irq(mpuirq_dev_data.irq, mpuirq_handler, flags,
+				interface, &mpuirq_dev_data.irq);
+		if (res) {
+			dev_err(&mpu_client->adapter->dev,
+				"myirqtest: cannot register IRQ %d\n",
+				mpuirq_dev_data.irq);
+		} else {
+			res = misc_register(&mpuirq_device);
+			if (res < 0) {
+				dev_err(&mpu_client->adapter->dev,
+					"misc_register returned %d\n",
+					res);
+				free_irq(mpuirq_dev_data.irq,
+					 &mpuirq_dev_data.irq);
+			}
+		}
+
+	} else {
+		res = 0;
+	}
+
+	return res;
+}
+
+void mpuirq_exit(void)
+{
+	/* Free the IRQ first before flushing the work */
+	if (mpuirq_dev_data.irq > 0)
+		free_irq(mpuirq_dev_data.irq, &mpuirq_dev_data.irq);
+
+	flush_scheduled_work();
+
+	dev_info(mpuirq_device.this_device, "Unregistering %s\n",
+		 MPUIRQ_NAME);
+	misc_deregister(&mpuirq_device);
+
+	return;
+}
+
+module_param(interface, charp, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(interface, "The Interface name");
diff --git a/drivers/misc/mpu3050/mpuirq.h b/drivers/misc/mpu3050/mpuirq.h
new file mode 100644
index 000000000000..70a2d35679f0
--- /dev/null
+++ b/drivers/misc/mpu3050/mpuirq.h
@@ -0,0 +1,42 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+#ifndef __MPUIRQ__
+#define __MPUIRQ__
+
+#ifdef __KERNEL__
+#include <linux/i2c-dev.h>
+#endif
+
+#define MPUIRQ_ENABLE_DEBUG          (1)
+#define MPUIRQ_GET_INTERRUPT_CNT     (2)
+#define MPUIRQ_GET_IRQ_TIME          (3)
+#define MPUIRQ_GET_LED_VALUE         (4)
+#define MPUIRQ_SET_TIMEOUT           (5)
+#define MPUIRQ_SET_ACCEL_INFO        (6)
+#define MPUIRQ_SET_FREQUENCY_DIVIDER (7)
+
+#ifdef __KERNEL__
+
+void mpuirq_exit(void);
+int mpuirq_init(struct i2c_client *mpu_client);
+
+#endif
+
+#endif
diff --git a/drivers/misc/mpu3050/slaveirq.c b/drivers/misc/mpu3050/slaveirq.c
new file mode 100644
index 000000000000..3791868505ee
--- /dev/null
+++ b/drivers/misc/mpu3050/slaveirq.c
@@ -0,0 +1,272 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/stat.h>
+#include <linux/irq.h>
+#include <linux/signal.h>
+#include <linux/miscdevice.h>
+#include <linux/i2c.h>
+#include <linux/i2c-dev.h>
+#include <linux/poll.h>
+
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+#include "mpu.h"
+#include "slaveirq.h"
+#include "mldl_cfg.h"
+#include "mpu-i2c.h"
+#include <linux/wait.h>
+#include <linux/slab.h>
+
+/* function which gets slave data and sends it to SLAVE */
+
+struct slaveirq_dev_data {
+	struct miscdevice dev;
+	struct i2c_client *slave_client;
+	struct irq_data data;
+	wait_queue_head_t slaveirq_wait;
+	int irq;
+	int pid;
+	int data_ready;
+	int timeout;
+};
+
+/* The following depends on patch fa1f68db6ca7ebb6fc4487ac215bffba06c01c28
+ * drivers: misc: pass miscdevice pointer via file private data
+ */
+static int slaveirq_open(struct inode *inode, struct file *file)
+{
+	/* Device node is availabe in the file->private_data, this is
+	 * exactly what we want so we leave it there */
+	struct slaveirq_dev_data *data =
+		container_of(file->private_data, struct slaveirq_dev_data, dev);
+
+	dev_dbg(data->dev.this_device,
+		"%s current->pid %d\n", __func__, current->pid);
+	data->pid = current->pid;
+	return 0;
+}
+
+static int slaveirq_release(struct inode *inode, struct file *file)
+{
+	struct slaveirq_dev_data *data =
+		container_of(file->private_data, struct slaveirq_dev_data, dev);
+	dev_dbg(data->dev.this_device, "slaveirq_release\n");
+	return 0;
+}
+
+/* read function called when from /dev/slaveirq is read */
+static ssize_t slaveirq_read(struct file *file,
+			   char *buf, size_t count, loff_t * ppos)
+{
+	int len, err;
+	struct slaveirq_dev_data *data =
+		container_of(file->private_data, struct slaveirq_dev_data, dev);
+
+	if (!data->data_ready) {
+		wait_event_interruptible_timeout(data->slaveirq_wait,
+						 data->data_ready,
+						 data->timeout);
+	}
+
+	if (data->data_ready && NULL != buf
+	    && count >= sizeof(data->data)) {
+		err = copy_to_user(buf, &data->data, sizeof(data->data));
+		data->data.data_type = 0;
+	} else {
+		return 0;
+	}
+	if (err != 0) {
+		dev_err(data->dev.this_device,
+			"Copy to user returned %d\n", err);
+		return -EFAULT;
+	}
+	data->data_ready = 0;
+	len = sizeof(data->data);
+	return len;
+}
+
+unsigned int slaveirq_poll(struct file *file, struct poll_table_struct *poll)
+{
+	int mask = 0;
+	struct slaveirq_dev_data *data =
+		container_of(file->private_data, struct slaveirq_dev_data, dev);
+
+	poll_wait(file, &data->slaveirq_wait, poll);
+	if (data->data_ready)
+		mask |= POLLIN | POLLRDNORM;
+	return mask;
+}
+
+/* ioctl - I/O control */
+static long slaveirq_ioctl(struct file *file,
+			   unsigned int cmd, unsigned long arg)
+{
+	int retval = 0;
+	int tmp;
+	struct slaveirq_dev_data *data =
+		container_of(file->private_data, struct slaveirq_dev_data, dev);
+
+	switch (cmd) {
+	case SLAVEIRQ_SET_TIMEOUT:
+		data->timeout = arg;
+		break;
+
+	case SLAVEIRQ_GET_INTERRUPT_CNT:
+		tmp = data->data.interruptcount - 1;
+		if (data->data.interruptcount > 1)
+			data->data.interruptcount = 1;
+
+		if (copy_to_user((int *) arg, &tmp, sizeof(int)))
+			return -EFAULT;
+		break;
+	case SLAVEIRQ_GET_IRQ_TIME:
+		if (copy_to_user((int *) arg, &data->data.irqtime,
+				 sizeof(data->data.irqtime)))
+			return -EFAULT;
+		data->data.irqtime = 0;
+		break;
+	default:
+		retval = -EINVAL;
+	}
+	return retval;
+}
+
+static irqreturn_t slaveirq_handler(int irq, void *dev_id)
+{
+	struct slaveirq_dev_data *data = (struct slaveirq_dev_data *)dev_id;
+	static int mycount;
+	struct timeval irqtime;
+	mycount++;
+
+	data->data.interruptcount++;
+
+	/* wake up (unblock) for reading data from userspace */
+	/* and ignore first interrupt generated in module init */
+	if (data->data.interruptcount > 1) {
+		data->data_ready = 1;
+
+		do_gettimeofday(&irqtime);
+		data->data.irqtime = (((long long) irqtime.tv_sec) << 32);
+		data->data.irqtime += irqtime.tv_usec;
+		data->data.data_type |= 1;
+
+		wake_up_interruptible(&data->slaveirq_wait);
+	}
+
+	return IRQ_HANDLED;
+
+}
+
+/* define which file operations are supported */
+static const struct file_operations slaveirq_fops = {
+	.owner = THIS_MODULE,
+	.read = slaveirq_read,
+	.poll = slaveirq_poll,
+
+#if HAVE_COMPAT_IOCTL
+	.compat_ioctl = slaveirq_ioctl,
+#endif
+#if HAVE_UNLOCKED_IOCTL
+	.unlocked_ioctl = slaveirq_ioctl,
+#endif
+	.open = slaveirq_open,
+	.release = slaveirq_release,
+};
+
+int slaveirq_init(struct i2c_adapter *slave_adapter,
+		  struct ext_slave_platform_data *pdata,
+		  char *name)
+{
+
+	int res;
+	struct slaveirq_dev_data *data;
+
+	if (!pdata->irq)
+		return -EINVAL;
+
+	pdata->irq_data = kzalloc(sizeof(*data),
+				GFP_KERNEL);
+	data = (struct slaveirq_dev_data *) pdata->irq_data;
+	if (!data)
+		return -ENOMEM;
+
+	data->dev.minor = MISC_DYNAMIC_MINOR;
+	data->dev.name = name;
+	data->dev.fops = &slaveirq_fops;
+	data->irq = pdata->irq;
+	data->pid = 0;
+	data->data_ready = 0;
+	data->timeout = 0;
+
+	res = request_irq(data->irq, slaveirq_handler, IRQF_TRIGGER_RISING,
+			  data->dev.name, data);
+
+	if (res) {
+		dev_err(&slave_adapter->dev,
+			"myirqtest: cannot register IRQ %d\n",
+			data->irq);
+		goto out_request_irq;
+	}
+
+	res = misc_register(&data->dev);
+	if (res < 0) {
+		dev_err(&slave_adapter->dev,
+			"misc_register returned %d\n",
+			res);
+		goto out_misc_register;
+	}
+
+	init_waitqueue_head(&data->slaveirq_wait);
+	return res;
+
+out_misc_register:
+	free_irq(data->irq, data);
+out_request_irq:
+	kfree(pdata->irq_data);
+	pdata->irq_data = NULL;
+
+	return res;
+}
+
+void slaveirq_exit(struct ext_slave_platform_data *pdata)
+{
+	struct slaveirq_dev_data *data = pdata->irq_data;
+
+	if (!pdata->irq_data || data->irq <= 0)
+		return;
+
+	dev_info(data->dev.this_device, "Unregistering %s\n",
+		 data->dev.name);
+
+	free_irq(data->irq, data);
+	misc_deregister(&data->dev);
+	kfree(pdata->irq_data);
+	pdata->irq_data = NULL;
+}
diff --git a/drivers/misc/mpu3050/slaveirq.h b/drivers/misc/mpu3050/slaveirq.h
new file mode 100644
index 000000000000..ca9c7e496dab
--- /dev/null
+++ b/drivers/misc/mpu3050/slaveirq.h
@@ -0,0 +1,46 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+#ifndef __SLAVEIRQ__
+#define __SLAVEIRQ__
+
+#ifdef __KERNEL__
+#include <linux/i2c-dev.h>
+#endif
+
+#include "mpu.h"
+#include "mpuirq.h"
+
+#define SLAVEIRQ_ENABLE_DEBUG          (1)
+#define SLAVEIRQ_GET_INTERRUPT_CNT     (2)
+#define SLAVEIRQ_GET_IRQ_TIME          (3)
+#define SLAVEIRQ_GET_LED_VALUE         (4)
+#define SLAVEIRQ_SET_TIMEOUT           (5)
+#define SLAVEIRQ_SET_SLAVE_INFO        (6)
+
+#ifdef __KERNEL__
+
+void slaveirq_exit(struct ext_slave_platform_data *pdata);
+int slaveirq_init(struct i2c_adapter *slave_adapter,
+		struct ext_slave_platform_data *pdata,
+		char *name);
+
+#endif
+
+#endif
diff --git a/drivers/misc/nct1008.c b/drivers/misc/nct1008.c
index 4ae48e4003aa..6bdad35f3796 100755
--- a/drivers/misc/nct1008.c
+++ b/drivers/misc/nct1008.c
@@ -35,6 +35,8 @@
 
 /* Register Addresses */
 #define LOCAL_TEMP_RD			0x00
+#define EXT_HI_TEMP_RD			0x01
+#define EXT_LO_TEMP_RD			0x10
 #define STATUS_RD			0x02
 #define CONFIG_RD			0x03
 
@@ -65,6 +67,64 @@ struct nct1008_data {
 	void (*alarm_fn)(bool raised);
 };
 
+static ssize_t nct1008_show_temp(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	signed int temp_value = 0;
+	u8 data = 0;
+
+	if (!dev || !buf || !attr)
+		return -EINVAL;
+
+	data = i2c_smbus_read_byte_data(client, LOCAL_TEMP_RD);
+	if (data < 0) {
+		dev_err(&client->dev, "%s: failed to read "
+			"temperature\n", __func__);
+		return -EINVAL;
+	}
+
+	temp_value = (signed int)data;
+	return sprintf(buf, "%d\n", temp_value);
+}
+
+static ssize_t nct1008_show_ext_temp(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct i2c_client *client = to_i2c_client(dev);
+	signed int temp_value = 0;
+	u8 data = 0;
+
+	if (!dev || !buf || !attr)
+		return -EINVAL;
+
+	data = i2c_smbus_read_byte_data(client, EXT_HI_TEMP_RD);
+	if (data < 0) {
+		dev_err(&client->dev, "%s: failed to read "
+			"ext_temperature\n", __func__);
+		return -EINVAL;
+	}
+
+	temp_value = (signed int)data;
+
+	data = i2c_smbus_read_byte_data(client, EXT_LO_TEMP_RD);
+
+	return sprintf(buf, "%d.%d\n", temp_value, (25 * (data >> 6)));
+}
+
+static DEVICE_ATTR(temperature, S_IRUGO, nct1008_show_temp, NULL);
+static DEVICE_ATTR(ext_temperature, S_IRUGO, nct1008_show_ext_temp, NULL);
+
+static struct attribute *nct1008_attributes[] = {
+	&dev_attr_temperature.attr,
+	&dev_attr_ext_temperature.attr,
+	NULL
+};
+
+static const struct attribute_group nct1008_attr_group = {
+	.attrs = nct1008_attributes,
+};
+
 static void nct1008_enable(struct i2c_client *client)
 {
 	struct nct1008_data *data = i2c_get_clientdata(client);
@@ -212,6 +272,13 @@ static int __devinit nct1008_probe(struct i2c_client *client, const struct i2c_d
 	if (err < 0)
 		goto error;
 
+	/* register sysfs hooks */
+	err = sysfs_create_group(&client->dev.kobj, &nct1008_attr_group);
+	if (err < 0)
+		goto error;
+
+	dev_info(&client->dev, "%s: initialized\n", __func__);
+
 	nct1008_enable(client);		/* sensor is running */
 
 	schedule_work(&data->work);		/* check initial state */
@@ -229,6 +296,7 @@ static int __devexit nct1008_remove(struct i2c_client *client)
 
 	free_irq(data->client->irq, data);
 	cancel_work_sync(&data->work);
+	sysfs_remove_group(&client->dev.kobj, &nct1008_attr_group);
 	kfree(data);
 
 	return 0;
diff --git a/drivers/misc/tegra-cryptodev.c b/drivers/misc/tegra-cryptodev.c
new file mode 100644
index 000000000000..453e40ef0945
--- /dev/null
+++ b/drivers/misc/tegra-cryptodev.c
@@ -0,0 +1,347 @@
+/*
+ * drivers/misc/tegra-cryptodev.c
+ *
+ * crypto dev node for NVIDIA tegra aes hardware
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/fs.h>
+#include <linux/miscdevice.h>
+#include <linux/crypto.h>
+#include <linux/scatterlist.h>
+#include <linux/uaccess.h>
+#include <crypto/rng.h>
+
+#include "tegra-cryptodev.h"
+
+#define NBUFS 2
+
+struct tegra_crypto_ctx {
+	struct crypto_ablkcipher *ecb_tfm;
+	struct crypto_ablkcipher *cbc_tfm;
+	struct crypto_rng *rng;
+	u8 seed[TEGRA_CRYPTO_RNG_SEED_SIZE];
+	int use_ssk;
+};
+
+struct tegra_crypto_completion {
+	struct completion restart;
+	int req_err;
+};
+
+static int alloc_bufs(unsigned long *buf[NBUFS])
+{
+	int i;
+
+	for (i = 0; i < NBUFS; i++) {
+		buf[i] = (void *)__get_free_page(GFP_KERNEL);
+		if (!buf[i])
+			goto err_free_buf;
+	}
+
+	return 0;
+
+err_free_buf:
+	while (i-- > 0)
+		free_page((unsigned long)buf[i]);
+
+	return -ENOMEM;
+}
+
+static void free_bufs(unsigned long *buf[NBUFS])
+{
+	int i;
+
+	for (i = 0; i < NBUFS; i++)
+		free_page((unsigned long)buf[i]);
+}
+
+static int tegra_crypto_dev_open(struct inode *inode, struct file *filp)
+{
+	struct tegra_crypto_ctx *ctx;
+	int ret = 0;
+
+	ctx = kzalloc(sizeof(struct tegra_crypto_ctx), GFP_KERNEL);
+	if (!ctx) {
+		pr_err("no memory for context\n");
+		return -ENOMEM;
+	}
+
+	ctx->ecb_tfm = crypto_alloc_ablkcipher("ecb-aes-tegra",
+		CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 0);
+	if (IS_ERR(ctx->ecb_tfm)) {
+		pr_err("Failed to load transform for ecb-aes-tegra: %ld\n",
+			PTR_ERR(ctx->ecb_tfm));
+		ret = PTR_ERR(ctx->ecb_tfm);
+		goto fail_ecb;
+	}
+
+	ctx->cbc_tfm = crypto_alloc_ablkcipher("cbc-aes-tegra",
+		CRYPTO_ALG_TYPE_ABLKCIPHER | CRYPTO_ALG_ASYNC, 0);
+	if (IS_ERR(ctx->cbc_tfm)) {
+		pr_err("Failed to load transform for cbc-aes-tegra: %ld\n",
+			PTR_ERR(ctx->cbc_tfm));
+		ret = PTR_ERR(ctx->cbc_tfm);
+		goto fail_cbc;
+	}
+
+	ctx->rng = crypto_alloc_rng("rng-aes-tegra", CRYPTO_ALG_TYPE_RNG, 0);
+	if (IS_ERR(ctx->rng)) {
+		pr_err("Failed to load transform for tegra rng: %ld\n",
+			PTR_ERR(ctx->rng));
+		ret = PTR_ERR(ctx->rng);
+		goto fail_rng;
+	}
+
+	filp->private_data = ctx;
+	return ret;
+
+fail_rng:
+	crypto_free_ablkcipher(ctx->cbc_tfm);
+
+fail_cbc:
+	crypto_free_ablkcipher(ctx->ecb_tfm);
+
+fail_ecb:
+	kfree(ctx);
+	return ret;
+}
+
+static int tegra_crypto_dev_release(struct inode *inode, struct file *filp)
+{
+	struct tegra_crypto_ctx *ctx = filp->private_data;
+
+	crypto_free_ablkcipher(ctx->ecb_tfm);
+	crypto_free_ablkcipher(ctx->cbc_tfm);
+	crypto_free_rng(ctx->rng);
+	kfree(ctx);
+	filp->private_data = NULL;
+	return 0;
+}
+
+static void tegra_crypt_complete(struct crypto_async_request *req, int err)
+{
+	struct tegra_crypto_completion *done = req->data;
+
+	if (err != -EINPROGRESS) {
+		done->req_err = err;
+		complete(&done->restart);
+	}
+}
+
+static int process_crypt_req(struct tegra_crypto_ctx *ctx, struct tegra_crypt_req *crypt_req)
+{
+	struct crypto_ablkcipher *tfm;
+	struct ablkcipher_request *req = NULL;
+	struct scatterlist in_sg;
+	struct scatterlist out_sg;
+	unsigned long *xbuf[NBUFS];
+	int ret = 0, size = 0;
+	unsigned long total = 0;
+	struct tegra_crypto_completion tcrypt_complete;
+
+	if (crypt_req->op & TEGRA_CRYPTO_ECB) {
+		req = ablkcipher_request_alloc(ctx->ecb_tfm, GFP_KERNEL);
+		tfm = ctx->ecb_tfm;
+	} else {
+		req = ablkcipher_request_alloc(ctx->cbc_tfm, GFP_KERNEL);
+		tfm = ctx->cbc_tfm;
+	}
+	if (!req) {
+		pr_err("%s: Failed to allocate request\n", __func__);
+		return -ENOMEM;
+	}
+
+	if ((crypt_req->keylen < 0) || (crypt_req->keylen > AES_MAX_KEY_SIZE))
+		return -EINVAL;
+
+	crypto_ablkcipher_clear_flags(tfm, ~0);
+
+	if (!ctx->use_ssk) {
+		ret = crypto_ablkcipher_setkey(tfm, crypt_req->key,
+			crypt_req->keylen);
+		if (ret < 0) {
+			pr_err("setkey failed");
+			goto process_req_out;
+		}
+	}
+
+	ret = alloc_bufs(xbuf);
+	if (ret < 0) {
+		pr_err("alloc_bufs failed");
+		goto process_req_out;
+	}
+
+	init_completion(&tcrypt_complete.restart);
+
+	ablkcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
+		tegra_crypt_complete, &tcrypt_complete);
+
+	total = crypt_req->plaintext_sz;
+	while (total > 0) {
+		size = min(total, PAGE_SIZE);
+		ret = copy_from_user((void *)xbuf[0],
+			(void __user *)crypt_req->plaintext, size);
+		if (ret < 0) {
+			pr_debug("%s: copy_from_user failed (%d)\n", __func__, ret);
+			goto process_req_buf_out;
+		}
+		sg_init_one(&in_sg, xbuf[0], size);
+		sg_init_one(&out_sg, xbuf[1], size);
+
+		ablkcipher_request_set_crypt(req, &in_sg,
+			&out_sg, size, crypt_req->iv);
+
+		INIT_COMPLETION(tcrypt_complete.restart);
+		tcrypt_complete.req_err = 0;
+		ret = crypt_req->encrypt ?
+			crypto_ablkcipher_encrypt(req) :
+			crypto_ablkcipher_decrypt(req);
+
+		if ((ret == -EINPROGRESS) || (ret == -EBUSY)) {
+			/* crypto driver is asynchronous */
+			ret = wait_for_completion_interruptible(&tcrypt_complete.restart);
+
+			if (ret < 0)
+				goto process_req_buf_out;
+
+			if (tcrypt_complete.req_err < 0) {
+				ret = tcrypt_complete.req_err;
+				goto process_req_buf_out;
+			}
+		} else if (ret < 0) {
+			pr_debug("%scrypt failed (%d)\n",
+				crypt_req->encrypt ? "en" : "de", ret);
+			goto process_req_buf_out;
+		}
+
+		ret = copy_to_user((void __user *)crypt_req->result,
+			(const void *)xbuf[1], size);
+		if (ret < 0)
+			goto process_req_buf_out;
+
+		total -= size;
+		crypt_req->result += size;
+		crypt_req->plaintext += size;
+	}
+
+process_req_buf_out:
+	free_bufs(xbuf);
+process_req_out:
+	ablkcipher_request_free(req);
+
+	return ret;
+}
+
+static long tegra_crypto_dev_ioctl(struct file *filp,
+	unsigned int ioctl_num, unsigned long arg)
+{
+	struct tegra_crypto_ctx *ctx = filp->private_data;
+	struct tegra_crypt_req crypt_req;
+	struct tegra_rng_req rng_req;
+	char *rng;
+	int ret = 0;
+
+	switch (ioctl_num) {
+	case TEGRA_CRYPTO_IOCTL_NEED_SSK:
+		ctx->use_ssk = (int)arg;
+		break;
+	case TEGRA_CRYPTO_IOCTL_PROCESS_REQ:
+		ret = copy_from_user(&crypt_req, (void __user *)arg, sizeof(crypt_req));
+		if (ret < 0) {
+			pr_debug("%s: copy_from_user fail(%d)\n", __func__, ret);
+			break;
+		}
+
+		ret = process_crypt_req(ctx, &crypt_req);
+		break;
+
+	case TEGRA_CRYPTO_IOCTL_SET_SEED:
+		if (copy_from_user(&rng_req, (void __user *)arg, sizeof(rng_req)))
+			return -EFAULT;
+
+		memcpy(ctx->seed, rng_req.seed, TEGRA_CRYPTO_RNG_SEED_SIZE);
+
+		ret = crypto_rng_reset(ctx->rng, ctx->seed,
+			crypto_rng_seedsize(ctx->rng));
+		break;
+	case TEGRA_CRYPTO_IOCTL_GET_RANDOM:
+		if (copy_from_user(&rng_req, (void __user *)arg, sizeof(rng_req)))
+			return -EFAULT;
+
+		rng = kzalloc(rng_req.nbytes, GFP_KERNEL);
+		if (!rng) {
+			pr_err("mem alloc for rng fail");
+			ret = -ENODATA;
+			goto rng_out;
+		}
+
+		ret = crypto_rng_get_bytes(ctx->rng, rng,
+			rng_req.nbytes);
+
+		if (ret != rng_req.nbytes) {
+			pr_debug("rng failed");
+			ret = -ENODATA;
+			goto rng_out;
+		}
+
+		ret = copy_to_user((void __user *)rng_req.rdata,
+			(const void *)rng, rng_req.nbytes);
+		ret = (ret < 0) ? -ENODATA : 0;
+rng_out:
+		if (rng)
+			kfree(rng);
+
+		break;
+
+
+	default:
+		pr_debug("invalid ioctl code(%d)", ioctl_num);
+		ret = -EINVAL;
+	}
+	return ret;
+}
+
+struct file_operations tegra_crypto_fops = {
+	.owner = THIS_MODULE,
+	.open = tegra_crypto_dev_open,
+	.release = tegra_crypto_dev_release,
+	.unlocked_ioctl = tegra_crypto_dev_ioctl,
+};
+
+struct miscdevice tegra_crypto_device = {
+	.minor = MISC_DYNAMIC_MINOR,
+	.name = "tegra-crypto",
+	.fops = &tegra_crypto_fops,
+};
+
+static int __init tegra_crypto_dev_init(void)
+{
+	return misc_register(&tegra_crypto_device);
+}
+
+late_initcall(tegra_crypto_dev_init);
+
+MODULE_DESCRIPTION("Tegra AES hw device node.");
+MODULE_AUTHOR("NVIDIA Corporation");
+MODULE_LICENSE("GPLv2");
diff --git a/drivers/misc/tegra-cryptodev.h b/drivers/misc/tegra-cryptodev.h
new file mode 100644
index 000000000000..ed62a52eca03
--- /dev/null
+++ b/drivers/misc/tegra-cryptodev.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __TEGRA_CRYPTODEV_H
+#define __TEGRA_CRYPTODEV_H
+
+#include <crypto/aes.h>
+
+#include <asm-generic/ioctl.h>
+
+/* ioctl arg = 1 if you want to use ssk. arg = 0 to use normal key */
+#define TEGRA_CRYPTO_IOCTL_NEED_SSK	_IOWR(0x98, 100, int)
+#define TEGRA_CRYPTO_IOCTL_PROCESS_REQ	_IOWR(0x98, 101, int*)
+#define TEGRA_CRYPTO_IOCTL_SET_SEED	_IOWR(0x98, 102, int*)
+#define TEGRA_CRYPTO_IOCTL_GET_RANDOM	_IOWR(0x98, 103, int*)
+
+#define TEGRA_CRYPTO_MAX_KEY_SIZE	AES_MAX_KEY_SIZE
+#define TEGRA_CRYPTO_IV_SIZE	AES_BLOCK_SIZE
+#define DEFAULT_RNG_BLK_SZ	16
+
+/* the seed consists of 16 bytes of key + 16 bytes of init vector */
+#define TEGRA_CRYPTO_RNG_SEED_SIZE	AES_KEYSIZE_128 + DEFAULT_RNG_BLK_SZ
+#define TEGRA_CRYPTO_RNG_SIZE	SZ_16
+
+/* encrypt/decrypt operations */
+#define TEGRA_CRYPTO_ECB	BIT(0)
+#define TEGRA_CRYPTO_CBC	BIT(1)
+#define TEGRA_CRYPTO_RNG	BIT(2)
+
+/* a pointer to this struct needs to be passed to:
+ * TEGRA_CRYPTO_IOCTL_PROCESS_REQ
+ */
+struct tegra_crypt_req {
+	int op; /* e.g. TEGRA_CRYPTO_ECB */
+	bool encrypt;
+	char key[TEGRA_CRYPTO_MAX_KEY_SIZE];
+	int keylen;
+	char iv[TEGRA_CRYPTO_IV_SIZE];
+	int ivlen;
+	u8 *plaintext;
+	int plaintext_sz;
+	u8 *result;
+};
+
+/* pointer to this struct should be passed to:
+ * TEGRA_CRYPTO_IOCTL_SET_SEED
+ * TEGRA_CRYPTO_IOCTL_GET_RANDOM
+ */
+struct tegra_rng_req {
+	u8 seed[TEGRA_CRYPTO_RNG_SEED_SIZE];
+	u8 *rdata; /* random generated data */
+	int nbytes; /* random data length */
+};
+
+#endif
diff --git a/drivers/mmc/core/sdio_io.c b/drivers/mmc/core/sdio_io.c
index 549a34144646..549a34144646 100755..100644
--- a/drivers/mmc/core/sdio_io.c
+++ b/drivers/mmc/core/sdio_io.c
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 153bd9a16dd9..a16aa2b53417 100644..100755
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -22,6 +22,8 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
 #include <linux/mmc/card.h>
 
 #include <mach/sdhci.h>
@@ -36,6 +38,8 @@ struct tegra_sdhci_host {
 	struct sdhci_host *sdhci;
 	struct clk *clk;
 	int clk_enabled;
+	bool card_always_on;
+	u32 sdhci_ints;
 };
 
 static irqreturn_t carddetect_irq(int irq, void *data)
@@ -46,6 +50,14 @@ static irqreturn_t carddetect_irq(int irq, void *data)
 	return IRQ_HANDLED;
 };
 
+static void tegra_sdhci_status_notify_cb(int card_present, void *dev_id)
+{
+	struct sdhci_host *sdhci = (struct sdhci_host *)dev_id;
+	pr_debug("%s: card_present %d\n",
+		mmc_hostname(sdhci->mmc), card_present);
+	sdhci_card_detect_callback(sdhci);
+}
+
 static int tegra_sdhci_enable_dma(struct sdhci_host *host)
 {
 	return 0;
@@ -112,6 +124,7 @@ static int __devinit tegra_sdhci_probe(struct platform_device *pdev)
 
 	host = sdhci_priv(sdhci);
 	host->sdhci = sdhci;
+	host->card_always_on = (plat->power_gpio == -1) ? 1 : 0;
 
 	host->clk = clk_get(&pdev->dev, plat->clk_id);
 	if (IS_ERR(host->clk)) {
@@ -137,11 +150,17 @@ static int __devinit tegra_sdhci_probe(struct platform_device *pdev)
 			SDHCI_QUIRK_NO_HISPD_BIT |
 			SDHCI_QUIRK_8_BIT_DATA |
 			SDHCI_QUIRK_NO_VERSION_REG |
-			SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC |
-			SDHCI_QUIRK_NO_SDIO_IRQ;
+			SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC;
 
 	if (plat->force_hs != 0)
 		sdhci->quirks |= SDHCI_QUIRK_FORCE_HIGH_SPEED_MODE;
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+	mmc_set_embedded_sdio_data(sdhci->mmc,
+			&plat->cis,
+			&plat->cccr,
+			plat->funcs,
+			plat->num_funcs);
+#endif
 
 	rc = sdhci_add_host(sdhci);
 	if (rc)
@@ -156,6 +175,9 @@ static int __devinit tegra_sdhci_probe(struct platform_device *pdev)
 
 		if (rc)
 			goto err_remove_host;
+	} else if (plat->register_status_notify) {
+		plat->register_status_notify(
+			tegra_sdhci_status_notify_cb, sdhci);
 	}
 
 	if (plat->board_probe)
@@ -196,11 +218,95 @@ static int tegra_sdhci_remove(struct platform_device *pdev)
 	return 0;
 }
 
+
+#define is_card_sdio(_card) \
+((_card) && ((_card)->type == MMC_TYPE_SDIO))
+
 #ifdef CONFIG_PM
+
+
+static void tegra_sdhci_restore_interrupts(struct sdhci_host *sdhost)
+{
+	u32 ierr;
+	u32 clear = SDHCI_INT_ALL_MASK;
+	struct tegra_sdhci_host *host = sdhci_priv(sdhost);
+
+	/* enable required interrupts */
+	ierr = sdhci_readl(sdhost, SDHCI_INT_ENABLE);
+	ierr &= ~clear;
+	ierr |= host->sdhci_ints;
+	sdhci_writel(sdhost, ierr, SDHCI_INT_ENABLE);
+	sdhci_writel(sdhost, ierr, SDHCI_SIGNAL_ENABLE);
+
+	if ((host->sdhci_ints & SDHCI_INT_CARD_INT) &&
+		(sdhost->quirks & SDHCI_QUIRK_ENABLE_INTERRUPT_AT_BLOCK_GAP)) {
+		u8 gap_ctrl = sdhci_readb(sdhost, SDHCI_BLOCK_GAP_CONTROL);
+		gap_ctrl |= 0x8;
+		sdhci_writeb(sdhost, gap_ctrl, SDHCI_BLOCK_GAP_CONTROL);
+	}
+}
+
+static int tegra_sdhci_restore(struct sdhci_host *sdhost)
+{
+	unsigned long timeout;
+	u8 mask = SDHCI_RESET_ALL;
+
+	sdhci_writeb(sdhost, mask, SDHCI_SOFTWARE_RESET);
+
+	sdhost->clock = 0;
+
+	/* Wait max 100 ms */
+	timeout = 100;
+
+	/* hw clears the bit when it's done */
+	while (sdhci_readb(sdhost, SDHCI_SOFTWARE_RESET) & mask) {
+		if (timeout == 0) {
+			printk(KERN_ERR "%s: Reset 0x%x never completed.\n",
+				mmc_hostname(sdhost->mmc), (int)mask);
+			return -EIO;
+		}
+		timeout--;
+		mdelay(1);
+	}
+
+	tegra_sdhci_restore_interrupts(sdhost);
+	return 0;
+}
+
 static int tegra_sdhci_suspend(struct platform_device *pdev, pm_message_t state)
 {
 	struct tegra_sdhci_host *host = platform_get_drvdata(pdev);
-	int ret;
+	int ret = 0;
+
+	if (host->card_always_on && is_card_sdio(host->sdhci->mmc->card)) {
+		int div = 0;
+		u16 clk;
+		unsigned int clock = 100000;
+
+		if (device_may_wakeup(&pdev->dev)) {
+		        enable_irq_wake(host->sdhci->irq);
+		}
+
+		/* save interrupt status before suspending */
+		host->sdhci_ints = sdhci_readl(host->sdhci, SDHCI_INT_ENABLE);
+
+		/* reduce host controller clk and card clk to 100 KHz */
+		tegra_sdhci_set_clock(host->sdhci, clock);
+		sdhci_writew(host->sdhci, 0, SDHCI_CLOCK_CONTROL);
+
+		if (host->sdhci->max_clk > clock) {
+			div =  1 << (fls(host->sdhci->max_clk / clock) - 2);
+			if (div > 128)
+				div = 128;
+		}
+
+		clk = div << SDHCI_DIVIDER_SHIFT;
+		clk |= SDHCI_CLOCK_INT_EN | SDHCI_CLOCK_CARD_EN;
+		sdhci_writew(host->sdhci, clk, SDHCI_CLOCK_CONTROL);
+
+		return ret;
+	}
+
 
 	ret = sdhci_suspend_host(host->sdhci, state);
 	if (ret)
@@ -215,6 +321,26 @@ static int tegra_sdhci_resume(struct platform_device *pdev)
 	struct tegra_sdhci_host *host = platform_get_drvdata(pdev);
 	int ret;
 
+	if (host->card_always_on && is_card_sdio(host->sdhci->mmc->card)) {
+		int ret = 0;
+
+		if (device_may_wakeup(&pdev->dev)) {
+		        disable_irq_wake(host->sdhci->irq);
+		}
+
+		/* soft reset SD host controller and enable interrupts */
+		ret = tegra_sdhci_restore(host->sdhci);
+		if (ret) {
+			pr_err("%s: failed, error = %d\n", __func__, ret);
+			return ret;
+		}
+
+		mmiowb();
+		host->sdhci->mmc->ops->set_ios(host->sdhci->mmc,
+			&host->sdhci->mmc->ios);
+		return 0;
+	}
+
 	tegra_sdhci_enable_clock(host, 1);
 	ret = sdhci_resume_host(host->sdhci);
 	if (ret)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 7af27866c4ed..e4d155912812 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -251,7 +251,7 @@ struct sdhci_host {
 /* Controller write protect bit is broken. Assume no write protection */
 #define SDHCI_QUIRK_BROKEN_WRITE_PROTECT		(1<<30)
 /* Controller needs INTERRUPT_AT_BLOCK_GAP enabled to detect card interrupts */
-#define SDHCI_QUIRK_ENABLE_INTERRUPT_AT_BLOCK_GAP	(1<<31)
+#define SDHCI_QUIRK_ENABLE_INTERRUPT_AT_BLOCK_GAP	(1LL<<31)
 /* Controller should not program HIGH_SPEED_EN after switching to high speed */
 #define SDHCI_QUIRK_BROKEN_CTRL_HISPD			(1LL<<32)
 /* Controller supports 8-bit data width */
diff --git a/drivers/net/ppp_deflate.c b/drivers/net/ppp_deflate.c
index 695bc83e0cfd..bda70852c5ef 100644
--- a/drivers/net/ppp_deflate.c
+++ b/drivers/net/ppp_deflate.c
@@ -306,7 +306,7 @@ static void z_decomp_free(void *arg)
 
 	if (state) {
 		zlib_inflateEnd(&state->strm);
-		kfree(state->strm.workspace);
+		vfree(state->strm.workspace);
 		kfree(state);
 	}
 }
@@ -346,8 +346,7 @@ static void *z_decomp_alloc(unsigned char *options, int opt_len)
 
 	state->w_size         = w_size;
 	state->strm.next_out  = NULL;
-	state->strm.workspace = kmalloc(zlib_inflate_workspacesize(),
-					GFP_KERNEL|__GFP_REPEAT);
+	state->strm.workspace = vmalloc(zlib_inflate_workspacesize());
 	if (state->strm.workspace == NULL)
 		goto out_free;
 
diff --git a/drivers/net/wireless/bcm4329/Kconfig b/drivers/net/wireless/bcm4329/Kconfig
index ca5760d32385..0f07a7847acd 100644
--- a/drivers/net/wireless/bcm4329/Kconfig
+++ b/drivers/net/wireless/bcm4329/Kconfig
@@ -25,3 +25,43 @@ config BCM4329_NVRAM_PATH
 	default "/proc/calibration"
 	---help---
 	  Path to the calibration file.
+
+config BCM4329_WIFI_CONTROL_FUNC
+	bool "Use bcm4329_wlan device"
+	depends on BCM4329
+	default n
+	---help---
+	   Use this option to get various parameters from architecture specific
+	   bcm4329_wlan platform device. Say n if unsure.
+
+if BCM4329_WIFI_CONTROL_FUNC
+
+config BCM4329_DHD_USE_STATIC_BUF
+	bool "Use static buffer"
+	depends on BCM4329
+	default n
+	---help---
+	   Use static buffer from kernel heap allocated during bcm4329_wlan
+	   platform device creation.
+
+config BCM4329_HW_OOB
+	bool "Use out of band interrupt"
+	depends on BCM4329
+	default n
+	---help---
+	   Use out of band interrupt for wake on wireless.
+
+config BCM4329_OOB_INTR_ONLY
+	bool "Use out of band interrupt only"
+	depends on BCM4329
+	default n
+	---help---
+	   Use out of band interrupt for all interrupts(including SDIO interrupts).
+
+config BCM4329_GET_CUSTOM_MAC_ENABLE
+	bool "Use custom mac address"
+	depends on BCM4329
+	default n
+	---help---
+	   Use mac address provided by bcm4329_wlan platform device.
+endif
diff --git a/drivers/net/wireless/bcm4329/Makefile b/drivers/net/wireless/bcm4329/Makefile
index 3f49a643e8ff..bffe59160c54 100644
--- a/drivers/net/wireless/bcm4329/Makefile
+++ b/drivers/net/wireless/bcm4329/Makefile
@@ -3,13 +3,28 @@ DHDCFLAGS = -DLINUX -DBCMDRIVER -DBCMDONGLEHOST -DDHDTHREAD -DBCMWPA2         \
 	-DUNRELEASEDCHIP -Dlinux -DDHD_SDALIGN=64 -DMAX_HDR_READ=64           \
 	-DDHD_FIRSTREAD=64 -DDHD_GPL -DDHD_SCHED -DBDC -DTOE -DDHD_BCMEVENTS  \
 	-DSHOW_EVENTS -DBCMSDIO -DDHD_GPL -DBCMLXSDMMC -DBCMPLATFORM_BUS      \
-	-Wall -Wstrict-prototypes -Werror -DOOB_INTR_ONLY -DCUSTOMER_HW2      \
-	-DDHD_USE_STATIC_BUF -DMMC_SDIO_ABORT -DDHD_DEBUG_TRAP -DSOFTAP       \
-	-DEMBEDDED_PLATFORM -DARP_OFFLOAD_SUPPORT -DPKT_FILTER_SUPPORT        \
-	-DGET_CUSTOM_MAC_ENABLE -DSET_RANDOM_MAC_SOFTAP -DCSCAN -DHW_OOB      \
+	-Wall -Wstrict-prototypes -Werror -DCUSTOMER_HW2 -DMMC_SDIO_ABORT     \
+	-DDHD_DEBUG_TRAP -DSOFTAP -DEMBEDDED_PLATFORM -DARP_OFFLOAD_SUPPORT   \
+	-DPKT_FILTER_SUPPORT -DSET_RANDOM_MAC_SOFTAP -DCSCAN                  \
 	-DKEEP_ALIVE                                                          \
 	-Idrivers/net/wireless/bcm4329 -Idrivers/net/wireless/bcm4329/include
 
+ifeq ($(CONFIG_BCM4329_WIFI_CONTROL_FUNC),y)
+DHDCFLAGS += -DCONFIG_WIFI_CONTROL_FUNC
+endif
+ifeq ($(CONFIG_BCM4329_DHD_USE_STATIC_BUF),y)
+DHDCFLAGS += -DDHD_USE_STATIC_BUF
+endif
+ifeq ($(CONFIG_BCM4329_OOB_INTR_ONLY),y)
+DHDCFLAGS += -DOOB_INTR_ONLY
+endif
+ifeq ($(CONFIG_BCM4329_GET_CUSTOM_MAC_ENABLE),y)
+DHDCFLAGS += -DGET_CUSTOM_MAC_ENABLE
+endif
+ifeq ($(CONFIG_BCM4329_HW_OOB),y)
+DHDCFLAGS += -DHW_OOB
+endif
+
 DHDOFILES = dhd_linux.o linux_osl.o bcmutils.o dhd_common.o dhd_custom_gpio.o \
 	wl_iw.o siutils.o sbutils.o aiutils.o hndpmu.o bcmwifi.o dhd_sdio.o   \
 	dhd_linux_sched.o dhd_cdc.o bcmsdh_sdmmc.o bcmsdh.o bcmsdh_linux.o    \
diff --git a/drivers/net/wireless/bcm4329/dhd.h b/drivers/net/wireless/bcm4329/dhd.h
index 1ddf1ff61e70..41672672477e 100644..100755
--- a/drivers/net/wireless/bcm4329/dhd.h
+++ b/drivers/net/wireless/bcm4329/dhd.h
@@ -47,6 +47,10 @@
 #include <asm/uaccess.h>
 #include <asm/unaligned.h>
 
+#ifdef CONFIG_HAS_WAKELOCK
+#include <linux/wakelock.h>
+#endif
+
 /* The kernel threading is sdio-specific */
 #else /* LINUX */
 #define ENOMEM		1
@@ -167,6 +171,9 @@ typedef struct dhd_pub {
 	uint8 country_code[WLC_CNTRY_BUF_SZ];
 	char eventmask[WL_EVENTING_MASK_LEN];
 
+#ifdef CONFIG_HAS_WAKELOCK
+	struct wake_lock 	wow_wakelock;
+#endif
 } dhd_pub_t;
 
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP)
diff --git a/drivers/net/wireless/bcm4329/dhd_linux.c b/drivers/net/wireless/bcm4329/dhd_linux.c
index c7ef3edd908f..a052386f28a7 100644
--- a/drivers/net/wireless/bcm4329/dhd_linux.c
+++ b/drivers/net/wireless/bcm4329/dhd_linux.c
@@ -2153,6 +2153,10 @@ dhd_attach(osl_t *osh, struct dhd_bus *bus, uint bus_hdrlen)
 	register_pm_notifier(&dhd_sleep_pm_notifier);
 #endif /*  (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP) */
 
+#ifdef CONFIG_HAS_WAKELOCK
+	wake_lock_init(&dhd->pub.wow_wakelock, WAKE_LOCK_SUSPEND, "wow_wake_lock");
+#endif
+
 #ifdef CONFIG_HAS_EARLYSUSPEND
 	dhd->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 20;
 	dhd->early_suspend.suspend = dhd_early_suspend;
@@ -2500,6 +2504,10 @@ dhd_detach(dhd_pub_t *dhdp)
 			if (dhdp->prot)
 				dhd_prot_detach(dhdp);
 
+#ifdef CONFIG_HAS_WAKELOCK
+			wake_lock_destroy(&dhdp->wow_wakelock);
+#endif
+
 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP)
 			unregister_pm_notifier(&dhd_sleep_pm_notifier);
 #endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && defined(CONFIG_PM_SLEEP) */
diff --git a/drivers/net/wireless/bcm4329/dhd_sdio.c b/drivers/net/wireless/bcm4329/dhd_sdio.c
index f9b9eceb91c7..1742deaf74b0 100644
--- a/drivers/net/wireless/bcm4329/dhd_sdio.c
+++ b/drivers/net/wireless/bcm4329/dhd_sdio.c
@@ -58,6 +58,10 @@
 #include <dhdioctl.h>
 #include <sdiovar.h>
 
+#ifdef CONFIG_HAS_WAKELOCK
+#include <linux/wakelock.h>
+#endif
+
 #ifdef DHD_DEBUG
 #include <hndrte_cons.h>
 #endif /* DHD_DEBUG */
@@ -4122,6 +4126,9 @@ dhdsdio_dpc(dhd_bus_t *bus)
 
 	/* Handle host mailbox indication */
 	if (intstatus & I_HMB_HOST_INT) {
+#ifdef CONFIG_HAS_WAKELOCK
+		wake_lock_timeout(&bus->dhd->wow_wakelock, 3*HZ);
+#endif
 		intstatus &= ~I_HMB_HOST_INT;
 		intstatus |= dhdsdio_hostmail(bus);
 	}
@@ -4154,6 +4161,9 @@ dhdsdio_dpc(dhd_bus_t *bus)
 
 	/* On frame indication, read available frames */
 	if (PKT_AVAILABLE()) {
+#ifdef CONFIG_HAS_WAKELOCK
+		wake_lock_timeout(&bus->dhd->wow_wakelock, 3*HZ);
+#endif
 		framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
 		if (rxdone || bus->rxskip)
 			intstatus &= ~I_HMB_FRAME_IND;
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 07343568a12e..331395108649 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -109,6 +109,12 @@ config BATTERY_WM97XX
 	help
 	  Say Y to enable support for battery measured by WM97xx aux port.
 
+config BATTERY_BQ20Z75
+	tristate "TI BQ20Z75 Fuel gauge"
+	depends on I2C
+	help
+	 Say Y to include support for TI BQ20Z75 (I2C) fuel gauge chips.
+
 config BATTERY_BQ27x00
 	tristate "BQ27x00 battery driver"
 	depends on I2C
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index 10143aaf4ee3..69d76223ffe2 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -29,6 +29,7 @@ obj-$(CONFIG_BATTERY_OLPC)	+= olpc_battery.o
 obj-$(CONFIG_BATTERY_TOSA)	+= tosa_battery.o
 obj-$(CONFIG_BATTERY_COLLIE)	+= collie_battery.o
 obj-$(CONFIG_BATTERY_WM97XX)	+= wm97xx_battery.o
+obj-$(CONFIG_BATTERY_BQ20Z75)	+= bq20z75_battery.o
 obj-$(CONFIG_BATTERY_BQ27x00)	+= bq27x00_battery.o
 obj-$(CONFIG_BATTERY_DA9030)	+= da9030_battery.o
 obj-$(CONFIG_BATTERY_MAX17040)	+= max17040_battery.o
diff --git a/drivers/power/bq20z75_battery.c b/drivers/power/bq20z75_battery.c
new file mode 100644
index 000000000000..8d1dfc39a9e7
--- /dev/null
+++ b/drivers/power/bq20z75_battery.c
@@ -0,0 +1,610 @@
+/*
+ * drivers/power/bq20z75_battery.c
+ *
+ * Gas Gauge driver for TI's BQ20Z75
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/debugfs.h>
+#include <linux/power_supply.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/interrupt.h>
+
+#include <mach/gpio.h>
+
+enum {
+	REG_MANUFACTURER_DATA,
+	REG_TEMPERATURE,
+	REG_VOLTAGE,
+	REG_CURRENT,
+	REG_TIME_TO_EMPTY,
+	REG_TIME_TO_FULL,
+	REG_STATUS,
+	REG_CYCLE_COUNT,
+	REG_CAPACITY,
+	REG_SERIAL_NUMBER,
+	REG_REMAINING_CAPACITY,
+	REG_FULL_CHARGE_CAPACITY,
+	REG_DESIGN_CAPACITY,
+	REG_DESIGN_VOLTAGE,
+	REG_MAX
+};
+
+#define BATTERY_MANUFACTURER_SIZE	12
+#define BATTERY_NAME_SIZE		8
+
+/* manufacturer access defines */
+#define MANUFACTURER_ACCESS_STATUS	0x0006
+#define MANUFACTURER_ACCESS_SLEEP	0x0011
+
+/* battery status value bits */
+#define BATTERY_INIT_DONE		0x80
+#define BATTERY_DISCHARGING		0x40
+#define BATTERY_FULL_CHARGED		0x20
+#define BATTERY_FULL_DISCHARGED		0x10
+
+#define BATTERY_POLL_PERIOD		30000
+
+#define BQ20Z75_DATA(_psp, _addr, _min_value, _max_value)	\
+	{							\
+		.psp = POWER_SUPPLY_PROP_##_psp,		\
+		.addr = _addr,					\
+		.min_value = _min_value,			\
+		.max_value = _max_value,			\
+	}
+
+static struct bq20z75_device_data {
+	enum power_supply_property psp;
+	u8 addr;
+	int min_value;
+	int max_value;
+} bq20z75_data[] = {
+	[REG_MANUFACTURER_DATA] = BQ20Z75_DATA(PRESENT, 0x00, 0, 65535),
+	[REG_TEMPERATURE]       = BQ20Z75_DATA(TEMP, 0x08, 0, 65535),
+	[REG_VOLTAGE]           = BQ20Z75_DATA(VOLTAGE_NOW, 0x09, 0, 20000),
+	[REG_CURRENT]           = BQ20Z75_DATA(CURRENT_NOW, 0x0A, -32768, 32767),
+	[REG_CAPACITY]          = BQ20Z75_DATA(CAPACITY, 0x0e, 0, 100),
+	[REG_REMAINING_CAPACITY] = BQ20Z75_DATA(ENERGY_NOW, 0x0F, 0, 65535),
+	[REG_FULL_CHARGE_CAPACITY] = BQ20Z75_DATA(ENERGY_FULL, 0x10, 0, 65535),
+	[REG_TIME_TO_EMPTY]     = BQ20Z75_DATA(TIME_TO_EMPTY_AVG, 0x12, 0, 65535),
+	[REG_TIME_TO_FULL]      = BQ20Z75_DATA(TIME_TO_FULL_AVG, 0x13, 0, 65535),
+	[REG_STATUS]            = BQ20Z75_DATA(STATUS, 0x16, 0, 65535),
+	[REG_CYCLE_COUNT]       = BQ20Z75_DATA(CYCLE_COUNT, 0x17, 0, 65535),
+	[REG_DESIGN_CAPACITY]   = BQ20Z75_DATA(ENERGY_FULL_DESIGN, 0x18, 0, 65535),
+	[REG_DESIGN_VOLTAGE]    = BQ20Z75_DATA(VOLTAGE_MAX_DESIGN, 0x19, 0, 65535),
+	[REG_SERIAL_NUMBER]     = BQ20Z75_DATA(SERIAL_NUMBER, 0x1C, 0, 65535),
+};
+
+static enum power_supply_property bq20z75_battery_properties[] = {
+	POWER_SUPPLY_PROP_STATUS,
+	POWER_SUPPLY_PROP_HEALTH,
+	POWER_SUPPLY_PROP_PRESENT,
+	POWER_SUPPLY_PROP_TECHNOLOGY,
+	POWER_SUPPLY_PROP_CYCLE_COUNT,
+	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+	POWER_SUPPLY_PROP_CURRENT_NOW,
+	POWER_SUPPLY_PROP_CAPACITY,
+	POWER_SUPPLY_PROP_TEMP,
+	POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG,
+	POWER_SUPPLY_PROP_TIME_TO_FULL_AVG,
+	POWER_SUPPLY_PROP_SERIAL_NUMBER,
+	POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN,
+	POWER_SUPPLY_PROP_ENERGY_NOW,
+	POWER_SUPPLY_PROP_ENERGY_FULL,
+	POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN,
+};
+
+static enum power_supply_property bq20z75_ac_properties[] = {
+	POWER_SUPPLY_PROP_ONLINE,
+};
+
+static char *power_supplied_to[] = {
+	"battery",
+};
+
+static int bq20z75_bat_get_property(struct power_supply *psy,
+	enum power_supply_property psp, union power_supply_propval *val);
+static int bq20z75_ac_get_property(struct power_supply *psy,
+	enum power_supply_property psp, union power_supply_propval *val);
+
+enum supply_type {
+	SUPPLY_TYPE_BATTERY = 0,
+	SUPPLY_TYPE_AC,
+};
+
+static struct power_supply bq20z75_supply[] = {
+	[SUPPLY_TYPE_BATTERY] = {
+		.name		= "battery",
+		.type		= POWER_SUPPLY_TYPE_BATTERY,
+		.properties	= bq20z75_battery_properties,
+		.num_properties	= ARRAY_SIZE(bq20z75_battery_properties),
+		.get_property	= bq20z75_bat_get_property,
+	},
+	[SUPPLY_TYPE_AC] = {
+		.name = "ac",
+		.type = POWER_SUPPLY_TYPE_MAINS,
+		.supplied_to = power_supplied_to,
+		.num_supplicants = ARRAY_SIZE(power_supplied_to),
+		.properties = bq20z75_ac_properties,
+		.num_properties = ARRAY_SIZE(bq20z75_ac_properties),
+		.get_property = bq20z75_ac_get_property,
+	},
+};
+
+static struct bq20z75_device_info {
+	struct timer_list	battery_poll_timer;
+	struct i2c_client	*client;
+	int irq;
+	bool battery_present;
+} *bq20z75_device;
+
+static int bq20z75_get_ac_status(void)
+{
+	int charger_gpio = irq_to_gpio(bq20z75_device->irq);
+	return !gpio_get_value(charger_gpio);
+}
+
+static int bq20z75_ac_get_property(struct power_supply *psy,
+	enum power_supply_property psp,
+	union power_supply_propval *val)
+{
+	switch (psp) {
+	case POWER_SUPPLY_PROP_ONLINE:
+		val->intval = bq20z75_get_ac_status();
+		break;
+	default:
+		dev_err(&bq20z75_device->client->dev,
+			"%s: INVALID property\n", __func__);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int bq20z75_get_battery_presence_and_health(
+	struct i2c_client *client, enum power_supply_property psp,
+	union power_supply_propval *val)
+{
+	s32 ret;
+
+	/* Write to ManufacturerAccess with
+	 * ManufacturerAccess command and then
+	 * read the status */
+	ret = i2c_smbus_write_word_data(client,
+		bq20z75_data[REG_MANUFACTURER_DATA].addr,
+		MANUFACTURER_ACCESS_STATUS);
+	if (ret < 0)
+		return ret;
+
+
+	ret = i2c_smbus_read_word_data(client,
+		bq20z75_data[REG_MANUFACTURER_DATA].addr);
+	if (ret < 0)
+		return ret;
+
+	if (ret < bq20z75_data[REG_MANUFACTURER_DATA].min_value ||
+	    ret > bq20z75_data[REG_MANUFACTURER_DATA].max_value) {
+		val->intval = 0;
+		return 0;
+	}
+
+	/* Mask the upper nibble of 2nd byte and
+	 * lower byte of response then
+	 * shift the result by 8 to get status*/
+	ret &= 0x0F00;
+	ret >>= 8;
+	if (psp == POWER_SUPPLY_PROP_PRESENT) {
+		if (ret == 0x0F)
+			/* battery removed */
+			val->intval = 0;
+		else
+			val->intval = 1;
+	} else if (psp == POWER_SUPPLY_PROP_HEALTH) {
+		if (ret == 0x09)
+			val->intval = POWER_SUPPLY_HEALTH_UNSPEC_FAILURE;
+		else if (ret == 0x0B)
+			val->intval = POWER_SUPPLY_HEALTH_OVERHEAT;
+		else if (ret == 0x0C)
+			val->intval = POWER_SUPPLY_HEALTH_DEAD;
+		else
+			val->intval = POWER_SUPPLY_HEALTH_GOOD;
+	}
+
+	return 0;
+}
+
+static int bq20z75_get_battery_property(struct i2c_client *client, int reg_offset,
+	enum power_supply_property psp, union power_supply_propval *val)
+{
+	s32 ret;
+	int ac_status;
+
+	ret = i2c_smbus_read_word_data(client, bq20z75_data[reg_offset].addr);
+	if (ret < 0) {
+		dev_err(&client->dev,
+			"%s: i2c read for %d failed\n", __func__, reg_offset);
+		return -EINVAL;
+	}
+
+	/* returned values are 16 bit */
+	if (bq20z75_data[reg_offset].min_value < 0)
+		ret = (s16)ret;
+
+	if (ret >= bq20z75_data[reg_offset].min_value &&
+	    ret <= bq20z75_data[reg_offset].max_value) {
+		val->intval = ret;
+		if (psp == POWER_SUPPLY_PROP_STATUS) {
+			ac_status = bq20z75_get_ac_status();
+			val->intval = ac_status ?
+				POWER_SUPPLY_STATUS_CHARGING :
+				POWER_SUPPLY_STATUS_DISCHARGING;
+
+			if (ret & BATTERY_FULL_CHARGED)
+				val->intval = POWER_SUPPLY_STATUS_FULL;
+		}
+	} else {
+		if (psp == POWER_SUPPLY_PROP_STATUS)
+			val->intval = POWER_SUPPLY_STATUS_UNKNOWN;
+		else
+			val->intval = 0;
+	}
+
+	return 0;
+}
+
+static void  bq20z75_unit_adjustment(struct i2c_client *client,
+	enum power_supply_property psp, union power_supply_propval *val)
+{
+#define BASE_UNIT_CONVERSION		1000
+#define BATTERY_MODE_CAP_MULT_WATT	(10 * BASE_UNIT_CONVERSION)
+#define TIME_UNIT_CONVERSION		600
+#define TEMP_KELVIN_TO_CELCIUS		2731
+	switch (psp) {
+	case POWER_SUPPLY_PROP_ENERGY_NOW:
+	case POWER_SUPPLY_PROP_ENERGY_FULL:
+	case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN:
+		val->intval *= BATTERY_MODE_CAP_MULT_WATT;
+		break;
+
+	case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+	case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+	case POWER_SUPPLY_PROP_CURRENT_NOW:
+		val->intval *= BASE_UNIT_CONVERSION;
+		break;
+
+	case POWER_SUPPLY_PROP_TEMP:
+		/* bq20z75 provides battery tempreture in 0.1°K
+		 * so convert it to 0.1°C */
+		val->intval -= TEMP_KELVIN_TO_CELCIUS;
+		break;
+
+	case POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG:
+	case POWER_SUPPLY_PROP_TIME_TO_FULL_AVG:
+		val->intval *= TIME_UNIT_CONVERSION;
+		break;
+
+	default:
+		dev_dbg(&client->dev,
+			"%s: no need for unit conversion %d\n", __func__, psp);
+	}
+}
+
+static int bq20z75_get_battery_capacity(struct i2c_client *client,
+	int reg_offset, enum power_supply_property psp,
+	union power_supply_propval *val)
+{
+	s32 ret;
+
+	ret = i2c_smbus_read_word_data(client, bq20z75_data[reg_offset].addr);
+	if (ret < 0)
+		return ret;
+
+	if (psp == POWER_SUPPLY_PROP_CAPACITY) {
+		/* bq20z75 spec says that this can be >100 %
+		* even if max value is 100 % */
+		val->intval = min(ret, 100);
+	} else
+		val->intval = ret;
+
+	return 0;
+}
+
+static char bq20z75_serial[5];
+static int bq20z75_get_battery_serial_number(struct i2c_client *client,
+	union power_supply_propval *val)
+{
+	int ret;
+
+	ret = i2c_smbus_read_word_data(client,
+		bq20z75_data[REG_SERIAL_NUMBER].addr);
+	if (ret < 0)
+		return ret;
+
+	ret = sprintf(bq20z75_serial, "%04x", ret);
+	val->strval = bq20z75_serial;
+
+	return 0;
+}
+
+static int bq20z75_bat_get_property(struct power_supply *psy,
+	enum power_supply_property psp,
+	union power_supply_propval *val)
+{
+	int count;
+	int ret;
+	struct i2c_client *client = bq20z75_device->client;
+
+	switch (psp) {
+	case POWER_SUPPLY_PROP_PRESENT:
+	case POWER_SUPPLY_PROP_HEALTH:
+		ret = bq20z75_get_battery_presence_and_health(client, psp, val);
+		if (ret)
+			return ret;
+		break;
+
+	case POWER_SUPPLY_PROP_TECHNOLOGY:
+		val->intval = POWER_SUPPLY_TECHNOLOGY_LION;
+		break;
+
+	case POWER_SUPPLY_PROP_ENERGY_NOW:
+	case POWER_SUPPLY_PROP_ENERGY_FULL:
+	case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN:
+	case POWER_SUPPLY_PROP_CAPACITY:
+		for (count = 0; count < ARRAY_SIZE(bq20z75_data); count++) {
+			if (psp == bq20z75_data[count].psp)
+				break;
+		}
+
+		ret = bq20z75_get_battery_capacity(client, count, psp, val);
+		if (ret)
+			return ret;
+
+		break;
+
+	case POWER_SUPPLY_PROP_SERIAL_NUMBER:
+		ret = bq20z75_get_battery_serial_number(client, val);
+		if (ret)
+			return ret;
+		break;
+
+	case POWER_SUPPLY_PROP_STATUS:
+	case POWER_SUPPLY_PROP_CYCLE_COUNT:
+	case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+	case POWER_SUPPLY_PROP_CURRENT_NOW:
+	case POWER_SUPPLY_PROP_TEMP:
+	case POWER_SUPPLY_PROP_TIME_TO_EMPTY_AVG:
+	case POWER_SUPPLY_PROP_TIME_TO_FULL_AVG:
+	case POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN:
+		for (count = 0; count < REG_MAX; count++) {
+			if (psp == bq20z75_data[count].psp)
+				break;
+		}
+
+		ret = bq20z75_get_battery_property(client, count, psp, val);
+		if (ret)
+			return ret;
+
+		break;
+
+	default:
+		dev_err(&bq20z75_device->client->dev,
+			"%s: INVALID property\n", __func__);
+		return -EINVAL;
+	}
+
+	/* Convert units to match requirements for power supply class */
+	bq20z75_unit_adjustment(client, psp, val);
+
+	dev_dbg(&client->dev,
+		"%s: property = %d, value = %d\n", __func__, psp, val->intval);
+
+	return 0;
+}
+
+static irqreturn_t ac_present_irq(int irq, void *data)
+{
+	power_supply_changed(&bq20z75_supply[SUPPLY_TYPE_AC]);
+	power_supply_changed(&bq20z75_supply[SUPPLY_TYPE_BATTERY]);
+	return IRQ_HANDLED;
+}
+
+static void battery_poll_timer_func(unsigned long unused)
+{
+	power_supply_changed(&bq20z75_supply[SUPPLY_TYPE_BATTERY]);
+	power_supply_changed(&bq20z75_supply[SUPPLY_TYPE_AC]);
+	mod_timer(&bq20z75_device->battery_poll_timer,
+		jiffies + msecs_to_jiffies(BATTERY_POLL_PERIOD));
+}
+
+static int bq20z75_probe(struct i2c_client *client,
+	const struct i2c_device_id *id)
+{
+	int rc, i, flags;
+	int supply_index = SUPPLY_TYPE_BATTERY;
+
+	bq20z75_device = kzalloc(sizeof(*bq20z75_device), GFP_KERNEL);
+	if (!bq20z75_device)
+		return -ENOMEM;
+
+	bq20z75_device->client = client;
+	flags = bq20z75_device->client->flags;
+	bq20z75_device->client->flags &= ~I2C_M_IGNORE_NAK;
+
+	rc = i2c_smbus_read_word_data(bq20z75_device->client,
+		bq20z75_data[REG_SERIAL_NUMBER].addr);
+	if (rc < 0) {
+		dev_err(&bq20z75_device->client->dev,
+			"%s: no battery present(%d)\n", __func__, rc);
+		supply_index = SUPPLY_TYPE_AC;
+	} else {
+		bq20z75_device->battery_present = true;
+	}
+
+	bq20z75_device->client->flags = flags;
+	bq20z75_device->irq = client->irq;
+	i2c_set_clientdata(client, bq20z75_device);
+
+	rc = request_threaded_irq(bq20z75_device->irq, NULL,
+		ac_present_irq,
+		IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+		"ac_present", bq20z75_device);
+	if (rc < 0) {
+		dev_err(&bq20z75_device->client->dev,
+			"%s: request_irq failed(%d)\n", __func__, rc);
+		goto fail_irq;
+	}
+
+	for (i = supply_index; i < ARRAY_SIZE(bq20z75_supply); i++) {
+		rc = power_supply_register(&client->dev,
+			&bq20z75_supply[i]);
+		if (rc) {
+			dev_err(&bq20z75_device->client->dev,
+				"%s: Failed to register power supply\n",
+				 __func__);
+			goto fail_power_register;
+		}
+	}
+
+	if (bq20z75_device->battery_present) {
+		setup_timer(&bq20z75_device->battery_poll_timer,
+			battery_poll_timer_func, 0);
+		mod_timer(&bq20z75_device->battery_poll_timer,
+			jiffies + msecs_to_jiffies(BATTERY_POLL_PERIOD));
+	}
+
+	dev_info(&bq20z75_device->client->dev, "driver registered\n");
+	return 0;
+
+fail_power_register:
+	while (i--)
+		power_supply_unregister(&bq20z75_supply[i]);
+	free_irq(bq20z75_device->irq, bq20z75_device);
+fail_irq:
+	kfree(bq20z75_device);
+	return rc;
+}
+
+static int bq20z75_remove(struct i2c_client *client)
+{
+	struct bq20z75_device_info *bq20z75_device =
+		i2c_get_clientdata(client);
+	int supply_index = 0, i;
+
+	if (bq20z75_device->battery_present)
+		del_timer_sync(&bq20z75_device->battery_poll_timer);
+	else
+		supply_index = SUPPLY_TYPE_AC;
+
+	for (i = supply_index; i < ARRAY_SIZE(bq20z75_supply); i++)
+		power_supply_unregister(&bq20z75_supply[i]);
+
+	kfree(bq20z75_device);
+
+	return 0;
+}
+
+#if defined (CONFIG_PM)
+static int bq20z75_suspend(struct i2c_client *client,
+	pm_message_t state)
+{
+	s32 ret;
+	struct bq20z75_device_info *bq20z75_device =
+		i2c_get_clientdata(client);
+
+	if (!bq20z75_device->battery_present)
+		return 0;
+
+	del_timer_sync(&bq20z75_device->battery_poll_timer);
+
+	/* write to manufacture access with sleep command */
+	ret = i2c_smbus_write_word_data(bq20z75_device->client,
+		bq20z75_data[REG_MANUFACTURER_DATA].addr,
+		MANUFACTURER_ACCESS_SLEEP);
+	if (ret < 0) {
+		dev_err(&bq20z75_device->client->dev,
+			"%s: i2c write for %d failed\n",
+			__func__, MANUFACTURER_ACCESS_SLEEP);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* any smbus transaction will wake up bq20z75 */
+static int bq20z75_resume(struct i2c_client *client)
+{
+	struct bq20z75_device_info *bq20z75_device =
+		i2c_get_clientdata(client);
+
+	if (!bq20z75_device->battery_present)
+		return 0;
+
+	setup_timer(&bq20z75_device->battery_poll_timer,
+		battery_poll_timer_func, 0);
+	mod_timer(&bq20z75_device->battery_poll_timer,
+		jiffies + msecs_to_jiffies(BATTERY_POLL_PERIOD));
+	return 0;
+}
+#endif
+
+static const struct i2c_device_id bq20z75_id[] = {
+	{ "bq20z75-battery", 0 },
+	{},
+};
+
+static struct i2c_driver bq20z75_battery_driver = {
+	.probe		= bq20z75_probe,
+	.remove		= bq20z75_remove,
+#if defined (CONFIG_PM)
+	.suspend	= bq20z75_suspend,
+	.resume		= bq20z75_resume,
+#endif
+	.id_table	= bq20z75_id,
+	.driver = {
+		.name	= "bq20z75-battery",
+	},
+};
+
+static int __init bq20z75_battery_init(void)
+{
+	int ret;
+
+	ret = i2c_add_driver(&bq20z75_battery_driver);
+	if (ret)
+		dev_err(&bq20z75_device->client->dev,
+			"%s: i2c_add_driver failed\n", __func__);
+
+	return ret;
+}
+module_init(bq20z75_battery_init);
+
+static void __exit bq20z75_battery_exit(void)
+{
+	i2c_del_driver(&bq20z75_battery_driver);
+}
+module_exit(bq20z75_battery_exit);
+
+MODULE_AUTHOR("NVIDIA Corporation");
+MODULE_DESCRIPTION("BQ20z75 battery monitor driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 172951bf23a4..82fba419f2f5 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -108,6 +108,22 @@ config REGULATOR_MAX8998
 	  via I2C bus. The provided regulator is suitable for S3C6410
 	  and S5PC1XX chips to control VCC_CORE and VCC_USIM voltages.
 
+config REGULATOR_MAX8907C
+	tristate "Maxim 8907C voltage regulator"
+	depends on MFD_MAX8907C
+	help
+	  This driver controls a Maxim 8907C voltage output regulator
+	  via I2C bus. The provided regulator is suitable for Tegra
+	  chip to control Step-Down DC-DC and LDOs.
+
+config REGULATOR_MAX8952
+	tristate "Maxim 8952 voltage regulator"
+	depends on I2C
+	help
+	  This driver controls a Maxim 8952 voltage output regulator
+	  via I2C bus. The provided regulator is suitable for Tegra
+	  chip to control Step-Down Regulator.
+
 config REGULATOR_TWL4030
 	bool "TI TWL4030/TWL5030/TWL6030/TPS695x0 PMIC"
 	depends on TWL4030_CORE
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 8285fd832e16..13ab9f9b09a0 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -18,6 +18,8 @@ obj-$(CONFIG_REGULATOR_MAX8649)	+= max8649.o
 obj-$(CONFIG_REGULATOR_MAX8660) += max8660.o
 obj-$(CONFIG_REGULATOR_MAX8925) += max8925-regulator.o
 obj-$(CONFIG_REGULATOR_MAX8998) += max8998.o
+obj-$(CONFIG_REGULATOR_MAX8907C) += max8907c-regulator.o
+obj-$(CONFIG_REGULATOR_MAX8952) += max8952.o
 obj-$(CONFIG_REGULATOR_WM831X) += wm831x-dcdc.o
 obj-$(CONFIG_REGULATOR_WM831X) += wm831x-isink.o
 obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o
diff --git a/drivers/regulator/max8907c-regulator.c b/drivers/regulator/max8907c-regulator.c
new file mode 100644
index 000000000000..925f161d9922
--- /dev/null
+++ b/drivers/regulator/max8907c-regulator.c
@@ -0,0 +1,421 @@
+/*
+ * max8907c-regulator.c -- support regulators in max8907c
+ *
+ * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/mfd/max8907c.h>
+#include <linux/regulator/max8907c-regulator.h>
+
+#define MAX8907C_II2RR_VERSION_MASK	0xF0
+#define MAX8907C_II2RR_VERSION_REV_A	0x00
+#define MAX8907C_II2RR_VERSION_REV_B	0x10
+#define MAX8907C_II2RR_VERSION_REV_C	0x30
+
+#define MAX8907C_REGULATOR_CNT (ARRAY_SIZE(max8907c_regulators))
+
+struct max8907c_regulator_info {
+	u32 min_uV;
+	u32 max_uV;
+	u32 step_uV;
+	u8 reg_base;
+	struct regulator_desc desc;
+	struct i2c_client *i2c;
+};
+
+#define REG_LDO(ids, base, min, max, step) \
+	{ \
+		.min_uV = (min), \
+		.max_uV = (max), \
+		.step_uV = (step), \
+		.reg_base = (base), \
+		.desc = { \
+			.name = #ids, \
+			.id = MAX8907C_##ids, \
+			.n_voltages = ((max) - (min)) / (step) + 1, \
+			.ops = &max8907c_ldo_ops, \
+			.type = REGULATOR_VOLTAGE, \
+			.owner = THIS_MODULE, \
+		}, \
+	}
+
+#define REG_FIXED(ids, voltage) \
+	{ \
+		.min_uV = (voltage), \
+		.max_uV = (voltage), \
+		.desc = { \
+			.name = #ids, \
+			.id = MAX8907C_##ids, \
+			.n_voltages = 1, \
+			.ops = &max8907c_fixed_ops, \
+			.type = REGULATOR_VOLTAGE, \
+			.owner = THIS_MODULE, \
+		}, \
+	}
+
+#define REG_OUT5V(ids, base, voltage) \
+	{ \
+		.min_uV = (voltage), \
+		.max_uV = (voltage), \
+		.reg_base = (base), \
+		.desc = { \
+			.name = #ids, \
+			.id = MAX8907C_##ids, \
+			.n_voltages = 1, \
+			.ops = &max8907c_out5v_ops, \
+			.type = REGULATOR_VOLTAGE, \
+			.owner = THIS_MODULE, \
+		}, \
+	}
+
+#define REG_BBAT(ids, base, min, max, step) \
+	{ \
+		.min_uV = (min), \
+		.max_uV = (max), \
+		.step_uV = (step), \
+		.reg_base = (base), \
+		.desc = { \
+			.name = #ids, \
+			.id = MAX8907C_##ids, \
+			.n_voltages = ((max) - (min)) / (step) + 1, \
+			.ops = &max8907c_bbat_ops, \
+			.type = REGULATOR_VOLTAGE, \
+			.owner = THIS_MODULE, \
+		}, \
+	}
+
+#define REG_WLED(ids, base, voltage) \
+	{ \
+		.min_uV = (voltage), \
+		.max_uV = (voltage), \
+		.reg_base = (base), \
+		.desc = { \
+			.name = #ids, \
+			.id = MAX8907C_##ids, \
+			.n_voltages = 1, \
+			.ops = &max8907c_wled_ops, \
+			.type = REGULATOR_CURRENT, \
+			.owner = THIS_MODULE, \
+		}, \
+	}
+
+#define LDO_750_50(id, base) REG_LDO(id, (base), 750000, 3900000, 50000)
+#define LDO_650_25(id, base) REG_LDO(id, (base), 650000, 2225000, 25000)
+
+static int max8907c_regulator_list_voltage(struct regulator_dev *dev,
+					   unsigned index);
+static int max8907c_regulator_ldo_set_voltage(struct regulator_dev *dev,
+					      int min_uV, int max_uV);
+static int max8907c_regulator_bbat_set_voltage(struct regulator_dev *dev,
+					       int min_uV, int max_uV);
+static int max8907c_regulator_ldo_get_voltage(struct regulator_dev *dev);
+static int max8907c_regulator_fixed_get_voltage(struct regulator_dev *dev);
+static int max8907c_regulator_bbat_get_voltage(struct regulator_dev *dev);
+static int max8907c_regulator_wled_set_current_limit(struct regulator_dev *dev,
+						     int min_uA, int max_uA);
+static int max8907c_regulator_wled_get_current_limit(struct regulator_dev *dev);
+static int max8907c_regulator_ldo_enable(struct regulator_dev *dev);
+static int max8907c_regulator_out5v_enable(struct regulator_dev *dev);
+static int max8907c_regulator_ldo_disable(struct regulator_dev *dev);
+static int max8907c_regulator_out5v_disable(struct regulator_dev *dev);
+static int max8907c_regulator_ldo_is_enabled(struct regulator_dev *dev);
+static int max8907c_regulator_out5v_is_enabled(struct regulator_dev *dev);
+
+static struct regulator_ops max8907c_ldo_ops = {
+	.list_voltage = max8907c_regulator_list_voltage,
+	.set_voltage = max8907c_regulator_ldo_set_voltage,
+	.get_voltage = max8907c_regulator_ldo_get_voltage,
+	.enable = max8907c_regulator_ldo_enable,
+	.disable = max8907c_regulator_ldo_disable,
+	.is_enabled = max8907c_regulator_ldo_is_enabled,
+};
+
+static struct regulator_ops max8907c_fixed_ops = {
+	.list_voltage = max8907c_regulator_list_voltage,
+	.get_voltage = max8907c_regulator_fixed_get_voltage,
+};
+
+static struct regulator_ops max8907c_out5v_ops = {
+	.list_voltage = max8907c_regulator_list_voltage,
+	.get_voltage = max8907c_regulator_fixed_get_voltage,
+	.enable = max8907c_regulator_out5v_enable,
+	.disable = max8907c_regulator_out5v_disable,
+	.is_enabled = max8907c_regulator_out5v_is_enabled,
+};
+
+static struct regulator_ops max8907c_bbat_ops = {
+	.list_voltage = max8907c_regulator_list_voltage,
+	.set_voltage = max8907c_regulator_bbat_set_voltage,
+	.get_voltage = max8907c_regulator_bbat_get_voltage,
+};
+
+static struct regulator_ops max8907c_wled_ops = {
+	.list_voltage = max8907c_regulator_list_voltage,
+	.set_current_limit = max8907c_regulator_wled_set_current_limit,
+	.get_current_limit = max8907c_regulator_wled_get_current_limit,
+	.get_voltage = max8907c_regulator_fixed_get_voltage,
+};
+
+static struct max8907c_regulator_info max8907c_regulators[] = {
+	REG_LDO(SD1, MAX8907C_REG_SDCTL1, 650000, 2225000, 25000),
+	REG_LDO(SD2, MAX8907C_REG_SDCTL2, 637500, 1425000, 12500),
+	REG_LDO(SD3, MAX8907C_REG_SDCTL3, 750000, 3900000, 50000),
+	LDO_750_50(LDO1, MAX8907C_REG_LDOCTL1),
+	LDO_650_25(LDO2, MAX8907C_REG_LDOCTL2),
+	LDO_650_25(LDO3, MAX8907C_REG_LDOCTL3),
+	LDO_750_50(LDO4, MAX8907C_REG_LDOCTL4),
+	LDO_750_50(LDO5, MAX8907C_REG_LDOCTL5),
+	LDO_750_50(LDO6, MAX8907C_REG_LDOCTL6),
+	LDO_750_50(LDO7, MAX8907C_REG_LDOCTL7),
+	LDO_750_50(LDO8, MAX8907C_REG_LDOCTL8),
+	LDO_750_50(LDO9, MAX8907C_REG_LDOCTL9),
+	LDO_750_50(LDO10, MAX8907C_REG_LDOCTL10),
+	LDO_750_50(LDO11, MAX8907C_REG_LDOCTL11),
+	LDO_750_50(LDO12, MAX8907C_REG_LDOCTL12),
+	LDO_750_50(LDO13, MAX8907C_REG_LDOCTL13),
+	LDO_750_50(LDO14, MAX8907C_REG_LDOCTL14),
+	LDO_750_50(LDO15, MAX8907C_REG_LDOCTL15),
+	LDO_750_50(LDO16, MAX8907C_REG_LDOCTL16),
+	LDO_650_25(LDO17, MAX8907C_REG_LDOCTL17),
+	LDO_650_25(LDO18, MAX8907C_REG_LDOCTL18),
+	LDO_750_50(LDO19, MAX8907C_REG_LDOCTL19),
+	LDO_750_50(LDO20, MAX8907C_REG_LDOCTL20),
+	REG_OUT5V(OUT5V, MAX8907C_REG_OUT5VEN, 5000000),
+	REG_OUT5V(OUT33V, MAX8907C_REG_OUT33VEN, 3300000),
+	REG_BBAT(BBAT, MAX8907C_REG_BBAT_CNFG, 2400000, 3000000, 200000),
+	REG_FIXED(SDBY, 1200000),
+	REG_FIXED(VRTC, 3300000),
+	REG_WLED(WLED, MAX8907C_REG_ILED_CNTL, 0),
+};
+
+static int max8907c_regulator_list_voltage(struct regulator_dev *rdev,
+					   unsigned index)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+
+	return info->min_uV + info->step_uV * index;
+}
+
+static int max8907c_regulator_ldo_set_voltage(struct regulator_dev *rdev,
+					      int min_uV, int max_uV)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+	int val;
+
+	if (min_uV < info->min_uV || max_uV > info->max_uV)
+		return -EDOM;
+
+	val = (min_uV - info->min_uV) / info->step_uV;
+
+	return max8907c_reg_write(info->i2c, info->reg_base + MAX8907C_VOUT, val);
+}
+
+static int max8907c_regulator_bbat_set_voltage(struct regulator_dev *rdev,
+					       int min_uV, int max_uV)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+	int val;
+
+	if (min_uV < info->min_uV || max_uV > info->max_uV)
+		return -EDOM;
+
+	val = (min_uV - info->min_uV) / info->step_uV;
+
+	return max8907c_set_bits(info->i2c, info->reg_base, MAX8907C_MASK_VBBATTCV,
+				 val);
+}
+
+static int max8907c_regulator_ldo_get_voltage(struct regulator_dev *rdev)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+	int val;
+
+	val = max8907c_reg_read(info->i2c, info->reg_base + MAX8907C_VOUT);
+	return val * info->step_uV + info->min_uV;
+}
+
+static int max8907c_regulator_fixed_get_voltage(struct regulator_dev *rdev)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+
+	return info->min_uV;
+}
+
+static int max8907c_regulator_bbat_get_voltage(struct regulator_dev *rdev)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+	int val;
+
+	val =
+	    max8907c_reg_read(info->i2c, info->reg_base) & MAX8907C_MASK_VBBATTCV;
+	return val * info->step_uV + info->min_uV;
+}
+
+static int max8907c_regulator_wled_set_current_limit(struct regulator_dev *rdev,
+						     int min_uA, int max_uA)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+
+	if (min_uA > 25500)
+		return -EDOM;
+
+	return max8907c_reg_write(info->i2c, info->reg_base, min_uA / 100);
+}
+
+static int max8907c_regulator_wled_get_current_limit(struct regulator_dev *rdev)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+	int val;
+
+	val = max8907c_reg_read(info->i2c, info->reg_base);
+	return val * 100;
+}
+
+static int max8907c_regulator_ldo_enable(struct regulator_dev *rdev)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+
+	return max8907c_set_bits(info->i2c, info->reg_base + MAX8907C_CTL,
+				 MAX8907C_MASK_LDO_EN | MAX8907C_MASK_LDO_SEQ,
+				 MAX8907C_MASK_LDO_EN | MAX8907C_MASK_LDO_SEQ);
+}
+
+static int max8907c_regulator_out5v_enable(struct regulator_dev *rdev)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+
+	return max8907c_set_bits(info->i2c, info->reg_base,
+				 MAX8907C_MASK_OUT5V_VINEN |
+				 MAX8907C_MASK_OUT5V_ENSRC |
+				 MAX8907C_MASK_OUT5V_EN,
+				 MAX8907C_MASK_OUT5V_ENSRC |
+				 MAX8907C_MASK_OUT5V_EN);
+}
+
+static int max8907c_regulator_ldo_disable(struct regulator_dev *rdev)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+
+	return max8907c_set_bits(info->i2c, info->reg_base + MAX8907C_CTL,
+				 MAX8907C_MASK_LDO_EN | MAX8907C_MASK_LDO_SEQ,
+				 MAX8907C_MASK_LDO_SEQ);
+}
+
+static int max8907c_regulator_out5v_disable(struct regulator_dev *rdev)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+
+	return max8907c_set_bits(info->i2c, info->reg_base,
+				 MAX8907C_MASK_OUT5V_VINEN |
+				 MAX8907C_MASK_OUT5V_ENSRC |
+				 MAX8907C_MASK_OUT5V_EN,
+				 MAX8907C_MASK_OUT5V_ENSRC);
+}
+
+static int max8907c_regulator_ldo_is_enabled(struct regulator_dev *rdev)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+	int val;
+
+	val = max8907c_reg_read(info->i2c, info->reg_base + MAX8907C_CTL);
+	if (val < 0)
+		return -EDOM;
+
+	return (val & MAX8907C_MASK_LDO_EN) || !(val & MAX8907C_MASK_LDO_SEQ);
+}
+
+static int max8907c_regulator_out5v_is_enabled(struct regulator_dev *rdev)
+{
+	const struct max8907c_regulator_info *info = rdev_get_drvdata(rdev);
+	int val;
+
+	val = max8907c_reg_read(info->i2c, info->reg_base);
+	if (val < 0)
+		return -EDOM;
+
+	if ((val &
+	     (MAX8907C_MASK_OUT5V_VINEN | MAX8907C_MASK_OUT5V_ENSRC |
+	      MAX8907C_MASK_OUT5V_EN))
+	    == MAX8907C_MASK_OUT5V_ENSRC)
+		return 1;
+
+	return 0;
+}
+
+static int max8907c_regulator_probe(struct platform_device *pdev)
+{
+	struct max8907c *max8907c = dev_get_drvdata(pdev->dev.parent);
+	struct max8907c_regulator_info *info;
+	struct regulator_dev *rdev;
+	u8 version;
+
+	/* Backwards compatibility with max8907b, SD1 uses different voltages */
+	version = max8907c_reg_read(max8907c->i2c_power, MAX8907C_REG_II2RR);
+	if ((version & MAX8907C_II2RR_VERSION_MASK) == MAX8907C_II2RR_VERSION_REV_B) {
+		max8907c_regulators[MAX8907C_SD1].min_uV = 637500;
+		max8907c_regulators[MAX8907C_SD1].max_uV = 1425000;
+		max8907c_regulators[MAX8907C_SD1].step_uV = 12500;
+	}
+
+	info = &max8907c_regulators[pdev->id];
+	info->i2c = max8907c->i2c_power;
+
+	rdev = regulator_register(&info->desc,
+				  &pdev->dev, pdev->dev.platform_data, info);
+	if (IS_ERR(rdev)) {
+		dev_err(&pdev->dev, "Cannot register regulator \"%s\", %ld\n",
+			info->desc.name, PTR_ERR(rdev));
+		goto error;
+	}
+
+	platform_set_drvdata(pdev, rdev);
+	return 0;
+
+error:
+	return PTR_ERR(rdev);
+}
+
+static int max8907c_regulator_remove(struct platform_device *pdev)
+{
+	struct regulator_dev *rdev = platform_get_drvdata(pdev);
+
+	regulator_unregister(rdev);
+	return 0;
+}
+
+static struct platform_driver max8907c_regulator_driver = {
+	.driver = {
+		   .name = "max8907c-regulator",
+		   .owner = THIS_MODULE,
+		   },
+	.probe = max8907c_regulator_probe,
+	.remove = __devexit_p(max8907c_regulator_remove),
+};
+
+static int __init max8907c_regulator_init(void)
+{
+	return platform_driver_register(&max8907c_regulator_driver);
+}
+
+subsys_initcall(max8907c_regulator_init);
+
+static void __exit max8907c_reg_exit(void)
+{
+	platform_driver_unregister(&max8907c_regulator_driver);
+}
+
+module_exit(max8907c_reg_exit);
+
+MODULE_DESCRIPTION("MAX8907C regulator driver");
+MODULE_AUTHOR("Gyungoh Yoo <jack.yoo@maxim-ic.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/max8952.c b/drivers/regulator/max8952.c
new file mode 100644
index 000000000000..bc0c8b8835c5
--- /dev/null
+++ b/drivers/regulator/max8952.c
@@ -0,0 +1,313 @@
+/*
+ * max8952.c -- support regulators in max8952
+ *
+ * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/regulator/driver.h>
+#include <linux/slab.h>
+#include <linux/regulator/max8952.h>
+#include <linux/platform_device.h>
+
+#define VOLTAGE_TO_VALUE(v) (((v) - 750000) / 10000)
+#define VALUE_TO_VOLTAGE(val) ((val) * 10000 + 750000)
+
+struct max8952_info {
+	int voltages_count;
+	const int *voltages_list;
+	u8 reg_base;
+	struct regulator_desc desc;
+};
+
+#define REG(ids, base, list) \
+	{ \
+		.voltages_list = (list), \
+		.reg_base = (base), \
+		.desc = { \
+			.name = #ids, \
+			.id = MAX8952_##ids, \
+			.n_voltages = ARRAY_SIZE((list)), \
+			.ops = &max8952_ops, \
+			.type = REGULATOR_VOLTAGE, \
+			.owner = THIS_MODULE, \
+		}, \
+	}
+
+static const int max8952_mode0_voltages[] = {
+	750000, 760000, 1260000, 1270000, 1280000, 1370000, 1380000
+};
+
+static const int max8952_mode1_voltages[] = {
+	750000, 760000, 1040000, 1050000, 1060000, 1370000, 1380000
+};
+
+static const int max8952_mode2_voltages[] = {
+	750000, 760000, 1210000, 1220000, 1230000, 1370000, 1380000
+};
+
+static const int max8952_mode3_voltages[] = {
+	750000, 760000, 1040000, 1050000, 1060000, 1370000, 1380000
+};
+
+static int max8952_list_voltage(struct regulator_dev *dev, unsigned index);
+static int max8952_set_voltage(struct regulator_dev *dev, int min_uV,
+			       int max_uV);
+static int max8952_get_voltage(struct regulator_dev *dev);
+
+static struct regulator_ops max8952_ops = {
+	.list_voltage = max8952_list_voltage,
+	.set_voltage = max8952_set_voltage,
+	.get_voltage = max8952_get_voltage,
+};
+
+static struct max8952_info max8952_regulators[] = {
+	REG(MODE0, MAX8952_REG_MODE0, max8952_mode0_voltages),
+	REG(MODE1, MAX8952_REG_MODE1, max8952_mode1_voltages),
+	REG(MODE2, MAX8952_REG_MODE2, max8952_mode2_voltages),
+	REG(MODE3, MAX8952_REG_MODE3, max8952_mode3_voltages),
+};
+
+#define MAX8952_REGULATOR_CNT (ARRAY_SIZE(max8952_regulators))
+
+struct max8952 {
+	struct i2c_client *i2c;
+	struct mutex io_lock;
+	struct regulator_dev *rdev[MAX8952_REGULATOR_CNT];
+};
+
+static int max8952_i2c_read(struct i2c_client *i2c, u8 reg, u8 count, u8 * dest)
+{
+	struct i2c_msg xfer[2];
+	int ret;
+
+	xfer[0].addr = i2c->addr;
+	xfer[0].flags = I2C_M_NOSTART;
+	xfer[0].len = 1;
+	xfer[0].buf = &reg;
+
+	xfer[1].addr = i2c->addr;
+	xfer[1].flags = I2C_M_RD;
+	xfer[1].len = count;
+	xfer[1].buf = dest;
+
+	ret = i2c_transfer(i2c->adapter, xfer, 2);
+	if (ret == 2)
+		ret = 0;
+	else if (ret >= 0)
+		ret = -EIO;
+
+	return ret;
+}
+
+static int max8952_i2c_write(struct i2c_client *i2c, u8 reg, u8 count,
+			     const u8 *src)
+{
+	u8 msg[0x100 + 1];
+	int ret;
+
+	msg[0] = reg;
+	memcpy(&msg[1], src, count);
+
+	ret = i2c_master_send(i2c, msg, count + 1);
+	if (ret < 0)
+		return ret;
+	if (ret != count + 1)
+		return -EIO;
+	return 0;
+}
+
+static u8 max8952_read(struct max8952 *max8952, u8 reg)
+{
+	u8 val;
+	int ret;
+
+	mutex_lock(&max8952->io_lock);
+
+	ret = max8952_i2c_read(max8952->i2c, reg, 1, &val);
+
+	mutex_unlock(&max8952->io_lock);
+	pr_debug("max8952: reg read  reg=%x, val=%x\n", (unsigned int)reg,
+		 (unsigned int)val);
+
+	if (ret < 0)
+		pr_err("Failed to read max8952 I2C driver: %d\n", ret);
+	return val;
+}
+
+static int max8952_write(struct max8952 *max8952, u8 reg, u8 val)
+{
+	int ret;
+
+	pr_debug("max8952: reg write  reg=%x, val=%x\n", (unsigned int)reg,
+		 (unsigned int)val);
+	mutex_lock(&max8952->io_lock);
+
+	ret = max8952_i2c_write(max8952->i2c, reg, 1, &val);
+
+	mutex_unlock(&max8952->io_lock);
+
+	if (ret < 0)
+		pr_err("Failed to write max8952 I2C driver: %d\n", ret);
+	return ret;
+}
+
+int max8952_set_bits(struct max8952 *max8952, u8 reg, u8 mask, u8 val)
+{
+	u8 tmp;
+	int ret;
+
+	pr_debug("max8952: reg write  reg=%02X, val=%02X, mask=%02X\n",
+		 (unsigned int)reg, (unsigned int)val, (unsigned int)mask);
+	mutex_lock(&max8952->io_lock);
+
+	ret = max8952_i2c_read(max8952->i2c, reg, 1, &tmp);
+	if (ret == 0) {
+		val = (tmp & ~mask) | (val & mask);
+		ret = max8952_i2c_write(max8952->i2c, reg, 1, &val);
+	}
+
+	mutex_unlock(&max8952->io_lock);
+
+	if (ret != 0)
+		pr_err("Failed to write max8952 I2C driver: %d\n", ret);
+	return ret;
+}
+
+static int max8952_list_voltage(struct regulator_dev *rdev, unsigned index)
+{
+	const struct max8952_info *reg = &max8952_regulators[rdev_get_id(rdev)];
+
+	return reg->voltages_list[index];
+}
+
+static int max8952_set_voltage(struct regulator_dev *rdev, int min_uV,
+			       int max_uV)
+{
+	struct max8952 *max8952 = rdev_get_drvdata(rdev);
+	const struct max8952_info *reg = &max8952_regulators[rdev_get_id(rdev)];
+	int val = -1;
+	int voltage;
+	int i;
+
+	for (i = 0; i < reg->desc.n_voltages; i++) {
+		voltage = reg->voltages_list[i];
+		if (min_uV <= voltage && voltage <= max_uV) {
+			val = VOLTAGE_TO_VALUE(voltage);
+			break;
+		}
+	}
+	if (val == -1)
+		return -EDOM;
+
+	return max8952_set_bits(max8952, reg->reg_base, MAX8952_MASK_OUTMODE,
+				val);
+}
+
+static int max8952_get_voltage(struct regulator_dev *rdev)
+{
+	struct max8952 *max8952 = rdev_get_drvdata(rdev);
+	const struct max8952_info *reg = &max8952_regulators[rdev_get_id(rdev)];
+	int val;
+
+	val = max8952_read(max8952, reg->reg_base);
+	val &= MAX8952_MASK_OUTMODE;
+
+	return VALUE_TO_VOLTAGE(val);
+}
+
+static int __devinit max8952_probe(struct i2c_client *i2c,
+				   const struct i2c_device_id *i2c_id)
+{
+	struct max8952 *max8952;
+	struct max8952_platform_data *pdata = i2c->dev.platform_data;
+	struct regulator_dev *rdev;
+	int id;
+	int i;
+
+	max8952 = kzalloc(sizeof(struct max8952), GFP_KERNEL);
+	if (max8952 == NULL)
+		return -ENOMEM;
+
+	max8952->i2c = i2c;
+	mutex_init(&max8952->io_lock);
+
+	for (i = 0; i < pdata->num_subdevs; i++) {
+		id = pdata->subdevs[i]->id;
+		rdev =
+		    regulator_register(&max8952_regulators[id].desc, &i2c->dev,
+				       (struct regulator_init_data *)pdata->
+				       subdevs[i]->dev.platform_data, max8952);
+		if (IS_ERR(rdev)) {
+			dev_err(&i2c->dev,
+				"Cannot register regulator \"%s\", %ld\n",
+				max8952_regulators[id].desc.name,
+				PTR_ERR(rdev));
+			goto error;
+		}
+		max8952->rdev[id] = rdev;
+	}
+
+	i2c_set_clientdata(i2c, max8952);
+	return 0;
+
+error:
+	kfree(max8952);
+	return PTR_ERR(rdev);
+}
+
+static int __devexit max8952_remove(struct i2c_client *i2c)
+{
+	struct max8952 *max8952 = i2c_get_clientdata(i2c);
+	int i;
+
+	for (i = 0; i < MAX8952_REGULATOR_CNT; i++) {
+		if (max8952->rdev[i])
+			regulator_unregister(max8952->rdev[i]);
+	}
+	kfree(max8952);
+
+	return 0;
+}
+
+static const struct i2c_device_id max8952_id[] = {
+	{"max8952", 0},
+	{}
+};
+
+MODULE_DEVICE_TABLE(i2c, max8952_id);
+
+static struct i2c_driver max8952_driver = {
+	.probe = max8952_probe,
+	.remove = __devexit_p(max8952_remove),
+	.driver = {
+		   .name = "max8952",
+		   .owner = THIS_MODULE,
+		   },
+	.id_table = max8952_id,
+};
+
+static int __init max8952_init(void)
+{
+	return i2c_add_driver(&max8952_driver);
+}
+
+subsys_initcall(max8952_init);
+
+static void __exit max8952_exit(void)
+{
+	i2c_del_driver(&max8952_driver);
+}
+
+module_exit(max8952_exit);
+
+MODULE_DESCRIPTION("MAX8952 regulator driver");
+MODULE_AUTHOR("Gyungoh Yoo <jack.yoo@maxim-ic.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index a86401ea8e71..2532d54eb111 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -249,6 +249,16 @@ config RTC_DRV_X1205
 	  This driver can also be built as a module. If so, the module
 	  will be called rtc-x1205.
 
+config RTC_DRV_TEGRA
+	tristate "NVIDIA Tegra Internal RTC driver"
+	depends on ARCH_TEGRA
+	help
+	  If you say yes here you get support for the
+	  Tegra 200 series internal RTC module.
+
+	  This drive can also be built as a module. If so, the module
+	  will be called rtc-tegra.
+
 config RTC_DRV_PCF8563
 	tristate "Philips PCF8563/Epson RTC8564"
 	help
@@ -306,8 +316,7 @@ config RTC_DRV_DM355EVM
 
 config RTC_DRV_TPS6586X
 	tristate "TI TPS6586X RTC"
-	depends on I2C
-	select MFD_TPS6586X
+	depends on MFD_TPS6586X
 	help
 	  This driver supports TPS6586X RTC
 
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 5520733748d2..cc4a28918637 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_RTC_DRV_MV)	+= rtc-mv.o
 obj-$(CONFIG_RTC_DRV_NUC900)	+= rtc-nuc900.o
 obj-$(CONFIG_RTC_DRV_OMAP)	+= rtc-omap.o
 obj-$(CONFIG_RTC_DRV_PCAP)	+= rtc-pcap.o
+obj-$(CONFIG_RTC_DRV_TEGRA)	+= rtc-tegra.o
 obj-$(CONFIG_RTC_DRV_PCF8563)	+= rtc-pcf8563.o
 obj-$(CONFIG_RTC_DRV_PCF8583)	+= rtc-pcf8583.o
 obj-$(CONFIG_RTC_DRV_PCF2123)	+= rtc-pcf2123.o
diff --git a/drivers/rtc/rtc-tegra.c b/drivers/rtc/rtc-tegra.c
new file mode 100644
index 000000000000..f5cccd65a12c
--- /dev/null
+++ b/drivers/rtc/rtc-tegra.c
@@ -0,0 +1,471 @@
+/*
+ * drivers/rtc/rtc-tegra.c
+ *
+ * An RTC driver for the NVIDIA Tegra 200 series internal RTC.
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ * Copyright (c) 2010 Jon Mayo <jmayo@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <asm/io.h>
+#include <linux/delay.h>
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+
+/* how many attempts to wait in tegra_rtc_wait_while_busy(). */
+#define RTC_TEGRA_RETRIES 15
+
+#define tegra_rtc_read(ofs)		readl(rtc_base + (ofs))
+#define tegra_rtc_write(ofs, val)	writel((val), rtc_base + (ofs))
+
+/* STATUS: This bit is set when a write is initiated on the APB side. It is
+ * cleared once the write completes in RTC 32KHz clock domain which could be
+ * several thousands of APB clocks. This must be IDLE before a write is
+ * initiated. Note that this bit is only for writes.
+ * 0 = IDLE
+ * 1 = BUSY
+ */
+#define RTC_TEGRA_REG_BUSY			0x004
+#define RTC_TEGRA_REG_SECONDS			0x008
+#define RTC_TEGRA_REG_SHADOW_SECONDS		0x00c
+#define RTC_TEGRA_REG_MILLI_SECONDS		0x010
+#define RTC_TEGRA_REG_SECONDS_ALARM0		0x014
+#define RTC_TEGRA_REG_SECONDS_ALARM1		0x018
+#define RTC_TEGRA_REG_MILLI_SECONDS_ALARM0	0x01c
+#define RTC_TEGRA_REG_INTR_MASK			0x028
+/* a write to this register performs a clear. reg=reg&(~x) */
+#define RTC_TEGRA_REG_INTR_STATUS		0x02c
+
+/* bits in INTR_MASK */
+#define RTC_TEGRA_INTR_MASK_MSEC_CDN_ALARM (1<<4)
+#define RTC_TEGRA_INTR_MASK_SEC_CDN_ALARM (1<<3)
+#define RTC_TEGRA_INTR_MASK_MSEC_ALARM (1<<2)
+#define RTC_TEGRA_INTR_MASK_SEC_ALARM1 (1<<1)
+#define RTC_TEGRA_INTR_MASK_SEC_ALARM0 (1<<0)
+
+/* bits in INTR_STATUS */
+#define RTC_TEGRA_INTR_STATUS_MSEC_CDN_ALARM (1<<4)
+#define RTC_TEGRA_INTR_STATUS_SEC_CDN_ALARM (1<<3)
+#define RTC_TEGRA_INTR_STATUS_MSEC_ALARM (1<<2)
+#define RTC_TEGRA_INTR_STATUS_SEC_ALARM1 (1<<1)
+#define RTC_TEGRA_INTR_STATUS_SEC_ALARM0 (1<<0)
+
+static struct rtc_device *rtc_dev;
+static DEFINE_SPINLOCK(tegra_rtc_lock);
+static void __iomem *rtc_base; /* NULL if not initialized. */
+static int tegra_rtc_irq; /* alarm and periodic interrupt */
+
+/* check is hardware is accessing APB. */
+static inline u32 tegra_rtc_check_busy(void)
+{
+	return tegra_rtc_read(RTC_TEGRA_REG_BUSY);
+}
+
+/* wait for hardware to be ready for writing.
+ * do not call this inside the spin lock because it sleeps.
+ */
+static int tegra_rtc_wait_while_busy(struct device *dev)
+{
+	/* TODO: wait for busy then not busy to catch a leading edge. */
+	int retries = RTC_TEGRA_RETRIES;
+	while (tegra_rtc_check_busy()) {
+		if (!retries--) {
+			dev_err(dev, "write failed:retry count exceeded.\n");
+			return -ETIMEDOUT;
+		}
+		msleep(1);
+	}
+	return 0;
+}
+
+/* waits for the RTC to not be busy accessing APB, then write a single value. */
+static int tegra_rtc_write_not_busy(struct device *dev, unsigned ofs, u32 value)
+{
+	unsigned long sl_irq_flags;
+	int ret;
+	spin_lock_irqsave(&tegra_rtc_lock, sl_irq_flags);
+	if(tegra_rtc_check_busy()) {
+		spin_unlock_irqrestore(&tegra_rtc_lock, sl_irq_flags);
+		ret = tegra_rtc_wait_while_busy(dev);
+		if (ret)
+			return ret;
+		spin_lock_irqsave(&tegra_rtc_lock, sl_irq_flags);
+	}
+	tegra_rtc_write(ofs, value);
+	spin_unlock_irqrestore(&tegra_rtc_lock, sl_irq_flags);
+	return 0;
+}
+
+
+static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	unsigned long sec, msec;
+	unsigned long sl_irq_flags;
+
+	spin_lock_irqsave(&tegra_rtc_lock, sl_irq_flags);
+
+	msec = tegra_rtc_read(RTC_TEGRA_REG_MILLI_SECONDS);
+	sec = tegra_rtc_read(RTC_TEGRA_REG_SHADOW_SECONDS);
+
+	spin_unlock_irqrestore(&tegra_rtc_lock, sl_irq_flags);
+
+	rtc_time_to_tm(sec, tm);
+
+	dev_vdbg(dev, "time read as %lu. %d/%d/%d %d:%02u:%02u\n",
+		sec,
+		tm->tm_mon+1,
+		tm->tm_mday,
+		tm->tm_year+1900,
+		tm->tm_hour,
+		tm->tm_min,
+		tm->tm_sec
+	);
+
+	return 0;
+}
+
+static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	unsigned long sec;
+	int ret;
+
+	/* convert tm to seconds. */
+	ret = rtc_valid_tm(tm);
+	if (ret) return ret;
+	rtc_tm_to_time(tm, &sec);
+
+	dev_vdbg(dev, "time set to %lu. %d/%d/%d %d:%02u:%02u\n",
+		sec,
+		tm->tm_mon+1,
+		tm->tm_mday,
+		tm->tm_year+1900,
+		tm->tm_hour,
+		tm->tm_min,
+		tm->tm_sec
+	);
+
+	/* seconds only written if wait succeeded. */
+	ret = tegra_rtc_write_not_busy(dev, RTC_TEGRA_REG_SECONDS, sec);
+
+	dev_vdbg(
+		dev, "time read back as %d\n",
+		tegra_rtc_read(RTC_TEGRA_REG_SECONDS)
+	);
+	return ret;
+}
+
+static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *t)
+{
+	unsigned long sec;
+	unsigned long sl_irq_flags;
+	unsigned tmp;
+
+	spin_lock_irqsave(&tegra_rtc_lock, sl_irq_flags);
+
+	sec = tegra_rtc_read(RTC_TEGRA_REG_SECONDS_ALARM0);
+
+	spin_unlock_irqrestore(&tegra_rtc_lock, sl_irq_flags);
+
+	if (sec == 0) {
+		/* alarm is disabled. */
+		t->enabled = 0;
+		t->time.tm_mon = -1;
+		t->time.tm_mday = -1;
+		t->time.tm_year = -1;
+		t->time.tm_hour = -1;
+		t->time.tm_min = -1;
+		t->time.tm_sec = -1;
+	} else {
+		/* alarm is enabled. */
+		t->enabled = 1;
+		rtc_time_to_tm(sec, &t->time);
+	}
+
+	tmp = tegra_rtc_read(RTC_TEGRA_REG_INTR_STATUS);
+	t->pending = (tmp & RTC_TEGRA_INTR_STATUS_SEC_ALARM0) != 0;
+
+	return 0;
+}
+
+static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
+{
+	unsigned status;
+	unsigned long sl_irq_flags;
+	int ret;
+
+	spin_lock_irqsave(&tegra_rtc_lock, sl_irq_flags);
+	if(tegra_rtc_check_busy()) { /* wait for the busy bit to clear. */
+		spin_unlock_irqrestore(&tegra_rtc_lock, sl_irq_flags);
+		ret = tegra_rtc_wait_while_busy(dev);
+		if (ret)
+			return ret;
+		spin_lock_irqsave(&tegra_rtc_lock, sl_irq_flags);
+	}
+	/* read the original value, and OR in the flag. */
+	status = tegra_rtc_read(RTC_TEGRA_REG_INTR_MASK);
+	if (enabled)
+		status |= RTC_TEGRA_INTR_MASK_SEC_ALARM0; /* set it */
+	else
+		status &= ~RTC_TEGRA_INTR_MASK_SEC_ALARM0; /* clear it */
+	tegra_rtc_write(RTC_TEGRA_REG_INTR_MASK, status);
+	spin_unlock_irqrestore(&tegra_rtc_lock, sl_irq_flags);
+
+	return 0;
+}
+
+static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *t)
+{
+	int ret;
+	unsigned long sec;
+
+	if (t->enabled)
+		rtc_tm_to_time(&t->time, &sec);
+	else
+		sec = 0;
+
+	ret = tegra_rtc_write_not_busy(dev, RTC_TEGRA_REG_SECONDS_ALARM0, sec);
+	dev_vdbg(
+		dev, "alarm read back as %d\n",
+		tegra_rtc_read(RTC_TEGRA_REG_SECONDS_ALARM0)
+	);
+
+	/* if successfully written and alarm is enabled ... */
+	if (ret == 0 && sec) {
+		tegra_rtc_alarm_irq_enable(dev, 1);
+
+		dev_vdbg(dev, "alarm set as %lu. %d/%d/%d %d:%02u:%02u\n",
+			sec,
+			t->time.tm_mon+1,
+			t->time.tm_mday,
+			t->time.tm_year+1900,
+			t->time.tm_hour,
+			t->time.tm_min,
+			t->time.tm_sec
+		);
+	} else {
+		/* disable alarm if 0 or write error. */
+		dev_vdbg(dev, "alarm disabled\n");
+		tegra_rtc_alarm_irq_enable(dev, 0);
+	}
+
+	return ret;
+}
+
+static int tegra_rtc_ioctl(
+	struct device *dev, unsigned int cmd, unsigned long arg)
+{
+	/* use default ioctl handlers for:
+	 * RTC_RD_TIME, RTC_SET_TIME, RTC_ALM_SET, RTC_ALM_READ, RTC_WKALM_SET,
+	 * RTC_WKALM_RD, RTC_IRQP_SET, RTC_IRQP_READ, RTC_PIE_ON, RTC_PIE_OFF
+	 */
+	return -ENOIOCTLCMD;
+}
+
+/* additional proc lines. */
+static int tegra_rtc_proc(struct device *dev, struct seq_file *seq)
+{
+	if (!dev || !dev->driver)
+		return 0;
+	return seq_printf(seq, "name\t\t: %s\n", dev_name(dev));
+}
+
+static irqreturn_t tegra_rtc_irq_handler(int irq, void *dev_id)
+{
+	unsigned long events = 0;
+	unsigned status;
+	unsigned long sl_irq_flags;
+
+	status = tegra_rtc_read(RTC_TEGRA_REG_INTR_STATUS);
+
+	if (status) {
+		/* clear the interrupt masks and status on any irq. */
+		spin_lock_irqsave(&tegra_rtc_lock, sl_irq_flags);
+		tegra_rtc_write(RTC_TEGRA_REG_INTR_MASK, 0);
+		tegra_rtc_write(RTC_TEGRA_REG_INTR_STATUS, -1);
+		spin_unlock_irqrestore(&tegra_rtc_lock, sl_irq_flags);
+	}
+
+	/* check if Alarm */
+	if ((status & RTC_TEGRA_INTR_STATUS_SEC_ALARM0))
+		events |= RTC_IRQF | RTC_AF;
+
+	/* check if Periodic */
+	if ((status & RTC_TEGRA_INTR_STATUS_SEC_CDN_ALARM))
+		events |= RTC_IRQF | RTC_PF;
+
+	rtc_update_irq(rtc_dev, 1, events);
+	return IRQ_HANDLED;
+}
+
+static struct rtc_class_ops tegra_rtc_ops = {
+	.ioctl		= tegra_rtc_ioctl,
+	.read_time	= tegra_rtc_read_time,
+	.set_time	= tegra_rtc_set_time,
+	.read_alarm	= tegra_rtc_read_alarm,
+	.set_alarm	= tegra_rtc_set_alarm,
+	.proc		= tegra_rtc_proc,
+	.alarm_irq_enable = tegra_rtc_alarm_irq_enable,
+};
+
+static int __init tegra_rtc_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	int ret;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(
+			&pdev->dev, "Unable to allocate resources for device.\n"
+		);
+		return -EBUSY;
+	}
+
+	tegra_rtc_irq = platform_get_irq(pdev, 0);
+	if (tegra_rtc_irq <= 0) {
+		tegra_rtc_irq = 0;
+		return -EBUSY;
+	}
+
+	rtc_base = ioremap(res->start, res->end - res->start + 1);
+	if (!rtc_base) {
+		dev_err(&pdev->dev, "Unable to grab IOs for device.\n");
+		return -EBUSY;
+	}
+
+	/* clear out the hardware. */
+	tegra_rtc_write_not_busy(&pdev->dev, RTC_TEGRA_REG_SECONDS_ALARM0, 0);
+	tegra_rtc_write_not_busy(&pdev->dev, RTC_TEGRA_REG_INTR_STATUS, -1);
+	tegra_rtc_write_not_busy(&pdev->dev, RTC_TEGRA_REG_INTR_MASK, 0);
+
+	device_init_wakeup(&pdev->dev, 1);
+
+	rtc_dev = rtc_device_register(
+		pdev->name, &pdev->dev, &tegra_rtc_ops, THIS_MODULE);
+	if (IS_ERR(rtc_dev)) {
+		ret = PTR_ERR(rtc_dev);
+		rtc_dev = NULL;
+		dev_err(&pdev->dev, "Unable to register device (err=%d).\n", ret);
+		goto err_iounmap;
+	}
+
+	ret = request_irq(tegra_rtc_irq, tegra_rtc_irq_handler,
+		IRQF_DISABLED, "rtc alarm", &pdev->dev);
+	if (ret) {
+		dev_err(&pdev->dev, "Unable to request interrupt for device (err=%d).\n", ret);
+		goto err_dev_unreg;
+	}
+
+	dev_notice(&pdev->dev, "Tegra internal Real Time Clock\n");
+
+	return 0;
+
+err_dev_unreg:
+	rtc_device_unregister(rtc_dev);
+	rtc_dev = NULL;
+err_iounmap:
+	iounmap(rtc_base);
+	rtc_base = NULL;
+
+	return ret;
+}
+
+static int __devexit tegra_rtc_remove(struct platform_device *pdev)
+{
+	if (rtc_dev) {
+		rtc_device_unregister(rtc_dev);
+		rtc_dev = NULL;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int tegra_rtc_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct device *dev=&pdev->dev;
+
+	/* only use ALARM0 as a wake source. */
+	tegra_rtc_write(RTC_TEGRA_REG_INTR_STATUS, -1);
+	tegra_rtc_write(RTC_TEGRA_REG_INTR_MASK,
+		RTC_TEGRA_INTR_STATUS_SEC_ALARM0);
+	dev_vdbg(dev, "alarm sec = %d\n",
+		tegra_rtc_read(RTC_TEGRA_REG_SECONDS_ALARM0));
+
+	dev_vdbg(dev, "Suspend (device_may_wakeup=%d) irq:%d\n",
+		device_may_wakeup(dev), tegra_rtc_irq);
+	/* leave the alarms on as a wake source. */
+	if (device_may_wakeup(dev))
+		enable_irq_wake(tegra_rtc_irq);
+	return 0;
+}
+
+static int tegra_rtc_resume(struct platform_device *pdev)
+{
+	struct device *dev=&pdev->dev;
+	unsigned int intr_status;
+
+	/* clear */
+	intr_status = tegra_rtc_read(RTC_TEGRA_REG_INTR_STATUS);
+	if (intr_status & RTC_TEGRA_INTR_STATUS_SEC_ALARM0) {
+		tegra_rtc_write_not_busy(dev, RTC_TEGRA_REG_INTR_MASK, 0);
+		tegra_rtc_write_not_busy(dev, RTC_TEGRA_REG_INTR_STATUS, -1);
+	}
+
+	dev_vdbg(dev, "Resume (device_may_wakeup=%d)\n", device_may_wakeup(dev));
+	/* alarms were left on as a wake source, turn them off. */
+	if (device_may_wakeup(dev))
+		disable_irq_wake(tegra_rtc_irq);
+	return 0;
+}
+#endif
+
+static void tegra_rtc_shutdown(struct platform_device *pdev)
+{
+	dev_vdbg(&pdev->dev, "disabling interrupts.\n");
+	tegra_rtc_alarm_irq_enable(&pdev->dev, 0);
+}
+
+static struct platform_driver tegra_rtc_driver = {
+	.remove		= __devexit_p(tegra_rtc_remove),
+	.shutdown	= tegra_rtc_shutdown,
+	.driver		= {
+		.name	= "tegra_rtc",
+		.owner	= THIS_MODULE,
+	},
+#ifdef CONFIG_PM
+	.suspend	= tegra_rtc_suspend,
+	.resume		= tegra_rtc_resume,
+#endif
+};
+
+static int __init tegra_rtc_init(void)
+{
+	return platform_driver_probe(&tegra_rtc_driver, tegra_rtc_probe);
+}
+module_init(tegra_rtc_init);
+
+static void __exit tegra_rtc_exit(void)
+{
+	platform_driver_unregister(&tegra_rtc_driver);
+}
+module_exit(tegra_rtc_exit);
+
+MODULE_ALIAS("platform:tegra_rtc");
+MODULE_AUTHOR("NVIDIA Corporation");
+MODULE_DESCRIPTION("driver for Tegra internal RTC");
+MODULE_LICENSE("GPL");
diff --git a/drivers/rtc/rtc-tps6586x.c b/drivers/rtc/rtc-tps6586x.c
index ca6138bbda4b..2ff339a21a5c 100644
--- a/drivers/rtc/rtc-tps6586x.c
+++ b/drivers/rtc/rtc-tps6586x.c
@@ -29,19 +29,16 @@
 #include <linux/rtc.h>
 #include <linux/slab.h>
 
-#define TPS_EPOCH	2009
-
 #define RTC_CTRL	0xc0
-#  define RTC_ENABLE	(1 << 5)	/* enables tick updates */
-#  define RTC_HIRES	(1 << 4)	/* 1Khz or 32Khz updates */
+#define RTC_ENABLE	BIT(5)	/* enables alarm */
+#define RTC_HIRES	BIT(4)	/* 1Khz or 32Khz updates */
 #define RTC_ALARM1_HI	0xc1
 #define RTC_COUNT4	0xc6
 
 struct tps6586x_rtc {
-	unsigned long     epoch_start;
-	int		  irq;
-	bool		  irq_en;
-	struct rtc_device *rtc;
+	unsigned long		epoch_start;
+	int			irq;
+	struct rtc_device	*rtc;
 };
 
 static inline struct device *to_tps6586x_dev(struct device *dev)
@@ -142,11 +139,6 @@ static int tps6586x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 		return -EINVAL;
 	}
 
-	if (rtc->irq_en && rtc->irq_en && (rtc->irq != -1)) {
-		disable_irq(rtc->irq);
-		rtc->irq_en = false;
-	}
-
 	seconds -= rtc->epoch_start;
 	ticks = (unsigned long long)seconds << 10;
 
@@ -155,15 +147,8 @@ static int tps6586x_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 	buff[2] = ticks & 0xff;
 
 	err = tps6586x_writes(tps_dev, RTC_ALARM1_HI, sizeof(buff), buff);
-	if (err) {
+	if (err)
 		dev_err(tps_dev, "unable to program alarm\n");
-		return err;
-	}
-
-	if (alrm->enabled && (rtc->irq != -1)) {
-		enable_irq(rtc->irq);
-		rtc->irq_en = true;
-	}
 
 	return err;
 }
@@ -186,29 +171,47 @@ static int tps6586x_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 	seconds += rtc->epoch_start;
 
 	rtc_time_to_tm(seconds, &alrm->time);
-	alrm->enabled = rtc->irq_en;
 
 	return 0;
 }
 
-static int tps6586x_rtc_update_irq_enable(struct device *dev,
-					  unsigned int enabled)
+static int tps6586x_rtc_alarm_irq_enable(struct device *dev,
+					 unsigned int enabled)
 {
 	struct tps6586x_rtc *rtc = dev_get_drvdata(dev);
+	struct device *tps_dev = to_tps6586x_dev(dev);
+	u8 buff;
+	int err;
 
 	if (rtc->irq == -1)
 		return -EIO;
 
-	enabled = !!enabled;
-	if (enabled == rtc->irq_en)
+	err = tps6586x_read(tps_dev, RTC_CTRL, &buff);
+	if (err < 0) {
+		dev_err(dev, "failed to read RTC_CTRL\n");
+		return err;
+	}
+
+	if ((enabled && (buff & RTC_ENABLE)) ||
+	    (!enabled && !(buff & RTC_ENABLE)))
 		return 0;
 
-	if (enabled)
+	if (enabled) {
+		err = tps6586x_set_bits(tps_dev, RTC_CTRL, RTC_ENABLE);
+		if (err < 0) {
+			dev_err(dev, "failed to set RTC_ENABLE\n");
+			return err;
+		}
 		enable_irq(rtc->irq);
-	else
+	} else {
+		err = tps6586x_clr_bits(tps_dev, RTC_CTRL, RTC_ENABLE);
+		if (err < 0) {
+			dev_err(dev, "failed to clear RTC_ENABLE\n");
+			return err;
+		}
 		disable_irq(rtc->irq);
+	}
 
-	rtc->irq_en = enabled;
 	return 0;
 }
 
@@ -217,7 +220,7 @@ static const struct rtc_class_ops tps6586x_rtc_ops = {
 	.set_time	= tps6586x_rtc_set_time,
 	.set_alarm	= tps6586x_rtc_set_alarm,
 	.read_alarm	= tps6586x_rtc_read_alarm,
-	.update_irq_enable = tps6586x_rtc_update_irq_enable,
+	.alarm_irq_enable = tps6586x_rtc_alarm_irq_enable,
 };
 
 static irqreturn_t tps6586x_rtc_irq(int irq, void *data)
@@ -235,6 +238,7 @@ static int __devinit tps6586x_rtc_probe(struct platform_device *pdev)
 	struct device *tps_dev = to_tps6586x_dev(&pdev->dev);
 	struct tps6586x_rtc *rtc;
 	int err;
+	struct tps6586x_epoch_start *epoch;
 
 	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
 
@@ -242,10 +246,18 @@ static int __devinit tps6586x_rtc_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	rtc->irq = -1;
-	if (!pdata || (pdata->irq < 0))
+
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform_data specified\n");
+		return -EINVAL;
+	}
+
+	if (pdata->irq < 0)
 		dev_warn(&pdev->dev, "no IRQ specified, wakeup is disabled\n");
 
-	rtc->epoch_start = mktime(TPS_EPOCH, 1, 1, 0, 0, 0);
+	epoch = &pdata->start;
+	rtc->epoch_start = mktime(epoch->year, epoch->month, epoch->day,
+				  epoch->hour, epoch->min, epoch->sec);
 
 	rtc->rtc = rtc_device_register("tps6586x-rtc", &pdev->dev,
 				       &tps6586x_rtc_ops, THIS_MODULE);
@@ -270,7 +282,7 @@ static int __devinit tps6586x_rtc_probe(struct platform_device *pdev)
 					   IRQF_ONESHOT, "tps6586x-rtc",
 					   &pdev->dev);
 		if (err) {
-			dev_warn(&pdev->dev, "unable to request IRQ\n");
+			dev_warn(&pdev->dev, "unable to request IRQ(%d)\n", rtc->irq);
 			rtc->irq = -1;
 		} else {
 			device_init_wakeup(&pdev->dev, 1);
@@ -323,3 +335,4 @@ module_exit(tps6586x_rtc_exit);
 MODULE_DESCRIPTION("TI TPS6586x RTC driver");
 MODULE_AUTHOR("NVIDIA Corporation");
 MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:rtc-tps6586x")
diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 24110f6f61e0..0243be5bded1 100644
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -307,6 +307,14 @@ static const struct serial8250_config uart_config[] = {
 		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
 		.flags		= UART_CAP_FIFO | UART_CAP_AFE,
 	},
+	[PORT_TEGRA] = {
+		.name		= "Tegra",
+		.fifo_size	= 32,
+		.tx_loadsz	= 8,
+		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_T_TRIG_01 |
+				  UART_FCR_R_TRIG_01,
+		.flags		= UART_CAP_FIFO,
+	},
 };
 
 #if defined(CONFIG_MIPS_ALCHEMY)
@@ -2158,6 +2166,9 @@ dont_test_tx_en:
 	 * anyway, so we don't enable them here.
 	 */
 	up->ier = UART_IER_RLSI | UART_IER_RDI;
+	/* Use the receive timeout interrupt for tegra port*/
+	if (up->port.type == PORT_TEGRA)
+		up->ier |= UART_IER_RTOIE;
 	serial_outp(up, UART_IER, up->ier);
 
 	if (up->port.flags & UPF_FOURPORT) {
diff --git a/drivers/serial/tegra_hsuart.c b/drivers/serial/tegra_hsuart.c
index 09f5f454683c..0250789253ea 100644
--- a/drivers/serial/tegra_hsuart.c
+++ b/drivers/serial/tegra_hsuart.c
@@ -41,6 +41,8 @@
 #include <linux/debugfs.h>
 #include <linux/slab.h>
 #include <linux/workqueue.h>
+#include <linux/tegra_uart.h>
+
 #include <mach/dma.h>
 #include <mach/clk.h>
 
@@ -107,7 +109,6 @@ struct tegra_uart_port {
 	/* TX DMA */
 	struct tegra_dma_req	tx_dma_req;
 	struct tegra_dma_channel *tx_dma;
-	struct work_struct	tx_work;
 
 	/* RX DMA */
 	struct tegra_dma_req	rx_dma_req;
@@ -411,34 +412,6 @@ static void do_handle_tx_pio(struct tegra_uart_port *t)
 	return;
 }
 
-static void tegra_tx_dma_complete_work(struct work_struct *work)
-{
-	struct tegra_uart_port *t =
-			container_of(work, struct tegra_uart_port, tx_work);
-	struct tegra_dma_req *req = &t->tx_dma_req;
-	unsigned long flags;
-	int timeout = 20;
-
-	while ((uart_readb(t, UART_LSR) & TX_EMPTY_STATUS) != TX_EMPTY_STATUS) {
-		timeout--;
-		if (timeout == 0) {
-			dev_err(t->uport.dev,
-				"timed out waiting for TX FIFO to empty\n");
-			return;
-		}
-		msleep(1);
-	}
-
-	spin_lock_irqsave(&t->uport.lock, flags);
-
-	t->tx_in_progress = 0;
-
-	if (req->status != -TEGRA_DMA_REQ_ERROR_ABORTED)
-		tegra_start_next_tx(t);
-
-	spin_unlock_irqrestore(&t->uport.lock, flags);
-}
-
 static void tegra_tx_dma_complete_callback(struct tegra_dma_req *req)
 {
 	struct tegra_uart_port *t = req->dev;
@@ -450,11 +423,13 @@ static void tegra_tx_dma_complete_callback(struct tegra_dma_req *req)
 
 	spin_lock_irqsave(&t->uport.lock, flags);
 	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
+	t->tx_in_progress = 0;
 
 	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 		uart_write_wakeup(&t->uport);
 
-	schedule_work(&t->tx_work);
+	if (req->status != -TEGRA_DMA_REQ_ERROR_ABORTED)
+		tegra_start_next_tx(t);
 
 	spin_unlock_irqrestore(&t->uport.lock, flags);
 }
@@ -561,8 +536,6 @@ static void tegra_uart_hw_deinit(struct tegra_uart_port *t)
 	unsigned char fcr;
 	unsigned long flags;
 
-	flush_work(&t->tx_work);
-
 	/* Disable interrupts */
 	uart_writeb(t, 0, UART_IER);
 
@@ -842,6 +815,14 @@ static void tegra_shutdown(struct uart_port *u)
 	dev_vdbg(u->dev, "-tegra_shutdown\n");
 }
 
+static void tegra_wake_peer(struct uart_port *u)
+{
+	struct tegra_uart_platform_data *pdata = u->dev->platform_data;
+
+	if (pdata && pdata->wake_peer)
+		pdata->wake_peer(u);
+}
+
 static unsigned int tegra_get_mctrl(struct uart_port *u)
 {
 	/* RI - Ring detector is active
@@ -939,13 +920,17 @@ static unsigned int tegra_tx_empty(struct uart_port *u)
 	struct tegra_uart_port *t;
 	unsigned int ret = 0;
 	unsigned long flags;
+	unsigned char lsr;
 
 	t = container_of(u, struct tegra_uart_port, uport);
 	dev_vdbg(u->dev, "+tegra_tx_empty\n");
 
 	spin_lock_irqsave(&u->lock, flags);
-	if (!t->tx_in_progress)
-		ret = TIOCSER_TEMT;
+	if (!t->tx_in_progress) {
+		lsr = uart_readb(t, UART_LSR);
+		if ((lsr & TX_EMPTY_STATUS) == TX_EMPTY_STATUS)
+			ret = TIOCSER_TEMT;
+	}
 	spin_unlock_irqrestore(&u->lock, flags);
 
 	dev_vdbg(u->dev, "-tegra_tx_empty\n");
@@ -1138,6 +1123,7 @@ static struct uart_ops tegra_uart_ops = {
 	.break_ctl	= tegra_break_ctl,
 	.startup	= tegra_startup,
 	.shutdown	= tegra_shutdown,
+	.wake_peer	= tegra_wake_peer,
 	.set_termios	= tegra_set_termios,
 	.pm		= tegra_pm,
 	.type		= tegra_type,
@@ -1180,7 +1166,6 @@ static int tegra_uart_suspend(struct platform_device *pdev, pm_message_t state)
 	u = &t->uport;
 	uart_suspend_port(&tegra_uart_driver, u);
 
-	flush_work(&t->tx_work);
 	return 0;
 }
 
@@ -1277,7 +1262,6 @@ static int tegra_uart_probe(struct platform_device *pdev)
 	pr_info("Registered UART port %s%d\n",
 		tegra_uart_driver.dev_name, u->line);
 
-	INIT_WORK(&t->tx_work, tegra_tx_dma_complete_work);
 	return ret;
 fail:
 	kfree(t);
diff --git a/drivers/spi/spi_tegra.c b/drivers/spi/spi_tegra.c
index 842ac14f745d..ece84a670fd2 100644
--- a/drivers/spi/spi_tegra.c
+++ b/drivers/spi/spi_tegra.c
@@ -129,6 +129,7 @@
 
 #define SLINK_TX_FIFO		0x100
 #define SLINK_RX_FIFO		0x180
+#define SLINK_FIFO_DEPTH	0x20
 
 static const unsigned long spi_tegra_req_sels[] = {
 	TEGRA_DMA_REQ_SEL_SL2B1,
@@ -137,7 +138,14 @@ static const unsigned long spi_tegra_req_sels[] = {
 	TEGRA_DMA_REQ_SEL_SL2B4,
 };
 
-#define BB_LEN			32
+#define BB_LEN				2048
+#define TX_FIFO_EMPTY_COUNT_MAX		SLINK_TX_FIFO_EMPTY_COUNT(0x20)
+#define RX_FIFO_FULL_COUNT_ZERO		SLINK_RX_FIFO_FULL_COUNT(0)
+
+#define SLINK_STATUS2_RESET \
+	(TX_FIFO_EMPTY_COUNT_MAX | \
+	RX_FIFO_FULL_COUNT_ZERO << 16)
+
 
 struct spi_tegra_data {
 	struct spi_master	*master;
@@ -165,8 +173,23 @@ struct spi_tegra_data {
 	struct tegra_dma_channel *rx_dma;
 	u32			*rx_bb;
 	dma_addr_t		rx_bb_phys;
+	struct tegra_dma_req	tx_dma_req;
+	struct tegra_dma_channel *tx_dma;
+	u32			*tx_bb;
+	dma_addr_t		tx_bb_phys;
+
 	bool			is_suspended;
 	unsigned long		save_slink_cmd;
+
+	u32	rx_complete;
+	u32	tx_complete;
+	bool			is_packed;
+	unsigned long	packed_size;
+	unsigned (*spi_tegra_rx)(struct spi_tegra_data *tspi,
+				  struct spi_transfer *t);
+	unsigned (*spi_tegra_tx)(struct spi_tegra_data *tspi,
+				  struct spi_transfer *t);
+	u8 g_bits_per_word;
 };
 
 
@@ -183,22 +206,99 @@ static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
 	writel(val, tspi->base + reg);
 }
 
+static void spi_tegra_clear_status(struct spi_tegra_data *tspi)
+{
+	unsigned long val;
+	unsigned long val_write = 0;
+
+	val = spi_tegra_readl(tspi, SLINK_STATUS);
+	if (val & SLINK_BSY)
+		val_write |= SLINK_BSY;
+
+	if (val & SLINK_ERR) {
+		val_write |= SLINK_ERR;
+		pr_err("%s ERROR bit set 0x%lx \n", __func__, val);
+		if (val & SLINK_TX_OVF)
+			val_write |= SLINK_TX_OVF;
+		if (val & SLINK_RX_OVF)
+			val_write |= SLINK_RX_OVF;
+		if (val & SLINK_RX_UNF)
+			val_write |= SLINK_RX_UNF;
+		if (val & SLINK_TX_UNF)
+			val_write |= SLINK_TX_UNF;
+		if (!(val & SLINK_TX_EMPTY))
+			val_write |= SLINK_TX_FLUSH;
+		if (!(val & SLINK_RX_EMPTY))
+			val_write |= SLINK_RX_FLUSH;
+	}
+	spi_tegra_writel(tspi, val_write, SLINK_STATUS);
+}
 static void spi_tegra_go(struct spi_tegra_data *tspi)
 {
 	unsigned long val;
+	unsigned long test_val;
+	unsigned unused_fifo_size;
 
 	wmb();
 
 	val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
 	val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
-	val |= SLINK_DMA_BLOCK_SIZE(tspi->rx_dma_req.size / 4 - 1);
+	if (tspi->is_packed) {
+		val |= SLINK_DMA_BLOCK_SIZE(tspi->rx_dma_req.size - 1);
+		val |= tspi->packed_size;
+	} else {
+		val |= SLINK_DMA_BLOCK_SIZE(tspi->rx_dma_req.size / 4 - 1);
+	}
 	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
-
+	tegra_dma_enqueue_req(tspi->tx_dma, &tspi->tx_dma_req);
 	tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
 
+	val &= ~SLINK_TX_TRIG_MASK & ~SLINK_RX_TRIG_MASK;
+
+	if (tspi->rx_dma_req.size & 0xF)
+		val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1;
+	else if (((tspi->rx_dma_req.size) >> 4) & 0x1)
+		val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4;
+	else
+		val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8;
+
+	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
+	/*
+	 * TRM 24.1.1.7 wait for the FIFO to be full
+	 */
+	test_val = spi_tegra_readl(tspi, SLINK_STATUS2);
+	unused_fifo_size = (tspi->tx_dma_req.size/4) >= 0x20 ?
+					0:
+					SLINK_FIFO_DEPTH - (tspi->tx_dma_req.size/4);
+	while (SLINK_TX_FIFO_EMPTY_COUNT(test_val) != (unused_fifo_size))
+		test_val = spi_tegra_readl(tspi, SLINK_STATUS2);
+
+	if (tspi->is_packed) {
+		val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
+		val |= SLINK_PACKED;
+		spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
+		udelay(1);
+	}
+
+	val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
 	val |= SLINK_DMA_EN;
 	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
 }
+static unsigned spi_tegra_fill_tx_fifo_packed(struct spi_tegra_data *tspi,
+				  struct spi_transfer *t)
+{
+	unsigned len = min(t->len - tspi->cur_pos, BB_LEN *
+				tspi->cur_bytes_per_word);
+	unsigned long val;
+
+	val = spi_tegra_readl(tspi, SLINK_COMMAND);
+	val &= ~SLINK_WORD_SIZE(~0);
+	val |= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1);
+	spi_tegra_writel(tspi, val, SLINK_COMMAND);
+	memcpy(tspi->tx_bb, t->tx_buf, len);
+	tspi->tx_dma_req.size = len;
+	return len;
+}
 
 static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,
 				  struct spi_transfer *t)
@@ -214,16 +314,31 @@ static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,
 	val |= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1);
 	spi_tegra_writel(tspi, val, SLINK_COMMAND);
 
-	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
-		val = 0;
-		for (j = 0; j < tspi->cur_bytes_per_word; j++)
-			val |= tx_buf[i + j] << j * 8;
+	if (tspi->g_bits_per_word == 32) {
+		memcpy(tspi->tx_bb, (void *)tx_buf, len);
+	} else {
+		for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
+			val = 0;
+			for (j = 0; j < tspi->cur_bytes_per_word; j++)
+				val |= tx_buf[i + j] << (tspi->cur_bytes_per_word-j-1) * 8;
 
-		spi_tegra_writel(tspi, val, SLINK_TX_FIFO);
+			tspi->tx_bb[i / tspi->cur_bytes_per_word] = val;
+		}
 	}
 
-	tspi->rx_dma_req.size = len / tspi->cur_bytes_per_word * 4;
+	tspi->tx_dma_req.size = len / tspi->cur_bytes_per_word * 4;
+
+	return len;
+}
 
+static unsigned spi_tegra_drain_rx_fifo_packed(struct spi_tegra_data *tspi,
+				  struct spi_transfer *t)
+{
+	unsigned len = min(t->len - tspi->cur_pos, BB_LEN *
+				tspi->cur_bytes_per_word);
+
+	memcpy(t->rx_buf, tspi->rx_bb, len);
+	tspi->rx_dma_req.size = len;
 	return len;
 }
 
@@ -231,19 +346,47 @@ static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data *tspi,
 				  struct spi_transfer *t)
 {
 	unsigned len = tspi->cur_len;
-	u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_pos;
 	int i, j;
+	u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_pos;
 	unsigned long val;
 
-	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
-		val = tspi->rx_bb[i / tspi->cur_bytes_per_word];
-		for (j = 0; j < tspi->cur_bytes_per_word; j++)
-			rx_buf[i + j] = (val >> (j * 8)) & 0xff;
+	if (tspi->g_bits_per_word == 32) {
+		memcpy(rx_buf, (void *)tspi->rx_bb, len);
+	} else {
+		for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
+			val = tspi->rx_bb[i / tspi->cur_bytes_per_word];
+			for (j = 0; j < tspi->cur_bytes_per_word; j++)
+				rx_buf[i + j] =
+					(val >> (tspi->cur_bytes_per_word - j - 1) * 8) & 0xff;
+		}
 	}
 
 	return len;
 }
 
+static unsigned long spi_tegra_get_packed_size(struct spi_tegra_data *tspi,
+				  struct spi_transfer *t)
+{
+	unsigned long val;
+
+	switch (tspi->cur_bytes_per_word) {
+	case 0:
+		val = SLINK_PACK_SIZE_4;
+		break;
+	case 1:
+		val = SLINK_PACK_SIZE_8;
+		break;
+	case 2:
+		val = SLINK_PACK_SIZE_16;
+		break;
+	case 4:
+		val = SLINK_PACK_SIZE_32;
+		break;
+	default:
+		val = 0;
+	}
+	return val;
+}
 static void spi_tegra_start_transfer(struct spi_device *spi,
 				    struct spi_transfer *t)
 {
@@ -256,8 +399,22 @@ static void spi_tegra_start_transfer(struct spi_device *spi,
 	bits_per_word = t->bits_per_word ? t->bits_per_word  :
 		spi->bits_per_word;
 
+	tspi->g_bits_per_word = bits_per_word;
+
 	tspi->cur_bytes_per_word = (bits_per_word - 1) / 8 + 1;
 
+	/* !!! fix me: Packed mode disabled */
+	tspi->is_packed = 0;
+
+	tspi->packed_size = spi_tegra_get_packed_size(tspi, t);
+	if (tspi->is_packed) {
+		tspi->spi_tegra_tx = spi_tegra_fill_tx_fifo_packed;
+		tspi->spi_tegra_rx = spi_tegra_drain_rx_fifo_packed;
+	} else {
+		tspi->spi_tegra_tx = spi_tegra_fill_tx_fifo;
+		tspi->spi_tegra_rx = spi_tegra_drain_rx_fifo;
+	}
+
 	if (speed != tspi->cur_speed)
 		clk_set_rate(tspi->clk, speed);
 
@@ -266,15 +423,17 @@ static void spi_tegra_start_transfer(struct spi_device *spi,
 
 	tspi->cur_speed = speed;
 
+	spi_tegra_clear_status(tspi);
 	val = spi_tegra_readl(tspi, SLINK_COMMAND2);
-	val &= ~SLINK_SS_EN_CS(~0) | SLINK_RXEN | SLINK_TXEN;
+	val &= ~(SLINK_SS_EN_CS(~0) | SLINK_RXEN | SLINK_TXEN);
 	if (t->rx_buf)
 		val |= SLINK_RXEN;
 	if (t->tx_buf)
 		val |= SLINK_TXEN;
 	val |= SLINK_SS_EN_CS(spi->chip_select);
 	val |= SLINK_SPIE;
-	val |= SLINK_SS_SETUP(3);
+	if (tspi->is_packed)
+		val |= SLINK_CS_ACTIVE_BETWEEN;
 	spi_tegra_writel(tspi, val, SLINK_COMMAND2);
 
 	val = spi_tegra_readl(tspi, SLINK_COMMAND);
@@ -303,8 +462,10 @@ static void spi_tegra_start_transfer(struct spi_device *spi,
 
 	tspi->cur = t;
 	tspi->cur_pos = 0;
-	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, t);
-
+	tspi->cur_len = tspi->spi_tegra_tx(tspi, t);
+	tspi->rx_dma_req.size = tspi->tx_dma_req.size;
+	tspi->rx_complete = 0;
+	tspi->tx_complete = 0;
 	spi_tegra_go(tspi);
 }
 
@@ -319,27 +480,31 @@ static void spi_tegra_start_message(struct spi_device *spi,
 	t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
 	spi_tegra_start_transfer(spi, t);
 }
-
-static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
+static void complete_operation(struct tegra_dma_req *req)
 {
 	struct spi_tegra_data *tspi = req->dev;
-	unsigned long flags;
+	unsigned long val;
 	struct spi_message *m;
 	struct spi_device *spi;
-	int timeout = 0;
-	unsigned long val;
+	u32 timeout = 0;
+	u32 temp = 0;
 
 	/* the SPI controller may come back with both the BSY and RDY bits
-	 * set.  In this case we need to wait for the BSY bit to clear so
-	 * that we are sure the DMA is finished.  1000 reads was empirically
-	 * determined to be long enough.
-	 */
-	while (timeout++ < 1000) {
-		if (!(spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY))
+	* set.  In this case we need to wait for the BSY bit to clear so
+	* that we are sure the DMA is finished.  1000 reads was empirically
+	* determined to be long enough.
+	*/
+
+	while ((spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY)) {
+		if (timeout++ > 1000)
+			break;
+	}
+	while ((spi_tegra_readl(tspi, SLINK_STATUS2)) != SLINK_STATUS2_RESET) {
+		if (temp++ > 50000)
 			break;
 	}
 
-	spin_lock_irqsave(&tspi->lock, flags);
+	spi_tegra_clear_status(tspi);
 
 	val = spi_tegra_readl(tspi, SLINK_STATUS);
 	val |= SLINK_RDY;
@@ -347,22 +512,17 @@ static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
 
 	m = list_first_entry(&tspi->queue, struct spi_message, queue);
 
-	if (timeout >= 1000)
+	if ((timeout >= 1000) || (temp >= 50000))
 		m->status = -EIO;
 
 	spi = m->state;
 
-	tspi->cur_pos += spi_tegra_drain_rx_fifo(tspi, tspi->cur);
+	tspi->cur_pos += tspi->spi_tegra_rx(tspi, tspi->cur);
 	m->actual_length += tspi->cur_pos;
 
-	if (tspi->cur_pos < tspi->cur->len) {
-		tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, tspi->cur);
-		spi_tegra_go(tspi);
-	} else if (!list_is_last(&tspi->cur->transfer_list,
-				 &m->transfers)) {
-		tspi->cur =  list_first_entry(&tspi->cur->transfer_list,
-					      struct spi_transfer,
-					      transfer_list);
+	if (!list_is_last(&tspi->cur->transfer_list, &m->transfers)) {
+		tspi->cur = list_first_entry(&tspi->cur->transfer_list,
+			struct spi_transfer, transfer_list);
 		spi_tegra_start_transfer(spi, tspi->cur);
 	} else {
 		list_del(&m->queue);
@@ -371,7 +531,7 @@ static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
 
 		if (!list_empty(&tspi->queue)) {
 			m = list_first_entry(&tspi->queue, struct spi_message,
-					     queue);
+				queue);
 			spi = m->state;
 			spi_tegra_start_message(spi, m);
 		} else {
@@ -379,6 +539,35 @@ static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
 			tspi->cur_speed = 0;
 		}
 	}
+}
+static void tegra_spi_tx_dma_complete(struct tegra_dma_req *req)
+{
+	struct spi_tegra_data *tspi = req->dev;
+	unsigned long flags;
+
+	spin_lock_irqsave(&tspi->lock, flags);
+
+	(tspi->tx_complete)++;
+
+	if (((tspi->rx_complete) == 1) && ((tspi->tx_complete) == 1))
+		complete_operation(req);
+
+	spin_unlock_irqrestore(&tspi->lock, flags);
+
+}
+
+static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
+{
+	struct spi_tegra_data *tspi = req->dev;
+	unsigned long flags;
+
+
+	spin_lock_irqsave(&tspi->lock, flags);
+
+	(tspi->rx_complete)++;
+
+	if (((tspi->rx_complete) == 1) && ((tspi->tx_complete) == 1))
+		complete_operation(req);
 
 	spin_unlock_irqrestore(&tspi->lock, flags);
 }
@@ -396,7 +585,6 @@ static int spi_tegra_setup(struct spi_device *spi)
 		spi->mode & SPI_CPHA ? "" : "~",
 		spi->max_speed_hz);
 
-
 	switch (spi->chip_select) {
 	case 0:
 		cs_bit = SLINK_CS_POLARITY;
@@ -420,6 +608,13 @@ static int spi_tegra_setup(struct spi_device *spi)
 
 	spin_lock_irqsave(&tspi->lock, flags);
 
+	if (spi->max_speed_hz != tspi->cur_speed)
+		clk_set_rate(tspi->clk, spi->max_speed_hz);
+
+	if (tspi->cur_speed == 0)
+		clk_enable(tspi->clk);
+	tspi->cur_speed = spi->max_speed_hz;
+
 	val = spi_tegra_readl(tspi, SLINK_COMMAND);
 	if (spi->mode & SPI_CS_HIGH)
 		val |= cs_bit;
@@ -489,7 +684,8 @@ static int __init spi_tegra_probe(struct platform_device *pdev)
 	/* the spi->mode bits understood by this driver: */
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
 
-	master->bus_num = pdev->id;
+	if (pdev->id != -1)
+		master->bus_num = pdev->id;
 
 	master->setup = spi_tegra_setup;
 	master->transfer = spi_tegra_transfer;
@@ -530,8 +726,7 @@ static int __init spi_tegra_probe(struct platform_device *pdev)
 
 	INIT_LIST_HEAD(&tspi->queue);
 
-	tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT |
-		TEGRA_DMA_SHARED);
+	tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
 	if (!tspi->rx_dma) {
 		dev_err(&pdev->dev, "can not allocate rx dma channel\n");
 		ret = -ENODEV;
@@ -546,23 +741,58 @@ static int __init spi_tegra_probe(struct platform_device *pdev)
 		goto err4;
 	}
 
+	memset(&tspi->rx_dma_req, 0, sizeof(struct tegra_dma_req));
 	tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
 	tspi->rx_dma_req.to_memory = 1;
 	tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
+	tspi->rx_dma_req.virt_addr = tspi->rx_bb;
 	tspi->rx_dma_req.dest_bus_width = 32;
 	tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
 	tspi->rx_dma_req.source_bus_width = 32;
 	tspi->rx_dma_req.source_wrap = 4;
+	tspi->rx_dma_req.dest_wrap = 0;
 	tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
 	tspi->rx_dma_req.dev = tspi;
 
+	tspi->tx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
+	if (IS_ERR(tspi->tx_dma)) {
+		dev_err(&pdev->dev, "can not allocate tx dma channel\n");
+		ret = PTR_ERR(tspi->tx_dma);
+		goto err5;
+	}
+
+	tspi->tx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
+					 &tspi->tx_bb_phys, GFP_KERNEL);
+	if (!tspi->tx_bb) {
+		dev_err(&pdev->dev, "can not allocate tx bounce buffer\n");
+		ret = -ENOMEM;
+		goto err6;
+	}
+
+	memset(&tspi->tx_dma_req, 0, sizeof(struct tegra_dma_req));
+	tspi->tx_dma_req.complete = tegra_spi_tx_dma_complete;
+	tspi->tx_dma_req.to_memory = 0;
+	tspi->tx_dma_req.dest_addr = tspi->phys + SLINK_TX_FIFO;
+	tspi->tx_dma_req.virt_addr = tspi->tx_bb;
+	tspi->tx_dma_req.dest_bus_width = 32;
+	tspi->tx_dma_req.dest_wrap = 4;
+	tspi->tx_dma_req.source_wrap = 0;
+	tspi->tx_dma_req.source_addr = tspi->tx_bb_phys;
+	tspi->tx_dma_req.source_bus_width = 32;
+	tspi->tx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
+	tspi->tx_dma_req.dev = tspi;
 	ret = spi_register_master(master);
 
 	if (ret < 0)
-		goto err5;
+		goto err7;
 
 	return ret;
 
+err7:
+	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
+				tspi->tx_bb, tspi->tx_bb_phys);
+err6:
+	tegra_dma_free_channel(tspi->tx_dma);
 err5:
 	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
 			  tspi->rx_bb, tspi->rx_bb_phys);
@@ -609,7 +839,7 @@ static int spi_tegra_suspend(struct platform_device *pdev, pm_message_t state)
 	struct spi_master	*master;
 	struct spi_tegra_data	*tspi;
 	unsigned long		flags;
-	unsigned                limit = 500;
+	unsigned		limit = 50;
 
 	master = dev_get_drvdata(&pdev->dev);
 	tspi = spi_master_get_devdata(master);
diff --git a/drivers/staging/iio/light/Kconfig b/drivers/staging/iio/light/Kconfig
index 3ddc478e6182..0d601440c6f0 100644
--- a/drivers/staging/iio/light/Kconfig
+++ b/drivers/staging/iio/light/Kconfig
@@ -9,6 +9,17 @@ config SENSORS_TSL2563
 	help
 	 If you say yes here you get support for the Taos TSL2560,
 	 TSL2561, TSL2562 and TSL2563 ambient light sensors.
-
 	 This driver can also be built as a module.  If so, the module
 	 will be called tsl2563.
+
+config ISL29018
+	tristate "ISL 29018 light and proximity sensor"
+	depends on I2C
+	default n
+	help
+	 If you say yes here you get support for ambient light sensing and
+	 proximity ir sensing from intersil ISL29018.
+	 This driver will provide the measurements of ambient light intensity
+	 in lux, proximity infrared sensing and normal infrared sensing.
+	 Data from sensor is accessible via sysfs.
+
diff --git a/drivers/staging/iio/light/Makefile b/drivers/staging/iio/light/Makefile
index 30f3300e2a68..3978722c7a29 100644
--- a/drivers/staging/iio/light/Makefile
+++ b/drivers/staging/iio/light/Makefile
@@ -2,4 +2,5 @@
 # Makefile for industrial I/O Light sensors
 #
 
-obj-$(CONFIG_SENSORS_TSL2563)	+= tsl2563.o
+obj-$(CONFIG_SENSORS_TSL2563)   += tsl2563.o
+obj-$(CONFIG_ISL29018)          += isl29018.o
diff --git a/drivers/staging/iio/light/isl29018.c b/drivers/staging/iio/light/isl29018.c
new file mode 100644
index 000000000000..179835e7a84f
--- /dev/null
+++ b/drivers/staging/iio/light/isl29018.c
@@ -0,0 +1,580 @@
+/*
+ * A iio driver for the light sensor ISL 29018.
+ *
+ * Hwmon driver for monitoring ambient light intensity in luxi, proximity
+ * sensing and infrared sensing.
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA	02110-1301, USA.
+ */
+
+#include <linux/regulator/consumer.h>
+#include <linux/module.h>
+#include <linux/i2c.h>
+#include <linux/err.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include "../iio.h"
+
+#define CONVERSION_TIME_MS		100
+
+#define ISL29018_REG_ADD_COMMAND1	0x00
+#define COMMMAND1_OPMODE_SHIFT		5
+#define COMMMAND1_OPMODE_MASK		(7 << COMMMAND1_OPMODE_SHIFT)
+#define COMMMAND1_OPMODE_POWER_DOWN	0
+#define COMMMAND1_OPMODE_ALS_ONCE	1
+#define COMMMAND1_OPMODE_IR_ONCE	2
+#define COMMMAND1_OPMODE_PROX_ONCE	3
+
+#define ISL29018_REG_ADD_COMMANDII	0x01
+#define COMMANDII_RESOLUTION_SHIFT	2
+#define COMMANDII_RESOLUTION_MASK	(0x3 << COMMANDII_RESOLUTION_SHIFT)
+
+#define COMMANDII_RANGE_SHIFT		0
+#define COMMANDII_RANGE_MASK		(0x3 << COMMANDII_RANGE_SHIFT)
+
+#define COMMANDII_SCHEME_SHIFT		7
+#define COMMANDII_SCHEME_MASK		(0x1 << COMMANDII_SCHEME_SHIFT)
+
+#define ISL29018_REG_ADD_DATA_LSB	0x02
+#define ISL29018_REG_ADD_DATA_MSB	0x03
+#define ISL29018_MAX_REGS		ISL29018_REG_ADD_DATA_MSB
+
+struct isl29018_chip {
+	struct iio_dev		*indio_dev;
+	struct i2c_client	*client;
+	struct mutex		lock;
+	unsigned int		range;
+	unsigned int		adc_bit;
+	int			prox_scheme;
+	u8			reg_cache[ISL29018_MAX_REGS];
+	struct regulator 	*regulator;
+};
+
+static bool isl29018_write_data(struct i2c_client *client, u8 reg,
+	u8 val, u8 mask, u8 shift)
+{
+	u8 regval;
+	int ret = 0;
+	struct isl29018_chip *chip = i2c_get_clientdata(client);
+
+	regval = chip->reg_cache[reg];
+	regval &= ~mask;
+	regval |= val << shift;
+
+	ret = i2c_smbus_write_byte_data(client, reg, regval);
+	if (ret) {
+		dev_err(&client->dev, "Write to device fails status %x\n", ret);
+		return false;
+	}
+	chip->reg_cache[reg] = regval;
+	return true;
+}
+
+static bool isl29018_set_range(struct i2c_client *client, unsigned long range,
+		unsigned int *new_range)
+{
+	unsigned long supp_ranges[] = {1000, 4000, 16000, 64000};
+	int i;
+
+	for (i = 0; i < (ARRAY_SIZE(supp_ranges) -1); ++i) {
+		if (range <= supp_ranges[i])
+			break;
+	}
+	*new_range = (unsigned int)supp_ranges[i];
+
+	return isl29018_write_data(client, ISL29018_REG_ADD_COMMANDII,
+		i, COMMANDII_RANGE_MASK, COMMANDII_RANGE_SHIFT);
+}
+
+static bool isl29018_set_resolution(struct i2c_client *client,
+			unsigned long adcbit, unsigned int *conf_adc_bit)
+{
+	unsigned long supp_adcbit[] = {16, 12, 8, 4};
+	int i;
+
+	for (i = 0; i < (ARRAY_SIZE(supp_adcbit)); ++i) {
+		if (adcbit == supp_adcbit[i])
+			break;
+	}
+	*conf_adc_bit = (unsigned int)supp_adcbit[i];
+
+	return isl29018_write_data(client, ISL29018_REG_ADD_COMMANDII,
+		i, COMMANDII_RESOLUTION_MASK, COMMANDII_RESOLUTION_SHIFT);
+}
+
+static int isl29018_read_sensor_input(struct i2c_client *client, int mode)
+{
+	bool status;
+	int lsb;
+	int msb;
+
+	/* Set mode */
+	status = isl29018_write_data(client, ISL29018_REG_ADD_COMMAND1,
+			mode, COMMMAND1_OPMODE_MASK, COMMMAND1_OPMODE_SHIFT);
+	if (!status) {
+		dev_err(&client->dev, "Error in setting operating mode\n");
+		return -EBUSY;
+	}
+
+	msleep(CONVERSION_TIME_MS);
+	lsb = i2c_smbus_read_byte_data(client, ISL29018_REG_ADD_DATA_LSB);
+	if (lsb < 0) {
+		dev_err(&client->dev, "Error in reading LSB DATA\n");
+		return lsb;
+	}
+
+	msb = i2c_smbus_read_byte_data(client, ISL29018_REG_ADD_DATA_MSB);
+	if (msb < 0) {
+		dev_err(&client->dev, "Error in reading MSB DATA\n");
+		return msb;
+	}
+
+	dev_vdbg(&client->dev, "MSB 0x%x and LSB 0x%x\n", msb, lsb);
+
+	return ((msb << 8) | lsb);
+}
+
+static bool isl29018_read_lux(struct i2c_client *client, int *lux)
+{
+	int lux_data;
+	struct isl29018_chip *chip = i2c_get_clientdata(client);
+
+	lux_data = isl29018_read_sensor_input(client, COMMMAND1_OPMODE_ALS_ONCE);
+	if (lux_data > 0) {
+		*lux = (lux_data * chip->range) >> chip->adc_bit;
+		return true;
+	}
+	return false;
+}
+
+static bool isl29018_read_ir(struct i2c_client *client, int *ir)
+{
+	int ir_data;
+
+	ir_data = isl29018_read_sensor_input(client, COMMMAND1_OPMODE_IR_ONCE);
+	if (ir_data > 0) {
+		*ir = ir_data;
+		return true;
+	}
+	return false;
+}
+
+static bool isl29018_read_proximity_ir(struct i2c_client *client, int scheme,
+	int *near_ir)
+{
+	bool status;
+	int prox_data = -1;
+	int ir_data = -1;
+
+	/* Do proximity sensing with required scheme */
+	status = isl29018_write_data(client, ISL29018_REG_ADD_COMMANDII,
+			scheme, COMMANDII_SCHEME_MASK, COMMANDII_SCHEME_SHIFT);
+	if (!status) {
+		dev_err(&client->dev, "Error in setting operating mode\n");
+		return false;
+	}
+
+	prox_data = isl29018_read_sensor_input(client,
+		COMMMAND1_OPMODE_PROX_ONCE);
+	if (scheme == 1) {
+		if (prox_data >= 0) {
+			*near_ir = prox_data;
+			return true;
+		}
+		return false;
+	}
+
+	if (prox_data >= 0)
+		ir_data = isl29018_read_sensor_input(client,
+				COMMMAND1_OPMODE_IR_ONCE);
+
+	if (prox_data >= 0 && ir_data >= 0) {
+		if (prox_data >= ir_data) {
+			*near_ir = prox_data - ir_data;
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static ssize_t get_sensor_data(struct device *dev, char *buf, int mode)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+	struct isl29018_chip *chip = indio_dev->dev_data;
+	struct i2c_client *client = chip->client;
+	int value = 0;
+	bool status;
+
+	mutex_lock(&chip->lock);
+	switch (mode) {
+		case COMMMAND1_OPMODE_PROX_ONCE:
+			status = isl29018_read_proximity_ir(client,
+				chip->prox_scheme, &value);
+			break;
+
+		case COMMMAND1_OPMODE_ALS_ONCE:
+			status = isl29018_read_lux(client, &value);
+			break;
+
+		case COMMMAND1_OPMODE_IR_ONCE:
+			status = isl29018_read_ir(client, &value);
+			break;
+
+		default:
+			dev_err(&client->dev,"Mode %d is not supported\n",mode);
+			mutex_unlock(&chip->lock);
+			return -EBUSY;
+	}
+
+	if (!status) {
+		dev_err(&client->dev, "Error in Reading data");
+		mutex_unlock(&chip->lock);
+		return -EBUSY;
+	}
+
+	mutex_unlock(&chip->lock);
+	return sprintf(buf, "%d\n", value);
+}
+
+/* Sysfs interface */
+/* range */
+static ssize_t show_range(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+	struct isl29018_chip *chip = indio_dev->dev_data;
+
+	dev_vdbg(dev, "%s()\n", __func__);
+	return sprintf(buf, "%u\n", chip->range);
+}
+
+static ssize_t store_range(struct device *dev,
+		struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+	struct isl29018_chip *chip = indio_dev->dev_data;
+	struct i2c_client *client = chip->client;
+	bool status;
+	unsigned long lval;
+	unsigned int new_range;
+
+	dev_vdbg(dev, "%s()\n", __func__);
+
+	if (strict_strtoul(buf, 10, &lval))
+		return -EINVAL;
+
+	if (!(lval == 1000UL || lval == 4000UL ||
+		lval == 16000UL || lval == 64000UL)) {
+		dev_err(dev, "The range is not supported\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&chip->lock);
+	status = isl29018_set_range(client, lval, &new_range);
+	if (!status) {
+		mutex_unlock(&chip->lock);
+		dev_err(dev, "Error in setting max range\n");
+		return -EINVAL;
+	}
+	chip->range = new_range;
+	mutex_unlock(&chip->lock);
+	return count;
+}
+
+/* resolution */
+static ssize_t show_resolution(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+	struct isl29018_chip *chip = indio_dev->dev_data;
+
+	dev_vdbg(dev, "%s()\n", __func__);
+	return sprintf(buf, "%u\n", chip->adc_bit);
+}
+
+static ssize_t store_resolution(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+	struct isl29018_chip *chip = indio_dev->dev_data;
+	struct i2c_client *client = chip->client;
+	bool status;
+	unsigned long lval;
+	unsigned int new_adc_bit;
+
+	dev_vdbg(dev, "%s()\n", __func__);
+
+	if (strict_strtoul(buf, 10, &lval))
+		return -EINVAL;
+	if (!(lval == 4 || lval == 8 || lval == 12 || lval == 16)) {
+		dev_err(dev, "The resolution is not supported\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&chip->lock);
+	status = isl29018_set_resolution(client, lval, &new_adc_bit);
+	if (!status) {
+		mutex_unlock(&chip->lock);
+		dev_err(dev, "Error in setting resolution\n");
+		return -EINVAL;
+	}
+	chip->adc_bit = new_adc_bit;
+	mutex_unlock(&chip->lock);
+	return count;
+}
+
+/* proximity scheme */
+static ssize_t show_prox_scheme(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+	struct isl29018_chip *chip = indio_dev->dev_data;
+
+	dev_vdbg(dev, "%s()\n", __func__);
+	return sprintf(buf, "%d\n", chip->prox_scheme);
+}
+
+static ssize_t store_prox_scheme(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+	struct isl29018_chip *chip = indio_dev->dev_data;
+	unsigned long lval;
+
+	dev_vdbg(dev, "%s()\n", __func__);
+
+	if (strict_strtoul(buf, 10, &lval))
+		return -EINVAL;
+	if (!(lval == 0UL || lval == 1UL)) {
+		dev_err(dev, "The scheme is not supported\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&chip->lock);
+	chip->prox_scheme = (int)lval;
+	mutex_unlock(&chip->lock);
+	return count;
+}
+
+/* Read lux */
+static ssize_t show_lux(struct device *dev,
+	struct device_attribute *devattr, char *buf)
+{
+	return get_sensor_data(dev, buf, COMMMAND1_OPMODE_ALS_ONCE);
+}
+
+/* Read ir */
+static ssize_t show_ir(struct device *dev,
+	struct device_attribute *devattr, char *buf)
+{
+	return get_sensor_data(dev, buf, COMMMAND1_OPMODE_IR_ONCE);
+}
+
+/* Read nearest ir */
+static ssize_t show_proxim_ir(struct device *dev,
+	struct device_attribute *devattr, char *buf)
+{
+	return get_sensor_data(dev, buf, COMMMAND1_OPMODE_PROX_ONCE);
+}
+
+/* Read name */
+static ssize_t show_name(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+	struct isl29018_chip *chip = indio_dev->dev_data;
+	return sprintf(buf, "%s\n", chip->client->name);
+}
+
+static IIO_DEVICE_ATTR(range, S_IRUGO | S_IWUSR, show_range, store_range, 0);
+static IIO_DEVICE_ATTR(resolution, S_IRUGO | S_IWUSR,
+	show_resolution, store_resolution, 0);
+static IIO_DEVICE_ATTR(proximity_scheme, S_IRUGO | S_IWUSR,
+	show_prox_scheme, store_prox_scheme, 0);
+static IIO_DEVICE_ATTR(lux, S_IRUGO, show_lux, NULL, 0);
+static IIO_DEVICE_ATTR(ir, S_IRUGO, show_ir, NULL, 0);
+static IIO_DEVICE_ATTR(proxim_ir, S_IRUGO, show_proxim_ir, NULL, 0);
+static IIO_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, 0);
+
+static struct attribute *isl29018_attributes[] = {
+	&iio_dev_attr_name.dev_attr.attr,
+	&iio_dev_attr_range.dev_attr.attr,
+	&iio_dev_attr_resolution.dev_attr.attr,
+	&iio_dev_attr_proximity_scheme.dev_attr.attr,
+	&iio_dev_attr_lux.dev_attr.attr,
+	&iio_dev_attr_ir.dev_attr.attr,
+	&iio_dev_attr_proxim_ir.dev_attr.attr,
+	NULL
+};
+
+static const struct attribute_group isl29108_group = {
+	.attrs = isl29018_attributes,
+};
+
+static void isl29018_regulator_enable(struct i2c_client *client)
+{
+	struct isl29018_chip *chip = i2c_get_clientdata(client);
+
+	chip->regulator = regulator_get(NULL, "vdd_vcore_phtn");
+	if (IS_ERR_OR_NULL(chip->regulator)) {
+		dev_err(&client->dev, "Couldn't get regulator vdd_vcore_phtn\n");
+		chip->regulator = NULL;
+	}
+	else {
+		regulator_enable(chip->regulator);
+		/* Optimal time to get the regulator turned on
+		 * before initializing isl29018 chip*/
+		mdelay(5);
+	}
+}
+
+static void isl29018_regulator_disable(struct i2c_client *client)
+{
+	struct isl29018_chip *chip = i2c_get_clientdata(client);
+	struct regulator *isl29018_reg = chip->regulator;
+	int ret;
+
+	if (isl29018_reg) {
+		ret = regulator_is_enabled(isl29018_reg);
+		if (ret > 0)
+			regulator_disable(isl29018_reg);
+		regulator_put(isl29018_reg);
+	}
+	chip->regulator = NULL;
+}
+
+static int isl29018_chip_init(struct i2c_client *client)
+{
+	struct isl29018_chip *chip = i2c_get_clientdata(client);
+	bool status;
+	int i;
+	int new_adc_bit;
+	unsigned int new_range;
+
+	isl29018_regulator_enable(client);
+
+	for (i = 0; i < ARRAY_SIZE(chip->reg_cache); i++) {
+		chip->reg_cache[i] = 0;
+	}
+
+	/* set defaults */
+	status = isl29018_set_range(client, chip->range, &new_range);
+	if (status)
+		status = isl29018_set_resolution(client, chip->adc_bit,
+				&new_adc_bit);
+	if (!status) {
+		dev_err(&client->dev, "Init of isl29018 fails\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+static int __devinit isl29018_probe(struct i2c_client *client,
+	const struct i2c_device_id *id)
+{
+	struct isl29018_chip *chip;
+	int err;
+
+	chip = kzalloc(sizeof (struct isl29018_chip), GFP_KERNEL);
+	if (!chip) {
+		dev_err(&client->dev, "Memory allocation fails\n");
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	i2c_set_clientdata(client, chip);
+	chip->client = client;
+
+	mutex_init(&chip->lock);
+
+	chip->range = 1000;
+	chip->adc_bit = 16;
+
+	err = isl29018_chip_init(client);
+	if (err)
+		goto exit_free;
+
+	chip->indio_dev = iio_allocate_device();
+	if (!chip->indio_dev) {
+		dev_err(&client->dev, "iio allocation fails\n");
+		goto exit_free;
+	}
+
+	chip->indio_dev->attrs = &isl29108_group;
+	chip->indio_dev->dev.parent = &client->dev;
+	chip->indio_dev->dev_data = (void *)(chip);
+	chip->indio_dev->driver_module = THIS_MODULE;
+	chip->indio_dev->modes = INDIO_DIRECT_MODE;
+	err = iio_device_register(chip->indio_dev);
+	if (err) {
+		dev_err(&client->dev, "iio registration fails\n");
+		goto exit_iio_free;
+	}
+
+	return 0;
+
+exit_iio_free:
+	iio_free_device(chip->indio_dev);
+exit_free:
+	kfree(chip);
+exit:
+	return err;
+}
+
+static int __devexit isl29018_remove(struct i2c_client *client)
+{
+	struct isl29018_chip *chip = i2c_get_clientdata(client);
+
+	dev_dbg(&client->dev, "%s()\n", __func__);
+	isl29018_regulator_disable(client);
+	iio_device_unregister(chip->indio_dev);
+	kfree(chip);
+	return 0;
+}
+
+static const struct i2c_device_id isl29018_id[] = {
+	{"isl29018", 0},
+	{}
+};
+
+MODULE_DEVICE_TABLE(i2c, isl29018_id);
+
+static struct i2c_driver isl29018_driver = {
+	.class	= I2C_CLASS_HWMON,
+	.driver  = {
+		.name = "isl29018",
+		.owner = THIS_MODULE,
+	},
+	.probe	 = isl29018_probe,
+	.remove  = __devexit_p(isl29018_remove),
+	.id_table = isl29018_id,
+};
+
+static int __init isl29018_init(void)
+{
+	return i2c_add_driver(&isl29018_driver);
+}
+
+static void __exit isl29018_exit(void)
+{
+	i2c_del_driver(&isl29018_driver);
+}
+
+module_init(isl29018_init);
+module_exit(isl29018_exit);
diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 5cca00a6d09d..84fee0f5dc34 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -1265,6 +1265,14 @@ static void hcd_free_coherent(struct usb_bus *bus, dma_addr_t *dma_handle,
 
 static void unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
 {
+	if (hcd->driver->unmap_urb_for_dma)
+		hcd->driver->unmap_urb_for_dma(hcd, urb);
+	else
+		usb_hcd_unmap_urb_for_dma(hcd, urb);
+}
+
+void usb_hcd_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
+{
 	enum dma_data_direction dir;
 
 	if (urb->transfer_flags & URB_SETUP_MAP_SINGLE)
@@ -1311,6 +1319,15 @@ static void unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
 static int map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
 			   gfp_t mem_flags)
 {
+	if (hcd->driver->map_urb_for_dma)
+		return hcd->driver->map_urb_for_dma(hcd, urb, mem_flags);
+	else
+		return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
+}
+
+int usb_hcd_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
+			    gfp_t mem_flags)
+{
 	enum dma_data_direction dir;
 	int ret = 0;
 
@@ -1400,7 +1417,7 @@ static int map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
 		}
 		if (ret && (urb->transfer_flags & (URB_SETUP_MAP_SINGLE |
 				URB_SETUP_MAP_LOCAL)))
-			unmap_urb_for_dma(hcd, urb);
+			usb_hcd_unmap_urb_for_dma(hcd, urb);
 	}
 	return ret;
 }
diff --git a/drivers/usb/gadget/f_adb.c b/drivers/usb/gadget/f_adb.c
index a0b0774b9556..b9884d408a2a 100644
--- a/drivers/usb/gadget/f_adb.c
+++ b/drivers/usb/gadget/f_adb.c
@@ -154,12 +154,16 @@ static void adb_request_free(struct usb_request *req, struct usb_ep *ep)
 
 static inline int _lock(atomic_t *excl)
 {
+	int ret = -1;
+
+	preempt_disable();
 	if (atomic_inc_return(excl) == 1) {
-		return 0;
-	} else {
+		ret = 0;
+	} else
 		atomic_dec(excl);
-		return -1;
-	}
+
+	preempt_enable();
+	return ret;
 }
 
 static inline void _unlock(atomic_t *excl)
@@ -409,9 +413,25 @@ static ssize_t adb_write(struct file *fp, const char __user *buf,
 
 static int adb_open(struct inode *ip, struct file *fp)
 {
-	printk(KERN_INFO "adb_open\n");
-	if (_lock(&_adb_dev->open_excl))
+	static unsigned long last_print;
+	static unsigned long count = 0;
+
+	if (++count == 1)
+		last_print = jiffies;
+	else {
+		if (!time_before(jiffies, last_print + HZ/2))
+			count = 0;
+		last_print = jiffies;
+	}
+
+	if (_lock(&_adb_dev->open_excl)) {
+		cpu_relax();
 		return -EBUSY;
+	}
+
+	if (count < 5)
+		printk(KERN_INFO "adb_open(%s)\n", current->comm);
+
 
 	fp->private_data = _adb_dev;
 
@@ -423,7 +443,19 @@ static int adb_open(struct inode *ip, struct file *fp)
 
 static int adb_release(struct inode *ip, struct file *fp)
 {
-	printk(KERN_INFO "adb_release\n");
+	static unsigned long last_print;
+	static unsigned long count = 0;
+
+	if (++count == 1)
+		last_print = jiffies;
+	else {
+		if (!time_before(jiffies, last_print + HZ/2))
+			count = 0;
+		last_print = jiffies;
+	}
+
+	if (count < 5)
+		printk(KERN_INFO "adb_release\n");
 	_unlock(&_adb_dev->open_excl);
 	return 0;
 }
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
index 2fab37a2a094..8ad167503696 100644
--- a/drivers/usb/gadget/fsl_udc_core.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -367,6 +367,10 @@ static void dr_controller_stop(struct fsl_udc *udc)
 {
 	unsigned int tmp;
 
+	/* Clear pending interrupt status bits */
+	tmp = fsl_readl(&dr_regs->usbsts);
+	fsl_writel(tmp, &dr_regs->usbsts);
+
 	/* disable all INTR */
 	fsl_writel(0, &dr_regs->usbintr);
 
@@ -623,12 +627,18 @@ static int fsl_ep_disable(struct usb_ep *_ep)
 
 	/* disable ep on controller */
 	ep_num = ep_index(ep);
-	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
-	if (ep_is_in(ep))
-		epctrl &= ~EPCTRL_TX_ENABLE;
-	else
-		epctrl &= ~EPCTRL_RX_ENABLE;
-	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+#if defined(CONFIG_ARCH_TEGRA)
+	/* Touch the registers if cable is connected and phy is on */
+	if (udc_controller->vbus_active)
+#endif
+	{
+		epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+		if (ep_is_in(ep))
+			epctrl &= ~EPCTRL_TX_ENABLE;
+		else
+			epctrl &= ~EPCTRL_RX_ENABLE;
+		fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+	}
 
 	udc = (struct fsl_udc *)ep->udc;
 	spin_lock_irqsave(&udc->lock, flags);
@@ -955,12 +965,19 @@ static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 	/* Stop the ep before we deal with the queue */
 	ep->stopped = 1;
 	ep_num = ep_index(ep);
-	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
-	if (ep_is_in(ep))
-		epctrl &= ~EPCTRL_TX_ENABLE;
-	else
-		epctrl &= ~EPCTRL_RX_ENABLE;
-	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+
+#if defined(CONFIG_ARCH_TEGRA)
+	/* Touch the registers if cable is connected and phy is on */
+	if (udc_controller->vbus_active)
+#endif
+	{
+		epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+		if (ep_is_in(ep))
+			epctrl &= ~EPCTRL_TX_ENABLE;
+		else
+			epctrl &= ~EPCTRL_RX_ENABLE;
+		fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+	}
 
 	/* make sure it's actually queued on this endpoint */
 	list_for_each_entry(req, &ep->queue, queue) {
@@ -1003,12 +1020,19 @@ static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 	done(ep, req, -ECONNRESET);
 
 	/* Enable EP */
-out:	epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
-	if (ep_is_in(ep))
-		epctrl |= EPCTRL_TX_ENABLE;
-	else
-		epctrl |= EPCTRL_RX_ENABLE;
-	fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+out:
+#if defined(CONFIG_ARCH_TEGRA)
+	/* Touch the registers if cable is connected and phy is on */
+	if (udc_controller->vbus_active)
+#endif
+	{
+		epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
+		if (ep_is_in(ep))
+			epctrl |= EPCTRL_TX_ENABLE;
+		else
+			epctrl |= EPCTRL_RX_ENABLE;
+		fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
+	}
 	ep->stopped = stopped;
 
 	spin_unlock_irqrestore(&ep->udc->lock, flags);
@@ -1076,6 +1100,12 @@ static void fsl_ep_fifo_flush(struct usb_ep *_ep)
 	unsigned long timeout;
 #define FSL_UDC_FLUSH_TIMEOUT 1000
 
+#if defined(CONFIG_ARCH_TEGRA)
+	/* Touch the registers if cable is connected and phy is on */
+	if (!udc_controller->vbus_active)
+		return;
+#endif
+
 	if (!_ep) {
 		return;
 	} else {
@@ -1138,6 +1168,7 @@ static int fsl_get_frame(struct usb_gadget *gadget)
 /*-----------------------------------------------------------------------
  * Tries to wake up the host connected to this gadget
  -----------------------------------------------------------------------*/
+#ifndef CONFIG_USB_ANDROID
 static int fsl_wakeup(struct usb_gadget *gadget)
 {
 	struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
@@ -1156,6 +1187,7 @@ static int fsl_wakeup(struct usb_gadget *gadget)
 	fsl_writel(portsc, &dr_regs->portsc1);
 	return 0;
 }
+#endif
 
 static int can_pullup(struct fsl_udc *udc)
 {
@@ -1253,7 +1285,9 @@ static int fsl_pullup(struct usb_gadget *gadget, int is_on)
 /* defined in gadget.h */
 static struct usb_gadget_ops fsl_gadget_ops = {
 	.get_frame = fsl_get_frame,
+#ifndef CONFIG_USB_ANDROID
 	.wakeup = fsl_wakeup,
+#endif
 /*	.set_selfpowered = fsl_set_selfpowered,	*/ /* Always selfpowered */
 	.vbus_session = fsl_vbus_session,
 	.vbus_draw = fsl_vbus_draw,
@@ -1581,7 +1615,7 @@ static void setup_received_irq(struct fsl_udc *udc,
 		udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
 				?  USB_DIR_IN : USB_DIR_OUT;
 		spin_unlock(&udc->lock);
-		if (udc->driver->setup(&udc->gadget,
+		if (udc->driver && udc->driver->setup(&udc->gadget,
 				&udc->local_setup_buff) < 0)
 			ep0stall(udc);
 		spin_lock(&udc->lock);
@@ -1591,7 +1625,7 @@ static void setup_received_irq(struct fsl_udc *udc,
 		/* No data phase, IN status from gadget */
 		udc->ep0_dir = USB_DIR_IN;
 		spin_unlock(&udc->lock);
-		if (udc->driver->setup(&udc->gadget,
+		if (udc->driver && udc->driver->setup(&udc->gadget,
 				&udc->local_setup_buff) < 0)
 			ep0stall(udc);
 		spin_lock(&udc->lock);
@@ -1837,7 +1871,7 @@ static void suspend_irq(struct fsl_udc *udc)
 	udc->usb_state = USB_STATE_SUSPENDED;
 
 	/* report suspend to the driver, serial.c does not support this */
-	if (udc->driver->suspend)
+	if (udc->driver && udc->driver->suspend)
 		udc->driver->suspend(&udc->gadget);
 }
 
@@ -1847,7 +1881,7 @@ static void bus_resume(struct fsl_udc *udc)
 	udc->resume_state = 0;
 
 	/* report resume to the driver, serial.c does not support this */
-	if (udc->driver->resume)
+	if (udc->driver && udc->driver->resume)
 		udc->driver->resume(&udc->gadget);
 }
 
@@ -1861,7 +1895,8 @@ static int reset_queues(struct fsl_udc *udc)
 
 	/* report disconnect; the driver is already quiesced */
 	spin_unlock(&udc->lock);
-	udc->driver->disconnect(&udc->gadget);
+	if (udc->driver && udc->driver->disconnect)
+		udc->driver->disconnect(&udc->gadget);
 	spin_lock(&udc->lock);
 
 	return 0;
@@ -1942,6 +1977,25 @@ static void reset_irq(struct fsl_udc *udc)
 #endif
 }
 
+#if defined(CONFIG_ARCH_TEGRA)
+/*
+ * Restart device controller in the OTG mode on VBUS detection
+ */
+static void fsl_udc_restart(struct fsl_udc *udc)
+{
+       /* setup the controller in the device mode */
+       dr_controller_setup(udc);
+       /* setup EP0 for setup packet */
+       ep0_setup(udc);
+       /* start the controller */
+       dr_controller_run(udc);
+       /* initialize the USB and EP states */
+       udc->usb_state = USB_STATE_ATTACHED;
+       udc->ep0_state = WAIT_FOR_SETUP;
+       udc->ep0_dir = 0;
+}
+#endif
+
 /*
  * USB device controller interrupt handler
  */
@@ -2756,12 +2810,27 @@ static int __exit fsl_udc_remove(struct platform_device *pdev)
  -----------------------------------------------------------------*/
 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
 {
-	if (udc_controller->transceiver &&
-		    udc_controller->transceiver->state != OTG_STATE_B_PERIPHERAL)
-		return 0;
-
-	dr_controller_stop(udc_controller);
-	return 0;
+    if (udc_controller->transceiver) {
+        if (udc_controller->transceiver->state != OTG_STATE_B_PERIPHERAL) {
+            /* we are not in device mode, return */
+            return 0;
+        }
+    }
+    if (udc_controller->vbus_active) {
+        spin_lock(&udc_controller->lock);
+        /* Reset all internal Queues and inform client driver */
+        reset_queues(udc_controller);
+        udc_controller->vbus_active = 0;
+        udc_controller->usb_state = USB_STATE_DEFAULT;
+        spin_unlock(&udc_controller->lock);
+    }
+    /* stop the controller and turn off the clocks */
+    dr_controller_stop(udc_controller);
+    if (udc_controller->transceiver) {
+        udc_controller->transceiver->state = OTG_STATE_UNDEFINED;
+    }
+    fsl_udc_clk_suspend();
+    return 0;
 }
 
 /*-----------------------------------------------------------------
@@ -2770,19 +2839,43 @@ static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
  *-----------------------------------------------------------------*/
 static int fsl_udc_resume(struct platform_device *pdev)
 {
-	if (udc_controller->transceiver &&
-		    udc_controller->transceiver->state != OTG_STATE_B_PERIPHERAL)
-		return 0;
+    if (udc_controller->transceiver) {
+        if (!(fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_ID_PIN_STATUS)) {
+            /* If ID status is low means host is connected, return */
+            return 0;
+        }
+        /* enable clock and check for VBUS */
+        fsl_udc_clk_resume();
+        if (!(fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_VBUS_STATUS)) {
+            /* if there is no VBUS then power down the clocks and return */
+            fsl_udc_clk_suspend();
+            return 0;
+        } else {
+            /* Detected VBUS set the transceiver state to device mode */
+            udc_controller->transceiver->state = OTG_STATE_B_PERIPHERAL;
+        }
+    } else {
+        /* enable the clocks to the controller */
+        fsl_udc_clk_resume();
+    }
 
-	/* Enable DR irq reg and set controller Run */
-	if (udc_controller->stopped) {
-		dr_controller_setup(udc_controller);
-		dr_controller_run(udc_controller);
-	}
-	udc_controller->usb_state = USB_STATE_ATTACHED;
-	udc_controller->ep0_state = WAIT_FOR_SETUP;
-	udc_controller->ep0_dir = 0;
-	return 0;
+#if defined(CONFIG_ARCH_TEGRA)
+    fsl_udc_restart(udc_controller);
+#else
+    /* Enable DR irq reg and set controller Run */
+    if (udc_controller->stopped) {
+        dr_controller_setup(udc_controller);
+        dr_controller_run(udc_controller);
+    }
+    udc_controller->usb_state = USB_STATE_ATTACHED;
+    udc_controller->ep0_state = WAIT_FOR_SETUP;
+    udc_controller->ep0_dir = 0;
+#endif
+    /* Power down the phy if cable is not connected */
+    if (!(fsl_readl(&usb_sys_regs->vbus_wakeup) & USB_SYS_VBUS_STATUS))
+        fsl_udc_clk_suspend();
+
+    return 0;
 }
 
 /*-------------------------------------------------------------------------
diff --git a/drivers/usb/gadget/fsl_usb2_udc.h b/drivers/usb/gadget/fsl_usb2_udc.h
index 8d5bd2fe7475..99c36054e66c 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.h
+++ b/drivers/usb/gadget/fsl_usb2_udc.h
@@ -442,7 +442,7 @@ struct ep_td_struct {
 #define USB_SYS_VBUS_WAKEUP_INT_ENABLE		0x100
 #define USB_SYS_VBUS_WAKEUP_INT_STATUS		0x200
 #define USB_SYS_VBUS_STATUS			0x400
-
+#define USB_SYS_ID_PIN_STATUS       (0x4)
 /*-------------------------------------------------------------------------*/
 
 /* ### driver private data
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index 3c72ed4c6cdc..5765496218a1 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -32,6 +32,10 @@
 #define TEGRA_USB_USBMODE_HOST			(3 << 0)
 #define TEGRA_USB_PORTSC1_PTC(x)		(((x) & 0xf) << 16)
 
+#define TEGRA_USB_DMA_ALIGN 32
+
+#define URB_ALIGNED_TEMP_BUFFER 0x80000000
+
 struct tegra_ehci_context {
 	bool valid;
 	u32 command;
@@ -394,6 +398,9 @@ static void tegra_ehci_shutdown(struct usb_hcd *hcd)
 
 	/* call ehci shut down */
 	ehci_shutdown(hcd);
+
+	/* we are ready to shut down, powerdown the phy */
+	tegra_ehci_power_down(hcd);
 }
 
 static int tegra_ehci_setup(struct usb_hcd *hcd)
@@ -468,6 +475,94 @@ static int tegra_ehci_bus_resume(struct usb_hcd *hcd)
 }
 #endif
 
+struct temp_buffer {
+        void *kmalloc_ptr;
+	void *old_xfer_buffer;
+	u8 data[0];
+};
+
+static void free_temp_buffer(struct urb *urb)
+{
+	enum dma_data_direction dir;
+	struct temp_buffer *temp;
+
+	if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
+		return;
+
+	dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+
+	temp = container_of(urb->transfer_buffer, struct temp_buffer,
+			    data);
+
+	if (dir == DMA_FROM_DEVICE)
+		memcpy(temp->old_xfer_buffer, temp->data,
+		       urb->transfer_buffer_length);
+	urb->transfer_buffer = temp->old_xfer_buffer;
+	kfree(temp->kmalloc_ptr);
+
+	urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
+}
+
+static int alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
+{
+	enum dma_data_direction dir;
+	struct temp_buffer *temp, *kmalloc_ptr;
+        size_t kmalloc_size;
+	void *data;
+
+	if (urb->num_sgs || urb->sg ||
+	    urb->transfer_buffer_length == 0 ||
+	    !((uintptr_t)urb->transfer_buffer & (TEGRA_USB_DMA_ALIGN - 1)))
+		return 0;
+
+	dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
+
+	/* Allocate a buffer with enough padding for alignment */
+	kmalloc_size = urb->transfer_buffer_length +
+		sizeof(struct temp_buffer) + TEGRA_USB_DMA_ALIGN - 1;
+
+	kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
+	if (!kmalloc_ptr)
+		return -ENOMEM;
+
+	/* Position our struct temp_buffer such that data is aligned */
+	temp = PTR_ALIGN(kmalloc_ptr + 1, TEGRA_USB_DMA_ALIGN) - 1;
+
+	temp->kmalloc_ptr = kmalloc_ptr;
+	temp->old_xfer_buffer = urb->transfer_buffer;
+	if (dir == DMA_TO_DEVICE)
+		memcpy(temp->data, urb->transfer_buffer,
+		       urb->transfer_buffer_length);
+	urb->transfer_buffer = temp->data;
+
+        BUILD_BUG_ON(!(URB_ALIGNED_TEMP_BUFFER & URB_DRIVER_PRIVATE));
+	urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
+
+	return 0;
+}
+
+static int tegra_ehci_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
+				      gfp_t mem_flags)
+{
+	int ret;
+
+	ret = alloc_temp_buffer(urb, mem_flags);
+	if (ret)
+		return ret;
+
+	ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
+	if (ret)
+		free_temp_buffer(urb);
+
+	return ret;
+}
+
+static void tegra_ehci_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
+{
+	usb_hcd_unmap_urb_for_dma(hcd, urb);
+	free_temp_buffer(urb);
+}
+
 static const struct hc_driver tegra_ehci_hc_driver = {
 	.description		= hcd_name,
 	.product_desc		= "Tegra EHCI Host Controller",
@@ -483,6 +578,8 @@ static const struct hc_driver tegra_ehci_hc_driver = {
 	.shutdown		= tegra_ehci_shutdown,
 	.urb_enqueue		= ehci_urb_enqueue,
 	.urb_dequeue		= ehci_urb_dequeue,
+	.map_urb_for_dma	= tegra_ehci_map_urb_for_dma,
+	.unmap_urb_for_dma	= tegra_ehci_unmap_urb_for_dma,
 	.endpoint_disable	= ehci_endpoint_disable,
 	.endpoint_reset		= ehci_endpoint_reset,
 	.get_frame_number	= ehci_get_frame,
@@ -679,9 +776,12 @@ static int tegra_ehci_remove(struct platform_device *pdev)
 	}
 #endif
 
+	/* Turn Off Interrupts */
+	ehci_writel(tegra->ehci, 0, &tegra->ehci->regs->intr_enable);
+	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 	usb_remove_hcd(hcd);
 	usb_put_hcd(hcd);
-
+	tegra_usb_phy_power_off(tegra->phy);
 	tegra_usb_phy_close(tegra->phy);
 	iounmap(hcd->regs);
 
diff --git a/drivers/usb/otg/tegra-otg.c b/drivers/usb/otg/tegra-otg.c
index 542a184824a3..413a79191578 100644
--- a/drivers/usb/otg/tegra-otg.c
+++ b/drivers/usb/otg/tegra-otg.c
@@ -52,6 +52,7 @@ struct tegra_otg_data {
 	int irq;
 	struct platform_device *host;
 	struct platform_device *pdev;
+	struct work_struct work;
 };
 
 static inline unsigned long otg_readl(struct tegra_otg_data *tegra,
@@ -79,58 +80,25 @@ static const char *tegra_state_name(enum usb_otg_state state)
 
 void tegra_start_host(struct tegra_otg_data *tegra)
 {
-	int retval;
-	struct platform_device *pdev;
-	struct platform_device *host = tegra->host;
-	void *platform_data;
-
-	pdev = platform_device_alloc(host->name, host->id);
-	if (!pdev)
-		return;
-
-	if (host->resource) {
-		retval = platform_device_add_resources(pdev, host->resource,
-							host->num_resources);
-		if (retval)
-			goto error;
+	struct tegra_otg_platform_data *pdata = tegra->otg.dev->platform_data;
+	if (!tegra->pdev) {
+		tegra->pdev = pdata->host_register();
 	}
-
-	pdev->dev.dma_mask = host->dev.dma_mask;
-	pdev->dev.coherent_dma_mask = host->dev.coherent_dma_mask;
-
-	platform_data = kmalloc(sizeof(struct tegra_ehci_platform_data), GFP_KERNEL);
-	if (!platform_data)
-		goto error;
-
-	memcpy(platform_data, host->dev.platform_data,
-				sizeof(struct tegra_ehci_platform_data));
-	pdev->dev.platform_data = platform_data;
-
-	retval = platform_device_add(pdev);
-	if (retval)
-		goto error_add;
-
-	tegra->pdev = pdev;
-	return;
-
-error_add:
-	kfree(platform_data);
-error:
-	pr_err("%s: failed to add the host contoller device\n", __func__);
-	platform_device_put(pdev);
 }
 
 void tegra_stop_host(struct tegra_otg_data *tegra)
 {
+	struct tegra_otg_platform_data *pdata = tegra->otg.dev->platform_data;
 	if (tegra->pdev) {
-		platform_device_unregister(tegra->pdev);
+		pdata->host_unregister(tegra->pdev);
 		tegra->pdev = NULL;
 	}
 }
 
-static irqreturn_t tegra_otg_irq_thread(int irq, void *data)
+static void irq_work(struct work_struct *work)
 {
-	struct tegra_otg_data *tegra = data;
+	struct tegra_otg_data *tegra =
+		container_of(work, struct tegra_otg_data, work);
 	struct otg_transceiver *otg = &tegra->otg;
 	enum usb_otg_state from = otg->state;
 	enum usb_otg_state to = OTG_STATE_UNDEFINED;
@@ -139,71 +107,72 @@ static irqreturn_t tegra_otg_irq_thread(int irq, void *data)
 
 	clk_enable(tegra->clk);
 
-	status = otg_readl(tegra, USB_PHY_WAKEUP);
-
 	spin_lock_irqsave(&tegra->lock, flags);
 
+	status = tegra->int_status;
+
 	if (tegra->int_status & USB_ID_INT_STATUS) {
-		if (status & USB_ID_STATUS)
-			to = OTG_STATE_A_SUSPEND;
+		if (status & USB_ID_STATUS) {
+			if ((status & USB_VBUS_STATUS) && (from != OTG_STATE_A_HOST))
+				to = OTG_STATE_B_PERIPHERAL;
+			else
+				to = OTG_STATE_A_SUSPEND;
+		}
 		else
 			to = OTG_STATE_A_HOST;
-	} else if (tegra->int_status & USB_VBUS_INT_STATUS) {
-		if (status & USB_VBUS_STATUS)
-			to = OTG_STATE_B_PERIPHERAL;
-		else
-			to = OTG_STATE_A_SUSPEND;
 	}
-
-	tegra->int_status = 0;
-
+	if (from != OTG_STATE_A_HOST) {
+		if (tegra->int_status & USB_VBUS_INT_STATUS) {
+			if (status & USB_VBUS_STATUS)
+				to = OTG_STATE_B_PERIPHERAL;
+			else
+				to = OTG_STATE_A_SUSPEND;
+		}
+	}
 	spin_unlock_irqrestore(&tegra->lock, flags);
 
-	otg->state = to;
+	if (to != OTG_STATE_UNDEFINED) {
+		otg->state = to;
 
-	dev_info(tegra->otg.dev, "%s --> %s", tegra_state_name(from),
+		dev_info(tegra->otg.dev, "%s --> %s\n", tegra_state_name(from),
 					      tegra_state_name(to));
 
-	if (to == OTG_STATE_A_SUSPEND) {
-		if (from == OTG_STATE_A_HOST && tegra->host)
-			tegra_stop_host(tegra);
-		else if (from == OTG_STATE_B_PERIPHERAL && otg->gadget)
-			usb_gadget_vbus_disconnect(otg->gadget);
-	} else if (to == OTG_STATE_B_PERIPHERAL && otg->gadget) {
-		if (from == OTG_STATE_A_SUSPEND)
-			usb_gadget_vbus_connect(otg->gadget);
-	} else if (to == OTG_STATE_A_HOST && tegra->host) {
-		if (from == OTG_STATE_A_SUSPEND)
+		if (to == OTG_STATE_A_SUSPEND) {
+			if (from == OTG_STATE_A_HOST)
+				tegra_stop_host(tegra);
+			else if (from == OTG_STATE_B_PERIPHERAL && otg->gadget)
+				usb_gadget_vbus_disconnect(otg->gadget);
+		} else if (to == OTG_STATE_B_PERIPHERAL && otg->gadget) {
+			if (from == OTG_STATE_A_SUSPEND)
+				usb_gadget_vbus_connect(otg->gadget);
+		} else if (to == OTG_STATE_A_HOST) {
+			if (from == OTG_STATE_A_SUSPEND)
 			tegra_start_host(tegra);
+		}
 	}
-
 	clk_disable(tegra->clk);
 
-	return IRQ_HANDLED;
-
 }
 
 static irqreturn_t tegra_otg_irq(int irq, void *data)
 {
 	struct tegra_otg_data *tegra = data;
+	unsigned long flags;
 	unsigned long val;
 
-	clk_enable(tegra->clk);
+	spin_lock_irqsave(&tegra->lock, flags);
 
-	spin_lock(&tegra->lock);
 	val = otg_readl(tegra, USB_PHY_WAKEUP);
 	otg_writel(tegra, val, USB_PHY_WAKEUP);
 
-	/* and the interrupt enables into the interrupt status bits */
-	val = (val & (val << 1)) & USB_INTS;
-
-	tegra->int_status |= val;
-
-	spin_unlock(&tegra->lock);
+	if ((val & USB_ID_INT_STATUS) || (val & USB_VBUS_INT_STATUS)) {
+		tegra->int_status = val;
+		schedule_work(&tegra->work);
+	}
 
-	clk_disable(tegra->clk);
+	spin_unlock_irqrestore(&tegra->lock, flags);
 
-	return (val) ? IRQ_WAKE_THREAD : IRQ_NONE;
+	return IRQ_HANDLED;
 }
 
 static int tegra_otg_set_peripheral(struct otg_transceiver *otg,
@@ -217,16 +186,24 @@ static int tegra_otg_set_peripheral(struct otg_transceiver *otg,
 
 	clk_enable(tegra->clk);
 	val = otg_readl(tegra, USB_PHY_WAKEUP);
-	val &= ~(USB_VBUS_INT_STATUS | USB_ID_INT_STATUS);
-
-	if (gadget)
-		val |= (USB_VBUS_INT_EN | USB_VBUS_WAKEUP_EN);
-	else
-		val &= ~(USB_VBUS_INT_EN | USB_VBUS_WAKEUP_EN);
-
+	val |= (USB_VBUS_INT_EN | USB_VBUS_WAKEUP_EN);
+	val |= (USB_ID_INT_EN | USB_ID_PIN_WAKEUP_EN);
 	otg_writel(tegra, val, USB_PHY_WAKEUP);
 	clk_disable(tegra->clk);
 
+	if ((val & USB_ID_STATUS) && (val & USB_VBUS_STATUS)) {
+		val |= USB_VBUS_INT_STATUS;
+	} else if (!(val & USB_ID_STATUS)) {
+		val |= USB_ID_INT_STATUS;
+	} else {
+		val &= ~(USB_ID_INT_STATUS | USB_VBUS_INT_STATUS);
+	}
+
+	if ((val & USB_ID_INT_STATUS) || (val & USB_VBUS_INT_STATUS)) {
+		tegra->int_status = val;
+		schedule_work (&tegra->work);
+	}
+
 	return 0;
 }
 
@@ -243,10 +220,7 @@ static int tegra_otg_set_host(struct otg_transceiver *otg,
 	val = otg_readl(tegra, USB_PHY_WAKEUP);
 	val &= ~(USB_VBUS_INT_STATUS | USB_ID_INT_STATUS);
 
-	if (host)
-		val |= USB_ID_INT_EN | USB_ID_PIN_WAKEUP_EN;
-	else
-		val &= ~(USB_ID_INT_EN | USB_ID_PIN_WAKEUP_EN);
+	val |= (USB_ID_INT_EN | USB_ID_PIN_WAKEUP_EN);
 	otg_writel(tegra, val, USB_PHY_WAKEUP);
 	clk_disable(tegra->clk);
 
@@ -267,7 +241,6 @@ static int tegra_otg_probe(struct platform_device *pdev)
 {
 	struct tegra_otg_data *tegra;
 	struct resource *res;
-	unsigned long val;
 	int err;
 
 	tegra = kzalloc(sizeof(struct tegra_otg_data), GFP_KERNEL);
@@ -281,7 +254,6 @@ static int tegra_otg_probe(struct platform_device *pdev)
 	tegra->otg.set_peripheral = tegra_otg_set_peripheral;
 	tegra->otg.set_suspend = tegra_otg_set_suspend;
 	tegra->otg.set_power = tegra_otg_set_power;
-	tegra->host = pdev->dev.platform_data;
 	spin_lock_init(&tegra->lock);
 
 	platform_set_drvdata(pdev, tegra);
@@ -309,14 +281,6 @@ static int tegra_otg_probe(struct platform_device *pdev)
 		goto err_io;
 	}
 
-	val = otg_readl(tegra, USB_PHY_WAKEUP);
-
-	val &= ~(USB_VBUS_INT_STATUS | USB_VBUS_INT_EN |
-		 USB_ID_INT_STATUS | USB_ID_INT_EN |
-		 USB_VBUS_WAKEUP_EN | USB_ID_PIN_WAKEUP_EN);
-
-	otg_writel(tegra, val, USB_PHY_WAKEUP);
-
 	tegra->otg.state = OTG_STATE_A_SUSPEND;
 
 	err = otg_set_transceiver(&tegra->otg);
@@ -333,12 +297,13 @@ static int tegra_otg_probe(struct platform_device *pdev)
 	}
 	tegra->irq = res->start;
 	err = request_threaded_irq(tegra->irq, tegra_otg_irq,
-				   tegra_otg_irq_thread,
+				   NULL,
 				   IRQF_SHARED, "tegra-otg", tegra);
 	if (err) {
 		dev_err(&pdev->dev, "Failed to register IRQ\n");
 		goto err_irq;
 	}
+	INIT_WORK (&tegra->work, irq_work);
 
 	dev_info(&pdev->dev, "otg transceiver registered\n");
 	return 0;
diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c
index 209e6be1163e..930070e3ccf4 100644
--- a/drivers/video/modedb.c
+++ b/drivers/video/modedb.c
@@ -1163,7 +1163,7 @@ void fb_var_to_videomode(struct fb_videomode *mode,
 	mode->upper_margin = var->upper_margin;
 	mode->lower_margin = var->lower_margin;
 	mode->sync = var->sync;
-	mode->vmode = var->vmode & FB_VMODE_MASK;
+	mode->vmode = var->vmode & (FB_VMODE_MASK | FB_VMODE_STEREO_MASK);
 	mode->flag = FB_MODE_IS_FROM_VAR;
 	mode->refresh = 0;
 
@@ -1208,7 +1208,7 @@ void fb_videomode_to_var(struct fb_var_screeninfo *var,
 	var->hsync_len = mode->hsync_len;
 	var->vsync_len = mode->vsync_len;
 	var->sync = mode->sync;
-	var->vmode = mode->vmode & FB_VMODE_MASK;
+	var->vmode = mode->vmode & (FB_VMODE_MASK | FB_VMODE_STEREO_MASK);
 }
 
 /**
diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig
index c431cc670a46..c9e5f21a69c2 100644
--- a/drivers/video/tegra/Kconfig
+++ b/drivers/video/tegra/Kconfig
@@ -17,6 +17,13 @@ config TEGRA_DC
 	help
 	  Tegra display controller support.
 
+config TEGRA_OVERLAY
+	tristate "Tegra Overlay Device Node"
+	depends on TEGRA_DC
+	default y
+	help
+	  Device node for multi-client overlay support.
+
 config FB_TEGRA
 	tristate "Tegra Framebuffer driver"
 	depends on TEGRA_DC && FB = y
@@ -70,5 +77,16 @@ config NVMAP_CARVEOUT_KILLER
 	  processes. This will kill the largest consumers of lowest priority
 	  first.
 
+config NVMAP_SEARCH_GLOBAL_HANDLES
+	bool "Check global handle list when generating memory IDs"
+	depends on TEGRA_NVMAP
+	default n
+	help
+	  Say Y here to allow the system to search through memory handles not
+	  owned by the caller when generating a memory ID.  This shouldn't be
+	  necessary for well-written applications, but is provided for
+	  compatibility with legacy applications.
+	  If unsure, say N.
+
 endif
 
diff --git a/drivers/video/tegra/dc/Makefile b/drivers/video/tegra/dc/Makefile
index eb39d5d28e92..7336f46111e0 100644
--- a/drivers/video/tegra/dc/Makefile
+++ b/drivers/video/tegra/dc/Makefile
@@ -1,4 +1,6 @@
 obj-y += dc.o
 obj-y += rgb.o
 obj-y += hdmi.o
-obj-y += edid.o
\ No newline at end of file
+obj-y += edid.o
+obj-y += nvhdcp.o
+obj-$(CONFIG_TEGRA_OVERLAY) += overlay.o
diff --git a/drivers/video/tegra/dc/dc.c b/drivers/video/tegra/dc/dc.c
index 1768efbc6e13..83070a76834e 100644
--- a/drivers/video/tegra/dc/dc.c
+++ b/drivers/video/tegra/dc/dc.c
@@ -39,6 +39,7 @@
 
 #include "dc_reg.h"
 #include "dc_priv.h"
+#include "overlay.h"
 
 static int no_vsync;
 
@@ -567,6 +568,17 @@ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
 					DC_WIN_LINE_STRIDE);
 		}
 
+		if (win->flags & TEGRA_WIN_FLAG_TILED)
+			tegra_dc_writel(dc,
+					DC_WIN_BUFFER_ADDR_MODE_TILE |
+					DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
+					DC_WIN_BUFFER_ADDR_MODE);
+		else
+			tegra_dc_writel(dc,
+					DC_WIN_BUFFER_ADDR_MODE_LINEAR |
+					DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
+					DC_WIN_BUFFER_ADDR_MODE);
+
 		tegra_dc_writel(dc, win->x * tegra_dc_fmt_bpp(win->fmt) / 8,
 				DC_WINBUF_ADDR_H_OFFSET);
 		tegra_dc_writel(dc, win->y, DC_WINBUF_ADDR_V_OFFSET);
@@ -711,7 +723,6 @@ void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
 
 	pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
 	tegra_dvfs_set_rate(clk, pclk);
-
 }
 
 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
@@ -796,6 +807,72 @@ int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
 }
 EXPORT_SYMBOL(tegra_dc_set_mode);
 
+static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
+				const struct tegra_dc_out_pin *pins,
+				const unsigned int n_pins)
+{
+	unsigned int i;
+
+	int name;
+	int pol;
+
+	u32 pol1, pol3;
+
+	u32 set1, unset1;
+	u32 set3, unset3;
+
+	set1 = set3 = unset1 = unset3 = 0;
+
+	for (i = 0; i < n_pins; i++) {
+		name = (pins + i)->name;
+		pol  = (pins + i)->pol;
+
+		/* set polarity by name */
+		switch (name) {
+		case TEGRA_DC_OUT_PIN_DATA_ENABLE:
+			if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
+				set3 |= LSPI_OUTPUT_POLARITY_LOW;
+			else
+				unset3 |= LSPI_OUTPUT_POLARITY_LOW;
+			break;
+		case TEGRA_DC_OUT_PIN_H_SYNC:
+			if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
+				set1 |= LHS_OUTPUT_POLARITY_LOW;
+			else
+				unset1 |= LHS_OUTPUT_POLARITY_LOW;
+			break;
+		case TEGRA_DC_OUT_PIN_V_SYNC:
+			if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
+				set1 |= LVS_OUTPUT_POLARITY_LOW;
+			else
+				unset1 |= LVS_OUTPUT_POLARITY_LOW;
+			break;
+		case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
+			if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
+				set1 |= LSC0_OUTPUT_POLARITY_LOW;
+			else
+				unset1 |= LSC0_OUTPUT_POLARITY_LOW;
+			break;
+		default:
+			printk("Invalid argument in function %s\n",
+			       __FUNCTION__);
+			break;
+		}
+	}
+
+	pol1 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
+	pol3 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY3);
+
+	pol1 |= set1;
+	pol1 &= ~unset1;
+
+	pol3 |= set3;
+	pol3 &= ~unset3;
+
+	tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
+	tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
+}
+
 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
 {
 	dc->out = out;
@@ -959,6 +1036,18 @@ static void tegra_dc_set_color_control(struct tegra_dc *dc)
 		break;
 	}
 
+	switch (dc->out->dither) {
+	case TEGRA_DC_DISABLE_DITHER:
+		color_control |= DITHER_CONTROL_DISABLE;
+		break;
+	case TEGRA_DC_ORDERED_DITHER:
+		color_control |= DITHER_CONTROL_ORDERED;
+		break;
+	case TEGRA_DC_ERRDIFF_DITHER:
+		color_control |= DITHER_CONTROL_ERRDIFF;
+		break;
+	}
+
 	tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
 }
 
@@ -1035,14 +1124,17 @@ static void tegra_dc_init(struct tegra_dc *dc)
 
 static bool _tegra_dc_enable(struct tegra_dc *dc)
 {
+	if (!dc->out)
+		return false;
+
+	if (dc->out->enable)
+		dc->out->enable();
+
 	if (dc->mode.pclk == 0)
 		return false;
 
 	tegra_dc_io_start(dc);
 
-	if (dc->out && dc->out->enable)
-		dc->out->enable();
-
 	tegra_dc_setup_clk(dc, dc->clk);
 
 	clk_enable(dc->clk);
@@ -1054,6 +1146,13 @@ static bool _tegra_dc_enable(struct tegra_dc *dc)
 	if (dc->out_ops && dc->out_ops->enable)
 		dc->out_ops->enable(dc);
 
+	if (dc->out->out_pins)
+		tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
+					    dc->out->n_out_pins);
+
+	if (dc->out->postpoweron)
+		dc->out->postpoweron();
+
 	/* force a full blending update */
 	dc->blend.z[0] = -1;
 
@@ -1246,8 +1345,10 @@ static int tegra_dc_probe(struct nvhost_device *ndev)
 	else
 		dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
 
+	mutex_lock(&dc->lock);
 	if (dc->enabled)
 		_tegra_dc_enable(dc);
+	mutex_unlock(&dc->lock);
 
 	tegra_dc_dbg_add(dc);
 
@@ -1270,6 +1371,12 @@ static int tegra_dc_probe(struct nvhost_device *ndev)
 			dc->fb = NULL;
 	}
 
+	if (dc->fb) {
+		dc->overlay = tegra_overlay_register(ndev, dc);
+		if (IS_ERR_OR_NULL(dc->overlay))
+			dc->overlay = NULL;
+	}
+
 	if (dc->out_ops && dc->out_ops->detect)
 		dc->out_ops->detect(dc);
 
@@ -1297,6 +1404,10 @@ static int tegra_dc_remove(struct nvhost_device *ndev)
 {
 	struct tegra_dc *dc = nvhost_get_drvdata(ndev);
 
+	if (dc->overlay) {
+		tegra_overlay_unregister(dc->overlay);
+	}
+
 	if (dc->fb) {
 		tegra_fb_unregister(dc->fb);
 		if (dc->fb_mem)
diff --git a/drivers/video/tegra/dc/dc_priv.h b/drivers/video/tegra/dc/dc_priv.h
index 3f7fdbff023b..ddd7d341e429 100644
--- a/drivers/video/tegra/dc/dc_priv.h
+++ b/drivers/video/tegra/dc/dc_priv.h
@@ -81,6 +81,8 @@ struct tegra_dc {
 	struct resource			*fb_mem;
 	struct tegra_fb_info		*fb;
 
+	struct tegra_overlay_info	*overlay;
+
 	u32				syncpt_id;
 	u32				syncpt_min;
 	u32				syncpt_max;
diff --git a/drivers/video/tegra/dc/dc_reg.h b/drivers/video/tegra/dc/dc_reg.h
index ab21c6eba0e1..240d8a48d03e 100644
--- a/drivers/video/tegra/dc/dc_reg.h
+++ b/drivers/video/tegra/dc/dc_reg.h
@@ -108,9 +108,17 @@
 #define DC_COM_PIN_OUTPUT_ENABLE2		0x304
 #define DC_COM_PIN_OUTPUT_ENABLE3		0x305
 #define DC_COM_PIN_OUTPUT_POLARITY0		0x306
+
 #define DC_COM_PIN_OUTPUT_POLARITY1		0x307
+#define  LHS_OUTPUT_POLARITY_LOW	(1 << 30)
+#define  LVS_OUTPUT_POLARITY_LOW	(1 << 28)
+#define  LSC0_OUTPUT_POLARITY_LOW	(1 << 24)
+
 #define DC_COM_PIN_OUTPUT_POLARITY2		0x308
+
 #define DC_COM_PIN_OUTPUT_POLARITY3		0x309
+#define  LSPI_OUTPUT_POLARITY_LOW	(1 << 8)
+
 #define DC_COM_PIN_OUTPUT_DATA0			0x30a
 #define DC_COM_PIN_OUTPUT_DATA1			0x30b
 #define DC_COM_PIN_OUTPUT_DATA2			0x30c
@@ -382,6 +390,10 @@
 #define DC_WIN_BUF_STRIDE			0x70b
 #define DC_WIN_UV_BUF_STRIDE			0x70c
 #define DC_WIN_BUFFER_ADDR_MODE			0x70d
+#define  DC_WIN_BUFFER_ADDR_MODE_LINEAR		(0 << 0)
+#define  DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV	(0 << 16)
+#define  DC_WIN_BUFFER_ADDR_MODE_TILE		(1 << 0)
+#define  DC_WIN_BUFFER_ADDR_MODE_TILE_UV	(1 << 16)
 #define DC_WIN_DV_CONTROL			0x70e
 #define DC_WIN_BLEND_NOKEY			0x70f
 #define DC_WIN_BLEND_1WIN			0x710
diff --git a/drivers/video/tegra/dc/edid.c b/drivers/video/tegra/dc/edid.c
index 812a0087a96d..0833ea6e4575 100644
--- a/drivers/video/tegra/dc/edid.c
+++ b/drivers/video/tegra/dc/edid.c
@@ -32,6 +32,7 @@ struct tegra_edid {
 
 	u8			*data;
 	unsigned		len;
+	u8			support_stereo;
 };
 
 #if defined(DEBUG) || defined(CONFIG_DEBUG_FS)
@@ -116,7 +117,7 @@ static void tegra_edid_dump(struct tegra_edid *edid)
 }
 #endif
 
-int tegra_edid_read_block(struct tegra_edid *edid, int block, u8 *data)
+static int tegra_edid_read_block(struct tegra_edid *edid, int block, u8 *data)
 {
 	u8 block_buf[] = {block >> 1};
 	u8 cmd_buf[] = {(block & 0x1) * 128};
@@ -162,14 +163,90 @@ int tegra_edid_read_block(struct tegra_edid *edid, int block, u8 *data)
 	return 0;
 }
 
+int tegra_edid_parse_ext_block(u8 *raw, int idx, struct tegra_edid *edid)
+{
+	u8 *ptr;
+	u8 tmp;
+	u8 code;
+	int len;
+
+	ptr = &raw[4];
+
+	while (ptr < &raw[idx]) {
+		tmp = *ptr;
+		len = tmp & 0x1f;
+
+		/* HDMI Specification v1.4a, section 8.3.2:
+		 * see Table 8-16 for HDMI VSDB format.
+		 * data blocks have tags in top 3 bits:
+		 * tag code 2: video data block
+		 * tag code 3: vendor specific data block
+		 */
+		code = (tmp >> 5) & 0x3;
+		switch (code) {
+		/* case 2 is commented out for now */
+		case 3:
+		{
+			int j = 0;
+
+			if ((len >= 8) &&
+				(ptr[1] == 0x03) &&
+				(ptr[2] == 0x0c) &&
+				(ptr[3] == 0)) {
+				j = 8;
+				tmp = ptr[j++];
+				/* HDMI_Video_present? */
+				if (tmp & 0x20) {
+					/* Latency_Fields_present? */
+					if (tmp & 0x80)
+						j += 2;
+					/* I_Latency_Fields_present? */
+					if (tmp & 0x40)
+						j += 2;
+					/* 3D_present? */
+					if (j <= len && (ptr[j] & 0x80))
+						edid->support_stereo = 1;
+				}
+			}
+
+			len++;
+			ptr += len; /* adding the header */
+			break;
+		}
+		default:
+			len++; /* len does not include header */
+			ptr += len;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+int tegra_edid_mode_support_stereo(struct fb_videomode *mode)
+{
+	if (!mode)
+		return 0;
+
+	if (mode->xres == 1280 && mode->yres == 720 && mode->refresh == 60)
+		return 1;
+
+	if (mode->xres == 1280 && mode->yres == 720 && mode->refresh == 50)
+		return 1;
+
+	return 0;
+}
 
 int tegra_edid_get_monspecs(struct tegra_edid *edid, struct fb_monspecs *specs)
 {
 	int i;
+	int j;
 	int ret;
 	int extension_blocks;
 
 	ret = tegra_edid_read_block(edid, 0, edid->data);
+	if (ret)
+		return ret;
 
 	memset(specs, 0x0, sizeof(struct fb_monspecs));
 	fb_edid_to_monspecs(edid->data, specs);
@@ -183,8 +260,21 @@ int tegra_edid_get_monspecs(struct tegra_edid *edid, struct fb_monspecs *specs)
 		if (ret < 0)
 			break;
 
-		if (edid->data[i * 128] == 0x2)
+		if (edid->data[i * 128] == 0x2) {
 			fb_edid_add_monspecs(edid->data + i * 128, specs);
+
+			tegra_edid_parse_ext_block(edid->data + i * 128,
+					edid->data[i * 128 + 2], edid);
+
+			if (edid->support_stereo) {
+				for (j = 0; j < specs->modedb_len; j++) {
+					if (tegra_edid_mode_support_stereo(
+						&specs->modedb[j]))
+						specs->modedb[j].vmode |=
+						FB_VMODE_STEREO_FRAME_PACK;
+				}
+			}
+		}
 	}
 
 	edid->len = i * 128;
diff --git a/drivers/video/tegra/dc/hdmi.c b/drivers/video/tegra/dc/hdmi.c
index dd2a51195880..24e4fed37b40 100644
--- a/drivers/video/tegra/dc/hdmi.c
+++ b/drivers/video/tegra/dc/hdmi.c
@@ -32,11 +32,14 @@
 #include <mach/fb.h>
 #include <mach/nvhost.h>
 
+#include <video/tegrafb.h>
+
 #include "dc_reg.h"
 #include "dc_priv.h"
 #include "hdmi_reg.h"
 #include "hdmi.h"
 #include "edid.h"
+#include "nvhdcp.h"
 
 /* datasheet claims this will always be 216MHz */
 #define HDMI_AUDIOCLK_FREQ		216000000
@@ -46,6 +49,7 @@
 struct tegra_dc_hdmi_data {
 	struct tegra_dc			*dc;
 	struct tegra_edid		*edid;
+	struct tegra_nvhdcp		*nvhdcp;
 	struct delayed_work		work;
 
 	struct resource			*base_res;
@@ -62,7 +66,7 @@ struct tegra_dc_hdmi_data {
 	bool				hpd_pending;
 };
 
-const struct fb_videomode tegra_dc_hdmi_supported_modes[] = {
+static const struct fb_videomode tegra_dc_hdmi_supported_modes[] = {
 	/* 1280x720p 60hz: EIA/CEA-861-B Format 4 */
 	{
 		.xres =		1280,
@@ -78,6 +82,22 @@ const struct fb_videomode tegra_dc_hdmi_supported_modes[] = {
 		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 	},
 
+	/* 1280x720p 60hz: EIA/CEA-861-B Format 4 (Stereo)*/
+	{
+		.xres =		1280,
+		.yres =		720,
+		.pixclock =	KHZ2PICOS(74250),
+		.hsync_len =	40,	/* h_sync_width */
+		.vsync_len =	5,	/* v_sync_width */
+		.left_margin =	220,	/* h_back_porch */
+		.upper_margin =	20,	/* v_back_porch */
+		.right_margin =	110,	/* h_front_porch */
+		.lower_margin =	5,	/* v_front_porch */
+		.vmode = FB_VMODE_NONINTERLACED |
+				 FB_VMODE_STEREO_FRAME_PACK,
+		.sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+	},
+
 	/* 720x480p 59.94hz: EIA/CEA-861-B Formats 2 & 3 */
 	{
 		.xres =		720,
@@ -204,13 +224,13 @@ static const struct tegra_hdmi_audio_config
 }
 
 
-static inline unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
+static inline unsigned long _tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
 					     unsigned long reg)
 {
 	return readl(hdmi->base + reg * 4);
 }
 
-static inline void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
+static inline void _tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
 				     unsigned long val, unsigned long reg)
 {
 	writel(val, hdmi->base + reg * 4);
@@ -220,15 +240,15 @@ static inline void tegra_hdmi_clrsetbits(struct tegra_dc_hdmi_data *hdmi,
 					 unsigned long reg, unsigned long clr,
 					 unsigned long set)
 {
-	unsigned long val = tegra_hdmi_readl(hdmi, reg);
+	unsigned long val = _tegra_hdmi_readl(hdmi, reg);
 	val &= ~clr;
 	val |= set;
-	tegra_hdmi_writel(hdmi, val, reg);
+	_tegra_hdmi_writel(hdmi, val, reg);
 }
 
 #define DUMP_REG(a) do {						\
 		printk("HDMI %-32s\t%03x\t%08lx\n",			\
-		       #a, a, tegra_hdmi_readl(hdmi, a));		\
+		       #a, a, _tegra_hdmi_readl(hdmi, a));		\
 	} while (0)
 
 #ifdef DEBUG
@@ -457,12 +477,14 @@ static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
 	dc->out->v_size = specs.max_y * 1000;
 
 	tegra_fb_update_monspecs(dc->fb, &specs, tegra_dc_hdmi_mode_filter);
+	hdmi->hpd_switch.state = 0;
 	switch_set_state(&hdmi->hpd_switch, 1);
 	dev_info(&dc->ndev->dev, "display detected\n");
 	return true;
 
 fail:
 	switch_set_state(&hdmi->hpd_switch, 0);
+	tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
 	return false;
 }
 
@@ -473,6 +495,8 @@ static void tegra_dc_hdmi_detect_worker(struct work_struct *work)
 		container_of(to_delayed_work(work), struct tegra_dc_hdmi_data, work);
 	struct tegra_dc *dc = hdmi->dc;
 
+	tegra_dc_enable(dc);
+	msleep(5);
 	if (!tegra_dc_hdmi_detect(dc)) {
 		tegra_dc_disable(dc);
 		tegra_fb_update_monspecs(dc->fb, NULL, NULL);
@@ -489,7 +513,8 @@ static irqreturn_t tegra_dc_hdmi_irq(int irq, void *ptr)
 	if (hdmi->suspended) {
 		hdmi->hpd_pending = true;
 	} else {
-		if (tegra_dc_hdmi_hpd(dc))
+		bool v = tegra_dc_hdmi_hpd(dc);
+		if (v)
 			schedule_delayed_work(&hdmi->work, msecs_to_jiffies(100));
 		else
 			schedule_delayed_work(&hdmi->work, msecs_to_jiffies(0));
@@ -504,6 +529,7 @@ static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
 	struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 	unsigned long flags;
 
+	tegra_nvhdcp_suspend(hdmi->nvhdcp);
 	spin_lock_irqsave(&hdmi->suspend_lock, flags);
 	hdmi->suspended = true;
 	spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
@@ -600,6 +626,14 @@ static int tegra_dc_hdmi_init(struct tegra_dc *dc)
 		goto err_free_irq;
 	}
 
+	hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
+			dc->out->dcc_bus);
+	if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
+		dev_err(&dc->ndev->dev, "hdmi: can't create nvhdcp\n");
+		err = PTR_ERR(hdmi->nvhdcp);
+		goto err_edid_destroy;
+	}
+
 	INIT_DELAYED_WORK(&hdmi->work, tegra_dc_hdmi_detect_worker);
 
 	hdmi->dc = dc;
@@ -619,8 +653,18 @@ static int tegra_dc_hdmi_init(struct tegra_dc *dc)
 
 	tegra_dc_set_outdata(dc, hdmi);
 
+	/* boards can select default content protection policy */
+	if (dc->out->flags & TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND) {
+		tegra_nvhdcp_set_policy(hdmi->nvhdcp,
+			TEGRA_NVHDCP_POLICY_ON_DEMAND);
+	} else {
+		tegra_nvhdcp_set_policy(hdmi->nvhdcp,
+			TEGRA_NVHDCP_POLICY_ALWAYS_ON);
+	}
 	return 0;
 
+err_edid_destroy:
+	tegra_edid_destroy(hdmi->edid);
 err_free_irq:
 	free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
 err_put_clock:
@@ -652,6 +696,7 @@ static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
 	clk_put(hdmi->disp1_clk);
 	clk_put(hdmi->disp2_clk);
 	tegra_edid_destroy(hdmi->edid);
+	tegra_nvhdcp_destroy(hdmi->nvhdcp);
 
 	kfree(hdmi);
 
@@ -684,7 +729,7 @@ static void tegra_dc_hdmi_setup_audio_fs_tables(struct tegra_dc *dc)
 			delta = 9;
 
 		eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
-		tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) |
+		_tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) |
 				  AUDIO_FS_HIGH(eight_half + delta),
 				  HDMI_NV_PDISP_AUDIO_FS(i));
 	}
@@ -697,7 +742,7 @@ static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc)
 	unsigned long audio_n;
 	unsigned audio_freq = 44100; /* TODO: find some way of configuring this */
 
-	tegra_hdmi_writel(hdmi,
+	_tegra_hdmi_writel(hdmi,
 			  AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
 			  AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
 			  AUDIO_CNTRL0_SOURCE_SELECT_AUTO,
@@ -711,24 +756,24 @@ static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc)
 		return -EINVAL;
 	}
 
-	tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
+	_tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
 
 	audio_n = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNALTE |
 		AUDIO_N_VALUE(config->n - 1);
-	tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
+	_tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
 
-	tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
+	_tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
 			  HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 
-	tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
+	_tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
 			  HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 
-	tegra_hdmi_writel(hdmi, SPARE_HW_CTS | SPARE_FORCE_SW_CTS |
+	_tegra_hdmi_writel(hdmi, SPARE_HW_CTS | SPARE_FORCE_SW_CTS |
 			  SPARE_CTS_RESET_VAL(1),
 			  HDMI_NV_PDISP_HDMI_SPARE);
 
 	audio_n &= ~AUDIO_N_RESETF;
-	tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
+	_tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
 
 	tegra_dc_hdmi_setup_audio_fs_tables(dc);
 
@@ -749,7 +794,7 @@ static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg,
 		csum +=((u8 *)data)[i];
 	((u8 *)data)[0] = 0x100 - csum;
 
-	tegra_hdmi_writel(hdmi, INFOFRAME_HEADER_TYPE(type) |
+	_tegra_hdmi_writel(hdmi, INFOFRAME_HEADER_TYPE(type) |
 			  INFOFRAME_HEADER_VERSION(version) |
 			  INFOFRAME_HEADER_LEN(len - 1),
 			  header_reg);
@@ -776,8 +821,8 @@ static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg,
 		if (subpack_idx == 6 || (i + 1 == len)) {
 			int reg = header_reg + 1 + (i / 7) * 2;
 
-			tegra_hdmi_writel(hdmi, subpack[0], reg);
-			tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
+			_tegra_hdmi_writel(hdmi, subpack[0], reg);
+			_tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
 		}
 	}
 }
@@ -788,7 +833,7 @@ static void tegra_dc_hdmi_setup_avi_infoframe(struct tegra_dc *dc, bool dvi)
 	struct hdmi_avi_infoframe avi;
 
 	if (dvi) {
-		tegra_hdmi_writel(hdmi, 0x0,
+		_tegra_hdmi_writel(hdmi, 0x0,
 				  HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 		return;
 	}
@@ -842,17 +887,49 @@ static void tegra_dc_hdmi_setup_avi_infoframe(struct tegra_dc *dc, bool dvi)
 				     HDMI_AVI_VERSION,
 				     &avi, sizeof(avi));
 
-	tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
+	_tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 			  HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 }
 
+static void tegra_dc_hdmi_setup_stereo_infoframe(struct tegra_dc *dc)
+{
+	struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
+	struct hdmi_stereo_infoframe stereo;
+	u32 val;
+
+	if (!dc->mode.stereo_mode) {
+		val  = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
+		val &= ~GENERIC_CTRL_ENABLE;
+		tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
+		return;
+	}
+
+	memset(&stereo, 0x0, sizeof(stereo));
+
+	stereo.regid0 = 0x03;
+	stereo.regid1 = 0x0c;
+	stereo.regid2 = 0x00;
+	stereo.hdmi_video_format = 2; /* 3D_Structure present */
+	stereo._3d_structure = 0; /* frame packing */
+
+	tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
+					HDMI_INFOFRAME_TYPE_VENDOR,
+					HDMI_VENDOR_VERSION,
+					&stereo, 6);
+
+	val  = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
+	val |= GENERIC_CTRL_ENABLE;
+
+	tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
+}
+
 static void tegra_dc_hdmi_setup_audio_infoframe(struct tegra_dc *dc, bool dvi)
 {
 	struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 	struct hdmi_audio_infoframe audio;
 
 	if (dvi) {
-		tegra_hdmi_writel(hdmi, 0x0,
+		_tegra_hdmi_writel(hdmi, 0x0,
 				  HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 		return;
 	}
@@ -865,7 +942,7 @@ static void tegra_dc_hdmi_setup_audio_infoframe(struct tegra_dc *dc, bool dvi)
 				     HDMI_AUDIO_VERSION,
 				     &audio, sizeof(audio));
 
-	tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
+	_tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 			  HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 }
 
@@ -922,13 +999,13 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 	tegra_dc_writel(dc, PULSE_START(pulse_start) | PULSE_END(pulse_start + 8),
 		  DC_DISP_H_PULSE2_POSITION_A);
 
-	tegra_hdmi_writel(hdmi,
+	_tegra_hdmi_writel(hdmi,
 			  VSYNC_WINDOW_END(0x210) |
 			  VSYNC_WINDOW_START(0x200) |
 			  VSYNC_WINDOW_ENABLE,
 			  HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 
-	tegra_hdmi_writel(hdmi,
+	_tegra_hdmi_writel(hdmi,
 			  (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
 			  ARM_VIDEO_RANGE_LIMITED,
 			  HDMI_NV_PDISP_INPUT_CONTROL);
@@ -937,7 +1014,7 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 	clk_disable(hdmi->disp2_clk);
 
 	dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4;
-	tegra_hdmi_writel(hdmi,
+	_tegra_hdmi_writel(hdmi,
 			  SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
 			  SOR_REFCLK_DIV_FRAC(dispclk_div_8_2),
 			  HDMI_NV_PDISP_SOR_REFCLK);
@@ -954,18 +1031,19 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 					rekey - 18) / 32);
 	if (!dvi)
 		val |= HDMI_CTRL_ENABLE;
-	tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_CTRL);
+	_tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_CTRL);
 
 	if (dvi)
-		tegra_hdmi_writel(hdmi, 0x0,
+		_tegra_hdmi_writel(hdmi, 0x0,
 				  HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 	else
-		tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
+		_tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
 				  HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 
 
 	tegra_dc_hdmi_setup_avi_infoframe(dc, dvi);
 	tegra_dc_hdmi_setup_audio_infoframe(dc, dvi);
+	tegra_dc_hdmi_setup_stereo_infoframe(dc);
 
 	/* TMDS CONFIG */
 	pll0 = 0x200033f;
@@ -990,11 +1068,11 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 		pll0 |= SOR_PLL_ICHPMP(2);
 	}
 
-	tegra_hdmi_writel(hdmi, pll0, HDMI_NV_PDISP_SOR_PLL0);
-	tegra_hdmi_writel(hdmi, pll1, HDMI_NV_PDISP_SOR_PLL1);
+	_tegra_hdmi_writel(hdmi, pll0, HDMI_NV_PDISP_SOR_PLL0);
+	_tegra_hdmi_writel(hdmi, pll1, HDMI_NV_PDISP_SOR_PLL1);
 
 	if (pll1 & SOR_PLL_PE_EN) {
-		tegra_hdmi_writel(hdmi,
+		_tegra_hdmi_writel(hdmi,
 				  PE_CURRENT0(0xf) |
 				  PE_CURRENT1(0xf) |
 				  PE_CURRENT2(0xf) |
@@ -1008,7 +1086,7 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 	else
 		ds = DRIVE_CURRENT_5_250_mA;
 
-	tegra_hdmi_writel(hdmi,
+	_tegra_hdmi_writel(hdmi,
 			  DRIVE_CURRENT_LANE0(ds) |
 			  DRIVE_CURRENT_LANE1(ds) |
 			  DRIVE_CURRENT_LANE2(ds) |
@@ -1016,7 +1094,7 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 			  DRIVE_CURRENT_FUSE_OVERRIDE,
 			  HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 
-	tegra_hdmi_writel(hdmi,
+	_tegra_hdmi_writel(hdmi,
 			  SOR_SEQ_CTL_PU_PC(0) |
 			  SOR_SEQ_PU_PC_ALT(0) |
 			  SOR_SEQ_PD_PC(8) |
@@ -1030,13 +1108,13 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 		SOR_SEQ_INST_PIN_B_LOW |
 		SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
 
-	tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST0);
-	tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST8);
+	_tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST0);
+	_tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST8);
 
 	val = 0x1c800;
 	val &= ~SOR_CSTM_ROTCLK(~0);
 	val |= SOR_CSTM_ROTCLK(2);
-	tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_CSTM);
+	_tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_CSTM);
 
 
 	tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
@@ -1045,13 +1123,13 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 
 
 	/* start SOR */
-	tegra_hdmi_writel(hdmi,
+	_tegra_hdmi_writel(hdmi,
 			  SOR_PWR_NORMAL_STATE_PU |
 			  SOR_PWR_NORMAL_START_NORMAL |
 			  SOR_PWR_SAFE_STATE_PD |
 			  SOR_PWR_SETTING_NEW_TRIGGER,
 			  HDMI_NV_PDISP_SOR_PWR);
-	tegra_hdmi_writel(hdmi,
+	_tegra_hdmi_writel(hdmi,
 			  SOR_PWR_NORMAL_STATE_PU |
 			  SOR_PWR_NORMAL_START_NORMAL |
 			  SOR_PWR_SAFE_STATE_PD |
@@ -1061,7 +1139,7 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 	retries = 1000;
 	do {
 		BUG_ON(--retries < 0);
-		val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
+		val = _tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
 	} while (val & SOR_PWR_SETTING_NEW_PENDING);
 
 	val = SOR_STATE_ASY_CRCMODE_COMPLETE |
@@ -1083,13 +1161,13 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 	tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE2);
 
 	val = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
-	tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE1);
+	_tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE1);
 
-	tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
-	tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
-	tegra_hdmi_writel(hdmi, val | SOR_STATE_ATTACHED,
+	_tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
+	_tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
+	_tegra_hdmi_writel(hdmi, val | SOR_STATE_ATTACHED,
 			  HDMI_NV_PDISP_SOR_STATE1);
-	tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
+	_tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
 
 	tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
 
@@ -1100,15 +1178,21 @@ static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 	tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
 	tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 	tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
+
+	tegra_nvhdcp_set_plug(hdmi->nvhdcp, 1);
+
 }
 
 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
 {
 	struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 
+	tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
+
 	tegra_periph_reset_assert(hdmi->clk);
 	clk_disable(hdmi->clk);
 }
+
 struct tegra_dc_out_ops tegra_dc_hdmi_ops = {
 	.init = tegra_dc_hdmi_init,
 	.destroy = tegra_dc_hdmi_destroy,
@@ -1119,3 +1203,14 @@ struct tegra_dc_out_ops tegra_dc_hdmi_ops = {
 	.resume = tegra_dc_hdmi_resume,
 };
 
+unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
+					     unsigned long reg)
+{
+	return _tegra_hdmi_readl(hdmi, reg);
+}
+
+void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
+				     unsigned long val, unsigned long reg)
+{
+	_tegra_hdmi_writel(hdmi, val, reg);
+}
diff --git a/drivers/video/tegra/dc/hdmi.h b/drivers/video/tegra/dc/hdmi.h
index 0189f08719fe..a280cbdcb720 100644
--- a/drivers/video/tegra/dc/hdmi.h
+++ b/drivers/video/tegra/dc/hdmi.h
@@ -180,4 +180,42 @@ struct hdmi_audio_infoframe {
 #define HDMI_AUDIO_CXT_HE_AAC_V2	0x2
 #define HDMI_AUDIO_CXT_MPEG_SURROUND	0x3
 
+/* all fields little endian */
+struct hdmi_stereo_infoframe {
+	/* PB0 */
+	u8		csum;
+
+	/* PB1 */
+	u8		regid0;
+
+	/* PB2 */
+	u8		regid1;
+
+	/* PB3 */
+	u8		regid2;
+
+	/* PB4 */
+	unsigned	res1:5;
+	unsigned	hdmi_video_format:3;
+
+	/* PB5 */
+	unsigned	res2:4;
+	unsigned	_3d_structure:4;
+
+	/* PB6*/
+	unsigned	res3:4;
+	unsigned	_3d_ext_data:4;
+
+} __attribute__((packed));
+
+#define HDMI_VENDOR_VERSION 0x01
+
+struct tegra_dc_hdmi_data;
+
+unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
+				unsigned long reg);
+void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
+				unsigned long val, unsigned long reg);
+int tegra_hdmi_i2c(struct tegra_dc_hdmi_data *hdmi,
+				struct i2c_msg *msg, int msg_len);
 #endif
diff --git a/drivers/video/tegra/dc/hdmi_reg.h b/drivers/video/tegra/dc/hdmi_reg.h
index 67d2b23a3d81..db9c1b76e09f 100644
--- a/drivers/video/tegra/dc/hdmi_reg.h
+++ b/drivers/video/tegra/dc/hdmi_reg.h
@@ -57,16 +57,29 @@
 #define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB				0x08
 #define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB				0x09
 #define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB				0x0a
+#define  REPEATER				(1 << 31)
 #define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB				0x0b
 #define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB				0x0c
 #define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB				0x0d
 #define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB				0x0e
 #define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB				0x0f
 #define HDMI_NV_PDISP_RG_HDCP_CTRL				0x10
+#define  HDCP_RUN_YES				(1 << 0)
+#define  CRYPT_ENABLED				(1 << 1)
+#define  ONEONE_ENABLED				(1 << 3)
+#define  AN_VALID				(1 << 8)
+#define  R0_VALID				(1 << 9)
+#define  SPRIME_VALID				(1 << 10)
+#define  MPRIME_VALID				(1 << 11)
+#define  SROM_ERR				(1 << 13)
 #define HDMI_NV_PDISP_RG_HDCP_CMODE				0x11
+#define  TMDS0_LINK0				(1 << 4)
+#define  READ_S					(1 << 0)
+#define  READ_M					(2 << 0)
 #define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB			0x12
 #define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB			0x13
 #define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB			0x14
+#define  STATUS_CS				(1 << 6)
 #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2			0x15
 #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1			0x16
 #define HDMI_NV_PDISP_RG_HDCP_RI				0x17
@@ -417,6 +430,11 @@
 #define  PE_CURRENT3(x)				(((x) & 0xf) << 24)
 
 #define HDMI_NV_PDISP_KEY_CTRL					0x9a
+#define  LOCAL_KEYS				(1 << 0)
+#define  AUTOINC				(1 << 1)
+#define  WRITE16				(1 << 4)
+#define  PKEY_REQUEST_RELOAD_TRIGGER		(1 << 5)
+#define  PKEY_LOADED				(1 << 6)
 #define HDMI_NV_PDISP_KEY_DEBUG0				0x9b
 #define HDMI_NV_PDISP_KEY_DEBUG1				0x9c
 #define HDMI_NV_PDISP_KEY_DEBUG2				0x9d
diff --git a/drivers/video/tegra/dc/nvhdcp.c b/drivers/video/tegra/dc/nvhdcp.c
new file mode 100644
index 000000000000..2bec36a53219
--- /dev/null
+++ b/drivers/video/tegra/dc/nvhdcp.c
@@ -0,0 +1,1188 @@
+/*
+ * drivers/video/tegra/dc/nvhdcp.c
+ *
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/miscdevice.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+#include <linux/uaccess.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#include <asm/atomic.h>
+
+#include <mach/dc.h>
+#include <mach/nvhost.h>
+#include <mach/kfuse.h>
+
+#include <video/nvhdcp.h>
+
+#include "dc_reg.h"
+#include "dc_priv.h"
+#include "hdmi_reg.h"
+#include "hdmi.h"
+
+/* for 0x40 Bcaps */
+#define BCAPS_REPEATER (1 << 6)
+#define BCAPS_READY (1 << 5)
+#define BCAPS_11 (1 << 1) /* used for both Bcaps and Ainfo */
+
+/* for 0x41 Bstatus */
+#define BSTATUS_MAX_DEVS_EXCEEDED	(1 << 7)
+#define BSTATUS_MAX_CASCADE_EXCEEDED	(1 << 11)
+
+#ifdef VERBOSE_DEBUG
+#define nvhdcp_vdbg(...)	\
+		printk("nvhdcp: " __VA_ARGS__)
+#else
+#define nvhdcp_vdbg(...)		\
+({						\
+	if(0)					\
+		printk("nvhdcp: " __VA_ARGS__); \
+	0;					\
+})
+#endif
+#define nvhdcp_debug(...)	\
+		pr_debug("nvhdcp: " __VA_ARGS__)
+#define nvhdcp_err(...)	\
+		pr_err("nvhdcp: Error: " __VA_ARGS__)
+#define nvhdcp_info(...)	\
+		pr_info("nvhdcp: " __VA_ARGS__)
+
+
+/* for nvhdcp.state */
+enum {
+	STATE_OFF,
+	STATE_UNAUTHENTICATED,
+	STATE_LINK_VERIFY,
+	STATE_RENEGOTIATE,
+};
+
+struct tegra_nvhdcp {
+	struct work_struct		work;
+	struct tegra_dc_hdmi_data	*hdmi;
+	struct workqueue_struct		*downstream_wq;
+	struct mutex			lock;
+	struct miscdevice		miscdev;
+	char				name[12];
+	unsigned			id;
+	atomic_t			plugged; /* true if hotplug detected */
+	atomic_t			policy; /* set policy */
+	atomic_t			state; /* STATE_xxx */
+	struct i2c_client		*client;
+	struct i2c_board_info		info;
+	int				bus;
+	u32				b_status;
+	u64				a_n;
+	u64				c_n;
+	u64				a_ksv;
+	u64				b_ksv;
+	u64				c_ksv;
+	u64				d_ksv;
+	u8				v_prime[20];
+	u64				m_prime;
+	u32				num_bksv_list;
+	u64				bksv_list[TEGRA_NVHDCP_MAX_DEVS];
+};
+
+#define TEGRA_NVHDCP_NUM_AP 1
+static struct tegra_nvhdcp *nvhdcp_dev[TEGRA_NVHDCP_NUM_AP];
+static int nvhdcp_ap;
+
+static int nvhdcp_i2c_read(struct tegra_nvhdcp *nvhdcp, u8 reg,
+					size_t len, void *data)
+{
+	int status;
+	struct i2c_msg msg[] = {
+		{
+			.addr = 0x74 >> 1, /* primary link */
+			.flags = 0,
+			.len = 1,
+			.buf = &reg,
+		},
+		{
+			.addr = 0x74 >> 1, /* primary link */
+			.flags = I2C_M_RD,
+			.len = len,
+			.buf = data,
+		},
+	};
+
+	status = i2c_transfer(nvhdcp->client->adapter, msg, ARRAY_SIZE(msg));
+
+	if (status < 0) {
+		nvhdcp_err("i2c xfer error %d\n", status);
+		return status;
+	}
+
+	return 0;
+}
+
+static int nvhdcp_i2c_write(struct tegra_nvhdcp *nvhdcp, u8 reg,
+					size_t len, const void *data)
+{
+	int status;
+	u8 buf[len + 1];
+	struct i2c_msg msg[] = {
+		{
+			.addr = 0x74 >> 1, /* primary link */
+			.flags = 0,
+			.len = len + 1,
+			.buf = buf,
+		},
+	};
+
+	buf[0] = reg;
+	memcpy(buf + 1, data, len);
+
+	status = i2c_transfer(nvhdcp->client->adapter, msg, ARRAY_SIZE(msg));
+
+	if (status < 0) {
+		nvhdcp_err("i2c xfer error %d\n", status);
+		return status;
+	}
+
+	return 0;
+}
+
+static inline int nvhdcp_i2c_read8(struct tegra_nvhdcp *nvhdcp, u8 reg, u8 *val)
+{
+	return nvhdcp_i2c_read(nvhdcp, reg, 1, val);
+}
+
+static inline int nvhdcp_i2c_write8(struct tegra_nvhdcp *nvhdcp, u8 reg, u8 val)
+{
+	return nvhdcp_i2c_write(nvhdcp, reg, 1, &val);
+}
+
+static inline int nvhdcp_i2c_read16(struct tegra_nvhdcp *nvhdcp,
+					u8 reg, u16 *val)
+{
+	u8 buf[2];
+	int e;
+
+	e = nvhdcp_i2c_read(nvhdcp, reg, sizeof buf, buf);
+	if (e)
+		return e;
+
+	if (val)
+		*val = buf[0] | (u16)buf[1] << 8;
+
+	return 0;
+}
+
+static int nvhdcp_i2c_read40(struct tegra_nvhdcp *nvhdcp, u8 reg, u64 *val)
+{
+	u8 buf[5];
+	int e, i;
+	u64 n;
+
+	e = nvhdcp_i2c_read(nvhdcp, reg, sizeof buf, buf);
+	if (e)
+		return e;
+
+	for(i = 0, n = 0; i < 5; i++ ) {
+		n <<= 8;
+		n |= buf[4 - i];
+	}
+
+	if (val)
+		*val = n;
+
+	return 0;
+}
+
+static int nvhdcp_i2c_write40(struct tegra_nvhdcp *nvhdcp, u8 reg, u64 val)
+{
+	char buf[5];
+	int i;
+	for(i = 0; i < 5; i++ ) {
+		buf[i] = val;
+		val >>= 8;
+	}
+	return nvhdcp_i2c_write(nvhdcp, reg, sizeof buf, buf);
+}
+
+static int nvhdcp_i2c_write64(struct tegra_nvhdcp *nvhdcp, u8 reg, u64 val)
+{
+	char buf[8];
+	int i;
+	for(i = 0; i < 8; i++ ) {
+		buf[i] = val;
+		val >>= 8;
+	}
+	return nvhdcp_i2c_write(nvhdcp, reg, sizeof buf, buf);
+}
+
+
+/* 64-bit link encryption session random number */
+static inline u64 get_an(struct tegra_dc_hdmi_data *hdmi)
+{
+	u64 r;
+	r = (u64)tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_AN_MSB) << 32;
+	r |= tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_AN_LSB);
+	return r;
+}
+
+/* 64-bit upstream exchange random number */
+static inline void set_cn(struct tegra_dc_hdmi_data *hdmi, u64 c_n)
+{
+	tegra_hdmi_writel(hdmi, (u32)c_n, HDMI_NV_PDISP_RG_HDCP_CN_LSB);
+	tegra_hdmi_writel(hdmi, c_n >> 32, HDMI_NV_PDISP_RG_HDCP_CN_MSB);
+}
+
+
+/* 40-bit transmitter's key selection vector */
+static inline u64 get_aksv(struct tegra_dc_hdmi_data *hdmi)
+{
+	u64 r;
+	r = (u64)tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_AKSV_MSB) << 32;
+	r |= tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
+	return r;
+}
+
+/* 40-bit receiver's key selection vector */
+static inline void set_bksv(struct tegra_dc_hdmi_data *hdmi, u64 b_ksv, bool repeater)
+{
+	if (repeater)
+		b_ksv |= (u64)REPEATER << 32;
+	tegra_hdmi_writel(hdmi, (u32)b_ksv, HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
+	tegra_hdmi_writel(hdmi, b_ksv >> 32, HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
+}
+
+
+/* 40-bit software's key selection vector */
+static inline void set_cksv(struct tegra_dc_hdmi_data *hdmi, u64 c_ksv)
+{
+	tegra_hdmi_writel(hdmi, (u32)c_ksv, HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
+	tegra_hdmi_writel(hdmi, c_ksv >> 32, HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
+}
+
+/* 40-bit connection state */
+static inline u64 get_cs(struct tegra_dc_hdmi_data *hdmi)
+{
+	u64 r;
+	r = (u64)tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_CS_MSB) << 32;
+	r |= tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_CS_LSB);
+	return r;
+}
+
+/* 40-bit upstream key selection vector */
+static inline u64 get_dksv(struct tegra_dc_hdmi_data *hdmi)
+{
+	u64 r;
+	r = (u64)tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_DKSV_MSB) << 32;
+	r |= tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
+	return r;
+}
+
+/* 64-bit encrypted M0 value */
+static inline u64 get_mprime(struct tegra_dc_hdmi_data *hdmi)
+{
+	u64 r;
+	r = (u64)tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB) << 32;
+	r |= tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
+	return r;
+}
+
+static inline u16 get_transmitter_ri(struct tegra_dc_hdmi_data *hdmi)
+{
+	return tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_RI);
+}
+
+static inline int get_receiver_ri(struct tegra_nvhdcp *nvhdcp, u16 *r)
+{
+	return nvhdcp_i2c_read16(nvhdcp, 0x8, r); /* long read */
+}
+
+static int get_bcaps(struct tegra_nvhdcp *nvhdcp, u8 *b_caps)
+{
+	int e, retries = 3;
+	do {
+		e = nvhdcp_i2c_read8(nvhdcp, 0x40, b_caps);
+		if (!e)
+			return 0;
+		msleep(100);
+	} while (--retries);
+
+	return -EIO;
+}
+
+static int get_ksvfifo(struct tegra_nvhdcp *nvhdcp,
+					unsigned num_bksv_list, u64 *ksv_list)
+{
+	u8 *buf, *p;
+	int e;
+	unsigned i;
+	size_t buf_len = num_bksv_list * 5;
+
+	if (!ksv_list || num_bksv_list > TEGRA_NVHDCP_MAX_DEVS)
+		return -EINVAL;
+
+	buf = kmalloc(buf_len, GFP_KERNEL);
+	if (IS_ERR_OR_NULL(buf))
+		return -ENOMEM;
+
+	e = nvhdcp_i2c_read(nvhdcp, 0x43, buf_len, buf);
+	if (e) {
+		kfree(buf);
+		return e;
+	}
+
+	/* load 40-bit keys from repeater into array of u64 */
+	p = buf;
+	for (i = 0; i < num_bksv_list; i++) {
+		ksv_list[i] = p[0] | ((u64)p[1] << 8) | ((u64)p[2] << 16)
+				| ((u64)p[3] << 24) | ((u64)p[4] << 32);
+		p += 5;
+	}
+
+	kfree(buf);
+	return 0;
+}
+
+/* get V' 160-bit SHA-1 hash from repeater */
+static int get_vprime(struct tegra_nvhdcp *nvhdcp, u8 *v_prime)
+{
+	int e, i;
+
+	for (i = 0; i < 20; i += 4) {
+		e = nvhdcp_i2c_read(nvhdcp, 0x20 + i, 4, v_prime + i);
+		if (e)
+			return e;
+	}
+	return 0;
+}
+
+
+/* set or clear RUN_YES */
+static void hdcp_ctrl_run(struct tegra_dc_hdmi_data *hdmi, bool v)
+{
+	u32 ctrl;
+
+	if (v) {
+		ctrl = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_CTRL);
+		ctrl |= HDCP_RUN_YES;
+	} else {
+		ctrl = 0;
+	}
+
+	tegra_hdmi_writel(hdmi, ctrl, HDMI_NV_PDISP_RG_HDCP_CTRL);
+}
+
+/* wait for any bits in mask to be set in HDMI_NV_PDISP_RG_HDCP_CTRL
+ * sleeps up to 120mS */
+static int wait_hdcp_ctrl(struct tegra_dc_hdmi_data *hdmi, u32 mask, u32 *v)
+{
+	int retries = 12;
+	u32 ctrl;
+
+	do {
+		ctrl = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_CTRL);
+		if ((ctrl | (mask))) {
+			if (v)
+				*v = ctrl;
+			break;
+		}
+		msleep(10);
+	} while (--retries);
+	if (!retries) {
+		nvhdcp_err("ctrl read timeout (mask=0x%x)\n", mask);
+		return -EIO;
+	}
+	return 0;
+}
+
+/* wait for any bits in mask to be set in HDMI_NV_PDISP_KEY_CTRL
+ * waits up to 100mS */
+static int wait_key_ctrl(struct tegra_dc_hdmi_data *hdmi, u32 mask)
+{
+	int retries = 100;
+	u32 ctrl;
+
+	do {
+		ctrl = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_KEY_CTRL);
+		if ((ctrl | (mask)))
+			break;
+		msleep(1);
+	} while (--retries);
+	if (!retries) {
+		nvhdcp_err("key ctrl read timeout (mask=0x%x)\n", mask);
+		return -EIO;
+	}
+	return 0;
+}
+
+/* check that key selection vector is well formed.
+ * NOTE: this function assumes KSV has already been checked against
+ * revocation list.
+ */
+static int verify_ksv(u64 k)
+{
+	unsigned i;
+
+	/* count set bits, must be exactly 20 set to be valid */
+	for(i = 0; k; i++)
+		k ^= k & -k;
+
+	return  (i != 20) ? -EINVAL : 0;
+}
+
+/* get Status and Kprime signature - READ_S on TMDS0_LINK0 only */
+static int get_s_prime(struct tegra_nvhdcp *nvhdcp, struct tegra_nvhdcp_packet *pkt)
+{
+	struct tegra_dc_hdmi_data *hdmi = nvhdcp->hdmi;
+	u32 sp_msb, sp_lsb1, sp_lsb2;
+	int e;
+
+	/* if connection isn't authenticated ... */
+	if (atomic_read(&nvhdcp->state) != STATE_LINK_VERIFY) {
+		memset(pkt, 0, sizeof *pkt);
+		pkt->packet_results = TEGRA_NVHDCP_RESULT_LINK_FAILED;
+		return 0;
+	}
+
+
+	pkt->packet_results = TEGRA_NVHDCP_RESULT_UNSUCCESSFUL;
+
+	/* we will be taking c_n, c_ksv as input */
+	if (!(pkt->value_flags & TEGRA_NVHDCP_FLAG_CN)
+			|| !(pkt->value_flags & TEGRA_NVHDCP_FLAG_CKSV)) {
+		nvhdcp_err("missing value_flags (0x%x)\n", pkt->value_flags);
+		return -EINVAL;
+	}
+
+	pkt->value_flags = 0;
+
+	pkt->a_ksv = nvhdcp->a_ksv;
+	pkt->a_n = nvhdcp->a_n;
+	pkt->value_flags = TEGRA_NVHDCP_FLAG_AKSV | TEGRA_NVHDCP_FLAG_AN;
+
+	nvhdcp_vdbg("%s():cn %llx cksv %llx\n", __func__, pkt->c_n, pkt->c_ksv);
+
+	set_cn(hdmi, pkt->c_n);
+
+	tegra_hdmi_writel(hdmi, TMDS0_LINK0 | READ_S,
+					HDMI_NV_PDISP_RG_HDCP_CMODE);
+
+	set_cksv(hdmi, pkt->c_ksv);
+
+	e = wait_hdcp_ctrl(hdmi, SPRIME_VALID, NULL);
+	if (e) {
+		nvhdcp_err("Sprime read timeout\n");
+		pkt->packet_results = TEGRA_NVHDCP_RESULT_UNSUCCESSFUL;
+		return -EIO;
+	}
+
+	msleep(50);
+
+	/* read 56-bit Sprime plus 16 status bits */
+	sp_msb = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
+	sp_lsb1 = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
+	sp_lsb2 = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
+
+	/* top 8 bits of LSB2 and bottom 8 bits of MSB hold status bits. */
+	pkt->hdcp_status = ( sp_msb << 8 ) | ( sp_lsb2 >> 24);
+	pkt->value_flags |= TEGRA_NVHDCP_FLAG_S;
+
+	/* 56-bit Kprime */
+	pkt->k_prime = ((u64)(sp_lsb2 & 0xffffff) << 32) | sp_lsb1;
+	pkt->value_flags |= TEGRA_NVHDCP_FLAG_KP;
+
+	/* is connection state supported? */
+	if (sp_msb & STATUS_CS) {
+		pkt->cs = get_cs(hdmi);
+		pkt->value_flags |= TEGRA_NVHDCP_FLAG_CS;
+	}
+
+	/* load Dksv */
+	pkt->d_ksv = get_dksv(hdmi);
+	if (verify_ksv(pkt->d_ksv)) {
+		nvhdcp_err("Dksv invalid!\n");
+		pkt->packet_results = TEGRA_NVHDCP_RESULT_UNSUCCESSFUL;
+		return -EIO; /* treat bad Dksv as I/O error */
+	}
+	pkt->value_flags |= TEGRA_NVHDCP_FLAG_DKSV;
+
+	/* copy current Bksv */
+	pkt->b_ksv = nvhdcp->b_ksv;
+	pkt->value_flags |= TEGRA_NVHDCP_FLAG_BKSV;
+
+	pkt->packet_results = TEGRA_NVHDCP_RESULT_SUCCESS;
+	return 0;
+}
+
+/* get M prime - READ_M on TMDS0_LINK0 only */
+static inline int get_m_prime(struct tegra_nvhdcp *nvhdcp, struct tegra_nvhdcp_packet *pkt)
+{
+	struct tegra_dc_hdmi_data *hdmi = nvhdcp->hdmi;
+	int e;
+
+	pkt->packet_results = TEGRA_NVHDCP_RESULT_UNSUCCESSFUL;
+
+	/* if connection isn't authenticated ... */
+	if (atomic_read(&nvhdcp->state) != STATE_LINK_VERIFY) {
+		memset(pkt, 0, sizeof *pkt);
+		pkt->packet_results = TEGRA_NVHDCP_RESULT_LINK_FAILED;
+		return 0;
+	}
+
+	pkt->a_ksv = nvhdcp->a_ksv;
+	pkt->a_n = nvhdcp->a_n;
+	pkt->value_flags = TEGRA_NVHDCP_FLAG_AKSV | TEGRA_NVHDCP_FLAG_AN;
+
+	set_cn(hdmi, pkt->c_n);
+
+	tegra_hdmi_writel(hdmi, TMDS0_LINK0 | READ_M,
+					HDMI_NV_PDISP_RG_HDCP_CMODE);
+
+	/* Cksv write triggers Mprime update */
+	set_cksv(hdmi, pkt->c_ksv);
+
+	e = wait_hdcp_ctrl(hdmi, MPRIME_VALID, NULL);
+	if (e) {
+		nvhdcp_err("Mprime read timeout\n");
+		return -EIO;
+	}
+	msleep(50);
+
+	/* load Mprime */
+	pkt->m_prime = get_mprime(hdmi);
+	pkt->value_flags |= TEGRA_NVHDCP_FLAG_MP;
+
+	pkt->b_status = nvhdcp->b_status;
+	pkt->value_flags |= TEGRA_NVHDCP_FLAG_BSTATUS;
+
+	/* copy most recent KSVFIFO, if it is non-zero */
+	pkt->num_bksv_list = nvhdcp->num_bksv_list;
+	if( nvhdcp->num_bksv_list ) {
+		BUILD_BUG_ON(sizeof(pkt->bksv_list) != sizeof(nvhdcp->bksv_list));
+		memcpy(pkt->bksv_list, nvhdcp->bksv_list,
+			nvhdcp->num_bksv_list * sizeof(*pkt->bksv_list));
+		pkt->value_flags |= TEGRA_NVHDCP_FLAG_BKSVLIST;
+	}
+
+	/* copy v_prime */
+	BUILD_BUG_ON(sizeof(pkt->v_prime) != sizeof(nvhdcp->v_prime));
+	memcpy(pkt->v_prime, nvhdcp->v_prime, sizeof(nvhdcp->v_prime));
+	pkt->value_flags |= TEGRA_NVHDCP_FLAG_V;
+
+	/* load Dksv */
+	pkt->d_ksv = get_dksv(hdmi);
+	if (verify_ksv(pkt->d_ksv)) {
+		nvhdcp_err("Dksv invalid!\n");
+		return -EIO; /* treat bad Dksv as I/O error */
+	}
+	pkt->value_flags |= TEGRA_NVHDCP_FLAG_DKSV;
+
+	/* copy current Bksv */
+	pkt->b_ksv = nvhdcp->b_ksv;
+	pkt->value_flags |= TEGRA_NVHDCP_FLAG_BKSV;
+
+	pkt->packet_results = TEGRA_NVHDCP_RESULT_SUCCESS;
+	return 0;
+}
+
+static int load_kfuse(struct tegra_dc_hdmi_data *hdmi)
+{
+	unsigned buf[KFUSE_DATA_SZ / 4];
+	int e, i;
+	u32 ctrl;
+	u32 tmp;
+	int retries;
+
+	/* copy load kfuse into buffer - only needed for early Tegra parts */
+	e = tegra_kfuse_read(buf, sizeof buf);
+	if (e) {
+		nvhdcp_err("Kfuse read failure\n");
+		return e;
+	}
+
+	/* write the kfuse to HDMI SRAM */
+
+	tegra_hdmi_writel(hdmi, 1, HDMI_NV_PDISP_KEY_CTRL); /* LOAD_KEYS */
+
+	/* issue a reload */
+	ctrl = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_KEY_CTRL);
+	tegra_hdmi_writel(hdmi, ctrl | PKEY_REQUEST_RELOAD_TRIGGER
+					| LOCAL_KEYS , HDMI_NV_PDISP_KEY_CTRL);
+
+	e = wait_key_ctrl(hdmi, PKEY_LOADED);
+	if (e) {
+		nvhdcp_err("key reload timeout\n");
+		return -EIO;
+	}
+
+	tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_KEY_SKEY_INDEX);
+
+	/* wait for SRAM to be cleared */
+	retries = 5;
+	do {
+		tmp = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_KEY_DEBUG0);
+		if ((tmp & 1) == 0) break;
+		mdelay(1);
+	} while (--retries);
+	if (!retries) {
+		nvhdcp_err("key SRAM clear timeout\n");
+		return -EIO;
+	}
+
+	for (i = 0; i < KFUSE_DATA_SZ / 4; i += 4) {
+
+		/* load 128-bits*/
+		tegra_hdmi_writel(hdmi, buf[i], HDMI_NV_PDISP_KEY_HDCP_KEY_0);
+		tegra_hdmi_writel(hdmi, buf[i+1], HDMI_NV_PDISP_KEY_HDCP_KEY_1);
+		tegra_hdmi_writel(hdmi, buf[i+2], HDMI_NV_PDISP_KEY_HDCP_KEY_2);
+		tegra_hdmi_writel(hdmi, buf[i+3], HDMI_NV_PDISP_KEY_HDCP_KEY_3);
+
+		/* trigger LOAD_HDCP_KEY */
+		tegra_hdmi_writel(hdmi, 0x100, HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
+
+		tmp = LOCAL_KEYS | WRITE16;
+		if (i)
+			tmp |= AUTOINC;
+		tegra_hdmi_writel(hdmi, tmp, HDMI_NV_PDISP_KEY_CTRL);
+
+		/* wait for WRITE16 to complete */
+		e = wait_key_ctrl(hdmi, 0x10); /* WRITE16 */
+		if (e) {
+			nvhdcp_err("key write timeout\n");
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+static int verify_link(struct tegra_nvhdcp *nvhdcp, bool wait_ri)
+{
+	struct tegra_dc_hdmi_data *hdmi = nvhdcp->hdmi;
+	int retries = 3;
+	u16 old, rx, tx;
+	int e;
+
+	old = 0;
+	rx = 0;
+	tx = 0;
+	/* retry 3 times to deal with I2C link issues */
+	do {
+		if (wait_ri)
+			old = get_transmitter_ri(hdmi);
+
+		e = get_receiver_ri(nvhdcp, &rx);
+		if (!e) {
+			if (!rx) {
+				nvhdcp_err("Ri is 0!\n");
+				return -EINVAL;
+			}
+
+			tx = get_transmitter_ri(hdmi);
+		} else {
+			rx = ~tx;
+			msleep(50);
+		}
+
+	} while (wait_ri && --retries && old != tx);
+
+	nvhdcp_debug("R0 Ri poll:rx=0x%04x tx=0x%04x\n", rx, tx);
+
+	if (!atomic_read(&nvhdcp->plugged)) {
+		nvhdcp_err("aborting verify links - lost hdmi connection\n");
+		return -EIO;
+	}
+
+	if (rx != tx)
+		return -EINVAL;
+
+	return 0;
+}
+
+static int get_repeater_info(struct tegra_nvhdcp *nvhdcp)
+{
+	int e, retries;
+	u8 b_caps;
+	u16 b_status;
+
+	nvhdcp_vdbg("repeater found:fetching repeater info\n");
+
+	/* wait up to 5 seconds for READY on repeater */
+	retries = 50;
+	do {
+		if (!atomic_read(&nvhdcp->plugged)) {
+			nvhdcp_err("disconnect while waiting for repeater\n");
+			return -EIO;
+		}
+
+		e = get_bcaps(nvhdcp, &b_caps);
+		if (!e && (b_caps & BCAPS_READY)) {
+			nvhdcp_debug("Bcaps READY from repeater\n");
+			break;
+		}
+		msleep(100);
+	} while (--retries);
+	if (!retries) {
+		nvhdcp_err("repeater Bcaps read timeout\n");
+		return -ETIMEDOUT;
+	}
+
+	memset(nvhdcp->v_prime, 0, sizeof nvhdcp->v_prime);
+	e = get_vprime(nvhdcp, nvhdcp->v_prime);
+	if (e) {
+		nvhdcp_err("repeater Vprime read failure!\n");
+		return e;
+	}
+
+	e = nvhdcp_i2c_read16(nvhdcp, 0x41, &b_status);
+	if (e) {
+		nvhdcp_err("Bstatus read failure!\n");
+		return e;
+	}
+
+	if (b_status & BSTATUS_MAX_DEVS_EXCEEDED) {
+		nvhdcp_err("repeater:max devices (0x%04x)\n", b_status);
+		return -EINVAL;
+	}
+
+	if (b_status & BSTATUS_MAX_CASCADE_EXCEEDED) {
+		nvhdcp_err("repeater:max cascade (0x%04x)\n", b_status);
+		return -EINVAL;
+	}
+
+	nvhdcp->b_status = b_status;
+	nvhdcp->num_bksv_list = b_status & 0x7f;
+	nvhdcp_vdbg("Bstatus 0x%x (devices: %d)\n",
+				b_status, nvhdcp->num_bksv_list);
+
+	memset(nvhdcp->bksv_list, 0, sizeof nvhdcp->bksv_list);
+	e = get_ksvfifo(nvhdcp, nvhdcp->num_bksv_list, nvhdcp->bksv_list);
+	if (e) {
+		nvhdcp_err("repeater:could not read KSVFIFO (err %d)\n", e);
+		return e;
+	}
+
+	return 0;
+}
+
+static void nvhdcp_downstream_worker(struct work_struct *work)
+{
+	struct tegra_nvhdcp *nvhdcp =
+	        container_of(work, struct tegra_nvhdcp, work);
+	struct tegra_dc_hdmi_data *hdmi = nvhdcp->hdmi;
+	int e;
+	u8 b_caps;
+	u32 tmp;
+	u32 res;
+	int st;
+
+	nvhdcp_vdbg("%s():started thread %s\n", __func__, nvhdcp->name);
+
+	st = atomic_read(&nvhdcp->state);
+	if (st == STATE_OFF) {
+		nvhdcp_err("nvhdcp failure - giving up\n");
+		return;
+	}
+
+	atomic_set(&nvhdcp->state, STATE_UNAUTHENTICATED);
+
+	/* check plug state to terminate early in case flush_workqueue() */
+	if (!atomic_read(&nvhdcp->plugged)) {
+		nvhdcp_err("worker started while unplugged!\n");
+		goto lost_hdmi;
+	}
+
+	nvhdcp->a_ksv = 0;
+	nvhdcp->b_ksv = 0;
+	nvhdcp->a_n = 0;
+
+	nvhdcp_vdbg("%s():hpd=%d\n", __func__, atomic_read(&nvhdcp->plugged));
+
+	e = get_bcaps(nvhdcp, &b_caps);
+	if (e) {
+		nvhdcp_err("Bcaps read failure\n");
+		goto failure;
+	}
+
+	nvhdcp_vdbg("read Bcaps = 0x%02x\n", b_caps);
+
+	nvhdcp_vdbg("kfuse loading ...\n");
+
+	/* repeater flag in Bskv must be configured before loading fuses */
+	set_bksv(hdmi, 0, (b_caps & BCAPS_REPEATER));
+
+	e = load_kfuse(hdmi);
+	if (e) {
+		nvhdcp_err("kfuse could not be loaded\n");
+		goto failure;
+	}
+
+	hdcp_ctrl_run(hdmi, 1);
+
+	nvhdcp_vdbg("wait AN_VALID ...\n");
+
+	/* wait for hardware to generate HDCP values */
+	e = wait_hdcp_ctrl(hdmi, AN_VALID | SROM_ERR, &res);
+	if (e) {
+		nvhdcp_err("An key generation timeout\n");
+		goto failure;
+	}
+	if (res & SROM_ERR) {
+		nvhdcp_err("SROM error\n");
+		goto failure;
+	}
+
+	msleep(25);
+
+	nvhdcp->a_ksv = get_aksv(hdmi);
+	nvhdcp->a_n = get_an(hdmi);
+	nvhdcp_vdbg("Aksv is 0x%016llx\n", nvhdcp->a_ksv);
+	nvhdcp_vdbg("An is 0x%016llx\n", nvhdcp->a_n);
+	if (verify_ksv(nvhdcp->a_ksv)) {
+		nvhdcp_err("Aksv verify failure! (0x%016llx)\n", nvhdcp->a_ksv);
+		goto failure;
+	}
+
+	/* write Ainfo to receiver - set 1.1 only if b_caps supports it */
+	e = nvhdcp_i2c_write8(nvhdcp, 0x15, b_caps & BCAPS_11);
+	if (e) {
+		nvhdcp_err("Ainfo write failure\n");
+		goto failure;
+	}
+
+	/* write An to receiver */
+	e = nvhdcp_i2c_write64(nvhdcp, 0x18, nvhdcp->a_n);
+	if (e) {
+		nvhdcp_err("An write failure\n");
+		goto failure;
+	}
+
+	nvhdcp_vdbg("wrote An = 0x%016llx\n", nvhdcp->a_n);
+
+	/* write Aksv to receiver - triggers auth sequence */
+	e = nvhdcp_i2c_write40(nvhdcp, 0x10, nvhdcp->a_ksv);
+	if (e) {
+		nvhdcp_err("Aksv write failure\n");
+		goto failure;
+	}
+
+	nvhdcp_vdbg("wrote Aksv = 0x%010llx\n", nvhdcp->a_ksv);
+
+	/* bail out if unplugged in the middle of negotiation */
+	if (!atomic_read(&nvhdcp->plugged))
+		goto lost_hdmi;
+
+	/* get Bksv from receiver */
+	e = nvhdcp_i2c_read40(nvhdcp, 0x00, &nvhdcp->b_ksv);
+	if (e) {
+		nvhdcp_err("Bksv read failure\n");
+		goto failure;
+	}
+	nvhdcp_vdbg("Bksv is 0x%016llx\n", nvhdcp->b_ksv);
+	if (verify_ksv(nvhdcp->b_ksv)) {
+		nvhdcp_err("Bksv verify failure!\n");
+		goto failure;
+	}
+
+	nvhdcp_vdbg("read Bksv = 0x%010llx from device\n", nvhdcp->b_ksv);
+
+	set_bksv(hdmi, nvhdcp->b_ksv, (b_caps & BCAPS_REPEATER));
+
+	nvhdcp_vdbg("loaded Bksv into controller\n");
+
+	e = wait_hdcp_ctrl(hdmi, R0_VALID, NULL);
+	if (e) {
+		nvhdcp_err("R0 read failure!\n");
+		goto failure;
+	}
+
+	nvhdcp_vdbg("R0 valid\n");
+
+	msleep(100); /* can't read R0' within 100ms of writing Aksv */
+
+	nvhdcp_vdbg("verifying links ...\n");
+
+	e = verify_link(nvhdcp, false);
+	if (e) {
+		nvhdcp_err("link verification failed err %d\n", e);
+		goto failure;
+	}
+
+	tmp = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_RG_HDCP_CTRL);
+	tmp |= CRYPT_ENABLED;
+	if (b_caps & BCAPS_11) /* HDCP 1.1 ? */
+		tmp |= ONEONE_ENABLED;
+	tegra_hdmi_writel(hdmi, tmp, HDMI_NV_PDISP_RG_HDCP_CTRL);
+
+	nvhdcp_vdbg("CRYPT enabled\n");
+
+	/* if repeater then get repeater info */
+	if (b_caps & BCAPS_REPEATER) {
+		e = get_repeater_info(nvhdcp);
+		if (e) {
+			nvhdcp_err("get repeater info failed\n");
+			goto failure;
+		}
+	}
+
+	atomic_set(&nvhdcp->state, STATE_LINK_VERIFY);
+	nvhdcp_info("link verified!\n");
+
+	while (atomic_read(&nvhdcp->state) == STATE_LINK_VERIFY) {
+		if (!atomic_read(&nvhdcp->plugged))
+			goto lost_hdmi;
+		e = verify_link(nvhdcp, true);
+		if (e) {
+			nvhdcp_err("link verification failed err %d\n", e);
+			goto failure;
+		}
+		msleep(1500);
+	}
+
+failure:
+	/* TODO: check policy to see if we should start again
+	 * or wait for read_m/read_s to come in (on-demand)
+	 */
+	nvhdcp_err("nvhdcp failure - renegotiating in 1.75 seconds\n");
+	atomic_set(&nvhdcp->state, STATE_UNAUTHENTICATED);
+	hdcp_ctrl_run(hdmi, 0);
+	msleep(1750);
+	queue_work(nvhdcp->downstream_wq, &nvhdcp->work);
+	return;
+lost_hdmi:
+	nvhdcp_err("lost hdmi connection\n");
+	atomic_set(&nvhdcp->state, STATE_UNAUTHENTICATED);
+	hdcp_ctrl_run(hdmi, 0);
+	return;
+}
+
+void tegra_nvhdcp_set_plug(struct tegra_nvhdcp *nvhdcp, bool hpd)
+{
+	nvhdcp_info("hdmi hotplug detected (hpd = %d)\n", hpd);
+
+	atomic_set(&nvhdcp->plugged, hpd);
+
+	if (hpd) {
+		queue_work(nvhdcp->downstream_wq, &nvhdcp->work);
+	} else {
+		flush_workqueue(nvhdcp->downstream_wq);
+	}
+}
+
+static int tegra_nvhdcp_on(struct tegra_nvhdcp *nvhdcp)
+{
+	atomic_set(&nvhdcp->state, STATE_UNAUTHENTICATED);
+	if (atomic_read(&nvhdcp->plugged))
+		queue_work(nvhdcp->downstream_wq, &nvhdcp->work);
+	return 0;
+}
+
+static int tegra_nvhdcp_off(struct tegra_nvhdcp *nvhdcp)
+{
+	atomic_set(&nvhdcp->state, STATE_OFF);
+	atomic_set(&nvhdcp->plugged, 0); /* force early termination */
+	flush_workqueue(nvhdcp->downstream_wq);
+	return 0;
+}
+
+int tegra_nvhdcp_set_policy(struct tegra_nvhdcp *nvhdcp, int pol)
+{
+	pol = !!pol;
+	nvhdcp_info("using \"%s\" policy.\n",
+					pol ? "always on" : "on demand");
+	if (atomic_xchg(&nvhdcp->policy, pol) == TEGRA_NVHDCP_POLICY_ON_DEMAND
+				&& pol == TEGRA_NVHDCP_POLICY_ALWAYS_ON) {
+		/* policy was off but now it is on, start working */
+		tegra_nvhdcp_on(nvhdcp);
+	}
+	return 0;
+}
+
+static int tegra_nvhdcp_renegotiate(struct tegra_nvhdcp *nvhdcp)
+{
+	atomic_set(&nvhdcp->state, STATE_RENEGOTIATE);
+	tegra_nvhdcp_on(nvhdcp);
+	return 0;
+}
+
+void tegra_nvhdcp_suspend(struct tegra_nvhdcp *nvhdcp)
+{
+	if (!nvhdcp) return;
+	tegra_nvhdcp_off(nvhdcp);
+}
+
+
+static long nvhdcp_dev_ioctl(struct file *filp,
+                unsigned int cmd, unsigned long arg)
+{
+	struct tegra_nvhdcp *nvhdcp = filp->private_data;
+	struct tegra_nvhdcp_packet *pkt;
+	int e = -ENOTTY;
+
+	switch (cmd) {
+	case TEGRAIO_NVHDCP_ON:
+		return tegra_nvhdcp_on(nvhdcp);
+
+	case TEGRAIO_NVHDCP_OFF:
+		return tegra_nvhdcp_off(nvhdcp);
+
+	case TEGRAIO_NVHDCP_SET_POLICY:
+		return tegra_nvhdcp_set_policy(nvhdcp, arg);
+
+	case TEGRAIO_NVHDCP_READ_M:
+		pkt = kmalloc(sizeof(*pkt), GFP_KERNEL);
+		if (!pkt)
+			return -ENOMEM;
+		if (copy_from_user(pkt, (void __user *)arg, sizeof(*pkt))) {
+			e = -EFAULT;
+			goto kfree_pkt;
+		}
+		e = get_m_prime(nvhdcp, pkt);
+		if (copy_to_user((void __user *)arg, pkt, sizeof(*pkt))) {
+			e = -EFAULT;
+			goto kfree_pkt;
+		}
+		kfree(pkt);
+		return e;
+
+	case TEGRAIO_NVHDCP_READ_S:
+		pkt = kmalloc(sizeof(*pkt), GFP_KERNEL);
+		if (!pkt)
+			return -ENOMEM;
+		if (copy_from_user(pkt, (void __user *)arg, sizeof(*pkt))) {
+			e = -EFAULT;
+			goto kfree_pkt;
+		}
+		e = get_s_prime(nvhdcp, pkt);
+		if (copy_to_user((void __user *)arg, pkt, sizeof(*pkt))) {
+			e = -EFAULT;
+			goto kfree_pkt;
+		}
+		kfree(pkt);
+		return e;
+
+	case TEGRAIO_NVHDCP_RENEGOTIATE:
+		e = tegra_nvhdcp_renegotiate(nvhdcp);
+		break;
+	}
+
+	return e;
+kfree_pkt:
+	kfree(pkt);
+	return e;
+}
+
+/* every open indexes a new AP link */
+static int nvhdcp_dev_open(struct inode *inode, struct file *filp)
+{
+	if (nvhdcp_ap >= TEGRA_NVHDCP_NUM_AP)
+		return -EMFILE;
+
+	if (!nvhdcp_dev[nvhdcp_ap])
+		return -ENODEV;
+
+	filp->private_data = nvhdcp_dev[nvhdcp_ap++];
+
+	return 0;
+}
+
+static int nvhdcp_dev_release(struct inode *inode, struct file *filp)
+{
+	filp->private_data = NULL;
+	--nvhdcp_ap;
+	return 0;
+}
+
+static const struct file_operations nvhdcp_fops = {
+	.owner          = THIS_MODULE,
+	.llseek         = no_llseek,
+	.unlocked_ioctl = nvhdcp_dev_ioctl,
+	.open           = nvhdcp_dev_open,
+	.release        = nvhdcp_dev_release,
+};
+
+struct tegra_nvhdcp *tegra_nvhdcp_create(struct tegra_dc_hdmi_data *hdmi,
+			int id, int bus)
+{
+	struct tegra_nvhdcp *nvhdcp;
+	struct i2c_adapter *adapter;
+	int e;
+
+	nvhdcp = kzalloc(sizeof(*nvhdcp), GFP_KERNEL);
+	if (!nvhdcp)
+		return ERR_PTR(-ENOMEM);
+
+	nvhdcp->id = id;
+	snprintf(nvhdcp->name, sizeof(nvhdcp->name), "nvhdcp%u", id);
+	nvhdcp->hdmi = hdmi;
+	mutex_init(&nvhdcp->lock);
+
+	strlcpy(nvhdcp->info.type, nvhdcp->name, sizeof(nvhdcp->info.type));
+	nvhdcp->bus = bus;
+	nvhdcp->info.addr = 0x74 >> 1;
+	nvhdcp->info.platform_data = nvhdcp;
+
+	adapter = i2c_get_adapter(bus);
+	if (!adapter) {
+		nvhdcp_err("can't get adapter for bus %d\n", bus);
+		e = -EBUSY;
+		goto free_nvhdcp;
+	}
+
+	nvhdcp->client = i2c_new_device(adapter, &nvhdcp->info);
+	i2c_put_adapter(adapter);
+
+	if (!nvhdcp->client) {
+		nvhdcp_err("can't create new device\n");
+		e = -EBUSY;
+		goto free_nvhdcp;
+	}
+
+	atomic_set(&nvhdcp->state, STATE_UNAUTHENTICATED);
+
+	nvhdcp->downstream_wq = create_singlethread_workqueue(nvhdcp->name);
+	INIT_WORK(&nvhdcp->work, nvhdcp_downstream_worker);
+
+	nvhdcp->miscdev.minor = MISC_DYNAMIC_MINOR;
+	nvhdcp->miscdev.name = nvhdcp->name;
+	nvhdcp->miscdev.fops = &nvhdcp_fops;
+
+	e = misc_register(&nvhdcp->miscdev);
+	if (e)
+		goto free_workqueue;
+
+	nvhdcp_vdbg("%s(): created misc device %s\n", __func__, nvhdcp->name);
+
+	nvhdcp_dev[0] = nvhdcp; /* we only support on AP right now */
+
+	return nvhdcp;
+free_workqueue:
+	destroy_workqueue(nvhdcp->downstream_wq);
+	i2c_release_client(nvhdcp->client);
+free_nvhdcp:
+	kfree(nvhdcp);
+	nvhdcp_err("unable to create device.\n");
+	return ERR_PTR(e);
+}
+
+void tegra_nvhdcp_destroy(struct tegra_nvhdcp *nvhdcp)
+{
+	misc_deregister(&nvhdcp->miscdev);
+	atomic_set(&nvhdcp->plugged, 0); /* force early termination */
+	flush_workqueue(nvhdcp->downstream_wq);
+	destroy_workqueue(nvhdcp->downstream_wq);
+	i2c_release_client(nvhdcp->client);
+	kfree(nvhdcp);
+}
diff --git a/drivers/video/tegra/dc/nvhdcp.h b/drivers/video/tegra/dc/nvhdcp.h
new file mode 100644
index 000000000000..9b898252d534
--- /dev/null
+++ b/drivers/video/tegra/dc/nvhdcp.h
@@ -0,0 +1,29 @@
+/*
+ * drivers/video/tegra/dc/nvhdcp.h
+ *
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __DRIVERS_VIDEO_TEGRA_DC_NVHDCP_H
+#define __DRIVERS_VIDEO_TEGRA_DC_NVHDCP_H
+#include <video/nvhdcp.h>
+
+struct tegra_nvhdcp;
+void tegra_nvhdcp_set_plug(struct tegra_nvhdcp *nvhdcp, bool hpd);
+int tegra_nvhdcp_set_policy(struct tegra_nvhdcp *nvhdcp, int pol);
+void tegra_nvhdcp_suspend(struct tegra_nvhdcp *nvhdcp);
+struct tegra_nvhdcp *tegra_nvhdcp_create(struct tegra_dc_hdmi_data *hdmi,
+					int id, int bus);
+void tegra_nvhdcp_destroy(struct tegra_nvhdcp *nvhdcp);
+
+#endif
diff --git a/drivers/video/tegra/dc/overlay.c b/drivers/video/tegra/dc/overlay.c
new file mode 100644
index 000000000000..d522b394fcc6
--- /dev/null
+++ b/drivers/video/tegra/dc/overlay.c
@@ -0,0 +1,647 @@
+/*
+ * drivers/video/tegra/overlay/overlay.c
+ *
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/miscdevice.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/tegra_overlay.h>
+#include <linux/uaccess.h>
+
+#include <asm/atomic.h>
+
+#include <mach/dc.h>
+#include <mach/fb.h>
+#include <mach/nvhost.h>
+
+#include "dc_priv.h"
+#include "../nvmap/nvmap.h"
+#include "overlay.h"
+
+struct overlay_client;
+
+struct overlay {
+	struct overlay_client	*owner;
+};
+
+struct tegra_overlay_info {
+	struct miscdevice	dev;
+
+	struct list_head	clients;
+	spinlock_t		clients_lock;
+
+	struct overlay		overlays[DC_N_WINDOWS];
+	spinlock_t		overlays_lock;
+
+	struct nvhost_device	*ndev;
+
+	struct nvmap_client	*overlay_nvmap;
+
+	struct tegra_dc		*dc;
+
+	struct workqueue_struct	*flip_wq;
+
+	/* Big enough for tegra_dc%u when %u < 10 */
+	char			name[10];
+};
+
+struct overlay_client {
+	struct tegra_overlay_info	*dev;
+	struct list_head		list;
+	struct task_struct		*task;
+	struct nvmap_client		*user_nvmap;
+};
+
+struct tegra_overlay_flip_win {
+	struct tegra_overlay_windowattr	attr;
+	struct nvmap_handle_ref		*handle;
+	dma_addr_t			phys_addr;
+};
+
+struct tegra_overlay_flip_data {
+	struct work_struct		work;
+	struct tegra_overlay_info	*overlay;
+	struct tegra_overlay_flip_win	win[TEGRA_FB_FLIP_N_WINDOWS];
+	u32				syncpt_max;
+};
+
+/* Overlay window manipulation */
+static int tegra_overlay_pin_window(struct tegra_overlay_info *overlay,
+				    struct tegra_overlay_flip_win *flip_win,
+				    struct nvmap_client *user_nvmap)
+{
+	struct nvmap_handle_ref *win_dupe;
+	struct nvmap_handle *win_handle;
+	unsigned long buff_id = flip_win->attr.buff_id;
+
+	if (!buff_id)
+		return 0;
+
+	win_handle = nvmap_get_handle_id(user_nvmap, buff_id);
+	if (win_handle == NULL) {
+		dev_err(&overlay->ndev->dev, "%s: flip invalid "
+			"handle %08lx\n", current->comm, buff_id);
+		return -EPERM;
+	}
+
+	/* duplicate the new framebuffer's handle into the fb driver's
+	 * nvmap context, to ensure that the handle won't be freed as
+	 * long as it is in-use by the fb driver */
+	win_dupe = nvmap_duplicate_handle_id(overlay->overlay_nvmap, buff_id);
+	nvmap_handle_put(win_handle);
+
+	if (IS_ERR(win_dupe)) {
+		dev_err(&overlay->ndev->dev, "couldn't duplicate handle\n");
+		return PTR_ERR(win_dupe);
+	}
+
+	flip_win->handle = win_dupe;
+
+	flip_win->phys_addr = nvmap_pin(overlay->overlay_nvmap, win_dupe);
+	if (IS_ERR((void *)flip_win->phys_addr)) {
+		dev_err(&overlay->ndev->dev, "couldn't pin handle\n");
+		nvmap_free(overlay->overlay_nvmap, win_dupe);
+		return PTR_ERR((void *)flip_win->phys_addr);
+	}
+
+	return 0;
+}
+
+static int tegra_overlay_set_windowattr(struct tegra_overlay_info *overlay,
+					struct tegra_dc_win *win,
+					const struct tegra_overlay_flip_win *flip_win)
+{
+	int xres, yres;
+	if (flip_win->handle == NULL) {
+		win->flags = 0;
+		win->cur_handle = NULL;
+		return 0;
+	}
+
+	xres = overlay->dc->mode.h_active;
+	yres = overlay->dc->mode.v_active;
+
+	win->flags = TEGRA_WIN_FLAG_ENABLED;
+	if (flip_win->attr.blend == TEGRA_FB_WIN_BLEND_PREMULT)
+		win->flags |= TEGRA_WIN_FLAG_BLEND_PREMULT;
+	else if (flip_win->attr.blend == TEGRA_FB_WIN_BLEND_COVERAGE)
+		win->flags |= TEGRA_WIN_FLAG_BLEND_COVERAGE;
+	win->fmt = flip_win->attr.pixformat;
+	win->x = flip_win->attr.x;
+	win->y = flip_win->attr.y;
+	win->w = flip_win->attr.w;
+	win->h = flip_win->attr.h;
+	win->out_x = flip_win->attr.out_x;
+	win->out_y = flip_win->attr.out_y;
+	win->out_w = flip_win->attr.out_w;
+	win->out_h = flip_win->attr.out_h;
+
+	if (((win->out_x + win->out_w) > xres) && (win->out_x < xres))
+		win->out_w = xres - win->out_x;
+
+	if (((win->out_y + win->out_h) > yres) && (win->out_y < yres))
+		win->out_h = yres - win->out_y;
+
+	win->z = flip_win->attr.z;
+	win->cur_handle = flip_win->handle;
+
+	/* STOPSHIP verify that this won't read outside of the surface */
+	win->phys_addr = flip_win->phys_addr + flip_win->attr.offset;
+	win->offset_u = flip_win->attr.offset_u + flip_win->attr.offset;
+	win->offset_v = flip_win->attr.offset_v + flip_win->attr.offset;
+	win->stride = flip_win->attr.stride;
+	win->stride_uv = flip_win->attr.stride_uv;
+	if (flip_win->attr.tiled)
+		win->flags |= TEGRA_WIN_FLAG_TILED;
+
+	if ((s32)flip_win->attr.pre_syncpt_id >= 0) {
+		nvhost_syncpt_wait_timeout(&overlay->ndev->host->syncpt,
+					   flip_win->attr.pre_syncpt_id,
+					   flip_win->attr.pre_syncpt_val,
+					   msecs_to_jiffies(500));
+	}
+
+
+	return 0;
+}
+
+static void tegra_overlay_flip_worker(struct work_struct *work)
+{
+	struct tegra_overlay_flip_data *data =
+		container_of(work, struct tegra_overlay_flip_data, work);
+	struct tegra_overlay_info *overlay = data->overlay;
+	struct tegra_dc_win *win;
+	struct tegra_dc_win *wins[TEGRA_FB_FLIP_N_WINDOWS];
+	struct nvmap_handle_ref *unpin_handles[TEGRA_FB_FLIP_N_WINDOWS];
+	int i, nr_win = 0, nr_unpin = 0;
+
+	data = container_of(work, struct tegra_overlay_flip_data, work);
+
+	for (i = 0; i < TEGRA_FB_FLIP_N_WINDOWS; i++) {
+		struct tegra_overlay_flip_win *flip_win = &data->win[i];
+		int idx = flip_win->attr.index;
+
+		if (idx == -1)
+			continue;
+
+		win = tegra_dc_get_window(overlay->dc, idx);
+
+		if (!win)
+			continue;
+
+		if (win->flags && win->cur_handle)
+			unpin_handles[nr_unpin++] = win->cur_handle;
+
+		tegra_overlay_set_windowattr(overlay, win, &data->win[i]);
+
+		wins[nr_win++] = win;
+
+#if 0
+		if (flip_win->attr.pre_syncpt_id < 0)
+			continue;
+		printk("%08x %08x\n",
+		       flip_win->attr.pre_syncpt_id,
+		       flip_win->attr.pre_syncpt_val);
+
+		nvhost_syncpt_wait_timeout(&overlay->ndev->host->syncpt,
+					   flip_win->attr.pre_syncpt_id,
+					   flip_win->attr.pre_syncpt_val,
+					   msecs_to_jiffies(500));
+#endif
+	}
+
+	tegra_dc_update_windows(wins, nr_win);
+	/* TODO: implement swapinterval here */
+	tegra_dc_sync_windows(wins, nr_win);
+
+	tegra_dc_incr_syncpt_min(overlay->dc, data->syncpt_max);
+
+	/* unpin and deref previous front buffers */
+	for (i = 0; i < nr_unpin; i++) {
+		nvmap_unpin(overlay->overlay_nvmap, unpin_handles[i]);
+		nvmap_free(overlay->overlay_nvmap, unpin_handles[i]);
+	}
+
+	kfree(data);
+}
+
+static int tegra_overlay_flip(struct tegra_overlay_info *overlay,
+			      struct tegra_overlay_flip_args *args,
+			      struct nvmap_client *user_nvmap)
+{
+	struct tegra_overlay_flip_data *data;
+	struct tegra_overlay_flip_win *flip_win;
+	u32 syncpt_max;
+	int i, err;
+
+	if (WARN_ON(!overlay->ndev))
+		return -EFAULT;
+
+	data = kzalloc(sizeof(*data), GFP_KERNEL);
+	if (data == NULL) {
+		dev_err(&overlay->ndev->dev,
+			"can't allocate memory for flip\n");
+		return -ENOMEM;
+	}
+
+	INIT_WORK(&data->work, tegra_overlay_flip_worker);
+	data->overlay = overlay;
+
+	for (i = 0; i < TEGRA_FB_FLIP_N_WINDOWS; i++) {
+		flip_win = &data->win[i];
+
+		memcpy(&flip_win->attr, &args->win[i], sizeof(flip_win->attr));
+
+		if (flip_win->attr.index == -1)
+			continue;
+
+		err = tegra_overlay_pin_window(overlay, flip_win, user_nvmap);
+		if (err < 0) {
+			dev_err(&overlay->ndev->dev,
+				"error setting window attributes\n");
+			goto surf_err;
+		}
+	}
+
+	syncpt_max = tegra_dc_incr_syncpt_max(overlay->dc);
+	data->syncpt_max = syncpt_max;
+
+	queue_work(overlay->flip_wq, &data->work);
+
+	args->post_syncpt_val = syncpt_max;
+	args->post_syncpt_id = tegra_dc_get_syncpt_id(overlay->dc);
+
+	return 0;
+
+surf_err:
+	while (i--) {
+		if (data->win[i].handle) {
+			nvmap_unpin(overlay->overlay_nvmap,
+				    data->win[i].handle);
+			nvmap_free(overlay->overlay_nvmap,
+				   data->win[i].handle);
+		}
+	}
+	kfree(data);
+	return err;
+}
+
+
+/* Overlay functions */
+static bool tegra_overlay_get(struct overlay_client *client, int idx)
+{
+	unsigned long flags;
+	struct tegra_overlay_info *dev = client->dev;
+	bool ret = false;
+
+	if (idx < 0 || idx > dev->dc->n_windows)
+		return ret;
+
+	spin_lock_irqsave(&dev->overlays_lock, flags);
+	if (dev->overlays[idx].owner == NULL) {
+		dev->overlays[idx].owner = client;
+		ret = true;
+	}
+	spin_unlock_irqrestore(&dev->overlays_lock, flags);
+
+	return ret;
+}
+
+static void tegra_overlay_put_unlocked(struct overlay_client *client, int idx)
+{
+	struct tegra_overlay_flip_args flip_args;
+	struct tegra_overlay_info *dev = client->dev;
+
+	if (idx < 0 || idx > dev->dc->n_windows)
+		return;
+
+	if (dev->overlays[idx].owner != client)
+		return;
+
+	dev->overlays[idx].owner = NULL;
+
+	flip_args.win[0].index = idx;
+	flip_args.win[0].buff_id = 0;
+	flip_args.win[1].index = -1;
+	flip_args.win[2].index = -1;
+
+	tegra_overlay_flip(dev, &flip_args, NULL);
+}
+
+static void tegra_overlay_put(struct overlay_client *client, int idx)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&client->dev->overlays_lock, flags);
+	tegra_overlay_put_unlocked(client, idx);
+	spin_unlock_irqrestore(&client->dev->overlays_lock, flags);
+}
+
+/* Ioctl implementations */
+static int tegra_overlay_ioctl_open(struct overlay_client *client,
+				    void __user *arg)
+{
+	int idx = -1;
+
+	if (copy_from_user(&idx, arg, sizeof(idx)))
+		return -EFAULT;
+
+	if (!tegra_overlay_get(client, idx))
+		return -EBUSY;
+
+	if (copy_to_user(arg, &idx, sizeof(idx))) {
+		tegra_overlay_put(client, idx);
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+static int tegra_overlay_ioctl_close(struct overlay_client *client,
+				     void __user *arg)
+{
+	int err = 0;
+	int idx;
+	unsigned long flags;
+
+	if (copy_from_user(&idx, arg, sizeof(idx)))
+		return -EFAULT;
+
+	if (idx < 0 || idx > client->dev->dc->n_windows)
+		return -EINVAL;
+
+	spin_lock_irqsave(&client->dev->overlays_lock, flags);
+	if (client->dev->overlays[idx].owner == client)
+		tegra_overlay_put_unlocked(client, idx);
+	else
+		err = -EINVAL;
+	spin_unlock_irqrestore(&client->dev->overlays_lock, flags);
+
+	return err;
+}
+
+static int tegra_overlay_ioctl_flip(struct overlay_client *client,
+				    void __user *arg)
+{
+	int i = 0;
+	int idx = 0;
+	bool found_one = false;
+	struct tegra_overlay_flip_args flip_args;
+
+	if (copy_from_user(&flip_args, arg, sizeof(flip_args)))
+		return -EFAULT;
+
+	for (i = 0; i < TEGRA_FB_FLIP_N_WINDOWS; i++) {
+		idx = flip_args.win[i].index;
+		if (idx == -1) {
+			flip_args.win[i].buff_id = 0;
+			continue;
+		}
+
+		if (idx < 0 || idx > client->dev->dc->n_windows) {
+			dev_err(&client->dev->ndev->dev,
+				"Flipping an invalid overlay! %d\n", idx);
+			flip_args.win[i].index = -1;
+			flip_args.win[i].buff_id = 0;
+			continue;
+		}
+
+		if (client->dev->overlays[idx].owner != client) {
+			dev_err(&client->dev->ndev->dev,
+				"Flipping a non-owned overlay! %d\n", idx);
+			flip_args.win[i].index = -1;
+			flip_args.win[i].buff_id = 0;
+			continue;
+		}
+
+		found_one = true;
+	}
+
+	if (!found_one)
+		return -EFAULT;
+
+	tegra_overlay_flip(client->dev, &flip_args, client->user_nvmap);
+
+	if (copy_to_user(arg, &flip_args, sizeof(flip_args)))
+		return -EFAULT;
+
+	return 0;
+}
+
+static int tegra_overlay_ioctl_set_nvmap_fd(struct overlay_client *client,
+					    void __user *arg)
+{
+	int fd;
+	struct nvmap_client *nvmap = NULL;
+
+	if (copy_from_user(&fd, arg, sizeof(fd)))
+		return -EFAULT;
+
+	if (fd < 0)
+		return -EINVAL;
+
+	nvmap = nvmap_client_get_file(fd);
+	if (IS_ERR(nvmap))
+		return PTR_ERR(nvmap);
+
+	if (client->user_nvmap)
+		nvmap_client_put(client->user_nvmap);
+
+	client->user_nvmap = nvmap;
+
+	return 0;
+}
+
+/* File operations */
+static int tegra_overlay_open(struct inode *inode, struct file *filp)
+{
+	struct miscdevice *miscdev = filp->private_data;
+	struct tegra_overlay_info *dev = container_of(miscdev,
+						      struct tegra_overlay_info,
+						      dev);
+	struct overlay_client *priv;
+	unsigned long flags;
+	int ret;
+
+	ret = nonseekable_open(inode, filp);
+	if (unlikely(ret))
+		return ret;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = dev;
+
+	get_task_struct(current);
+	priv->task = current;
+
+	spin_lock_irqsave(&dev->clients_lock, flags);
+	list_add(&priv->list, &dev->clients);
+	spin_unlock_irqrestore(&dev->clients_lock, flags);
+
+	filp->private_data = priv;
+	return 0;
+}
+
+static int tegra_overlay_release(struct inode *inode, struct file *filp)
+{
+	struct overlay_client *client = filp->private_data;
+	unsigned long flags;
+	int i;
+
+	spin_lock_irqsave(&client->dev->overlays_lock, flags);
+	for (i = 0; i < client->dev->dc->n_windows; i++)
+		if (client->dev->overlays[i].owner == client)
+			tegra_overlay_put_unlocked(client, i);
+	spin_unlock_irqrestore(&client->dev->overlays_lock, flags);
+
+	spin_lock_irqsave(&client->dev->clients_lock, flags);
+	list_del(&client->list);
+	spin_unlock_irqrestore(&client->dev->clients_lock, flags);
+
+	put_task_struct(client->task);
+
+	kfree(client);
+	return 0;
+}
+
+static long tegra_overlay_ioctl(struct file *filp, unsigned int cmd,
+				unsigned long arg)
+{
+	struct overlay_client *client = filp->private_data;
+	int err = 0;
+	void __user *uarg = (void __user *)arg;
+
+	if (_IOC_TYPE(cmd) != TEGRA_OVERLAY_IOCTL_MAGIC)
+		return -ENOTTY;
+
+	if (_IOC_NR(cmd) < TEGRA_OVERLAY_IOCTL_MIN_NR)
+		return -ENOTTY;
+
+	if (_IOC_NR(cmd) > TEGRA_OVERLAY_IOCTL_MAX_NR)
+		return -ENOTTY;
+
+	if (_IOC_DIR(cmd) & _IOC_READ)
+		err = !access_ok(VERIFY_WRITE, uarg, _IOC_SIZE(cmd));
+	if (_IOC_DIR(cmd) & _IOC_WRITE)
+		err = !access_ok(VERIFY_READ, uarg, _IOC_SIZE(cmd));
+
+	if (err)
+		return -EFAULT;
+
+	switch (cmd) {
+	case TEGRA_OVERLAY_IOCTL_OPEN_WINDOW:
+		err = tegra_overlay_ioctl_open(client, uarg);
+		break;
+	case TEGRA_OVERLAY_IOCTL_CLOSE_WINDOW:
+		err = tegra_overlay_ioctl_close(client, uarg);
+		break;
+	case TEGRA_OVERLAY_IOCTL_FLIP:
+		err = tegra_overlay_ioctl_flip(client, uarg);
+		break;
+	case TEGRA_OVERLAY_IOCTL_SET_NVMAP_FD:
+		err = tegra_overlay_ioctl_set_nvmap_fd(client, uarg);
+		break;
+	default:
+		return -ENOTTY;
+	}
+	return err;
+}
+
+static const struct file_operations overlay_fops = {
+	.owner		= THIS_MODULE,
+	.open		= tegra_overlay_open,
+	.release	= tegra_overlay_release,
+	.unlocked_ioctl = tegra_overlay_ioctl,
+};
+
+/* Registration */
+struct tegra_overlay_info *tegra_overlay_register(struct nvhost_device *ndev,
+						  struct tegra_dc *dc)
+{
+	struct tegra_overlay_info *dev;
+	int e;
+
+	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+	if (!dev) {
+		dev_err(&ndev->dev, "out of memory for device\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	snprintf(dev->name, sizeof(dev->name), "tegra_dc%u", ndev->id);
+
+	dev->ndev = ndev;
+	dev->dev.minor = MISC_DYNAMIC_MINOR;
+	dev->dev.name = dev->name;
+	dev->dev.fops = &overlay_fops;
+	dev->dev.parent = &ndev->dev;
+
+	spin_lock_init(&dev->clients_lock);
+	INIT_LIST_HEAD(&dev->clients);
+
+	spin_lock_init(&dev->overlays_lock);
+
+	e = misc_register(&dev->dev);
+	if (e) {
+		dev_err(&ndev->dev, "unable to register miscdevice %s\n",
+			dev->dev.name);
+		goto fail;
+	}
+
+	dev->overlay_nvmap = nvmap_create_client(nvmap_dev, "overlay");
+	if (!dev->overlay_nvmap) {
+		dev_err(&ndev->dev, "couldn't create nvmap client\n");
+		e = -ENOMEM;
+		goto err_free;
+	}
+
+	dev->flip_wq = create_singlethread_workqueue(dev_name(&ndev->dev));
+	if (!dev->flip_wq) {
+		dev_err(&ndev->dev, "couldn't create flip work-queue\n");
+		e = -ENOMEM;
+		goto err_delete_wq;
+	}
+
+	dev->dc = dc;
+
+	dev_info(&ndev->dev, "registered overlay\n");
+
+	return dev;
+
+err_delete_wq:
+err_free:
+fail:
+	if (dev->dev.minor != MISC_DYNAMIC_MINOR)
+		misc_deregister(&dev->dev);
+	kfree(dev);
+	return ERR_PTR(e);
+}
+
+void tegra_overlay_unregister(struct tegra_overlay_info *info)
+{
+	misc_deregister(&info->dev);
+
+	kfree(info);
+}
+
+
diff --git a/drivers/video/tegra/dc/overlay.h b/drivers/video/tegra/dc/overlay.h
new file mode 100644
index 000000000000..a3469813b1bf
--- /dev/null
+++ b/drivers/video/tegra/dc/overlay.h
@@ -0,0 +1,38 @@
+/*
+ * drivers/video/tegra/dc/overlay.h
+ *
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __DRIVERS_VIDEO_TEGRA_OVERLAY_H
+#define __DRIVERS_VIDEO_TEGRA_OVERLAY_H
+
+struct tegra_overlay_info;
+
+#ifdef CONFIG_TEGRA_OVERLAY
+struct tegra_overlay_info *tegra_overlay_register(struct nvhost_device *ndev,
+						  struct tegra_dc *dc);
+void tegra_overlay_unregister(struct tegra_overlay_info *overlay_info);
+#else
+static inline struct tegra_overlay_info *tegra_overlay_register(struct nvhost_device *ndev,
+								struct tegra_dc *dc)
+{
+	return NULL;
+}
+
+static inline void tegra_overlay_unregister(struct tegra_overlay_info *overlay_info)
+{
+}
+#endif
+
+#endif
diff --git a/drivers/video/tegra/fb.c b/drivers/video/tegra/fb.c
index 1f0b967acd89..01b3d756b930 100644
--- a/drivers/video/tegra/fb.c
+++ b/drivers/video/tegra/fb.c
@@ -193,6 +193,21 @@ static int tegra_fb_set_par(struct fb_info *info)
 		mode.v_active = info->mode->yres;
 		mode.h_front_porch = info->mode->right_margin;
 		mode.v_front_porch = info->mode->lower_margin;
+		/*
+		 * only enable stereo if the mode supports it and
+		 * client requests it
+		 */
+		mode.stereo_mode = !!(var->vmode & info->mode->vmode &
+					FB_VMODE_STEREO_FRAME_PACK);
+
+		if (mode.stereo_mode) {
+			mode.pclk *= 2;
+			/* total v_active = yres*2 + activespace */
+			mode.v_active = info->mode->yres*2 +
+					info->mode->vsync_len +
+					info->mode->upper_margin +
+					info->mode->lower_margin;
+		}
 
 		mode.flags = 0;
 
@@ -376,12 +391,16 @@ static int tegra_fb_set_windowattr(struct tegra_fb_info *tegra_fb,
 				   struct tegra_dc_win *win,
 				   const struct tegra_fb_flip_win *flip_win)
 {
+	int xres, yres;
 	if (flip_win->handle == NULL) {
 		win->flags = 0;
 		win->cur_handle = NULL;
 		return 0;
 	}
 
+	xres = tegra_fb->info->var.xres;
+	yres = tegra_fb->info->var.yres;
+
 	win->flags = TEGRA_WIN_FLAG_ENABLED;
 	if (flip_win->attr.blend == TEGRA_FB_WIN_BLEND_PREMULT)
 		win->flags |= TEGRA_WIN_FLAG_BLEND_PREMULT;
@@ -396,6 +415,15 @@ static int tegra_fb_set_windowattr(struct tegra_fb_info *tegra_fb,
 	win->out_y = flip_win->attr.out_y;
 	win->out_w = flip_win->attr.out_w;
 	win->out_h = flip_win->attr.out_h;
+
+	if (((win->out_x + win->out_w) > xres) && (win->out_x < xres)) {
+		win->out_w = xres - win->out_x;
+	}
+
+	if (((win->out_y + win->out_h) > yres) && (win->out_y < yres)) {
+		win->out_h = yres - win->out_y;
+	}
+
 	win->z = flip_win->attr.z;
 	win->cur_handle = flip_win->handle;
 
@@ -579,6 +607,17 @@ static int tegra_fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long
 					 &var, sizeof(var)))
 				return -EFAULT;
 			i++;
+
+			if (var.vmode & FB_VMODE_STEREO_MASK) {
+				if (i >= modedb.modedb_len)
+					break;
+				var.vmode &= ~FB_VMODE_STEREO_MASK;
+				if (copy_to_user(
+					(void __user *)&modedb.modedb[i],
+					 &var, sizeof(var)))
+					return -EFAULT;
+				i++;
+			}
 		}
 		modedb.modedb_len = i;
 
diff --git a/drivers/video/tegra/host/dev.c b/drivers/video/tegra/host/dev.c
index 20a4eda0fb53..8b577cc9045f 100644
--- a/drivers/video/tegra/host/dev.c
+++ b/drivers/video/tegra/host/dev.c
@@ -210,7 +210,8 @@ static ssize_t nvhost_channelwrite(struct file *filp, const char __user *buf,
 }
 
 static int nvhost_ioctl_channel_flush(struct nvhost_channel_userctx *ctx,
-                                      struct nvhost_get_param_args *args)
+                                      struct nvhost_get_param_args *args,
+                                      int null_kickoff)
 {
 	struct nvhost_cpuinterrupt ctxsw;
 	int gather_idx = 2;
@@ -218,6 +219,7 @@ static int nvhost_ioctl_channel_flush(struct nvhost_channel_userctx *ctx,
 	u32 syncval;
 	int num_unpin;
 	int err;
+	int nulled_incrs = null_kickoff ? ctx->syncpt_incrs : 0;
 
 	if (ctx->relocs_pending || ctx->cmdbufs_pending) {
 		reset_submit(ctx);
@@ -300,9 +302,10 @@ static int nvhost_ioctl_channel_flush(struct nvhost_channel_userctx *ctx,
 	ctxsw.syncpt_val += syncval - ctx->syncpt_incrs;
 
 	nvhost_channel_submit(ctx->ch, ctx->nvmap, &ctx->gathers[gather_idx],
-			      ctx->num_gathers - gather_idx, &ctxsw, num_intrs,
+			      (null_kickoff ? 2 : ctx->num_gathers) - gather_idx, &ctxsw, num_intrs,
 			      ctx->unpinarray, num_unpin,
-			      ctx->syncpt_id, syncval);
+			      ctx->syncpt_id, syncval,
+			      nulled_incrs);
 
 	/* schedule a submit complete interrupt */
 	nvhost_intr_add_action(&ctx->ch->dev->intr, ctx->syncpt_id, syncval,
@@ -334,7 +337,10 @@ static long nvhost_channelctl(struct file *filp,
 
 	switch (cmd) {
 	case NVHOST_IOCTL_CHANNEL_FLUSH:
-		err = nvhost_ioctl_channel_flush(priv, (void *)buf);
+		err = nvhost_ioctl_channel_flush(priv, (void *)buf, 0);
+		break;
+	case NVHOST_IOCTL_CHANNEL_NULL_KICKOFF:
+		err = nvhost_ioctl_channel_flush(priv, (void *)buf, 1);
 		break;
 	case NVHOST_IOCTL_CHANNEL_GET_SYNCPOINTS:
 		((struct nvhost_get_param_args *)buf)->value =
@@ -741,7 +747,7 @@ static int nvhost_suspend(struct platform_device *pdev, pm_message_t state)
 {
 	struct nvhost_master *host = platform_get_drvdata(pdev);
 	dev_info(&pdev->dev, "suspending\n");
-	nvhost_module_suspend(&host->mod);
+	nvhost_module_suspend(&host->mod, true);
 	clk_enable(host->mod.clk[0]);
 	nvhost_syncpt_save(&host->syncpt);
 	clk_disable(host->mod.clk[0]);
diff --git a/drivers/video/tegra/host/nvhost_acm.c b/drivers/video/tegra/host/nvhost_acm.c
index ef8f1ea2c13a..c2152287506f 100644
--- a/drivers/video/tegra/host/nvhost_acm.c
+++ b/drivers/video/tegra/host/nvhost_acm.c
@@ -20,7 +20,7 @@
  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  */
 
-#include "nvhost_acm.h"
+#include "dev.h"
 #include <linux/string.h>
 #include <linux/sched.h>
 #include <linux/err.h>
@@ -194,22 +194,55 @@ static int is_module_idle(struct nvhost_module *mod)
 	return (count == 0);
 }
 
-void nvhost_module_suspend(struct nvhost_module *mod)
+static void debug_not_idle(struct nvhost_module *mod)
+{
+	int i;
+	bool lock_released = true;
+	struct nvhost_master *dev = container_of(mod, struct nvhost_master, mod);
+
+	for (i = 0; i < NVHOST_NUMCHANNELS; i++) {
+		struct nvhost_module *m = &dev->channels[i].mod;
+		if (m->name)
+			printk("tegra_grhost: %s: refcnt %d\n",
+				m->name, atomic_read(&m->refcount));
+	}
+
+	for (i = 0; i < NV_HOST1X_SYNC_MLOCK_NUM; i++) {
+		int c = atomic_read(&dev->cpuaccess.lock_counts[i]);
+		if (c) {
+			printk("tegra_grhost: lock id %d: refcnt %d\n", i, c);
+			lock_released = false;
+		}
+	}
+	if (lock_released)
+		printk("tegra_grhost: all locks released\n");
+}
+
+void nvhost_module_suspend(struct nvhost_module *mod, bool system_suspend)
 {
 	int ret;
 
+	if (system_suspend && (!is_module_idle(mod)))
+		debug_not_idle(mod);
+
 	ret = wait_event_timeout(mod->idle, is_module_idle(mod),
 			   ACM_TIMEOUT + msecs_to_jiffies(500));
 	if (ret == 0)
 		nvhost_debug_dump();
+
+	if (system_suspend)
+		printk("tegra_grhost: entered idle\n");
+
 	flush_delayed_work(&mod->powerdown);
+	if (system_suspend)
+		printk("tegra_grhost: flushed delayed work\n");
 	BUG_ON(mod->powered);
 }
 
 void nvhost_module_deinit(struct nvhost_module *mod)
 {
 	int i;
-	nvhost_module_suspend(mod);
+	nvhost_module_suspend(mod, false);
 	for (i = 0; i < mod->num_clks; i++)
 		clk_put(mod->clk[i]);
 }
diff --git a/drivers/video/tegra/host/nvhost_acm.h b/drivers/video/tegra/host/nvhost_acm.h
index 41f3f31dc12a..f7e28af8e9cb 100644
--- a/drivers/video/tegra/host/nvhost_acm.h
+++ b/drivers/video/tegra/host/nvhost_acm.h
@@ -57,7 +57,7 @@ int nvhost_module_init(struct nvhost_module *mod, const char *name,
 		nvhost_modulef func, struct nvhost_module *parent,
 		struct device *dev);
 void nvhost_module_deinit(struct nvhost_module *mod);
-void nvhost_module_suspend(struct nvhost_module *mod);
+void nvhost_module_suspend(struct nvhost_module *mod, bool system_suspend);
 
 void nvhost_module_busy(struct nvhost_module *mod);
 void nvhost_module_idle_mult(struct nvhost_module *mod, int refs);
diff --git a/drivers/video/tegra/host/nvhost_channel.c b/drivers/video/tegra/host/nvhost_channel.c
index 40b67181c33d..70fb173d7f41 100644
--- a/drivers/video/tegra/host/nvhost_channel.c
+++ b/drivers/video/tegra/host/nvhost_channel.c
@@ -168,11 +168,12 @@ void nvhost_channel_suspend(struct nvhost_channel *ch)
 }
 
 void nvhost_channel_submit(struct nvhost_channel *ch,
-                           struct nvmap_client *user_nvmap,
-                           struct nvhost_op_pair *ops, int num_pairs,
-                           struct nvhost_cpuinterrupt *intrs, int num_intrs,
-                           struct nvmap_handle **unpins, int num_unpins,
-                           u32 syncpt_id, u32 syncpt_val)
+			   struct nvmap_client *user_nvmap,
+			   struct nvhost_op_pair *ops, int num_pairs,
+			   struct nvhost_cpuinterrupt *intrs, int num_intrs,
+			   struct nvmap_handle **unpins, int num_unpins,
+			   u32 syncpt_id, u32 syncpt_val,
+			   int num_nulled_incrs)
 {
 	int i;
 	struct nvhost_op_pair* p;
@@ -190,6 +191,31 @@ void nvhost_channel_submit(struct nvhost_channel *ch,
 	for (i = 0, p = ops; i < num_pairs; i++, p++)
 		nvhost_cdma_push(&ch->cdma, p->op1, p->op2);
 
+	/* extra work to do for null kickoff */
+	if (num_nulled_incrs) {
+		u32 incr;
+		u32 op_incr;
+
+		/* TODO ideally we'd also perform host waits here */
+
+		/* push increments that correspond to nulled out commands */
+		op_incr = nvhost_opcode_imm(0, 0x100 | syncpt_id);
+		for (incr = 0; incr < (num_nulled_incrs >> 1); incr++)
+			nvhost_cdma_push(&ch->cdma, op_incr, op_incr);
+		if (num_nulled_incrs & 1)
+			nvhost_cdma_push(&ch->cdma, op_incr, NVHOST_OPCODE_NOOP);
+
+		/* for 3d, waitbase needs to be incremented after each submit */
+		if (ch->desc->class == NV_GRAPHICS_3D_CLASS_ID) {
+			u32 op1 = nvhost_opcode_setclass(NV_HOST1X_CLASS_ID,
+					NV_CLASS_HOST_INCR_SYNCPT_BASE, 1);
+			u32 op2 = nvhost_class_host_incr_syncpt_base(NVWAITBASE_3D,
+					num_nulled_incrs);
+
+			nvhost_cdma_push(&ch->cdma, op1, op2);
+		}
+	}
+
 	/* end CDMA submit & stash pinned hMems into sync queue for later cleanup */
 	nvhost_cdma_end(user_nvmap, &ch->cdma, syncpt_id, syncpt_val,
                         unpins, num_unpins);
@@ -227,8 +253,8 @@ static void power_3d(struct nvhost_module *mod, enum nvhost_power_action action)
 			ch->cur_ctx = NULL;
 
 			nvhost_channel_submit(ch, ch->dev->nvmap,
-					      &save, 1, &ctxsw, 1, NULL, 0,
-					      NVSYNCPT_3D, syncval);
+						&save, 1, &ctxsw, 1, NULL, 0,
+						NVSYNCPT_3D, syncval, 0);
 
 			nvhost_intr_add_action(&ch->dev->intr, NVSYNCPT_3D,
 					       syncval,
diff --git a/drivers/video/tegra/host/nvhost_channel.h b/drivers/video/tegra/host/nvhost_channel.h
index c62d7397a192..59ba06543a48 100644
--- a/drivers/video/tegra/host/nvhost_channel.h
+++ b/drivers/video/tegra/host/nvhost_channel.h
@@ -80,7 +80,8 @@ void nvhost_channel_submit(struct nvhost_channel *ch,
 			   struct nvhost_op_pair *ops, int num_pairs,
 			   struct nvhost_cpuinterrupt *intrs, int num_intrs,
 			   struct nvmap_handle **unpins, int num_unpins,
-			   u32 syncpt_id, u32 syncpt_val);
+			   u32 syncpt_id, u32 syncpt_val,
+			   int num_nulled_incrs);
 
 struct nvhost_channel *nvhost_getchannel(struct nvhost_channel *ch);
 void nvhost_putchannel(struct nvhost_channel *ch, struct nvhost_hwctx *ctx);
diff --git a/drivers/video/tegra/host/nvhost_cpuaccess.c b/drivers/video/tegra/host/nvhost_cpuaccess.c
index 9114dad97783..4a5c34d593fc 100644
--- a/drivers/video/tegra/host/nvhost_cpuaccess.c
+++ b/drivers/video/tegra/host/nvhost_cpuaccess.c
@@ -71,6 +71,7 @@ int nvhost_mutex_try_lock(struct nvhost_cpuaccess *ctx, unsigned int idx)
 		nvhost_module_idle(&dev->mod);
 		return -ERESTARTSYS;
 	}
+	atomic_inc(&ctx->lock_counts[idx]);
 	return 0;
 }
 
@@ -80,6 +81,7 @@ void nvhost_mutex_unlock(struct nvhost_cpuaccess *ctx, unsigned int idx)
 	void __iomem *sync_regs = dev->sync_aperture;
 	writel(0, sync_regs + (HOST1X_SYNC_MLOCK_0 + idx * 4));
 	nvhost_module_idle(&dev->mod);
+	atomic_dec(&ctx->lock_counts[idx]);
 }
 
 void nvhost_read_module_regs(struct nvhost_cpuaccess *ctx, u32 module,
diff --git a/drivers/video/tegra/host/nvhost_cpuaccess.h b/drivers/video/tegra/host/nvhost_cpuaccess.h
index d7d6c99cd416..98ea1e1e1f8f 100644
--- a/drivers/video/tegra/host/nvhost_cpuaccess.h
+++ b/drivers/video/tegra/host/nvhost_cpuaccess.h
@@ -45,6 +45,7 @@ enum nvhost_module_id {
 struct nvhost_cpuaccess {
 	struct resource *reg_mem[NVHOST_MODULE_NUM];
 	void __iomem *regs[NVHOST_MODULE_NUM];
+	atomic_t lock_counts[NV_HOST1X_SYNC_MLOCK_NUM];
 };
 
 int nvhost_cpuaccess_init(struct nvhost_cpuaccess *ctx,
diff --git a/drivers/video/tegra/host/nvhost_hardware.h b/drivers/video/tegra/host/nvhost_hardware.h
index f69f467dd64e..a7663489727e 100644
--- a/drivers/video/tegra/host/nvhost_hardware.h
+++ b/drivers/video/tegra/host/nvhost_hardware.h
@@ -38,7 +38,7 @@ enum {
 #define NV_HOST1X_CHANNELS 8
 #define NV_HOST1X_CHANNEL0_BASE 0
 #define NV_HOST1X_CHANNEL_MAP_SIZE_BYTES 16384
-
+#define NV_HOST1X_SYNC_MLOCK_NUM 16
 
 #define HOST1X_CHANNEL_FIFOSTAT		0x00
 #define HOST1X_CHANNEL_INDDATA		0x0c
diff --git a/drivers/video/tegra/host/nvhost_intr.c b/drivers/video/tegra/host/nvhost_intr.c
index 007aaed9909f..51387ee62f8e 100644
--- a/drivers/video/tegra/host/nvhost_intr.c
+++ b/drivers/video/tegra/host/nvhost_intr.c
@@ -446,7 +446,7 @@ void nvhost_intr_configure (struct nvhost_intr *intr, u32 hz)
 {
 	void __iomem *sync_regs = intr_to_dev(intr)->sync_aperture;
 
-	// write microsecond clock register
+	/* write microsecond clock register */
 	writel((hz + 1000000 - 1)/1000000, sync_regs + HOST1X_SYNC_USEC_CLK);
 
 	/* disable the ip_busy_timeout. this prevents write drops, etc.
diff --git a/drivers/video/tegra/nvmap/nvmap_ioctl.c b/drivers/video/tegra/nvmap/nvmap_ioctl.c
index b943065a44c0..5e1392e56567 100644..100755
--- a/drivers/video/tegra/nvmap/nvmap_ioctl.c
+++ b/drivers/video/tegra/nvmap/nvmap_ioctl.c
@@ -143,6 +143,16 @@ int nvmap_ioctl_getid(struct file *filp, void __user *arg)
 
 	h = nvmap_get_handle_id(client, op.handle);
 
+#ifdef CONFIG_NVMAP_SEARCH_GLOBAL_HANDLES
+	/*
+	 * Check for device-wide global handles. This may be needed in broken
+	 * memory sharing scenarios when handles are passed from client to
+	 * client instead of the memory IDs.
+	 */
+	if (!h)
+		h = nvmap_validate_get(client, op.handle);
+#endif
+
 	if (!h)
 		return -EPERM;
 
@@ -613,6 +623,9 @@ static ssize_t rw_handle(struct nvmap_client *client, struct nvmap_handle *h,
 			ret = -EFAULT;
 			break;
 		}
+		if(is_read)
+			cache_maint(client, h, h_offs,
+				h_offs + elem_size, NVMAP_CACHE_OP_INV);
 
 		ret = rw_handle_page(h, is_read, h_offs, sys_addr,
 				     elem_size, (unsigned long)addr, *pte);
@@ -620,6 +633,10 @@ static ssize_t rw_handle(struct nvmap_client *client, struct nvmap_handle *h,
 		if (ret)
 			break;
 
+		if(!is_read)
+			cache_maint(client, h, h_offs,
+				h_offs + elem_size, NVMAP_CACHE_OP_WB);
+
 		copied += elem_size;
 		sys_addr += sys_stride;
 		h_offs += h_stride;
diff --git a/include/linux/earlysuspend.h b/include/linux/earlysuspend.h
index 8343b817af31..8343b817af31 100755..100644
--- a/include/linux/earlysuspend.h
+++ b/include/linux/earlysuspend.h
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 8b1f0a982bdb..3e816a73b448 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -225,6 +225,15 @@ struct fb_bitfield {
 #define FB_VMODE_CONUPDATE	512	/* don't update x/yoffset	*/
 
 /*
+ * Stereo modes
+ */
+#define FB_VMODE_STEREO_NONE        0x00000000  /* not stereo */
+#define FB_VMODE_STEREO_FRAME_PACK  0x01000000  /* frame packing */
+#define FB_VMODE_STEREO_TOP_BOTTOM  0x02000000  /* top-bottom */
+#define FB_VMODE_STEREO_LEFT_RIGHT  0x04000000  /* left-right */
+#define FB_VMODE_STEREO_MASK        0xFF000000
+
+/*
  * Display rotation support
  */
 #define FB_ROTATE_UR      0
diff --git a/include/linux/gpio_keys.h b/include/linux/gpio_keys.h
index ce73a30113b4..89dbe27149be 100644
--- a/include/linux/gpio_keys.h
+++ b/include/linux/gpio_keys.h
@@ -19,6 +19,7 @@ struct gpio_keys_platform_data {
 	unsigned int rep:1;		/* enable input subsystem auto repeat */
 	int (*enable)(struct device *dev);
 	void (*disable)(struct device *dev);
+	int (*wakeup_key)(void);
 };
 
 #endif
diff --git a/include/linux/gpio_scrollwheel.h b/include/linux/gpio_scrollwheel.h
new file mode 100644
index 000000000000..33d17a0199ea
--- /dev/null
+++ b/include/linux/gpio_scrollwheel.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _GPIO_SCROLLWHEEL_H
+#define _GPIO_SCROLLWHEEL_H
+
+#define GPIO_SCROLLWHEEL_PIN_ONOFF	0
+#define GPIO_SCROLLWHEEL_PIN_PRESS	1
+#define GPIO_SCROLLWHEEL_PIN_ROT1	2
+#define GPIO_SCROLLWHEEL_PIN_ROT2	3
+#define GPIO_SCROLLWHEEL_PIN_MAX	4
+
+struct gpio_scrollwheel_button {
+	/* Configuration parameters */
+	int pinaction;		/* GPIO_SCROLLWHEEL_PIN_* */
+	int gpio;
+	char *desc;
+	int active_low;
+	int debounce_interval;	/* debounce ticks interval in msecs */
+};
+
+struct gpio_scrollwheel_platform_data {
+	struct gpio_scrollwheel_button *buttons;
+	int nbuttons;
+	unsigned int rep:1;	/* enable input subsystem auto repeat */
+	int (*enable)(struct device *dev);
+	void (*disable)(struct device *dev);
+};
+
+#endif
+
diff --git a/include/linux/i2c-tegra.h b/include/linux/i2c-tegra.h
index 6123502b8ddd..f92fe26c7535 100644
--- a/include/linux/i2c-tegra.h
+++ b/include/linux/i2c-tegra.h
@@ -29,6 +29,8 @@ struct tegra_i2c_platform_data {
 	int bus_mux_len[TEGRA_I2C_MAX_BUS];
 	unsigned long bus_clk_rate[TEGRA_I2C_MAX_BUS];
 	bool is_dvc;
+	int retries;
+	int timeout;	/* in jiffies */
 };
 
 #endif /* _LINUX_I2C_TEGRA_H */
diff --git a/include/linux/i2c/atmel_maxtouch.h b/include/linux/i2c/atmel_maxtouch.h
new file mode 100755
index 000000000000..d827909ecbbd
--- /dev/null
+++ b/include/linux/i2c/atmel_maxtouch.h
@@ -0,0 +1,301 @@
+/*
+ *  Atmel maXTouch header file
+ *
+ *  Copyright (c) 2010 Atmel Corporation
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 or 3 as
+ *  published by the Free Software Foundation.
+ *  See the file "COPYING" in the main directory of this archive
+ *  for more details.
+ *
+ */
+
+#define	MXT224_I2C_ADDR1				0x4A
+#define	MXT224_I2C_ADDR2				0x4B
+#define	MXT1386_I2C_ADDR1				0x4C
+#define	MXT1386_I2C_ADDR2				0x4D
+#define	MXT1386_I2C_ADDR3				0x5A
+#define	MXT1386_I2C_ADDR4				0x5B
+
+/*
+ * Select this address from above depending on what maXTouch
+ * chip you have and how it's address pins are configured;
+ * see datasheet.
+ */
+
+#define MXT_I2C_ADDRESS                                 MXT1386_I2C_ADDR3
+
+#define MXT_BL_ADDRESS                                  0x25
+
+#define	MXT224_FAMILYID				        0x80
+#define MXT1386_FAMILYID                                0xA0
+
+#define	MXT224_CAL_VARIANTID				0x01
+#define MXT224_UNCAL_VARIANTID                          0x00
+#define MXT1386_CAL_VARIANTID                           0x00
+
+#define MXT_MAX_REPORTED_WIDTH                          255
+#define MXT_MAX_REPORTED_PRESSURE                       255
+#define MXT_MAX_TOUCH_SIZE                              255
+#define MXT_MAX_NUM_TOUCHES                             10
+
+/* Fixed addresses inside maXTouch device */
+#define	MXT_ADDR_INFO_BLOCK				0
+#define	MXT_ADDR_OBJECT_TABLE				7
+#define MXT_ID_BLOCK_SIZE                               7
+#define	MXT_OBJECT_TABLE_ELEMENT_SIZE			6
+
+/* Object types */
+#define	MXT_DEBUG_DELTAS_T2				2
+#define	MXT_DEBUG_REFERENCES_T3				3
+#define	MXT_GEN_MESSAGEPROCESSOR_T5			5
+#define	MXT_GEN_COMMANDPROCESSOR_T6			6
+#define	MXT_GEN_POWERCONFIG_T7				7
+#define	MXT_GEN_ACQUIRECONFIG_T8			8
+#define	MXT_TOUCH_MULTITOUCHSCREEN_T9			9
+#define MXT_TOUCH_SINGLETOUCHSCREEN_T10                 10
+#define MXT_TOUCH_XSLIDER_T11                           11
+#define MXT_TOUCH_YSLIDER_T12                           12
+#define MXT_TOUCH_XWHEEL_T13                            13
+#define MXT_TOUCH_YWHEEL_T14                            14
+#define	MXT_TOUCH_KEYARRAY_T15				15
+#define	MXT_SPT_GPIOPWM_T19				19
+#define	MXT_PROCI_GRIPFACESUPPRESSION_T20		20
+#define	MXT_PROCG_NOISESUPPRESSION_T22			22
+#define	MXT_TOUCH_PROXIMITY_T23				23
+#define	MXT_PROCI_ONETOUCHGESTUREPROCESSOR_T24		24
+#define	MXT_SPT_SELFTEST_T25				25
+#define MXT_DEBUG_CTERANGE_T26				26
+#define	MXT_PROCI_TWOTOUCHGESTUREPROCESSOR_T27		27
+#define	MXT_SPT_CTECONFIG_T28				28
+#define	MXT_TOUCH_KEYSET_T31				31
+#define	MXT_TOUCH_XSLIDERSET_T32			32
+#define	MXT_DEBUG_DIAGNOSTIC_T37			37
+#define	MXT_USER_INFO_T38				38
+
+/*
+ * If a message is read from mXT when there's no new messages available,
+ * the report ID of the message will be 0xFF.
+ */
+#define	MXT_END_OF_MESSAGES				0xFF
+
+/* GEN_COMMANDPROCESSOR_T6 Register offsets from T6 base address */
+#define	MXT_ADR_T6_RESET				0x00
+#define	MXT_ADR_T6_BACKUPNV				0x01
+#define	MXT_ADR_T6_CALIBRATE				0x02
+#define	MXT_ADR_T6_REPORTALL				0x03
+#define	MXT_ADR_T6_RESERVED				0x04
+#define	MXT_ADR_T6_DIAGNOSTIC				0x05
+
+/* T6 Debug Diagnostics Commands */
+#define	MXT_CMD_T6_PAGE_UP          0x01
+#define	MXT_CMD_T6_PAGE_DOWN        0x02
+#define	MXT_CMD_T6_DELTAS_MODE      0x10
+#define	MXT_CMD_T6_REFERENCES_MODE  0x11
+#define	MXT_CMD_T6_CTE_MODE         0x31
+
+/* T6 Backup Command */
+#define MXT_CMD_T6_BACKUP           0x55
+
+/* SPT_DEBUG_DIAGNOSTIC_T37 Register offsets from T37 base address */
+#define MXT_ADR_T37_PAGE                                0x01
+#define	MXT_ADR_T37_DATA				0x02
+
+/************************************************************************
+ * MESSAGE OBJECTS ADDRESS FIELDS
+ *
+ ************************************************************************/
+#define MXT_MSG_REPORTID                                0x00
+
+/* MXT_GEN_MESSAGEPROCESSOR_T5 Message address definitions		*/
+#define	MXT_MSG_T5_REPORTID				0x00
+#define	MXT_MSG_T5_MESSAGE				0x01
+#define	MXT_MSG_T5_CHECKSUM				0x08
+
+/* MXT_GEN_COMMANDPROCESSOR_T6 Message address definitions		*/
+#define	MXT_MSG_T6_STATUS				0x01
+#define		MXT_MSGB_T6_COMSERR		0x04
+#define		MXT_MSGB_T6_CFGERR		0x08
+#define		MXT_MSGB_T6_CAL			0x10
+#define		MXT_MSGB_T6_SIGERR		0x20
+#define		MXT_MSGB_T6_OFL			0x40
+#define		MXT_MSGB_T6_RESET		0x80
+/* Three bytes */
+#define	MXT_MSG_T6_CHECKSUM				0x02
+
+/* MXT_GEN_POWERCONFIG_T7 NO Message address definitions		*/
+/* MXT_GEN_ACQUIRECONFIG_T8 Message address definitions			*/
+/* MXT_TOUCH_MULTITOUCHSCREEN_T9 Message address definitions		*/
+
+#define	MXT_MSG_T9_STATUS				0x01
+/* Status bit field */
+#define		MXT_MSGB_T9_SUPPRESS		0x02
+#define		MXT_MSGB_T9_AMP			0x04
+#define		MXT_MSGB_T9_VECTOR		0x08
+#define		MXT_MSGB_T9_MOVE		0x10
+#define		MXT_MSGB_T9_RELEASE		0x20
+#define		MXT_MSGB_T9_PRESS		0x40
+#define		MXT_MSGB_T9_DETECT		0x80
+
+#define	MXT_MSG_T9_XPOSMSB				0x02
+#define	MXT_MSG_T9_YPOSMSB				0x03
+#define	MXT_MSG_T9_XYPOSLSB				0x04
+#define	MXT_MSG_T9_TCHAREA				0x05
+#define	MXT_MSG_T9_TCHAMPLITUDE				0x06
+#define	MXT_MSG_T9_TCHVECTOR				0x07
+
+/* MXT_SPT_GPIOPWM_T19 Message address definitions			*/
+#define	MXT_MSG_T19_STATUS				0x01
+
+/* MXT_PROCI_GRIPFACESUPPRESSION_T20 Message address definitions	*/
+#define	MXT_MSG_T20_STATUS				0x01
+#define		MXT_MSGB_T20_FACE_SUPPRESS	0x01
+/* MXT_PROCG_NOISESUPPRESSION_T22 Message address definitions		*/
+#define	MXT_MSG_T22_STATUS				0x01
+#define		MXT_MSGB_T22_FHCHG		0x01
+#define		MXT_MSGB_T22_GCAFERR		0x04
+#define		MXT_MSGB_T22_FHERR		0x08
+#define	MXT_MSG_T22_GCAFDEPTH				0x02
+
+/* MXT_TOUCH_PROXIMITY_T23 Message address definitions			*/
+#define	MXT_MSG_T23_STATUS				0x01
+#define		MXT_MSGB_T23_FALL		0x20
+#define		MXT_MSGB_T23_RISE		0x40
+#define		MXT_MSGB_T23_DETECT		0x80
+/* 16 bit */
+#define	MXT_MSG_T23_PROXDELTA				0x02
+
+/* MXT_PROCI_ONETOUCHGESTUREPROCESSOR_T24 Message address definitions	*/
+#define	MXT_MSG_T24_STATUS				0x01
+#define	MXT_MSG_T24_XPOSMSB				0x02
+#define	MXT_MSG_T24_YPOSMSB				0x03
+#define	MXT_MSG_T24_XYPOSLSB				0x04
+#define	MXT_MSG_T24_DIR					0x05
+/* 16 bit */
+#define	MXT_MSG_T24_DIST				0x06
+
+/* MXT_SPT_SELFTEST_T25 Message address definitions			*/
+#define	MXT_MSG_T25_STATUS				0x01
+/* 5 Bytes */
+#define		MXT_MSGR_T25_OK			0xFE
+#define		MXT_MSGR_T25_INVALID_TEST	0xFD
+#define		MXT_MSGR_T25_PIN_FAULT		0x11
+#define		MXT_MSGR_T25_SIGNAL_LIMIT_FAULT	0x17
+#define		MXT_MSGR_T25_GAIN_ERROR		0x20
+#define	MXT_MSG_T25_INFO				0x02
+
+/* MXT_PROCI_TWOTOUCHGESTUREPROCESSOR_T27 Message address definitions	*/
+#define	MXT_MSG_T27_STATUS			0x01
+#define		MXT_MSGB_T27_ROTATEDIR		0x10
+#define		MXT_MSGB_T27_PINCH		0x20
+#define		MXT_MSGB_T27_ROTATE		0x40
+#define		MXT_MSGB_T27_STRETCH		0x80
+#define	MXT_MSG_T27_XPOSMSB			0x02
+#define	MXT_MSG_T27_YPOSMSB			0x03
+#define	MXT_MSG_T27_XYPOSLSB			0x04
+#define	MXT_MSG_T27_ANGLE			0x05
+
+/* 16 bit */
+#define	MXT_MSG_T27_SEPARATION				0x06
+
+/* MXT_SPT_CTECONFIG_T28 Message address definitions			*/
+#define	MXT_MSG_T28_STATUS				0x01
+#define	MXT_MSGB_T28_CHKERR		0x01
+
+/* One Touch Events */
+#define	MT_GESTURE_RESERVED				0x00
+#define	MT_GESTURE_PRESS				0x01
+#define	MT_GESTURE_RELEASE				0x02
+#define	MT_GESTURE_TAP					0x03
+#define	MT_GESTURE_DOUBLE_TAP				0x04
+#define	MT_GESTURE_FLICK				0x05
+#define	MT_GESTURE_DRAG					0x06
+#define	MT_GESTURE_SHORT_PRESS				0x07
+#define	MT_GESTURE_LONG_PRESS				0x08
+#define	MT_GESTURE_REPEAT_PRESS				0x09
+#define	MT_GESTURE_TAP_AND_PRESS			0x0a
+#define	MT_GESTURE_THROW				0x0b
+
+/* Bootloader states */
+#define WAITING_BOOTLOAD_COMMAND   0xC0
+#define WAITING_FRAME_DATA         0x80
+#define APP_CRC_FAIL               0x40
+#define FRAME_CRC_CHECK            0x02
+#define FRAME_CRC_PASS             0x04
+#define FRAME_CRC_FAIL             0x03
+
+#define MXT_MAX_FRAME_SIZE         276
+
+/* Debug levels */
+#define NO_DEBUG       0
+#define DEBUG_INFO     1
+#define DEBUG_VERBOSE  2
+#define DEBUG_MESSAGES 5
+#define DEBUG_RAW      8
+#define DEBUG_TRACE   10
+
+/* IOCTL commands */
+#define MXT_SET_ADDRESS     1	/* Sets the internal address pointer */
+#define MXT_RESET           2	/* Resets the device */
+#define MXT_CALIBRATE       3	/* Calibrates the device */
+#define MXT_BACKUP          4	/* Backups the current state of registers to
+				   NVM */
+#define MXT_NONTOUCH_MSG    5	/* Only non-touch messages can be read from
+				   the message buffer
+				   (/dev/maXTouch_messages) */
+#define MXT_ALL_MSG         6	/* All messages can be read from the message
+				   buffer */
+
+/* Message buffer size. This is a ring buffer, and when full, the oldest entry
+   will be overwritten. */
+#define MXT_MESSAGE_BUFFER_SIZE  128
+
+/* Routines for memory access within a 16 bit address space */
+
+static int mxt_read_block(struct i2c_client *client, u16 addr, u16 length,
+			  u8 *value);
+static int mxt_write_byte(struct i2c_client *client, u16 addr, u8 value);
+static int mxt_write_block(struct i2c_client *client, u16 addr, u16 length,
+			   u8 *value);
+
+/* TODO: */
+/* Bootloader specific function prototypes. */
+static int mxt_read_byte_bl(struct i2c_client *client, u8 * value);
+static int mxt_read_block_bl(struct i2c_client *client, u16 length, u8 * value);
+static int mxt_write_byte_bl(struct i2c_client *client, u8 value);
+static int mxt_write_block_bl(struct i2c_client *client, u16 length,
+			      u8 *value);
+
+/**
+ * struct mxt_platform_data - includes platform specific informatio
+ * related to Atmel maXTouch touchscreen controller.
+ *
+ * @numtouch:           Number of simultaneous touches supported
+ * @init_platform_hw(): Initialization function, which can for example
+ *                      trigger a hardware reset by toggling a GPIO pin
+ * @exit_platform_hw(): Function to run when the driver is unloaded.
+ * @valid_interrupt():  Function that checks the validity of the interrupt -
+ *                      function that check the validity of a interrupt (by
+ *                      reading the changeline interrupt pin and checking that
+ *                      it really is low for example).
+ * @max_x:              Reported X range
+ * @max_y:              Reported Y range
+ */
+
+struct mxt_platform_data {
+	u8 numtouch;		/* Number of touches to report  */
+	void (*init_platform_hw) (void);
+	void (*exit_platform_hw) (void);
+	int max_x;		/* The default reported X range   */
+	int max_y;		/* The default reported Y range   */
+	 u8(*valid_interrupt) (void);
+	 u8(*read_chg) (void);
+};
+
+static u8 mxt_valid_interrupt_dummy(void)
+{
+	return 1;
+}
+
+void mxt_hw_reset(void);
diff --git a/include/linux/mfd/max8907c.h b/include/linux/mfd/max8907c.h
new file mode 100644
index 000000000000..d4d62d4a6421
--- /dev/null
+++ b/include/linux/mfd/max8907c.h
@@ -0,0 +1,221 @@
+/* linux/mfd/max8907c.h
+ *
+ * Functions to access MAX8907C power management chip.
+ *
+ * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_MFD_MAX8907C_H
+#define __LINUX_MFD_MAX8907C_H
+
+/* MAX8907C register map */
+#define MAX8907C_REG_SYSENSEL               0x00
+#define MAX8907C_REG_ON_OFF_IRQ1            0x01
+#define MAX8907C_REG_ON_OFF_IRQ1_MASK       0x02
+#define MAX8907C_REG_ON_OFF_STAT            0x03
+#define MAX8907C_REG_SDCTL1                 0x04
+#define MAX8907C_REG_SDSEQCNT1              0x05
+#define MAX8907C_REG_SDV1                   0x06
+#define MAX8907C_REG_SDCTL2                 0x07
+#define MAX8907C_REG_SDSEQCNT2              0x08
+#define MAX8907C_REG_SDV2                   0x09
+#define MAX8907C_REG_SDCTL3                 0x0A
+#define MAX8907C_REG_SDSEQCNT3              0x0B
+#define MAX8907C_REG_SDV3                   0x0C
+#define MAX8907C_REG_ON_OFF_IRQ2            0x0D
+#define MAX8907C_REG_ON_OFF_IRQ2_MASK       0x0E
+#define MAX8907C_REG_RESET_CNFG             0x0F
+#define MAX8907C_REG_LDOCTL16               0x10
+#define MAX8907C_REG_LDOSEQCNT16            0x11
+#define MAX8907C_REG_LDO16VOUT              0x12
+#define MAX8907C_REG_SDBYSEQCNT             0x13
+#define MAX8907C_REG_LDOCTL17               0x14
+#define MAX8907C_REG_LDOSEQCNT17            0x15
+#define MAX8907C_REG_LDO17VOUT              0x16
+#define MAX8907C_REG_LDOCTL1                0x18
+#define MAX8907C_REG_LDOSEQCNT1             0x19
+#define MAX8907C_REG_LDO1VOUT               0x1A
+#define MAX8907C_REG_LDOCTL2                0x1C
+#define MAX8907C_REG_LDOSEQCNT2             0x1D
+#define MAX8907C_REG_LDO2VOUT               0x1E
+#define MAX8907C_REG_LDOCTL3                0x20
+#define MAX8907C_REG_LDOSEQCNT3             0x21
+#define MAX8907C_REG_LDO3VOUT               0x22
+#define MAX8907C_REG_LDOCTL4                0x24
+#define MAX8907C_REG_LDOSEQCNT4             0x25
+#define MAX8907C_REG_LDO4VOUT               0x26
+#define MAX8907C_REG_LDOCTL5                0x28
+#define MAX8907C_REG_LDOSEQCNT5             0x29
+#define MAX8907C_REG_LDO5VOUT               0x2A
+#define MAX8907C_REG_LDOCTL6                0x2C
+#define MAX8907C_REG_LDOSEQCNT6             0x2D
+#define MAX8907C_REG_LDO6VOUT               0x2E
+#define MAX8907C_REG_LDOCTL7                0x30
+#define MAX8907C_REG_LDOSEQCNT7             0x31
+#define MAX8907C_REG_LDO7VOUT               0x32
+#define MAX8907C_REG_LDOCTL8                0x34
+#define MAX8907C_REG_LDOSEQCNT8             0x35
+#define MAX8907C_REG_LDO8VOUT               0x36
+#define MAX8907C_REG_LDOCTL9                0x38
+#define MAX8907C_REG_LDOSEQCNT9             0x39
+#define MAX8907C_REG_LDO9VOUT               0x3A
+#define MAX8907C_REG_LDOCTL10               0x3C
+#define MAX8907C_REG_LDOSEQCNT10            0x3D
+#define MAX8907C_REG_LDO10VOUT              0x3E
+#define MAX8907C_REG_LDOCTL11               0x40
+#define MAX8907C_REG_LDOSEQCNT11            0x41
+#define MAX8907C_REG_LDO11VOUT              0x42
+#define MAX8907C_REG_LDOCTL12               0x44
+#define MAX8907C_REG_LDOSEQCNT12            0x45
+#define MAX8907C_REG_LDO12VOUT              0x46
+#define MAX8907C_REG_LDOCTL13               0x48
+#define MAX8907C_REG_LDOSEQCNT13            0x49
+#define MAX8907C_REG_LDO13VOUT              0x4A
+#define MAX8907C_REG_LDOCTL14               0x4C
+#define MAX8907C_REG_LDOSEQCNT14            0x4D
+#define MAX8907C_REG_LDO14VOUT              0x4E
+#define MAX8907C_REG_LDOCTL15               0x50
+#define MAX8907C_REG_LDOSEQCNT15            0x51
+#define MAX8907C_REG_LDO15VOUT              0x52
+#define MAX8907C_REG_OUT5VEN                0x54
+#define MAX8907C_REG_OUT5VSEQ               0x55
+#define MAX8907C_REG_OUT33VEN               0x58
+#define MAX8907C_REG_OUT33VSEQ              0x59
+#define MAX8907C_REG_LDOCTL19               0x5C
+#define MAX8907C_REG_LDOSEQCNT19            0x5D
+#define MAX8907C_REG_LDO19VOUT              0x5E
+#define MAX8907C_REG_LBCNFG                 0x60
+#define MAX8907C_REG_SEQ1CNFG               0x64
+#define MAX8907C_REG_SEQ2CNFG               0x65
+#define MAX8907C_REG_SEQ3CNFG               0x66
+#define MAX8907C_REG_SEQ4CNFG               0x67
+#define MAX8907C_REG_SEQ5CNFG               0x68
+#define MAX8907C_REG_SEQ6CNFG               0x69
+#define MAX8907C_REG_SEQ7CNFG               0x6A
+#define MAX8907C_REG_LDOCTL18               0x72
+#define MAX8907C_REG_LDOSEQCNT18            0x73
+#define MAX8907C_REG_LDO18VOUT              0x74
+#define MAX8907C_REG_BBAT_CNFG              0x78
+#define MAX8907C_REG_CHG_CNTL1              0x7C
+#define MAX8907C_REG_CHG_CNTL2              0x7D
+#define MAX8907C_REG_CHG_IRQ1               0x7E
+#define MAX8907C_REG_CHG_IRQ2               0x7F
+#define MAX8907C_REG_CHG_IRQ1_MASK          0x80
+#define MAX8907C_REG_CHG_IRQ2_MASK          0x81
+#define MAX8907C_REG_CHG_STAT               0x82
+#define MAX8907C_REG_WLED_MODE_CNTL         0x84
+#define MAX8907C_REG_ILED_CNTL              0x84
+#define MAX8907C_REG_II1RR                  0x8E
+#define MAX8907C_REG_II2RR                  0x8F
+#define MAX8907C_REG_LDOCTL20               0x9C
+#define MAX8907C_REG_LDOSEQCNT20            0x9D
+#define MAX8907C_REG_LDO20VOUT              0x9E
+
+/* RTC register */
+#define MAX8907C_REG_RTC_SEC                0x00
+#define MAX8907C_REG_RTC_MIN                0x01
+#define MAX8907C_REG_RTC_HOURS              0x02
+#define MAX8907C_REG_RTC_WEEKDAY            0x03
+#define MAX8907C_REG_RTC_DATE               0x04
+#define MAX8907C_REG_RTC_MONTH              0x05
+#define MAX8907C_REG_RTC_YEAR1              0x06
+#define MAX8907C_REG_RTC_YEAR2              0x07
+#define MAX8907C_REG_ALARM0_SEC             0x08
+#define MAX8907C_REG_ALARM0_MIN             0x09
+#define MAX8907C_REG_ALARM0_HOURS           0x0A
+#define MAX8907C_REG_ALARM0_WEEKDAY         0x0B
+#define MAX8907C_REG_ALARM0_DATE            0x0C
+#define MAX8907C_REG_ALARM0_MONTH           0x0D
+#define MAX8907C_REG_ALARM0_YEAR1           0x0E
+#define MAX8907C_REG_ALARM0_YEAR2           0x0F
+#define MAX8907C_REG_ALARM1_SEC             0x10
+#define MAX8907C_REG_ALARM1_MIN             0x11
+#define MAX8907C_REG_ALARM1_HOURS           0x12
+#define MAX8907C_REG_ALARM1_WEEKDAY         0x13
+#define MAX8907C_REG_ALARM1_DATE            0x14
+#define MAX8907C_REG_ALARM1_MONTH           0x15
+#define MAX8907C_REG_ALARM1_YEAR1           0x16
+#define MAX8907C_REG_ALARM1_YEAR2           0x17
+#define MAX8907C_REG_ALARM0_CNTL            0x18
+#define MAX8907C_REG_ALARM1_CNTL            0x19
+#define MAX8907C_REG_RTC_STATUS             0x1A
+#define MAX8907C_REG_RTC_CNTL               0x1B
+#define MAX8907C_REG_RTC_IRQ                0x1C
+#define MAX8907C_REG_RTC_IRQ_MASK           0x1D
+#define MAX8907C_REG_MPL_CNTL               0x1E
+
+/* ADC and Touch Screen Controller register map */
+
+#define MAX8907C_CTL     0
+#define MAX8907C_SEQCNT  1
+#define MAX8907C_VOUT    2
+
+/* mask bit fields */
+#define MAX8907C_MASK_LDO_SEQ           0x1C
+#define MAX8907C_MASK_LDO_EN            0x01
+#define MAX8907C_MASK_VBBATTCV          0x03
+#define MAX8907C_MASK_OUT5V_VINEN       0x10
+#define MAX8907C_MASK_OUT5V_ENSRC       0x0E
+#define MAX8907C_MASK_OUT5V_EN          0x01
+
+#define RTC_I2C_ADDR			0x68
+
+/* IRQ definitions */
+enum {
+	MAX8907C_IRQ_VCHG_DC_OVP,
+	MAX8907C_IRQ_VCHG_DC_F,
+	MAX8907C_IRQ_VCHG_DC_R,
+	MAX8907C_IRQ_VCHG_THM_OK_R,
+	MAX8907C_IRQ_VCHG_THM_OK_F,
+	MAX8907C_IRQ_VCHG_MBATTLOW_F,
+	MAX8907C_IRQ_VCHG_MBATTLOW_R,
+	MAX8907C_IRQ_VCHG_RST,
+	MAX8907C_IRQ_VCHG_DONE,
+	MAX8907C_IRQ_VCHG_TOPOFF,
+	MAX8907C_IRQ_VCHG_TMR_FAULT,
+	MAX8907C_IRQ_GPM_RSTIN,
+	MAX8907C_IRQ_GPM_MPL,
+	MAX8907C_IRQ_GPM_SW_3SEC,
+	MAX8907C_IRQ_GPM_EXTON_F,
+	MAX8907C_IRQ_GPM_EXTON_R,
+	MAX8907C_IRQ_GPM_SW_1SEC,
+	MAX8907C_IRQ_GPM_SW_F,
+	MAX8907C_IRQ_GPM_SW_R,
+	MAX8907C_IRQ_GPM_SYSCKEN_F,
+	MAX8907C_IRQ_GPM_SYSCKEN_R,
+	MAX8907C_IRQ_RTC_ALARM1,
+	MAX8907C_IRQ_RTC_ALARM0,
+	MAX8907C_NR_IRQS,
+};
+
+struct max8907c {
+	struct device 		*dev;
+	struct mutex 		io_lock;
+	struct mutex		irq_lock;
+	struct i2c_client 	*i2c_power;
+	struct i2c_client 	*i2c_rtc;
+	int			irq_base;
+	int			core_irq;
+};
+
+struct max8907c_platform_data {
+	int num_subdevs;
+	struct platform_device **subdevs;
+	int irq_base;
+};
+
+int max8907c_reg_read(struct i2c_client *i2c, u8 reg);
+int max8907c_reg_bulk_read(struct i2c_client *i2c, u8 reg, u8 count, u8 *val);
+int max8907c_reg_write(struct i2c_client *i2c, u8 reg, u8 val);
+int max8907c_reg_bulk_write(struct i2c_client *i2c, u8 reg, u8 count, u8 *val);
+int max8907c_set_bits(struct i2c_client *i2c, u8 reg, u8 mask, u8 val);
+
+int max8907c_irq_init(struct max8907c *chip, int irq, int irq_base);
+void max8907c_irq_free(struct max8907c *chip);
+int max8907c_suspend(struct i2c_client *i2c, pm_message_t state);
+int max8907c_resume(struct i2c_client *i2c);
+#endif
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
index d96fb3d3e624..9002714f1f68 100644
--- a/include/linux/mfd/tps6586x.h
+++ b/include/linux/mfd/tps6586x.h
@@ -54,8 +54,18 @@ struct tps6586x_subdev_info {
 	void		*platform_data;
 };
 
+struct tps6586x_epoch_start {
+	int year;
+	int month;
+	int day;
+	int hour;
+	int min;
+	int sec;
+};
+
 struct tps6586x_rtc_platform_data {
 	int irq;
+	struct tps6586x_epoch_start start;
 };
 
 struct tps6586x_platform_data {
@@ -78,5 +88,6 @@ extern int tps6586x_set_bits(struct device *dev, int reg, uint8_t bit_mask);
 extern int tps6586x_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
 extern int tps6586x_update(struct device *dev, int reg, uint8_t val,
 			   uint8_t mask);
+extern int tps6586x_power_off(void);
 
 #endif /*__LINUX_MFD_TPS6586X_H */
diff --git a/include/linux/mmc/sdio_func.h b/include/linux/mmc/sdio_func.h
index 557acae8cf95..557acae8cf95 100755..100644
--- a/include/linux/mmc/sdio_func.h
+++ b/include/linux/mmc/sdio_func.h
diff --git a/include/linux/mpu.h b/include/linux/mpu.h
new file mode 100644
index 000000000000..f3ae55b42086
--- /dev/null
+++ b/include/linux/mpu.h
@@ -0,0 +1,425 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+#ifndef __MPU_H_
+#define __MPU_H_
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#endif
+
+#ifdef M_HW
+#include "mpu6000.h"
+#else
+#include "mpu3050.h"
+#endif
+
+/* Number of axes on each sensor */
+#define GYRO_NUM_AXES    (3)
+#define ACCEL_NUM_AXES   (3)
+#define COMPASS_NUM_AXES (3)
+
+/* IOCTL commands for /dev/mpu */
+#define MPU_SET_MPU_CONFIG          (0x00)
+#define MPU_SET_INT_CONFIG          (0x01)
+#define MPU_SET_EXT_SYNC            (0x02)
+#define MPU_SET_FULL_SCALE          (0x03)
+#define MPU_SET_LPF                 (0x04)
+#define MPU_SET_CLK_SRC             (0x05)
+#define MPU_SET_DIVIDER             (0x06)
+#define MPU_SET_LEVEL_SHIFTER       (0x07)
+#define MPU_SET_DMP_ENABLE          (0x08)
+#define MPU_SET_FIFO_ENABLE         (0x09)
+#define MPU_SET_DMP_CFG1            (0x0a)
+#define MPU_SET_DMP_CFG2            (0x0b)
+#define MPU_SET_OFFSET_TC           (0x0c)
+#define MPU_SET_RAM                 (0x0d)
+
+#define MPU_SET_PLATFORM_DATA       (0x0e)
+
+#define MPU_GET_MPU_CONFIG          (0x80)
+#define MPU_GET_INT_CONFIG          (0x81)
+#define MPU_GET_EXT_SYNC            (0x82)
+#define MPU_GET_FULL_SCALE          (0x83)
+#define MPU_GET_LPF                 (0x84)
+#define MPU_GET_CLK_SRC             (0x85)
+#define MPU_GET_DIVIDER             (0x86)
+#define MPU_GET_LEVEL_SHIFTER       (0x87)
+#define MPU_GET_DMP_ENABLE          (0x88)
+#define MPU_GET_FIFO_ENABLE         (0x89)
+#define MPU_GET_DMP_CFG1            (0x8a)
+#define MPU_GET_DMP_CFG2            (0x8b)
+#define MPU_GET_OFFSET_TC           (0x8c)
+#define MPU_GET_RAM                 (0x8d)
+
+#define MPU_READ_REGISTER           (0x40)
+#define MPU_WRITE_REGISTER          (0x41)
+#define MPU_READ_MEMORY             (0x42)
+#define MPU_WRITE_MEMORY            (0x43)
+
+#define MPU_SUSPEND                 (0x44)
+#define MPU_RESUME                  (0x45)
+#define MPU_READ_COMPASS            (0x46)
+#define MPU_READ_ACCEL              (0x47)
+#define MPU_READ_PRESSURE           (0x48)
+
+#define MPU_CONFIG_ACCEL            (0x20)
+#define MPU_CONFIG_COMPASS          (0x21)
+#define MPU_CONFIG_PRESSURE         (0x22)
+
+/* Structure for the following IOCTL's:
+   MPU_SET_RAM
+   MPU_GET_RAM
+   MPU_READ_REGISTER
+   MPU_WRITE_REGISTER
+   MPU_READ_MEMORY
+   MPU_WRITE_MEMORY
+*/
+struct mpu_read_write {
+	unsigned short address;
+	unsigned short length;
+	unsigned char *data;
+};
+
+/* Structure for the following IOCTL's
+   MPU_SUSPEND
+   MPU_RESUME
+*/
+struct mpu_suspend_resume {
+	int gyro;
+	int accel;
+	int compass;
+	int pressure;
+};
+
+struct irq_data {
+	int interruptcount;
+	unsigned long long irqtime;
+	int data_type;
+	int data_size;
+	void *data;
+};
+enum ext_slave_config_key {
+    MPU_SLAVE_CONFIG_ODR_SUSPEND,
+    MPU_SLAVE_CONFIG_ODR_RESUME,
+    MPU_SLAVE_CONFIG_FSR_SUSPEND,
+    MPU_SLAVE_CONFIG_FSR_RESUME,
+    MPU_SLAVE_CONFIG_MOT_THS,
+    MPU_SLAVE_CONFIG_NMOT_THS,
+    MPU_SLAVE_CONFIG_MOT_DUR,
+    MPU_SLAVE_CONFIG_NMOT_DUR,
+    MPU_SLAVE_CONFIG_NUM_CONFIG_KEYS,
+};
+/* Structure for the following IOCTS's
+ * MPU_CONFIG_ACCEL
+ * MPU_CONFIG_COMPASS
+ * MPU_CONFIG_PRESSURE
+ */
+struct ext_slave_config {
+	int key;
+	int len;
+	void *data;
+};
+
+enum ext_slave_type {
+	EXT_SLAVE_TYPE_GYROSCOPE,
+	EXT_SLAVE_TYPE_ACCELEROMETER,
+	EXT_SLAVE_TYPE_COMPASS,
+	EXT_SLAVE_TYPE_PRESSURE,
+	/*EXT_SLAVE_TYPE_TEMPERATURE */
+};
+
+enum ext_slave_id {
+	ID_INVALID = 0,
+
+	ACCEL_ID_LIS331,
+	ACCEL_ID_LSM303,
+	ACCEL_ID_KXSD9,
+	ACCEL_ID_KXTF9,
+	ACCEL_ID_BMA150,
+	ACCEL_ID_BMA222,
+	ACCEL_ID_ADI346,
+	ACCEL_ID_MMA8450,
+	ACCEL_ID_MMA8451,
+	ACCEL_ID_MPU6000,
+
+	COMPASS_ID_AKM,
+	COMPASS_ID_AMI30X,
+	COMPASS_ID_YAS529,
+	COMPASS_ID_HMC5883,
+	COMPASS_ID_LSM303,
+	COMPASS_ID_MMC314X,
+	COMPASS_ID_HSCDTD002B,
+
+	PRESSURE_ID_BMA085,
+};
+
+enum ext_slave_endian {
+	EXT_SLAVE_BIG_ENDIAN,
+	EXT_SLAVE_LITTLE_ENDIAN,
+	EXT_SLAVE_FS8_BIG_ENDIAN,
+	EXT_SLAVE_FS16_BIG_ENDIAN,
+};
+
+enum ext_slave_bus {
+	EXT_SLAVE_BUS_INVALID = -1,
+	EXT_SLAVE_BUS_PRIMARY = 0,
+	EXT_SLAVE_BUS_SECONDARY = 1
+};
+
+
+/**
+ *  struct ext_slave_platform_data - Platform data for mpu3050 slave devices
+ *
+ *  @get_slave_descr: Function pointer to retrieve the struct ext_slave_descr
+ *                    for this slave
+ *  @irq: the irq number attached to the slave if any.
+ *  @adapt_num: the I2C adapter number.
+ *  @bus: the bus the slave is attached to: enum ext_slave_bus
+ *  @address: the I2C slave address of the slave device.
+ *  @orientation: the mounting matrix of the device relative to MPU.
+ *  @irq_data: private data for the slave irq handler
+ *  @private_data: additional data, user customizable.  Not touched by the MPU
+ *                 driver.
+ *
+ * The orientation matricies are 3x3 rotation matricies
+ * that are applied to the data to rotate from the mounting orientation to the
+ * platform orientation.  The values must be one of 0, 1, or -1 and each row and
+ * column should have exactly 1 non-zero value.
+ */
+struct ext_slave_platform_data {
+	struct ext_slave_descr *(*get_slave_descr) (void);
+	int irq;
+	int adapt_num;
+	int bus;
+	unsigned char address;
+	signed char orientation[9];
+	void *irq_data;
+	void *private_data;
+};
+
+
+struct tFixPntRange {
+	long mantissa;
+	long fraction;
+};
+
+/**
+ *  struct ext_slave_descr - Description of the slave device for programming.
+ *
+ *  @suspend:	function pointer to put the device in suspended state
+ *  @resume:	function pointer to put the device in running state
+ *  @read:	function that reads the device data
+ *  @init:	function used to preallocate memory used by the driver
+ *  @exit:	function used to free memory allocated for the driver
+ *  @config:	function used to configure the device
+ *
+ *  @name:	text name of the device
+ *  @type:	device type. enum ext_slave_type
+ *  @id:	enum ext_slave_id
+ *  @reg:	starting register address to retrieve data.
+ *  @len:	length in bytes of the sensor data.  Should be 6.
+ *  @endian:	byte order of the data. enum ext_slave_endian
+ *  @range:	full scale range of the slave ouput: struct tFixPntRange
+ *
+ *  Defines the functions and information about the slave the mpu3050 needs to
+ *  use the slave device.
+ */
+struct ext_slave_descr {
+	int (*init) (void *mlsl_handle,
+		     struct ext_slave_descr *slave,
+		     struct ext_slave_platform_data *pdata);
+	int (*exit) (void *mlsl_handle,
+		     struct ext_slave_descr *slave,
+		     struct ext_slave_platform_data *pdata);
+	int (*suspend) (void *mlsl_handle,
+			struct ext_slave_descr *slave,
+			struct ext_slave_platform_data *pdata);
+	int (*resume) (void *mlsl_handle,
+		       struct ext_slave_descr *slave,
+		       struct ext_slave_platform_data *pdata);
+	int (*read) (void *mlsl_handle,
+		     struct ext_slave_descr *slave,
+		     struct ext_slave_platform_data *pdata,
+		     unsigned char *data);
+	int (*config) (void *mlsl_handle,
+		       struct ext_slave_descr *slave,
+		       struct ext_slave_platform_data *pdata,
+		       struct ext_slave_config *config);
+
+	char *name;
+	unsigned char type;
+	unsigned char id;
+	unsigned char reg;
+	unsigned int len;
+	unsigned char endian;
+	struct tFixPntRange range;
+};
+
+/**
+ * struct mpu3050_platform_data - Platform data for the mpu3050 driver
+ * @int_config:		Bits [7:3] of the int config register.
+ * @orientation:	Orientation matrix of the gyroscope
+ * @level_shifter:	0: VLogic, 1: VDD
+ * @accel:		Accel platform data
+ * @compass:		Compass platform data
+ * @pressure:		Pressure platform data
+ *
+ * Contains platform specific information on how to configure the MPU3050 to
+ * work on this platform.  The orientation matricies are 3x3 rotation matricies
+ * that are applied to the data to rotate from the mounting orientation to the
+ * platform orientation.  The values must be one of 0, 1, or -1 and each row and
+ * column should have exactly 1 non-zero value.
+ */
+struct mpu3050_platform_data {
+	unsigned char int_config;
+	signed char orientation[MPU_NUM_AXES * MPU_NUM_AXES];
+	unsigned char level_shifter;
+	struct ext_slave_platform_data accel;
+	struct ext_slave_platform_data compass;
+	struct ext_slave_platform_data pressure;
+};
+
+
+/*
+    Accelerometer
+*/
+#define get_accel_slave_descr NULL
+
+#ifdef CONFIG_SENSORS_ADXL346	/* ADI accelerometer */
+struct ext_slave_descr *adxl346_get_slave_descr(void);
+#undef get_accel_slave_descr
+#define get_accel_slave_descr adxl346_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_BMA150	/* Bosch accelerometer */
+struct ext_slave_descr *bma150_get_slave_descr(void);
+#undef get_accel_slave_descr
+#define get_accel_slave_descr bma150_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_BMA222	/* Bosch 222 accelerometer */
+struct ext_slave_descr *bma222_get_slave_descr(void);
+#undef get_accel_slave_descr
+#define get_accel_slave_descr bma222_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_KXSD9	/* Kionix accelerometer */
+struct ext_slave_descr *kxsd9_get_slave_descr(void);
+#undef get_accel_slave_descr
+#define get_accel_slave_descr kxsd9_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_KXTF9	/* Kionix accelerometer */
+struct ext_slave_descr *kxtf9_get_slave_descr(void);
+#undef get_accel_slave_descr
+#define get_accel_slave_descr kxtf9_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_LIS331DLH	/* ST accelerometer */
+struct ext_slave_descr *lis331dlh_get_slave_descr(void);
+#undef get_accel_slave_descr
+#define get_accel_slave_descr lis331dlh_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_LSM303DLHA	/* ST accelerometer */
+struct ext_slave_descr *lsm303dlha_get_slave_descr(void);
+#undef get_accel_slave_descr
+#define get_accel_slave_descr lsm303dlha_get_slave_descr
+#endif
+
+/* MPU6000 Accel */
+#if defined(CONFIG_SENSORS_MPU6000) || defined(CONFIG_SENSORS_MPU6000_MODULE)
+struct ext_slave_descr *mantis_get_slave_descr(void);
+#undef get_accel_slave_descr
+#define get_accel_slave_descr mantis_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_MMA8450	/* Freescale accelerometer */
+struct ext_slave_descr *mma8450_get_slave_descr(void);
+#undef get_accel_slave_descr
+#define get_accel_slave_descr mma8450_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_MMA8451	/* Freescale accelerometer */
+struct ext_slave_descr *mma8451_get_slave_descr(void);
+#undef get_accel_slave_descr
+#define get_accel_slave_descr mma8451_get_slave_descr
+#endif
+
+
+/*
+    Compass
+*/
+#define get_compass_slave_descr NULL
+
+#ifdef CONFIG_SENSORS_AK8975	/* AKM compass */
+struct ext_slave_descr *ak8975_get_slave_descr(void);
+#undef get_compass_slave_descr
+#define get_compass_slave_descr ak8975_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_AMI30X	/* AICHI Steel compass */
+struct ext_slave_descr *ami30x_get_slave_descr(void);
+#undef get_compass_slave_descr
+#define get_compass_slave_descr ami30x_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_HMC5883	/* Honeywell compass */
+struct ext_slave_descr *hmc5883_get_slave_descr(void);
+#undef get_compass_slave_descr
+#define get_compass_slave_descr hmc5883_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_MMC314X	/* MEMSIC compass */
+struct ext_slave_descr *mmc314x_get_slave_descr(void);
+#undef get_compass_slave_descr
+#define get_compass_slave_descr mmc314x_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_LSM303DLHM	/* ST compass */
+struct ext_slave_descr *lsm303dlhm_get_slave_descr(void);
+#undef get_compass_slave_descr
+#define get_compass_slave_descr lsm303dlhm_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_YAS529	/* Yamaha compass */
+struct ext_slave_descr *yas529_get_slave_descr(void);
+#undef get_compass_slave_descr
+#define get_compass_slave_descr yas529_get_slave_descr
+#endif
+
+#ifdef CONFIG_SENSORS_HSCDTD002B	/* Alps compass */
+struct ext_slave_descr *hscdtd002b_get_slave_descr(void);
+#undef get_compass_slave_descr
+#define get_compass_slave_descr hscdtd002b_get_slave_descr
+#endif
+
+/*
+    Pressure
+*/
+#define get_pressure_slave_descr NULL
+
+#ifdef CONFIG_SENSORS_BMA085	/* BMA pressure */
+struct ext_slave_descr *bma085_get_slave_descr(void);
+#undef get_pressure_slave_descr
+#define get_pressure_slave_descr bma085_get_slave_descr
+#endif
+
+#endif				/* __MPU_H_ */
diff --git a/include/linux/mpu3050.h b/include/linux/mpu3050.h
new file mode 100644
index 000000000000..a8dcd5a9473f
--- /dev/null
+++ b/include/linux/mpu3050.h
@@ -0,0 +1,255 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+#ifndef __MPU3050_H_
+#define __MPU3050_H_
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#endif
+
+#ifdef M_HW
+#error MPU6000 build including MPU3050 header
+#endif
+
+#define MPU_NAME "mpu3050"
+#define DEFAULT_MPU_SLAVEADDR       0x68
+
+/*==== MPU REGISTER SET ====*/
+enum mpu_register {
+	MPUREG_WHO_AM_I = 0,	/* 00 0x00 */
+	MPUREG_PRODUCT_ID,	/* 01 0x01 */
+	MPUREG_02_RSVD,		/* 02 0x02 */
+	MPUREG_03_RSVD,		/* 03 0x03 */
+	MPUREG_04_RSVD,		/* 04 0x04 */
+	MPUREG_XG_OFFS_TC,	/* 05 0x05 */
+	MPUREG_06_RSVD,		/* 06 0x06 */
+	MPUREG_07_RSVD,		/* 07 0x07 */
+	MPUREG_YG_OFFS_TC,	/* 08 0x08 */
+	MPUREG_09_RSVD,		/* 09 0x09 */
+	MPUREG_0A_RSVD,		/* 10 0x0a */
+	MPUREG_ZG_OFFS_TC,	/* 11 0x0b */
+	MPUREG_X_OFFS_USRH,	/* 12 0x0c */
+	MPUREG_X_OFFS_USRL,	/* 13 0x0d */
+	MPUREG_Y_OFFS_USRH,	/* 14 0x0e */
+	MPUREG_Y_OFFS_USRL,	/* 15 0x0f */
+	MPUREG_Z_OFFS_USRH,	/* 16 0x10 */
+	MPUREG_Z_OFFS_USRL,	/* 17 0x11 */
+	MPUREG_FIFO_EN1,	/* 18 0x12 */
+	MPUREG_FIFO_EN2,	/* 19 0x13 */
+	MPUREG_AUX_SLV_ADDR,	/* 20 0x14 */
+	MPUREG_SMPLRT_DIV,	/* 21 0x15 */
+	MPUREG_DLPF_FS_SYNC,	/* 22 0x16 */
+	MPUREG_INT_CFG,		/* 23 0x17 */
+	MPUREG_ACCEL_BURST_ADDR,/* 24 0x18 */
+	MPUREG_19_RSVD,		/* 25 0x19 */
+	MPUREG_INT_STATUS,	/* 26 0x1a */
+	MPUREG_TEMP_OUT_H,	/* 27 0x1b */
+	MPUREG_TEMP_OUT_L,	/* 28 0x1c */
+	MPUREG_GYRO_XOUT_H,	/* 29 0x1d */
+	MPUREG_GYRO_XOUT_L,	/* 30 0x1e */
+	MPUREG_GYRO_YOUT_H,	/* 31 0x1f */
+	MPUREG_GYRO_YOUT_L,	/* 32 0x20 */
+	MPUREG_GYRO_ZOUT_H,	/* 33 0x21 */
+	MPUREG_GYRO_ZOUT_L,	/* 34 0x22 */
+	MPUREG_23_RSVD,		/* 35 0x23 */
+	MPUREG_24_RSVD,		/* 36 0x24 */
+	MPUREG_25_RSVD,		/* 37 0x25 */
+	MPUREG_26_RSVD,		/* 38 0x26 */
+	MPUREG_27_RSVD,		/* 39 0x27 */
+	MPUREG_28_RSVD,		/* 40 0x28 */
+	MPUREG_29_RSVD,		/* 41 0x29 */
+	MPUREG_2A_RSVD,		/* 42 0x2a */
+	MPUREG_2B_RSVD,		/* 43 0x2b */
+	MPUREG_2C_RSVD,		/* 44 0x2c */
+	MPUREG_2D_RSVD,		/* 45 0x2d */
+	MPUREG_2E_RSVD,		/* 46 0x2e */
+	MPUREG_2F_RSVD,		/* 47 0x2f */
+	MPUREG_30_RSVD,		/* 48 0x30 */
+	MPUREG_31_RSVD,		/* 49 0x31 */
+	MPUREG_32_RSVD,		/* 50 0x32 */
+	MPUREG_33_RSVD,		/* 51 0x33 */
+	MPUREG_34_RSVD,		/* 52 0x34 */
+	MPUREG_DMP_CFG_1,	/* 53 0x35 */
+	MPUREG_DMP_CFG_2,	/* 54 0x36 */
+	MPUREG_BANK_SEL,	/* 55 0x37 */
+	MPUREG_MEM_START_ADDR,	/* 56 0x38 */
+	MPUREG_MEM_R_W,		/* 57 0x39 */
+	MPUREG_FIFO_COUNTH,	/* 58 0x3a */
+	MPUREG_FIFO_COUNTL,	/* 59 0x3b */
+	MPUREG_FIFO_R_W,	/* 60 0x3c */
+	MPUREG_USER_CTRL,	/* 61 0x3d */
+	MPUREG_PWR_MGM,		/* 62 0x3e */
+	MPUREG_3F_RSVD,		/* 63 0x3f */
+	NUM_OF_MPU_REGISTERS	/* 64 0x40 */
+};
+
+/*==== BITS FOR MPU ====*/
+
+/*---- MPU 'FIFO_EN1' register (12) ----*/
+#define BIT_TEMP_OUT                0x80
+#define BIT_GYRO_XOUT               0x40
+#define BIT_GYRO_YOUT               0x20
+#define BIT_GYRO_ZOUT               0x10
+#define BIT_ACCEL_XOUT              0x08
+#define BIT_ACCEL_YOUT              0x04
+#define BIT_ACCEL_ZOUT              0x02
+#define BIT_AUX_1OUT                0x01
+/*---- MPU 'FIFO_EN2' register (13) ----*/
+#define BIT_AUX_2OUT                0x02
+#define BIT_AUX_3OUT                0x01
+/*---- MPU 'DLPF_FS_SYNC' register (16) ----*/
+#define BITS_EXT_SYNC_NONE          0x00
+#define BITS_EXT_SYNC_TEMP          0x20
+#define BITS_EXT_SYNC_GYROX         0x40
+#define BITS_EXT_SYNC_GYROY         0x60
+#define BITS_EXT_SYNC_GYROZ         0x80
+#define BITS_EXT_SYNC_ACCELX        0xA0
+#define BITS_EXT_SYNC_ACCELY        0xC0
+#define BITS_EXT_SYNC_ACCELZ        0xE0
+#define BITS_EXT_SYNC_MASK          0xE0
+#define BITS_FS_250DPS              0x00
+#define BITS_FS_500DPS              0x08
+#define BITS_FS_1000DPS             0x10
+#define BITS_FS_2000DPS             0x18
+#define BITS_FS_MASK                0x18
+#define BITS_DLPF_CFG_256HZ_NOLPF2  0x00
+#define BITS_DLPF_CFG_188HZ         0x01
+#define BITS_DLPF_CFG_98HZ          0x02
+#define BITS_DLPF_CFG_42HZ          0x03
+#define BITS_DLPF_CFG_20HZ          0x04
+#define BITS_DLPF_CFG_10HZ          0x05
+#define BITS_DLPF_CFG_5HZ           0x06
+#define BITS_DLPF_CFG_2100HZ_NOLPF  0x07
+#define BITS_DLPF_CFG_MASK          0x07
+/*---- MPU 'INT_CFG' register (17) ----*/
+#define BIT_ACTL                    0x80
+#define BIT_ACTL_LOW                0x80
+#define BIT_ACTL_HIGH               0x00
+#define BIT_OPEN                    0x40
+#define BIT_OPEN_DRAIN              0x40
+#define BIT_PUSH_PULL               0x00
+#define BIT_LATCH_INT_EN            0x20
+#define BIT_LATCH_INT_EN            0x20
+#define BIT_INT_PULSE_WIDTH_50US    0x00
+#define BIT_INT_ANYRD_2CLEAR        0x10
+#define BIT_INT_STAT_READ_2CLEAR    0x00
+#define BIT_MPU_RDY_EN              0x04
+#define BIT_DMP_INT_EN              0x02
+#define BIT_RAW_RDY_EN              0x01
+/*---- MPU 'INT_STATUS' register (1A) ----*/
+#define BIT_INT_STATUS_FIFO_OVERLOW 0x80
+#define BIT_MPU_RDY                 0x04
+#define BIT_DMP_INT                 0x02
+#define BIT_RAW_RDY                 0x01
+/*---- MPU 'BANK_SEL' register (37) ----*/
+#define BIT_PRFTCH_EN               0x20
+#define BIT_CFG_USER_BANK           0x10
+#define BITS_MEM_SEL                0x0f
+/*---- MPU 'USER_CTRL' register (3D) ----*/
+#define BIT_DMP_EN                  0x80
+#define BIT_FIFO_EN                 0x40
+#define BIT_AUX_IF_EN               0x20
+#define BIT_AUX_RD_LENG             0x10
+#define BIT_AUX_IF_RST              0x08
+#define BIT_DMP_RST                 0x04
+#define BIT_FIFO_RST                0x02
+#define BIT_GYRO_RST                0x01
+/*---- MPU 'PWR_MGM' register (3E) ----*/
+#define BIT_H_RESET                 0x80
+#define BIT_SLEEP                   0x40
+#define BIT_STBY_XG                 0x20
+#define BIT_STBY_YG                 0x10
+#define BIT_STBY_ZG                 0x08
+#define BITS_CLKSEL                 0x07
+
+/*---- MPU Silicon Revision ----*/
+#define MPU_SILICON_REV_A4           1	/* MPU A4 Device */
+#define MPU_SILICON_REV_B1           2	/* MPU B1 Device */
+#define MPU_SILICON_REV_B4           3	/* MPU B4 Device */
+#define MPU_SILICON_REV_B6           4	/* MPU B6 Device */
+
+/*---- MPU Memory ----*/
+#define MPU_MEM_BANK_SIZE           (256)
+#define FIFO_HW_SIZE                (512)
+
+enum MPU_MEMORY_BANKS {
+	MPU_MEM_RAM_BANK_0 = 0,
+	MPU_MEM_RAM_BANK_1,
+	MPU_MEM_RAM_BANK_2,
+	MPU_MEM_RAM_BANK_3,
+	MPU_MEM_NUM_RAM_BANKS,
+	MPU_MEM_OTP_BANK_0 = MPU_MEM_NUM_RAM_BANKS,
+	/* This one is always last */
+	MPU_MEM_NUM_BANKS
+};
+
+#define MPU_NUM_AXES (3)
+
+/*---- structure containing control variables used by MLDL ----*/
+/*---- MPU clock source settings ----*/
+/*---- MPU filter selections ----*/
+enum mpu_filter {
+	MPU_FILTER_256HZ_NOLPF2 = 0,
+	MPU_FILTER_188HZ,
+	MPU_FILTER_98HZ,
+	MPU_FILTER_42HZ,
+	MPU_FILTER_20HZ,
+	MPU_FILTER_10HZ,
+	MPU_FILTER_5HZ,
+	MPU_FILTER_2100HZ_NOLPF,
+	NUM_MPU_FILTER
+};
+
+enum mpu_fullscale {
+	MPU_FS_250DPS = 0,
+	MPU_FS_500DPS,
+	MPU_FS_1000DPS,
+	MPU_FS_2000DPS,
+	NUM_MPU_FS
+};
+
+enum mpu_clock_sel {
+	MPU_CLK_SEL_INTERNAL = 0,
+	MPU_CLK_SEL_PLLGYROX,
+	MPU_CLK_SEL_PLLGYROY,
+	MPU_CLK_SEL_PLLGYROZ,
+	MPU_CLK_SEL_PLLEXT32K,
+	MPU_CLK_SEL_PLLEXT19M,
+	MPU_CLK_SEL_RESERVED,
+	MPU_CLK_SEL_STOP,
+	NUM_CLK_SEL
+};
+
+enum mpu_ext_sync {
+	MPU_EXT_SYNC_NONE = 0,
+	MPU_EXT_SYNC_TEMP,
+	MPU_EXT_SYNC_GYROX,
+	MPU_EXT_SYNC_GYROY,
+	MPU_EXT_SYNC_GYROZ,
+	MPU_EXT_SYNC_ACCELX,
+	MPU_EXT_SYNC_ACCELY,
+	MPU_EXT_SYNC_ACCELZ,
+	NUM_MPU_EXT_SYNC
+};
+
+#define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \
+    ((ext_sync << 5) | (full_scale << 3) | lpf)
+
+#endif				/* __MPU3050_H_ */
diff --git a/include/linux/mpu6000.h b/include/linux/mpu6000.h
new file mode 100644
index 000000000000..89c4cbb90b69
--- /dev/null
+++ b/include/linux/mpu6000.h
@@ -0,0 +1,401 @@
+/*
+ $License:
+    Copyright (C) 2010 InvenSense Corporation, All Rights Reserved.
+
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+  $
+ */
+
+/**
+ * @defgroup
+ * @brief
+ *
+ * @{
+ *      @file     mpu6000.h
+ *      @brief
+ */
+
+#ifndef __MPU6000_H_
+#define __MPU6000_H_
+
+#define MPU_NAME "mpu6000"
+#define DEFAULT_MPU_SLAVEADDR       0x68
+
+/*==== M_HW REGISTER SET ====*/
+enum {
+	MPUREG_XG_OFFS_TC = 0,
+	MPUREG_YG_OFFS_TC,
+	MPUREG_ZG_OFFS_TC,
+	MPUREG_X_FINE_GAIN,
+	MPUREG_Y_FINE_GAIN,
+	MPUREG_Z_FINE_GAIN,
+	MPUREG_XA_OFFS_H,
+	MPUREG_XA_OFFS_L_TC,
+	MPUREG_YA_OFFS_H,
+	MPUREG_YA_OFFS_L_TC,
+	MPUREG_ZA_OFFS_H,
+	MPUREG_ZA_OFFS_L_TC,	/* 0xB */
+	MPUREG_0C_RSVD,
+	MPUREG_0D_RSVD,
+	MPUREG_0E_RSVD,
+	MPUREG_0F_RSVD,
+	MPUREG_10_RSVD,
+	MPUREG_11_RSVD,
+	MPUREG_12_RSVD,
+	MPUREG_XG_OFFS_USRH,
+	MPUREG_XG_OFFS_USRL,
+	MPUREG_YG_OFFS_USRH,
+	MPUREG_YG_OFFS_USRL,
+	MPUREG_ZG_OFFS_USRH,
+	MPUREG_ZG_OFFS_USRL,
+	MPUREG_SMPLRT_DIV,	/* 0x19 */
+	MPUREG_CONFIG,		/* 0x1A ==> DLPF_FS_SYNC */
+	MPUREG_GYRO_CONFIG,
+	MPUREG_ACCEL_CONFIG,
+	MPUREG_ACCEL_FF_THR,
+	MPUREG_ACCEL_FF_DUR,
+	MPUREG_ACCEL_MOT_THR,
+	MPUREG_ACCEL_MOT_DUR,
+	MPUREG_ACCEL_ZRMOT_THR,
+	MPUREG_ACCEL_ZRMOT_DUR,
+	MPUREG_FIFO_EN,		/* 0x23 */
+	MPUREG_I2C_MST_CTRL,
+	MPUREG_I2C_SLV0_ADDR,	/* 0x25 */
+	MPUREG_I2C_SLV0_REG,
+	MPUREG_I2C_SLV0_CTRL,
+	MPUREG_I2C_SLV1_ADDR,	/* 0x28 */
+	MPUREG_I2C_SLV1_REG_PASSWORD,
+	MPUREG_I2C_SLV1_CTRL,
+	MPUREG_I2C_SLV2_ADDR,	/* 0x2B */
+	MPUREG_I2C_SLV2_REG,
+	MPUREG_I2C_SLV2_CTRL,
+	MPUREG_I2C_SLV3_ADDR,	/* 0x2E */
+	MPUREG_I2C_SLV3_REG,
+	MPUREG_I2C_SLV3_CTRL,
+	MPUREG_I2C_SLV4_ADDR,	/* 0x31 */
+	MPUREG_I2C_SLV4_REG,
+	MPUREG_I2C_SLV4_DO,
+	MPUREG_I2C_SLV4_CTRL,
+	MPUREG_I2C_SLV4_DI,
+	MPUREG_I2C_MST_STATUS,	/* 0x36 */
+	MPUREG_INT_PIN_CFG,	/* 0x37 ==> -* INT_CFG */
+	MPUREG_INT_ENABLE,	/* 0x38 ==> / */
+	MPUREG_DMP_INT_STATUS,	/* 0x39 */
+	MPUREG_INT_STATUS,	/* 0x3A */
+	MPUREG_ACCEL_XOUT_H,	/* 0x3B */
+	MPUREG_ACCEL_XOUT_L,
+	MPUREG_ACCEL_YOUT_H,
+	MPUREG_ACCEL_YOUT_L,
+	MPUREG_ACCEL_ZOUT_H,
+	MPUREG_ACCEL_ZOUT_L,
+	MPUREG_TEMP_OUT_H,	/* 0x41 */
+	MPUREG_TEMP_OUT_L,
+	MPUREG_GYRO_XOUT_H,	/* 0x43 */
+	MPUREG_GYRO_XOUT_L,
+	MPUREG_GYRO_YOUT_H,
+	MPUREG_GYRO_YOUT_L,
+	MPUREG_GYRO_ZOUT_H,
+	MPUREG_GYRO_ZOUT_L,
+	MPUREG_EXT_SLV_SENS_DATA_00,	/* 0x49 */
+	MPUREG_EXT_SLV_SENS_DATA_01,
+	MPUREG_EXT_SLV_SENS_DATA_02,
+	MPUREG_EXT_SLV_SENS_DATA_03,
+	MPUREG_EXT_SLV_SENS_DATA_04,
+	MPUREG_EXT_SLV_SENS_DATA_05,
+	MPUREG_EXT_SLV_SENS_DATA_06,	/* 0x4F */
+	MPUREG_EXT_SLV_SENS_DATA_07,
+	MPUREG_EXT_SLV_SENS_DATA_08,
+	MPUREG_EXT_SLV_SENS_DATA_09,
+	MPUREG_EXT_SLV_SENS_DATA_10,
+	MPUREG_EXT_SLV_SENS_DATA_11,
+	MPUREG_EXT_SLV_SENS_DATA_12,	/* 0x55 */
+	MPUREG_EXT_SLV_SENS_DATA_13,
+	MPUREG_EXT_SLV_SENS_DATA_14,
+	MPUREG_EXT_SLV_SENS_DATA_15,
+	MPUREG_EXT_SLV_SENS_DATA_16,
+	MPUREG_EXT_SLV_SENS_DATA_17,
+	MPUREG_EXT_SLV_SENS_DATA_18,	/* 0x5B */
+	MPUREG_EXT_SLV_SENS_DATA_19,
+	MPUREG_EXT_SLV_SENS_DATA_20,
+	MPUREG_EXT_SLV_SENS_DATA_21,
+	MPUREG_EXT_SLV_SENS_DATA_22,
+	MPUREG_EXT_SLV_SENS_DATA_23,
+	ACCEL_INTEL_STATUS,	/* 0x61 */
+	MPUREG_62_RSVD,
+	MPUREG_63_RSVD,
+	MPUREG_64_RSVD,
+	MPUREG_65_RSVD,
+	MPUREG_66_RSVD,
+	MPUREG_67_RSVD,
+	SIGNAL_PATH_RESET,	/* 0x68 */
+	ACCEL_INTEL_CTRL,	/* 0x69 */
+	MPUREG_USER_CTRL,	/* 0x6A */
+	MPUREG_PWR_MGMT_1,	/* 0x6B */
+	MPUREG_PWR_MGMT_2,
+	MPUREG_BANK_SEL,	/* 0x6D */
+	MPUREG_MEM_START_ADDR,	/* 0x6E */
+	MPUREG_MEM_R_W,		/* 0x6F */
+	MPUREG_PRGM_STRT_ADDRH,
+	MPUREG_PRGM_STRT_ADDRL,
+	MPUREG_FIFO_COUNTH,	/* 0x72 */
+	MPUREG_FIFO_COUNTL,
+	MPUREG_FIFO_R_W,	/* 0x74 */
+	MPUREG_WHOAMI,		/* 0x75,117 */
+
+	NUM_OF_MPU_REGISTERS	/* = 0x76,118 */
+};
+
+/*==== M_HW MEMORY ====*/
+enum MPU_MEMORY_BANKS {
+	MEM_RAM_BANK_0 = 0,
+	MEM_RAM_BANK_1,
+	MEM_RAM_BANK_2,
+	MEM_RAM_BANK_3,
+	MEM_RAM_BANK_4,
+	MEM_RAM_BANK_5,
+	MEM_RAM_BANK_6,
+	MEM_RAM_BANK_7,
+	MEM_RAM_BANK_8,
+	MEM_RAM_BANK_9,
+	MEM_RAM_BANK_10,
+	MEM_RAM_BANK_11,
+	MPU_MEM_NUM_RAM_BANKS,
+	MPU_MEM_OTP_BANK_0 = 16
+};
+
+
+/*==== M_HW parameters ====*/
+
+#define NUM_REGS            (NUM_OF_MPU_REGISTERS)
+#define START_SENS_REGS     (0x3B)
+#define NUM_SENS_REGS       (0x60-START_SENS_REGS+1)
+
+/*---- MPU Memory ----*/
+#define NUM_BANKS           (MPU_MEM_NUM_RAM_BANKS)
+#define BANK_SIZE           (256)
+#define MEM_SIZE            (NUM_BANKS*BANK_SIZE)
+#define MPU_MEM_BANK_SIZE   (BANK_SIZE)	/*alternative name */
+
+#define FIFO_HW_SIZE        (1024)
+
+#define NUM_EXT_SLAVES      (4)
+
+
+/*==== BITS FOR M_HW ====*/
+
+/*---- M_HW 'FIFO_EN' register (23) ----*/
+#define	BIT_TEMP_OUT				0x80
+#define	BIT_GYRO_XOUT				0x40
+#define	BIT_GYRO_YOUT				0x20
+#define	BIT_GYRO_ZOUT				0x10
+#define	BIT_ACCEL				0x08
+#define	BIT_SLV_2				0x04
+#define	BIT_SLV_1				0x02
+#define	BIT_SLV_0				0x01
+/*---- M_HW 'CONFIG' register (1A) ----*/
+/*NONE                              		0xC0 */
+#define	BITS_EXT_SYNC_SET			0x38
+#define	BITS_DLPF_CFG				0x07
+/*---- M_HW 'GYRO_CONFIG' register (1B) ----*/
+/* voluntarily modified label from BITS_FS_SEL to
+ * BITS_GYRO_FS_SEL to avoid confusion with MPU
+ */
+#define BITS_GYRO_FS_SEL            		0x18
+/*NONE                              		0x07 */
+/*---- M_HW 'ACCEL_CONFIG' register (1C) ----*/
+#define BITS_ACCEL_FS_SEL           		0x18
+#define BITS_ACCEL_HPF              		0x07
+/*---- M_HW 'I2C_MST_CTRL' register (24) ----*/
+#define BIT_MULT_MST_DIS            		0x80
+#define BIT_WAIT_FOR_ES             		0x40
+#define BIT_I2C_MST_VDDIO           		0x20
+/*NONE                              		0x10 */
+#define BITS_I2C_MST_CLK            		0x0F
+/*---- M_HW 'I2C_SLV?_CTRL' register (27,2A,2D,30) ----*/
+#define BIT_SLV_ENABLE              		0x80
+#define BIT_SLV_BYTE_SW             		0x40
+/*NONE                              		0x20 */
+#define BIT_SLV_GRP                 		0x10
+#define BITS_SLV_LENG               		0x0F
+/*---- M_HW 'I2C_SLV4_ADDR' register (31) ----*/
+#define BIT_I2C_SLV4_RNW            		0x80
+/*---- M_HW 'I2C_SLV4_CTRL' register (34) ----*/
+#define BIT_I2C_SLV4_EN             		0x80
+#define BIT_SLV4_DONE_INT_EN        		0x40
+/*NONE                              		0x3F */
+/*---- M_HW 'I2C_MST_STATUS' register (36) ----*/
+#define BIT_PASSTHROUGH             		0x80
+#define BIT_I2C_SLV4_DONE           		0x40
+#define BIT_I2C_LOST_ARB            		0x20
+#define BIT_I2C_SLV4_NACK           		0x10
+#define BIT_I2C_SLV3_NACK           		0x08
+#define BIT_I2C_SLV2_NACK           		0x04
+#define BIT_I2C_SLV1_NACK           		0x02
+#define BIT_I2C_SLV0_NACK           		0x01
+/*---- M_HW 'INT_PIN_CFG' register (37) ----*/
+#define	BIT_ACTL				0x80
+#define BIT_ACTL_LOW				0x80
+#define BIT_ACTL_HIGH				0x00
+#define	BIT_OPEN				0x40
+#define	BIT_LATCH_INT_EN			0x20
+#define	BIT_INT_ANYRD_2CLEAR			0x10
+#define	BIT_ACTL_FSYNC				0x08
+#define	BIT_FSYNC_INT_EN 			0x04
+#define	BIT_BYPASS_EN    			0x02
+#define	BIT_CLKOUT_EN				0x01
+/*---- M_HW 'INT_ENABLE' register (38) ----*/
+#define	BIT_FF_EN				0x80
+#define	BIT_MOT_EN				0x40
+#define	BIT_ZMOT_EN				0x20
+#define	BIT_FIFO_OVERFLOW_EN			0x10
+#define BIT_I2C_MST_INT_EN			0x08
+#define	BIT_PLL_RDY_EN				0x04
+#define BIT_DMP_INT_EN				0x02
+#define	BIT_RAW_RDY_EN				0x01
+/*---- M_HW 'DMP_INT_STATUS' register (39) ----*/
+/*NONE                                          0x80 */
+/*NONE                                          0x40 */
+#define	BIT_DMP_INT_5				0x20
+#define	BIT_DMP_INT_4				0x10
+#define	BIT_DMP_INT_3				0x08
+#define	BIT_DMP_INT_2 				0x04
+#define	BIT_DMP_INT_1				0x02
+#define	BIT_DMP_INT_0				0x01
+/*---- M_HW 'INT_STATUS' register (3A) ----*/
+#define	BIT_FF_INT				0x80
+#define	BIT_MOT_INT				0x40
+#define	BIT_ZMOT_INT				0x20
+#define	BIT_FIFO_OVERFLOW_INT			0x10
+#define	BIT_I2C_MST_INT				0x08
+#define	BIT_PLL_RDY_INT 			0x04
+#define BIT_DMP_INT				0x02
+#define	BIT_RAW_DATA_RDY_INT			0x01
+/*---- M_HW 'BANK_SEL' register (6D) ----*/
+#define	BIT_PRFTCH_EN				0x40
+#define	BIT_CFG_USER_BANK			0x20
+#define	BITS_MEM_SEL				0x1f
+/*---- M_HW 'USER_CTRL' register (6A) ----*/
+#define	BIT_DMP_EN				0x80
+#define	BIT_FIFO_EN				0x40
+#define	BIT_I2C_MST_EN				0x20
+#define	BIT_I2C_IF_DIS				0x10
+#define	BIT_DMP_RST				0x08
+#define	BIT_FIFO_RST				0x04
+#define	BIT_I2C_MST_RST				0x02
+#define	BIT_SIG_COND_RST			0x01
+/*---- M_HW 'PWR_MGMT_1' register (6B) ----*/
+#define	BIT_H_RESET				0x80
+#define BITS_PWRSEL                 		0x70
+#define BIT_WKUP_INT                		0x08
+#define BITS_CLKSEL				0x07
+/*---- M_HW 'PWR_MGMT_2' register (6C) ----*/
+#define BITS_LPA_WAKE_CTRL          		0xC0
+#define	BIT_STBY_XA				0x20
+#define	BIT_STBY_YA				0x10
+#define	BIT_STBY_ZA				0x08
+#define	BIT_STBY_XG				0x04
+#define	BIT_STBY_YG				0x02
+#define	BIT_STBY_ZG				0x01
+
+/* although it has 6, this refers to the gyros */
+#define MPU_NUM_AXES (3)
+
+/*----------------------------------------------------------------------------*/
+/*---- Alternative names to take care of conflicts with current mpu3050.h ----*/
+/*----------------------------------------------------------------------------*/
+
+/*-- registers --*/
+#define MPUREG_DLPF_FS_SYNC        MPUREG_CONFIG		/* 0x1A */
+
+#define MPUREG_PRODUCT_ID          MPUREG_WHOAMI		/* 0x75  HACK!*/
+#define MPUREG_PWR_MGM             MPUREG_PWR_MGMT_1		/* 0x6B */
+#define MPUREG_FIFO_EN1            MPUREG_FIFO_EN		/* 0x23 */
+#define MPUREG_DMP_CFG_1           MPUREG_PRGM_STRT_ADDRH	/* 0x70 */
+#define MPUREG_DMP_CFG_2           MPUREG_PRGM_STRT_ADDRL	/* 0x71 */
+#define MPUREG_INT_CFG             MPUREG_INT_ENABLE		/* 0x38 */
+#define MPUREG_X_OFFS_USRH         MPUREG_XG_OFFS_USRH		/* 0x13 */
+#define MPUREG_WHO_AM_I            MPUREG_WHOAMI		/* 0x75 */
+#define MPUREG_23_RSVD             MPUREG_EXT_SLV_SENS_DATA_00	/* 0x49 */
+#define MPUREG_AUX_SLV_ADDR        MPUREG_I2C_SLV0_ADDR		/* 0x25 */
+#define MPUREG_ACCEL_BURST_ADDR    MPUREG_I2C_SLV0_REG		/* 0x26 */
+
+/*-- bits --*/
+/* 'USER_CTRL' register */
+#define BIT_AUX_IF_EN               BIT_I2C_MST_EN
+#define BIT_AUX_RD_LENG             BIT_I2C_MST_EN
+#define BIT_IME_IF_RST              BIT_I2C_MST_RST
+#define BIT_GYRO_RST                BIT_SIG_COND_RST
+/* 'INT_ENABLE' register */
+#define BIT_RAW_RDY                 BIT_RAW_DATA_RDY_INT
+#define BIT_MPU_RDY_EN              BIT_PLL_RDY_EN
+/* 'INT_STATUS' register */
+#define BIT_INT_STATUS_FIFO_OVERLOW BIT_FIFO_OVERFLOW_INT
+
+
+
+/*---- M_HW Silicon Revisions ----*/
+#define MPU_SILICON_REV_A1           1	/* M_HW A1 Device */
+#define MPU_SILICON_REV_B1           2	/* M_HW B1 Device */
+
+/*---- structure containing control variables used by MLDL ----*/
+/*---- MPU clock source settings ----*/
+/*---- MPU filter selections ----*/
+enum mpu_filter {
+	MPU_FILTER_256HZ_NOLPF2 = 0,
+	MPU_FILTER_188HZ,
+	MPU_FILTER_98HZ,
+	MPU_FILTER_42HZ,
+	MPU_FILTER_20HZ,
+	MPU_FILTER_10HZ,
+	MPU_FILTER_5HZ,
+	MPU_FILTER_2100HZ_NOLPF,
+	NUM_MPU_FILTER
+};
+
+enum mpu_fullscale {
+	MPU_FS_250DPS = 0,
+	MPU_FS_500DPS,
+	MPU_FS_1000DPS,
+	MPU_FS_2000DPS,
+	NUM_MPU_FS
+};
+
+enum mpu_clock_sel {
+	MPU_CLK_SEL_INTERNAL = 0,
+	MPU_CLK_SEL_PLLGYROX,
+	MPU_CLK_SEL_PLLGYROY,
+	MPU_CLK_SEL_PLLGYROZ,
+	MPU_CLK_SEL_PLLEXT32K,
+	MPU_CLK_SEL_PLLEXT19M,
+	MPU_CLK_SEL_RESERVED,
+	MPU_CLK_SEL_STOP,
+	NUM_CLK_SEL
+};
+
+enum mpu_ext_sync {
+	MPU_EXT_SYNC_NONE = 0,
+	MPU_EXT_SYNC_TEMP,
+	MPU_EXT_SYNC_GYROX,
+	MPU_EXT_SYNC_GYROY,
+	MPU_EXT_SYNC_GYROZ,
+	MPU_EXT_SYNC_ACCELX,
+	MPU_EXT_SYNC_ACCELY,
+	MPU_EXT_SYNC_ACCELZ,
+	NUM_MPU_EXT_SYNC
+};
+
+#define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \
+    ((ext_sync << 5) | (full_scale << 3) | lpf)
+
+#endif				/* __IMU6000_H_ */
diff --git a/include/linux/regulator/max8907c-regulator.h b/include/linux/regulator/max8907c-regulator.h
new file mode 100644
index 000000000000..ddc5f0a60339
--- /dev/null
+++ b/include/linux/regulator/max8907c-regulator.h
@@ -0,0 +1,46 @@
+/* linux/regulator/max8907c-regulator.h
+ *
+ * Functions to access MAX8907C power management chip.
+ *
+ * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_REGULATOR_MAX8907C_H
+#define __LINUX_REGULATOR_MAX8907C_H
+
+/* IDs */
+#define MAX8907C_SD1    0
+#define MAX8907C_SD2    1
+#define MAX8907C_SD3    2
+#define MAX8907C_LDO1   3
+#define MAX8907C_LDO2   4
+#define MAX8907C_LDO3   5
+#define MAX8907C_LDO4   6
+#define MAX8907C_LDO5   7
+#define MAX8907C_LDO6   8
+#define MAX8907C_LDO7   9
+#define MAX8907C_LDO8   10
+#define MAX8907C_LDO9   11
+#define MAX8907C_LDO10  12
+#define MAX8907C_LDO11  13
+#define MAX8907C_LDO12  14
+#define MAX8907C_LDO13  15
+#define MAX8907C_LDO14  16
+#define MAX8907C_LDO15  17
+#define MAX8907C_LDO16  18
+#define MAX8907C_LDO17  19
+#define MAX8907C_LDO18  20
+#define MAX8907C_LDO19  21
+#define MAX8907C_LDO20  22
+#define MAX8907C_OUT5V  23
+#define MAX8907C_OUT33V 24
+#define MAX8907C_BBAT   25
+#define MAX8907C_SDBY   26
+#define MAX8907C_VRTC   27
+#define MAX8907C_WLED   27
+
+#endif
diff --git a/include/linux/regulator/max8952.h b/include/linux/regulator/max8952.h
new file mode 100644
index 000000000000..abe50beb1b55
--- /dev/null
+++ b/include/linux/regulator/max8952.h
@@ -0,0 +1,40 @@
+/* linux/regulator/max8952.h
+ *
+ * Functions to access MAX8952 power management chip.
+ *
+ * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_REGULATOR_MAX8952_H
+#define __LINUX_REGULATOR_MAX8952_H
+
+/* Regiater map */
+#define MAX8952_REG_MODE0           0x00
+#define MAX8952_REG_MODE1           0x01
+#define MAX8952_REG_MODE2           0x02
+#define MAX8952_REG_MODE3           0x03
+#define MAX8952_REG_CONTROL         0x04
+#define MAX8952_REG_SYNC            0x05
+#define MAX8952_REG_RAMP            0x06
+#define MAX8952_REG_CHIP_ID1        0x08
+#define MAX8952_REG_CHIP_ID2        0x09
+
+/* Register bit-mask */
+#define MAX8952_MASK_OUTMODE    0x3F
+
+/* IDs */
+#define MAX8952_MODE0   0
+#define MAX8952_MODE1   1
+#define MAX8952_MODE2   2
+#define MAX8952_MODE3   3
+
+struct max8952_platform_data {
+	int num_subdevs;
+	struct platform_device **subdevs;
+};
+
+#endif
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 7b8a09e2ec7f..bb76e8c12d29 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -45,7 +45,8 @@
 #define PORT_OCTEON	17	/* Cavium OCTEON internal UART */
 #define PORT_AR7	18	/* Texas Instruments AR7 internal UART */
 #define PORT_U6_16550A	19	/* ST-Ericsson U6xxx internal UART */
-#define PORT_MAX_8250	19	/* max port ID */
+#define PORT_TEGRA	20	/* NVIDIA Tegra internal UART */
+#define PORT_MAX_8250	20	/* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed
diff --git a/include/linux/tegra_audio.h b/include/linux/tegra_audio.h
index db4661aacb4f..215cfef62f7d 100644
--- a/include/linux/tegra_audio.h
+++ b/include/linux/tegra_audio.h
@@ -31,6 +31,45 @@ struct tegra_audio_in_config {
 	int stereo;
 };
 
+enum tegra_audio_device {
+	TEGRA_AUDIO_DEVICE_NONE = 0x00000000,
+	TEGRA_AUDIO_DEVICE_OUT_HEADPHONE = 0x00000001,
+	TEGRA_AUDIO_DEVICE_OUT_HEADSET = 0x00000002,
+	TEGRA_AUDIO_DEVICE_OUT_SPEAKER = 0x00000004,
+	TEGRA_AUDIO_DEVICE_OUT_EAR_SPEAKER = 0x00000008,
+	TEGRA_AUDIO_DEVICE_OUT_LINE = 0x00000010,
+	TEGRA_AUDIO_DEVICE_OUT_BT_SCO = 0x00000020,
+	TEGRA_AUDIO_DEVICE_OUT_AUX_DIGITAL = 0x00000040,
+	TEGRA_AUDIO_DEVICE_OUT_RADIO = 0x00000080,
+	TEGRA_AUDIO_DEVICE_OUT_ALL = TEGRA_AUDIO_DEVICE_OUT_HEADPHONE |
+				TEGRA_AUDIO_DEVICE_OUT_HEADSET |
+				TEGRA_AUDIO_DEVICE_OUT_SPEAKER |
+				TEGRA_AUDIO_DEVICE_OUT_EAR_SPEAKER |
+				TEGRA_AUDIO_DEVICE_OUT_LINE |
+				TEGRA_AUDIO_DEVICE_OUT_BT_SCO |
+				TEGRA_AUDIO_DEVICE_OUT_AUX_DIGITAL |
+				TEGRA_AUDIO_DEVICE_OUT_RADIO,
+	TEGRA_AUDIO_DEVICE_IN_BUILTIN_MIC = 0x00010000,
+	TEGRA_AUDIO_DEVICE_IN_MIC = 0x00020000,
+	TEGRA_AUDIO_DEVICE_IN_HEADSET = 0x00040000,
+	TEGRA_AUDIO_DEVICE_IN_BACK_MIC = 0x00080000,
+	TEGRA_AUDIO_DEVICE_IN_LINE = 0x00100000,
+	TEGRA_AUDIO_DEVICE_IN_BT_SCO = 0x00200000,
+	TEGRA_AUDIO_DEVICE_IN_AUX_DIGITAL = 0x00400000,
+	TEGRA_AUDIO_DEVICE_IN_PHONE = 0x00800000,
+	TEGRA_AUDIO_DEVICE_IN_RADIO = 0x01000000,
+	TEGRA_AUDIO_DEVICE_IN_ALL = TEGRA_AUDIO_DEVICE_IN_BUILTIN_MIC |
+				TEGRA_AUDIO_DEVICE_IN_MIC |
+				TEGRA_AUDIO_DEVICE_IN_HEADSET |
+				TEGRA_AUDIO_DEVICE_IN_BACK_MIC |
+				TEGRA_AUDIO_DEVICE_IN_LINE |
+				TEGRA_AUDIO_DEVICE_IN_BT_SCO |
+				TEGRA_AUDIO_DEVICE_IN_AUX_DIGITAL |
+				TEGRA_AUDIO_DEVICE_IN_PHONE |
+				TEGRA_AUDIO_DEVICE_IN_RADIO,
+	TEGRA_AUDIO_DEVICE_MAX = 0x7FFFFFFF
+};
+
 #define TEGRA_AUDIO_IN_SET_CONFIG	_IOW(TEGRA_AUDIO_MAGIC, 2, \
 			const struct tegra_audio_in_config *)
 #define TEGRA_AUDIO_IN_GET_CONFIG	_IOR(TEGRA_AUDIO_MAGIC, 3, \
diff --git a/include/linux/tegra_overlay.h b/include/linux/tegra_overlay.h
new file mode 100644
index 000000000000..673a40f832c0
--- /dev/null
+++ b/include/linux/tegra_overlay.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (C) 2010 NVIDIA Corporation
+ * Author: Dan Willemsen <dwillemsen@nvidia.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __LINUX_TEGRA_OVERLAY_H
+#define __LINUX_TEGRA_OVERLAY_H
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+#include <video/tegrafb.h>
+
+/* set index to -1 to ignore window data */
+struct tegra_overlay_windowattr {
+	__s32	index;
+	__u32	buff_id;
+	__u32	blend;
+	__u32	offset;
+	__u32	offset_u;
+	__u32	offset_v;
+	__u32	stride;
+	__u32	stride_uv;
+	__u32	pixformat;
+	__u32	x;
+	__u32	y;
+	__u32	w;
+	__u32	h;
+	__u32	out_x;
+	__u32	out_y;
+	__u32	out_w;
+	__u32	out_h;
+	__u32	z;
+	__u32	pre_syncpt_id;
+	__u32	pre_syncpt_val;
+	__u32	hfilter;
+	__u32	vfilter;
+	__u32	tiled;
+	__u32	flags;
+};
+
+struct tegra_overlay_flip_args {
+	struct tegra_overlay_windowattr win[TEGRA_FB_FLIP_N_WINDOWS];
+	__u32 post_syncpt_id;
+	__u32 post_syncpt_val;
+};
+
+#define TEGRA_OVERLAY_IOCTL_MAGIC		'O'
+
+#define TEGRA_OVERLAY_IOCTL_OPEN_WINDOW		_IOWR(TEGRA_OVERLAY_IOCTL_MAGIC, 0x40, __u32)
+#define TEGRA_OVERLAY_IOCTL_CLOSE_WINDOW	_IOW(TEGRA_OVERLAY_IOCTL_MAGIC, 0x41, __u32)
+#define TEGRA_OVERLAY_IOCTL_FLIP		_IOW(TEGRA_OVERLAY_IOCTL_MAGIC, 0x42, struct tegra_overlay_flip_args)
+#define TEGRA_OVERLAY_IOCTL_SET_NVMAP_FD	_IOW(TEGRA_OVERLAY_IOCTL_MAGIC, 0x43, __u32)
+
+#define TEGRA_OVERLAY_IOCTL_MIN_NR		_IOC_NR(TEGRA_OVERLAY_IOCTL_OPEN_WINDOW)
+#define TEGRA_OVERLAY_IOCTL_MAX_NR		_IOC_NR(TEGRA_OVERLAY_IOCTL_SET_NVMAP_FD)
+
+#endif
diff --git a/include/linux/tegra_uart.h b/include/linux/tegra_uart.h
new file mode 100644
index 000000000000..b33bbb6f366a
--- /dev/null
+++ b/include/linux/tegra_uart.h
@@ -0,0 +1,27 @@
+/* include/linux/tegra_uart.h
+ *
+ * Copyright (C) 2011 NVIDIA Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef _TEGRA_UART_H_
+#define _TEGRA_UART_H_
+
+struct tegra_uart_platform_data {
+	void (*wake_peer)(struct uart_port *);
+};
+
+#endif /* _TEGRA_UART_H_ */
diff --git a/include/linux/tegra_usb.h b/include/linux/tegra_usb.h
index 2947ed26879a..6ae8c1e85229 100644
--- a/include/linux/tegra_usb.h
+++ b/include/linux/tegra_usb.h
@@ -32,4 +32,9 @@ struct tegra_ehci_platform_data {
 	void *phy_config;
 };
 
+struct tegra_otg_platform_data {
+	struct platform_device* (*host_register)(void);
+	void (*host_unregister)(struct platform_device*);
+};
+
 #endif /* _TEGRA_USB_H_ */
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 35fe6ab222bb..cd07173c1bc0 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -975,6 +975,7 @@ extern int usb_disabled(void);
 #define URB_SETUP_MAP_SINGLE	0x00100000	/* Setup packet DMA mapped */
 #define URB_SETUP_MAP_LOCAL	0x00200000	/* HCD-local setup packet */
 #define URB_DMA_SG_COMBINED	0x00400000	/* S-G entries were combined */
+#define URB_DRIVER_PRIVATE	0x80000000	/* For driver-private use */
 
 struct usb_iso_packet_descriptor {
 	unsigned int offset;
diff --git a/include/linux/usb/hcd.h b/include/linux/usb/hcd.h
index 3b571f1ffbb3..8aaf6872949f 100644
--- a/include/linux/usb/hcd.h
+++ b/include/linux/usb/hcd.h
@@ -233,6 +233,11 @@ struct hc_driver {
 	int	(*urb_dequeue)(struct usb_hcd *hcd,
 				struct urb *urb, int status);
 
+	/* dma support */
+	int	(*map_urb_for_dma)(struct usb_hcd *hcd, struct urb *urb,
+				   gfp_t mem_flags);
+	void    (*unmap_urb_for_dma)(struct usb_hcd *hcd, struct urb *urb);
+
 	/* hw synch, freeing endpoint resources that urb_dequeue can't */
 	void	(*endpoint_disable)(struct usb_hcd *hcd,
 			struct usb_host_endpoint *ep);
@@ -327,6 +332,9 @@ extern void usb_hcd_unlink_urb_from_ep(struct usb_hcd *hcd, struct urb *urb);
 
 extern int usb_hcd_submit_urb(struct urb *urb, gfp_t mem_flags);
 extern int usb_hcd_unlink_urb(struct urb *urb, int status);
+extern int usb_hcd_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
+		gfp_t mem_flags);
+extern void usb_hcd_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb);
 extern void usb_hcd_giveback_urb(struct usb_hcd *hcd, struct urb *urb,
 		int status);
 extern void usb_hcd_flush_endpoint(struct usb_device *udev,
diff --git a/include/linux/wakelock.h b/include/linux/wakelock.h
index a096d24ada1d..a096d24ada1d 100755..100644
--- a/include/linux/wakelock.h
+++ b/include/linux/wakelock.h
diff --git a/include/media/ov5650.h b/include/media/ov5650.h
new file mode 100644
index 000000000000..cc3ec7194526
--- /dev/null
+++ b/include/media/ov5650.h
@@ -0,0 +1,38 @@
+/**
+ * Copyright (c) 2008 NVIDIA Corporation.  All rights reserved.
+ *
+ * NVIDIA Corporation and its licensors retain all intellectual property
+ * and proprietary rights in and to this software and related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA Corporation is strictly prohibited.
+ */
+
+#ifndef __OV5650_H__
+#define __OV5650_H__
+
+#include <linux/ioctl.h>  /* For IOCTL macros */
+
+#define OV5650_IOCTL_SET_MODE		_IOW('o', 1, struct ov5650_mode)
+#define OV5650_IOCTL_SET_FRAME_LENGTH	_IOW('o', 2, __u32)
+#define OV5650_IOCTL_SET_COARSE_TIME	_IOW('o', 3, __u32)
+#define OV5650_IOCTL_SET_GAIN		_IOW('o', 4, __u16)
+#define OV5650_IOCTL_GET_STATUS		_IOR('o', 5, __u8)
+
+struct ov5650_mode {
+	int xres;
+	int yres;
+	__u32 frame_length;
+	__u32 coarse_time;
+	__u16 gain;
+};
+#ifdef __KERNEL__
+struct ov5650_platform_data {
+	int (*power_on)(void);
+	int (*power_off)(void);
+
+};
+#endif /* __KERNEL__ */
+
+#endif  /* __OV5650_H__ */
+
diff --git a/include/video/nvhdcp.h b/include/video/nvhdcp.h
new file mode 100644
index 000000000000..f282ff8caa99
--- /dev/null
+++ b/include/video/nvhdcp.h
@@ -0,0 +1,91 @@
+/*
+ * include/video/nvhdcp.h
+ *
+ * Copyright (c) 2010-2011, NVIDIA Corporation.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_NVHDCP_H_
+#define _LINUX_NVHDCP_H_
+
+#include <linux/fb.h>
+#include <linux/types.h>
+#include <asm/ioctl.h>
+
+/* maximum receivers and repeaters connected at a time */
+#define TEGRA_NVHDCP_MAX_DEVS	127
+
+/* values for value_flags */
+#define TEGRA_NVHDCP_FLAG_AN			0x0001
+#define TEGRA_NVHDCP_FLAG_AKSV			0x0002
+#define TEGRA_NVHDCP_FLAG_BKSV			0x0004
+#define TEGRA_NVHDCP_FLAG_BSTATUS		0x0008 /* repeater status */
+#define TEGRA_NVHDCP_FLAG_CN			0x0010 /* c_n */
+#define TEGRA_NVHDCP_FLAG_CKSV			0x0020 /* c_ksv */
+#define TEGRA_NVHDCP_FLAG_DKSV			0x0040 /* d_ksv */
+#define TEGRA_NVHDCP_FLAG_KP			0x0080 /* k_prime */
+#define TEGRA_NVHDCP_FLAG_S			0x0100 /* hdcp_status */
+#define TEGRA_NVHDCP_FLAG_CS			0x0200 /* connection state */
+#define TEGRA_NVHDCP_FLAG_V			0x0400
+#define TEGRA_NVHDCP_FLAG_MP			0x0800
+#define TEGRA_NVHDCP_FLAG_BKSVLIST		0x1000
+
+/* values for packet_results */
+#define TEGRA_NVHDCP_RESULT_SUCCESS		0
+#define TEGRA_NVHDCP_RESULT_UNSUCCESSFUL	1
+#define TEGRA_NVHDCP_RESULT_PENDING		0x103
+#define TEGRA_NVHDCP_RESULT_LINK_FAILED		0xc0000013
+/* TODO: replace with -EINVAL */
+#define TEGRA_NVHDCP_RESULT_INVALID_PARAMETER	0xc000000d
+#define TEGRA_NVHDCP_RESULT_INVALID_PARAMETER_MIX	0xc0000030
+/* TODO: replace with -ENOMEM */
+#define TEGRA_NVHDCP_RESULT_NO_MEMORY		0xc0000017
+
+struct tegra_nvhdcp_packet {
+	__u32	value_flags;		// (IN/OUT)
+	__u32	packet_results;		// (OUT)
+
+	__u64	c_n;			// (IN) upstream exchange number
+	__u64	c_ksv;			// (IN)
+
+	__u32	b_status;	// (OUT) link/repeater status
+	__u64	hdcp_status;	// (OUT) READ_S
+	__u64	cs;		// (OUT) Connection State
+
+	__u64	k_prime;	// (OUT)
+	__u64	a_n;		// (OUT)
+	__u64	a_ksv;		// (OUT)
+	__u64	b_ksv;		// (OUT)
+	__u64	d_ksv;		// (OUT)
+	__u8	v_prime[20];	// (OUT) 160-bit
+	__u64	m_prime;	// (OUT)
+
+	// (OUT) Valid KSVs in the bKsvList. Maximum is 127 devices
+	__u32	num_bksv_list;
+
+	// (OUT) Up to 127 receivers & repeaters
+	__u64	bksv_list[TEGRA_NVHDCP_MAX_DEVS];
+};
+
+/* parameters to TEGRAIO_NVHDCP_SET_POLICY */
+#define TEGRA_NVHDCP_POLICY_ON_DEMAND	0
+#define TEGRA_NVHDCP_POLICY_ALWAYS_ON	1
+
+/* ioctls */
+#define TEGRAIO_NVHDCP_ON		_IO('F', 0x70)
+#define TEGRAIO_NVHDCP_OFF		_IO('F', 0x71)
+#define TEGRAIO_NVHDCP_SET_POLICY	_IOW('F', 0x72, __u32)
+#define TEGRAIO_NVHDCP_READ_M		_IOWR('F', 0x73, struct tegra_nvhdcp_packet)
+#define TEGRAIO_NVHDCP_READ_S		_IOWR('F', 0x74, struct tegra_nvhdcp_packet)
+#define TEGRAIO_NVHDCP_RENEGOTIATE	_IO('F', 0x75)
+
+#endif
diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index 3e598e756e54..ba426cd21390 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -40,6 +40,7 @@ source "sound/soc/s3c24xx/Kconfig"
 source "sound/soc/s6000/Kconfig"
 source "sound/soc/sh/Kconfig"
 source "sound/soc/txx9/Kconfig"
+source "sound/soc/tegra/Kconfig"
 
 # Supported codecs
 source "sound/soc/codecs/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index eb183443eee4..d4d25076ea14 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -18,3 +18,4 @@ obj-$(CONFIG_SND_SOC)	+= s3c24xx/
 obj-$(CONFIG_SND_SOC)	+= s6000/
 obj-$(CONFIG_SND_SOC)	+= sh/
 obj-$(CONFIG_SND_SOC)	+= txx9/
+obj-$(CONFIG_SND_SOC)	+= tegra/
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index 83f5c67d3c41..cf3fe9b7b12e 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -222,7 +222,7 @@ config SND_SOC_WM8750
 	tristate
 
 config SND_SOC_WM8753
-	tristate
+	tristate "WM8753 Codec"
 
 config SND_SOC_WM8776
 	tristate
@@ -231,7 +231,7 @@ config SND_SOC_WM8900
 	tristate
 
 config SND_SOC_WM8903
-	tristate
+	tristate "WM8903 Codec"
 
 config SND_SOC_WM8904
 	tristate
diff --git a/sound/soc/codecs/wm8903.c b/sound/soc/codecs/wm8903.c
index bf08282d5ee5..dbe9b52456ef 100644
--- a/sound/soc/codecs/wm8903.c
+++ b/sound/soc/codecs/wm8903.c
@@ -945,6 +945,7 @@ static int wm8903_set_bias_level(struct snd_soc_codec *codec,
 		reg &= ~(WM8903_VMID_RES_MASK);
 		reg |= WM8903_VMID_RES_50K;
 		snd_soc_write(codec, WM8903_VMID_CONTROL_0, reg);
+		snd_soc_write(codec, WM8903_BIAS_CONTROL_0, 0xB);
 		break;
 
 	case SND_SOC_BIAS_STANDBY:
diff --git a/sound/soc/tegra/Kconfig b/sound/soc/tegra/Kconfig
new file mode 100644
index 000000000000..09d1d26450c8
--- /dev/null
+++ b/sound/soc/tegra/Kconfig
@@ -0,0 +1,17 @@
+config TEGRA_ALSA
+    tristate "Tegra ALSA SoC support"
+    select TEGRA_PCM
+    select TEGRA_I2S
+    select TEGRA_IEC
+    help
+       Say Y if you for ALSA SoC support
+
+config TEGRA_PCM
+    tristate "Tegra ALSA pcm callbacks"
+
+config TEGRA_I2S
+    tristate "Tegra I2S"
+
+config TEGRA_IEC
+    tristate "Tegra IEC"
+
diff --git a/sound/soc/tegra/Makefile b/sound/soc/tegra/Makefile
new file mode 100644
index 000000000000..d7fa52bc28f2
--- /dev/null
+++ b/sound/soc/tegra/Makefile
@@ -0,0 +1,8 @@
+ccflags-y                       += -DNV_DEBUG=0
+obj-$(CONFIG_TEGRA_PCM)         += tegra_pcm.o
+obj-$(CONFIG_TEGRA_I2S)         += tegra_i2s.o
+obj-$(CONFIG_TEGRA_ALSA)        += tegra_soc_controls.o
+obj-${CONFIG_SND_SOC_WM8903}    += tegra_soc_wm8903.o
+obj-${CONFIG_SND_SOC_WM8753}    += tegra_soc_wm8753.o
+
+
diff --git a/sound/soc/tegra/tegra_i2s.c b/sound/soc/tegra/tegra_i2s.c
new file mode 100644
index 000000000000..fe65aabb6f09
--- /dev/null
+++ b/sound/soc/tegra/tegra_i2s.c
@@ -0,0 +1,600 @@
+/*
+ * tegra_i2s.c  --  ALSA Soc Audio Layer
+ *
+ * (c) 2010 Nvidia Graphics Pvt. Ltd.
+ *  http://www.nvidia.com
+ *
+ * (c) 2006 Wolfson Microelectronics PLC.
+ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
+ *
+ * (c) 2004-2005 Simtec Electronics
+ *    http://armlinux.simtec.co.uk/
+ *    Ben Dooks <ben@simtec.co.uk>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include "tegra_soc.h"
+
+/* i2s controller */
+struct tegra_i2s_info {
+	struct platform_device *pdev;
+	struct tegra_audio_platform_data *pdata;
+	struct clk *i2s_clk;
+	struct clk *dap_mclk;
+	struct clk *audio_sync_clk;
+	phys_addr_t i2s_phys;
+	void __iomem *i2s_base;
+
+	unsigned long dma_req_sel;
+
+	int irq;
+	/* Control for whole I2S (Data format, etc.) */
+	unsigned int bit_format;
+	struct i2s_runtime_data i2s_regs;
+};
+
+void setup_dma_request(struct snd_pcm_substream *substream,
+			struct tegra_dma_req *req,
+			void (*dma_callback)(struct tegra_dma_req *req),
+			void *dma_data)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct tegra_i2s_info *info = cpu_dai->private_data;
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		req->to_memory = false;
+		req->dest_addr =
+			i2s_get_fifo_phy_base(cpu_dai->id, I2S_FIFO_TX);
+		req->dest_wrap = 4;
+		req->source_wrap = 0;
+		if (info->bit_format == TEGRA_AUDIO_BIT_FORMAT_DSP)
+			req->dest_bus_width = info->pdata->dsp_bus_width;
+		else
+			req->dest_bus_width = info->pdata->i2s_bus_width;
+		req->source_bus_width = 32;
+	} else {
+		req->to_memory = true;
+		req->source_addr =
+			i2s_get_fifo_phy_base(cpu_dai->id, I2S_FIFO_RX);
+		req->dest_wrap = 0;
+		req->source_wrap = 4;
+		if (info->bit_format == TEGRA_AUDIO_BIT_FORMAT_DSP)
+			req->source_bus_width = info->pdata->dsp_bus_width;
+		else
+			req->source_bus_width = info->pdata->i2s_bus_width;
+		req->dest_bus_width = 32;
+	}
+
+	req->complete = dma_callback;
+	req->dev = dma_data;
+	req->req_sel = info->dma_req_sel;
+
+	return;
+}
+
+
+/* playback */
+static inline void start_i2s_playback(struct snd_soc_dai *cpu_dai)
+{
+	i2s_fifo_set_attention_level(cpu_dai->id, I2S_FIFO_TX,
+					I2S_FIFO_ATN_LVL_FOUR_SLOTS);
+	i2s_fifo_enable(cpu_dai->id, I2S_FIFO_TX, 1);
+}
+
+static inline void stop_i2s_playback(struct snd_soc_dai *cpu_dai)
+{
+	i2s_set_fifo_irq_on_err(cpu_dai->id, I2S_FIFO_TX, 0);
+	i2s_set_fifo_irq_on_qe(cpu_dai->id, I2S_FIFO_TX, 0);
+	i2s_fifo_enable(cpu_dai->id, I2S_FIFO_TX, 0);
+	while (i2s_get_status(cpu_dai->id) & I2S_I2S_FIFO_TX_BUSY);
+}
+
+/* recording */
+static inline void start_i2s_capture(struct snd_soc_dai *cpu_dai)
+{
+	i2s_fifo_set_attention_level(cpu_dai->id, I2S_FIFO_RX,
+					I2S_FIFO_ATN_LVL_FOUR_SLOTS);
+	i2s_fifo_enable(cpu_dai->id, I2S_FIFO_RX, 1);
+}
+
+static inline void stop_i2s_capture(struct snd_soc_dai *cpu_dai)
+{
+	i2s_set_fifo_irq_on_err(cpu_dai->id, I2S_FIFO_RX, 0);
+	i2s_set_fifo_irq_on_qe(cpu_dai->id, I2S_FIFO_RX, 0);
+	i2s_fifo_enable(cpu_dai->id, I2S_FIFO_RX, 0);
+	while (i2s_get_status(cpu_dai->id) & I2S_I2S_FIFO_RX_BUSY);
+}
+
+
+static int tegra_i2s_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params,
+				struct snd_soc_dai *dai)
+{
+	struct tegra_i2s_info *info = dai->private_data;
+	int ret = 0;
+	int val;
+	unsigned int i2s_id = dai->id;
+	unsigned int rate;
+
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		val = I2S_BIT_SIZE_16;
+		break;
+	case SNDRV_PCM_FORMAT_S24_LE:
+		val = I2S_BIT_SIZE_24;
+		break;
+	case SNDRV_PCM_FORMAT_S32_LE:
+		val = I2S_BIT_SIZE_32;
+		break;
+	default:
+		ret =-EINVAL;
+		goto err;
+	}
+
+	i2s_set_bit_size(i2s_id, val);
+
+	switch (params_rate(params)) {
+	case 8000:
+	case 32000:
+	case 44100:
+	case 48000:
+	case 88200:
+	case 96000:
+		val = params_rate(params);
+		break;
+	default:
+		ret = -EINVAL;
+		goto err;
+	}
+
+	rate = clk_get_rate(info->i2s_clk);
+	if (info->bit_format == TEGRA_AUDIO_BIT_FORMAT_DSP)
+		rate *= 2;
+
+	i2s_set_channel_bit_count(i2s_id, val, rate);
+
+	return 0;
+
+err:
+	return ret;
+}
+
+
+static int tegra_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
+					unsigned int fmt)
+{
+	int val1;
+	int val2;
+	unsigned int i2s_id = cpu_dai->id;
+
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBS_CFS:
+		val1 = 1;
+		break;
+	case SND_SOC_DAIFMT_CBM_CFM:
+		val1= 0;
+		break;
+	case SND_SOC_DAIFMT_CBS_CFM:
+	case SND_SOC_DAIFMT_CBM_CFS:
+		/* Tegra does not support different combinations of
+		 * master and slave for FSYNC and BCLK */
+	default:
+		return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_DSP_A:
+		val1 = I2S_BIT_FORMAT_DSP;
+		val2 = 0;
+		break;
+	case SND_SOC_DAIFMT_DSP_B:
+		val1 = I2S_BIT_FORMAT_DSP;
+		val2 = 1;
+		break;
+	case SND_SOC_DAIFMT_I2S:
+		val1 = I2S_BIT_FORMAT_I2S;
+		val2 = 0;
+		break;
+	case SND_SOC_DAIFMT_RIGHT_J:
+		val1 = I2S_BIT_FORMAT_RJM;
+		val2 = 0;
+		break;
+	case SND_SOC_DAIFMT_LEFT_J:
+		val1 = I2S_BIT_FORMAT_LJM;
+		val2 = 0;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	i2s_set_bit_format(i2s_id,val1);
+	i2s_set_left_right_control_polarity(i2s_id,val2);
+
+	/* Clock inversion */
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_DSP_A:
+	case SND_SOC_DAIFMT_DSP_B:
+		/* frame inversion not valid for DSP modes */
+		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+		case SND_SOC_DAIFMT_NB_NF:
+			break;
+		case SND_SOC_DAIFMT_IB_NF:
+			/* aif1 |= WM8903_AIF_BCLK_INV; */
+			break;
+		default:
+			return -EINVAL;
+		}
+		break;
+	case SND_SOC_DAIFMT_I2S:
+	case SND_SOC_DAIFMT_RIGHT_J:
+	case SND_SOC_DAIFMT_LEFT_J:
+		switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+		case SND_SOC_DAIFMT_NB_NF:
+			break;
+		case SND_SOC_DAIFMT_IB_IF:
+			/* aif1 |= WM8903_AIF_BCLK_INV |
+			 * WM8903_AIF_LRCLK_INV; */
+			break;
+		case SND_SOC_DAIFMT_IB_NF:
+			/* aif1 |= WM8903_AIF_BCLK_INV; */
+			break;
+		case SND_SOC_DAIFMT_NB_IF:
+			/* aif1 |= WM8903_AIF_LRCLK_INV; */
+			break;
+		default:
+			return -EINVAL;
+		}
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int tegra_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
+					int clk_id, unsigned int freq, int dir)
+{
+	struct tegra_i2s_info* info = cpu_dai->private_data;
+	struct tegra_audio_platform_data *pdata = info->pdev->dev.platform_data;
+
+	if (info && info->i2s_clk) {
+		clk_set_rate(info->i2s_clk, pdata->i2s_clk_rate);
+		if (clk_enable(info->i2s_clk)) {
+			pr_err("%s: failed to enable i2s-%d clock\n", __func__,
+			      cpu_dai->id+1);
+			return -EIO;
+		}
+	}
+	else {
+		pr_err("%s: could not get i2s-%d clock\n", __func__,
+		      cpu_dai->id+1);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int tegra_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
+				struct snd_soc_dai *dai)
+{
+	int ret = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+			start_i2s_playback(dai);
+		else
+			start_i2s_capture(dai);
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+			stop_i2s_playback(dai);
+		else
+			stop_i2s_capture(dai);
+		break;
+	default:
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+static int i2s_configure(struct tegra_i2s_info *info )
+{
+	struct platform_device *pdev = info->pdev;
+	struct tegra_audio_platform_data *pdata = pdev->dev.platform_data;
+	struct clk *i2s_clk;
+	unsigned int i2s_id = pdev->id;
+	unsigned int rate;
+
+	i2s_enable_fifos(i2s_id, 0);
+	i2s_fifo_clear(i2s_id, I2S_FIFO_TX);
+	i2s_fifo_clear(i2s_id, I2S_FIFO_RX);
+	i2s_set_left_right_control_polarity(i2s_id, 0); /* default */
+
+	i2s_clk = clk_get(&pdev->dev, NULL);
+	if (!i2s_clk) {
+		dev_err(&pdev->dev, "%s: could not get i2s clock\n",
+			__func__);
+		return -EIO;
+	}
+
+	rate = clk_get_rate(i2s_clk);
+	if (info->bit_format == TEGRA_AUDIO_BIT_FORMAT_DSP)
+		rate *= 2;
+
+	if (pdata->i2s_master && pdata->i2s_master_clk)
+		i2s_set_channel_bit_count(i2s_id, pdata->i2s_master_clk, rate);
+
+	i2s_set_master(i2s_id, pdata->i2s_master);
+
+	i2s_set_fifo_mode(i2s_id, I2S_FIFO_TX, 1);
+	i2s_set_fifo_mode(i2s_id, I2S_FIFO_RX, 0);
+
+	i2s_set_bit_format(i2s_id, pdata->mode);
+	i2s_set_bit_size(i2s_id, pdata->bit_size);
+	i2s_set_fifo_format(i2s_id, pdata->fifo_fmt);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+int tegra_i2s_suspend(struct snd_soc_dai *cpu_dai)
+{
+	struct tegra_i2s_info *info = cpu_dai->private_data;
+
+	i2s_get_all_regs(cpu_dai->id, &info->i2s_regs);
+
+	return 0;
+}
+
+int tegra_i2s_resume(struct snd_soc_dai *cpu_dai)
+{
+	struct tegra_i2s_info *info = cpu_dai->private_data;
+
+	i2s_set_all_regs(cpu_dai->id, &info->i2s_regs);
+
+	return 0;
+}
+
+#else
+#define tegra_i2s_suspend	NULL
+#define tegra_i2s_resume	NULL
+#endif
+
+static int tegra_i2s_startup(struct snd_pcm_substream *substream,
+				struct snd_soc_dai *dai)
+{
+	struct tegra_i2s_info *info = dai->private_data;
+
+	clk_enable(info->dap_mclk);
+	clk_enable(info->audio_sync_clk);
+
+	return 0;
+}
+
+static void tegra_i2s_shutdown(struct snd_pcm_substream *substream,
+				struct snd_soc_dai *dai)
+{
+	struct tegra_i2s_info *info = dai->private_data;
+
+	clk_disable(info->dap_mclk);
+	clk_disable(info->audio_sync_clk);
+
+	return;
+}
+
+static int tegra_i2s_probe(struct platform_device *pdev,
+				struct snd_soc_dai *dai)
+{
+	return 0;
+}
+
+static struct snd_soc_dai_ops tegra_i2s_dai_ops = {
+	.startup	= tegra_i2s_startup,
+	.shutdown	= tegra_i2s_shutdown,
+	.trigger	= tegra_i2s_trigger,
+	.hw_params	= tegra_i2s_hw_params,
+	.set_fmt	= tegra_i2s_set_dai_fmt,
+	.set_sysclk	= tegra_i2s_set_dai_sysclk,
+};
+
+struct snd_soc_dai tegra_i2s_dai[] = {
+	{
+		.name = "tegra-i2s-1",
+		.id = 0,
+		.probe = tegra_i2s_probe,
+		.suspend = tegra_i2s_suspend,
+		.resume = tegra_i2s_resume,
+		.playback = {
+			.channels_min = 2,
+			.channels_max = 2,
+			.rates = TEGRA_SAMPLE_RATES,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+		},
+		.capture = {
+			.channels_min = 2,
+			.channels_max = 2,
+			.rates = TEGRA_SAMPLE_RATES,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+		},
+		.ops = &tegra_i2s_dai_ops,
+	},
+	{
+		.name = "tegra-i2s-2",
+		.id = 1,
+		.probe = tegra_i2s_probe,
+		.suspend = tegra_i2s_suspend,
+		.resume = tegra_i2s_resume,
+		.playback = {
+			.channels_min = 2,
+			.channels_max = 2,
+			.rates = TEGRA_SAMPLE_RATES,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+		},
+		.capture = {
+			.channels_min = 2,
+			.channels_max = 2,
+			.rates = TEGRA_SAMPLE_RATES,
+			.formats = SNDRV_PCM_FMTBIT_S16_LE,
+		},
+		.ops = &tegra_i2s_dai_ops,
+	},
+};
+EXPORT_SYMBOL_GPL(tegra_i2s_dai);
+
+static int tegra_i2s_driver_probe(struct platform_device *pdev)
+{
+	int err = 0;
+	struct resource *res, *mem;
+	struct tegra_i2s_info *info;
+	int i = 0;
+
+	pr_info("%s\n", __func__);
+
+	info = kzalloc(sizeof(*info), GFP_KERNEL);
+	if (!info)
+		return -ENOMEM;
+
+	info->pdev = pdev;
+	info->pdata = pdev->dev.platform_data;
+	info->pdata->driver_data = info;
+	BUG_ON(!info->pdata);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "no mem resource!\n");
+		err = -ENODEV;
+		goto fail;
+	}
+
+	mem = request_mem_region(res->start, resource_size(res), pdev->name);
+	if (!mem) {
+		dev_err(&pdev->dev, "memory region already claimed!\n");
+		err = -EBUSY;
+		goto fail;
+	}
+
+	info->i2s_phys = res->start;
+	info->i2s_base = ioremap(res->start, res->end - res->start + 1);
+	if (!info->i2s_base) {
+		dev_err(&pdev->dev, "cannot remap iomem!\n");
+		err = -ENOMEM;
+		goto fail_release_mem;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "no dma resource!\n");
+		err = -ENODEV;
+		goto fail_unmap_mem;
+	}
+	info->dma_req_sel = res->start;
+
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "no irq resource!\n");
+		err = -ENODEV;
+		goto fail_unmap_mem;
+	}
+	info->irq = res->start;
+
+	info->i2s_clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(info->i2s_clk)) {
+		err = PTR_ERR(info->i2s_clk);
+		goto fail_unmap_mem;
+	}
+	clk_set_rate(info->i2s_clk, info->pdata->i2s_clk_rate);
+
+	info->dap_mclk = i2s_get_clock_by_name(info->pdata->dap_clk);
+	if (IS_ERR(info->dap_mclk)) {
+		err = PTR_ERR(info->dap_mclk);
+		goto fail_unmap_mem;
+	}
+
+	info->audio_sync_clk = i2s_get_clock_by_name(
+					info->pdata->audio_sync_clk);
+	if (IS_ERR(info->audio_sync_clk)) {
+		err = PTR_ERR(info->audio_sync_clk);
+		goto fail_unmap_mem;
+	}
+
+	info->bit_format = TEGRA_AUDIO_BIT_FORMAT_DEFAULT;
+	if (info->pdata->mode == I2S_BIT_FORMAT_DSP)
+		info->bit_format = TEGRA_AUDIO_BIT_FORMAT_DSP;
+
+	i2s_configure(info);
+
+	for (i = 0; i < ARRAY_SIZE(tegra_i2s_dai); i++) {
+		if (tegra_i2s_dai[i].id == pdev->id) {
+			tegra_i2s_dai[i].dev = &pdev->dev;
+			tegra_i2s_dai[i].private_data = info;
+			err = snd_soc_register_dai(&tegra_i2s_dai[i]);
+			if (err)
+				goto fail_unmap_mem;
+		}
+	}
+
+	return 0;
+
+fail_unmap_mem:
+	iounmap(info->i2s_base);
+fail_release_mem:
+	release_mem_region(mem->start, resource_size(mem));
+fail:
+	kfree(info);
+	return err;
+}
+
+
+static int __devexit tegra_i2s_driver_remove(struct platform_device *pdev)
+{
+	struct tegra_i2s_info *info = tegra_i2s_dai[pdev->id].private_data;
+
+	if (info->i2s_base)
+		iounmap(info->i2s_base);
+
+	if (info)
+		kfree(info);
+
+	snd_soc_unregister_dai(&tegra_i2s_dai[pdev->id]);
+	return 0;
+}
+
+static struct platform_driver tegra_i2s_driver = {
+	.probe = tegra_i2s_driver_probe,
+	.remove = __devexit_p(tegra_i2s_driver_remove),
+	.driver = {
+		.name = "i2s",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init tegra_i2s_init(void)
+{
+	int ret = 0;
+
+	ret = platform_driver_register(&tegra_i2s_driver);
+	return ret;
+}
+module_init(tegra_i2s_init);
+
+static void __exit tegra_i2s_exit(void)
+{
+	platform_driver_unregister(&tegra_i2s_driver);
+}
+module_exit(tegra_i2s_exit);
+
+/* Module information */
+MODULE_DESCRIPTION("Tegra I2S SoC interface");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/tegra/tegra_pcm.c b/sound/soc/tegra/tegra_pcm.c
new file mode 100644
index 000000000000..1bddb5547c3c
--- /dev/null
+++ b/sound/soc/tegra/tegra_pcm.c
@@ -0,0 +1,432 @@
+/*
+ * tegra_pcm.c  --  ALSA Soc Audio Layer
+ *
+ * (c) 2010 Nvidia Graphics Pvt. Ltd.
+ *  http://www.nvidia.com
+ *
+ * (c) 2006 Wolfson Microelectronics PLC.
+ * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
+ *
+ * (c) 2004-2005 Simtec Electronics
+ *    http://armlinux.simtec.co.uk/
+ *    Ben Dooks <ben@simtec.co.uk>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include "tegra_soc.h"
+#include <mach/tegra_das.h>
+
+#define PLAYBACK_STARTED true
+#define PLAYBACK_STOPPED false
+
+static void tegra_pcm_play(struct tegra_runtime_data *prtd)
+{
+	static int reqid = 0;
+	struct snd_pcm_substream *substream = prtd->substream;
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct snd_dma_buffer *buf = &substream->dma_buffer;
+
+	if (runtime->dma_addr) {
+		prtd->size = frames_to_bytes(runtime, runtime->period_size);
+		if (reqid == 0) {
+			if (prtd->dma_state != STATE_ABORT) {
+				prtd->dma_req1.source_addr = buf->addr +
+				frames_to_bytes(runtime,prtd->dma_pos);
+				prtd->dma_req1.size = prtd->size;
+				tegra_dma_enqueue_req(prtd->dma_chan,
+							&prtd->dma_req1);
+				reqid = 1;
+			}
+		} else {
+			if (prtd->dma_state != STATE_ABORT) {
+				prtd->dma_req2.source_addr = buf->addr +
+				frames_to_bytes(runtime,prtd->dma_pos);
+				prtd->dma_req2.size = prtd->size;
+				tegra_dma_enqueue_req(prtd->dma_chan,
+							&prtd->dma_req2);
+				reqid = 0;
+			}
+		}
+	}
+
+	prtd->dma_pos += runtime->period_size;
+	if (prtd->dma_pos >= runtime->buffer_size) {
+		prtd->dma_pos = 0;
+	}
+
+}
+
+static void tegra_pcm_capture(struct tegra_runtime_data *prtd)
+{
+	static int reqid = 0;
+	struct snd_pcm_substream *substream = prtd->substream;
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct snd_dma_buffer *buf = &substream->dma_buffer;
+
+	if (runtime->dma_addr) {
+		prtd->size = frames_to_bytes(runtime, runtime->period_size);
+		if (reqid == 0) {
+			if (prtd->dma_state != STATE_ABORT) {
+				prtd->dma_req1.dest_addr = buf->addr +
+				frames_to_bytes(runtime,prtd->dma_pos);
+				prtd->dma_req1.size = prtd->size;
+				tegra_dma_enqueue_req(prtd->dma_chan,
+							&prtd->dma_req1);
+				reqid = 1;
+			}
+		} else {
+			if (prtd->dma_state != STATE_ABORT) {
+				prtd->dma_req2.dest_addr = buf->addr +
+				frames_to_bytes(runtime,prtd->dma_pos);
+				prtd->dma_req2.size = prtd->size;
+				tegra_dma_enqueue_req(prtd->dma_chan,
+							&prtd->dma_req2);
+				reqid = 0;
+			}
+		}
+	}
+
+	prtd->dma_pos += runtime->period_size;
+	if (prtd->dma_pos >= runtime->buffer_size) {
+		prtd->dma_pos = 0;
+	}
+
+}
+
+static void dma_complete_callback (struct tegra_dma_req *req)
+{
+	struct tegra_runtime_data *prtd = (struct tegra_runtime_data *)req->dev;
+	struct snd_pcm_substream *substream = prtd->substream;
+	struct snd_pcm_runtime *runtime = substream->runtime;
+
+	if (++prtd->period_index >= runtime->periods) {
+		prtd->period_index = 0;
+	}
+
+	if (prtd->dma_state != STATE_ABORT) {
+		snd_pcm_period_elapsed(substream);
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			tegra_pcm_play(prtd);
+		} else {
+			tegra_pcm_capture(prtd);
+		}
+	}
+}
+
+static const struct snd_pcm_hardware tegra_pcm_hardware = {
+	.info 	= SNDRV_PCM_INFO_INTERLEAVED | \
+			SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME | \
+			SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_MMAP_VALID ,
+	.formats		= SNDRV_PCM_FMTBIT_S16_LE,
+	.channels_min		= 1,
+	.channels_max		= 2,
+	.buffer_bytes_max	= (PAGE_SIZE * 8),
+	.period_bytes_min	= 1024,
+	.period_bytes_max	= (PAGE_SIZE),
+	.periods_min		= 2,
+	.periods_max		= 8,
+	.fifo_size 		= 4,
+};
+
+static int tegra_pcm_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params)
+{
+	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+	return 0;
+}
+
+static int tegra_pcm_hw_free(struct snd_pcm_substream *substream)
+{
+	snd_pcm_set_runtime_buffer(substream, NULL);
+	return 0;
+}
+
+static int tegra_pcm_prepare(struct snd_pcm_substream *substream)
+{
+	struct tegra_runtime_data *prtd = substream->runtime->private_data;
+
+	prtd->dma_pos = 0;
+	prtd->period_index = 0;
+
+	return 0;
+}
+
+static int tegra_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+	struct tegra_runtime_data *prtd = substream->runtime->private_data;
+	int ret = 0;
+
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			prtd->state = STATE_INIT;
+			prtd->dma_state = STATE_INIT;
+			tegra_pcm_play(prtd); /* dma enqueue req1 */
+			tegra_pcm_play(prtd); /* dma enqueue req2 */
+		} else if (prtd->state != STATE_INIT) {
+			/* start recording */
+			prtd->state = STATE_INIT;
+			prtd->dma_state = STATE_INIT;
+			tegra_pcm_capture(prtd); /* dma enqueue req1 */
+			tegra_pcm_capture(prtd); /* dma enqueue req2 */
+		}
+		break;
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		prtd->state = STATE_ABORT;
+		prtd->dma_state = STATE_ABORT;
+		tegra_dma_cancel(prtd->dma_chan);
+		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+			if (prtd->dma_chan) {
+				tegra_dma_dequeue_req(prtd->dma_chan,
+							&prtd->dma_req1);
+				tegra_dma_dequeue_req(prtd->dma_chan,
+							&prtd->dma_req2);
+			}
+		} else {
+			if (prtd->dma_chan) {
+				tegra_dma_dequeue_req(prtd->dma_chan,
+							&prtd->dma_req1);
+				tegra_dma_dequeue_req(prtd->dma_chan,
+							&prtd->dma_req2);
+			}
+		}
+		break;
+	default:
+		ret = -EINVAL;
+		break;
+	}
+	return ret;
+}
+
+static snd_pcm_uframes_t tegra_pcm_pointer(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct tegra_runtime_data *prtd = runtime->private_data;
+	int size;
+	size = prtd->period_index * runtime->period_size;
+	return (size);
+}
+
+static int tegra_pcm_open(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct tegra_runtime_data *prtd;
+	int ret=0;
+
+	prtd = kzalloc(sizeof(struct tegra_runtime_data), GFP_KERNEL);
+	if (prtd == NULL)
+		return -ENOMEM;
+
+	memset(prtd, 0, sizeof(*prtd));
+	runtime->private_data = prtd;
+	prtd->substream = substream;
+
+	/* set pins state to normal */
+	tegra_das_power_mode(true);
+
+	prtd->state = STATE_INVALID;
+
+	setup_dma_request(substream,
+			&prtd->dma_req1,
+			dma_complete_callback,
+			prtd);
+
+	setup_dma_request(substream,
+			&prtd->dma_req2,
+			dma_complete_callback,
+			prtd);
+
+	prtd->dma_chan = tegra_dma_allocate_channel(TEGRA_DMA_MODE_CONTINUOUS_DOUBLE);
+	if (IS_ERR(prtd->dma_chan)) {
+		pr_err("%s: could not allocate DMA channel for I2S: %ld\n",
+		       __func__, PTR_ERR(prtd->dma_chan));
+		ret = PTR_ERR(prtd->dma_chan);
+		goto fail;
+	}
+
+	/* Set HW params now that initialization is complete */
+	snd_soc_set_runtime_hwparams(substream, &tegra_pcm_hardware);
+
+	goto end;
+
+fail:
+	prtd->state = STATE_EXIT;
+
+	if (prtd->dma_chan) {
+		tegra_dma_flush(prtd->dma_chan);
+		tegra_dma_free_channel(prtd->dma_chan);
+	}
+
+	/* set pins state to tristate */
+	tegra_das_power_mode(false);
+
+	kfree(prtd);
+
+end:
+	return ret;
+}
+
+static int tegra_pcm_close(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct tegra_runtime_data *prtd = runtime->private_data;
+
+	if (!prtd) {
+		printk(KERN_ERR "tegra_pcm_close called with prtd == NULL\n");
+		return 0;
+	}
+
+	prtd->state = STATE_EXIT;
+
+	if (prtd->dma_chan) {
+		prtd->dma_state = STATE_EXIT;
+		tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req1);
+		tegra_dma_dequeue_req(prtd->dma_chan, &prtd->dma_req2);
+		tegra_dma_flush(prtd->dma_chan);
+		tegra_dma_free_channel(prtd->dma_chan);
+		prtd->dma_chan = NULL;
+	}
+
+	/* set pins state to tristate */
+	tegra_das_power_mode(false);
+
+	kfree(prtd);
+
+	return 0;
+}
+
+static int tegra_pcm_mmap(struct snd_pcm_substream *substream,
+				struct vm_area_struct *vma)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+
+	return dma_mmap_writecombine(substream->pcm->card->dev, vma,
+					runtime->dma_area,
+					runtime->dma_addr,
+					runtime->dma_bytes);
+}
+
+static struct snd_pcm_ops tegra_pcm_ops = {
+	.open       = tegra_pcm_open,
+	.close      = tegra_pcm_close,
+	.ioctl      = snd_pcm_lib_ioctl,
+	.hw_params  = tegra_pcm_hw_params,
+	.hw_free    = tegra_pcm_hw_free,
+	.prepare    = tegra_pcm_prepare,
+	.trigger    = tegra_pcm_trigger,
+	.pointer    = tegra_pcm_pointer,
+	.mmap       = tegra_pcm_mmap,
+};
+
+static int tegra_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
+{
+	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+	struct snd_dma_buffer *buf = &substream->dma_buffer;
+	size_t size = tegra_pcm_hardware.buffer_bytes_max;
+
+	buf->dev.type = SNDRV_DMA_TYPE_DEV;
+	buf->dev.dev = pcm->card->dev;
+	buf->private_data = NULL;
+	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
+						&buf->addr, GFP_KERNEL);
+	buf->bytes = size;
+	return 0;
+}
+
+static void tegra_pcm_deallocate_dma_buffer(struct snd_pcm *pcm, int stream)
+{
+	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+	struct snd_dma_buffer *buf = &substream->dma_buffer;
+
+	for (stream = 0; stream < 2; stream++) {
+		substream = pcm->streams[stream].substream;
+		if (!substream)
+			continue;
+
+		buf = &substream->dma_buffer;
+		if (!buf->area)
+			continue;
+
+		dma_free_writecombine(pcm->card->dev, buf->bytes,
+					buf->area, buf->addr);
+		buf->area = NULL;
+	}
+}
+
+static void tegra_pcm_free_dma_buffers(struct snd_pcm *pcm)
+{
+	struct snd_pcm_substream *substream;
+	struct snd_dma_buffer *buf;
+	int stream;
+
+	for (stream = 0; stream < 2; stream++) {
+		substream = pcm->streams[stream].substream;
+		buf = &substream->dma_buffer;
+		if (!buf) {
+			printk(KERN_ERR "no buffer %d \n",stream);
+			continue;
+		}
+		tegra_pcm_deallocate_dma_buffer(pcm ,stream);
+	}
+
+}
+
+static u64 tegra_dma_mask = DMA_BIT_MASK(32);
+
+static int tegra_pcm_new(struct snd_card *card,
+				struct snd_soc_dai *dai, struct snd_pcm *pcm)
+{
+	int ret = 0;
+
+	if (!card->dev->dma_mask)
+		card->dev->dma_mask = &tegra_dma_mask;
+	if (!card->dev->coherent_dma_mask)
+		card->dev->coherent_dma_mask = 0xffffffff;
+
+	if (dai->playback.channels_min) {
+		ret = tegra_pcm_preallocate_dma_buffer(pcm,
+						SNDRV_PCM_STREAM_PLAYBACK);
+		if (ret)
+			goto out;
+	}
+
+	if (dai->capture.channels_min) {
+		ret = tegra_pcm_preallocate_dma_buffer(pcm,
+						SNDRV_PCM_STREAM_CAPTURE);
+		if (ret)
+			goto out;
+	}
+out:
+	return ret;
+}
+
+struct snd_soc_platform tegra_soc_platform = {
+	.name     = "tegra-audio",
+	.pcm_ops  = &tegra_pcm_ops,
+	.pcm_new  = tegra_pcm_new,
+	.pcm_free = tegra_pcm_free_dma_buffers,
+};
+EXPORT_SYMBOL_GPL(tegra_soc_platform);
+
+static int __init tegra_soc_platform_init(void)
+{
+	return snd_soc_register_platform(&tegra_soc_platform);
+}
+module_init(tegra_soc_platform_init);
+
+static void __exit tegra_soc_platform_exit(void)
+{
+	snd_soc_unregister_platform(&tegra_soc_platform);
+}
+module_exit(tegra_soc_platform_exit);
+
+MODULE_DESCRIPTION("Tegra PCM DMA module");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/tegra/tegra_soc.h b/sound/soc/tegra/tegra_soc.h
new file mode 100644
index 000000000000..29f4fcf13651
--- /dev/null
+++ b/sound/soc/tegra/tegra_soc.h
@@ -0,0 +1,108 @@
+/*
+ * tegra_soc.h  --  SoC audio for tegra
+ *
+ * (c) 2010 Nvidia Graphics Pvt. Ltd.
+ *  http://www.nvidia.com
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC.
+ * Author: Graeme Gregory
+ *         graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __TEGRA_AUDIO__
+#define __TEGRA_AUDIO__
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/jiffies.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/kthread.h>
+#include <linux/moduleparam.h>
+#include <linux/timer.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/tegra_audio.h>
+#include <mach/iomap.h>
+#include <mach/tegra2_i2s.h>
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/audio.h>
+#include <mach/tegra_das.h>
+#include <mach/dma.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/initval.h>
+#include <sound/soc.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc-dapm.h>
+#include <sound/soc-dai.h>
+#include <sound/tlv.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/scoop.h>
+
+#define STATE_INIT	0
+#define STATE_ABORT	1
+#define STATE_EXIT	2
+#define STATE_EXITED	3
+#define STATE_INVALID	4
+
+#define I2S_I2S_FIFO_TX_BUSY	I2S_I2S_STATUS_FIFO1_BSY
+#define I2S_I2S_FIFO_TX_QS	I2S_I2S_STATUS_QS_FIFO1
+#define I2S_I2S_FIFO_RX_BUSY	I2S_I2S_STATUS_FIFO2_BSY
+#define I2S_I2S_FIFO_RX_QS	I2S_I2S_STATUS_QS_FIFO2
+
+#define I2S_CLK 		11289600
+#define TEGRA_DEFAULT_SR	44100
+
+#define TEGRA_SAMPLE_RATES \
+	(SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
+	SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
+
+struct tegra_dma_channel;
+
+struct tegra_runtime_data {
+	struct snd_pcm_substream *substream;
+	int size;
+	int dma_pos;
+	struct tegra_dma_req dma_req1, dma_req2;
+	volatile int state;
+	int period_index;
+	int i2s_shutdown;
+	int dma_state;
+	struct tegra_dma_channel *dma_chan;
+	struct clk *i2s_clk;
+	struct clk *dap_mclk;
+	struct clk *audio_sync_clk;
+};
+
+struct tegra_audio_data {
+	struct snd_soc_codec *codec;
+	int play_device;
+	int capture_device;
+	bool is_call_mode;
+};
+
+int tegra_controls_init(struct snd_soc_codec *codec);
+void tegra_controls_exit(void);
+
+void setup_dma_request(struct snd_pcm_substream *substream,
+			struct tegra_dma_req *req,
+			void (*dma_callback)(struct tegra_dma_req *req),
+			void *dma_data);
+
+#endif
diff --git a/sound/soc/tegra/tegra_soc_controls.c b/sound/soc/tegra/tegra_soc_controls.c
new file mode 100644
index 000000000000..f73e80df751f
--- /dev/null
+++ b/sound/soc/tegra/tegra_soc_controls.c
@@ -0,0 +1,453 @@
+/*
+ * tegra_soc_controls.c -- alsa controls for tegra SoC
+ *
+ * Copyright (c) 2010, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+
+#include "tegra_soc.h"
+#include <mach/audio.h>
+
+static struct tegra_audio_data *audio_data;
+static int tegra_jack_func;
+static int tegra_spk_func;
+
+#define TEGRA_HP	0
+#define TEGRA_MIC	1
+#define TEGRA_LINE	2
+#define TEGRA_HEADSET	3
+#define TEGRA_HP_OFF	4
+#define TEGRA_SPK_ON	0
+#define TEGRA_SPK_OFF	1
+
+static void tegra_ext_control(struct snd_soc_codec *codec)
+{
+	/* set up jack connection */
+	switch (tegra_jack_func) {
+	case TEGRA_HP:
+		/* set = unmute headphone */
+		snd_soc_dapm_enable_pin(codec, "Mic Jack");
+		snd_soc_dapm_disable_pin(codec, "Line Jack");
+		snd_soc_dapm_enable_pin(codec, "Headphone Jack");
+		snd_soc_dapm_disable_pin(codec, "Headset Jack");
+		break;
+	case TEGRA_MIC:
+		/* reset = mute headphone */
+		snd_soc_dapm_enable_pin(codec, "Mic Jack");
+		snd_soc_dapm_disable_pin(codec, "Line Jack");
+		snd_soc_dapm_disable_pin(codec, "Headphone Jack");
+		snd_soc_dapm_disable_pin(codec, "Headset Jack");
+		break;
+	case TEGRA_LINE:
+		snd_soc_dapm_disable_pin(codec, "Mic Jack");
+		snd_soc_dapm_enable_pin(codec, "Line Jack");
+		snd_soc_dapm_disable_pin(codec, "Headphone Jack");
+		snd_soc_dapm_disable_pin(codec, "Headset Jack");
+		break;
+	case TEGRA_HEADSET:
+		snd_soc_dapm_enable_pin(codec, "Mic Jack");
+		snd_soc_dapm_disable_pin(codec, "Line Jack");
+		snd_soc_dapm_disable_pin(codec, "Headphone Jack");
+		snd_soc_dapm_enable_pin(codec, "Headset Jack");
+		break;
+	}
+
+	if (tegra_spk_func == TEGRA_SPK_ON) {
+		snd_soc_dapm_enable_pin(codec, "Ext Spk");
+	} else {
+		snd_soc_dapm_disable_pin(codec, "Ext Spk");
+	}
+	/* signal a DAPM event */
+	snd_soc_dapm_sync(codec);
+}
+
+static int tegra_get_jack(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.integer.value[0] = tegra_jack_func;
+	return 0;
+}
+
+static int tegra_set_jack(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+
+	if (tegra_jack_func == ucontrol->value.integer.value[0])
+		return 0;
+
+	tegra_jack_func = ucontrol->value.integer.value[0];
+	tegra_ext_control(codec);
+	return 1;
+}
+
+static int tegra_get_spk(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.integer.value[0] = tegra_spk_func;
+	return 0;
+}
+
+static int tegra_set_spk(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_codec *codec =  snd_kcontrol_chip(kcontrol);
+
+
+	if (tegra_spk_func == ucontrol->value.integer.value[0])
+		return 0;
+
+	tegra_spk_func = ucontrol->value.integer.value[0];
+	tegra_ext_control(codec);
+	return 1;
+}
+
+/*tegra machine dapm widgets */
+static const struct snd_soc_dapm_widget tegra_dapm_widgets[] = {
+	SND_SOC_DAPM_HP("Headphone Jack", NULL),
+	SND_SOC_DAPM_MIC("Mic Jack", NULL),
+	SND_SOC_DAPM_SPK("Ext Spk", NULL),
+	SND_SOC_DAPM_LINE("Line Jack", NULL),
+	SND_SOC_DAPM_HP("Headset Jack", NULL),
+};
+
+/* Tegra machine audio map (connections to the codec pins) */
+static const struct snd_soc_dapm_route audio_map[] = {
+
+	/* headset Jack  - in = micin, out = LHPOUT*/
+	{"Headset Jack", NULL, "HPOUTL"},
+
+	/* headphone connected to LHPOUT1, RHPOUT1 */
+	{"Headphone Jack", NULL, "HPOUTR"}, {"Headphone Jack", NULL, "HPOUTL"},
+
+	/* speaker connected to LOUT, ROUT */
+	{"Ext Spk", NULL, "LINEOUTR"}, {"Ext Spk", NULL, "LINEOUTL"},
+
+	/* mic is connected to MICIN (via right channel of headphone jack) */
+	{"IN1L", NULL, "Mic Jack"},
+
+	/* Same as the above but no mic bias for line signals */
+	{"IN2L", NULL, "Line Jack"},
+};
+
+static const char *jack_function[] = {"Headphone", "Mic", "Line", "Headset",
+					"Off"
+					};
+static const char *spk_function[] = {"On", "Off"};
+static const struct soc_enum tegra_enum[] = {
+	SOC_ENUM_SINGLE_EXT(5, jack_function),
+	SOC_ENUM_SINGLE_EXT(2, spk_function),
+};
+
+static const struct snd_kcontrol_new tegra_controls[] = {
+	SOC_ENUM_EXT("Jack Function", tegra_enum[0], tegra_get_jack,
+			tegra_set_jack),
+	SOC_ENUM_EXT("Speaker Function", tegra_enum[1], tegra_get_spk,
+			tegra_set_spk),
+};
+
+static void tegra_audio_route(int device_new, int is_call_mode_new)
+{
+	int play_device_new = device_new & TEGRA_AUDIO_DEVICE_OUT_ALL;
+	int capture_device_new = device_new & TEGRA_AUDIO_DEVICE_IN_ALL;
+	int is_bt_sco_mode =
+		(play_device_new & TEGRA_AUDIO_DEVICE_OUT_BT_SCO) ||
+		(capture_device_new & TEGRA_AUDIO_DEVICE_OUT_BT_SCO);
+	int was_bt_sco_mode =
+		(audio_data->play_device & TEGRA_AUDIO_DEVICE_OUT_BT_SCO) ||
+		(audio_data->capture_device & TEGRA_AUDIO_DEVICE_OUT_BT_SCO);
+
+	if (play_device_new != audio_data->play_device) {
+		if (play_device_new & TEGRA_AUDIO_DEVICE_OUT_HEADPHONE) {
+			tegra_jack_func = TEGRA_HP;
+		}
+		else if (play_device_new & TEGRA_AUDIO_DEVICE_OUT_HEADSET) {
+			tegra_jack_func = TEGRA_HEADSET;
+		}
+		else if (play_device_new & TEGRA_AUDIO_DEVICE_OUT_LINE) {
+			tegra_jack_func = TEGRA_LINE;
+		}
+
+		if (play_device_new & TEGRA_AUDIO_DEVICE_OUT_SPEAKER) {
+			tegra_spk_func = TEGRA_SPK_ON;
+		}
+		else if (play_device_new & TEGRA_AUDIO_DEVICE_OUT_EAR_SPEAKER) {
+			tegra_spk_func = TEGRA_SPK_ON;
+		}
+		else {
+			tegra_spk_func = TEGRA_SPK_OFF;
+		}
+		tegra_ext_control(audio_data->codec);
+		audio_data->play_device = play_device_new;
+	}
+
+	if (capture_device_new != audio_data->capture_device) {
+		if (capture_device_new & (TEGRA_AUDIO_DEVICE_IN_BUILTIN_MIC |
+					TEGRA_AUDIO_DEVICE_IN_MIC |
+					TEGRA_AUDIO_DEVICE_IN_BACK_MIC)) {
+			if ((tegra_jack_func != TEGRA_HP) &&
+				(tegra_jack_func != TEGRA_HEADSET)) {
+				tegra_jack_func = TEGRA_MIC;
+			}
+		}
+		else if (capture_device_new & TEGRA_AUDIO_DEVICE_IN_HEADSET) {
+			tegra_jack_func = TEGRA_HEADSET;
+		}
+		else if (capture_device_new & TEGRA_AUDIO_DEVICE_IN_LINE) {
+			tegra_jack_func = TEGRA_LINE;
+		}
+		tegra_ext_control(audio_data->codec);
+		audio_data->capture_device = capture_device_new;
+	}
+
+	if ((is_call_mode_new != audio_data->is_call_mode) ||
+		(is_bt_sco_mode != was_bt_sco_mode)) {
+		if (is_call_mode_new && is_bt_sco_mode) {
+			tegra_das_set_connection
+				(tegra_das_port_con_id_voicecall_with_bt);
+		}
+		else if (is_call_mode_new && !is_bt_sco_mode) {
+			tegra_das_set_connection
+				(tegra_das_port_con_id_voicecall_no_bt);
+		}
+		else if (!is_call_mode_new && is_bt_sco_mode) {
+			tegra_das_set_connection
+				(tegra_das_port_con_id_bt_codec);
+		}
+		else {
+			tegra_das_set_connection
+				(tegra_das_port_con_id_hifi);
+		}
+		audio_data->is_call_mode = is_call_mode_new;
+	}
+}
+
+static int tegra_play_route_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	uinfo->value.integer.min = TEGRA_AUDIO_DEVICE_NONE;
+	uinfo->value.integer.max = TEGRA_AUDIO_DEVICE_MAX;
+	return 0;
+}
+
+static int tegra_play_route_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.integer.value[0] = TEGRA_AUDIO_DEVICE_NONE;
+	if (audio_data) {
+		ucontrol->value.integer.value[0] = audio_data->play_device;
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static int tegra_play_route_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	if (audio_data) {
+		int play_device_new = ucontrol->value.integer.value[0] &
+				TEGRA_AUDIO_DEVICE_OUT_ALL;
+
+		if (audio_data->play_device != play_device_new) {
+			tegra_audio_route(
+				play_device_new | audio_data->capture_device,
+				audio_data->is_call_mode);
+			return 1;
+		}
+		return 0;
+	}
+	return -EINVAL;
+}
+
+struct snd_kcontrol_new tegra_play_route_control = {
+	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	.name = "Pcm Playback Route",
+	.private_value = 0xffff,
+	.info = tegra_play_route_info,
+	.get = tegra_play_route_get,
+	.put = tegra_play_route_put
+};
+
+static int tegra_capture_route_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	uinfo->value.integer.min = TEGRA_AUDIO_DEVICE_NONE;
+	uinfo->value.integer.max = TEGRA_AUDIO_DEVICE_MAX;
+	return 0;
+}
+
+static int tegra_capture_route_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.integer.value[0] = TEGRA_AUDIO_DEVICE_NONE;
+	if (audio_data) {
+		ucontrol->value.integer.value[0] = audio_data->capture_device;
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static int tegra_capture_route_put(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	if (audio_data) {
+		int capture_device_new = ucontrol->value.integer.value[0] &
+				TEGRA_AUDIO_DEVICE_IN_ALL;
+
+		if (audio_data->capture_device != capture_device_new) {
+			tegra_audio_route(
+				audio_data->play_device | capture_device_new,
+				audio_data->is_call_mode);
+			return 1;
+		}
+		return 0;
+	}
+	return -EINVAL;
+}
+
+struct snd_kcontrol_new tegra_capture_route_control = {
+	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	.name = "Pcm Capture Route",
+	.private_value = 0xffff,
+	.info = tegra_capture_route_info,
+	.get = tegra_capture_route_get,
+	.put = tegra_capture_route_put
+};
+
+static int tegra_call_mode_info(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_info *uinfo)
+{
+	uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
+	uinfo->count = 1;
+	uinfo->value.integer.min = 0;
+	uinfo->value.integer.max = 1;
+	return 0;
+}
+
+static int tegra_call_mode_get(struct snd_kcontrol *kcontrol,
+				struct snd_ctl_elem_value *ucontrol)
+{
+	ucontrol->value.integer.value[0] = TEGRA_AUDIO_DEVICE_NONE;
+	if (audio_data) {
+		ucontrol->value.integer.value[0] = audio_data->is_call_mode;
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static int tegra_call_mode_put(struct snd_kcontrol *kcontrol,
+				   struct snd_ctl_elem_value *ucontrol)
+{
+	if (audio_data) {
+		int is_call_mode_new = ucontrol->value.integer.value[0];
+
+		if (audio_data->is_call_mode != is_call_mode_new) {
+			tegra_audio_route(
+				audio_data->play_device |
+				audio_data->capture_device,
+				is_call_mode_new);
+			return 1;
+		}
+		return 0;
+	}
+	return -EINVAL;
+}
+
+struct snd_kcontrol_new tegra_call_mode_control = {
+	.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+	.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+	.name = "Call Mode Switch",
+	.private_value = 0xffff,
+	.info = tegra_call_mode_info,
+	.get = tegra_call_mode_get,
+	.put = tegra_call_mode_put
+};
+
+int tegra_controls_init(struct snd_soc_codec *codec)
+{
+	int err;
+
+	if (!audio_data) {
+		audio_data = kzalloc(sizeof(*audio_data), GFP_KERNEL);
+		if (!audio_data) {
+			pr_err("failed to allocate tegra_audio_data \n");
+			return -ENOMEM;
+		}
+
+		/* Add tegra specific controls */
+		err = snd_soc_add_controls(codec, tegra_controls,
+						ARRAY_SIZE(tegra_controls));
+		if (err < 0)
+			goto fail;
+
+		/* Add tegra specific widgets */
+		snd_soc_dapm_new_controls(codec, tegra_dapm_widgets,
+						ARRAY_SIZE(tegra_dapm_widgets));
+
+		/* Set up tegra specific audio path audio_map */
+		snd_soc_dapm_add_routes(codec, audio_map,
+				ARRAY_SIZE(audio_map));
+
+		audio_data->codec = codec;
+		/* Add play route control */
+		err = snd_ctl_add(codec->card,
+			snd_ctl_new1(&tegra_play_route_control, NULL));
+		if (err < 0)
+			goto fail;
+
+		/* Add capture route control */
+		err = snd_ctl_add(codec->card,
+			snd_ctl_new1(&tegra_capture_route_control, NULL));
+		if (err < 0)
+			goto fail;
+
+		/* Add call mode switch control */
+		err = snd_ctl_add(codec->card,
+			snd_ctl_new1(&tegra_call_mode_control, NULL));
+		if (err < 0)
+			goto fail;
+
+		/* Default to HP output */
+		tegra_jack_func = TEGRA_HP;
+		tegra_spk_func = TEGRA_SPK_ON;
+		tegra_ext_control(codec);
+
+		snd_soc_dapm_sync(codec);
+	}
+
+	return 0;
+fail:
+	if (audio_data) {
+		kfree(audio_data);
+		audio_data = 0;
+	}
+	return err;
+}
+
+void tegra_controls_exit(void)
+{
+	if (audio_data) {
+		kfree(audio_data);
+		audio_data = 0;
+	}
+}
diff --git a/sound/soc/tegra/tegra_soc_wm8753.c b/sound/soc/tegra/tegra_soc_wm8753.c
new file mode 100644
index 000000000000..103774e60639
--- /dev/null
+++ b/sound/soc/tegra/tegra_soc_wm8753.c
@@ -0,0 +1,402 @@
+ /*
+  * tegra_soc_wm8753.c  --  SoC audio for tegra
+  *
+  * Copyright  2011 Nvidia Graphics Pvt. Ltd.
+  *
+  * Author: Sachin Nikam
+  *             snikam@nvidia.com
+  *  http://www.nvidia.com
+  *
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful, but WITHOUT
+  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+  * more details.
+  *
+  * You should have received a copy of the GNU General Public License along
+  * with this program; if not, write to the Free Software Foundation, Inc.,
+  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+*/
+
+
+#include "tegra_soc.h"
+#include "../codecs/wm8753.h"
+#include <linux/regulator/consumer.h>
+
+#define WM8753_PWR1_VMIDSEL_1		1<<8
+#define WM8753_PWR1_VMIDSEL_0		1<<7
+#define WM8753_PWR1_VREF		1<<6
+#define WM8753_PWR1_MICB		1<<5
+#define WM8753_PWR1_DACL		1<<3
+#define WM8753_PWR1_DACR		1<<2
+
+#define WM8753_PWR2_MICAMP1EN		1<<8
+#define WM8753_PWR2_MICAMP2EN		1<<7
+#define WM8753_PWR2_ALCMIX		1<<6
+#define WM8753_PWR2_PGAL		1<<5
+#define WM8753_PWR2_PGAR		1<<4
+#define WM8753_PWR2_ADCL		1<<3
+#define WM8753_PWR2_ADCR		1<<2
+#define WM8753_PWR2_RXMIX		1<<1
+#define WM8753_PWR2_LINEMIX		1<<0
+
+#define WM8753_PWR3_LOUT1		1<<8
+#define WM8753_PWR3_ROUT1		1<<7
+#define WM8753_PWR3_LOUT2		1<<6
+#define WM8753_PWR3_ROUT2		1<<5
+#define WM8753_PWR3_OUT3		1<<4
+#define WM8753_PWR3_OUT4		1<<3
+#define WM8753_PWR3_MONO1		1<<2
+#define WM8753_PWR3_MONO2		1<<1
+
+#define WM8753_PWR4_RECMIX		1<<3
+#define WM8753_PWR4_MONOMIX		1<<2
+#define WM8753_PWR4_RIGHTMIX		1<<1
+#define WM8753_PWR4_LEFTMIX		1<<0
+
+#define WM8753_IOCTL_VXCLKTRI		1<<7
+#define WM8753_IOCTL_BCCLKTRI		1<<6
+#define WM8753_IOCTL_VXDTRI		1<<5
+#define WM8753_IOCTL_ADCTRI		1<<4
+#define WM8753_IOCTL_IFMODE_1		1<<3
+#define WM8753_IOCTL_IFMODE_0		1<<2
+#define WM8753_IOCTL_VXFSOE		1<<1
+#define WM8753_IOCTL_LRCOE		1<<0
+
+#define WM8753_LOUTM1_LD2LO		1<<8
+
+#define WM8753_ROUTM1_RD2RO		1<<8
+
+#define WM8753_ADCIN_MONOMIX_1		1<<5
+#define WM8753_ADCIN_MONOMIX_0		1<<4
+#define WM8753_ADCIN_RADCSEL_1		1<<3
+#define WM8753_ADCIN_RADCSEL_0		1<<2
+#define WM8753_ADCIN_LADCSEL_1		1<<1
+#define WM8753_ADCIN_LADCSEL_0		1<<0
+
+#define WM8753_INCTL1_MIC2BOOST_1	1<<8
+#define WM8753_INCTL1_MIC2BOOST_0	1<<7
+
+#define WM8753_INCTL2_MICMUX_1		1<<5
+#define WM8753_INCTL2_MICMUX_0		1<<4
+
+#define WM8753_ADC_DATSEL_1		1<<8
+#define WM8753_ADC_DATSEL_0		1<<7
+#define WM8753_ADC_ADCPOL_1		1<<6
+#define WM8753_ADC_ADCPOL_0		1<<5
+#define WM8753_ADC_VXFILT		1<<4
+#define WM8753_ADC_HPMODE_1		1<<3
+#define WM8753_ADC_HPMODE_0		1<<2
+#define WM8753_ADC_HPOR			1<<1
+#define WM8753_ADC_ADCHPD		1<<0
+
+#define WM8753_LINVOL_MAX		0x11F
+
+#define WM8753_RINVOL_MAX		0x11F
+
+static struct platform_device *tegra_snd_device;
+static struct regulator* wm8753_reg;
+
+extern struct snd_soc_dai tegra_i2s_dai[];
+extern struct snd_soc_platform tegra_soc_platform;
+
+static int tegra_hifi_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	int err;
+	unsigned int value;
+	unsigned int channels, rate, bit_size = 16;
+	struct snd_soc_codec *codec = codec_dai->codec;
+
+	rate	 = params_rate(params);		/* Sampling Rate in Hz */
+	channels = params_channels(params);	/* Number of channels */
+
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		bit_size = 16;
+		break;
+	case SNDRV_PCM_FORMAT_S20_3LE:
+		bit_size = 20;
+		break;
+	case SNDRV_PCM_FORMAT_S24_LE:
+		bit_size = 24;
+		break;
+	case SNDRV_PCM_FORMAT_S32_LE:
+		bit_size = 32;
+		break;
+	default:
+		pr_err(KERN_ERR "Invalid pcm format size\n");
+		return EINVAL;
+	}
+
+	err = snd_soc_dai_set_fmt(codec_dai,
+			SND_SOC_DAIFMT_I2S |
+			SND_SOC_DAIFMT_NB_NF |
+			SND_SOC_DAIFMT_CBS_CFS);
+	if (err < 0) {
+		pr_err(KERN_ERR "codec_dai fmt not set\n");
+		return err;
+	}
+
+	err = snd_soc_dai_set_fmt(cpu_dai,
+			SND_SOC_DAIFMT_I2S |
+			SND_SOC_DAIFMT_NB_NF |
+			SND_SOC_DAIFMT_CBS_CFS);
+	if (err < 0) {
+		pr_err(KERN_ERR "cpu_dai fmt not set\n");
+		return err;
+	}
+
+	err = snd_soc_dai_set_sysclk(codec_dai, 0, bit_size*rate*channels*2*4,
+			SND_SOC_CLOCK_IN);
+	if (err < 0) {
+		pr_err(KERN_ERR "codec_dai clock not set\n");
+		return err;
+	}
+
+	err = snd_soc_dai_set_sysclk(cpu_dai, 0, bit_size*rate*channels*2,
+			SND_SOC_CLOCK_IN);
+	if (err < 0) {
+		pr_err(KERN_ERR "cpu_dai clock not set\n");
+		return err;
+	}
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
+		/* Enables MICBIAS, VMIDSEL and VREF, DAC-L and DAC-R */
+		value = snd_soc_read(codec_dai->codec, WM8753_PWR1);
+		value |= (WM8753_PWR1_VMIDSEL_0 | WM8753_PWR1_VREF |
+				WM8753_PWR1_MICB | WM8753_PWR1_DACL |
+				WM8753_PWR1_DACR);
+		value &= ~(WM8753_PWR1_VMIDSEL_1);
+		snd_soc_write(codec_dai->codec, WM8753_PWR1, value);
+
+		/* Enables Lout1 and Rout1 */
+		value = snd_soc_read(codec_dai->codec, WM8753_PWR3);
+		value |= (WM8753_PWR3_LOUT1 | WM8753_PWR3_ROUT1);
+		snd_soc_write(codec_dai->codec, WM8753_PWR3, value);
+
+		/* Left and Right Mix Enabled */
+		value = snd_soc_read(codec_dai->codec, WM8753_PWR4);
+		value |= (WM8753_PWR4_RIGHTMIX | WM8753_PWR4_LEFTMIX);
+		snd_soc_write(codec_dai->codec, WM8753_PWR4, value);
+
+		/* Mode set to HiFi over HiFi interface and VXDOUT,ADCDAT,
+			VXCLK and BCLK pin enabled */
+		value = snd_soc_read(codec_dai->codec, WM8753_IOCTL);
+		value |= (WM8753_IOCTL_IFMODE_1);
+		value &= ~(WM8753_IOCTL_VXCLKTRI | WM8753_IOCTL_BCCLKTRI |
+				WM8753_IOCTL_VXDTRI | WM8753_IOCTL_ADCTRI |
+				WM8753_IOCTL_IFMODE_0 | WM8753_IOCTL_VXFSOE |
+				WM8753_IOCTL_LRCOE);
+		snd_soc_write(codec_dai->codec, WM8753_IOCTL, value);
+
+		/* L-DAC to L-Mix */
+		value = snd_soc_read(codec_dai->codec, WM8753_LOUTM1);
+		value |= WM8753_LOUTM1_LD2LO;
+		snd_soc_write(codec_dai->codec, WM8753_LOUTM1, value);
+
+		/* R-DAC to R-Mix */
+		value = snd_soc_read(codec_dai->codec, WM8753_ROUTM1);
+		value |= WM8753_ROUTM1_RD2RO;
+		snd_soc_write(codec_dai->codec, WM8753_ROUTM1, value);
+	}
+
+	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+		/* PGA i/p's to L and R ADC and operation in stero mode */
+		value = snd_soc_read(codec_dai->codec, WM8753_ADCIN);
+		value &= ~(WM8753_ADCIN_MONOMIX_1 | WM8753_ADCIN_MONOMIX_0 |
+				WM8753_ADCIN_RADCSEL_1 | WM8753_ADCIN_RADCSEL_0 |
+				WM8753_ADCIN_LADCSEL_1 | WM8753_ADCIN_LADCSEL_0);
+		snd_soc_write(codec_dai->codec, WM8753_ADCIN, value);
+
+		/* 24 db boost for Mic2 */
+		value = snd_soc_read(codec_dai->codec, WM8753_INCTL1);
+		value |= (WM8753_INCTL1_MIC2BOOST_1);
+		value &= ~(WM8753_INCTL1_MIC2BOOST_0);
+		snd_soc_write(codec_dai->codec, WM8753_INCTL1, value);
+
+		/* Side-Tone-Mic2 preamp o/p */
+		value = snd_soc_read(codec_dai->codec, WM8753_INCTL2);
+		value |= (WM8753_INCTL2_MICMUX_1);
+		value &= ~(WM8753_INCTL2_MICMUX_0);
+		snd_soc_write(codec_dai->codec, WM8753_INCTL2, value);
+
+		/* L and R data from R-ADC */
+		value = snd_soc_read(codec_dai->codec, WM8753_ADC);
+		value |= (WM8753_ADC_DATSEL_1);
+		value &= ~(WM8753_ADC_DATSEL_0 | WM8753_ADC_ADCPOL_1 |
+				WM8753_ADC_ADCPOL_0 | WM8753_ADC_VXFILT |
+				WM8753_ADC_HPMODE_1 | WM8753_ADC_HPMODE_0 |
+				WM8753_ADC_HPOR | WM8753_ADC_ADCHPD);
+		snd_soc_write(codec_dai->codec, WM8753_ADC, value);
+
+		/* Disable Mute and set L-PGA Vol to max */
+		snd_soc_write(codec, WM8753_LINVOL, WM8753_LINVOL_MAX);
+
+		/* Disable Mute and set R-PGA Vol to max */
+		snd_soc_write(codec, WM8753_RINVOL, WM8753_RINVOL_MAX);
+
+		/* Enables MICBIAS, VMIDSEL and VREF */
+		value = snd_soc_read(codec_dai->codec, WM8753_PWR1);
+		value |= (WM8753_PWR1_VMIDSEL_0|WM8753_PWR1_VREF|
+				WM8753_PWR1_MICB);
+		value &= ~(WM8753_PWR1_VMIDSEL_1);
+		snd_soc_write(codec_dai->codec, WM8753_PWR1, value);
+
+		/* Enable Mic2 preamp, PGA-R and ADC-R (Mic1 preamp,ALC Mix,
+			PGA-L , ADC-L, RXMIX and LINEMIX disabled) */
+		value = snd_soc_read(codec_dai->codec, WM8753_PWR2);
+		value |= (WM8753_PWR2_MICAMP2EN | WM8753_PWR2_PGAR|
+					WM8753_PWR2_ADCR);
+		value &= ~(WM8753_PWR2_MICAMP1EN | WM8753_PWR2_ALCMIX |
+					WM8753_PWR2_PGAL | WM8753_PWR2_ADCL |
+					WM8753_PWR2_RXMIX | WM8753_PWR2_LINEMIX);
+		snd_soc_write(codec, WM8753_PWR2, value);
+
+		/* Mode set to HiFi over HiFi interface and VXDOUT,ADCDAT,
+			VXCLK and BCLK pin enabled */
+		value = snd_soc_read(codec_dai->codec, WM8753_IOCTL);
+		value |= (WM8753_IOCTL_IFMODE_1);
+		value &= ~(WM8753_IOCTL_VXCLKTRI | WM8753_IOCTL_BCCLKTRI |
+				WM8753_IOCTL_VXDTRI | WM8753_IOCTL_ADCTRI |
+				WM8753_IOCTL_IFMODE_0 | WM8753_IOCTL_VXFSOE |
+				WM8753_IOCTL_LRCOE);
+		snd_soc_write(codec_dai->codec, WM8753_IOCTL, value);
+	}
+
+	return 0;
+}
+
+static int tegra_hifi_hw_free(struct snd_pcm_substream *substream)
+{
+	return 0;
+}
+
+static int tegra_voice_hw_params(struct snd_pcm_substream *substream,
+					struct snd_pcm_hw_params *params)
+{
+	return 0;
+}
+
+static int tegra_voice_hw_free(struct snd_pcm_substream *substream)
+{
+	return 0;
+}
+
+static struct snd_soc_ops tegra_hifi_ops = {
+	.hw_params = tegra_hifi_hw_params,
+	.hw_free   = tegra_hifi_hw_free,
+};
+
+static struct snd_soc_ops tegra_voice_ops = {
+	.hw_params = tegra_voice_hw_params,
+	.hw_free   = tegra_voice_hw_free,
+};
+
+
+static int tegra_codec_init(struct snd_soc_codec *codec)
+{
+	return tegra_controls_init(codec);
+}
+
+static struct snd_soc_dai_link tegra_soc_dai[] = {
+	{
+		.name = "WM8753",
+		.stream_name = "WM8753 HiFi",
+		.cpu_dai = &tegra_i2s_dai[0],
+		.codec_dai = &wm8753_dai[WM8753_DAI_HIFI],
+		.init = tegra_codec_init,
+		.ops = &tegra_hifi_ops,
+	},
+	{
+		.name = "WM8753",
+		.stream_name = "WM8753 Voice",
+		.cpu_dai = &tegra_i2s_dai[1],
+		.codec_dai = &wm8753_dai[WM8753_DAI_VOICE],
+		.init = tegra_codec_init,
+		.ops = &tegra_voice_ops,
+	},
+
+};
+
+static struct snd_soc_card tegra_snd_soc = {
+	.name = "tegra",
+	.platform = &tegra_soc_platform,
+	.dai_link = tegra_soc_dai,
+	.num_links = ARRAY_SIZE(tegra_soc_dai),
+};
+
+static struct snd_soc_device tegra_snd_devdata = {
+	.card = &tegra_snd_soc,
+	.codec_dev = &soc_codec_dev_wm8753,
+};
+
+static int __init tegra_init(void)
+{
+	int ret = 0;
+
+	tegra_snd_device = platform_device_alloc("soc-audio", -1);
+	if (!tegra_snd_device) {
+		pr_err("failed to allocate soc-audio \n");
+		return ENOMEM;
+	}
+
+	platform_set_drvdata(tegra_snd_device, &tegra_snd_devdata);
+	tegra_snd_devdata.dev = &tegra_snd_device->dev;
+	ret = platform_device_add(tegra_snd_device);
+	if (ret) {
+		pr_err("audio device could not be added \n");
+		goto fail;
+	}
+
+	wm8753_reg = regulator_get(NULL, "avddio_audio");
+	if (IS_ERR(wm8753_reg)) {
+		ret = PTR_ERR(wm8753_reg);
+		pr_err("unable to get wm8753 regulator\n");
+		goto fail;
+	}
+
+	ret = regulator_enable(wm8753_reg);
+	if (ret) {
+		pr_err("wm8753 regulator enable failed\n");
+		goto err_put_regulator;
+	}
+
+	return 0;
+
+fail:
+	if (tegra_snd_device) {
+		platform_device_put(tegra_snd_device);
+		tegra_snd_device = 0;
+	}
+
+	return ret;
+
+err_put_regulator:
+	regulator_put(wm8753_reg);
+	return ret;
+}
+
+static void __exit tegra_exit(void)
+{
+	tegra_controls_exit();
+	platform_device_unregister(tegra_snd_device);
+	regulator_disable(wm8753_reg);
+	regulator_put(wm8753_reg);
+}
+
+module_init(tegra_init);
+module_exit(tegra_exit);
+
+/* Module information */
+MODULE_DESCRIPTION("Tegra ALSA SoC");
+MODULE_LICENSE("GPL");
+
diff --git a/sound/soc/tegra/tegra_soc_wm8903.c b/sound/soc/tegra/tegra_soc_wm8903.c
new file mode 100644
index 000000000000..dc5103c36377
--- /dev/null
+++ b/sound/soc/tegra/tegra_soc_wm8903.c
@@ -0,0 +1,238 @@
+/*
+ * tegra_soc_wm8903.c  --  SoC audio for tegra
+ *
+ * (c) 2010 Nvidia Graphics Pvt. Ltd.
+ *  http://www.nvidia.com
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC.
+ * Author: Graeme Gregory
+ *         graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include "tegra_soc.h"
+#include "../codecs/wm8903.h"
+
+static struct platform_device *tegra_snd_device;
+
+extern struct snd_soc_dai tegra_i2s_dai[];
+extern struct snd_soc_platform tegra_soc_platform;
+
+/* codec register values */
+#define B07_INEMUTE		7
+#define B06_VOL_M3DB		6
+#define B00_IN_VOL		0
+#define B00_INR_ENA		0
+#define B01_INL_ENA		1
+#define R06_MICBIAS_CTRL_0	6
+#define B07_MICDET_HYST_ENA	7
+#define B04_MICDET_THR		4
+#define B02_MICSHORT_THR	2
+#define B01_MICDET_ENA		1
+#define B00_MICBIAS_ENA		0
+#define B15_DRC_ENA		15
+#define B03_DACL_ENA		3
+#define B02_DACR_ENA		2
+#define B01_ADCL_ENA		1
+#define B00_ADCR_ENA		0
+#define B06_IN_CM_ENA		6
+#define B04_IP_SEL_N		4
+#define B02_IP_SEL_P		2
+#define B00_MODE 		0
+#define B06_AIF_ADCL		7
+#define B06_AIF_ADCR		6
+#define B05_ADC_HPF_CUT		5
+#define B04_ADC_HPF_ENA		4
+#define B01_ADCL_DATINV		1
+#define B00_ADCR_DATINV		0
+#define R20_SIDETONE_CTRL	32
+#define R29_DRC_1		41
+#define SET_REG_VAL(r,m,l,v) (((r)&(~((m)<<(l))))|(((v)&(m))<<(l)))
+
+
+static int tegra_hifi_hw_params(struct snd_pcm_substream *substream,
+					struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	int err;
+	struct snd_soc_codec *codec = codec_dai->codec;
+	int CtrlReg = 0;
+	int VolumeCtrlReg = 0;
+	int SidetoneCtrlReg = 0;
+	int SideToneAtenuation = 0;
+
+	err = snd_soc_dai_set_fmt(codec_dai,
+					SND_SOC_DAIFMT_I2S | \
+					SND_SOC_DAIFMT_NB_NF | \
+					SND_SOC_DAIFMT_CBS_CFS);
+	if (err < 0) {
+		printk(KERN_ERR "codec_dai fmt not set \n");
+		return err;
+	}
+
+	err = snd_soc_dai_set_fmt(cpu_dai,
+					SND_SOC_DAIFMT_I2S | \
+					SND_SOC_DAIFMT_NB_NF | \
+					SND_SOC_DAIFMT_CBS_CFS);
+	if (err < 0) {
+		printk(KERN_ERR "cpu_dai fmt not set \n");
+		return err;
+	}
+
+	err = snd_soc_dai_set_sysclk(codec_dai, 0, I2S_CLK, SND_SOC_CLOCK_IN);
+	if (err < 0) {
+		printk(KERN_ERR "codec_dai clock not set\n");
+		return err;
+	}
+
+	err = snd_soc_dai_set_sysclk(cpu_dai, 0, I2S_CLK, SND_SOC_CLOCK_IN);
+	if (err < 0) {
+		printk(KERN_ERR "cpu_dai clock not set\n");
+		return err;
+	}
+
+	if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK) {
+		snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0, 0X7);
+		snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0, 0X7);
+		// Mic Bias enable
+		CtrlReg = (0x1<<B00_MICBIAS_ENA) | (0x1<<B01_MICDET_ENA);
+		snd_soc_write(codec, WM8903_MIC_BIAS_CONTROL_0, CtrlReg);
+		// Enable DRC
+		CtrlReg = snd_soc_read(codec, WM8903_DRC_0);
+		CtrlReg |= (1<<B15_DRC_ENA);
+		snd_soc_write(codec, WM8903_DRC_0, CtrlReg);
+		// Single Ended Mic
+		CtrlReg = (0x0<<B06_IN_CM_ENA) |
+			(0x0<<B00_MODE) | (0x0<<B04_IP_SEL_N)
+					| (0x1<<B02_IP_SEL_P);
+		VolumeCtrlReg = (0x1C << B00_IN_VOL);
+		// Mic Setting
+		snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_1, CtrlReg);
+		snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_1, CtrlReg);
+		// voulme for single ended mic
+		snd_soc_write(codec, WM8903_ANALOGUE_LEFT_INPUT_0,
+				VolumeCtrlReg);
+		snd_soc_write(codec, WM8903_ANALOGUE_RIGHT_INPUT_0,
+				VolumeCtrlReg);
+		// replicate mic setting on both channels
+		CtrlReg = snd_soc_read(codec, WM8903_AUDIO_INTERFACE_0);
+		CtrlReg  = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCR, 0x0);
+		CtrlReg  = SET_REG_VAL(CtrlReg, 0x1, B06_AIF_ADCL, 0x0);
+		snd_soc_write(codec, WM8903_AUDIO_INTERFACE_0, CtrlReg);
+		// Enable analog inputs
+		CtrlReg = (0x1<<B01_INL_ENA) | (0x1<<B00_INR_ENA);
+		snd_soc_write(codec, WM8903_POWER_MANAGEMENT_0, CtrlReg);
+		// ADC Settings
+		CtrlReg = snd_soc_read(codec, WM8903_ADC_DIGITAL_0);
+		CtrlReg |= (0x1<<B04_ADC_HPF_ENA);
+		snd_soc_write(codec, WM8903_ADC_DIGITAL_0, CtrlReg);
+		SidetoneCtrlReg = 0;
+		snd_soc_write(codec, R20_SIDETONE_CTRL, SidetoneCtrlReg);
+		// Enable ADC
+		CtrlReg = snd_soc_read(codec, WM8903_POWER_MANAGEMENT_6);
+		CtrlReg |= (0x1<<B00_ADCR_ENA)|(0x1<<B01_ADCL_ENA);
+		snd_soc_write(codec, WM8903_POWER_MANAGEMENT_6, CtrlReg);
+		// Enable Sidetone
+		SidetoneCtrlReg = (0x1<<2) | (0x2<<0);
+		SideToneAtenuation = 12 ; // sidetone 0 db
+		SidetoneCtrlReg |= (SideToneAtenuation<<8)
+				| (SideToneAtenuation<<4);
+		snd_soc_write(codec, R20_SIDETONE_CTRL, SidetoneCtrlReg);
+		CtrlReg = snd_soc_read(codec, R29_DRC_1);
+		CtrlReg |= 0x3; //mic volume 18 db
+		snd_soc_write(codec, R29_DRC_1, CtrlReg);
+	}
+
+	return 0;
+}
+
+static struct snd_soc_ops tegra_hifi_ops = {
+	.hw_params = tegra_hifi_hw_params,
+};
+
+static int tegra_codec_init(struct snd_soc_codec *codec)
+{
+	return tegra_controls_init(codec);
+}
+
+static struct snd_soc_dai_link tegra_soc_dai[] = {
+	{
+		.name = "WM8903",
+		.stream_name = "WM8903 HiFi",
+		.cpu_dai = &tegra_i2s_dai[0],
+		.codec_dai = &wm8903_dai,
+		.init = tegra_codec_init,
+		.ops = &tegra_hifi_ops,
+	},
+	{
+		.name = "WM8903",
+		.stream_name = "WM8903 Voice",
+		.cpu_dai = &tegra_i2s_dai[1],
+		.codec_dai = &wm8903_dai,
+		.init = tegra_codec_init,
+		.ops = &tegra_hifi_ops,
+	},
+
+};
+
+static struct snd_soc_card tegra_snd_soc = {
+	.name = "tegra",
+	.platform = &tegra_soc_platform,
+	.dai_link = tegra_soc_dai,
+	.num_links = ARRAY_SIZE(tegra_soc_dai),
+};
+
+
+static struct snd_soc_device tegra_snd_devdata = {
+	.card = &tegra_snd_soc,
+	.codec_dev = &soc_codec_dev_wm8903,
+};
+
+static int __init tegra_init(void)
+{
+	int ret = 0;
+
+	tegra_snd_device = platform_device_alloc("soc-audio", -1);
+	if (!tegra_snd_device) {
+		pr_err("failed to allocate soc-audio \n");
+		return ENOMEM;
+	}
+
+	platform_set_drvdata(tegra_snd_device, &tegra_snd_devdata);
+	tegra_snd_devdata.dev = &tegra_snd_device->dev;
+	ret = platform_device_add(tegra_snd_device);
+	if (ret) {
+		pr_err("audio device could not be added \n");
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	if (tegra_snd_device) {
+		platform_device_put(tegra_snd_device);
+		tegra_snd_device = 0;
+	}
+
+	return ret;
+}
+
+static void __exit tegra_exit(void)
+{
+	tegra_controls_exit();
+	platform_device_unregister(tegra_snd_device);
+}
+
+module_init(tegra_init);
+module_exit(tegra_exit);
+
+/* Module information */
+MODULE_DESCRIPTION("Tegra ALSA SoC");
+MODULE_LICENSE("GPL");